From ccef2d248b7269766f00b9122eb1930aa1100605 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Wed, 26 Aug 2015 10:03:11 +0000 Subject: SPI working on F7 but cache handling unfinished. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8241 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c | 10 ---------- os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h | 10 ++++++---- os/hal/ports/STM32/LLD/SPIv2/spi_lld.c | 8 ++++---- testhal/STM32/STM32F7xx/SPI/main.c | 27 +++++++++++++++------------ 4 files changed, 25 insertions(+), 30 deletions(-) diff --git a/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c b/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c index 9e8d31bc8..2b59004a2 100644 --- a/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c +++ b/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.c @@ -49,16 +49,6 @@ */ #define STM32_DMA2_STREAMS_MASK 0x0000FF00U -/** - * @brief Post-reset value of the stream CR register. - */ -#define STM32_DMA_CR_RESET_VALUE 0x00000000U - -/** - * @brief Post-reset value of the stream FCR register. - */ -#define STM32_DMA_FCR_RESET_VALUE 0x00000021U - /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ diff --git a/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h b/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h index ab46ecf43..49139f831 100644 --- a/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h +++ b/os/hal/ports/STM32/LLD/DMAv2/stm32_dma.h @@ -126,6 +126,7 @@ * @name CR register constants common to all DMA types * @{ */ +#define STM32_DMA_CR_RESET_VALUE 0x00000000U #define STM32_DMA_CR_EN DMA_SxCR_EN #define STM32_DMA_CR_TEIE DMA_SxCR_TEIE #define STM32_DMA_CR_HTIE DMA_SxCR_HTIE @@ -178,6 +179,7 @@ * @name FCR register constants only found in STM32F2xx/STM32F4xx * @{ */ +#define STM32_DMA_FCR_RESET_VALUE 0x00000021U #define STM32_DMA_FCR_FEIE DMA_SxFCR_FEIE #define STM32_DMA_FCR_FS_MASK DMA_SxFCR_FS #define STM32_DMA_FCR_DMDIS DMA_SxFCR_DMDIS @@ -398,11 +400,10 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); * @special */ #define dmaStreamDisable(dmastp) { \ - (dmastp)->stream->CR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE | \ - STM32_DMA_CR_TEIE | STM32_DMA_CR_DMEIE | \ - STM32_DMA_CR_EN); \ + (dmastp)->stream->CR &= ~STM32_DMA_CR_EN; \ while (((dmastp)->stream->CR & STM32_DMA_CR_EN) != 0U) \ ; \ + (dmastp)->stream->CR = STM32_DMA_CR_RESET_VALUE; \ dmaStreamClearInterrupt(dmastp); \ } @@ -445,7 +446,8 @@ typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags); dmaStreamSetTransactionSize(dmastp, n); \ dmaStreamSetMode(dmastp, (mode) | \ STM32_DMA_CR_MINC | STM32_DMA_CR_PINC | \ - STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN); \ + STM32_DMA_CR_DIR_M2M); \ + dmaStreamEnable(dmastp); \ } /** diff --git a/os/hal/ports/STM32/LLD/SPIv2/spi_lld.c b/os/hal/ports/STM32/LLD/SPIv2/spi_lld.c index 8a218ac46..8704e5a21 100644 --- a/os/hal/ports/STM32/LLD/SPIv2/spi_lld.c +++ b/os/hal/ports/STM32/LLD/SPIv2/spi_lld.c @@ -259,7 +259,7 @@ void spi_lld_init(void) { #endif #if STM32_SPI_USE_SPI5 - spiObjectInit(&SPID3); + spiObjectInit(&SPID5); SPID5.spi = SPI5; SPID5.dmarx = STM32_DMA_STREAM(STM32_SPI_SPI5_RX_DMA_STREAM); SPID5.dmatx = STM32_DMA_STREAM(STM32_SPI_SPI5_TX_DMA_STREAM); @@ -427,10 +427,10 @@ void spi_lld_start(SPIDriver *spip) { STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; spip->fsize = sizeof (uint16_t); } + /* SPI setup and enable.*/ spip->spi->CR1 = 0; - spip->spi->CR1 = spip->config->cr1 | SPI_CR1_MSTR | SPI_CR1_SSM | - SPI_CR1_SSI; + spip->spi->CR1 = spip->config->cr1 | SPI_CR1_MSTR; spip->spi->CR2 = spip->config->cr2 | SPI_CR2_FRXTH | SPI_CR2_SSOE | SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN; spip->spi->CR1 |= SPI_CR1_SPE; @@ -554,7 +554,7 @@ void spi_lld_exchange(SPIDriver *spip, size_t n, dmaStreamSetMemory0(spip->dmarx, rxbuf); dmaStreamSetTransactionSize(spip->dmarx, n); - dmaStreamSetMode(spip->dmarx, spip->rxdmamode| STM32_DMA_CR_MINC); + dmaStreamSetMode(spip->dmarx, spip->rxdmamode | STM32_DMA_CR_MINC); dmaStreamSetMemory0(spip->dmatx, txbuf); dmaStreamSetTransactionSize(spip->dmatx, n); diff --git a/testhal/STM32/STM32F7xx/SPI/main.c b/testhal/STM32/STM32F7xx/SPI/main.c index 4e14474e4..996b3c9b7 100644 --- a/testhal/STM32/STM32F7xx/SPI/main.c +++ b/testhal/STM32/STM32F7xx/SPI/main.c @@ -26,9 +26,9 @@ */ static const SPIConfig hs_spicfg = { NULL, - GPIOI, - GPIOI_ARD_D13, - 0, + GPIOB, + GPIOB_ARD_D15, + SPI_CR1_BR_0, SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0 }; @@ -37,8 +37,8 @@ static const SPIConfig hs_spicfg = { */ static const SPIConfig ls_spicfg = { NULL, - GPIOI, - GPIOI_ARD_D13, + GPIOB, + GPIOB_ARD_D14, SPI_CR1_BR_2 | SPI_CR1_BR_1, SPI_CR2_DS_2 | SPI_CR2_DS_1 | SPI_CR2_DS_0 }; @@ -114,8 +114,8 @@ int main(void) { */ palSetPadMode(GPIOI, GPIOI_ARD_D13, - PAL_MODE_OUTPUT_PUSHPULL | - PAL_STM32_OSPEED_HIGHEST); /* LED over SPI SCK. */ + PAL_MODE_ALTERNATE(5) | + PAL_STM32_OSPEED_HIGHEST); /* SPI SCK. */ palSetPadMode(GPIOB, GPIOB_ARD_D12, PAL_MODE_ALTERNATE(5) | @@ -124,11 +124,14 @@ int main(void) { GPIOB_ARD_D11, PAL_MODE_ALTERNATE(5) | PAL_STM32_OSPEED_HIGHEST); /* MOSI. */ - palSetPadMode(GPIOI, - GPIOI_ARD_D10, - PAL_MODE_OUTPUT_PUSHPULL | - PAL_STM32_OSPEED_HIGHEST); /* CS. */ - palSetPad(GPIOI, GPIOI_ARD_D10); + palSetPad(GPIOB, GPIOB_ARD_D15); + palSetPadMode(GPIOB, + GPIOB_ARD_D15, + PAL_MODE_OUTPUT_PUSHPULL); /* CS0. */ + palSetPad(GPIOB, GPIOB_ARD_D14); + palSetPadMode(GPIOB, + GPIOB_ARD_D14, + PAL_MODE_OUTPUT_PUSHPULL); /* CS1. */ /* * Prepare transmit pattern. -- cgit v1.2.3