From cccd652cb580ed98ab53eeef2ddda9fed2fa682b Mon Sep 17 00:00:00 2001
From: Giovanni Di Sirio <gdisirio@gmail.com>
Date: Mon, 8 Jan 2018 09:30:23 +0000
Subject: Added SRAMs cache settings to STM32H7 mcuconf.h.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11235 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h      |  6 ++++
 os/hal/ports/STM32/STM32H7xx/hal_lld.c             | 36 +++++++++++++++++++++-
 os/hal/ports/STM32/STM32H7xx/hal_lld.h             | 16 ++++++++++
 .../multi/SPI/cfg-stm32h743_nucleo144/mcuconf.h    |  6 ++++
 4 files changed, 63 insertions(+), 1 deletion(-)

diff --git a/demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h b/demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h
index d26cec4bc..e1ac3d1a5 100644
--- a/demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h
+++ b/demos/STM32/RT-STM32H743I-NUCLEO144/mcuconf.h
@@ -39,6 +39,12 @@
 #define STM32_NO_INIT                       FALSE
 #define STM32_SYS_CK_ENFORCED_VALUE         STM32_HSICLK
 
+/*
+ * Memory attributes settings.
+ */
+#define STM32_NOCACHE_SRAM1_SRAM2           FALSE
+#define STM32_NOCACHE_SRAM3                 TRUE
+
 /*
  * PWR system settings.
  * Reading STM32 Reference Manual is required.
diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.c b/os/hal/ports/STM32/STM32H7xx/hal_lld.c
index 1a8bf7fbb..7e7b0c3b1 100644
--- a/os/hal/ports/STM32/STM32H7xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32H7xx/hal_lld.c
@@ -150,10 +150,44 @@ void hal_lld_init(void) {
 
   /* IRQ subsystem initialization.*/
   irqInit();
+
+  /* MPU initialization.*/
+#if (STM32_NOCACHE_SRAM1_SRAM2 == TRUE) || (STM32_NOCACHE_SRAM3 == TRUE)
+  {
+    uint32_t base, size;
+
+#if (STM32_NOCACHE_SRAM1_SRAM2 == TRUE) && (STM32_NOCACHE_SRAM3 == TRUE)
+    base = 0x30000000U;
+    size = MPU_RASR_SIZE_512K;
+#elif (STM32_NOCACHE_SRAM1_SRAM2 == TRUE) && (STM32_NOCACHE_SRAM3 == FALSE)
+    base = 0x30000000U;
+    size = MPU_RASR_SIZE_256K;
+#elif (STM32_NOCACHE_SRAM1_SRAM2 == FALSE) && (STM32_NOCACHE_SRAM3 == TRUE)
+    base = 0x30040000U;
+    size = MPU_RASR_SIZE_16K;
+#else
+#error "invalid constants used in mcuconf.h"
+#endif
+
+    /* The SRAM2 bank can optionally made a non cache-able area for use by
+       DMA engines.*/
+    mpuConfigureRegion(MPU_REGION_7,
+                       base,
+                       MPU_RASR_ATTR_AP_RW_RW |
+                       MPU_RASR_ATTR_NON_CACHEABLE |
+                       size |
+                       MPU_RASR_ENABLE);
+    mpuEnable(MPU_CTRL_PRIVDEFENA);
+
+    /* Invalidating data cache to make sure that the MPU settings are taken
+       immediately.*/
+    SCB_CleanInvalidateDCache();
+  }
+#endif
 }
 
 /**
- * @brief   STM32F2xx clocks and PLL initialization.
+ * @brief   STM32H7xx clocks and PLL initialization.
  * @note    All the involved constants come from the file @p board.h.
  * @note    This function should be invoked just after the system reset.
  *
diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.h b/os/hal/ports/STM32/STM32H7xx/hal_lld.h
index 7217a579f..21a1cb739 100644
--- a/os/hal/ports/STM32/STM32H7xx/hal_lld.h
+++ b/os/hal/ports/STM32/STM32H7xx/hal_lld.h
@@ -542,6 +542,22 @@
 #define STM32_SYS_CK_ENFORCED_VALUE         STM32_HSICLK
 #endif
 
+/**
+ * @brief   Add no-cache attribute to SRAM1 and SRAM2.
+ * @note    MPU region 7 is used if enabled.
+ */
+#if !defined(STM32_NOCACHE_SRAM1_SRAM2) || defined(__DOXYGEN__)
+#define STM32_NOCACHE_SRAM1_SRAM2           FALSE
+#endif
+
+/**
+ * @brief   Add no-cache attribute to SRAM3.
+ * @note    MPU region 7 is used if enabled.
+ */
+#if !defined(STM32_NOCACHE_SRAM3) || defined(__DOXYGEN__)
+#define STM32_NOCACHE_SRAM3                 TRUE
+#endif
+
 /**
  * @brief   PWR CR1 initializer.
  */
diff --git a/testhal/STM32/multi/SPI/cfg-stm32h743_nucleo144/mcuconf.h b/testhal/STM32/multi/SPI/cfg-stm32h743_nucleo144/mcuconf.h
index c46fbb3a4..8a8304dc0 100644
--- a/testhal/STM32/multi/SPI/cfg-stm32h743_nucleo144/mcuconf.h
+++ b/testhal/STM32/multi/SPI/cfg-stm32h743_nucleo144/mcuconf.h
@@ -39,6 +39,12 @@
 #define STM32_NO_INIT                       FALSE
 #define STM32_SYS_CK_ENFORCED_VALUE         STM32_HSICLK
 
+/*
+ * Memory attributes settings.
+ */
+#define STM32_NOCACHE_SRAM1_SRAM2           FALSE
+#define STM32_NOCACHE_SRAM3                 TRUE
+
 /*
  * PWR system settings.
  * Reading STM32 Reference Manual is required.
-- 
cgit v1.2.3