From cc330f65ccb0ec1eac58612972bb43f19efda4f2 Mon Sep 17 00:00:00 2001
From: Giovanni Di Sirio <gdisirio@gmail.com>
Date: Sat, 20 Jan 2018 14:53:29 +0000
Subject: Added HRTIM support.

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11366 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 os/hal/ports/STM32/STM32F3xx/hal_lld.c        |  2 +-
 os/hal/ports/STM32/STM32F3xx/hal_lld.h        | 32 ++++++++++++++++++++++++++
 os/hal/ports/STM32/STM32F3xx/stm32_rcc.h      | 33 +++++++++++++++++++++++++++
 os/hal/ports/STM32/STM32F3xx/stm32_registry.h |  3 +++
 4 files changed, 69 insertions(+), 1 deletion(-)

diff --git a/os/hal/ports/STM32/STM32F3xx/hal_lld.c b/os/hal/ports/STM32/STM32F3xx/hal_lld.c
index 653f1b4a8..71e298147 100644
--- a/os/hal/ports/STM32/STM32F3xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F3xx/hal_lld.c
@@ -217,7 +217,7 @@ void stm32_clock_init(void) {
 
   /* After PLL activation because the special requirements for TIM1 and
      TIM8 bits.*/
-  RCC->CFGR3 |= STM32_TIM8SW | STM32_TIM1SW;
+  RCC->CFGR3 |= STM32_HRTIM1SW | STM32_TIM8SW | STM32_TIM1SW;
 #endif /* !STM32_NO_INIT */
 }
 
diff --git a/os/hal/ports/STM32/STM32F3xx/hal_lld.h b/os/hal/ports/STM32/STM32F3xx/hal_lld.h
index 33e3805d9..e98905172 100644
--- a/os/hal/ports/STM32/STM32F3xx/hal_lld.h
+++ b/os/hal/ports/STM32/STM32F3xx/hal_lld.h
@@ -300,6 +300,9 @@
 #define STM32_TIM8SW_MASK       (1 << 9)    /**< TIM8 clock source mask.   */
 #define STM32_TIM8SW_PCLK2      (0 << 9)    /**< TIM8 clock is PCLK2.      */
 #define STM32_TIM8SW_PLLX2      (1 << 9)    /**< TIM8 clock is PLL*2.      */
+#define STM32_HRTIM1SW_MASK     (1 << 12)   /**< HRTIM1 clock source mask. */
+#define STM32_HRTIM1SW_PCLK2    (0 << 12)   /**< HRTIM1 clock is PCLK2.    */
+#define STM32_HRTIM1SW_PLLX2    (1 << 12)   /**< HRTIM1 clock is PLL*2.    */
 #define STM32_USART2SW_MASK     (3 << 16)   /**< USART2 clock source mask. */
 #define STM32_USART2SW_PCLK     (0 << 16)   /**< USART2 clock is PCLK.     */
 #define STM32_USART2SW_SYSCLK   (1 << 16)   /**< USART2 clock is SYSCLK.   */
@@ -529,6 +532,13 @@
 #define STM32_TIM8SW                        STM32_TIM8SW_PCLK2
 #endif
 
+/**
+ * @brief   HRTIM1 clock source.
+ */
+#if !defined(STM32_HRTIM1SW) || defined(__DOXYGEN__)
+#define STM32_HRTIM1SW                      STM32_HRTIM1SW_PCLK2
+#endif
+
 /**
  * @brief   RTC clock source.
  */
@@ -1090,6 +1100,28 @@
 #error "invalid source selected for TIM8 clock"
 #endif
 
+/**
+ * @brief   HRTIM1 frequency.
+ */
+#if STM32_HRTIM1SW == STM32_HRTIM1SW_PCLK2
+#if STM32_PPRE2 == STM32_PPRE2_DIV1
+#define STM32_HRTIM1CLK               STM32_PCLK2
+#else
+#define STM32_HRTIM1CLK               (STM32_PCLK2 * 2)
+#endif
+
+#elif STM32_HRTIM1SW == STM32_HRTIM1SW_PLLX2
+#if (STM32_SW != STM32_SW_PLL) ||                                           \
+    (STM32_HPRE != STM32_HPRE_DIV1) ||                                      \
+    (STM32_PPRE2 != STM32_PPRE2_DIV1)
+#error "double clock mode cannot be activated for HRTIM1 under the current settings"
+#endif
+#define STM32_HRTIM1CLK               (STM32_PLLCLKOUT * 2)
+
+#else
+#error "invalid source selected for HRTIM1 clock"
+#endif
+
 /**
  * @brief   Timers 2, 3, 4, 6, 7 frequency.
  */
diff --git a/os/hal/ports/STM32/STM32F3xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F3xx/stm32_rcc.h
index cd209baef..1c1d4fc19 100644
--- a/os/hal/ports/STM32/STM32F3xx/stm32_rcc.h
+++ b/os/hal/ports/STM32/STM32F3xx/stm32_rcc.h
@@ -778,6 +778,39 @@
 #define rccResetTIM20() rccResetAPB2(RCC_APB2RSTR_TIM20RST)
 /** @} */
 
+/**
+ * @name    HRTIM peripheral specific RCC operations
+ * @{
+ */
+/**
+
+ * @brief   Enables the HRTIM1 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableHRTIM1(lp) rccEnableAPB2(RCC_APB2ENR_HRTIM1EN, lp)
+
+/**
+ * @brief   Disables the HRTIM1 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableHRTIM1(lp) rccDisableAPB2(RCC_APB2ENR_HRTIM1EN, lp)
+
+/**
+ * @brief   Resets the HRTIM1 peripheral.
+ *
+ * @api
+
+ */
+#define rccResetHRTIM1() rccResetAPB2(RCC_APB2RSTR_HRTIM1RST)
+/** @} */
+
 /**
  * @name    USART/UART peripherals specific RCC operations
  * @{
diff --git a/os/hal/ports/STM32/STM32F3xx/stm32_registry.h b/os/hal/ports/STM32/STM32F3xx/stm32_registry.h
index 472ed66fd..4a1efbc64 100644
--- a/os/hal/ports/STM32/STM32F3xx/stm32_registry.h
+++ b/os/hal/ports/STM32/STM32F3xx/stm32_registry.h
@@ -2584,6 +2584,9 @@
 #define STM32_HAS_TIM21                     FALSE
 #define STM32_HAS_TIM22                     FALSE
 
+/* HRTIM attributes.*/
+#define STM32_HAS_HRTIM1                    TRUE
+
 /* USART attributes.*/
 #define STM32_HAS_USART1                    TRUE
 #define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
-- 
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