From c4ca86b1c14e4f943636555b17fa14e54b12b881 Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Mon, 18 Dec 2017 15:05:59 +0000 Subject: More H7 code, incomplete. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11146 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/ports/STM32/STM32F7xx/stm32_isr.c | 2 +- os/hal/ports/STM32/STM32H7xx/hal_lld.c | 305 ++++ os/hal/ports/STM32/STM32H7xx/hal_lld.h | 2073 +++++++++++++++++++++++++ os/hal/ports/STM32/STM32H7xx/platform.mk | 29 + os/hal/ports/STM32/STM32H7xx/stm32_isr.c | 255 +++ os/hal/ports/STM32/STM32H7xx/stm32_isr.h | 173 +++ os/hal/ports/STM32/STM32H7xx/stm32_rcc.h | 1653 ++++++++++++++++++++ os/hal/ports/STM32/STM32H7xx/stm32_registry.h | 318 ++++ 8 files changed, 4807 insertions(+), 1 deletion(-) create mode 100644 os/hal/ports/STM32/STM32H7xx/hal_lld.c create mode 100644 os/hal/ports/STM32/STM32H7xx/hal_lld.h create mode 100644 os/hal/ports/STM32/STM32H7xx/platform.mk create mode 100644 os/hal/ports/STM32/STM32H7xx/stm32_isr.c create mode 100644 os/hal/ports/STM32/STM32H7xx/stm32_isr.h create mode 100644 os/hal/ports/STM32/STM32H7xx/stm32_rcc.h create mode 100644 os/hal/ports/STM32/STM32H7xx/stm32_registry.h diff --git a/os/hal/ports/STM32/STM32F7xx/stm32_isr.c b/os/hal/ports/STM32/STM32F7xx/stm32_isr.c index a51705a11..afee67ed4 100644 --- a/os/hal/ports/STM32/STM32F7xx/stm32_isr.c +++ b/os/hal/ports/STM32/STM32F7xx/stm32_isr.c @@ -18,7 +18,7 @@ * @file STM32F7xx/stm32_isr.h * @brief STM32F7xx ISR handler code. * - * @addtogroup SRM32F7xx_ISR + * @addtogroup STM32F7xx_ISR * @{ */ diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.c b/os/hal/ports/STM32/STM32H7xx/hal_lld.c new file mode 100644 index 000000000..c174c859e --- /dev/null +++ b/os/hal/ports/STM32/STM32H7xx/hal_lld.c @@ -0,0 +1,305 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32H7xx/hal_lld.c + * @brief STM32H7xx HAL subsystem low level driver source. + * + * @addtogroup HAL + * @{ + */ + +#include "hal.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief CMSIS system core clock variable. + * @note It is declared in system_stm32f7xx.h. + */ +uint32_t SystemCoreClock = STM32_HCLK; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Initializes the backup domain. + * @note WARNING! Changing clock source impossible without resetting + * of the whole BKP domain. + */ +static void hal_lld_backup_domain_init(void) { + + /* Backup domain access enabled and left open.*/ + PWR->CR1 |= PWR_CR1_DBP; + + /* Reset BKP domain if different clock source selected.*/ + if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL) { + /* Backup domain reset.*/ + RCC->BDCR = RCC_BDCR_BDRST; + RCC->BDCR = 0; + } + +#if STM32_LSE_ENABLED +#if defined(STM32_LSE_BYPASS) + /* LSE Bypass.*/ + RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP; +#else + /* No LSE Bypass.*/ + RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON; +#endif + while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0) + ; /* Waits until LSE is stable. */ +#endif + +#if HAL_USE_RTC + /* If the backup domain hasn't been initialized yet then proceed with + initialization.*/ + if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) { + /* Selects clock source.*/ + RCC->BDCR |= STM32_RTCSEL; + + /* RTC clock enabled.*/ + RCC->BDCR |= RCC_BDCR_RTCEN; + } +#endif /* HAL_USE_RTC */ + +#if STM32_BKPRAM_ENABLE + rccEnableBKPSRAM(false); + + PWR->CSR1 |= PWR_CSR1_BRE; + while ((PWR->CSR1 & PWR_CSR1_BRR) == 0) + ; /* Waits until the regulator is stable */ +#else + PWR->CSR1 &= ~PWR_CSR1_BRE; +#endif /* STM32_BKPRAM_ENABLE */ +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level HAL driver initialization. + * + * @notapi + */ +void hal_lld_init(void) { + + /* Reset of all peripherals. AHB3 is not reseted because it could have + been initialized in the board initialization file (board.c). + Note, GPIOs are not reset because initialized before this point in + board files.*/ + rccResetAHB1(~STM32_GPIO_EN_MASK); + rccResetAHB2(~0); + rccResetAPB1(~RCC_APB1RSTR_PWRRST); + rccResetAPB2(~0); + + /* Initializes the backup domain.*/ + hal_lld_backup_domain_init(); + + /* DMA subsystems initialization.*/ +#if defined(STM32_DMA_REQUIRED) + dmaInit(); +#endif + + /* IRQ subsystem initialization.*/ + irqInit(); + +#if STM32_SRAM2_NOCACHE + /* The SRAM2 bank can optionally made a non cache-able area for use by + DMA engines.*/ + mpuConfigureRegion(MPU_REGION_7, + SRAM2_BASE, + MPU_RASR_ATTR_AP_RW_RW | + MPU_RASR_ATTR_NON_CACHEABLE | + MPU_RASR_SIZE_16K | + MPU_RASR_ENABLE); + mpuEnable(MPU_CTRL_PRIVDEFENA); + + /* Invalidating data cache to make sure that the MPU settings are taken + immediately.*/ + SCB_CleanInvalidateDCache(); +#endif + + /* Programmable voltage detector enable.*/ +#if STM32_PVD_ENABLE + PWR->CR1 |= PWR_CR1_PVDE | (STM32_PLS & STM32_PLS_MASK); +#endif /* STM32_PVD_ENABLE */ +} + +/** + * @brief STM32F2xx clocks and PLL initialization. + * @note All the involved constants come from the file @p board.h. + * @note This function should be invoked just after the system reset. + * + * @special + */ +void stm32_clock_init(void) { + +#if !STM32_NO_INIT + /* PWR clock enabled.*/ +#if defined(HAL_USE_RTC) && defined(RCC_APB1ENR_RTCEN) + RCC->APB1ENR = RCC_APB1ENR_PWREN | RCC_APB1ENR_RTCEN; +#else + RCC->APB1ENR = RCC_APB1ENR_PWREN; +#endif + + /* PWR initialization.*/ + PWR->CR1 = STM32_VOS; + + /* HSI setup, it enforces the reset situation in order to handle possible + problems with JTAG probes and re-initializations.*/ + RCC->CR |= RCC_CR_HSION; /* Make sure HSI is ON. */ + while (!(RCC->CR & RCC_CR_HSIRDY)) + ; /* Wait until HSI is stable. */ + + /* HSI is selected as new source without touching the other fields in + CFGR. Clearing the register has to be postponed after HSI is the + new source.*/ + RCC->CFGR &= ~RCC_CFGR_SW; /* Reset SW */ + RCC->CFGR |= RCC_CFGR_SWS_HSI; /* Select HSI as internal*/ + while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) + ; /* Wait until HSI is selected. */ + + /* Registers finally cleared to reset values.*/ + RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value. */ + RCC->CFGR = 0; /* CFGR reset value. */ + +#if STM32_HSE_ENABLED + /* HSE activation.*/ +#if defined(STM32_HSE_BYPASS) + /* HSE Bypass.*/ + RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP; +#else + /* No HSE Bypass.*/ + RCC->CR |= RCC_CR_HSEON; +#endif + while ((RCC->CR & RCC_CR_HSERDY) == 0) + ; /* Waits until HSE is stable. */ +#endif + +#if STM32_LSI_ENABLED + /* LSI activation.*/ + RCC->CSR |= RCC_CSR_LSION; + while ((RCC->CSR & RCC_CSR_LSIRDY) == 0) + ; /* Waits until LSI is stable. */ +#endif + +#if STM32_ACTIVATE_PLL + /* PLL activation.*/ + RCC->PLLCFGR = STM32_PLLQ | STM32_PLLSRC | STM32_PLLP | STM32_PLLN | + STM32_PLLM; + RCC->CR |= RCC_CR_PLLON; + + /* Synchronization with voltage regulator stabilization.*/ + while ((PWR->CSR1 & PWR_CSR1_VOSRDY) == 0) + ; /* Waits until power regulator is stable. */ + +#if STM32_OVERDRIVE_REQUIRED + /* Overdrive activation performed after activating the PLL in order to save + time as recommended in RM in "Entering Over-drive mode" paragraph.*/ + PWR->CR1 |= PWR_CR1_ODEN; + while (!(PWR->CSR1 & PWR_CSR1_ODRDY)) + ; + PWR->CR1 |= PWR_CR1_ODSWEN; + while (!(PWR->CSR1 & PWR_CSR1_ODSWRDY)) + ; +#endif /* STM32_OVERDRIVE_REQUIRED */ + + /* Waiting for PLL lock.*/ + while (!(RCC->CR & RCC_CR_PLLRDY)) + ; +#endif /* STM32_OVERDRIVE_REQUIRED */ + +#if STM32_ACTIVATE_PLLI2S + /* PLLI2S activation.*/ + RCC->PLLI2SCFGR = STM32_PLLI2SR | STM32_PLLI2SN; + RCC->CR |= RCC_CR_PLLI2SON; + + /* Waiting for PLL lock.*/ + while (!(RCC->CR & RCC_CR_PLLI2SRDY)) + ; +#endif + +#if STM32_ACTIVATE_PLLSAI + /* PLLSAI activation.*/ + RCC->PLLSAICFGR = STM32_PLLSAIR | STM32_PLLSAIQ | STM32_PLLSAIP | + STM32_PLLSAIN; + RCC->CR |= RCC_CR_PLLSAION; + + /* Waiting for PLL lock.*/ + while (!(RCC->CR & RCC_CR_PLLSAIRDY)) + ; +#endif + + /* Other clock-related settings (dividers, MCO etc).*/ + RCC->CFGR = STM32_MCO2SEL | STM32_MCO2PRE | STM32_MCO1PRE | STM32_I2SSRC | + STM32_MCO1SEL | STM32_RTCPRE | STM32_PPRE2 | STM32_PPRE1 | + STM32_HPRE; + + /* DCKCFGR1 register initialization, note, must take care of the _OFF + pseudo settings.*/ + { + uint32_t dckcfgr1 = STM32_PLLI2SDIVQ | STM32_PLLSAIDIVQ | STM32_PLLSAIDIVR; +#if STM32_SAI2SEL != STM32_SAI2SEL_OFF + dckcfgr1 |= STM32_SAI2SEL; +#endif +#if STM32_SAI1SEL != STM32_SAI1SEL_OFF + dckcfgr1 |= STM32_SAI1SEL; +#endif + RCC->DCKCFGR1 = dckcfgr1; + } + + /* Peripheral clock sources.*/ + RCC->DCKCFGR2 = STM32_SDMMCSEL | STM32_CK48MSEL | STM32_CECSEL | + STM32_LPTIM1SEL | STM32_I2C4SEL | STM32_I2C3SEL | + STM32_I2C2SEL | STM32_I2C1SEL | STM32_UART8SEL | + STM32_UART7SEL | STM32_USART6SEL | STM32_UART5SEL | + STM32_UART4SEL | STM32_USART3SEL | STM32_USART2SEL | + STM32_USART1SEL; + + /* Flash setup.*/ + FLASH->ACR = FLASH_ACR_ARTEN | FLASH_ACR_PRFTEN | STM32_FLASHBITS; + + /* Switching to the configured clock source if it is different from HSI.*/ +#if (STM32_SW != STM32_SW_HSI) + RCC->CFGR |= STM32_SW; /* Switches on the selected clock source. */ + while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2)) + ; +#endif +#endif /* STM32_NO_INIT */ + + /* SYSCFG clock enabled here because it is a multi-functional unit shared + among multiple drivers.*/ + rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE); +} + +/** @} */ diff --git a/os/hal/ports/STM32/STM32H7xx/hal_lld.h b/os/hal/ports/STM32/STM32H7xx/hal_lld.h new file mode 100644 index 000000000..aebc9f8ab --- /dev/null +++ b/os/hal/ports/STM32/STM32H7xx/hal_lld.h @@ -0,0 +1,2073 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32H7xx/hal_lld.h + * @brief STM32H7xx HAL subsystem low level driver header. + * @pre This module requires the following macros to be defined in the + * @p board.h file: + * - STM32_LSECLK. + * - STM32_LSEDRV. + * - STM32_LSE_BYPASS (optionally). + * - STM32_HSECLK. + * - STM32_HSE_BYPASS (optionally). + * - STM32_VDD (as hundredths of Volt). + * . + * One of the following macros must also be defined: + * - STM32H743xx, STM32H753xx very high-performance MCUs. + * . + * + * @addtogroup HAL + * @{ + */ + +#ifndef HAL_LLD_H +#define HAL_LLD_H + +#include "stm32_registry.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Platform identification macros + * @{ + */ +#if defined(STM32H743xx) || defined(__DOXYGEN__) +#define PLATFORM_NAME "STM32H743 Very High Performance with DSP and FPU" + +#elif defined(STM32H753xx) +#define PLATFORM_NAME "STM32H753 Very High Performance with DSP and FPU" + +#else +#error "STM32H7xx device not specified" +#endif +/** @} */ + +/** + * @name Sub-family identifier + */ +#if !defined(STM32H7XX) || defined(__DOXYGEN__) +#define STM32H7XX +#endif +/** @} */ + +/** + * @name Absolute Maximum Ratings + * @{ + */ +/** + * @brief Absolute maximum system clock. + */ +#define STM32_SYSCLK_MAX 400000000 + +/** + * @brief Absolute maximum HCLK clock. + */ +#define STM32_HCLK_MAX 200000000 + +/** + * @brief Maximum HSE clock frequency. + */ +#define STM32_HSECLK_MAX 48000000 + +/** + * @brief Maximum HSE clock frequency using an external source. + */ +#define STM32_HSECLK_BYP_MAX 50000000 + +/** + * @brief Minimum HSE clock frequency. + */ +#define STM32_HSECLK_MIN 4000000 + +/** + * @brief Minimum HSE clock frequency. + */ +#define STM32_HSECLK_BYP_MIN 4000000 + +/** + * @brief Maximum LSE clock frequency. + */ +#define STM32_LSECLK_MAX 32768 + +/** + * @brief Maximum LSE clock frequency. + */ +#define STM32_LSECLK_BYP_MAX 1000000 + +/** + * @brief Minimum LSE clock frequency. + */ +#define STM32_LSECLK_MIN 32768 + +/** + * @brief Maximum PLLs input clock frequency using VCOL. + */ +#define STM32_PLLINL_MAX 2000000 + +/** + * @brief Minimum PLLs input clock frequency using VCOL. + */ +#define STM32_PLLINL_MIN 1000000 + +/** + * @brief Maximum PLLs input clock frequency using VCOH. + */ +#define STM32_PLLINH_MAX 16000000 + +/** + * @brief Minimum PLLs input clock frequency using VCOH. + */ +#define STM32_PLLINH_MIN 2000000 + +/** + * @brief Maximum PLLs VCOL clock frequency. + */ +#define STM32_PLLVCOL_MAX 420000000 + +/** + * @brief Minimum PLLs VCOL clock frequency. + */ +#define STM32_PLLVCOL_MIN 150000000 + +/** + * @brief Maximum PLLs VCOH clock frequency. + */ +#define STM32_PLLVCOH_MAX 836000000 + +/** + * @brief Minimum PLLs VCOH clock frequency. + */ +#define STM32_PLLVCOH_MIN 192000000 + +/** + * @brief Maximum PLL output clock frequency. + */ +#define STM32_PLLOUT_MAX 400000000 + +/** + * @brief Minimum PLL output clock frequency. + */ +#define STM32_PLLOUT_MIN 1500000 + +/** + * @brief Maximum APB1 clock frequency. + */ +#define STM32_PCLK1_MAX (STM32_HCLK_MAX / 2) + +/** + * @brief Maximum APB2 clock frequency. + */ +#define STM32_PCLK2_MAX (STM32_HCLK_MAX / 2) + +/** + * @brief Maximum APB3 clock frequency. + */ +#define STM32_PCLK3_MAX (STM32_HCLK_MAX / 1) + +/** + * @brief Maximum APB4 clock frequency. + */ +#define STM32_PCLK4_MAX (STM32_HCLK_MAX / 2) + +/** + * @brief Maximum SPI1, SPI2 and SPI3 max clock frequency. + */ +#define STM32_SPI123_MAX 133000000 + +/** + * @brief Maximum SPI4, SPI5 and SPI6 max clock frequency. + */ +#define STM32_SPI456_MAX 100000000 +/** @} */ + +/** + * @name Internal clock sources + * @{ + */ +#define STM32_HSICLK 16000000 /**< High speed internal clock. */ +#define STM32_LSICLK 32000 /**< Low speed internal clock. */ +/** @} */ + +/** + * @name PWR_CR register bits definitions + * @{ + */ +#define STM32_VOS_SCALE3 (PWR_CR1_VOS_0) +#define STM32_VOS_SCALE2 (PWR_CR1_VOS_1) +#define STM32_VOS_SCALE1 (PWR_CR1_VOS_1 | PWR_CR1_VOS_0) + +#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */ +#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */ +#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 1. */ +#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 2. */ +#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 3. */ +#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 4. */ +#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 5. */ +#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 6. */ +#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 7. */ +/** @} */ + +/** + * @name RCC_PLLCFGR register bits definitions + * @{ + */ +#define STM32_PLLP_MASK (3 << 16) /**< PLLP mask. */ +#define STM32_PLLP_DIV2 (0 << 16) /**< PLL clock divided by 2. */ +#define STM32_PLLP_DIV4 (1 << 16) /**< PLL clock divided by 4. */ +#define STM32_PLLP_DIV6 (2 << 16) /**< PLL clock divided by 6. */ +#define STM32_PLLP_DIV8 (3 << 16) /**< PLL clock divided by 8. */ + +#define STM32_PLLSRC_HSI (0 << 22) /**< PLL clock source is HSI. */ +#define STM32_PLLSRC_HSE (1 << 22) /**< PLL clock source is HSE. */ +/** @} */ + +/** + * @name RCC_CFGR register bits definitions + * @{ + */ +#define STM32_SW_MASK (3 << 0) /**< SW mask. */ +#define STM32_SW_HSI (0 << 0) /**< SYSCLK source is HSI. */ +#define STM32_SW_HSE (1 << 0) /**< SYSCLK source is HSE. */ +#define STM32_SW_PLL (2 << 0) /**< SYSCLK source is PLL. */ + +#define STM32_HPRE_MASK (15 << 4) /**< HPRE mask. */ +#define STM32_HPRE_DIV1 (0 << 4) /**< SYSCLK divided by 1. */ +#define STM32_HPRE_DIV2 (8 << 4) /**< SYSCLK divided by 2. */ +#define STM32_HPRE_DIV4 (9 << 4) /**< SYSCLK divided by 4. */ +#define STM32_HPRE_DIV8 (10 << 4) /**< SYSCLK divided by 8. */ +#define STM32_HPRE_DIV16 (11 << 4) /**< SYSCLK divided by 16. */ +#define STM32_HPRE_DIV64 (12 << 4) /**< SYSCLK divided by 64. */ +#define STM32_HPRE_DIV128 (13 << 4) /**< SYSCLK divided by 128. */ +#define STM32_HPRE_DIV256 (14 << 4) /**< SYSCLK divided by 256. */ +#define STM32_HPRE_DIV512 (15 << 4) /**< SYSCLK divided by 512. */ + +#define STM32_PPRE1_MASK (7 << 10) /**< PPRE1 mask. */ +#define STM32_PPRE1_DIV1 (0 << 10) /**< HCLK divided by 1. */ +#define STM32_PPRE1_DIV2 (4 << 10) /**< HCLK divided by 2. */ +#define STM32_PPRE1_DIV4 (5 << 10) /**< HCLK divided by 4. */ +#define STM32_PPRE1_DIV8 (6 << 10) /**< HCLK divided by 8. */ +#define STM32_PPRE1_DIV16 (7 << 10) /**< HCLK divided by 16. */ + +#define STM32_PPRE2_MASK (7 << 13) /**< PPRE2 mask. */ +#define STM32_PPRE2_DIV1 (0 << 13) /**< HCLK divided by 1. */ +#define STM32_PPRE2_DIV2 (4 << 13) /**< HCLK divided by 2. */ +#define STM32_PPRE2_DIV4 (5 << 13) /**< HCLK divided by 4. */ +#define STM32_PPRE2_DIV8 (6 << 13) /**< HCLK divided by 8. */ +#define STM32_PPRE2_DIV16 (7 << 13) /**< HCLK divided by 16. */ + +#define STM32_RTCPRE_MASK (31 << 16) /**< RTCPRE mask. */ + +#define STM32_MCO1SEL_MASK (3 << 21) /**< MCO1 mask. */ +#define STM32_MCO1SEL_HSI (0 << 21) /**< HSI clock on MCO1 pin. */ +#define STM32_MCO1SEL_LSE (1 << 21) /**< LSE clock on MCO1 pin. */ +#define STM32_MCO1SEL_HSE (2 << 21) /**< HSE clock on MCO1 pin. */ +#define STM32_MCO1SEL_PLL (3 << 21) /**< PLL clock on MCO1 pin. */ + +#define STM32_I2SSRC_MASK (1 << 23) /**< I2CSRC mask. */ +#define STM32_I2SSRC_PLLI2S (0 << 23) /**< I2SSRC is PLLI2S. */ +#define STM32_I2SSRC_CKIN (1 << 23) /**< I2S_CKIN is PLLI2S. */ +#define STM32_I2SSRC_OFF (1 << 23) /**< ISS clock not required. */ + +#define STM32_MCO1PRE_MASK (7 << 24) /**< MCO1PRE mask. */ +#define STM32_MCO1PRE_DIV1 (0 << 24) /**< MCO1 divided by 1. */ +#define STM32_MCO1PRE_DIV2 (4 << 24) /**< MCO1 divided by 2. */ +#define STM32_MCO1PRE_DIV3 (5 << 24) /**< MCO1 divided by 3. */ +#define STM32_MCO1PRE_DIV4 (6 << 24) /**< MCO1 divided by 4. */ +#define STM32_MCO1PRE_DIV5 (7 << 24) /**< MCO1 divided by 5. */ + +#define STM32_MCO2PRE_MASK (7 << 27) /**< MCO2PRE mask. */ +#define STM32_MCO2PRE_DIV1 (0 << 27) /**< MCO2 divided by 1. */ +#define STM32_MCO2PRE_DIV2 (4 << 27) /**< MCO2 divided by 2. */ +#define STM32_MCO2PRE_DIV3 (5 << 27) /**< MCO2 divided by 3. */ +#define STM32_MCO2PRE_DIV4 (6 << 27) /**< MCO2 divided by 4. */ +#define STM32_MCO2PRE_DIV5 (7 << 27) /**< MCO2 divided by 5. */ + +#define STM32_MCO2SEL_MASK (3 << 30) /**< MCO2 mask. */ +#define STM32_MCO2SEL_SYSCLK (0 << 30) /**< SYSCLK clock on MCO2 pin. */ +#define STM32_MCO2SEL_PLLI2S (1 << 30) /**< PLLI2S clock on MCO2 pin. */ +#define STM32_MCO2SEL_HSE (2 << 30) /**< HSE clock on MCO2 pin. */ +#define STM32_MCO2SEL_PLL (3 << 30) /**< PLL clock on MCO2 pin. */ + +/** + * @name RCC_PLLI2SCFGR register bits definitions + * @{ + */ +#define STM32_PLLI2SN_MASK (511 << 6) /**< PLLI2SN mask. */ +#define STM32_PLLI2SR_MASK (7 << 28) /**< PLLI2SR mask. */ +/** @} */ + +/** + * @name RCC_DCKCFGR1 register bits definitions + * @{ + */ +#define STM32_PLLSAIDIVR_MASK (3 << 16) /**< PLLSAIDIVR mask. */ +#define STM32_PLLSAIDIVR_DIV2 (0 << 16) /**< LCD_CLK is R divided by 2. */ +#define STM32_PLLSAIDIVR_DIV4 (1 << 16) /**< LCD_CLK is R divided by 4. */ +#define STM32_PLLSAIDIVR_DIV8 (2 << 16) /**< LCD_CLK is R divided by 8. */ +#define STM32_PLLSAIDIVR_DIV16 (3 << 16) /**< LCD_CLK is R divided by 16.*/ + +#define STM32_SAI1SEL_MASK (3 << 20) /**< SAI1SEL mask. */ +#define STM32_SAI1SEL_SAIPLL (0 << 20) /**< SAI1 source is SAIPLL. */ +#define STM32_SAI1SEL_I2SPLL (1 << 20) /**< SAI1 source is I2SPLL. */ +#define STM32_SAI1SEL_CKIN (2 << 20) /**< SAI1 source is I2S_CKIN. */ +#define STM32_SAI1SEL_OFF 0xFFFFFFFFU /**< SAI1 clock is not required.*/ + +#define STM32_SAI2SEL_MASK (3 << 22) /**< SAI2SEL mask. */ +#define STM32_SAI2SEL_SAIPLL (0 << 22) /**< SAI2 source is SAIPLL. */ +#define STM32_SAI2SEL_I2SPLL (1 << 22) /**< SAI2 source is I2SPLL. */ +#define STM32_SAI2SEL_CKIN (2 << 22) /**< SAI2 source is I2S_CKIN. */ +#define STM32_SAI2SEL_OFF 0xFFFFFFFFU /**< SAI2 clock is not required.*/ + +#define STM32_TIMPRE_MASK (1 << 24) /**< TIMPRE mask. */ +#define STM32_TIMPRE_PCLK (0 << 24) /**< TIM clocks from PCLKx. */ +#define STM32_TIMPRE_HCLK (1 << 24) /**< TIM clocks from HCLK. */ +/** @} */ + +/** + * @name RCC_DCKCFGR2 register bits definitions + * @{ + */ +#define STM32_USART1SEL_MASK (3 << 0) /**< USART1SEL mask. */ +#define STM32_USART1SEL_PCLK2 (0 << 0) /**< USART1 source is PCLK2. */ +#define STM32_USART1SEL_SYSCLK (1 << 0) /**< USART1 source is SYSCLK. */ +#define STM32_USART1SEL_HSI (2 << 0) /**< USART1 source is HSI. */ +#define STM32_USART1SEL_LSE (3 << 0) /**< USART1 source is LSE. */ + +#define STM32_USART2SEL_MASK (3 << 2) /**< USART2 mask. */ +#define STM32_USART2SEL_PCLK1 (0 << 2) /**< USART2 source is PCLK1. */ +#define STM32_USART2SEL_SYSCLK (1 << 2) /**< USART2 source is SYSCLK. */ +#define STM32_USART2SEL_HSI (2 << 2) /**< USART2 source is HSI. */ +#define STM32_USART2SEL_LSE (3 << 2) /**< USART2 source is LSE. */ + +#define STM32_USART3SEL_MASK (3 << 4) /**< USART3 mask. */ +#define STM32_USART3SEL_PCLK1 (0 << 4) /**< USART3 source is PCLK1. */ +#define STM32_USART3SEL_SYSCLK (1 << 4) /**< USART3 source is SYSCLK. */ +#define STM32_USART3SEL_HSI (2 << 4) /**< USART3 source is HSI. */ +#define STM32_USART3SEL_LSE (3 << 4) /**< USART3 source is LSE. */ + +#define STM32_UART4SEL_MASK (3 << 6) /**< UART4 mask. */ +#define STM32_UART4SEL_PCLK1 (0 << 6) /**< UART4 source is PCLK1. */ +#define STM32_UART4SEL_SYSCLK (1 << 6) /**< UART4 source is SYSCLK. */ +#define STM32_UART4SEL_HSI (2 << 6) /**< UART4 source is HSI. */ +#define STM32_UART4SEL_LSE (3 << 6) /**< UART4 source is LSE. */ + +#define STM32_UART5SEL_MASK (3 << 8) /**< UART5 mask. */ +#define STM32_UART5SEL_PCLK1 (0 << 8) /**< UART5 source is PCLK1. */ +#define STM32_UART5SEL_SYSCLK (1 << 8) /**< UART5 source is SYSCLK. */ +#define STM32_UART5SEL_HSI (2 << 8) /**< UART5 source is HSI. */ +#define STM32_UART5SEL_LSE (3 << 8) /**< UART5 source is LSE. */ + +#define STM32_USART6SEL_MASK (3 << 10) /**< USART6SEL mask. */ +#define STM32_USART6SEL_PCLK2 (0 << 10) /**< USART6 source is PCLK2. */ +#define STM32_USART6SEL_SYSCLK (1 << 10) /**< USART6 source is SYSCLK. */ +#define STM32_USART6SEL_HSI (2 << 10) /**< USART6 source is HSI. */ +#define STM32_USART6SEL_LSE (3 << 10) /**< USART6 source is LSE. */ + +#define STM32_UART7SEL_MASK (3 << 12) /**< UART7 mask. */ +#define STM32_UART7SEL_PCLK1 (0 << 12) /**< UART7 source is PCLK1. */ +#define STM32_UART7SEL_SYSCLK (1 << 12) /**< UART7 source is SYSCLK. */ +#define STM32_UART7SEL_HSI (2 << 12) /**< UART7 source is HSI. */ +#define STM32_UART7SEL_LSE (3 << 12) /**< UART7 source is LSE. */ + +#define STM32_UART8SEL_MASK (3 << 14) /**< UART8 mask. */ +#define STM32_UART8SEL_PCLK1 (0 << 14) /**< UART8 source is PCLK1. */ +#define STM32_UART8SEL_SYSCLK (1 << 14) /**< UART8 source is SYSCLK. */ +#define STM32_UART8SEL_HSI (2 << 14) /**< UART8 source is HSI. */ +#define STM32_UART8SEL_LSE (3 << 14) /**< UART8 source is LSE. */ + +#define STM32_I2C1SEL_MASK (3 << 16) /**< I2C1SEL mask. */ +#define STM32_I2C1SEL_PCLK1 (0 << 16) /**< I2C1 source is PCLK1. */ +#define STM32_I2C1SEL_SYSCLK (1 << 16) /**< I2C1 source is SYSCLK. */ +#define STM32_I2C1SEL_HSI (2 << 16) /**< I2C1 source is HSI. */ +#define STM32_I2C1SEL_LSE (3 << 16) /**< I2C1 source is LSE. */ + +#define STM32_I2C2SEL_MASK (3 << 18) /**< I2C2SEL mask. */ +#define STM32_I2C2SEL_PCLK1 (0 << 18) /**< I2C2 source is PCLK1. */ +#define STM32_I2C2SEL_SYSCLK (1 << 18) /**< I2C2 source is SYSCLK. */ +#define STM32_I2C2SEL_HSI (2 << 18) /**< I2C2 source is HSI. */ +#define STM32_I2C2SEL_LSE (3 << 18) /**< I2C2 source is LSE. */ + +#define STM32_I2C3SEL_MASK (3 << 20) /**< I2C3SEL mask. */ +#define STM32_I2C3SEL_PCLK1 (0 << 20) /**< I2C3 source is PCLK1. */ +#define STM32_I2C3SEL_SYSCLK (1 << 20) /**< I2C3 source is SYSCLK. */ +#define STM32_I2C3SEL_HSI (2 << 20) /**< I2C3 source is HSI. */ +#define STM32_I2C3SEL_LSE (3 << 20) /**< I2C3 source is LSE. */ + +#define STM32_I2C4SEL_MASK (3 << 22) /**< I2C4SEL mask. */ +#define STM32_I2C4SEL_PCLK1 (0 << 22) /**< I2C4 source is PCLK1. */ +#define STM32_I2C4SEL_SYSCLK (1 << 22) /**< I2C4 source is SYSCLK. */ +#define STM32_I2C4SEL_HSI (2 << 22) /**< I2C4 source is HSI. */ +#define STM32_I2C4SEL_LSE (3 << 22) /**< I2C4 source is LSE. */ + +#define STM32_LPTIM1SEL_MASK (3 << 24) /**< LPTIM1SEL mask. */ +#define STM32_LPTIM1SEL_PCLK1 (0 << 24) /**< LPTIM1 source is PCLK1. */ +#define STM32_LPTIM1SEL_LSI (1 << 24) /**< LPTIM1 source is LSI. */ +#define STM32_LPTIM1SEL_HSI (2 << 24) /**< LPTIM1 source is HSI. */ +#define STM32_LPTIM1SEL_LSE (3 << 24) /**< LPTIM1 source is LSE. */ + +#define STM32_CECSEL_MASK (1 << 26) /**< CECSEL mask. */ +#define STM32_CECSEL_LSE (0 << 26) /**< CEC source is LSE. */ +#define STM32_CECSEL_HSIDIV488 (1 << 26) /**< CEC source is HSI/488. */ + +#define STM32_CK48MSEL_MASK (1 << 27) /**< CK48MSEL mask. */ +#define STM32_CK48MSEL_PLL (0 << 27) /**< PLL48CLK source is PLL. */ +#define STM32_CK48MSEL_PLLSAI (1 << 27) /**< PLL48CLK source is PLLSAI. */ + +#define STM32_SDMMCSEL_MASK (1 << 28) /**< SDMMCSEL mask. */ +#define STM32_SDMMCSEL_PLL48CLK (0 << 28) /**< SDMMC source is PLL48CLK. */ +#define STM32_SDMMCSEL_SYSCLK (1 << 28) /**< SDMMC source is SYSCLK. */ +/** @} */ + +/** + * @name RCC_BDCR register bits definitions + * @{ + */ +#define STM32_RTCSEL_MASK (3 << 8) /**< RTC source mask. */ +#define STM32_RTCSEL_NOCLOCK (0 << 8) /**< No RTC source. */ +#define STM32_RTCSEL_LSE (1 << 8) /**< RTC source is LSE. */ +#define STM32_RTCSEL_LSI (2 << 8) /**< RTC source is LSI. */ +#define STM32_RTCSEL_HSEDIV (3 << 8) /**< RTC source is HSE divided. */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief Disables the PWR/RCC initialization in the HAL. + */ +#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__) +#define STM32_NO_INIT FALSE +#endif + +/** + * @brief Enables or disables the programmable voltage detector. + */ +#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__) +#define STM32_PVD_ENABLE FALSE +#endif + +/** + * @brief Sets voltage level for programmable voltage detector. + */ +#if !defined(STM32_PLS) || defined(__DOXYGEN__) +#define STM32_PLS STM32_PLS_LEV0 +#endif + +/** + * @brief Enables the backup RAM regulator. + */ +#if !defined(STM32_BKPRAM_ENABLE) || defined(__DOXYGEN__) +#define STM32_BKPRAM_ENABLE FALSE +#endif + +/** + * @brief Enables or disables the HSI clock source. + */ +#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__) +#define STM32_HSI_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the LSI clock source. + */ +#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__) +#define STM32_LSI_ENABLED FALSE +#endif + +/** + * @brief Enables or disables the HSE clock source. + */ +#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__) +#define STM32_HSE_ENABLED TRUE +#endif + +/** + * @brief Enables or disables the LSE clock source. + */ +#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__) +#define STM32_LSE_ENABLED TRUE +#endif + +/** + * @brief USB/SDIO clock setting. + */ +#if !defined(STM32_CLOCK48_REQUIRED) || defined(__DOXYGEN__) +#define STM32_CLOCK48_REQUIRED TRUE +#endif + +/** + * @brief Main clock source selection. + * @note If the selected clock source is not the PLL then the PLL is not + * initialized and started. + * @note The default value is calculated for a 216MHz system clock from + * an external 25MHz HSE clock. + */ +#if !defined(STM32_SW) || defined(__DOXYGEN__) +#define STM32_SW STM32_SW_PLL +#endif + +/** + * @brief Clock source for the PLLs. + * @note This setting has only effect if the PLL is selected as the + * system clock source. + * @note The default value is calculated for a 216MHz system clock from + * an external 25MHz HSE clock. + */ +#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__) +#define STM32_PLLSRC STM32_PLLSRC_HSE +#endif + +/** + * @brief PLLM divider value. + * @note The allowed values are 2..63. + * @note The default value is calculated for a 216MHz system clock from + * an external 25MHz HSE clock. + */ +#if !defined(STM32_PLLM_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLM_VALUE 25 +#endif + +/** + * @brief PLLN multiplier value. + * @note The allowed values are 192..432. + * @note The default value is calculated for a 216MHz system clock from + * an external 25MHz HSE clock. + */ +#if !defined(STM32_PLLN_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLN_VALUE 432 +#endif + +/** + * @brief PLLP divider value. + * @note The allowed values are 2, 4, 6, 8. + * @note The default value is calculated for a 216MHz system clock from + * an external 25MHz HSE clock. + */ +#if !defined(STM32_PLLP_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLP_VALUE 2 +#endif + +/** + * @brief PLLQ divider value. + * @note The allowed values are 2..15. + * @note The default value is calculated for a 216MHz system clock from + * an external 25MHz HSE clock. + */ +#if !defined(STM32_PLLQ_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLQ_VALUE 9 +#endif + +/** + * @brief AHB prescaler value. + */ +#if !defined(STM32_HPRE) || defined(__DOXYGEN__) +#define STM32_HPRE STM32_HPRE_DIV1 +#endif + +/** + * @brief APB1 prescaler value. + */ +#if !defined(STM32_PPRE1) || defined(__DOXYGEN__) +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#endif + +/** + * @brief APB2 prescaler value. + */ +#if !defined(STM32_PPRE2) || defined(__DOXYGEN__) +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#endif + +/** + * @brief RTC clock source. + */ +#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__) +#define STM32_RTCSEL STM32_RTCSEL_LSE +#endif + +/** + * @brief RTC HSE prescaler value. + * @note The allowed values are 2..31. + */ +#if !defined(STM32_RTCPRE_VALUE) || defined(__DOXYGEN__) +#define STM32_RTCPRE_VALUE 25 +#endif + +/** + * @brief MCO1 clock source value. + * @note The default value outputs HSI clock on MCO1 pin. + */ +#if !defined(STM32_MCO1SEL) || defined(__DOXYGEN__) +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#endif + +/** + * @brief MCO1 prescaler value. + * @note The default value outputs HSI clock on MCO1 pin. + */ +#if !defined(STM32_MCO1PRE) || defined(__DOXYGEN__) +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#endif + +/** + * @brief MCO2 clock source value. + * @note The default value outputs SYSCLK / 4 on MCO2 pin. + */ +#if !defined(STM32_MCO2SEL) || defined(__DOXYGEN__) +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#endif + +/** + * @brief MCO2 prescaler value. + * @note The default value outputs SYSCLK / 4 on MCO2 pin. + */ +#if !defined(STM32_MCO2PRE) || defined(__DOXYGEN__) +#define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#endif + +/** + * @brief I2S clock source. + */ +#if !defined(STM32_I2SSRC) || defined(__DOXYGEN__) +#define STM32_I2SSRC STM32_I2SSRC_PLLI2S +#endif + +/** + * @brief PLLI2SN multiplier value. + * @note The allowed values are 49..432. + */ +#if !defined(STM32_PLLI2SN_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLI2SN_VALUE 192 +#endif + +/** + * @brief PLLI2SP divider value. + * @note The allowed values are 2, 4, 6 and 8. + */ +#if !defined(STM32_PLLI2SP_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLI2SP_VALUE 4 +#endif + +/** + * @brief PLLI2SQ divider value. + * @note The allowed values are 2..15. + */ +#if !defined(STM32_PLLI2SQ_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLI2SQ_VALUE 4 +#endif + +/** + * @brief PLLI2SDIVQ divider value (SAI clock divider). + */ +#if !defined(STM32_PLLI2SDIVQ_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLI2SDIVQ_VALUE 2 +#endif + +/** + * @brief PLLI2SR divider value. + * @note The allowed values are 2..7. + */ +#if !defined(STM32_PLLI2SR_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLI2SR_VALUE 4 +#endif + +/** + * @brief PLLSAIN multiplier value. + * @note The allowed values are 49..432. + */ +#if !defined(STM32_PLLSAIN_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLSAIN_VALUE 192 +#endif + +/** + * @brief PLLSAIP divider value. + * @note The allowed values are 2, 4, 6 and 8. + */ +#if !defined(STM32_PLLSAIP_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLSAIP_VALUE 4 +#endif + +/** + * @brief PLLSAIQ divider value. + * @note The allowed values are 2..15. + */ +#if !defined(STM32_PLLSAIQ_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLSAIQ_VALUE 4 +#endif + +/** + * @brief PLLSAIR divider value. + * @note The allowed values are 2..7. + */ +#if !defined(STM32_PLLSAIR_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLSAIR_VALUE 4 +#endif + +/** + * @brief PLLSAIDIVQ divider value (SAI clock divider). + */ +#if !defined(STM32_PLLSAIDIVQ_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLSAIDIVQ_VALUE 2 +#endif + +/** + * @brief PLLSAIDIVR divider value (LCD clock divider). + */ +#if !defined(STM32_PLLSAIDIVR_VALUE) || defined(__DOXYGEN__) +#define STM32_PLLSAIDIVR_VALUE 2 +#endif + +/** + * @brief SAI1SEL value (SAI1 clock source). + */ +#if !defined(STM32_SAI1SEL) || defined(__DOXYGEN__) +#define STM32_SAI1SEL STM32_SAI1SEL_OFF +#endif + +/** + * @brief SAI2SEL value (SAI2 clock source). + */ +#if !defined(STM32_SAI2SEL) || defined(__DOXYGEN__) +#define STM32_SAI2SEL STM32_SAI2SEL_OFF +#endif + +/** + * @brief LCD-TFT clock enable switch. + */ +#if !defined(STM32_LCDTFT_REQUIRED) || defined(__DOXYGEN__) +#define STM32_LCDTFT_REQUIRED FALSE +#endif + +/** + * @brief USART1 clock source. + */ +#if !defined(STM32_USART1SEL) || defined(__DOXYGEN__) +#define STM32_USART1SEL STM32_USART1SEL_PCLK2 +#endif + +/** + * @brief USART2 clock source. + */ +#if !defined(STM32_USART2SEL) || defined(__DOXYGEN__) +#define STM32_USART2SEL STM32_USART2SEL_PCLK1 +#endif + +/** + * @brief USART3 clock source. + */ +#if !defined(STM32_USART3SEL) || defined(__DOXYGEN__) +#define STM32_USART3SEL STM32_USART3SEL_PCLK1 +#endif + +/** + * @brief UART4 clock source. + */ +#if !defined(STM32_UART4SEL) || defined(__DOXYGEN__) +#define STM32_UART4SEL STM32_UART4SEL_PCLK1 +#endif + +/** + * @brief UART5 clock source. + */ +#if !defined(STM32_UART5SEL) || defined(__DOXYGEN__) +#define STM32_UART5SEL STM32_UART5SEL_PCLK1 +#endif + +/** + * @brief USART6 clock source. + */ +#if !defined(STM32_USART6SEL) || defined(__DOXYGEN__) +#define STM32_USART6SEL STM32_USART6SEL_PCLK2 +#endif + +/** + * @brief UART7 clock source. + */ +#if !defined(STM32_UART7SEL) || defined(__DOXYGEN__) +#define STM32_UART7SEL STM32_UART7SEL_PCLK1 +#endif + +/** + * @brief UART8 clock source. + */ +#if !defined(STM32_UART8SEL) || defined(__DOXYGEN__) +#define STM32_UART8SEL STM32_UART8SEL_PCLK1 +#endif + +/** + * @brief I2C1 clock source. + */ +#if !defined(STM32_I2C1SEL) || defined(__DOXYGEN__) +#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1 +#endif + +/** + * @brief I2C2 clock source. + */ +#if !defined(STM32_I2C2SEL) || defined(__DOXYGEN__) +#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1 +#endif + +/** + * @brief I2C3 clock source. + */ +#if !defined(STM32_I2C3SEL) || defined(__DOXYGEN__) +#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1 +#endif + +/** + * @brief I2C4 clock source. + */ +#if !defined(STM32_I2C4SEL) || defined(__DOXYGEN__) +#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1 +#endif + +/** + * @brief LPTIM1 clock source. + */ +#if !defined(STM32_LPTIM1SEL) || defined(__DOXYGEN__) +#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 +#endif + +/** + * @brief CEC clock source. + */ +#if !defined(STM32_CECSEL) || defined(__DOXYGEN__) +#define STM32_CECSEL STM32_CECSEL_LSE +#endif + +/** + * @brief PLL48CLK clock source. + */ +#if !defined(STM32_CK48MSEL) || defined(__DOXYGEN__) +#define STM32_CK48MSEL STM32_CK48MSEL_PLL +#endif + +/** + * @brief SDMMC clock source. + */ +#if !defined(STM32_SDMMCSEL) || defined(__DOXYGEN__) +#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK +#endif + +/** + * @brief SRAM2 cache-ability. + * @note This setting uses the MPU region 7 if at @p TRUE. + */ +#if !defined(STM32_SRAM2_NOCACHE) || defined(__DOXYGEN__) +#define STM32_SRAM2_NOCACHE FALSE +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/* + * Configuration-related checks. + */ +#if !defined(STM32H7xx_MCUCONF) +#error "Using a wrong mcuconf.h file, STM32H7xx_MCUCONF not defined" +#endif + +/* + * Board file checks. + */ +#if !defined(STM32_LSECLK) +#error "STM32_LSECLK not defined in board.h" +#endif +#if !defined(STM32_LSEDRV) +#error "STM32_LSEDRV not defined in board.h" +#endif +#if !defined(STM32_HSECLK) +#error "STM32_HSECLK not defined in board.h" +#endif +#if !defined(STM32_VDD) +#error "STM32_VDD not defined in board.h" +#endif + +/** + * @brief Maximum frequency thresholds and wait states for flash access. + * @note The values are valid for 2.7V to 3.6V supply range. + */ +#if ((STM32_VDD >= 270) && (STM32_VDD <= 360)) || defined(__DOXYGEN__) +#define STM32_0WS_THRESHOLD 30000000 +#define STM32_1WS_THRESHOLD 60000000 +#define STM32_2WS_THRESHOLD 90000000 +#define STM32_3WS_THRESHOLD 120000000 +#define STM32_4WS_THRESHOLD 150000000 +#define STM32_5WS_THRESHOLD 180000000 +#define STM32_6WS_THRESHOLD 210000000 +#define STM32_7WS_THRESHOLD 0 +#define STM32_8WS_THRESHOLD 0 + +#elif (STM32_VDD >= 240) && (STM32_VDD < 270) +#define STM32_0WS_THRESHOLD 24000000 +#define STM32_1WS_THRESHOLD 48000000 +#define STM32_2WS_THRESHOLD 72000000 +#define STM32_3WS_THRESHOLD 96000000 +#define STM32_4WS_THRESHOLD 120000000 +#define STM32_5WS_THRESHOLD 144000000 +#define STM32_6WS_THRESHOLD 168000000 +#define STM32_7WS_THRESHOLD 192000000 +#define STM32_8WS_THRESHOLD 0 + +#elif (STM32_VDD >= 210) && (STM32_VDD < 240) +#define STM32_0WS_THRESHOLD 22000000 +#define STM32_1WS_THRESHOLD 44000000 +#define STM32_2WS_THRESHOLD 66000000 +#define STM32_3WS_THRESHOLD 88000000 +#define STM32_4WS_THRESHOLD 110000000 +#define STM32_5WS_THRESHOLD 132000000 +#define STM32_6WS_THRESHOLD 154000000 +#define STM32_7WS_THRESHOLD 176000000 +#define STM32_8WS_THRESHOLD 198000000 + +#elif (STM32_VDD >= 180) && (STM32_VDD < 210) +#define STM32_0WS_THRESHOLD 20000000 +#define STM32_1WS_THRESHOLD 40000000 +#define STM32_2WS_THRESHOLD 60000000 +#define STM32_3WS_THRESHOLD 80000000 +#define STM32_4WS_THRESHOLD 100000000 +#define STM32_5WS_THRESHOLD 120000000 +#define STM32_6WS_THRESHOLD 140000000 +#define STM32_7WS_THRESHOLD 160000000 +#define STM32_8WS_THRESHOLD 0 + +#else +#error "invalid VDD voltage specified" +#endif + +/* + * HSI related checks. + */ +#if STM32_HSI_ENABLED +#else /* !STM32_HSI_ENABLED */ + +#if STM32_SW == STM32_SW_HSI +#error "HSI not enabled, required by STM32_SW" +#endif + +#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI) +#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC" +#endif + +#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || \ + ((STM32_MCO1SEL == STM32_MCO1SEL_PLL) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI)) +#error "HSI not enabled, required by STM32_MCO1SEL" +#endif + +#if (STM32_MCO2SEL == STM32_MCO2SEL_PLL) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI) +#error "HSI not enabled, required by STM32_MCO2SEL" +#endif + +#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI) +#error "HSI not enabled, required by STM32_I2SSRC" +#endif + +#if ((STM32_SAI1SEL == STM32_SAI1SEL_SAIPLL) || \ + (STM32_SAI1SEL == STM32_SAI1SEL_I2SPLL)) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI) +#error "HSI not enabled, required by STM32_SAI1SEL" +#endif + +#if ((STM32_SAI2SEL == STM32_SAI2SEL_SAIPLL) || \ + (STM32_SAI2SEL == STM32_SAI2SEL_I2SPLL)) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI) +#error "HSI not enabled, required by STM32_SAI2SEL" +#endif + +#if STM32_LCDTFT_REQUIRED && \ + (STM32_PLLSRC == STM32_PLLSRC_HSI) +#error "HSI not enabled, required by STM32_LCDTFT_REQUIRED" +#endif + +#endif /* !STM32_HSI_ENABLED */ + +/* + * HSE related checks. + */ +#if STM32_HSE_ENABLED + +#if STM32_HSECLK == 0 +#error "HSE frequency not defined" +#else /* STM32_HSECLK != 0 */ +#if defined(STM32_HSE_BYPASS) +#if (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_BYP_MAX) +#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_BYP_MAX)" +#endif +#else /* !defined(STM32_HSE_BYPASS) */ +#if (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX) +#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)" +#endif +#endif /* !defined(STM32_HSE_BYPASS) */ +#endif /* STM32_HSECLK != 0 */ +#else /* !STM32_HSE_ENABLED */ + +#if STM32_SW == STM32_SW_HSE +#error "HSE not enabled, required by STM32_SW" +#endif + +#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE) +#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC" +#endif + +#if (STM32_MCO1SEL == STM32_MCO1SEL_HSE) || \ + ((STM32_MCO1SEL == STM32_MCO1SEL_PLL) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSE)) +#error "HSE not enabled, required by STM32_MCO1SEL" +#endif + +#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || \ + ((STM32_MCO2SEL == STM32_MCO2SEL_PLL) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSE)) +#error "HSE not enabled, required by STM32_MCO2SEL" +#endif + +#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSE) +#error "HSE not enabled, required by STM32_I2SSRC" +#endif + +#if ((STM32_SAI1SEL == STM32_SAI1SEL_SAIPLL) | \ + (STM32_SAI1SEL == STM32_SAI1SEL_I2SPLL)) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSE) +#error "HSE not enabled, required by STM32_SAI1SEL" +#endif + +#if ((STM32_SAI2SEL == STM32_SAI2SEL_SAIPLL) | \ + (STM32_SAI2SEL == STM32_SAI2SEL_I2SPLL)) && \ + (STM32_PLLSRC == STM32_PLLSRC_HSE) +#error "HSE not enabled, required by STM32_SAI2SEL" +#endif + +#if STM32_LCDTFT_REQUIRED && \ + (STM32_PLLSRC == STM32_PLLSRC_HSE) +#error "HSE not enabled, required by STM32_LCDTFT_REQUIRED" +#endif + +#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV +#error "HSE not enabled, required by STM32_RTCSEL" +#endif + +#endif /* !STM32_HSE_ENABLED */ + +/* + * LSI related checks. + */ +#if STM32_LSI_ENABLED +#else /* !STM32_LSI_ENABLED */ + +#if STM32_RTCSEL == STM32_RTCSEL_LSI +#error "LSI not enabled, required by STM32_RTCSEL" +#endif + +#endif /* !STM32_LSI_ENABLED */ + +/* + * LSE related checks. + */ +#if STM32_LSE_ENABLED + +#if (STM32_LSECLK == 0) +#error "LSE frequency not defined" +#endif + +#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX) +#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)" +#endif + +#if !defined(STM32_LSEDRV) +#error "STM32_LSEDRV not defined" +#endif + +#if (STM32_LSEDRV >> 3) > 3 +#error "STM32_LSEDRV outside acceptable range ((0<<3)...(3<<3))" +#endif + +#else /* !STM32_LSE_ENABLED */ + +#if STM32_RTCSEL == STM32_RTCSEL_LSE +#error "LSE not enabled, required by STM32_RTCSEL" +#endif + +#if STM32_MCO1SEL == STM32_MCO1SEL_LSE +#error "LSE not enabled, required by STM32_MCO1SEL" +#endif + +#endif /* !STM32_LSE_ENABLED */ + +/** + * @brief STM32_PLLM field. + */ +#if ((STM32_PLLM_VALUE >= 2) && (STM32_PLLM_VALUE <= 63)) || \ + defined(__DOXYGEN__) +#define STM32_PLLM (STM32_PLLM_VALUE << 0) +#else +#error "invalid STM32_PLLM_VALUE value specified" +#endif + +/** + * @brief PLLs input clock frequency. + */ +#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__) +#define STM32_PLLCLKIN (STM32_HSECLK / STM32_PLLM_VALUE) + +#elif STM32_PLLSRC == STM32_PLLSRC_HSI +#define STM32_PLLCLKIN (STM32_HSICLK / STM32_PLLM_VALUE) + +#else +#error "invalid STM32_PLLSRC value specified" +#endif + +/* + * PLLs input frequency range check. + */ +#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX) +#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)" +#endif + +/* + * PLL enable check. + */ +#if (STM32_CLOCK48_REQUIRED && (STM32_CK48MSEL == STM32_CK48MSEL_PLL)) || \ + (STM32_SW == STM32_SW_PLL) || \ + (STM32_MCO1SEL == STM32_MCO1SEL_PLL) || \ + (STM32_MCO2SEL == STM32_MCO2SEL_PLL) || \ + defined(__DOXYGEN__) +/** + * @brief PLL activation flag. + */ +#define STM32_ACTIVATE_PLL TRUE +#else +#define STM32_ACTIVATE_PLL FALSE +#endif + +/** + * @brief STM32_PLLN field. + */ +#if ((STM32_PLLN_VALUE >= 64) && (STM32_PLLN_VALUE <= 432)) || \ + defined(__DOXYGEN__) +#define STM32_PLLN (STM32_PLLN_VALUE << 6) +#else +#error "invalid STM32_PLLN_VALUE value specified" +#endif + +/** + * @brief STM32_PLLP field. + */ +#if (STM32_PLLP_VALUE == 2) || defined(__DOXYGEN__) +#define STM32_PLLP (0 << 16) + +#elif STM32_PLLP_VALUE == 4 +#define STM32_PLLP (1 << 16) + +#elif STM32_PLLP_VALUE == 6 +#define STM32_PLLP (2 << 16) + +#elif STM32_PLLP_VALUE == 8 +#define STM32_PLLP (3 << 16) + +#else +#error "invalid STM32_PLLP_VALUE value specified" +#endif + +/** + * @brief STM32_PLLQ field. + */ +#if ((STM32_PLLQ_VALUE >= 2) && (STM32_PLLQ_VALUE <= 15)) || \ + defined(__DOXYGEN__) +#define STM32_PLLQ (STM32_PLLQ_VALUE << 24) +#else +#error "invalid STM32_PLLQ_VALUE value specified" +#endif + +/** + * @brief PLL VCO frequency. + */ +#define STM32_PLLVCO (STM32_PLLCLKIN * STM32_PLLN_VALUE) + +/* + * PLL VCO frequency range check. + */ +#if (STM32_PLLVCO < STM32_PLLVCO_MIN) || (STM32_PLLVCO > STM32_PLLVCO_MAX) +#error "STM32_PLLVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)" +#endif + +/** + * @brief PLL P output clock frequency. + */ +#define STM32_PLL_P_CLKOUT (STM32_PLLVCO / STM32_PLLP_VALUE) + +/** + * @brief PLL Q output clock frequency. + */ +#define STM32_PLL_Q_CLKOUT (STM32_PLLVCO / STM32_PLLQ_VALUE) + +/* + * PLL output frequency range check. + */ +#if (STM32_PLL_P_CLKOUT < STM32_PLLOUT_MIN) || (STM32_PLL_P_CLKOUT > STM32_PLLOUT_MAX) +#error "STM32_PLL_P_CLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)" +#endif + +/** + * @brief System clock source. + */ +#if STM32_NO_INIT || defined(__DOXYGEN__) +#define STM32_SYSCLK STM32_HSICLK + +#elif (STM32_SW == STM32_SW_HSI) +#define STM32_SYSCLK STM32_HSICLK + +#elif (STM32_SW == STM32_SW_HSE) +#define STM32_SYSCLK STM32_HSECLK + +#elif (STM32_SW == STM32_SW_PLL) +#define STM32_SYSCLK STM32_PLL_P_CLKOUT + +#else +#error "invalid STM32_SW value specified" +#endif + +/* Check on the system clock.*/ +#if STM32_SYSCLK > STM32_SYSCLK_MAX +#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)" +#endif + +/* Calculating VOS settings.*/ +#if STM32_SYSCLK <= 144000000 +#define STM32_VOS STM32_VOS_SCALE3 +#define STM32_OVERDRIVE_REQUIRED FALSE + +#elif STM32_SYSCLK <= 168000000 +#define STM32_VOS STM32_VOS_SCALE2 +#define STM32_OVERDRIVE_REQUIRED FALSE + +#elif STM32_SYSCLK <= 180000000 +#define STM32_VOS STM32_VOS_SCALE1 +#define STM32_OVERDRIVE_REQUIRED FALSE + +#else +#define STM32_VOS STM32_VOS_SCALE1 +#define STM32_OVERDRIVE_REQUIRED TRUE +#endif + +/** + * @brief AHB frequency. + */ +#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__) +#define STM32_HCLK (STM32_SYSCLK / 1) + +#elif STM32_HPRE == STM32_HPRE_DIV2 +#define STM32_HCLK (STM32_SYSCLK / 2) + +#elif STM32_HPRE == STM32_HPRE_DIV4 +#define STM32_HCLK (STM32_SYSCLK / 4) + +#elif STM32_HPRE == STM32_HPRE_DIV8 +#define STM32_HCLK (STM32_SYSCLK / 8) + +#elif STM32_HPRE == STM32_HPRE_DIV16 +#define STM32_HCLK (STM32_SYSCLK / 16) + +#elif STM32_HPRE == STM32_HPRE_DIV64 +#define STM32_HCLK (STM32_SYSCLK / 64) + +#elif STM32_HPRE == STM32_HPRE_DIV128 +#define STM32_HCLK (STM32_SYSCLK / 128) + +#elif STM32_HPRE == STM32_HPRE_DIV256 +#define STM32_HCLK (STM32_SYSCLK / 256) + +#elif STM32_HPRE == STM32_HPRE_DIV512 +#define STM32_HCLK (STM32_SYSCLK / 512) + +#else +#error "invalid STM32_HPRE value specified" +#endif + +/* + * AHB frequency check. + */ +#if STM32_HCLK > STM32_SYSCLK_MAX +#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)" +#endif + +/** + * @brief APB1 frequency. + */ +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) +#define STM32_PCLK1 (STM32_HCLK / 1) + +#elif STM32_PPRE1 == STM32_PPRE1_DIV2 +#define STM32_PCLK1 (STM32_HCLK / 2) + +#elif STM32_PPRE1 == STM32_PPRE1_DIV4 +#define STM32_PCLK1 (STM32_HCLK / 4) + +#elif STM32_PPRE1 == STM32_PPRE1_DIV8 +#define STM32_PCLK1 (STM32_HCLK / 8) + +#elif STM32_PPRE1 == STM32_PPRE1_DIV16 +#define STM32_PCLK1 (STM32_HCLK / 16) + +#else +#error "invalid STM32_PPRE1 value specified" +#endif + +/* + * APB1 frequency check. + */ +#if STM32_PCLK1 > STM32_PCLK1_MAX +#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)" +#endif + +/** + * @brief APB2 frequency. + */ +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) +#define STM32_PCLK2 (STM32_HCLK / 1) + +#elif STM32_PPRE2 == STM32_PPRE2_DIV2 +#define STM32_PCLK2 (STM32_HCLK / 2) + +#elif STM32_PPRE2 == STM32_PPRE2_DIV4 +#define STM32_PCLK2 (STM32_HCLK / 4) + +#elif STM32_PPRE2 == STM32_PPRE2_DIV8 +#define STM32_PCLK2 (STM32_HCLK / 8) + +#elif STM32_PPRE2 == STM32_PPRE2_DIV16 +#define STM32_PCLK2 (STM32_HCLK / 16) + +#else +#error "invalid STM32_PPRE2 value specified" +#endif + +/* + * APB2 frequency check. + */ +#if STM32_PCLK2 > STM32_PCLK2_MAX +#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)" +#endif + +/* + * PLLI2S enable check. + */ +#if (STM32_I2SSRC == STM32_I2SSRC_PLLI2S) || \ + (STM32_SAI1SEL == STM32_SAI1SEL_I2SPLL) || \ + (STM32_SAI2SEL == STM32_SAI2SEL_I2SPLL) || \ + defined(__DOXYGEN__) +/** + * @brief PLLI2S activation flag. + */ +#define STM32_ACTIVATE_PLLI2S TRUE +#else +#define STM32_ACTIVATE_PLLI2S FALSE +#endif + +/** + * @brief STM32_PLLI2SN field. + */ +#if ((STM32_PLLI2SN_VALUE >= 49) && (STM32_PLLI2SN_VALUE <= 432)) || \ + defined(__DOXYGEN__) +#define STM32_PLLI2SN (STM32_PLLI2SN_VALUE << 6) +#else +#error "invalid STM32_PLLI2SN_VALUE value specified" +#endif + +/** + * @brief STM32_PLLI2SQ field. + */ +#if ((STM32_PLLI2SQ_VALUE >= 2) && (STM32_PLLI2SQ_VALUE <= 15)) || \ + defined(__DOXYGEN__) +#define STM32_PLLI2SQ (STM32_PLLI2SQ_VALUE << 24) +#else +#error "invalid STM32_PLLI2SQ_VALUE value specified" +#endif + +/** + * @brief STM32_PLLI2SR field. + */ +#if ((STM32_PLLI2SR_VALUE >= 2) && (STM32_PLLI2SR_VALUE <= 7)) || \ + defined(__DOXYGEN__) +#define STM32_PLLI2SR (STM32_PLLI2SR_VALUE << 28) +#else +#error "invalid STM32_PLLI2SR_VALUE value specified" +#endif + +/** + * @brief STM32_PLLI2SP field. + */ +#if (STM32_PLLI2SP_VALUE == 2) || defined(__DOXYGEN__) +#define STM32_PLLI2SP (0 << 16) + +#elif STM32_PLLI2SP_VALUE == 4 +#define STM32_PLLI2SP (1 << 16) + +#elif STM32_PLLI2SP_VALUE == 6 +#define STM32_PLLI2SP (2 << 16) + +#elif STM32_PLLI2SP_VALUE == 8 +#define STM32_PLLI2SP (3 << 16) + +#else +#error "invalid STM32_PLLI2SP_VALUE value specified" +#endif + +/** + * @brief PLLI2S VCO frequency. + */ +#define STM32_PLLI2SVCO (STM32_PLLCLKIN * STM32_PLLI2SN_VALUE) + +/* + * PLLI2S VCO frequency range check. + */ +#if (STM32_PLLI2SVCO < STM32_PLLVCO_MIN) || \ + (STM32_PLLI2SVCO > STM32_PLLVCO_MAX) +#error "STM32_PLLI2SVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)" +#endif + +/** + * @brief PLLI2S P output clock frequency. + */ +#define STM32_PLLI2S_P_CLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SP_VALUE) + +/** + * @brief PLLI2S Q output clock frequency. + */ +#define STM32_PLLI2S_Q_CLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SQ_VALUE) + +/** + * @brief PLLI2S R output clock frequency. + */ +#define STM32_PLLI2S_R_CLKOUT (STM32_PLLI2SVCO / STM32_PLLI2SR_VALUE) + +/** + * @brief STM32_PLLI2SDIVQ field. + */ +#if (STM32_PLLI2SDIVQ_VALUE < 1) || (STM32_PLLI2SDIVQ_VALUE > 32) +#error "STM32_PLLI2SDIVQ_VALUE out of acceptable range" +#endif +#define STM32_PLLI2SDIVQ ((STM32_PLLI2SDIVQ_VALUE - 1) << 0) + +/** + * @brief PLLI2S Q output clock frequency after divisor. + */ +#define STM32_PLLI2SDIVQ_CLKOUT (STM32_PLLI2S_Q_CLKOUT / STM32_PLLI2SDIVQ_VALUE) + +/* + * PLLSAI enable check. + */ +#if (STM32_CLOCK48_REQUIRED && (STM32_CK48MSEL == STM32_CK48MSEL_PLLSAI)) | \ + STM32_LCDTFT_REQUIRED || \ + (STM32_SAI1SEL == STM32_SAI1SEL_SAIPLL) || \ + (STM32_SAI2SEL == STM32_SAI2SEL_SAIPLL) || \ + defined(__DOXYGEN__) +/** + * @brief PLLSAI activation flag. + */ +#define STM32_ACTIVATE_PLLSAI TRUE +#else +#define STM32_ACTIVATE_PLLSAI FALSE +#endif + +/** + * @brief STM32_PLLSAIN field. + */ +#if ((STM32_PLLSAIN_VALUE >= 49) && (STM32_PLLSAIN_VALUE <= 432)) || \ + defined(__DOXYGEN__) +#define STM32_PLLSAIN (STM32_PLLSAIN_VALUE << 6) +#else +#error "invalid STM32_PLLSAIN_VALUE value specified" +#endif + +/** + * @brief STM32_PLLSAIQ field. + */ +#if ((STM32_PLLSAIQ_VALUE >= 2) && (STM32_PLLSAIQ_VALUE <= 15)) || \ + defined(__DOXYGEN__) +#define STM32_PLLSAIQ (STM32_PLLSAIQ_VALUE << 24) +#else +#error "invalid STM32_PLLSAIR_VALUE value specified" +#endif + +/** + * @brief STM32_PLLSAIR field. + */ +#if ((STM32_PLLSAIR_VALUE >= 2) && (STM32_PLLSAIR_VALUE <= 7)) || \ + defined(__DOXYGEN__) +#define STM32_PLLSAIR (STM32_PLLSAIR_VALUE << 28) +#else +#error "invalid STM32_PLLSAIR_VALUE value specified" +#endif + +/** + * @brief STM32_PLLSAIP field. + */ +#if (STM32_PLLSAIP_VALUE == 2) || defined(__DOXYGEN__) +#define STM32_PLLSAIP (0 << 16) + +#elif STM32_PLLSAIP_VALUE == 4 +#define STM32_PLLSAIP (1 << 16) + +#elif STM32_PLLSAIP_VALUE == 6 +#define STM32_PLLSAIP (2 << 16) + +#elif STM32_PLLSAIP_VALUE == 8 +#define STM32_PLLSAIP (3 << 16) + +#else +#error "invalid STM32_PLLSAIP_VALUE value specified" +#endif + +/** + * @brief PLLSAI VCO frequency. + */ +#define STM32_PLLSAIVCO (STM32_PLLCLKIN * STM32_PLLSAIN_VALUE) + +/* + * PLLSAI VCO frequency range check. + */ +#if (STM32_PLLSAIVCO < STM32_PLLVCO_MIN) || \ + (STM32_PLLSAIVCO > STM32_PLLVCO_MAX) +#error "STM32_PLLSAIVCO outside acceptable range (STM32_PLLVCO_MIN...STM32_PLLVCO_MAX)" +#endif + +/** + * @brief PLLSAI P output clock frequency. + */ +#define STM32_PLLSAI_P_CLKOUT (STM32_PLLSAIVCO / STM32_PLLSAIP_VALUE) + +/** + * @brief PLLSAI Q output clock frequency. + */ +#define STM32_PLLSAI_Q_CLKOUT (STM32_PLLSAIVCO / STM32_PLLSAIQ_VALUE) + +/** + * @brief PLLSAI R output clock frequency. + */ +#define STM32_PLLSAI_R_CLKOUT (STM32_PLLSAIVCO / STM32_PLLSAIR_VALUE) + +/** + * @brief STM32_PLLSAIDIVQ field. + */ +#if (STM32_PLLSAIDIVQ_VALUE < 1) || (STM32_PLLSAIDIVQ_VALUE > 32) +#error "STM32_PLLSAIDIVQ_VALUE out of acceptable range" +#endif +#define STM32_PLLSAIDIVQ ((STM32_PLLSAIDIVQ_VALUE - 1) << 8) + +/** + * @brief PLLSAI Q output clock frequency after divisor. + */ +#define STM32_PLLSAIDIVQ_CLKOUT (STM32_PLLSAI_Q_CLKOUT / STM32_PLLSAIDIVQ_VALUE) + +/* + * STM32_PLLSAIDIVR field. + */ +#if (STM32_PLLSAIDIVR_VALUE == 2) || defined(__DOXYGEN__) +#define STM32_PLLSAIDIVR (0 << 16) + +#elif STM32_PLLSAIDIVR_VALUE == 4 +#define STM32_PLLSAIDIVR (1 << 16) + +#elif STM32_PLLSAIDIVR_VALUE == 8 +#define STM32_PLLSAIDIVR (2 << 16) + +#elif STM32_PLLSAIDIVR_VALUE == 16 +#define STM32_PLLSAIDIVR (3 << 16) + +#else +#error "invalid STM32_PLLSAIDIVR_VALUE value specified" +#endif + +/** + * @brief PLLSAI R output clock frequency after divisor. + */ +#define STM32_PLLSAIDIVR_CLKOUT (STM32_PLLSAI_R_CLKOUT / STM32_PLLSAIDIVR_VALUE) + +/** + * @brief MCO1 divider clock. + */ +#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || defined(__DOXYGEN__) +#define STM32_MCO1DIVCLK STM32_HSICLK + +#elif STM32_MCO1SEL == STM32_MCO1SEL_LSE +#define STM32_MCO1DIVCLK STM32_LSECLK + +#elif STM32_MCO1SEL == STM32_MCO1SEL_HSE +#define STM32_MCO1DIVCLK STM32_HSECLK + +#elif STM32_MCO1SEL == STM32_MCO1SEL_PLL +#define STM32_MCO1DIVCLK STM32_PLL_P_CLKOUT + +#else +#error "invalid STM32_MCO1SEL value specified" +#endif + +/** + * @brief MCO1 output pin clock. + */ +#if (STM32_MCO1PRE == STM32_MCO1PRE_DIV1) || defined(__DOXYGEN__) +#define STM32_MCO1CLK STM32_MCO1DIVCLK + +#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV2 +#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 2) + +#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV3 +#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 3) + +#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV4 +#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 4) + +#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV5 +#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 5) + +#else +#error "invalid STM32_MCO1PRE value specified" +#endif + +/** + * @brief MCO2 divider clock. + */ +#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || defined(__DOXYGEN__) +#define STM32_MCO2DIVCLK STM32_HSECLK + +#elif STM32_MCO2SEL == STM32_MCO2SEL_PLL +#define STM32_MCO2DIVCLK STM32_PLL_P_CLKOUT + +#elif STM32_MCO2SEL == STM32_MCO2SEL_SYSCLK +#define STM32_MCO2DIVCLK STM32_SYSCLK + +#elif STM32_MCO2SEL == STM32_MCO2SEL_PLLI2S +#define STM32_MCO2DIVCLK STM32_PLLI2S + +#else +#error "invalid STM32_MCO2SEL value specified" +#endif + +/** + * @brief MCO2 output pin clock. + */ +#if (STM32_MCO2PRE == STM32_MCO2PRE_DIV1) || defined(__DOXYGEN__) +#define STM32_MCO2CLK STM32_MCO2DIVCLK + +#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV2 +#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 2) + +#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV3 +#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 3) + +#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV4 +#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 4) + +#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV5 +#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 5) + +#else +#error "invalid STM32_MCO2PRE value specified" +#endif + +/** + * @brief RTC HSE divider setting. + */ +#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \ + defined(__DOXYGEN__) +#define STM32_RTCPRE (STM32_RTCPRE_VALUE << 16) +#else +#error "invalid STM32_RTCPRE value specified" +#endif + +/** + * @brief HSE divider toward RTC clock. + */ +#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \ + defined(__DOXYGEN__) +#define STM32_HSEDIVCLK (STM32_HSECLK / STM32_RTCPRE_VALUE) +#else +#error "invalid STM32_RTCPRE value specified" +#endif + +/** + * @brief RTC clock. + */ +#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__) +#define STM32_RTCCLK 0 + +#elif STM32_RTCSEL == STM32_RTCSEL_LSE +#define STM32_RTCCLK STM32_LSECLK + +#elif STM32_RTCSEL == STM32_RTCSEL_LSI +#define STM32_RTCCLK STM32_LSICLK + +#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV +#define STM32_RTCCLK STM32_HSEDIVCLK + +#else +#error "invalid STM32_RTCSEL value specified" +#endif + +/** + * @brief USART1 frequency. + */ +#if (STM32_USART1SEL == STM32_USART1SEL_PCLK2) || defined(__DOXYGEN__) +#define STM32_USART1CLK STM32_PCLK2 +#elif STM32_USART1SEL == STM32_USART1SEL_SYSCLK +#define STM32_USART1CLK STM32_SYSCLK +#elif STM32_USART1SEL == STM32_USART1SEL_HSI +#define STM32_USART1CLK STM32_HSICLK +#elif STM32_USART1SEL == STM32_USART1SEL_LSE +#define STM32_USART1CLK STM32_LSECLK +#else +#error "invalid source selected for USART1 clock" +#endif + +/** + * @brief USART2 frequency. + */ +#if (STM32_USART2SEL == STM32_USART2SEL_PCLK1) || defined(__DOXYGEN__) +#define STM32_USART2CLK STM32_PCLK1 +#elif STM32_USART2SEL == STM32_USART2SEL_SYSCLK +#define STM32_USART2CLK STM32_SYSCLK +#elif STM32_USART2SEL == STM32_USART2SEL_HSI +#define STM32_USART2CLK STM32_HSICLK +#elif STM32_USART2SEL == STM32_USART2SEL_LSE +#define STM32_USART2CLK STM32_LSECLK +#else +#error "invalid source selected for USART2 clock" +#endif + +/** + * @brief USART3 frequency. + */ +#if (STM32_USART3SEL == STM32_USART3SEL_PCLK1) || defined(__DOXYGEN__) +#define STM32_USART3CLK STM32_PCLK1 +#elif STM32_USART3SEL == STM32_USART3SEL_SYSCLK +#define STM32_USART3CLK STM32_SYSCLK +#elif STM32_USART3SEL == STM32_USART3SEL_HSI +#define STM32_USART3CLK STM32_HSICLK +#elif STM32_USART3SEL == STM32_USART3SEL_LSE +#define STM32_USART3CLK STM32_LSECLK +#else +#error "invalid source selected for USART3 clock" +#endif + +/** + * @brief UART4 frequency. + */ +#if (STM32_UART4SEL == STM32_UART4SEL_PCLK1) || defined(__DOXYGEN__) +#define STM32_UART4CLK STM32_PCLK1 +#elif STM32_UART4SEL == STM32_UART4SEL_SYSCLK +#define STM32_UART4CLK STM32_SYSCLK +#elif STM32_UART4SEL == STM32_UART4SEL_HSI +#define STM32_UART4CLK STM32_HSICLK +#elif STM32_UART4SEL == STM32_UART4SEL_LSE +#define STM32_UART4CLK STM32_LSECLK +#else +#error "invalid source selected for UART4 clock" +#endif + +/** + * @brief UART5 frequency. + */ +#if (STM32_UART5SEL == STM32_UART5SEL_PCLK1) || defined(__DOXYGEN__) +#define STM32_UART5CLK STM32_PCLK1 +#elif STM32_UART5SEL == STM32_UART5SEL_SYSCLK +#define STM32_UART5CLK STM32_SYSCLK +#elif STM32_UART5SEL == STM32_UART5SEL_HSI +#define STM32_UART5CLK STM32_HSICLK +#elif STM32_UART5SEL == STM32_UART5SEL_LSE +#define STM32_UART5CLK STM32_LSECLK +#else +#error "invalid source selected for UART5 clock" +#endif + +/** + * @brief USART6 frequency. + */ +#if (STM32_USART6SEL == STM32_USART6SEL_PCLK2) || defined(__DOXYGEN__) +#define STM32_USART6CLK STM32_PCLK2 +#elif STM32_USART6SEL == STM32_USART6SEL_SYSCLK +#define STM32_USART6CLK STM32_SYSCLK +#elif STM32_USART6SEL == STM32_USART6SEL_HSI +#define STM32_USART6CLK STM32_HSICLK +#elif STM32_USART6SEL == STM32_USART6SEL_LSE +#define STM32_USART6CLK STM32_LSECLK +#else +#error "invalid source selected for USART6 clock" +#endif + +/** + * @brief UART7 frequency. + */ +#if (STM32_UART7SEL == STM32_UART7SEL_PCLK1) || defined(__DOXYGEN__) +#define STM32_UART7CLK STM32_PCLK1 +#elif STM32_UART7SEL == STM32_UART7SEL_SYSCLK +#define STM32_UART7CLK STM32_SYSCLK +#elif STM32_UART7SEL == STM32_UART7SEL_HSI +#define STM32_UART7CLK STM32_HSICLK +#elif STM32_UART7SEL == STM32_UART7SEL_LSE +#define STM32_UART7CLK STM32_LSECLK +#else +#error "invalid source selected for UART7 clock" +#endif + +/** + * @brief UART8 frequency. + */ +#if (STM32_UART8SEL == STM32_UART8SEL_PCLK1) || defined(__DOXYGEN__) +#define STM32_UART8CLK STM32_PCLK1 +#elif STM32_UART8SEL == STM32_UART8SEL_SYSCLK +#define STM32_UART8CLK STM32_SYSCLK +#elif STM32_UART8SEL == STM32_UART8SEL_HSI +#define STM32_UART8CLK STM32_HSICLK +#elif STM32_UART8SEL == STM32_UART8SEL_LSE +#define STM32_UART8CLK STM32_LSECLK +#else +#error "invalid source selected for UART8 clock" +#endif + +/** + * @brief I2C1 frequency. + */ +#if (STM32_I2C1SEL == STM32_I2C1SEL_PCLK1) || defined(__DOXYGEN__) +#define STM32_I2C1CLK STM32_PCLK1 +#elif STM32_I2C1SEL == STM32_I2C1SEL_SYSCLK +#define STM32_I2C1CLK STM32_SYSCLK +#elif STM32_I2C1SEL == STM32_I2C1SEL_HSI +#define STM32_I2C1CLK STM32_HSICLK +#else +#error "invalid source selected for I2C1 clock" +#endif + +/** + * @brief I2C2 frequency. + */ +#if (STM32_I2C2SEL == STM32_I2C2SEL_PCLK1) || defined(__DOXYGEN__) +#define STM32_I2C2CLK STM32_PCLK1 +#elif STM32_I2C2SEL == STM32_I2C2SEL_SYSCLK +#define STM32_I2C2CLK STM32_SYSCLK +#elif STM32_I2C2SEL == STM32_I2C2SEL_HSI +#define STM32_I2C2CLK STM32_HSICLK +#else +#error "invalid source selected for I2C2 clock" +#endif + +/** + * @brief I2C3 frequency. + */ +#if (STM32_I2C3SEL == STM32_I2C3SEL_PCLK1) || defined(__DOXYGEN__) +#define STM32_I2C3CLK STM32_PCLK1 +#elif STM32_I2C3SEL == STM32_I2C3SEL_SYSCLK +#define STM32_I2C3CLK STM32_SYSCLK +#elif STM32_I2C3SEL == STM32_I2C3SEL_HSI +#define STM32_I2C3CLK STM32_HSICLK +#else +#error "invalid source selected for I2C3 clock" +#endif + +/** + * @brief I2C4 frequency. + */ +#if (STM32_I2C4SEL == STM32_I2C4SEL_PCLK1) || defined(__DOXYGEN__) +#define STM32_I2C4CLK STM32_PCLK1 +#elif STM32_I2C4SEL == STM32_I2C4SEL_SYSCLK +#define STM32_I2C4CLK STM32_SYSCLK +#elif STM32_I2C4SEL == STM32_I2C4SEL_HSI +#define STM32_I2C4CLK STM32_HSICLK +#else +#error "invalid source selected for I2C4 clock" +#endif + +/** + * @brief LPTIM1 frequency. + */ +#if (STM32_LPTIM1SEL == STM32_LPTIM1SEL_PCLK1) || defined(__DOXYGEN__) +#define STM32_LPTIM1CLK STM32_PCLK1 +#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSI +#define STM32_LPTIM1CLK STM32_LSICLK +#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_HSI +#define STM32_LPTIM1CLK STM32_HSICLK +#elif STM32_LPTIM1SEL == STM32_LPTIM1SEL_LSE +#define STM32_LPTIM1CLK STM32_LSECLK +#else +#error "invalid source selected for LPTIM1 clock" +#endif + +/** + * @brief 48MHz frequency. + */ +#if STM32_CLOCK48_REQUIRED || defined(__DOXYGEN__) +#if (STM32_CK48MSEL == STM32_CK48MSEL_PLL) || defined(__DOXYGEN__) +#define STM32_PLL48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE) +#elif STM32_CK48MSEL == STM32_CK48MSEL_PLLSAI +#define STM32_PLL48CLK (STM32_PLLSAIVCO / STM32_PLLSAIQ_VALUE) +#else +#error "invalid source selected for PLL48CLK clock" +#endif +#else /* !STM32_CLOCK48_REQUIRED */ +#define STM32_PLL48CLK 0 +#endif /* !STM32_CLOCK48_REQUIRED */ + +/** + * @brief I2S frequency. + */ +#if (STM32_I2SSRC == STM32_I2SSRC_OFF) || defined(__DOXYGEN__) +#define STM32_I2SCLK 0 +#elif STM32_I2SSRC == STM32_I2SSRC_CKIN +#define STM32_I2SCLK 0 /* Unknown, would require a board value */ +#elif STM32_I2SSRC == STM32_I2SSRC_PLLI2S +#define STM32_I2SCLK STM32_PLLI2S_R_CLKOUT +#else +#error "invalid source selected for I2S clock" +#endif + +/** + * @brief SAI1 frequency. + */ +#if (STM32_SAI1SEL == STM32_SAI1SEL_OFF) || defined(__DOXYGEN__) +#define STM32_SAI1CLK 0 +#elif STM32_SAI1SEL == STM32_SAI1SEL_SAIPLL +#define STM32_SAI1CLK STM32_PLLSAIDIVQ_CLKOUT +#elif STM32_SAI1SEL == STM32_SAI1SEL_I2SPLL +#define STM32_SAI1CLK STM32_PLLI2SDIVQ_CLKOUT +#elif STM32_SAI1SEL == STM32_SAI1SEL_CKIN +#define STM32_SAI1CLK 0 /* Unknown, would require a board value */ +#else +#error "invalid source selected for SAI1 clock" +#endif + +/** + * @brief SAI2 frequency. + */ +#if (STM32_SAI2SEL == STM32_SAI2SEL_OFF) || defined(__DOXYGEN__) +#define STM32_SAI2CLK 0 +#elif STM32_SAI2SEL == STM32_SAI2SEL_SAIPLL +#define STM32_SAI2CLK STM32_PLLSAIDIVQ_CLKOUT +#elif STM32_SAI2SEL == STM32_SAI2SEL_I2SPLL +#define STM32_SAI2CLK STM32_PLLI2SDIVQ_CLKOUT +#elif STM32_SAI2SEL == STM32_SAI2SEL_CKIN +#define STM32_SAI2CLK 0 /* Unknown, would require a board value */ +#else +#error "invalid source selected for SAI2 clock" +#endif + +/** + * @brief SDMMC frequency. + */ +#if (STM32_SDMMCSEL == STM32_SDMMCSEL_PLL48CLK) || defined(__DOXYGEN__) +#define STM32_SDMMCCLK STM32_PLL48CLK +#elif STM32_SDMMCSEL == STM32_SDMMCSEL_SYSCLK +#define STM32_SDMMCCLK STM32_SYSCLK +#else +#error "invalid source selected for SDMMC clock" +#endif + +/** + * @brief Clock of timers connected to APB1 + */ +#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK1 (STM32_PCLK1 * 1) +#else +#define STM32_TIMCLK1 (STM32_PCLK1 * 2) +#endif + +/** + * @brief Clock of timers connected to APB2. + */ +#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__) +#define STM32_TIMCLK2 (STM32_PCLK2 * 1) +#else +#define STM32_TIMCLK2 (STM32_PCLK2 * 2) +#endif + +/** + * @brief Flash settings. + */ +#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__) +#define STM32_FLASHBITS 0x00000000 + +#elif STM32_HCLK <= STM32_1WS_THRESHOLD +#define STM32_FLASHBITS 0x00000001 + +#elif STM32_HCLK <= STM32_2WS_THRESHOLD +#define STM32_FLASHBITS 0x00000002 + +#elif STM32_HCLK <= STM32_3WS_THRESHOLD +#define STM32_FLASHBITS 0x00000003 + +#elif STM32_HCLK <= STM32_4WS_THRESHOLD +#define STM32_FLASHBITS 0x00000004 + +#elif STM32_HCLK <= STM32_5WS_THRESHOLD +#define STM32_FLASHBITS 0x00000005 + +#elif STM32_HCLK <= STM32_6WS_THRESHOLD +#define STM32_FLASHBITS 0x00000006 + +#elif STM32_HCLK <= STM32_7WS_THRESHOLD +#define STM32_FLASHBITS 0x00000007 + +#elif STM32_HCLK <= STM32_8WS_THRESHOLD +#define STM32_FLASHBITS 0x00000008 + +#else +#define STM32_FLASHBITS 0x00000009 +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +/* Various helpers.*/ +#include "nvic.h" +#include "mpu.h" +#include "stm32_isr.h" +#include "stm32_dma.h" +#include "stm32_rcc.h" + +#ifdef __cplusplus +extern "C" { +#endif + void hal_lld_init(void); + void stm32_clock_init(void); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32H7xx/platform.mk b/os/hal/ports/STM32/STM32H7xx/platform.mk new file mode 100644 index 000000000..4d00677c0 --- /dev/null +++ b/os/hal/ports/STM32/STM32H7xx/platform.mk @@ -0,0 +1,29 @@ +# Required platform files. +PLATFORMSRC := $(CHIBIOS)/os/hal/ports/common/ARMCMx/nvic.c \ + $(CHIBIOS)/os/hal/ports/STM32/STM32H7xx/stm32_isr.c \ + $(CHIBIOS)/os/hal/ports/STM32/STM32H7xx/hal_lld.c + +# Required include directories. +PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \ + $(CHIBIOS)/os/hal/ports/STM32/STM32H7xx + +# Optional platform files. +ifeq ($(USE_SMART_BUILD),yes) + +# Configuration files directory +ifeq ($(CONFDIR),) + CONFDIR = . +endif + +HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h | egrep -e "\#define")) + +else +endif + +# Drivers compatible with the platform. +include $(CHIBIOS)/os/hal/ports/STM32/LLD/GPIOv2/driver.mk +include $(CHIBIOS)/os/hal/ports/STM32/LLD/USARTv2/driver.mk + +# Shared variables +ALLCSRC += $(PLATFORMSRC) +ALLINC += $(PLATFORMINC) diff --git a/os/hal/ports/STM32/STM32H7xx/stm32_isr.c b/os/hal/ports/STM32/STM32H7xx/stm32_isr.c new file mode 100644 index 000000000..005466142 --- /dev/null +++ b/os/hal/ports/STM32/STM32H7xx/stm32_isr.c @@ -0,0 +1,255 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32H7xx/stm32_isr.h + * @brief STM32H7xx ISR handler code. + * + * @addtogroup STM32H7xx_ISR + * @{ + */ + +#include "hal.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +#define exti_serve_irq(pr, channel) { \ + \ + if ((pr) & (1U << (channel))) { \ + _pal_isr_code(channel); \ + } \ +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if (HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS)) || defined(__DOXYGEN__) +#if !defined(STM32_DISABLE_EXTI0_HANDLER) +/** + * @brief EXTI[0] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector58) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 0); + EXTI->PR = pr; + + exti_serve_irq(pr, 0); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI1_HANDLER) +/** + * @brief EXTI[1] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector5C) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 1); + EXTI->PR = pr; + + exti_serve_irq(pr, 1); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI2_HANDLER) +/** + * @brief EXTI[2] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector60) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 2); + EXTI->PR = pr; + + exti_serve_irq(pr, 2); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI3_HANDLER) +/** + * @brief EXTI[3] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector64) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 3); + EXTI->PR = pr; + + exti_serve_irq(pr, 3); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI4_HANDLER) +/** + * @brief EXTI[4] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector68) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & (1U << 4); + EXTI->PR = pr; + + exti_serve_irq(pr, 4); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI5_9_HANDLER) +/** + * @brief EXTI[5]...EXTI[9] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(Vector9C) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & ((1U << 5) | (1U << 6) | (1U << 7) | (1U << 8) | + (1U << 9)); + EXTI->PR = pr; + + exti_serve_irq(pr, 5); + exti_serve_irq(pr, 6); + exti_serve_irq(pr, 7); + exti_serve_irq(pr, 8); + exti_serve_irq(pr, 9); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if !defined(STM32_DISABLE_EXTI10_15_HANDLER) +/** + * @brief EXTI[10]...EXTI[15] interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(VectorE0) { + uint32_t pr; + + OSAL_IRQ_PROLOGUE(); + + pr = EXTI->PR; + pr &= EXTI->IMR & ((1U << 10) | (1U << 11) | (1U << 12) | (1U << 13) | + (1U << 14) | (1U << 15)); + EXTI->PR = pr; + + exti_serve_irq(pr, 10); + exti_serve_irq(pr, 11); + exti_serve_irq(pr, 12); + exti_serve_irq(pr, 13); + exti_serve_irq(pr, 14); + exti_serve_irq(pr, 15); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#endif /* HAL_USE_PAL && (PAL_USE_WAIT || PAL_USE_CALLBACKS) */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Enables IRQ sources. + * + * @notapi + */ +void irqInit(void) { + +#if HAL_USE_PAL + nvicEnableVector(EXTI0_IRQn, STM32_IRQ_EXTI0_PRIORITY); + nvicEnableVector(EXTI1_IRQn, STM32_IRQ_EXTI1_PRIORITY); + nvicEnableVector(EXTI2_IRQn, STM32_IRQ_EXTI2_PRIORITY); + nvicEnableVector(EXTI3_IRQn, STM32_IRQ_EXTI3_PRIORITY); + nvicEnableVector(EXTI4_IRQn, STM32_IRQ_EXTI4_PRIORITY); + nvicEnableVector(EXTI9_5_IRQn, STM32_IRQ_EXTI5_9_PRIORITY); + nvicEnableVector(EXTI15_10_IRQn, STM32_IRQ_EXTI10_15_PRIORITY); +#endif +} + +/** + * @brief Disables IRQ sources. + * + * @notapi + */ +void irqDeinit(void) { + +#if HAL_USE_PAL + nvicDisableVector(EXTI0_IRQn); + nvicDisableVector(EXTI1_IRQn); + nvicDisableVector(EXTI2_IRQn); + nvicDisableVector(EXTI3_IRQn); + nvicDisableVector(EXTI4_IRQn); + nvicDisableVector(EXTI9_5_IRQn); + nvicDisableVector(EXTI15_10_IRQn); +#endif +} + +/** @} */ diff --git a/os/hal/ports/STM32/STM32H7xx/stm32_isr.h b/os/hal/ports/STM32/STM32H7xx/stm32_isr.h new file mode 100644 index 000000000..22b16e677 --- /dev/null +++ b/os/hal/ports/STM32/STM32H7xx/stm32_isr.h @@ -0,0 +1,173 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F7xx/stm32_isr.h + * @brief STM32F7xx ISR handler header. + * + * @addtogroup STM32F7xx_ISR + * @{ + */ + +#ifndef STM32_ISR_H +#define STM32_ISR_H + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief EXTI0 interrupt priority level setting. + */ +#if !defined(STM32_IRQ_EXTI0_PRIORITY) || defined(__DOXYGEN__) +#define STM32_IRQ_EXTI0_PRIORITY 6 +#endif + +/** + * @brief EXTI1 interrupt priority level setting. + */ +#if !defined(STM32_IRQ_EXTI1_PRIORITY) || defined(__DOXYGEN__) +#define STM32_IRQ_EXTI1_PRIORITY 6 +#endif + +/** + * @brief EXTI2 interrupt priority level setting. + */ +#if !defined(STM32_IRQ_EXTI2_PRIORITY) || defined(__DOXYGEN__) +#define STM32_IRQ_EXTI2_PRIORITY 6 +#endif + +/** + * @brief EXTI3 interrupt priority level setting. + */ +#if !defined(STM32_IRQ_EXTI3_PRIORITY) || defined(__DOXYGEN__) +#define STM32_IRQ_EXTI3_PRIORITY 6 +#endif + +/** + * @brief EXTI4 interrupt priority level setting. + */ +#if !defined(STM32_IRQ_EXTI4_PRIORITY) || defined(__DOXYGEN__) +#define STM32_IRQ_EXTI4_PRIORITY 6 +#endif + +/** + * @brief EXTI9..5 interrupt priority level setting. + */ +#if !defined(STM32_IRQ_EXTI5_9_PRIORITY) || defined(__DOXYGEN__) +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#endif + +/** + * @brief EXTI15..10 interrupt priority level setting. + */ +#if !defined(STM32_IRQ_EXTI10_15_PRIORITY) || defined(__DOXYGEN__) +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#endif + +/** + * @brief EXTI16 interrupt priority level setting. + */ +#if !defined(STM32_IRQ_EXTI16_PRIORITY) || defined(__DOXYGEN__) +#define STM32_IRQ_EXTI16_PRIORITY 6 +#endif + +/** + * @brief EXTI17 interrupt priority level setting. + */ +#if !defined(STM32_IRQ_EXTI17_PRIORITY) || defined(__DOXYGEN__) +#define STM32_IRQ_EXTI17_PRIORITY 6 +#endif + +/** + * @brief EXTI18 interrupt priority level setting. + */ +#if !defined(STM32_IRQ_EXTI18_PRIORITY) || defined(__DOXYGEN__) +#define STM32_IRQ_EXTI18_PRIORITY 6 +#endif + +/** + * @brief EXTI19 interrupt priority level setting. + */ +#if !defined(STM32_IRQ_EXTI19_PRIORITY) || defined(__DOXYGEN__) +#define STM32_IRQ_EXTI19_PRIORITY 6 +#endif + +/** + * @brief EXTI20 interrupt priority level setting. + */ +#if !defined(STM32_IRQ_EXTI20_PRIORITY) || defined(__DOXYGEN__) +#define STM32_IRQ_EXTI20_PRIORITY 6 +#endif + +/** + * @brief EXTI21 interrupt priority level setting. + */ +#if !defined(STM32_IRQ_EXTI21_PRIORITY) || defined(__DOXYGEN__) +#define STM32_IRQ_EXTI21_PRIORITY 6 +#endif + +/** + * @brief EXTI22 interrupt priority level setting. + */ +#if !defined(STM32_IRQ_EXTI22_PRIORITY) || defined(__DOXYGEN__) +#define STM32_IRQ_EXTI22_PRIORITY 6 +#endif + +/** + * @brief EXTI23 interrupt priority level setting. + */ +#if !defined(STM32_IRQ_EXTI23_PRIORITY) || defined(__DOXYGEN__) +#define STM32_IRQ_EXTI23_PRIORITY 6 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void irqInit(void); + void irqDeinit(void); +#ifdef __cplusplus +} +#endif + +#endif /* STM32_ISR_H */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32H7xx/stm32_rcc.h b/os/hal/ports/STM32/STM32H7xx/stm32_rcc.h new file mode 100644 index 000000000..27e52e3a4 --- /dev/null +++ b/os/hal/ports/STM32/STM32H7xx/stm32_rcc.h @@ -0,0 +1,1653 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32F7xx/stm32_rcc.h + * @brief RCC helper driver header. + * @note This file requires definitions from the ST header file + * @p stm32f7xx.h. + * + * @addtogroup STM32F7xx_RCC + * @{ + */ +#ifndef _STM32_RCC_ +#define _STM32_RCC_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @name Generic RCC operations + * @{ + */ +/** + * @brief Enables the clock of one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAPB1(mask, lp) { \ + RCC->APB1ENR |= (mask); \ + if (lp) \ + RCC->APB1LPENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAPB1(mask, lp) { \ + RCC->APB1ENR &= ~(mask); \ + if (lp) \ + RCC->APB1LPENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the APB1 bus. + * + * @param[in] mask APB1 peripherals mask + * + * @api + */ +#define rccResetAPB1(mask) { \ + RCC->APB1RSTR |= (mask); \ + RCC->APB1RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAPB2(mask, lp) { \ + RCC->APB2ENR |= (mask); \ + if (lp) \ + RCC->APB2LPENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAPB2(mask, lp) { \ + RCC->APB2ENR &= ~(mask); \ + if (lp) \ + RCC->APB2LPENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the APB2 bus. + * + * @param[in] mask APB2 peripherals mask + * + * @api + */ +#define rccResetAPB2(mask) { \ + RCC->APB2RSTR |= (mask); \ + RCC->APB2RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the AHB1 bus. + * + * @param[in] mask AHB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAHB1(mask, lp) { \ + RCC->AHB1ENR |= (mask); \ + if (lp) \ + RCC->AHB1LPENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the AHB1 bus. + * + * @param[in] mask AHB1 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAHB1(mask, lp) { \ + RCC->AHB1ENR &= ~(mask); \ + if (lp) \ + RCC->AHB1LPENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the AHB1 bus. + * + * @param[in] mask AHB1 peripherals mask + * + * @api + */ +#define rccResetAHB1(mask) { \ + RCC->AHB1RSTR |= (mask); \ + RCC->AHB1RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the AHB2 bus. + * + * @param[in] mask AHB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAHB2(mask, lp) { \ + RCC->AHB2ENR |= (mask); \ + if (lp) \ + RCC->AHB2LPENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the AHB2 bus. + * + * @param[in] mask AHB2 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAHB2(mask, lp) { \ + RCC->AHB2ENR &= ~(mask); \ + if (lp) \ + RCC->AHB2LPENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the AHB2 bus. + * + * @param[in] mask AHB2 peripherals mask + * + * @api + */ +#define rccResetAHB2(mask) { \ + RCC->AHB2RSTR |= (mask); \ + RCC->AHB2RSTR = 0; \ +} + +/** + * @brief Enables the clock of one or more peripheral on the AHB3 (FSMC) bus. + * + * @param[in] mask AHB3 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableAHB3(mask, lp) { \ + RCC->AHB3ENR |= (mask); \ + if (lp) \ + RCC->AHB3LPENR |= (mask); \ +} + +/** + * @brief Disables the clock of one or more peripheral on the AHB3 (FSMC) bus. + * + * @param[in] mask AHB3 peripherals mask + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableAHB3(mask, lp) { \ + RCC->AHB3ENR &= ~(mask); \ + if (lp) \ + RCC->AHB3LPENR &= ~(mask); \ +} + +/** + * @brief Resets one or more peripheral on the AHB3 (FSMC) bus. + * + * @param[in] mask AHB3 peripherals mask + * + * @api + */ +#define rccResetAHB3(mask) { \ + RCC->AHB3RSTR |= (mask); \ + RCC->AHB3RSTR = 0; \ +} +/** @} */ + +/** + * @name ADC peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the ADC1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableADC1(lp) rccEnableAPB2(RCC_APB2ENR_ADC1EN, lp) + +/** + * @brief Disables the ADC1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableADC1(lp) rccDisableAPB2(RCC_APB2ENR_ADC1EN, lp) + +/** + * @brief Resets the ADC1 peripheral. + * + * @api + */ +#define rccResetADC1() rccResetAPB2(RCC_APB2RSTR_ADC1RST) + +/** + * @brief Enables the ADC2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableADC2(lp) rccEnableAPB2(RCC_APB2ENR_ADC2EN, lp) + +/** + * @brief Disables the ADC2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableADC2(lp) rccDisableAPB2(RCC_APB2ENR_ADC2EN, lp) + +/** + * @brief Resets the ADC2 peripheral. + * + * @api + */ +#define rccResetADC2() rccResetAPB2(RCC_APB2RSTR_ADC2RST) + +/** + * @brief Enables the ADC3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableADC3(lp) rccEnableAPB2(RCC_APB2ENR_ADC3EN, lp) + +/** + * @brief Disables the ADC3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableADC3(lp) rccDisableAPB2(RCC_APB2ENR_ADC3EN, lp) + +/** + * @brief Resets the ADC3 peripheral. + * + * @api + */ +#define rccResetADC3() rccResetAPB2(RCC_APB2RSTR_ADC3RST) +/** @} */ + +/** + * @name DAC peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the DAC1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableDAC1(lp) rccEnableAPB1(RCC_APB1ENR_DACEN, lp) + +/** + * @brief Disables the DAC1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableDAC1(lp) rccDisableAPB1(RCC_APB1ENR_DACEN, lp) + +/** + * @brief Resets the DAC1 peripheral. + * + * @api + */ +#define rccResetDAC1() rccResetAPB1(RCC_APB1RSTR_DACRST) +/** @} */ + +/** + * @name DMA peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the DMA1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableDMA1(lp) rccEnableAHB1(RCC_AHB1ENR_DMA1EN, lp) + +/** + * @brief Disables the DMA1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableDMA1(lp) rccDisableAHB1(RCC_AHB1ENR_DMA1EN, lp) + +/** + * @brief Resets the DMA1 peripheral. + * + * @api + */ +#define rccResetDMA1() rccResetAHB1(RCC_AHB1RSTR_DMA1RST) + +/** + * @brief Enables the DMA2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableDMA2(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2EN, lp) + +/** + * @brief Disables the DMA2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableDMA2(lp) rccDisableAHB1(RCC_AHB1ENR_DMA2EN, lp) + +/** + * @brief Resets the DMA2 peripheral. + * + * @api + */ +#define rccResetDMA2() rccResetAHB1(RCC_AHB1RSTR_DMA2RST) +/** @} */ + +/** + * @name BKPSRAM specific RCC operations + * @{ + */ +/** + * @brief Enables the BKPSRAM peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableBKPSRAM(lp) rccEnableAHB1(RCC_AHB1ENR_BKPSRAMEN, lp) + +/** + * @brief Disables the BKPSRAM peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableBKPSRAM(lp) rccDisableAHB1(RCC_AHB1ENR_BKPSRAMEN, lp) +/** @} */ + +/** + * @name PWR interface specific RCC operations + * @{ + */ +/** + * @brief Enables the PWR interface clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp) + +/** + * @brief Disables PWR interface clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp) + +/** + * @brief Resets the PWR interface. + * + * @api + */ +#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST) +/** @} */ + +/** + * @name CAN peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the CAN1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CAN1EN, lp) + +/** + * @brief Disables the CAN1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableCAN1(lp) rccDisableAPB1(RCC_APB1ENR_CAN1EN, lp) + +/** + * @brief Resets the CAN1 peripheral. + * + * @api + */ +#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CAN1RST) + +/** + * @brief Enables the CAN2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableCAN2(lp) rccEnableAPB1(RCC_APB1ENR_CAN2EN, lp) + +/** + * @brief Disables the CAN2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableCAN2(lp) rccDisableAPB1(RCC_APB1ENR_CAN2EN, lp) + +/** + * @brief Resets the CAN2 peripheral. + * + * @api + */ +#define rccResetCAN2() rccResetAPB1(RCC_APB1RSTR_CAN2RST) + +/** + * @brief Resets the CAN3 peripheral. + * + * @api + */ +#define rccResetCAN3() rccResetAPB1(RCC_APB1RSTR_CAN3RST) + +/** + * @brief Enables the CAN3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableCAN3(lp) rccEnableAPB1(RCC_APB1ENR_CAN3EN, lp) + +/** + * @brief Disables the CAN3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableCAN3(lp) rccDisableAPB1(RCC_APB1ENR_CAN3EN, lp) +/** @} */ + +/** + * @name ETH peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the ETH peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableETH(lp) rccEnableAHB1(RCC_AHB1ENR_ETHMACEN | \ + RCC_AHB1ENR_ETHMACTXEN | \ + RCC_AHB1ENR_ETHMACRXEN, lp) + +/** + * @brief Disables the ETH peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableETH(lp) rccDisableAHB1(RCC_AHB1ENR_ETHMACEN | \ + RCC_AHB1ENR_ETHMACTXEN | \ + RCC_AHB1ENR_ETHMACRXEN, lp) + +/** + * @brief Resets the ETH peripheral. + * + * @api + */ +#define rccResetETH() rccResetAHB1(RCC_AHB1RSTR_ETHMACRST) +/** @} */ + +/** + * @name I2C peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the I2C1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp) + +/** + * @brief Disables the I2C1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp) + +/** + * @brief Resets the I2C1 peripheral. + * + * @api + */ +#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST) + +/** + * @brief Enables the I2C2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp) + +/** + * @brief Disables the I2C2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp) + +/** + * @brief Resets the I2C2 peripheral. + * + * @api + */ +#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST) + +/** + * @brief Enables the I2C3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C3(lp) rccEnableAPB1(RCC_APB1ENR_I2C3EN, lp) + +/** + * @brief Disables the I2C3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableI2C3(lp) rccDisableAPB1(RCC_APB1ENR_I2C3EN, lp) + +/** + * @brief Resets the I2C3 peripheral. + * + * @api + */ +#define rccResetI2C3() rccResetAPB1(RCC_APB1RSTR_I2C3RST) + +/** + * @brief Enables the I2C4 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableI2C4(lp) rccEnableAPB1(RCC_APB1ENR_I2C4EN, lp) + +/** + * @brief Disables the I2C4 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableI2C4(lp) rccDisableAPB1(RCC_APB1ENR_I2C4EN, lp) + +/** + * @brief Resets the I2C4 peripheral. + * + * @api + */ +#define rccResetI2C4() rccResetAPB1(RCC_APB1RSTR_I2C4RST) +/** @} */ + +/** + * @name OTG peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the OTG_FS peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableOTG_FS(lp) rccEnableAHB2(RCC_AHB2ENR_OTGFSEN, lp) + +/** + * @brief Disables the OTG_FS peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableOTG_FS(lp) rccDisableAHB2(RCC_AHB2ENR_OTGFSEN, lp) + +/** + * @brief Resets the OTG_FS peripheral. + * + * @api + */ +#define rccResetOTG_FS() rccResetAHB2(RCC_AHB2RSTR_OTGFSRST) + +/** + * @brief Enables the OTG_HS peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableOTG_HS(lp) rccEnableAHB1(RCC_AHB1ENR_OTGHSEN, lp) + +/** + * @brief Disables the OTG_HS peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableOTG_HS(lp) rccDisableAHB1(RCC_AHB1ENR_OTGHSEN, lp) + +/** + * @brief Resets the OTG_HS peripheral. + * + * @api + */ +#define rccResetOTG_HS() rccResetAHB1(RCC_AHB1RSTR_OTGHRST) + +/** + * @brief Enables the OTG_HS peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableOTG_HSULPI(lp) rccEnableAHB1(RCC_AHB1ENR_OTGHSULPIEN, lp) + +/** + * @brief Disables the OTG_HS peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableOTG_HSULPI(lp) rccDisableAHB1(RCC_AHB1ENR_OTGHSULPIEN, lp) +/** @} */ + +/** + * @name QUADSPI peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the QUADSPI1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableQUADSPI1(lp) rccEnableAHB3(RCC_AHB3ENR_QSPIEN, lp) + +/** + * @brief Disables the QUADSPI1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableQUADSPI1(lp) rccDisableAHB3(RCC_AHB3ENR_QSPIEN, lp) + +/** + * @brief Resets the QUADSPI1 peripheral. + * + * @api + */ +#define rccResetQUADSPI1() rccResetAHB3(RCC_AHB3RSTR_QSPIRST) +/** @} */ + +/** + * @name SDMMC peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the SDMMC1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSDMMC1(lp) rccEnableAPB2(RCC_APB2ENR_SDMMC1EN, lp) + +/** + * @brief Disables the SDMMC1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSDMMC1(lp) rccDisableAPB2(RCC_APB2ENR_SDMMC1EN, lp) + +/** + * @brief Resets the SDMMC1 peripheral. + * + * @api + */ +#define rccResetSDMMC1() rccResetAPB2(RCC_APB2RSTR_SDMMC1RST) +/** @} */ + +/** + * @name SPI peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the SPI1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp) + +/** + * @brief Disables the SPI1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp) + +/** + * @brief Resets the SPI1 peripheral. + * + * @api + */ +#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST) + +/** + * @brief Enables the SPI2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp) + +/** + * @brief Disables the SPI2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp) + +/** + * @brief Resets the SPI2 peripheral. + * + * @api + */ +#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST) + +/** + * @brief Enables the SPI3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI3(lp) rccEnableAPB1(RCC_APB1ENR_SPI3EN, lp) + +/** + * @brief Disables the SPI3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI3(lp) rccDisableAPB1(RCC_APB1ENR_SPI3EN, lp) + +/** + * @brief Resets the SPI3 peripheral. + * + * @api + */ +#define rccResetSPI3() rccResetAPB1(RCC_APB1RSTR_SPI3RST) + +/** + * @brief Enables the SPI4 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI4(lp) rccEnableAPB2(RCC_APB2ENR_SPI4EN, lp) + +/** + * @brief Disables the SPI4 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI4(lp) rccDisableAPB2(RCC_APB2ENR_SPI4EN, lp) + +/** + * @brief Resets the SPI4 peripheral. + * + * @api + */ +#define rccResetSPI4() rccResetAPB2(RCC_APB2RSTR_SPI4RST) + +/** + * @brief Enables the SPI5 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI5(lp) rccEnableAPB2(RCC_APB2ENR_SPI5EN, lp) + +/** + * @brief Disables the SPI5 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI5(lp) rccDisableAPB2(RCC_APB2ENR_SPI5EN, lp) + +/** + * @brief Resets the SPI5 peripheral. + * + * @api + */ +#define rccResetSPI5() rccResetAPB2(RCC_APB2RSTR_SPI5RST) + +/** + * @brief Enables the SPI6 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableSPI6(lp) rccEnableAPB2(RCC_APB2ENR_SPI6EN, lp) + +/** + * @brief Disables the SPI6 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableSPI6(lp) rccDisableAPB2(RCC_APB2ENR_SPI6EN, lp) + +/** + * @brief Resets the SPI6 peripheral. + * + * @api + */ +#define rccResetSPI6() rccResetAPB2(RCC_APB2RSTR_SPI6RST) +/** @} */ + +/** + * @name TIM peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the TIM1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp) + +/** + * @brief Disables the TIM1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM1(lp) rccDisableAPB2(RCC_APB2ENR_TIM1EN, lp) + +/** + * @brief Resets the TIM1 peripheral. + * + * @api + */ +#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST) + +/** + * @brief Enables the TIM2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp) + +/** + * @brief Disables the TIM2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp) + +/** + * @brief Resets the TIM2 peripheral. + * + * @api + */ +#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST) + +/** + * @brief Enables the TIM3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp) + +/** + * @brief Disables the TIM3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp) + +/** + * @brief Resets the TIM3 peripheral. + * + * @api + */ +#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST) + +/** + * @brief Enables the TIM4 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp) + +/** + * @brief Disables the TIM4 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM4(lp) rccDisableAPB1(RCC_APB1ENR_TIM4EN, lp) + +/** + * @brief Resets the TIM4 peripheral. + * + * @api + */ +#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST) + +/** + * @brief Enables the TIM5 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM5(lp) rccEnableAPB1(RCC_APB1ENR_TIM5EN, lp) + +/** + * @brief Disables the TIM5 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM5(lp) rccDisableAPB1(RCC_APB1ENR_TIM5EN, lp) + +/** + * @brief Resets the TIM5 peripheral. + * + * @api + */ +#define rccResetTIM5() rccResetAPB1(RCC_APB1RSTR_TIM5RST) + +/** + * @brief Enables the TIM6 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM6(lp) rccEnableAPB1(RCC_APB1ENR_TIM6EN, lp) + +/** + * @brief Disables the TIM6 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM6(lp) rccDisableAPB1(RCC_APB1ENR_TIM6EN, lp) + +/** + * @brief Resets the TIM6 peripheral. + * + * @api + */ +#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST) + +/** + * @brief Enables the TIM7 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp) + +/** + * @brief Disables the TIM7 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM7(lp) rccDisableAPB1(RCC_APB1ENR_TIM7EN, lp) + +/** + * @brief Resets the TIM7 peripheral. + * + * @api + */ +#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST) + +/** + * @brief Enables the TIM8 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp) + +/** + * @brief Disables the TIM8 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM8(lp) rccDisableAPB2(RCC_APB2ENR_TIM8EN, lp) + +/** + * @brief Resets the TIM8 peripheral. + * + * @api + */ +#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST) + +/** + * @brief Enables the TIM9 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM9(lp) rccEnableAPB2(RCC_APB2ENR_TIM9EN, lp) + +/** + * @brief Disables the TIM9 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM9(lp) rccDisableAPB2(RCC_APB2ENR_TIM9EN, lp) + +/** + * @brief Resets the TIM9 peripheral. + * + * @api + */ +#define rccResetTIM9() rccResetAPB2(RCC_APB2RSTR_TIM9RST) + +/** + * @brief Enables the TIM10 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM10(lp) rccEnableAPB2(RCC_APB2ENR_TIM10EN, lp) + +/** + * @brief Disables the TIM10 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM10(lp) rccDisableAPB2(RCC_APB2ENR_TIM10EN, lp) + +/** + * @brief Resets the TIM10 peripheral. + * + * @api + */ +#define rccResetTIM10() rccResetAPB2(RCC_APB2RSTR_TIM10RST) + +/** + * @brief Enables the TIM11 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM11(lp) rccEnableAPB2(RCC_APB2ENR_TIM11EN, lp) + +/** + * @brief Disables the TIM11 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM11(lp) rccDisableAPB2(RCC_APB2ENR_TIM11EN, lp) + +/** + * @brief Resets the TIM11 peripheral. + * + * @api + */ +#define rccResetTIM11() rccResetAPB2(RCC_APB2RSTR_TIM11RST) + +/** + * @brief Enables the TIM12 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM12(lp) rccEnableAPB1(RCC_APB1ENR_TIM12EN, lp) + +/** + * @brief Disables the TIM12 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM12(lp) rccDisableAPB1(RCC_APB1ENR_TIM12EN, lp) + +/** + * @brief Resets the TIM12 peripheral. + * + * @api + */ +#define rccResetTIM12() rccResetAPB1(RCC_APB1RSTR_TIM12RST) + +/** + * @brief Enables the TIM13 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM13(lp) rccEnableAPB1(RCC_APB1ENR_TIM13EN, lp) + +/** + * @brief Disables the TIM13 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM13(lp) rccDisableAPB1(RCC_APB1ENR_TIM13EN, lp) + +/** + * @brief Resets the TIM13 peripheral. + * + * @api + */ +#define rccResetTIM13() rccResetAPB1(RCC_APB1RSTR_TIM13RST) + +/** + * @brief Enables the TIM14 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableTIM14(lp) rccEnableAPB1(RCC_APB1ENR_TIM14EN, lp) + +/** + * @brief Disables the TIM14 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableTIM14(lp) rccDisableAPB1(RCC_APB1ENR_TIM14EN, lp) + +/** + * @brief Resets the TIM14 peripheral. + * + * @api + */ +#define rccResetTIM14() rccResetAPB1(RCC_APB1RSTR_TIM14RST) +/** @} */ + +/** + * @name USART/UART peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the USART1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp) + +/** + * @brief Disables the USART1 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp) + +/** + * @brief Resets the USART1 peripheral. + * + * @api + */ +#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST) + +/** + * @brief Enables the USART2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp) + +/** + * @brief Disables the USART2 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp) + +/** + * @brief Resets the USART2 peripheral. + * + * @api + */ +#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST) + +/** + * @brief Enables the USART3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp) + +/** + * @brief Disables the USART3 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART3(lp) rccDisableAPB1(RCC_APB1ENR_USART3EN, lp) + +/** + * @brief Resets the USART3 peripheral. + * + * @api + */ +#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST) + +/** + * @brief Enables the UART4 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUART4(lp) rccEnableAPB1(RCC_APB1ENR_UART4EN, lp) + +/** + * @brief Disables the UART4 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUART4(lp) rccDisableAPB1(RCC_APB1ENR_UART4EN, lp) + +/** + * @brief Resets the UART4 peripheral. + * + * @api + */ +#define rccResetUART4() rccResetAPB1(RCC_APB1RSTR_UART4RST) + +/** + * @brief Enables the UART5 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_UART5EN, lp) + +/** + * @brief Disables the UART5 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUART5(lp) rccDisableAPB1(RCC_APB1ENR_UART5EN, lp) + +/** + * @brief Resets the UART5 peripheral. + * + * @api + */ +#define rccResetUART5() rccResetAPB1(RCC_APB1RSTR_UART5RST) + +/** + * @brief Enables the USART6 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUSART6(lp) rccEnableAPB2(RCC_APB2ENR_USART6EN, lp) + +/** + * @brief Disables the USART6 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUSART6(lp) rccDisableAPB2(RCC_APB2ENR_USART6EN, lp) + +/** + * @brief Resets the USART6 peripheral. + * + * @api + */ +#define rccResetUSART6() rccResetAPB2(RCC_APB2RSTR_USART6RST) + +/** + * @brief Enables the UART7 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUART7(lp) rccEnableAPB1(RCC_APB1ENR_UART7EN, lp) + +/** + * @brief Disables the UART7 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUART7(lp) rccDisableAPB1(RCC_APB1ENR_UART7EN, lp) + +/** + * @brief Resets the UART7 peripheral. + * + * @api + */ +#define rccResetUART7() rccResetAPB1(RCC_APB1RSTR_UART7RST) + +/** + * @brief Enables the UART8 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableUART8(lp) rccEnableAPB1(RCC_APB1ENR_UART8EN, lp) + +/** + * @brief Disables the UART8 peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableUART8(lp) rccDisableAPB1(RCC_APB1ENR_UART8EN, lp) + +/** + * @brief Resets the UART8 peripheral. + * + * @api + */ +#define rccResetUART8() rccResetAPB1(RCC_APB1RSTR_UART8RST) +/** @} */ + +/** + * @name LTDC peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the LTDC peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableLTDC(lp) rccEnableAPB2(RCC_APB2ENR_LTDCEN, lp) + +/** + * @brief Disables the LTDC peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableLTDC(lp) rccDisableAPB2(RCC_APB2ENR_LTDCEN, lp) + +/** + * @brief Resets the LTDC peripheral. + * + * @api + */ +#define rccResetLTDC() rccResetAPB2(RCC_APB2RSTR_LTDCRST) + +/** + * @name DMA2D peripheral specific RCC operations + * @{ + */ +/** + * @brief Enables the DMA2D peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccEnableDMA2D(lp) rccEnableAHB1(RCC_AHB1ENR_DMA2DEN, lp) + +/** + * @brief Disables the DMA2D peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#define rccDisableDMA2D(lp) rccDisableAHB1(RCC_AHB1ENR_DMA2DEN, lp) + +/** + * @brief Resets the DMA2D peripheral. + * + * @api + */ +#define rccResetDMA2D() rccResetAHB1(RCC_AHB1RSTR_DMA2DRST) +/** @} */ + +/** + * @name FSMC peripherals specific RCC operations + * @{ + */ +/** + * @brief Enables the FSMC peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#if defined(STM32_FSMC_IS_FMC) + #define rccEnableFSMC(lp) rccEnableAHB3(RCC_AHB3ENR_FMCEN, lp) +#else + #define rccEnableFSMC(lp) rccEnableAHB3(RCC_AHB3ENR_FSMCEN, lp) +#endif + +/** + * @brief Disables the FSMC peripheral clock. + * + * @param[in] lp low power enable flag + * + * @api + */ +#if defined(STM32_FSMC_IS_FMC) + #define rccDisableFSMC(lp) rccDisableAHB3(RCC_AHB3ENR_FMCEN, lp) +#else + #define rccDisableFSMC(lp) rccDisableAHB3(RCC_AHB3ENR_FSMCEN, lp) +#endif + +/** + * @brief Resets the FSMC peripheral. + * + * @api + */ +#if defined(STM32_FSMC_IS_FMC) + #define rccResetFSMC() rccResetAHB3(RCC_AHB3RSTR_FMCRST) +#else + #define rccResetFSMC() rccResetAHB3(RCC_AHB3RSTR_FSMCRST) +#endif +/** @} */ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif +#ifdef __cplusplus +} +#endif + +#endif /* _STM32_RCC_ */ + +/** @} */ diff --git a/os/hal/ports/STM32/STM32H7xx/stm32_registry.h b/os/hal/ports/STM32/STM32H7xx/stm32_registry.h new file mode 100644 index 000000000..df64d5a39 --- /dev/null +++ b/os/hal/ports/STM32/STM32H7xx/stm32_registry.h @@ -0,0 +1,318 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file STM32H7xx/stm32_registry.h + * @brief STM32H7xx capabilities registry. + * + * @addtogroup HAL + * @{ + */ + +#ifndef STM32_REGISTRY_H +#define STM32_REGISTRY_H + +/*===========================================================================*/ +/* Platform capabilities. */ +/*===========================================================================*/ + +/** + * @name STM32F7xx capabilities + * @{ + */ +/*===========================================================================*/ +/* STM32F745xx, STM32F746xx, STM32F756xx. */ +/*===========================================================================*/ +#if defined(STM32H743xx) || defined(STM32H753xx) || \ + defined(__DOXYGEN__) +/* ADC attributes.*/ +#define STM32_ADC12_HANDLER Vector88 +#define STM32_ADC12_NUMBER 18 +#define STM32_ADC3_HANDLER Vector23C +#define STM32_ADC3_NUMBER 127 + +#define STM32_HAS_ADC1 TRUE + +#define STM32_HAS_ADC2 TRUE + +#define STM32_HAS_ADC3 TRUE + +#define STM32_HAS_ADC4 FALSE + +#define STM32_HAS_SDADC1 FALSE +#define STM32_HAS_SDADC2 FALSE +#define STM32_HAS_SDADC3 FALSE + +/* CAN attributes.*/ +#define STM32_HAS_CAN1 FALSE +#define STM32_HAS_CAN2 FALSE +#define STM32_HAS_CAN3 FALSE + +/* DAC attributes.*/ +#define STM32_HAS_DAC1_CH1 FALSE +#define STM32_HAS_DAC1_CH2 FALSE +#define STM32_HAS_DAC2_CH1 FALSE +#define STM32_HAS_DAC2_CH2 FALSE + +/* DMA attributes.*/ +#define STM32_HAS_DMA1 FALSE +#define STM32_HAS_DMA2 FALSE + +/* ETH attributes.*/ +#define STM32_HAS_ETH TRUE +#define STM32_ETH_HANDLER Vector134 +#define STM32_ETH_NUMBER 61 + +/* EXTI attributes.*/ + +/* GPIO attributes.*/ +#define STM32_HAS_GPIOA TRUE +#define STM32_HAS_GPIOB TRUE +#define STM32_HAS_GPIOC TRUE +#define STM32_HAS_GPIOD TRUE +#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOH TRUE +#define STM32_HAS_GPIOF TRUE +#define STM32_HAS_GPIOG TRUE +#define STM32_HAS_GPIOI TRUE +#define STM32_HAS_GPIOJ TRUE +#define STM32_HAS_GPIOK TRUE +#define STM32_GPIO_EN_MASK (RCC_AHB4ENR_GPIOAEN | \ + RCC_AHB4ENR_GPIOBEN | \ + RCC_AHB4ENR_GPIOCEN | \ + RCC_AHB4ENR_GPIODEN | \ + RCC_AHB4ENR_GPIOEEN | \ + RCC_AHB4ENR_GPIOFEN | \ + RCC_AHB4ENR_GPIOGEN | \ + RCC_AHB4ENR_GPIOHEN | \ + RCC_AHB4ENR_GPIOIEN | \ + RCC_AHB4ENR_GPIOJEN | \ + RCC_AHB4ENR_GPIOKEN) + +/* I2C attributes.*/ +#define STM32_HAS_I2C1 FALSE +#define STM32_HAS_I2C2 FALSE +#define STM32_HAS_I2C3 FALSE +#define STM32_HAS_I2C4 FALSE + +/* QUADSPI attributes.*/ +#define STM32_HAS_QUADSPI1 FALSE + +/* RTC attributes.*/ +#define STM32_HAS_RTC TRUE +#define STM32_RTC_HAS_SUBSECONDS TRUE +#define STM32_RTC_HAS_PERIODIC_WAKEUPS TRUE +#define STM32_RTC_NUM_ALARMS 2 +#define STM32_RTC_HAS_INTERRUPTS FALSE + +/* SDMMC attributes.*/ +#define STM32_HAS_SDMMC1 FALSE +#define STM32_HAS_SDMMC2 FALSE + +/* SPI attributes.*/ +#define STM32_HAS_SPI1 FALSE +#define STM32_HAS_SPI2 FALSE +#define STM32_HAS_SPI3 FALSE +#define STM32_HAS_SPI4 FALSE +#define STM32_HAS_SPI5 FALSE +#define STM32_HAS_SPI6 FALSE + +/* TIM attributes.*/ +#define STM32_TIM_MAX_CHANNELS 6 + +#define STM32_HAS_TIM1 TRUE +#define STM32_TIM1_IS_32BITS FALSE +#define STM32_TIM1_CHANNELS 6 +#define STM32_TIM1_UP_HANDLER VectorA4 +#define STM32_TIM1_CC_HANDLER VectorAC +#define STM32_TIM1_UP_NUMBER 25 +#define STM32_TIM1_CC_NUMBER 27 + +#define STM32_HAS_TIM2 TRUE +#define STM32_TIM2_IS_32BITS TRUE +#define STM32_TIM2_CHANNELS 4 +#define STM32_TIM2_HANDLER VectorB0 +#define STM32_TIM2_NUMBER 28 + +#define STM32_HAS_TIM3 TRUE +#define STM32_TIM3_IS_32BITS FALSE +#define STM32_TIM3_CHANNELS 4 +#define STM32_TIM3_HANDLER VectorB4 +#define STM32_TIM3_NUMBER 29 + +#define STM32_HAS_TIM4 TRUE +#define STM32_TIM4_IS_32BITS FALSE +#define STM32_TIM4_CHANNELS 4 +#define STM32_TIM4_HANDLER VectorB8 +#define STM32_TIM4_NUMBER 30 + +#define STM32_HAS_TIM5 TRUE +#define STM32_TIM5_IS_32BITS TRUE +#define STM32_TIM5_CHANNELS 4 +#define STM32_TIM5_HANDLER Vector108 +#define STM32_TIM5_NUMBER 50 + +#define STM32_HAS_TIM6 TRUE +#define STM32_TIM6_IS_32BITS FALSE +#define STM32_TIM6_CHANNELS 0 +#define STM32_TIM6_HANDLER Vector118 +#define STM32_TIM6_NUMBER 54 + +#define STM32_HAS_TIM7 TRUE +#define STM32_TIM7_IS_32BITS FALSE +#define STM32_TIM7_CHANNELS 0 +#define STM32_TIM7_HANDLER Vector11C +#define STM32_TIM7_NUMBER 55 + +#define STM32_HAS_TIM12 TRUE +#define STM32_TIM12_IS_32BITS FALSE +#define STM32_TIM12_CHANNELS 2 +#define STM32_TIM12_HANDLER VectorEC +#define STM32_TIM12_NUMBER 43 + +#define STM32_HAS_TIM13 TRUE +#define STM32_TIM13_IS_32BITS FALSE +#define STM32_TIM13_CHANNELS 1 +#define STM32_TIM13_HANDLER VectorF0 +#define STM32_TIM13_NUMBER 44 + +#define STM32_HAS_TIM14 TRUE +#define STM32_TIM14_IS_32BITS FALSE +#define STM32_TIM14_CHANNELS 1 +#define STM32_TIM14_HANDLER VectorF4 +#define STM32_TIM14_NUMBER 45 + +#define STM32_HAS_TIM15 FALSE +#define STM32_TIM15_IS_32BITS FALSE +#define STM32_TIM15_CHANNELS 2 +#define STM32_TIM15_HANDLER Vector210 +#define STM32_TIM15_NUMBER 116 + +#define STM32_HAS_TIM16 FALSE +#define STM32_TIM16_IS_32BITS FALSE +#define STM32_TIM16_CHANNELS 1 +#define STM32_TIM16_HANDLER Vector214 +#define STM32_TIM16_NUMBER 117 + +#define STM32_HAS_TIM17 FALSE +#define STM32_TIM17_IS_32BITS FALSE +#define STM32_TIM17_CHANNELS 1 +#define STM32_TIM17_HANDLER Vector218 +#define STM32_TIM17_NUMBER 118 + +#define STM32_HAS_TIM8 FALSE +#define STM32_HAS_TIM9 FALSE +#define STM32_HAS_TIM10 FALSE +#define STM32_HAS_TIM11 FALSE +#define STM32_HAS_TIM18 FALSE +#define STM32_HAS_TIM19 FALSE +#define STM32_HAS_TIM20 FALSE +#define STM32_HAS_TIM21 FALSE +#define STM32_HAS_TIM22 FALSE + +/* USART attributes.*/ +#define STM32_HAS_USART1 TRUE +#define STM32_USART1_HANDLER VectorD4 +#define STM32_USART1_NUMBER 37 + +#define STM32_HAS_USART2 TRUE +#define STM32_USART2_HANDLER VectorD8 +#define STM32_USART2_NUMBER 38 + +#define STM32_HAS_USART3 TRUE +#define STM32_USART3_HANDLER VectorDC +#define STM32_USART3_NUMBER 39 + +#define STM32_HAS_UART4 TRUE +#define STM32_UART4_HANDLER Vector110 +#define STM32_UART4_NUMBER 52 + +#define STM32_HAS_UART5 TRUE +#define STM32_UART5_HANDLER Vector114 +#define STM32_UART5_NUMBER 53 + +#define STM32_HAS_USART6 TRUE +#define STM32_USART6_HANDLER Vector15C +#define STM32_USART6_NUMBER 71 + +#define STM32_HAS_UART7 TRUE +#define STM32_UART7_HANDLER Vector188 +#define STM32_UART7_NUMBER 82 + +#define STM32_HAS_UART8 TRUE +#define STM32_UART8_HANDLER Vector18C +#define STM32_UART8_NUMBER 83 + +#define STM32_HAS_LPUART1 FALSE + +/* USB attributes.*/ +#define STM32_OTG_STEPPING 2 +#define STM32_HAS_OTG1 TRUE +#define STM32_OTG1_ENDPOINTS 8 +#define STM32_OTG1_HANDLER Vector1D4 +#define STM32_OTG1_EP1OUT_HANDLER Vector1C8 +#define STM32_OTG1_EP1IN_HANDLER Vector1CC +#define STM32_OTG1_NUMBER 101 +#define STM32_OTG1_EP1OUT_NUMBER 98 +#define STM32_OTG1_EP1IN_NUMBER 99 + +#define STM32_HAS_OTG2 TRUE +#define STM32_OTG2_ENDPOINTS 8 +#define STM32_OTG2_HANDLER Vector174 +#define STM32_OTG2_EP1OUT_HANDLER Vector168 +#define STM32_OTG2_EP1IN_HANDLER Vector16C +#define STM32_OTG2_NUMBER 77 +#define STM32_OTG2_EP1OUT_NUMBER 74 +#define STM32_OTG2_EP1IN_NUMBER 75 + +#define STM32_HAS_USB FALSE + +/* IWDG attributes.*/ +#define STM32_HAS_IWDG TRUE +#define STM32_IWDG_IS_WINDOWED TRUE + +/* LTDC attributes.*/ +#define STM32_HAS_LTDC TRUE + +/* DMA2D attributes.*/ +#define STM32_HAS_DMA2D TRUE + +/* FSMC attributes.*/ +#define STM32_HAS_FSMC TRUE +#define STM32_FSMC_IS_FMC TRUE +#define STM32_FSMC_HANDLER Vector100 +#define STM32_FSMC_NUMBER 48 + +/* LTDC attributes.*/ +#define STM32_LTDC_EV_HANDLER Vector1A0 +#define STM32_LTDC_ER_HANDLER Vector1A4 +#define STM32_LTDC_EV_NUMBER 88 +#define STM32_LTDC_ER_NUMBER 89 + +/* DMA2D attributes.*/ +#define STM32_DMA2D_HANDLER Vector1A8 +#define STM32_DMA2D_NUMBER 90 + +/* CRC attributes.*/ +#define STM32_HAS_CRC TRUE +#define STM32_CRC_PROGRAMMABLE FALSE + +#endif /* defined(STM32H743xx) || defined(STM32H753xx) */ +/** @} */ + +#endif /* STM32_REGISTRY_H */ + +/** @} */ -- cgit v1.2.3