From af8938572a826e089d8dfe5dafe956870b05c7ea Mon Sep 17 00:00:00 2001 From: Giovanni Di Sirio Date: Sun, 8 Nov 2015 19:21:20 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8452 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/ports/STM32/LLD/OTGv1/stm32_otg.h | 7 +- os/hal/ports/STM32/LLD/SPIv1/i2s_lld.c | 134 +++++++++++++++++++++++++++++-- os/hal/ports/STM32/LLD/SPIv1/i2s_lld.h | 71 +++++++++++++++- 3 files changed, 202 insertions(+), 10 deletions(-) diff --git a/os/hal/ports/STM32/LLD/OTGv1/stm32_otg.h b/os/hal/ports/STM32/LLD/OTGv1/stm32_otg.h index e64038f21..f9f48ad32 100644 --- a/os/hal/ports/STM32/LLD/OTGv1/stm32_otg.h +++ b/os/hal/ports/STM32/LLD/OTGv1/stm32_otg.h @@ -570,8 +570,8 @@ typedef struct { #define HCCHAR_EPDIR (1U<<15) /**< Endpoint direction. */ #define HCCHAR_EPNUM_MASK (15U<<11) /**< Endpoint number mask. */ #define HCCHAR_EPNUM(n) ((n)<<11) /**< Endpoint number value. */ -#define HCCHAR_MPS_MASK (11U<<0) /**< Maximum packet size mask. */ -#define HCCHAR_MPS(n) (11U<<0) /**< Maximum packet size value. */ +#define HCCHAR_MPS_MASK (0x7FFU<<0) /**< Maximum packet size mask. */ +#define HCCHAR_MPS(n) ((n)<<0) /**< Maximum packet size value. */ /** @} */ /** @@ -589,6 +589,7 @@ typedef struct { interrupt. */ #define HCINT_STALL (1U<<3) /**< STALL response received interrupt. */ +#define HCINT_AHBERR (1U<<2) /**< AHB error interrupt. */ #define HCINT_CHH (1U<<1) /**< Channel halted. */ #define HCINT_XFRC (1U<<0) /**< Transfer completed. */ /** @} */ @@ -610,6 +611,7 @@ typedef struct { interrupt mask. */ #define HCINTMSK_STALLM (1U<<3) /**< STALL response received interrupt mask. */ +#define HCINTMSK_AHBERRM (1U<<2) /**< AHB error interrupt mask. */ #define HCINTMSK_CHHM (1U<<1) /**< Channel halted mask. */ #define HCINTMSK_XFRCM (1U<<0) /**< Transfer completed mask. */ /** @} */ @@ -623,6 +625,7 @@ typedef struct { #define HCTSIZ_DPID_DATA2 (1U<<29) /**< DATA2. */ #define HCTSIZ_DPID_DATA1 (2U<<29) /**< DATA1. */ #define HCTSIZ_DPID_MDATA (3U<<29) /**< MDATA. */ +#define HCTSIZ_DPID_SETUP (3U<<29) /**< SETUP. */ #define HCTSIZ_PKTCNT_MASK (0x3FFU<<19)/**< Packet count mask. */ #define HCTSIZ_PKTCNT(n) ((n)<<19) /**< Packet count value. */ #define HCTSIZ_XFRSIZ_MASK (0x7FFFF<<0)/**< Transfer size mask. */ diff --git a/os/hal/ports/STM32/LLD/SPIv1/i2s_lld.c b/os/hal/ports/STM32/LLD/SPIv1/i2s_lld.c index 6be5df7bd..fe95636ac 100644 --- a/os/hal/ports/STM32/LLD/SPIv1/i2s_lld.c +++ b/os/hal/ports/STM32/LLD/SPIv1/i2s_lld.c @@ -30,6 +30,14 @@ /* Driver local definitions. */ /*===========================================================================*/ +#define I2S1_RX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_I2S_SPI1_RX_DMA_STREAM, \ + STM32_SPI1_RX_DMA_CHN) + +#define I2S1_TX_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_I2S_SPI1_TX_DMA_STREAM, \ + STM32_SPI1_TX_DMA_CHN) + #define I2S2_RX_DMA_CHANNEL \ STM32_DMA_GETCHANNEL(STM32_I2S_SPI2_RX_DMA_STREAM, \ STM32_SPI2_RX_DMA_CHN) @@ -46,6 +54,26 @@ STM32_DMA_GETCHANNEL(STM32_I2S_SPI3_TX_DMA_STREAM, \ STM32_SPI3_TX_DMA_CHN) +/* + * Static I2S settings for I2S1. + */ +#if !STM32_I2S_IS_MASTER(STM32_I2S_SPI1_MODE) +#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE) +#define STM32_I2S1_CFGR_CFG 0 +#endif +#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE) +#define STM32_I2S1_CFGR_CFG SPI_I2SCFGR_I2SCFG_0 +#endif +#else /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI1_MODE) */ +#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE) +#define STM32_I2S1_CFGR_CFG SPI_I2SCFGR_I2SCFG_1 +#endif +#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE) +#define STM32_I2S1_CFGR_CFG (SPI_I2SCFGR_I2SCFG_1 | \ + SPI_I2SCFGR_I2SCFG_0) +#endif +#endif /* !STM32_I2S_IS_MASTER(STM32_I2S_SPI1_MODE) */ + /* * Static I2S settings for I2S2. */ @@ -90,11 +118,16 @@ /* Driver exported variables. */ /*===========================================================================*/ -/** @brief I2S2 driver identifier.*/ -#if STM32_I2S_USE_SPI2 || defined(__DOXYGEN__) -I2SDriver I2SD2; +/** @brief I2S1 driver identifier.*/ +#if STM32_I2S_USE_SPI1 || defined(__DOXYGEN__) +I2SDriver I2SD1; #endif + /** @brief I2S2 driver identifier.*/ + #if STM32_I2S_USE_SPI2 || defined(__DOXYGEN__) + I2SDriver I2SD2; + #endif + /** @brief I2S3 driver identifier.*/ #if STM32_I2S_USE_SPI3 || defined(__DOXYGEN__) I2SDriver I2SD3; @@ -108,7 +141,8 @@ I2SDriver I2SD3; /* Driver local functions. */ /*===========================================================================*/ -#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE) || \ +#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE) || \ + STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE) || \ STM32_I2S_RX_ENABLED(STM32_I2S_SPI3_MODE) || defined(__DOXYGEN__) /** * @brief Shared end-of-rx service routine. @@ -140,7 +174,8 @@ static void i2s_lld_serve_rx_interrupt(I2SDriver *i2sp, uint32_t flags) { } #endif -#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE) || \ +#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE) || \ + STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE) || \ STM32_I2S_TX_ENABLED(STM32_I2S_SPI3_MODE) || defined(__DOXYGEN__) /** * @brief Shared end-of-tx service routine. @@ -187,6 +222,46 @@ static void i2s_lld_serve_tx_interrupt(I2SDriver *i2sp, uint32_t flags) { */ void i2s_lld_init(void) { +#if STM32_I2S_USE_SPI1 + i2sObjectInit(&I2SD1); + I2SD1.spi = SPI1; + I2SD1.cfg = STM32_I2S1_CFGR_CFG; +#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE) + I2SD1.dmarx = STM32_DMA_STREAM(STM32_I2S_SPI1_RX_DMA_STREAM); + I2SD1.rxdmamode = STM32_DMA_CR_CHSEL(I2S1_RX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_I2S_SPI1_DMA_PRIORITY) | + STM32_DMA_CR_PSIZE_HWORD | + STM32_DMA_CR_MSIZE_HWORD | + STM32_DMA_CR_DIR_P2M | + STM32_DMA_CR_MINC | + STM32_DMA_CR_CIRC | + STM32_DMA_CR_HTIE | + STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | + STM32_DMA_CR_TEIE; +#else + I2SD1.dmarx = NULL; + I2SD1.rxdmamode = 0; +#endif +#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE) + I2SD1.dmatx = STM32_DMA_STREAM(STM32_I2S_SPI1_TX_DMA_STREAM); + I2SD1.txdmamode = STM32_DMA_CR_CHSEL(I2S1_TX_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_I2S_SPI1_DMA_PRIORITY) | + STM32_DMA_CR_PSIZE_HWORD | + STM32_DMA_CR_MSIZE_HWORD | + STM32_DMA_CR_DIR_M2P | + STM32_DMA_CR_MINC | + STM32_DMA_CR_CIRC | + STM32_DMA_CR_HTIE | + STM32_DMA_CR_TCIE | + STM32_DMA_CR_DMEIE | + STM32_DMA_CR_TEIE; +#else + I2SD1.dmatx = NULL; + I2SD1.txdmamode = 0; +#endif +#endif + #if STM32_I2S_USE_SPI2 i2sObjectInit(&I2SD2); I2SD2.spi = SPI2; @@ -280,6 +355,40 @@ void i2s_lld_start(I2SDriver *i2sp) { /* If in stopped state then enables the SPI and DMA clocks.*/ if (i2sp->state == I2S_STOP) { +#if STM32_I2S_USE_SPI1 + if (&I2SD1 == i2sp) { + bool b; + + /* Enabling I2S unit clock.*/ + rccEnableSPI1(FALSE); + +#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE) + b = dmaStreamAllocate(i2sp->dmarx, + STM32_I2S_SPI1_IRQ_PRIORITY, + (stm32_dmaisr_t)i2s_lld_serve_rx_interrupt, + (void *)i2sp); + osalDbgAssert(!b, "stream already allocated"); + + /* CRs settings are done here because those never changes until + the driver is stopped.*/ + i2sp->spi->CR1 = 0; + i2sp->spi->CR2 = SPI_CR2_RXDMAEN; +#endif +#if STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE) + b = dmaStreamAllocate(i2sp->dmatx, + STM32_I2S_SPI1_IRQ_PRIORITY, + (stm32_dmaisr_t)i2s_lld_serve_tx_interrupt, + (void *)i2sp); + osalDbgAssert(!b, "stream already allocated"); + + /* CRs settings are done here because those never changes until + the driver is stopped.*/ + i2sp->spi->CR1 = 0; + i2sp->spi->CR2 = SPI_CR2_TXDMAEN; +#endif + } +#endif + #if STM32_I2S_USE_SPI2 if (&I2SD2 == i2sp) { bool b; @@ -295,7 +404,7 @@ void i2s_lld_start(I2SDriver *i2sp) { osalDbgAssert(!b, "stream already allocated"); /* CRs settings are done here because those never changes until - the driver is stopped.*/ + the driver is stopped.*/ i2sp->spi->CR1 = 0; i2sp->spi->CR2 = SPI_CR2_RXDMAEN; #endif @@ -307,12 +416,13 @@ void i2s_lld_start(I2SDriver *i2sp) { osalDbgAssert(!b, "stream already allocated"); /* CRs settings are done here because those never changes until - the driver is stopped.*/ + the driver is stopped.*/ i2sp->spi->CR1 = 0; i2sp->spi->CR2 = SPI_CR2_TXDMAEN; #endif } #endif + #if STM32_I2S_USE_SPI3 if (&I2SD3 == i2sp) { bool b; @@ -327,6 +437,8 @@ void i2s_lld_start(I2SDriver *i2sp) { (void *)i2sp); osalDbgAssert(!b, "stream already allocated"); + /* CRs settings are done here because those never changes until + the driver is stopped.*/ i2sp->spi->CR1 = 0; i2sp->spi->CR2 = SPI_CR2_RXDMAEN; #endif @@ -337,6 +449,8 @@ void i2s_lld_start(I2SDriver *i2sp) { (void *)i2sp); osalDbgAssert(!b, "stream already allocated"); + /* CRs settings are done here because those never changes until + the driver is stopped.*/ i2sp->spi->CR1 = 0; i2sp->spi->CR2 = SPI_CR2_TXDMAEN; #endif @@ -368,10 +482,16 @@ void i2s_lld_stop(I2SDriver *i2sp) { if (NULL != i2sp->dmatx) dmaStreamRelease(i2sp->dmatx); +#if STM32_I2S_USE_SPI1 + if (&I2SD1 == i2sp) + rccDisableSPI1(FALSE); +#endif + #if STM32_I2S_USE_SPI2 if (&I2SD2 == i2sp) rccDisableSPI2(FALSE); #endif + #if STM32_I2S_USE_SPI3 if (&I2SD3 == i2sp) rccDisableSPI3(FALSE); diff --git a/os/hal/ports/STM32/LLD/SPIv1/i2s_lld.h b/os/hal/ports/STM32/LLD/SPIv1/i2s_lld.h index 3e007b7db..95ccf7bb2 100644 --- a/os/hal/ports/STM32/LLD/SPIv1/i2s_lld.h +++ b/os/hal/ports/STM32/LLD/SPIv1/i2s_lld.h @@ -60,6 +60,15 @@ * @name Configuration options * @{ */ +/** + * @brief I2S1 driver enable switch. + * @details If set to @p TRUE the support for I2S1 is included. + * @note The default is @p TRUE. + */ +#if !defined(STM32_I2S_USE_SPI1) || defined(__DOXYGEN__) +#define STM32_I2S_USE_SPI1 FALSE +#endif + /** * @brief I2S2 driver enable switch. * @details If set to @p TRUE the support for I2S2 is included. @@ -78,6 +87,14 @@ #define STM32_I2S_USE_SPI3 FALSE #endif +/** + * @brief I2S1 mode. + */ +#if !defined(STM32_I2S_SPI1_MODE) || defined(__DOXYGEN__) +#define STM32_I2S_SPI1_MODE (STM32_I2S_MODE_MASTER | \ + STM32_I2S_MODE_RX) +#endif + /** * @brief I2S2 mode. */ @@ -94,6 +111,13 @@ STM32_I2S_MODE_RX) #endif +/** + * @brief I2S1 interrupt priority level setting. + */ +#if !defined(STM32_I2S_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_I2S_SPI1_IRQ_PRIORITY 10 +#endif + /** * @brief I2S2 interrupt priority level setting. */ @@ -108,6 +132,13 @@ #define STM32_I2S_SPI3_IRQ_PRIORITY 10 #endif +/** + * @brief I2S1 DMA priority (0..3|lowest..highest). + */ +#if !defined(STM32_I2S_SPI1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_I2S_SPI1_DMA_PRIORITY 1 +#endif + /** * @brief I2S2 DMA priority (0..3|lowest..highest). */ @@ -134,6 +165,11 @@ /* Derived constants and error checks. */ /*===========================================================================*/ +#if STM32_I2S_RX_ENABLED(STM32_I2S_SPI1_MODE) && \ + STM32_I2S_TX_ENABLED(STM32_I2S_SPI1_MODE) +#error "I2S1 RX and TX mode not supported in this driver implementation" +#endif + #if STM32_I2S_RX_ENABLED(STM32_I2S_SPI2_MODE) && \ STM32_I2S_TX_ENABLED(STM32_I2S_SPI2_MODE) #error "I2S2 RX and TX mode not supported in this driver implementation" @@ -144,6 +180,10 @@ #error "I2S3 RX and TX mode not supported in this driver implementation" #endif +#if STM32_I2S_USE_SPI1 && !STM32_HAS_SPI1 +#error "SPI1 not present in the selected device" +#endif + #if STM32_I2S_USE_SPI2 && !STM32_HAS_SPI2 #error "SPI2 not present in the selected device" #endif @@ -152,10 +192,15 @@ #error "SPI3 not present in the selected device" #endif -#if !STM32_I2S_USE_SPI2 && !STM32_I2S_USE_SPI3 +#if !STM32_I2S_USE_SPI1 && !STM32_I2S_USE_SPI2 && !STM32_I2S_USE_SPI3 #error "I2S driver activated but no SPI peripheral assigned" #endif +#if STM32_I2S_USE_SPI1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2S_SPI1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to SPI1" +#endif + #if STM32_I2S_USE_SPI2 && \ !OSAL_IRQ_IS_VALID_PRIORITY(STM32_I2S_SPI2_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to SPI2" @@ -166,6 +211,11 @@ #error "Invalid IRQ priority assigned to SPI3" #endif +#if STM32_I2S_USE_SPI1 && \ + !STM32_DMA_IS_VALID_PRIORITY(STM32_I2S_SPI1_DMA_PRIORITY) +#error "Invalid DMA priority assigned to SPI1" +#endif + #if STM32_I2S_USE_SPI2 && \ !STM32_DMA_IS_VALID_PRIORITY(STM32_I2S_SPI2_DMA_PRIORITY) #error "Invalid DMA priority assigned to SPI2" @@ -180,6 +230,11 @@ reassign streams to different channels.*/ #if STM32_ADVANCED_DMA /* Check on the presence of the DMA streams settings in mcuconf.h.*/ +#if STM32_I2S_USE_SPI1 && (!defined(STM32_I2S_SPI1_RX_DMA_STREAM) || \ + !defined(STM32_I2S_SPI1_TX_DMA_STREAM)) +#error "SPI1 DMA streams not defined" +#endif + #if STM32_I2S_USE_SPI2 && (!defined(STM32_I2S_SPI2_RX_DMA_STREAM) || \ !defined(STM32_I2S_SPI2_TX_DMA_STREAM)) #error "SPI2 DMA streams not defined" @@ -191,6 +246,16 @@ #endif /* Check on the validity of the assigned DMA channels.*/ +#if STM32_I2S_USE_SPI1 && \ + !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI1_RX_DMA_STREAM, STM32_SPI1_RX_DMA_MSK) +#error "invalid DMA stream associated to SPI1 RX" +#endif + +#if STM32_I2S_USE_SPI1 && \ + !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI1_TX_DMA_STREAM, STM32_SPI1_TX_DMA_MSK) +#error "invalid DMA stream associated to SPI1 TX" +#endif + #if STM32_I2S_USE_SPI2 && \ !STM32_DMA_IS_VALID_ID(STM32_I2S_SPI2_RX_DMA_STREAM, STM32_SPI2_RX_DMA_MSK) #error "invalid DMA stream associated to SPI2 RX" @@ -324,6 +389,10 @@ struct I2SDriver { /* External declarations. */ /*===========================================================================*/ +#if STM32_I2S_USE_SPI1 && !defined(__DOXYGEN__) +extern I2SDriver I2SD1; +#endif + #if STM32_I2S_USE_SPI2 && !defined(__DOXYGEN__) extern I2SDriver I2SD2; #endif -- cgit v1.2.3