From a5de0f57f49d16166069905927df1422e53d4c1f Mon Sep 17 00:00:00 2001 From: gdisirio Date: Thu, 25 Oct 2012 13:09:23 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4779 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- boards/ST_STM32F3_DISCOVERY/board.c | 22 + boards/ST_STM32F3_DISCOVERY/board.h | 828 +++++++++++++++++++-- boards/ST_STM32F3_DISCOVERY/cfg/board.chcfg | 817 ++++++-------------- os/hal/platforms/STM32F3xx/hal_lld.h | 2 +- tools/eclipse/config_wizard/plugin.xml | 3 + .../boards/stm32f3xx/templates/board.c.ftl | 133 ++++ .../boards/stm32f3xx/templates/board.h.ftl | 327 ++++++++ .../boards/stm32f3xx/templates/board.mk.ftl | 28 + .../resources/gencfg/processors/processors.xml | 24 +- .../gencfg/schema/boards/stm32f0xx_board.xsd | 11 + .../gencfg/schema/boards/stm32f3xx_board.xsd | 100 +++ .../gencfg/schema/boards/stm32f4xx_board.xsd | 49 +- .../gencfg/schema/boards/stm32l1xx_board.xsd | 16 +- .../resources/gencfg/xml/stm32f3board.xml | 797 ++++++++++++++++++++ 14 files changed, 2471 insertions(+), 686 deletions(-) create mode 100644 tools/eclipse/config_wizard/resources/gencfg/processors/boards/stm32f3xx/templates/board.c.ftl create mode 100644 tools/eclipse/config_wizard/resources/gencfg/processors/boards/stm32f3xx/templates/board.h.ftl create mode 100644 tools/eclipse/config_wizard/resources/gencfg/processors/boards/stm32f3xx/templates/board.mk.ftl create mode 100644 tools/eclipse/config_wizard/resources/gencfg/schema/boards/stm32f3xx_board.xsd create mode 100644 tools/eclipse/config_wizard/resources/gencfg/xml/stm32f3board.xml diff --git a/boards/ST_STM32F3_DISCOVERY/board.c b/boards/ST_STM32F3_DISCOVERY/board.c index ef65f94aa..3b54b4fe5 100644 --- a/boards/ST_STM32F3_DISCOVERY/board.c +++ b/boards/ST_STM32F3_DISCOVERY/board.c @@ -54,6 +54,28 @@ void __early_init(void) { stm32_clock_init(); } +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return TRUE; +} + +/** + * @brief SDC card write protection detection. + */ +bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return FALSE; +} +#endif /* HAL_USE_SDC */ + #if HAL_USE_MMC_SPI || defined(__DOXYGEN__) /** * @brief MMC_SPI card detection. diff --git a/boards/ST_STM32F3_DISCOVERY/board.h b/boards/ST_STM32F3_DISCOVERY/board.h index a79d6a122..e2b064fdc 100644 --- a/boards/ST_STM32F3_DISCOVERY/board.h +++ b/boards/ST_STM32F3_DISCOVERY/board.h @@ -22,7 +22,7 @@ #define _BOARD_H_ /* - * Setup for STMicroelectronics STM32F4-Discovery board. + * Setup for STMicroelectronics STM32F3-Discovery board. */ /* @@ -31,7 +31,6 @@ #define BOARD_ST_STM32F3_DISCOVERY #define BOARD_NAME "STMicroelectronics STM32F3-Discovery" - /* * Board oscillators-related settings. * NOTE: LSE not fitted. @@ -40,6 +39,8 @@ #define STM32_LSECLK 0 #endif +#define STM32_LSEDRV (3 << 3) + #if !defined(STM32_HSECLK) #define STM32_HSECLK 8000000 #endif @@ -54,6 +55,107 @@ /* * IO pins assignments. */ +#define GPIOA_PIN0 0 +#define GPIOA_PIN1 1 +#define GPIOA_PIN2 2 +#define GPIOA_PIN3 3 +#define GPIOA_PIN4 4 +#define GPIOA_PIN5 5 +#define GPIOA_PIN6 6 +#define GPIOA_PIN7 7 +#define GPIOA_PIN8 8 +#define GPIOA_PIN9 9 +#define GPIOA_PIN10 10 +#define GPIOA_PIN11 11 +#define GPIOA_PIN12 12 +#define GPIOA_JTAG_TMS 13 +#define GPIOA_JTAG_TCK 14 +#define GPIOA_JTAG_TDI 15 + +#define GPIOB_PIN0 0 +#define GPIOB_PIN1 1 +#define GPIOB_BOOT1 2 +#define GPIOB_JTAG_TDO 3 +#define GPIOB_JTAG_TRST 4 +#define GPIOB_PIN5 5 +#define GPIOB_PIN6 6 +#define GPIOB_PIN7 7 +#define GPIOB_PIN8 8 +#define GPIOB_PIN9 9 +#define GPIOB_PIN10 10 +#define GPIOB_PIN11 11 +#define GPIOB_PIN12 12 +#define GPIOB_PIN13 13 +#define GPIOB_PIN14 14 +#define GPIOB_PIN15 15 + +#define GPIOC_PIN0 0 +#define GPIOC_PIN1 1 +#define GPIOC_PIN2 2 +#define GPIOC_PIN3 3 +#define GPIOC_PIN4 4 +#define GPIOC_PIN5 5 +#define GPIOC_PIN6 6 +#define GPIOC_PIN7 7 +#define GPIOC_PIN8 8 +#define GPIOC_PIN9 9 +#define GPIOC_PIN10 10 +#define GPIOC_PIN11 11 +#define GPIOC_PIN12 12 +#define GPIOC_PIN13 13 +#define GPIOC_OSC32_IN 14 +#define GPIOC_OSC32_OUT 15 + +#define GPIOD_PIN0 0 +#define GPIOD_PIN1 1 +#define GPIOD_PIN2 2 +#define GPIOD_PIN3 3 +#define GPIOD_PIN4 4 +#define GPIOD_PIN5 5 +#define GPIOD_PIN6 6 +#define GPIOD_PIN7 7 +#define GPIOD_PIN8 8 +#define GPIOD_PIN9 9 +#define GPIOD_PIN10 10 +#define GPIOD_PIN11 11 +#define GPIOD_PIN12 12 +#define GPIOD_PIN13 13 +#define GPIOD_PIN14 14 +#define GPIOD_PIN15 15 + +#define GPIOE_PIN0 0 +#define GPIOE_PIN1 1 +#define GPIOE_PIN2 2 +#define GPIOE_PIN3 3 +#define GPIOE_PIN4 4 +#define GPIOE_PIN5 5 +#define GPIOE_PIN6 6 +#define GPIOE_PIN7 7 +#define GPIOE_PIN8 8 +#define GPIOE_PIN9 9 +#define GPIOE_PIN10 10 +#define GPIOE_PIN11 11 +#define GPIOE_PIN12 12 +#define GPIOE_PIN13 13 +#define GPIOE_PIN14 14 +#define GPIOE_PIN15 15 + +#define GPIOF_PIN0 0 +#define GPIOF_PIN1 1 +#define GPIOF_PIN2 2 +#define GPIOF_PIN3 3 +#define GPIOF_PIN4 4 +#define GPIOF_PIN5 5 +#define GPIOF_PIN6 6 +#define GPIOF_PIN7 7 +#define GPIOF_PIN8 8 +#define GPIOF_PIN9 9 +#define GPIOF_PIN10 10 +#define GPIOF_PIN11 11 +#define GPIOF_PIN12 12 +#define GPIOF_PIN13 13 +#define GPIOF_PIN14 14 +#define GPIOF_PIN15 15 /* * I/O ports initial setup, this configuration is established soon after reset @@ -69,8 +171,9 @@ #define PIN_OTYPE_PUSHPULL(n) (0U << (n)) #define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) #define PIN_OSPEED_2M(n) (0U << ((n) * 2)) -#define PIN_OSPEED_10M(n) (1U << ((n) * 2)) -#define PIN_OSPEED_50M(n) (3U << ((n) * 2)) +#define PIN_OSPEED_25M(n) (1U << ((n) * 2)) +#define PIN_OSPEED_50M(n) (2U << ((n) * 2)) +#define PIN_OSPEED_100M(n) (3U << ((n) * 2)) #define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2)) #define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2)) #define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2)) @@ -79,74 +182,705 @@ /* * GPIOA setup: * + * PA0 - PIN0 (input pullup). + * PA1 - PIN1 (input pullup). + * PA2 - PIN2 (input pullup). + * PA3 - PIN3 (input pullup). + * PA4 - PIN4 (input pullup). + * PA5 - PIN5 (input pullup). + * PA6 - PIN6 (input pullup). + * PA7 - PIN7 (input pullup). + * PA8 - PIN8 (input pullup). + * PA9 - PIN9 (input pullup). + * PA10 - PIN10 (input pullup). + * PA11 - PIN11 (input pullup). + * PA12 - PIN12 (input pullup). + * PA13 - JTAG_TMS (alternate 0). + * PA14 - JTAG_TCK (alternate 0). + * PA15 - JTAG_TDI (alternate 0). */ -#define VAL_GPIOA_MODER 0 -#define VAL_GPIOA_OTYPER 0 -#define VAL_GPIOA_OSPEEDR 0 -#define VAL_GPIOA_PUPDR 0 -#define VAL_GPIOA_ODR 0 -#define VAL_GPIOA_AFRL 0 -#define VAL_GPIOA_AFRH 0 +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_PIN0) | \ + PIN_MODE_INPUT(GPIOA_PIN1) | \ + PIN_MODE_INPUT(GPIOA_PIN2) | \ + PIN_MODE_INPUT(GPIOA_PIN3) | \ + PIN_MODE_INPUT(GPIOA_PIN4) | \ + PIN_MODE_INPUT(GPIOA_PIN5) | \ + PIN_MODE_INPUT(GPIOA_PIN6) | \ + PIN_MODE_INPUT(GPIOA_PIN7) | \ + PIN_MODE_INPUT(GPIOA_PIN8) | \ + PIN_MODE_INPUT(GPIOA_PIN9) | \ + PIN_MODE_INPUT(GPIOA_PIN10) | \ + PIN_MODE_INPUT(GPIOA_PIN11) | \ + PIN_MODE_INPUT(GPIOA_PIN12) | \ + PIN_MODE_ALTERNATE(GPIOA_JTAG_TMS) | \ + PIN_MODE_ALTERNATE(GPIOA_JTAG_TCK) | \ + PIN_MODE_ALTERNATE(GPIOA_JTAG_TDI)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOA_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOA_JTAG_TMS) | \ + PIN_OTYPE_PUSHPULL(GPIOA_JTAG_TCK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_JTAG_TDI)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_2M(GPIOA_PIN0) | \ + PIN_OSPEED_2M(GPIOA_PIN1) | \ + PIN_OSPEED_2M(GPIOA_PIN2) | \ + PIN_OSPEED_2M(GPIOA_PIN3) | \ + PIN_OSPEED_2M(GPIOA_PIN4) | \ + PIN_OSPEED_2M(GPIOA_PIN5) | \ + PIN_OSPEED_2M(GPIOA_PIN6) | \ + PIN_OSPEED_2M(GPIOA_PIN7) | \ + PIN_OSPEED_2M(GPIOA_PIN8) | \ + PIN_OSPEED_2M(GPIOA_PIN9) | \ + PIN_OSPEED_2M(GPIOA_PIN10) | \ + PIN_OSPEED_2M(GPIOA_PIN11) | \ + PIN_OSPEED_2M(GPIOA_PIN12) | \ + PIN_OSPEED_100M(GPIOA_JTAG_TMS) | \ + PIN_OSPEED_100M(GPIOA_JTAG_TCK) | \ + PIN_OSPEED_100M(GPIOA_JTAG_TDI)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOA_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOA_JTAG_TMS) | \ + PIN_PUPDR_PULLDOWN(GPIOA_JTAG_TCK) | \ + PIN_PUPDR_PULLUP(GPIOA_JTAG_TDI)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_PIN0) | \ + PIN_ODR_HIGH(GPIOA_PIN1) | \ + PIN_ODR_HIGH(GPIOA_PIN2) | \ + PIN_ODR_HIGH(GPIOA_PIN3) | \ + PIN_ODR_HIGH(GPIOA_PIN4) | \ + PIN_ODR_HIGH(GPIOA_PIN5) | \ + PIN_ODR_HIGH(GPIOA_PIN6) | \ + PIN_ODR_HIGH(GPIOA_PIN7) | \ + PIN_ODR_HIGH(GPIOA_PIN8) | \ + PIN_ODR_HIGH(GPIOA_PIN9) | \ + PIN_ODR_HIGH(GPIOA_PIN10) | \ + PIN_ODR_HIGH(GPIOA_PIN11) | \ + PIN_ODR_HIGH(GPIOA_PIN12) | \ + PIN_ODR_HIGH(GPIOA_JTAG_TMS) | \ + PIN_ODR_HIGH(GPIOA_JTAG_TCK) | \ + PIN_ODR_HIGH(GPIOA_JTAG_TDI)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PIN0, 0) | \ + PIN_AFIO_AF(GPIOA_PIN1, 0) | \ + PIN_AFIO_AF(GPIOA_PIN2, 0) | \ + PIN_AFIO_AF(GPIOA_PIN3, 0) | \ + PIN_AFIO_AF(GPIOA_PIN4, 0) | \ + PIN_AFIO_AF(GPIOA_PIN5, 0) | \ + PIN_AFIO_AF(GPIOA_PIN6, 0) | \ + PIN_AFIO_AF(GPIOA_PIN7, 0)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0) | \ + PIN_AFIO_AF(GPIOA_PIN9, 0) | \ + PIN_AFIO_AF(GPIOA_PIN10, 0) | \ + PIN_AFIO_AF(GPIOA_PIN11, 0) | \ + PIN_AFIO_AF(GPIOA_PIN12, 0) | \ + PIN_AFIO_AF(GPIOA_JTAG_TMS, 0) | \ + PIN_AFIO_AF(GPIOA_JTAG_TCK, 0) | \ + PIN_AFIO_AF(GPIOA_JTAG_TDI, 0)) /* * GPIOB setup: * + * PB0 - PIN0 (input pullup). + * PB1 - PIN1 (input pullup). + * PB2 - BOOT1 (input floating). + * PB3 - JTAG_TDO (alternate 0). + * PB4 - JTAG_TRST (alternate 0). + * PB5 - PIN5 (input pullup). + * PB6 - PIN6 (input pullup). + * PB7 - PIN7 (input pullup). + * PB8 - PIN8 (input pullup). + * PB9 - PIN9 (input pullup). + * PB10 - PIN10 (input pullup). + * PB11 - PIN11 (input pullup). + * PB12 - PIN12 (input pullup). + * PB13 - PIN13 (input pullup). + * PB14 - PIN14 (input pullup). + * PB15 - PIN15 (input pullup). */ -#define VAL_GPIOB_MODER 0 -#define VAL_GPIOB_OTYPER 0 -#define VAL_GPIOB_OSPEEDR 0 -#define VAL_GPIOB_PUPDR 0 -#define VAL_GPIOB_ODR 0 -#define VAL_GPIOB_AFRL 0 -#define VAL_GPIOB_AFRH 0 +#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \ + PIN_MODE_INPUT(GPIOB_PIN1) | \ + PIN_MODE_INPUT(GPIOB_BOOT1) | \ + PIN_MODE_ALTERNATE(GPIOB_JTAG_TDO) | \ + PIN_MODE_ALTERNATE(GPIOB_JTAG_TRST) | \ + PIN_MODE_INPUT(GPIOB_PIN5) | \ + PIN_MODE_INPUT(GPIOB_PIN6) | \ + PIN_MODE_INPUT(GPIOB_PIN7) | \ + PIN_MODE_INPUT(GPIOB_PIN8) | \ + PIN_MODE_INPUT(GPIOB_PIN9) | \ + PIN_MODE_INPUT(GPIOB_PIN10) | \ + PIN_MODE_INPUT(GPIOB_PIN11) | \ + PIN_MODE_INPUT(GPIOB_PIN12) | \ + PIN_MODE_INPUT(GPIOB_PIN13) | \ + PIN_MODE_INPUT(GPIOB_PIN14) | \ + PIN_MODE_INPUT(GPIOB_PIN15)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_BOOT1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_JTAG_TDO) | \ + PIN_OTYPE_PUSHPULL(GPIOB_JTAG_TRST) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOB_PIN15)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_2M(GPIOB_PIN0) | \ + PIN_OSPEED_2M(GPIOB_PIN1) | \ + PIN_OSPEED_100M(GPIOB_BOOT1) | \ + PIN_OSPEED_100M(GPIOB_JTAG_TDO) | \ + PIN_OSPEED_100M(GPIOB_JTAG_TRST) | \ + PIN_OSPEED_2M(GPIOB_PIN5) | \ + PIN_OSPEED_2M(GPIOB_PIN6) | \ + PIN_OSPEED_2M(GPIOB_PIN7) | \ + PIN_OSPEED_2M(GPIOB_PIN8) | \ + PIN_OSPEED_2M(GPIOB_PIN9) | \ + PIN_OSPEED_2M(GPIOB_PIN10) | \ + PIN_OSPEED_2M(GPIOB_PIN11) | \ + PIN_OSPEED_2M(GPIOB_PIN12) | \ + PIN_OSPEED_2M(GPIOB_PIN13) | \ + PIN_OSPEED_2M(GPIOB_PIN14) | \ + PIN_OSPEED_2M(GPIOB_PIN15)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOB_BOOT1) | \ + PIN_PUPDR_FLOATING(GPIOB_JTAG_TDO) | \ + PIN_PUPDR_PULLUP(GPIOB_JTAG_TRST) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOB_PIN15)) +#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \ + PIN_ODR_HIGH(GPIOB_PIN1) | \ + PIN_ODR_HIGH(GPIOB_BOOT1) | \ + PIN_ODR_HIGH(GPIOB_JTAG_TDO) | \ + PIN_ODR_HIGH(GPIOB_JTAG_TRST) | \ + PIN_ODR_HIGH(GPIOB_PIN5) | \ + PIN_ODR_HIGH(GPIOB_PIN6) | \ + PIN_ODR_HIGH(GPIOB_PIN7) | \ + PIN_ODR_HIGH(GPIOB_PIN8) | \ + PIN_ODR_HIGH(GPIOB_PIN9) | \ + PIN_ODR_HIGH(GPIOB_PIN10) | \ + PIN_ODR_HIGH(GPIOB_PIN11) | \ + PIN_ODR_HIGH(GPIOB_PIN12) | \ + PIN_ODR_HIGH(GPIOB_PIN13) | \ + PIN_ODR_HIGH(GPIOB_PIN14) | \ + PIN_ODR_HIGH(GPIOB_PIN15)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0) | \ + PIN_AFIO_AF(GPIOB_PIN1, 0) | \ + PIN_AFIO_AF(GPIOB_BOOT1, 0) | \ + PIN_AFIO_AF(GPIOB_JTAG_TDO, 0) | \ + PIN_AFIO_AF(GPIOB_JTAG_TRST, 0) | \ + PIN_AFIO_AF(GPIOB_PIN5, 0) | \ + PIN_AFIO_AF(GPIOB_PIN6, 0) | \ + PIN_AFIO_AF(GPIOB_PIN7, 0)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0) | \ + PIN_AFIO_AF(GPIOB_PIN9, 0) | \ + PIN_AFIO_AF(GPIOB_PIN10, 0) | \ + PIN_AFIO_AF(GPIOB_PIN11, 0) | \ + PIN_AFIO_AF(GPIOB_PIN12, 0) | \ + PIN_AFIO_AF(GPIOB_PIN13, 0) | \ + PIN_AFIO_AF(GPIOB_PIN14, 0) | \ + PIN_AFIO_AF(GPIOB_PIN15, 0)) /* * GPIOC setup: * + * PC0 - PIN0 (input pullup). + * PC1 - PIN1 (input pullup). + * PC2 - PIN2 (input pullup). + * PC3 - PIN3 (input pullup). + * PC4 - PIN4 (input pullup). + * PC5 - PIN5 (input pullup). + * PC6 - PIN6 (input pullup). + * PC7 - PIN7 (input pullup). + * PC8 - PIN8 (input pullup). + * PC9 - PIN9 (input pullup). + * PC10 - PIN10 (input pullup). + * PC11 - PIN11 (input pullup). + * PC12 - PIN12 (input pullup). + * PC13 - PIN13 (input pullup). + * PC14 - OSC32_IN (input floating). + * PC15 - OSC32_OUT (input floating). */ -#define VAL_GPIOC_MODER 0 -#define VAL_GPIOC_OTYPER 0 -#define VAL_GPIOC_OSPEEDR 0 -#define VAL_GPIOC_PUPDR 0 -#define VAL_GPIOC_ODR 0 -#define VAL_GPIOC_AFRL 0 -#define VAL_GPIOC_AFRH 0 +#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \ + PIN_MODE_INPUT(GPIOC_PIN1) | \ + PIN_MODE_INPUT(GPIOC_PIN2) | \ + PIN_MODE_INPUT(GPIOC_PIN3) | \ + PIN_MODE_INPUT(GPIOC_PIN4) | \ + PIN_MODE_INPUT(GPIOC_PIN5) | \ + PIN_MODE_INPUT(GPIOC_PIN6) | \ + PIN_MODE_INPUT(GPIOC_PIN7) | \ + PIN_MODE_INPUT(GPIOC_PIN8) | \ + PIN_MODE_INPUT(GPIOC_PIN9) | \ + PIN_MODE_INPUT(GPIOC_PIN10) | \ + PIN_MODE_INPUT(GPIOC_PIN11) | \ + PIN_MODE_INPUT(GPIOC_PIN12) | \ + PIN_MODE_INPUT(GPIOC_PIN13) | \ + PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ + PIN_MODE_INPUT(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_2M(GPIOC_PIN0) | \ + PIN_OSPEED_2M(GPIOC_PIN1) | \ + PIN_OSPEED_2M(GPIOC_PIN2) | \ + PIN_OSPEED_2M(GPIOC_PIN3) | \ + PIN_OSPEED_2M(GPIOC_PIN4) | \ + PIN_OSPEED_2M(GPIOC_PIN5) | \ + PIN_OSPEED_2M(GPIOC_PIN6) | \ + PIN_OSPEED_2M(GPIOC_PIN7) | \ + PIN_OSPEED_2M(GPIOC_PIN8) | \ + PIN_OSPEED_2M(GPIOC_PIN9) | \ + PIN_OSPEED_2M(GPIOC_PIN10) | \ + PIN_OSPEED_2M(GPIOC_PIN11) | \ + PIN_OSPEED_2M(GPIOC_PIN12) | \ + PIN_OSPEED_2M(GPIOC_PIN13) | \ + PIN_OSPEED_100M(GPIOC_OSC32_IN) | \ + PIN_OSPEED_100M(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \ + PIN_ODR_HIGH(GPIOC_PIN1) | \ + PIN_ODR_HIGH(GPIOC_PIN2) | \ + PIN_ODR_HIGH(GPIOC_PIN3) | \ + PIN_ODR_HIGH(GPIOC_PIN4) | \ + PIN_ODR_HIGH(GPIOC_PIN5) | \ + PIN_ODR_HIGH(GPIOC_PIN6) | \ + PIN_ODR_HIGH(GPIOC_PIN7) | \ + PIN_ODR_HIGH(GPIOC_PIN8) | \ + PIN_ODR_HIGH(GPIOC_PIN9) | \ + PIN_ODR_HIGH(GPIOC_PIN10) | \ + PIN_ODR_HIGH(GPIOC_PIN11) | \ + PIN_ODR_HIGH(GPIOC_PIN12) | \ + PIN_ODR_HIGH(GPIOC_PIN13) | \ + PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ + PIN_ODR_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0) | \ + PIN_AFIO_AF(GPIOC_PIN1, 0) | \ + PIN_AFIO_AF(GPIOC_PIN2, 0) | \ + PIN_AFIO_AF(GPIOC_PIN3, 0) | \ + PIN_AFIO_AF(GPIOC_PIN4, 0) | \ + PIN_AFIO_AF(GPIOC_PIN5, 0) | \ + PIN_AFIO_AF(GPIOC_PIN6, 0) | \ + PIN_AFIO_AF(GPIOC_PIN7, 0)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0) | \ + PIN_AFIO_AF(GPIOC_PIN9, 0) | \ + PIN_AFIO_AF(GPIOC_PIN10, 0) | \ + PIN_AFIO_AF(GPIOC_PIN11, 0) | \ + PIN_AFIO_AF(GPIOC_PIN12, 0) | \ + PIN_AFIO_AF(GPIOC_PIN13, 0) | \ + PIN_AFIO_AF(GPIOC_OSC32_IN, 0) | \ + PIN_AFIO_AF(GPIOC_OSC32_OUT, 0)) /* * GPIOD setup: * -0 */ -#define VAL_GPIOD_MODER 0 -#define VAL_GPIOD_OTYPER 0 -#define VAL_GPIOD_OSPEEDR 0 -#define VAL_GPIOD_PUPDR 0 -#define VAL_GPIOD_ODR 0 -#define VAL_GPIOD_AFRL 0 -#define VAL_GPIOD_AFRH 0 + * PD0 - PIN0 (input pullup). + * PD1 - PIN1 (input pullup). + * PD2 - PIN2 (input pullup). + * PD3 - PIN3 (input pullup). + * PD4 - PIN4 (input pullup). + * PD5 - PIN5 (input pullup). + * PD6 - PIN6 (input pullup). + * PD7 - PIN7 (input pullup). + * PD8 - PIN8 (input pullup). + * PD9 - PIN9 (input pullup). + * PD10 - PIN10 (input pullup). + * PD11 - PIN11 (input pullup). + * PD12 - PIN12 (input pullup). + * PD13 - PIN13 (input pullup). + * PD14 - PIN14 (input pullup). + * PD15 - PIN15 (input pullup). + */ +#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \ + PIN_MODE_INPUT(GPIOD_PIN1) | \ + PIN_MODE_INPUT(GPIOD_PIN2) | \ + PIN_MODE_INPUT(GPIOD_PIN3) | \ + PIN_MODE_INPUT(GPIOD_PIN4) | \ + PIN_MODE_INPUT(GPIOD_PIN5) | \ + PIN_MODE_INPUT(GPIOD_PIN6) | \ + PIN_MODE_INPUT(GPIOD_PIN7) | \ + PIN_MODE_INPUT(GPIOD_PIN8) | \ + PIN_MODE_INPUT(GPIOD_PIN9) | \ + PIN_MODE_INPUT(GPIOD_PIN10) | \ + PIN_MODE_INPUT(GPIOD_PIN11) | \ + PIN_MODE_INPUT(GPIOD_PIN12) | \ + PIN_MODE_INPUT(GPIOD_PIN13) | \ + PIN_MODE_INPUT(GPIOD_PIN14) | \ + PIN_MODE_INPUT(GPIOD_PIN15)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOD_PIN15)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_2M(GPIOD_PIN0) | \ + PIN_OSPEED_2M(GPIOD_PIN1) | \ + PIN_OSPEED_2M(GPIOD_PIN2) | \ + PIN_OSPEED_2M(GPIOD_PIN3) | \ + PIN_OSPEED_2M(GPIOD_PIN4) | \ + PIN_OSPEED_2M(GPIOD_PIN5) | \ + PIN_OSPEED_2M(GPIOD_PIN6) | \ + PIN_OSPEED_2M(GPIOD_PIN7) | \ + PIN_OSPEED_2M(GPIOD_PIN8) | \ + PIN_OSPEED_2M(GPIOD_PIN9) | \ + PIN_OSPEED_2M(GPIOD_PIN10) | \ + PIN_OSPEED_2M(GPIOD_PIN11) | \ + PIN_OSPEED_2M(GPIOD_PIN12) | \ + PIN_OSPEED_2M(GPIOD_PIN13) | \ + PIN_OSPEED_2M(GPIOD_PIN14) | \ + PIN_OSPEED_2M(GPIOD_PIN15)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOD_PIN15)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \ + PIN_ODR_HIGH(GPIOD_PIN1) | \ + PIN_ODR_HIGH(GPIOD_PIN2) | \ + PIN_ODR_HIGH(GPIOD_PIN3) | \ + PIN_ODR_HIGH(GPIOD_PIN4) | \ + PIN_ODR_HIGH(GPIOD_PIN5) | \ + PIN_ODR_HIGH(GPIOD_PIN6) | \ + PIN_ODR_HIGH(GPIOD_PIN7) | \ + PIN_ODR_HIGH(GPIOD_PIN8) | \ + PIN_ODR_HIGH(GPIOD_PIN9) | \ + PIN_ODR_HIGH(GPIOD_PIN10) | \ + PIN_ODR_HIGH(GPIOD_PIN11) | \ + PIN_ODR_HIGH(GPIOD_PIN12) | \ + PIN_ODR_HIGH(GPIOD_PIN13) | \ + PIN_ODR_HIGH(GPIOD_PIN14) | \ + PIN_ODR_HIGH(GPIOD_PIN15)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0) | \ + PIN_AFIO_AF(GPIOD_PIN1, 0) | \ + PIN_AFIO_AF(GPIOD_PIN2, 0) | \ + PIN_AFIO_AF(GPIOD_PIN3, 0) | \ + PIN_AFIO_AF(GPIOD_PIN4, 0) | \ + PIN_AFIO_AF(GPIOD_PIN5, 0) | \ + PIN_AFIO_AF(GPIOD_PIN6, 0) | \ + PIN_AFIO_AF(GPIOD_PIN7, 0)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | \ + PIN_AFIO_AF(GPIOD_PIN9, 0) | \ + PIN_AFIO_AF(GPIOD_PIN10, 0) | \ + PIN_AFIO_AF(GPIOD_PIN11, 0) | \ + PIN_AFIO_AF(GPIOD_PIN12, 0) | \ + PIN_AFIO_AF(GPIOD_PIN13, 0) | \ + PIN_AFIO_AF(GPIOD_PIN14, 0) | \ + PIN_AFIO_AF(GPIOD_PIN15, 0)) /* * GPIOE setup: * + * PE0 - PIN0 (input pullup). + * PE1 - PIN1 (input pullup). + * PE2 - PIN2 (input pullup). + * PE3 - PIN3 (input pullup). + * PE4 - PIN4 (input pullup). + * PE5 - PIN5 (input pullup). + * PE6 - PIN6 (input pullup). + * PE7 - PIN7 (input pullup). + * PE8 - PIN8 (input pullup). + * PE9 - PIN9 (input pullup). + * PE10 - PIN10 (input pullup). + * PE11 - PIN11 (input pullup). + * PE12 - PIN12 (input pullup). + * PE13 - PIN13 (input pullup). + * PE14 - PIN14 (input pullup). + * PE15 - PIN15 (input pullup). */ -#define VAL_GPIOE_MODER 0 -#define VAL_GPIOE_OTYPER 0 -#define VAL_GPIOE_OSPEEDR 0 -#define VAL_GPIOE_PUPDR 0 -#define VAL_GPIOE_ODR 0 -#define VAL_GPIOE_AFRL 0 -#define VAL_GPIOE_AFRH 0 +#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \ + PIN_MODE_INPUT(GPIOE_PIN1) | \ + PIN_MODE_INPUT(GPIOE_PIN2) | \ + PIN_MODE_INPUT(GPIOE_PIN3) | \ + PIN_MODE_INPUT(GPIOE_PIN4) | \ + PIN_MODE_INPUT(GPIOE_PIN5) | \ + PIN_MODE_INPUT(GPIOE_PIN6) | \ + PIN_MODE_INPUT(GPIOE_PIN7) | \ + PIN_MODE_INPUT(GPIOE_PIN8) | \ + PIN_MODE_INPUT(GPIOE_PIN9) | \ + PIN_MODE_INPUT(GPIOE_PIN10) | \ + PIN_MODE_INPUT(GPIOE_PIN11) | \ + PIN_MODE_INPUT(GPIOE_PIN12) | \ + PIN_MODE_INPUT(GPIOE_PIN13) | \ + PIN_MODE_INPUT(GPIOE_PIN14) | \ + PIN_MODE_INPUT(GPIOE_PIN15)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOE_PIN15)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_2M(GPIOE_PIN0) | \ + PIN_OSPEED_2M(GPIOE_PIN1) | \ + PIN_OSPEED_2M(GPIOE_PIN2) | \ + PIN_OSPEED_2M(GPIOE_PIN3) | \ + PIN_OSPEED_2M(GPIOE_PIN4) | \ + PIN_OSPEED_2M(GPIOE_PIN5) | \ + PIN_OSPEED_2M(GPIOE_PIN6) | \ + PIN_OSPEED_2M(GPIOE_PIN7) | \ + PIN_OSPEED_2M(GPIOE_PIN8) | \ + PIN_OSPEED_2M(GPIOE_PIN9) | \ + PIN_OSPEED_2M(GPIOE_PIN10) | \ + PIN_OSPEED_2M(GPIOE_PIN11) | \ + PIN_OSPEED_2M(GPIOE_PIN12) | \ + PIN_OSPEED_2M(GPIOE_PIN13) | \ + PIN_OSPEED_2M(GPIOE_PIN14) | \ + PIN_OSPEED_2M(GPIOE_PIN15)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOE_PIN15)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \ + PIN_ODR_HIGH(GPIOE_PIN1) | \ + PIN_ODR_HIGH(GPIOE_PIN2) | \ + PIN_ODR_HIGH(GPIOE_PIN3) | \ + PIN_ODR_HIGH(GPIOE_PIN4) | \ + PIN_ODR_HIGH(GPIOE_PIN5) | \ + PIN_ODR_HIGH(GPIOE_PIN6) | \ + PIN_ODR_HIGH(GPIOE_PIN7) | \ + PIN_ODR_HIGH(GPIOE_PIN8) | \ + PIN_ODR_HIGH(GPIOE_PIN9) | \ + PIN_ODR_HIGH(GPIOE_PIN10) | \ + PIN_ODR_HIGH(GPIOE_PIN11) | \ + PIN_ODR_HIGH(GPIOE_PIN12) | \ + PIN_ODR_HIGH(GPIOE_PIN13) | \ + PIN_ODR_HIGH(GPIOE_PIN14) | \ + PIN_ODR_HIGH(GPIOE_PIN15)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0) | \ + PIN_AFIO_AF(GPIOE_PIN1, 0) | \ + PIN_AFIO_AF(GPIOE_PIN2, 0) | \ + PIN_AFIO_AF(GPIOE_PIN3, 0) | \ + PIN_AFIO_AF(GPIOE_PIN4, 0) | \ + PIN_AFIO_AF(GPIOE_PIN5, 0) | \ + PIN_AFIO_AF(GPIOE_PIN6, 0) | \ + PIN_AFIO_AF(GPIOE_PIN7, 0)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0) | \ + PIN_AFIO_AF(GPIOE_PIN9, 0) | \ + PIN_AFIO_AF(GPIOE_PIN10, 0) | \ + PIN_AFIO_AF(GPIOE_PIN11, 0) | \ + PIN_AFIO_AF(GPIOE_PIN12, 0) | \ + PIN_AFIO_AF(GPIOE_PIN13, 0) | \ + PIN_AFIO_AF(GPIOE_PIN14, 0) | \ + PIN_AFIO_AF(GPIOE_PIN15, 0)) /* * GPIOF setup: * + * PF0 - PIN0 (input pullup). + * PF1 - PIN1 (input pullup). + * PF2 - PIN2 (input pullup). + * PF3 - PIN3 (input pullup). + * PF4 - PIN4 (input pullup). + * PF5 - PIN5 (input pullup). + * PF6 - PIN6 (input pullup). + * PF7 - PIN7 (input pullup). + * PF8 - PIN8 (input pullup). + * PF9 - PIN9 (input pullup). + * PF10 - PIN10 (input pullup). + * PF11 - PIN11 (input pullup). + * PF12 - PIN12 (input pullup). + * PF13 - PIN13 (input pullup). + * PF14 - PIN14 (input pullup). + * PF15 - PIN15 (input pullup). */ -#define VAL_GPIOF_MODER 0 -#define VAL_GPIOF_OTYPER 0 -#define VAL_GPIOF_OSPEEDR 0 -#define VAL_GPIOF_PUPDR 0 -#define VAL_GPIOF_ODR 0 -#define VAL_GPIOF_AFRL 0 -#define VAL_GPIOF_AFRH 0 +#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \ + PIN_MODE_INPUT(GPIOF_PIN1) | \ + PIN_MODE_INPUT(GPIOF_PIN2) | \ + PIN_MODE_INPUT(GPIOF_PIN3) | \ + PIN_MODE_INPUT(GPIOF_PIN4) | \ + PIN_MODE_INPUT(GPIOF_PIN5) | \ + PIN_MODE_INPUT(GPIOF_PIN6) | \ + PIN_MODE_INPUT(GPIOF_PIN7) | \ + PIN_MODE_INPUT(GPIOF_PIN8) | \ + PIN_MODE_INPUT(GPIOF_PIN9) | \ + PIN_MODE_INPUT(GPIOF_PIN10) | \ + PIN_MODE_INPUT(GPIOF_PIN11) | \ + PIN_MODE_INPUT(GPIOF_PIN12) | \ + PIN_MODE_INPUT(GPIOF_PIN13) | \ + PIN_MODE_INPUT(GPIOF_PIN14) | \ + PIN_MODE_INPUT(GPIOF_PIN15)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOF_PIN15)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_2M(GPIOF_PIN0) | \ + PIN_OSPEED_2M(GPIOF_PIN1) | \ + PIN_OSPEED_2M(GPIOF_PIN2) | \ + PIN_OSPEED_2M(GPIOF_PIN3) | \ + PIN_OSPEED_2M(GPIOF_PIN4) | \ + PIN_OSPEED_2M(GPIOF_PIN5) | \ + PIN_OSPEED_2M(GPIOF_PIN6) | \ + PIN_OSPEED_2M(GPIOF_PIN7) | \ + PIN_OSPEED_2M(GPIOF_PIN8) | \ + PIN_OSPEED_2M(GPIOF_PIN9) | \ + PIN_OSPEED_2M(GPIOF_PIN10) | \ + PIN_OSPEED_2M(GPIOF_PIN11) | \ + PIN_OSPEED_2M(GPIOF_PIN12) | \ + PIN_OSPEED_2M(GPIOF_PIN13) | \ + PIN_OSPEED_2M(GPIOF_PIN14) | \ + PIN_OSPEED_2M(GPIOF_PIN15)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLUP(GPIOF_PIN0) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN1) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN2) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN3) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN4) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN5) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN6) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN7) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN8) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN9) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN10) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN11) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN12) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN13) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN14) | \ + PIN_PUPDR_PULLUP(GPIOF_PIN15)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \ + PIN_ODR_HIGH(GPIOF_PIN1) | \ + PIN_ODR_HIGH(GPIOF_PIN2) | \ + PIN_ODR_HIGH(GPIOF_PIN3) | \ + PIN_ODR_HIGH(GPIOF_PIN4) | \ + PIN_ODR_HIGH(GPIOF_PIN5) | \ + PIN_ODR_HIGH(GPIOF_PIN6) | \ + PIN_ODR_HIGH(GPIOF_PIN7) | \ + PIN_ODR_HIGH(GPIOF_PIN8) | \ + PIN_ODR_HIGH(GPIOF_PIN9) | \ + PIN_ODR_HIGH(GPIOF_PIN10) | \ + PIN_ODR_HIGH(GPIOF_PIN11) | \ + PIN_ODR_HIGH(GPIOF_PIN12) | \ + PIN_ODR_HIGH(GPIOF_PIN13) | \ + PIN_ODR_HIGH(GPIOF_PIN14) | \ + PIN_ODR_HIGH(GPIOF_PIN15)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0) | \ + PIN_AFIO_AF(GPIOF_PIN1, 0) | \ + PIN_AFIO_AF(GPIOF_PIN2, 0) | \ + PIN_AFIO_AF(GPIOF_PIN3, 0) | \ + PIN_AFIO_AF(GPIOF_PIN4, 0) | \ + PIN_AFIO_AF(GPIOF_PIN5, 0) | \ + PIN_AFIO_AF(GPIOF_PIN6, 0) | \ + PIN_AFIO_AF(GPIOF_PIN7, 0)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \ + PIN_AFIO_AF(GPIOF_PIN9, 0) | \ + PIN_AFIO_AF(GPIOF_PIN10, 0) | \ + PIN_AFIO_AF(GPIOF_PIN11, 0) | \ + PIN_AFIO_AF(GPIOF_PIN12, 0) | \ + PIN_AFIO_AF(GPIOF_PIN13, 0) | \ + PIN_AFIO_AF(GPIOF_PIN14, 0) | \ + PIN_AFIO_AF(GPIOF_PIN15, 0)) + #if !defined(_FROM_ASM_) #ifdef __cplusplus diff --git a/boards/ST_STM32F3_DISCOVERY/cfg/board.chcfg b/boards/ST_STM32F3_DISCOVERY/cfg/board.chcfg index a54fca2fe..8dbfcc732 100644 --- a/boards/ST_STM32F3_DISCOVERY/cfg/board.chcfg +++ b/boards/ST_STM32F3_DISCOVERY/cfg/board.chcfg @@ -4,1183 +4,794 @@ xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32f3xx_board.xsd"> - resources/gencfg/processors/boards/stm32f3xx/templates - .. + resources/gencfg/processors/boards/stm32f3xx/templates + .. STMicroelectronics STM32F3-Discovery ST_STM32F3_DISCOVERY - + - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - + + - - - - - - - - - - + + - - + + - - + + + Alternate="0" /> - - + + - + diff --git a/os/hal/platforms/STM32F3xx/hal_lld.h b/os/hal/platforms/STM32F3xx/hal_lld.h index e549d3d8f..79e971743 100644 --- a/os/hal/platforms/STM32F3xx/hal_lld.h +++ b/os/hal/platforms/STM32F3xx/hal_lld.h @@ -25,7 +25,7 @@ * @p board.h file: * - STM32_LSECLK. * - STM32_LSEDRV. - * - STM32_LSEBYP (optionally). + * - STM32_LSE_BYPASS (optionally). * - STM32_HSECLK. * - STM32_HSE_BYPASS (optionally). * . diff --git a/tools/eclipse/config_wizard/plugin.xml b/tools/eclipse/config_wizard/plugin.xml index 5e8e23e7d..d8c660eea 100644 --- a/tools/eclipse/config_wizard/plugin.xml +++ b/tools/eclipse/config_wizard/plugin.xml @@ -40,6 +40,9 @@ + diff --git a/tools/eclipse/config_wizard/resources/gencfg/processors/boards/stm32f3xx/templates/board.c.ftl b/tools/eclipse/config_wizard/resources/gencfg/processors/boards/stm32f3xx/templates/board.c.ftl new file mode 100644 index 000000000..03a4df8c3 --- /dev/null +++ b/tools/eclipse/config_wizard/resources/gencfg/processors/boards/stm32f3xx/templates/board.c.ftl @@ -0,0 +1,133 @@ +[#ftl] +[#-- + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + --] +[@pp.dropOutputFile /] +[#import "/@lib/libutils.ftl" as utils /] +[#import "/@lib/liblicense.ftl" as license /] +[@pp.changeOutputFile name="board.c" /] +/* +[@license.EmitLicenseAsText /] +*/ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +const PALConfig pal_default_config = +{ + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH} +}; +#endif + +/** + * @brief Early initialization code. + * @details This initialization must be performed just after stack setup + * and before any other initialization. + */ +void __early_init(void) { + + stm32_clock_init(); +[#if doc1.board.board_functions.__early_init[0]??] + ${doc1.board.board_functions.__early_init[0]} +[/#if] +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) { +[#if doc1.board.board_functions.sdc_lld_is_card_inserted[0]??] +${doc1.board.board_functions.sdc_lld_is_card_inserted[0]} +[#else] + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return TRUE; +[/#if] +} + +/** + * @brief SDC card write protection detection. + */ +bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) { +[#if doc1.board.board_functions.sdc_lld_is_write_protected[0]??] +${doc1.board.board_functions.sdc_lld_is_write_protected[0]} +[#else] + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return FALSE; +[/#if] +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) { +[#if doc1.board.board_functions.mmc_lld_is_card_inserted[0]??] +${doc1.board.board_functions.mmc_lld_is_card_inserted[0]} +[#else] + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return TRUE; +[/#if] +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) { +[#if doc1.board.board_functions.mmc_lld_is_write_protected[0]??] +${doc1.board.board_functions.mmc_lld_is_write_protected[0]} +[#else] + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return FALSE; +[/#if] +} +#endif + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { +} diff --git a/tools/eclipse/config_wizard/resources/gencfg/processors/boards/stm32f3xx/templates/board.h.ftl b/tools/eclipse/config_wizard/resources/gencfg/processors/boards/stm32f3xx/templates/board.h.ftl new file mode 100644 index 000000000..da8169026 --- /dev/null +++ b/tools/eclipse/config_wizard/resources/gencfg/processors/boards/stm32f3xx/templates/board.h.ftl @@ -0,0 +1,327 @@ +[#ftl] +[#-- + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + --] +[@pp.dropOutputFile /] +[#import "/@lib/libutils.ftl" as utils /] +[#import "/@lib/liblicense.ftl" as license /] +[@pp.changeOutputFile name="board.h" /] +/* +[@license.EmitLicenseAsText /] +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for ${doc1.board.board_name[0]} board. + */ + +/* + * Board identifier. + */ +#define BOARD_${doc1.board.board_id[0]} +#define BOARD_NAME "${doc1.board.board_name[0]}" + +[#if doc1.board.ethernet_phy[0]??] +/* + * Ethernet PHY type. + */ +#define BOARD_PHY_ID ${doc1.board.ethernet_phy.identifier[0]} +[#if doc1.board.ethernet_phy.bus_type[0]?string == "RMII"] +#define BOARD_PHY_RMII +[/#if] + +[/#if] +/* + * Board oscillators-related settings. +[#if doc1.board.clocks.@LSEFrequency[0]?number == 0] + * NOTE: LSE not fitted. +[/#if] +[#if doc1.board.clocks.@HSEFrequency[0]?number == 0] + * NOTE: HSE not fitted. +[/#if] + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK ${doc1.board.clocks.@LSEFrequency[0]} +#endif + +[#if doc1.board.clocks.@LSEBypass[0]?string == "true"] +#define STM32_LSE_BYPASS + +[/#if] +#define STM32_LSEDRV (${doc1.board.clocks.@LSEDrive[0]?word_list[0]?number} << 3) + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK ${doc1.board.clocks.@HSEFrequency[0]} +#endif + +[#if doc1.board.clocks.@HSEBypass[0]?string == "true"] +#define STM32_HSE_BYPASS + +[/#if] +/* + * MCU type as defined in the ST header file stm32f30x.h. + */ +#define STM32F30X + +/* + * IO pins assignments. + */ +[#list doc1.board.ports.* as port] + [#assign port_name = port?node_name?upper_case /] + [#list port.* as pin] + [#assign pin_name = pin?node_name?upper_case /] + [#assign name = pin.@ID[0]?string?trim /] + [#if name?length == 0] + [#assign name = pin_name /] + [/#if] +#define ${(port_name + "_" + name)?right_pad(27, " ")} ${pin_index?string} + [/#list] + +[/#list] +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_2M(n) (0U << ((n) * 2)) +#define PIN_OSPEED_25M(n) (1U << ((n) * 2)) +#define PIN_OSPEED_50M(n) (2U << ((n) * 2)) +#define PIN_OSPEED_100M(n) (3U << ((n) * 2)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2)) +#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4)) + +[#list doc1.board.ports.* as port] + [#assign port_name = port?node_name?upper_case /] +/* + * ${port_name} setup: + * + [#-- Generating pin descriptions inside the comment.--] + [#list port.* as pin] + [#assign pin_name = pin?node_name?upper_case /] + [#assign name = pin.@ID[0]?string?trim /] + [#if name?length == 0] + [#assign name = pin_name /] + [/#if] + [#assign mode = pin.@Mode[0] /] + [#assign type = pin.@Type[0] /] + [#assign resistor = pin.@Resistor[0] /] + [#assign speed = pin.@Speed[0] /] + [#assign alternate = pin.@Alternate[0] /] + [#if mode == "Input"] + [#assign desc = mode + " " + resistor /] + [#elseif mode == "Output"] + [#assign desc = mode + " " + type + " " + speed /] + [#elseif mode == "Alternate"] + [#assign desc = mode + " " + alternate /] + [#else] + [#assign desc = "Analog" /] + [/#if] + * P${(port?node_name[4..] + pin_index?string)?right_pad(3, " ")} - ${name?right_pad(26, " ")}(${desc?lower_case}). + [/#list] + */ + [#-- + -- Generating MODER register value. + --] + [#list port.* as pin] + [#assign pin_name = pin?node_name?upper_case /] + [#assign name = pin.@ID[0]?string?trim /] + [#if name?length == 0] + [#assign name = pin_name /] + [/#if] + [#assign mode = pin.@Mode[0] /] + [#if mode == "Input"] + [#assign out = "PIN_MODE_INPUT(" + port_name + "_" + name + ")" /] + [#elseif mode == "Output"] + [#assign out = "PIN_MODE_OUTPUT(" + port_name + "_" + name + ")" /] + [#elseif mode == "Alternate"] + [#assign out = "PIN_MODE_ALTERNATE(" + port_name + "_" + name + ")" /] + [#else] + [#assign out = "PIN_MODE_ANALOG(" + port_name + "_" + name + ")" /] + [/#if] + [#if pin_index == 0] + [#assign line = "#define VAL_" + port_name + "_MODER (" + out /] + [#else] + [#assign line = " " + out /] + [/#if] + [#if pin_index < 15] +${(line + " |")?right_pad(76, " ") + "\\"} + [#else] +${line + ")"} + [/#if] + [/#list] + [#-- + -- Generating OTYPER register value. + --] + [#list port.* as pin] + [#assign pin_name = pin?node_name?upper_case /] + [#assign name = pin.@ID[0]?string?trim /] + [#if name?length == 0] + [#assign name = pin_name /] + [/#if] + [#assign type = pin.@Type[0] /] + [#if type == "PushPull"] + [#assign out = "PIN_OTYPE_PUSHPULL(" + port_name + "_" + name + ")" /] + [#else] + [#assign out = "PIN_OTYPE_OPENDRAIN(" + port_name + "_" + name + ")" /] + [/#if] + [#if pin_index == 0] + [#assign line = "#define VAL_" + port_name + "_OTYPER (" + out /] + [#else] + [#assign line = " " + out /] + [/#if] + [#if pin_index < 15] +${(line + " |")?right_pad(76, " ") + "\\"} + [#else] +${line + ")"} + [/#if] + [/#list] + [#-- + -- Generating SPEEDR register value. + --] + [#list port.* as pin] + [#assign pin_name = pin?node_name?upper_case /] + [#assign name = pin.@ID[0]?string?trim /] + [#if name?length == 0] + [#assign name = pin_name /] + [/#if] + [#assign speed = pin.@Speed[0] /] + [#if speed == "Minimum"] + [#assign out = "PIN_OSPEED_2M(" + port_name + "_" + name + ")" /] + [#elseif speed == "Low"] + [#assign out = "PIN_OSPEED_25M(" + port_name + "_" + name + ")" /] + [#elseif speed == "High"] + [#assign out = "PIN_OSPEED_50M(" + port_name + "_" + name + ")" /] + [#else] + [#assign out = "PIN_OSPEED_100M(" + port_name + "_" + name + ")" /] + [/#if] + [#if pin_index == 0] + [#assign line = "#define VAL_" + port_name + "_OSPEEDR (" + out /] + [#else] + [#assign line = " " + out /] + [/#if] + [#if pin_index < 15] +${(line + " |")?right_pad(76, " ") + "\\"} + [#else] +${line + ")"} + [/#if] + [/#list] + [#-- + -- Generating PUPDR register value. + --] + [#list port.* as pin] + [#assign pin_name = pin?node_name?upper_case /] + [#assign name = pin.@ID[0]?string?trim /] + [#if name?length == 0] + [#assign name = pin_name /] + [/#if] + [#assign resistor = pin.@Resistor[0] /] + [#if resistor == "Floating"] + [#assign out = "PIN_PUPDR_FLOATING(" + port_name + "_" + name + ")" /] + [#elseif resistor == "PullUp"] + [#assign out = "PIN_PUPDR_PULLUP(" + port_name + "_" + name + ")" /] + [#else] + [#assign out = "PIN_PUPDR_PULLDOWN(" + port_name + "_" + name + ")" /] + [/#if] + [#if pin_index == 0] + [#assign line = "#define VAL_" + port_name + "_PUPDR (" + out /] + [#else] + [#assign line = " " + out /] + [/#if] + [#if pin_index < 15] +${(line + " |")?right_pad(76, " ") + "\\"} + [#else] +${line + ")"} + [/#if] + [/#list] + [#-- + -- Generating ODR register value. + --] + [#list port.* as pin] + [#assign pin_name = pin?node_name?upper_case /] + [#assign name = pin.@ID[0]?string?trim /] + [#if name?length == 0] + [#assign name = pin_name /] + [/#if] + [#assign level = pin.@Level[0] /] + [#if level == "Low"] + [#assign out = "PIN_ODR_LOW(" + port_name + "_" + name + ")" /] + [#else] + [#assign out = "PIN_ODR_HIGH(" + port_name + "_" + name + ")" /] + [/#if] + [#if pin_index == 0] + [#assign line = "#define VAL_" + port_name + "_ODR (" + out /] + [#else] + [#assign line = " " + out /] + [/#if] + [#if pin_index < 15] +${(line + " |")?right_pad(76, " ") + "\\"} + [#else] +${line + ")"} + [/#if] + [/#list] + [#-- + -- Generating AFRx registers values. + --] + [#list port.* as pin] + [#assign pin_name = pin?node_name?upper_case /] + [#assign name = pin.@ID[0]?string?trim /] + [#if name?length == 0] + [#assign name = pin_name /] + [/#if] + [#assign alternate = pin.@Alternate[0]?trim /] + [#assign out = "PIN_AFIO_AF(" + port_name + "_" + name + ", " + alternate + ")" /] + [#if pin_index == 0] + [#assign line = "#define VAL_" + port_name + "_AFRL (" + out /] + [#elseif pin_index == 8] + [#assign line = "#define VAL_" + port_name + "_AFRH (" + out /] + [#else] + [#assign line = " " + out /] + [/#if] + [#if (pin_index == 7) || (pin_index == 15)] +${line + ")"} + [#else] +${(line + " |")?right_pad(76, " ") + "\\"} + [/#if] + [/#list] + +[/#list] + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/tools/eclipse/config_wizard/resources/gencfg/processors/boards/stm32f3xx/templates/board.mk.ftl b/tools/eclipse/config_wizard/resources/gencfg/processors/boards/stm32f3xx/templates/board.mk.ftl new file mode 100644 index 000000000..c88471ac3 --- /dev/null +++ b/tools/eclipse/config_wizard/resources/gencfg/processors/boards/stm32f3xx/templates/board.mk.ftl @@ -0,0 +1,28 @@ +[#ftl] +[#-- + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . + --] +[@pp.dropOutputFile /] +[#import "/@lib/libutils.ftl" as utils /] +[@pp.changeOutputFile name="board.mk" /] +# List of all the board related files. +BOARDSRC = ${'$'}{CHIBIOS}/boards/${doc1.board.board_id[0]}/board.c + +# Required include directories +BOARDINC = ${'$'}{CHIBIOS}/boards/${doc1.board.board_id[0]} diff --git a/tools/eclipse/config_wizard/resources/gencfg/processors/processors.xml b/tools/eclipse/config_wizard/resources/gencfg/processors/processors.xml index 30a70c069..b4998fd9a 100644 --- a/tools/eclipse/config_wizard/resources/gencfg/processors/processors.xml +++ b/tools/eclipse/config_wizard/resources/gencfg/processors/processors.xml @@ -5,6 +5,12 @@ resources/gencfg/xml/stm32f0board.xml board + + STM32F3xx Board Configuration + resources/gencfg/processors/boards/stm32f3xx/templates + resources/gencfg/xml/stm32f3board.xml + board + STM32F4xx Board Configuration resources/gencfg/processors/boards/stm32f4xx/templates @@ -17,22 +23,4 @@ resources/gencfg/xml/stm32l1board.xml board - - STM32F0xx Build Environment Configuration - resources/gencfg/processors/builds/stm32f0xx/templates - resources/gencfg/xml/stm32f0build.xml - build - - - STM32F4xx Build Environment Configuration - resources/gencfg/processors/builds/stm32f4xx/templates - resources/gencfg/xml/stm32f4build.xml - build - - - STM32L1xx Build Environment Configuration - resources/gencfg/processors/builds/stm32l1xx/templates - resources/gencfg/xml/stm32l1build.xml - build - diff --git a/tools/eclipse/config_wizard/resources/gencfg/schema/boards/stm32f0xx_board.xsd b/tools/eclipse/config_wizard/resources/gencfg/schema/boards/stm32f0xx_board.xsd index 6fe520699..59b6e3d68 100644 --- a/tools/eclipse/config_wizard/resources/gencfg/schema/boards/stm32f0xx_board.xsd +++ b/tools/eclipse/config_wizard/resources/gencfg/schema/boards/stm32f0xx_board.xsd @@ -30,6 +30,17 @@ + + + + + + + + + + diff --git a/tools/eclipse/config_wizard/resources/gencfg/schema/boards/stm32f3xx_board.xsd b/tools/eclipse/config_wizard/resources/gencfg/schema/boards/stm32f3xx_board.xsd new file mode 100644 index 000000000..74ad4d7ba --- /dev/null +++ b/tools/eclipse/config_wizard/resources/gencfg/schema/boards/stm32f3xx_board.xsd @@ -0,0 +1,100 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/tools/eclipse/config_wizard/resources/gencfg/schema/boards/stm32f4xx_board.xsd b/tools/eclipse/config_wizard/resources/gencfg/schema/boards/stm32f4xx_board.xsd index 072880711..f0d5a0a87 100644 --- a/tools/eclipse/config_wizard/resources/gencfg/schema/boards/stm32f4xx_board.xsd +++ b/tools/eclipse/config_wizard/resources/gencfg/schema/boards/stm32f4xx_board.xsd @@ -12,27 +12,46 @@ - - - - - - - - + + + + + + + + + - + - + + - + + + + + + + + + + + - + + @@ -41,14 +60,16 @@ - + + - + diff --git a/tools/eclipse/config_wizard/resources/gencfg/schema/boards/stm32l1xx_board.xsd b/tools/eclipse/config_wizard/resources/gencfg/schema/boards/stm32l1xx_board.xsd index 448a51a9c..01350cc7c 100644 --- a/tools/eclipse/config_wizard/resources/gencfg/schema/boards/stm32l1xx_board.xsd +++ b/tools/eclipse/config_wizard/resources/gencfg/schema/boards/stm32l1xx_board.xsd @@ -30,19 +30,29 @@ + + + + + + + + + + - - + + minOccurs="1"> diff --git a/tools/eclipse/config_wizard/resources/gencfg/xml/stm32f3board.xml b/tools/eclipse/config_wizard/resources/gencfg/xml/stm32f3board.xml new file mode 100644 index 000000000..4213e137b --- /dev/null +++ b/tools/eclipse/config_wizard/resources/gencfg/xml/stm32f3board.xml @@ -0,0 +1,797 @@ + + + + + resources/gencfg/processors/boards/stm32f3xx/templates + . + + -----human readable board name----- + BOARD_IDENTIFIER + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + -- cgit v1.2.3