From a240ea59984b670fcae849dd911682f364ae906e Mon Sep 17 00:00:00 2001 From: Rocco Marco Guglielmi Date: Fri, 6 May 2016 09:56:29 +0000 Subject: Reorganized STM32F0xx registry by reordering it git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9429 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/ports/STM32/STM32F0xx/stm32_registry.h | 501 +++++++++++++------------- 1 file changed, 251 insertions(+), 250 deletions(-) diff --git a/os/hal/ports/STM32/STM32F0xx/stm32_registry.h b/os/hal/ports/STM32/STM32F0xx/stm32_registry.h index e7abf8165..d9fc5080d 100644 --- a/os/hal/ports/STM32/STM32F0xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F0xx/stm32_registry.h @@ -38,21 +38,24 @@ * @{ */ /*===========================================================================*/ -/* STM32F051x8, STM32F058xx. */ +/* STM32F030x6, STM32F030x8, STM32F030xC. */ /*===========================================================================*/ -#if defined(STM32F051x8) || defined(STM32F058xx) || \ - defined(__DOXYGEN__) +#if defined(STM32F030x6) || defined(STM32F030x8) || \ + defined(STM32F030xC) || defined(__DOXYGEN__) + +/* Common identifier of all STM32F030 devices.*/ +#define STM32F030 /* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE #define STM32_ADC_SUPPORTS_PRESCALER FALSE #define STM32_ADC_SUPPORTS_OVERSAMPLING FALSE -#define STM32_ADC1_IRQ_SHARED_WITH_EXTI TRUE +#define STM32_ADC1_IRQ_SHARED_WITH_EXTI FALSE #define STM32_ADC1_HANDLER Vector70 #define STM32_ADC1_NUMBER 12 #define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\ STM32_DMA_STREAM_ID_MSK(1, 2)) -#define STM32_ADC1_DMA_CHN 0x00000000 +#define STM32_ADC1_DMA_CHN 0x00000011 #define STM32_HAS_ADC2 FALSE #define STM32_HAS_ADC3 FALSE @@ -63,20 +66,20 @@ #define STM32_HAS_CAN2 FALSE /* DAC attributes.*/ -#define STM32_HAS_DAC1_CH1 TRUE -#define STM32_DAC1_CH1_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) -#define STM32_DAC1_CH1_DMA_CHN 0x00000000 - +#define STM32_HAS_DAC1_CH1 FALSE #define STM32_HAS_DAC1_CH2 FALSE #define STM32_HAS_DAC2_CH1 FALSE #define STM32_HAS_DAC2_CH2 FALSE /* DMA attributes.*/ #define STM32_ADVANCED_DMA TRUE +#if defined(STM32F030xC) || defined(__DOXYGEN__) +#define STM32_DMA_SUPPORTS_CSELR TRUE +#else #define STM32_DMA_SUPPORTS_CSELR FALSE +#endif #define STM32_DMA1_NUM_CHANNELS 5 #define STM32_DMA2_NUM_CHANNELS 0 - #define STM32_DMA1_CH1_HANDLER Vector64 #define STM32_DMA1_CH23_HANDLER Vector68 #define STM32_DMA1_CH4567_HANDLER Vector6C @@ -102,14 +105,18 @@ #define STM32_HAS_ETH FALSE /* EXTI attributes.*/ -#define STM32_EXTI_NUM_LINES 32 -#define STM32_EXTI_IMR_MASK 0x0F940000U +#define STM32_EXTI_NUM_LINES 20 +#define STM32_EXTI_IMR_MASK 0xFFF50000U /* GPIO attributes.*/ #define STM32_HAS_GPIOA TRUE #define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOC TRUE +#if defined(STM32F030x8) #define STM32_HAS_GPIOD TRUE +#else +#define STM32_HAS_GPIOD FALSE +#endif #define STM32_HAS_GPIOE FALSE #define STM32_HAS_GPIOF TRUE #define STM32_HAS_GPIOG FALSE @@ -117,24 +124,31 @@ #define STM32_HAS_GPIOI FALSE #define STM32_HAS_GPIOJ FALSE #define STM32_HAS_GPIOK FALSE +#if defined(STM32F030x8) #define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \ RCC_AHBENR_GPIOBEN | \ RCC_AHBENR_GPIOCEN | \ RCC_AHBENR_GPIODEN | \ RCC_AHBENR_GPIOFEN) +#else +#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \ + RCC_AHBENR_GPIOBEN | \ + RCC_AHBENR_GPIOCEN | \ + RCC_AHBENR_GPIOFEN) +#endif /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE #define STM32_I2C1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) -#define STM32_I2C1_RX_DMA_CHN 0x00000000 +#define STM32_I2C1_RX_DMA_CHN 0x00000200 #define STM32_I2C1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) -#define STM32_I2C1_TX_DMA_CHN 0x00000000 +#define STM32_I2C1_TX_DMA_CHN 0x00000020 #define STM32_HAS_I2C2 TRUE #define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) -#define STM32_I2C2_RX_DMA_CHN 0x00000000 +#define STM32_I2C2_RX_DMA_CHN 0x00020000 #define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_I2C2_TX_DMA_CHN 0x00000000 +#define STM32_I2C2_TX_DMA_CHN 0x00002000 #define STM32_HAS_I2C3 FALSE #define STM32_HAS_I2C4 FALSE @@ -151,19 +165,18 @@ /* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_SUPPORTS_I2S TRUE -#define STM32_SPI1_I2S_FULLDUPLEX FALSE +#define STM32_SPI1_SUPPORTS_I2S FALSE #define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) -#define STM32_SPI1_RX_DMA_CHN 0x00000000 +#define STM32_SPI1_RX_DMA_CHN 0x00000030 #define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) -#define STM32_SPI1_TX_DMA_CHN 0x00000000 +#define STM32_SPI1_TX_DMA_CHN 0x00000300 #define STM32_HAS_SPI2 TRUE #define STM32_SPI2_SUPPORTS_I2S FALSE #define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_RX_DMA_CHN 0x00003000 #define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) -#define STM32_SPI2_TX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_CHN 0x00030000 #define STM32_HAS_SPI3 FALSE #define STM32_HAS_SPI4 FALSE @@ -177,10 +190,6 @@ #define STM32_TIM1_IS_32BITS FALSE #define STM32_TIM1_CHANNELS 4 -#define STM32_HAS_TIM2 TRUE -#define STM32_TIM2_IS_32BITS TRUE -#define STM32_TIM2_CHANNELS 4 - #define STM32_HAS_TIM3 TRUE #define STM32_TIM3_IS_32BITS FALSE #define STM32_TIM3_CHANNELS 4 @@ -205,6 +214,7 @@ #define STM32_TIM17_IS_32BITS FALSE #define STM32_TIM17_CHANNELS 2 +#define STM32_HAS_TIM2 FALSE #define STM32_HAS_TIM4 FALSE #define STM32_HAS_TIM5 FALSE #define STM32_HAS_TIM7 FALSE @@ -222,19 +232,64 @@ /* USART attributes.*/ #define STM32_HAS_USART1 TRUE -#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\ +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\ + STM32_DMA_STREAM_ID_MSK(1, 3) |\ STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_USART1_RX_DMA_CHN 0x00000000 +#define STM32_USART1_RX_DMA_CHN 0x00080808 #define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_USART1_TX_DMA_CHN 0x00000000 +#define STM32_USART1_TX_DMA_CHN 0x00008080 #define STM32_HAS_USART2 TRUE -#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) -#define STM32_USART2_RX_DMA_CHN 0x00000000 -#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_USART2_TX_DMA_CHN 0x00000000 +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\ + STM32_DMA_STREAM_ID_MSK(1, 3) |\ + STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART2_RX_DMA_CHN 0x00090909 +#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ + STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART2_TX_DMA_CHN 0x00009090 + +#if defined(STM32F030xC) +#define STM32_HAS_USART3 TRUE +#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\ + STM32_DMA_STREAM_ID_MSK(1, 3) |\ + STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART3_RX_DMA_CHN 0x000A0A0A +#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ + STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART3_TX_DMA_CHN 0x0000A0A0 + +#define STM32_HAS_UART4 TRUE +#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\ + STM32_DMA_STREAM_ID_MSK(1, 3) |\ + STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_UART4_RX_DMA_CHN 0x000B0B0B +#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ + STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_UART4_TX_DMA_CHN 0x0000B0B0 + +#define STM32_HAS_UART5 TRUE +#define STM32_UART5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\ + STM32_DMA_STREAM_ID_MSK(1, 3) |\ + STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_UART5_RX_DMA_CHN 0x000C0C0C +#define STM32_UART5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ + STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_UART5_TX_DMA_CHN 0x0000C0C0 +#define STM32_HAS_USART6 TRUE +#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\ + STM32_DMA_STREAM_ID_MSK(1, 3) |\ + STM32_DMA_STREAM_ID_MSK(1, 5)) +#define STM32_USART6_RX_DMA_CHN 0x000D0D0D +#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ + STM32_DMA_STREAM_ID_MSK(1, 4)) +#define STM32_USART6_TX_DMA_CHN 0x0000D0D0 + +#define STM32_HAS_UART7 FALSE +#define STM32_HAS_UART8 FALSE +#define STM32_HAS_LPUART1 FALSE +#else #define STM32_HAS_USART3 FALSE #define STM32_HAS_UART4 FALSE #define STM32_HAS_UART5 FALSE @@ -242,6 +297,7 @@ #define STM32_HAS_UART7 FALSE #define STM32_HAS_UART8 FALSE #define STM32_HAS_LPUART1 FALSE +#endif /* USB attributes.*/ #define STM32_HAS_USB FALSE @@ -263,13 +319,12 @@ /* CRC attributes.*/ #define STM32_HAS_CRC TRUE -#define STM32_CRC_PROGRAMMABLE TRUE +#define STM32_CRC_PROGRAMMABLE FALSE /*===========================================================================*/ -/* STM32F071xB, STM32F072xB, STM32F078xx. */ +/* STM32F031x6, STM32F038xx. */ /*===========================================================================*/ -#elif defined(STM32F071xB) || defined(STM32F072xB) || \ - defined(STM32F078xx) +#elif defined(STM32F031x6) || defined(STM32F038xx) /* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE @@ -287,31 +342,19 @@ #define STM32_HAS_ADC4 FALSE /* CAN attributes.*/ -#if defined(STM32F072xB) -#define STM32_HAS_CAN1 TRUE -#define STM32_CAN_MAX_FILTERS 14 -#else #define STM32_HAS_CAN1 FALSE -#endif #define STM32_HAS_CAN2 FALSE /* DAC attributes.*/ -#define STM32_HAS_DAC1_CH1 TRUE -#define STM32_DAC1_CH1_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) -#define STM32_DAC1_CH1_DMA_CHN 0x00000000 - -#define STM32_HAS_DAC1_CH2 TRUE -#define STM32_DAC1_CH2_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_DAC1_CH2_DMA_CHN 0x00000000 - +#define STM32_HAS_DAC1_CH1 FALSE +#define STM32_HAS_DAC1_CH2 FALSE #define STM32_HAS_DAC2_CH1 FALSE #define STM32_HAS_DAC2_CH2 FALSE - /* DMA attributes.*/ #define STM32_ADVANCED_DMA TRUE #define STM32_DMA_SUPPORTS_CSELR FALSE -#define STM32_DMA1_NUM_CHANNELS 7 +#define STM32_DMA1_NUM_CHANNELS 5 #define STM32_DMA2_NUM_CHANNELS 0 #define STM32_DMA1_CH1_HANDLER Vector64 #define STM32_DMA1_CH23_HANDLER Vector68 @@ -339,14 +382,14 @@ /* EXTI attributes.*/ #define STM32_EXTI_NUM_LINES 32 -#define STM32_EXTI_IMR_MASK 0x7F840000U +#define STM32_EXTI_IMR_MASK 0x0FF40000U /* GPIO attributes.*/ #define STM32_HAS_GPIOA TRUE #define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE TRUE +#define STM32_HAS_GPIOD FALSE +#define STM32_HAS_GPIOE FALSE #define STM32_HAS_GPIOF TRUE #define STM32_HAS_GPIOG FALSE #define STM32_HAS_GPIOH FALSE @@ -356,25 +399,16 @@ #define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \ RCC_AHBENR_GPIOBEN | \ RCC_AHBENR_GPIOCEN | \ - RCC_AHBENR_GPIODEN | \ - RCC_AHBENR_GPIOEEN | \ RCC_AHBENR_GPIOFEN) /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\ - STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_I2C1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) #define STM32_I2C1_RX_DMA_CHN 0x00000000 -#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ - STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_I2C1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) #define STM32_I2C1_TX_DMA_CHN 0x00000000 -#define STM32_HAS_I2C2 TRUE -#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) -#define STM32_I2C2_RX_DMA_CHN 0x00000000 -#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_I2C2_TX_DMA_CHN 0x00000000 - +#define STM32_HAS_I2C2 FALSE #define STM32_HAS_I2C3 FALSE #define STM32_HAS_I2C4 FALSE @@ -397,16 +431,7 @@ #define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) #define STM32_SPI1_TX_DMA_CHN 0x00000000 -#define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_SUPPORTS_I2S TRUE -#define STM32_SPI2_I2S_FULLDUPLEX FALSE -#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\ - STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_SPI2_RX_DMA_CHN 0x00000000 -#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\ - STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_SPI2_TX_DMA_CHN 0x00000000 - +#define STM32_HAS_SPI2 FALSE #define STM32_HAS_SPI3 FALSE #define STM32_HAS_SPI4 FALSE #define STM32_HAS_SPI5 FALSE @@ -427,18 +452,10 @@ #define STM32_TIM3_IS_32BITS FALSE #define STM32_TIM3_CHANNELS 4 -#define STM32_HAS_TIM6 TRUE -#define STM32_TIM6_IS_32BITS FALSE -#define STM32_TIM6_CHANNELS 0 - #define STM32_HAS_TIM14 TRUE #define STM32_TIM14_IS_32BITS FALSE #define STM32_TIM14_CHANNELS 1 -#define STM32_HAS_TIM15 TRUE -#define STM32_TIM15_IS_32BITS FALSE -#define STM32_TIM15_CHANNELS 2 - #define STM32_HAS_TIM16 TRUE #define STM32_TIM16_IS_32BITS FALSE #define STM32_TIM16_CHANNELS 2 @@ -449,6 +466,7 @@ #define STM32_HAS_TIM4 FALSE #define STM32_HAS_TIM5 FALSE +#define STM32_HAS_TIM6 FALSE #define STM32_HAS_TIM7 FALSE #define STM32_HAS_TIM8 FALSE #define STM32_HAS_TIM9 FALSE @@ -456,6 +474,7 @@ #define STM32_HAS_TIM11 FALSE #define STM32_HAS_TIM12 FALSE #define STM32_HAS_TIM13 FALSE +#define STM32_HAS_TIM15 FALSE #define STM32_HAS_TIM18 FALSE #define STM32_HAS_TIM19 FALSE #define STM32_HAS_TIM20 FALSE @@ -471,26 +490,9 @@ STM32_DMA_STREAM_ID_MSK(1, 4)) #define STM32_USART1_TX_DMA_CHN 0x00000000 -#define STM32_HAS_USART2 TRUE -#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\ - STM32_DMA_STREAM_ID_MSK(1, 6)) -#define STM32_USART2_RX_DMA_CHN 0x00000000 -#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\ - STM32_DMA_STREAM_ID_MSK(1, 7)) -#define STM32_USART2_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_USART3 TRUE -#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6) -#define STM32_USART3_RX_DMA_CHN 0x00000000 -#define STM32_USART3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7) -#define STM32_USART3_TX_DMA_CHN 0x00000000 - -#define STM32_HAS_UART4 TRUE -#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6) -#define STM32_UART4_RX_DMA_CHN 0x00000000 -#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7) -#define STM32_UART4_TX_DMA_CHN 0x00000000 - +#define STM32_HAS_USART2 FALSE +#define STM32_HAS_USART3 FALSE +#define STM32_HAS_UART4 FALSE #define STM32_HAS_UART5 FALSE #define STM32_HAS_USART6 FALSE #define STM32_HAS_UART7 FALSE @@ -498,14 +500,7 @@ #define STM32_HAS_LPUART1 FALSE /* USB attributes.*/ -#if defined(STM32F072xB) || defined(STM32F078xx) -#define STM32_HAS_USB TRUE -#define STM32_USB_ACCESS_SCHEME_2x16 TRUE -#define STM32_USB_PMA_SIZE 768 -#define STM32_USB_HAS_BCDR TRUE -#else #define STM32_HAS_USB FALSE -#endif #define STM32_HAS_OTG1 FALSE #define STM32_HAS_OTG2 FALSE @@ -527,9 +522,9 @@ #define STM32_CRC_PROGRAMMABLE TRUE /*===========================================================================*/ -/* STM32F048xx. */ +/* STM32F042x6. */ /*===========================================================================*/ -#elif defined(STM32F048xx) +#elif defined(STM32F042x6) /* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE @@ -547,8 +542,9 @@ #define STM32_HAS_ADC4 FALSE /* CAN attributes.*/ -#define STM32_HAS_CAN1 FALSE +#define STM32_HAS_CAN1 TRUE #define STM32_HAS_CAN2 FALSE +#define STM32_CAN_MAX_FILTERS 14 /* DAC attributes.*/ #define STM32_HAS_DAC1_CH1 FALSE @@ -636,13 +632,7 @@ #define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) #define STM32_SPI1_TX_DMA_CHN 0x00000000 -#define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_SUPPORTS_I2S FALSE -#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_SPI2_RX_DMA_CHN 0x00000000 -#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) -#define STM32_SPI2_TX_DMA_CHN 0x00000000 - +#define STM32_HAS_SPI2 FALSE #define STM32_HAS_SPI3 FALSE #define STM32_HAS_SPI4 FALSE #define STM32_HAS_SPI5 FALSE @@ -720,6 +710,7 @@ #define STM32_USB_ACCESS_SCHEME_2x16 TRUE #define STM32_USB_PMA_SIZE 768 #define STM32_USB_HAS_BCDR TRUE + #define STM32_HAS_OTG1 FALSE #define STM32_HAS_OTG2 FALSE @@ -741,9 +732,9 @@ #define STM32_CRC_PROGRAMMABLE TRUE /*===========================================================================*/ -/* STM32F031x6, STM32F038xx. */ +/* STM32F048xx. */ /*===========================================================================*/ -#elif defined(STM32F031x6) || defined(STM32F038xx) +#elif defined(STM32F048xx) /* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE @@ -801,7 +792,7 @@ /* EXTI attributes.*/ #define STM32_EXTI_NUM_LINES 32 -#define STM32_EXTI_IMR_MASK 0x0FF40000U +#define STM32_EXTI_IMR_MASK 0x7FF40000U /* GPIO attributes.*/ #define STM32_HAS_GPIOA TRUE @@ -850,7 +841,13 @@ #define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) #define STM32_SPI1_TX_DMA_CHN 0x00000000 -#define STM32_HAS_SPI2 FALSE +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_SUPPORTS_I2S FALSE +#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + #define STM32_HAS_SPI3 FALSE #define STM32_HAS_SPI4 FALSE #define STM32_HAS_SPI5 FALSE @@ -909,7 +906,12 @@ STM32_DMA_STREAM_ID_MSK(1, 4)) #define STM32_USART1_TX_DMA_CHN 0x00000000 -#define STM32_HAS_USART2 FALSE +#define STM32_HAS_USART2 TRUE +#define STM32_USART2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_USART2_RX_DMA_CHN 0x00000000 +#define STM32_USART2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_USART2_TX_DMA_CHN 0x00000000 + #define STM32_HAS_USART3 FALSE #define STM32_HAS_UART4 FALSE #define STM32_HAS_UART5 FALSE @@ -919,7 +921,10 @@ #define STM32_HAS_LPUART1 FALSE /* USB attributes.*/ -#define STM32_HAS_USB FALSE +#define STM32_HAS_USB TRUE +#define STM32_USB_ACCESS_SCHEME_2x16 TRUE +#define STM32_USB_PMA_SIZE 768 +#define STM32_USB_HAS_BCDR TRUE #define STM32_HAS_OTG1 FALSE #define STM32_HAS_OTG2 FALSE @@ -941,9 +946,9 @@ #define STM32_CRC_PROGRAMMABLE TRUE /*===========================================================================*/ -/* STM32F042x6. */ +/* STM32F051x8, STM32F058xx. */ /*===========================================================================*/ -#elif defined(STM32F042x6) +#elif defined(STM32F051x8) || defined(STM32F058xx) /* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE @@ -961,12 +966,14 @@ #define STM32_HAS_ADC4 FALSE /* CAN attributes.*/ -#define STM32_HAS_CAN1 TRUE +#define STM32_HAS_CAN1 FALSE #define STM32_HAS_CAN2 FALSE -#define STM32_CAN_MAX_FILTERS 14 /* DAC attributes.*/ -#define STM32_HAS_DAC1_CH1 FALSE +#define STM32_HAS_DAC1_CH1 TRUE +#define STM32_DAC1_CH1_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_DAC1_CH1_DMA_CHN 0x00000000 + #define STM32_HAS_DAC1_CH2 FALSE #define STM32_HAS_DAC2_CH1 FALSE #define STM32_HAS_DAC2_CH2 FALSE @@ -976,6 +983,7 @@ #define STM32_DMA_SUPPORTS_CSELR FALSE #define STM32_DMA1_NUM_CHANNELS 5 #define STM32_DMA2_NUM_CHANNELS 0 + #define STM32_DMA1_CH1_HANDLER Vector64 #define STM32_DMA1_CH23_HANDLER Vector68 #define STM32_DMA1_CH4567_HANDLER Vector6C @@ -1002,13 +1010,13 @@ /* EXTI attributes.*/ #define STM32_EXTI_NUM_LINES 32 -#define STM32_EXTI_IMR_MASK 0x7FF40000U +#define STM32_EXTI_IMR_MASK 0x0F940000U /* GPIO attributes.*/ #define STM32_HAS_GPIOA TRUE #define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOC TRUE -#define STM32_HAS_GPIOD FALSE +#define STM32_HAS_GPIOD TRUE #define STM32_HAS_GPIOE FALSE #define STM32_HAS_GPIOF TRUE #define STM32_HAS_GPIOG FALSE @@ -1019,6 +1027,7 @@ #define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \ RCC_AHBENR_GPIOBEN | \ RCC_AHBENR_GPIOCEN | \ + RCC_AHBENR_GPIODEN | \ RCC_AHBENR_GPIOFEN) /* I2C attributes.*/ @@ -1028,7 +1037,12 @@ #define STM32_I2C1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) #define STM32_I2C1_TX_DMA_CHN 0x00000000 -#define STM32_HAS_I2C2 FALSE +#define STM32_HAS_I2C2 TRUE +#define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_I2C2_RX_DMA_CHN 0x00000000 +#define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_I2C2_TX_DMA_CHN 0x00000000 + #define STM32_HAS_I2C3 FALSE #define STM32_HAS_I2C4 FALSE @@ -1051,7 +1065,13 @@ #define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) #define STM32_SPI1_TX_DMA_CHN 0x00000000 -#define STM32_HAS_SPI2 FALSE +#define STM32_HAS_SPI2 TRUE +#define STM32_SPI2_SUPPORTS_I2S FALSE +#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 + #define STM32_HAS_SPI3 FALSE #define STM32_HAS_SPI4 FALSE #define STM32_HAS_SPI5 FALSE @@ -1072,10 +1092,18 @@ #define STM32_TIM3_IS_32BITS FALSE #define STM32_TIM3_CHANNELS 4 +#define STM32_HAS_TIM6 TRUE +#define STM32_TIM6_IS_32BITS FALSE +#define STM32_TIM6_CHANNELS 0 + #define STM32_HAS_TIM14 TRUE #define STM32_TIM14_IS_32BITS FALSE #define STM32_TIM14_CHANNELS 1 +#define STM32_HAS_TIM15 TRUE +#define STM32_TIM15_IS_32BITS FALSE +#define STM32_TIM15_CHANNELS 2 + #define STM32_HAS_TIM16 TRUE #define STM32_TIM16_IS_32BITS FALSE #define STM32_TIM16_CHANNELS 2 @@ -1086,7 +1114,6 @@ #define STM32_HAS_TIM4 FALSE #define STM32_HAS_TIM5 FALSE -#define STM32_HAS_TIM6 FALSE #define STM32_HAS_TIM7 FALSE #define STM32_HAS_TIM8 FALSE #define STM32_HAS_TIM9 FALSE @@ -1094,7 +1121,6 @@ #define STM32_HAS_TIM11 FALSE #define STM32_HAS_TIM12 FALSE #define STM32_HAS_TIM13 FALSE -#define STM32_HAS_TIM15 FALSE #define STM32_HAS_TIM18 FALSE #define STM32_HAS_TIM19 FALSE #define STM32_HAS_TIM20 FALSE @@ -1125,11 +1151,7 @@ #define STM32_HAS_LPUART1 FALSE /* USB attributes.*/ -#define STM32_HAS_USB TRUE -#define STM32_USB_ACCESS_SCHEME_2x16 TRUE -#define STM32_USB_PMA_SIZE 768 -#define STM32_USB_HAS_BCDR TRUE - +#define STM32_HAS_USB FALSE #define STM32_HAS_OTG1 FALSE #define STM32_HAS_OTG2 FALSE @@ -1151,23 +1173,23 @@ #define STM32_CRC_PROGRAMMABLE TRUE /*===========================================================================*/ -/* STM32F030x6, STM32F030x8, STM32F030xC. */ +/* STM32F070x6, STM32F070xB. */ /*===========================================================================*/ -#elif defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F030xC) +#elif defined(STM32F070x6) || defined(STM32F070xB) -/* Common identifier of all STM32F030 devices.*/ -#define STM32F030 +/* Common identifier of all STM32F070 devices.*/ +#define STM32F070 /* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE #define STM32_ADC_SUPPORTS_PRESCALER FALSE #define STM32_ADC_SUPPORTS_OVERSAMPLING FALSE -#define STM32_ADC1_IRQ_SHARED_WITH_EXTI FALSE +#define STM32_ADC1_IRQ_SHARED_WITH_EXTI TRUE #define STM32_ADC1_HANDLER Vector70 #define STM32_ADC1_NUMBER 12 #define STM32_ADC1_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\ STM32_DMA_STREAM_ID_MSK(1, 2)) -#define STM32_ADC1_DMA_CHN 0x00000011 +#define STM32_ADC1_DMA_CHN 0x00000000 #define STM32_HAS_ADC2 FALSE #define STM32_HAS_ADC3 FALSE @@ -1185,11 +1207,7 @@ /* DMA attributes.*/ #define STM32_ADVANCED_DMA TRUE -#if defined(STM32F030xC) || defined(__DOXYGEN__) -#define STM32_DMA_SUPPORTS_CSELR TRUE -#else #define STM32_DMA_SUPPORTS_CSELR FALSE -#endif #define STM32_DMA1_NUM_CHANNELS 5 #define STM32_DMA2_NUM_CHANNELS 0 #define STM32_DMA1_CH1_HANDLER Vector64 @@ -1217,18 +1235,14 @@ #define STM32_HAS_ETH FALSE /* EXTI attributes.*/ -#define STM32_EXTI_NUM_LINES 20 -#define STM32_EXTI_IMR_MASK 0xFFF50000U +#define STM32_EXTI_NUM_LINES 32 +#define STM32_EXTI_IMR_MASK 0x7F840000U /* GPIO attributes.*/ #define STM32_HAS_GPIOA TRUE #define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOC TRUE -#if defined(STM32F030x8) #define STM32_HAS_GPIOD TRUE -#else -#define STM32_HAS_GPIOD FALSE -#endif #define STM32_HAS_GPIOE FALSE #define STM32_HAS_GPIOF TRUE #define STM32_HAS_GPIOG FALSE @@ -1236,31 +1250,26 @@ #define STM32_HAS_GPIOI FALSE #define STM32_HAS_GPIOJ FALSE #define STM32_HAS_GPIOK FALSE -#if defined(STM32F030x8) #define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \ RCC_AHBENR_GPIOBEN | \ RCC_AHBENR_GPIOCEN | \ RCC_AHBENR_GPIODEN | \ RCC_AHBENR_GPIOFEN) -#else -#define STM32_GPIO_EN_MASK (RCC_AHBENR_GPIOAEN | \ - RCC_AHBENR_GPIOBEN | \ - RCC_AHBENR_GPIOCEN | \ - RCC_AHBENR_GPIOFEN) -#endif /* I2C attributes.*/ #define STM32_HAS_I2C1 TRUE -#define STM32_I2C1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) -#define STM32_I2C1_RX_DMA_CHN 0x00000200 -#define STM32_I2C1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) -#define STM32_I2C1_TX_DMA_CHN 0x00000020 +#define STM32_I2C1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\ + STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_I2C1_RX_DMA_CHN 0x00000000 +#define STM32_I2C1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ + STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_I2C1_TX_DMA_CHN 0x00000000 #define STM32_HAS_I2C2 TRUE #define STM32_I2C2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) -#define STM32_I2C2_RX_DMA_CHN 0x00020000 +#define STM32_I2C2_RX_DMA_CHN 0x00000000 #define STM32_I2C2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_I2C2_TX_DMA_CHN 0x00002000 +#define STM32_I2C2_TX_DMA_CHN 0x00000000 #define STM32_HAS_I2C3 FALSE #define STM32_HAS_I2C4 FALSE @@ -1279,16 +1288,18 @@ #define STM32_HAS_SPI1 TRUE #define STM32_SPI1_SUPPORTS_I2S FALSE #define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) -#define STM32_SPI1_RX_DMA_CHN 0x00000030 +#define STM32_SPI1_RX_DMA_CHN 0x00000000 #define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) -#define STM32_SPI1_TX_DMA_CHN 0x00000300 +#define STM32_SPI1_TX_DMA_CHN 0x00000000 #define STM32_HAS_SPI2 TRUE #define STM32_SPI2_SUPPORTS_I2S FALSE -#define STM32_SPI2_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) -#define STM32_SPI2_RX_DMA_CHN 0x00003000 -#define STM32_SPI2_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 5) -#define STM32_SPI2_TX_DMA_CHN 0x00030000 +#define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\ + STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_SPI2_RX_DMA_CHN 0x00000000 +#define STM32_SPI2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\ + STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_SPI2_TX_DMA_CHN 0x00000000 #define STM32_HAS_SPI3 FALSE #define STM32_HAS_SPI4 FALSE @@ -1310,6 +1321,10 @@ #define STM32_TIM6_IS_32BITS FALSE #define STM32_TIM6_CHANNELS 0 +#define STM32_HAS_TIM7 TRUE +#define STM32_TIM7_IS_32BITS FALSE +#define STM32_TIM7_CHANNELS 0 + #define STM32_HAS_TIM14 TRUE #define STM32_TIM14_IS_32BITS FALSE #define STM32_TIM14_CHANNELS 1 @@ -1329,7 +1344,6 @@ #define STM32_HAS_TIM2 FALSE #define STM32_HAS_TIM4 FALSE #define STM32_HAS_TIM5 FALSE -#define STM32_HAS_TIM7 FALSE #define STM32_HAS_TIM8 FALSE #define STM32_HAS_TIM9 FALSE #define STM32_HAS_TIM10 FALSE @@ -1344,75 +1358,45 @@ /* USART attributes.*/ #define STM32_HAS_USART1 TRUE -#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\ - STM32_DMA_STREAM_ID_MSK(1, 3) |\ +#define STM32_USART1_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) |\ STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_USART1_RX_DMA_CHN 0x00080808 +#define STM32_USART1_RX_DMA_CHN 0x00000000 #define STM32_USART1_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_USART1_TX_DMA_CHN 0x00008080 +#define STM32_USART1_TX_DMA_CHN 0x00000000 #define STM32_HAS_USART2 TRUE -#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\ - STM32_DMA_STREAM_ID_MSK(1, 3) |\ - STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_USART2_RX_DMA_CHN 0x00090909 -#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ - STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_USART2_TX_DMA_CHN 0x00009090 +#define STM32_USART2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 5) |\ + STM32_DMA_STREAM_ID_MSK(1, 6)) +#define STM32_USART2_RX_DMA_CHN 0x00000000 +#define STM32_USART2_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\ + STM32_DMA_STREAM_ID_MSK(1, 7)) +#define STM32_USART2_TX_DMA_CHN 0x00000000 -#if defined(STM32F030xC) #define STM32_HAS_USART3 TRUE -#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\ - STM32_DMA_STREAM_ID_MSK(1, 3) |\ - STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_USART3_RX_DMA_CHN 0x000A0A0A -#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ - STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_USART3_TX_DMA_CHN 0x0000A0A0 +#define STM32_USART3_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6) +#define STM32_USART3_RX_DMA_CHN 0x00000000 +#define STM32_USART3_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7) +#define STM32_USART3_TX_DMA_CHN 0x00000000 #define STM32_HAS_UART4 TRUE -#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\ - STM32_DMA_STREAM_ID_MSK(1, 3) |\ - STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_UART4_RX_DMA_CHN 0x000B0B0B -#define STM32_UART4_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ - STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_UART4_TX_DMA_CHN 0x0000B0B0 - -#define STM32_HAS_UART5 TRUE -#define STM32_UART5_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\ - STM32_DMA_STREAM_ID_MSK(1, 3) |\ - STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_UART5_RX_DMA_CHN 0x000C0C0C -#define STM32_UART5_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ - STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_UART5_TX_DMA_CHN 0x0000C0C0 - -#define STM32_HAS_USART6 TRUE -#define STM32_USART6_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1) |\ - STM32_DMA_STREAM_ID_MSK(1, 3) |\ - STM32_DMA_STREAM_ID_MSK(1, 5)) -#define STM32_USART6_RX_DMA_CHN 0x000D0D0D -#define STM32_USART6_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2) |\ - STM32_DMA_STREAM_ID_MSK(1, 4)) -#define STM32_USART6_TX_DMA_CHN 0x0000D0D0 +#define STM32_UART4_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 6) +#define STM32_UART4_RX_DMA_CHN 0x00000000 +#define STM32_UART4_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 7) +#define STM32_UART4_TX_DMA_CHN 0x00000000 -#define STM32_HAS_UART7 FALSE -#define STM32_HAS_UART8 FALSE -#define STM32_HAS_LPUART1 FALSE -#else -#define STM32_HAS_USART3 FALSE -#define STM32_HAS_UART4 FALSE #define STM32_HAS_UART5 FALSE #define STM32_HAS_USART6 FALSE #define STM32_HAS_UART7 FALSE #define STM32_HAS_UART8 FALSE #define STM32_HAS_LPUART1 FALSE -#endif /* USB attributes.*/ -#define STM32_HAS_USB FALSE +#define STM32_HAS_USB TRUE +#define STM32_USB_ACCESS_SCHEME_2x16 TRUE +#define STM32_USB_PMA_SIZE 768 +#define STM32_USB_HAS_BCDR TRUE + #define STM32_HAS_OTG1 FALSE #define STM32_HAS_OTG2 FALSE @@ -1434,12 +1418,10 @@ #define STM32_CRC_PROGRAMMABLE FALSE /*===========================================================================*/ -/* STM32F070x6, STM32F070xB. */ +/* STM32F071xB, STM32F072xB, STM32F078xx. */ /*===========================================================================*/ -#elif defined(STM32F070x6) || defined(STM32F070xB) - -/* Common identifier of all STM32F070 devices.*/ -#define STM32F070 +#elif defined(STM32F071xB) || defined(STM32F072xB) || \ + defined(STM32F078xx) /* ADC attributes.*/ #define STM32_HAS_ADC1 TRUE @@ -1457,19 +1439,31 @@ #define STM32_HAS_ADC4 FALSE /* CAN attributes.*/ +#if defined(STM32F072xB) +#define STM32_HAS_CAN1 TRUE +#define STM32_CAN_MAX_FILTERS 14 +#else #define STM32_HAS_CAN1 FALSE +#endif #define STM32_HAS_CAN2 FALSE /* DAC attributes.*/ -#define STM32_HAS_DAC1_CH1 FALSE -#define STM32_HAS_DAC1_CH2 FALSE +#define STM32_HAS_DAC1_CH1 TRUE +#define STM32_DAC1_CH1_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) +#define STM32_DAC1_CH1_DMA_CHN 0x00000000 + +#define STM32_HAS_DAC1_CH2 TRUE +#define STM32_DAC1_CH2_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 4) +#define STM32_DAC1_CH2_DMA_CHN 0x00000000 + #define STM32_HAS_DAC2_CH1 FALSE #define STM32_HAS_DAC2_CH2 FALSE + /* DMA attributes.*/ #define STM32_ADVANCED_DMA TRUE #define STM32_DMA_SUPPORTS_CSELR FALSE -#define STM32_DMA1_NUM_CHANNELS 5 +#define STM32_DMA1_NUM_CHANNELS 7 #define STM32_DMA2_NUM_CHANNELS 0 #define STM32_DMA1_CH1_HANDLER Vector64 #define STM32_DMA1_CH23_HANDLER Vector68 @@ -1504,7 +1498,7 @@ #define STM32_HAS_GPIOB TRUE #define STM32_HAS_GPIOC TRUE #define STM32_HAS_GPIOD TRUE -#define STM32_HAS_GPIOE FALSE +#define STM32_HAS_GPIOE TRUE #define STM32_HAS_GPIOF TRUE #define STM32_HAS_GPIOG FALSE #define STM32_HAS_GPIOH FALSE @@ -1515,6 +1509,7 @@ RCC_AHBENR_GPIOBEN | \ RCC_AHBENR_GPIOCEN | \ RCC_AHBENR_GPIODEN | \ + RCC_AHBENR_GPIOEEN | \ RCC_AHBENR_GPIOFEN) /* I2C attributes.*/ @@ -1547,14 +1542,16 @@ /* SPI attributes.*/ #define STM32_HAS_SPI1 TRUE -#define STM32_SPI1_SUPPORTS_I2S FALSE +#define STM32_SPI1_SUPPORTS_I2S TRUE +#define STM32_SPI1_I2S_FULLDUPLEX FALSE #define STM32_SPI1_RX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 2) #define STM32_SPI1_RX_DMA_CHN 0x00000000 #define STM32_SPI1_TX_DMA_MSK STM32_DMA_STREAM_ID_MSK(1, 3) #define STM32_SPI1_TX_DMA_CHN 0x00000000 #define STM32_HAS_SPI2 TRUE -#define STM32_SPI2_SUPPORTS_I2S FALSE +#define STM32_SPI2_SUPPORTS_I2S TRUE +#define STM32_SPI2_I2S_FULLDUPLEX FALSE #define STM32_SPI2_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 4) |\ STM32_DMA_STREAM_ID_MSK(1, 6)) #define STM32_SPI2_RX_DMA_CHN 0x00000000 @@ -1574,6 +1571,10 @@ #define STM32_TIM1_IS_32BITS FALSE #define STM32_TIM1_CHANNELS 4 +#define STM32_HAS_TIM2 TRUE +#define STM32_TIM2_IS_32BITS TRUE +#define STM32_TIM2_CHANNELS 4 + #define STM32_HAS_TIM3 TRUE #define STM32_TIM3_IS_32BITS FALSE #define STM32_TIM3_CHANNELS 4 @@ -1582,10 +1583,6 @@ #define STM32_TIM6_IS_32BITS FALSE #define STM32_TIM6_CHANNELS 0 -#define STM32_HAS_TIM7 TRUE -#define STM32_TIM7_IS_32BITS FALSE -#define STM32_TIM7_CHANNELS 0 - #define STM32_HAS_TIM14 TRUE #define STM32_TIM14_IS_32BITS FALSE #define STM32_TIM14_CHANNELS 1 @@ -1602,9 +1599,9 @@ #define STM32_TIM17_IS_32BITS FALSE #define STM32_TIM17_CHANNELS 2 -#define STM32_HAS_TIM2 FALSE #define STM32_HAS_TIM4 FALSE #define STM32_HAS_TIM5 FALSE +#define STM32_HAS_TIM7 FALSE #define STM32_HAS_TIM8 FALSE #define STM32_HAS_TIM9 FALSE #define STM32_HAS_TIM10 FALSE @@ -1653,11 +1650,14 @@ #define STM32_HAS_LPUART1 FALSE /* USB attributes.*/ +#if defined(STM32F072xB) || defined(STM32F078xx) #define STM32_HAS_USB TRUE #define STM32_USB_ACCESS_SCHEME_2x16 TRUE #define STM32_USB_PMA_SIZE 768 #define STM32_USB_HAS_BCDR TRUE - +#else +#define STM32_HAS_USB FALSE +#endif #define STM32_HAS_OTG1 FALSE #define STM32_HAS_OTG2 FALSE @@ -1676,7 +1676,8 @@ /* CRC attributes.*/ #define STM32_HAS_CRC TRUE -#define STM32_CRC_PROGRAMMABLE FALSE +#define STM32_CRC_PROGRAMMABLE TRUE + /*===========================================================================*/ /* STM32F091xC, STM32F098xx. */ -- cgit v1.2.3