From 93369a9bd2c5d59fc70b1c21466fb2c82b4361ad Mon Sep 17 00:00:00 2001 From: gdisirio Date: Tue, 18 Mar 2014 09:42:04 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/kernel_3_dev@6781 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/ports/STM32/STM32F30x/hal_lld.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/os/hal/ports/STM32/STM32F30x/hal_lld.h b/os/hal/ports/STM32/STM32F30x/hal_lld.h index 81f7bf288..97e564724 100644 --- a/os/hal/ports/STM32/STM32F30x/hal_lld.h +++ b/os/hal/ports/STM32/STM32F30x/hal_lld.h @@ -247,10 +247,10 @@ #define STM32_I2C2SW_SYSCLK (1 << 5) /**< I2C2 clock is SYSCLK. */ #define STM32_TIM1SW_MASK (1 << 8) /**< TIM1 clock source mask. */ #define STM32_TIM1SW_PCLK2 (0 << 8) /**< TIM1 clock is PCLK2. */ -#define STM32_TIM1SW_PLLX2 (1 << 10) /**< TIM1 clock is PLL*2. */ -#define STM32_TIM8SW_MASK (1 << 10) /**< TIM8 clock source mask. */ -#define STM32_TIM8SW_PCLK2 (0 << 10) /**< TIM8 clock is PCLK2. */ -#define STM32_TIM8SW_PLLX2 (1 << 10) /**< TIM8 clock is PLL*2. */ +#define STM32_TIM1SW_PLLX2 (1 << 8) /**< TIM1 clock is PLL*2. */ +#define STM32_TIM8SW_MASK (1 << 9) /**< TIM8 clock source mask. */ +#define STM32_TIM8SW_PCLK2 (0 << 9) /**< TIM8 clock is PCLK2. */ +#define STM32_TIM8SW_PLLX2 (1 << 9) /**< TIM8 clock is PLL*2. */ #define STM32_USART2SW_MASK (3 << 16) /**< USART2 clock source mask. */ #define STM32_USART2SW_PCLK (0 << 16) /**< USART2 clock is PCLK. */ #define STM32_USART2SW_SYSCLK (1 << 16) /**< USART2 clock is SYSCLK. */ -- cgit v1.2.3