From 7aa44fe530c4492f07d37844870960f08213e89b Mon Sep 17 00:00:00 2001 From: Rocco Marco Guglielmi Date: Mon, 2 Jan 2017 16:17:41 +0000 Subject: Fixed bug 808. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@10010 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/ports/STM32/STM32F0xx/hal_lld.c | 6 +++++- readme.txt | 3 +++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/os/hal/ports/STM32/STM32F0xx/hal_lld.c b/os/hal/ports/STM32/STM32F0xx/hal_lld.c index a85e92ac8..847fa8562 100644 --- a/os/hal/ports/STM32/STM32F0xx/hal_lld.c +++ b/os/hal/ports/STM32/STM32F0xx/hal_lld.c @@ -28,6 +28,9 @@ /* Driver local definitions. */ /*===========================================================================*/ +#define STM32_PLLXTPRE_OFFSET 17 /**< PLLXTPRE offset */ +#define STM32_PLLXTPRE_MASK 0x01 /**< PLLXTPRE mask */ + /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ @@ -310,7 +313,8 @@ void stm32_clock_init(void) { /* CFGR2 must be configured first since CFGR value could change CFGR2 */ RCC->CFGR2 = STM32_PREDIV; RCC->CFGR = STM32_PLLNODIV | STM32_MCOPRE | STM32_MCOSEL | STM32_PLLMUL | - STM32_PLLSRC | STM32_PPRE | STM32_HPRE; + STM32_PLLSRC | STM32_PPRE | STM32_HPRE | + ((STM32_PREDIV & STM32_PLLXTPRE_MASK) << STM32_PLLXTPRE_OFFSET); #if STM32_CECSW == STM32_CECSW_OFF RCC->CFGR3 = STM32_USBSW | STM32_I2C1SW | STM32_USART1SW; #else diff --git a/readme.txt b/readme.txt index f1c0cb5fd..58ad64157 100644 --- a/readme.txt +++ b/readme.txt @@ -153,6 +153,9 @@ - RT: Merged RT4. - NIL: Merged NIL2. - NIL: Added STM32F7 demo. +- HAL: Fixed clock init in STM32F0x port which doesn't take in account + PLL_XTPRE and PREDIV_0 are hard-wired (bug #808) + (backported to 16.1.7). - HAL: Fixed wrong initialization in ADC lld v3 (bug #807) (backported to 16.1.6). - HAL: Fixed wrong clock init in STM32F0 port ad added more error checks -- cgit v1.2.3