From 736e966cf5cd6cae1732d874229f363ecfcb9b3a Mon Sep 17 00:00:00 2001
From: gdisirio <gdisirio@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Thu, 2 Oct 2014 10:13:13 +0000
Subject: renamed STM32F3 directories to reflect new models

git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@7342 35acf78f-673a-0410-8e92-d51de3d6d3f4
---
 demos/STM32/RT-STM32F303-DISCOVERY/Makefile        |    4 +-
 demos/STM32/RT-STM32F303-DISCOVERY/iar/ch.ewp      |   40 +-
 demos/STM32/RT-STM32F303-DISCOVERY/keil/ch.uvproj  |   36 +-
 demos/STM32/RT-STM32F303-DISCOVERY/mcuconf.h       |    4 +-
 demos/STM32/RT-STM32F373-STM32373C_EVAL/Makefile   |    2 +-
 .../ports/ARMCMx/devices/STM32F30x/cmparams.h      |   90 --
 .../ports/ARMCMx/devices/STM32F37x/cmparams.h      |   85 --
 .../ports/ARMCMx/devices/STM32F3xx/cmparams.h      |   90 ++
 os/hal/ports/STM32/STM32F30x/adc_lld.c             |  548 --------
 os/hal/ports/STM32/STM32F30x/adc_lld.h             |  619 ---------
 os/hal/ports/STM32/STM32F30x/ext_lld_isr.c         |  406 ------
 os/hal/ports/STM32/STM32F30x/ext_lld_isr.h         |  177 ---
 os/hal/ports/STM32/STM32F30x/hal_lld.c             |  202 ---
 os/hal/ports/STM32/STM32F30x/hal_lld.h             | 1150 ----------------
 os/hal/ports/STM32/STM32F30x/platform.mk           |   31 -
 os/hal/ports/STM32/STM32F30x/stm32_dma.c           |  449 ------
 os/hal/ports/STM32/STM32F30x/stm32_dma.h           |  406 ------
 os/hal/ports/STM32/STM32F30x/stm32_isr.h           |  132 --
 os/hal/ports/STM32/STM32F30x/stm32_rcc.h           |  835 -----------
 os/hal/ports/STM32/STM32F30x/stm32_registry.h      | 1444 --------------------
 os/hal/ports/STM32/STM32F3xx/adc_lld.c             |  548 ++++++++
 os/hal/ports/STM32/STM32F3xx/adc_lld.h             |  619 +++++++++
 os/hal/ports/STM32/STM32F3xx/ext_lld_isr.c         |  406 ++++++
 os/hal/ports/STM32/STM32F3xx/ext_lld_isr.h         |  177 +++
 os/hal/ports/STM32/STM32F3xx/hal_lld.c             |  202 +++
 os/hal/ports/STM32/STM32F3xx/hal_lld.h             | 1150 ++++++++++++++++
 os/hal/ports/STM32/STM32F3xx/platform.mk           |   31 +
 os/hal/ports/STM32/STM32F3xx/stm32_dma.c           |  449 ++++++
 os/hal/ports/STM32/STM32F3xx/stm32_dma.h           |  406 ++++++
 os/hal/ports/STM32/STM32F3xx/stm32_isr.h           |  132 ++
 os/hal/ports/STM32/STM32F3xx/stm32_rcc.h           |  835 +++++++++++
 os/hal/ports/STM32/STM32F3xx/stm32_registry.h      | 1444 ++++++++++++++++++++
 .../ARMCMx/compilers/GCC/mk/port_stm32f30x.mk      |   15 -
 .../ARMCMx/compilers/GCC/mk/port_stm32f3xx.mk      |   15 +
 .../ARMCMx/compilers/GCC/mk/port_stm32f30x.mk      |   15 -
 .../ARMCMx/compilers/GCC/mk/port_stm32f3xx.mk      |   15 +
 testhal/STM32/STM32F30x/ADC/Makefile               |    4 +-
 testhal/STM32/STM32F30x/ADC/mcuconf.h              |    4 +-
 testhal/STM32/STM32F30x/ADC_DUAL/Makefile          |    4 +-
 testhal/STM32/STM32F30x/ADC_DUAL/mcuconf.h         |    4 +-
 testhal/STM32/STM32F30x/CAN/Makefile               |    4 +-
 testhal/STM32/STM32F30x/CAN/mcuconf.h              |    4 +-
 testhal/STM32/STM32F30x/EXT/Makefile               |    4 +-
 testhal/STM32/STM32F30x/EXT/mcuconf.h              |    4 +-
 testhal/STM32/STM32F30x/IRQ_STORM/Makefile         |    4 +-
 testhal/STM32/STM32F30x/IRQ_STORM/mcuconf.h        |    4 +-
 testhal/STM32/STM32F30x/PWM-ICU/Makefile           |    4 +-
 testhal/STM32/STM32F30x/PWM-ICU/mcuconf.h          |    4 +-
 testhal/STM32/STM32F30x/SPI/Makefile               |    4 +-
 testhal/STM32/STM32F30x/SPI/mcuconf.h              |    4 +-
 testhal/STM32/STM32F30x/UART/Makefile              |    4 +-
 testhal/STM32/STM32F30x/UART/mcuconf.h             |    4 +-
 testhal/STM32/STM32F30x/USB_CDC/Makefile           |    4 +-
 testhal/STM32/STM32F30x/USB_CDC/mcuconf.h          |    4 +-
 testhal/STM32/STM32F37x/ADC/Makefile               |    2 +-
 testhal/STM32/STM32F37x/CAN/Makefile               |    2 +-
 testhal/STM32/STM32F37x/EXT/Makefile               |    2 +-
 testhal/STM32/STM32F37x/I2C/Makefile               |    2 +-
 testhal/STM32/STM32F37x/IRQ_STORM/Makefile         |    2 +-
 testhal/STM32/STM32F37x/PWM-ICU/Makefile           |    2 +-
 testhal/STM32/STM32F37x/SDADC/Makefile             |    2 +-
 testhal/STM32/STM32F37x/SPI/Makefile               |    2 +-
 testhal/STM32/STM32F37x/UART/Makefile              |    2 +-
 testhal/STM32/STM32F37x/USB_CDC/Makefile           |    2 +-
 64 files changed, 6608 insertions(+), 6693 deletions(-)
 delete mode 100644 os/common/ports/ARMCMx/devices/STM32F30x/cmparams.h
 delete mode 100644 os/common/ports/ARMCMx/devices/STM32F37x/cmparams.h
 create mode 100644 os/common/ports/ARMCMx/devices/STM32F3xx/cmparams.h
 delete mode 100644 os/hal/ports/STM32/STM32F30x/adc_lld.c
 delete mode 100644 os/hal/ports/STM32/STM32F30x/adc_lld.h
 delete mode 100644 os/hal/ports/STM32/STM32F30x/ext_lld_isr.c
 delete mode 100644 os/hal/ports/STM32/STM32F30x/ext_lld_isr.h
 delete mode 100644 os/hal/ports/STM32/STM32F30x/hal_lld.c
 delete mode 100644 os/hal/ports/STM32/STM32F30x/hal_lld.h
 delete mode 100644 os/hal/ports/STM32/STM32F30x/platform.mk
 delete mode 100644 os/hal/ports/STM32/STM32F30x/stm32_dma.c
 delete mode 100644 os/hal/ports/STM32/STM32F30x/stm32_dma.h
 delete mode 100644 os/hal/ports/STM32/STM32F30x/stm32_isr.h
 delete mode 100644 os/hal/ports/STM32/STM32F30x/stm32_rcc.h
 delete mode 100644 os/hal/ports/STM32/STM32F30x/stm32_registry.h
 create mode 100644 os/hal/ports/STM32/STM32F3xx/adc_lld.c
 create mode 100644 os/hal/ports/STM32/STM32F3xx/adc_lld.h
 create mode 100644 os/hal/ports/STM32/STM32F3xx/ext_lld_isr.c
 create mode 100644 os/hal/ports/STM32/STM32F3xx/ext_lld_isr.h
 create mode 100644 os/hal/ports/STM32/STM32F3xx/hal_lld.c
 create mode 100644 os/hal/ports/STM32/STM32F3xx/hal_lld.h
 create mode 100644 os/hal/ports/STM32/STM32F3xx/platform.mk
 create mode 100644 os/hal/ports/STM32/STM32F3xx/stm32_dma.c
 create mode 100644 os/hal/ports/STM32/STM32F3xx/stm32_dma.h
 create mode 100644 os/hal/ports/STM32/STM32F3xx/stm32_isr.h
 create mode 100644 os/hal/ports/STM32/STM32F3xx/stm32_rcc.h
 create mode 100644 os/hal/ports/STM32/STM32F3xx/stm32_registry.h
 delete mode 100644 os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f30x.mk
 create mode 100644 os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f3xx.mk
 delete mode 100644 os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f30x.mk
 create mode 100644 os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f3xx.mk

diff --git a/demos/STM32/RT-STM32F303-DISCOVERY/Makefile b/demos/STM32/RT-STM32F303-DISCOVERY/Makefile
index 6f276f8f9..fcd7c512e 100644
--- a/demos/STM32/RT-STM32F303-DISCOVERY/Makefile
+++ b/demos/STM32/RT-STM32F303-DISCOVERY/Makefile
@@ -83,10 +83,10 @@ PROJECT = ch
 CHIBIOS = ../../..
 include $(CHIBIOS)/os/hal/hal.mk
 include $(CHIBIOS)/os/hal/boards/ST_STM32F3_DISCOVERY/board.mk
-include $(CHIBIOS)/os/hal/ports/STM32/STM32F30x/platform.mk
+include $(CHIBIOS)/os/hal/ports/STM32/STM32F3xx/platform.mk
 include $(CHIBIOS)/os/hal/osal/rt/osal.mk
 include $(CHIBIOS)/os/rt/rt.mk
-include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f30x.mk
+include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f3xx.mk
 include $(CHIBIOS)/test/rt/test.mk
 
 # Define linker script file here
diff --git a/demos/STM32/RT-STM32F303-DISCOVERY/iar/ch.ewp b/demos/STM32/RT-STM32F303-DISCOVERY/iar/ch.ewp
index 9427f0f63..fd7b13a99 100644
--- a/demos/STM32/RT-STM32F303-DISCOVERY/iar/ch.ewp
+++ b/demos/STM32/RT-STM32F303-DISCOVERY/iar/ch.ewp
@@ -302,7 +302,7 @@
         <option>
           <name>CCIncludePath2</name>
           <state>$PROJ_DIR$\..\</state>
-          <state>$PROJ_DIR$\..\..\..\..\os\common\ports\ARMCMx\devices\STM32F30x</state>
+          <state>$PROJ_DIR$\..\..\..\..\os\common\ports\ARMCMx\devices\STM32F3xx</state>
           <state>$PROJ_DIR$\..\..\..\..\os\ext\CMSIS\include</state>
           <state>$PROJ_DIR$\..\..\..\..\os\ext\CMSIS\ST</state>
           <state>$PROJ_DIR$\..\..\..\..\os\rt\ports\ARMCMx</state>
@@ -312,7 +312,7 @@
           <state>$PROJ_DIR$\..\..\..\..\os\hal\include</state>
           <state>$PROJ_DIR$\..\..\..\..\os\hal\boards\ST_STM32F3_DISCOVERY</state>
           <state>$PROJ_DIR$\..\..\..\..\os\hal\ports\common\ARMCMx</state>
-          <state>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\STM32F30x</state>
+          <state>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\STM32F3xx</state>
           <state>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\LLD</state>
           <state>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\LLD\GPIOv2</state>
           <state>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\LLD\I2Cv2</state>
@@ -571,7 +571,7 @@
         <option>
           <name>AUserIncludes</name>
           <state>$PROJ_DIR$\..</state>
-          <state>$PROJ_DIR$\..\..\..\..\os\common\ports\ARMCMx\devices\STM32F30x</state>
+          <state>$PROJ_DIR$\..\..\..\..\os\common\ports\ARMCMx\devices\STM32F3xx</state>
           <state>$PROJ_DIR$\..\..\..\..\os\rt\ports\ARMCMx</state>
         </option>
         <option>
@@ -1256,7 +1256,7 @@
         <option>
           <name>CCIncludePath2</name>
           <state>$PROJ_DIR$\..\</state>
-          <state>$PROJ_DIR$\..\..\..\..\os\common\ports\ARMCMx\devices\STM32F30x</state>
+          <state>$PROJ_DIR$\..\..\..\..\os\common\ports\ARMCMx\devices\STM32F3xx</state>
           <state>$PROJ_DIR$\..\..\..\..\os\ext\CMSIS\include</state>
           <state>$PROJ_DIR$\..\..\..\..\os\ext\CMSIS\ST</state>
           <state>$PROJ_DIR$\..\..\..\..\os\rt\ports\ARMCMx</state>
@@ -1266,7 +1266,7 @@
           <state>$PROJ_DIR$\..\..\..\..\os\hal\include</state>
           <state>$PROJ_DIR$\..\..\..\..\os\hal\boards\ST_STM32F3_DISCOVERY</state>
           <state>$PROJ_DIR$\..\..\..\..\os\hal\ports\common\ARMCMx</state>
-          <state>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\STM32F30x</state>
+          <state>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\STM32F3xx</state>
           <state>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\LLD</state>
           <state>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\LLD\GPIOv2</state>
           <state>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\LLD\I2Cv2</state>
@@ -1525,7 +1525,7 @@
         <option>
           <name>AUserIncludes</name>
           <state>$PROJ_DIR$\..</state>
-          <state>$PROJ_DIR$\..\..\..\..\os\common\ports\ARMCMx\devices\STM32F30x</state>
+          <state>$PROJ_DIR$\..\..\..\..\os\common\ports\ARMCMx\devices\STM32F3xx</state>
           <state>$PROJ_DIR$\..\..\..\..\os\rt\ports\ARMCMx</state>
         </option>
         <option>
@@ -1920,7 +1920,7 @@
       <group>
         <name>ports</name>
         <file>
-          <name>$PROJ_DIR$\..\..\..\..\os\common\ports\ARMCMx\devices\STM32F30x\cmparams.h</name>
+          <name>$PROJ_DIR$\..\..\..\..\os\common\ports\ARMCMx\devices\STM32F3xx\cmparams.h</name>
         </file>
         <file>
           <name>$PROJ_DIR$\..\..\..\..\os\common\ports\ARMCMx\compilers\IAR\cstartup.s</name>
@@ -1947,10 +1947,10 @@
           <name>$PROJ_DIR$\..\..\..\..\os\ext\CMSIS\include\core_cmInstr.h</name>
         </file>
         <file>
-          <name>$PROJ_DIR$\..\..\..\..\os\ext\CMSIS\ST\stm32f30x.h</name>
+          <name>$PROJ_DIR$\..\..\..\..\os\ext\CMSIS\ST\stm32f3xx.h</name>
         </file>
         <file>
-          <name>$PROJ_DIR$\..\..\..\..\os\ext\CMSIS\ST\system_stm32f30x.h</name>
+          <name>$PROJ_DIR$\..\..\..\..\os\ext\CMSIS\ST\system_stm32f3xx.h</name>
         </file>
       </group>
     </group>
@@ -2037,10 +2037,10 @@
       <group>
         <name>port</name>
         <file>
-          <name>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\STM32F30x\adc_lld.c</name>
+          <name>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\STM32F3xx\adc_lld.c</name>
         </file>
         <file>
-          <name>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\STM32F30x\adc_lld.h</name>
+          <name>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\STM32F3xx\adc_lld.h</name>
         </file>
         <file>
           <name>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\LLD\can_lld.c</name>
@@ -2055,10 +2055,10 @@
           <name>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\LLD\ext_lld.h</name>
         </file>
         <file>
-          <name>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\STM32F30x\ext_lld_isr.c</name>
+          <name>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\STM32F3xx\ext_lld_isr.c</name>
         </file>
         <file>
-          <name>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\STM32F30x\ext_lld_isr.h</name>
+          <name>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\STM32F3xx\ext_lld_isr.h</name>
         </file>
         <file>
           <name>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\LLD\TIMv1\gpt_lld.c</name>
@@ -2067,10 +2067,10 @@
           <name>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\LLD\TIMv1\gpt_lld.h</name>
         </file>
         <file>
-          <name>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\STM32F30x\hal_lld.c</name>
+          <name>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\STM32F3xx\hal_lld.c</name>
         </file>
         <file>
-          <name>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\STM32F30x\hal_lld.h</name>
+          <name>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\STM32F3xx\hal_lld.h</name>
         </file>
         <file>
           <name>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\LLD\I2Cv2\i2c_lld.c</name>
@@ -2127,19 +2127,19 @@
           <name>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\LLD\TIMv1\st_lld.h</name>
         </file>
         <file>
-          <name>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\STM32F30x\stm32_dma.c</name>
+          <name>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\STM32F3xx\stm32_dma.c</name>
         </file>
         <file>
-          <name>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\STM32F30x\stm32_dma.h</name>
+          <name>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\STM32F3xx\stm32_dma.h</name>
         </file>
         <file>
-          <name>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\STM32F30x\stm32_isr.h</name>
+          <name>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\STM32F3xx\stm32_isr.h</name>
         </file>
         <file>
-          <name>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\STM32F30x\stm32_rcc.h</name>
+          <name>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\STM32F3xx\stm32_rcc.h</name>
         </file>
         <file>
-          <name>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\STM32F30x\stm32_registry.h</name>
+          <name>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\STM32F3xx\stm32_registry.h</name>
         </file>
         <file>
           <name>$PROJ_DIR$\..\..\..\..\os\hal\ports\STM32\LLD\TIMv1\stm32_tim.h</name>
diff --git a/demos/STM32/RT-STM32F303-DISCOVERY/keil/ch.uvproj b/demos/STM32/RT-STM32F303-DISCOVERY/keil/ch.uvproj
index 9ef19d043..a51f20d30 100644
--- a/demos/STM32/RT-STM32F303-DISCOVERY/keil/ch.uvproj
+++ b/demos/STM32/RT-STM32F303-DISCOVERY/keil/ch.uvproj
@@ -19,7 +19,7 @@
           <StartupFile></StartupFile>
           <FlashDriverDll>UL2CM3(-S0 -C0 -P0 -FD20000000 -FC1000 -FN1 -FF0STM32F3xx_256 -FS08000000 -FL040000 -FP0($$Device:STM32F303VC$Flash\STM32F3xx_256.FLM))</FlashDriverDll>
           <DeviceId>6331</DeviceId>
-          <RegisterFile>$$Device:STM32F303VC$Device\Include\STM32F30x.h</RegisterFile>
+          <RegisterFile>$$Device:STM32F303VC$Device\Include\STM32F3xx.h</RegisterFile>
           <MemoryEnv></MemoryEnv>
           <Cmp></Cmp>
           <Asm></Asm>
@@ -29,7 +29,7 @@
           <SLE66CMisc></SLE66CMisc>
           <SLE66AMisc></SLE66AMisc>
           <SLE66LinkerMisc></SLE66LinkerMisc>
-          <SFDFile>$$Device:STM32F303VC$SVD\STM32F30x.svd</SFDFile>
+          <SFDFile>$$Device:STM32F303VC$SVD\STM32F3xx.svd</SFDFile>
           <bCustSvd>0</bCustSvd>
           <UseEnv>0</UseEnv>
           <BinPath></BinPath>
@@ -357,7 +357,7 @@
               <MiscControls>--c99</MiscControls>
               <Define>CORTEX_USE_FPU=1 __heap_base__=Image$$RW_IRAM1$$ZI$$Limit __heap_end__=Image$$RW_IRAM2$$Base</Define>
               <Undefine></Undefine>
-              <IncludePath>..\;..\..\..\..\os\common\ports\ARMCMx\devices\STM32F30x;..\..\..\..\os\ext\CMSIS\include;..\..\..\..\os\ext\CMSIS\ST;..\..\..\..\os\rt\ports\ARMCMx;..\..\..\..\os\rt\ports\ARMCMx\compilers\RVCT;..\..\..\..\os\rt\include;..\..\..\..\os\hal\osal\rt;..\..\..\..\os\hal\include;..\..\..\..\os\hal\boards\ST_STM32F3_DISCOVERY;..\..\..\..\os\hal\ports\common\ARMCMx;..\..\..\..\os\hal\ports\STM32\STM32F30x;..\..\..\..\os\hal\ports\STM32\LLD;..\..\..\..\os\hal\ports\STM32\LLD\GPIOv2;..\..\..\..\os\hal\ports\STM32\LLD\I2Cv2;..\..\..\..\os\hal\ports\STM32\LLD\RTCv2;..\..\..\..\os\hal\ports\STM32\LLD\SPIv2;..\..\..\..\os\hal\ports\STM32\LLD\TIMv1;..\..\..\..\os\hal\ports\STM32\LLD\USARTv2;..\..\..\..\os\hal\ports\STM32\LLD\USBv1;..\..\..\..\test</IncludePath>
+              <IncludePath>..\;..\..\..\..\os\common\ports\ARMCMx\devices\STM32F3xx;..\..\..\..\os\ext\CMSIS\include;..\..\..\..\os\ext\CMSIS\ST;..\..\..\..\os\rt\ports\ARMCMx;..\..\..\..\os\rt\ports\ARMCMx\compilers\RVCT;..\..\..\..\os\rt\include;..\..\..\..\os\hal\osal\rt;..\..\..\..\os\hal\include;..\..\..\..\os\hal\boards\ST_STM32F3_DISCOVERY;..\..\..\..\os\hal\ports\common\ARMCMx;..\..\..\..\os\hal\ports\STM32\STM32F3xx;..\..\..\..\os\hal\ports\STM32\LLD;..\..\..\..\os\hal\ports\STM32\LLD\GPIOv2;..\..\..\..\os\hal\ports\STM32\LLD\I2Cv2;..\..\..\..\os\hal\ports\STM32\LLD\RTCv2;..\..\..\..\os\hal\ports\STM32\LLD\SPIv2;..\..\..\..\os\hal\ports\STM32\LLD\TIMv1;..\..\..\..\os\hal\ports\STM32\LLD\USARTv2;..\..\..\..\os\hal\ports\STM32\LLD\USBv1;..\..\..\..\test</IncludePath>
             </VariousControls>
           </Cads>
           <Aads>
@@ -373,7 +373,7 @@
               <MiscControls>--cpreproc</MiscControls>
               <Define>CORTEX_USE_FPU=1</Define>
               <Undefine></Undefine>
-              <IncludePath>..\;..\..\..\..\os\common\ports\ARMCMx\devices\STM32F30x;..\..\..\..\os\rt\ports\ARMCMx</IncludePath>
+              <IncludePath>..\;..\..\..\..\os\common\ports\ARMCMx\devices\STM32F3xx;..\..\..\..\os\rt\ports\ARMCMx</IncludePath>
             </VariousControls>
           </Aads>
           <LDads>
@@ -401,7 +401,7 @@
             <File>
               <FileName>cmparams.h</FileName>
               <FileType>5</FileType>
-              <FilePath>..\..\..\..\os\common\ports\ARMCMx\devices\STM32F30x\cmparams.h</FilePath>
+              <FilePath>..\..\..\..\os\common\ports\ARMCMx\devices\STM32F3xx\cmparams.h</FilePath>
             </File>
             <File>
               <FileName>cstartup.s</FileName>
@@ -439,9 +439,9 @@
               <FilePath>..\..\..\..\os\ext\CMSIS\include\core_cmFunc.h</FilePath>
             </File>
             <File>
-              <FileName>system_stm32f30x.h</FileName>
+              <FileName>system_stm32f3xx.h</FileName>
               <FileType>5</FileType>
-              <FilePath>..\..\..\..\os\ext\CMSIS\ST\system_stm32f30x.h</FilePath>
+              <FilePath>..\..\..\..\os\ext\CMSIS\ST\system_stm32f3xx.h</FilePath>
             </File>
           </Files>
         </Group>
@@ -716,57 +716,57 @@
             <File>
               <FileName>adc_lld.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\..\os\hal\ports\STM32\STM32F30x\adc_lld.c</FilePath>
+              <FilePath>..\..\..\..\os\hal\ports\STM32\STM32F3xx\adc_lld.c</FilePath>
             </File>
             <File>
               <FileName>adc_lld.h</FileName>
               <FileType>5</FileType>
-              <FilePath>..\..\..\..\os\hal\ports\STM32\STM32F30x\adc_lld.h</FilePath>
+              <FilePath>..\..\..\..\os\hal\ports\STM32\STM32F3xx\adc_lld.h</FilePath>
             </File>
             <File>
               <FileName>ext_lld_isr.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\..\os\hal\ports\STM32\STM32F30x\ext_lld_isr.c</FilePath>
+              <FilePath>..\..\..\..\os\hal\ports\STM32\STM32F3xx\ext_lld_isr.c</FilePath>
             </File>
             <File>
               <FileName>ext_lld_isr.h</FileName>
               <FileType>5</FileType>
-              <FilePath>..\..\..\..\os\hal\ports\STM32\STM32F30x\ext_lld_isr.h</FilePath>
+              <FilePath>..\..\..\..\os\hal\ports\STM32\STM32F3xx\ext_lld_isr.h</FilePath>
             </File>
             <File>
               <FileName>hal_lld.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\..\os\hal\ports\STM32\STM32F30x\hal_lld.c</FilePath>
+              <FilePath>..\..\..\..\os\hal\ports\STM32\STM32F3xx\hal_lld.c</FilePath>
             </File>
             <File>
               <FileName>hal_lld.h</FileName>
               <FileType>5</FileType>
-              <FilePath>..\..\..\..\os\hal\ports\STM32\STM32F30x\hal_lld.h</FilePath>
+              <FilePath>..\..\..\..\os\hal\ports\STM32\STM32F3xx\hal_lld.h</FilePath>
             </File>
             <File>
               <FileName>stm32_dma.c</FileName>
               <FileType>1</FileType>
-              <FilePath>..\..\..\..\os\hal\ports\STM32\STM32F30x\stm32_dma.c</FilePath>
+              <FilePath>..\..\..\..\os\hal\ports\STM32\STM32F3xx\stm32_dma.c</FilePath>
             </File>
             <File>
               <FileName>stm32_dma.h</FileName>
               <FileType>5</FileType>
-              <FilePath>..\..\..\..\os\hal\ports\STM32\STM32F30x\stm32_dma.h</FilePath>
+              <FilePath>..\..\..\..\os\hal\ports\STM32\STM32F3xx\stm32_dma.h</FilePath>
             </File>
             <File>
               <FileName>stm32_isr.h</FileName>
               <FileType>5</FileType>
-              <FilePath>..\..\..\..\os\hal\ports\STM32\STM32F30x\stm32_isr.h</FilePath>
+              <FilePath>..\..\..\..\os\hal\ports\STM32\STM32F3xx\stm32_isr.h</FilePath>
             </File>
             <File>
               <FileName>stm32_rcc.h</FileName>
               <FileType>5</FileType>
-              <FilePath>..\..\..\..\os\hal\ports\STM32\STM32F30x\stm32_rcc.h</FilePath>
+              <FilePath>..\..\..\..\os\hal\ports\STM32\STM32F3xx\stm32_rcc.h</FilePath>
             </File>
             <File>
               <FileName>stm32_registry.h</FileName>
               <FileType>5</FileType>
-              <FilePath>..\..\..\..\os\hal\ports\STM32\STM32F30x\stm32_registry.h</FilePath>
+              <FilePath>..\..\..\..\os\hal\ports\STM32\STM32F3xx\stm32_registry.h</FilePath>
             </File>
             <File>
               <FileName>can_lld.c</FileName>
diff --git a/demos/STM32/RT-STM32F303-DISCOVERY/mcuconf.h b/demos/STM32/RT-STM32F303-DISCOVERY/mcuconf.h
index 28b5e1351..131092493 100644
--- a/demos/STM32/RT-STM32F303-DISCOVERY/mcuconf.h
+++ b/demos/STM32/RT-STM32F303-DISCOVERY/mcuconf.h
@@ -15,7 +15,7 @@
 */
 
 /*
- * STM32F30x drivers configuration.
+ * STM32F3xx drivers configuration.
  * The following settings override the default settings present in
  * the various device driver implementation headers.
  * Note that the settings for each driver only have effect if the whole
@@ -28,7 +28,7 @@
  * 0...3        Lowest...Highest.
  */
 
-#define STM32F30x_MCUCONF
+#define STM32F3xx_MCUCONF
 
 /*
  * HAL driver system settings.
diff --git a/demos/STM32/RT-STM32F373-STM32373C_EVAL/Makefile b/demos/STM32/RT-STM32F373-STM32373C_EVAL/Makefile
index 37ed37def..bafcc1f1c 100644
--- a/demos/STM32/RT-STM32F373-STM32373C_EVAL/Makefile
+++ b/demos/STM32/RT-STM32F373-STM32373C_EVAL/Makefile
@@ -86,7 +86,7 @@ include $(CHIBIOS)/os/hal/boards/ST_STM32373C_EVAL/board.mk
 include $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/platform.mk
 include $(CHIBIOS)/os/hal/osal/rt/osal.mk
 include $(CHIBIOS)/os/rt/rt.mk
-include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f37x.mk
+include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f3xx.mk
 include $(CHIBIOS)/test/rt/test.mk
 
 # Define linker script file here
diff --git a/os/common/ports/ARMCMx/devices/STM32F30x/cmparams.h b/os/common/ports/ARMCMx/devices/STM32F30x/cmparams.h
deleted file mode 100644
index 526453f99..000000000
--- a/os/common/ports/ARMCMx/devices/STM32F30x/cmparams.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
-    ChibiOS - Copyright (C) 2006,2007,2008,2009,2010,
-              2011,2012,2013,2014 Giovanni Di Sirio.
-
-    This file is part of ChibiOS.
-
-    ChibiOS is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    STM32F3xx/cmparams.h
- * @brief   ARM Cortex-M4 parameters for the STM32F3xx.
- *
- * @defgroup ARMCMx_STM32F3xx STM32F3xx Specific Parameters
- * @ingroup ARMCMx_SPECIFIC
- * @details This file contains the Cortex-M4 specific parameters for the
- *          STM32F3xx platform.
- * @{
- */
-
-#ifndef _CMPARAMS_H_
-#define _CMPARAMS_H_
-
-/**
- * @brief   Cortex core model.
- */
-#define CORTEX_MODEL            CORTEX_M4
-
-/**
- * @brief   Floating Point unit presence.
- */
-#define CORTEX_HAS_FPU          1
-
-/**
- * @brief   Number of bits in priority masks.
- */
-#define CORTEX_PRIORITY_BITS    4
-
-/**
- * @brief   Number of interrupt vectors.
- * @note    This number does not include the 16 system vectors and must be
- *          rounded to a multiple of 8.
- */
-#define CORTEX_NUM_VECTORS      88
-
-/* The following code is not processed when the file is included from an
-   asm module.*/
-#if !defined(_FROM_ASM_)
-
-/* If the device type is not externally defined, for example from the Makefile,
-   then a file named board.h is included. This file must contain a device
-   definition compatible with the vendor include file.*/
-#if !defined (STM32F301x8) && !defined (STM32F318xx) &&                     \
-    !defined (STM32F302x8) && !defined (STM32F302xC) &&                     \
-    !defined (STM32F303x8) && !defined (STM32F303xC) &&                     \
-    !defined (STM32F358xx) && !defined (STM32F334x8) &&                     \
-    !defined (STM32F328xx) &&                                               \
-    !defined (STM32F373xC) && !defined (STM32F378xx)
-#include "board.h"
-#endif
-
-/* Including the device CMSIS header. Note, we are not using the definitions
-   from this header because we need this file to be usable also from
-   assembler source files. We verify that the info matches instead.*/
-#include "stm32f3xx.h"
-
-#if !CORTEX_HAS_FPU != !__FPU_PRESENT
-#error "CMSIS __FPU_PRESENT mismatch"
-#endif
-
-#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
-#error "CMSIS __NVIC_PRIO_BITS mismatch"
-#endif
-
-#endif /* !defined(_FROM_ASM_) */
-
-#endif /* _CMPARAMS_H_ */
-
-/** @} */
diff --git a/os/common/ports/ARMCMx/devices/STM32F37x/cmparams.h b/os/common/ports/ARMCMx/devices/STM32F37x/cmparams.h
deleted file mode 100644
index a877c1bd4..000000000
--- a/os/common/ports/ARMCMx/devices/STM32F37x/cmparams.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
-    ChibiOS - Copyright (C) 2006,2007,2008,2009,2010,
-              2011,2012,2013,2014 Giovanni Di Sirio.
-
-    This file is part of ChibiOS.
-
-    ChibiOS is free software; you can redistribute it and/or modify
-    it under the terms of the GNU General Public License as published by
-    the Free Software Foundation; either version 3 of the License, or
-    (at your option) any later version.
-
-    ChibiOS is distributed in the hope that it will be useful,
-    but WITHOUT ANY WARRANTY; without even the implied warranty of
-    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    GNU General Public License for more details.
-
-    You should have received a copy of the GNU General Public License
-    along with this program.  If not, see <http://www.gnu.org/licenses/>.
-*/
-
-/**
- * @file    STM32F37x/cmparams.h
- * @brief   ARM Cortex-M4 parameters for the STM32F37x.
- *
- * @defgroup ARMCMx_STM32F37x STM32F37x Specific Parameters
- * @ingroup ARMCMx_SPECIFIC
- * @details This file contains the Cortex-M4 specific parameters for the
- *          STM32F37x platform.
- * @{
- */
-
-#ifndef _CMPARAMS_H_
-#define _CMPARAMS_H_
-
-/**
- * @brief   Cortex core model.
- */
-#define CORTEX_MODEL            CORTEX_M4
-
-/**
- * @brief   Floating Point unit presence.
- */
-#define CORTEX_HAS_FPU          1
-
-/**
- * @brief   Number of bits in priority masks.
- */
-#define CORTEX_PRIORITY_BITS    4
-
-/**
- * @brief   Number of interrupt vectors.
- * @note    This number does not include the 16 system vectors and must be
- *          rounded to a multiple of 8.
- */
-#define CORTEX_NUM_VECTORS      88
-
-/* The following code is not processed when the file is included from an
-   asm module.*/
-#if !defined(_FROM_ASM_)
-
-/* If the device type is not externally defined, for example from the Makefile,
-   then a file named board.h is included. This file must contain a device
-   definition compatible with the vendor include file.*/
-#if !defined (STM32F373xC) && !defined (STM32F378xx)
-#include "board.h"
-#endif
-
-/* Including the device CMSIS header. Note, we are not using the definitions
-   from this header because we need this file to be usable also from
-   assembler source files. We verify that the info matches instead.*/
-#include "stm32f3xx.h"
-
-#if !CORTEX_HAS_FPU != !__FPU_PRESENT
-#error "CMSIS __FPU_PRESENT mismatch"
-#endif
-
-#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
-#error "CMSIS __NVIC_PRIO_BITS mismatch"
-#endif
-
-#endif /* !defined(_FROM_ASM_) */
-
-#endif /* _CMPARAMS_H_ */
-
-/** @} */
diff --git a/os/common/ports/ARMCMx/devices/STM32F3xx/cmparams.h b/os/common/ports/ARMCMx/devices/STM32F3xx/cmparams.h
new file mode 100644
index 000000000..526453f99
--- /dev/null
+++ b/os/common/ports/ARMCMx/devices/STM32F3xx/cmparams.h
@@ -0,0 +1,90 @@
+/*
+    ChibiOS - Copyright (C) 2006,2007,2008,2009,2010,
+              2011,2012,2013,2014 Giovanni Di Sirio.
+
+    This file is part of ChibiOS.
+
+    ChibiOS is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    STM32F3xx/cmparams.h
+ * @brief   ARM Cortex-M4 parameters for the STM32F3xx.
+ *
+ * @defgroup ARMCMx_STM32F3xx STM32F3xx Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M4 specific parameters for the
+ *          STM32F3xx platform.
+ * @{
+ */
+
+#ifndef _CMPARAMS_H_
+#define _CMPARAMS_H_
+
+/**
+ * @brief   Cortex core model.
+ */
+#define CORTEX_MODEL            CORTEX_M4
+
+/**
+ * @brief   Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU          1
+
+/**
+ * @brief   Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS    4
+
+/**
+ * @brief   Number of interrupt vectors.
+ * @note    This number does not include the 16 system vectors and must be
+ *          rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS      88
+
+/* The following code is not processed when the file is included from an
+   asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* If the device type is not externally defined, for example from the Makefile,
+   then a file named board.h is included. This file must contain a device
+   definition compatible with the vendor include file.*/
+#if !defined (STM32F301x8) && !defined (STM32F318xx) &&                     \
+    !defined (STM32F302x8) && !defined (STM32F302xC) &&                     \
+    !defined (STM32F303x8) && !defined (STM32F303xC) &&                     \
+    !defined (STM32F358xx) && !defined (STM32F334x8) &&                     \
+    !defined (STM32F328xx) &&                                               \
+    !defined (STM32F373xC) && !defined (STM32F378xx)
+#include "board.h"
+#endif
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+   from this header because we need this file to be usable also from
+   assembler source files. We verify that the info matches instead.*/
+#include "stm32f3xx.h"
+
+#if !CORTEX_HAS_FPU != !__FPU_PRESENT
+#error "CMSIS __FPU_PRESENT mismatch"
+#endif
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* _CMPARAMS_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F30x/adc_lld.c b/os/hal/ports/STM32/STM32F30x/adc_lld.c
deleted file mode 100644
index 2e875f169..000000000
--- a/os/hal/ports/STM32/STM32F30x/adc_lld.c
+++ /dev/null
@@ -1,548 +0,0 @@
-/*
-    ChibiOS/HAL - Copyright (C) 2006-2014 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F30x/adc_lld.c
- * @brief   STM32F30x ADC subsystem low level driver source.
- *
- * @addtogroup ADC
- * @{
- */
-
-#include "hal.h"
-
-#if HAL_USE_ADC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-#if STM32_ADC_DUAL_MODE
-#if STM32_ADC_COMPACT_SAMPLES
-/* Compact type dual mode.*/
-#define ADC_DMA_SIZE    (STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD)
-#define ADC_DMA_MDMA    ADC_CCR_MDMA_HWORD
-
-#else /* !STM32_ADC_COMPACT_SAMPLES */
-/* Large type dual mode.*/
-#define ADC_DMA_SIZE    (STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_PSIZE_WORD)
-#define ADC_DMA_MDMA    ADC_CCR_MDMA_WORD
-#endif /* !STM32_ADC_COMPACT_SAMPLES */
-
-#else /* !STM32_ADC_DUAL_MODE */
-#if STM32_ADC_COMPACT_SAMPLES
-/* Compact type single mode.*/
-#define ADC_DMA_SIZE    (STM32_DMA_CR_MSIZE_BYTE | STM32_DMA_CR_PSIZE_BYTE)
-#define ADC_DMA_MDMA    ADC_CCR_MDMA_DISABLED
-
-#else /* !STM32_ADC_COMPACT_SAMPLES */
-/* Large type single mode.*/
-#define ADC_DMA_SIZE    (STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD)
-#define ADC_DMA_MDMA    ADC_CCR_MDMA_DISABLED
-#endif /* !STM32_ADC_COMPACT_SAMPLES */
-#endif /* !STM32_ADC_DUAL_MODE */
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/** @brief ADC1 driver identifier.*/
-#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
-ADCDriver ADCD1;
-#endif
-
-/** @brief ADC1 driver identifier.*/
-#if STM32_ADC_USE_ADC3 || defined(__DOXYGEN__)
-ADCDriver ADCD3;
-#endif
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Enables the ADC voltage regulator.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- */
-static void adc_lld_vreg_on(ADCDriver *adcp) {
-
-  adcp->adcm->CR = 0;   /* RM 12.4.3.*/
-  adcp->adcm->CR = ADC_CR_ADVREGEN_0;
-#if STM32_ADC_DUAL_MODE
-  adcp->adcs->CR = ADC_CR_ADVREGEN_0;
-#endif
-  osalSysPolledDelayX(US2RTC(STM32_HCLK, 10));
-}
-
-/**
- * @brief   Disables the ADC voltage regulator.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- */
-static void adc_lld_vreg_off(ADCDriver *adcp) {
-
-  adcp->adcm->CR = 0;   /* RM 12.4.3.*/
-  adcp->adcm->CR = ADC_CR_ADVREGEN_1;
-#if STM32_ADC_DUAL_MODE
-  adcp->adcs->CR = ADC_CR_ADVREGEN_1;
-#endif
-}
-
-/**
- * @brief   Enables the ADC analog circuit.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- */
-static void adc_lld_analog_on(ADCDriver *adcp) {
-
-  adcp->adcm->CR |= ADC_CR_ADEN;
-  while ((adcp->adcm->ISR & ADC_ISR_ADRD) == 0)
-    ;
-#if STM32_ADC_DUAL_MODE
-  adcp->adcs->CR |= ADC_CR_ADEN;
-  while ((adcp->adcs->ISR & ADC_ISR_ADRD) == 0)
-    ;
-#endif
-}
-
-/**
- * @brief   Disables the ADC  analog circuit.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- */
-static void adc_lld_analog_off(ADCDriver *adcp) {
-
-  adcp->adcm->CR |= ADC_CR_ADDIS;
-  while ((adcp->adcm->CR & ADC_CR_ADDIS) != 0)
-    ;
-#if STM32_ADC_DUAL_MODE
-  adcp->adcs->CR |= ADC_CR_ADDIS;
-  while ((adcp->adcs->CR & ADC_CR_ADDIS) != 0)
-    ;
-#endif
-}
-
-/**
- * @brief   Calibrates and ADC unit.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- */
-static void adc_lld_calibrate(ADCDriver *adcp) {
-
-  osalDbgAssert(adcp->adcm->CR == ADC_CR_ADVREGEN_0, "invalid register state");
-  adcp->adcm->CR |= ADC_CR_ADCAL;
-  while ((adcp->adcm->CR & ADC_CR_ADCAL) != 0)
-    ;
-#if STM32_ADC_DUAL_MODE
-  osalDbgAssert(adcp->adcs->CR == ADC_CR_ADVREGEN_0, "invalid register state");
-  adcp->adcs->CR |= ADC_CR_ADCAL;
-  while ((adcp->adcs->CR & ADC_CR_ADCAL) != 0)
-    ;
-#endif
-}
-
-/**
- * @brief   Stops an ongoing conversion, if any.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- */
-static void adc_lld_stop_adc(ADCDriver *adcp) {
-
-  if (adcp->adcm->CR & ADC_CR_ADSTART) {
-    adcp->adcm->CR |= ADC_CR_ADSTP;
-    while (adcp->adcm->CR & ADC_CR_ADSTP)
-      ;
-  }
-}
-
-/**
- * @brief   ADC DMA ISR service routine.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- * @param[in] flags     pre-shifted content of the ISR register
- */
-static void adc_lld_serve_dma_interrupt(ADCDriver *adcp, uint32_t flags) {
-
-  /* DMA errors handling.*/
-  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
-    /* DMA, this could help only if the DMA tries to access an unmapped
-       address space or violates alignment rules.*/
-    _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
-  }
-  else {
-    /* It is possible that the conversion group has already be reset by the
-       ADC error handler, in this case this interrupt is spurious.*/
-    if (adcp->grpp != NULL) {
-      if ((flags & STM32_DMA_ISR_TCIF) != 0) {
-        /* Transfer complete processing.*/
-        _adc_isr_full_code(adcp);
-      }
-      else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
-        /* Half transfer processing.*/
-        _adc_isr_half_code(adcp);
-      }
-    }
-  }
-}
-
-/**
- * @brief   ADC ISR service routine.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- * @param[in] isr       content of the ISR register
- */
-static void adc_lld_serve_interrupt(ADCDriver *adcp, uint32_t isr) {
-
-  /* It could be a spurious interrupt caused by overflows after DMA disabling,
-     just ignore it in this case.*/
-  if (adcp->grpp != NULL) {
-    /* Note, an overflow may occur after the conversion ended before the driver
-       is able to stop the ADC, this is why the DMA channel is checked too.*/
-    if ((isr & ADC_ISR_OVR) &&
-        (dmaStreamGetTransactionSize(adcp->dmastp) > 0)) {
-      /* ADC overflow condition, this could happen only if the DMA is unable
-         to read data fast enough.*/
-      _adc_isr_error_code(adcp, ADC_ERR_OVERFLOW);
-    }
-    if (isr & ADC_ISR_AWD1) {
-      /* Analog watchdog error.*/
-      _adc_isr_error_code(adcp, ADC_ERR_AWD1);
-    }
-    if (isr & ADC_ISR_AWD2) {
-      /* Analog watchdog error.*/
-      _adc_isr_error_code(adcp, ADC_ERR_AWD2);
-    }
-    if (isr & ADC_ISR_AWD3) {
-      /* Analog watchdog error.*/
-      _adc_isr_error_code(adcp, ADC_ERR_AWD3);
-    }
-  }
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
-/**
- * @brief   ADC1/ADC2 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector88) {
-  uint32_t isr;
-
-  OSAL_IRQ_PROLOGUE();
-
-#if STM32_ADC_DUAL_MODE
-  isr  = ADC1->ISR;
-  isr |= ADC2->ISR;
-  ADC1->ISR = isr;
-  ADC2->ISR = isr;
-#else /* !STM32_ADC_DUAL_MODE */
-  isr  = ADC1->ISR;
-  ADC1->ISR = isr;
-#endif /* !STM32_ADC_DUAL_MODE */
-
-  adc_lld_serve_interrupt(&ADCD1, isr);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif /* STM32_ADC_USE_ADC1 */
-
-#if STM32_ADC_USE_ADC3 || defined(__DOXYGEN__)
-/**
- * @brief   ADC3 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(VectorFC) {
-  uint32_t isr;
-
-  OSAL_IRQ_PROLOGUE();
-
-  isr  = ADC3->ISR;
-  ADC3->ISR = isr;
-
-  adc_lld_serve_interrupt(&ADCD3, isr);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-#if STM32_ADC_DUAL_MODE
-/**
- * @brief   ADC4 interrupt handler (as ADC3 slave).
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector134) {
-  uint32_t isr;
-
-  OSAL_IRQ_PROLOGUE();
-
-  isr  = ADC4->ISR;
-  ADC4->ISR = isr;
-
-  adc_lld_serve_interrupt(&ADCD3, isr);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif /* STM32_ADC_DUAL_MODE */
-#endif /* STM32_ADC_USE_ADC3 */
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level ADC driver initialization.
- *
- * @notapi
- */
-void adc_lld_init(void) {
-
-#if STM32_ADC_USE_ADC1
-  /* Driver initialization.*/
-  adcObjectInit(&ADCD1);
-  ADCD1.adcc = ADC1_2_COMMON;
-  ADCD1.adcm = ADC1;
-#if STM32_ADC_DUAL_MODE
-  ADCD1.adcs = ADC2;
-#endif
-  ADCD1.dmastp  = STM32_DMA1_STREAM1;
-  ADCD1.dmamode = ADC_DMA_SIZE |
-                  STM32_DMA_CR_PL(STM32_ADC_ADC12_DMA_PRIORITY) |
-                  STM32_DMA_CR_DIR_P2M |
-                  STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |
-                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;
-  nvicEnableVector(ADC1_2_IRQn, STM32_ADC_ADC12_IRQ_PRIORITY);
-#endif /* STM32_ADC_USE_ADC1 */
-
-#if STM32_ADC_USE_ADC3
-  /* Driver initialization.*/
-  adcObjectInit(&ADCD3);
-  ADCD3.adcc = ADC3_4_COMMON;
-  ADCD3.adcm = ADC3;
-#if STM32_ADC_DUAL_MODE
-  ADCD3.adcs = ADC4;
-#endif
-  ADCD3.dmastp  = STM32_DMA2_STREAM5;
-  ADCD3.dmamode = ADC_DMA_SIZE |
-                  STM32_DMA_CR_PL(STM32_ADC_ADC12_DMA_PRIORITY) |
-                  STM32_DMA_CR_DIR_P2M |
-                  STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |
-                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;
-  nvicEnableVector(ADC3_IRQn, STM32_ADC_ADC34_IRQ_PRIORITY);
-#if STM32_ADC_DUAL_MODE
-  nvicEnableVector(ADC4_IRQn, STM32_ADC_ADC34_IRQ_PRIORITY);
-#endif
-#endif /* STM32_ADC_USE_ADC3 */
-}
-
-/**
- * @brief   Configures and activates the ADC peripheral.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_start(ADCDriver *adcp) {
-
-  /* If in stopped state then enables the ADC and DMA clocks.*/
-  if (adcp->state == ADC_STOP) {
-#if STM32_ADC_USE_ADC1
-    if (&ADCD1 == adcp) {
-      bool b;
-      b = dmaStreamAllocate(adcp->dmastp,
-                            STM32_ADC_ADC12_DMA_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
-                            (void *)adcp);
-      osalDbgAssert(!b, "stream already allocated");
-      rccEnableADC12(FALSE);
-    }
-#endif /* STM32_ADC_USE_ADC1 */
-
-#if STM32_ADC_USE_ADC3
-    if (&ADCD3 == adcp) {
-      bool b;
-      b = dmaStreamAllocate(adcp->dmastp,
-                            STM32_ADC_ADC34_DMA_IRQ_PRIORITY,
-                            (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
-                            (void *)adcp);
-      osalDbgAssert(!b, "stream already allocated");
-      rccEnableADC34(FALSE);
-    }
-#endif /* STM32_ADC_USE_ADC2 */
-
-    /* Setting DMA peripheral-side pointer.*/
-#if STM32_ADC_DUAL_MODE
-      dmaStreamSetPeripheral(adcp->dmastp, &adcp->adcc->CDR);
-#else
-      dmaStreamSetPeripheral(adcp->dmastp, &adcp->adcm->DR);
-#endif
-
-    /* Clock source setting.*/
-    adcp->adcc->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;
-
-    /* Master ADC calibration.*/
-    adc_lld_vreg_on(adcp);
-    adc_lld_calibrate(adcp);
-
-    /* Master ADC enabled here in order to reduce conversions latencies.*/
-    adc_lld_analog_on(adcp);
-  }
-}
-
-/**
- * @brief   Deactivates the ADC peripheral.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_stop(ADCDriver *adcp) {
-
-  /* If in ready state then disables the ADC clock and analog part.*/
-  if (adcp->state == ADC_READY) {
-
-    /* Releasing the associated DMA channel.*/
-    dmaStreamRelease(adcp->dmastp);
-
-    /* Stopping the ongoing conversion, if any.*/
-    adc_lld_stop_adc(adcp);
-
-    /* Disabling ADC analog circuit and regulator.*/
-    adc_lld_analog_off(adcp);
-    adc_lld_vreg_off(adcp);
-
-#if STM32_ADC_USE_ADC1
-    if (&ADCD1 == adcp)
-      rccDisableADC12(FALSE);
-#endif
-
-#if STM32_ADC_USE_ADC3
-    if (&ADCD3 == adcp)
-      rccDisableADC34(FALSE);
-#endif
-  }
-}
-
-/**
- * @brief   Starts an ADC conversion.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_start_conversion(ADCDriver *adcp) {
-  uint32_t dmamode, ccr, cfgr;
-  const ADCConversionGroup *grpp = adcp->grpp;
-
-  osalDbgAssert(!STM32_ADC_DUAL_MODE || ((grpp->num_channels & 1) == 0),
-                "odd number of channels in dual mode");
-
-  /* Calculating control registers values.*/
-  dmamode = adcp->dmamode;
-  ccr     = grpp->ccr | (adcp->adcc->CCR & (ADC_CCR_CKMODE_MASK |
-                                            ADC_CCR_MDMA_MASK));
-  cfgr    = grpp->cfgr | ADC_CFGR_DMAEN;
-  if (grpp->circular) {
-    dmamode |= STM32_DMA_CR_CIRC;
-#if STM32_ADC_DUAL_MODE
-    ccr  |= ADC_CCR_DMACFG_CIRCULAR;
-#else
-    cfgr |= ADC_CFGR_DMACFG_CIRCULAR;
-#endif
-    if (adcp->depth > 1) {
-      /* If circular buffer depth > 1, then the half transfer interrupt
-         is enabled in order to allow streaming processing.*/
-      dmamode |= STM32_DMA_CR_HTIE;
-    }
-  }
-
-  /* DMA setup.*/
-  dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
-#if STM32_ADC_DUAL_MODE
-  dmaStreamSetTransactionSize(adcp->dmastp, ((uint32_t)grpp->num_channels/2) *
-                                            (uint32_t)adcp->depth);
-#else
-    dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
-                                              (uint32_t)adcp->depth);
-#endif
-  dmaStreamSetMode(adcp->dmastp, dmamode);
-  dmaStreamEnable(adcp->dmastp);
-
-  /* Configuring the CCR register with the static settings ORed with
-     the user-specified settings in the conversion group configuration
-     structure.*/
-  adcp->adcc->CCR   = ccr;
-
-  /* ADC setup, if it is defined a callback for the analog watch dog then it
-     is enabled.*/
-  adcp->adcm->ISR   = adcp->adcm->ISR;
-  adcp->adcm->IER   = ADC_IER_OVR | ADC_IER_AWD1;
-  adcp->adcm->TR1   = grpp->tr1;
-#if STM32_ADC_DUAL_MODE
-  adcp->adcm->SMPR1 = grpp->smpr[0];
-  adcp->adcm->SMPR2 = grpp->smpr[1];
-  adcp->adcm->SQR1  = grpp->sqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels / 2);
-  adcp->adcm->SQR2  = grpp->sqr[1];
-  adcp->adcm->SQR3  = grpp->sqr[2];
-  adcp->adcm->SQR4  = grpp->sqr[3];
-  adcp->adcs->SMPR1 = grpp->ssmpr[0];
-  adcp->adcs->SMPR2 = grpp->ssmpr[1];
-  adcp->adcs->SQR1  = grpp->ssqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels / 2);
-  adcp->adcs->SQR2  = grpp->ssqr[1];
-  adcp->adcs->SQR3  = grpp->ssqr[2];
-  adcp->adcs->SQR4  = grpp->ssqr[3];
-
-#else /* !STM32_ADC_DUAL_MODE */
-  adcp->adcm->SMPR1 = grpp->smpr[0];
-  adcp->adcm->SMPR2 = grpp->smpr[1];
-  adcp->adcm->SQR1  = grpp->sqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels);
-  adcp->adcm->SQR2  = grpp->sqr[1];
-  adcp->adcm->SQR3  = grpp->sqr[2];
-  adcp->adcm->SQR4  = grpp->sqr[3];
-#endif /* !STM32_ADC_DUAL_MODE */
-
-  /* ADC configuration.*/
-  adcp->adcm->CFGR  = cfgr;
-
-  /* Starting conversion.*/
-  adcp->adcm->CR   |= ADC_CR_ADSTART;
-}
-
-/**
- * @brief   Stops an ongoing conversion.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object
- *
- * @notapi
- */
-void adc_lld_stop_conversion(ADCDriver *adcp) {
-
-  dmaStreamDisable(adcp->dmastp);
-  adc_lld_stop_adc(adcp);
-}
-
-#endif /* HAL_USE_ADC */
-
-/** @} */
diff --git a/os/hal/ports/STM32/STM32F30x/adc_lld.h b/os/hal/ports/STM32/STM32F30x/adc_lld.h
deleted file mode 100644
index bc8a7c25b..000000000
--- a/os/hal/ports/STM32/STM32F30x/adc_lld.h
+++ /dev/null
@@ -1,619 +0,0 @@
-/*
-    ChibiOS/HAL - Copyright (C) 2006-2014 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F30x/adc_lld.h
- * @brief   STM32F30x ADC subsystem low level driver header.
- *
- * @addtogroup ADC
- * @{
- */
-
-#ifndef _ADC_LLD_H_
-#define _ADC_LLD_H_
-
-#if HAL_USE_ADC || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @name    Available analog channels
- * @{
- */
-#define ADC_CHANNEL_IN1         1   /**< @brief External analog input 1.    */
-#define ADC_CHANNEL_IN2         2   /**< @brief External analog input 2.    */
-#define ADC_CHANNEL_IN3         3   /**< @brief External analog input 3.    */
-#define ADC_CHANNEL_IN4         4   /**< @brief External analog input 4.    */
-#define ADC_CHANNEL_IN5         5   /**< @brief External analog input 5.    */
-#define ADC_CHANNEL_IN6         6   /**< @brief External analog input 6.    */
-#define ADC_CHANNEL_IN7         7   /**< @brief External analog input 7.    */
-#define ADC_CHANNEL_IN8         8   /**< @brief External analog input 8.    */
-#define ADC_CHANNEL_IN9         9   /**< @brief External analog input 9.    */
-#define ADC_CHANNEL_IN10        10  /**< @brief External analog input 10.   */
-#define ADC_CHANNEL_IN11        11  /**< @brief External analog input 11.   */
-#define ADC_CHANNEL_IN12        12  /**< @brief External analog input 12.   */
-#define ADC_CHANNEL_IN13        13  /**< @brief External analog input 13.   */
-#define ADC_CHANNEL_IN14        14  /**< @brief External analog input 14.   */
-#define ADC_CHANNEL_IN15        15  /**< @brief External analog input 15.   */
-#define ADC_CHANNEL_IN16        16  /**< @brief External analog input 16.   */
-#define ADC_CHANNEL_IN17        17  /**< @brief External analog input 17.   */
-#define ADC_CHANNEL_IN18        18  /**< @brief External analog input 18.   */
-/** @} */
-
-/**
- * @name    Sampling rates
- * @{
- */
-#define ADC_SMPR_SMP_1P5        0   /**< @brief 14 cycles conversion time   */
-#define ADC_SMPR_SMP_2P5        1   /**< @brief 15 cycles conversion time.  */
-#define ADC_SMPR_SMP_4P5        2   /**< @brief 17 cycles conversion time.  */
-#define ADC_SMPR_SMP_7P5        3   /**< @brief 20 cycles conversion time.  */
-#define ADC_SMPR_SMP_19P5       4   /**< @brief 32 cycles conversion time.  */
-#define ADC_SMPR_SMP_61P5       5   /**< @brief 74 cycles conversion time.  */
-#define ADC_SMPR_SMP_181P5      6   /**< @brief 194 cycles conversion time. */
-#define ADC_SMPR_SMP_601P5      7   /**< @brief 614 cycles conversion time. */
-/** @} */
-
-/**
- * @name    Resolution
- * @{
- */
-#define ADC_CFGR1_RES_12BIT     (0 << 3)
-#define ADC_CFGR1_RES_10BIT     (1 << 3)
-#define ADC_CFGR1_RES_8BIT      (2 << 3)
-#define ADC_CFGR1_RES_6BIT      (3 << 3)
-/** @} */
-
-/**
- * @name    CFGR register configuration helpers
- * @{
- */
-#define ADC_CFGR_DMACFG_MASK            (1 << 1)
-#define ADC_CFGR_DMACFG_ONESHOT         (0 << 1)
-#define ADC_CFGR_DMACFG_CIRCULAR        (1 << 1)
-
-#define ADC_CFGR_RES_MASK               (3 << 3)
-#define ADC_CFGR_RES_12BITS             (0 << 3)
-#define ADC_CFGR_RES_10BITS             (1 << 3)
-#define ADC_CFGR_RES_8BITS              (2 << 3)
-#define ADC_CFGR_RES_6BITS              (3 << 3)
-
-#define ADC_CFGR_ALIGN_MASK             (1 << 5)
-#define ADC_CFGR_ALIGN_RIGHT            (0 << 5)
-#define ADC_CFGR_ALIGN_LEFT             (1 << 5)
-
-#define ADC_CFGR_EXTSEL_MASK            (15 << 6)
-#define ADC_CFGR_EXTSEL_SRC(n)          ((n) << 6)
-
-#define ADC_CFGR_EXTEN_MASK             (3 << 10)
-#define ADC_CFGR_EXTEN_DISABLED         (0 << 10)
-#define ADC_CFGR_EXTEN_RISING           (1 << 10)
-#define ADC_CFGR_EXTEN_FALLING          (2 << 10)
-#define ADC_CFGR_EXTEN_BOTH             (3 << 10)
-
-#define ADC_CFGR_DISCEN_MASK            (1 << 16)
-#define ADC_CFGR_DISCEN_DISABLED        (0 << 16)
-#define ADC_CFGR_DISCEN_ENABLED         (1 << 16)
-
-#define ADC_CFGR_DISCNUM_MASK           (7 << 17)
-#define ADC_CFGR_DISCNUM_VAL(n)         ((n) << 17)
-
-#define ADC_CFGR_AWD1_DISABLED          0
-#define ADC_CFGR_AWD1_ALL               (1 << 23)
-#define ADC_CFGR_AWD1_SINGLE(n)         (((n) << 26) | (1 << 23) | (1 << 22))
-/** @} */
-
-/**
- * @name    CCR register configuration helpers
- * @{
- */
-#define ADC_CCR_DUAL_MASK               (31 << 0)
-#define ADC_CCR_DUAL(n)                 ((n) << 0)
-#define ADC_CCR_DELAY_MASK              (15 << 8)
-#define ADC_CCR_DELAY(n)                ((n) << 8)
-#define ADC_CCR_DMACFG_MASK             (1 << 13)
-#define ADC_CCR_DMACFG_ONESHOT          (0 << 13)
-#define ADC_CCR_DMACFG_CIRCULAR         (1 << 13)
-#define ADC_CCR_MDMA_MASK               (3 << 14)
-#define ADC_CCR_MDMA_DISABLED           (0 << 14)
-#define ADC_CCR_MDMA_WORD               (2 << 14)
-#define ADC_CCR_MDMA_HWORD              (3 << 14)
-#define ADC_CCR_CKMODE_MASK             (3 << 16)
-#define ADC_CCR_CKMODE_ADCCK            (0 << 16)
-#define ADC_CCR_CKMODE_AHB_DIV1         (1 << 16)
-#define ADC_CCR_CKMODE_AHB_DIV2         (2 << 16)
-#define ADC_CCR_CKMODE_AHB_DIV4         (3 << 16)
-#define ADC_CCR_VREFEN                  (1 << 22)
-#define ADC_CCR_TSEN                    (1 << 23)
-#define ADC_CCR_VBATEN                  (1 << 24)
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   ADC1 driver enable switch.
- * @details If set to @p TRUE the support for ADC1 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
-#define STM32_ADC_USE_ADC1                  FALSE
-#endif
-
-/**
- * @brief   ADC3 driver enable switch.
- * @details If set to @p TRUE the support for ADC3 is included.
- * @note    The default is @p FALSE.
- */
-#if !defined(STM32_ADC_USE_ADC3) || defined(__DOXYGEN__)
-#define STM32_ADC_USE_ADC3                  FALSE
-#endif
-
-/**
- * @brief   ADC1/ADC2 DMA priority (0..3|lowest..highest).
- */
-#if !defined(STM32_ADC_ADC12_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC12_DMA_PRIORITY        2
-#endif
-
-/**
- * @brief   ADC3/ADC4 DMA priority (0..3|lowest..highest).
- */
-#if !defined(STM32_ADC_ADC34_DMA_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC34_DMA_PRIORITY        2
-#endif
-
-/**
- * @brief   ADC1/ADC2 interrupt priority level setting.
- */
-#if !defined(STM32_ADC_ADC12_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC12_IRQ_PRIORITY        5
-#endif
-
-/**
- * @brief   ADC3/ADC4 interrupt priority level setting.
- */
-#if !defined(STM32_ADC34_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC34_IRQ_PRIORITY        5
-#endif
-
-/**
- * @brief   ADC1/ADC2 DMA interrupt priority level setting.
- */
-#if !defined(STM32_ADC_ADC12_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY    5
-#endif
-
-/**
- * @brief   ADC3/ADC4 DMA interrupt priority level setting.
- */
-#if !defined(STM32_ADC_ADC34_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY    5
-#endif
-
-/**
- * @brief   ADC1/ADC2 clock source and mode.
- */
-#if !defined(STM32_ADC_ADC12_CLOCK_MODE) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC12_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1
-#endif
-
-/**
- * @brief   ADC3/ADC4 clock source and mode.
- */
-#if !defined(STM32_ADC_ADC34_CLOCK_MODE) || defined(__DOXYGEN__)
-#define STM32_ADC_ADC34_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1
-#endif
-
-/**
- * @brief   Enables the ADC master/slave mode.
- */
-#if !defined(STM32_ADC_DUAL_MODE) || defined(__DOXYGEN__)
-#define STM32_ADC_DUAL_MODE                 FALSE
-#endif
-
-/**
- * @brief   Makes the ADC samples type an 8bits one.
- */
-#if !defined(STM32_ADC_COMPACT_SAMPLES) || defined(__DOXYGEN__)
-#define STM32_ADC_COMPACT_SAMPLES           FALSE
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
-#error "ADC1 not present in the selected device"
-#endif
-
-#if STM32_ADC_DUAL_MODE && STM32_ADC_USE_ADC1 && !STM32_HAS_ADC2
-#error "ADC2 not present in the selected device"
-#endif
-
-#if STM32_ADC_USE_ADC3 && !STM32_HAS_ADC3
-#error "ADC3 not present in the selected device"
-#endif
-
-#if STM32_ADC_DUAL_MODE && STM32_ADC_USE_ADC2 && !STM32_HAS_ADC4
-#error "ADC4 not present in the selected device"
-#endif
-
-#if !STM32_ADC_USE_ADC1 && !STM32_ADC_USE_ADC3
-#error "ADC driver activated but no ADC peripheral assigned"
-#endif
-
-#if STM32_ADC_USE_ADC1 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC12_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to ADC1"
-#endif
-
-#if STM32_ADC_USE_ADC1 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC12_DMA_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to ADC1 DMA"
-#endif
-
-#if STM32_ADC_USE_ADC1 &&                                                   \
-    !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC12_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to ADC1"
-#endif
-
-#if STM32_ADC_USE_ADC3 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC34_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to ADC3"
-#endif
-
-#if STM32_ADC_USE_ADC3 &&                                                   \
-    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC34_DMA_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to ADC3 DMA"
-#endif
-
-#if STM32_ADC_USE_ADC3 &&                                                   \
-    !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC34_DMA_PRIORITY)
-#error "Invalid DMA priority assigned to ADC3"
-#endif
-
-#if STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
-#define STM32_ADC12_CLOCK               STM32_ADC12CLK
-#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
-#define STM32_ADC12_CLOCK               (STM32_HCLK / 1)
-#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
-#define STM32_ADC12_CLOCK               (STM32_HCLK / 2)
-#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
-#define STM32_ADC12_CLOCK               (STM32_HCLK / 4)
-#else
-#error "invalid clock mode selected for STM32_ADC_ADC12_CLOCK_MODE"
-#endif
-
-#if STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
-#define STM32_ADC34_CLOCK               STM32_ADC34CLK
-#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
-#define STM32_ADC34_CLOCK               (STM32_HCLK / 1)
-#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
-#define STM32_ADC34_CLOCK               (STM32_HCLK / 2)
-#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
-#define STM32_ADC34_CLOCK               (STM32_HCLK / 4)
-#else
-#error "invalid clock mode selected for STM32_ADC_ADC12_CLOCK_MODE"
-#endif
-
-#if STM32_ADC12_CLOCK > 72000000
-#error "STM32_ADC12_CLOCK exceeding maximum frequency (72000000)"
-#endif
-
-#if STM32_ADC34_CLOCK > 72000000
-#error "STM32_ADC34_CLOCK exceeding maximum frequency (72000000)"
-#endif
-
-#if !defined(STM32_DMA_REQUIRED)
-#define STM32_DMA_REQUIRED
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   ADC sample data type.
- */
-#if !STM32_ADC_COMPACT_SAMPLES || defined(__DOXYGEN__)
-typedef uint16_t adcsample_t;
-#else
-typedef uint8_t adcsample_t;
-#endif
-
-/**
- * @brief   Channels number in a conversion group.
- */
-typedef uint16_t adc_channels_num_t;
-
-/**
- * @brief   Possible ADC failure causes.
- * @note    Error codes are architecture dependent and should not relied
- *          upon.
- */
-typedef enum {
-  ADC_ERR_DMAFAILURE = 0,                   /**< DMA operations failure.    */
-  ADC_ERR_OVERFLOW = 1,                     /**< ADC overflow condition.    */
-  ADC_ERR_AWD1 = 2,                         /**< Watchdog 1 triggered.      */
-  ADC_ERR_AWD2 = 3,                         /**< Watchdog 2 triggered.      */
-  ADC_ERR_AWD3 = 4                          /**< Watchdog 3 triggered.      */
-} adcerror_t;
-
-/**
- * @brief   Type of a structure representing an ADC driver.
- */
-typedef struct ADCDriver ADCDriver;
-
-/**
- * @brief   ADC notification callback type.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object triggering the
- *                      callback
- * @param[in] buffer    pointer to the most recent samples data
- * @param[in] n         number of buffer rows available starting from @p buffer
- */
-typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
-
-/**
- * @brief   ADC error callback type.
- *
- * @param[in] adcp      pointer to the @p ADCDriver object triggering the
- *                      callback
- * @param[in] err       ADC error code
- */
-typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
-
-/**
- * @brief   Conversion group configuration structure.
- * @details This implementation-dependent structure describes a conversion
- *          operation.
- * @note    The use of this configuration structure requires knowledge of
- *          STM32 ADC cell registers interface, please refer to the STM32
- *          reference manual for details.
- */
-typedef struct {
-  /**
-   * @brief   Enables the circular buffer mode for the group.
-   */
-  bool                      circular;
-  /**
-   * @brief   Number of the analog channels belonging to the conversion group.
-   */
-  adc_channels_num_t        num_channels;
-  /**
-   * @brief   Callback function associated to the group or @p NULL.
-   */
-  adccallback_t             end_cb;
-  /**
-   * @brief   Error callback or @p NULL.
-   */
-  adcerrorcallback_t        error_cb;
-  /* End of the mandatory fields.*/
-  /**
-   * @brief   ADC CFGR register initialization data.
-   * @note    The bits DMAEN and DMACFG are enforced internally
-   *          to the driver, keep them to zero.
-   * @note    The bits @p ADC_CFGR_CONT or @p ADC_CFGR_DISCEN must be
-   *          specified in continuous more or if the buffer depth is
-   *          greater than one.
-   */
-  uint32_t                  cfgr;
-  /**
-   * @brief   ADC TR1 register initialization data.
-   */
-  uint32_t                  tr1;
-  /**
-   * @brief   ADC CCR register initialization data.
-   * @note    The bits CKMODE, MDMA, DMACFG are enforced internally to the
-   *          driver, keep them to zero.
-   */
-  uint32_t                  ccr;
-  /**
-   * @brief   ADC SMPRx registers initialization data.
-   */
-  uint32_t                  smpr[2];
-  /**
-   * @brief   ADC SQRx register initialization data.
-   */
-  uint32_t                  sqr[4];
-#if STM32_ADC_DUAL_MODE || defined(__DOXYGEN__)
-  /**
-   * @brief   Slave ADC SMPRx registers initialization data.
-   */
-  uint32_t                  ssmpr[2];
-  /**
-   * @brief   Slave ADC SQRx register initialization data.
-   */
-  uint32_t                  ssqr[4];
-#endif /* STM32_ADC_DUAL_MODE */
-} ADCConversionGroup;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  uint32_t                  dummy;
-} ADCConfig;
-
-/**
- * @brief   Structure representing an ADC driver.
- */
-struct ADCDriver {
-  /**
-   * @brief   Driver state.
-   */
-  adcstate_t                state;
-  /**
-   * @brief   Current configuration data.
-   */
-  const ADCConfig           *config;
-  /**
-   * @brief   Current samples buffer pointer or @p NULL.
-   */
-  adcsample_t               *samples;
-  /**
-   * @brief   Current samples buffer depth or @p 0.
-   */
-  size_t                    depth;
-  /**
-   * @brief   Current conversion group pointer or @p NULL.
-   */
-  const ADCConversionGroup  *grpp;
-#if ADC_USE_WAIT || defined(__DOXYGEN__)
-  /**
-   * @brief   Waiting thread.
-   */
-  thread_reference_t        thread;
-#endif
-#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
-  /**
-   * @brief   Mutex protecting the peripheral.
-   */
-  mutex_t                   mutex;
-#endif /* ADC_USE_MUTUAL_EXCLUSION */
-#if defined(ADC_DRIVER_EXT_FIELDS)
-  ADC_DRIVER_EXT_FIELDS
-#endif
-  /* End of the mandatory fields.*/
-  /**
-   * @brief   Pointer to the common ADCx_y registers block.
-   */
-  ADC_Common_TypeDef        *adcc;
-  /**
-   * @brief   Pointer to the master ADCx registers block.
-   */
-  ADC_TypeDef               *adcm;
-#if STM32_ADC_DUAL_MODE || defined(__DOXYGEN__)
-  /**
-   * @brief   Pointer to the slave ADCx registers block.
-   */
-  ADC_TypeDef               *adcs;
-#endif /* STM32_ADC_DUAL_MODE */
-  /**
-   * @brief   Pointer to associated DMA channel.
-   */
-  const stm32_dma_stream_t  *dmastp;
-  /**
-   * @brief   DMA mode bit mask.
-   */
-  uint32_t                  dmamode;
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @name    Threashold register initializer
- * @{
- */
-#define ADC_TR(low, high)       (((uint32_t)(high) << 16) | (uint32_t)(low))
-/** @} */
-
-/**
- * @name    Sequences building helper macros
- * @{
- */
-/**
- * @brief   Number of channels in a conversion sequence.
- */
-#define ADC_SQR1_NUM_CH(n)      (((n) - 1) << 0)
-
-#define ADC_SQR1_SQ1_N(n)       ((n) << 6)  /**< @brief 1st channel in seq. */
-#define ADC_SQR1_SQ2_N(n)       ((n) << 12) /**< @brief 2nd channel in seq. */
-#define ADC_SQR1_SQ3_N(n)       ((n) << 18) /**< @brief 3rd channel in seq. */
-#define ADC_SQR1_SQ4_N(n)       ((n) << 24) /**< @brief 4th channel in seq. */
-
-#define ADC_SQR2_SQ5_N(n)       ((n) << 0)  /**< @brief 5th channel in seq. */
-#define ADC_SQR2_SQ6_N(n)       ((n) << 6)  /**< @brief 6th channel in seq. */
-#define ADC_SQR2_SQ7_N(n)       ((n) << 12) /**< @brief 7th channel in seq. */
-#define ADC_SQR2_SQ8_N(n)       ((n) << 18) /**< @brief 8th channel in seq. */
-#define ADC_SQR2_SQ9_N(n)       ((n) << 24) /**< @brief 9th channel in seq. */
-
-#define ADC_SQR3_SQ10_N(n)      ((n) << 0)  /**< @brief 10th channel in seq.*/
-#define ADC_SQR3_SQ11_N(n)      ((n) << 6)  /**< @brief 11th channel in seq.*/
-#define ADC_SQR3_SQ12_N(n)      ((n) << 12) /**< @brief 12th channel in seq.*/
-#define ADC_SQR3_SQ13_N(n)      ((n) << 18) /**< @brief 13th channel in seq.*/
-#define ADC_SQR3_SQ14_N(n)      ((n) << 24) /**< @brief 14th channel in seq.*/
-
-#define ADC_SQR4_SQ15_N(n)      ((n) << 0)  /**< @brief 15th channel in seq.*/
-#define ADC_SQR4_SQ16_N(n)      ((n) << 6)  /**< @brief 16th channel in seq.*/
-/** @} */
-
-/**
- * @name    Sampling rate settings helper macros
- * @{
- */
-#define ADC_SMPR1_SMP_AN1(n)    ((n) << 3)  /**< @brief AN1 sampling time.  */
-#define ADC_SMPR1_SMP_AN2(n)    ((n) << 6)  /**< @brief AN2 sampling time.  */
-#define ADC_SMPR1_SMP_AN3(n)    ((n) << 9)  /**< @brief AN3 sampling time.  */
-#define ADC_SMPR1_SMP_AN4(n)    ((n) << 12) /**< @brief AN4 sampling time.  */
-#define ADC_SMPR1_SMP_AN5(n)    ((n) << 15) /**< @brief AN5 sampling time.  */
-#define ADC_SMPR1_SMP_AN6(n)    ((n) << 18) /**< @brief AN6 sampling time.  */
-#define ADC_SMPR1_SMP_AN7(n)    ((n) << 21) /**< @brief AN7 sampling time.  */
-#define ADC_SMPR1_SMP_AN8(n)    ((n) << 24) /**< @brief AN8 sampling time.  */
-#define ADC_SMPR1_SMP_AN9(n)    ((n) << 27) /**< @brief AN9 sampling time.  */
-
-#define ADC_SMPR2_SMP_AN10(n)   ((n) << 0)  /**< @brief AN10 sampling time. */
-#define ADC_SMPR2_SMP_AN11(n)   ((n) << 3)  /**< @brief AN11 sampling time. */
-#define ADC_SMPR2_SMP_AN12(n)   ((n) << 6)  /**< @brief AN12 sampling time. */
-#define ADC_SMPR2_SMP_AN13(n)   ((n) << 9)  /**< @brief AN13 sampling time. */
-#define ADC_SMPR2_SMP_AN14(n)   ((n) << 12) /**< @brief AN14 sampling time. */
-#define ADC_SMPR2_SMP_AN15(n)   ((n) << 15) /**< @brief AN15 sampling time. */
-#define ADC_SMPR2_SMP_AN16(n)   ((n) << 18) /**< @brief AN16 sampling time. */
-#define ADC_SMPR2_SMP_AN17(n)   ((n) << 21) /**< @brief AN17 sampling time. */
-#define ADC_SMPR2_SMP_AN18(n)   ((n) << 24) /**< @brief AN18 sampling time. */
-/** @} */
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__)
-extern ADCDriver ADCD1;
-#endif
-
-#if STM32_ADC_USE_ADC3 && !defined(__DOXYGEN__)
-extern ADCDriver ADCD3;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void adc_lld_init(void);
-  void adc_lld_start(ADCDriver *adcp);
-  void adc_lld_stop(ADCDriver *adcp);
-  void adc_lld_start_conversion(ADCDriver *adcp);
-  void adc_lld_stop_conversion(ADCDriver *adcp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_ADC */
-
-#endif /* _ADC_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/ports/STM32/STM32F30x/ext_lld_isr.c b/os/hal/ports/STM32/STM32F30x/ext_lld_isr.c
deleted file mode 100644
index b16158d8b..000000000
--- a/os/hal/ports/STM32/STM32F30x/ext_lld_isr.c
+++ /dev/null
@@ -1,406 +0,0 @@
-/*
-    ChibiOS/HAL - Copyright (C) 2006-2014 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F30x/ext_lld_isr.c
- * @brief   STM32F30x EXT subsystem low level driver ISR code.
- *
- * @addtogroup EXT
- * @{
- */
-
-#include "hal.h"
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-#include "ext_lld_isr.h"
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if !defined(STM32_DISABLE_EXTI0_HANDLER)
-/**
- * @brief   EXTI[0] interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector58) {
-
-  OSAL_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 0);
-  EXTD1.config->channels[0].cb(&EXTD1, 0);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI1_HANDLER)
-/**
- * @brief   EXTI[1] interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector5C) {
-
-  OSAL_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 1);
-  EXTD1.config->channels[1].cb(&EXTD1, 1);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI2_HANDLER)
-/**
- * @brief   EXTI[2] interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector60) {
-
-  OSAL_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 2);
-  EXTD1.config->channels[2].cb(&EXTD1, 2);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI3_HANDLER)
-/**
- * @brief   EXTI[3] interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector64) {
-
-  OSAL_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 3);
-  EXTD1.config->channels[3].cb(&EXTD1, 3);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI4_HANDLER)
-/**
- * @brief   EXTI[4] interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector68) {
-
-  OSAL_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 4);
-  EXTD1.config->channels[4].cb(&EXTD1, 4);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI5_9_HANDLER)
-/**
- * @brief   EXTI[5]...EXTI[9] interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector9C) {
-  uint32_t pr;
-
-  OSAL_IRQ_PROLOGUE();
-
-  pr = EXTI->PR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9));
-  EXTI->PR = pr;
-  if (pr & (1 << 5))
-    EXTD1.config->channels[5].cb(&EXTD1, 5);
-  if (pr & (1 << 6))
-    EXTD1.config->channels[6].cb(&EXTD1, 6);
-  if (pr & (1 << 7))
-    EXTD1.config->channels[7].cb(&EXTD1, 7);
-  if (pr & (1 << 8))
-    EXTD1.config->channels[8].cb(&EXTD1, 8);
-  if (pr & (1 << 9))
-    EXTD1.config->channels[9].cb(&EXTD1, 9);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI10_15_HANDLER)
-/**
- * @brief   EXTI[10]...EXTI[15] interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(VectorE0) {
-  uint32_t pr;
-
-  OSAL_IRQ_PROLOGUE();
-
-  pr = EXTI->PR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) |
-                   (1 << 15));
-  EXTI->PR = pr;
-  if (pr & (1 << 10))
-    EXTD1.config->channels[10].cb(&EXTD1, 10);
-  if (pr & (1 << 11))
-    EXTD1.config->channels[11].cb(&EXTD1, 11);
-  if (pr & (1 << 12))
-    EXTD1.config->channels[12].cb(&EXTD1, 12);
-  if (pr & (1 << 13))
-    EXTD1.config->channels[13].cb(&EXTD1, 13);
-  if (pr & (1 << 14))
-    EXTD1.config->channels[14].cb(&EXTD1, 14);
-  if (pr & (1 << 15))
-    EXTD1.config->channels[15].cb(&EXTD1, 15);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI16_HANDLER)
-/**
- * @brief   EXTI[16] interrupt handler (PVD).
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector44) {
-
-  OSAL_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 16);
-  EXTD1.config->channels[16].cb(&EXTD1, 16);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI17_HANDLER)
-/**
- * @brief   EXTI[17] interrupt handler (RTC Alarm).
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(VectorE4) {
-
-  OSAL_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 17);
-  EXTD1.config->channels[17].cb(&EXTD1, 17);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI18_HANDLER)
-/**
- * @brief   EXTI[18] interrupt handler (USB Wakeup).
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(VectorE8) {
-
-  OSAL_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 18);
-  EXTD1.config->channels[18].cb(&EXTD1, 18);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI19_HANDLER)
-/**
- * @brief   EXTI[19] interrupt handler (Tamper TimeStamp).
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector48) {
-
-  OSAL_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 19);
-  EXTD1.config->channels[19].cb(&EXTD1, 19);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI20_HANDLER)
-/**
- * @brief   EXTI[20] interrupt handler (RTC Wakeup).
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector4C) {
-
-  OSAL_IRQ_PROLOGUE();
-
-  EXTI->PR = (1 << 20);
-  EXTD1.config->channels[20].cb(&EXTD1, 20);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI21_22_29_HANDLER)
-/**
- * @brief   EXTI[21],EXTI[22],EXTI[29] interrupt handler (COMP1, COMP2, COMP3).
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector140) {
-  uint32_t pr;
-
-  OSAL_IRQ_PROLOGUE();
-
-  pr = EXTI->PR & ((1 << 21) | (1 << 22) | (1 << 29));
-  EXTI->PR = pr;
-  if (pr & (1 << 21))
-    EXTD1.config->channels[21].cb(&EXTD1, 21);
-  if (pr & (1 << 22))
-    EXTD1.config->channels[22].cb(&EXTD1, 22);
-  if (pr & (1 << 29))
-    EXTD1.config->channels[29].cb(&EXTD1, 29);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI30_32_HANDLER)
-/**
- * @brief   EXTI[30]...EXTI[32] interrupt handler (COMP4, COMP5, COMP6).
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector144) {
-  uint32_t pr;
-
-  OSAL_IRQ_PROLOGUE();
-
-  pr = EXTI->PR & ((1 << 30) | (1 << 31));
-  EXTI->PR = pr;
-  if (pr & (1 << 30))
-    EXTD1.config->channels[30].cb(&EXTD1, 30);
-  if (pr & (1 << 31))
-    EXTD1.config->channels[31].cb(&EXTD1, 31);
-
-  pr = EXTI->PR2 & (1 << 0);
-  EXTI->PR2 = pr;
-  if (pr & (1 << 0))
-    EXTD1.config->channels[32].cb(&EXTD1, 32);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if !defined(STM32_DISABLE_EXTI33_HANDLER)
-/**
- * @brief   EXTI[33] interrupt handler (COMP7).
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(RTC_WKUP_IRQHandler) {
-
-  OSAL_IRQ_PROLOGUE();
-
-  EXTI->PR2 = (1 << 1);
-  EXTD1.config->channels[33].cb(&EXTD1, 33);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Enables EXTI IRQ sources.
- *
- * @notapi
- */
-void ext_lld_exti_irq_enable(void) {
-
-  nvicEnableVector(EXTI0_IRQn, STM32_EXT_EXTI0_IRQ_PRIORITY);
-  nvicEnableVector(EXTI1_IRQn, STM32_EXT_EXTI1_IRQ_PRIORITY);
-  nvicEnableVector(EXTI2_TSC_IRQn, STM32_EXT_EXTI2_IRQ_PRIORITY);
-  nvicEnableVector(EXTI3_IRQn, STM32_EXT_EXTI3_IRQ_PRIORITY);
-  nvicEnableVector(EXTI4_IRQn, STM32_EXT_EXTI4_IRQ_PRIORITY);
-  nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY);
-  nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY);
-  nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY);
-  nvicEnableVector(RTC_Alarm_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY);
-  nvicEnableVector(USBWakeUp_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY);
-  nvicEnableVector(TAMP_STAMP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY);
-  nvicEnableVector(RTC_WKUP_IRQn, STM32_EXT_EXTI20_IRQ_PRIORITY);
-  nvicEnableVector(COMP1_2_3_IRQn, STM32_EXT_EXTI21_22_29_IRQ_PRIORITY);
-  nvicEnableVector(COMP4_5_6_IRQn, STM32_EXT_EXTI30_32_IRQ_PRIORITY);
-#if STM32_EXTI_NUM_CHANNELS >= 34
-  nvicEnableVector(COMP7_IRQn, STM32_EXT_EXTI33_IRQ_PRIORITY);
-#endif
-}
-
-/**
- * @brief   Disables EXTI IRQ sources.
- *
- * @notapi
- */
-void ext_lld_exti_irq_disable(void) {
-
-  nvicDisableVector(EXTI0_IRQn);
-  nvicDisableVector(EXTI1_IRQn);
-  nvicDisableVector(EXTI2_TSC_IRQn);
-  nvicDisableVector(EXTI3_IRQn);
-  nvicDisableVector(EXTI4_IRQn);
-  nvicDisableVector(EXTI9_5_IRQn);
-  nvicDisableVector(EXTI15_10_IRQn);
-  nvicDisableVector(PVD_IRQn);
-  nvicDisableVector(RTC_Alarm_IRQn);
-  nvicDisableVector(USBWakeUp_IRQn);
-  nvicDisableVector(TAMP_STAMP_IRQn);
-  nvicDisableVector(RTC_WKUP_IRQn);
-  nvicDisableVector(COMP1_2_3_IRQn);
-  nvicDisableVector(COMP4_5_6_IRQn);
-#if STM32_EXTI_NUM_CHANNELS >= 34
-  nvicDisableVector(COMP7_IRQn);
-#endif
-}
-
-#endif /* HAL_USE_EXT */
-
-/** @} */
diff --git a/os/hal/ports/STM32/STM32F30x/ext_lld_isr.h b/os/hal/ports/STM32/STM32F30x/ext_lld_isr.h
deleted file mode 100644
index 35e379e26..000000000
--- a/os/hal/ports/STM32/STM32F30x/ext_lld_isr.h
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
-    ChibiOS/HAL - Copyright (C) 2006-2014 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F30x/ext_lld_isr.h
- * @brief   STM32F30x EXT subsystem low level driver ISR header.
- *
- * @addtogroup EXT
- * @{
- */
-
-#ifndef _EXT_LLD_ISR_H_
-#define _EXT_LLD_ISR_H_
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   EXTI0 interrupt priority level setting.
- */
-#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_EXT_EXTI0_IRQ_PRIORITY        6
-#endif
-
-/**
- * @brief   EXTI1 interrupt priority level setting.
- */
-#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_EXT_EXTI1_IRQ_PRIORITY        6
-#endif
-
-/**
- * @brief   EXTI2 interrupt priority level setting.
- */
-#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_EXT_EXTI2_IRQ_PRIORITY        6
-#endif
-
-/**
- * @brief   EXTI3 interrupt priority level setting.
- */
-#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_EXT_EXTI3_IRQ_PRIORITY        6
-#endif
-
-/**
- * @brief   EXTI4 interrupt priority level setting.
- */
-#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_EXT_EXTI4_IRQ_PRIORITY        6
-#endif
-
-/**
- * @brief   EXTI5..9 interrupt priority level setting.
- */
-#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_EXT_EXTI5_9_IRQ_PRIORITY      6
-#endif
-
-/**
- * @brief   EXTI10..15 interrupt priority level setting.
- */
-#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_EXT_EXTI10_15_IRQ_PRIORITY    6
-#endif
-
-/**
- * @brief   EXTI16 interrupt priority level setting.
- */
-#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_EXT_EXTI16_IRQ_PRIORITY       6
-#endif
-
-/**
- * @brief   EXTI17 interrupt priority level setting.
- */
-#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_EXT_EXTI17_IRQ_PRIORITY       6
-#endif
-
-/**
- * @brief   EXTI18 interrupt priority level setting.
- */
-#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_EXT_EXTI18_IRQ_PRIORITY       6
-#endif
-
-/**
- * @brief   EXTI19 interrupt priority level setting.
- */
-#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_EXT_EXTI19_IRQ_PRIORITY       6
-#endif
-
-/**
- * @brief   EXTI20 interrupt priority level setting.
- */
-#if !defined(STM32_EXT_EXTI20_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_EXT_EXTI20_IRQ_PRIORITY       6
-#endif
-
-/**
- * @brief   EXTI21,22,29 interrupt priority level setting.
- */
-#if !defined(STM32_EXT_EXTI21_22_29_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_EXT_EXTI21_22_29_IRQ_PRIORITY 6
-#endif
-
-/**
- * @brief   EXTI30..32 interrupt priority level setting.
- */
-#if !defined(STM32_EXT_EXTI30_32_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_EXT_EXTI30_32_IRQ_PRIORITY    6
-#endif
-
-/**
- * @brief   EXTI33 interrupt priority level setting.
- */
-#if !defined(STM32_EXT_EXTI33_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_EXT_EXTI33_IRQ_PRIORITY       6
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void ext_lld_exti_irq_enable(void);
-  void ext_lld_exti_irq_disable(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_EXT */
-
-#endif /* _EXT_LLD_ISR_H_ */
-
-/** @} */
diff --git a/os/hal/ports/STM32/STM32F30x/hal_lld.c b/os/hal/ports/STM32/STM32F30x/hal_lld.c
deleted file mode 100644
index 6e5a8db8d..000000000
--- a/os/hal/ports/STM32/STM32F30x/hal_lld.c
+++ /dev/null
@@ -1,202 +0,0 @@
-/*
-    ChibiOS/HAL - Copyright (C) 2006-2014 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F30x/hal_lld.c
- * @brief   STM32F30x HAL subsystem low level driver source.
- *
- * @addtogroup HAL
- * @{
- */
-
-#include "hal.h"
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Initializes the backup domain.
- * @note    WARNING! Changing clock source impossible without resetting
- *          of the whole BKP domain.
- */
-static void hal_lld_backup_domain_init(void) {
-
-  /* Backup domain access enabled and left open.*/
-  PWR->CR |= PWR_CR_DBP;
-
-  /* Reset BKP domain if different clock source selected.*/
-  if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){
-    /* Backup domain reset.*/
-    RCC->BDCR = RCC_BDCR_BDRST;
-    RCC->BDCR = 0;
-  }
-
-  /* If enabled then the LSE is started.*/
-#if STM32_LSE_ENABLED
-#if defined(STM32_LSE_BYPASS)
-  /* LSE Bypass.*/
-  RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
-#else
-  /* No LSE Bypass.*/
-  RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
-#endif
-  while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
-    ;                                     /* Waits until LSE is stable.   */
-#endif
-
-#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
-  /* If the backup domain hasn't been initialized yet then proceed with
-     initialization.*/
-  if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
-    /* Selects clock source.*/
-    RCC->BDCR |= STM32_RTCSEL;
-
-    /* RTC clock enabled.*/
-    RCC->BDCR |= RCC_BDCR_RTCEN;
-  }
-#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level HAL driver initialization.
- *
- * @notapi
- */
-void hal_lld_init(void) {
-
-  /* Reset of all peripherals.*/
-  rccResetAHB(0xFFFFFFFF);
-  rccResetAPB1(0xFFFFFFFF);
-  rccResetAPB2(0xFFFFFFFF);
-
-  /* PWR clock enabled.*/
-  rccEnablePWRInterface(FALSE);
-
-  /* Initializes the backup domain.*/
-  hal_lld_backup_domain_init();
-
-#if defined(STM32_DMA_REQUIRED)
-  dmaInit();
-#endif
-
-  /* Programmable voltage detector enable.*/
-#if STM32_PVD_ENABLE
-  PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
-#endif /* STM32_PVD_ENABLE */
-
-  /* SYSCFG clock enabled here because it is a multi-functional unit shared
-     among multiple drivers.*/
-  rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
-
-  /* USB IRQ relocated to not conflict with CAN.*/
-  SYSCFG->CFGR1 |= SYSCFG_CFGR1_USB_IT_RMP;
-}
-
-/**
- * @brief   STM32 clocks and PLL initialization.
- * @note    All the involved constants come from the file @p board.h.
- * @note    This function should be invoked just after the system reset.
- *
- * @special
- */
-void stm32_clock_init(void) {
-
-#if !STM32_NO_INIT
-  /* HSI setup, it enforces the reset situation in order to handle possible
-     problems with JTAG probes and re-initializations.*/
-  RCC->CR |= RCC_CR_HSION;                  /* Make sure HSI is ON.         */
-  while (!(RCC->CR & RCC_CR_HSIRDY))
-    ;                                       /* Wait until HSI is stable.    */
-  RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value.              */
-  RCC->CFGR = 0;                            /* CFGR reset value.            */
-  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
-    ;                                       /* Waits until HSI is selected. */
-
-#if STM32_HSE_ENABLED
-  /* HSE activation.*/
-#if defined(STM32_HSE_BYPASS)
-  /* HSE Bypass.*/
-  RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
-#else
-  /* No HSE Bypass.*/
-  RCC->CR |= RCC_CR_HSEON;
-#endif
-  while (!(RCC->CR & RCC_CR_HSERDY))
-    ;                                       /* Waits until HSE is stable.   */
-#endif
-
-#if STM32_LSI_ENABLED
-  /* LSI activation.*/
-  RCC->CSR |= RCC_CSR_LSION;
-  while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
-    ;                                       /* Waits until LSI is stable.   */
-#endif
-
-  /* Clock settings.*/
-  RCC->CFGR  = STM32_MCOSEL    | STM32_USBPRE    | STM32_PLLMUL   |
-               STM32_PLLSRC    | STM32_PPRE1     | STM32_PPRE2    |
-               STM32_HPRE;
-  RCC->CFGR2 = STM32_ADC34PRES | STM32_ADC12PRES | STM32_PREDIV;
-  RCC->CFGR3 = STM32_UART5SW   | STM32_UART4SW   | STM32_USART3SW |
-               STM32_USART2SW  | STM32_I2C2SW    | STM32_I2C1SW   |
-               STM32_USART1SW;
-
-#if STM32_ACTIVATE_PLL
-  /* PLL activation.*/
-  RCC->CR   |= RCC_CR_PLLON;
-  while (!(RCC->CR & RCC_CR_PLLRDY))
-    ;                                       /* Waits until PLL is stable.   */
-#endif
-
-  /* Flash setup and final clock selection.   */
-  FLASH->ACR = STM32_FLASHBITS;
-
-  /* Switching to the configured clock source if it is different from HSI.*/
-#if (STM32_SW != STM32_SW_HSI)
-  /* Switches clock source.*/
-  RCC->CFGR |= STM32_SW;
-  while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
-    ;                                       /* Waits selection complete.    */
-#endif
-
-  /* After PLL activation because the special requirements for TIM1 and
-     TIM8 bits.*/
-  RCC->CFGR3 |= STM32_TIM8SW | STM32_TIM1SW;
-#endif /* !STM32_NO_INIT */
-}
-
-/** @} */
diff --git a/os/hal/ports/STM32/STM32F30x/hal_lld.h b/os/hal/ports/STM32/STM32F30x/hal_lld.h
deleted file mode 100644
index d95efd4dd..000000000
--- a/os/hal/ports/STM32/STM32F30x/hal_lld.h
+++ /dev/null
@@ -1,1150 +0,0 @@
-/*
-    ChibiOS/HAL - Copyright (C) 2006-2014 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F30x/hal_lld.h
- * @brief   STM32F30x HAL subsystem low level driver header.
- * @pre     This module requires the following macros to be defined in the
- *          @p board.h file:
- *          - STM32_LSECLK.
- *          - STM32_LSEDRV.
- *          - STM32_LSE_BYPASS (optionally).
- *          - STM32_HSECLK.
- *          - STM32_HSE_BYPASS (optionally).
- *          .
- *          One of the following macros must also be defined:
- *          - STM32F301x8 for Analog & DSP devices.
- *          - STM32F302x8 for Analog & DSP devices.
- *          - STM32F302xC for Analog & DSP devices.
- *          - STM32F303x8 for Analog & DSP devices.
- *          - STM32F303xC for Analog & DSP devices.
- *          - STM32F318xx for Analog & DSP devices.
- *          - STM32F328xx for Analog & DSP devices.
- *          - STM32F334x8 for Analog & DSP devices.
- *          - STM32F358xx for Analog & DSP devices.
- *          .
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _HAL_LLD_H_
-#define _HAL_LLD_H_
-
-#include "stm32_registry.h"
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @name    Platform identification macros
- * @{
- */
-#if defined(STM32F301x8) || defined(__DOXYGEN__)
-#define PLATFORM_NAME           "STM32F301x8 Analog & DSP"
-
-#elif defined(STM32F302x8)
-#define PLATFORM_NAME           "STM32F302x8 Analog & DSP"
-
-#elif defined(STM32F302xC)
-#define PLATFORM_NAME           "STM32F302xC Analog & DSP"
-
-#elif defined(STM32F303x8)
-#define PLATFORM_NAME           "STM32F303x8 Analog & DSP"
-
-#elif defined(STM32F303xC)
-#define PLATFORM_NAME           "STM32F303xC Analog & DSP"
-
-#elif defined(STM32F318xx)
-#define PLATFORM_NAME           "STM32F318xx Analog & DSP"
-
-#elif defined(STM32F328xx)
-#define PLATFORM_NAME           "STM32F328xx Analog & DSP"
-
-#elif defined(STM32F334x8)
-#define PLATFORM_NAME           "STM32F334x8 Analog & DSP"
-
-#elif defined(STM32F358xx)
-#define PLATFORM_NAME           "STM32F358xx Analog & DSP"
-
-#else
-#error "STM32F3xx device not specified"
-#endif
-/** @} */
-
-/**
- * @name    Absolute Maximum Ratings
- * @{
- */
-/**
- * @brief   Maximum system clock frequency.
- */
-#define STM32_SYSCLK_MAX        72000000
-
-/**
- * @brief   Maximum HSE clock frequency.
- */
-#define STM32_HSECLK_MAX        32000000
-
-/**
- * @brief   Minimum HSE clock frequency.
- */
-#define STM32_HSECLK_MIN        1000000
-
-/**
- * @brief   Maximum LSE clock frequency.
- */
-#define STM32_LSECLK_MAX        1000000
-
-/**
- * @brief   Minimum LSE clock frequency.
- */
-#define STM32_LSECLK_MIN        32768
-
-/**
- * @brief   Maximum PLLs input clock frequency.
- */
-#define STM32_PLLIN_MAX         24000000
-
-/**
- * @brief   Minimum PLLs input clock frequency.
- */
-#define STM32_PLLIN_MIN         1000000
-
-/**
- * @brief   Maximum PLL output clock frequency.
- */
-#define STM32_PLLOUT_MAX        72000000
-
-/**
- * @brief   Maximum PLL output clock frequency.
- */
-#define STM32_PLLOUT_MIN        16000000
-
-/**
- * @brief   Maximum APB1 clock frequency.
- */
-#define STM32_PCLK1_MAX         36000000
-
-/**
- * @brief   Maximum APB2 clock frequency.
- */
-#define STM32_PCLK2_MAX         72000000
-
-/**
- * @brief   Maximum ADC clock frequency.
- */
-#define STM32_ADCCLK_MAX        72000000
-/** @} */
-
-/**
- * @name    Internal clock sources
- * @{
- */
-#define STM32_HSICLK            8000000     /**< High speed internal clock. */
-#define STM32_LSICLK            40000       /**< Low speed internal clock.  */
-/** @} */
-
-/**
- * @name    PWR_CR register bits definitions
- * @{
- */
-#define STM32_PLS_MASK          (7 << 5)    /**< PLS bits mask.             */
-#define STM32_PLS_LEV0          (0 << 5)    /**< PVD level 0.               */
-#define STM32_PLS_LEV1          (1 << 5)    /**< PVD level 1.               */
-#define STM32_PLS_LEV2          (2 << 5)    /**< PVD level 2.               */
-#define STM32_PLS_LEV3          (3 << 5)    /**< PVD level 3.               */
-#define STM32_PLS_LEV4          (4 << 5)    /**< PVD level 4.               */
-#define STM32_PLS_LEV5          (5 << 5)    /**< PVD level 5.               */
-#define STM32_PLS_LEV6          (6 << 5)    /**< PVD level 6.               */
-#define STM32_PLS_LEV7          (7 << 5)    /**< PVD level 7.               */
-/** @} */
-
-/**
- * @name    RCC_CFGR register bits definitions
- * @{
- */
-#define STM32_SW_HSI            (0 << 0)    /**< SYSCLK source is HSI.      */
-#define STM32_SW_HSE            (1 << 0)    /**< SYSCLK source is HSE.      */
-#define STM32_SW_PLL            (2 << 0)    /**< SYSCLK source is PLL.      */
-
-#define STM32_HPRE_DIV1         (0 << 4)    /**< SYSCLK divided by 1.       */
-#define STM32_HPRE_DIV2         (8 << 4)    /**< SYSCLK divided by 2.       */
-#define STM32_HPRE_DIV4         (9 << 4)    /**< SYSCLK divided by 4.       */
-#define STM32_HPRE_DIV8         (10 << 4)   /**< SYSCLK divided by 8.       */
-#define STM32_HPRE_DIV16        (11 << 4)   /**< SYSCLK divided by 16.      */
-#define STM32_HPRE_DIV64        (12 << 4)   /**< SYSCLK divided by 64.      */
-#define STM32_HPRE_DIV128       (13 << 4)   /**< SYSCLK divided by 128.     */
-#define STM32_HPRE_DIV256       (14 << 4)   /**< SYSCLK divided by 256.     */
-#define STM32_HPRE_DIV512       (15 << 4)   /**< SYSCLK divided by 512.     */
-
-#define STM32_PPRE1_DIV1        (0 << 8)    /**< HCLK divided by 1.         */
-#define STM32_PPRE1_DIV2        (4 << 8)    /**< HCLK divided by 2.         */
-#define STM32_PPRE1_DIV4        (5 << 8)    /**< HCLK divided by 4.         */
-#define STM32_PPRE1_DIV8        (6 << 8)    /**< HCLK divided by 8.         */
-#define STM32_PPRE1_DIV16       (7 << 8)    /**< HCLK divided by 16.        */
-
-#define STM32_PPRE2_DIV1        (0 << 11)   /**< HCLK divided by 1.         */
-#define STM32_PPRE2_DIV2        (4 << 11)   /**< HCLK divided by 2.         */
-#define STM32_PPRE2_DIV4        (5 << 11)   /**< HCLK divided by 4.         */
-#define STM32_PPRE2_DIV8        (6 << 11)   /**< HCLK divided by 8.         */
-#define STM32_PPRE2_DIV16       (7 << 11)   /**< HCLK divided by 16.        */
-
-#define STM32_PLLSRC_HSI        (0 << 16)   /**< PLL clock source is HSI/2. */
-#define STM32_PLLSRC_HSE        (1 << 16)   /**< PLL clock source is
-                                                 HSE/PREDIV.                */
-
-#define STM32_USBPRE_DIV1P5     (0 << 22)   /**< USB clock is PLLCLK/1.5.   */
-#define STM32_USBPRE_DIV1       (1 << 22)   /**< USB clock is PLLCLK/1.     */
-
-#define STM32_MCOSEL_NOCLOCK    (0 << 24)   /**< No clock on MCO pin.       */
-#define STM32_MCOSEL_LSI        (2 << 24)   /**< LSI clock on MCO pin.      */
-#define STM32_MCOSEL_LSE        (3 << 24)   /**< LSE clock on MCO pin.      */
-#define STM32_MCOSEL_SYSCLK     (4 << 24)   /**< SYSCLK on MCO pin.         */
-#define STM32_MCOSEL_HSI        (5 << 24)   /**< HSI clock on MCO pin.      */
-#define STM32_MCOSEL_HSE        (6 << 24)   /**< HSE clock on MCO pin.      */
-#define STM32_MCOSEL_PLLDIV2    (7 << 24)   /**< PLL/2 clock on MCO pin.    */
-/** @} */
-
-/**
- * @name    RCC_BDCR register bits definitions
- * @{
- */
-#define STM32_RTCSEL_MASK       (3 << 8)    /**< RTC clock source mask.     */
-#define STM32_RTCSEL_NOCLOCK    (0 << 8)    /**< No clock.                  */
-#define STM32_RTCSEL_LSE        (1 << 8)    /**< LSE used as RTC clock.     */
-#define STM32_RTCSEL_LSI        (2 << 8)    /**< LSI used as RTC clock.     */
-#define STM32_RTCSEL_HSEDIV     (3 << 8)    /**< HSE divided by 32 used as
-                                                 RTC clock.                 */
-/** @} */
-
-/**
- * @name    RCC_CFGR2 register bits definitions
- * @{
- */
-#define STM32_PREDIV_MASK       (15 << 0)   /**< PREDIV divisor mask.       */
-#define STM32_ADC12PRES_MASK    (31 << 4)   /**< ADC12 clock source mask.   */
-#define STM32_ADC12PRES_NOCLOCK (0 << 4)    /**< ADC12 clock is disabled.   */
-#define STM32_ADC12PRES_DIV1    (16 << 4)   /**< ADC12 clock is PLL/1.      */
-#define STM32_ADC12PRES_DIV2    (17 << 4)   /**< ADC12 clock is PLL/2.      */
-#define STM32_ADC12PRES_DIV4    (18 << 4)   /**< ADC12 clock is PLL/4.      */
-#define STM32_ADC12PRES_DIV6    (19 << 4)   /**< ADC12 clock is PLL/6.      */
-#define STM32_ADC12PRES_DIV8    (20 << 4)   /**< ADC12 clock is PLL/8.      */
-#define STM32_ADC12PRES_DIV10   (21 << 4)   /**< ADC12 clock is PLL/10.     */
-#define STM32_ADC12PRES_DIV12   (22 << 4)   /**< ADC12 clock is PLL/12.     */
-#define STM32_ADC12PRES_DIV16   (23 << 4)   /**< ADC12 clock is PLL/16.     */
-#define STM32_ADC12PRES_DIV32   (24 << 4)   /**< ADC12 clock is PLL/32.     */
-#define STM32_ADC12PRES_DIV64   (25 << 4)   /**< ADC12 clock is PLL/64.     */
-#define STM32_ADC12PRES_DIV128  (26 << 4)   /**< ADC12 clock is PLL/128.    */
-#define STM32_ADC12PRES_DIV256  (27 << 4)   /**< ADC12 clock is PLL/256.    */
-#define STM32_ADC34PRES_MASK    (31 << 9)   /**< ADC34 clock source mask.   */
-#define STM32_ADC34PRES_NOCLOCK (0 << 9)    /**< ADC34 clock is disabled.   */
-#define STM32_ADC34PRES_DIV1    (16 << 9)   /**< ADC34 clock is PLL/1.      */
-#define STM32_ADC34PRES_DIV2    (17 << 9)   /**< ADC34 clock is PLL/2.      */
-#define STM32_ADC34PRES_DIV4    (18 << 9)   /**< ADC34 clock is PLL/4.      */
-#define STM32_ADC34PRES_DIV6    (19 << 9)   /**< ADC34 clock is PLL/6.      */
-#define STM32_ADC34PRES_DIV8    (20 << 9)   /**< ADC34 clock is PLL/8.      */
-#define STM32_ADC34PRES_DIV10   (21 << 9)   /**< ADC34 clock is PLL/10.     */
-#define STM32_ADC34PRES_DIV12   (22 << 9)   /**< ADC34 clock is PLL/12.     */
-#define STM32_ADC34PRES_DIV16   (23 << 9)   /**< ADC34 clock is PLL/16.     */
-#define STM32_ADC34PRES_DIV32   (24 << 9)   /**< ADC34 clock is PLL/32.     */
-#define STM32_ADC34PRES_DIV64   (25 << 9)   /**< ADC34 clock is PLL/64.     */
-#define STM32_ADC34PRES_DIV128  (26 << 9)   /**< ADC34 clock is PLL/128.    */
-#define STM32_ADC34PRES_DIV256  (27 << 9)   /**< ADC34 clock is PLL/256.    */
-/** @} */
-
-/**
- * @name    RCC_CFGR3 register bits definitions
- * @{
- */
-#define STM32_USART1SW_MASK     (3 << 0)    /**< USART1 clock source mask. */
-#define STM32_USART1SW_PCLK     (0 << 0)    /**< USART1 clock is PCLK.     */
-#define STM32_USART1SW_SYSCLK   (1 << 0)    /**< USART1 clock is SYSCLK.   */
-#define STM32_USART1SW_LSE      (2 << 0)    /**< USART1 clock is LSE.      */
-#define STM32_USART1SW_HSI      (3 << 0)    /**< USART1 clock is HSI.      */
-#define STM32_I2C1SW_MASK       (1 << 4)    /**< I2C1 clock source mask.   */
-#define STM32_I2C1SW_HSI        (0 << 4)    /**< I2C1 clock is HSI.        */
-#define STM32_I2C1SW_SYSCLK     (1 << 4)    /**< I2C1 clock is SYSCLK.     */
-#define STM32_I2C2SW_MASK       (1 << 5)    /**< I2C2 clock source mask.   */
-#define STM32_I2C2SW_HSI        (0 << 5)    /**< I2C2 clock is HSI.        */
-#define STM32_I2C2SW_SYSCLK     (1 << 5)    /**< I2C2 clock is SYSCLK.     */
-#define STM32_TIM1SW_MASK       (1 << 8)    /**< TIM1 clock source mask.   */
-#define STM32_TIM1SW_PCLK2      (0 << 8)    /**< TIM1 clock is PCLK2.      */
-#define STM32_TIM1SW_PLLX2      (1 << 8)    /**< TIM1 clock is PLL*2.      */
-#define STM32_TIM8SW_MASK       (1 << 9)    /**< TIM8 clock source mask.   */
-#define STM32_TIM8SW_PCLK2      (0 << 9)    /**< TIM8 clock is PCLK2.      */
-#define STM32_TIM8SW_PLLX2      (1 << 9)    /**< TIM8 clock is PLL*2.      */
-#define STM32_USART2SW_MASK     (3 << 16)   /**< USART2 clock source mask. */
-#define STM32_USART2SW_PCLK     (0 << 16)   /**< USART2 clock is PCLK.     */
-#define STM32_USART2SW_SYSCLK   (1 << 16)   /**< USART2 clock is SYSCLK.   */
-#define STM32_USART2SW_LSE      (2 << 16)   /**< USART2 clock is LSE.      */
-#define STM32_USART2SW_HSI      (3 << 16)   /**< USART2 clock is HSI.      */
-#define STM32_USART3SW_MASK     (3 << 18)   /**< USART3 clock source mask. */
-#define STM32_USART3SW_PCLK     (0 << 18)   /**< USART3 clock is PCLK.     */
-#define STM32_USART3SW_SYSCLK   (1 << 18)   /**< USART3 clock is SYSCLK.   */
-#define STM32_USART3SW_LSE      (2 << 18)   /**< USART3 clock is LSE.      */
-#define STM32_USART3SW_HSI      (3 << 18)   /**< USART3 clock is HSI.      */
-#define STM32_UART4SW_MASK      (3 << 20)   /**< USART4 clock source mask. */
-#define STM32_UART4SW_PCLK      (0 << 20)   /**< USART4 clock is PCLK.     */
-#define STM32_UART4SW_SYSCLK    (1 << 20)   /**< USART4 clock is SYSCLK.   */
-#define STM32_UART4SW_LSE       (2 << 20)   /**< USART4 clock is LSE.      */
-#define STM32_UART4SW_HSI       (3 << 20)   /**< USART4 clock is HSI.      */
-#define STM32_UART5SW_MASK      (3 << 22)   /**< USART5 clock source mask. */
-#define STM32_UART5SW_PCLK      (0 << 22)   /**< USART5 clock is PCLK.     */
-#define STM32_UART5SW_SYSCLK    (1 << 22)   /**< USART5 clock is SYSCLK.   */
-#define STM32_UART5SW_LSE       (2 << 22)   /**< USART5 clock is LSE.      */
-#define STM32_UART5SW_HSI       (3 << 22)   /**< USART5 clock is HSI.      */
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   Disables the PWR/RCC initialization in the HAL.
- */
-#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
-#define STM32_NO_INIT                       FALSE
-#endif
-
-/**
- * @brief   Enables or disables the programmable voltage detector.
- */
-#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
-#define STM32_PVD_ENABLE                    FALSE
-#endif
-
-/**
- * @brief   Sets voltage level for programmable voltage detector.
- */
-#if !defined(STM32_PLS) || defined(__DOXYGEN__)
-#define STM32_PLS                           STM32_PLS_LEV0
-#endif
-
-/**
- * @brief   Enables or disables the HSI clock source.
- */
-#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
-#define STM32_HSI_ENABLED                   TRUE
-#endif
-
-/**
- * @brief   Enables or disables the LSI clock source.
- */
-#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
-#define STM32_LSI_ENABLED                   TRUE
-#endif
-
-/**
- * @brief   Enables or disables the HSE clock source.
- */
-#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
-#define STM32_HSE_ENABLED                   TRUE
-#endif
-
-/**
- * @brief   Enables or disables the LSE clock source.
- */
-#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
-#define STM32_LSE_ENABLED                   FALSE
-#endif
-
-/**
- * @brief   Main clock source selection.
- * @note    If the selected clock source is not the PLL then the PLL is not
- *          initialized and started.
- * @note    The default value is calculated for a 72MHz system clock from
- *          a 8MHz crystal using the PLL.
- */
-#if !defined(STM32_SW) || defined(__DOXYGEN__)
-#define STM32_SW                            STM32_SW_PLL
-#endif
-
-/**
- * @brief   Clock source for the PLL.
- * @note    This setting has only effect if the PLL is selected as the
- *          system clock source.
- * @note    The default value is calculated for a 72MHz system clock from
- *          a 8MHz crystal using the PLL.
- */
-#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
-#define STM32_PLLSRC                        STM32_PLLSRC_HSE
-#endif
-
-/**
- * @brief   Crystal PLL pre-divider.
- * @note    This setting has only effect if the PLL is selected as the
- *          system clock source.
- * @note    The default value is calculated for a 72MHz system clock from
- *          a 8MHz crystal using the PLL.
- */
-#if !defined(STM32_PREDIV_VALUE) || defined(__DOXYGEN__)
-#define STM32_PREDIV_VALUE                  1
-#endif
-
-/**
- * @brief   PLL multiplier value.
- * @note    The allowed range is 2...16.
- * @note    The default value is calculated for a 72MHz system clock from
- *          a 8MHz crystal using the PLL.
- */
-#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
-#define STM32_PLLMUL_VALUE                  9
-#endif
-
-/**
- * @brief   AHB prescaler value.
- * @note    The default value is calculated for a 72MHz system clock from
- *          a 8MHz crystal using the PLL.
- */
-#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
-#define STM32_HPRE                          STM32_HPRE_DIV1
-#endif
-
-/**
- * @brief   APB1 prescaler value.
- */
-#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
-#define STM32_PPRE1                         STM32_PPRE1_DIV2
-#endif
-
-/**
- * @brief   APB2 prescaler value.
- */
-#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
-#define STM32_PPRE2                         STM32_PPRE2_DIV2
-#endif
-
-/**
- * @brief   MCO pin setting.
- */
-#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
-#define STM32_MCOSEL                        STM32_MCOSEL_NOCLOCK
-#endif
-
-/**
- * @brief   ADC12 prescaler value.
- */
-#if !defined(STM32_ADC12PRES) || defined(__DOXYGEN__)
-#define STM32_ADC12PRES                     STM32_ADC12PRES_DIV1
-#endif
-
-/**
- * @brief   ADC34 prescaler value.
- */
-#if !defined(STM32_ADC34PRES) || defined(__DOXYGEN__)
-#define STM32_ADC34PRES                     STM32_ADC34PRES_DIV1
-#endif
-
-/**
- * @brief   USART1 clock source.
- */
-#if !defined(STM32_USART1SW) || defined(__DOXYGEN__)
-#define STM32_USART1SW                      STM32_USART1SW_PCLK
-#endif
-
-/**
- * @brief   USART2 clock source.
- */
-#if !defined(STM32_USART2SW) || defined(__DOXYGEN__)
-#define STM32_USART2SW                      STM32_USART2SW_PCLK
-#endif
-
-/**
- * @brief   USART3 clock source.
- */
-#if !defined(STM32_USART3SW) || defined(__DOXYGEN__)
-#define STM32_USART3SW                      STM32_USART3SW_PCLK
-#endif
-
-/**
- * @brief   UART4 clock source.
- */
-#if !defined(STM32_UART4SW) || defined(__DOXYGEN__)
-#define STM32_UART4SW                       STM32_UART4SW_PCLK
-#endif
-
-/**
- * @brief   UART5 clock source.
- */
-#if !defined(STM32_UART5SW) || defined(__DOXYGEN__)
-#define STM32_UART5SW                       STM32_UART5SW_PCLK
-#endif
-
-/**
- * @brief   I2C1 clock source.
- */
-#if !defined(STM32_I2C1SW) || defined(__DOXYGEN__)
-#define STM32_I2C1SW                        STM32_I2C1SW_SYSCLK
-#endif
-
-/**
- * @brief   I2C2 clock source.
- */
-#if !defined(STM32_I2C2SW) || defined(__DOXYGEN__)
-#define STM32_I2C2SW                        STM32_I2C2SW_SYSCLK
-#endif
-
-/**
- * @brief   TIM1 clock source.
- */
-#if !defined(STM32_TIM1SW) || defined(__DOXYGEN__)
-#define STM32_TIM1SW                        STM32_TIM1SW_PCLK2
-#endif
-
-/**
- * @brief   TIM8 clock source.
- */
-#if !defined(STM32_TIM8SW) || defined(__DOXYGEN__)
-#define STM32_TIM8SW                        STM32_TIM8SW_PCLK2
-#endif
-
-/**
- * @brief   RTC clock source.
- */
-#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
-#define STM32_RTCSEL                        STM32_RTCSEL_LSI
-#endif
-
-/**
- * @brief   USB clock setting.
- */
-#if !defined(STM32_USB_CLOCK_REQUIRED) || defined(__DOXYGEN__)
-#define STM32_USB_CLOCK_REQUIRED            TRUE
-#endif
-
-/**
- * @brief   USB prescaler initialization.
- */
-#if !defined(STM32_USBPRE) || defined(__DOXYGEN__)
-#define STM32_USBPRE                        STM32_USBPRE_DIV1P5
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*
- * Configuration-related checks.
- */
-#if !defined(STM32F30x_MCUCONF)
-#error "Using a wrong mcuconf.h file, STM32F30x_MCUCONF not defined"
-#endif
-
-/*
- * HSI related checks.
- */
-#if STM32_HSI_ENABLED
-#else /* !STM32_HSI_ENABLED */
-
-#if STM32_SW == STM32_SW_HSI
-#error "HSI not enabled, required by STM32_SW"
-#endif
-
-#if STM32_USART1SW == STM32_USART1SW_HSI
-#error "HSI not enabled, required by STM32_USART1SW"
-#endif
-
-#if STM32_USART2SW == STM32_USART2SW_HSI
-#error "HSI not enabled, required by STM32_USART2SW"
-#endif
-
-#if STM32_USART3SW == STM32_USART3SW_HSI
-#error "HSI not enabled, required by STM32_USART3SW"
-#endif
-
-#if STM32_UART4SW == STM32_UART4SW_HSI
-#error "HSI not enabled, required by STM32_UART4SW"
-#endif
-
-#if STM32_UART5SW == STM32_UART5SW_HSI
-#error "HSI not enabled, required by STM32_UART5SW"
-#endif
-
-#if STM32_I2C1SW == STM32_I2C1SW_HSI
-#error "HSI not enabled, required by STM32_I2C1SW"
-#endif
-
-#if STM32_I2C2SW == STM32_I2C2SW_HSI
-#error "HSI not enabled, required by STM32_I2C2SW"
-#endif
-
-#if STM32_TIM1SW == STM32_TIM1SW_HSI
-#error "HSI not enabled, required by STM32_TIM1SW"
-#endif
-
-#if STM32_TIM8SW == STM32_TIM8SW_HSI
-#error "HSI not enabled, required by STM32_TIM8SW"
-#endif
-
-#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
-#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
-#endif
-
-#if (STM32_MCOSEL == STM32_MCOSEL_HSI) ||                                   \
-    ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) &&                              \
-     (STM32_PLLSRC == STM32_PLLSRC_HSI))
-#error "HSI not enabled, required by STM32_MCOSEL"
-#endif
-
-#endif /* !STM32_HSI_ENABLED */
-
-/*
- * HSE related checks.
- */
-#if STM32_HSE_ENABLED
-
-#if STM32_HSECLK == 0
-#error "HSE frequency not defined"
-#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
-#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
-#endif
-
-#else /* !STM32_HSE_ENABLED */
-
-#if STM32_SW == STM32_SW_HSE
-#error "HSE not enabled, required by STM32_SW"
-#endif
-
-#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
-#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
-#endif
-
-#if (STM32_MCOSEL == STM32_MCOSEL_HSE) ||                                   \
-    ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) &&                              \
-     (STM32_PLLSRC == STM32_PLLSRC_HSE))
-#error "HSE not enabled, required by STM32_MCOSEL"
-#endif
-
-#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
-#error "HSE not enabled, required by STM32_RTCSEL"
-#endif
-
-#endif /* !STM32_HSE_ENABLED */
-
-/*
- * LSI related checks.
- */
-#if STM32_LSI_ENABLED
-#else /* !STM32_LSI_ENABLED */
-
-#if STM32_RTCSEL == STM32_RTCSEL_LSI
-#error "LSI not enabled, required by STM32_RTCSEL"
-#endif
-
-#endif /* !STM32_LSI_ENABLED */
-
-/*
- * LSE related checks.
- */
-#if STM32_LSE_ENABLED
-
-#if !defined(STM32_LSECLK) || (STM32_LSECLK == 0)
-#error "STM32_LSECLK not defined"
-#endif
-
-#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
-#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
-#endif
-
-#if !defined(STM32_LSEDRV)
-#error "STM32_LSEDRV not defined"
-#endif
-
-#if (STM32_LSEDRV >> 3) > 3
-#error "STM32_LSEDRV outside acceptable range ((0<<3)...(3<<3))"
-#endif
-
-#if STM32_USART1SW == STM32_USART1SW_LSE
-#error "LSE not enabled, required by STM32_USART1SW"
-#endif
-
-#if STM32_USART2SW == STM32_USART2SW_LSE
-#error "LSE not enabled, required by STM32_USART2SW"
-#endif
-
-#if STM32_USART3SW == STM32_USART3SW_LSE
-#error "LSE not enabled, required by STM32_USART3SW"
-#endif
-
-#if STM32_UART4SW == STM32_UART4SW_LSE
-#error "LSE not enabled, required by STM32_UART4SW"
-#endif
-
-#if STM32_UART5SW == STM32_UART5SW_LSE
-#error "LSE not enabled, required by STM32_UART5SW"
-#endif
-
-#else /* !STM32_LSE_ENABLED */
-
-#if STM32_RTCSEL == STM32_RTCSEL_LSE
-#error "LSE not enabled, required by STM32_RTCSEL"
-#endif
-
-#endif /* !STM32_LSE_ENABLED */
-
-/* PLL activation conditions.*/
-#if (STM32_SW == STM32_SW_PLL) ||                                           \
-    (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) ||                               \
-    (STM32_TIM1SW == STM32_TIM1SW_PLLX2) ||                                 \
-    (STM32_TIM8SW == STM32_TIM8SW_PLLX2) ||                                 \
-    (STM32_ADC12PRES != STM32_ADC12PRES_NOCLOCK) ||                         \
-    (STM32_ADC34PRES != STM32_ADC34PRES_NOCLOCK) ||                         \
-    STM32_USB_CLOCK_REQUIRED ||                                             \
-    defined(__DOXYGEN__)
-/**
- * @brief   PLL activation flag.
- */
-#define STM32_ACTIVATE_PLL          TRUE
-#else
-#define STM32_ACTIVATE_PLL          FALSE
-#endif
-
-/* HSE prescaler setting check.*/
-#if ((STM32_PREDIV_VALUE >= 1) || (STM32_PREDIV_VALUE <= 16))
-#define STM32_PREDIV                ((STM32_PREDIV_VALUE - 1) << 0)
-#else
-#error "invalid STM32_PREDIV value specified"
-#endif
-
-/**
- * @brief   PLLMUL field.
- */
-#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) ||            \
-    defined(__DOXYGEN__)
-#define STM32_PLLMUL                ((STM32_PLLMUL_VALUE - 2) << 18)
-#else
-#error "invalid STM32_PLLMUL_VALUE value specified"
-#endif
-
-/**
- * @brief   PLL input clock frequency.
- */
-#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
-#define STM32_PLLCLKIN              (STM32_HSECLK / STM32_PREDIV_VALUE)
-#elif STM32_PLLSRC == STM32_PLLSRC_HSI
-#define STM32_PLLCLKIN              (STM32_HSICLK / 2)
-#else
-#error "invalid STM32_PLLSRC value specified"
-#endif
-
-/* PLL input frequency range check.*/
-#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
-#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
-#endif
-
-/**
- * @brief   PLL output clock frequency.
- */
-#define STM32_PLLCLKOUT             (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
-
-/* PLL output frequency range check.*/
-#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX)
-#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
-#endif
-
-/**
- * @brief   System clock source.
- */
-#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)
-#define STM32_SYSCLK                STM32_PLLCLKOUT
-#elif (STM32_SW == STM32_SW_HSI)
-#define STM32_SYSCLK                STM32_HSICLK
-#elif (STM32_SW == STM32_SW_HSE)
-#define STM32_SYSCLK                STM32_HSECLK
-#else
-#error "invalid STM32_SW value specified"
-#endif
-
-/* Check on the system clock.*/
-#if STM32_SYSCLK > STM32_SYSCLK_MAX
-#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
-#endif
-
-/**
- * @brief   AHB frequency.
- */
-#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
-#define STM32_HCLK                  (STM32_SYSCLK / 1)
-#elif STM32_HPRE == STM32_HPRE_DIV2
-#define STM32_HCLK                  (STM32_SYSCLK / 2)
-#elif STM32_HPRE == STM32_HPRE_DIV4
-#define STM32_HCLK                  (STM32_SYSCLK / 4)
-#elif STM32_HPRE == STM32_HPRE_DIV8
-#define STM32_HCLK                  (STM32_SYSCLK / 8)
-#elif STM32_HPRE == STM32_HPRE_DIV16
-#define STM32_HCLK                  (STM32_SYSCLK / 16)
-#elif STM32_HPRE == STM32_HPRE_DIV64
-#define STM32_HCLK                  (STM32_SYSCLK / 64)
-#elif STM32_HPRE == STM32_HPRE_DIV128
-#define STM32_HCLK                  (STM32_SYSCLK / 128)
-#elif STM32_HPRE == STM32_HPRE_DIV256
-#define STM32_HCLK                  (STM32_SYSCLK / 256)
-#elif STM32_HPRE == STM32_HPRE_DIV512
-#define STM32_HCLK                  (STM32_SYSCLK / 512)
-#else
-#error "invalid STM32_HPRE value specified"
-#endif
-
-/* AHB frequency check.*/
-#if STM32_HCLK > STM32_SYSCLK_MAX
-#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
-#endif
-
-/**
- * @brief   APB1 frequency.
- */
-#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
-#define STM32_PCLK1                  (STM32_HCLK / 1)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV2
-#define STM32_PCLK1                  (STM32_HCLK / 2)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV4
-#define STM32_PCLK1                  (STM32_HCLK / 4)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV8
-#define STM32_PCLK1                  (STM32_HCLK / 8)
-#elif STM32_PPRE1 == STM32_PPRE1_DIV16
-#define STM32_PCLK1                  (STM32_HCLK / 16)
-#else
-#error "invalid STM32_PPRE1 value specified"
-#endif
-
-/* APB1 frequency check.*/
-#if STM32_PCLK1 > STM32_PCLK1_MAX
-#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
-#endif
-
-/**
- * @brief   APB2 frequency.
- */
-#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
-#define STM32_PCLK2                  (STM32_HCLK / 1)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV2
-#define STM32_PCLK2                  (STM32_HCLK / 2)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV4
-#define STM32_PCLK2                  (STM32_HCLK / 4)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV8
-#define STM32_PCLK2                  (STM32_HCLK / 8)
-#elif STM32_PPRE2 == STM32_PPRE2_DIV16
-#define STM32_PCLK2                  (STM32_HCLK / 16)
-#else
-#error "invalid STM32_PPRE2 value specified"
-#endif
-
-/* APB2 frequency check.*/
-#if STM32_PCLK2 > STM32_PCLK2_MAX
-#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
-#endif
-
-/**
- * @brief   RTC clock.
- */
-#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__)
-#define STM32_RTCCLK                STM32_LSECLK
-#elif STM32_RTCSEL == STM32_RTCSEL_LSI
-#define STM32_RTCCLK                STM32_LSICLK
-#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
-#define STM32_RTCCLK                (STM32_HSECLK / 32)
-#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
-#define STM32_RTCCLK                0
-#else
-#error "invalid source selected for RTC clock"
-#endif
-
-/**
- * @brief   ADC12 frequency.
- */
-#if (STM32_ADC12PRES == STM32_ADC12PRES_NOCLOCK) || defined(__DOXYGEN__)
-#define STM32_ADC12CLK              0
-#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV1
-#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 1)
-#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV2
-#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 2)
-#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV4
-#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 4)
-#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV6
-#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 6)
-#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV8
-#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 8)
-#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV10
-#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 10)
-#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV12
-#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 12)
-#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV16
-#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 16)
-#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV32
-#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 32)
-#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV64
-#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 64)
-#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV128
-#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 128)
-#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV256
-#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 256)
-#else
-#error "invalid STM32_ADC12PRES value specified"
-#endif
-
-/**
- * @brief   ADC34 frequency.
- */
-#if (STM32_ADC43PRES == STM32_ADC34PRES_NOCLOCK) || defined(__DOXYGEN__)
-#define STM32_ADC34CLK              0
-#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV1
-#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 1)
-#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV2
-#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 2)
-#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV4
-#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 4)
-#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV6
-#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 6)
-#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV8
-#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 8)
-#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV10
-#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 10)
-#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV12
-#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 12)
-#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV16
-#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 16)
-#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV32
-#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 32)
-#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV64
-#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 64)
-#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV128
-#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 128)
-#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV256
-#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 256)
-#else
-#error "invalid STM32_ADC34PRES value specified"
-#endif
-
-/* ADC12 frequency check.*/
-#if STM32_ADC12CLK > STM32_ADCCLK_MAX
-#error "STM32_ADC12CLK exceeding maximum frequency (STM32_ADCCLK_MAX)"
-#endif
-
-/* ADC34 frequency check.*/
-#if STM32_ADC34CLK > STM32_ADCCLK_MAX
-#error "STM32_ADC34CLK exceeding maximum frequency (STM32_ADCCLK_MAX)"
-#endif
-
-/**
- * @brief   I2C1 frequency.
- */
-#if STM32_I2C1SW == STM32_I2C1SW_HSI
-#define STM32_I2C1CLK               STM32_HSICLK
-#elif STM32_I2C1SW == STM32_I2C1SW_SYSCLK
-#define STM32_I2C1CLK               STM32_SYSCLK
-#else
-#error "invalid source selected for I2C1 clock"
-#endif
-
-/**
- * @brief   I2C2 frequency.
- */
-#if STM32_I2C2SW == STM32_I2C2SW_HSI
-#define STM32_I2C2CLK               STM32_HSICLK
-#elif STM32_I2C2SW == STM32_I2C2SW_SYSCLK
-#define STM32_I2C2CLK               STM32_SYSCLK
-#else
-#error "invalid source selected for I2C2 clock"
-#endif
-
-/**
- * @brief   USART1 frequency.
- */
-#if STM32_USART1SW == STM32_USART1SW_PCLK
-#define STM32_USART1CLK             STM32_PCLK2
-#elif STM32_USART1SW == STM32_USART1SW_SYSCLK
-#define STM32_USART1CLK             STM32_SYSCLK
-#elif STM32_USART1SW == STM32_USART1SW_LSECLK
-#define STM32_USART1CLK             STM32_LSECLK
-#elif STM32_USART1SW == STM32_USART1SW_HSICLK
-#define STM32_USART1CLK             STM32_HSICLK
-#else
-#error "invalid source selected for USART1 clock"
-#endif
-
-/**
- * @brief   USART2 frequency.
- */
-#if STM32_USART2SW == STM32_USART2SW_PCLK
-#define STM32_USART2CLK             STM32_PCLK1
-#elif STM32_USART2SW == STM32_USART2SW_SYSCLK
-#define STM32_USART2CLK             STM32_SYSCLK
-#elif STM32_USART2SW == STM32_USART2SW_LSECLK
-#define STM32_USART2CLK             STM32_LSECLK
-#elif STM32_USART2SW == STM32_USART2SW_HSICLK
-#define STM32_USART2CLK             STM32_HSICLK
-#else
-#error "invalid source selected for USART2 clock"
-#endif
-
-/**
- * @brief   USART3 frequency.
- */
-#if STM32_USART3SW == STM32_USART3SW_PCLK
-#define STM32_USART3CLK             STM32_PCLK1
-#elif STM32_USART3SW == STM32_USART3SW_SYSCLK
-#define STM32_USART3CLK             STM32_SYSCLK
-#elif STM32_USART3SW == STM32_USART3SW_LSECLK
-#define STM32_USART3CLK             STM32_LSECLK
-#elif STM32_USART3SW == STM32_USART3SW_HSICLK
-#define STM32_USART3CLK             STM32_HSICLK
-#else
-#error "invalid source selected for USART3 clock"
-#endif
-
-/**
- * @brief   UART4 frequency.
- */
-#if STM32_UART4SW == STM32_UART4SW_PCLK
-#define STM32_UART4CLK             STM32_PCLK1
-#elif STM32_UART4SW == STM32_UART4SW_SYSCLK
-#define STM32_UART4CLK             STM32_SYSCLK
-#elif STM32_UART4SW == STM32_UART4SW_LSECLK
-#define STM32_UART4CLK             STM32_LSECLK
-#elif STM32_UART4SW == STM32_UART4SW_HSICLK
-#define STM32_UART4CLK             STM32_HSICLK
-#else
-#error "invalid source selected for UART4 clock"
-#endif
-
-/**
- * @brief   UART5 frequency.
- */
-#if STM32_UART5SW == STM32_UART5SW_PCLK
-#define STM32_UART5CLK             STM32_PCLK1
-#elif STM32_UART5SW == STM32_UART5SW_SYSCLK
-#define STM32_UART5CLK             STM32_SYSCLK
-#elif STM32_UART5SW == STM32_UART5SW_LSECLK
-#define STM32_UART5CLK             STM32_LSECLK
-#elif STM32_UART5SW == STM32_UART5SW_HSICLK
-#define STM32_UART5CLK             STM32_HSICLK
-#else
-#error "invalid source selected for UART5 clock"
-#endif
-
-/**
- * @brief   TIM1 frequency.
- */
-#if STM32_TIM1SW == STM32_TIM1SW_PCLK2
-#define STM32_TIM1CLK               STM32_PCLK2
-
-#elif STM32_TIM1SW == STM32_TIM1SW_PLLX2
-#if (STM32_SW != STM32_SW_PLL) ||                                           \
-    (STM32_HPRE != STM32_HPRE_DIV1) ||                                      \
-    (STM32_PPRE2 != STM32_PPRE2_DIV1)
-#error "double clock mode cannot be activated for TIM1 under the current settings"
-#endif
-#define STM32_TIM1CLK               (STM32_PLLCLKOUT * 2)
-
-#else
-#error "invalid source selected for TIM1 clock"
-#endif
-
-/**
- * @brief   TIM8 frequency.
- */
-#if STM32_TIM8SW == STM32_TIM8SW_PCLK2
-#define STM32_TIM8CLK               STM32_PCLK2
-
-#elif STM32_TIM8SW == STM32_TIM8SW_PLLX2
-#if (STM32_SW != STM32_SW_PLL) ||                                           \
-    (STM32_HPRE != STM32_HPRE_DIV1) ||                                      \
-    (STM32_PPRE2 != STM32_PPRE2_DIV1)
-#error "double clock mode cannot be activated for TIM8 under the current settings"
-#endif
-#define STM32_TIM8CLK               (STM32_PLLCLKOUT * 2)
-
-#else
-#error "invalid source selected for TIM8 clock"
-#endif
-
-/**
- * @brief   Timers 2, 3, 4, 6, 7 frequency.
- */
-#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
-#define STM32_TIMCLK1               (STM32_PCLK1 * 1)
-#else
-#define STM32_TIMCLK1               (STM32_PCLK1 * 2)
-#endif
-
-/**
- * @brief   Timers 1, 8, 15, 16, 17 frequency.
- */
-#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
-#define STM32_TIMCLK2               (STM32_PCLK2 * 1)
-#else
-#define STM32_TIMCLK2               (STM32_PCLK2 * 2)
-#endif
-
-/**
- * @brief   USB frequency.
- */
-#if (STM32_USBPRE == STM32_USBPRE_DIV1P5) || defined(__DOXYGEN__)
-#define STM32_USBCLK                ((STM32_PLLCLKOUT * 2) / 3)
-#elif (STM32_USBPRE == STM32_USBPRE_DIV1)
-#define STM32_USBCLK                STM32_PLLCLKOUT
-#else
-#error "invalid STM32_USBPRE value specified"
-#endif
-
-/**
- * @brief   Flash settings.
- */
-#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__)
-#define STM32_FLASHBITS             0x00000010
-#elif STM32_HCLK <= 48000000
-#define STM32_FLASHBITS             0x00000011
-#else
-#define STM32_FLASHBITS             0x00000012
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-/* Various helpers.*/
-#include "nvic.h"
-#include "stm32_isr.h"
-#include "stm32_dma.h"
-#include "stm32_rcc.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void hal_lld_init(void);
-  void stm32_clock_init(void);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _HAL_LLD_H_ */
-
-/** @} */
diff --git a/os/hal/ports/STM32/STM32F30x/platform.mk b/os/hal/ports/STM32/STM32F30x/platform.mk
deleted file mode 100644
index f24aee535..000000000
--- a/os/hal/ports/STM32/STM32F30x/platform.mk
+++ /dev/null
@@ -1,31 +0,0 @@
-# List of all the STM32F30x platform files.
-PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
-              ${CHIBIOS}/os/hal/ports/STM32/STM32F30x/stm32_dma.c \
-              ${CHIBIOS}/os/hal/ports/STM32/STM32F30x/hal_lld.c \
-              ${CHIBIOS}/os/hal/ports/STM32/STM32F30x/adc_lld.c \
-              ${CHIBIOS}/os/hal/ports/STM32/STM32F30x/ext_lld_isr.c \
-              ${CHIBIOS}/os/hal/ports/STM32/LLD/can_lld.c \
-              ${CHIBIOS}/os/hal/ports/STM32/LLD/ext_lld.c \
-              ${CHIBIOS}/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c \
-              ${CHIBIOS}/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.c \
-              ${CHIBIOS}/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c \
-              ${CHIBIOS}/os/hal/ports/STM32/LLD/SPIv2/spi_lld.c \
-              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c \
-              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c \
-              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c \
-              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1/st_lld.c \
-              ${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv2/serial_lld.c \
-              ${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv2/uart_lld.c \
-              ${CHIBIOS}/os/hal/ports/STM32/LLD/USBv1/usb_lld.c
-
-# Required include directories
-PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
-              ${CHIBIOS}/os/hal/ports/STM32/STM32F30x \
-              ${CHIBIOS}/os/hal/ports/STM32/LLD \
-              ${CHIBIOS}/os/hal/ports/STM32/LLD/GPIOv2 \
-              ${CHIBIOS}/os/hal/ports/STM32/LLD/I2Cv2 \
-              ${CHIBIOS}/os/hal/ports/STM32/LLD/RTCv2 \
-              ${CHIBIOS}/os/hal/ports/STM32/LLD/SPIv2 \
-              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1 \
-              ${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv2 \
-              ${CHIBIOS}/os/hal/ports/STM32/LLD/USBv1
diff --git a/os/hal/ports/STM32/STM32F30x/stm32_dma.c b/os/hal/ports/STM32/STM32F30x/stm32_dma.c
deleted file mode 100644
index 6794e5992..000000000
--- a/os/hal/ports/STM32/STM32F30x/stm32_dma.c
+++ /dev/null
@@ -1,449 +0,0 @@
-/*
-    ChibiOS/HAL - Copyright (C) 2006-2014 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F30x/stm32_dma.c
- * @brief   DMA helper driver code.
- *
- * @addtogroup STM32F30x_DMA
- * @details DMA sharing helper driver. In the STM32 the DMA streams are a
- *          shared resource, this driver allows to allocate and free DMA
- *          streams at runtime in order to allow all the other device
- *          drivers to coordinate the access to the resource.
- * @note    The DMA ISR handlers are all declared into this module because
- *          sharing, the various device drivers can associate a callback to
- *          ISRs when allocating streams.
- * @{
- */
-
-#include "hal.h"
-
-/* The following macro is only defined if some driver requiring DMA services
-   has been enabled.*/
-#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/**
- * @brief   Mask of the DMA1 streams in @p dma_streams_mask.
- */
-#define STM32_DMA1_STREAMS_MASK     0x0000007F
-
-/**
- * @brief   Mask of the DMA2 streams in @p dma_streams_mask.
- */
-#define STM32_DMA2_STREAMS_MASK     0x00000F80
-
-/**
- * @brief   Post-reset value of the stream CCR register.
- */
-#define STM32_DMA_CCR_RESET_VALUE   0x00000000
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   DMA streams descriptors.
- * @details This table keeps the association between an unique stream
- *          identifier and the involved physical registers.
- * @note    Don't use this array directly, use the appropriate wrapper macros
- *          instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc.
- */
-const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
-  {DMA1_Channel1, &DMA1->IFCR, 0, 0, DMA1_Channel1_IRQn},
-  {DMA1_Channel2, &DMA1->IFCR, 4, 1, DMA1_Channel2_IRQn},
-  {DMA1_Channel3, &DMA1->IFCR, 8, 2, DMA1_Channel3_IRQn},
-  {DMA1_Channel4, &DMA1->IFCR, 12, 3, DMA1_Channel4_IRQn},
-  {DMA1_Channel5, &DMA1->IFCR, 16, 4, DMA1_Channel5_IRQn},
-  {DMA1_Channel6, &DMA1->IFCR, 20, 5, DMA1_Channel6_IRQn},
-  {DMA1_Channel7, &DMA1->IFCR, 24, 6, DMA1_Channel7_IRQn},
-  {DMA2_Channel1, &DMA2->IFCR, 0, 7, DMA2_Channel1_IRQn},
-  {DMA2_Channel2, &DMA2->IFCR, 4, 8, DMA2_Channel2_IRQn},
-  {DMA2_Channel3, &DMA2->IFCR, 8, 9, DMA2_Channel3_IRQn},
-  {DMA2_Channel4, &DMA2->IFCR, 12, 10, DMA2_Channel4_IRQn},
-  {DMA2_Channel5, &DMA2->IFCR, 16, 11, DMA2_Channel5_IRQn},
-};
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   DMA ISR redirector type.
- */
-typedef struct {
-  stm32_dmaisr_t        dma_func;       /**< @brief DMA callback function.  */
-  void                  *dma_param;     /**< @brief DMA callback parameter. */
-} dma_isr_redir_t;
-
-/**
- * @brief   Mask of the allocated streams.
- */
-static uint32_t dma_streams_mask;
-
-/**
- * @brief   DMA IRQ redirectors.
- */
-static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   DMA1 stream 1 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector6C) {
-  uint32_t flags;
-
-  OSAL_IRQ_PROLOGUE();
-
-  flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = flags << 0;
-  if (dma_isr_redir[0].dma_func)
-    dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 2 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector70) {
-  uint32_t flags;
-
-  OSAL_IRQ_PROLOGUE();
-
-  flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = flags << 4;
-  if (dma_isr_redir[1].dma_func)
-    dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 3 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector74) {
-  uint32_t flags;
-
-  OSAL_IRQ_PROLOGUE();
-
-  flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = flags << 8;
-  if (dma_isr_redir[2].dma_func)
-    dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 4 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector78) {
-  uint32_t flags;
-
-  OSAL_IRQ_PROLOGUE();
-
-  flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = flags << 12;
-  if (dma_isr_redir[3].dma_func)
-    dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 5 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector7C) {
-  uint32_t flags;
-
-  OSAL_IRQ_PROLOGUE();
-
-  flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = flags << 16;
-  if (dma_isr_redir[4].dma_func)
-    dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 6 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector80) {
-  uint32_t flags;
-
-  OSAL_IRQ_PROLOGUE();
-
-  flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = flags << 20;
-  if (dma_isr_redir[5].dma_func)
-    dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA1 stream 7 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector84) {
-  uint32_t flags;
-
-  OSAL_IRQ_PROLOGUE();
-
-  flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK;
-  DMA1->IFCR = flags << 24;
-  if (dma_isr_redir[6].dma_func)
-    dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA2 stream 1 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector120) {
-  uint32_t flags;
-
-  OSAL_IRQ_PROLOGUE();
-
-  flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = flags << 0;
-  if (dma_isr_redir[7].dma_func)
-    dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA2 stream 2 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector124) {
-  uint32_t flags;
-
-  OSAL_IRQ_PROLOGUE();
-
-  flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = flags << 4;
-  if (dma_isr_redir[8].dma_func)
-    dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA2 stream 3 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector128) {
-  uint32_t flags;
-
-  OSAL_IRQ_PROLOGUE();
-
-  flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = flags << 8;
-  if (dma_isr_redir[9].dma_func)
-    dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA2 stream 4 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector12C) {
-  uint32_t flags;
-
-  OSAL_IRQ_PROLOGUE();
-
-  flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = flags << 12;
-  if (dma_isr_redir[10].dma_func)
-    dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   DMA2 stream 5 shared interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(Vector130) {
-  uint32_t flags;
-
-  OSAL_IRQ_PROLOGUE();
-
-  flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK;
-  DMA2->IFCR = flags << 16;
-  if (dma_isr_redir[11].dma_func)
-    dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   STM32 DMA helper initialization.
- *
- * @init
- */
-void dmaInit(void) {
-  int i;
-
-  dma_streams_mask = 0;
-  for (i = 0; i < STM32_DMA_STREAMS; i++) {
-    _stm32_dma_streams[i].channel->CCR = 0;
-    dma_isr_redir[i].dma_func = NULL;
-  }
-  DMA1->IFCR = 0xFFFFFFFF;
-#if STM32_HAS_DMA2
-  DMA2->IFCR = 0xFFFFFFFF;
-#endif
-}
-
-/**
- * @brief   Allocates a DMA stream.
- * @details The stream is allocated and, if required, the DMA clock enabled.
- *          The function also enables the IRQ vector associated to the stream
- *          and initializes its priority.
- * @pre     The stream must not be already in use or an error is returned.
- * @post    The stream is allocated and the default ISR handler redirected
- *          to the specified function.
- * @post    The stream ISR vector is enabled and its priority configured.
- * @post    The stream must be freed using @p dmaStreamRelease() before it can
- *          be reused with another peripheral.
- * @post    The stream is in its post-reset state.
- * @note    This function can be invoked in both ISR or thread context.
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] priority  IRQ priority mask for the DMA stream
- * @param[in] func      handling function pointer, can be @p NULL
- * @param[in] param     a parameter to be passed to the handling function
- * @return              The operation status.
- * @retval FALSE        no error, stream taken.
- * @retval TRUE         error, stream already taken.
- *
- * @special
- */
-bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
-                       uint32_t priority,
-                       stm32_dmaisr_t func,
-                       void *param) {
-
-  osalDbgCheck(dmastp != NULL);
-
-  /* Checks if the stream is already taken.*/
-  if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)
-    return TRUE;
-
-  /* Marks the stream as allocated.*/
-  dma_isr_redir[dmastp->selfindex].dma_func  = func;
-  dma_isr_redir[dmastp->selfindex].dma_param = param;
-  dma_streams_mask |= (1 << dmastp->selfindex);
-
-  /* Enabling DMA clocks required by the current streams set.*/
-  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0)
-    rccEnableDMA1(FALSE);
-#if STM32_HAS_DMA2
-  if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0)
-    rccEnableDMA2(FALSE);
-#endif
-
-  /* Putting the stream in a safe state.*/
-  dmaStreamDisable(dmastp);
-  dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE;
-
-  /* Enables the associated IRQ vector if a callback is defined.*/
-  if (func != NULL)
-    nvicEnableVector(dmastp->vector, priority);
-
-  return FALSE;
-}
-
-/**
- * @brief   Releases a DMA stream.
- * @details The stream is freed and, if required, the DMA clock disabled.
- *          Trying to release a unallocated stream is an illegal operation
- *          and is trapped if assertions are enabled.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    The stream is again available.
- * @note    This function can be invoked in both ISR or thread context.
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
-
-  osalDbgCheck(dmastp != NULL);
-
-  /* Check if the streams is not taken.*/
-  osalDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
-                "not allocated");
-
-  /* Disables the associated IRQ vector.*/
-  nvicDisableVector(dmastp->vector);
-
-  /* Marks the stream as not allocated.*/
-  dma_streams_mask &= ~(1 << dmastp->selfindex);
-
-  /* Shutting down clocks that are no more required, if any.*/
-  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0)
-    rccDisableDMA1(FALSE);
-#if STM32_HAS_DMA2
-  if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0)
-    rccDisableDMA2(FALSE);
-#endif
-}
-
-#endif /* STM32_DMA_REQUIRED */
-
-/** @} */
diff --git a/os/hal/ports/STM32/STM32F30x/stm32_dma.h b/os/hal/ports/STM32/STM32F30x/stm32_dma.h
deleted file mode 100644
index 4c3d4284c..000000000
--- a/os/hal/ports/STM32/STM32F30x/stm32_dma.h
+++ /dev/null
@@ -1,406 +0,0 @@
-/*
-    ChibiOS/HAL - Copyright (C) 2006-2014 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F30x/stm32_dma.h
- * @brief   DMA helper driver header.
- * @note    This file requires definitions from the ST header file stm32f30x.h.
- * @note    This driver uses the new naming convention used for the STM32F2xx
- *          so the "DMA channels" are referred as "DMA streams".
- *
- * @addtogroup STM32F30x_DMA
- * @{
- */
-
-#ifndef _STM32_DMA_H_
-#define _STM32_DMA_H_
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Total number of DMA streams.
- * @note    This is the total number of streams among all the DMA units.
- */
-#if STM32_HAS_DMA2 || defined(__DOXYGEN__)
-#define STM32_DMA_STREAMS           12
-#else
-#define STM32_DMA_STREAMS           7
-#endif
-
-/**
- * @brief   Mask of the ISR bits passed to the DMA callback functions.
- */
-#define STM32_DMA_ISR_MASK          0x0F
-
-/**
- * @brief   Returns the channel associated to the specified stream.
- *
- * @param[in] n         the stream number (0...STM32_DMA_STREAMS-1)
- * @param[in] c         a stream/channel association word, one channel per
- *                      nibble, not associated channels must be set to 0xF
- * @return              Always zero, in this platform there is no dynamic
- *                      association between streams and channels.
- */
-#define STM32_DMA_GETCHANNEL(n, c)  0
-
-/**
- * @brief   Checks if a DMA priority is within the valid range.
- * @param[in] prio      DMA priority
- *
- * @retval              The check result.
- * @retval FALSE        invalid DMA priority.
- * @retval TRUE         correct DMA priority.
- */
-#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3))
-
-/**
- * @brief   Returns an unique numeric identifier for a DMA stream.
- *
- * @param[in] dma       the DMA unit number
- * @param[in] stream    the stream number
- * @return              An unique numeric stream identifier.
- */
-#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 7) + ((stream) - 1))
-
-/**
- * @brief   Returns a DMA stream identifier mask.
- *
- *
- * @param[in] dma       the DMA unit number
- * @param[in] stream    the stream number
- * @return              A DMA stream identifier mask.
- */
-#define STM32_DMA_STREAM_ID_MSK(dma, stream)                                \
-  (1 << STM32_DMA_STREAM_ID(dma, stream))
-
-/**
- * @brief   Checks if a DMA stream unique identifier belongs to a mask.
- * @param[in] id        the stream numeric identifier
- * @param[in] mask      the stream numeric identifiers mask
- *
- * @retval              The check result.
- * @retval FALSE        id does not belong to the mask.
- * @retval TRUE         id belongs to the mask.
- */
-#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask)))
-
-/**
- * @name    DMA streams identifiers
- * @{
- */
-/**
- * @brief   Returns a pointer to a stm32_dma_stream_t structure.
- *
- * @param[in] id        the stream numeric identifier
- * @return              A pointer to the stm32_dma_stream_t constant structure
- *                      associated to the DMA stream.
- */
-#define STM32_DMA_STREAM(id)        (&_stm32_dma_streams[id])
-
-#define STM32_DMA1_STREAM1          STM32_DMA_STREAM(0)
-#define STM32_DMA1_STREAM2          STM32_DMA_STREAM(1)
-#define STM32_DMA1_STREAM3          STM32_DMA_STREAM(2)
-#define STM32_DMA1_STREAM4          STM32_DMA_STREAM(3)
-#define STM32_DMA1_STREAM5          STM32_DMA_STREAM(4)
-#define STM32_DMA1_STREAM6          STM32_DMA_STREAM(5)
-#define STM32_DMA1_STREAM7          STM32_DMA_STREAM(6)
-#define STM32_DMA2_STREAM1          STM32_DMA_STREAM(7)
-#define STM32_DMA2_STREAM2          STM32_DMA_STREAM(8)
-#define STM32_DMA2_STREAM3          STM32_DMA_STREAM(9)
-#define STM32_DMA2_STREAM4          STM32_DMA_STREAM(10)
-#define STM32_DMA2_STREAM5          STM32_DMA_STREAM(11)
-/** @} */
-
-/**
- * @name    CR register constants common to all DMA types
- * @{
- */
-#define STM32_DMA_CR_EN             DMA_CCR_EN
-#define STM32_DMA_CR_TEIE           DMA_CCR_TEIE
-#define STM32_DMA_CR_HTIE           DMA_CCR_HTIE
-#define STM32_DMA_CR_TCIE           DMA_CCR_TCIE
-#define STM32_DMA_CR_DIR_MASK       (DMA_CCR_DIR | DMA_CCR_MEM2MEM)
-#define STM32_DMA_CR_DIR_P2M        0
-#define STM32_DMA_CR_DIR_M2P        DMA_CCR_DIR
-#define STM32_DMA_CR_DIR_M2M        DMA_CCR_MEM2MEM
-#define STM32_DMA_CR_CIRC           DMA_CCR_CIRC
-#define STM32_DMA_CR_PINC           DMA_CCR_PINC
-#define STM32_DMA_CR_MINC           DMA_CCR_MINC
-#define STM32_DMA_CR_PSIZE_MASK     DMA_CCR_PSIZE
-#define STM32_DMA_CR_PSIZE_BYTE     0
-#define STM32_DMA_CR_PSIZE_HWORD    DMA_CCR_PSIZE_0
-#define STM32_DMA_CR_PSIZE_WORD     DMA_CCR_PSIZE_1
-#define STM32_DMA_CR_MSIZE_MASK     DMA_CCR_MSIZE
-#define STM32_DMA_CR_MSIZE_BYTE     0
-#define STM32_DMA_CR_MSIZE_HWORD    DMA_CCR_MSIZE_0
-#define STM32_DMA_CR_MSIZE_WORD     DMA_CCR_MSIZE_1
-#define STM32_DMA_CR_SIZE_MASK      (STM32_DMA_CR_PSIZE_MASK |              \
-                                     STM32_DMA_CR_MSIZE_MASK)
-#define STM32_DMA_CR_PL_MASK        DMA_CCR_PL
-#define STM32_DMA_CR_PL(n)          ((n) << 12)
-/** @} */
-
-/**
- * @name    CR register constants only found in enhanced DMA
- * @{
- */
-#define STM32_DMA_CR_DMEIE          0   /**< @brief Ignored by normal DMA.  */
-#define STM32_DMA_CR_CHSEL_MASK     0   /**< @brief Ignored by normal DMA.  */
-#define STM32_DMA_CR_CHSEL(n)       0   /**< @brief Ignored by normal DMA.  */
-/** @} */
-
-/**
- * @name    Status flags passed to the ISR callbacks
- * @{
- */
-#define STM32_DMA_ISR_FEIF          0
-#define STM32_DMA_ISR_DMEIF         0
-#define STM32_DMA_ISR_TEIF          DMA_ISR_TEIF1
-#define STM32_DMA_ISR_HTIF          DMA_ISR_HTIF1
-#define STM32_DMA_ISR_TCIF          DMA_ISR_TCIF1
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   STM32 DMA stream descriptor structure.
- */
-typedef struct {
-  DMA_Channel_TypeDef   *channel;       /**< @brief Associated DMA channel. */
-  volatile uint32_t     *ifcr;          /**< @brief Associated IFCR reg.    */
-  uint8_t               ishift;         /**< @brief Bits offset in xIFCR
-                                             register.                      */
-  uint8_t               selfindex;      /**< @brief Index to self in array. */
-  uint8_t               vector;         /**< @brief Associated IRQ vector.  */
-} stm32_dma_stream_t;
-
-/**
- * @brief   STM32 DMA ISR function type.
- *
- * @param[in] p         parameter for the registered function
- * @param[in] flags     pre-shifted content of the ISR register, the bits
- *                      are aligned to bit zero
- */
-typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @name    Macro Functions
- * @{
- */
-/**
- * @brief   Associates a peripheral data register to a DMA stream.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] addr      value to be written in the CPAR register
- *
- * @special
- */
-#define dmaStreamSetPeripheral(dmastp, addr) {                              \
-  (dmastp)->channel->CPAR  = (uint32_t)(addr);                              \
-}
-
-/**
- * @brief   Associates a memory destination to a DMA stream.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] addr      value to be written in the CMAR register
- *
- * @special
- */
-#define dmaStreamSetMemory0(dmastp, addr) {                                 \
-  (dmastp)->channel->CMAR  = (uint32_t)(addr);                              \
-}
-
-/**
- * @brief   Sets the number of transfers to be performed.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] size      value to be written in the CNDTR register
- *
- * @special
- */
-#define dmaStreamSetTransactionSize(dmastp, size) {                         \
-  (dmastp)->channel->CNDTR  = (uint32_t)(size);                             \
-}
-
-/**
- * @brief   Returns the number of transfers to be performed.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @return              The number of transfers to be performed.
- *
- * @special
- */
-#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR))
-
-/**
- * @brief   Programs the stream mode settings.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] mode      value to be written in the CCR register
- *
- * @special
- */
-#define dmaStreamSetMode(dmastp, mode) {                                    \
-  (dmastp)->channel->CCR  = (uint32_t)(mode);                               \
-}
-
-/**
- * @brief   DMA stream enable.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-#define dmaStreamEnable(dmastp) {                                           \
-  (dmastp)->channel->CCR |= STM32_DMA_CR_EN;                                \
-}
-
-/**
- * @brief   DMA stream disable.
- * @details The function disables the specified stream and then clears any
- *          pending interrupt.
- * @note    This function can be invoked in both ISR or thread context.
- * @note    Interrupts enabling flags are set to zero after this call, see
- *          bug 3607518.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-#define dmaStreamDisable(dmastp) {                                          \
-  (dmastp)->channel->CCR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE |       \
-                              STM32_DMA_CR_TEIE | STM32_DMA_CR_EN);         \
-  dmaStreamClearInterrupt(dmastp);                                          \
-}
-
-/**
- * @brief   DMA stream interrupt sources clear.
- * @note    This function can be invoked in both ISR or thread context.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- *
- * @special
- */
-#define dmaStreamClearInterrupt(dmastp) {                                   \
-  *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift;                 \
-}
-
-/**
- * @brief   Starts a memory to memory operation using the specified stream.
- * @note    The default transfer data mode is "byte to byte" but it can be
- *          changed by specifying extra options in the @p mode parameter.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- * @param[in] mode      value to be written in the CCR register, this value
- *                      is implicitly ORed with:
- *                      - @p STM32_DMA_CR_MINC
- *                      - @p STM32_DMA_CR_PINC
- *                      - @p STM32_DMA_CR_DIR_M2M
- *                      - @p STM32_DMA_CR_EN
- *                      .
- * @param[in] src       source address
- * @param[in] dst       destination address
- * @param[in] n         number of data units to copy
- */
-#define dmaStartMemCopy(dmastp, mode, src, dst, n) {                        \
-  dmaStreamSetPeripheral(dmastp, src);                                      \
-  dmaStreamSetMemory0(dmastp, dst);                                         \
-  dmaStreamSetTransactionSize(dmastp, n);                                   \
-  dmaStreamSetMode(dmastp, (mode) |                                         \
-                           STM32_DMA_CR_MINC | STM32_DMA_CR_PINC |          \
-                           STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN);         \
-}
-
-/**
- * @brief   Polled wait for DMA transfer end.
- * @pre     The stream must have been allocated using @p dmaStreamAllocate().
- * @post    After use the stream can be released using @p dmaStreamRelease().
- *
- * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
- */
-#define dmaWaitCompletion(dmastp) {                                         \
-  while ((dmastp)->channel->CNDTR > 0)                                      \
-    ;                                                                       \
-  dmaStreamDisable(dmastp);                                                 \
-}
-
-/** @} */
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void dmaInit(void);
-  bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
-                         uint32_t priority,
-                         stm32_dmaisr_t func,
-                         void *param);
-  void dmaStreamRelease(const stm32_dma_stream_t *dmastp);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _STM32_DMA_H_ */
-
-/** @} */
diff --git a/os/hal/ports/STM32/STM32F30x/stm32_isr.h b/os/hal/ports/STM32/STM32F30x/stm32_isr.h
deleted file mode 100644
index a03f74c06..000000000
--- a/os/hal/ports/STM32/STM32F30x/stm32_isr.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
-    ChibiOS/HAL - Copyright (C) 2006-2014 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F30x/stm32_isr.h
- * @brief   ISR remapper driver header.
- *
- * @addtogroup STM32F30x_ISR
- * @{
- */
-
-#ifndef _STM32_ISR_H_
-#define _STM32_ISR_H_
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @name    ISR names and numbers remapping
- * @{
- */
-/*
- * CAN units.
- */
-#define STM32_CAN1_TX_HANDLER       Vector8C
-#define STM32_CAN1_RX0_HANDLER      Vector90
-#define STM32_CAN1_RX1_HANDLER      Vector94
-#define STM32_CAN1_SCE_HANDLER      Vector98
-
-#define STM32_CAN1_TX_NUMBER        19
-#define STM32_CAN1_RX0_NUMBER       20
-#define STM32_CAN1_RX1_NUMBER       21
-#define STM32_CAN1_SCE_NUMBER       22
-
-/*
- * I2C units.
- */
-#define STM32_I2C1_EVENT_HANDLER    VectorBC
-#define STM32_I2C1_ERROR_HANDLER    VectorC0
-#define STM32_I2C1_EVENT_NUMBER     31
-#define STM32_I2C1_ERROR_NUMBER     32
-
-#define STM32_I2C2_EVENT_HANDLER    VectorC4
-#define STM32_I2C2_ERROR_HANDLER    VectorC8
-#define STM32_I2C2_EVENT_NUMBER     33
-#define STM32_I2C2_ERROR_NUMBER     34
-
-/*
- * TIM units.
- */
-#define STM32_TIM1_UP_HANDLER       VectorA4
-#define STM32_TIM1_CC_HANDLER       VectorAC
-#define STM32_TIM2_HANDLER          VectorB0
-#define STM32_TIM3_HANDLER          VectorB4
-#define STM32_TIM4_HANDLER          VectorB8
-#define STM32_TIM6_HANDLER          Vector118
-#define STM32_TIM7_HANDLER          Vector11C
-#define STM32_TIM8_UP_HANDLER       VectorF0
-#define STM32_TIM8_CC_HANDLER       VectorF8
-
-#define STM32_TIM1_UP_NUMBER        25
-#define STM32_TIM1_CC_NUMBER        27
-#define STM32_TIM2_NUMBER           28
-#define STM32_TIM3_NUMBER           29
-#define STM32_TIM4_NUMBER           30
-#define STM32_TIM6_NUMBER           54
-#define STM32_TIM7_NUMBER           55
-#define STM32_TIM8_UP_NUMBER        44
-#define STM32_TIM8_CC_NUMBER        46
-
-/*
- * USART units.
- */
-#define STM32_USART1_HANDLER        VectorD4
-#define STM32_USART2_HANDLER        VectorD8
-#define STM32_USART3_HANDLER        VectorDC
-#define STM32_UART4_HANDLER         Vector110
-#define STM32_UART5_HANDLER         Vector114
-
-#define STM32_USART1_NUMBER         37
-#define STM32_USART2_NUMBER         38
-#define STM32_USART3_NUMBER         39
-#define STM32_UART4_NUMBER          52
-#define STM32_UART5_NUMBER          53
-
-/*
- * USB units.
- */
-#define STM32_USB1_HP_HANDLER       Vector168
-#define STM32_USB1_LP_HANDLER       Vector16C
-
-#define STM32_USB1_HP_NUMBER        74
-#define STM32_USB1_LP_NUMBER        75
-/** @} */
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#endif /* _STM32_ISR_H_ */
-
-/** @} */
diff --git a/os/hal/ports/STM32/STM32F30x/stm32_rcc.h b/os/hal/ports/STM32/STM32F30x/stm32_rcc.h
deleted file mode 100644
index a152dfadd..000000000
--- a/os/hal/ports/STM32/STM32F30x/stm32_rcc.h
+++ /dev/null
@@ -1,835 +0,0 @@
-/*
-    ChibiOS/HAL - Copyright (C) 2006-2014 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F30x/stm32_rcc.h
- * @brief   RCC helper driver header.
- * @note    This file requires definitions from the ST header file
- *          @p stm32f30x.h.
- *
- * @addtogroup STM32F30x_RCC
- * @{
- */
-
-#ifndef _STM32_RCC_
-#define _STM32_RCC_
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/**
- * @name    Generic RCC operations
- * @{
- */
-/**
- * @brief   Enables the clock of one or more peripheral on the APB1 bus.
- *
- * @param[in] mask      APB1 peripherals mask
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccEnableAPB1(mask, lp) {                                           \
-  RCC->APB1ENR |= (mask);                                                   \
-}
-
-/**
- * @brief   Disables the clock of one or more peripheral on the APB1 bus.
- *
- * @param[in] mask      APB1 peripherals mask
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccDisableAPB1(mask, lp) {                                          \
-  RCC->APB1ENR &= ~(mask);                                                  \
-}
-
-/**
- * @brief   Resets one or more peripheral on the APB1 bus.
- *
- * @param[in] mask      APB1 peripherals mask
- *
- * @api
- */
-#define rccResetAPB1(mask) {                                                \
-  RCC->APB1RSTR |= (mask);                                                  \
-  RCC->APB1RSTR = 0;                                                        \
-}
-
-/**
- * @brief   Enables the clock of one or more peripheral on the APB2 bus.
- *
- * @param[in] mask      APB2 peripherals mask
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccEnableAPB2(mask, lp) {                                           \
-  RCC->APB2ENR |= (mask);                                                   \
-}
-
-/**
- * @brief   Disables the clock of one or more peripheral on the APB2 bus.
- *
- * @param[in] mask      APB2 peripherals mask
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccDisableAPB2(mask, lp) {                                          \
-  RCC->APB2ENR &= ~(mask);                                                  \
-}
-
-/**
- * @brief   Resets one or more peripheral on the APB2 bus.
- *
- * @param[in] mask      APB2 peripherals mask
- *
- * @api
- */
-#define rccResetAPB2(mask) {                                                \
-  RCC->APB2RSTR |= (mask);                                                  \
-  RCC->APB2RSTR = 0;                                                        \
-}
-
-/**
- * @brief   Enables the clock of one or more peripheral on the AHB bus.
- *
- * @param[in] mask      AHB peripherals mask
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccEnableAHB(mask, lp) {                                            \
-  RCC->AHBENR |= (mask);                                                    \
-}
-
-/**
- * @brief   Disables the clock of one or more peripheral on the AHB bus.
- *
- * @param[in] mask      AHB peripherals mask
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccDisableAHB(mask, lp) {                                           \
-  RCC->AHBENR &= ~(mask);                                                   \
-}
-
-/**
- * @brief   Resets one or more peripheral on the AHB bus.
- *
- * @param[in] mask      AHB peripherals mask
- *
- * @api
- */
-#define rccResetAHB(mask) {                                                 \
-  RCC->AHBRSTR |= (mask);                                                   \
-  RCC->AHBRSTR = 0;                                                         \
-}
-/** @} */
-
-/**
- * @name    ADC peripherals specific RCC operations
- * @{
- */
-/**
- * @brief   Enables the ADC1/ADC2 peripheral clock.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccEnableADC12(lp) rccEnableAHB(RCC_AHBENR_ADC12EN, lp)
-
-/**
- * @brief   Disables the ADC1/ADC2 peripheral clock.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccDisableADC12(lp) rccDisableAHB(RCC_AHBENR_ADC12EN, lp)
-
-/**
- * @brief   Resets the ADC1/ADC2 peripheral.
- *
- * @api
- */
-#define rccResetADC12() rccResetAHB(RCC_AHBRSTR_ADC12RST)
-
-/**
- * @brief   Enables the ADC3/ADC4 peripheral clock.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccEnableADC34(lp) rccEnableAHB(RCC_AHBENR_ADC34EN, lp)
-
-/**
- * @brief   Disables the ADC3/ADC4 peripheral clock.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccDisableADC34(lp) rccDisableAHB(RCC_AHBENR_ADC34EN, lp)
-
-/**
- * @brief   Resets the ADC3/ADC4 peripheral.
- *
- * @api
- */
-#define rccResetADC34() rccResetAHB(RCC_AHBRSTR_ADC34RST)
-/** @} */
-
-/**
- * @name    CAN peripherals specific RCC operations
- * @{
- */
-/**
- * @brief   Enables the CAN1 peripheral clock.
- * @note    The @p lp parameter is ignored in this family.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CANEN, lp)
-
-/**
- * @brief   Disables the CAN1 peripheral clock.
- * @note    The @p lp parameter is ignored in this family.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccDisableCAN1(lp) rccDisableAPB1(RCC_APB1ENR_CANEN, lp)
-
-/**
- * @brief   Resets the CAN1 peripheral.
- *
- * @api
- */
-#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CANRST)
-/** @} */
-
-/**
- * @name    DMA peripheral specific RCC operations
- * @{
- */
-/**
- * @brief   Enables the DMA1 peripheral clock.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccEnableDMA1(lp) rccEnableAHB(RCC_AHBENR_DMA1EN, lp)
-
-/**
- * @brief   Disables the DMA1 peripheral clock.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccDisableDMA1(lp) rccDisableAHB(RCC_AHBENR_DMA1EN, lp)
-
-/**
- * @brief   Resets the DMA1 peripheral.
- *
- * @api
- */
-#define rccResetDMA1() rccResetAHB(RCC_AHBRSTR_DMA1RST)
-
-/**
- * @brief   Enables the DMA2 peripheral clock.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccEnableDMA2(lp) rccEnableAHB(RCC_AHBENR_DMA2EN, lp)
-
-/**
- * @brief   Disables the DMA2 peripheral clock.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccDisableDMA2(lp) rccDisableAHB(RCC_AHBENR_DMA2EN, lp)
-
-/**
- * @brief   Resets the DMA2 peripheral.
- *
- * @api
- */
-#define rccResetDMA2() rccResetAHB(RCC_AHBRSTR_DMA2RST)
-/** @} */
-
-/**
- * @name    PWR interface specific RCC operations
- * @{
- */
-/**
- * @brief   Enables the PWR interface clock.
- * @note    The @p lp parameter is ignored in this family.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp)
-
-/**
- * @brief   Disables PWR interface clock.
- * @note    The @p lp parameter is ignored in this family.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp)
-
-/**
- * @brief   Resets the PWR interface.
- *
- * @api
- */
-#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)
-/** @} */
-
-/**
- * @name    I2C peripherals specific RCC operations
- * @{
- */
-/**
- * @brief   Enables the I2C1 peripheral clock.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp)
-
-/**
- * @brief   Disables the I2C1 peripheral clock.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp)
-
-/**
- * @brief   Resets the I2C1 peripheral.
- *
- * @api
- */
-#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST)
-
-/**
- * @brief   Enables the I2C2 peripheral clock.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp)
-
-/**
- * @brief   Disables the I2C2 peripheral clock.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp)
-
-/**
- * @brief   Resets the I2C2 peripheral.
- *
- * @api
- */
-#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST)
-/** @} */
-
-/**
- * @name    SPI peripherals specific RCC operations
- * @{
- */
-/**
- * @brief   Enables the SPI1 peripheral clock.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)
-
-/**
- * @brief   Disables the SPI1 peripheral clock.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp)
-
-/**
- * @brief   Resets the SPI1 peripheral.
- *
- * @api
- */
-#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)
-
-/**
- * @brief   Enables the SPI2 peripheral clock.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp)
-
-/**
- * @brief   Disables the SPI2 peripheral clock.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp)
-
-/**
- * @brief   Resets the SPI2 peripheral.
- *
- * @api
- */
-#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST)
-
-/**
- * @brief   Enables the SPI3 peripheral clock.
- * @note    The @p lp parameter is ignored in this family.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccEnableSPI3(lp) rccEnableAPB1(RCC_APB1ENR_SPI3EN, lp)
-
-/**
- * @brief   Disables the SPI3 peripheral clock.
- * @note    The @p lp parameter is ignored in this family.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccDisableSPI3(lp) rccDisableAPB1(RCC_APB1ENR_SPI3EN, lp)
-
-/**
- * @brief   Resets the SPI3 peripheral.
- *
- * @api
- */
-#define rccResetSPI3() rccResetAPB1(RCC_APB1RSTR_SPI3RST)
-/** @} */
-
-/**
- * @name    TIM peripherals specific RCC operations
- * @{
- */
-/**
- * @brief   Enables the TIM1 peripheral clock.
- * @note    The @p lp parameter is ignored in this family.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp)
-
-/**
- * @brief   Disables the TIM1 peripheral clock.
- * @note    The @p lp parameter is ignored in this family.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccDisableTIM1(lp) rccDisableAPB2(RCC_APB2ENR_TIM1EN, lp)
-
-/**
- * @brief   Resets the TIM1 peripheral.
- *
- * @api
- */
-#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST)
-
-/**
- * @brief   Enables the TIM2 peripheral clock.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp)
-
-/**
- * @brief   Disables the TIM2 peripheral clock.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp)
-
-/**
- * @brief   Resets the TIM2 peripheral.
- *
- * @api
- */
-#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST)
-
-/**
- * @brief   Enables the TIM3 peripheral clock.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp)
-
-/**
- * @brief   Disables the TIM3 peripheral clock.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp)
-
-/**
- * @brief   Resets the TIM3 peripheral.
- *
- * @api
- */
-#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST)
-
-/**
- * @brief   Enables the TIM4 peripheral clock.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp)
-
-/**
- * @brief   Disables the TIM4 peripheral clock.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccDisableTIM4(lp) rccDisableAPB1(RCC_APB1ENR_TIM4EN, lp)
-
-/**
- * @brief   Resets the TIM4 peripheral.
- *
- * @api
- */
-#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST)
-
-/**
- * @brief   Enables the TIM6 peripheral clock.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccEnableTIM6(lp) rccEnableAPB1(RCC_APB1ENR_TIM6EN, lp)
-
-/**
- * @brief   Disables the TIM6 peripheral clock.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccDisableTIM6(lp) rccDisableAPB1(RCC_APB1ENR_TIM6EN, lp)
-
-/**
- * @brief   Resets the TIM6 peripheral.
- *
- * @api
- */
-#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST)
-
-/**
- * @brief   Enables the TIM7 peripheral clock.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp)
-
-/**
- * @brief   Disables the TIM7 peripheral clock.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccDisableTIM7(lp) rccDisableAPB1(RCC_APB1ENR_TIM7EN, lp)
-
-/**
- * @brief   Resets the TIM7 peripheral.
- *
- * @api
- */
-#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST)
-
-/**
- * @brief   Enables the TIM8 peripheral clock.
- * @note    The @p lp parameter is ignored in this family.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp)
-
-/**
- * @brief   Disables the TIM8 peripheral clock.
- * @note    The @p lp parameter is ignored in this family.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccDisableTIM8(lp) rccDisableAPB2(RCC_APB2ENR_TIM8EN, lp)
-
-/**
- * @brief   Resets the TIM8 peripheral.
- *
- * @api
- */
-#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST)
-/** @} */
-
-/**
- * @name    USART/UART peripherals specific RCC operations
- * @{
- */
-/**
- * @brief   Enables the USART1 peripheral clock.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)
-
-/**
- * @brief   Disables the USART1 peripheral clock.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp)
-
-/**
- * @brief   Resets the USART1 peripheral.
- *
- * @api
- */
-#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)
-
-/**
- * @brief   Enables the USART2 peripheral clock.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp)
-
-/**
- * @brief   Disables the USART2 peripheral clock.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp)
-
-/**
- * @brief   Resets the USART2 peripheral.
- *
- * @api
- */
-#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST)
-
-/**
- * @brief   Enables the USART3 peripheral clock.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp)
-
-/**
- * @brief   Disables the USART3 peripheral clock.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccDisableUSART3(lp) rccDisableAPB1(RCC_APB1ENR_USART3EN, lp)
-
-/**
- * @brief   Resets the USART3 peripheral.
- *
- * @api
- */
-#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST)
-
-/**
- * @brief   Enables the UART4 peripheral clock.
- * @note    The @p lp parameter is ignored in this family.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccEnableUART4(lp) rccEnableAPB1(RCC_APB1ENR_UART4EN, lp)
-
-/**
- * @brief   Disables the UART4 peripheral clock.
- * @note    The @p lp parameter is ignored in this family.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccDisableUART4(lp) rccDisableAPB1(RCC_APB1ENR_UART4EN, lp)
-
-/**
- * @brief   Resets the UART4 peripheral.
- *
- * @api
- */
-#define rccResetUART4() rccResetAPB1(RCC_APB1RSTR_UART4RST)
-
-/**
- * @brief   Enables the UART5 peripheral clock.
- * @note    The @p lp parameter is ignored in this family.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_UART5EN, lp)
-
-/**
- * @brief   Disables the UART5 peripheral clock.
- * @note    The @p lp parameter is ignored in this family.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccDisableUART5(lp) rccDisableAPB1(RCC_APB1ENR_UART5EN, lp)
-
-/**
- * @brief   Resets the UART5 peripheral.
- *
- * @api
- */
-#define rccResetUART5() rccResetAPB1(RCC_APB1RSTR_UART5RST)
-/** @} */
-
-/**
- * @name    USB peripheral specific RCC operations
- * @{
- */
-/**
- * @brief   Enables the USB peripheral clock.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccEnableUSB(lp) rccEnableAPB1(RCC_APB1ENR_USBEN, lp)
-
-/**
- * @brief   Disables the USB peripheral clock.
- *
- * @param[in] lp        low power enable flag
- *
- * @api
- */
-#define rccDisableUSB(lp) rccDisableAPB1(RCC_APB1ENR_USBEN, lp)
-
-/**
- * @brief   Resets the USB peripheral.
- *
- * @api
- */
-#define rccResetUSB() rccResetAPB1(RCC_APB1RSTR_USBRST)
-/** @} */
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _STM32_RCC_ */
-
-/** @} */
diff --git a/os/hal/ports/STM32/STM32F30x/stm32_registry.h b/os/hal/ports/STM32/STM32F30x/stm32_registry.h
deleted file mode 100644
index 0ebf0d2e0..000000000
--- a/os/hal/ports/STM32/STM32F30x/stm32_registry.h
+++ /dev/null
@@ -1,1444 +0,0 @@
-/*
-    ChibiOS/HAL - Copyright (C) 2006-2014 Giovanni Di Sirio
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    STM32F30x/stm32_registry.h
- * @brief   STM32F30x capabilities registry.
- *
- * @addtogroup HAL
- * @{
- */
-
-#ifndef _STM32_REGISTRY_H_
-#define _STM32_REGISTRY_H_
-
-/**
- * @brief   Sub-family identifier.
- */
-#if !defined(STM32F3XX) || defined(__DOXYGEN__)
-#define STM32F3XX
-#endif
-
-/*===========================================================================*/
-/* Platform capabilities.                                                    */
-/*===========================================================================*/
-
-/**
- * @name    STM32F3xx capabilities
- * @{
- */
-/*===========================================================================*/
-/* STM32F303xC.                                                              */
-/*===========================================================================*/
-#if defined(STM32F303xC) || defined(__DOXYGEN__)
-/* ADC attributes.*/
-#define STM32_HAS_ADC1                      TRUE
-#define STM32_HAS_ADC2                      TRUE
-#define STM32_HAS_ADC3                      TRUE
-#define STM32_HAS_ADC4                      TRUE
-
-#define STM32_HAS_SDADC1                    FALSE
-#define STM32_HAS_SDADC2                    FALSE
-#define STM32_HAS_SDADC3                    FALSE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1                      TRUE
-#define STM32_HAS_CAN2                      FALSE
-#define STM32_CAN_MAX_FILTERS               14
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC1                      TRUE
-#define STM32_HAS_DAC2                      TRUE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA                  FALSE
-#define STM32_HAS_DMA1                      TRUE
-#define STM32_HAS_DMA2                      TRUE
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH                       FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS             34
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA                     TRUE
-#define STM32_HAS_GPIOB                     TRUE
-#define STM32_HAS_GPIOC                     TRUE
-#define STM32_HAS_GPIOD                     TRUE
-#define STM32_HAS_GPIOE                     TRUE
-#define STM32_HAS_GPIOF                     TRUE
-#define STM32_HAS_GPIOG                     FALSE
-#define STM32_HAS_GPIOH                     FALSE
-#define STM32_HAS_GPIOI                     FALSE
-#define STM32_GPIO_EN_MASK                  (RCC_AHBENR_GPIOAEN |           \
-                                             RCC_AHBENR_GPIOBEN |           \
-                                             RCC_AHBENR_GPIOCEN |           \
-                                             RCC_AHBENR_GPIODEN |           \
-                                             RCC_AHBENR_GPIOEEN |           \
-                                             RCC_AHBENR_GPIOFEN)
-/* I2C attributes.*/
-#define STM32_HAS_I2C1                      TRUE
-#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
-#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
-
-#define STM32_HAS_I2C2                      TRUE
-#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
-#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
-
-#define STM32_HAS_I2C3                      FALSE
-
-/* RTC attributes.*/
-#define STM32_HAS_RTC                       TRUE
-#define STM32_RTC_HAS_SUBSECONDS            TRUE
-#define STM32_RTC_HAS_PERIODIC_WAKEUPS      TRUE
-#define STM32_RTC_NUM_ALARMS                1
-#define STM32_RTC_HAS_INTERRUPTS            FALSE
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO                      FALSE
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1                      TRUE
-#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
-#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
-
-#define STM32_HAS_SPI2                      TRUE
-#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
-#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
-
-#define STM32_HAS_SPI3                      TRUE
-#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 1)
-#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 2)
-
-#define STM32_HAS_SPI4                      FALSE
-#define STM32_HAS_SPI5                      FALSE
-#define STM32_HAS_SPI6                      FALSE
-
-/* TIM attributes.*/
-#define STM32_TIM_MAX_CHANNELS              6
-
-#define STM32_HAS_TIM1                      TRUE
-#define STM32_TIM1_IS_32BITS                FALSE
-#define STM32_TIM1_CHANNELS                 6
-
-#define STM32_HAS_TIM2                      TRUE
-#define STM32_TIM2_IS_32BITS                TRUE
-#define STM32_TIM2_CHANNELS                 4
-
-#define STM32_HAS_TIM3                      TRUE
-#define STM32_TIM3_IS_32BITS                FALSE
-#define STM32_TIM3_CHANNELS                 4
-
-#define STM32_HAS_TIM4                      TRUE
-#define STM32_TIM4_IS_32BITS                FALSE
-#define STM32_TIM4_CHANNELS                 4
-
-#define STM32_HAS_TIM6                      TRUE
-#define STM32_TIM6_IS_32BITS                FALSE
-#define STM32_TIM6_CHANNELS                 0
-
-#define STM32_HAS_TIM7                      TRUE
-#define STM32_TIM7_IS_32BITS                FALSE
-#define STM32_TIM7_CHANNELS                 0
-
-#define STM32_HAS_TIM8                      TRUE
-#define STM32_TIM8_IS_32BITS                FALSE
-#define STM32_TIM8_CHANNELS                 6
-
-#define STM32_HAS_TIM15                     TRUE
-#define STM32_TIM15_IS_32BITS               FALSE
-#define STM32_TIM15_CHANNELS                2
-
-#define STM32_HAS_TIM16                     TRUE
-#define STM32_TIM16_IS_32BITS               FALSE
-#define STM32_TIM16_CHANNELS                2
-
-#define STM32_HAS_TIM17                     TRUE
-#define STM32_TIM17_IS_32BITS               FALSE
-#define STM32_TIM17_CHANNELS                2
-
-#define STM32_HAS_TIM5                      FALSE
-#define STM32_HAS_TIM9                      FALSE
-#define STM32_HAS_TIM10                     FALSE
-#define STM32_HAS_TIM11                     FALSE
-#define STM32_HAS_TIM12                     FALSE
-#define STM32_HAS_TIM13                     FALSE
-#define STM32_HAS_TIM14                     FALSE
-#define STM32_HAS_TIM18                     FALSE
-#define STM32_HAS_TIM19                     FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1                    TRUE
-#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
-#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
-
-#define STM32_HAS_USART2                    TRUE
-#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
-#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
-
-#define STM32_HAS_USART3                    TRUE
-#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
-#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
-
-#define STM32_HAS_UART4                     TRUE
-#define STM32_UART_UART4_RX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 3)
-#define STM32_UART_UART4_TX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 5)
-
-#define STM32_HAS_UART5                     TRUE
-
-#define STM32_HAS_USART6                    FALSE
-
-/* USB attributes.*/
-#define STM32_HAS_USB                       TRUE
-#define STM32_HAS_OTG1                      FALSE
-#define STM32_HAS_OTG2                      FALSE
-#endif /* defined(STM32F303xC) */
-
-/*===========================================================================*/
-/* STM32F303x8.                                                              */
-/*===========================================================================*/
-#if defined(STM32F303x8)
-/* ADC attributes.*/
-#define STM32_HAS_ADC1                      TRUE
-#define STM32_HAS_ADC2                      TRUE
-#define STM32_HAS_ADC3                      FALSE
-#define STM32_HAS_ADC4                      FALSE
-
-#define STM32_HAS_SDADC1                    FALSE
-#define STM32_HAS_SDADC2                    FALSE
-#define STM32_HAS_SDADC3                    FALSE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1                      TRUE
-#define STM32_HAS_CAN2                      FALSE
-#define STM32_CAN_MAX_FILTERS               14
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC1                      TRUE
-#define STM32_HAS_DAC2                      TRUE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA                  FALSE
-#define STM32_HAS_DMA1                      TRUE
-#define STM32_HAS_DMA2                      FALSE
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH                       FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS             34
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA                     TRUE
-#define STM32_HAS_GPIOB                     TRUE
-#define STM32_HAS_GPIOC                     TRUE
-#define STM32_HAS_GPIOD                     TRUE
-#define STM32_HAS_GPIOE                     FALSE
-#define STM32_HAS_GPIOF                     TRUE
-#define STM32_HAS_GPIOG                     FALSE
-#define STM32_HAS_GPIOH                     FALSE
-#define STM32_HAS_GPIOI                     FALSE
-#define STM32_GPIO_EN_MASK                  (RCC_AHBENR_GPIOAEN |           \
-                                             RCC_AHBENR_GPIOBEN |           \
-                                             RCC_AHBENR_GPIOCEN |           \
-                                             RCC_AHBENR_GPIODEN |           \
-                                             RCC_AHBENR_GPIOFEN)
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1                      TRUE
-#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
-#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
-
-#define STM32_HAS_I2C2                      FALSE
-#define STM32_HAS_I2C3                      FALSE
-
-/* RTC attributes.*/
-#define STM32_HAS_RTC                       TRUE
-#define STM32_RTC_HAS_SUBSECONDS            TRUE
-#define STM32_RTC_HAS_PERIODIC_WAKEUPS      TRUE
-#define STM32_RTC_NUM_ALARMS                2
-#define STM32_RTC_HAS_INTERRUPTS            FALSE
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO                      FALSE
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1                      TRUE
-#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
-#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
-
-#define STM32_HAS_SPI2                      FALSE
-#define STM32_HAS_SPI3                      FALSE
-#define STM32_HAS_SPI4                      FALSE
-#define STM32_HAS_SPI5                      FALSE
-#define STM32_HAS_SPI6                      FALSE
-
-/* TIM attributes.*/
-#define STM32_TIM_MAX_CHANNELS              6
-
-#define STM32_HAS_TIM1                      TRUE
-#define STM32_TIM1_IS_32BITS                FALSE
-#define STM32_TIM1_CHANNELS                 6
-
-#define STM32_HAS_TIM2                      TRUE
-#define STM32_TIM2_IS_32BITS                TRUE
-#define STM32_TIM2_CHANNELS                 4
-
-#define STM32_HAS_TIM3                      TRUE
-#define STM32_TIM3_IS_32BITS                FALSE
-#define STM32_TIM3_CHANNELS                 4
-
-#define STM32_HAS_TIM4                      TRUE
-#define STM32_TIM4_IS_32BITS                FALSE
-#define STM32_TIM4_CHANNELS                 4
-
-#define STM32_HAS_TIM6                      TRUE
-#define STM32_TIM6_IS_32BITS                FALSE
-#define STM32_TIM6_CHANNELS                 0
-
-#define STM32_HAS_TIM7                      TRUE
-#define STM32_TIM7_IS_32BITS                FALSE
-#define STM32_TIM7_CHANNELS                 0
-
-#define STM32_HAS_TIM15                     TRUE
-#define STM32_TIM15_IS_32BITS               FALSE
-#define STM32_TIM15_CHANNELS                2
-
-#define STM32_HAS_TIM16                     TRUE
-#define STM32_TIM16_IS_32BITS               FALSE
-#define STM32_TIM16_CHANNELS                2
-
-#define STM32_HAS_TIM17                     TRUE
-#define STM32_TIM17_IS_32BITS               FALSE
-#define STM32_TIM17_CHANNELS                2
-
-#define STM32_HAS_TIM5                      FALSE
-#define STM32_HAS_TIM8                      FALSE
-#define STM32_HAS_TIM9                      FALSE
-#define STM32_HAS_TIM10                     FALSE
-#define STM32_HAS_TIM11                     FALSE
-#define STM32_HAS_TIM12                     FALSE
-#define STM32_HAS_TIM13                     FALSE
-#define STM32_HAS_TIM14                     FALSE
-#define STM32_HAS_TIM18                     FALSE
-#define STM32_HAS_TIM19                     FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1                    TRUE
-#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
-#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
-
-#define STM32_HAS_USART2                    TRUE
-#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
-#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
-
-#define STM32_HAS_USART3                    TRUE
-#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
-#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
-
-#define STM32_HAS_UART4                     FALSE
-#define STM32_HAS_UART5                     FALSE
-#define STM32_HAS_USART6                    FALSE
-
-/* USB attributes.*/
-#define STM32_HAS_USB                       FALSE
-#define STM32_HAS_OTG1                      FALSE
-#define STM32_HAS_OTG2                      FALSE
-#endif /* defined(STM32F303x8) */
-
-/*===========================================================================*/
-/* STM32F301x8.                                                              */
-/*===========================================================================*/
-#if defined(STM32F301x8)
-/* ADC attributes.*/
-#define STM32_HAS_ADC1                      TRUE
-#define STM32_HAS_ADC2                      FALSE
-#define STM32_HAS_ADC3                      FALSE
-#define STM32_HAS_ADC4                      FALSE
-
-#define STM32_HAS_SDADC1                    FALSE
-#define STM32_HAS_SDADC2                    FALSE
-#define STM32_HAS_SDADC3                    FALSE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1                      FALSE
-#define STM32_HAS_CAN2                      FALSE
-#define STM32_CAN_MAX_FILTERS               14
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC1                      TRUE
-#define STM32_HAS_DAC2                      FALSE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA                  FALSE
-#define STM32_HAS_DMA1                      TRUE
-#define STM32_HAS_DMA2                      FALSE
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH                       FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS             33
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA                     TRUE
-#define STM32_HAS_GPIOB                     TRUE
-#define STM32_HAS_GPIOC                     TRUE
-#define STM32_HAS_GPIOD                     TRUE
-#define STM32_HAS_GPIOE                     FALSE
-#define STM32_HAS_GPIOF                     TRUE
-#define STM32_HAS_GPIOG                     FALSE
-#define STM32_HAS_GPIOH                     FALSE
-#define STM32_HAS_GPIOI                     FALSE
-#define STM32_GPIO_EN_MASK                  (RCC_AHBENR_GPIOAEN |           \
-                                             RCC_AHBENR_GPIOBEN |           \
-                                             RCC_AHBENR_GPIOCEN |           \
-                                             RCC_AHBENR_GPIODEN |           \
-                                             RCC_AHBENR_GPIOFEN)
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1                      TRUE
-#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
-#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
-
-#define STM32_HAS_I2C2                      TRUE
-#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
-#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
-
-#define STM32_HAS_I2C3                      TRUE
-#define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
-#define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 1)
-
-/* RTC attributes.*/
-#define STM32_HAS_RTC                       TRUE
-#define STM32_RTC_HAS_SUBSECONDS            TRUE
-#define STM32_RTC_HAS_PERIODIC_WAKEUPS      TRUE
-#define STM32_RTC_NUM_ALARMS                2
-#define STM32_RTC_HAS_INTERRUPTS            FALSE
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO                      FALSE
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI2                      TRUE
-#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
-#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
-
-#define STM32_HAS_SPI3                      TRUE
-#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
-#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
-
-#define STM32_HAS_SPI1                      FALSE
-#define STM32_HAS_SPI4                      FALSE
-#define STM32_HAS_SPI5                      FALSE
-#define STM32_HAS_SPI6                      FALSE
-
-/* TIM attributes.*/
-#define STM32_TIM_MAX_CHANNELS              6
-
-#define STM32_HAS_TIM1                      TRUE
-#define STM32_TIM1_IS_32BITS                FALSE
-#define STM32_TIM1_CHANNELS                 6
-
-#define STM32_HAS_TIM2                      TRUE
-#define STM32_TIM2_IS_32BITS                TRUE
-#define STM32_TIM2_CHANNELS                 4
-
-#define STM32_HAS_TIM6                      TRUE
-#define STM32_TIM6_IS_32BITS                FALSE
-#define STM32_TIM6_CHANNELS                 0
-
-#define STM32_HAS_TIM15                     TRUE
-#define STM32_TIM15_IS_32BITS               FALSE
-#define STM32_TIM15_CHANNELS                2
-
-#define STM32_HAS_TIM16                     TRUE
-#define STM32_TIM16_IS_32BITS               FALSE
-#define STM32_TIM16_CHANNELS                2
-
-#define STM32_HAS_TIM17                     TRUE
-#define STM32_TIM17_IS_32BITS               FALSE
-#define STM32_TIM17_CHANNELS                2
-
-#define STM32_HAS_TIM3                      FALSE
-#define STM32_HAS_TIM4                      FALSE
-#define STM32_HAS_TIM5                      FALSE
-#define STM32_HAS_TIM7                      FALSE
-#define STM32_HAS_TIM8                      FALSE
-#define STM32_HAS_TIM9                      FALSE
-#define STM32_HAS_TIM10                     FALSE
-#define STM32_HAS_TIM11                     FALSE
-#define STM32_HAS_TIM12                     FALSE
-#define STM32_HAS_TIM13                     FALSE
-#define STM32_HAS_TIM14                     FALSE
-#define STM32_HAS_TIM18                     FALSE
-#define STM32_HAS_TIM19                     FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1                    TRUE
-#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
-#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
-
-#define STM32_HAS_USART2                    TRUE
-#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
-#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
-
-#define STM32_HAS_USART3                    TRUE
-#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
-#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
-
-#define STM32_HAS_UART4                     FALSE
-#define STM32_HAS_UART5                     FALSE
-#define STM32_HAS_USART6                    FALSE
-
-/* USB attributes.*/
-#define STM32_HAS_USB                       FALSE
-#define STM32_HAS_OTG1                      FALSE
-#define STM32_HAS_OTG2                      FALSE
-#endif /* defined(STM32F301x8) */
-
-/*===========================================================================*/
-/* STM32F302x8.                                                              */
-/*===========================================================================*/
-#if defined(STM32F302x8)
-/* ADC attributes.*/
-#define STM32_HAS_ADC1                      TRUE
-#define STM32_HAS_ADC2                      FALSE
-#define STM32_HAS_ADC3                      FALSE
-#define STM32_HAS_ADC4                      FALSE
-
-#define STM32_HAS_SDADC1                    FALSE
-#define STM32_HAS_SDADC2                    FALSE
-#define STM32_HAS_SDADC3                    FALSE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1                      TRUE
-#define STM32_HAS_CAN2                      FALSE
-#define STM32_CAN_MAX_FILTERS               14
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC1                      TRUE
-#define STM32_HAS_DAC2                      FALSE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA                  FALSE
-#define STM32_HAS_DMA1                      TRUE
-#define STM32_HAS_DMA2                      FALSE
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH                       FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS             33
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA                     TRUE
-#define STM32_HAS_GPIOB                     TRUE
-#define STM32_HAS_GPIOC                     TRUE
-#define STM32_HAS_GPIOD                     TRUE
-#define STM32_HAS_GPIOE                     FALSE
-#define STM32_HAS_GPIOF                     TRUE
-#define STM32_HAS_GPIOG                     FALSE
-#define STM32_HAS_GPIOH                     FALSE
-#define STM32_HAS_GPIOI                     FALSE
-#define STM32_GPIO_EN_MASK                  (RCC_AHBENR_GPIOAEN |           \
-                                             RCC_AHBENR_GPIOBEN |           \
-                                             RCC_AHBENR_GPIOCEN |           \
-                                             RCC_AHBENR_GPIODEN |           \
-                                             RCC_AHBENR_GPIOFEN)
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1                      TRUE
-#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
-#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
-
-#define STM32_HAS_I2C2                      TRUE
-#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
-#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
-
-#define STM32_HAS_I2C3                      TRUE
-#define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
-#define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 1)
-
-/* RTC attributes.*/
-#define STM32_HAS_RTC                       TRUE
-#define STM32_RTC_HAS_SUBSECONDS            TRUE
-#define STM32_RTC_HAS_PERIODIC_WAKEUPS      TRUE
-#define STM32_RTC_NUM_ALARMS                2
-#define STM32_RTC_HAS_INTERRUPTS            FALSE
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO                      FALSE
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI2                      TRUE
-#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
-#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
-
-#define STM32_HAS_SPI3                      TRUE
-#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
-#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
-
-#define STM32_HAS_SPI1                      FALSE
-#define STM32_HAS_SPI4                      FALSE
-#define STM32_HAS_SPI5                      FALSE
-#define STM32_HAS_SPI6                      FALSE
-
-/* TIM attributes.*/
-#define STM32_TIM_MAX_CHANNELS              6
-
-#define STM32_HAS_TIM1                      TRUE
-#define STM32_TIM1_IS_32BITS                FALSE
-#define STM32_TIM1_CHANNELS                 6
-
-#define STM32_HAS_TIM2                      TRUE
-#define STM32_TIM2_IS_32BITS                TRUE
-#define STM32_TIM2_CHANNELS                 4
-
-#define STM32_HAS_TIM6                      TRUE
-#define STM32_TIM6_IS_32BITS                FALSE
-#define STM32_TIM6_CHANNELS                 0
-
-#define STM32_HAS_TIM15                     TRUE
-#define STM32_TIM15_IS_32BITS               FALSE
-#define STM32_TIM15_CHANNELS                2
-
-#define STM32_HAS_TIM16                     TRUE
-#define STM32_TIM16_IS_32BITS               FALSE
-#define STM32_TIM16_CHANNELS                2
-
-#define STM32_HAS_TIM17                     TRUE
-#define STM32_TIM17_IS_32BITS               FALSE
-#define STM32_TIM17_CHANNELS                2
-
-#define STM32_HAS_TIM3                      FALSE
-#define STM32_HAS_TIM4                      FALSE
-#define STM32_HAS_TIM5                      FALSE
-#define STM32_HAS_TIM7                      FALSE
-#define STM32_HAS_TIM8                      FALSE
-#define STM32_HAS_TIM9                      FALSE
-#define STM32_HAS_TIM10                     FALSE
-#define STM32_HAS_TIM11                     FALSE
-#define STM32_HAS_TIM12                     FALSE
-#define STM32_HAS_TIM13                     FALSE
-#define STM32_HAS_TIM14                     FALSE
-#define STM32_HAS_TIM18                     FALSE
-#define STM32_HAS_TIM19                     FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1                    TRUE
-#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
-#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
-
-#define STM32_HAS_USART2                    TRUE
-#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
-#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
-
-#define STM32_HAS_USART3                    TRUE
-#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
-#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
-
-#define STM32_HAS_UART4                     FALSE
-#define STM32_HAS_UART5                     FALSE
-#define STM32_HAS_USART6                    FALSE
-
-/* USB attributes.*/
-#define STM32_HAS_USB                       TRUE
-#define STM32_HAS_OTG1                      FALSE
-#define STM32_HAS_OTG2                      FALSE
-#endif /* defined(STM32F302x8) */
-
-/*===========================================================================*/
-/* STM32F302xC.                                                              */
-/*===========================================================================*/
-#if defined(STM32F302xC)
-/* ADC attributes.*/
-#define STM32_HAS_ADC1                      TRUE
-#define STM32_HAS_ADC2                      TRUE
-#define STM32_HAS_ADC3                      FALSE
-#define STM32_HAS_ADC4                      FALSE
-
-#define STM32_HAS_SDADC1                    FALSE
-#define STM32_HAS_SDADC2                    FALSE
-#define STM32_HAS_SDADC3                    FALSE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1                      TRUE
-#define STM32_HAS_CAN2                      FALSE
-#define STM32_CAN_MAX_FILTERS               14
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC1                      TRUE
-#define STM32_HAS_DAC2                      FALSE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA                  FALSE
-#define STM32_HAS_DMA1                      TRUE
-#define STM32_HAS_DMA2                      TRUE
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH                       FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS             34
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA                     TRUE
-#define STM32_HAS_GPIOB                     TRUE
-#define STM32_HAS_GPIOC                     TRUE
-#define STM32_HAS_GPIOD                     TRUE
-#define STM32_HAS_GPIOE                     TRUE
-#define STM32_HAS_GPIOF                     TRUE
-#define STM32_HAS_GPIOG                     FALSE
-#define STM32_HAS_GPIOH                     FALSE
-#define STM32_HAS_GPIOI                     FALSE
-#define STM32_GPIO_EN_MASK                  (RCC_AHBENR_GPIOAEN |           \
-                                             RCC_AHBENR_GPIOBEN |           \
-                                             RCC_AHBENR_GPIOCEN |           \
-                                             RCC_AHBENR_GPIODEN |           \
-                                             RCC_AHBENR_GPIOEEN |           \
-                                             RCC_AHBENR_GPIOFEN)
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1                      FALSE
-
-#define STM32_HAS_I2C2                      TRUE
-#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
-#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
-
-#define STM32_HAS_I2C3                      TRUE
-#define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
-#define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 1)
-
-/* RTC attributes.*/
-#define STM32_HAS_RTC                       TRUE
-#define STM32_RTC_HAS_SUBSECONDS            TRUE
-#define STM32_RTC_HAS_PERIODIC_WAKEUPS      TRUE
-#define STM32_RTC_NUM_ALARMS                2
-#define STM32_RTC_HAS_INTERRUPTS            FALSE
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO                      FALSE
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1                      TRUE
-#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
-#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
-
-#define STM32_HAS_SPI2                      TRUE
-#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
-#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
-
-#define STM32_HAS_SPI3                      TRUE
-#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 1)
-#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 2)
-
-#define STM32_HAS_SPI4                      FALSE
-#define STM32_HAS_SPI5                      FALSE
-#define STM32_HAS_SPI6                      FALSE
-
-/* TIM attributes.*/
-#define STM32_TIM_MAX_CHANNELS              6
-
-#define STM32_HAS_TIM1                      TRUE
-#define STM32_TIM1_IS_32BITS                FALSE
-#define STM32_TIM1_CHANNELS                 6
-
-#define STM32_HAS_TIM2                      TRUE
-#define STM32_TIM2_IS_32BITS                TRUE
-#define STM32_TIM2_CHANNELS                 4
-
-#define STM32_HAS_TIM3                      TRUE
-#define STM32_TIM3_IS_32BITS                FALSE
-#define STM32_TIM3_CHANNELS                 4
-
-#define STM32_HAS_TIM4                      TRUE
-#define STM32_TIM4_IS_32BITS                FALSE
-#define STM32_TIM4_CHANNELS                 4
-
-#define STM32_HAS_TIM6                      TRUE
-#define STM32_TIM6_IS_32BITS                FALSE
-#define STM32_TIM6_CHANNELS                 0
-
-#define STM32_HAS_TIM15                     TRUE
-#define STM32_TIM15_IS_32BITS               FALSE
-#define STM32_TIM15_CHANNELS                2
-
-#define STM32_HAS_TIM16                     TRUE
-#define STM32_TIM16_IS_32BITS               FALSE
-#define STM32_TIM16_CHANNELS                2
-
-#define STM32_HAS_TIM17                     TRUE
-#define STM32_TIM17_IS_32BITS               FALSE
-#define STM32_TIM17_CHANNELS                2
-
-#define STM32_HAS_TIM5                      FALSE
-#define STM32_HAS_TIM7                      FALSE
-#define STM32_HAS_TIM8                      FALSE
-#define STM32_HAS_TIM9                      FALSE
-#define STM32_HAS_TIM10                     FALSE
-#define STM32_HAS_TIM11                     FALSE
-#define STM32_HAS_TIM12                     FALSE
-#define STM32_HAS_TIM13                     FALSE
-#define STM32_HAS_TIM14                     FALSE
-#define STM32_HAS_TIM18                     FALSE
-#define STM32_HAS_TIM19                     FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1                    TRUE
-#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
-#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
-
-#define STM32_HAS_USART2                    TRUE
-#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
-#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
-
-#define STM32_HAS_USART3                    TRUE
-#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
-#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
-
-#define STM32_HAS_UART4                     TRUE
-#define STM32_UART_UART4_RX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 3)
-#define STM32_UART_UART4_TX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 5)
-
-#define STM32_HAS_UART5                     TRUE
-
-#define STM32_HAS_USART6                    FALSE
-
-/* USB attributes.*/
-#define STM32_HAS_USB                       TRUE
-#define STM32_HAS_OTG1                      FALSE
-#define STM32_HAS_OTG2                      FALSE
-#endif /* defined(STM32F302xC) */
-
-/*===========================================================================*/
-/* STM32F318x8.                                                              */
-/*===========================================================================*/
-#if defined(STM32F318x8)
-/* ADC attributes.*/
-#define STM32_HAS_ADC1                      TRUE
-#define STM32_HAS_ADC2                      FALSE
-#define STM32_HAS_ADC3                      FALSE
-#define STM32_HAS_ADC4                      FALSE
-
-#define STM32_HAS_SDADC1                    FALSE
-#define STM32_HAS_SDADC2                    FALSE
-#define STM32_HAS_SDADC3                    FALSE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1                      TRUE
-#define STM32_HAS_CAN2                      FALSE
-#define STM32_CAN_MAX_FILTERS               14
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC1                      TRUE
-#define STM32_HAS_DAC2                      FALSE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA                  FALSE
-#define STM32_HAS_DMA1                      TRUE
-#define STM32_HAS_DMA2                      FALSE
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH                       FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS             33
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA                     TRUE
-#define STM32_HAS_GPIOB                     TRUE
-#define STM32_HAS_GPIOC                     TRUE
-#define STM32_HAS_GPIOD                     FALSE
-#define STM32_HAS_GPIOE                     FALSE
-#define STM32_HAS_GPIOF                     TRUE
-#define STM32_HAS_GPIOG                     FALSE
-#define STM32_HAS_GPIOH                     FALSE
-#define STM32_HAS_GPIOI                     FALSE
-#define STM32_GPIO_EN_MASK                  (RCC_AHBENR_GPIOAEN |           \
-                                             RCC_AHBENR_GPIOBEN |           \
-                                             RCC_AHBENR_GPIOCEN |           \
-                                             RCC_AHBENR_GPIOFEN)
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1                      TRUE
-#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
-#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
-
-#define STM32_HAS_I2C2                      TRUE
-#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
-#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
-
-#define STM32_HAS_I2C3                      TRUE
-#define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
-#define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 1)
-
-/* RTC attributes.*/
-#define STM32_HAS_RTC                       TRUE
-#define STM32_RTC_HAS_SUBSECONDS            TRUE
-#define STM32_RTC_HAS_PERIODIC_WAKEUPS      TRUE
-#define STM32_RTC_NUM_ALARMS                2
-#define STM32_RTC_HAS_INTERRUPTS            FALSE
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO                      FALSE
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI2                      TRUE
-#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
-#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
-
-#define STM32_HAS_SPI3                      TRUE
-#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
-#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
-
-#define STM32_HAS_SPI1                      FALSE
-#define STM32_HAS_SPI4                      FALSE
-#define STM32_HAS_SPI5                      FALSE
-#define STM32_HAS_SPI6                      FALSE
-
-/* TIM attributes.*/
-#define STM32_TIM_MAX_CHANNELS              6
-
-#define STM32_HAS_TIM1                      TRUE
-#define STM32_TIM1_IS_32BITS                FALSE
-#define STM32_TIM1_CHANNELS                 6
-
-#define STM32_HAS_TIM2                      TRUE
-#define STM32_TIM2_IS_32BITS                TRUE
-#define STM32_TIM2_CHANNELS                 4
-
-#define STM32_HAS_TIM6                      TRUE
-#define STM32_TIM6_IS_32BITS                FALSE
-#define STM32_TIM6_CHANNELS                 0
-
-#define STM32_HAS_TIM15                     TRUE
-#define STM32_TIM15_IS_32BITS               FALSE
-#define STM32_TIM15_CHANNELS                2
-
-#define STM32_HAS_TIM16                     TRUE
-#define STM32_TIM16_IS_32BITS               FALSE
-#define STM32_TIM16_CHANNELS                2
-
-#define STM32_HAS_TIM17                     TRUE
-#define STM32_TIM17_IS_32BITS               FALSE
-#define STM32_TIM17_CHANNELS                2
-
-#define STM32_HAS_TIM3                      FALSE
-#define STM32_HAS_TIM4                      FALSE
-#define STM32_HAS_TIM5                      FALSE
-#define STM32_HAS_TIM7                      FALSE
-#define STM32_HAS_TIM8                      FALSE
-#define STM32_HAS_TIM9                      FALSE
-#define STM32_HAS_TIM10                     FALSE
-#define STM32_HAS_TIM11                     FALSE
-#define STM32_HAS_TIM12                     FALSE
-#define STM32_HAS_TIM13                     FALSE
-#define STM32_HAS_TIM14                     FALSE
-#define STM32_HAS_TIM18                     FALSE
-#define STM32_HAS_TIM19                     FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1                    TRUE
-#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
-#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
-
-#define STM32_HAS_USART2                    TRUE
-#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
-#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
-
-#define STM32_HAS_USART3                    TRUE
-#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
-#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
-
-#define STM32_HAS_UART4                     FALSE
-#define STM32_HAS_UART5                     FALSE
-#define STM32_HAS_USART6                    FALSE
-
-/* USB attributes.*/
-#define STM32_HAS_USB                       TRUE
-#define STM32_HAS_OTG1                      FALSE
-#define STM32_HAS_OTG2                      FALSE
-#endif /* defined(STM32F318x8) */
-
-/*===========================================================================*/
-/* STM32F328x8.                                                              */
-/*===========================================================================*/
-#if defined(STM32F328x8)
-/* ADC attributes.*/
-#define STM32_HAS_ADC1                      TRUE
-#define STM32_HAS_ADC2                      TRUE
-#define STM32_HAS_ADC3                      FALSE
-#define STM32_HAS_ADC4                      FALSE
-
-#define STM32_HAS_SDADC1                    FALSE
-#define STM32_HAS_SDADC2                    FALSE
-#define STM32_HAS_SDADC3                    FALSE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1                      TRUE
-#define STM32_HAS_CAN2                      FALSE
-#define STM32_CAN_MAX_FILTERS               14
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC1                      TRUE
-#define STM32_HAS_DAC2                      TRUE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA                  FALSE
-#define STM32_HAS_DMA1                      TRUE
-#define STM32_HAS_DMA2                      FALSE
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH                       FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS             33
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA                     TRUE
-#define STM32_HAS_GPIOB                     TRUE
-#define STM32_HAS_GPIOC                     TRUE
-#define STM32_HAS_GPIOD                     TRUE
-#define STM32_HAS_GPIOE                     FALSE
-#define STM32_HAS_GPIOF                     TRUE
-#define STM32_HAS_GPIOG                     FALSE
-#define STM32_HAS_GPIOH                     FALSE
-#define STM32_HAS_GPIOI                     FALSE
-#define STM32_GPIO_EN_MASK                  (RCC_AHBENR_GPIOAEN |           \
-                                             RCC_AHBENR_GPIOBEN |           \
-                                             RCC_AHBENR_GPIOCEN |           \
-                                             RCC_AHBENR_GPIODEN |           \
-                                             RCC_AHBENR_GPIOFEN)
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1                      TRUE
-#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
-#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
-
-#define STM32_HAS_I2C2                      FALSE
-#define STM32_HAS_I2C3                      FALSE
-
-/* RTC attributes.*/
-#define STM32_HAS_RTC                       TRUE
-#define STM32_RTC_HAS_SUBSECONDS            TRUE
-#define STM32_RTC_HAS_PERIODIC_WAKEUPS      TRUE
-#define STM32_RTC_NUM_ALARMS                2
-#define STM32_RTC_HAS_INTERRUPTS            FALSE
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO                      FALSE
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1                      TRUE
-#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
-#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
-
-#define STM32_HAS_SPI2                      FALSE
-#define STM32_HAS_SPI3                      FALSE
-#define STM32_HAS_SPI4                      FALSE
-#define STM32_HAS_SPI5                      FALSE
-#define STM32_HAS_SPI6                      FALSE
-
-/* TIM attributes.*/
-#define STM32_TIM_MAX_CHANNELS              6
-
-#define STM32_HAS_TIM1                      TRUE
-#define STM32_TIM1_IS_32BITS                FALSE
-#define STM32_TIM1_CHANNELS                 6
-
-#define STM32_HAS_TIM2                      TRUE
-#define STM32_TIM2_IS_32BITS                TRUE
-#define STM32_TIM2_CHANNELS                 4
-
-#define STM32_HAS_TIM3                      TRUE
-#define STM32_TIM3_IS_32BITS                FALSE
-#define STM32_TIM3_CHANNELS                 4
-
-#define STM32_HAS_TIM6                      TRUE
-#define STM32_TIM6_IS_32BITS                FALSE
-#define STM32_TIM6_CHANNELS                 0
-
-#define STM32_HAS_TIM7                      TRUE
-#define STM32_TIM7_IS_32BITS                FALSE
-#define STM32_TIM7_CHANNELS                 0
-
-#define STM32_HAS_TIM15                     TRUE
-#define STM32_TIM15_IS_32BITS               FALSE
-#define STM32_TIM15_CHANNELS                2
-
-#define STM32_HAS_TIM16                     TRUE
-#define STM32_TIM16_IS_32BITS               FALSE
-#define STM32_TIM16_CHANNELS                2
-
-#define STM32_HAS_TIM17                     TRUE
-#define STM32_TIM17_IS_32BITS               FALSE
-#define STM32_TIM17_CHANNELS                2
-
-#define STM32_HAS_TIM4                      FALSE
-#define STM32_HAS_TIM5                      FALSE
-#define STM32_HAS_TIM8                      FALSE
-#define STM32_HAS_TIM9                      FALSE
-#define STM32_HAS_TIM10                     FALSE
-#define STM32_HAS_TIM11                     FALSE
-#define STM32_HAS_TIM12                     FALSE
-#define STM32_HAS_TIM13                     FALSE
-#define STM32_HAS_TIM14                     FALSE
-#define STM32_HAS_TIM18                     FALSE
-#define STM32_HAS_TIM19                     FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1                    TRUE
-#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
-#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
-
-#define STM32_HAS_USART2                    TRUE
-#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
-#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
-
-#define STM32_HAS_USART3                    TRUE
-#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
-#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
-
-#define STM32_HAS_UART4                     FALSE
-#define STM32_HAS_UART5                     FALSE
-#define STM32_HAS_USART6                    FALSE
-
-/* USB attributes.*/
-#define STM32_HAS_USB                       FALSE
-#define STM32_HAS_OTG1                      FALSE
-#define STM32_HAS_OTG2                      FALSE
-#endif /* defined(STM32F328x8) */
-
-/*===========================================================================*/
-/* STM32F358xC.                                                              */
-/*===========================================================================*/
-#if defined(STM32F358xC) || defined(__DOXYGEN__)
-/* ADC attributes.*/
-#define STM32_HAS_ADC1                      TRUE
-#define STM32_HAS_ADC2                      TRUE
-#define STM32_HAS_ADC3                      FALSE
-#define STM32_HAS_ADC4                      FALSE
-
-#define STM32_HAS_SDADC1                    FALSE
-#define STM32_HAS_SDADC2                    FALSE
-#define STM32_HAS_SDADC3                    FALSE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1                      TRUE
-#define STM32_HAS_CAN2                      FALSE
-#define STM32_CAN_MAX_FILTERS               14
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC1                      TRUE
-#define STM32_HAS_DAC2                      FALSE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA                  FALSE
-#define STM32_HAS_DMA1                      TRUE
-#define STM32_HAS_DMA2                      TRUE
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH                       FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS             34
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA                     TRUE
-#define STM32_HAS_GPIOB                     TRUE
-#define STM32_HAS_GPIOC                     TRUE
-#define STM32_HAS_GPIOD                     TRUE
-#define STM32_HAS_GPIOE                     TRUE
-#define STM32_HAS_GPIOF                     TRUE
-#define STM32_HAS_GPIOG                     FALSE
-#define STM32_HAS_GPIOH                     FALSE
-#define STM32_HAS_GPIOI                     FALSE
-#define STM32_GPIO_EN_MASK                  (RCC_AHBENR_GPIOAEN |           \
-                                             RCC_AHBENR_GPIOBEN |           \
-                                             RCC_AHBENR_GPIOCEN |           \
-                                             RCC_AHBENR_GPIODEN |           \
-                                             RCC_AHBENR_GPIOEEN |           \
-                                             RCC_AHBENR_GPIOFEN)
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1                      TRUE
-#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
-#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
-
-#define STM32_HAS_I2C2                      TRUE
-#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
-#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
-
-#define STM32_HAS_I2C3                      FALSE
-
-/* RTC attributes.*/
-#define STM32_HAS_RTC                       TRUE
-#define STM32_RTC_HAS_SUBSECONDS            TRUE
-#define STM32_RTC_HAS_PERIODIC_WAKEUPS      TRUE
-#define STM32_RTC_NUM_ALARMS                1
-#define STM32_RTC_HAS_INTERRUPTS            FALSE
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO                      FALSE
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1                      TRUE
-#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
-#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
-
-#define STM32_HAS_SPI2                      TRUE
-#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
-#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
-
-#define STM32_HAS_SPI3                      TRUE
-#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 1)
-#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 2)
-
-#define STM32_HAS_SPI4                      FALSE
-#define STM32_HAS_SPI5                      FALSE
-#define STM32_HAS_SPI6                      FALSE
-
-/* TIM attributes.*/
-#define STM32_TIM_MAX_CHANNELS              6
-
-#define STM32_HAS_TIM1                      TRUE
-#define STM32_TIM1_IS_32BITS                FALSE
-#define STM32_TIM1_CHANNELS                 6
-
-#define STM32_HAS_TIM2                      TRUE
-#define STM32_TIM2_IS_32BITS                TRUE
-#define STM32_TIM2_CHANNELS                 4
-
-#define STM32_HAS_TIM3                      TRUE
-#define STM32_TIM3_IS_32BITS                FALSE
-#define STM32_TIM3_CHANNELS                 4
-
-#define STM32_HAS_TIM4                      TRUE
-#define STM32_TIM4_IS_32BITS                FALSE
-#define STM32_TIM4_CHANNELS                 4
-
-#define STM32_HAS_TIM6                      TRUE
-#define STM32_TIM6_IS_32BITS                FALSE
-#define STM32_TIM6_CHANNELS                 0
-
-#define STM32_HAS_TIM15                     TRUE
-#define STM32_TIM15_IS_32BITS               FALSE
-#define STM32_TIM15_CHANNELS                2
-
-#define STM32_HAS_TIM16                     TRUE
-#define STM32_TIM16_IS_32BITS               FALSE
-#define STM32_TIM16_CHANNELS                2
-
-#define STM32_HAS_TIM17                     TRUE
-#define STM32_TIM17_IS_32BITS               FALSE
-#define STM32_TIM17_CHANNELS                2
-
-#define STM32_HAS_TIM5                      FALSE
-#define STM32_HAS_TIM7                      FALSE
-#define STM32_HAS_TIM8                      FALSE
-#define STM32_HAS_TIM9                      FALSE
-#define STM32_HAS_TIM10                     FALSE
-#define STM32_HAS_TIM11                     FALSE
-#define STM32_HAS_TIM12                     FALSE
-#define STM32_HAS_TIM13                     FALSE
-#define STM32_HAS_TIM14                     FALSE
-#define STM32_HAS_TIM18                     FALSE
-#define STM32_HAS_TIM19                     FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1                    TRUE
-#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
-#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
-
-#define STM32_HAS_USART2                    TRUE
-#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
-#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
-
-#define STM32_HAS_USART3                    TRUE
-#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
-#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
-
-#define STM32_HAS_UART4                     TRUE
-#define STM32_UART_UART4_RX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 3)
-#define STM32_UART_UART4_TX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 5)
-
-#define STM32_HAS_UART5                     TRUE
-
-#define STM32_HAS_USART6                    FALSE
-
-/* USB attributes.*/
-#define STM32_HAS_USB                       TRUE
-#define STM32_HAS_OTG1                      FALSE
-#define STM32_HAS_OTG2                      FALSE
-#endif /* defined(STM32F358xC) */
-
-
-/*===========================================================================*/
-/* STM32F334xC.                                                              */
-/*===========================================================================*/
-#if defined(STM32F334xC) || defined(__DOXYGEN__)
-/* ADC attributes.*/
-#define STM32_HAS_ADC1                      TRUE
-#define STM32_HAS_ADC2                      TRUE
-#define STM32_HAS_ADC3                      FALSE
-#define STM32_HAS_ADC4                      FALSE
-
-#define STM32_HAS_SDADC1                    FALSE
-#define STM32_HAS_SDADC2                    FALSE
-#define STM32_HAS_SDADC3                    FALSE
-
-/* CAN attributes.*/
-#define STM32_HAS_CAN1                      TRUE
-#define STM32_HAS_CAN2                      FALSE
-#define STM32_CAN_MAX_FILTERS               14
-
-/* DAC attributes.*/
-#define STM32_HAS_DAC1                      TRUE
-#define STM32_HAS_DAC2                      TRUE
-
-/* DMA attributes.*/
-#define STM32_ADVANCED_DMA                  FALSE
-#define STM32_HAS_DMA1                      TRUE
-#define STM32_HAS_DMA2                      FALSE
-
-/* ETH attributes.*/
-#define STM32_HAS_ETH                       FALSE
-
-/* EXTI attributes.*/
-#define STM32_EXTI_NUM_CHANNELS             33
-
-/* GPIO attributes.*/
-#define STM32_HAS_GPIOA                     TRUE
-#define STM32_HAS_GPIOB                     TRUE
-#define STM32_HAS_GPIOC                     TRUE
-#define STM32_HAS_GPIOD                     TRUE
-#define STM32_HAS_GPIOE                     FALSE
-#define STM32_HAS_GPIOF                     TRUE
-#define STM32_HAS_GPIOG                     FALSE
-#define STM32_HAS_GPIOH                     FALSE
-#define STM32_HAS_GPIOI                     FALSE
-#define STM32_GPIO_EN_MASK                  (RCC_AHBENR_GPIOAEN |           \
-                                             RCC_AHBENR_GPIOBEN |           \
-                                             RCC_AHBENR_GPIOCEN |           \
-                                             RCC_AHBENR_GPIODEN |           \
-                                             RCC_AHBENR_GPIOFEN)
-
-/* I2C attributes.*/
-#define STM32_HAS_I2C1                      TRUE
-#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
-#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
-
-#define STM32_HAS_I2C2                      FALSE
-#define STM32_HAS_I2C3                      FALSE
-
-/* RTC attributes.*/
-#define STM32_HAS_RTC                       TRUE
-#define STM32_RTC_HAS_SUBSECONDS            TRUE
-#define STM32_RTC_HAS_PERIODIC_WAKEUPS      TRUE
-#define STM32_RTC_NUM_ALARMS                1
-#define STM32_RTC_HAS_INTERRUPTS            FALSE
-
-/* SDIO attributes.*/
-#define STM32_HAS_SDIO                      FALSE
-
-/* SPI attributes.*/
-#define STM32_HAS_SPI1                      TRUE
-#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
-#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
-
-#define STM32_HAS_SPI2                      FALSE
-#define STM32_HAS_SPI3                      FALSE
-#define STM32_HAS_SPI4                      FALSE
-#define STM32_HAS_SPI5                      FALSE
-#define STM32_HAS_SPI6                      FALSE
-
-/* TIM attributes.*/
-#define STM32_TIM_MAX_CHANNELS              6
-
-#define STM32_HAS_TIM1                      TRUE
-#define STM32_TIM1_IS_32BITS                FALSE
-#define STM32_TIM1_CHANNELS                 6
-
-#define STM32_HAS_TIM2                      TRUE
-#define STM32_TIM2_IS_32BITS                TRUE
-#define STM32_TIM2_CHANNELS                 4
-
-#define STM32_HAS_TIM3                      TRUE
-#define STM32_TIM3_IS_32BITS                FALSE
-#define STM32_TIM3_CHANNELS                 4
-
-#define STM32_HAS_TIM6                      TRUE
-#define STM32_TIM6_IS_32BITS                FALSE
-#define STM32_TIM6_CHANNELS                 0
-
-#define STM32_HAS_TIM7                      TRUE
-#define STM32_TIM7_IS_32BITS                FALSE
-#define STM32_TIM7_CHANNELS                 0
-
-#define STM32_HAS_TIM15                     TRUE
-#define STM32_TIM15_IS_32BITS               FALSE
-#define STM32_TIM15_CHANNELS                2
-
-#define STM32_HAS_TIM16                     TRUE
-#define STM32_TIM16_IS_32BITS               FALSE
-#define STM32_TIM16_CHANNELS                2
-
-#define STM32_HAS_TIM17                     TRUE
-#define STM32_TIM17_IS_32BITS               FALSE
-#define STM32_TIM17_CHANNELS                2
-
-#define STM32_HAS_TIM4                      FALSE
-#define STM32_HAS_TIM5                      FALSE
-#define STM32_HAS_TIM8                      FALSE
-#define STM32_HAS_TIM9                      FALSE
-#define STM32_HAS_TIM10                     FALSE
-#define STM32_HAS_TIM11                     FALSE
-#define STM32_HAS_TIM12                     FALSE
-#define STM32_HAS_TIM13                     FALSE
-#define STM32_HAS_TIM14                     FALSE
-#define STM32_HAS_TIM18                     FALSE
-#define STM32_HAS_TIM19                     FALSE
-
-/* USART attributes.*/
-#define STM32_HAS_USART1                    TRUE
-#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
-#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
-
-#define STM32_HAS_USART2                    TRUE
-#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
-#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
-
-#define STM32_HAS_USART3                    TRUE
-#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
-#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
-
-#define STM32_HAS_UART4                     FALSE
-#define STM32_HAS_UART5                     FALSE
-#define STM32_HAS_USART6                    FALSE
-
-/* USB attributes.*/
-#define STM32_HAS_USB                       FALSE
-#define STM32_HAS_OTG1                      FALSE
-#define STM32_HAS_OTG2                      FALSE
-#endif /* defined(STM32F334xC) */
-
-/** @} */
-
-#endif /* _STM32_REGISTRY_H_ */
-
-/** @} */
diff --git a/os/hal/ports/STM32/STM32F3xx/adc_lld.c b/os/hal/ports/STM32/STM32F3xx/adc_lld.c
new file mode 100644
index 000000000..1ceb7dafd
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F3xx/adc_lld.c
@@ -0,0 +1,548 @@
+/*
+    ChibiOS/HAL - Copyright (C) 2006-2014 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F3xx/adc_lld.c
+ * @brief   STM32F3xx ADC subsystem low level driver source.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_ADC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+#if STM32_ADC_DUAL_MODE
+#if STM32_ADC_COMPACT_SAMPLES
+/* Compact type dual mode.*/
+#define ADC_DMA_SIZE    (STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD)
+#define ADC_DMA_MDMA    ADC_CCR_MDMA_HWORD
+
+#else /* !STM32_ADC_COMPACT_SAMPLES */
+/* Large type dual mode.*/
+#define ADC_DMA_SIZE    (STM32_DMA_CR_MSIZE_WORD | STM32_DMA_CR_PSIZE_WORD)
+#define ADC_DMA_MDMA    ADC_CCR_MDMA_WORD
+#endif /* !STM32_ADC_COMPACT_SAMPLES */
+
+#else /* !STM32_ADC_DUAL_MODE */
+#if STM32_ADC_COMPACT_SAMPLES
+/* Compact type single mode.*/
+#define ADC_DMA_SIZE    (STM32_DMA_CR_MSIZE_BYTE | STM32_DMA_CR_PSIZE_BYTE)
+#define ADC_DMA_MDMA    ADC_CCR_MDMA_DISABLED
+
+#else /* !STM32_ADC_COMPACT_SAMPLES */
+/* Large type single mode.*/
+#define ADC_DMA_SIZE    (STM32_DMA_CR_MSIZE_HWORD | STM32_DMA_CR_PSIZE_HWORD)
+#define ADC_DMA_MDMA    ADC_CCR_MDMA_DISABLED
+#endif /* !STM32_ADC_COMPACT_SAMPLES */
+#endif /* !STM32_ADC_DUAL_MODE */
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/** @brief ADC1 driver identifier.*/
+#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
+ADCDriver ADCD1;
+#endif
+
+/** @brief ADC1 driver identifier.*/
+#if STM32_ADC_USE_ADC3 || defined(__DOXYGEN__)
+ADCDriver ADCD3;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables the ADC voltage regulator.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ */
+static void adc_lld_vreg_on(ADCDriver *adcp) {
+
+  adcp->adcm->CR = 0;   /* RM 12.4.3.*/
+  adcp->adcm->CR = ADC_CR_ADVREGEN_0;
+#if STM32_ADC_DUAL_MODE
+  adcp->adcs->CR = ADC_CR_ADVREGEN_0;
+#endif
+  osalSysPolledDelayX(US2RTC(STM32_HCLK, 10));
+}
+
+/**
+ * @brief   Disables the ADC voltage regulator.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ */
+static void adc_lld_vreg_off(ADCDriver *adcp) {
+
+  adcp->adcm->CR = 0;   /* RM 12.4.3.*/
+  adcp->adcm->CR = ADC_CR_ADVREGEN_1;
+#if STM32_ADC_DUAL_MODE
+  adcp->adcs->CR = ADC_CR_ADVREGEN_1;
+#endif
+}
+
+/**
+ * @brief   Enables the ADC analog circuit.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ */
+static void adc_lld_analog_on(ADCDriver *adcp) {
+
+  adcp->adcm->CR |= ADC_CR_ADEN;
+  while ((adcp->adcm->ISR & ADC_ISR_ADRD) == 0)
+    ;
+#if STM32_ADC_DUAL_MODE
+  adcp->adcs->CR |= ADC_CR_ADEN;
+  while ((adcp->adcs->ISR & ADC_ISR_ADRD) == 0)
+    ;
+#endif
+}
+
+/**
+ * @brief   Disables the ADC  analog circuit.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ */
+static void adc_lld_analog_off(ADCDriver *adcp) {
+
+  adcp->adcm->CR |= ADC_CR_ADDIS;
+  while ((adcp->adcm->CR & ADC_CR_ADDIS) != 0)
+    ;
+#if STM32_ADC_DUAL_MODE
+  adcp->adcs->CR |= ADC_CR_ADDIS;
+  while ((adcp->adcs->CR & ADC_CR_ADDIS) != 0)
+    ;
+#endif
+}
+
+/**
+ * @brief   Calibrates and ADC unit.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ */
+static void adc_lld_calibrate(ADCDriver *adcp) {
+
+  osalDbgAssert(adcp->adcm->CR == ADC_CR_ADVREGEN_0, "invalid register state");
+  adcp->adcm->CR |= ADC_CR_ADCAL;
+  while ((adcp->adcm->CR & ADC_CR_ADCAL) != 0)
+    ;
+#if STM32_ADC_DUAL_MODE
+  osalDbgAssert(adcp->adcs->CR == ADC_CR_ADVREGEN_0, "invalid register state");
+  adcp->adcs->CR |= ADC_CR_ADCAL;
+  while ((adcp->adcs->CR & ADC_CR_ADCAL) != 0)
+    ;
+#endif
+}
+
+/**
+ * @brief   Stops an ongoing conversion, if any.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ */
+static void adc_lld_stop_adc(ADCDriver *adcp) {
+
+  if (adcp->adcm->CR & ADC_CR_ADSTART) {
+    adcp->adcm->CR |= ADC_CR_ADSTP;
+    while (adcp->adcm->CR & ADC_CR_ADSTP)
+      ;
+  }
+}
+
+/**
+ * @brief   ADC DMA ISR service routine.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ * @param[in] flags     pre-shifted content of the ISR register
+ */
+static void adc_lld_serve_dma_interrupt(ADCDriver *adcp, uint32_t flags) {
+
+  /* DMA errors handling.*/
+  if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) {
+    /* DMA, this could help only if the DMA tries to access an unmapped
+       address space or violates alignment rules.*/
+    _adc_isr_error_code(adcp, ADC_ERR_DMAFAILURE);
+  }
+  else {
+    /* It is possible that the conversion group has already be reset by the
+       ADC error handler, in this case this interrupt is spurious.*/
+    if (adcp->grpp != NULL) {
+      if ((flags & STM32_DMA_ISR_TCIF) != 0) {
+        /* Transfer complete processing.*/
+        _adc_isr_full_code(adcp);
+      }
+      else if ((flags & STM32_DMA_ISR_HTIF) != 0) {
+        /* Half transfer processing.*/
+        _adc_isr_half_code(adcp);
+      }
+    }
+  }
+}
+
+/**
+ * @brief   ADC ISR service routine.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ * @param[in] isr       content of the ISR register
+ */
+static void adc_lld_serve_interrupt(ADCDriver *adcp, uint32_t isr) {
+
+  /* It could be a spurious interrupt caused by overflows after DMA disabling,
+     just ignore it in this case.*/
+  if (adcp->grpp != NULL) {
+    /* Note, an overflow may occur after the conversion ended before the driver
+       is able to stop the ADC, this is why the DMA channel is checked too.*/
+    if ((isr & ADC_ISR_OVR) &&
+        (dmaStreamGetTransactionSize(adcp->dmastp) > 0)) {
+      /* ADC overflow condition, this could happen only if the DMA is unable
+         to read data fast enough.*/
+      _adc_isr_error_code(adcp, ADC_ERR_OVERFLOW);
+    }
+    if (isr & ADC_ISR_AWD1) {
+      /* Analog watchdog error.*/
+      _adc_isr_error_code(adcp, ADC_ERR_AWD1);
+    }
+    if (isr & ADC_ISR_AWD2) {
+      /* Analog watchdog error.*/
+      _adc_isr_error_code(adcp, ADC_ERR_AWD2);
+    }
+    if (isr & ADC_ISR_AWD3) {
+      /* Analog watchdog error.*/
+      _adc_isr_error_code(adcp, ADC_ERR_AWD3);
+    }
+  }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if STM32_ADC_USE_ADC1 || defined(__DOXYGEN__)
+/**
+ * @brief   ADC1/ADC2 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector88) {
+  uint32_t isr;
+
+  OSAL_IRQ_PROLOGUE();
+
+#if STM32_ADC_DUAL_MODE
+  isr  = ADC1->ISR;
+  isr |= ADC2->ISR;
+  ADC1->ISR = isr;
+  ADC2->ISR = isr;
+#else /* !STM32_ADC_DUAL_MODE */
+  isr  = ADC1->ISR;
+  ADC1->ISR = isr;
+#endif /* !STM32_ADC_DUAL_MODE */
+
+  adc_lld_serve_interrupt(&ADCD1, isr);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_ADC_USE_ADC1 */
+
+#if STM32_ADC_USE_ADC3 || defined(__DOXYGEN__)
+/**
+ * @brief   ADC3 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(VectorFC) {
+  uint32_t isr;
+
+  OSAL_IRQ_PROLOGUE();
+
+  isr  = ADC3->ISR;
+  ADC3->ISR = isr;
+
+  adc_lld_serve_interrupt(&ADCD3, isr);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+#if STM32_ADC_DUAL_MODE
+/**
+ * @brief   ADC4 interrupt handler (as ADC3 slave).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector134) {
+  uint32_t isr;
+
+  OSAL_IRQ_PROLOGUE();
+
+  isr  = ADC4->ISR;
+  ADC4->ISR = isr;
+
+  adc_lld_serve_interrupt(&ADCD3, isr);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* STM32_ADC_DUAL_MODE */
+#endif /* STM32_ADC_USE_ADC3 */
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level ADC driver initialization.
+ *
+ * @notapi
+ */
+void adc_lld_init(void) {
+
+#if STM32_ADC_USE_ADC1
+  /* Driver initialization.*/
+  adcObjectInit(&ADCD1);
+  ADCD1.adcc = ADC1_2_COMMON;
+  ADCD1.adcm = ADC1;
+#if STM32_ADC_DUAL_MODE
+  ADCD1.adcs = ADC2;
+#endif
+  ADCD1.dmastp  = STM32_DMA1_STREAM1;
+  ADCD1.dmamode = ADC_DMA_SIZE |
+                  STM32_DMA_CR_PL(STM32_ADC_ADC12_DMA_PRIORITY) |
+                  STM32_DMA_CR_DIR_P2M |
+                  STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |
+                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;
+  nvicEnableVector(ADC1_2_IRQn, STM32_ADC_ADC12_IRQ_PRIORITY);
+#endif /* STM32_ADC_USE_ADC1 */
+
+#if STM32_ADC_USE_ADC3
+  /* Driver initialization.*/
+  adcObjectInit(&ADCD3);
+  ADCD3.adcc = ADC3_4_COMMON;
+  ADCD3.adcm = ADC3;
+#if STM32_ADC_DUAL_MODE
+  ADCD3.adcs = ADC4;
+#endif
+  ADCD3.dmastp  = STM32_DMA2_STREAM5;
+  ADCD3.dmamode = ADC_DMA_SIZE |
+                  STM32_DMA_CR_PL(STM32_ADC_ADC12_DMA_PRIORITY) |
+                  STM32_DMA_CR_DIR_P2M |
+                  STM32_DMA_CR_MINC        | STM32_DMA_CR_TCIE        |
+                  STM32_DMA_CR_DMEIE       | STM32_DMA_CR_TEIE;
+  nvicEnableVector(ADC3_IRQn, STM32_ADC_ADC34_IRQ_PRIORITY);
+#if STM32_ADC_DUAL_MODE
+  nvicEnableVector(ADC4_IRQn, STM32_ADC_ADC34_IRQ_PRIORITY);
+#endif
+#endif /* STM32_ADC_USE_ADC3 */
+}
+
+/**
+ * @brief   Configures and activates the ADC peripheral.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start(ADCDriver *adcp) {
+
+  /* If in stopped state then enables the ADC and DMA clocks.*/
+  if (adcp->state == ADC_STOP) {
+#if STM32_ADC_USE_ADC1
+    if (&ADCD1 == adcp) {
+      bool b;
+      b = dmaStreamAllocate(adcp->dmastp,
+                            STM32_ADC_ADC12_DMA_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
+                            (void *)adcp);
+      osalDbgAssert(!b, "stream already allocated");
+      rccEnableADC12(FALSE);
+    }
+#endif /* STM32_ADC_USE_ADC1 */
+
+#if STM32_ADC_USE_ADC3
+    if (&ADCD3 == adcp) {
+      bool b;
+      b = dmaStreamAllocate(adcp->dmastp,
+                            STM32_ADC_ADC34_DMA_IRQ_PRIORITY,
+                            (stm32_dmaisr_t)adc_lld_serve_dma_interrupt,
+                            (void *)adcp);
+      osalDbgAssert(!b, "stream already allocated");
+      rccEnableADC34(FALSE);
+    }
+#endif /* STM32_ADC_USE_ADC2 */
+
+    /* Setting DMA peripheral-side pointer.*/
+#if STM32_ADC_DUAL_MODE
+      dmaStreamSetPeripheral(adcp->dmastp, &adcp->adcc->CDR);
+#else
+      dmaStreamSetPeripheral(adcp->dmastp, &adcp->adcm->DR);
+#endif
+
+    /* Clock source setting.*/
+    adcp->adcc->CCR = STM32_ADC_ADC12_CLOCK_MODE | ADC_DMA_MDMA;
+
+    /* Master ADC calibration.*/
+    adc_lld_vreg_on(adcp);
+    adc_lld_calibrate(adcp);
+
+    /* Master ADC enabled here in order to reduce conversions latencies.*/
+    adc_lld_analog_on(adcp);
+  }
+}
+
+/**
+ * @brief   Deactivates the ADC peripheral.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop(ADCDriver *adcp) {
+
+  /* If in ready state then disables the ADC clock and analog part.*/
+  if (adcp->state == ADC_READY) {
+
+    /* Releasing the associated DMA channel.*/
+    dmaStreamRelease(adcp->dmastp);
+
+    /* Stopping the ongoing conversion, if any.*/
+    adc_lld_stop_adc(adcp);
+
+    /* Disabling ADC analog circuit and regulator.*/
+    adc_lld_analog_off(adcp);
+    adc_lld_vreg_off(adcp);
+
+#if STM32_ADC_USE_ADC1
+    if (&ADCD1 == adcp)
+      rccDisableADC12(FALSE);
+#endif
+
+#if STM32_ADC_USE_ADC3
+    if (&ADCD3 == adcp)
+      rccDisableADC34(FALSE);
+#endif
+  }
+}
+
+/**
+ * @brief   Starts an ADC conversion.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_start_conversion(ADCDriver *adcp) {
+  uint32_t dmamode, ccr, cfgr;
+  const ADCConversionGroup *grpp = adcp->grpp;
+
+  osalDbgAssert(!STM32_ADC_DUAL_MODE || ((grpp->num_channels & 1) == 0),
+                "odd number of channels in dual mode");
+
+  /* Calculating control registers values.*/
+  dmamode = adcp->dmamode;
+  ccr     = grpp->ccr | (adcp->adcc->CCR & (ADC_CCR_CKMODE_MASK |
+                                            ADC_CCR_MDMA_MASK));
+  cfgr    = grpp->cfgr | ADC_CFGR_DMAEN;
+  if (grpp->circular) {
+    dmamode |= STM32_DMA_CR_CIRC;
+#if STM32_ADC_DUAL_MODE
+    ccr  |= ADC_CCR_DMACFG_CIRCULAR;
+#else
+    cfgr |= ADC_CFGR_DMACFG_CIRCULAR;
+#endif
+    if (adcp->depth > 1) {
+      /* If circular buffer depth > 1, then the half transfer interrupt
+         is enabled in order to allow streaming processing.*/
+      dmamode |= STM32_DMA_CR_HTIE;
+    }
+  }
+
+  /* DMA setup.*/
+  dmaStreamSetMemory0(adcp->dmastp, adcp->samples);
+#if STM32_ADC_DUAL_MODE
+  dmaStreamSetTransactionSize(adcp->dmastp, ((uint32_t)grpp->num_channels/2) *
+                                            (uint32_t)adcp->depth);
+#else
+    dmaStreamSetTransactionSize(adcp->dmastp, (uint32_t)grpp->num_channels *
+                                              (uint32_t)adcp->depth);
+#endif
+  dmaStreamSetMode(adcp->dmastp, dmamode);
+  dmaStreamEnable(adcp->dmastp);
+
+  /* Configuring the CCR register with the static settings ORed with
+     the user-specified settings in the conversion group configuration
+     structure.*/
+  adcp->adcc->CCR   = ccr;
+
+  /* ADC setup, if it is defined a callback for the analog watch dog then it
+     is enabled.*/
+  adcp->adcm->ISR   = adcp->adcm->ISR;
+  adcp->adcm->IER   = ADC_IER_OVR | ADC_IER_AWD1;
+  adcp->adcm->TR1   = grpp->tr1;
+#if STM32_ADC_DUAL_MODE
+  adcp->adcm->SMPR1 = grpp->smpr[0];
+  adcp->adcm->SMPR2 = grpp->smpr[1];
+  adcp->adcm->SQR1  = grpp->sqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels / 2);
+  adcp->adcm->SQR2  = grpp->sqr[1];
+  adcp->adcm->SQR3  = grpp->sqr[2];
+  adcp->adcm->SQR4  = grpp->sqr[3];
+  adcp->adcs->SMPR1 = grpp->ssmpr[0];
+  adcp->adcs->SMPR2 = grpp->ssmpr[1];
+  adcp->adcs->SQR1  = grpp->ssqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels / 2);
+  adcp->adcs->SQR2  = grpp->ssqr[1];
+  adcp->adcs->SQR3  = grpp->ssqr[2];
+  adcp->adcs->SQR4  = grpp->ssqr[3];
+
+#else /* !STM32_ADC_DUAL_MODE */
+  adcp->adcm->SMPR1 = grpp->smpr[0];
+  adcp->adcm->SMPR2 = grpp->smpr[1];
+  adcp->adcm->SQR1  = grpp->sqr[0] | ADC_SQR1_NUM_CH(grpp->num_channels);
+  adcp->adcm->SQR2  = grpp->sqr[1];
+  adcp->adcm->SQR3  = grpp->sqr[2];
+  adcp->adcm->SQR4  = grpp->sqr[3];
+#endif /* !STM32_ADC_DUAL_MODE */
+
+  /* ADC configuration.*/
+  adcp->adcm->CFGR  = cfgr;
+
+  /* Starting conversion.*/
+  adcp->adcm->CR   |= ADC_CR_ADSTART;
+}
+
+/**
+ * @brief   Stops an ongoing conversion.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object
+ *
+ * @notapi
+ */
+void adc_lld_stop_conversion(ADCDriver *adcp) {
+
+  dmaStreamDisable(adcp->dmastp);
+  adc_lld_stop_adc(adcp);
+}
+
+#endif /* HAL_USE_ADC */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F3xx/adc_lld.h b/os/hal/ports/STM32/STM32F3xx/adc_lld.h
new file mode 100644
index 000000000..a2631505a
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F3xx/adc_lld.h
@@ -0,0 +1,619 @@
+/*
+    ChibiOS/HAL - Copyright (C) 2006-2014 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F3xx/adc_lld.h
+ * @brief   STM32F3xx ADC subsystem low level driver header.
+ *
+ * @addtogroup ADC
+ * @{
+ */
+
+#ifndef _ADC_LLD_H_
+#define _ADC_LLD_H_
+
+#if HAL_USE_ADC || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Available analog channels
+ * @{
+ */
+#define ADC_CHANNEL_IN1         1   /**< @brief External analog input 1.    */
+#define ADC_CHANNEL_IN2         2   /**< @brief External analog input 2.    */
+#define ADC_CHANNEL_IN3         3   /**< @brief External analog input 3.    */
+#define ADC_CHANNEL_IN4         4   /**< @brief External analog input 4.    */
+#define ADC_CHANNEL_IN5         5   /**< @brief External analog input 5.    */
+#define ADC_CHANNEL_IN6         6   /**< @brief External analog input 6.    */
+#define ADC_CHANNEL_IN7         7   /**< @brief External analog input 7.    */
+#define ADC_CHANNEL_IN8         8   /**< @brief External analog input 8.    */
+#define ADC_CHANNEL_IN9         9   /**< @brief External analog input 9.    */
+#define ADC_CHANNEL_IN10        10  /**< @brief External analog input 10.   */
+#define ADC_CHANNEL_IN11        11  /**< @brief External analog input 11.   */
+#define ADC_CHANNEL_IN12        12  /**< @brief External analog input 12.   */
+#define ADC_CHANNEL_IN13        13  /**< @brief External analog input 13.   */
+#define ADC_CHANNEL_IN14        14  /**< @brief External analog input 14.   */
+#define ADC_CHANNEL_IN15        15  /**< @brief External analog input 15.   */
+#define ADC_CHANNEL_IN16        16  /**< @brief External analog input 16.   */
+#define ADC_CHANNEL_IN17        17  /**< @brief External analog input 17.   */
+#define ADC_CHANNEL_IN18        18  /**< @brief External analog input 18.   */
+/** @} */
+
+/**
+ * @name    Sampling rates
+ * @{
+ */
+#define ADC_SMPR_SMP_1P5        0   /**< @brief 14 cycles conversion time   */
+#define ADC_SMPR_SMP_2P5        1   /**< @brief 15 cycles conversion time.  */
+#define ADC_SMPR_SMP_4P5        2   /**< @brief 17 cycles conversion time.  */
+#define ADC_SMPR_SMP_7P5        3   /**< @brief 20 cycles conversion time.  */
+#define ADC_SMPR_SMP_19P5       4   /**< @brief 32 cycles conversion time.  */
+#define ADC_SMPR_SMP_61P5       5   /**< @brief 74 cycles conversion time.  */
+#define ADC_SMPR_SMP_181P5      6   /**< @brief 194 cycles conversion time. */
+#define ADC_SMPR_SMP_601P5      7   /**< @brief 614 cycles conversion time. */
+/** @} */
+
+/**
+ * @name    Resolution
+ * @{
+ */
+#define ADC_CFGR1_RES_12BIT     (0 << 3)
+#define ADC_CFGR1_RES_10BIT     (1 << 3)
+#define ADC_CFGR1_RES_8BIT      (2 << 3)
+#define ADC_CFGR1_RES_6BIT      (3 << 3)
+/** @} */
+
+/**
+ * @name    CFGR register configuration helpers
+ * @{
+ */
+#define ADC_CFGR_DMACFG_MASK            (1 << 1)
+#define ADC_CFGR_DMACFG_ONESHOT         (0 << 1)
+#define ADC_CFGR_DMACFG_CIRCULAR        (1 << 1)
+
+#define ADC_CFGR_RES_MASK               (3 << 3)
+#define ADC_CFGR_RES_12BITS             (0 << 3)
+#define ADC_CFGR_RES_10BITS             (1 << 3)
+#define ADC_CFGR_RES_8BITS              (2 << 3)
+#define ADC_CFGR_RES_6BITS              (3 << 3)
+
+#define ADC_CFGR_ALIGN_MASK             (1 << 5)
+#define ADC_CFGR_ALIGN_RIGHT            (0 << 5)
+#define ADC_CFGR_ALIGN_LEFT             (1 << 5)
+
+#define ADC_CFGR_EXTSEL_MASK            (15 << 6)
+#define ADC_CFGR_EXTSEL_SRC(n)          ((n) << 6)
+
+#define ADC_CFGR_EXTEN_MASK             (3 << 10)
+#define ADC_CFGR_EXTEN_DISABLED         (0 << 10)
+#define ADC_CFGR_EXTEN_RISING           (1 << 10)
+#define ADC_CFGR_EXTEN_FALLING          (2 << 10)
+#define ADC_CFGR_EXTEN_BOTH             (3 << 10)
+
+#define ADC_CFGR_DISCEN_MASK            (1 << 16)
+#define ADC_CFGR_DISCEN_DISABLED        (0 << 16)
+#define ADC_CFGR_DISCEN_ENABLED         (1 << 16)
+
+#define ADC_CFGR_DISCNUM_MASK           (7 << 17)
+#define ADC_CFGR_DISCNUM_VAL(n)         ((n) << 17)
+
+#define ADC_CFGR_AWD1_DISABLED          0
+#define ADC_CFGR_AWD1_ALL               (1 << 23)
+#define ADC_CFGR_AWD1_SINGLE(n)         (((n) << 26) | (1 << 23) | (1 << 22))
+/** @} */
+
+/**
+ * @name    CCR register configuration helpers
+ * @{
+ */
+#define ADC_CCR_DUAL_MASK               (31 << 0)
+#define ADC_CCR_DUAL(n)                 ((n) << 0)
+#define ADC_CCR_DELAY_MASK              (15 << 8)
+#define ADC_CCR_DELAY(n)                ((n) << 8)
+#define ADC_CCR_DMACFG_MASK             (1 << 13)
+#define ADC_CCR_DMACFG_ONESHOT          (0 << 13)
+#define ADC_CCR_DMACFG_CIRCULAR         (1 << 13)
+#define ADC_CCR_MDMA_MASK               (3 << 14)
+#define ADC_CCR_MDMA_DISABLED           (0 << 14)
+#define ADC_CCR_MDMA_WORD               (2 << 14)
+#define ADC_CCR_MDMA_HWORD              (3 << 14)
+#define ADC_CCR_CKMODE_MASK             (3 << 16)
+#define ADC_CCR_CKMODE_ADCCK            (0 << 16)
+#define ADC_CCR_CKMODE_AHB_DIV1         (1 << 16)
+#define ADC_CCR_CKMODE_AHB_DIV2         (2 << 16)
+#define ADC_CCR_CKMODE_AHB_DIV4         (3 << 16)
+#define ADC_CCR_VREFEN                  (1 << 22)
+#define ADC_CCR_TSEN                    (1 << 23)
+#define ADC_CCR_VBATEN                  (1 << 24)
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   ADC1 driver enable switch.
+ * @details If set to @p TRUE the support for ADC1 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(STM32_ADC_USE_ADC1) || defined(__DOXYGEN__)
+#define STM32_ADC_USE_ADC1                  FALSE
+#endif
+
+/**
+ * @brief   ADC3 driver enable switch.
+ * @details If set to @p TRUE the support for ADC3 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(STM32_ADC_USE_ADC3) || defined(__DOXYGEN__)
+#define STM32_ADC_USE_ADC3                  FALSE
+#endif
+
+/**
+ * @brief   ADC1/ADC2 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_ADC_ADC12_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC12_DMA_PRIORITY        2
+#endif
+
+/**
+ * @brief   ADC3/ADC4 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_ADC_ADC34_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC34_DMA_PRIORITY        2
+#endif
+
+/**
+ * @brief   ADC1/ADC2 interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_ADC12_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC12_IRQ_PRIORITY        5
+#endif
+
+/**
+ * @brief   ADC3/ADC4 interrupt priority level setting.
+ */
+#if !defined(STM32_ADC34_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC34_IRQ_PRIORITY        5
+#endif
+
+/**
+ * @brief   ADC1/ADC2 DMA interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_ADC12_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC12_DMA_IRQ_PRIORITY    5
+#endif
+
+/**
+ * @brief   ADC3/ADC4 DMA interrupt priority level setting.
+ */
+#if !defined(STM32_ADC_ADC34_DMA_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC34_DMA_IRQ_PRIORITY    5
+#endif
+
+/**
+ * @brief   ADC1/ADC2 clock source and mode.
+ */
+#if !defined(STM32_ADC_ADC12_CLOCK_MODE) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC12_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1
+#endif
+
+/**
+ * @brief   ADC3/ADC4 clock source and mode.
+ */
+#if !defined(STM32_ADC_ADC34_CLOCK_MODE) || defined(__DOXYGEN__)
+#define STM32_ADC_ADC34_CLOCK_MODE          ADC_CCR_CKMODE_AHB_DIV1
+#endif
+
+/**
+ * @brief   Enables the ADC master/slave mode.
+ */
+#if !defined(STM32_ADC_DUAL_MODE) || defined(__DOXYGEN__)
+#define STM32_ADC_DUAL_MODE                 FALSE
+#endif
+
+/**
+ * @brief   Makes the ADC samples type an 8bits one.
+ */
+#if !defined(STM32_ADC_COMPACT_SAMPLES) || defined(__DOXYGEN__)
+#define STM32_ADC_COMPACT_SAMPLES           FALSE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if STM32_ADC_USE_ADC1 && !STM32_HAS_ADC1
+#error "ADC1 not present in the selected device"
+#endif
+
+#if STM32_ADC_DUAL_MODE && STM32_ADC_USE_ADC1 && !STM32_HAS_ADC2
+#error "ADC2 not present in the selected device"
+#endif
+
+#if STM32_ADC_USE_ADC3 && !STM32_HAS_ADC3
+#error "ADC3 not present in the selected device"
+#endif
+
+#if STM32_ADC_DUAL_MODE && STM32_ADC_USE_ADC2 && !STM32_HAS_ADC4
+#error "ADC4 not present in the selected device"
+#endif
+
+#if !STM32_ADC_USE_ADC1 && !STM32_ADC_USE_ADC3
+#error "ADC driver activated but no ADC peripheral assigned"
+#endif
+
+#if STM32_ADC_USE_ADC1 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC12_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to ADC1"
+#endif
+
+#if STM32_ADC_USE_ADC1 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC12_DMA_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to ADC1 DMA"
+#endif
+
+#if STM32_ADC_USE_ADC1 &&                                                   \
+    !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC12_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to ADC1"
+#endif
+
+#if STM32_ADC_USE_ADC3 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC34_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to ADC3"
+#endif
+
+#if STM32_ADC_USE_ADC3 &&                                                   \
+    !CORTEX_IS_VALID_KERNEL_PRIORITY(STM32_ADC_ADC34_DMA_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to ADC3 DMA"
+#endif
+
+#if STM32_ADC_USE_ADC3 &&                                                   \
+    !STM32_DMA_IS_VALID_PRIORITY(STM32_ADC_ADC34_DMA_PRIORITY)
+#error "Invalid DMA priority assigned to ADC3"
+#endif
+
+#if STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
+#define STM32_ADC12_CLOCK               STM32_ADC12CLK
+#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
+#define STM32_ADC12_CLOCK               (STM32_HCLK / 1)
+#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
+#define STM32_ADC12_CLOCK               (STM32_HCLK / 2)
+#elif STM32_ADC_ADC12_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
+#define STM32_ADC12_CLOCK               (STM32_HCLK / 4)
+#else
+#error "invalid clock mode selected for STM32_ADC_ADC12_CLOCK_MODE"
+#endif
+
+#if STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_ADCCK
+#define STM32_ADC34_CLOCK               STM32_ADC34CLK
+#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV1
+#define STM32_ADC34_CLOCK               (STM32_HCLK / 1)
+#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV2
+#define STM32_ADC34_CLOCK               (STM32_HCLK / 2)
+#elif STM32_ADC_ADC34_CLOCK_MODE == ADC_CCR_CKMODE_AHB_DIV4
+#define STM32_ADC34_CLOCK               (STM32_HCLK / 4)
+#else
+#error "invalid clock mode selected for STM32_ADC_ADC12_CLOCK_MODE"
+#endif
+
+#if STM32_ADC12_CLOCK > 72000000
+#error "STM32_ADC12_CLOCK exceeding maximum frequency (72000000)"
+#endif
+
+#if STM32_ADC34_CLOCK > 72000000
+#error "STM32_ADC34_CLOCK exceeding maximum frequency (72000000)"
+#endif
+
+#if !defined(STM32_DMA_REQUIRED)
+#define STM32_DMA_REQUIRED
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   ADC sample data type.
+ */
+#if !STM32_ADC_COMPACT_SAMPLES || defined(__DOXYGEN__)
+typedef uint16_t adcsample_t;
+#else
+typedef uint8_t adcsample_t;
+#endif
+
+/**
+ * @brief   Channels number in a conversion group.
+ */
+typedef uint16_t adc_channels_num_t;
+
+/**
+ * @brief   Possible ADC failure causes.
+ * @note    Error codes are architecture dependent and should not relied
+ *          upon.
+ */
+typedef enum {
+  ADC_ERR_DMAFAILURE = 0,                   /**< DMA operations failure.    */
+  ADC_ERR_OVERFLOW = 1,                     /**< ADC overflow condition.    */
+  ADC_ERR_AWD1 = 2,                         /**< Watchdog 1 triggered.      */
+  ADC_ERR_AWD2 = 3,                         /**< Watchdog 2 triggered.      */
+  ADC_ERR_AWD3 = 4                          /**< Watchdog 3 triggered.      */
+} adcerror_t;
+
+/**
+ * @brief   Type of a structure representing an ADC driver.
+ */
+typedef struct ADCDriver ADCDriver;
+
+/**
+ * @brief   ADC notification callback type.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object triggering the
+ *                      callback
+ * @param[in] buffer    pointer to the most recent samples data
+ * @param[in] n         number of buffer rows available starting from @p buffer
+ */
+typedef void (*adccallback_t)(ADCDriver *adcp, adcsample_t *buffer, size_t n);
+
+/**
+ * @brief   ADC error callback type.
+ *
+ * @param[in] adcp      pointer to the @p ADCDriver object triggering the
+ *                      callback
+ * @param[in] err       ADC error code
+ */
+typedef void (*adcerrorcallback_t)(ADCDriver *adcp, adcerror_t err);
+
+/**
+ * @brief   Conversion group configuration structure.
+ * @details This implementation-dependent structure describes a conversion
+ *          operation.
+ * @note    The use of this configuration structure requires knowledge of
+ *          STM32 ADC cell registers interface, please refer to the STM32
+ *          reference manual for details.
+ */
+typedef struct {
+  /**
+   * @brief   Enables the circular buffer mode for the group.
+   */
+  bool                      circular;
+  /**
+   * @brief   Number of the analog channels belonging to the conversion group.
+   */
+  adc_channels_num_t        num_channels;
+  /**
+   * @brief   Callback function associated to the group or @p NULL.
+   */
+  adccallback_t             end_cb;
+  /**
+   * @brief   Error callback or @p NULL.
+   */
+  adcerrorcallback_t        error_cb;
+  /* End of the mandatory fields.*/
+  /**
+   * @brief   ADC CFGR register initialization data.
+   * @note    The bits DMAEN and DMACFG are enforced internally
+   *          to the driver, keep them to zero.
+   * @note    The bits @p ADC_CFGR_CONT or @p ADC_CFGR_DISCEN must be
+   *          specified in continuous more or if the buffer depth is
+   *          greater than one.
+   */
+  uint32_t                  cfgr;
+  /**
+   * @brief   ADC TR1 register initialization data.
+   */
+  uint32_t                  tr1;
+  /**
+   * @brief   ADC CCR register initialization data.
+   * @note    The bits CKMODE, MDMA, DMACFG are enforced internally to the
+   *          driver, keep them to zero.
+   */
+  uint32_t                  ccr;
+  /**
+   * @brief   ADC SMPRx registers initialization data.
+   */
+  uint32_t                  smpr[2];
+  /**
+   * @brief   ADC SQRx register initialization data.
+   */
+  uint32_t                  sqr[4];
+#if STM32_ADC_DUAL_MODE || defined(__DOXYGEN__)
+  /**
+   * @brief   Slave ADC SMPRx registers initialization data.
+   */
+  uint32_t                  ssmpr[2];
+  /**
+   * @brief   Slave ADC SQRx register initialization data.
+   */
+  uint32_t                  ssqr[4];
+#endif /* STM32_ADC_DUAL_MODE */
+} ADCConversionGroup;
+
+/**
+ * @brief   Driver configuration structure.
+ * @note    It could be empty on some architectures.
+ */
+typedef struct {
+  uint32_t                  dummy;
+} ADCConfig;
+
+/**
+ * @brief   Structure representing an ADC driver.
+ */
+struct ADCDriver {
+  /**
+   * @brief   Driver state.
+   */
+  adcstate_t                state;
+  /**
+   * @brief   Current configuration data.
+   */
+  const ADCConfig           *config;
+  /**
+   * @brief   Current samples buffer pointer or @p NULL.
+   */
+  adcsample_t               *samples;
+  /**
+   * @brief   Current samples buffer depth or @p 0.
+   */
+  size_t                    depth;
+  /**
+   * @brief   Current conversion group pointer or @p NULL.
+   */
+  const ADCConversionGroup  *grpp;
+#if ADC_USE_WAIT || defined(__DOXYGEN__)
+  /**
+   * @brief   Waiting thread.
+   */
+  thread_reference_t        thread;
+#endif
+#if ADC_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+  /**
+   * @brief   Mutex protecting the peripheral.
+   */
+  mutex_t                   mutex;
+#endif /* ADC_USE_MUTUAL_EXCLUSION */
+#if defined(ADC_DRIVER_EXT_FIELDS)
+  ADC_DRIVER_EXT_FIELDS
+#endif
+  /* End of the mandatory fields.*/
+  /**
+   * @brief   Pointer to the common ADCx_y registers block.
+   */
+  ADC_Common_TypeDef        *adcc;
+  /**
+   * @brief   Pointer to the master ADCx registers block.
+   */
+  ADC_TypeDef               *adcm;
+#if STM32_ADC_DUAL_MODE || defined(__DOXYGEN__)
+  /**
+   * @brief   Pointer to the slave ADCx registers block.
+   */
+  ADC_TypeDef               *adcs;
+#endif /* STM32_ADC_DUAL_MODE */
+  /**
+   * @brief   Pointer to associated DMA channel.
+   */
+  const stm32_dma_stream_t  *dmastp;
+  /**
+   * @brief   DMA mode bit mask.
+   */
+  uint32_t                  dmamode;
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @name    Threashold register initializer
+ * @{
+ */
+#define ADC_TR(low, high)       (((uint32_t)(high) << 16) | (uint32_t)(low))
+/** @} */
+
+/**
+ * @name    Sequences building helper macros
+ * @{
+ */
+/**
+ * @brief   Number of channels in a conversion sequence.
+ */
+#define ADC_SQR1_NUM_CH(n)      (((n) - 1) << 0)
+
+#define ADC_SQR1_SQ1_N(n)       ((n) << 6)  /**< @brief 1st channel in seq. */
+#define ADC_SQR1_SQ2_N(n)       ((n) << 12) /**< @brief 2nd channel in seq. */
+#define ADC_SQR1_SQ3_N(n)       ((n) << 18) /**< @brief 3rd channel in seq. */
+#define ADC_SQR1_SQ4_N(n)       ((n) << 24) /**< @brief 4th channel in seq. */
+
+#define ADC_SQR2_SQ5_N(n)       ((n) << 0)  /**< @brief 5th channel in seq. */
+#define ADC_SQR2_SQ6_N(n)       ((n) << 6)  /**< @brief 6th channel in seq. */
+#define ADC_SQR2_SQ7_N(n)       ((n) << 12) /**< @brief 7th channel in seq. */
+#define ADC_SQR2_SQ8_N(n)       ((n) << 18) /**< @brief 8th channel in seq. */
+#define ADC_SQR2_SQ9_N(n)       ((n) << 24) /**< @brief 9th channel in seq. */
+
+#define ADC_SQR3_SQ10_N(n)      ((n) << 0)  /**< @brief 10th channel in seq.*/
+#define ADC_SQR3_SQ11_N(n)      ((n) << 6)  /**< @brief 11th channel in seq.*/
+#define ADC_SQR3_SQ12_N(n)      ((n) << 12) /**< @brief 12th channel in seq.*/
+#define ADC_SQR3_SQ13_N(n)      ((n) << 18) /**< @brief 13th channel in seq.*/
+#define ADC_SQR3_SQ14_N(n)      ((n) << 24) /**< @brief 14th channel in seq.*/
+
+#define ADC_SQR4_SQ15_N(n)      ((n) << 0)  /**< @brief 15th channel in seq.*/
+#define ADC_SQR4_SQ16_N(n)      ((n) << 6)  /**< @brief 16th channel in seq.*/
+/** @} */
+
+/**
+ * @name    Sampling rate settings helper macros
+ * @{
+ */
+#define ADC_SMPR1_SMP_AN1(n)    ((n) << 3)  /**< @brief AN1 sampling time.  */
+#define ADC_SMPR1_SMP_AN2(n)    ((n) << 6)  /**< @brief AN2 sampling time.  */
+#define ADC_SMPR1_SMP_AN3(n)    ((n) << 9)  /**< @brief AN3 sampling time.  */
+#define ADC_SMPR1_SMP_AN4(n)    ((n) << 12) /**< @brief AN4 sampling time.  */
+#define ADC_SMPR1_SMP_AN5(n)    ((n) << 15) /**< @brief AN5 sampling time.  */
+#define ADC_SMPR1_SMP_AN6(n)    ((n) << 18) /**< @brief AN6 sampling time.  */
+#define ADC_SMPR1_SMP_AN7(n)    ((n) << 21) /**< @brief AN7 sampling time.  */
+#define ADC_SMPR1_SMP_AN8(n)    ((n) << 24) /**< @brief AN8 sampling time.  */
+#define ADC_SMPR1_SMP_AN9(n)    ((n) << 27) /**< @brief AN9 sampling time.  */
+
+#define ADC_SMPR2_SMP_AN10(n)   ((n) << 0)  /**< @brief AN10 sampling time. */
+#define ADC_SMPR2_SMP_AN11(n)   ((n) << 3)  /**< @brief AN11 sampling time. */
+#define ADC_SMPR2_SMP_AN12(n)   ((n) << 6)  /**< @brief AN12 sampling time. */
+#define ADC_SMPR2_SMP_AN13(n)   ((n) << 9)  /**< @brief AN13 sampling time. */
+#define ADC_SMPR2_SMP_AN14(n)   ((n) << 12) /**< @brief AN14 sampling time. */
+#define ADC_SMPR2_SMP_AN15(n)   ((n) << 15) /**< @brief AN15 sampling time. */
+#define ADC_SMPR2_SMP_AN16(n)   ((n) << 18) /**< @brief AN16 sampling time. */
+#define ADC_SMPR2_SMP_AN17(n)   ((n) << 21) /**< @brief AN17 sampling time. */
+#define ADC_SMPR2_SMP_AN18(n)   ((n) << 24) /**< @brief AN18 sampling time. */
+/** @} */
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if STM32_ADC_USE_ADC1 && !defined(__DOXYGEN__)
+extern ADCDriver ADCD1;
+#endif
+
+#if STM32_ADC_USE_ADC3 && !defined(__DOXYGEN__)
+extern ADCDriver ADCD3;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void adc_lld_init(void);
+  void adc_lld_start(ADCDriver *adcp);
+  void adc_lld_stop(ADCDriver *adcp);
+  void adc_lld_start_conversion(ADCDriver *adcp);
+  void adc_lld_stop_conversion(ADCDriver *adcp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_ADC */
+
+#endif /* _ADC_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F3xx/ext_lld_isr.c b/os/hal/ports/STM32/STM32F3xx/ext_lld_isr.c
new file mode 100644
index 000000000..1ac1c2c78
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F3xx/ext_lld_isr.c
@@ -0,0 +1,406 @@
+/*
+    ChibiOS/HAL - Copyright (C) 2006-2014 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F3xx/ext_lld_isr.c
+ * @brief   STM32F3xx EXT subsystem low level driver ISR code.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+#include "ext_lld_isr.h"
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if !defined(STM32_DISABLE_EXTI0_HANDLER)
+/**
+ * @brief   EXTI[0] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector58) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 0);
+  EXTD1.config->channels[0].cb(&EXTD1, 0);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI1_HANDLER)
+/**
+ * @brief   EXTI[1] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector5C) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 1);
+  EXTD1.config->channels[1].cb(&EXTD1, 1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI2_HANDLER)
+/**
+ * @brief   EXTI[2] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector60) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 2);
+  EXTD1.config->channels[2].cb(&EXTD1, 2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI3_HANDLER)
+/**
+ * @brief   EXTI[3] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector64) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 3);
+  EXTD1.config->channels[3].cb(&EXTD1, 3);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI4_HANDLER)
+/**
+ * @brief   EXTI[4] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector68) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 4);
+  EXTD1.config->channels[4].cb(&EXTD1, 4);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI5_9_HANDLER)
+/**
+ * @brief   EXTI[5]...EXTI[9] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector9C) {
+  uint32_t pr;
+
+  OSAL_IRQ_PROLOGUE();
+
+  pr = EXTI->PR & ((1 << 5) | (1 << 6) | (1 << 7) | (1 << 8) | (1 << 9));
+  EXTI->PR = pr;
+  if (pr & (1 << 5))
+    EXTD1.config->channels[5].cb(&EXTD1, 5);
+  if (pr & (1 << 6))
+    EXTD1.config->channels[6].cb(&EXTD1, 6);
+  if (pr & (1 << 7))
+    EXTD1.config->channels[7].cb(&EXTD1, 7);
+  if (pr & (1 << 8))
+    EXTD1.config->channels[8].cb(&EXTD1, 8);
+  if (pr & (1 << 9))
+    EXTD1.config->channels[9].cb(&EXTD1, 9);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI10_15_HANDLER)
+/**
+ * @brief   EXTI[10]...EXTI[15] interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(VectorE0) {
+  uint32_t pr;
+
+  OSAL_IRQ_PROLOGUE();
+
+  pr = EXTI->PR & ((1 << 10) | (1 << 11) | (1 << 12) | (1 << 13) | (1 << 14) |
+                   (1 << 15));
+  EXTI->PR = pr;
+  if (pr & (1 << 10))
+    EXTD1.config->channels[10].cb(&EXTD1, 10);
+  if (pr & (1 << 11))
+    EXTD1.config->channels[11].cb(&EXTD1, 11);
+  if (pr & (1 << 12))
+    EXTD1.config->channels[12].cb(&EXTD1, 12);
+  if (pr & (1 << 13))
+    EXTD1.config->channels[13].cb(&EXTD1, 13);
+  if (pr & (1 << 14))
+    EXTD1.config->channels[14].cb(&EXTD1, 14);
+  if (pr & (1 << 15))
+    EXTD1.config->channels[15].cb(&EXTD1, 15);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI16_HANDLER)
+/**
+ * @brief   EXTI[16] interrupt handler (PVD).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector44) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 16);
+  EXTD1.config->channels[16].cb(&EXTD1, 16);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI17_HANDLER)
+/**
+ * @brief   EXTI[17] interrupt handler (RTC Alarm).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(VectorE4) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 17);
+  EXTD1.config->channels[17].cb(&EXTD1, 17);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI18_HANDLER)
+/**
+ * @brief   EXTI[18] interrupt handler (USB Wakeup).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(VectorE8) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 18);
+  EXTD1.config->channels[18].cb(&EXTD1, 18);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI19_HANDLER)
+/**
+ * @brief   EXTI[19] interrupt handler (Tamper TimeStamp).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector48) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 19);
+  EXTD1.config->channels[19].cb(&EXTD1, 19);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI20_HANDLER)
+/**
+ * @brief   EXTI[20] interrupt handler (RTC Wakeup).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector4C) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR = (1 << 20);
+  EXTD1.config->channels[20].cb(&EXTD1, 20);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI21_22_29_HANDLER)
+/**
+ * @brief   EXTI[21],EXTI[22],EXTI[29] interrupt handler (COMP1, COMP2, COMP3).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector140) {
+  uint32_t pr;
+
+  OSAL_IRQ_PROLOGUE();
+
+  pr = EXTI->PR & ((1 << 21) | (1 << 22) | (1 << 29));
+  EXTI->PR = pr;
+  if (pr & (1 << 21))
+    EXTD1.config->channels[21].cb(&EXTD1, 21);
+  if (pr & (1 << 22))
+    EXTD1.config->channels[22].cb(&EXTD1, 22);
+  if (pr & (1 << 29))
+    EXTD1.config->channels[29].cb(&EXTD1, 29);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI30_32_HANDLER)
+/**
+ * @brief   EXTI[30]...EXTI[32] interrupt handler (COMP4, COMP5, COMP6).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector144) {
+  uint32_t pr;
+
+  OSAL_IRQ_PROLOGUE();
+
+  pr = EXTI->PR & ((1 << 30) | (1 << 31));
+  EXTI->PR = pr;
+  if (pr & (1 << 30))
+    EXTD1.config->channels[30].cb(&EXTD1, 30);
+  if (pr & (1 << 31))
+    EXTD1.config->channels[31].cb(&EXTD1, 31);
+
+  pr = EXTI->PR2 & (1 << 0);
+  EXTI->PR2 = pr;
+  if (pr & (1 << 0))
+    EXTD1.config->channels[32].cb(&EXTD1, 32);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if !defined(STM32_DISABLE_EXTI33_HANDLER)
+/**
+ * @brief   EXTI[33] interrupt handler (COMP7).
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(RTC_WKUP_IRQHandler) {
+
+  OSAL_IRQ_PROLOGUE();
+
+  EXTI->PR2 = (1 << 1);
+  EXTD1.config->channels[33].cb(&EXTD1, 33);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Enables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+void ext_lld_exti_irq_enable(void) {
+
+  nvicEnableVector(EXTI0_IRQn, STM32_EXT_EXTI0_IRQ_PRIORITY);
+  nvicEnableVector(EXTI1_IRQn, STM32_EXT_EXTI1_IRQ_PRIORITY);
+  nvicEnableVector(EXTI2_TSC_IRQn, STM32_EXT_EXTI2_IRQ_PRIORITY);
+  nvicEnableVector(EXTI3_IRQn, STM32_EXT_EXTI3_IRQ_PRIORITY);
+  nvicEnableVector(EXTI4_IRQn, STM32_EXT_EXTI4_IRQ_PRIORITY);
+  nvicEnableVector(EXTI9_5_IRQn, STM32_EXT_EXTI5_9_IRQ_PRIORITY);
+  nvicEnableVector(EXTI15_10_IRQn, STM32_EXT_EXTI10_15_IRQ_PRIORITY);
+  nvicEnableVector(PVD_IRQn, STM32_EXT_EXTI16_IRQ_PRIORITY);
+  nvicEnableVector(RTC_Alarm_IRQn, STM32_EXT_EXTI17_IRQ_PRIORITY);
+  nvicEnableVector(USBWakeUp_IRQn, STM32_EXT_EXTI18_IRQ_PRIORITY);
+  nvicEnableVector(TAMP_STAMP_IRQn, STM32_EXT_EXTI19_IRQ_PRIORITY);
+  nvicEnableVector(RTC_WKUP_IRQn, STM32_EXT_EXTI20_IRQ_PRIORITY);
+  nvicEnableVector(COMP1_2_3_IRQn, STM32_EXT_EXTI21_22_29_IRQ_PRIORITY);
+  nvicEnableVector(COMP4_5_6_IRQn, STM32_EXT_EXTI30_32_IRQ_PRIORITY);
+#if STM32_EXTI_NUM_CHANNELS >= 34
+  nvicEnableVector(COMP7_IRQn, STM32_EXT_EXTI33_IRQ_PRIORITY);
+#endif
+}
+
+/**
+ * @brief   Disables EXTI IRQ sources.
+ *
+ * @notapi
+ */
+void ext_lld_exti_irq_disable(void) {
+
+  nvicDisableVector(EXTI0_IRQn);
+  nvicDisableVector(EXTI1_IRQn);
+  nvicDisableVector(EXTI2_TSC_IRQn);
+  nvicDisableVector(EXTI3_IRQn);
+  nvicDisableVector(EXTI4_IRQn);
+  nvicDisableVector(EXTI9_5_IRQn);
+  nvicDisableVector(EXTI15_10_IRQn);
+  nvicDisableVector(PVD_IRQn);
+  nvicDisableVector(RTC_Alarm_IRQn);
+  nvicDisableVector(USBWakeUp_IRQn);
+  nvicDisableVector(TAMP_STAMP_IRQn);
+  nvicDisableVector(RTC_WKUP_IRQn);
+  nvicDisableVector(COMP1_2_3_IRQn);
+  nvicDisableVector(COMP4_5_6_IRQn);
+#if STM32_EXTI_NUM_CHANNELS >= 34
+  nvicDisableVector(COMP7_IRQn);
+#endif
+}
+
+#endif /* HAL_USE_EXT */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F3xx/ext_lld_isr.h b/os/hal/ports/STM32/STM32F3xx/ext_lld_isr.h
new file mode 100644
index 000000000..b94c89b2c
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F3xx/ext_lld_isr.h
@@ -0,0 +1,177 @@
+/*
+    ChibiOS/HAL - Copyright (C) 2006-2014 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F3xx/ext_lld_isr.h
+ * @brief   STM32F3xx EXT subsystem low level driver ISR header.
+ *
+ * @addtogroup EXT
+ * @{
+ */
+
+#ifndef _EXT_LLD_ISR_H_
+#define _EXT_LLD_ISR_H_
+
+#if HAL_USE_EXT || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   EXTI0 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI0_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI0_IRQ_PRIORITY        6
+#endif
+
+/**
+ * @brief   EXTI1 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI1_IRQ_PRIORITY        6
+#endif
+
+/**
+ * @brief   EXTI2 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI2_IRQ_PRIORITY        6
+#endif
+
+/**
+ * @brief   EXTI3 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI3_IRQ_PRIORITY        6
+#endif
+
+/**
+ * @brief   EXTI4 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI4_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI4_IRQ_PRIORITY        6
+#endif
+
+/**
+ * @brief   EXTI5..9 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI5_9_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI5_9_IRQ_PRIORITY      6
+#endif
+
+/**
+ * @brief   EXTI10..15 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI10_15_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI10_15_IRQ_PRIORITY    6
+#endif
+
+/**
+ * @brief   EXTI16 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI16_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI16_IRQ_PRIORITY       6
+#endif
+
+/**
+ * @brief   EXTI17 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI17_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI17_IRQ_PRIORITY       6
+#endif
+
+/**
+ * @brief   EXTI18 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI18_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI18_IRQ_PRIORITY       6
+#endif
+
+/**
+ * @brief   EXTI19 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI19_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI19_IRQ_PRIORITY       6
+#endif
+
+/**
+ * @brief   EXTI20 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI20_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI20_IRQ_PRIORITY       6
+#endif
+
+/**
+ * @brief   EXTI21,22,29 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI21_22_29_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI21_22_29_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief   EXTI30..32 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI30_32_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI30_32_IRQ_PRIORITY    6
+#endif
+
+/**
+ * @brief   EXTI33 interrupt priority level setting.
+ */
+#if !defined(STM32_EXT_EXTI33_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_EXT_EXTI33_IRQ_PRIORITY       6
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void ext_lld_exti_irq_enable(void);
+  void ext_lld_exti_irq_disable(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_EXT */
+
+#endif /* _EXT_LLD_ISR_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F3xx/hal_lld.c b/os/hal/ports/STM32/STM32F3xx/hal_lld.c
new file mode 100644
index 000000000..cfa538e2e
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F3xx/hal_lld.c
@@ -0,0 +1,202 @@
+/*
+    ChibiOS/HAL - Copyright (C) 2006-2014 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F3xx/hal_lld.c
+ * @brief   STM32F3xx HAL subsystem low level driver source.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Initializes the backup domain.
+ * @note    WARNING! Changing clock source impossible without resetting
+ *          of the whole BKP domain.
+ */
+static void hal_lld_backup_domain_init(void) {
+
+  /* Backup domain access enabled and left open.*/
+  PWR->CR |= PWR_CR_DBP;
+
+  /* Reset BKP domain if different clock source selected.*/
+  if ((RCC->BDCR & STM32_RTCSEL_MASK) != STM32_RTCSEL){
+    /* Backup domain reset.*/
+    RCC->BDCR = RCC_BDCR_BDRST;
+    RCC->BDCR = 0;
+  }
+
+  /* If enabled then the LSE is started.*/
+#if STM32_LSE_ENABLED
+#if defined(STM32_LSE_BYPASS)
+  /* LSE Bypass.*/
+  RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON | RCC_BDCR_LSEBYP;
+#else
+  /* No LSE Bypass.*/
+  RCC->BDCR |= STM32_LSEDRV | RCC_BDCR_LSEON;
+#endif
+  while ((RCC->BDCR & RCC_BDCR_LSERDY) == 0)
+    ;                                     /* Waits until LSE is stable.   */
+#endif
+
+#if STM32_RTCSEL != STM32_RTCSEL_NOCLOCK
+  /* If the backup domain hasn't been initialized yet then proceed with
+     initialization.*/
+  if ((RCC->BDCR & RCC_BDCR_RTCEN) == 0) {
+    /* Selects clock source.*/
+    RCC->BDCR |= STM32_RTCSEL;
+
+    /* RTC clock enabled.*/
+    RCC->BDCR |= RCC_BDCR_RTCEN;
+  }
+#endif /* STM32_RTCSEL != STM32_RTCSEL_NOCLOCK */
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level HAL driver initialization.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+
+  /* Reset of all peripherals.*/
+  rccResetAHB(0xFFFFFFFF);
+  rccResetAPB1(0xFFFFFFFF);
+  rccResetAPB2(0xFFFFFFFF);
+
+  /* PWR clock enabled.*/
+  rccEnablePWRInterface(FALSE);
+
+  /* Initializes the backup domain.*/
+  hal_lld_backup_domain_init();
+
+#if defined(STM32_DMA_REQUIRED)
+  dmaInit();
+#endif
+
+  /* Programmable voltage detector enable.*/
+#if STM32_PVD_ENABLE
+  PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
+#endif /* STM32_PVD_ENABLE */
+
+  /* SYSCFG clock enabled here because it is a multi-functional unit shared
+     among multiple drivers.*/
+  rccEnableAPB2(RCC_APB2ENR_SYSCFGEN, TRUE);
+
+  /* USB IRQ relocated to not conflict with CAN.*/
+  SYSCFG->CFGR1 |= SYSCFG_CFGR1_USB_IT_RMP;
+}
+
+/**
+ * @brief   STM32 clocks and PLL initialization.
+ * @note    All the involved constants come from the file @p board.h.
+ * @note    This function should be invoked just after the system reset.
+ *
+ * @special
+ */
+void stm32_clock_init(void) {
+
+#if !STM32_NO_INIT
+  /* HSI setup, it enforces the reset situation in order to handle possible
+     problems with JTAG probes and re-initializations.*/
+  RCC->CR |= RCC_CR_HSION;                  /* Make sure HSI is ON.         */
+  while (!(RCC->CR & RCC_CR_HSIRDY))
+    ;                                       /* Wait until HSI is stable.    */
+  RCC->CR &= RCC_CR_HSITRIM | RCC_CR_HSION; /* CR Reset value.              */
+  RCC->CFGR = 0;                            /* CFGR reset value.            */
+  while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI)
+    ;                                       /* Waits until HSI is selected. */
+
+#if STM32_HSE_ENABLED
+  /* HSE activation.*/
+#if defined(STM32_HSE_BYPASS)
+  /* HSE Bypass.*/
+  RCC->CR |= RCC_CR_HSEON | RCC_CR_HSEBYP;
+#else
+  /* No HSE Bypass.*/
+  RCC->CR |= RCC_CR_HSEON;
+#endif
+  while (!(RCC->CR & RCC_CR_HSERDY))
+    ;                                       /* Waits until HSE is stable.   */
+#endif
+
+#if STM32_LSI_ENABLED
+  /* LSI activation.*/
+  RCC->CSR |= RCC_CSR_LSION;
+  while ((RCC->CSR & RCC_CSR_LSIRDY) == 0)
+    ;                                       /* Waits until LSI is stable.   */
+#endif
+
+  /* Clock settings.*/
+  RCC->CFGR  = STM32_MCOSEL    | STM32_USBPRE    | STM32_PLLMUL   |
+               STM32_PLLSRC    | STM32_PPRE1     | STM32_PPRE2    |
+               STM32_HPRE;
+  RCC->CFGR2 = STM32_ADC34PRES | STM32_ADC12PRES | STM32_PREDIV;
+  RCC->CFGR3 = STM32_UART5SW   | STM32_UART4SW   | STM32_USART3SW |
+               STM32_USART2SW  | STM32_I2C2SW    | STM32_I2C1SW   |
+               STM32_USART1SW;
+
+#if STM32_ACTIVATE_PLL
+  /* PLL activation.*/
+  RCC->CR   |= RCC_CR_PLLON;
+  while (!(RCC->CR & RCC_CR_PLLRDY))
+    ;                                       /* Waits until PLL is stable.   */
+#endif
+
+  /* Flash setup and final clock selection.   */
+  FLASH->ACR = STM32_FLASHBITS;
+
+  /* Switching to the configured clock source if it is different from HSI.*/
+#if (STM32_SW != STM32_SW_HSI)
+  /* Switches clock source.*/
+  RCC->CFGR |= STM32_SW;
+  while ((RCC->CFGR & RCC_CFGR_SWS) != (STM32_SW << 2))
+    ;                                       /* Waits selection complete.    */
+#endif
+
+  /* After PLL activation because the special requirements for TIM1 and
+     TIM8 bits.*/
+  RCC->CFGR3 |= STM32_TIM8SW | STM32_TIM1SW;
+#endif /* !STM32_NO_INIT */
+}
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F3xx/hal_lld.h b/os/hal/ports/STM32/STM32F3xx/hal_lld.h
new file mode 100644
index 000000000..21f6d4a84
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F3xx/hal_lld.h
@@ -0,0 +1,1150 @@
+/*
+    ChibiOS/HAL - Copyright (C) 2006-2014 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F3xx/hal_lld.h
+ * @brief   STM32F3xx HAL subsystem low level driver header.
+ * @pre     This module requires the following macros to be defined in the
+ *          @p board.h file:
+ *          - STM32_LSECLK.
+ *          - STM32_LSEDRV.
+ *          - STM32_LSE_BYPASS (optionally).
+ *          - STM32_HSECLK.
+ *          - STM32_HSE_BYPASS (optionally).
+ *          .
+ *          One of the following macros must also be defined:
+ *          - STM32F301x8 for Analog & DSP devices.
+ *          - STM32F302x8 for Analog & DSP devices.
+ *          - STM32F302xC for Analog & DSP devices.
+ *          - STM32F303x8 for Analog & DSP devices.
+ *          - STM32F303xC for Analog & DSP devices.
+ *          - STM32F318xx for Analog & DSP devices.
+ *          - STM32F328xx for Analog & DSP devices.
+ *          - STM32F334x8 for Analog & DSP devices.
+ *          - STM32F358xx for Analog & DSP devices.
+ *          .
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef _HAL_LLD_H_
+#define _HAL_LLD_H_
+
+#include "stm32_registry.h"
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Platform identification macros
+ * @{
+ */
+#if defined(STM32F301x8) || defined(__DOXYGEN__)
+#define PLATFORM_NAME           "STM32F301x8 Analog & DSP"
+
+#elif defined(STM32F302x8)
+#define PLATFORM_NAME           "STM32F302x8 Analog & DSP"
+
+#elif defined(STM32F302xC)
+#define PLATFORM_NAME           "STM32F302xC Analog & DSP"
+
+#elif defined(STM32F303x8)
+#define PLATFORM_NAME           "STM32F303x8 Analog & DSP"
+
+#elif defined(STM32F303xC)
+#define PLATFORM_NAME           "STM32F303xC Analog & DSP"
+
+#elif defined(STM32F318xx)
+#define PLATFORM_NAME           "STM32F318xx Analog & DSP"
+
+#elif defined(STM32F328xx)
+#define PLATFORM_NAME           "STM32F328xx Analog & DSP"
+
+#elif defined(STM32F334x8)
+#define PLATFORM_NAME           "STM32F334x8 Analog & DSP"
+
+#elif defined(STM32F358xx)
+#define PLATFORM_NAME           "STM32F358xx Analog & DSP"
+
+#else
+#error "STM32F3xx device not specified"
+#endif
+/** @} */
+
+/**
+ * @name    Absolute Maximum Ratings
+ * @{
+ */
+/**
+ * @brief   Maximum system clock frequency.
+ */
+#define STM32_SYSCLK_MAX        72000000
+
+/**
+ * @brief   Maximum HSE clock frequency.
+ */
+#define STM32_HSECLK_MAX        32000000
+
+/**
+ * @brief   Minimum HSE clock frequency.
+ */
+#define STM32_HSECLK_MIN        1000000
+
+/**
+ * @brief   Maximum LSE clock frequency.
+ */
+#define STM32_LSECLK_MAX        1000000
+
+/**
+ * @brief   Minimum LSE clock frequency.
+ */
+#define STM32_LSECLK_MIN        32768
+
+/**
+ * @brief   Maximum PLLs input clock frequency.
+ */
+#define STM32_PLLIN_MAX         24000000
+
+/**
+ * @brief   Minimum PLLs input clock frequency.
+ */
+#define STM32_PLLIN_MIN         1000000
+
+/**
+ * @brief   Maximum PLL output clock frequency.
+ */
+#define STM32_PLLOUT_MAX        72000000
+
+/**
+ * @brief   Maximum PLL output clock frequency.
+ */
+#define STM32_PLLOUT_MIN        16000000
+
+/**
+ * @brief   Maximum APB1 clock frequency.
+ */
+#define STM32_PCLK1_MAX         36000000
+
+/**
+ * @brief   Maximum APB2 clock frequency.
+ */
+#define STM32_PCLK2_MAX         72000000
+
+/**
+ * @brief   Maximum ADC clock frequency.
+ */
+#define STM32_ADCCLK_MAX        72000000
+/** @} */
+
+/**
+ * @name    Internal clock sources
+ * @{
+ */
+#define STM32_HSICLK            8000000     /**< High speed internal clock. */
+#define STM32_LSICLK            40000       /**< Low speed internal clock.  */
+/** @} */
+
+/**
+ * @name    PWR_CR register bits definitions
+ * @{
+ */
+#define STM32_PLS_MASK          (7 << 5)    /**< PLS bits mask.             */
+#define STM32_PLS_LEV0          (0 << 5)    /**< PVD level 0.               */
+#define STM32_PLS_LEV1          (1 << 5)    /**< PVD level 1.               */
+#define STM32_PLS_LEV2          (2 << 5)    /**< PVD level 2.               */
+#define STM32_PLS_LEV3          (3 << 5)    /**< PVD level 3.               */
+#define STM32_PLS_LEV4          (4 << 5)    /**< PVD level 4.               */
+#define STM32_PLS_LEV5          (5 << 5)    /**< PVD level 5.               */
+#define STM32_PLS_LEV6          (6 << 5)    /**< PVD level 6.               */
+#define STM32_PLS_LEV7          (7 << 5)    /**< PVD level 7.               */
+/** @} */
+
+/**
+ * @name    RCC_CFGR register bits definitions
+ * @{
+ */
+#define STM32_SW_HSI            (0 << 0)    /**< SYSCLK source is HSI.      */
+#define STM32_SW_HSE            (1 << 0)    /**< SYSCLK source is HSE.      */
+#define STM32_SW_PLL            (2 << 0)    /**< SYSCLK source is PLL.      */
+
+#define STM32_HPRE_DIV1         (0 << 4)    /**< SYSCLK divided by 1.       */
+#define STM32_HPRE_DIV2         (8 << 4)    /**< SYSCLK divided by 2.       */
+#define STM32_HPRE_DIV4         (9 << 4)    /**< SYSCLK divided by 4.       */
+#define STM32_HPRE_DIV8         (10 << 4)   /**< SYSCLK divided by 8.       */
+#define STM32_HPRE_DIV16        (11 << 4)   /**< SYSCLK divided by 16.      */
+#define STM32_HPRE_DIV64        (12 << 4)   /**< SYSCLK divided by 64.      */
+#define STM32_HPRE_DIV128       (13 << 4)   /**< SYSCLK divided by 128.     */
+#define STM32_HPRE_DIV256       (14 << 4)   /**< SYSCLK divided by 256.     */
+#define STM32_HPRE_DIV512       (15 << 4)   /**< SYSCLK divided by 512.     */
+
+#define STM32_PPRE1_DIV1        (0 << 8)    /**< HCLK divided by 1.         */
+#define STM32_PPRE1_DIV2        (4 << 8)    /**< HCLK divided by 2.         */
+#define STM32_PPRE1_DIV4        (5 << 8)    /**< HCLK divided by 4.         */
+#define STM32_PPRE1_DIV8        (6 << 8)    /**< HCLK divided by 8.         */
+#define STM32_PPRE1_DIV16       (7 << 8)    /**< HCLK divided by 16.        */
+
+#define STM32_PPRE2_DIV1        (0 << 11)   /**< HCLK divided by 1.         */
+#define STM32_PPRE2_DIV2        (4 << 11)   /**< HCLK divided by 2.         */
+#define STM32_PPRE2_DIV4        (5 << 11)   /**< HCLK divided by 4.         */
+#define STM32_PPRE2_DIV8        (6 << 11)   /**< HCLK divided by 8.         */
+#define STM32_PPRE2_DIV16       (7 << 11)   /**< HCLK divided by 16.        */
+
+#define STM32_PLLSRC_HSI        (0 << 16)   /**< PLL clock source is HSI/2. */
+#define STM32_PLLSRC_HSE        (1 << 16)   /**< PLL clock source is
+                                                 HSE/PREDIV.                */
+
+#define STM32_USBPRE_DIV1P5     (0 << 22)   /**< USB clock is PLLCLK/1.5.   */
+#define STM32_USBPRE_DIV1       (1 << 22)   /**< USB clock is PLLCLK/1.     */
+
+#define STM32_MCOSEL_NOCLOCK    (0 << 24)   /**< No clock on MCO pin.       */
+#define STM32_MCOSEL_LSI        (2 << 24)   /**< LSI clock on MCO pin.      */
+#define STM32_MCOSEL_LSE        (3 << 24)   /**< LSE clock on MCO pin.      */
+#define STM32_MCOSEL_SYSCLK     (4 << 24)   /**< SYSCLK on MCO pin.         */
+#define STM32_MCOSEL_HSI        (5 << 24)   /**< HSI clock on MCO pin.      */
+#define STM32_MCOSEL_HSE        (6 << 24)   /**< HSE clock on MCO pin.      */
+#define STM32_MCOSEL_PLLDIV2    (7 << 24)   /**< PLL/2 clock on MCO pin.    */
+/** @} */
+
+/**
+ * @name    RCC_BDCR register bits definitions
+ * @{
+ */
+#define STM32_RTCSEL_MASK       (3 << 8)    /**< RTC clock source mask.     */
+#define STM32_RTCSEL_NOCLOCK    (0 << 8)    /**< No clock.                  */
+#define STM32_RTCSEL_LSE        (1 << 8)    /**< LSE used as RTC clock.     */
+#define STM32_RTCSEL_LSI        (2 << 8)    /**< LSI used as RTC clock.     */
+#define STM32_RTCSEL_HSEDIV     (3 << 8)    /**< HSE divided by 32 used as
+                                                 RTC clock.                 */
+/** @} */
+
+/**
+ * @name    RCC_CFGR2 register bits definitions
+ * @{
+ */
+#define STM32_PREDIV_MASK       (15 << 0)   /**< PREDIV divisor mask.       */
+#define STM32_ADC12PRES_MASK    (31 << 4)   /**< ADC12 clock source mask.   */
+#define STM32_ADC12PRES_NOCLOCK (0 << 4)    /**< ADC12 clock is disabled.   */
+#define STM32_ADC12PRES_DIV1    (16 << 4)   /**< ADC12 clock is PLL/1.      */
+#define STM32_ADC12PRES_DIV2    (17 << 4)   /**< ADC12 clock is PLL/2.      */
+#define STM32_ADC12PRES_DIV4    (18 << 4)   /**< ADC12 clock is PLL/4.      */
+#define STM32_ADC12PRES_DIV6    (19 << 4)   /**< ADC12 clock is PLL/6.      */
+#define STM32_ADC12PRES_DIV8    (20 << 4)   /**< ADC12 clock is PLL/8.      */
+#define STM32_ADC12PRES_DIV10   (21 << 4)   /**< ADC12 clock is PLL/10.     */
+#define STM32_ADC12PRES_DIV12   (22 << 4)   /**< ADC12 clock is PLL/12.     */
+#define STM32_ADC12PRES_DIV16   (23 << 4)   /**< ADC12 clock is PLL/16.     */
+#define STM32_ADC12PRES_DIV32   (24 << 4)   /**< ADC12 clock is PLL/32.     */
+#define STM32_ADC12PRES_DIV64   (25 << 4)   /**< ADC12 clock is PLL/64.     */
+#define STM32_ADC12PRES_DIV128  (26 << 4)   /**< ADC12 clock is PLL/128.    */
+#define STM32_ADC12PRES_DIV256  (27 << 4)   /**< ADC12 clock is PLL/256.    */
+#define STM32_ADC34PRES_MASK    (31 << 9)   /**< ADC34 clock source mask.   */
+#define STM32_ADC34PRES_NOCLOCK (0 << 9)    /**< ADC34 clock is disabled.   */
+#define STM32_ADC34PRES_DIV1    (16 << 9)   /**< ADC34 clock is PLL/1.      */
+#define STM32_ADC34PRES_DIV2    (17 << 9)   /**< ADC34 clock is PLL/2.      */
+#define STM32_ADC34PRES_DIV4    (18 << 9)   /**< ADC34 clock is PLL/4.      */
+#define STM32_ADC34PRES_DIV6    (19 << 9)   /**< ADC34 clock is PLL/6.      */
+#define STM32_ADC34PRES_DIV8    (20 << 9)   /**< ADC34 clock is PLL/8.      */
+#define STM32_ADC34PRES_DIV10   (21 << 9)   /**< ADC34 clock is PLL/10.     */
+#define STM32_ADC34PRES_DIV12   (22 << 9)   /**< ADC34 clock is PLL/12.     */
+#define STM32_ADC34PRES_DIV16   (23 << 9)   /**< ADC34 clock is PLL/16.     */
+#define STM32_ADC34PRES_DIV32   (24 << 9)   /**< ADC34 clock is PLL/32.     */
+#define STM32_ADC34PRES_DIV64   (25 << 9)   /**< ADC34 clock is PLL/64.     */
+#define STM32_ADC34PRES_DIV128  (26 << 9)   /**< ADC34 clock is PLL/128.    */
+#define STM32_ADC34PRES_DIV256  (27 << 9)   /**< ADC34 clock is PLL/256.    */
+/** @} */
+
+/**
+ * @name    RCC_CFGR3 register bits definitions
+ * @{
+ */
+#define STM32_USART1SW_MASK     (3 << 0)    /**< USART1 clock source mask. */
+#define STM32_USART1SW_PCLK     (0 << 0)    /**< USART1 clock is PCLK.     */
+#define STM32_USART1SW_SYSCLK   (1 << 0)    /**< USART1 clock is SYSCLK.   */
+#define STM32_USART1SW_LSE      (2 << 0)    /**< USART1 clock is LSE.      */
+#define STM32_USART1SW_HSI      (3 << 0)    /**< USART1 clock is HSI.      */
+#define STM32_I2C1SW_MASK       (1 << 4)    /**< I2C1 clock source mask.   */
+#define STM32_I2C1SW_HSI        (0 << 4)    /**< I2C1 clock is HSI.        */
+#define STM32_I2C1SW_SYSCLK     (1 << 4)    /**< I2C1 clock is SYSCLK.     */
+#define STM32_I2C2SW_MASK       (1 << 5)    /**< I2C2 clock source mask.   */
+#define STM32_I2C2SW_HSI        (0 << 5)    /**< I2C2 clock is HSI.        */
+#define STM32_I2C2SW_SYSCLK     (1 << 5)    /**< I2C2 clock is SYSCLK.     */
+#define STM32_TIM1SW_MASK       (1 << 8)    /**< TIM1 clock source mask.   */
+#define STM32_TIM1SW_PCLK2      (0 << 8)    /**< TIM1 clock is PCLK2.      */
+#define STM32_TIM1SW_PLLX2      (1 << 8)    /**< TIM1 clock is PLL*2.      */
+#define STM32_TIM8SW_MASK       (1 << 9)    /**< TIM8 clock source mask.   */
+#define STM32_TIM8SW_PCLK2      (0 << 9)    /**< TIM8 clock is PCLK2.      */
+#define STM32_TIM8SW_PLLX2      (1 << 9)    /**< TIM8 clock is PLL*2.      */
+#define STM32_USART2SW_MASK     (3 << 16)   /**< USART2 clock source mask. */
+#define STM32_USART2SW_PCLK     (0 << 16)   /**< USART2 clock is PCLK.     */
+#define STM32_USART2SW_SYSCLK   (1 << 16)   /**< USART2 clock is SYSCLK.   */
+#define STM32_USART2SW_LSE      (2 << 16)   /**< USART2 clock is LSE.      */
+#define STM32_USART2SW_HSI      (3 << 16)   /**< USART2 clock is HSI.      */
+#define STM32_USART3SW_MASK     (3 << 18)   /**< USART3 clock source mask. */
+#define STM32_USART3SW_PCLK     (0 << 18)   /**< USART3 clock is PCLK.     */
+#define STM32_USART3SW_SYSCLK   (1 << 18)   /**< USART3 clock is SYSCLK.   */
+#define STM32_USART3SW_LSE      (2 << 18)   /**< USART3 clock is LSE.      */
+#define STM32_USART3SW_HSI      (3 << 18)   /**< USART3 clock is HSI.      */
+#define STM32_UART4SW_MASK      (3 << 20)   /**< USART4 clock source mask. */
+#define STM32_UART4SW_PCLK      (0 << 20)   /**< USART4 clock is PCLK.     */
+#define STM32_UART4SW_SYSCLK    (1 << 20)   /**< USART4 clock is SYSCLK.   */
+#define STM32_UART4SW_LSE       (2 << 20)   /**< USART4 clock is LSE.      */
+#define STM32_UART4SW_HSI       (3 << 20)   /**< USART4 clock is HSI.      */
+#define STM32_UART5SW_MASK      (3 << 22)   /**< USART5 clock source mask. */
+#define STM32_UART5SW_PCLK      (0 << 22)   /**< USART5 clock is PCLK.     */
+#define STM32_UART5SW_SYSCLK    (1 << 22)   /**< USART5 clock is SYSCLK.   */
+#define STM32_UART5SW_LSE       (2 << 22)   /**< USART5 clock is LSE.      */
+#define STM32_UART5SW_HSI       (3 << 22)   /**< USART5 clock is HSI.      */
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   Disables the PWR/RCC initialization in the HAL.
+ */
+#if !defined(STM32_NO_INIT) || defined(__DOXYGEN__)
+#define STM32_NO_INIT                       FALSE
+#endif
+
+/**
+ * @brief   Enables or disables the programmable voltage detector.
+ */
+#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
+#define STM32_PVD_ENABLE                    FALSE
+#endif
+
+/**
+ * @brief   Sets voltage level for programmable voltage detector.
+ */
+#if !defined(STM32_PLS) || defined(__DOXYGEN__)
+#define STM32_PLS                           STM32_PLS_LEV0
+#endif
+
+/**
+ * @brief   Enables or disables the HSI clock source.
+ */
+#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSI_ENABLED                   TRUE
+#endif
+
+/**
+ * @brief   Enables or disables the LSI clock source.
+ */
+#if !defined(STM32_LSI_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSI_ENABLED                   TRUE
+#endif
+
+/**
+ * @brief   Enables or disables the HSE clock source.
+ */
+#if !defined(STM32_HSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_HSE_ENABLED                   TRUE
+#endif
+
+/**
+ * @brief   Enables or disables the LSE clock source.
+ */
+#if !defined(STM32_LSE_ENABLED) || defined(__DOXYGEN__)
+#define STM32_LSE_ENABLED                   FALSE
+#endif
+
+/**
+ * @brief   Main clock source selection.
+ * @note    If the selected clock source is not the PLL then the PLL is not
+ *          initialized and started.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_SW) || defined(__DOXYGEN__)
+#define STM32_SW                            STM32_SW_PLL
+#endif
+
+/**
+ * @brief   Clock source for the PLL.
+ * @note    This setting has only effect if the PLL is selected as the
+ *          system clock source.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_PLLSRC) || defined(__DOXYGEN__)
+#define STM32_PLLSRC                        STM32_PLLSRC_HSE
+#endif
+
+/**
+ * @brief   Crystal PLL pre-divider.
+ * @note    This setting has only effect if the PLL is selected as the
+ *          system clock source.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_PREDIV_VALUE) || defined(__DOXYGEN__)
+#define STM32_PREDIV_VALUE                  1
+#endif
+
+/**
+ * @brief   PLL multiplier value.
+ * @note    The allowed range is 2...16.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_PLLMUL_VALUE) || defined(__DOXYGEN__)
+#define STM32_PLLMUL_VALUE                  9
+#endif
+
+/**
+ * @brief   AHB prescaler value.
+ * @note    The default value is calculated for a 72MHz system clock from
+ *          a 8MHz crystal using the PLL.
+ */
+#if !defined(STM32_HPRE) || defined(__DOXYGEN__)
+#define STM32_HPRE                          STM32_HPRE_DIV1
+#endif
+
+/**
+ * @brief   APB1 prescaler value.
+ */
+#if !defined(STM32_PPRE1) || defined(__DOXYGEN__)
+#define STM32_PPRE1                         STM32_PPRE1_DIV2
+#endif
+
+/**
+ * @brief   APB2 prescaler value.
+ */
+#if !defined(STM32_PPRE2) || defined(__DOXYGEN__)
+#define STM32_PPRE2                         STM32_PPRE2_DIV2
+#endif
+
+/**
+ * @brief   MCO pin setting.
+ */
+#if !defined(STM32_MCOSEL) || defined(__DOXYGEN__)
+#define STM32_MCOSEL                        STM32_MCOSEL_NOCLOCK
+#endif
+
+/**
+ * @brief   ADC12 prescaler value.
+ */
+#if !defined(STM32_ADC12PRES) || defined(__DOXYGEN__)
+#define STM32_ADC12PRES                     STM32_ADC12PRES_DIV1
+#endif
+
+/**
+ * @brief   ADC34 prescaler value.
+ */
+#if !defined(STM32_ADC34PRES) || defined(__DOXYGEN__)
+#define STM32_ADC34PRES                     STM32_ADC34PRES_DIV1
+#endif
+
+/**
+ * @brief   USART1 clock source.
+ */
+#if !defined(STM32_USART1SW) || defined(__DOXYGEN__)
+#define STM32_USART1SW                      STM32_USART1SW_PCLK
+#endif
+
+/**
+ * @brief   USART2 clock source.
+ */
+#if !defined(STM32_USART2SW) || defined(__DOXYGEN__)
+#define STM32_USART2SW                      STM32_USART2SW_PCLK
+#endif
+
+/**
+ * @brief   USART3 clock source.
+ */
+#if !defined(STM32_USART3SW) || defined(__DOXYGEN__)
+#define STM32_USART3SW                      STM32_USART3SW_PCLK
+#endif
+
+/**
+ * @brief   UART4 clock source.
+ */
+#if !defined(STM32_UART4SW) || defined(__DOXYGEN__)
+#define STM32_UART4SW                       STM32_UART4SW_PCLK
+#endif
+
+/**
+ * @brief   UART5 clock source.
+ */
+#if !defined(STM32_UART5SW) || defined(__DOXYGEN__)
+#define STM32_UART5SW                       STM32_UART5SW_PCLK
+#endif
+
+/**
+ * @brief   I2C1 clock source.
+ */
+#if !defined(STM32_I2C1SW) || defined(__DOXYGEN__)
+#define STM32_I2C1SW                        STM32_I2C1SW_SYSCLK
+#endif
+
+/**
+ * @brief   I2C2 clock source.
+ */
+#if !defined(STM32_I2C2SW) || defined(__DOXYGEN__)
+#define STM32_I2C2SW                        STM32_I2C2SW_SYSCLK
+#endif
+
+/**
+ * @brief   TIM1 clock source.
+ */
+#if !defined(STM32_TIM1SW) || defined(__DOXYGEN__)
+#define STM32_TIM1SW                        STM32_TIM1SW_PCLK2
+#endif
+
+/**
+ * @brief   TIM8 clock source.
+ */
+#if !defined(STM32_TIM8SW) || defined(__DOXYGEN__)
+#define STM32_TIM8SW                        STM32_TIM8SW_PCLK2
+#endif
+
+/**
+ * @brief   RTC clock source.
+ */
+#if !defined(STM32_RTCSEL) || defined(__DOXYGEN__)
+#define STM32_RTCSEL                        STM32_RTCSEL_LSI
+#endif
+
+/**
+ * @brief   USB clock setting.
+ */
+#if !defined(STM32_USB_CLOCK_REQUIRED) || defined(__DOXYGEN__)
+#define STM32_USB_CLOCK_REQUIRED            TRUE
+#endif
+
+/**
+ * @brief   USB prescaler initialization.
+ */
+#if !defined(STM32_USBPRE) || defined(__DOXYGEN__)
+#define STM32_USBPRE                        STM32_USBPRE_DIV1P5
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*
+ * Configuration-related checks.
+ */
+#if !defined(STM32F3xx_MCUCONF)
+#error "Using a wrong mcuconf.h file, STM32F3xx_MCUCONF not defined"
+#endif
+
+/*
+ * HSI related checks.
+ */
+#if STM32_HSI_ENABLED
+#else /* !STM32_HSI_ENABLED */
+
+#if STM32_SW == STM32_SW_HSI
+#error "HSI not enabled, required by STM32_SW"
+#endif
+
+#if STM32_USART1SW == STM32_USART1SW_HSI
+#error "HSI not enabled, required by STM32_USART1SW"
+#endif
+
+#if STM32_USART2SW == STM32_USART2SW_HSI
+#error "HSI not enabled, required by STM32_USART2SW"
+#endif
+
+#if STM32_USART3SW == STM32_USART3SW_HSI
+#error "HSI not enabled, required by STM32_USART3SW"
+#endif
+
+#if STM32_UART4SW == STM32_UART4SW_HSI
+#error "HSI not enabled, required by STM32_UART4SW"
+#endif
+
+#if STM32_UART5SW == STM32_UART5SW_HSI
+#error "HSI not enabled, required by STM32_UART5SW"
+#endif
+
+#if STM32_I2C1SW == STM32_I2C1SW_HSI
+#error "HSI not enabled, required by STM32_I2C1SW"
+#endif
+
+#if STM32_I2C2SW == STM32_I2C2SW_HSI
+#error "HSI not enabled, required by STM32_I2C2SW"
+#endif
+
+#if STM32_TIM1SW == STM32_TIM1SW_HSI
+#error "HSI not enabled, required by STM32_TIM1SW"
+#endif
+
+#if STM32_TIM8SW == STM32_TIM8SW_HSI
+#error "HSI not enabled, required by STM32_TIM8SW"
+#endif
+
+#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSI)
+#error "HSI not enabled, required by STM32_SW and STM32_PLLSRC"
+#endif
+
+#if (STM32_MCOSEL == STM32_MCOSEL_HSI) ||                                   \
+    ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) &&                              \
+     (STM32_PLLSRC == STM32_PLLSRC_HSI))
+#error "HSI not enabled, required by STM32_MCOSEL"
+#endif
+
+#endif /* !STM32_HSI_ENABLED */
+
+/*
+ * HSE related checks.
+ */
+#if STM32_HSE_ENABLED
+
+#if STM32_HSECLK == 0
+#error "HSE frequency not defined"
+#elif (STM32_HSECLK < STM32_HSECLK_MIN) || (STM32_HSECLK > STM32_HSECLK_MAX)
+#error "STM32_HSECLK outside acceptable range (STM32_HSECLK_MIN...STM32_HSECLK_MAX)"
+#endif
+
+#else /* !STM32_HSE_ENABLED */
+
+#if STM32_SW == STM32_SW_HSE
+#error "HSE not enabled, required by STM32_SW"
+#endif
+
+#if (STM32_SW == STM32_SW_PLL) && (STM32_PLLSRC == STM32_PLLSRC_HSE)
+#error "HSE not enabled, required by STM32_SW and STM32_PLLSRC"
+#endif
+
+#if (STM32_MCOSEL == STM32_MCOSEL_HSE) ||                                   \
+    ((STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) &&                              \
+     (STM32_PLLSRC == STM32_PLLSRC_HSE))
+#error "HSE not enabled, required by STM32_MCOSEL"
+#endif
+
+#if STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+#error "HSE not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_HSE_ENABLED */
+
+/*
+ * LSI related checks.
+ */
+#if STM32_LSI_ENABLED
+#else /* !STM32_LSI_ENABLED */
+
+#if STM32_RTCSEL == STM32_RTCSEL_LSI
+#error "LSI not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_LSI_ENABLED */
+
+/*
+ * LSE related checks.
+ */
+#if STM32_LSE_ENABLED
+
+#if !defined(STM32_LSECLK) || (STM32_LSECLK == 0)
+#error "STM32_LSECLK not defined"
+#endif
+
+#if (STM32_LSECLK < STM32_LSECLK_MIN) || (STM32_LSECLK > STM32_LSECLK_MAX)
+#error "STM32_LSECLK outside acceptable range (STM32_LSECLK_MIN...STM32_LSECLK_MAX)"
+#endif
+
+#if !defined(STM32_LSEDRV)
+#error "STM32_LSEDRV not defined"
+#endif
+
+#if (STM32_LSEDRV >> 3) > 3
+#error "STM32_LSEDRV outside acceptable range ((0<<3)...(3<<3))"
+#endif
+
+#if STM32_USART1SW == STM32_USART1SW_LSE
+#error "LSE not enabled, required by STM32_USART1SW"
+#endif
+
+#if STM32_USART2SW == STM32_USART2SW_LSE
+#error "LSE not enabled, required by STM32_USART2SW"
+#endif
+
+#if STM32_USART3SW == STM32_USART3SW_LSE
+#error "LSE not enabled, required by STM32_USART3SW"
+#endif
+
+#if STM32_UART4SW == STM32_UART4SW_LSE
+#error "LSE not enabled, required by STM32_UART4SW"
+#endif
+
+#if STM32_UART5SW == STM32_UART5SW_LSE
+#error "LSE not enabled, required by STM32_UART5SW"
+#endif
+
+#else /* !STM32_LSE_ENABLED */
+
+#if STM32_RTCSEL == STM32_RTCSEL_LSE
+#error "LSE not enabled, required by STM32_RTCSEL"
+#endif
+
+#endif /* !STM32_LSE_ENABLED */
+
+/* PLL activation conditions.*/
+#if (STM32_SW == STM32_SW_PLL) ||                                           \
+    (STM32_MCOSEL == STM32_MCOSEL_PLLDIV2) ||                               \
+    (STM32_TIM1SW == STM32_TIM1SW_PLLX2) ||                                 \
+    (STM32_TIM8SW == STM32_TIM8SW_PLLX2) ||                                 \
+    (STM32_ADC12PRES != STM32_ADC12PRES_NOCLOCK) ||                         \
+    (STM32_ADC34PRES != STM32_ADC34PRES_NOCLOCK) ||                         \
+    STM32_USB_CLOCK_REQUIRED ||                                             \
+    defined(__DOXYGEN__)
+/**
+ * @brief   PLL activation flag.
+ */
+#define STM32_ACTIVATE_PLL          TRUE
+#else
+#define STM32_ACTIVATE_PLL          FALSE
+#endif
+
+/* HSE prescaler setting check.*/
+#if ((STM32_PREDIV_VALUE >= 1) || (STM32_PREDIV_VALUE <= 16))
+#define STM32_PREDIV                ((STM32_PREDIV_VALUE - 1) << 0)
+#else
+#error "invalid STM32_PREDIV value specified"
+#endif
+
+/**
+ * @brief   PLLMUL field.
+ */
+#if ((STM32_PLLMUL_VALUE >= 2) && (STM32_PLLMUL_VALUE <= 16)) ||            \
+    defined(__DOXYGEN__)
+#define STM32_PLLMUL                ((STM32_PLLMUL_VALUE - 2) << 18)
+#else
+#error "invalid STM32_PLLMUL_VALUE value specified"
+#endif
+
+/**
+ * @brief   PLL input clock frequency.
+ */
+#if (STM32_PLLSRC == STM32_PLLSRC_HSE) || defined(__DOXYGEN__)
+#define STM32_PLLCLKIN              (STM32_HSECLK / STM32_PREDIV_VALUE)
+#elif STM32_PLLSRC == STM32_PLLSRC_HSI
+#define STM32_PLLCLKIN              (STM32_HSICLK / 2)
+#else
+#error "invalid STM32_PLLSRC value specified"
+#endif
+
+/* PLL input frequency range check.*/
+#if (STM32_PLLCLKIN < STM32_PLLIN_MIN) || (STM32_PLLCLKIN > STM32_PLLIN_MAX)
+#error "STM32_PLLCLKIN outside acceptable range (STM32_PLLIN_MIN...STM32_PLLIN_MAX)"
+#endif
+
+/**
+ * @brief   PLL output clock frequency.
+ */
+#define STM32_PLLCLKOUT             (STM32_PLLCLKIN * STM32_PLLMUL_VALUE)
+
+/* PLL output frequency range check.*/
+#if (STM32_PLLCLKOUT < STM32_PLLOUT_MIN) || (STM32_PLLCLKOUT > STM32_PLLOUT_MAX)
+#error "STM32_PLLCLKOUT outside acceptable range (STM32_PLLOUT_MIN...STM32_PLLOUT_MAX)"
+#endif
+
+/**
+ * @brief   System clock source.
+ */
+#if (STM32_SW == STM32_SW_PLL) || defined(__DOXYGEN__)
+#define STM32_SYSCLK                STM32_PLLCLKOUT
+#elif (STM32_SW == STM32_SW_HSI)
+#define STM32_SYSCLK                STM32_HSICLK
+#elif (STM32_SW == STM32_SW_HSE)
+#define STM32_SYSCLK                STM32_HSECLK
+#else
+#error "invalid STM32_SW value specified"
+#endif
+
+/* Check on the system clock.*/
+#if STM32_SYSCLK > STM32_SYSCLK_MAX
+#error "STM32_SYSCLK above maximum rated frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief   AHB frequency.
+ */
+#if (STM32_HPRE == STM32_HPRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_HCLK                  (STM32_SYSCLK / 1)
+#elif STM32_HPRE == STM32_HPRE_DIV2
+#define STM32_HCLK                  (STM32_SYSCLK / 2)
+#elif STM32_HPRE == STM32_HPRE_DIV4
+#define STM32_HCLK                  (STM32_SYSCLK / 4)
+#elif STM32_HPRE == STM32_HPRE_DIV8
+#define STM32_HCLK                  (STM32_SYSCLK / 8)
+#elif STM32_HPRE == STM32_HPRE_DIV16
+#define STM32_HCLK                  (STM32_SYSCLK / 16)
+#elif STM32_HPRE == STM32_HPRE_DIV64
+#define STM32_HCLK                  (STM32_SYSCLK / 64)
+#elif STM32_HPRE == STM32_HPRE_DIV128
+#define STM32_HCLK                  (STM32_SYSCLK / 128)
+#elif STM32_HPRE == STM32_HPRE_DIV256
+#define STM32_HCLK                  (STM32_SYSCLK / 256)
+#elif STM32_HPRE == STM32_HPRE_DIV512
+#define STM32_HCLK                  (STM32_SYSCLK / 512)
+#else
+#error "invalid STM32_HPRE value specified"
+#endif
+
+/* AHB frequency check.*/
+#if STM32_HCLK > STM32_SYSCLK_MAX
+#error "STM32_HCLK exceeding maximum frequency (STM32_SYSCLK_MAX)"
+#endif
+
+/**
+ * @brief   APB1 frequency.
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK1                  (STM32_HCLK / 1)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV2
+#define STM32_PCLK1                  (STM32_HCLK / 2)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV4
+#define STM32_PCLK1                  (STM32_HCLK / 4)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV8
+#define STM32_PCLK1                  (STM32_HCLK / 8)
+#elif STM32_PPRE1 == STM32_PPRE1_DIV16
+#define STM32_PCLK1                  (STM32_HCLK / 16)
+#else
+#error "invalid STM32_PPRE1 value specified"
+#endif
+
+/* APB1 frequency check.*/
+#if STM32_PCLK1 > STM32_PCLK1_MAX
+#error "STM32_PCLK1 exceeding maximum frequency (STM32_PCLK1_MAX)"
+#endif
+
+/**
+ * @brief   APB2 frequency.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_PCLK2                  (STM32_HCLK / 1)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV2
+#define STM32_PCLK2                  (STM32_HCLK / 2)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV4
+#define STM32_PCLK2                  (STM32_HCLK / 4)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV8
+#define STM32_PCLK2                  (STM32_HCLK / 8)
+#elif STM32_PPRE2 == STM32_PPRE2_DIV16
+#define STM32_PCLK2                  (STM32_HCLK / 16)
+#else
+#error "invalid STM32_PPRE2 value specified"
+#endif
+
+/* APB2 frequency check.*/
+#if STM32_PCLK2 > STM32_PCLK2_MAX
+#error "STM32_PCLK2 exceeding maximum frequency (STM32_PCLK2_MAX)"
+#endif
+
+/**
+ * @brief   RTC clock.
+ */
+#if (STM32_RTCSEL == STM32_RTCSEL_LSE) || defined(__DOXYGEN__)
+#define STM32_RTCCLK                STM32_LSECLK
+#elif STM32_RTCSEL == STM32_RTCSEL_LSI
+#define STM32_RTCCLK                STM32_LSICLK
+#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+#define STM32_RTCCLK                (STM32_HSECLK / 32)
+#elif STM32_RTCSEL == STM32_RTCSEL_NOCLOCK
+#define STM32_RTCCLK                0
+#else
+#error "invalid source selected for RTC clock"
+#endif
+
+/**
+ * @brief   ADC12 frequency.
+ */
+#if (STM32_ADC12PRES == STM32_ADC12PRES_NOCLOCK) || defined(__DOXYGEN__)
+#define STM32_ADC12CLK              0
+#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV1
+#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 1)
+#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV2
+#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 2)
+#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV4
+#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 4)
+#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV6
+#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 6)
+#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV8
+#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 8)
+#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV10
+#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 10)
+#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV12
+#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 12)
+#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV16
+#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 16)
+#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV32
+#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 32)
+#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV64
+#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 64)
+#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV128
+#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 128)
+#elif STM32_ADC12PRES == STM32_ADC12PRES_DIV256
+#define STM32_ADC12CLK              (STM32_PLLCLKOUT / 256)
+#else
+#error "invalid STM32_ADC12PRES value specified"
+#endif
+
+/**
+ * @brief   ADC34 frequency.
+ */
+#if (STM32_ADC43PRES == STM32_ADC34PRES_NOCLOCK) || defined(__DOXYGEN__)
+#define STM32_ADC34CLK              0
+#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV1
+#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 1)
+#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV2
+#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 2)
+#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV4
+#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 4)
+#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV6
+#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 6)
+#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV8
+#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 8)
+#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV10
+#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 10)
+#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV12
+#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 12)
+#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV16
+#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 16)
+#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV32
+#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 32)
+#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV64
+#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 64)
+#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV128
+#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 128)
+#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV256
+#define STM32_ADC34CLK              (STM32_PLLCLKOUT / 256)
+#else
+#error "invalid STM32_ADC34PRES value specified"
+#endif
+
+/* ADC12 frequency check.*/
+#if STM32_ADC12CLK > STM32_ADCCLK_MAX
+#error "STM32_ADC12CLK exceeding maximum frequency (STM32_ADCCLK_MAX)"
+#endif
+
+/* ADC34 frequency check.*/
+#if STM32_ADC34CLK > STM32_ADCCLK_MAX
+#error "STM32_ADC34CLK exceeding maximum frequency (STM32_ADCCLK_MAX)"
+#endif
+
+/**
+ * @brief   I2C1 frequency.
+ */
+#if STM32_I2C1SW == STM32_I2C1SW_HSI
+#define STM32_I2C1CLK               STM32_HSICLK
+#elif STM32_I2C1SW == STM32_I2C1SW_SYSCLK
+#define STM32_I2C1CLK               STM32_SYSCLK
+#else
+#error "invalid source selected for I2C1 clock"
+#endif
+
+/**
+ * @brief   I2C2 frequency.
+ */
+#if STM32_I2C2SW == STM32_I2C2SW_HSI
+#define STM32_I2C2CLK               STM32_HSICLK
+#elif STM32_I2C2SW == STM32_I2C2SW_SYSCLK
+#define STM32_I2C2CLK               STM32_SYSCLK
+#else
+#error "invalid source selected for I2C2 clock"
+#endif
+
+/**
+ * @brief   USART1 frequency.
+ */
+#if STM32_USART1SW == STM32_USART1SW_PCLK
+#define STM32_USART1CLK             STM32_PCLK2
+#elif STM32_USART1SW == STM32_USART1SW_SYSCLK
+#define STM32_USART1CLK             STM32_SYSCLK
+#elif STM32_USART1SW == STM32_USART1SW_LSECLK
+#define STM32_USART1CLK             STM32_LSECLK
+#elif STM32_USART1SW == STM32_USART1SW_HSICLK
+#define STM32_USART1CLK             STM32_HSICLK
+#else
+#error "invalid source selected for USART1 clock"
+#endif
+
+/**
+ * @brief   USART2 frequency.
+ */
+#if STM32_USART2SW == STM32_USART2SW_PCLK
+#define STM32_USART2CLK             STM32_PCLK1
+#elif STM32_USART2SW == STM32_USART2SW_SYSCLK
+#define STM32_USART2CLK             STM32_SYSCLK
+#elif STM32_USART2SW == STM32_USART2SW_LSECLK
+#define STM32_USART2CLK             STM32_LSECLK
+#elif STM32_USART2SW == STM32_USART2SW_HSICLK
+#define STM32_USART2CLK             STM32_HSICLK
+#else
+#error "invalid source selected for USART2 clock"
+#endif
+
+/**
+ * @brief   USART3 frequency.
+ */
+#if STM32_USART3SW == STM32_USART3SW_PCLK
+#define STM32_USART3CLK             STM32_PCLK1
+#elif STM32_USART3SW == STM32_USART3SW_SYSCLK
+#define STM32_USART3CLK             STM32_SYSCLK
+#elif STM32_USART3SW == STM32_USART3SW_LSECLK
+#define STM32_USART3CLK             STM32_LSECLK
+#elif STM32_USART3SW == STM32_USART3SW_HSICLK
+#define STM32_USART3CLK             STM32_HSICLK
+#else
+#error "invalid source selected for USART3 clock"
+#endif
+
+/**
+ * @brief   UART4 frequency.
+ */
+#if STM32_UART4SW == STM32_UART4SW_PCLK
+#define STM32_UART4CLK             STM32_PCLK1
+#elif STM32_UART4SW == STM32_UART4SW_SYSCLK
+#define STM32_UART4CLK             STM32_SYSCLK
+#elif STM32_UART4SW == STM32_UART4SW_LSECLK
+#define STM32_UART4CLK             STM32_LSECLK
+#elif STM32_UART4SW == STM32_UART4SW_HSICLK
+#define STM32_UART4CLK             STM32_HSICLK
+#else
+#error "invalid source selected for UART4 clock"
+#endif
+
+/**
+ * @brief   UART5 frequency.
+ */
+#if STM32_UART5SW == STM32_UART5SW_PCLK
+#define STM32_UART5CLK             STM32_PCLK1
+#elif STM32_UART5SW == STM32_UART5SW_SYSCLK
+#define STM32_UART5CLK             STM32_SYSCLK
+#elif STM32_UART5SW == STM32_UART5SW_LSECLK
+#define STM32_UART5CLK             STM32_LSECLK
+#elif STM32_UART5SW == STM32_UART5SW_HSICLK
+#define STM32_UART5CLK             STM32_HSICLK
+#else
+#error "invalid source selected for UART5 clock"
+#endif
+
+/**
+ * @brief   TIM1 frequency.
+ */
+#if STM32_TIM1SW == STM32_TIM1SW_PCLK2
+#define STM32_TIM1CLK               STM32_PCLK2
+
+#elif STM32_TIM1SW == STM32_TIM1SW_PLLX2
+#if (STM32_SW != STM32_SW_PLL) ||                                           \
+    (STM32_HPRE != STM32_HPRE_DIV1) ||                                      \
+    (STM32_PPRE2 != STM32_PPRE2_DIV1)
+#error "double clock mode cannot be activated for TIM1 under the current settings"
+#endif
+#define STM32_TIM1CLK               (STM32_PLLCLKOUT * 2)
+
+#else
+#error "invalid source selected for TIM1 clock"
+#endif
+
+/**
+ * @brief   TIM8 frequency.
+ */
+#if STM32_TIM8SW == STM32_TIM8SW_PCLK2
+#define STM32_TIM8CLK               STM32_PCLK2
+
+#elif STM32_TIM8SW == STM32_TIM8SW_PLLX2
+#if (STM32_SW != STM32_SW_PLL) ||                                           \
+    (STM32_HPRE != STM32_HPRE_DIV1) ||                                      \
+    (STM32_PPRE2 != STM32_PPRE2_DIV1)
+#error "double clock mode cannot be activated for TIM8 under the current settings"
+#endif
+#define STM32_TIM8CLK               (STM32_PLLCLKOUT * 2)
+
+#else
+#error "invalid source selected for TIM8 clock"
+#endif
+
+/**
+ * @brief   Timers 2, 3, 4, 6, 7 frequency.
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK1               (STM32_PCLK1 * 1)
+#else
+#define STM32_TIMCLK1               (STM32_PCLK1 * 2)
+#endif
+
+/**
+ * @brief   Timers 1, 8, 15, 16, 17 frequency.
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK2               (STM32_PCLK2 * 1)
+#else
+#define STM32_TIMCLK2               (STM32_PCLK2 * 2)
+#endif
+
+/**
+ * @brief   USB frequency.
+ */
+#if (STM32_USBPRE == STM32_USBPRE_DIV1P5) || defined(__DOXYGEN__)
+#define STM32_USBCLK                ((STM32_PLLCLKOUT * 2) / 3)
+#elif (STM32_USBPRE == STM32_USBPRE_DIV1)
+#define STM32_USBCLK                STM32_PLLCLKOUT
+#else
+#error "invalid STM32_USBPRE value specified"
+#endif
+
+/**
+ * @brief   Flash settings.
+ */
+#if (STM32_HCLK <= 24000000) || defined(__DOXYGEN__)
+#define STM32_FLASHBITS             0x00000010
+#elif STM32_HCLK <= 48000000
+#define STM32_FLASHBITS             0x00000011
+#else
+#define STM32_FLASHBITS             0x00000012
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+/* Various helpers.*/
+#include "nvic.h"
+#include "stm32_isr.h"
+#include "stm32_dma.h"
+#include "stm32_rcc.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void hal_lld_init(void);
+  void stm32_clock_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _HAL_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F3xx/platform.mk b/os/hal/ports/STM32/STM32F3xx/platform.mk
new file mode 100644
index 000000000..5851cf65b
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F3xx/platform.mk
@@ -0,0 +1,31 @@
+# List of all the STM32F3xx platform files.
+PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32F3xx/stm32_dma.c \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32F3xx/hal_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32F3xx/adc_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32F3xx/ext_lld_isr.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/can_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/ext_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/GPIOv2/pal_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/I2Cv2/i2c_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/RTCv2/rtc_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/SPIv2/spi_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1/gpt_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1/icu_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1/pwm_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1/st_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv2/serial_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv2/uart_lld.c \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/USBv1/usb_lld.c
+
+# Required include directories
+PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
+              ${CHIBIOS}/os/hal/ports/STM32/STM32F3xx \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/GPIOv2 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/I2Cv2 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/RTCv2 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/SPIv2 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv2 \
+              ${CHIBIOS}/os/hal/ports/STM32/LLD/USBv1
diff --git a/os/hal/ports/STM32/STM32F3xx/stm32_dma.c b/os/hal/ports/STM32/STM32F3xx/stm32_dma.c
new file mode 100644
index 000000000..e956fe9e4
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F3xx/stm32_dma.c
@@ -0,0 +1,449 @@
+/*
+    ChibiOS/HAL - Copyright (C) 2006-2014 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F3xx/stm32_dma.c
+ * @brief   DMA helper driver code.
+ *
+ * @addtogroup STM32F3xx_DMA
+ * @details DMA sharing helper driver. In the STM32 the DMA streams are a
+ *          shared resource, this driver allows to allocate and free DMA
+ *          streams at runtime in order to allow all the other device
+ *          drivers to coordinate the access to the resource.
+ * @note    The DMA ISR handlers are all declared into this module because
+ *          sharing, the various device drivers can associate a callback to
+ *          ISRs when allocating streams.
+ * @{
+ */
+
+#include "hal.h"
+
+/* The following macro is only defined if some driver requiring DMA services
+   has been enabled.*/
+#if defined(STM32_DMA_REQUIRED) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/**
+ * @brief   Mask of the DMA1 streams in @p dma_streams_mask.
+ */
+#define STM32_DMA1_STREAMS_MASK     0x0000007F
+
+/**
+ * @brief   Mask of the DMA2 streams in @p dma_streams_mask.
+ */
+#define STM32_DMA2_STREAMS_MASK     0x00000F80
+
+/**
+ * @brief   Post-reset value of the stream CCR register.
+ */
+#define STM32_DMA_CCR_RESET_VALUE   0x00000000
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   DMA streams descriptors.
+ * @details This table keeps the association between an unique stream
+ *          identifier and the involved physical registers.
+ * @note    Don't use this array directly, use the appropriate wrapper macros
+ *          instead: @p STM32_DMA1_STREAM1, @p STM32_DMA1_STREAM2 etc.
+ */
+const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS] = {
+  {DMA1_Channel1, &DMA1->IFCR, 0, 0, DMA1_Channel1_IRQn},
+  {DMA1_Channel2, &DMA1->IFCR, 4, 1, DMA1_Channel2_IRQn},
+  {DMA1_Channel3, &DMA1->IFCR, 8, 2, DMA1_Channel3_IRQn},
+  {DMA1_Channel4, &DMA1->IFCR, 12, 3, DMA1_Channel4_IRQn},
+  {DMA1_Channel5, &DMA1->IFCR, 16, 4, DMA1_Channel5_IRQn},
+  {DMA1_Channel6, &DMA1->IFCR, 20, 5, DMA1_Channel6_IRQn},
+  {DMA1_Channel7, &DMA1->IFCR, 24, 6, DMA1_Channel7_IRQn},
+  {DMA2_Channel1, &DMA2->IFCR, 0, 7, DMA2_Channel1_IRQn},
+  {DMA2_Channel2, &DMA2->IFCR, 4, 8, DMA2_Channel2_IRQn},
+  {DMA2_Channel3, &DMA2->IFCR, 8, 9, DMA2_Channel3_IRQn},
+  {DMA2_Channel4, &DMA2->IFCR, 12, 10, DMA2_Channel4_IRQn},
+  {DMA2_Channel5, &DMA2->IFCR, 16, 11, DMA2_Channel5_IRQn},
+};
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   DMA ISR redirector type.
+ */
+typedef struct {
+  stm32_dmaisr_t        dma_func;       /**< @brief DMA callback function.  */
+  void                  *dma_param;     /**< @brief DMA callback parameter. */
+} dma_isr_redir_t;
+
+/**
+ * @brief   Mask of the allocated streams.
+ */
+static uint32_t dma_streams_mask;
+
+/**
+ * @brief   DMA IRQ redirectors.
+ */
+static dma_isr_redir_t dma_isr_redir[STM32_DMA_STREAMS];
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   DMA1 stream 1 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector6C) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 0) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = flags << 0;
+  if (dma_isr_redir[0].dma_func)
+    dma_isr_redir[0].dma_func(dma_isr_redir[0].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 2 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector70) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 4) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = flags << 4;
+  if (dma_isr_redir[1].dma_func)
+    dma_isr_redir[1].dma_func(dma_isr_redir[1].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 3 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector74) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 8) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = flags << 8;
+  if (dma_isr_redir[2].dma_func)
+    dma_isr_redir[2].dma_func(dma_isr_redir[2].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 4 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector78) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 12) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = flags << 12;
+  if (dma_isr_redir[3].dma_func)
+    dma_isr_redir[3].dma_func(dma_isr_redir[3].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 5 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector7C) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 16) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = flags << 16;
+  if (dma_isr_redir[4].dma_func)
+    dma_isr_redir[4].dma_func(dma_isr_redir[4].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 6 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector80) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 20) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = flags << 20;
+  if (dma_isr_redir[5].dma_func)
+    dma_isr_redir[5].dma_func(dma_isr_redir[5].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA1 stream 7 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector84) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA1->ISR >> 24) & STM32_DMA_ISR_MASK;
+  DMA1->IFCR = flags << 24;
+  if (dma_isr_redir[6].dma_func)
+    dma_isr_redir[6].dma_func(dma_isr_redir[6].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA2 stream 1 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector120) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA2->ISR >> 0) & STM32_DMA_ISR_MASK;
+  DMA2->IFCR = flags << 0;
+  if (dma_isr_redir[7].dma_func)
+    dma_isr_redir[7].dma_func(dma_isr_redir[7].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA2 stream 2 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector124) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA2->ISR >> 4) & STM32_DMA_ISR_MASK;
+  DMA2->IFCR = flags << 4;
+  if (dma_isr_redir[8].dma_func)
+    dma_isr_redir[8].dma_func(dma_isr_redir[8].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA2 stream 3 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector128) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA2->ISR >> 8) & STM32_DMA_ISR_MASK;
+  DMA2->IFCR = flags << 8;
+  if (dma_isr_redir[9].dma_func)
+    dma_isr_redir[9].dma_func(dma_isr_redir[9].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA2 stream 4 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector12C) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA2->ISR >> 12) & STM32_DMA_ISR_MASK;
+  DMA2->IFCR = flags << 12;
+  if (dma_isr_redir[10].dma_func)
+    dma_isr_redir[10].dma_func(dma_isr_redir[10].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   DMA2 stream 5 shared interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(Vector130) {
+  uint32_t flags;
+
+  OSAL_IRQ_PROLOGUE();
+
+  flags = (DMA2->ISR >> 16) & STM32_DMA_ISR_MASK;
+  DMA2->IFCR = flags << 16;
+  if (dma_isr_redir[11].dma_func)
+    dma_isr_redir[11].dma_func(dma_isr_redir[11].dma_param, flags);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   STM32 DMA helper initialization.
+ *
+ * @init
+ */
+void dmaInit(void) {
+  int i;
+
+  dma_streams_mask = 0;
+  for (i = 0; i < STM32_DMA_STREAMS; i++) {
+    _stm32_dma_streams[i].channel->CCR = 0;
+    dma_isr_redir[i].dma_func = NULL;
+  }
+  DMA1->IFCR = 0xFFFFFFFF;
+#if STM32_HAS_DMA2
+  DMA2->IFCR = 0xFFFFFFFF;
+#endif
+}
+
+/**
+ * @brief   Allocates a DMA stream.
+ * @details The stream is allocated and, if required, the DMA clock enabled.
+ *          The function also enables the IRQ vector associated to the stream
+ *          and initializes its priority.
+ * @pre     The stream must not be already in use or an error is returned.
+ * @post    The stream is allocated and the default ISR handler redirected
+ *          to the specified function.
+ * @post    The stream ISR vector is enabled and its priority configured.
+ * @post    The stream must be freed using @p dmaStreamRelease() before it can
+ *          be reused with another peripheral.
+ * @post    The stream is in its post-reset state.
+ * @note    This function can be invoked in both ISR or thread context.
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] priority  IRQ priority mask for the DMA stream
+ * @param[in] func      handling function pointer, can be @p NULL
+ * @param[in] param     a parameter to be passed to the handling function
+ * @return              The operation status.
+ * @retval FALSE        no error, stream taken.
+ * @retval TRUE         error, stream already taken.
+ *
+ * @special
+ */
+bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
+                       uint32_t priority,
+                       stm32_dmaisr_t func,
+                       void *param) {
+
+  osalDbgCheck(dmastp != NULL);
+
+  /* Checks if the stream is already taken.*/
+  if ((dma_streams_mask & (1 << dmastp->selfindex)) != 0)
+    return TRUE;
+
+  /* Marks the stream as allocated.*/
+  dma_isr_redir[dmastp->selfindex].dma_func  = func;
+  dma_isr_redir[dmastp->selfindex].dma_param = param;
+  dma_streams_mask |= (1 << dmastp->selfindex);
+
+  /* Enabling DMA clocks required by the current streams set.*/
+  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) != 0)
+    rccEnableDMA1(FALSE);
+#if STM32_HAS_DMA2
+  if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) != 0)
+    rccEnableDMA2(FALSE);
+#endif
+
+  /* Putting the stream in a safe state.*/
+  dmaStreamDisable(dmastp);
+  dmastp->channel->CCR = STM32_DMA_CCR_RESET_VALUE;
+
+  /* Enables the associated IRQ vector if a callback is defined.*/
+  if (func != NULL)
+    nvicEnableVector(dmastp->vector, priority);
+
+  return FALSE;
+}
+
+/**
+ * @brief   Releases a DMA stream.
+ * @details The stream is freed and, if required, the DMA clock disabled.
+ *          Trying to release a unallocated stream is an illegal operation
+ *          and is trapped if assertions are enabled.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    The stream is again available.
+ * @note    This function can be invoked in both ISR or thread context.
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ *
+ * @special
+ */
+void dmaStreamRelease(const stm32_dma_stream_t *dmastp) {
+
+  osalDbgCheck(dmastp != NULL);
+
+  /* Check if the streams is not taken.*/
+  osalDbgAssert((dma_streams_mask & (1 << dmastp->selfindex)) != 0,
+                "not allocated");
+
+  /* Disables the associated IRQ vector.*/
+  nvicDisableVector(dmastp->vector);
+
+  /* Marks the stream as not allocated.*/
+  dma_streams_mask &= ~(1 << dmastp->selfindex);
+
+  /* Shutting down clocks that are no more required, if any.*/
+  if ((dma_streams_mask & STM32_DMA1_STREAMS_MASK) == 0)
+    rccDisableDMA1(FALSE);
+#if STM32_HAS_DMA2
+  if ((dma_streams_mask & STM32_DMA2_STREAMS_MASK) == 0)
+    rccDisableDMA2(FALSE);
+#endif
+}
+
+#endif /* STM32_DMA_REQUIRED */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F3xx/stm32_dma.h b/os/hal/ports/STM32/STM32F3xx/stm32_dma.h
new file mode 100644
index 000000000..afb167615
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F3xx/stm32_dma.h
@@ -0,0 +1,406 @@
+/*
+    ChibiOS/HAL - Copyright (C) 2006-2014 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F3xx/stm32_dma.h
+ * @brief   DMA helper driver header.
+ * @note    This file requires definitions from the ST header file stm32f30x.h.
+ * @note    This driver uses the new naming convention used for the STM32F2xx
+ *          so the "DMA channels" are referred as "DMA streams".
+ *
+ * @addtogroup STM32F3xx_DMA
+ * @{
+ */
+
+#ifndef _STM32_DMA_H_
+#define _STM32_DMA_H_
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Total number of DMA streams.
+ * @note    This is the total number of streams among all the DMA units.
+ */
+#if STM32_HAS_DMA2 || defined(__DOXYGEN__)
+#define STM32_DMA_STREAMS           12
+#else
+#define STM32_DMA_STREAMS           7
+#endif
+
+/**
+ * @brief   Mask of the ISR bits passed to the DMA callback functions.
+ */
+#define STM32_DMA_ISR_MASK          0x0F
+
+/**
+ * @brief   Returns the channel associated to the specified stream.
+ *
+ * @param[in] n         the stream number (0...STM32_DMA_STREAMS-1)
+ * @param[in] c         a stream/channel association word, one channel per
+ *                      nibble, not associated channels must be set to 0xF
+ * @return              Always zero, in this platform there is no dynamic
+ *                      association between streams and channels.
+ */
+#define STM32_DMA_GETCHANNEL(n, c)  0
+
+/**
+ * @brief   Checks if a DMA priority is within the valid range.
+ * @param[in] prio      DMA priority
+ *
+ * @retval              The check result.
+ * @retval FALSE        invalid DMA priority.
+ * @retval TRUE         correct DMA priority.
+ */
+#define STM32_DMA_IS_VALID_PRIORITY(prio) (((prio) >= 0) && ((prio) <= 3))
+
+/**
+ * @brief   Returns an unique numeric identifier for a DMA stream.
+ *
+ * @param[in] dma       the DMA unit number
+ * @param[in] stream    the stream number
+ * @return              An unique numeric stream identifier.
+ */
+#define STM32_DMA_STREAM_ID(dma, stream) ((((dma) - 1) * 7) + ((stream) - 1))
+
+/**
+ * @brief   Returns a DMA stream identifier mask.
+ *
+ *
+ * @param[in] dma       the DMA unit number
+ * @param[in] stream    the stream number
+ * @return              A DMA stream identifier mask.
+ */
+#define STM32_DMA_STREAM_ID_MSK(dma, stream)                                \
+  (1 << STM32_DMA_STREAM_ID(dma, stream))
+
+/**
+ * @brief   Checks if a DMA stream unique identifier belongs to a mask.
+ * @param[in] id        the stream numeric identifier
+ * @param[in] mask      the stream numeric identifiers mask
+ *
+ * @retval              The check result.
+ * @retval FALSE        id does not belong to the mask.
+ * @retval TRUE         id belongs to the mask.
+ */
+#define STM32_DMA_IS_VALID_ID(id, mask) (((1 << (id)) & (mask)))
+
+/**
+ * @name    DMA streams identifiers
+ * @{
+ */
+/**
+ * @brief   Returns a pointer to a stm32_dma_stream_t structure.
+ *
+ * @param[in] id        the stream numeric identifier
+ * @return              A pointer to the stm32_dma_stream_t constant structure
+ *                      associated to the DMA stream.
+ */
+#define STM32_DMA_STREAM(id)        (&_stm32_dma_streams[id])
+
+#define STM32_DMA1_STREAM1          STM32_DMA_STREAM(0)
+#define STM32_DMA1_STREAM2          STM32_DMA_STREAM(1)
+#define STM32_DMA1_STREAM3          STM32_DMA_STREAM(2)
+#define STM32_DMA1_STREAM4          STM32_DMA_STREAM(3)
+#define STM32_DMA1_STREAM5          STM32_DMA_STREAM(4)
+#define STM32_DMA1_STREAM6          STM32_DMA_STREAM(5)
+#define STM32_DMA1_STREAM7          STM32_DMA_STREAM(6)
+#define STM32_DMA2_STREAM1          STM32_DMA_STREAM(7)
+#define STM32_DMA2_STREAM2          STM32_DMA_STREAM(8)
+#define STM32_DMA2_STREAM3          STM32_DMA_STREAM(9)
+#define STM32_DMA2_STREAM4          STM32_DMA_STREAM(10)
+#define STM32_DMA2_STREAM5          STM32_DMA_STREAM(11)
+/** @} */
+
+/**
+ * @name    CR register constants common to all DMA types
+ * @{
+ */
+#define STM32_DMA_CR_EN             DMA_CCR_EN
+#define STM32_DMA_CR_TEIE           DMA_CCR_TEIE
+#define STM32_DMA_CR_HTIE           DMA_CCR_HTIE
+#define STM32_DMA_CR_TCIE           DMA_CCR_TCIE
+#define STM32_DMA_CR_DIR_MASK       (DMA_CCR_DIR | DMA_CCR_MEM2MEM)
+#define STM32_DMA_CR_DIR_P2M        0
+#define STM32_DMA_CR_DIR_M2P        DMA_CCR_DIR
+#define STM32_DMA_CR_DIR_M2M        DMA_CCR_MEM2MEM
+#define STM32_DMA_CR_CIRC           DMA_CCR_CIRC
+#define STM32_DMA_CR_PINC           DMA_CCR_PINC
+#define STM32_DMA_CR_MINC           DMA_CCR_MINC
+#define STM32_DMA_CR_PSIZE_MASK     DMA_CCR_PSIZE
+#define STM32_DMA_CR_PSIZE_BYTE     0
+#define STM32_DMA_CR_PSIZE_HWORD    DMA_CCR_PSIZE_0
+#define STM32_DMA_CR_PSIZE_WORD     DMA_CCR_PSIZE_1
+#define STM32_DMA_CR_MSIZE_MASK     DMA_CCR_MSIZE
+#define STM32_DMA_CR_MSIZE_BYTE     0
+#define STM32_DMA_CR_MSIZE_HWORD    DMA_CCR_MSIZE_0
+#define STM32_DMA_CR_MSIZE_WORD     DMA_CCR_MSIZE_1
+#define STM32_DMA_CR_SIZE_MASK      (STM32_DMA_CR_PSIZE_MASK |              \
+                                     STM32_DMA_CR_MSIZE_MASK)
+#define STM32_DMA_CR_PL_MASK        DMA_CCR_PL
+#define STM32_DMA_CR_PL(n)          ((n) << 12)
+/** @} */
+
+/**
+ * @name    CR register constants only found in enhanced DMA
+ * @{
+ */
+#define STM32_DMA_CR_DMEIE          0   /**< @brief Ignored by normal DMA.  */
+#define STM32_DMA_CR_CHSEL_MASK     0   /**< @brief Ignored by normal DMA.  */
+#define STM32_DMA_CR_CHSEL(n)       0   /**< @brief Ignored by normal DMA.  */
+/** @} */
+
+/**
+ * @name    Status flags passed to the ISR callbacks
+ * @{
+ */
+#define STM32_DMA_ISR_FEIF          0
+#define STM32_DMA_ISR_DMEIF         0
+#define STM32_DMA_ISR_TEIF          DMA_ISR_TEIF1
+#define STM32_DMA_ISR_HTIF          DMA_ISR_HTIF1
+#define STM32_DMA_ISR_TCIF          DMA_ISR_TCIF1
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   STM32 DMA stream descriptor structure.
+ */
+typedef struct {
+  DMA_Channel_TypeDef   *channel;       /**< @brief Associated DMA channel. */
+  volatile uint32_t     *ifcr;          /**< @brief Associated IFCR reg.    */
+  uint8_t               ishift;         /**< @brief Bits offset in xIFCR
+                                             register.                      */
+  uint8_t               selfindex;      /**< @brief Index to self in array. */
+  uint8_t               vector;         /**< @brief Associated IRQ vector.  */
+} stm32_dma_stream_t;
+
+/**
+ * @brief   STM32 DMA ISR function type.
+ *
+ * @param[in] p         parameter for the registered function
+ * @param[in] flags     pre-shifted content of the ISR register, the bits
+ *                      are aligned to bit zero
+ */
+typedef void (*stm32_dmaisr_t)(void *p, uint32_t flags);
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @name    Macro Functions
+ * @{
+ */
+/**
+ * @brief   Associates a peripheral data register to a DMA stream.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] addr      value to be written in the CPAR register
+ *
+ * @special
+ */
+#define dmaStreamSetPeripheral(dmastp, addr) {                              \
+  (dmastp)->channel->CPAR  = (uint32_t)(addr);                              \
+}
+
+/**
+ * @brief   Associates a memory destination to a DMA stream.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] addr      value to be written in the CMAR register
+ *
+ * @special
+ */
+#define dmaStreamSetMemory0(dmastp, addr) {                                 \
+  (dmastp)->channel->CMAR  = (uint32_t)(addr);                              \
+}
+
+/**
+ * @brief   Sets the number of transfers to be performed.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] size      value to be written in the CNDTR register
+ *
+ * @special
+ */
+#define dmaStreamSetTransactionSize(dmastp, size) {                         \
+  (dmastp)->channel->CNDTR  = (uint32_t)(size);                             \
+}
+
+/**
+ * @brief   Returns the number of transfers to be performed.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @return              The number of transfers to be performed.
+ *
+ * @special
+ */
+#define dmaStreamGetTransactionSize(dmastp) ((size_t)((dmastp)->channel->CNDTR))
+
+/**
+ * @brief   Programs the stream mode settings.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] mode      value to be written in the CCR register
+ *
+ * @special
+ */
+#define dmaStreamSetMode(dmastp, mode) {                                    \
+  (dmastp)->channel->CCR  = (uint32_t)(mode);                               \
+}
+
+/**
+ * @brief   DMA stream enable.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ *
+ * @special
+ */
+#define dmaStreamEnable(dmastp) {                                           \
+  (dmastp)->channel->CCR |= STM32_DMA_CR_EN;                                \
+}
+
+/**
+ * @brief   DMA stream disable.
+ * @details The function disables the specified stream and then clears any
+ *          pending interrupt.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @note    Interrupts enabling flags are set to zero after this call, see
+ *          bug 3607518.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ *
+ * @special
+ */
+#define dmaStreamDisable(dmastp) {                                          \
+  (dmastp)->channel->CCR &= ~(STM32_DMA_CR_TCIE | STM32_DMA_CR_HTIE |       \
+                              STM32_DMA_CR_TEIE | STM32_DMA_CR_EN);         \
+  dmaStreamClearInterrupt(dmastp);                                          \
+}
+
+/**
+ * @brief   DMA stream interrupt sources clear.
+ * @note    This function can be invoked in both ISR or thread context.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ *
+ * @special
+ */
+#define dmaStreamClearInterrupt(dmastp) {                                   \
+  *(dmastp)->ifcr = STM32_DMA_ISR_MASK << (dmastp)->ishift;                 \
+}
+
+/**
+ * @brief   Starts a memory to memory operation using the specified stream.
+ * @note    The default transfer data mode is "byte to byte" but it can be
+ *          changed by specifying extra options in the @p mode parameter.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ * @param[in] mode      value to be written in the CCR register, this value
+ *                      is implicitly ORed with:
+ *                      - @p STM32_DMA_CR_MINC
+ *                      - @p STM32_DMA_CR_PINC
+ *                      - @p STM32_DMA_CR_DIR_M2M
+ *                      - @p STM32_DMA_CR_EN
+ *                      .
+ * @param[in] src       source address
+ * @param[in] dst       destination address
+ * @param[in] n         number of data units to copy
+ */
+#define dmaStartMemCopy(dmastp, mode, src, dst, n) {                        \
+  dmaStreamSetPeripheral(dmastp, src);                                      \
+  dmaStreamSetMemory0(dmastp, dst);                                         \
+  dmaStreamSetTransactionSize(dmastp, n);                                   \
+  dmaStreamSetMode(dmastp, (mode) |                                         \
+                           STM32_DMA_CR_MINC | STM32_DMA_CR_PINC |          \
+                           STM32_DMA_CR_DIR_M2M | STM32_DMA_CR_EN);         \
+}
+
+/**
+ * @brief   Polled wait for DMA transfer end.
+ * @pre     The stream must have been allocated using @p dmaStreamAllocate().
+ * @post    After use the stream can be released using @p dmaStreamRelease().
+ *
+ * @param[in] dmastp    pointer to a stm32_dma_stream_t structure
+ */
+#define dmaWaitCompletion(dmastp) {                                         \
+  while ((dmastp)->channel->CNDTR > 0)                                      \
+    ;                                                                       \
+  dmaStreamDisable(dmastp);                                                 \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if !defined(__DOXYGEN__)
+extern const stm32_dma_stream_t _stm32_dma_streams[STM32_DMA_STREAMS];
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void dmaInit(void);
+  bool dmaStreamAllocate(const stm32_dma_stream_t *dmastp,
+                         uint32_t priority,
+                         stm32_dmaisr_t func,
+                         void *param);
+  void dmaStreamRelease(const stm32_dma_stream_t *dmastp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _STM32_DMA_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F3xx/stm32_isr.h b/os/hal/ports/STM32/STM32F3xx/stm32_isr.h
new file mode 100644
index 000000000..410c2d793
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F3xx/stm32_isr.h
@@ -0,0 +1,132 @@
+/*
+    ChibiOS/HAL - Copyright (C) 2006-2014 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F3xx/stm32_isr.h
+ * @brief   ISR remapper driver header.
+ *
+ * @addtogroup STM32F3xx_ISR
+ * @{
+ */
+
+#ifndef _STM32_ISR_H_
+#define _STM32_ISR_H_
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @name    ISR names and numbers remapping
+ * @{
+ */
+/*
+ * CAN units.
+ */
+#define STM32_CAN1_TX_HANDLER       Vector8C
+#define STM32_CAN1_RX0_HANDLER      Vector90
+#define STM32_CAN1_RX1_HANDLER      Vector94
+#define STM32_CAN1_SCE_HANDLER      Vector98
+
+#define STM32_CAN1_TX_NUMBER        19
+#define STM32_CAN1_RX0_NUMBER       20
+#define STM32_CAN1_RX1_NUMBER       21
+#define STM32_CAN1_SCE_NUMBER       22
+
+/*
+ * I2C units.
+ */
+#define STM32_I2C1_EVENT_HANDLER    VectorBC
+#define STM32_I2C1_ERROR_HANDLER    VectorC0
+#define STM32_I2C1_EVENT_NUMBER     31
+#define STM32_I2C1_ERROR_NUMBER     32
+
+#define STM32_I2C2_EVENT_HANDLER    VectorC4
+#define STM32_I2C2_ERROR_HANDLER    VectorC8
+#define STM32_I2C2_EVENT_NUMBER     33
+#define STM32_I2C2_ERROR_NUMBER     34
+
+/*
+ * TIM units.
+ */
+#define STM32_TIM1_UP_HANDLER       VectorA4
+#define STM32_TIM1_CC_HANDLER       VectorAC
+#define STM32_TIM2_HANDLER          VectorB0
+#define STM32_TIM3_HANDLER          VectorB4
+#define STM32_TIM4_HANDLER          VectorB8
+#define STM32_TIM6_HANDLER          Vector118
+#define STM32_TIM7_HANDLER          Vector11C
+#define STM32_TIM8_UP_HANDLER       VectorF0
+#define STM32_TIM8_CC_HANDLER       VectorF8
+
+#define STM32_TIM1_UP_NUMBER        25
+#define STM32_TIM1_CC_NUMBER        27
+#define STM32_TIM2_NUMBER           28
+#define STM32_TIM3_NUMBER           29
+#define STM32_TIM4_NUMBER           30
+#define STM32_TIM6_NUMBER           54
+#define STM32_TIM7_NUMBER           55
+#define STM32_TIM8_UP_NUMBER        44
+#define STM32_TIM8_CC_NUMBER        46
+
+/*
+ * USART units.
+ */
+#define STM32_USART1_HANDLER        VectorD4
+#define STM32_USART2_HANDLER        VectorD8
+#define STM32_USART3_HANDLER        VectorDC
+#define STM32_UART4_HANDLER         Vector110
+#define STM32_UART5_HANDLER         Vector114
+
+#define STM32_USART1_NUMBER         37
+#define STM32_USART2_NUMBER         38
+#define STM32_USART3_NUMBER         39
+#define STM32_UART4_NUMBER          52
+#define STM32_UART5_NUMBER          53
+
+/*
+ * USB units.
+ */
+#define STM32_USB1_HP_HANDLER       Vector168
+#define STM32_USB1_LP_HANDLER       Vector16C
+
+#define STM32_USB1_HP_NUMBER        74
+#define STM32_USB1_LP_NUMBER        75
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#endif /* _STM32_ISR_H_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F3xx/stm32_rcc.h b/os/hal/ports/STM32/STM32F3xx/stm32_rcc.h
new file mode 100644
index 000000000..208c2e6c8
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F3xx/stm32_rcc.h
@@ -0,0 +1,835 @@
+/*
+    ChibiOS/HAL - Copyright (C) 2006-2014 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F3xx/stm32_rcc.h
+ * @brief   RCC helper driver header.
+ * @note    This file requires definitions from the ST header file
+ *          @p stm32f30x.h.
+ *
+ * @addtogroup STM32F3xx_RCC
+ * @{
+ */
+
+#ifndef _STM32_RCC_
+#define _STM32_RCC_
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @name    Generic RCC operations
+ * @{
+ */
+/**
+ * @brief   Enables the clock of one or more peripheral on the APB1 bus.
+ *
+ * @param[in] mask      APB1 peripherals mask
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAPB1(mask, lp) {                                           \
+  RCC->APB1ENR |= (mask);                                                   \
+}
+
+/**
+ * @brief   Disables the clock of one or more peripheral on the APB1 bus.
+ *
+ * @param[in] mask      APB1 peripherals mask
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableAPB1(mask, lp) {                                          \
+  RCC->APB1ENR &= ~(mask);                                                  \
+}
+
+/**
+ * @brief   Resets one or more peripheral on the APB1 bus.
+ *
+ * @param[in] mask      APB1 peripherals mask
+ *
+ * @api
+ */
+#define rccResetAPB1(mask) {                                                \
+  RCC->APB1RSTR |= (mask);                                                  \
+  RCC->APB1RSTR = 0;                                                        \
+}
+
+/**
+ * @brief   Enables the clock of one or more peripheral on the APB2 bus.
+ *
+ * @param[in] mask      APB2 peripherals mask
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAPB2(mask, lp) {                                           \
+  RCC->APB2ENR |= (mask);                                                   \
+}
+
+/**
+ * @brief   Disables the clock of one or more peripheral on the APB2 bus.
+ *
+ * @param[in] mask      APB2 peripherals mask
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableAPB2(mask, lp) {                                          \
+  RCC->APB2ENR &= ~(mask);                                                  \
+}
+
+/**
+ * @brief   Resets one or more peripheral on the APB2 bus.
+ *
+ * @param[in] mask      APB2 peripherals mask
+ *
+ * @api
+ */
+#define rccResetAPB2(mask) {                                                \
+  RCC->APB2RSTR |= (mask);                                                  \
+  RCC->APB2RSTR = 0;                                                        \
+}
+
+/**
+ * @brief   Enables the clock of one or more peripheral on the AHB bus.
+ *
+ * @param[in] mask      AHB peripherals mask
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableAHB(mask, lp) {                                            \
+  RCC->AHBENR |= (mask);                                                    \
+}
+
+/**
+ * @brief   Disables the clock of one or more peripheral on the AHB bus.
+ *
+ * @param[in] mask      AHB peripherals mask
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableAHB(mask, lp) {                                           \
+  RCC->AHBENR &= ~(mask);                                                   \
+}
+
+/**
+ * @brief   Resets one or more peripheral on the AHB bus.
+ *
+ * @param[in] mask      AHB peripherals mask
+ *
+ * @api
+ */
+#define rccResetAHB(mask) {                                                 \
+  RCC->AHBRSTR |= (mask);                                                   \
+  RCC->AHBRSTR = 0;                                                         \
+}
+/** @} */
+
+/**
+ * @name    ADC peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief   Enables the ADC1/ADC2 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableADC12(lp) rccEnableAHB(RCC_AHBENR_ADC12EN, lp)
+
+/**
+ * @brief   Disables the ADC1/ADC2 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableADC12(lp) rccDisableAHB(RCC_AHBENR_ADC12EN, lp)
+
+/**
+ * @brief   Resets the ADC1/ADC2 peripheral.
+ *
+ * @api
+ */
+#define rccResetADC12() rccResetAHB(RCC_AHBRSTR_ADC12RST)
+
+/**
+ * @brief   Enables the ADC3/ADC4 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableADC34(lp) rccEnableAHB(RCC_AHBENR_ADC34EN, lp)
+
+/**
+ * @brief   Disables the ADC3/ADC4 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableADC34(lp) rccDisableAHB(RCC_AHBENR_ADC34EN, lp)
+
+/**
+ * @brief   Resets the ADC3/ADC4 peripheral.
+ *
+ * @api
+ */
+#define rccResetADC34() rccResetAHB(RCC_AHBRSTR_ADC34RST)
+/** @} */
+
+/**
+ * @name    CAN peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief   Enables the CAN1 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableCAN1(lp) rccEnableAPB1(RCC_APB1ENR_CANEN, lp)
+
+/**
+ * @brief   Disables the CAN1 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableCAN1(lp) rccDisableAPB1(RCC_APB1ENR_CANEN, lp)
+
+/**
+ * @brief   Resets the CAN1 peripheral.
+ *
+ * @api
+ */
+#define rccResetCAN1() rccResetAPB1(RCC_APB1RSTR_CANRST)
+/** @} */
+
+/**
+ * @name    DMA peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief   Enables the DMA1 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDMA1(lp) rccEnableAHB(RCC_AHBENR_DMA1EN, lp)
+
+/**
+ * @brief   Disables the DMA1 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableDMA1(lp) rccDisableAHB(RCC_AHBENR_DMA1EN, lp)
+
+/**
+ * @brief   Resets the DMA1 peripheral.
+ *
+ * @api
+ */
+#define rccResetDMA1() rccResetAHB(RCC_AHBRSTR_DMA1RST)
+
+/**
+ * @brief   Enables the DMA2 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableDMA2(lp) rccEnableAHB(RCC_AHBENR_DMA2EN, lp)
+
+/**
+ * @brief   Disables the DMA2 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableDMA2(lp) rccDisableAHB(RCC_AHBENR_DMA2EN, lp)
+
+/**
+ * @brief   Resets the DMA2 peripheral.
+ *
+ * @api
+ */
+#define rccResetDMA2() rccResetAHB(RCC_AHBRSTR_DMA2RST)
+/** @} */
+
+/**
+ * @name    PWR interface specific RCC operations
+ * @{
+ */
+/**
+ * @brief   Enables the PWR interface clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp)
+
+/**
+ * @brief   Disables PWR interface clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_PWREN, lp)
+
+/**
+ * @brief   Resets the PWR interface.
+ *
+ * @api
+ */
+#define rccResetPWRInterface() rccResetAPB1(RCC_APB1RSTR_PWRRST)
+/** @} */
+
+/**
+ * @name    I2C peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief   Enables the I2C1 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableI2C1(lp) rccEnableAPB1(RCC_APB1ENR_I2C1EN, lp)
+
+/**
+ * @brief   Disables the I2C1 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableI2C1(lp) rccDisableAPB1(RCC_APB1ENR_I2C1EN, lp)
+
+/**
+ * @brief   Resets the I2C1 peripheral.
+ *
+ * @api
+ */
+#define rccResetI2C1() rccResetAPB1(RCC_APB1RSTR_I2C1RST)
+
+/**
+ * @brief   Enables the I2C2 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableI2C2(lp) rccEnableAPB1(RCC_APB1ENR_I2C2EN, lp)
+
+/**
+ * @brief   Disables the I2C2 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableI2C2(lp) rccDisableAPB1(RCC_APB1ENR_I2C2EN, lp)
+
+/**
+ * @brief   Resets the I2C2 peripheral.
+ *
+ * @api
+ */
+#define rccResetI2C2() rccResetAPB1(RCC_APB1RSTR_I2C2RST)
+/** @} */
+
+/**
+ * @name    SPI peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief   Enables the SPI1 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSPI1(lp) rccEnableAPB2(RCC_APB2ENR_SPI1EN, lp)
+
+/**
+ * @brief   Disables the SPI1 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableSPI1(lp) rccDisableAPB2(RCC_APB2ENR_SPI1EN, lp)
+
+/**
+ * @brief   Resets the SPI1 peripheral.
+ *
+ * @api
+ */
+#define rccResetSPI1() rccResetAPB2(RCC_APB2RSTR_SPI1RST)
+
+/**
+ * @brief   Enables the SPI2 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSPI2(lp) rccEnableAPB1(RCC_APB1ENR_SPI2EN, lp)
+
+/**
+ * @brief   Disables the SPI2 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableSPI2(lp) rccDisableAPB1(RCC_APB1ENR_SPI2EN, lp)
+
+/**
+ * @brief   Resets the SPI2 peripheral.
+ *
+ * @api
+ */
+#define rccResetSPI2() rccResetAPB1(RCC_APB1RSTR_SPI2RST)
+
+/**
+ * @brief   Enables the SPI3 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableSPI3(lp) rccEnableAPB1(RCC_APB1ENR_SPI3EN, lp)
+
+/**
+ * @brief   Disables the SPI3 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableSPI3(lp) rccDisableAPB1(RCC_APB1ENR_SPI3EN, lp)
+
+/**
+ * @brief   Resets the SPI3 peripheral.
+ *
+ * @api
+ */
+#define rccResetSPI3() rccResetAPB1(RCC_APB1RSTR_SPI3RST)
+/** @} */
+
+/**
+ * @name    TIM peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief   Enables the TIM1 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM1(lp) rccEnableAPB2(RCC_APB2ENR_TIM1EN, lp)
+
+/**
+ * @brief   Disables the TIM1 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM1(lp) rccDisableAPB2(RCC_APB2ENR_TIM1EN, lp)
+
+/**
+ * @brief   Resets the TIM1 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM1() rccResetAPB2(RCC_APB2RSTR_TIM1RST)
+
+/**
+ * @brief   Enables the TIM2 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM2(lp) rccEnableAPB1(RCC_APB1ENR_TIM2EN, lp)
+
+/**
+ * @brief   Disables the TIM2 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM2(lp) rccDisableAPB1(RCC_APB1ENR_TIM2EN, lp)
+
+/**
+ * @brief   Resets the TIM2 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM2() rccResetAPB1(RCC_APB1RSTR_TIM2RST)
+
+/**
+ * @brief   Enables the TIM3 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM3(lp) rccEnableAPB1(RCC_APB1ENR_TIM3EN, lp)
+
+/**
+ * @brief   Disables the TIM3 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM3(lp) rccDisableAPB1(RCC_APB1ENR_TIM3EN, lp)
+
+/**
+ * @brief   Resets the TIM3 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM3() rccResetAPB1(RCC_APB1RSTR_TIM3RST)
+
+/**
+ * @brief   Enables the TIM4 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM4(lp) rccEnableAPB1(RCC_APB1ENR_TIM4EN, lp)
+
+/**
+ * @brief   Disables the TIM4 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM4(lp) rccDisableAPB1(RCC_APB1ENR_TIM4EN, lp)
+
+/**
+ * @brief   Resets the TIM4 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM4() rccResetAPB1(RCC_APB1RSTR_TIM4RST)
+
+/**
+ * @brief   Enables the TIM6 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM6(lp) rccEnableAPB1(RCC_APB1ENR_TIM6EN, lp)
+
+/**
+ * @brief   Disables the TIM6 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM6(lp) rccDisableAPB1(RCC_APB1ENR_TIM6EN, lp)
+
+/**
+ * @brief   Resets the TIM6 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM6() rccResetAPB1(RCC_APB1RSTR_TIM6RST)
+
+/**
+ * @brief   Enables the TIM7 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM7(lp) rccEnableAPB1(RCC_APB1ENR_TIM7EN, lp)
+
+/**
+ * @brief   Disables the TIM7 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM7(lp) rccDisableAPB1(RCC_APB1ENR_TIM7EN, lp)
+
+/**
+ * @brief   Resets the TIM7 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM7() rccResetAPB1(RCC_APB1RSTR_TIM7RST)
+
+/**
+ * @brief   Enables the TIM8 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableTIM8(lp) rccEnableAPB2(RCC_APB2ENR_TIM8EN, lp)
+
+/**
+ * @brief   Disables the TIM8 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableTIM8(lp) rccDisableAPB2(RCC_APB2ENR_TIM8EN, lp)
+
+/**
+ * @brief   Resets the TIM8 peripheral.
+ *
+ * @api
+ */
+#define rccResetTIM8() rccResetAPB2(RCC_APB2RSTR_TIM8RST)
+/** @} */
+
+/**
+ * @name    USART/UART peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief   Enables the USART1 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSART1(lp) rccEnableAPB2(RCC_APB2ENR_USART1EN, lp)
+
+/**
+ * @brief   Disables the USART1 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUSART1(lp) rccDisableAPB2(RCC_APB2ENR_USART1EN, lp)
+
+/**
+ * @brief   Resets the USART1 peripheral.
+ *
+ * @api
+ */
+#define rccResetUSART1() rccResetAPB2(RCC_APB2RSTR_USART1RST)
+
+/**
+ * @brief   Enables the USART2 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSART2(lp) rccEnableAPB1(RCC_APB1ENR_USART2EN, lp)
+
+/**
+ * @brief   Disables the USART2 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUSART2(lp) rccDisableAPB1(RCC_APB1ENR_USART2EN, lp)
+
+/**
+ * @brief   Resets the USART2 peripheral.
+ *
+ * @api
+ */
+#define rccResetUSART2() rccResetAPB1(RCC_APB1RSTR_USART2RST)
+
+/**
+ * @brief   Enables the USART3 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSART3(lp) rccEnableAPB1(RCC_APB1ENR_USART3EN, lp)
+
+/**
+ * @brief   Disables the USART3 peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUSART3(lp) rccDisableAPB1(RCC_APB1ENR_USART3EN, lp)
+
+/**
+ * @brief   Resets the USART3 peripheral.
+ *
+ * @api
+ */
+#define rccResetUSART3() rccResetAPB1(RCC_APB1RSTR_USART3RST)
+
+/**
+ * @brief   Enables the UART4 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUART4(lp) rccEnableAPB1(RCC_APB1ENR_UART4EN, lp)
+
+/**
+ * @brief   Disables the UART4 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUART4(lp) rccDisableAPB1(RCC_APB1ENR_UART4EN, lp)
+
+/**
+ * @brief   Resets the UART4 peripheral.
+ *
+ * @api
+ */
+#define rccResetUART4() rccResetAPB1(RCC_APB1RSTR_UART4RST)
+
+/**
+ * @brief   Enables the UART5 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUART5(lp) rccEnableAPB1(RCC_APB1ENR_UART5EN, lp)
+
+/**
+ * @brief   Disables the UART5 peripheral clock.
+ * @note    The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUART5(lp) rccDisableAPB1(RCC_APB1ENR_UART5EN, lp)
+
+/**
+ * @brief   Resets the UART5 peripheral.
+ *
+ * @api
+ */
+#define rccResetUART5() rccResetAPB1(RCC_APB1RSTR_UART5RST)
+/** @} */
+
+/**
+ * @name    USB peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief   Enables the USB peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccEnableUSB(lp) rccEnableAPB1(RCC_APB1ENR_USBEN, lp)
+
+/**
+ * @brief   Disables the USB peripheral clock.
+ *
+ * @param[in] lp        low power enable flag
+ *
+ * @api
+ */
+#define rccDisableUSB(lp) rccDisableAPB1(RCC_APB1ENR_USBEN, lp)
+
+/**
+ * @brief   Resets the USB peripheral.
+ *
+ * @api
+ */
+#define rccResetUSB() rccResetAPB1(RCC_APB1RSTR_USBRST)
+/** @} */
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _STM32_RCC_ */
+
+/** @} */
diff --git a/os/hal/ports/STM32/STM32F3xx/stm32_registry.h b/os/hal/ports/STM32/STM32F3xx/stm32_registry.h
new file mode 100644
index 000000000..1a576e5dd
--- /dev/null
+++ b/os/hal/ports/STM32/STM32F3xx/stm32_registry.h
@@ -0,0 +1,1444 @@
+/*
+    ChibiOS/HAL - Copyright (C) 2006-2014 Giovanni Di Sirio
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    STM32F3xx/stm32_registry.h
+ * @brief   STM32F3xx capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef _STM32_REGISTRY_H_
+#define _STM32_REGISTRY_H_
+
+/**
+ * @brief   Sub-family identifier.
+ */
+#if !defined(STM32F3XX) || defined(__DOXYGEN__)
+#define STM32F3XX
+#endif
+
+/*===========================================================================*/
+/* Platform capabilities.                                                    */
+/*===========================================================================*/
+
+/**
+ * @name    STM32F3xx capabilities
+ * @{
+ */
+/*===========================================================================*/
+/* STM32F303xC.                                                              */
+/*===========================================================================*/
+#if defined(STM32F303xC) || defined(__DOXYGEN__)
+/* ADC attributes.*/
+#define STM32_HAS_ADC1                      TRUE
+#define STM32_HAS_ADC2                      TRUE
+#define STM32_HAS_ADC3                      TRUE
+#define STM32_HAS_ADC4                      TRUE
+
+#define STM32_HAS_SDADC1                    FALSE
+#define STM32_HAS_SDADC2                    FALSE
+#define STM32_HAS_SDADC3                    FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1                      TRUE
+#define STM32_HAS_CAN2                      FALSE
+#define STM32_CAN_MAX_FILTERS               14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1                      TRUE
+#define STM32_HAS_DAC2                      TRUE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA                  FALSE
+#define STM32_HAS_DMA1                      TRUE
+#define STM32_HAS_DMA2                      TRUE
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH                       FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_CHANNELS             34
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA                     TRUE
+#define STM32_HAS_GPIOB                     TRUE
+#define STM32_HAS_GPIOC                     TRUE
+#define STM32_HAS_GPIOD                     TRUE
+#define STM32_HAS_GPIOE                     TRUE
+#define STM32_HAS_GPIOF                     TRUE
+#define STM32_HAS_GPIOG                     FALSE
+#define STM32_HAS_GPIOH                     FALSE
+#define STM32_HAS_GPIOI                     FALSE
+#define STM32_GPIO_EN_MASK                  (RCC_AHBENR_GPIOAEN |           \
+                                             RCC_AHBENR_GPIOBEN |           \
+                                             RCC_AHBENR_GPIOCEN |           \
+                                             RCC_AHBENR_GPIODEN |           \
+                                             RCC_AHBENR_GPIOEEN |           \
+                                             RCC_AHBENR_GPIOFEN)
+/* I2C attributes.*/
+#define STM32_HAS_I2C1                      TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2                      TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3                      FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC                       TRUE
+#define STM32_RTC_HAS_SUBSECONDS            TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS      TRUE
+#define STM32_RTC_NUM_ALARMS                1
+#define STM32_RTC_HAS_INTERRUPTS            FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO                      FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1                      TRUE
+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2                      TRUE
+#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3                      TRUE
+#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 1)
+#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 2)
+
+#define STM32_HAS_SPI4                      FALSE
+#define STM32_HAS_SPI5                      FALSE
+#define STM32_HAS_SPI6                      FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS              6
+
+#define STM32_HAS_TIM1                      TRUE
+#define STM32_TIM1_IS_32BITS                FALSE
+#define STM32_TIM1_CHANNELS                 6
+
+#define STM32_HAS_TIM2                      TRUE
+#define STM32_TIM2_IS_32BITS                TRUE
+#define STM32_TIM2_CHANNELS                 4
+
+#define STM32_HAS_TIM3                      TRUE
+#define STM32_TIM3_IS_32BITS                FALSE
+#define STM32_TIM3_CHANNELS                 4
+
+#define STM32_HAS_TIM4                      TRUE
+#define STM32_TIM4_IS_32BITS                FALSE
+#define STM32_TIM4_CHANNELS                 4
+
+#define STM32_HAS_TIM6                      TRUE
+#define STM32_TIM6_IS_32BITS                FALSE
+#define STM32_TIM6_CHANNELS                 0
+
+#define STM32_HAS_TIM7                      TRUE
+#define STM32_TIM7_IS_32BITS                FALSE
+#define STM32_TIM7_CHANNELS                 0
+
+#define STM32_HAS_TIM8                      TRUE
+#define STM32_TIM8_IS_32BITS                FALSE
+#define STM32_TIM8_CHANNELS                 6
+
+#define STM32_HAS_TIM15                     TRUE
+#define STM32_TIM15_IS_32BITS               FALSE
+#define STM32_TIM15_CHANNELS                2
+
+#define STM32_HAS_TIM16                     TRUE
+#define STM32_TIM16_IS_32BITS               FALSE
+#define STM32_TIM16_CHANNELS                2
+
+#define STM32_HAS_TIM17                     TRUE
+#define STM32_TIM17_IS_32BITS               FALSE
+#define STM32_TIM17_CHANNELS                2
+
+#define STM32_HAS_TIM5                      FALSE
+#define STM32_HAS_TIM9                      FALSE
+#define STM32_HAS_TIM10                     FALSE
+#define STM32_HAS_TIM11                     FALSE
+#define STM32_HAS_TIM12                     FALSE
+#define STM32_HAS_TIM13                     FALSE
+#define STM32_HAS_TIM14                     FALSE
+#define STM32_HAS_TIM18                     FALSE
+#define STM32_HAS_TIM19                     FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1                    TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2                    TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3                    TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4                     TRUE
+#define STM32_UART_UART4_RX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 3)
+#define STM32_UART_UART4_TX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 5)
+
+#define STM32_HAS_UART5                     TRUE
+
+#define STM32_HAS_USART6                    FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB                       TRUE
+#define STM32_HAS_OTG1                      FALSE
+#define STM32_HAS_OTG2                      FALSE
+#endif /* defined(STM32F303xC) */
+
+/*===========================================================================*/
+/* STM32F303x8.                                                              */
+/*===========================================================================*/
+#if defined(STM32F303x8)
+/* ADC attributes.*/
+#define STM32_HAS_ADC1                      TRUE
+#define STM32_HAS_ADC2                      TRUE
+#define STM32_HAS_ADC3                      FALSE
+#define STM32_HAS_ADC4                      FALSE
+
+#define STM32_HAS_SDADC1                    FALSE
+#define STM32_HAS_SDADC2                    FALSE
+#define STM32_HAS_SDADC3                    FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1                      TRUE
+#define STM32_HAS_CAN2                      FALSE
+#define STM32_CAN_MAX_FILTERS               14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1                      TRUE
+#define STM32_HAS_DAC2                      TRUE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA                  FALSE
+#define STM32_HAS_DMA1                      TRUE
+#define STM32_HAS_DMA2                      FALSE
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH                       FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_CHANNELS             34
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA                     TRUE
+#define STM32_HAS_GPIOB                     TRUE
+#define STM32_HAS_GPIOC                     TRUE
+#define STM32_HAS_GPIOD                     TRUE
+#define STM32_HAS_GPIOE                     FALSE
+#define STM32_HAS_GPIOF                     TRUE
+#define STM32_HAS_GPIOG                     FALSE
+#define STM32_HAS_GPIOH                     FALSE
+#define STM32_HAS_GPIOI                     FALSE
+#define STM32_GPIO_EN_MASK                  (RCC_AHBENR_GPIOAEN |           \
+                                             RCC_AHBENR_GPIOBEN |           \
+                                             RCC_AHBENR_GPIOCEN |           \
+                                             RCC_AHBENR_GPIODEN |           \
+                                             RCC_AHBENR_GPIOFEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1                      TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2                      FALSE
+#define STM32_HAS_I2C3                      FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC                       TRUE
+#define STM32_RTC_HAS_SUBSECONDS            TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS      TRUE
+#define STM32_RTC_NUM_ALARMS                2
+#define STM32_RTC_HAS_INTERRUPTS            FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO                      FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1                      TRUE
+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2                      FALSE
+#define STM32_HAS_SPI3                      FALSE
+#define STM32_HAS_SPI4                      FALSE
+#define STM32_HAS_SPI5                      FALSE
+#define STM32_HAS_SPI6                      FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS              6
+
+#define STM32_HAS_TIM1                      TRUE
+#define STM32_TIM1_IS_32BITS                FALSE
+#define STM32_TIM1_CHANNELS                 6
+
+#define STM32_HAS_TIM2                      TRUE
+#define STM32_TIM2_IS_32BITS                TRUE
+#define STM32_TIM2_CHANNELS                 4
+
+#define STM32_HAS_TIM3                      TRUE
+#define STM32_TIM3_IS_32BITS                FALSE
+#define STM32_TIM3_CHANNELS                 4
+
+#define STM32_HAS_TIM4                      TRUE
+#define STM32_TIM4_IS_32BITS                FALSE
+#define STM32_TIM4_CHANNELS                 4
+
+#define STM32_HAS_TIM6                      TRUE
+#define STM32_TIM6_IS_32BITS                FALSE
+#define STM32_TIM6_CHANNELS                 0
+
+#define STM32_HAS_TIM7                      TRUE
+#define STM32_TIM7_IS_32BITS                FALSE
+#define STM32_TIM7_CHANNELS                 0
+
+#define STM32_HAS_TIM15                     TRUE
+#define STM32_TIM15_IS_32BITS               FALSE
+#define STM32_TIM15_CHANNELS                2
+
+#define STM32_HAS_TIM16                     TRUE
+#define STM32_TIM16_IS_32BITS               FALSE
+#define STM32_TIM16_CHANNELS                2
+
+#define STM32_HAS_TIM17                     TRUE
+#define STM32_TIM17_IS_32BITS               FALSE
+#define STM32_TIM17_CHANNELS                2
+
+#define STM32_HAS_TIM5                      FALSE
+#define STM32_HAS_TIM8                      FALSE
+#define STM32_HAS_TIM9                      FALSE
+#define STM32_HAS_TIM10                     FALSE
+#define STM32_HAS_TIM11                     FALSE
+#define STM32_HAS_TIM12                     FALSE
+#define STM32_HAS_TIM13                     FALSE
+#define STM32_HAS_TIM14                     FALSE
+#define STM32_HAS_TIM18                     FALSE
+#define STM32_HAS_TIM19                     FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1                    TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2                    TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3                    TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4                     FALSE
+#define STM32_HAS_UART5                     FALSE
+#define STM32_HAS_USART6                    FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB                       FALSE
+#define STM32_HAS_OTG1                      FALSE
+#define STM32_HAS_OTG2                      FALSE
+#endif /* defined(STM32F303x8) */
+
+/*===========================================================================*/
+/* STM32F301x8.                                                              */
+/*===========================================================================*/
+#if defined(STM32F301x8)
+/* ADC attributes.*/
+#define STM32_HAS_ADC1                      TRUE
+#define STM32_HAS_ADC2                      FALSE
+#define STM32_HAS_ADC3                      FALSE
+#define STM32_HAS_ADC4                      FALSE
+
+#define STM32_HAS_SDADC1                    FALSE
+#define STM32_HAS_SDADC2                    FALSE
+#define STM32_HAS_SDADC3                    FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1                      FALSE
+#define STM32_HAS_CAN2                      FALSE
+#define STM32_CAN_MAX_FILTERS               14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1                      TRUE
+#define STM32_HAS_DAC2                      FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA                  FALSE
+#define STM32_HAS_DMA1                      TRUE
+#define STM32_HAS_DMA2                      FALSE
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH                       FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_CHANNELS             33
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA                     TRUE
+#define STM32_HAS_GPIOB                     TRUE
+#define STM32_HAS_GPIOC                     TRUE
+#define STM32_HAS_GPIOD                     TRUE
+#define STM32_HAS_GPIOE                     FALSE
+#define STM32_HAS_GPIOF                     TRUE
+#define STM32_HAS_GPIOG                     FALSE
+#define STM32_HAS_GPIOH                     FALSE
+#define STM32_HAS_GPIOI                     FALSE
+#define STM32_GPIO_EN_MASK                  (RCC_AHBENR_GPIOAEN |           \
+                                             RCC_AHBENR_GPIOBEN |           \
+                                             RCC_AHBENR_GPIOCEN |           \
+                                             RCC_AHBENR_GPIODEN |           \
+                                             RCC_AHBENR_GPIOFEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1                      TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2                      TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3                      TRUE
+#define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 1)
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC                       TRUE
+#define STM32_RTC_HAS_SUBSECONDS            TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS      TRUE
+#define STM32_RTC_NUM_ALARMS                2
+#define STM32_RTC_HAS_INTERRUPTS            FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO                      FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI2                      TRUE
+#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3                      TRUE
+#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI1                      FALSE
+#define STM32_HAS_SPI4                      FALSE
+#define STM32_HAS_SPI5                      FALSE
+#define STM32_HAS_SPI6                      FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS              6
+
+#define STM32_HAS_TIM1                      TRUE
+#define STM32_TIM1_IS_32BITS                FALSE
+#define STM32_TIM1_CHANNELS                 6
+
+#define STM32_HAS_TIM2                      TRUE
+#define STM32_TIM2_IS_32BITS                TRUE
+#define STM32_TIM2_CHANNELS                 4
+
+#define STM32_HAS_TIM6                      TRUE
+#define STM32_TIM6_IS_32BITS                FALSE
+#define STM32_TIM6_CHANNELS                 0
+
+#define STM32_HAS_TIM15                     TRUE
+#define STM32_TIM15_IS_32BITS               FALSE
+#define STM32_TIM15_CHANNELS                2
+
+#define STM32_HAS_TIM16                     TRUE
+#define STM32_TIM16_IS_32BITS               FALSE
+#define STM32_TIM16_CHANNELS                2
+
+#define STM32_HAS_TIM17                     TRUE
+#define STM32_TIM17_IS_32BITS               FALSE
+#define STM32_TIM17_CHANNELS                2
+
+#define STM32_HAS_TIM3                      FALSE
+#define STM32_HAS_TIM4                      FALSE
+#define STM32_HAS_TIM5                      FALSE
+#define STM32_HAS_TIM7                      FALSE
+#define STM32_HAS_TIM8                      FALSE
+#define STM32_HAS_TIM9                      FALSE
+#define STM32_HAS_TIM10                     FALSE
+#define STM32_HAS_TIM11                     FALSE
+#define STM32_HAS_TIM12                     FALSE
+#define STM32_HAS_TIM13                     FALSE
+#define STM32_HAS_TIM14                     FALSE
+#define STM32_HAS_TIM18                     FALSE
+#define STM32_HAS_TIM19                     FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1                    TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2                    TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3                    TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4                     FALSE
+#define STM32_HAS_UART5                     FALSE
+#define STM32_HAS_USART6                    FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB                       FALSE
+#define STM32_HAS_OTG1                      FALSE
+#define STM32_HAS_OTG2                      FALSE
+#endif /* defined(STM32F301x8) */
+
+/*===========================================================================*/
+/* STM32F302x8.                                                              */
+/*===========================================================================*/
+#if defined(STM32F302x8)
+/* ADC attributes.*/
+#define STM32_HAS_ADC1                      TRUE
+#define STM32_HAS_ADC2                      FALSE
+#define STM32_HAS_ADC3                      FALSE
+#define STM32_HAS_ADC4                      FALSE
+
+#define STM32_HAS_SDADC1                    FALSE
+#define STM32_HAS_SDADC2                    FALSE
+#define STM32_HAS_SDADC3                    FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1                      TRUE
+#define STM32_HAS_CAN2                      FALSE
+#define STM32_CAN_MAX_FILTERS               14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1                      TRUE
+#define STM32_HAS_DAC2                      FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA                  FALSE
+#define STM32_HAS_DMA1                      TRUE
+#define STM32_HAS_DMA2                      FALSE
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH                       FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_CHANNELS             33
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA                     TRUE
+#define STM32_HAS_GPIOB                     TRUE
+#define STM32_HAS_GPIOC                     TRUE
+#define STM32_HAS_GPIOD                     TRUE
+#define STM32_HAS_GPIOE                     FALSE
+#define STM32_HAS_GPIOF                     TRUE
+#define STM32_HAS_GPIOG                     FALSE
+#define STM32_HAS_GPIOH                     FALSE
+#define STM32_HAS_GPIOI                     FALSE
+#define STM32_GPIO_EN_MASK                  (RCC_AHBENR_GPIOAEN |           \
+                                             RCC_AHBENR_GPIOBEN |           \
+                                             RCC_AHBENR_GPIOCEN |           \
+                                             RCC_AHBENR_GPIODEN |           \
+                                             RCC_AHBENR_GPIOFEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1                      TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2                      TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3                      TRUE
+#define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 1)
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC                       TRUE
+#define STM32_RTC_HAS_SUBSECONDS            TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS      TRUE
+#define STM32_RTC_NUM_ALARMS                2
+#define STM32_RTC_HAS_INTERRUPTS            FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO                      FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI2                      TRUE
+#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3                      TRUE
+#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI1                      FALSE
+#define STM32_HAS_SPI4                      FALSE
+#define STM32_HAS_SPI5                      FALSE
+#define STM32_HAS_SPI6                      FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS              6
+
+#define STM32_HAS_TIM1                      TRUE
+#define STM32_TIM1_IS_32BITS                FALSE
+#define STM32_TIM1_CHANNELS                 6
+
+#define STM32_HAS_TIM2                      TRUE
+#define STM32_TIM2_IS_32BITS                TRUE
+#define STM32_TIM2_CHANNELS                 4
+
+#define STM32_HAS_TIM6                      TRUE
+#define STM32_TIM6_IS_32BITS                FALSE
+#define STM32_TIM6_CHANNELS                 0
+
+#define STM32_HAS_TIM15                     TRUE
+#define STM32_TIM15_IS_32BITS               FALSE
+#define STM32_TIM15_CHANNELS                2
+
+#define STM32_HAS_TIM16                     TRUE
+#define STM32_TIM16_IS_32BITS               FALSE
+#define STM32_TIM16_CHANNELS                2
+
+#define STM32_HAS_TIM17                     TRUE
+#define STM32_TIM17_IS_32BITS               FALSE
+#define STM32_TIM17_CHANNELS                2
+
+#define STM32_HAS_TIM3                      FALSE
+#define STM32_HAS_TIM4                      FALSE
+#define STM32_HAS_TIM5                      FALSE
+#define STM32_HAS_TIM7                      FALSE
+#define STM32_HAS_TIM8                      FALSE
+#define STM32_HAS_TIM9                      FALSE
+#define STM32_HAS_TIM10                     FALSE
+#define STM32_HAS_TIM11                     FALSE
+#define STM32_HAS_TIM12                     FALSE
+#define STM32_HAS_TIM13                     FALSE
+#define STM32_HAS_TIM14                     FALSE
+#define STM32_HAS_TIM18                     FALSE
+#define STM32_HAS_TIM19                     FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1                    TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2                    TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3                    TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4                     FALSE
+#define STM32_HAS_UART5                     FALSE
+#define STM32_HAS_USART6                    FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB                       TRUE
+#define STM32_HAS_OTG1                      FALSE
+#define STM32_HAS_OTG2                      FALSE
+#endif /* defined(STM32F302x8) */
+
+/*===========================================================================*/
+/* STM32F302xC.                                                              */
+/*===========================================================================*/
+#if defined(STM32F302xC)
+/* ADC attributes.*/
+#define STM32_HAS_ADC1                      TRUE
+#define STM32_HAS_ADC2                      TRUE
+#define STM32_HAS_ADC3                      FALSE
+#define STM32_HAS_ADC4                      FALSE
+
+#define STM32_HAS_SDADC1                    FALSE
+#define STM32_HAS_SDADC2                    FALSE
+#define STM32_HAS_SDADC3                    FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1                      TRUE
+#define STM32_HAS_CAN2                      FALSE
+#define STM32_CAN_MAX_FILTERS               14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1                      TRUE
+#define STM32_HAS_DAC2                      FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA                  FALSE
+#define STM32_HAS_DMA1                      TRUE
+#define STM32_HAS_DMA2                      TRUE
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH                       FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_CHANNELS             34
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA                     TRUE
+#define STM32_HAS_GPIOB                     TRUE
+#define STM32_HAS_GPIOC                     TRUE
+#define STM32_HAS_GPIOD                     TRUE
+#define STM32_HAS_GPIOE                     TRUE
+#define STM32_HAS_GPIOF                     TRUE
+#define STM32_HAS_GPIOG                     FALSE
+#define STM32_HAS_GPIOH                     FALSE
+#define STM32_HAS_GPIOI                     FALSE
+#define STM32_GPIO_EN_MASK                  (RCC_AHBENR_GPIOAEN |           \
+                                             RCC_AHBENR_GPIOBEN |           \
+                                             RCC_AHBENR_GPIOCEN |           \
+                                             RCC_AHBENR_GPIODEN |           \
+                                             RCC_AHBENR_GPIOEEN |           \
+                                             RCC_AHBENR_GPIOFEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1                      FALSE
+
+#define STM32_HAS_I2C2                      TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3                      TRUE
+#define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 1)
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC                       TRUE
+#define STM32_RTC_HAS_SUBSECONDS            TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS      TRUE
+#define STM32_RTC_NUM_ALARMS                2
+#define STM32_RTC_HAS_INTERRUPTS            FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO                      FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1                      TRUE
+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2                      TRUE
+#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3                      TRUE
+#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 1)
+#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 2)
+
+#define STM32_HAS_SPI4                      FALSE
+#define STM32_HAS_SPI5                      FALSE
+#define STM32_HAS_SPI6                      FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS              6
+
+#define STM32_HAS_TIM1                      TRUE
+#define STM32_TIM1_IS_32BITS                FALSE
+#define STM32_TIM1_CHANNELS                 6
+
+#define STM32_HAS_TIM2                      TRUE
+#define STM32_TIM2_IS_32BITS                TRUE
+#define STM32_TIM2_CHANNELS                 4
+
+#define STM32_HAS_TIM3                      TRUE
+#define STM32_TIM3_IS_32BITS                FALSE
+#define STM32_TIM3_CHANNELS                 4
+
+#define STM32_HAS_TIM4                      TRUE
+#define STM32_TIM4_IS_32BITS                FALSE
+#define STM32_TIM4_CHANNELS                 4
+
+#define STM32_HAS_TIM6                      TRUE
+#define STM32_TIM6_IS_32BITS                FALSE
+#define STM32_TIM6_CHANNELS                 0
+
+#define STM32_HAS_TIM15                     TRUE
+#define STM32_TIM15_IS_32BITS               FALSE
+#define STM32_TIM15_CHANNELS                2
+
+#define STM32_HAS_TIM16                     TRUE
+#define STM32_TIM16_IS_32BITS               FALSE
+#define STM32_TIM16_CHANNELS                2
+
+#define STM32_HAS_TIM17                     TRUE
+#define STM32_TIM17_IS_32BITS               FALSE
+#define STM32_TIM17_CHANNELS                2
+
+#define STM32_HAS_TIM5                      FALSE
+#define STM32_HAS_TIM7                      FALSE
+#define STM32_HAS_TIM8                      FALSE
+#define STM32_HAS_TIM9                      FALSE
+#define STM32_HAS_TIM10                     FALSE
+#define STM32_HAS_TIM11                     FALSE
+#define STM32_HAS_TIM12                     FALSE
+#define STM32_HAS_TIM13                     FALSE
+#define STM32_HAS_TIM14                     FALSE
+#define STM32_HAS_TIM18                     FALSE
+#define STM32_HAS_TIM19                     FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1                    TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2                    TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3                    TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4                     TRUE
+#define STM32_UART_UART4_RX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 3)
+#define STM32_UART_UART4_TX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 5)
+
+#define STM32_HAS_UART5                     TRUE
+
+#define STM32_HAS_USART6                    FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB                       TRUE
+#define STM32_HAS_OTG1                      FALSE
+#define STM32_HAS_OTG2                      FALSE
+#endif /* defined(STM32F302xC) */
+
+/*===========================================================================*/
+/* STM32F318x8.                                                              */
+/*===========================================================================*/
+#if defined(STM32F318x8)
+/* ADC attributes.*/
+#define STM32_HAS_ADC1                      TRUE
+#define STM32_HAS_ADC2                      FALSE
+#define STM32_HAS_ADC3                      FALSE
+#define STM32_HAS_ADC4                      FALSE
+
+#define STM32_HAS_SDADC1                    FALSE
+#define STM32_HAS_SDADC2                    FALSE
+#define STM32_HAS_SDADC3                    FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1                      TRUE
+#define STM32_HAS_CAN2                      FALSE
+#define STM32_CAN_MAX_FILTERS               14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1                      TRUE
+#define STM32_HAS_DAC2                      FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA                  FALSE
+#define STM32_HAS_DMA1                      TRUE
+#define STM32_HAS_DMA2                      FALSE
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH                       FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_CHANNELS             33
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA                     TRUE
+#define STM32_HAS_GPIOB                     TRUE
+#define STM32_HAS_GPIOC                     TRUE
+#define STM32_HAS_GPIOD                     FALSE
+#define STM32_HAS_GPIOE                     FALSE
+#define STM32_HAS_GPIOF                     TRUE
+#define STM32_HAS_GPIOG                     FALSE
+#define STM32_HAS_GPIOH                     FALSE
+#define STM32_HAS_GPIOI                     FALSE
+#define STM32_GPIO_EN_MASK                  (RCC_AHBENR_GPIOAEN |           \
+                                             RCC_AHBENR_GPIOBEN |           \
+                                             RCC_AHBENR_GPIOCEN |           \
+                                             RCC_AHBENR_GPIOFEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1                      TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2                      TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3                      TRUE
+#define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 1)
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC                       TRUE
+#define STM32_RTC_HAS_SUBSECONDS            TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS      TRUE
+#define STM32_RTC_NUM_ALARMS                2
+#define STM32_RTC_HAS_INTERRUPTS            FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO                      FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI2                      TRUE
+#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3                      TRUE
+#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI1                      FALSE
+#define STM32_HAS_SPI4                      FALSE
+#define STM32_HAS_SPI5                      FALSE
+#define STM32_HAS_SPI6                      FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS              6
+
+#define STM32_HAS_TIM1                      TRUE
+#define STM32_TIM1_IS_32BITS                FALSE
+#define STM32_TIM1_CHANNELS                 6
+
+#define STM32_HAS_TIM2                      TRUE
+#define STM32_TIM2_IS_32BITS                TRUE
+#define STM32_TIM2_CHANNELS                 4
+
+#define STM32_HAS_TIM6                      TRUE
+#define STM32_TIM6_IS_32BITS                FALSE
+#define STM32_TIM6_CHANNELS                 0
+
+#define STM32_HAS_TIM15                     TRUE
+#define STM32_TIM15_IS_32BITS               FALSE
+#define STM32_TIM15_CHANNELS                2
+
+#define STM32_HAS_TIM16                     TRUE
+#define STM32_TIM16_IS_32BITS               FALSE
+#define STM32_TIM16_CHANNELS                2
+
+#define STM32_HAS_TIM17                     TRUE
+#define STM32_TIM17_IS_32BITS               FALSE
+#define STM32_TIM17_CHANNELS                2
+
+#define STM32_HAS_TIM3                      FALSE
+#define STM32_HAS_TIM4                      FALSE
+#define STM32_HAS_TIM5                      FALSE
+#define STM32_HAS_TIM7                      FALSE
+#define STM32_HAS_TIM8                      FALSE
+#define STM32_HAS_TIM9                      FALSE
+#define STM32_HAS_TIM10                     FALSE
+#define STM32_HAS_TIM11                     FALSE
+#define STM32_HAS_TIM12                     FALSE
+#define STM32_HAS_TIM13                     FALSE
+#define STM32_HAS_TIM14                     FALSE
+#define STM32_HAS_TIM18                     FALSE
+#define STM32_HAS_TIM19                     FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1                    TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2                    TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3                    TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4                     FALSE
+#define STM32_HAS_UART5                     FALSE
+#define STM32_HAS_USART6                    FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB                       TRUE
+#define STM32_HAS_OTG1                      FALSE
+#define STM32_HAS_OTG2                      FALSE
+#endif /* defined(STM32F318x8) */
+
+/*===========================================================================*/
+/* STM32F328x8.                                                              */
+/*===========================================================================*/
+#if defined(STM32F328x8)
+/* ADC attributes.*/
+#define STM32_HAS_ADC1                      TRUE
+#define STM32_HAS_ADC2                      TRUE
+#define STM32_HAS_ADC3                      FALSE
+#define STM32_HAS_ADC4                      FALSE
+
+#define STM32_HAS_SDADC1                    FALSE
+#define STM32_HAS_SDADC2                    FALSE
+#define STM32_HAS_SDADC3                    FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1                      TRUE
+#define STM32_HAS_CAN2                      FALSE
+#define STM32_CAN_MAX_FILTERS               14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1                      TRUE
+#define STM32_HAS_DAC2                      TRUE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA                  FALSE
+#define STM32_HAS_DMA1                      TRUE
+#define STM32_HAS_DMA2                      FALSE
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH                       FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_CHANNELS             33
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA                     TRUE
+#define STM32_HAS_GPIOB                     TRUE
+#define STM32_HAS_GPIOC                     TRUE
+#define STM32_HAS_GPIOD                     TRUE
+#define STM32_HAS_GPIOE                     FALSE
+#define STM32_HAS_GPIOF                     TRUE
+#define STM32_HAS_GPIOG                     FALSE
+#define STM32_HAS_GPIOH                     FALSE
+#define STM32_HAS_GPIOI                     FALSE
+#define STM32_GPIO_EN_MASK                  (RCC_AHBENR_GPIOAEN |           \
+                                             RCC_AHBENR_GPIOBEN |           \
+                                             RCC_AHBENR_GPIOCEN |           \
+                                             RCC_AHBENR_GPIODEN |           \
+                                             RCC_AHBENR_GPIOFEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1                      TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2                      FALSE
+#define STM32_HAS_I2C3                      FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC                       TRUE
+#define STM32_RTC_HAS_SUBSECONDS            TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS      TRUE
+#define STM32_RTC_NUM_ALARMS                2
+#define STM32_RTC_HAS_INTERRUPTS            FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO                      FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1                      TRUE
+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2                      FALSE
+#define STM32_HAS_SPI3                      FALSE
+#define STM32_HAS_SPI4                      FALSE
+#define STM32_HAS_SPI5                      FALSE
+#define STM32_HAS_SPI6                      FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS              6
+
+#define STM32_HAS_TIM1                      TRUE
+#define STM32_TIM1_IS_32BITS                FALSE
+#define STM32_TIM1_CHANNELS                 6
+
+#define STM32_HAS_TIM2                      TRUE
+#define STM32_TIM2_IS_32BITS                TRUE
+#define STM32_TIM2_CHANNELS                 4
+
+#define STM32_HAS_TIM3                      TRUE
+#define STM32_TIM3_IS_32BITS                FALSE
+#define STM32_TIM3_CHANNELS                 4
+
+#define STM32_HAS_TIM6                      TRUE
+#define STM32_TIM6_IS_32BITS                FALSE
+#define STM32_TIM6_CHANNELS                 0
+
+#define STM32_HAS_TIM7                      TRUE
+#define STM32_TIM7_IS_32BITS                FALSE
+#define STM32_TIM7_CHANNELS                 0
+
+#define STM32_HAS_TIM15                     TRUE
+#define STM32_TIM15_IS_32BITS               FALSE
+#define STM32_TIM15_CHANNELS                2
+
+#define STM32_HAS_TIM16                     TRUE
+#define STM32_TIM16_IS_32BITS               FALSE
+#define STM32_TIM16_CHANNELS                2
+
+#define STM32_HAS_TIM17                     TRUE
+#define STM32_TIM17_IS_32BITS               FALSE
+#define STM32_TIM17_CHANNELS                2
+
+#define STM32_HAS_TIM4                      FALSE
+#define STM32_HAS_TIM5                      FALSE
+#define STM32_HAS_TIM8                      FALSE
+#define STM32_HAS_TIM9                      FALSE
+#define STM32_HAS_TIM10                     FALSE
+#define STM32_HAS_TIM11                     FALSE
+#define STM32_HAS_TIM12                     FALSE
+#define STM32_HAS_TIM13                     FALSE
+#define STM32_HAS_TIM14                     FALSE
+#define STM32_HAS_TIM18                     FALSE
+#define STM32_HAS_TIM19                     FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1                    TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2                    TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3                    TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4                     FALSE
+#define STM32_HAS_UART5                     FALSE
+#define STM32_HAS_USART6                    FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB                       FALSE
+#define STM32_HAS_OTG1                      FALSE
+#define STM32_HAS_OTG2                      FALSE
+#endif /* defined(STM32F328x8) */
+
+/*===========================================================================*/
+/* STM32F358xC.                                                              */
+/*===========================================================================*/
+#if defined(STM32F358xC) || defined(__DOXYGEN__)
+/* ADC attributes.*/
+#define STM32_HAS_ADC1                      TRUE
+#define STM32_HAS_ADC2                      TRUE
+#define STM32_HAS_ADC3                      FALSE
+#define STM32_HAS_ADC4                      FALSE
+
+#define STM32_HAS_SDADC1                    FALSE
+#define STM32_HAS_SDADC2                    FALSE
+#define STM32_HAS_SDADC3                    FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1                      TRUE
+#define STM32_HAS_CAN2                      FALSE
+#define STM32_CAN_MAX_FILTERS               14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1                      TRUE
+#define STM32_HAS_DAC2                      FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA                  FALSE
+#define STM32_HAS_DMA1                      TRUE
+#define STM32_HAS_DMA2                      TRUE
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH                       FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_CHANNELS             34
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA                     TRUE
+#define STM32_HAS_GPIOB                     TRUE
+#define STM32_HAS_GPIOC                     TRUE
+#define STM32_HAS_GPIOD                     TRUE
+#define STM32_HAS_GPIOE                     TRUE
+#define STM32_HAS_GPIOF                     TRUE
+#define STM32_HAS_GPIOG                     FALSE
+#define STM32_HAS_GPIOH                     FALSE
+#define STM32_HAS_GPIOI                     FALSE
+#define STM32_GPIO_EN_MASK                  (RCC_AHBENR_GPIOAEN |           \
+                                             RCC_AHBENR_GPIOBEN |           \
+                                             RCC_AHBENR_GPIOCEN |           \
+                                             RCC_AHBENR_GPIODEN |           \
+                                             RCC_AHBENR_GPIOEEN |           \
+                                             RCC_AHBENR_GPIOFEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1                      TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2                      TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3                      FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC                       TRUE
+#define STM32_RTC_HAS_SUBSECONDS            TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS      TRUE
+#define STM32_RTC_NUM_ALARMS                1
+#define STM32_RTC_HAS_INTERRUPTS            FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO                      FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1                      TRUE
+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2                      TRUE
+#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3                      TRUE
+#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 1)
+#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 2)
+
+#define STM32_HAS_SPI4                      FALSE
+#define STM32_HAS_SPI5                      FALSE
+#define STM32_HAS_SPI6                      FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS              6
+
+#define STM32_HAS_TIM1                      TRUE
+#define STM32_TIM1_IS_32BITS                FALSE
+#define STM32_TIM1_CHANNELS                 6
+
+#define STM32_HAS_TIM2                      TRUE
+#define STM32_TIM2_IS_32BITS                TRUE
+#define STM32_TIM2_CHANNELS                 4
+
+#define STM32_HAS_TIM3                      TRUE
+#define STM32_TIM3_IS_32BITS                FALSE
+#define STM32_TIM3_CHANNELS                 4
+
+#define STM32_HAS_TIM4                      TRUE
+#define STM32_TIM4_IS_32BITS                FALSE
+#define STM32_TIM4_CHANNELS                 4
+
+#define STM32_HAS_TIM6                      TRUE
+#define STM32_TIM6_IS_32BITS                FALSE
+#define STM32_TIM6_CHANNELS                 0
+
+#define STM32_HAS_TIM15                     TRUE
+#define STM32_TIM15_IS_32BITS               FALSE
+#define STM32_TIM15_CHANNELS                2
+
+#define STM32_HAS_TIM16                     TRUE
+#define STM32_TIM16_IS_32BITS               FALSE
+#define STM32_TIM16_CHANNELS                2
+
+#define STM32_HAS_TIM17                     TRUE
+#define STM32_TIM17_IS_32BITS               FALSE
+#define STM32_TIM17_CHANNELS                2
+
+#define STM32_HAS_TIM5                      FALSE
+#define STM32_HAS_TIM7                      FALSE
+#define STM32_HAS_TIM8                      FALSE
+#define STM32_HAS_TIM9                      FALSE
+#define STM32_HAS_TIM10                     FALSE
+#define STM32_HAS_TIM11                     FALSE
+#define STM32_HAS_TIM12                     FALSE
+#define STM32_HAS_TIM13                     FALSE
+#define STM32_HAS_TIM14                     FALSE
+#define STM32_HAS_TIM18                     FALSE
+#define STM32_HAS_TIM19                     FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1                    TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2                    TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3                    TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4                     TRUE
+#define STM32_UART_UART4_RX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 3)
+#define STM32_UART_UART4_TX_DMA_STREAM      STM32_DMA_STREAM_ID(2, 5)
+
+#define STM32_HAS_UART5                     TRUE
+
+#define STM32_HAS_USART6                    FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB                       TRUE
+#define STM32_HAS_OTG1                      FALSE
+#define STM32_HAS_OTG2                      FALSE
+#endif /* defined(STM32F358xC) */
+
+
+/*===========================================================================*/
+/* STM32F334xC.                                                              */
+/*===========================================================================*/
+#if defined(STM32F334xC) || defined(__DOXYGEN__)
+/* ADC attributes.*/
+#define STM32_HAS_ADC1                      TRUE
+#define STM32_HAS_ADC2                      TRUE
+#define STM32_HAS_ADC3                      FALSE
+#define STM32_HAS_ADC4                      FALSE
+
+#define STM32_HAS_SDADC1                    FALSE
+#define STM32_HAS_SDADC2                    FALSE
+#define STM32_HAS_SDADC3                    FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1                      TRUE
+#define STM32_HAS_CAN2                      FALSE
+#define STM32_CAN_MAX_FILTERS               14
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC1                      TRUE
+#define STM32_HAS_DAC2                      TRUE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA                  FALSE
+#define STM32_HAS_DMA1                      TRUE
+#define STM32_HAS_DMA2                      FALSE
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH                       FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_CHANNELS             33
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA                     TRUE
+#define STM32_HAS_GPIOB                     TRUE
+#define STM32_HAS_GPIOC                     TRUE
+#define STM32_HAS_GPIOD                     TRUE
+#define STM32_HAS_GPIOE                     FALSE
+#define STM32_HAS_GPIOF                     TRUE
+#define STM32_HAS_GPIOG                     FALSE
+#define STM32_HAS_GPIOH                     FALSE
+#define STM32_HAS_GPIOI                     FALSE
+#define STM32_GPIO_EN_MASK                  (RCC_AHBENR_GPIOAEN |           \
+                                             RCC_AHBENR_GPIOBEN |           \
+                                             RCC_AHBENR_GPIOCEN |           \
+                                             RCC_AHBENR_GPIODEN |           \
+                                             RCC_AHBENR_GPIOFEN)
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1                      TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
+
+#define STM32_HAS_I2C2                      FALSE
+#define STM32_HAS_I2C3                      FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC                       TRUE
+#define STM32_RTC_HAS_SUBSECONDS            TRUE
+#define STM32_RTC_HAS_PERIODIC_WAKEUPS      TRUE
+#define STM32_RTC_NUM_ALARMS                1
+#define STM32_RTC_HAS_INTERRUPTS            FALSE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO                      FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1                      TRUE
+#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2                      FALSE
+#define STM32_HAS_SPI3                      FALSE
+#define STM32_HAS_SPI4                      FALSE
+#define STM32_HAS_SPI5                      FALSE
+#define STM32_HAS_SPI6                      FALSE
+
+/* TIM attributes.*/
+#define STM32_TIM_MAX_CHANNELS              6
+
+#define STM32_HAS_TIM1                      TRUE
+#define STM32_TIM1_IS_32BITS                FALSE
+#define STM32_TIM1_CHANNELS                 6
+
+#define STM32_HAS_TIM2                      TRUE
+#define STM32_TIM2_IS_32BITS                TRUE
+#define STM32_TIM2_CHANNELS                 4
+
+#define STM32_HAS_TIM3                      TRUE
+#define STM32_TIM3_IS_32BITS                FALSE
+#define STM32_TIM3_CHANNELS                 4
+
+#define STM32_HAS_TIM6                      TRUE
+#define STM32_TIM6_IS_32BITS                FALSE
+#define STM32_TIM6_CHANNELS                 0
+
+#define STM32_HAS_TIM7                      TRUE
+#define STM32_TIM7_IS_32BITS                FALSE
+#define STM32_TIM7_CHANNELS                 0
+
+#define STM32_HAS_TIM15                     TRUE
+#define STM32_TIM15_IS_32BITS               FALSE
+#define STM32_TIM15_CHANNELS                2
+
+#define STM32_HAS_TIM16                     TRUE
+#define STM32_TIM16_IS_32BITS               FALSE
+#define STM32_TIM16_CHANNELS                2
+
+#define STM32_HAS_TIM17                     TRUE
+#define STM32_TIM17_IS_32BITS               FALSE
+#define STM32_TIM17_CHANNELS                2
+
+#define STM32_HAS_TIM4                      FALSE
+#define STM32_HAS_TIM5                      FALSE
+#define STM32_HAS_TIM8                      FALSE
+#define STM32_HAS_TIM9                      FALSE
+#define STM32_HAS_TIM10                     FALSE
+#define STM32_HAS_TIM11                     FALSE
+#define STM32_HAS_TIM12                     FALSE
+#define STM32_HAS_TIM13                     FALSE
+#define STM32_HAS_TIM14                     FALSE
+#define STM32_HAS_TIM18                     FALSE
+#define STM32_HAS_TIM19                     FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1                    TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART2                    TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 7)
+
+#define STM32_HAS_USART3                    TRUE
+#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_UART4                     FALSE
+#define STM32_HAS_UART5                     FALSE
+#define STM32_HAS_USART6                    FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB                       FALSE
+#define STM32_HAS_OTG1                      FALSE
+#define STM32_HAS_OTG2                      FALSE
+#endif /* defined(STM32F334xC) */
+
+/** @} */
+
+#endif /* _STM32_REGISTRY_H_ */
+
+/** @} */
diff --git a/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f30x.mk b/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f30x.mk
deleted file mode 100644
index 18df7e0a9..000000000
--- a/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f30x.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# List of the ChibiOS/NIL Cortex-M4 STM32F30x port files.
-PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0.c \
-          $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c \
-          ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore.c \
-          ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore_v7m.c
-          
-PORTASM = $(CHIBIOS)/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v7m.s
-
-PORTINC = ${CHIBIOS}/os/ext/CMSIS/include \
-          ${CHIBIOS}/os/ext/CMSIS/ST \
-          ${CHIBIOS}/os/common/ports/ARMCMx/devices/STM32F30x \
-          ${CHIBIOS}/os/nil/ports/ARMCMx \
-          ${CHIBIOS}/os/nil/ports/ARMCMx/compilers/GCC
-
-PORTLD  = ${CHIBIOS}/os/common/ports/ARMCMx/compilers/GCC/ld
diff --git a/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f3xx.mk b/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f3xx.mk
new file mode 100644
index 000000000..2c02987dc
--- /dev/null
+++ b/os/nil/ports/ARMCMx/compilers/GCC/mk/port_stm32f3xx.mk
@@ -0,0 +1,15 @@
+# List of the ChibiOS/NIL Cortex-M4 STM32F3xx port files.
+PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0.c \
+          $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c \
+          ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore.c \
+          ${CHIBIOS}/os/nil/ports/ARMCMx/nilcore_v7m.c
+          
+PORTASM = $(CHIBIOS)/os/nil/ports/ARMCMx/compilers/GCC/nilcoreasm_v7m.s
+
+PORTINC = ${CHIBIOS}/os/ext/CMSIS/include \
+          ${CHIBIOS}/os/ext/CMSIS/ST \
+          ${CHIBIOS}/os/common/ports/ARMCMx/devices/STM32F3xx \
+          ${CHIBIOS}/os/nil/ports/ARMCMx \
+          ${CHIBIOS}/os/nil/ports/ARMCMx/compilers/GCC
+
+PORTLD  = ${CHIBIOS}/os/common/ports/ARMCMx/compilers/GCC/ld
diff --git a/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f30x.mk b/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f30x.mk
deleted file mode 100644
index e3d87f411..000000000
--- a/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f30x.mk
+++ /dev/null
@@ -1,15 +0,0 @@
-# List of the ChibiOS/RT Cortex-M4 STM32F30x port files.
-PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0.c \
-          $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c \
-          ${CHIBIOS}/os/rt/ports/ARMCMx/chcore.c \
-          ${CHIBIOS}/os/rt/ports/ARMCMx/chcore_v7m.c
-          
-PORTASM = $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.s
-
-PORTINC = ${CHIBIOS}/os/ext/CMSIS/include \
-          ${CHIBIOS}/os/ext/CMSIS/ST \
-          ${CHIBIOS}/os/common/ports/ARMCMx/devices/STM32F30x \
-          ${CHIBIOS}/os/rt/ports/ARMCMx \
-          ${CHIBIOS}/os/rt/ports/ARMCMx/compilers/GCC
-
-PORTLD  = ${CHIBIOS}/os/common/ports/ARMCMx/compilers/GCC/ld
diff --git a/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f3xx.mk b/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f3xx.mk
new file mode 100644
index 000000000..7df6d2c06
--- /dev/null
+++ b/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f3xx.mk
@@ -0,0 +1,15 @@
+# List of the ChibiOS/RT Cortex-M4 STM32F3xx port files.
+PORTSRC = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/crt0.c \
+          $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/vectors.c \
+          ${CHIBIOS}/os/rt/ports/ARMCMx/chcore.c \
+          ${CHIBIOS}/os/rt/ports/ARMCMx/chcore_v7m.c
+          
+PORTASM = $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/chcoreasm_v7m.s
+
+PORTINC = ${CHIBIOS}/os/ext/CMSIS/include \
+          ${CHIBIOS}/os/ext/CMSIS/ST \
+          ${CHIBIOS}/os/common/ports/ARMCMx/devices/STM32F3xx \
+          ${CHIBIOS}/os/rt/ports/ARMCMx \
+          ${CHIBIOS}/os/rt/ports/ARMCMx/compilers/GCC
+
+PORTLD  = ${CHIBIOS}/os/common/ports/ARMCMx/compilers/GCC/ld
diff --git a/testhal/STM32/STM32F30x/ADC/Makefile b/testhal/STM32/STM32F30x/ADC/Makefile
index 41542fcb2..5adcdade8 100644
--- a/testhal/STM32/STM32F30x/ADC/Makefile
+++ b/testhal/STM32/STM32F30x/ADC/Makefile
@@ -83,10 +83,10 @@ PROJECT = ch
 CHIBIOS = ../../../..
 include $(CHIBIOS)/os/hal/hal.mk
 include $(CHIBIOS)/os/hal/boards/ST_STM32F3_DISCOVERY/board.mk
-include $(CHIBIOS)/os/hal/ports/STM32/STM32F30x/platform.mk
+include $(CHIBIOS)/os/hal/ports/STM32/STM32F3xx/platform.mk
 include $(CHIBIOS)/os/hal/osal/rt/osal.mk
 include $(CHIBIOS)/os/rt/rt.mk
-include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f30x.mk
+include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f3xx.mk
 #include $(CHIBIOS)/test/rt/test.mk
 
 # Define linker script file here
diff --git a/testhal/STM32/STM32F30x/ADC/mcuconf.h b/testhal/STM32/STM32F30x/ADC/mcuconf.h
index 7838058a0..663294258 100644
--- a/testhal/STM32/STM32F30x/ADC/mcuconf.h
+++ b/testhal/STM32/STM32F30x/ADC/mcuconf.h
@@ -15,7 +15,7 @@
 */
 
 /*
- * STM32F30x drivers configuration.
+ * STM32F3xx drivers configuration.
  * The following settings override the default settings present in
  * the various device driver implementation headers.
  * Note that the settings for each driver only have effect if the whole
@@ -28,7 +28,7 @@
  * 0...3        Lowest...Highest.
  */
 
-#define STM32F30x_MCUCONF
+#define STM32F3xx_MCUCONF
 
 /*
  * HAL driver system settings.
diff --git a/testhal/STM32/STM32F30x/ADC_DUAL/Makefile b/testhal/STM32/STM32F30x/ADC_DUAL/Makefile
index 41542fcb2..5adcdade8 100644
--- a/testhal/STM32/STM32F30x/ADC_DUAL/Makefile
+++ b/testhal/STM32/STM32F30x/ADC_DUAL/Makefile
@@ -83,10 +83,10 @@ PROJECT = ch
 CHIBIOS = ../../../..
 include $(CHIBIOS)/os/hal/hal.mk
 include $(CHIBIOS)/os/hal/boards/ST_STM32F3_DISCOVERY/board.mk
-include $(CHIBIOS)/os/hal/ports/STM32/STM32F30x/platform.mk
+include $(CHIBIOS)/os/hal/ports/STM32/STM32F3xx/platform.mk
 include $(CHIBIOS)/os/hal/osal/rt/osal.mk
 include $(CHIBIOS)/os/rt/rt.mk
-include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f30x.mk
+include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f3xx.mk
 #include $(CHIBIOS)/test/rt/test.mk
 
 # Define linker script file here
diff --git a/testhal/STM32/STM32F30x/ADC_DUAL/mcuconf.h b/testhal/STM32/STM32F30x/ADC_DUAL/mcuconf.h
index 3468f7e92..4256fca85 100644
--- a/testhal/STM32/STM32F30x/ADC_DUAL/mcuconf.h
+++ b/testhal/STM32/STM32F30x/ADC_DUAL/mcuconf.h
@@ -15,7 +15,7 @@
 */
 
 /*
- * STM32F30x drivers configuration.
+ * STM32F3xx drivers configuration.
  * The following settings override the default settings present in
  * the various device driver implementation headers.
  * Note that the settings for each driver only have effect if the whole
@@ -28,7 +28,7 @@
  * 0...3        Lowest...Highest.
  */
 
-#define STM32F30x_MCUCONF
+#define STM32F3xx_MCUCONF
 
 /*
  * HAL driver system settings.
diff --git a/testhal/STM32/STM32F30x/CAN/Makefile b/testhal/STM32/STM32F30x/CAN/Makefile
index 41542fcb2..5adcdade8 100644
--- a/testhal/STM32/STM32F30x/CAN/Makefile
+++ b/testhal/STM32/STM32F30x/CAN/Makefile
@@ -83,10 +83,10 @@ PROJECT = ch
 CHIBIOS = ../../../..
 include $(CHIBIOS)/os/hal/hal.mk
 include $(CHIBIOS)/os/hal/boards/ST_STM32F3_DISCOVERY/board.mk
-include $(CHIBIOS)/os/hal/ports/STM32/STM32F30x/platform.mk
+include $(CHIBIOS)/os/hal/ports/STM32/STM32F3xx/platform.mk
 include $(CHIBIOS)/os/hal/osal/rt/osal.mk
 include $(CHIBIOS)/os/rt/rt.mk
-include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f30x.mk
+include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f3xx.mk
 #include $(CHIBIOS)/test/rt/test.mk
 
 # Define linker script file here
diff --git a/testhal/STM32/STM32F30x/CAN/mcuconf.h b/testhal/STM32/STM32F30x/CAN/mcuconf.h
index 86e830fe2..f5175fe03 100644
--- a/testhal/STM32/STM32F30x/CAN/mcuconf.h
+++ b/testhal/STM32/STM32F30x/CAN/mcuconf.h
@@ -15,7 +15,7 @@
 */
 
 /*
- * STM32F30x drivers configuration.
+ * STM32F3xx drivers configuration.
  * The following settings override the default settings present in
  * the various device driver implementation headers.
  * Note that the settings for each driver only have effect if the whole
@@ -28,7 +28,7 @@
  * 0...3        Lowest...Highest.
  */
 
-#define STM32F30x_MCUCONF
+#define STM32F3xx_MCUCONF
 
 /*
  * HAL driver system settings.
diff --git a/testhal/STM32/STM32F30x/EXT/Makefile b/testhal/STM32/STM32F30x/EXT/Makefile
index 41542fcb2..5adcdade8 100644
--- a/testhal/STM32/STM32F30x/EXT/Makefile
+++ b/testhal/STM32/STM32F30x/EXT/Makefile
@@ -83,10 +83,10 @@ PROJECT = ch
 CHIBIOS = ../../../..
 include $(CHIBIOS)/os/hal/hal.mk
 include $(CHIBIOS)/os/hal/boards/ST_STM32F3_DISCOVERY/board.mk
-include $(CHIBIOS)/os/hal/ports/STM32/STM32F30x/platform.mk
+include $(CHIBIOS)/os/hal/ports/STM32/STM32F3xx/platform.mk
 include $(CHIBIOS)/os/hal/osal/rt/osal.mk
 include $(CHIBIOS)/os/rt/rt.mk
-include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f30x.mk
+include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f3xx.mk
 #include $(CHIBIOS)/test/rt/test.mk
 
 # Define linker script file here
diff --git a/testhal/STM32/STM32F30x/EXT/mcuconf.h b/testhal/STM32/STM32F30x/EXT/mcuconf.h
index abb99ae10..01e6670a9 100644
--- a/testhal/STM32/STM32F30x/EXT/mcuconf.h
+++ b/testhal/STM32/STM32F30x/EXT/mcuconf.h
@@ -15,7 +15,7 @@
 */
 
 /*
- * STM32F30x drivers configuration.
+ * STM32F3xx drivers configuration.
  * The following settings override the default settings present in
  * the various device driver implementation headers.
  * Note that the settings for each driver only have effect if the whole
@@ -28,7 +28,7 @@
  * 0...3        Lowest...Highest.
  */
 
-#define STM32F30x_MCUCONF
+#define STM32F3xx_MCUCONF
 
 /*
  * HAL driver system settings.
diff --git a/testhal/STM32/STM32F30x/IRQ_STORM/Makefile b/testhal/STM32/STM32F30x/IRQ_STORM/Makefile
index 41542fcb2..5adcdade8 100644
--- a/testhal/STM32/STM32F30x/IRQ_STORM/Makefile
+++ b/testhal/STM32/STM32F30x/IRQ_STORM/Makefile
@@ -83,10 +83,10 @@ PROJECT = ch
 CHIBIOS = ../../../..
 include $(CHIBIOS)/os/hal/hal.mk
 include $(CHIBIOS)/os/hal/boards/ST_STM32F3_DISCOVERY/board.mk
-include $(CHIBIOS)/os/hal/ports/STM32/STM32F30x/platform.mk
+include $(CHIBIOS)/os/hal/ports/STM32/STM32F3xx/platform.mk
 include $(CHIBIOS)/os/hal/osal/rt/osal.mk
 include $(CHIBIOS)/os/rt/rt.mk
-include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f30x.mk
+include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f3xx.mk
 #include $(CHIBIOS)/test/rt/test.mk
 
 # Define linker script file here
diff --git a/testhal/STM32/STM32F30x/IRQ_STORM/mcuconf.h b/testhal/STM32/STM32F30x/IRQ_STORM/mcuconf.h
index 082f71c8f..3aa32b115 100644
--- a/testhal/STM32/STM32F30x/IRQ_STORM/mcuconf.h
+++ b/testhal/STM32/STM32F30x/IRQ_STORM/mcuconf.h
@@ -15,7 +15,7 @@
 */
 
 /*
- * STM32F30x drivers configuration.
+ * STM32F3xx drivers configuration.
  * The following settings override the default settings present in
  * the various device driver implementation headers.
  * Note that the settings for each driver only have effect if the whole
@@ -28,7 +28,7 @@
  * 0...3        Lowest...Highest.
  */
 
-#define STM32F30x_MCUCONF
+#define STM32F3xx_MCUCONF
 
 /*
  * HAL driver system settings.
diff --git a/testhal/STM32/STM32F30x/PWM-ICU/Makefile b/testhal/STM32/STM32F30x/PWM-ICU/Makefile
index 41542fcb2..5adcdade8 100644
--- a/testhal/STM32/STM32F30x/PWM-ICU/Makefile
+++ b/testhal/STM32/STM32F30x/PWM-ICU/Makefile
@@ -83,10 +83,10 @@ PROJECT = ch
 CHIBIOS = ../../../..
 include $(CHIBIOS)/os/hal/hal.mk
 include $(CHIBIOS)/os/hal/boards/ST_STM32F3_DISCOVERY/board.mk
-include $(CHIBIOS)/os/hal/ports/STM32/STM32F30x/platform.mk
+include $(CHIBIOS)/os/hal/ports/STM32/STM32F3xx/platform.mk
 include $(CHIBIOS)/os/hal/osal/rt/osal.mk
 include $(CHIBIOS)/os/rt/rt.mk
-include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f30x.mk
+include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f3xx.mk
 #include $(CHIBIOS)/test/rt/test.mk
 
 # Define linker script file here
diff --git a/testhal/STM32/STM32F30x/PWM-ICU/mcuconf.h b/testhal/STM32/STM32F30x/PWM-ICU/mcuconf.h
index bb59d7e27..626449cd5 100644
--- a/testhal/STM32/STM32F30x/PWM-ICU/mcuconf.h
+++ b/testhal/STM32/STM32F30x/PWM-ICU/mcuconf.h
@@ -15,7 +15,7 @@
 */
 
 /*
- * STM32F30x drivers configuration.
+ * STM32F3xx drivers configuration.
  * The following settings override the default settings present in
  * the various device driver implementation headers.
  * Note that the settings for each driver only have effect if the whole
@@ -28,7 +28,7 @@
  * 0...3        Lowest...Highest.
  */
 
-#define STM32F30x_MCUCONF
+#define STM32F3xx_MCUCONF
 
 /*
  * HAL driver system settings.
diff --git a/testhal/STM32/STM32F30x/SPI/Makefile b/testhal/STM32/STM32F30x/SPI/Makefile
index 41542fcb2..5adcdade8 100644
--- a/testhal/STM32/STM32F30x/SPI/Makefile
+++ b/testhal/STM32/STM32F30x/SPI/Makefile
@@ -83,10 +83,10 @@ PROJECT = ch
 CHIBIOS = ../../../..
 include $(CHIBIOS)/os/hal/hal.mk
 include $(CHIBIOS)/os/hal/boards/ST_STM32F3_DISCOVERY/board.mk
-include $(CHIBIOS)/os/hal/ports/STM32/STM32F30x/platform.mk
+include $(CHIBIOS)/os/hal/ports/STM32/STM32F3xx/platform.mk
 include $(CHIBIOS)/os/hal/osal/rt/osal.mk
 include $(CHIBIOS)/os/rt/rt.mk
-include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f30x.mk
+include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f3xx.mk
 #include $(CHIBIOS)/test/rt/test.mk
 
 # Define linker script file here
diff --git a/testhal/STM32/STM32F30x/SPI/mcuconf.h b/testhal/STM32/STM32F30x/SPI/mcuconf.h
index 8ba3d4ea8..281dd7706 100644
--- a/testhal/STM32/STM32F30x/SPI/mcuconf.h
+++ b/testhal/STM32/STM32F30x/SPI/mcuconf.h
@@ -15,7 +15,7 @@
 */
 
 /*
- * STM32F30x drivers configuration.
+ * STM32F3xx drivers configuration.
  * The following settings override the default settings present in
  * the various device driver implementation headers.
  * Note that the settings for each driver only have effect if the whole
@@ -28,7 +28,7 @@
  * 0...3        Lowest...Highest.
  */
 
-#define STM32F30x_MCUCONF
+#define STM32F3xx_MCUCONF
 
 /*
  * HAL driver system settings.
diff --git a/testhal/STM32/STM32F30x/UART/Makefile b/testhal/STM32/STM32F30x/UART/Makefile
index 41542fcb2..5adcdade8 100644
--- a/testhal/STM32/STM32F30x/UART/Makefile
+++ b/testhal/STM32/STM32F30x/UART/Makefile
@@ -83,10 +83,10 @@ PROJECT = ch
 CHIBIOS = ../../../..
 include $(CHIBIOS)/os/hal/hal.mk
 include $(CHIBIOS)/os/hal/boards/ST_STM32F3_DISCOVERY/board.mk
-include $(CHIBIOS)/os/hal/ports/STM32/STM32F30x/platform.mk
+include $(CHIBIOS)/os/hal/ports/STM32/STM32F3xx/platform.mk
 include $(CHIBIOS)/os/hal/osal/rt/osal.mk
 include $(CHIBIOS)/os/rt/rt.mk
-include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f30x.mk
+include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f3xx.mk
 #include $(CHIBIOS)/test/rt/test.mk
 
 # Define linker script file here
diff --git a/testhal/STM32/STM32F30x/UART/mcuconf.h b/testhal/STM32/STM32F30x/UART/mcuconf.h
index f3ebfcc2a..650d45ce4 100644
--- a/testhal/STM32/STM32F30x/UART/mcuconf.h
+++ b/testhal/STM32/STM32F30x/UART/mcuconf.h
@@ -15,7 +15,7 @@
 */
 
 /*
- * STM32F30x drivers configuration.
+ * STM32F3xx drivers configuration.
  * The following settings override the default settings present in
  * the various device driver implementation headers.
  * Note that the settings for each driver only have effect if the whole
@@ -28,7 +28,7 @@
  * 0...3        Lowest...Highest.
  */
 
-#define STM32F30x_MCUCONF
+#define STM32F3xx_MCUCONF
 
 /*
  * HAL driver system settings.
diff --git a/testhal/STM32/STM32F30x/USB_CDC/Makefile b/testhal/STM32/STM32F30x/USB_CDC/Makefile
index dc7053c2f..4028a4949 100644
--- a/testhal/STM32/STM32F30x/USB_CDC/Makefile
+++ b/testhal/STM32/STM32F30x/USB_CDC/Makefile
@@ -83,10 +83,10 @@ PROJECT = ch
 CHIBIOS = ../../../..
 include $(CHIBIOS)/os/hal/hal.mk
 include $(CHIBIOS)/os/hal/boards/ST_STM32F3_DISCOVERY/board.mk
-include $(CHIBIOS)/os/hal/ports/STM32/STM32F30x/platform.mk
+include $(CHIBIOS)/os/hal/ports/STM32/STM32F3xx/platform.mk
 include $(CHIBIOS)/os/hal/osal/rt/osal.mk
 include $(CHIBIOS)/os/rt/rt.mk
-include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f30x.mk
+include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f3xx.mk
 include $(CHIBIOS)/test/rt/test.mk
 
 # Define linker script file here
diff --git a/testhal/STM32/STM32F30x/USB_CDC/mcuconf.h b/testhal/STM32/STM32F30x/USB_CDC/mcuconf.h
index 57f596299..08038a3fe 100644
--- a/testhal/STM32/STM32F30x/USB_CDC/mcuconf.h
+++ b/testhal/STM32/STM32F30x/USB_CDC/mcuconf.h
@@ -15,7 +15,7 @@
 */
 
 /*
- * STM32F30x drivers configuration.
+ * STM32F3xx drivers configuration.
  * The following settings override the default settings present in
  * the various device driver implementation headers.
  * Note that the settings for each driver only have effect if the whole
@@ -28,7 +28,7 @@
  * 0...3        Lowest...Highest.
  */
 
-#define STM32F30x_MCUCONF
+#define STM32F3xx_MCUCONF
 
 /*
  * HAL driver system settings.
diff --git a/testhal/STM32/STM32F37x/ADC/Makefile b/testhal/STM32/STM32F37x/ADC/Makefile
index c8842b0e0..81ea22dcc 100644
--- a/testhal/STM32/STM32F37x/ADC/Makefile
+++ b/testhal/STM32/STM32F37x/ADC/Makefile
@@ -86,7 +86,7 @@ include $(CHIBIOS)/os/hal/boards/ST_STM32373C_EVAL/board.mk
 include $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/platform.mk
 include $(CHIBIOS)/os/hal/osal/rt/osal.mk
 include $(CHIBIOS)/os/rt/rt.mk
-include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f37x.mk
+include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f3xx.mk
 include $(CHIBIOS)/test/rt/test.mk
 
 # Define linker script file here
diff --git a/testhal/STM32/STM32F37x/CAN/Makefile b/testhal/STM32/STM32F37x/CAN/Makefile
index c8842b0e0..81ea22dcc 100644
--- a/testhal/STM32/STM32F37x/CAN/Makefile
+++ b/testhal/STM32/STM32F37x/CAN/Makefile
@@ -86,7 +86,7 @@ include $(CHIBIOS)/os/hal/boards/ST_STM32373C_EVAL/board.mk
 include $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/platform.mk
 include $(CHIBIOS)/os/hal/osal/rt/osal.mk
 include $(CHIBIOS)/os/rt/rt.mk
-include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f37x.mk
+include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f3xx.mk
 include $(CHIBIOS)/test/rt/test.mk
 
 # Define linker script file here
diff --git a/testhal/STM32/STM32F37x/EXT/Makefile b/testhal/STM32/STM32F37x/EXT/Makefile
index c8842b0e0..81ea22dcc 100644
--- a/testhal/STM32/STM32F37x/EXT/Makefile
+++ b/testhal/STM32/STM32F37x/EXT/Makefile
@@ -86,7 +86,7 @@ include $(CHIBIOS)/os/hal/boards/ST_STM32373C_EVAL/board.mk
 include $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/platform.mk
 include $(CHIBIOS)/os/hal/osal/rt/osal.mk
 include $(CHIBIOS)/os/rt/rt.mk
-include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f37x.mk
+include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f3xx.mk
 include $(CHIBIOS)/test/rt/test.mk
 
 # Define linker script file here
diff --git a/testhal/STM32/STM32F37x/I2C/Makefile b/testhal/STM32/STM32F37x/I2C/Makefile
index c8842b0e0..81ea22dcc 100644
--- a/testhal/STM32/STM32F37x/I2C/Makefile
+++ b/testhal/STM32/STM32F37x/I2C/Makefile
@@ -86,7 +86,7 @@ include $(CHIBIOS)/os/hal/boards/ST_STM32373C_EVAL/board.mk
 include $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/platform.mk
 include $(CHIBIOS)/os/hal/osal/rt/osal.mk
 include $(CHIBIOS)/os/rt/rt.mk
-include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f37x.mk
+include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f3xx.mk
 include $(CHIBIOS)/test/rt/test.mk
 
 # Define linker script file here
diff --git a/testhal/STM32/STM32F37x/IRQ_STORM/Makefile b/testhal/STM32/STM32F37x/IRQ_STORM/Makefile
index c8842b0e0..81ea22dcc 100644
--- a/testhal/STM32/STM32F37x/IRQ_STORM/Makefile
+++ b/testhal/STM32/STM32F37x/IRQ_STORM/Makefile
@@ -86,7 +86,7 @@ include $(CHIBIOS)/os/hal/boards/ST_STM32373C_EVAL/board.mk
 include $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/platform.mk
 include $(CHIBIOS)/os/hal/osal/rt/osal.mk
 include $(CHIBIOS)/os/rt/rt.mk
-include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f37x.mk
+include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f3xx.mk
 include $(CHIBIOS)/test/rt/test.mk
 
 # Define linker script file here
diff --git a/testhal/STM32/STM32F37x/PWM-ICU/Makefile b/testhal/STM32/STM32F37x/PWM-ICU/Makefile
index c8842b0e0..81ea22dcc 100644
--- a/testhal/STM32/STM32F37x/PWM-ICU/Makefile
+++ b/testhal/STM32/STM32F37x/PWM-ICU/Makefile
@@ -86,7 +86,7 @@ include $(CHIBIOS)/os/hal/boards/ST_STM32373C_EVAL/board.mk
 include $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/platform.mk
 include $(CHIBIOS)/os/hal/osal/rt/osal.mk
 include $(CHIBIOS)/os/rt/rt.mk
-include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f37x.mk
+include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f3xx.mk
 include $(CHIBIOS)/test/rt/test.mk
 
 # Define linker script file here
diff --git a/testhal/STM32/STM32F37x/SDADC/Makefile b/testhal/STM32/STM32F37x/SDADC/Makefile
index c8842b0e0..81ea22dcc 100644
--- a/testhal/STM32/STM32F37x/SDADC/Makefile
+++ b/testhal/STM32/STM32F37x/SDADC/Makefile
@@ -86,7 +86,7 @@ include $(CHIBIOS)/os/hal/boards/ST_STM32373C_EVAL/board.mk
 include $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/platform.mk
 include $(CHIBIOS)/os/hal/osal/rt/osal.mk
 include $(CHIBIOS)/os/rt/rt.mk
-include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f37x.mk
+include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f3xx.mk
 include $(CHIBIOS)/test/rt/test.mk
 
 # Define linker script file here
diff --git a/testhal/STM32/STM32F37x/SPI/Makefile b/testhal/STM32/STM32F37x/SPI/Makefile
index c8842b0e0..81ea22dcc 100644
--- a/testhal/STM32/STM32F37x/SPI/Makefile
+++ b/testhal/STM32/STM32F37x/SPI/Makefile
@@ -86,7 +86,7 @@ include $(CHIBIOS)/os/hal/boards/ST_STM32373C_EVAL/board.mk
 include $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/platform.mk
 include $(CHIBIOS)/os/hal/osal/rt/osal.mk
 include $(CHIBIOS)/os/rt/rt.mk
-include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f37x.mk
+include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f3xx.mk
 include $(CHIBIOS)/test/rt/test.mk
 
 # Define linker script file here
diff --git a/testhal/STM32/STM32F37x/UART/Makefile b/testhal/STM32/STM32F37x/UART/Makefile
index c8842b0e0..81ea22dcc 100644
--- a/testhal/STM32/STM32F37x/UART/Makefile
+++ b/testhal/STM32/STM32F37x/UART/Makefile
@@ -86,7 +86,7 @@ include $(CHIBIOS)/os/hal/boards/ST_STM32373C_EVAL/board.mk
 include $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/platform.mk
 include $(CHIBIOS)/os/hal/osal/rt/osal.mk
 include $(CHIBIOS)/os/rt/rt.mk
-include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f37x.mk
+include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f3xx.mk
 include $(CHIBIOS)/test/rt/test.mk
 
 # Define linker script file here
diff --git a/testhal/STM32/STM32F37x/USB_CDC/Makefile b/testhal/STM32/STM32F37x/USB_CDC/Makefile
index 14fadc572..537b6fa59 100644
--- a/testhal/STM32/STM32F37x/USB_CDC/Makefile
+++ b/testhal/STM32/STM32F37x/USB_CDC/Makefile
@@ -86,7 +86,7 @@ include $(CHIBIOS)/os/hal/boards/ST_STM32373C_EVAL/board.mk
 include $(CHIBIOS)/os/hal/ports/STM32/STM32F37x/platform.mk
 include $(CHIBIOS)/os/hal/osal/rt/osal.mk
 include $(CHIBIOS)/os/rt/rt.mk
-include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f37x.mk
+include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_stm32f3xx.mk
 include $(CHIBIOS)/test/rt/test.mk
 
 # Define linker script file here
-- 
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