From 6ee04cf23282fff92b088ac6f408e5233eb3aa75 Mon Sep 17 00:00:00 2001 From: barthess Date: Fri, 5 Aug 2011 17:24:23 +0000 Subject: I2C. Added template of synchronouse deriver. It does not work for a moment. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/branches/i2c_dev@3190 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/include/i2c.h | 1 + os/hal/platforms/STM32/i2c_lld.c | 242 +++++++++++++++++++++++++++++++++++---- os/hal/platforms/STM32/i2c_lld.h | 19 ++- os/hal/src/i2c.c | 8 ++ testhal/STM32/I2C/chconf.h | 2 +- testhal/STM32/I2C/halconf.h | 9 +- testhal/STM32/I2C/i2c_pns.c | 8 +- testhal/STM32/I2C/lis3.c | 91 +++------------ testhal/STM32/I2C/main.c | 4 +- testhal/STM32/I2C/max1236.c | 31 ++--- testhal/STM32/I2C/mcuconf.h | 4 +- testhal/STM32/I2C/tmp75.c | 8 +- 12 files changed, 291 insertions(+), 136 deletions(-) diff --git a/os/hal/include/i2c.h b/os/hal/include/i2c.h index 1ff50f471..acf09ec9c 100644 --- a/os/hal/include/i2c.h +++ b/os/hal/include/i2c.h @@ -270,6 +270,7 @@ extern "C" { void i2cAcquireBus(I2CDriver *i2cp); void i2cReleaseBus(I2CDriver *i2cp); #endif /* I2C_USE_MUTUAL_EXCLUSION */ + #ifdef __cplusplus } #endif diff --git a/os/hal/platforms/STM32/i2c_lld.c b/os/hal/platforms/STM32/i2c_lld.c index 033077f2c..a93e2f0a1 100644 --- a/os/hal/platforms/STM32/i2c_lld.c +++ b/os/hal/platforms/STM32/i2c_lld.c @@ -29,7 +29,7 @@ /* TODO: may be? move this defines in i2c_lld.h and mcuconf.h */ #define I2C_STOP_GPT_TIMEOUT 50 /* waiting timer value */ #define I2C_START_GPT_TIMEOUT 50 /* waiting timer value */ -#define I2C_POLLING_TIMEOUT 0xFFFF /* timeout for syncronouse driver */ +#define I2C_POLLING_TIMEOUT 0xFFFF /*===========================================================================*/ /* Driver exported variables. */ @@ -58,15 +58,16 @@ static volatile uint16_t dbgCR2 = 0; #endif /* CH_DBG_ENABLE_ASSERTS */ /* defines for convenience purpose */ +#if I2C_SUPPORTS_CALLBACKS #define txBuffp (i2cp->txbuff_p) #define rxBuffp (i2cp->rxbuff_p) +#endif /* I2C_SUPPORTS_CALLBACKS */ /*===========================================================================*/ /* Driver local functions. */ /*===========================================================================*/ - -#if STM32_I2C_I2C1_USE_POLLING_WAIT -#else +#if I2C_SUPPORTS_CALLBACKS +#if !(STM32_I2C_I2C1_USE_POLLING_WAIT) /* I2C1 GPT callback. */ static void i2c1gptcb(GPTDriver *gptp) { (void)gptp; @@ -100,8 +101,7 @@ static const GPTConfig i2c1gptcfg = { }; #endif /* STM32_I2C_I2C1_USE_POLLING_WAIT */ -#if STM32_I2C_I2C2_USE_POLLING_WAIT -#else +#if !(STM32_I2C_I2C2_USE_POLLING_WAIT) /* I2C2 GPT callback. */ static void i2c2gptcb(GPTDriver *gptp) { (void)gptp; @@ -134,6 +134,7 @@ static const GPTConfig i2c2gptcfg = { i2c2gptcb /* Timer callback.*/ }; #endif /* STM32_I2C_I2C2_USE_POLLING_WAIT */ +#endif /* I2C_SUPPORTS_CALLBACKS */ /** * @brief Function for I2C debugging purpose. @@ -155,6 +156,7 @@ void _i2c_unhandled_case(I2CDriver *i2cp){ #define _i2c_unhandled_case(i2cp) #endif /* CH_DBG_ENABLE_ASSERTS */ +#if I2C_SUPPORTS_CALLBACKS /** * @brief Return the last event value from I2C status registers. * @note Internal use only. @@ -372,7 +374,7 @@ static void i2c_serve_event_interrupt(I2CDriver *i2cp) { break; } } - +#endif /* I2C_SUPPORTS_CALLBACKS */ static void i2c_serve_error_interrupt(I2CDriver *i2cp) { i2cflags_t flags; @@ -417,7 +419,9 @@ static void i2c_serve_error_interrupt(I2CDriver *i2cp) { chSysLockFromIsr(); i2cAddFlagsI(i2cp, flags); chSysUnlockFromIsr(); + #if I2C_SUPPORTS_CALLBACKS _i2c_isr_err_code(i2cp, i2cp->id_slave_config); + #endif /* I2C_SUPPORTS_CALLBACKS */ } } @@ -426,13 +430,14 @@ static void i2c_serve_error_interrupt(I2CDriver *i2cp) { /** * @brief I2C1 event interrupt handler. */ +#if I2C_SUPPORTS_CALLBACKS CH_IRQ_HANDLER(VectorBC) { CH_IRQ_PROLOGUE(); i2c_serve_event_interrupt(&I2CD1); CH_IRQ_EPILOGUE(); } - +#endif /* I2C_SUPPORTS_CALLBACKS */ /** * @brief I2C1 error interrupt handler. */ @@ -442,19 +447,20 @@ CH_IRQ_HANDLER(VectorC0) { i2c_serve_error_interrupt(&I2CD1); CH_IRQ_EPILOGUE(); } -#endif +#endif /* STM32_I2C_USE_I2C1 */ #if STM32_I2C_USE_I2C2 || defined(__DOXYGEN__) /** * @brief I2C2 event interrupt handler. */ +#if I2C_SUPPORTS_CALLBACKS CH_IRQ_HANDLER(VectorC4) { CH_IRQ_PROLOGUE(); i2c_serve_event_interrupt(&I2CD2); CH_IRQ_EPILOGUE(); } - +#endif /* I2C_SUPPORTS_CALLBACKS */ /** * @brief I2C2 error interrupt handler. */ @@ -464,7 +470,7 @@ CH_IRQ_HANDLER(VectorC8) { i2c_serve_error_interrupt(&I2CD2); CH_IRQ_EPILOGUE(); } -#endif +#endif /* STM32_I2C_USE_I2C2 */ /** * @brief Low level I2C driver initialization. @@ -477,13 +483,12 @@ void i2c_lld_init(void) { i2cObjectInit(&I2CD1); I2CD1.id_i2c = I2C1; -#if STM32_I2C_I2C1_USE_POLLING_WAIT - I2CD1.timer = NULL; - I2CD1.timer_cfg = NULL; -#else +#if I2C_SUPPORTS_CALLBACKS +#if !(STM32_I2C_I2C1_USE_POLLING_WAIT) I2CD1.timer = &(STM32_I2C_I2C1_USE_GPT_TIM); I2CD1.timer_cfg = &i2c1gptcfg; #endif /* !(STM32_I2C_I2C1_USE_POLLING_WAIT) */ +#endif /* I2C_SUPPORTS_CALLBACKS */ #endif /* STM32_I2C_USE_I2C */ @@ -493,13 +498,12 @@ void i2c_lld_init(void) { i2cObjectInit(&I2CD2); I2CD2.id_i2c = I2C2; -#if STM32_I2C_I2C2_USE_POLLING_WAIT - I2CD2.timer = NULL; - I2CD2.timer_cfg = NULL; -#else +#if I2C_SUPPORTS_CALLBACKS +#if !(STM32_I2C_I2C2_USE_POLLING_WAIT) I2CD2.timer = &(STM32_I2C_I2C2_USE_GPT_TIM); I2CD2.timer_cfg = &i2c2gptcfg; #endif /* !(STM32_I2C_I2C2_USE_POLLING_WAIT) */ +#endif /* I2C_SUPPORTS_CALLBACKS */ #endif /* STM32_I2C_USE_I2C2 */ } @@ -510,14 +514,17 @@ void i2c_lld_init(void) { * @param[in] i2cp pointer to the @p I2CDriver object */ void i2c_lld_start(I2CDriver *i2cp) { - if (i2cp->timer != NULL || i2cp->timer_cfg != NULL) +#if (!(STM32_I2C_I2C2_USE_POLLING_WAIT) && I2C_SUPPORTS_CALLBACKS) gptStart(i2cp->timer, i2cp->timer_cfg); +#endif /* !(STM32_I2C_I2C2_USE_POLLING_WAIT) */ if (i2cp->id_state == I2C_STOP) { /* If in stopped state then enables the I2C clock.*/ #if STM32_I2C_USE_I2C1 if (&I2CD1 == i2cp) { +#if I2C_SUPPORTS_CALLBACKS NVICEnableVector(I2C1_EV_IRQn, CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); +#endif /* I2C_SUPPORTS_CALLBACKS */ NVICEnableVector(I2C1_ER_IRQn, CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); RCC->APB1ENR |= RCC_APB1ENR_I2C1EN; /* I2C 1 clock enable */ @@ -525,8 +532,10 @@ void i2c_lld_start(I2CDriver *i2cp) { #endif #if STM32_I2C_USE_I2C2 if (&I2CD2 == i2cp) { +#if I2C_SUPPORTS_CALLBACKS NVICEnableVector(I2C2_EV_IRQn, CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); +#endif /* I2C_SUPPORTS_CALLBACKS */ NVICEnableVector(I2C2_ER_IRQn, CORTEX_PRIORITY_MASK(STM32_I2C_I2C1_IRQ_PRIORITY)); RCC->APB1ENR |= RCC_APB1ENR_I2C2EN; /* I2C 2 clock enable */ @@ -690,6 +699,8 @@ void i2c_lld_stop(I2CDriver *i2cp) { i2cp->id_state = I2C_STOP; } + +#if I2C_SUPPORTS_CALLBACKS /** * @brief Transmits data via the I2C bus as master. * @@ -709,7 +720,6 @@ void i2c_lld_master_transmit(I2CDriver *i2cp, uint16_t slave_addr, /* "waiting" for STOP bit routine*/ #if STM32_I2C_I2C1_USE_POLLING_WAIT uint32_t timeout = I2C_POLLING_TIMEOUT; - /* TODO: timeout and Assert here */ while((i2cp->id_i2c->CR1 & I2C_CR1_STOP) && timeout) timeout--; chDbgAssert((timeout > 0), "i2c_lld_master_transmit(), #1", "time to STOP is out"); @@ -747,7 +757,6 @@ void i2c_lld_master_transmit(I2CDriver *i2cp, uint16_t slave_addr, i2cp->id_i2c->CR2 |= (I2C_CR2_ITERREN|I2C_CR2_ITEVTEN|I2C_CR2_ITBUFEN); /* enable ERR, EVT & BUF ITs */ } - /** * @brief Receives data from the I2C bus. * @@ -874,6 +883,195 @@ void i2c_lld_master_transceive(I2CDriver *i2cp){ i2cp->id_i2c->CR2 |= (I2C_CR2_ITERREN|I2C_CR2_ITEVTEN|I2C_CR2_ITBUFEN); /* enable ERR, EVT & BUF ITs */ } +#else /*I2C_SUPPORTS_CALLBACKS*/ + +/** + * @brief Synchronously transmits data via the I2C bus as master. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] slave_addr Slave device address. Bits 0-9 contain slave + * device address. Bit 15 must be set to 1 if 10-bit + * addressing modes used. Otherwise keep it cleared. + * Bits 10-14 unused. + * @param[in] txbuf pointer to the transmit buffer + * @param[in] txbytes number of bytes to be transmitted + * @param[in] rxbuf pointer to the receive buffer + * @param[in] rxbytes number of bytes to be received + */ +void i2c_lld_master_transmit(I2CDriver *i2cp, uint16_t slave_addr, + uint8_t *txbuf, size_t txbytes, uint8_t *rxbuf, size_t rxbytes) { + + /* init driver fields */ + i2cp->slave_addr = slave_addr; + i2cp->txbytes = txbytes; + i2cp->rxbytes = rxbytes; + i2cp->txbuf = txbuf; + i2cp->rxbuf = rxbuf; + + /* init address fields */ + if(slave_addr & 0x8000){ /* 10-bit mode used */ + i2cp->slave_addr1 = ((slave_addr >>7) & 0x0006); /* add the two msb of 10-bit address to the header */ + i2cp->slave_addr1 |= 0xF0; /* add the header bits with LSB = 0 -> write */ + i2cp->slave_addr2 = slave_addr & 0x00FF; /* the remaining 8 bit of 10-bit address */ + } + else{ + i2cp->slave_addr1 = ((slave_addr <<1) & 0x00FE); /* LSB = 0 -> write */ + } + + i2cp->flags = 0; + i2cp->errors = 0; + i2cp->id_i2c->CR1 &= ~I2C_CR1_POS; + i2cp->id_i2c->CR2 &= ~I2C_CR2_ITEVTEN; /* disable event interrupts */ + i2cp->id_i2c->CR2 |= I2C_CR2_ITERREN; /* enable error interrupts */ + + i2cp->id_i2c->CR1 |= I2C_CR1_START; + while (!(i2cp->id_i2c->SR1 & I2C_SR1_SB)) + ; + i2cp->id_i2c->DR = i2cp->slave_addr1; + while (!(i2cp->id_i2c->SR1 & I2C_SR1_ADDR)) + ; + while (!(i2cp->id_i2c->SR2 & I2C_SR2_BUSY)) + ; + i2cp->id_i2c->DR = *txbuf; + txbuf++; + i2cp->txbytes--; + while(i2cp->txbytes > 0){ + while(!(i2cp->id_i2c->SR1 & I2C_SR1_BTF)) + ; + i2cp->id_i2c->DR = *txbuf; + txbuf++; + i2cp->txbytes--; + } + while(!(i2cp->id_i2c->SR1 & I2C_SR1_BTF)) + ; + if(rxbytes == 0){ + i2cp->id_i2c->CR1 |= I2C_CR1_STOP; + while (i2cp->id_i2c->CR1 & I2C_CR1_STOP) + ; + } + else{ + i2c_lld_master_receive(i2cp, slave_addr, rxbuf, rxbytes); + } +} + + +/** + * @brief Synchronously receives data from the I2C bus. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] slave_addr Slave device address. Bits 0-9 contain slave + * device address. Bit 15 must be set to 1 if 10-bit + * addressing modes used. Otherwise keep it cleared. + * Bits 10-14 unused. + * @param[in] rxbuf pointer to the receive buffer + * @param[in] rxbytes number of bytes to be received + */ +void i2c_lld_master_receive(I2CDriver *i2cp, uint16_t slave_addr, + uint8_t *rxbuf, size_t rxbytes){ + + /* init driver fields */ + i2cp->slave_addr = slave_addr; + i2cp->rxbytes = rxbytes; + i2cp->rxbuf = rxbuf; + + /* init address fields */ + if(slave_addr & 0x8000){ /* 10-bit mode used */ + i2cp->slave_addr1 = ((slave_addr >>7) & 0x0006); /* add the two msb of 10-bit address to the header */ + i2cp->slave_addr1 |= 0xF0; /* add the header bits (the LSB -> 1 will be add to second */ + i2cp->slave_addr2 = slave_addr & 0x00FF; /* the remaining 8 bit of 10-bit address */ + } + else{ + i2cp->slave_addr1 = ((slave_addr <<1) | 0x01); /* LSB = 1 -> receive */ + } + + + /* setting flags and register bits */ + i2cp->flags = 0; + i2cp->errors = 0; + i2cp->id_i2c->CR1 &= ~I2C_CR1_POS; + i2cp->id_i2c->CR2 &= ~I2C_CR2_ITEVTEN; /* disable event interrupts */ + i2cp->id_i2c->CR2 |= I2C_CR2_ITERREN; /* enable error interrupts */ + + i2cp->id_i2c->CR1 |= I2C_CR1_START; + while (!(i2cp->id_i2c->SR1 & I2C_SR1_SB)) + ; + + i2cp->id_i2c->DR = i2cp->slave_addr1; + while (!(i2cp->id_i2c->SR1 & I2C_SR1_ADDR)) + ; + + if(i2cp->rxbytes >= 3){ /* more than 2 bytes receiving procedure */ + while(!(i2cp->id_i2c->SR2 & I2C_SR2_BUSY)) /* to clear ADDR bit */ + ; + while(i2cp->rxbytes > 3){ + while(!(i2cp->id_i2c->SR1 & I2C_SR1_BTF)) + ; + *rxbuf = i2cp->id_i2c->DR; + rxbuf++; + i2cp->rxbytes--; + } + while(!(i2cp->id_i2c->SR1 & I2C_SR1_BTF)) /* stopping procedure */ + ; + i2cp->id_i2c->CR1 &= ~I2C_CR1_ACK; + chSysLock(); + i2cp->id_i2c->CR1 |= I2C_CR1_STOP; + *rxbuf = i2cp->id_i2c->DR; + rxbuf++; + i2cp->rxbytes--; + chSysUnlock(); + while(!(i2cp->id_i2c->SR1 & I2C_SR1_RXNE)) + ; + *rxbuf = i2cp->id_i2c->DR; + rxbuf++; + i2cp->rxbytes--; + while (i2cp->id_i2c->CR1 & I2C_CR1_STOP) + ; + i2cp->id_i2c->CR1 |= I2C_CR1_ACK; + } + else{ /* 1 or 2 bytes receiving procedure */ + if(i2cp->rxbytes == 2){ + i2cp->id_i2c->CR1 |= I2C_CR1_POS; + chSysLock(); + while(!(i2cp->id_i2c->SR2 & I2C_SR2_BUSY)) /* to clear ADDR bit */ + ; + i2cp->id_i2c->CR1 &= ~I2C_CR1_ACK; + chSysUnlock(); + while(!(i2cp->id_i2c->SR1 & I2C_SR1_BTF)) + ; + chSysLock(); + i2cp->id_i2c->CR1 |= I2C_CR1_STOP; + *rxbuf = i2cp->id_i2c->DR; + rxbuf++; + i2cp->rxbytes--; + chSysUnlock(); + *rxbuf = i2cp->id_i2c->DR; + rxbuf++; + i2cp->rxbytes--; + while (i2cp->id_i2c->CR1 & I2C_CR1_STOP) + ; + i2cp->id_i2c->CR1 &= ~I2C_CR1_POS; + i2cp->id_i2c->CR1 |= I2C_CR1_ACK; + } + else{ /* 1 byte */ + i2cp->id_i2c->CR1 &= ~I2C_CR1_ACK; + chSysLock(); + while(!(i2cp->id_i2c->SR2 & I2C_SR2_BUSY)) /* to clear ADDR bit */ + ; + i2cp->id_i2c->CR1 |= I2C_CR1_STOP; + chSysUnlock(); + while(!(i2cp->id_i2c->SR1 & I2C_SR1_RXNE)) + ; + *rxbuf = i2cp->id_i2c->DR; + rxbuf++; + i2cp->rxbytes--; + while (i2cp->id_i2c->CR1 & I2C_CR1_STOP) + ; + i2cp->id_i2c->CR1 |= I2C_CR1_ACK; + } + } +} +#endif /* I2C_SUPPORTS_CALLBACKS */ + #undef rxBuffp #undef txBuffp diff --git a/os/hal/platforms/STM32/i2c_lld.h b/os/hal/platforms/STM32/i2c_lld.h index 6de73f6b0..69d1753bb 100644 --- a/os/hal/platforms/STM32/i2c_lld.h +++ b/os/hal/platforms/STM32/i2c_lld.h @@ -13,11 +13,17 @@ /*===========================================================================*/ /* Driver constants. */ /*===========================================================================*/ -#define I2C_START_TIMEOUT 0xFFFF /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ +/** + * @brief Switch between callback based and synchronouse driver. + * @note The default is synchronouse. + */ +#if !defined(I2C_SUPPORTS_CALLBACKS) || defined(__DOXYGEN__) +#define I2C_SUPPORTS_CALLBACKS FALSE +#endif /** * @brief I2C1 driver synchronization choice between GPT and polling. @@ -161,6 +167,7 @@ struct I2CDriver{ * @brief Driver state. */ i2cstate_t id_state; + #if I2C_USE_WAIT /** * @brief Thread waiting for I/O completion. @@ -177,6 +184,7 @@ struct I2CDriver{ Semaphore id_semaphore; #endif #endif /* I2C_USE_MUTUAL_EXCLUSION */ + /** * @brief Current configuration data. */ @@ -198,7 +206,7 @@ struct I2CDriver{ uint16_t slave_addr; /*!< @brief Current slave address. */ uint8_t slave_addr1;/*!< @brief 7-bit address of the slave with r\w bit.*/ - uint8_t slave_addr2;/*!< @brief Used in 10-bit address mode. */ + uint8_t slave_addr2;/*!< @brief Uses in 10-bit address mode. */ EventSource sevent; /*!< @brief Status Change @p EventSource.*/ @@ -209,6 +217,8 @@ struct I2CDriver{ */ I2C_TypeDef *id_i2c; +#if !(STM32_I2C_I2C1_USE_POLLING_WAIT) + /* TODO: capability to switch this GPT fields off */ /** * @brief Timer for waiting STOP condition on the bus. * @details This is workaround for STM32 buggy I2C cell. @@ -219,7 +229,8 @@ struct I2CDriver{ * @brief Config for workaround timer. */ const GPTConfig *timer_cfg; -} ; +#endif /* !(STM32_I2C_I2C1_USE_POLLING_WAIT) */ +}; /*===========================================================================*/ @@ -235,7 +246,7 @@ struct I2CDriver{ * does not block thread, only if slave not response it does. */ #define i2c_lld_wait_bus_free(i2cp) { \ - uint32_t tmo = 0xffff; \ + uint32_t tmo = 0xfffff; \ while((i2cp->id_i2c->SR2 & I2C_SR2_BUSY) && tmo--) \ ; \ } diff --git a/os/hal/src/i2c.c b/os/hal/src/i2c.c index b233764f5..9676a3250 100644 --- a/os/hal/src/i2c.c +++ b/os/hal/src/i2c.c @@ -178,7 +178,11 @@ void i2cMasterTransmit(I2CDriver *i2cp, i2cp->id_state = I2C_ACTIVE_TRANSMIT; i2c_lld_master_transmit(i2cp, slave_addr, txbuf, txbytes, rxbuf, rxbytes); +#if I2C_SUPPORTS_CALLBACKS _i2c_wait_s(i2cp); +#else + i2cp->id_state = I2C_READY; +#endif /* I2C_SUPPORTS_CALLBACKS */ } /** @@ -216,7 +220,11 @@ void i2cMasterReceive(I2CDriver *i2cp, i2cp->id_state = I2C_ACTIVE_RECEIVE; i2c_lld_master_receive(i2cp, slave_addr, rxbuf, rxbytes); +#if I2C_SUPPORTS_CALLBACKS _i2c_wait_s(i2cp); +#else + i2cp->id_state = I2C_READY; +#endif /* I2C_SUPPORTS_CALLBACKS */ } diff --git a/testhal/STM32/I2C/chconf.h b/testhal/STM32/I2C/chconf.h index 9f5273ba5..a293288d3 100644 --- a/testhal/STM32/I2C/chconf.h +++ b/testhal/STM32/I2C/chconf.h @@ -188,7 +188,7 @@ * @note The default is @p TRUE. */ #if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) -#define CH_USE_MUTEXES FALSE +#define CH_USE_MUTEXES TRUE #endif /** diff --git a/testhal/STM32/I2C/halconf.h b/testhal/STM32/I2C/halconf.h index f64120126..da52785c0 100644 --- a/testhal/STM32/I2C/halconf.h +++ b/testhal/STM32/I2C/halconf.h @@ -178,7 +178,7 @@ * @note Disabling this option saves both code and data space. */ #if !defined(I2C_USE_WAIT) || defined(__DOXYGEN__) -#define I2C_USE_WAIT TRUE +#define I2C_USE_WAIT FALSE #endif /** @@ -188,6 +188,13 @@ #define I2C_USE_MUTUAL_EXCLUSION TRUE #endif +/** + * @brief Switch to asynchronouse driver with callbacks. + */ +#if !defined(I2C_SUPPORTS_CALLBACKS) || defined(__DOXYGEN__) +#define I2C_SUPPORTS_CALLBACKS TRUE +#endif + /*===========================================================================*/ /* MAC driver related settings. */ /*===========================================================================*/ diff --git a/testhal/STM32/I2C/i2c_pns.c b/testhal/STM32/I2C/i2c_pns.c index 63f7d99bd..44f4a8a33 100644 --- a/testhal/STM32/I2C/i2c_pns.c +++ b/testhal/STM32/I2C/i2c_pns.c @@ -32,7 +32,6 @@ static const I2CConfig i2cfg2 = { void I2CInit_pns(void){ - i2cInit(); i2cStart(&I2CD1, &i2cfg1); @@ -46,13 +45,12 @@ void I2CInit_pns(void){ palSetPadMode(IOPORT2, 10, PAL_MODE_STM32_ALTERNATE_OPENDRAIN); palSetPadMode(IOPORT2, 11, PAL_MODE_STM32_ALTERNATE_OPENDRAIN); - /* startups. Pauses added just to be safe */ + chThdSleepMilliseconds(1000); init_max1236(); - chThdSleepMilliseconds(100); - + chThdSleepMilliseconds(1000); init_lis3(); - chThdSleepMilliseconds(100); + chThdSleepMilliseconds(1000); } diff --git a/testhal/STM32/I2C/lis3.c b/testhal/STM32/I2C/lis3.c index 26a3292f5..401f56199 100644 --- a/testhal/STM32/I2C/lis3.c +++ b/testhal/STM32/I2C/lis3.c @@ -14,10 +14,17 @@ #include "lis3.h" +#define lis3_addr 0b0011101 + + /* buffers */ static i2cblock_t accel_rx_data[ACCEL_RX_DEPTH]; static i2cblock_t accel_tx_data[ACCEL_TX_DEPTH]; +static int16_t acceleration_x = 0; +static int16_t acceleration_y = 0; +static int16_t acceleration_z = 0; + /* Error trap */ static void i2c_lis3_error_cb(I2CDriver *i2cp, const I2CSlaveConfig *i2cscfg){ (void)i2cscfg; @@ -26,50 +33,10 @@ static void i2c_lis3_error_cb(I2CDriver *i2cp, const I2CSlaveConfig *i2cscfg){ while(TRUE); } -/** - * This treading need for convenient realize - * "read through write" process. - */ -static WORKING_AREA(I2CAccelThreadWA, 128); -static Thread *i2c_accel_tp = NULL; -static msg_t I2CAccelThread(void *arg) { - (void)arg; - - int16_t acceleration_x = 0; - int16_t acceleration_y = 0; - int16_t acceleration_z = 0; - - I2CSlaveConfig *i2cscfg; - msg_t msg; - - while (TRUE) { - /* Waiting for wake up */ - chSysLock(); - i2c_accel_tp = chThdSelf(); - chSchGoSleepS(THD_STATE_SUSPENDED); - msg = chThdSelf()->p_msg; /* Retrieving the message, optional.*/ - chSysUnlock(); - - /***************** Perform processing here. ***************************/ - i2cscfg = (I2CSlaveConfig *)msg; - - /* collect measured data */ - acceleration_x = accel_rx_data[0] + (accel_rx_data[1] << 8); - acceleration_y = accel_rx_data[2] + (accel_rx_data[3] << 8); - acceleration_z = accel_rx_data[4] + (accel_rx_data[5] << 8); - } - return 0; -} - /* This callback raise up when transfer finished */ static void i2c_lis3_cb(I2CDriver *i2cp, const I2CSlaveConfig *i2cscfg){ - (void) i2cp; - /* only wake up processing thread */ - if (i2c_accel_tp != NULL) { - i2c_accel_tp->p_msg = (msg_t)i2cscfg; - chSchReadyI(i2c_accel_tp); - i2c_accel_tp = NULL; - } + (void)i2cp; + (void)i2cscfg; } @@ -80,29 +47,10 @@ static const I2CSlaveConfig lis3 = { }; -#define lis3_addr 0b0011101 - - - /** * Init function. Here we will also start personal serving thread. */ int init_lis3(void){ - - /* Starting the accelerometer serving thread.*/ - i2c_accel_tp = chThdCreateStatic(I2CAccelThreadWA, - sizeof(I2CAccelThreadWA), - HIGHPRIO, - I2CAccelThread, - NULL); - - /* wait thread statup */ - while (i2c_accel_tp == NULL) - chThdSleepMilliseconds(1); - -#define TXBYTES 4 -#define RXBYTES 0 /* set to 0 because we need only transmit */ - /* configure accelerometer */ accel_tx_data[0] = ACCEL_CTRL_REG1 | AUTO_INCREMENT_BIT; /* register address */ accel_tx_data[1] = 0b11100111; @@ -110,12 +58,7 @@ int init_lis3(void){ accel_tx_data[3] = 0b00000000; /* sending */ - i2cMasterTransmit(&I2CD1, &lis3, lis3_addr, accel_tx_data, TXBYTES, accel_rx_data, RXBYTES); - chThdSleepMilliseconds(1); - -#undef RXBYTES -#undef TXBYTES - + i2cMasterTransmit(&I2CD1, &lis3, lis3_addr, accel_tx_data, 4, accel_rx_data, 0); return 0; } @@ -123,13 +66,13 @@ int init_lis3(void){ * */ void request_acceleration_data(void){ -#define RXBYTES 6 -#define TXBYTES 1 accel_tx_data[0] = ACCEL_OUT_DATA | AUTO_INCREMENT_BIT; // register address - i2cAcquireBus(&I2CD1); - i2cMasterTransmit(&I2CD1, &lis3, lis3_addr, accel_tx_data, TXBYTES, accel_rx_data, RXBYTES); - i2cReleaseBus(&I2CD1); -#undef RXBYTES -#undef TXBYTES + //i2cAcquireBus(&I2CD1); + i2cMasterTransmit(&I2CD1, &lis3, lis3_addr, accel_tx_data, 1, accel_rx_data, 6); + //i2cReleaseBus(&I2CD1); + + acceleration_x = accel_rx_data[0] + (accel_rx_data[1] << 8); + acceleration_y = accel_rx_data[2] + (accel_rx_data[3] << 8); + acceleration_z = accel_rx_data[4] + (accel_rx_data[5] << 8); } diff --git a/testhal/STM32/I2C/main.c b/testhal/STM32/I2C/main.c index ce8cb5522..b828953c5 100644 --- a/testhal/STM32/I2C/main.c +++ b/testhal/STM32/I2C/main.c @@ -68,7 +68,7 @@ static msg_t PollMax1236Thread(void *arg) { systime_t time = chTimeNow(); while (TRUE) { - time += MS2ST(20); + time += MS2ST(200); /* Call reading function */ read_max1236(); chThdSleepUntil(time); @@ -83,7 +83,7 @@ static msg_t PollAccelThread(void *arg) { systime_t time = chTimeNow(); while (TRUE) { - time += MS2ST(2); + time += MS2ST(20); request_acceleration_data(); chThdSleepUntil(time); } diff --git a/testhal/STM32/I2C/max1236.c b/testhal/STM32/I2C/max1236.c index 3e3dbd0c1..09e2c8b35 100644 --- a/testhal/STM32/I2C/max1236.c +++ b/testhal/STM32/I2C/max1236.c @@ -10,6 +10,10 @@ #include "max1236.h" + +#define max1236_addr 0b0110100 + + /* Data buffers */ static i2cblock_t max1236_rx_data[MAX1236_RX_DEPTH]; static i2cblock_t max1236_tx_data[MAX1236_TX_DEPTH]; @@ -31,10 +35,6 @@ static void i2c_max1236_cb(I2CDriver *i2cp, const I2CSlaveConfig *i2cscfg){ (void)*i2cp; (void)*i2cscfg; /* get ADC data */ - ch1 = ((max1236_rx_data[0] & 0xF) << 8) + max1236_rx_data[1]; - ch2 = ((max1236_rx_data[2] & 0xF) << 8) + max1236_rx_data[3]; - ch3 = ((max1236_rx_data[4] & 0xF) << 8) + max1236_rx_data[5]; - ch4 = ((max1236_rx_data[6] & 0xF) << 8) + max1236_rx_data[7]; } @@ -45,7 +45,6 @@ static const I2CSlaveConfig max1236 = { i2c_max1236_error_cb, }; -#define max1236_addr 0b0110100 /** * Initilization routine. See datasheet on page 13 to understand @@ -53,32 +52,24 @@ static const I2CSlaveConfig max1236 = { */ void init_max1236(void){ /* this data we must send via IC to setup ADC */ -#define RXBYTES 0 -#define TXBYTES 2 max1236_tx_data[0] = 0b10000011; /* config register content. Consult datasheet */ max1236_tx_data[1] = 0b00000111; /* config register content. Consult datasheet */ - /* transmit out 2 bytes */ i2cAcquireBus(&I2CD2); - i2cMasterTransmit(&I2CD2, &max1236, max1236_addr, max1236_tx_data, TXBYTES, max1236_rx_data, RXBYTES); - while(I2CD2.id_state != I2C_READY){ - chThdSleepMilliseconds(1); - } + i2cMasterTransmit(&I2CD2, &max1236, max1236_addr, max1236_tx_data, 2, max1236_rx_data, 0); i2cReleaseBus(&I2CD2); -#undef RXBYTES -#undef TXBYTES } /* Now simply read 8 bytes to get all 4 ADC channels */ void read_max1236(void){ -#define TXBYTES 0 -#define RXBYTES 8 - i2cAcquireBus(&I2CD2); - i2cMasterReceive(&I2CD2, &max1236, max1236_addr, max1236_rx_data, RXBYTES); + i2cMasterReceive(&I2CD2, &max1236, max1236_addr, max1236_rx_data, 8); i2cReleaseBus(&I2CD2); -#undef RXBYTES -#undef TXBYTES + + ch1 = ((max1236_rx_data[0] & 0xF) << 8) + max1236_rx_data[1]; + ch2 = ((max1236_rx_data[2] & 0xF) << 8) + max1236_rx_data[3]; + ch3 = ((max1236_rx_data[4] & 0xF) << 8) + max1236_rx_data[5]; + ch4 = ((max1236_rx_data[6] & 0xF) << 8) + max1236_rx_data[7]; } diff --git a/testhal/STM32/I2C/mcuconf.h b/testhal/STM32/I2C/mcuconf.h index 105c168f4..809c3abd2 100644 --- a/testhal/STM32/I2C/mcuconf.h +++ b/testhal/STM32/I2C/mcuconf.h @@ -159,10 +159,10 @@ #define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt() /* I2C1 */ #define STM32_I2C_I2C1_USE_GPT_TIM GPTD1 -#define STM32_I2C_I2C1_USE_POLLING_WAIT FALSE +#define STM32_I2C_I2C1_USE_POLLING_WAIT TRUE /* I2C2 */ #define STM32_I2C_I2C2_USE_GPT_TIM GPTD2 -#define STM32_I2C_I2C2_USE_POLLING_WAIT FALSE +#define STM32_I2C_I2C2_USE_POLLING_WAIT TRUE /* diff --git a/testhal/STM32/I2C/tmp75.c b/testhal/STM32/I2C/tmp75.c index 6276e7c8e..72e634527 100644 --- a/testhal/STM32/I2C/tmp75.c +++ b/testhal/STM32/I2C/tmp75.c @@ -14,6 +14,7 @@ /* input buffer */ static i2cblock_t tmp75_rx_data[TMP75_RX_DEPTH]; + /* temperature value */ static int16_t temperature = 0; @@ -30,7 +31,6 @@ static void i2c_tmp75_cb(I2CDriver *i2cp, const I2CSlaveConfig *i2cscfg){ (void)*i2cp; (void)*i2cscfg; /* store temperature value */ - temperature = (tmp75_rx_data[0] << 8) + tmp75_rx_data[1]; } /* Fill TMP75 config. */ @@ -43,12 +43,10 @@ static const I2CSlaveConfig tmp75 = { /* This is main function. */ void request_temperature(void){ -#define TXBYTES 0 /* set to zero because we need only reading */ -#define RXBYTES 2 /* we need to read 2 bytes */ - i2cAcquireBus(&I2CD2); - i2cMasterReceive(&I2CD2, &tmp75, tmp75_addr, tmp75_rx_data, RXBYTES); + i2cMasterReceive(&I2CD2, &tmp75, tmp75_addr, tmp75_rx_data, 2); i2cReleaseBus(&I2CD2); + temperature = (tmp75_rx_data[0] << 8) + tmp75_rx_data[1]; } -- cgit v1.2.3