From 6ae531cde4660cff8217f96fa621306efdeea207 Mon Sep 17 00:00:00 2001 From: gdisirio Date: Mon, 21 May 2012 16:59:53 +0000 Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@4225 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- boards/EA_LPCXPRESSO_BB_11U14/board.c | 13 +- boards/EA_LPCXPRESSO_BB_11U14/board.h | 16 +- demos/ARMCM0-LPC11U14-LPCXPRESSO/Makefile | 196 +++++++++++ demos/ARMCM0-LPC11U14-LPCXPRESSO/chconf.h | 535 +++++++++++++++++++++++++++++ demos/ARMCM0-LPC11U14-LPCXPRESSO/halconf.h | 342 ++++++++++++++++++ demos/ARMCM0-LPC11U14-LPCXPRESSO/main.c | 145 ++++++++ demos/ARMCM0-LPC11U14-LPCXPRESSO/mcuconf.h | 70 ++++ os/hal/platforms/LPC11Uxx/gpt_lld.c | 342 ++++++++++++++++++ os/hal/platforms/LPC11Uxx/gpt_lld.h | 208 +++++++++++ os/hal/platforms/LPC11Uxx/hal_lld.c | 8 +- os/hal/platforms/LPC11Uxx/hal_lld.h | 4 +- os/hal/platforms/LPC11Uxx/platform.mk | 2 + os/hal/platforms/LPC11Uxx/serial_lld.c | 20 +- os/hal/platforms/LPC11Uxx/spi_lld.c | 395 +++++++++++++++++++++ os/hal/platforms/LPC11Uxx/spi_lld.h | 315 +++++++++++++++++ os/ports/GCC/ARMCMx/LPC11xx/ld/LPC1114.ld | 4 +- os/ports/GCC/ARMCMx/LPC11xx/ld/LPC11U14.ld | 151 ++++++++ os/ports/GCC/ARMCMx/LPC13xx/ld/LPC1343.ld | 4 +- 18 files changed, 2737 insertions(+), 33 deletions(-) create mode 100644 demos/ARMCM0-LPC11U14-LPCXPRESSO/Makefile create mode 100644 demos/ARMCM0-LPC11U14-LPCXPRESSO/chconf.h create mode 100644 demos/ARMCM0-LPC11U14-LPCXPRESSO/halconf.h create mode 100644 demos/ARMCM0-LPC11U14-LPCXPRESSO/main.c create mode 100644 demos/ARMCM0-LPC11U14-LPCXPRESSO/mcuconf.h create mode 100644 os/hal/platforms/LPC11Uxx/gpt_lld.c create mode 100644 os/hal/platforms/LPC11Uxx/gpt_lld.h create mode 100644 os/hal/platforms/LPC11Uxx/spi_lld.c create mode 100644 os/hal/platforms/LPC11Uxx/spi_lld.h create mode 100644 os/ports/GCC/ARMCMx/LPC11xx/ld/LPC11U14.ld diff --git a/boards/EA_LPCXPRESSO_BB_11U14/board.c b/boards/EA_LPCXPRESSO_BB_11U14/board.c index fdb33658e..3960cac57 100644 --- a/boards/EA_LPCXPRESSO_BB_11U14/board.c +++ b/boards/EA_LPCXPRESSO_BB_11U14/board.c @@ -28,8 +28,8 @@ */ #if HAL_USE_PAL || defined(__DOXYGEN__) const PALConfig pal_default_config = { - {VAL_GPIO0DATA, VAL_GPIO0DIR}, - {VAL_GPIO1DATA, VAL_GPIO1DIR} + {VAL_GPIO0DATA, VAL_GPIO0DIR}, + {VAL_GPIO1DATA, VAL_GPIO1DIR} }; #endif @@ -58,4 +58,13 @@ void boardInit(void) { and makes it GPIO1_2. */ LPC_IOCON->PIO0_21 = 0x80; /* Disables pull-up on LED3R output.*/ LPC_IOCON->PIO0_22 = 0x80; /* Disables pull-up on LED3G output.*/ + + /* SSP0 mapping.*/ + LPC_IOCON->PIO1_29 = 0x81; /* SCK0 without resistors. */ + LPC_IOCON->PIO0_8 = 0x81; /* MISO0 without resistors. */ + LPC_IOCON->PIO0_9 = 0x81; /* MOSI0 without resistors. */ + + /* USART mapping.*/ + LPC_IOCON->PIO0_18 = 0x81; /* RDX without resistors. */ + LPC_IOCON->PIO0_19 = 0x81; /* TDX without resistors. */ } diff --git a/boards/EA_LPCXPRESSO_BB_11U14/board.h b/boards/EA_LPCXPRESSO_BB_11U14/board.h index aea951a39..6529ebc82 100644 --- a/boards/EA_LPCXPRESSO_BB_11U14/board.h +++ b/boards/EA_LPCXPRESSO_BB_11U14/board.h @@ -48,16 +48,16 @@ #define VAL_GPIO0DIR PAL_PORT_BIT(GPIO0_OLEDSEL) | \ PAL_PORT_BIT(GPIO0_USB_DPCTL) | \ PAL_PORT_BIT(GPIO0_LED2) | \ - PAL_PORT_BIT(GPIO1_LED3B) | \ - PAL_PORT_BIT(GPIO1_LED3R) | \ - PAL_PORT_BIT(GPIO1_LED3G) | \ - PAL_PORT_BIT(GPIO1_SPI0SEL) + PAL_PORT_BIT(GPIO0_LED3B) | \ + PAL_PORT_BIT(GPIO0_LED3R) | \ + PAL_PORT_BIT(GPIO0_LED3G) | \ + PAL_PORT_BIT(GPIO0_SPI0SEL) #define VAL_GPIO0DATA PAL_PORT_BIT(GPIO0_OLEDSEL) | \ PAL_PORT_BIT(GPIO0_LED2) | \ - PAL_PORT_BIT(GPIO1_LED3B) | \ - PAL_PORT_BIT(GPIO1_LED3R) | \ - PAL_PORT_BIT(GPIO1_LED3G) | \ - PAL_PORT_BIT(GPIO1_SPI0SEL) + PAL_PORT_BIT(GPIO0_LED3B) | \ + PAL_PORT_BIT(GPIO0_LED3R) | \ + PAL_PORT_BIT(GPIO0_LED3G) | \ + PAL_PORT_BIT(GPIO0_SPI0SEL) /* * GPIO 1 initial setup. diff --git a/demos/ARMCM0-LPC11U14-LPCXPRESSO/Makefile b/demos/ARMCM0-LPC11U14-LPCXPRESSO/Makefile new file mode 100644 index 000000000..dc2aa318f --- /dev/null +++ b/demos/ARMCM0-LPC11U14-LPCXPRESSO/Makefile @@ -0,0 +1,196 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files +CHIBIOS = ../.. +include $(CHIBIOS)/boards/EA_LPCXPRESSO_BB_11U14/board.mk +include $(CHIBIOS)/os/hal/platforms/LPC11Uxx/platform.mk +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/ports/GCC/ARMCMx/LPC11xx/port.mk +include $(CHIBIOS)/os/kernel/kernel.mk +include $(CHIBIOS)/test/test.mk + +# Define linker script file here +LDSCRIPT= $(PORTLD)/LPC11U14.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(PORTSRC) \ + $(KERNSRC) \ + $(TESTSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(CHIBIOS)/os/various/evtimer.c \ + $(CHIBIOS)/os/various/syscalls.c \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = $(PORTASM) + +INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m0 + +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +OD = $(TRGT)objdump +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of default section +# + +# List all default C defines here, like -D_DEBUG=1 +DDEFS = -DLPC1114 -D__NEWLIB__ + +# List all default ASM defines here, like -D_DEBUG=1 +DADEFS = + +# List all default directories to look for include files here +DINCDIR = + +# List the default directory to look for the libraries here +DLIBDIR = + +# List all default libraries here +DLIBS = + +# +# End of default section +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk diff --git a/demos/ARMCM0-LPC11U14-LPCXPRESSO/chconf.h b/demos/ARMCM0-LPC11U14-LPCXPRESSO/chconf.h new file mode 100644 index 000000000..b1f2cd62c --- /dev/null +++ b/demos/ARMCM0-LPC11U14-LPCXPRESSO/chconf.h @@ -0,0 +1,535 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef _CHCONF_H_ +#define _CHCONF_H_ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__) +#define CH_FREQUENCY 1000 +#endif + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + */ +#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__) +#define CH_TIME_QUANTUM 20 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_USE_MEMCORE. + */ +#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__) +#define CH_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread automatically. The application has + * then the responsibility to do one of the following: + * - Spawn a custom idle thread at priority @p IDLEPRIO. + * - Change the main() thread priority to @p IDLEPRIO then enter + * an endless loop. In this scenario the @p main() thread acts as + * the idle thread. + * . + * @note Unless an idle thread is spawned the @p main() thread must not + * enter a sleep state. + */ +#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__) +#define CH_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__) +#define CH_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__) +#define CH_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__) +#define CH_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Atomic semaphore API. + * @details If enabled then the semaphores the @p chSemSignalWait() API + * is included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__) +#define CH_USE_SEMSW TRUE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__) +#define CH_USE_MUTEXES TRUE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MUTEXES. + */ +#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_CONDVARS. + */ +#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__) +#define CH_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_EVENTS. + */ +#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__) +#define CH_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special requirements. + * @note Requires @p CH_USE_MESSAGES. + */ +#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__) +#define CH_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_SEMAPHORES. + */ +#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__) +#define CH_USE_MAILBOXES TRUE +#endif + +/** + * @brief I/O Queues APIs. + * @details If enabled then the I/O queues APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__) +#define CH_USE_QUEUES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__) +#define CH_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or + * @p CH_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__) +#define CH_USE_HEAP TRUE +#endif + +/** + * @brief C-runtime allocator. + * @details If enabled the the heap allocator APIs just wrap the C-runtime + * @p malloc() and @p free() functions. + * + * @note The default is @p FALSE. + * @note Requires @p CH_USE_HEAP. + * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the + * appropriate documentation. + */ +#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__) +#define CH_USE_MALLOC_HEAP FALSE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__) +#define CH_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_USE_WAITEXIT. + * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS. + */ +#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__) +#define CH_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the context switch circular trace buffer is + * activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_TRACE FALSE +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p Thread structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p TRUE. + * @note This debug option is defaulted to TRUE because it is required by + * some test cases into the test suite. + */ +#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__) +#define CH_DBG_THREADS_PROFILING TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p Thread structure. + */ +#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__) +#define THREAD_EXT_FIELDS \ + /* Add threads custom fields here.*/ +#endif + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} +#endif + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + * + * @note It is inserted into lock zone. + * @note It is also invoked when the threads simply return in order to + * terminate. + */ +#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__) +#define THREAD_EXT_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} +#endif + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__) +#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* System halt code here.*/ \ +} +#endif + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__) +#define IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} +#endif + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_TICK_EVENT_HOOK() { \ + /* System tick event code here.*/ \ +} +#endif + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__) +#define SYSTEM_HALT_HOOK() { \ + /* System halt code here.*/ \ +} +#endif + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* _CHCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM0-LPC11U14-LPCXPRESSO/halconf.h b/demos/ARMCM0-LPC11U14-LPCXPRESSO/halconf.h new file mode 100644 index 000000000..d3766e0fd --- /dev/null +++ b/demos/ARMCM0-LPC11U14-LPCXPRESSO/halconf.h @@ -0,0 +1,342 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef _HALCONF_H_ +#define _HALCONF_H_ + +#include "mcuconf.h" + +/** + * @brief Enables the TM subsystem. + */ +#if !defined(HAL_USE_TM) || defined(__DOXYGEN__) +#define HAL_USE_TM FALSE +#endif + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Block size for MMC transfers. + */ +#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__) +#define MMC_SECTOR_SIZE 512 +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/** + * @brief Number of positive insertion queries before generating the + * insertion event. + */ +#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__) +#define MMC_POLLING_INTERVAL 10 +#endif + +/** + * @brief Interval, in milliseconds, between insertion queries. + */ +#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__) +#define MMC_POLLING_DELAY 10 +#endif + +/** + * @brief Uses the SPI polled API for small data transfers. + * @details Polled transfers usually improve performance because it + * saves two context switches and interrupt servicing. Note + * that this option has no effect on large transfers which + * are always performed using DMAs/IRQs. + */ +#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__) +#define MMC_USE_SPI_POLLING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 64 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* _HALCONF_H_ */ + +/** @} */ diff --git a/demos/ARMCM0-LPC11U14-LPCXPRESSO/main.c b/demos/ARMCM0-LPC11U14-LPCXPRESSO/main.c new file mode 100644 index 000000000..3afc14786 --- /dev/null +++ b/demos/ARMCM0-LPC11U14-LPCXPRESSO/main.c @@ -0,0 +1,145 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +#include "ch.h" +#include "hal.h" +#include "test.h" + +#if 0 +/* + * Conversion table from hex digit to 7 segments encoding, bit 5 controls the + * dot. + * 8 = LU, 4 = RL, 2 = D, 1 = RU, 8 = U, 4 = M, 2 = LL, 1 = L. + */ +static uint8_t digits[32] = { + 0x24, 0xAF, 0xE0, 0xA2, 0x2B, 0x32, 0x30, 0xA7, + 0x20, 0x22, 0x21, 0x38, 0x74, 0xA8, 0x70, 0x71, + 0x04, 0x8F, 0xC0, 0x82, 0x0B, 0x12, 0x10, 0x87, + 0x00, 0x02, 0x01, 0x18, 0x54, 0x88, 0x50, 0x51 +}; + +/* + * SPI configuration (1MHz, CPHA=0, CPOL=0). + */ +static SPIConfig spicfg = { + NULL, + GPIO1, + GPIO1_SPI0SEL, + CR0_DSS8BIT | CR0_FRFSPI | CR0_CLOCKRATE(0), + 48 +}; +#endif + +/* + * Red LED blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread1, 128); +static msg_t Thread1(void *arg) { + + (void)arg; + chRegSetThreadName("blinker1"); + while (TRUE) { + palClearPad(GPIO0, GPIO0_LED2); + chThdSleepMilliseconds(500); + palSetPad(GPIO0, GPIO0_LED2); + chThdSleepMilliseconds(500); + } +} + +/* + * RGB LED blinker thread, times are in milliseconds. + */ +static WORKING_AREA(waThread2, 128); +static msg_t Thread2(void *arg) { + + (void)arg; + chRegSetThreadName("blinker2"); + while (TRUE) { + palClearPort(GPIO0, PAL_PORT_BIT(GPIO0_LED3B) | + PAL_PORT_BIT(GPIO0_LED3R) | + PAL_PORT_BIT(GPIO0_LED3G)); + chThdSleepMilliseconds(250); + palClearPort(GPIO0, PAL_PORT_BIT(GPIO0_LED3B) | + PAL_PORT_BIT(GPIO0_LED3R) | + PAL_PORT_BIT(GPIO0_LED3G)); + palSetPort(GPIO0, PAL_PORT_BIT(GPIO0_LED3B)); + chThdSleepMilliseconds(250); + palClearPort(GPIO0, PAL_PORT_BIT(GPIO0_LED3B) | + PAL_PORT_BIT(GPIO0_LED3R) | + PAL_PORT_BIT(GPIO0_LED3G)); + palSetPort(GPIO0, PAL_PORT_BIT(GPIO0_LED3R)); + chThdSleepMilliseconds(250); + palClearPort(GPIO1, PAL_PORT_BIT(GPIO0_LED3B) | + PAL_PORT_BIT(GPIO0_LED3R) | + PAL_PORT_BIT(GPIO0_LED3G)); + palSetPort(GPIO0, PAL_PORT_BIT(GPIO0_LED3G)); + chThdSleepMilliseconds(250); + } +} + +/* + * Application entry point. + */ +int main(void) { + uint8_t i; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * Activates the SD1 and SPI1 drivers. + */ + sdStart(&SD1, NULL); /* Default: 38400,8,N,1. */ +// spiStart(&SPID1, &spicfg); + + /* + * Creates the blinker threads. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + chThdCreateStatic(waThread2, sizeof(waThread2), NORMALPRIO, Thread2, NULL); + + /* + * Normal main() thread activity, in this demo it updates the 7-segments + * display on the LPCXpresso main board using the SPI driver. + */ + i = 0; + while (TRUE) { + if (!palReadPad(GPIO0, GPIO0_SW3)) + TestThread(&SD1); +#if 0 + spiSelect(&SPID1); + spiSend(&SPID1, 1, &digits[i]); /* Non polled method. */ + spiUnselect(&SPID1); + chThdSleepMilliseconds(500); + spiSelect(&SPID1); + spiPolledExchange(&SPID1, digits[i | 0x10]); /* Polled method. */ + spiUnselect(&SPID1); + chThdSleepMilliseconds(500); +#endif + i = (i + 1) & 15; + } +} diff --git a/demos/ARMCM0-LPC11U14-LPCXPRESSO/mcuconf.h b/demos/ARMCM0-LPC11U14-LPCXPRESSO/mcuconf.h new file mode 100644 index 000000000..984ca40a2 --- /dev/null +++ b/demos/ARMCM0-LPC11U14-LPCXPRESSO/mcuconf.h @@ -0,0 +1,70 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * LPC11U14 drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the driver + * is enabled in halconf.h. + * + * IRQ priorities: + * 3...0 Lowest...highest. + */ + +/* + * HAL driver system settings. + */ +#define LPC_PLLCLK_SOURCE SYSPLLCLKSEL_SYSOSC +#define LPC_SYSPLL_MUL 4 +#define LPC_SYSPLL_DIV 4 +#define LPC_MAINCLK_SOURCE SYSMAINCLKSEL_PLLOUT +#define LPC_SYSABHCLK_DIV 1 + +/* + * GPT driver system settings. + */ +#define LPC_GPT_USE_CT16B0 TRUE +#define LPC_GPT_USE_CT16B1 TRUE +#define LPC_GPT_USE_CT32B0 TRUE +#define LPC_GPT_USE_CT32B1 TRUE +#define LPC_GPT_CT16B0_IRQ_PRIORITY 2 +#define LPC_GPT_CT16B1_IRQ_PRIORITY 2 +#define LPC_GPT_CT32B0_IRQ_PRIORITY 2 +#define LPC_GPT_CT32B1_IRQ_PRIORITY 2 + +/* + * SERIAL driver system settings. + */ +#define LPC_SERIAL_USE_UART0 TRUE +#define LPC_SERIAL_FIFO_PRELOAD 16 +#define LPC_SERIAL_UART0CLKDIV 1 +#define LPC_SERIAL_UART0_IRQ_PRIORITY 3 + +/* + * SPI driver system settings. + */ +#define LPC_SPI_USE_SSP0 TRUE +#define LPC_SPI_USE_SSP1 FALSE +#define LPC_SPI_SSP0CLKDIV 1 +#define LPC_SPI_SSP1CLKDIV 1 +#define LPC_SPI_SSP0_IRQ_PRIORITY 1 +#define LPC_SPI_SSP1_IRQ_PRIORITY 1 +#define LPC_SPI_SSP_ERROR_HOOK(spip) chSysHalt() diff --git a/os/hal/platforms/LPC11Uxx/gpt_lld.c b/os/hal/platforms/LPC11Uxx/gpt_lld.c new file mode 100644 index 000000000..0d3963f78 --- /dev/null +++ b/os/hal/platforms/LPC11Uxx/gpt_lld.c @@ -0,0 +1,342 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file LPC11Uxx/gpt_lld.c + * @brief LPC11Uxx GPT subsystem low level driver source. + * + * @addtogroup GPT + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief GPT1 driver identifier. + * @note The driver GPT1 allocates the complex timer CT16B0 when enabled. + */ +#if LPC_GPT_USE_CT16B0 || defined(__DOXYGEN__) +GPTDriver GPTD1; +#endif + +/** + * @brief GPT2 driver identifier. + * @note The driver GPT2 allocates the timer CT16B1 when enabled. + */ +#if LPC_GPT_USE_CT16B1 || defined(__DOXYGEN__) +GPTDriver GPTD2; +#endif + +/** + * @brief GPT3 driver identifier. + * @note The driver GPT3 allocates the timer CT32B0 when enabled. + */ +#if LPC_GPT_USE_CT32B0 || defined(__DOXYGEN__) +GPTDriver GPTD3; +#endif + +/** + * @brief GPT4 driver identifier. + * @note The driver GPT4 allocates the timer CT32B1 when enabled. + */ +#if LPC_GPT_USE_CT32B1 || defined(__DOXYGEN__) +GPTDriver GPTD4; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Shared IRQ handler. + * + * @param[in] gptp pointer to a @p GPTDriver object + */ +static void gpt_lld_serve_interrupt(GPTDriver *gptp) { + + gptp->tmr->IR = 1; /* Clear interrupt on match MR0.*/ + if (gptp->state == GPT_ONESHOT) { + gptp->state = GPT_READY; /* Back in GPT_READY state. */ + gpt_lld_stop_timer(gptp); /* Timer automatically stopped. */ + } + gptp->config->callback(gptp); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if LPC_GPT_USE_CT16B0 +/** + * @brief CT16B0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector80) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD1); + + CH_IRQ_EPILOGUE(); +} +#endif /* LPC_GPT_USE_CT16B0 */ + +#if LPC_GPT_USE_CT16B1 +/** + * @brief CT16B1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector84) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD2); + + CH_IRQ_EPILOGUE(); +} +#endif /* LPC_GPT_USE_CT16B0 */ + +#if LPC_GPT_USE_CT32B0 +/** + * @brief CT32B0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector88) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD3); + + CH_IRQ_EPILOGUE(); +} +#endif /* LPC_GPT_USE_CT32B0 */ + +#if LPC_GPT_USE_CT32B1 +/** + * @brief CT32B1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector8C) { + + CH_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD4); + + CH_IRQ_EPILOGUE(); +} +#endif /* LPC_GPT_USE_CT32B1 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level GPT driver initialization. + * + * @notapi + */ +void gpt_lld_init(void) { + +#if LPC_GPT_USE_CT16B0 + /* Driver initialization.*/ + GPTD1.tmr = LPC_CT16B0; + gptObjectInit(&GPTD1); +#endif + +#if LPC_GPT_USE_CT16B1 + /* Driver initialization.*/ + GPTD2.tmr = LPC_CT16B1; + gptObjectInit(&GPTD2); +#endif + +#if LPC_GPT_USE_CT32B0 + /* Driver initialization.*/ + GPTD3.tmr = LPC_CT32B0; + gptObjectInit(&GPTD3); +#endif + +#if LPC_GPT_USE_CT32B1 + /* Driver initialization.*/ + GPTD4.tmr = LPC_CT32B1; + gptObjectInit(&GPTD4); +#endif +} + +/** + * @brief Configures and activates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_start(GPTDriver *gptp) { + uint32_t pr; + + if (gptp->state == GPT_STOP) { + /* Clock activation.*/ +#if LPC_GPT_USE_CT16B0 + if (&GPTD1 == gptp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 7); + nvicEnableVector(TIMER_16_0_IRQn, CORTEX_PRIORITY_MASK(2)); + } +#endif +#if LPC_GPT_USE_CT16B1 + if (&GPTD2 == gptp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 8); + nvicEnableVector(TIMER_16_1_IRQn, CORTEX_PRIORITY_MASK(3)); + } +#endif +#if LPC_GPT_USE_CT32B0 + if (&GPTD3 == gptp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 9); + nvicEnableVector(TIMER_32_0_IRQn, CORTEX_PRIORITY_MASK(2)); + } +#endif +#if LPC_GPT_USE_CT32B1 + if (&GPTD4 == gptp) { + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 10); + nvicEnableVector(TIMER_32_1_IRQn, CORTEX_PRIORITY_MASK(2)); + } +#endif + } + + /* Prescaler value calculation.*/ + pr = (uint16_t)((LPC_SYSCLK / gptp->config->frequency) - 1); + chDbgAssert(((uint32_t)(pr + 1) * gptp->config->frequency) == LPC_SYSCLK, + "gpt_lld_start(), #1", "invalid frequency"); + + /* Timer configuration.*/ + gptp->tmr->PR = pr; + gptp->tmr->IR = 1; + gptp->tmr->MCR = 0; + gptp->tmr->TCR = 0; +} + +/** + * @brief Deactivates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop(GPTDriver *gptp) { + + if (gptp->state == GPT_READY) { + gptp->tmr->MCR = 0; + gptp->tmr->TCR = 0; + +#if LPC_GPT_USE_CT16B0 + if (&GPTD1 == gptp) { + nvicDisableVector(TIMER_16_0_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 7); + } +#endif +#if LPC_GPT_USE_CT16B1 + if (&GPTD2 == gptp) { + nvicDisableVector(TIMER_16_1_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 8); + } +#endif +#if LPC_GPT_USE_CT32B0 + if (&GPTD3 == gptp) { + nvicDisableVector(TIMER_32_0_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 9); + } +#endif +#if LPC_GPT_USE_CT32B1 + if (&GPTD4 == gptp) { + nvicDisableVector(TIMER_32_1_IRQn); + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 10); + } +#endif + } +} + +/** + * @brief Starts the timer in continuous mode. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval period in ticks + * + * @notapi + */ +void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) { + + gptp->tmr->MR0 = interval - 1; + gptp->tmr->IR = 1; + gptp->tmr->MCR = 3; /* IRQ and clr TC on match MR0. */ + gptp->tmr->TCR = 2; /* Reset counter and prescaler. */ + gptp->tmr->TCR = 1; /* Timer enabled. */ +} + +/** + * @brief Stops the timer. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop_timer(GPTDriver *gptp) { + + gptp->tmr->IR = 1; + gptp->tmr->MCR = 0; + gptp->tmr->TCR = 0; +} + +/** + * @brief Starts the timer in one shot mode and waits for completion. + * @details This function specifically polls the timer waiting for completion + * in order to not have extra delays caused by interrupt servicing, + * this function is only recommended for short delays. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval time interval in ticks + * + * @notapi + */ +void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) { + + gptp->tmr->MR0 = interval - 1; + gptp->tmr->IR = 1; + gptp->tmr->MCR = 4; /* Stop TC on match MR0. */ + gptp->tmr->TCR = 2; /* Reset counter and prescaler. */ + gptp->tmr->TCR = 1; /* Timer enabled. */ + while (gptp->tmr->TCR & 1) + ; +} + +#endif /* HAL_USE_GPT */ + +/** @} */ diff --git a/os/hal/platforms/LPC11Uxx/gpt_lld.h b/os/hal/platforms/LPC11Uxx/gpt_lld.h new file mode 100644 index 000000000..e8d347b09 --- /dev/null +++ b/os/hal/platforms/LPC11Uxx/gpt_lld.h @@ -0,0 +1,208 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file LPC11Uxx/gpt_lld.h + * @brief LPC11Uxx GPT subsystem low level driver header. + * + * @addtogroup GPT + * @{ + */ + +#ifndef _GPT_LLD_H_ +#define _GPT_LLD_H_ + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief GPT1 driver enable switch. + * @details If set to @p TRUE the support for GPT1 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC_GPT_USE_CT16B0) || defined(__DOXYGEN__) +#define LPC_GPT_USE_CT16B0 TRUE +#endif + +/** + * @brief GPT2 driver enable switch. + * @details If set to @p TRUE the support for GPT2 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC_GPT_USE_CT16B1) || defined(__DOXYGEN__) +#define LPC_GPT_USE_CT16B1 TRUE +#endif + +/** + * @brief GPT3 driver enable switch. + * @details If set to @p TRUE the support for GPT3 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC_GPT_USE_CT32B0) || defined(__DOXYGEN__) +#define LPC_GPT_USE_CT32B0 TRUE +#endif + +/** + * @brief GPT4 driver enable switch. + * @details If set to @p TRUE the support for GPT4 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC_GPT_USE_CT32B1) || defined(__DOXYGEN__) +#define LPC_GPT_USE_CT32B1 TRUE +#endif + +/** + * @brief GPT1 interrupt priority level setting. + */ +#if !defined(LPC_GPT_CT16B0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC_GPT_CT16B0_IRQ_PRIORITY 2 +#endif + +/** + * @brief GPT2 interrupt priority level setting. + */ +#if !defined(LPC_GPT_CT16B1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC_GPT_CT16B1_IRQ_PRIORITY 2 +#endif + +/** + * @brief GPT3 interrupt priority level setting. + */ +#if !defined(LPC_GPT_CT32B0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC_GPT_CT32B0_IRQ_PRIORITY 2 +#endif + +/** + * @brief GPT4 interrupt priority level setting. + */ +#if !defined(LPC_GPT_CT32B1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC_GPT_CT32B1_IRQ_PRIORITY 2 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !LPC_GPT_USE_CT16B0 && !LPC_GPT_USE_CT16B1 && \ + !LPC_GPT_USE_CT32B0 && !LPC_GPT_USE_CT32B1 +#error "GPT driver activated but no CT peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief GPT frequency type. + */ +typedef uint32_t gptfreq_t; + +/** + * @brief GPT counter type. + */ +typedef uint32_t gptcnt_t; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + gptfreq_t frequency; + /** + * @brief Timer callback pointer. + * @note This callback is invoked on GPT counter events. + */ + gptcallback_t callback; + /* End of the mandatory fields.*/ +} GPTConfig; + +/** + * @brief Structure representing a GPT driver. + */ +struct GPTDriver { + /** + * @brief Driver state. + */ + gptstate_t state; + /** + * @brief Current configuration data. + */ + const GPTConfig *config; + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the CTxxBy registers block. + */ + LPC_CTxxBx_Type *tmr; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if LPC_GPT_USE_CT16B0 && !defined(__DOXYGEN__) +extern GPTDriver GPTD1; +#endif + +#if LPC_GPT_USE_CT16B1 && !defined(__DOXYGEN__) +extern GPTDriver GPTD2; +#endif + +#if LPC_GPT_USE_CT32B0 && !defined(__DOXYGEN__) +extern GPTDriver GPTD3; +#endif + +#if LPC_GPT_USE_CT32B1 && !defined(__DOXYGEN__) +extern GPTDriver GPTD4; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void gpt_lld_init(void); + void gpt_lld_start(GPTDriver *gptp); + void gpt_lld_stop(GPTDriver *gptp); + void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period); + void gpt_lld_stop_timer(GPTDriver *gptp); + void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_GPT */ + +#endif /* _GPT_LLD_H_ */ + +/** @} */ diff --git a/os/hal/platforms/LPC11Uxx/hal_lld.c b/os/hal/platforms/LPC11Uxx/hal_lld.c index 9b1fac622..fa33511fe 100644 --- a/os/hal/platforms/LPC11Uxx/hal_lld.c +++ b/os/hal/platforms/LPC11Uxx/hal_lld.c @@ -29,11 +29,6 @@ #include "ch.h" #include "hal.h" -/** - * @brief Register missing in NXP header file. - */ -#define FLASHCFG (*((volatile uint32_t *)0x4003C010)) - /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ @@ -81,7 +76,8 @@ void lpc_clock_init(void) { unsigned i; /* Flash wait states setting, the code takes care to not touch TBD bits.*/ - FLASHCFG = (FLASHCFG & ~3) | LPC_FLASHCFG_FLASHTIM; + LPC_FLASHCTRL->FLASHCFG = (LPC_FLASHCTRL->FLASHCFG & ~3) | + LPC_FLASHCFG_FLASHTIM; /* System oscillator initialization if required.*/ #if LPC_MAINCLK_SOURCE == SYSMAINCLKSEL_PLLOUT diff --git a/os/hal/platforms/LPC11Uxx/hal_lld.h b/os/hal/platforms/LPC11Uxx/hal_lld.h index a544dfa9a..2f2347ef2 100644 --- a/os/hal/platforms/LPC11Uxx/hal_lld.h +++ b/os/hal/platforms/LPC11Uxx/hal_lld.h @@ -109,7 +109,7 @@ /** * @brief Calculated SYSOSCCTRL setting. */ -#if (SYSOSCCLK < 18000000) || defined(__DOXYGEN__) +#if (SYSOSCCLK < 20000000) || defined(__DOXYGEN__) #define LPC_SYSOSCCTRL 0 #else #define LPC_SYSOSCCTRL 1 @@ -212,7 +212,7 @@ extern "C" { #endif void hal_lld_init(void); - void lpc111x_clock_init(void); + void lpc_clock_init(void); #ifdef __cplusplus } #endif diff --git a/os/hal/platforms/LPC11Uxx/platform.mk b/os/hal/platforms/LPC11Uxx/platform.mk index 3dc47e897..45495ec46 100644 --- a/os/hal/platforms/LPC11Uxx/platform.mk +++ b/os/hal/platforms/LPC11Uxx/platform.mk @@ -1,6 +1,8 @@ # List of all the LPC11Uxx platform files. PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/LPC11Uxx/hal_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC11Uxx/gpt_lld.c \ ${CHIBIOS}/os/hal/platforms/LPC11Uxx/pal_lld.c \ + ${CHIBIOS}/os/hal/platforms/LPC11Uxx/spi_lld.c \ ${CHIBIOS}/os/hal/platforms/LPC11Uxx/serial_lld.c # Required include directories diff --git a/os/hal/platforms/LPC11Uxx/serial_lld.c b/os/hal/platforms/LPC11Uxx/serial_lld.c index 4463a15ad..03bc9bbf9 100644 --- a/os/hal/platforms/LPC11Uxx/serial_lld.c +++ b/os/hal/platforms/LPC11Uxx/serial_lld.c @@ -56,13 +56,13 @@ static const SerialConfig default_config = { /*===========================================================================*/ /** - * @brief UART initialization. + * @brief USART initialization. * - * @param[in] sdp communication channel associated to the UART + * @param[in] sdp communication channel associated to the USART * @param[in] config the architecture-dependent serial driver configuration */ static void uart_init(SerialDriver *sdp, const SerialConfig *config) { - LPC_UART_TypeDef *u = sdp->uart; + LPC_USART_Type *u = sdp->uart; uint32_t div = LPC_SERIAL_UART0_PCLK / (config->sc_speed << 4); u->LCR = config->sc_lcr | LCR_DLAB; @@ -77,11 +77,11 @@ static void uart_init(SerialDriver *sdp, const SerialConfig *config) { } /** - * @brief UART de-initialization. + * @brief USART de-initialization. * - * @param[in] u pointer to an UART I/O block + * @param[in] u pointer to an USART I/O block */ -static void uart_deinit(LPC_UART_TypeDef *u) { +static void uart_deinit(LPC_USART_Type *u) { u->LCR = LCR_DLAB; u->DLL = 1; @@ -126,7 +126,7 @@ static void set_error(SerialDriver *sdp, IOREG32 err) { * @param[in] sdp communication channel associated to the UART */ static void serve_interrupt(SerialDriver *sdp) { - LPC_UART_TypeDef *u = sdp->uart; + LPC_USART_Type *u = sdp->uart; while (TRUE) { switch (u->IIR & IIR_SRC_MASK) { @@ -179,7 +179,7 @@ static void serve_interrupt(SerialDriver *sdp) { * @brief Attempts a TX FIFO preload. */ static void preload(SerialDriver *sdp) { - LPC_UART_TypeDef *u = sdp->uart; + LPC_USART_Type *u = sdp->uart; if (u->LSR & LSR_THRE) { int i = LPC_SERIAL_FIFO_PRELOAD; @@ -239,9 +239,7 @@ void sd_lld_init(void) { #if LPC_SERIAL_USE_UART0 sdObjectInit(&SD1, NULL, notify1); - SD1.uart = LPC_UART; - LPC_IOCON->PIO0_18 = 0x81; /* RDX without resistors. */ - LPC_IOCON->PIO0_19 = 0x81; /* TDX without resistors. */ + SD1.uart = LPC_USART; #endif } diff --git a/os/hal/platforms/LPC11Uxx/spi_lld.c b/os/hal/platforms/LPC11Uxx/spi_lld.c new file mode 100644 index 000000000..49fcf1913 --- /dev/null +++ b/os/hal/platforms/LPC11Uxx/spi_lld.c @@ -0,0 +1,395 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file LPC11Uxx/spi_lld.c + * @brief LPC11Uxx low level SPI driver code. + * + * @addtogroup SPI + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if LPC_SPI_USE_SSP0 || defined(__DOXYGEN__) +/** @brief SPI1 driver identifier.*/ +SPIDriver SPID1; +#endif + +#if LPC_SPI_USE_SSP1 || defined(__DOXYGEN__) +/** @brief SPI2 driver identifier.*/ +SPIDriver SPID2; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Preloads the transmit FIFO. + * + * @param[in] spip pointer to the @p SPIDriver object + */ +static void ssp_fifo_preload(SPIDriver *spip) { + LPC_SSPx_Type *ssp = spip->ssp; + uint32_t n = spip->txcnt > LPC_SSP_FIFO_DEPTH ? + LPC_SSP_FIFO_DEPTH : spip->txcnt; + + while(((ssp->SR & SR_TNF) != 0) && (n > 0)) { + if (spip->txptr != NULL) { + if ((ssp->CR0 & CR0_DSSMASK) > CR0_DSS8BIT) { + const uint16_t *p = spip->txptr; + ssp->DR = *p++; + spip->txptr = p; + } + else { + const uint8_t *p = spip->txptr; + ssp->DR = *p++; + spip->txptr = p; + } + } + else + ssp->DR = 0xFFFFFFFF; + n--; + spip->txcnt--; + } +} + +/** + * @brief Common IRQ handler. + * + * @param[in] spip pointer to the @p SPIDriver object + */ +static void spi_serve_interrupt(SPIDriver *spip) { + LPC_SSPx_Type *ssp = spip->ssp; + + if ((ssp->MIS & MIS_ROR) != 0) { + /* The overflow condition should never happen because priority is given + to receive but a hook macro is provided anyway...*/ + LPC_SPI_SSP_ERROR_HOOK(spip); + } + ssp->ICR = ICR_RT | ICR_ROR; + while ((ssp->SR & SR_RNE) != 0) { + if (spip->rxptr != NULL) { + if ((ssp->CR0 & CR0_DSSMASK) > CR0_DSS8BIT) { + uint16_t *p = spip->rxptr; + *p++ = ssp->DR; + spip->rxptr = p; + } + else { + uint8_t *p = spip->rxptr; + *p++ = ssp->DR; + spip->rxptr = p; + } + } + else + (void)ssp->DR; + if (--spip->rxcnt == 0) { + chDbgAssert(spip->txcnt == 0, + "spi_serve_interrupt(), #1", "counter out of synch"); + /* Stops the IRQ sources.*/ + ssp->IMSC = 0; + /* Portable SPI ISR code defined in the high level driver, note, it is + a macro.*/ + _spi_isr_code(spip); + return; + } + } + ssp_fifo_preload(spip); + if (spip->txcnt == 0) + ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_RX; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if LPC_SPI_USE_SSP0 || defined(__DOXYGEN__) +/** + * @brief SSP0 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector90) { + + CH_IRQ_PROLOGUE(); + + spi_serve_interrupt(&SPID1); + + CH_IRQ_EPILOGUE(); +} +#endif + +#if LPC_SPI_USE_SSP1 || defined(__DOXYGEN__) +/** + * @brief SSP1 interrupt handler. + * + * @isr + */ +CH_IRQ_HANDLER(Vector78) { + + CH_IRQ_PROLOGUE(); + + spi_serve_interrupt(&SPID2); + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SPI driver initialization. + * + * @notapi + */ +void spi_lld_init(void) { + +#if LPC_SPI_USE_SSP0 + spiObjectInit(&SPID1); + SPID1.ssp = LPC_SSP0; +#endif /* LPC_SPI_USE_SSP0 */ + +#if LPC_SPI_USE_SSP1 + spiObjectInit(&SPID2); + SPID2.ssp = LPC_SSP1; +#endif /* LPC_SPI_USE_SSP0 */ +} + +/** + * @brief Configures and activates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_start(SPIDriver *spip) { + + if (spip->state == SPI_STOP) { + /* Clock activation.*/ +#if LPC_SPI_USE_SSP0 + if (&SPID1 == spip) { + LPC_SYSCON->SSP0CLKDIV = LPC_SPI_SSP0CLKDIV; + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 11); + LPC_SYSCON->PRESETCTRL |= 1; + nvicEnableVector(SSP0_IRQn, + CORTEX_PRIORITY_MASK(LPC_SPI_SSP0_IRQ_PRIORITY)); + } +#endif +#if LPC_SPI_USE_SSP1 + if (&SPID2 == spip) { + LPC_SYSCON->SSP1CLKDIV = LPC_SPI_SSP1CLKDIV; + LPC_SYSCON->SYSAHBCLKCTRL |= (1 << 18); + LPC_SYSCON->PRESETCTRL |= 4; + nvicEnableVector(SSP1_IRQn, + CORTEX_PRIORITY_MASK(LPC_SPI_SSP1_IRQ_PRIORITY)); + } +#endif + } + /* Configuration.*/ + spip->ssp->CR1 = 0; + spip->ssp->ICR = ICR_RT | ICR_ROR; + spip->ssp->CR0 = spip->config->cr0; + spip->ssp->CPSR = spip->config->cpsr; + spip->ssp->CR1 = CR1_SSE; +} + +/** + * @brief Deactivates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_stop(SPIDriver *spip) { + + if (spip->state != SPI_STOP) { + spip->ssp->CR1 = 0; + spip->ssp->CR0 = 0; + spip->ssp->CPSR = 0; +#if LPC_SPI_USE_SSP0 + if (&SPID1 == spip) { + LPC_SYSCON->PRESETCTRL &= ~1; + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 11); + LPC_SYSCON->SSP0CLKDIV = 0; + nvicDisableVector(SSP0_IRQn); + } +#endif +#if LPC_SPI_USE_SSP1 + if (&SPID2 == spip) { + LPC_SYSCON->PRESETCTRL &= ~4; + LPC_SYSCON->SYSAHBCLKCTRL &= ~(1 << 18); + LPC_SYSCON->SSP1CLKDIV = 0; + nvicDisableVector(SSP1_IRQn); + } +#endif + } +} + +/** + * @brief Asserts the slave select signal and prepares for transfers. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_select(SPIDriver *spip) { + + palClearPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_unselect(SPIDriver *spip) { + + palSetPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Ignores data on the SPI bus. + * @details This function transmits a series of idle words on the SPI bus and + * ignores the received data. This function can be invoked even + * when a slave select signal has not been yet asserted. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * + * @notapi + */ +void spi_lld_ignore(SPIDriver *spip, size_t n) { + + spip->rxptr = NULL; + spip->txptr = NULL; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This asynchronous function starts a simultaneous transmit/receive + * operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf) { + + spip->rxptr = rxbuf; + spip->txptr = txbuf; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Sends data over the SPI bus. + * @details This asynchronous function starts a transmit operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) { + + spip->rxptr = NULL; + spip->txptr = txbuf; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Receives data from the SPI bus. + * @details This asynchronous function starts a receive operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) { + + spip->rxptr = rxbuf; + spip->txptr = NULL; + spip->rxcnt = spip->txcnt = n; + ssp_fifo_preload(spip); + spip->ssp->IMSC = IMSC_ROR | IMSC_RT | IMSC_TX | IMSC_RX; +} + +/** + * @brief Exchanges one frame using a polled wait. + * @details This synchronous function exchanges one frame using a polled + * synchronization method. This function is useful when exchanging + * small amount of data on high speed channels, usually in this + * situation is much more efficient just wait for completion using + * polling than suspending the thread waiting for an interrupt. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] frame the data frame to send over the SPI bus + * @return The received data frame from the SPI bus. + */ +uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) { + + spip->ssp->DR = (uint32_t)frame; + while ((spip->ssp->SR & SR_RNE) == 0) + ; + return (uint16_t)spip->ssp->DR; +} + +#endif /* HAL_USE_SPI */ + +/** @} */ diff --git a/os/hal/platforms/LPC11Uxx/spi_lld.h b/os/hal/platforms/LPC11Uxx/spi_lld.h new file mode 100644 index 000000000..2cd018406 --- /dev/null +++ b/os/hal/platforms/LPC11Uxx/spi_lld.h @@ -0,0 +1,315 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/** + * @file LPC11Uxx/spi_lld.h + * @brief LPC11Uxx low level SPI driver header. + * + * @addtogroup SPI + * @{ + */ + +#ifndef _SPI_LLD_H_ +#define _SPI_LLD_H_ + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Hardware FIFO depth. + */ +#define LPC_SSP_FIFO_DEPTH 8 + +#define CR0_DSSMASK 0x0F +#define CR0_DSS4BIT 3 +#define CR0_DSS5BIT 4 +#define CR0_DSS6BIT 5 +#define CR0_DSS7BIT 6 +#define CR0_DSS8BIT 7 +#define CR0_DSS9BIT 8 +#define CR0_DSS10BIT 9 +#define CR0_DSS11BIT 0xA +#define CR0_DSS12BIT 0xB +#define CR0_DSS13BIT 0xC +#define CR0_DSS14BIT 0xD +#define CR0_DSS15BIT 0xE +#define CR0_DSS16BIT 0xF +#define CR0_FRFSPI 0 +#define CR0_FRFSSI 0x10 +#define CR0_FRFMW 0x20 +#define CR0_CPOL 0x40 +#define CR0_CPHA 0x80 +#define CR0_CLOCKRATE(n) ((n) << 8) + +#define CR1_LBM 1 +#define CR1_SSE 2 +#define CR1_MS 4 +#define CR1_SOD 8 + +#define SR_TFE 1 +#define SR_TNF 2 +#define SR_RNE 4 +#define SR_RFF 8 +#define SR_BSY 16 + +#define IMSC_ROR 1 +#define IMSC_RT 2 +#define IMSC_RX 4 +#define IMSC_TX 8 + +#define RIS_ROR 1 +#define RIS_RT 2 +#define RIS_RX 4 +#define RIS_TX 8 + +#define MIS_ROR 1 +#define MIS_RT 2 +#define MIS_RX 4 +#define MIS_TX 8 + +#define ICR_ROR 1 +#define ICR_RT 2 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief SPI1 driver enable switch. + * @details If set to @p TRUE the support for device SSP0 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC_SPI_USE_SSP0) || defined(__DOXYGEN__) +#define LPC_SPI_USE_SSP0 TRUE +#endif + +/** + * @brief SPI2 driver enable switch. + * @details If set to @p TRUE the support for device SSP1 is included. + * @note The default is @p TRUE. + */ +#if !defined(LPC_SPI_USE_SSP1) || defined(__DOXYGEN__) +#define LPC_SPI_USE_SSP1 TRUE +#endif + +/** + * @brief SSP0 PCLK divider. + */ +#if !defined(LPC_SPI_SSP0CLKDIV) || defined(__DOXYGEN__) +#define LPC_SPI_SSP0CLKDIV 1 +#endif + +/** + * @brief SSP1 PCLK divider. + */ +#if !defined(LPC_SPI_SSP1CLKDIV) || defined(__DOXYGEN__) +#define LPC_SPI_SSP1CLKDIV 1 +#endif + +/** + * @brief SPI0 interrupt priority level setting. + */ +#if !defined(LPC_SPI_SSP0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC_SPI_SSP0_IRQ_PRIORITY 1 +#endif + +/** + * @brief SPI1 interrupt priority level setting. + */ +#if !defined(LPC_SPI_SSP1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define LPC_SPI_SSP1_IRQ_PRIORITY 1 +#endif + +/** + * @brief Overflow error hook. + * @details The default action is to stop the system. + */ +#if !defined(LPC_SPI_SSP_ERROR_HOOK) || defined(__DOXYGEN__) +#define LPC_SPI_SSP_ERROR_HOOK(spip) chSysHalt() +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if (LPC_SPI_SSP0CLKDIV < 1) || (LPC_SPI_SSP0CLKDIV > 255) +#error "invalid LPC_SPI_SSP0CLKDIV setting" +#endif + +#if (LPC_SPI_SSP1CLKDIV < 1) || (LPC_SPI_SSP1CLKDIV > 255) +#error "invalid LPC_SPI_SSP1CLKDIV setting" +#endif + +#if !LPC_SPI_USE_SSP0 && !LPC_SPI_USE_SSP1 +#error "SPI driver activated but no SPI peripheral assigned" +#endif + +/** + * @brief SSP0 clock. + */ +#define LPC_SPI_SSP0_PCLK \ + (LPC_MAINCLK / LPC_SPI_SSP0CLKDIV) + +/** + * @brief SSP1 clock. + */ +#define LPC_SPI_SSP1_PCLK \ + (LPC_MAINCLK / LPC_SPI_SSP1CLKDIV) + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an SPI driver. + */ +typedef struct SPIDriver SPIDriver; + +/** + * @brief SPI notification callback type. + * + * @param[in] spip pointer to the @p SPIDriver object triggering the + * callback + */ +typedef void (*spicallback_t)(SPIDriver *spip); + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief Operation complete callback or @p NULL. + */ + spicallback_t end_cb; + /* End of the mandatory fields.*/ + /** + * @brief The chip select line port. + */ + ioportid_t ssport; + /** + * @brief The chip select line pad number. + */ + uint16_t sspad; + /** + * @brief SSP CR0 initialization data. + */ + uint16_t cr0; + /** + * @brief SSP CPSR initialization data. + */ + uint32_t cpsr; +} SPIConfig; + +/** + * @brief Structure representing a SPI driver. + */ +struct SPIDriver { + /** + * @brief Driver state. + */ + spistate_t state; + /** + * @brief Current configuration data. + */ + const SPIConfig *config; +#if SPI_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + Thread *thread; +#endif /* SPI_USE_WAIT */ +#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + Mutex mutex; +#elif CH_USE_SEMAPHORES + Semaphore semaphore; +#endif +#endif /* SPI_USE_MUTUAL_EXCLUSION */ +#if defined(SPI_DRIVER_EXT_FIELDS) + SPI_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the SSP registers block. + */ + LPC_SSPx_Type *ssp; + /** + * @brief Number of bytes yet to be received. + */ + uint32_t rxcnt; + /** + * @brief Receive pointer or @p NULL. + */ + void *rxptr; + /** + * @brief Number of bytes yet to be transmitted. + */ + uint32_t txcnt; + /** + * @brief Transmit pointer or @p NULL. + */ + const void *txptr; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if LPC_SPI_USE_SSP0 && !defined(__DOXYGEN__) +extern SPIDriver SPID1; +#endif + +#if LPC_SPI_USE_SSP1 && !defined(__DOXYGEN__) +extern SPIDriver SPID2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void spi_lld_init(void); + void spi_lld_start(SPIDriver *spip); + void spi_lld_stop(SPIDriver *spip); + void spi_lld_select(SPIDriver *spip); + void spi_lld_unselect(SPIDriver *spip); + void spi_lld_ignore(SPIDriver *spip, size_t n); + void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf); + void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); + void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); + uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SPI */ + +#endif /* _SPI_LLD_H_ */ + +/** @} */ diff --git a/os/ports/GCC/ARMCMx/LPC11xx/ld/LPC1114.ld b/os/ports/GCC/ARMCMx/LPC11xx/ld/LPC1114.ld index c4f328a15..214cd3feb 100644 --- a/os/ports/GCC/ARMCMx/LPC11xx/ld/LPC1114.ld +++ b/os/ports/GCC/ARMCMx/LPC11xx/ld/LPC1114.ld @@ -21,8 +21,8 @@ /* * LPC1114 memory setup. */ -__main_stack_size__ = 0x0200; -__process_stack_size__ = 0x0200; +__main_stack_size__ = 0x0100; +__process_stack_size__ = 0x0100; MEMORY { diff --git a/os/ports/GCC/ARMCMx/LPC11xx/ld/LPC11U14.ld b/os/ports/GCC/ARMCMx/LPC11xx/ld/LPC11U14.ld new file mode 100644 index 000000000..4f7b3839c --- /dev/null +++ b/os/ports/GCC/ARMCMx/LPC11xx/ld/LPC11U14.ld @@ -0,0 +1,151 @@ +/* + ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, + 2011,2012 Giovanni Di Sirio. + + This file is part of ChibiOS/RT. + + ChibiOS/RT is free software; you can redistribute it and/or modify + it under the terms of the GNU General Public License as published by + the Free Software Foundation; either version 3 of the License, or + (at your option) any later version. + + ChibiOS/RT is distributed in the hope that it will be useful, + but WITHOUT ANY WARRANTY; without even the implied warranty of + MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + GNU General Public License for more details. + + You should have received a copy of the GNU General Public License + along with this program. If not, see . +*/ + +/* + * LPC11U14 memory setup. + */ +__main_stack_size__ = 0x0100; +__process_stack_size__ = 0x0100; + +MEMORY +{ + flash : org = 0x00000000, len = 32k + ram : org = 0x10000000, len = 4k + usbram : org = 0x20004000, len = 2k +} + +__ram_start__ = ORIGIN(ram); +__ram_size__ = LENGTH(ram); +__ram_end__ = __ram_start__ + __ram_size__; + +SECTIONS +{ + . = 0; + _text = .; + + startup : ALIGN(16) SUBALIGN(16) + { + KEEP(*(vectors)) + } > flash + + constructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE(__init_array_end = .); + } > flash + + destructors : ALIGN(4) SUBALIGN(4) + { + PROVIDE(__fini_array_start = .); + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + PROVIDE(__fini_array_end = .); + } > flash + + .text : ALIGN(16) SUBALIGN(16) + { + *(.text.startup.*) + *(.text) + *(.text.*) + *(.rodata) + *(.rodata.*) + *(.glue_7t) + *(.glue_7) + *(.gcc*) + } > flash + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } > flash + + .ARM.exidx : { + PROVIDE(__exidx_start = .); + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + PROVIDE(__exidx_end = .); + } > flash + + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > flash + + .eh_frame : ONLY_IF_RO + { + *(.eh_frame) + } > flash + + .textalign : ONLY_IF_RO + { + . = ALIGN(8); + } > flash + + _etext = .; + _textdata = _etext; + + .stacks : + { + . = ALIGN(8); + __main_stack_base__ = .; + . += __main_stack_size__; + . = ALIGN(8); + __main_stack_end__ = .; + __process_stack_base__ = .; + __main_thread_stack_base__ = .; + . += __process_stack_size__; + . = ALIGN(8); + __process_stack_end__ = .; + __main_thread_stack_end__ = .; + } > ram + + .data : + { + . = ALIGN(4); + PROVIDE(_data = .); + *(.data) + . = ALIGN(4); + *(.data.*) + . = ALIGN(4); + *(.ramtext) + . = ALIGN(4); + PROVIDE(_edata = .); + } > ram AT > flash + + .bss : + { + . = ALIGN(4); + PROVIDE(_bss_start = .); + *(.bss) + . = ALIGN(4); + *(.bss.*) + . = ALIGN(4); + *(COMMON) + . = ALIGN(4); + PROVIDE(_bss_end = .); + } > ram +} + +PROVIDE(end = .); +_end = .; + +__heap_base__ = _end; +__heap_end__ = __ram_end__; diff --git a/os/ports/GCC/ARMCMx/LPC13xx/ld/LPC1343.ld b/os/ports/GCC/ARMCMx/LPC13xx/ld/LPC1343.ld index 4431d7a75..4e801eae9 100644 --- a/os/ports/GCC/ARMCMx/LPC13xx/ld/LPC1343.ld +++ b/os/ports/GCC/ARMCMx/LPC13xx/ld/LPC1343.ld @@ -21,8 +21,8 @@ /* * LPC1343 memory setup. */ -__main_stack_size__ = 0x0200; -__process_stack_size__ = 0x0200; +__main_stack_size__ = 0x0100; +__process_stack_size__ = 0x0100; MEMORY { -- cgit v1.2.3