From 5c969f63735eae2c813969bf41ee062c47b1da1b Mon Sep 17 00:00:00 2001 From: Rocco Marco Guglielmi Date: Wed, 24 Aug 2016 12:49:43 +0000 Subject: Fixed Bug #769. git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9739 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- os/hal/ports/STM32/STM32L0xx/hal_lld.h | 6 +++--- readme.txt | 2 ++ 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/os/hal/ports/STM32/STM32L0xx/hal_lld.h b/os/hal/ports/STM32/STM32L0xx/hal_lld.h index bd295856b..843e66dff 100644 --- a/os/hal/ports/STM32/STM32L0xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32L0xx/hal_lld.h @@ -273,9 +273,9 @@ #define STM32_LPTIM1SEL_HSI16 (2 << 18) /**< LPTIM1 clock is HSI16. */ #define STM32_LPTIM1SEL_LSE (3 << 18) /**< LPTIM1 clock is LSE. */ -#define STM32_HSI48SEL_MASK (1 << 27) /**< HSI48SEL clock source mask.*/ -#define STM32_HSI48SEL_USBPLL (0 << 27) /**< USB48 clock is PLL/2. */ -#define STM32_HSI48SEL_HSI48 (1 << 27) /**< USB48 clock is HSI48. */ +#define STM32_HSI48SEL_MASK (1 << 26) /**< HSI48SEL clock source mask.*/ +#define STM32_HSI48SEL_USBPLL (0 << 26) /**< USB48 clock is PLL/2. */ +#define STM32_HSI48SEL_HSI48 (1 << 26) /**< USB48 clock is HSI48. */ /** @} */ /*===========================================================================*/ diff --git a/readme.txt b/readme.txt index f3b5dd7d0..eed9540d3 100644 --- a/readme.txt +++ b/readme.txt @@ -123,6 +123,8 @@ - RT: Merged RT4. - NIL: Merged NIL2. - NIL: Added STM32F7 demo. +- HAL: Fixed wrong bit mask in STM32L0xx port (bug #769) (backported to 16.1.6) + (bug #768)(backported to 16.1.6). - HAL: Fixed potential wait states problem in STM32L4 initialization code (bug #768)(backported to 16.1.6). - HAL: Fixed SDIO driver not compiling on STM32F446 devices (bug #767) -- cgit v1.2.3