From 3b1848ed5158ed122867cbccfff376fb92b15f0b Mon Sep 17 00:00:00 2001 From: Rocco Marco Guglielmi Date: Fri, 24 Jun 2016 13:56:30 +0000 Subject: Added initial support for STM32F769I Discovery git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@9660 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- demos/STM32/RT-STM32F769I-DISCOVERY/.cproject | 50 + demos/STM32/RT-STM32F769I-DISCOVERY/.project | 95 ++ demos/STM32/RT-STM32F769I-DISCOVERY/Makefile | 218 +++ demos/STM32/RT-STM32F769I-DISCOVERY/chconf.h | 520 ++++++ ...F769I-DISCOVERY (OpenOCD, Flash and Run).launch | 52 + demos/STM32/RT-STM32F769I-DISCOVERY/halconf.h | 388 +++++ demos/STM32/RT-STM32F769I-DISCOVERY/main.c | 78 + demos/STM32/RT-STM32F769I-DISCOVERY/mcuconf.h | 386 +++++ demos/STM32/RT-STM32F769I-DISCOVERY/readme.txt | 25 + os/hal/boards/ST_STM32F769I_DISCOVERY/board.c | 132 ++ os/hal/boards/ST_STM32F769I_DISCOVERY/board.h | 1744 ++++++++++++++++++++ os/hal/boards/ST_STM32F769I_DISCOVERY/board.mk | 5 + .../boards/ST_STM32F769I_DISCOVERY/cfg/board.chcfg | 1466 ++++++++++++++++ os/hal/ports/STM32/STM32F7xx/hal_lld.h | 3 + os/hal/ports/STM32/STM32F7xx/stm32_registry.h | 4 +- 15 files changed, 5164 insertions(+), 2 deletions(-) create mode 100644 demos/STM32/RT-STM32F769I-DISCOVERY/.cproject create mode 100644 demos/STM32/RT-STM32F769I-DISCOVERY/.project create mode 100644 demos/STM32/RT-STM32F769I-DISCOVERY/Makefile create mode 100644 demos/STM32/RT-STM32F769I-DISCOVERY/chconf.h create mode 100644 demos/STM32/RT-STM32F769I-DISCOVERY/debug/RT-STM32F769I-DISCOVERY (OpenOCD, Flash and Run).launch create mode 100644 demos/STM32/RT-STM32F769I-DISCOVERY/halconf.h create mode 100644 demos/STM32/RT-STM32F769I-DISCOVERY/main.c create mode 100644 demos/STM32/RT-STM32F769I-DISCOVERY/mcuconf.h create mode 100644 demos/STM32/RT-STM32F769I-DISCOVERY/readme.txt create mode 100644 os/hal/boards/ST_STM32F769I_DISCOVERY/board.c create mode 100644 os/hal/boards/ST_STM32F769I_DISCOVERY/board.h create mode 100644 os/hal/boards/ST_STM32F769I_DISCOVERY/board.mk create mode 100644 os/hal/boards/ST_STM32F769I_DISCOVERY/cfg/board.chcfg diff --git a/demos/STM32/RT-STM32F769I-DISCOVERY/.cproject b/demos/STM32/RT-STM32F769I-DISCOVERY/.cproject new file mode 100644 index 000000000..3fd8a8ea2 --- /dev/null +++ b/demos/STM32/RT-STM32F769I-DISCOVERY/.cproject @@ -0,0 +1,50 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/STM32/RT-STM32F769I-DISCOVERY/.project b/demos/STM32/RT-STM32F769I-DISCOVERY/.project new file mode 100644 index 000000000..84110bb4d --- /dev/null +++ b/demos/STM32/RT-STM32F769I-DISCOVERY/.project @@ -0,0 +1,95 @@ + + + RT-STM32F769I-DISCOVERY + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + -j1 + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/os/hal/boards/ST_STM32F769I_DISCOVERY + + + os + 2 + CHIBIOS/os + + + test + 2 + CHIBIOS/test + + + diff --git a/demos/STM32/RT-STM32F769I-DISCOVERY/Makefile b/demos/STM32/RT-STM32F769I-DISCOVERY/Makefile new file mode 100644 index 000000000..74c55f61c --- /dev/null +++ b/demos/STM32/RT-STM32F769I-DISCOVERY/Makefile @@ -0,0 +1,218 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = yes +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +# Startup files. +include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f7xx.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/hal/ports/STM32/STM32F7xx/platform.mk +include $(CHIBIOS)/os/hal/boards/ST_STM32F769I_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Other files (optional). +include $(CHIBIOS)/test/rt/test.mk + +# Define linker script file here +LDSCRIPT= $(STARTUPLD)/STM32F769Ix.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(STARTUPSRC) \ + $(KERNSRC) \ + $(PORTSRC) \ + $(OSALSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(TESTSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = +ASMXSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) + +INCDIR = $(CHIBIOS)/os/license \ + $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-m4 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra -Wundef + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC +include $(RULESPATH)/rules.mk diff --git a/demos/STM32/RT-STM32F769I-DISCOVERY/chconf.h b/demos/STM32/RT-STM32F769I-DISCOVERY/chconf.h new file mode 100644 index 000000000..ad6b53ade --- /dev/null +++ b/demos/STM32/RT-STM32F769I-DISCOVERY/chconf.h @@ -0,0 +1,520 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 10000 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 2 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM TRUE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES TRUE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS TRUE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES TRUE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_BUFFER_SIZE 128 + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p chThdInit() API. + * + * @note It is invoked from within @p chThdInit() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/demos/STM32/RT-STM32F769I-DISCOVERY/debug/RT-STM32F769I-DISCOVERY (OpenOCD, Flash and Run).launch b/demos/STM32/RT-STM32F769I-DISCOVERY/debug/RT-STM32F769I-DISCOVERY (OpenOCD, Flash and Run).launch new file mode 100644 index 000000000..25e64adf8 --- /dev/null +++ b/demos/STM32/RT-STM32F769I-DISCOVERY/debug/RT-STM32F769I-DISCOVERY (OpenOCD, Flash and Run).launch @@ -0,0 +1,52 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/STM32/RT-STM32F769I-DISCOVERY/halconf.h b/demos/STM32/RT-STM32F769I-DISCOVERY/halconf.h new file mode 100644 index 000000000..82602b403 --- /dev/null +++ b/demos/STM32/RT-STM32F769I-DISCOVERY/halconf.h @@ -0,0 +1,388 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the QSPI subsystem. + */ +#if !defined(HAL_USE_QSPI) || defined(__DOXYGEN__) +#define HAL_USE_QSPI FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/demos/STM32/RT-STM32F769I-DISCOVERY/main.c b/demos/STM32/RT-STM32F769I-DISCOVERY/main.c new file mode 100644 index 000000000..ba9ae86a1 --- /dev/null +++ b/demos/STM32/RT-STM32F769I-DISCOVERY/main.c @@ -0,0 +1,78 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "ch_test.h" + +/* + * This is a periodic thread that does absolutely nothing except flashing + * a LED. + */ +static THD_WORKING_AREA(waThread1, 128); +static THD_FUNCTION(Thread1, arg) { + + (void)arg; + chRegSetThreadName("blinker"); + while (true) { + palSetLine(LINE_LED2_GREEN); + chThdSleepMilliseconds(500); + palClearLine(LINE_LED2_GREEN); + chThdSleepMilliseconds(500); + } +} + +/* + * Application entry point. + */ +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + * ARD_D13 is programmed as output (board LED). + */ + palClearLine(LINE_ARD_D13); + palSetLineMode(LINE_ARD_D13, PAL_MODE_OUTPUT_PUSHPULL); + + /* + * Activates the serial driver 1 using the driver default configuration. + */ + sdStart(&SD1, NULL); + + /* + * Creates the example thread. + */ + chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state. + */ + while (true) { + if (palReadLine(LINE_BUTTON_USER)) + test_execute((BaseSequentialStream *)&SD1); + chThdSleepMilliseconds(500); + } +} diff --git a/demos/STM32/RT-STM32F769I-DISCOVERY/mcuconf.h b/demos/STM32/RT-STM32F769I-DISCOVERY/mcuconf.h new file mode 100644 index 000000000..76c2d482e --- /dev/null +++ b/demos/STM32/RT-STM32F769I-DISCOVERY/mcuconf.h @@ -0,0 +1,386 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F7xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED TRUE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 25 +#define STM32_PLLN_VALUE 432 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSE +#define STM32_RTCPRE_VALUE 25 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV4 +#define STM32_I2SSRC STM32_I2SSRC_PLLI2S +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SP_VALUE 4 +#define STM32_PLLI2SQ_VALUE 4 +#define STM32_PLLI2SR_VALUE 4 +#define STM32_PLLSAIN_VALUE 192 +#define STM32_PLLSAIP_VALUE 4 +#define STM32_PLLSAIQ_VALUE 4 +#define STM32_PLLSAIR_VALUE 4 +#define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_OFF +#define STM32_SAI1SEL STM32_SAI1SEL_OFF +#define STM32_SAI2SEL STM32_SAI2SEL_OFF +#define STM32_USART1SEL STM32_USART1SEL_PCLK2 +#define STM32_USART2SEL STM32_USART2SEL_PCLK1 +#define STM32_USART3SEL STM32_USART3SEL_PCLK1 +#define STM32_UART4SEL STM32_UART4SEL_PCLK1 +#define STM32_UART5SEL STM32_UART5SEL_PCLK1 +#define STM32_USART6SEL STM32_USART6SEL_PCLK2 +#define STM32_UART7SEL STM32_UART7SEL_PCLK1 +#define STM32_UART8SEL STM32_UART8SEL_PCLK1 +#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1 +#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1 +#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1 +#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1 +#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1 +#define STM32_CECSEL STM32_CECSEL_LSE +#define STM32_CK48MSEL STM32_CK48MSEL_PLL +#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK +#define STM32_SRAM2_NOCACHE FALSE + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_USE_I2C4 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C4_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_I2C4_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_USE_SDMMC1 FALSE +#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDMMC_WRITE_TIMEOUT 1000 +#define STM32_SDC_SDMMC_READ_TIMEOUT 1000 +#define STM32_SDC_SDMMC_CLOCK_DELAY 10 +#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SDC_SDMMC1_DMA_PRIORITY 3 +#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9 + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 TRUE +#define STM32_SERIAL_USE_USART2 FALSE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USE_UART7 FALSE +#define STM32_SERIAL_USE_UART8 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 +#define STM32_SERIAL_UART7_PRIORITY 12 +#define STM32_SERIAL_UART8_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_USE_SPI4 FALSE +#define STM32_SPI_USE_SPI5 FALSE +#define STM32_SPI_USE_SPI6 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI4_DMA_PRIORITY 1 +#define STM32_SPI_SPI5_DMA_PRIORITY 1 +#define STM32_SPI_SPI6_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_SPI4_IRQ_PRIORITY 10 +#define STM32_SPI_SPI5_IRQ_PRIORITY 10 +#define STM32_SPI_SPI6_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USE_UART7 FALSE +#define STM32_UART_USE_UART8 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_UART7_DMA_PRIORITY 0 +#define STM32_UART_UART8_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +#endif /* MCUCONF_H */ diff --git a/demos/STM32/RT-STM32F769I-DISCOVERY/readme.txt b/demos/STM32/RT-STM32F769I-DISCOVERY/readme.txt new file mode 100644 index 000000000..2ab23ce41 --- /dev/null +++ b/demos/STM32/RT-STM32F769I-DISCOVERY/readme.txt @@ -0,0 +1,25 @@ +***************************************************************************** +** ChibiOS/RT port for ARM-Cortex-M7 STM32F746G. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an ST STM32F769I-Discovery board. + +** The Demo ** + + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. just modify the TRGT line in the makefile in order to use +different GCC toolchains. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/os/hal/boards/ST_STM32F769I_DISCOVERY/board.c b/os/hal/boards/ST_STM32F769I_DISCOVERY/board.c new file mode 100644 index 000000000..9e8d10bc1 --- /dev/null +++ b/os/hal/boards/ST_STM32F769I_DISCOVERY/board.c @@ -0,0 +1,132 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +const PALConfig pal_default_config = { +#if STM32_HAS_GPIOA + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, +#endif +#if STM32_HAS_GPIOB + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, +#endif +#if STM32_HAS_GPIOC + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, +#endif +#if STM32_HAS_GPIOD + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, +#endif +#if STM32_HAS_GPIOE + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, +#endif +#if STM32_HAS_GPIOF + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, +#endif +#if STM32_HAS_GPIOG + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, +#endif +#if STM32_HAS_GPIOH + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, +#endif +#if STM32_HAS_GPIOI + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, +#endif +#if STM32_HAS_GPIOJ + {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, + VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, +#endif +#if STM32_HAS_GPIOK + {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, + VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} +#endif +}; +#endif + +/** + * @brief Early initialization code. + * @details This initialization must be performed just after stack setup + * and before any other initialization. + */ +void __early_init(void) { + + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + + return !palReadPad(GPIOC, GPIOC_SD_DETECT); +} + +/** + * @brief SDC card write protection detection. + */ +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return true; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { +} diff --git a/os/hal/boards/ST_STM32F769I_DISCOVERY/board.h b/os/hal/boards/ST_STM32F769I_DISCOVERY/board.h new file mode 100644 index 000000000..45ba14321 --- /dev/null +++ b/os/hal/boards/ST_STM32F769I_DISCOVERY/board.h @@ -0,0 +1,1744 @@ +/* + ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for STMicroelectronics STM32F769I-Discovery board. + */ + +/* + * Board identifier. + */ +#define BOARD_ST_STM32F769I_DISCOVERY +#define BOARD_NAME "STMicroelectronics STM32F769I-Discovery" + +/* + * Ethernet PHY type. + */ +#define BOARD_PHY_ID MII_LAN8742A_ID +#define BOARD_PHY_RMII + +/* + * The board has an ULPI USB PHY. + */ +#define BOARD_OTG2_USES_ULPI + +/* + * Board oscillators-related settings. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 32768U +#endif + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 25000000U +#endif + +#define STM32_HSE_BYPASS + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 300U + +/* + * MCU type as defined in the ST header. + */ +#define STM32F769xx + +/* + * IO pins assignments. + */ +#define GPIOA_BUTTON_USER 0U +#define GPIOA_RMII_REF_CLK 1U +#define GPIOA_RMII_MDIO 2U +#define GPIOA_ULPI_D0 3U +#define GPIOA_ARD_A1 4U +#define GPIOA_ULPI_CK 5U +#define GPIOA_ARD_A0 6U +#define GPIOA_RMII_CRS_DV 7U +#define GPIOA_CEC_CLK 8U +#define GPIOA_VCP_TX 9U +#define GPIOA_VCP_RX 10U +#define GPIOA_ARD_D10 11U +#define GPIOA_ARD_D13 12U +#define GPIOA_SWDIO 13U +#define GPIOA_SWCLK 14U +#define GPIOA_CEC 15U + +#define GPIOB_ULPI_D1 0U +#define GPIOB_ULPI_D2 1U +#define GPIOB_QSPI_CLK 2U +#define GPIOB_SD_D2 3U +#define GPIOB_SD_D3 4U +#define GPIOB_ULPI_D7 5U +#define GPIOB_QSPI_NCS 6U +#define GPIOB_AUDIO_SDA 7U +#define GPIOB_LCD_SDA 7U +#define GPIOB_ARD_D15 8U +#define GPIOB_ARD_D14 9U +#define GPIOB_ULPI_D3 10U +#define GPIOB_ULPI_D4 11U +#define GPIOB_ULPI_D5 12U +#define GPIOB_ULPI_D6 13U +#define GPIOB_ARD_D12 14U +#define GPIOB_ARD_D11 15U + +#define GPIOC_ULPI_STP 0U +#define GPIOC_RMII_MDC 1U +#define GPIOC_ARD_A2 2U +#define GPIOC_DFSDM_DATIN1 3U +#define GPIOC_RMII_RXD0 4U +#define GPIOC_RMII_RXD1 5U +#define GPIOC_ARD_D1 6U +#define GPIOC_ARD_D0 7U +#define GPIOC_ARD_D5 8U +#define GPIOC_QSPI_D0 9U +#define GPIOC_QSPI_D1 10U +#define GPIOC_DFSDM_DATIN5 11U +#define GPIOC_WIFI_RX 12U +#define GPIOC_PIN13 13U +#define GPIOC_OSC32_IN 14U +#define GPIOC_OSC32_OUT 15U + +#define GPIOD_FMC_D2 0U +#define GPIOD_FMC_D3 1U +#define GPIOD_WIFI_TX 2U +#define GPIOD_DFSDM_CKOUT 3U +#define GPIOD_OTG_HS_OVER_CURRENT 4U +#define GPIOD_RMII_RXER 5U +#define GPIOD_SD_CLK 6U +#define GPIOD_SD_CMD 7U +#define GPIOD_FMC_D13 8U +#define GPIOD_FMC_D14 9U +#define GPIOD_FMC_D15 10U +#define GPIOD_SPDIF_I2S 11U +#define GPIOD_AUDIO_SCL 12U +#define GPIOD_LCD_SCL 12U +#define GPIOD_QSPI_D3 13U +#define GPIOD_FMC_D0 14U +#define GPIOD_FMC_D1 15U + +#define GPIOE_FMC_NBL0 0U +#define GPIOE_FMC_NBL1 1U +#define GPIOE_QSPI_D2 2U +#define GPIOE_SAI1_SDB 3U +#define GPIOE_SAI1_FSA 4U +#define GPIOE_SAI1_SCKA 5U +#define GPIOE_SAI1_SDA 6U +#define GPIOE_FMC_D4 7U +#define GPIOE_FMC_D5 8U +#define GPIOE_FMC_D6 9U +#define GPIOE_FMC_D7 10U +#define GPIOE_FMC_D8 11U +#define GPIOE_FMC_D9 12U +#define GPIOE_FMC_D10 13U +#define GPIOE_FMC_11 14U +#define GPIOE_FMC_D12 15U + +#define GPIOF_FMC_A0 0U +#define GPIOF_FMC_A1 1U +#define GPIOF_FMC_A2 2U +#define GPIOF_FMC_A3 3U +#define GPIOF_FMC_A4 4U +#define GPIOF_FMC_A5 5U +#define GPIOF_ARD_D3 6U +#define GPIOF_ARD_D6 7U +#define GPIOF_ARD_A4 8U +#define GPIOF_ARD_A5 9U +#define GPIOF_ARD_A3 10U +#define GPIOF_FMC_SDNRAS 11U +#define GPIOF_FMC_A6 12U +#define GPIOF_FMC_A7 13U +#define GPIOF_FMC_A8 14U +#define GPIOF_FMC_A9 15U + +#define GPIOG_FMC_A10 0U +#define GPIOG_FMC_A11 1U +#define GPIOG_FMC_A12 2U +#define GPIOG_EXT_SCL 3U +#define GPIOG_FMC_BA0 4U +#define GPIOG_FMC_BA1 5U +#define GPIOG_EXT_SDA 6U +#define GPIOG_SAI1_MCLKA 7U +#define GPIOG_FMC_SDCLK 8U +#define GPIOG_SD_D0 9U +#define GPIOG_SD_D1 10U +#define GPIOG_RMII_TX_EN 11U +#define GPIOG_SPDIF_RX 12U +#define GPIOG_RMII_TXD0 13U +#define GPIOG_RMII_TXD1 14U +#define GPIOG_FMC_SDNCAS 15U + +#define GPIOH_OSC_IN 0U +#define GPIOH_OSC_OUT 1U +#define GPIOH_FMC_SDCKE0 2U +#define GPIOH_FMC_SDNE0 3U +#define GPIOH_ULPI_NXT 4U +#define GPIOH_FMC_SDNWE 5U +#define GPIOH_ARD_D9 6U +#define GPIOH_EXT_RST 7U +#define GPIOH_FMC_D16 8U +#define GPIOH_FMC_D17 9U +#define GPIOH_FMC_D18 10U +#define GPIOH_FMC_D19 11U +#define GPIOH_FMC_D20 12U +#define GPIOH_FMC_D21 13U +#define GPIOH_FMC_D22 14U +#define GPIOH_FMC_D23 15U + +#define GPIOI_FMC_D24 0U +#define GPIOI_FMC_D25 1U +#define GPIOI_FMC_D26 2U +#define GPIOI_FMC_D27 3U +#define GPIOI_FMC_NBL2 4U +#define GPIOI_FMC_NBL3 5U +#define GPIOI_FMC_D28 6U +#define GPIOI_FMC_D29 7U +#define GPIOI_PIN8 8U +#define GPIOI_FMC_D30 9U +#define GPIOI_FMC_D31 10U +#define GPIOI_ULPI_DIR 11U +#define GPIOI_PIN12 12U +#define GPIOI_LCD_INT 13U +#define GPIOI_LCD_BL_CTRL 14U +#define GPIOI_SD_DETECT 15U + +#define GPIOJ_ARD_D4 0U +#define GPIOJ_ARD_D2 1U +#define GPIOJ_DSI_TE 2U +#define GPIOJ_ARD_D7 3U +#define GPIOJ_ARD_D8 4U +#define GPIOJ_LED2_GREEN 5U +#define GPIOJ_PIN6 6U +#define GPIOJ_PIN7 7U +#define GPIOJ_PIN8 8U +#define GPIOJ_PIN9 9U +#define GPIOJ_PIN10 10U +#define GPIOJ_PIN11 11U +#define GPIOJ_AUDIO_INT 12U +#define GPIOJ_LED1_RED 13U +#define GPIOJ_WIFI_RST 14U +#define GPIOJ_DSI_RESET 15U + +#define GPIOK_PIN0 0U +#define GPIOK_PIN1 1U +#define GPIOK_PIN2 2U +#define GPIOK_PIN3 3U +#define GPIOK_PIN4 4U +#define GPIOK_PIN5 5U +#define GPIOK_PIN6 6U +#define GPIOK_PIN7 7U +#define GPIOK_PIN8 8U +#define GPIOK_PIN9 9U +#define GPIOK_PIN10 10U +#define GPIOK_PIN11 11U +#define GPIOK_PIN12 12U +#define GPIOK_PIN13 13U +#define GPIOK_PIN14 14U +#define GPIOK_PIN15 15U + +/* + * IO lines assignments. + */ +#define LINE_BUTTON_USER PAL_LINE(GPIOA, 0U) +#define LINE_RMII_REF_CLK PAL_LINE(GPIOA, 1U) +#define LINE_RMII_MDIO PAL_LINE(GPIOA, 2U) +#define LINE_ULPI_D0 PAL_LINE(GPIOA, 3U) +#define LINE_ARD_A1 PAL_LINE(GPIOA, 4U) +#define LINE_ULPI_CK PAL_LINE(GPIOA, 5U) +#define LINE_ARD_A0 PAL_LINE(GPIOA, 6U) +#define LINE_RMII_CRS_DV PAL_LINE(GPIOA, 7U) +#define LINE_CEC_CLK PAL_LINE(GPIOA, 8U) +#define LINE_VCP_TX PAL_LINE(GPIOA, 9U) +#define LINE_VCP_RX PAL_LINE(GPIOA, 10U) +#define LINE_ARD_D10 PAL_LINE(GPIOA, 11U) +#define LINE_ARD_D13 PAL_LINE(GPIOA, 12U) +#define LINE_SWDIO PAL_LINE(GPIOA, 13U) +#define LINE_SWCLK PAL_LINE(GPIOA, 14U) +#define LINE_CEC PAL_LINE(GPIOA, 15U) + +#define LINE_ULPI_D1 PAL_LINE(GPIOB, 0U) +#define LINE_ULPI_D2 PAL_LINE(GPIOB, 1U) +#define LINE_QSPI_CLK PAL_LINE(GPIOB, 2U) +#define LINE_SD_D2 PAL_LINE(GPIOB, 3U) +#define LINE_SD_D3 PAL_LINE(GPIOB, 4U) +#define LINE_ULPI_D7 PAL_LINE(GPIOB, 5U) +#define LINE_QSPI_NCS PAL_LINE(GPIOB, 6U) +#define LINE_AUDIO_SDA PAL_LINE(GPIOB, 7U) +#define LINE_LCD_SDA PAL_LINE(GPIOB, 7U) +#define LINE_ARD_D15 PAL_LINE(GPIOB, 8U) +#define LINE_ARD_D14 PAL_LINE(GPIOB, 9U) +#define LINE_ULPI_D3 PAL_LINE(GPIOB, 10U) +#define LINE_ULPI_D4 PAL_LINE(GPIOB, 11U) +#define LINE_ULPI_D5 PAL_LINE(GPIOB, 12U) +#define LINE_ULPI_D6 PAL_LINE(GPIOB, 13U) +#define LINE_ARD_D12 PAL_LINE(GPIOB, 14U) +#define LINE_ARD_D11 PAL_LINE(GPIOB, 15U) + +#define LINE_ULPI_STP PAL_LINE(GPIOC, 0U) +#define LINE_RMII_MDC PAL_LINE(GPIOC, 1U) +#define LINE_ARD_A2 PAL_LINE(GPIOC, 2U) +#define LINE_DFSDM_DATIN1 PAL_LINE(GPIOC, 3U) +#define LINE_RMII_RXD0 PAL_LINE(GPIOC, 4U) +#define LINE_RMII_RXD1 PAL_LINE(GPIOC, 5U) +#define LINE_ARD_D1 PAL_LINE(GPIOC, 6U) +#define LINE_ARD_D0 PAL_LINE(GPIOC, 7U) +#define LINE_ARD_D5 PAL_LINE(GPIOC, 8U) +#define LINE_QSPI_D0 PAL_LINE(GPIOC, 9U) +#define LINE_QSPI_D1 PAL_LINE(GPIOC, 10U) +#define LINE_DFSDM_DATIN5 PAL_LINE(GPIOC, 11U) +#define LINE_WIFI_RX PAL_LINE(GPIOC, 12U) +#define LINE_OSC32_IN PAL_LINE(GPIOC, 14U) +#define LINE_OSC32_OUT PAL_LINE(GPIOC, 15U) + +#define LINE_FMC_D2 PAL_LINE(GPIOD, 0U) +#define LINE_FMC_D3 PAL_LINE(GPIOD, 1U) +#define LINE_WIFI_TX PAL_LINE(GPIOD, 2U) +#define LINE_DFSDM_CKOUT PAL_LINE(GPIOD, 3U) +#define LINE_OTG_HS_OVER_CURRENT PAL_LINE(GPIOD, 4U) +#define LINE_RMII_RXER PAL_LINE(GPIOD, 5U) +#define LINE_SD_CLK PAL_LINE(GPIOD, 6U) +#define LINE_SD_CMD PAL_LINE(GPIOD, 7U) +#define LINE_FMC_D13 PAL_LINE(GPIOD, 8U) +#define LINE_FMC_D14 PAL_LINE(GPIOD, 9U) +#define LINE_FMC_D15 PAL_LINE(GPIOD, 10U) +#define LINE_SPDIF_I2S PAL_LINE(GPIOD, 11U) +#define LINE_AUDIO_SCL PAL_LINE(GPIOD, 12U) +#define LINE_LCD_SCL PAL_LINE(GPIOD, 12U) +#define LINE_QSPI_D3 PAL_LINE(GPIOD, 13U) +#define LINE_FMC_D0 PAL_LINE(GPIOD, 14U) +#define LINE_FMC_D1 PAL_LINE(GPIOD, 15U) + +#define LINE_FMC_NBL0 PAL_LINE(GPIOE, 0U) +#define LINE_FMC_NBL1 PAL_LINE(GPIOE, 1U) +#define LINE_QSPI_D2 PAL_LINE(GPIOE, 2U) +#define LINE_SAI1_SDB PAL_LINE(GPIOE, 3U) +#define LINE_SAI1_FSA PAL_LINE(GPIOE, 4U) +#define LINE_SAI1_SCKA PAL_LINE(GPIOE, 5U) +#define LINE_SAI1_SDA PAL_LINE(GPIOE, 6U) +#define LINE_FMC_D4 PAL_LINE(GPIOE, 7U) +#define LINE_FMC_D5 PAL_LINE(GPIOE, 8U) +#define LINE_FMC_D6 PAL_LINE(GPIOE, 9U) +#define LINE_FMC_D7 PAL_LINE(GPIOE, 10U) +#define LINE_FMC_D8 PAL_LINE(GPIOE, 11U) +#define LINE_FMC_D9 PAL_LINE(GPIOE, 12U) +#define LINE_FMC_D10 PAL_LINE(GPIOE, 13U) +#define LINE_FMC_11 PAL_LINE(GPIOE, 14U) +#define LINE_FMC_D12 PAL_LINE(GPIOE, 15U) + +#define LINE_FMC_A0 PAL_LINE(GPIOF, 0U) +#define LINE_FMC_A1 PAL_LINE(GPIOF, 1U) +#define LINE_FMC_A2 PAL_LINE(GPIOF, 2U) +#define LINE_FMC_A3 PAL_LINE(GPIOF, 3U) +#define LINE_FMC_A4 PAL_LINE(GPIOF, 4U) +#define LINE_FMC_A5 PAL_LINE(GPIOF, 5U) +#define LINE_ARD_D3 PAL_LINE(GPIOF, 6U) +#define LINE_ARD_D6 PAL_LINE(GPIOF, 7U) +#define LINE_ARD_A4 PAL_LINE(GPIOF, 8U) +#define LINE_ARD_A5 PAL_LINE(GPIOF, 9U) +#define LINE_ARD_A3 PAL_LINE(GPIOF, 10U) +#define LINE_FMC_SDNRAS PAL_LINE(GPIOF, 11U) +#define LINE_FMC_A6 PAL_LINE(GPIOF, 12U) +#define LINE_FMC_A7 PAL_LINE(GPIOF, 13U) +#define LINE_FMC_A8 PAL_LINE(GPIOF, 14U) +#define LINE_FMC_A9 PAL_LINE(GPIOF, 15U) + +#define LINE_FMC_A10 PAL_LINE(GPIOG, 0U) +#define LINE_FMC_A11 PAL_LINE(GPIOG, 1U) +#define LINE_FMC_A12 PAL_LINE(GPIOG, 2U) +#define LINE_EXT_SCL PAL_LINE(GPIOG, 3U) +#define LINE_FMC_BA0 PAL_LINE(GPIOG, 4U) +#define LINE_FMC_BA1 PAL_LINE(GPIOG, 5U) +#define LINE_EXT_SDA PAL_LINE(GPIOG, 6U) +#define LINE_SAI1_MCLKA PAL_LINE(GPIOG, 7U) +#define LINE_FMC_SDCLK PAL_LINE(GPIOG, 8U) +#define LINE_SD_D0 PAL_LINE(GPIOG, 9U) +#define LINE_SD_D1 PAL_LINE(GPIOG, 10U) +#define LINE_RMII_TX_EN PAL_LINE(GPIOG, 11U) +#define LINE_SPDIF_RX PAL_LINE(GPIOG, 12U) +#define LINE_RMII_TXD0 PAL_LINE(GPIOG, 13U) +#define LINE_RMII_TXD1 PAL_LINE(GPIOG, 14U) +#define LINE_FMC_SDNCAS PAL_LINE(GPIOG, 15U) + +#define LINE_OSC_IN PAL_LINE(GPIOH, 0U) +#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U) +#define LINE_FMC_SDCKE0 PAL_LINE(GPIOH, 2U) +#define LINE_FMC_SDNE0 PAL_LINE(GPIOH, 3U) +#define LINE_ULPI_NXT PAL_LINE(GPIOH, 4U) +#define LINE_FMC_SDNWE PAL_LINE(GPIOH, 5U) +#define LINE_ARD_D9 PAL_LINE(GPIOH, 6U) +#define LINE_EXT_RST PAL_LINE(GPIOH, 7U) +#define LINE_FMC_D16 PAL_LINE(GPIOH, 8U) +#define LINE_FMC_D17 PAL_LINE(GPIOH, 9U) +#define LINE_FMC_D18 PAL_LINE(GPIOH, 10U) +#define LINE_FMC_D19 PAL_LINE(GPIOH, 11U) +#define LINE_FMC_D20 PAL_LINE(GPIOH, 12U) +#define LINE_FMC_D21 PAL_LINE(GPIOH, 13U) +#define LINE_FMC_D22 PAL_LINE(GPIOH, 14U) +#define LINE_FMC_D23 PAL_LINE(GPIOH, 15U) + +#define LINE_FMC_D24 PAL_LINE(GPIOI, 0U) +#define LINE_FMC_D25 PAL_LINE(GPIOI, 1U) +#define LINE_FMC_D26 PAL_LINE(GPIOI, 2U) +#define LINE_FMC_D27 PAL_LINE(GPIOI, 3U) +#define LINE_FMC_NBL2 PAL_LINE(GPIOI, 4U) +#define LINE_FMC_NBL3 PAL_LINE(GPIOI, 5U) +#define LINE_FMC_D28 PAL_LINE(GPIOI, 6U) +#define LINE_FMC_D29 PAL_LINE(GPIOI, 7U) +#define LINE_FMC_D30 PAL_LINE(GPIOI, 9U) +#define LINE_FMC_D31 PAL_LINE(GPIOI, 10U) +#define LINE_ULPI_DIR PAL_LINE(GPIOI, 11U) +#define LINE_LCD_INT PAL_LINE(GPIOI, 13U) +#define LINE_LCD_BL_CTRL PAL_LINE(GPIOI, 14U) +#define LINE_SD_DETECT PAL_LINE(GPIOI, 15U) + +#define LINE_ARD_D4 PAL_LINE(GPIOJ, 0U) +#define LINE_ARD_D2 PAL_LINE(GPIOJ, 1U) +#define LINE_DSI_TE PAL_LINE(GPIOJ, 2U) +#define LINE_ARD_D7 PAL_LINE(GPIOJ, 3U) +#define LINE_ARD_D8 PAL_LINE(GPIOJ, 4U) +#define LINE_LED2_GREEN PAL_LINE(GPIOJ, 5U) +#define LINE_AUDIO_INT PAL_LINE(GPIOJ, 12U) +#define LINE_LED1_RED PAL_LINE(GPIOJ, 13U) +#define LINE_WIFI_RST PAL_LINE(GPIOJ, 14U) +#define LINE_DSI_RESET PAL_LINE(GPIOJ, 15U) + + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_VERYLOW(n) (0U << ((n) * 2U)) +#define PIN_OSPEED_LOW(n) (1U << ((n) * 2U)) +#define PIN_OSPEED_MEDIUM(n) (2U << ((n) * 2U)) +#define PIN_OSPEED_HIGH(n) (3U << ((n) * 2U)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) + +/* + * GPIOA setup: + * + * PA0 - BUTTON_USER (input floating). + * PA1 - RMII_REF_CLK (alternate 11). + * PA2 - RMII_MDIO (alternate 11). + * PA3 - ULPI_D0 (alternate 10). + * PA4 - ARD_A1 (input pullup). + * PA5 - ULPI_CK (alternate 10). + * PA6 - ARD_A0 (input pullup). + * PA7 - RMII_CRS_DV (alternate 11). + * PA8 - CEC_CLK (alternate 0). + * PA9 - VCP_TX (alternate 7). + * PA10 - VCP_RX (alternate 7). + * PA11 - ARD_D10 (input pullup). + * PA12 - ARD_D13 (input pullup). + * PA13 - SWDIO (alternate 0). + * PA14 - SWCLK (alternate 0). + * PA15 - CEC (alternate 3). + */ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON_USER) | \ + PIN_MODE_ALTERNATE(GPIOA_RMII_REF_CLK) |\ + PIN_MODE_ALTERNATE(GPIOA_RMII_MDIO) | \ + PIN_MODE_ALTERNATE(GPIOA_ULPI_D0) | \ + PIN_MODE_INPUT(GPIOA_ARD_A1) | \ + PIN_MODE_ALTERNATE(GPIOA_ULPI_CK) | \ + PIN_MODE_INPUT(GPIOA_ARD_A0) | \ + PIN_MODE_ALTERNATE(GPIOA_RMII_CRS_DV) |\ + PIN_MODE_ALTERNATE(GPIOA_CEC_CLK) | \ + PIN_MODE_ALTERNATE(GPIOA_VCP_TX) | \ + PIN_MODE_ALTERNATE(GPIOA_VCP_RX) | \ + PIN_MODE_INPUT(GPIOA_ARD_D10) | \ + PIN_MODE_INPUT(GPIOA_ARD_D13) | \ + PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \ + PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \ + PIN_MODE_ALTERNATE(GPIOA_CEC)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_BUTTON_USER) |\ + PIN_OTYPE_PUSHPULL(GPIOA_RMII_REF_CLK) |\ + PIN_OTYPE_PUSHPULL(GPIOA_RMII_MDIO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ULPI_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_A1) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ULPI_CK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_A0) | \ + PIN_OTYPE_PUSHPULL(GPIOA_RMII_CRS_DV) |\ + PIN_OTYPE_PUSHPULL(GPIOA_CEC_CLK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_VCP_TX) | \ + PIN_OTYPE_PUSHPULL(GPIOA_VCP_RX) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D10) | \ + PIN_OTYPE_PUSHPULL(GPIOA_ARD_D13) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \ + PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOA_CEC)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_HIGH(GPIOA_BUTTON_USER) | \ + PIN_OSPEED_HIGH(GPIOA_RMII_REF_CLK) | \ + PIN_OSPEED_HIGH(GPIOA_RMII_MDIO) | \ + PIN_OSPEED_HIGH(GPIOA_ULPI_D0) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_A1) | \ + PIN_OSPEED_HIGH(GPIOA_ULPI_CK) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_A0) | \ + PIN_OSPEED_VERYLOW(GPIOA_RMII_CRS_DV) |\ + PIN_OSPEED_HIGH(GPIOA_CEC_CLK) | \ + PIN_OSPEED_HIGH(GPIOA_VCP_TX) | \ + PIN_OSPEED_HIGH(GPIOA_VCP_RX) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D10) | \ + PIN_OSPEED_HIGH(GPIOA_ARD_D13) | \ + PIN_OSPEED_HIGH(GPIOA_SWDIO) | \ + PIN_OSPEED_HIGH(GPIOA_SWCLK) | \ + PIN_OSPEED_HIGH(GPIOA_CEC)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(GPIOA_BUTTON_USER) |\ + PIN_PUPDR_FLOATING(GPIOA_RMII_REF_CLK) |\ + PIN_PUPDR_PULLUP(GPIOA_RMII_MDIO) | \ + PIN_PUPDR_FLOATING(GPIOA_ULPI_D0) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_A1) | \ + PIN_PUPDR_FLOATING(GPIOA_ULPI_CK) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_A0) | \ + PIN_PUPDR_FLOATING(GPIOA_RMII_CRS_DV) |\ + PIN_PUPDR_FLOATING(GPIOA_CEC_CLK) | \ + PIN_PUPDR_FLOATING(GPIOA_VCP_TX) | \ + PIN_PUPDR_FLOATING(GPIOA_VCP_RX) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_D10) | \ + PIN_PUPDR_PULLUP(GPIOA_ARD_D13) | \ + PIN_PUPDR_FLOATING(GPIOA_SWDIO) | \ + PIN_PUPDR_FLOATING(GPIOA_SWCLK) | \ + PIN_PUPDR_FLOATING(GPIOA_CEC)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_BUTTON_USER) | \ + PIN_ODR_HIGH(GPIOA_RMII_REF_CLK) | \ + PIN_ODR_HIGH(GPIOA_RMII_MDIO) | \ + PIN_ODR_HIGH(GPIOA_ULPI_D0) | \ + PIN_ODR_HIGH(GPIOA_ARD_A1) | \ + PIN_ODR_HIGH(GPIOA_ULPI_CK) | \ + PIN_ODR_HIGH(GPIOA_ARD_A0) | \ + PIN_ODR_HIGH(GPIOA_RMII_CRS_DV) | \ + PIN_ODR_HIGH(GPIOA_CEC_CLK) | \ + PIN_ODR_HIGH(GPIOA_VCP_TX) | \ + PIN_ODR_HIGH(GPIOA_VCP_RX) | \ + PIN_ODR_HIGH(GPIOA_ARD_D10) | \ + PIN_ODR_HIGH(GPIOA_ARD_D13) | \ + PIN_ODR_HIGH(GPIOA_SWDIO) | \ + PIN_ODR_HIGH(GPIOA_SWCLK) | \ + PIN_ODR_HIGH(GPIOA_CEC)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_BUTTON_USER, 0) | \ + PIN_AFIO_AF(GPIOA_RMII_REF_CLK, 11) | \ + PIN_AFIO_AF(GPIOA_RMII_MDIO, 11) | \ + PIN_AFIO_AF(GPIOA_ULPI_D0, 10) | \ + PIN_AFIO_AF(GPIOA_ARD_A1, 0) | \ + PIN_AFIO_AF(GPIOA_ULPI_CK, 10) | \ + PIN_AFIO_AF(GPIOA_ARD_A0, 0) | \ + PIN_AFIO_AF(GPIOA_RMII_CRS_DV, 11)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_CEC_CLK, 0) | \ + PIN_AFIO_AF(GPIOA_VCP_TX, 7) | \ + PIN_AFIO_AF(GPIOA_VCP_RX, 7) | \ + PIN_AFIO_AF(GPIOA_ARD_D10, 0) | \ + PIN_AFIO_AF(GPIOA_ARD_D13, 0) | \ + PIN_AFIO_AF(GPIOA_SWDIO, 0) | \ + PIN_AFIO_AF(GPIOA_SWCLK, 0) | \ + PIN_AFIO_AF(GPIOA_CEC, 3)) + +/* + * GPIOB setup: + * + * PB0 - ULPI_D1 (alternate 10). + * PB1 - ULPI_D2 (alternate 10). + * PB2 - QSPI_CLK (input pullup). + * PB3 - SD_D2 (alternate 10). + * PB4 - SD_D3 (alternate 10). + * PB5 - ULPI_D7 (alternate 10). + * PB6 - QSPI_NCS (input pullup). + * PB7 - AUDIO_SDA LCD_SDA (alternate 11). + * PB8 - ARD_D15 (input pullup). + * PB9 - ARD_D14 (input pullup). + * PB10 - ULPI_D3 (alternate 10). + * PB11 - ULPI_D4 (alternate 10). + * PB12 - ULPI_D5 (alternate 10). + * PB13 - ULPI_D6 (alternate 10). + * PB14 - ARD_D12 (input pullup). + * PB15 - ARD_D11 (input pullup). + */ +#define VAL_GPIOB_MODER (PIN_MODE_ALTERNATE(GPIOB_ULPI_D1) | \ + PIN_MODE_ALTERNATE(GPIOB_ULPI_D2) | \ + PIN_MODE_INPUT(GPIOB_QSPI_CLK) | \ + PIN_MODE_ALTERNATE(GPIOB_SD_D2) | \ + PIN_MODE_ALTERNATE(GPIOB_SD_D3) | \ + PIN_MODE_ALTERNATE(GPIOB_ULPI_D7) | \ + PIN_MODE_INPUT(GPIOB_QSPI_NCS) | \ + PIN_MODE_ALTERNATE(GPIOB_AUDIO_SDA) | \ + PIN_MODE_INPUT(GPIOB_ARD_D15) | \ + PIN_MODE_INPUT(GPIOB_ARD_D14) | \ + PIN_MODE_ALTERNATE(GPIOB_ULPI_D3) | \ + PIN_MODE_ALTERNATE(GPIOB_ULPI_D4) | \ + PIN_MODE_ALTERNATE(GPIOB_ULPI_D5) | \ + PIN_MODE_ALTERNATE(GPIOB_ULPI_D6) | \ + PIN_MODE_INPUT(GPIOB_ARD_D12) | \ + PIN_MODE_INPUT(GPIOB_ARD_D11)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_ULPI_D1) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ULPI_D2) | \ + PIN_OTYPE_PUSHPULL(GPIOB_QSPI_CLK) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SD_D2) | \ + PIN_OTYPE_PUSHPULL(GPIOB_SD_D3) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ULPI_D7) | \ + PIN_OTYPE_PUSHPULL(GPIOB_QSPI_NCS) | \ + PIN_OTYPE_PUSHPULL(GPIOB_AUDIO_SDA) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D15) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D14) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ULPI_D3) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ULPI_D4) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ULPI_D5) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ULPI_D6) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D12) | \ + PIN_OTYPE_PUSHPULL(GPIOB_ARD_D11)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_HIGH(GPIOB_ULPI_D1) | \ + PIN_OSPEED_HIGH(GPIOB_ULPI_D2) | \ + PIN_OSPEED_HIGH(GPIOB_QSPI_CLK) | \ + PIN_OSPEED_HIGH(GPIOB_SD_D2) | \ + PIN_OSPEED_HIGH(GPIOB_SD_D3) | \ + PIN_OSPEED_HIGH(GPIOB_ULPI_D7) | \ + PIN_OSPEED_HIGH(GPIOB_QSPI_NCS) | \ + PIN_OSPEED_HIGH(GPIOB_AUDIO_SDA) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D15) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D14) | \ + PIN_OSPEED_HIGH(GPIOB_ULPI_D3) | \ + PIN_OSPEED_HIGH(GPIOB_ULPI_D4) | \ + PIN_OSPEED_HIGH(GPIOB_ULPI_D5) | \ + PIN_OSPEED_HIGH(GPIOB_ULPI_D6) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D12) | \ + PIN_OSPEED_HIGH(GPIOB_ARD_D11)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_ULPI_D1) | \ + PIN_PUPDR_FLOATING(GPIOB_ULPI_D2) | \ + PIN_PUPDR_PULLUP(GPIOB_QSPI_CLK) | \ + PIN_PUPDR_FLOATING(GPIOB_SD_D2) | \ + PIN_PUPDR_FLOATING(GPIOB_SD_D3) | \ + PIN_PUPDR_PULLUP(GPIOB_ULPI_D7) | \ + PIN_PUPDR_PULLUP(GPIOB_QSPI_NCS) | \ + PIN_PUPDR_FLOATING(GPIOB_AUDIO_SDA) | \ + PIN_PUPDR_PULLUP(GPIOB_ARD_D15) | \ + PIN_PUPDR_PULLUP(GPIOB_ARD_D14) | \ + PIN_PUPDR_FLOATING(GPIOB_ULPI_D3) | \ + PIN_PUPDR_FLOATING(GPIOB_ULPI_D4) | \ + PIN_PUPDR_FLOATING(GPIOB_ULPI_D5) | \ + PIN_PUPDR_FLOATING(GPIOB_ULPI_D6) | \ + PIN_PUPDR_PULLUP(GPIOB_ARD_D12) | \ + PIN_PUPDR_PULLUP(GPIOB_ARD_D11)) +#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_ULPI_D1) | \ + PIN_ODR_HIGH(GPIOB_ULPI_D2) | \ + PIN_ODR_HIGH(GPIOB_QSPI_CLK) | \ + PIN_ODR_HIGH(GPIOB_SD_D2) | \ + PIN_ODR_HIGH(GPIOB_SD_D3) | \ + PIN_ODR_HIGH(GPIOB_ULPI_D7) | \ + PIN_ODR_HIGH(GPIOB_QSPI_NCS) | \ + PIN_ODR_HIGH(GPIOB_AUDIO_SDA) | \ + PIN_ODR_HIGH(GPIOB_ARD_D15) | \ + PIN_ODR_HIGH(GPIOB_ARD_D14) | \ + PIN_ODR_HIGH(GPIOB_ULPI_D3) | \ + PIN_ODR_HIGH(GPIOB_ULPI_D4) | \ + PIN_ODR_HIGH(GPIOB_ULPI_D5) | \ + PIN_ODR_HIGH(GPIOB_ULPI_D6) | \ + PIN_ODR_HIGH(GPIOB_ARD_D12) | \ + PIN_ODR_HIGH(GPIOB_ARD_D11)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_ULPI_D1, 10) | \ + PIN_AFIO_AF(GPIOB_ULPI_D2, 10) | \ + PIN_AFIO_AF(GPIOB_QSPI_CLK, 0) | \ + PIN_AFIO_AF(GPIOB_SD_D2, 10) | \ + PIN_AFIO_AF(GPIOB_SD_D3, 10) | \ + PIN_AFIO_AF(GPIOB_ULPI_D7, 10) | \ + PIN_AFIO_AF(GPIOB_QSPI_NCS, 0) | \ + PIN_AFIO_AF(GPIOB_AUDIO_SDA, 11)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_ARD_D15, 0) | \ + PIN_AFIO_AF(GPIOB_ARD_D14, 0) | \ + PIN_AFIO_AF(GPIOB_ULPI_D3, 10) | \ + PIN_AFIO_AF(GPIOB_ULPI_D4, 10) | \ + PIN_AFIO_AF(GPIOB_ULPI_D5, 10) | \ + PIN_AFIO_AF(GPIOB_ULPI_D6, 10) | \ + PIN_AFIO_AF(GPIOB_ARD_D12, 0) | \ + PIN_AFIO_AF(GPIOB_ARD_D11, 0)) + +/* + * GPIOC setup: + * + * PC0 - ULPI_STP (alternate 10). + * PC1 - RMII_MDC (alternate 11). + * PC2 - ARD_A2 (input pullup). + * PC3 - DFSDM_DATIN1 (alternate 3). + * PC4 - RMII_RXD0 (alternate 11). + * PC5 - RMII_RXD1 (alternate 11). + * PC6 - ARD_D1 (input pullup). + * PC7 - ARD_D0 (input floating). + * PC8 - ARD_D5 (input floating). + * PC9 - QSPI_D0 (alternate 9). + * PC10 - QSPI_D1 (alternate 9). + * PC11 - DFSDM_DATIN5 (alternate 3). + * PC12 - WIFI_RX (alternate 8). + * PC13 - PIN13 (input pullup). + * PC14 - OSC32_IN (input floating). + * PC15 - OSC32_OUT (input floating). + */ +#define VAL_GPIOC_MODER (PIN_MODE_ALTERNATE(GPIOC_ULPI_STP) | \ + PIN_MODE_ALTERNATE(GPIOC_RMII_MDC) | \ + PIN_MODE_INPUT(GPIOC_ARD_A2) | \ + PIN_MODE_ALTERNATE(GPIOC_DFSDM_DATIN1) |\ + PIN_MODE_ALTERNATE(GPIOC_RMII_RXD0) | \ + PIN_MODE_ALTERNATE(GPIOC_RMII_RXD1) | \ + PIN_MODE_INPUT(GPIOC_ARD_D1) | \ + PIN_MODE_INPUT(GPIOC_ARD_D0) | \ + PIN_MODE_INPUT(GPIOC_ARD_D5) | \ + PIN_MODE_ALTERNATE(GPIOC_QSPI_D0) | \ + PIN_MODE_ALTERNATE(GPIOC_QSPI_D1) | \ + PIN_MODE_ALTERNATE(GPIOC_DFSDM_DATIN5) |\ + PIN_MODE_ALTERNATE(GPIOC_WIFI_RX) | \ + PIN_MODE_INPUT(GPIOC_PIN13) | \ + PIN_MODE_INPUT(GPIOC_OSC32_IN) | \ + PIN_MODE_INPUT(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_ULPI_STP) | \ + PIN_OTYPE_PUSHPULL(GPIOC_RMII_MDC) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ARD_A2) | \ + PIN_OTYPE_PUSHPULL(GPIOC_DFSDM_DATIN1) |\ + PIN_OTYPE_PUSHPULL(GPIOC_RMII_RXD0) | \ + PIN_OTYPE_PUSHPULL(GPIOC_RMII_RXD1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ARD_D1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ARD_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOC_ARD_D5) | \ + PIN_OTYPE_PUSHPULL(GPIOC_QSPI_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOC_QSPI_D1) | \ + PIN_OTYPE_PUSHPULL(GPIOC_DFSDM_DATIN5) |\ + PIN_OTYPE_PUSHPULL(GPIOC_WIFI_RX) | \ + PIN_OTYPE_PUSHPULL(GPIOC_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_HIGH(GPIOC_ULPI_STP) | \ + PIN_OSPEED_HIGH(GPIOC_RMII_MDC) | \ + PIN_OSPEED_HIGH(GPIOC_ARD_A2) | \ + PIN_OSPEED_HIGH(GPIOC_DFSDM_DATIN1) | \ + PIN_OSPEED_HIGH(GPIOC_RMII_RXD0) | \ + PIN_OSPEED_HIGH(GPIOC_RMII_RXD1) | \ + PIN_OSPEED_HIGH(GPIOC_ARD_D1) | \ + PIN_OSPEED_HIGH(GPIOC_ARD_D0) | \ + PIN_OSPEED_HIGH(GPIOC_ARD_D5) | \ + PIN_OSPEED_HIGH(GPIOC_QSPI_D0) | \ + PIN_OSPEED_HIGH(GPIOC_QSPI_D1) | \ + PIN_OSPEED_HIGH(GPIOC_DFSDM_DATIN5) | \ + PIN_OSPEED_HIGH(GPIOC_WIFI_RX) | \ + PIN_OSPEED_HIGH(GPIOC_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOC_OSC32_IN) | \ + PIN_OSPEED_VERYLOW(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(GPIOC_ULPI_STP) | \ + PIN_PUPDR_FLOATING(GPIOC_RMII_MDC) | \ + PIN_PUPDR_PULLUP(GPIOC_ARD_A2) | \ + PIN_PUPDR_FLOATING(GPIOC_DFSDM_DATIN1) |\ + PIN_PUPDR_FLOATING(GPIOC_RMII_RXD0) | \ + PIN_PUPDR_FLOATING(GPIOC_RMII_RXD1) | \ + PIN_PUPDR_PULLUP(GPIOC_ARD_D1) | \ + PIN_PUPDR_FLOATING(GPIOC_ARD_D0) | \ + PIN_PUPDR_FLOATING(GPIOC_ARD_D5) | \ + PIN_PUPDR_FLOATING(GPIOC_QSPI_D0) | \ + PIN_PUPDR_FLOATING(GPIOC_QSPI_D1) | \ + PIN_PUPDR_FLOATING(GPIOC_DFSDM_DATIN5) |\ + PIN_PUPDR_FLOATING(GPIOC_WIFI_RX) | \ + PIN_PUPDR_PULLUP(GPIOC_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_IN) | \ + PIN_PUPDR_FLOATING(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_ULPI_STP) | \ + PIN_ODR_HIGH(GPIOC_RMII_MDC) | \ + PIN_ODR_HIGH(GPIOC_ARD_A2) | \ + PIN_ODR_HIGH(GPIOC_DFSDM_DATIN1) | \ + PIN_ODR_HIGH(GPIOC_RMII_RXD0) | \ + PIN_ODR_HIGH(GPIOC_RMII_RXD1) | \ + PIN_ODR_HIGH(GPIOC_ARD_D1) | \ + PIN_ODR_HIGH(GPIOC_ARD_D0) | \ + PIN_ODR_HIGH(GPIOC_ARD_D5) | \ + PIN_ODR_HIGH(GPIOC_QSPI_D0) | \ + PIN_ODR_HIGH(GPIOC_QSPI_D1) | \ + PIN_ODR_HIGH(GPIOC_DFSDM_DATIN5) | \ + PIN_ODR_HIGH(GPIOC_WIFI_RX) | \ + PIN_ODR_HIGH(GPIOC_PIN13) | \ + PIN_ODR_HIGH(GPIOC_OSC32_IN) | \ + PIN_ODR_HIGH(GPIOC_OSC32_OUT)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_ULPI_STP, 10) | \ + PIN_AFIO_AF(GPIOC_RMII_MDC, 11) | \ + PIN_AFIO_AF(GPIOC_ARD_A2, 0) | \ + PIN_AFIO_AF(GPIOC_DFSDM_DATIN1, 3) | \ + PIN_AFIO_AF(GPIOC_RMII_RXD0, 11) | \ + PIN_AFIO_AF(GPIOC_RMII_RXD1, 11) | \ + PIN_AFIO_AF(GPIOC_ARD_D1, 0) | \ + PIN_AFIO_AF(GPIOC_ARD_D0, 0)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_ARD_D5, 0) | \ + PIN_AFIO_AF(GPIOC_QSPI_D0, 9) | \ + PIN_AFIO_AF(GPIOC_QSPI_D1, 9) | \ + PIN_AFIO_AF(GPIOC_DFSDM_DATIN5, 3) | \ + PIN_AFIO_AF(GPIOC_WIFI_RX, 8) | \ + PIN_AFIO_AF(GPIOC_PIN13, 0) | \ + PIN_AFIO_AF(GPIOC_OSC32_IN, 0) | \ + PIN_AFIO_AF(GPIOC_OSC32_OUT, 0)) + +/* + * GPIOD setup: + * + * PD0 - FMC_D2 (alternate 12). + * PD1 - FMC_D3 (alternate 12). + * PD2 - WIFI_TX (alternate 8). + * PD3 - DFSDM_CKOUT (alternate 3). + * PD4 - OTG_HS_OVER_CURRENT (input floating). + * PD5 - RMII_RXER (alternate 7). + * PD6 - SD_CLK (alternate 11). + * PD7 - SD_CMD (alternate 11). + * PD8 - FMC_D13 (alternate 12). + * PD9 - FMC_D14 (alternate 12). + * PD10 - FMC_D15 (alternate 12). + * PD11 - SPDIF_I2S (alternate 10). + * PD12 - AUDIO_SCL LCD_SCL (alternate 4). + * PD13 - QSPI_D3 (input pullup). + * PD14 - FMC_D0 (alternate 12). + * PD15 - FMC_D1 (alternate 12). + */ +#define VAL_GPIOD_MODER (PIN_MODE_ALTERNATE(GPIOD_FMC_D2) | \ + PIN_MODE_ALTERNATE(GPIOD_FMC_D3) | \ + PIN_MODE_ALTERNATE(GPIOD_WIFI_TX) | \ + PIN_MODE_ALTERNATE(GPIOD_DFSDM_CKOUT) |\ + PIN_MODE_INPUT(GPIOD_OTG_HS_OVER_CURRENT) |\ + PIN_MODE_ALTERNATE(GPIOD_RMII_RXER) | \ + PIN_MODE_ALTERNATE(GPIOD_SD_CLK) | \ + PIN_MODE_ALTERNATE(GPIOD_SD_CMD) | \ + PIN_MODE_ALTERNATE(GPIOD_FMC_D13) | \ + PIN_MODE_ALTERNATE(GPIOD_FMC_D14) | \ + PIN_MODE_ALTERNATE(GPIOD_FMC_D15) | \ + PIN_MODE_ALTERNATE(GPIOD_SPDIF_I2S) | \ + PIN_MODE_ALTERNATE(GPIOD_AUDIO_SCL) | \ + PIN_MODE_INPUT(GPIOD_QSPI_D3) | \ + PIN_MODE_ALTERNATE(GPIOD_FMC_D0) | \ + PIN_MODE_ALTERNATE(GPIOD_FMC_D1)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_FMC_D2) | \ + PIN_OTYPE_PUSHPULL(GPIOD_FMC_D3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_WIFI_TX) | \ + PIN_OTYPE_PUSHPULL(GPIOD_DFSDM_CKOUT) |\ + PIN_OTYPE_PUSHPULL(GPIOD_OTG_HS_OVER_CURRENT) |\ + PIN_OTYPE_PUSHPULL(GPIOD_RMII_RXER) | \ + PIN_OTYPE_PUSHPULL(GPIOD_SD_CLK) | \ + PIN_OTYPE_PUSHPULL(GPIOD_SD_CMD) | \ + PIN_OTYPE_PUSHPULL(GPIOD_FMC_D13) | \ + PIN_OTYPE_PUSHPULL(GPIOD_FMC_D14) | \ + PIN_OTYPE_PUSHPULL(GPIOD_FMC_D15) | \ + PIN_OTYPE_PUSHPULL(GPIOD_SPDIF_I2S) | \ + PIN_OTYPE_PUSHPULL(GPIOD_AUDIO_SCL) | \ + PIN_OTYPE_PUSHPULL(GPIOD_QSPI_D3) | \ + PIN_OTYPE_PUSHPULL(GPIOD_FMC_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOD_FMC_D1)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_HIGH(GPIOD_FMC_D2) | \ + PIN_OSPEED_HIGH(GPIOD_FMC_D3) | \ + PIN_OSPEED_HIGH(GPIOD_WIFI_TX) | \ + PIN_OSPEED_HIGH(GPIOD_DFSDM_CKOUT) | \ + PIN_OSPEED_HIGH(GPIOD_OTG_HS_OVER_CURRENT) |\ + PIN_OSPEED_HIGH(GPIOD_RMII_RXER) | \ + PIN_OSPEED_HIGH(GPIOD_SD_CLK) | \ + PIN_OSPEED_HIGH(GPIOD_SD_CMD) | \ + PIN_OSPEED_HIGH(GPIOD_FMC_D13) | \ + PIN_OSPEED_HIGH(GPIOD_FMC_D14) | \ + PIN_OSPEED_HIGH(GPIOD_FMC_D15) | \ + PIN_OSPEED_HIGH(GPIOD_SPDIF_I2S) | \ + PIN_OSPEED_HIGH(GPIOD_AUDIO_SCL) | \ + PIN_OSPEED_HIGH(GPIOD_QSPI_D3) | \ + PIN_OSPEED_HIGH(GPIOD_FMC_D0) | \ + PIN_OSPEED_HIGH(GPIOD_FMC_D1)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_FMC_D2) | \ + PIN_PUPDR_FLOATING(GPIOD_FMC_D3) | \ + PIN_PUPDR_FLOATING(GPIOD_WIFI_TX) | \ + PIN_PUPDR_FLOATING(GPIOD_DFSDM_CKOUT) |\ + PIN_PUPDR_FLOATING(GPIOD_OTG_HS_OVER_CURRENT) |\ + PIN_PUPDR_FLOATING(GPIOD_RMII_RXER) | \ + PIN_PUPDR_FLOATING(GPIOD_SD_CLK) | \ + PIN_PUPDR_FLOATING(GPIOD_SD_CMD) | \ + PIN_PUPDR_FLOATING(GPIOD_FMC_D13) | \ + PIN_PUPDR_FLOATING(GPIOD_FMC_D14) | \ + PIN_PUPDR_FLOATING(GPIOD_FMC_D15) | \ + PIN_PUPDR_FLOATING(GPIOD_SPDIF_I2S) | \ + PIN_PUPDR_FLOATING(GPIOD_AUDIO_SCL) | \ + PIN_PUPDR_PULLUP(GPIOD_QSPI_D3) | \ + PIN_PUPDR_FLOATING(GPIOD_FMC_D0) | \ + PIN_PUPDR_FLOATING(GPIOD_FMC_D1)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_FMC_D2) | \ + PIN_ODR_HIGH(GPIOD_FMC_D3) | \ + PIN_ODR_HIGH(GPIOD_WIFI_TX) | \ + PIN_ODR_HIGH(GPIOD_DFSDM_CKOUT) | \ + PIN_ODR_HIGH(GPIOD_OTG_HS_OVER_CURRENT) |\ + PIN_ODR_HIGH(GPIOD_RMII_RXER) | \ + PIN_ODR_HIGH(GPIOD_SD_CLK) | \ + PIN_ODR_HIGH(GPIOD_SD_CMD) | \ + PIN_ODR_HIGH(GPIOD_FMC_D13) | \ + PIN_ODR_HIGH(GPIOD_FMC_D14) | \ + PIN_ODR_HIGH(GPIOD_FMC_D15) | \ + PIN_ODR_HIGH(GPIOD_SPDIF_I2S) | \ + PIN_ODR_HIGH(GPIOD_AUDIO_SCL) | \ + PIN_ODR_LOW(GPIOD_QSPI_D3) | \ + PIN_ODR_LOW(GPIOD_FMC_D0) | \ + PIN_ODR_LOW(GPIOD_FMC_D1)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_FMC_D2, 12) | \ + PIN_AFIO_AF(GPIOD_FMC_D3, 12) | \ + PIN_AFIO_AF(GPIOD_WIFI_TX, 8) | \ + PIN_AFIO_AF(GPIOD_DFSDM_CKOUT, 3) | \ + PIN_AFIO_AF(GPIOD_OTG_HS_OVER_CURRENT, 0) |\ + PIN_AFIO_AF(GPIOD_RMII_RXER, 7) | \ + PIN_AFIO_AF(GPIOD_SD_CLK, 11) | \ + PIN_AFIO_AF(GPIOD_SD_CMD, 11)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_FMC_D13, 12) | \ + PIN_AFIO_AF(GPIOD_FMC_D14, 12) | \ + PIN_AFIO_AF(GPIOD_FMC_D15, 12) | \ + PIN_AFIO_AF(GPIOD_SPDIF_I2S, 10) | \ + PIN_AFIO_AF(GPIOD_AUDIO_SCL, 4) | \ + PIN_AFIO_AF(GPIOD_QSPI_D3, 0) | \ + PIN_AFIO_AF(GPIOD_FMC_D0, 12) | \ + PIN_AFIO_AF(GPIOD_FMC_D1, 12)) + +/* + * GPIOE setup: + * + * PE0 - FMC_NBL0 (alternate 12). + * PE1 - FMC_NBL1 (alternate 12). + * PE2 - QSPI_D2 (input pullup). + * PE3 - SAI1_SDB (alternate 6). + * PE4 - SAI1_FSA (alternate 6). + * PE5 - SAI1_SCKA (alternate 6). + * PE6 - SAI1_SDA (alternate 6). + * PE7 - FMC_D4 (alternate 12). + * PE8 - FMC_D5 (alternate 12). + * PE9 - FMC_D6 (alternate 12). + * PE10 - FMC_D7 (alternate 12). + * PE11 - FMC_D8 (alternate 12). + * PE12 - FMC_D9 (alternate 12). + * PE13 - FMC_D10 (alternate 12). + * PE14 - FMC_11 (alternate 12). + * PE15 - FMC_D12 (alternate 12). + */ +#define VAL_GPIOE_MODER (PIN_MODE_ALTERNATE(GPIOE_FMC_NBL0) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_NBL1) | \ + PIN_MODE_INPUT(GPIOE_QSPI_D2) | \ + PIN_MODE_ALTERNATE(GPIOE_SAI1_SDB) | \ + PIN_MODE_ALTERNATE(GPIOE_SAI1_FSA) | \ + PIN_MODE_ALTERNATE(GPIOE_SAI1_SCKA) | \ + PIN_MODE_ALTERNATE(GPIOE_SAI1_SDA) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D4) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D5) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D6) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D7) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D8) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D9) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D10) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_11) | \ + PIN_MODE_ALTERNATE(GPIOE_FMC_D12)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_FMC_NBL0) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_NBL1) | \ + PIN_OTYPE_PUSHPULL(GPIOE_QSPI_D2) | \ + PIN_OTYPE_PUSHPULL(GPIOE_SAI1_SDB) | \ + PIN_OTYPE_PUSHPULL(GPIOE_SAI1_FSA) | \ + PIN_OTYPE_PUSHPULL(GPIOE_SAI1_SCKA) | \ + PIN_OTYPE_PUSHPULL(GPIOE_SAI1_SDA) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D4) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D5) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D6) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D7) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D8) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D9) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D10) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_11) | \ + PIN_OTYPE_PUSHPULL(GPIOE_FMC_D12)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_HIGH(GPIOE_FMC_NBL0) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_NBL1) | \ + PIN_OSPEED_HIGH(GPIOE_QSPI_D2) | \ + PIN_OSPEED_HIGH(GPIOE_SAI1_SDB) | \ + PIN_OSPEED_HIGH(GPIOE_SAI1_FSA) | \ + PIN_OSPEED_HIGH(GPIOE_SAI1_SCKA) | \ + PIN_OSPEED_HIGH(GPIOE_SAI1_SDA) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D4) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D5) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D6) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D7) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D8) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D9) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D10) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_11) | \ + PIN_OSPEED_HIGH(GPIOE_FMC_D12)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(GPIOE_FMC_NBL0) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_NBL1) | \ + PIN_PUPDR_PULLUP(GPIOE_QSPI_D2) | \ + PIN_PUPDR_FLOATING(GPIOE_SAI1_SDB) | \ + PIN_PUPDR_FLOATING(GPIOE_SAI1_FSA) | \ + PIN_PUPDR_FLOATING(GPIOE_SAI1_SCKA) | \ + PIN_PUPDR_FLOATING(GPIOE_SAI1_SDA) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D4) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D5) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D6) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D7) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D8) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D9) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D10) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_11) | \ + PIN_PUPDR_FLOATING(GPIOE_FMC_D12)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_FMC_NBL0) | \ + PIN_ODR_HIGH(GPIOE_FMC_NBL1) | \ + PIN_ODR_HIGH(GPIOE_QSPI_D2) | \ + PIN_ODR_HIGH(GPIOE_SAI1_SDB) | \ + PIN_ODR_HIGH(GPIOE_SAI1_FSA) | \ + PIN_ODR_HIGH(GPIOE_SAI1_SCKA) | \ + PIN_ODR_HIGH(GPIOE_SAI1_SDA) | \ + PIN_ODR_HIGH(GPIOE_FMC_D4) | \ + PIN_ODR_HIGH(GPIOE_FMC_D5) | \ + PIN_ODR_HIGH(GPIOE_FMC_D6) | \ + PIN_ODR_HIGH(GPIOE_FMC_D7) | \ + PIN_ODR_HIGH(GPIOE_FMC_D8) | \ + PIN_ODR_HIGH(GPIOE_FMC_D9) | \ + PIN_ODR_HIGH(GPIOE_FMC_D10) | \ + PIN_ODR_HIGH(GPIOE_FMC_11) | \ + PIN_ODR_HIGH(GPIOE_FMC_D12)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_FMC_NBL0, 12) | \ + PIN_AFIO_AF(GPIOE_FMC_NBL1, 12) | \ + PIN_AFIO_AF(GPIOE_QSPI_D2, 0) | \ + PIN_AFIO_AF(GPIOE_SAI1_SDB, 6) | \ + PIN_AFIO_AF(GPIOE_SAI1_FSA, 6) | \ + PIN_AFIO_AF(GPIOE_SAI1_SCKA, 6) | \ + PIN_AFIO_AF(GPIOE_SAI1_SDA, 6) | \ + PIN_AFIO_AF(GPIOE_FMC_D4, 12)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_FMC_D5, 12) | \ + PIN_AFIO_AF(GPIOE_FMC_D6, 12) | \ + PIN_AFIO_AF(GPIOE_FMC_D7, 12) | \ + PIN_AFIO_AF(GPIOE_FMC_D8, 12) | \ + PIN_AFIO_AF(GPIOE_FMC_D9, 12) | \ + PIN_AFIO_AF(GPIOE_FMC_D10, 12) | \ + PIN_AFIO_AF(GPIOE_FMC_11, 12) | \ + PIN_AFIO_AF(GPIOE_FMC_D12, 12)) + +/* + * GPIOF setup: + * + * PF0 - FMC_A0 (alternate 12). + * PF1 - FMC_A1 (alternate 12). + * PF2 - FMC_A2 (alternate 12). + * PF3 - FMC_A3 (alternate 12). + * PF4 - FMC_A4 (alternate 12). + * PF5 - FMC_A5 (alternate 12). + * PF6 - ARD_D3 (input pullup). + * PF7 - ARD_D6 (input pullup). + * PF8 - ARD_A4 (input pullup). + * PF9 - ARD_A5 (input pullup). + * PF10 - ARD_A3 (input pullup). + * PF11 - FMC_SDNRAS (alternate 12). + * PF12 - FMC_A6 (alternate 12). + * PF13 - FMC_A7 (alternate 12). + * PF14 - FMC_A8 (alternate 12). + * PF15 - FMC_A9 (alternate 12). + */ +#define VAL_GPIOF_MODER (PIN_MODE_ALTERNATE(GPIOF_FMC_A0) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A1) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A2) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A3) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A4) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A5) | \ + PIN_MODE_INPUT(GPIOF_ARD_D3) | \ + PIN_MODE_INPUT(GPIOF_ARD_D6) | \ + PIN_MODE_INPUT(GPIOF_ARD_A4) | \ + PIN_MODE_INPUT(GPIOF_ARD_A5) | \ + PIN_MODE_INPUT(GPIOF_ARD_A3) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_SDNRAS) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A6) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A7) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A8) | \ + PIN_MODE_ALTERNATE(GPIOF_FMC_A9)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_FMC_A0) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A1) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A2) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A5) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_D3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_D6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_A4) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_A5) | \ + PIN_OTYPE_PUSHPULL(GPIOF_ARD_A3) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_SDNRAS) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A6) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A7) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A8) | \ + PIN_OTYPE_PUSHPULL(GPIOF_FMC_A9)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_HIGH(GPIOF_FMC_A0) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A1) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A2) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A3) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A4) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A5) | \ + PIN_OSPEED_HIGH(GPIOF_ARD_D3) | \ + PIN_OSPEED_HIGH(GPIOF_ARD_D6) | \ + PIN_OSPEED_HIGH(GPIOF_ARD_A4) | \ + PIN_OSPEED_HIGH(GPIOF_ARD_A5) | \ + PIN_OSPEED_HIGH(GPIOF_ARD_A3) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_SDNRAS) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A6) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A7) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A8) | \ + PIN_OSPEED_HIGH(GPIOF_FMC_A9)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_FMC_A0) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A1) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A2) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A3) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A4) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A5) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_D3) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_D6) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_A4) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_A5) | \ + PIN_PUPDR_PULLUP(GPIOF_ARD_A3) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_SDNRAS) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A6) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A7) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A8) | \ + PIN_PUPDR_FLOATING(GPIOF_FMC_A9)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_FMC_A0) | \ + PIN_ODR_HIGH(GPIOF_FMC_A1) | \ + PIN_ODR_HIGH(GPIOF_FMC_A2) | \ + PIN_ODR_HIGH(GPIOF_FMC_A3) | \ + PIN_ODR_HIGH(GPIOF_FMC_A4) | \ + PIN_ODR_HIGH(GPIOF_FMC_A5) | \ + PIN_ODR_HIGH(GPIOF_ARD_D3) | \ + PIN_ODR_HIGH(GPIOF_ARD_D6) | \ + PIN_ODR_HIGH(GPIOF_ARD_A4) | \ + PIN_ODR_HIGH(GPIOF_ARD_A5) | \ + PIN_ODR_HIGH(GPIOF_ARD_A3) | \ + PIN_ODR_HIGH(GPIOF_FMC_SDNRAS) | \ + PIN_ODR_HIGH(GPIOF_FMC_A6) | \ + PIN_ODR_HIGH(GPIOF_FMC_A7) | \ + PIN_ODR_HIGH(GPIOF_FMC_A8) | \ + PIN_ODR_HIGH(GPIOF_FMC_A9)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_FMC_A0, 12) | \ + PIN_AFIO_AF(GPIOF_FMC_A1, 12) | \ + PIN_AFIO_AF(GPIOF_FMC_A2, 12) | \ + PIN_AFIO_AF(GPIOF_FMC_A3, 12) | \ + PIN_AFIO_AF(GPIOF_FMC_A4, 12) | \ + PIN_AFIO_AF(GPIOF_FMC_A5, 12) | \ + PIN_AFIO_AF(GPIOF_ARD_D3, 0) | \ + PIN_AFIO_AF(GPIOF_ARD_D6, 0)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_ARD_A4, 0) | \ + PIN_AFIO_AF(GPIOF_ARD_A5, 0) | \ + PIN_AFIO_AF(GPIOF_ARD_A3, 0) | \ + PIN_AFIO_AF(GPIOF_FMC_SDNRAS, 12) | \ + PIN_AFIO_AF(GPIOF_FMC_A6, 12) | \ + PIN_AFIO_AF(GPIOF_FMC_A7, 12) | \ + PIN_AFIO_AF(GPIOF_FMC_A8, 12) | \ + PIN_AFIO_AF(GPIOF_FMC_A9, 12)) + +/* + * GPIOG setup: + * + * PG0 - FMC_A10 (alternate 12). + * PG1 - FMC_A11 (alternate 12). + * PG2 - FMC_A12 (alternate 12). + * PG3 - EXT_SCL (input pullup). + * PG4 - FMC_BA0 (alternate 12). + * PG5 - FMC_BA1 (alternate 12). + * PG6 - EXT_SDA (input pullup). + * PG7 - SAI1_MCLKA (alternate 6). + * PG8 - FMC_SDCLK (input floating). + * PG9 - SD_D0 (alternate 11). + * PG10 - SD_D1 (alternate 11). + * PG11 - RMII_TX_EN (alternate 11). + * PG12 - SPDIF_RX (alternate 7). + * PG13 - RMII_TXD0 (alternate 11). + * PG14 - RMII_TXD1 (alternate 11). + * PG15 - FMC_SDNCAS (alternate 12). + */ +#define VAL_GPIOG_MODER (PIN_MODE_ALTERNATE(GPIOG_FMC_A10) | \ + PIN_MODE_ALTERNATE(GPIOG_FMC_A11) | \ + PIN_MODE_ALTERNATE(GPIOG_FMC_A12) | \ + PIN_MODE_INPUT(GPIOG_EXT_SCL) | \ + PIN_MODE_ALTERNATE(GPIOG_FMC_BA0) | \ + PIN_MODE_ALTERNATE(GPIOG_FMC_BA1) | \ + PIN_MODE_INPUT(GPIOG_EXT_SDA) | \ + PIN_MODE_ALTERNATE(GPIOG_SAI1_MCLKA) | \ + PIN_MODE_INPUT(GPIOG_FMC_SDCLK) | \ + PIN_MODE_ALTERNATE(GPIOG_SD_D0) | \ + PIN_MODE_ALTERNATE(GPIOG_SD_D1) | \ + PIN_MODE_ALTERNATE(GPIOG_RMII_TX_EN) | \ + PIN_MODE_ALTERNATE(GPIOG_SPDIF_RX) | \ + PIN_MODE_ALTERNATE(GPIOG_RMII_TXD0) | \ + PIN_MODE_ALTERNATE(GPIOG_RMII_TXD1) | \ + PIN_MODE_ALTERNATE(GPIOG_FMC_SDNCAS)) +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_FMC_A10) | \ + PIN_OTYPE_PUSHPULL(GPIOG_FMC_A11) | \ + PIN_OTYPE_PUSHPULL(GPIOG_FMC_A12) | \ + PIN_OTYPE_PUSHPULL(GPIOG_EXT_SCL) | \ + PIN_OTYPE_PUSHPULL(GPIOG_FMC_BA0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_FMC_BA1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_EXT_SDA) | \ + PIN_OTYPE_PUSHPULL(GPIOG_SAI1_MCLKA) | \ + PIN_OTYPE_PUSHPULL(GPIOG_FMC_SDCLK) | \ + PIN_OTYPE_PUSHPULL(GPIOG_SD_D0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_SD_D1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_RMII_TX_EN) | \ + PIN_OTYPE_PUSHPULL(GPIOG_SPDIF_RX) | \ + PIN_OTYPE_PUSHPULL(GPIOG_RMII_TXD0) | \ + PIN_OTYPE_PUSHPULL(GPIOG_RMII_TXD1) | \ + PIN_OTYPE_PUSHPULL(GPIOG_FMC_SDNCAS)) +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_HIGH(GPIOG_FMC_A10) | \ + PIN_OSPEED_HIGH(GPIOG_FMC_A11) | \ + PIN_OSPEED_HIGH(GPIOG_FMC_A12) | \ + PIN_OSPEED_HIGH(GPIOG_EXT_SCL) | \ + PIN_OSPEED_HIGH(GPIOG_FMC_BA0) | \ + PIN_OSPEED_HIGH(GPIOG_FMC_BA1) | \ + PIN_OSPEED_HIGH(GPIOG_EXT_SDA) | \ + PIN_OSPEED_HIGH(GPIOG_SAI1_MCLKA) | \ + PIN_OSPEED_HIGH(GPIOG_FMC_SDCLK) | \ + PIN_OSPEED_HIGH(GPIOG_SD_D0) | \ + PIN_OSPEED_HIGH(GPIOG_SD_D1) | \ + PIN_OSPEED_HIGH(GPIOG_RMII_TX_EN) | \ + PIN_OSPEED_HIGH(GPIOG_SPDIF_RX) | \ + PIN_OSPEED_HIGH(GPIOG_RMII_TXD0) | \ + PIN_OSPEED_HIGH(GPIOG_RMII_TXD1) | \ + PIN_OSPEED_HIGH(GPIOG_FMC_SDNCAS)) +#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_FMC_A10) | \ + PIN_PUPDR_FLOATING(GPIOG_FMC_A11) | \ + PIN_PUPDR_FLOATING(GPIOG_FMC_A12) | \ + PIN_PUPDR_PULLUP(GPIOG_EXT_SCL) | \ + PIN_PUPDR_FLOATING(GPIOG_FMC_BA0) | \ + PIN_PUPDR_FLOATING(GPIOG_FMC_BA1) | \ + PIN_PUPDR_PULLUP(GPIOG_EXT_SDA) | \ + PIN_PUPDR_PULLUP(GPIOG_SAI1_MCLKA) | \ + PIN_PUPDR_FLOATING(GPIOG_FMC_SDCLK) | \ + PIN_PUPDR_PULLUP(GPIOG_SD_D0) | \ + PIN_PUPDR_PULLUP(GPIOG_SD_D1) | \ + PIN_PUPDR_FLOATING(GPIOG_RMII_TX_EN) | \ + PIN_PUPDR_FLOATING(GPIOG_SPDIF_RX) | \ + PIN_PUPDR_FLOATING(GPIOG_RMII_TXD0) | \ + PIN_PUPDR_FLOATING(GPIOG_RMII_TXD1) | \ + PIN_PUPDR_FLOATING(GPIOG_FMC_SDNCAS)) +#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_FMC_A10) | \ + PIN_ODR_HIGH(GPIOG_FMC_A11) | \ + PIN_ODR_HIGH(GPIOG_FMC_A12) | \ + PIN_ODR_HIGH(GPIOG_EXT_SCL) | \ + PIN_ODR_HIGH(GPIOG_FMC_BA0) | \ + PIN_ODR_HIGH(GPIOG_FMC_BA1) | \ + PIN_ODR_HIGH(GPIOG_EXT_SDA) | \ + PIN_ODR_HIGH(GPIOG_SAI1_MCLKA) | \ + PIN_ODR_HIGH(GPIOG_FMC_SDCLK) | \ + PIN_ODR_HIGH(GPIOG_SD_D0) | \ + PIN_ODR_HIGH(GPIOG_SD_D1) | \ + PIN_ODR_HIGH(GPIOG_RMII_TX_EN) | \ + PIN_ODR_HIGH(GPIOG_SPDIF_RX) | \ + PIN_ODR_HIGH(GPIOG_RMII_TXD0) | \ + PIN_ODR_HIGH(GPIOG_RMII_TXD1) | \ + PIN_ODR_HIGH(GPIOG_FMC_SDNCAS)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_FMC_A10, 12) | \ + PIN_AFIO_AF(GPIOG_FMC_A11, 12) | \ + PIN_AFIO_AF(GPIOG_FMC_A12, 12) | \ + PIN_AFIO_AF(GPIOG_EXT_SCL, 0) | \ + PIN_AFIO_AF(GPIOG_FMC_BA0, 12) | \ + PIN_AFIO_AF(GPIOG_FMC_BA1, 12) | \ + PIN_AFIO_AF(GPIOG_EXT_SDA, 0) | \ + PIN_AFIO_AF(GPIOG_SAI1_MCLKA, 6)) +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_FMC_SDCLK, 0) | \ + PIN_AFIO_AF(GPIOG_SD_D0, 11) | \ + PIN_AFIO_AF(GPIOG_SD_D1, 11) | \ + PIN_AFIO_AF(GPIOG_RMII_TX_EN, 11) | \ + PIN_AFIO_AF(GPIOG_SPDIF_RX, 7) | \ + PIN_AFIO_AF(GPIOG_RMII_TXD0, 11) | \ + PIN_AFIO_AF(GPIOG_RMII_TXD1, 11) | \ + PIN_AFIO_AF(GPIOG_FMC_SDNCAS, 12)) + +/* + * GPIOH setup: + * + * PH0 - OSC_IN (input floating). + * PH1 - OSC_OUT (input floating). + * PH2 - FMC_SDCKE0 (alternate 12). + * PH3 - FMC_SDNE0 (alternate 12). + * PH4 - ULPI_NXT (alternate 10). + * PH5 - FMC_SDNWE (alternate 12). + * PH6 - ARD_D9 (input pullup). + * PH7 - EXT_RST (input floating). + * PH8 - FMC_D16 (alternate 12). + * PH9 - FMC_D17 (alternate 12). + * PH10 - FMC_D18 (alternate 12). + * PH11 - FMC_D19 (alternate 12). + * PH12 - FMC_D20 (alternate 12). + * PH13 - FMC_D21 (alternate 12). + * PH14 - FMC_D22 (alternate 12). + * PH15 - FMC_D23 (alternate 12). + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \ + PIN_MODE_INPUT(GPIOH_OSC_OUT) | \ + PIN_MODE_ALTERNATE(GPIOH_FMC_SDCKE0) | \ + PIN_MODE_ALTERNATE(GPIOH_FMC_SDNE0) | \ + PIN_MODE_ALTERNATE(GPIOH_ULPI_NXT) | \ + PIN_MODE_ALTERNATE(GPIOH_FMC_SDNWE) | \ + PIN_MODE_INPUT(GPIOH_ARD_D9) | \ + PIN_MODE_INPUT(GPIOH_EXT_RST) | \ + PIN_MODE_ALTERNATE(GPIOH_FMC_D16) | \ + PIN_MODE_ALTERNATE(GPIOH_FMC_D17) | \ + PIN_MODE_ALTERNATE(GPIOH_FMC_D18) | \ + PIN_MODE_ALTERNATE(GPIOH_FMC_D19) | \ + PIN_MODE_ALTERNATE(GPIOH_FMC_D20) | \ + PIN_MODE_ALTERNATE(GPIOH_FMC_D21) | \ + PIN_MODE_ALTERNATE(GPIOH_FMC_D22) | \ + PIN_MODE_ALTERNATE(GPIOH_FMC_D23)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \ + PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \ + PIN_OTYPE_PUSHPULL(GPIOH_FMC_SDCKE0) | \ + PIN_OTYPE_PUSHPULL(GPIOH_FMC_SDNE0) | \ + PIN_OTYPE_PUSHPULL(GPIOH_ULPI_NXT) | \ + PIN_OTYPE_PUSHPULL(GPIOH_FMC_SDNWE) | \ + PIN_OTYPE_PUSHPULL(GPIOH_ARD_D9) | \ + PIN_OTYPE_OPENDRAIN(GPIOH_EXT_RST) | \ + PIN_OTYPE_PUSHPULL(GPIOH_FMC_D16) | \ + PIN_OTYPE_PUSHPULL(GPIOH_FMC_D17) | \ + PIN_OTYPE_PUSHPULL(GPIOH_FMC_D18) | \ + PIN_OTYPE_PUSHPULL(GPIOH_FMC_D19) | \ + PIN_OTYPE_PUSHPULL(GPIOH_FMC_D20) | \ + PIN_OTYPE_PUSHPULL(GPIOH_FMC_D21) | \ + PIN_OTYPE_PUSHPULL(GPIOH_FMC_D22) | \ + PIN_OTYPE_PUSHPULL(GPIOH_FMC_D23)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_HIGH(GPIOH_OSC_IN) | \ + PIN_OSPEED_HIGH(GPIOH_OSC_OUT) | \ + PIN_OSPEED_HIGH(GPIOH_FMC_SDCKE0) | \ + PIN_OSPEED_HIGH(GPIOH_FMC_SDNE0) | \ + PIN_OSPEED_HIGH(GPIOH_ULPI_NXT) | \ + PIN_OSPEED_HIGH(GPIOH_FMC_SDNWE) | \ + PIN_OSPEED_HIGH(GPIOH_ARD_D9) | \ + PIN_OSPEED_HIGH(GPIOH_EXT_RST) | \ + PIN_OSPEED_HIGH(GPIOH_FMC_D16) | \ + PIN_OSPEED_HIGH(GPIOH_FMC_D17) | \ + PIN_OSPEED_HIGH(GPIOH_FMC_D18) | \ + PIN_OSPEED_HIGH(GPIOH_FMC_D19) | \ + PIN_OSPEED_HIGH(GPIOH_FMC_D20) | \ + PIN_OSPEED_HIGH(GPIOH_FMC_D21) | \ + PIN_OSPEED_HIGH(GPIOH_FMC_D22) | \ + PIN_OSPEED_HIGH(GPIOH_FMC_D23)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \ + PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \ + PIN_PUPDR_FLOATING(GPIOH_FMC_SDCKE0) | \ + PIN_PUPDR_FLOATING(GPIOH_FMC_SDNE0) | \ + PIN_PUPDR_FLOATING(GPIOH_ULPI_NXT) | \ + PIN_PUPDR_FLOATING(GPIOH_FMC_SDNWE) | \ + PIN_PUPDR_PULLUP(GPIOH_ARD_D9) | \ + PIN_PUPDR_FLOATING(GPIOH_EXT_RST) | \ + PIN_PUPDR_FLOATING(GPIOH_FMC_D16) | \ + PIN_PUPDR_FLOATING(GPIOH_FMC_D17) | \ + PIN_PUPDR_FLOATING(GPIOH_FMC_D18) | \ + PIN_PUPDR_FLOATING(GPIOH_FMC_D19) | \ + PIN_PUPDR_FLOATING(GPIOH_FMC_D20) | \ + PIN_PUPDR_FLOATING(GPIOH_FMC_D21) | \ + PIN_PUPDR_FLOATING(GPIOH_FMC_D22) | \ + PIN_PUPDR_FLOATING(GPIOH_FMC_D23)) +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \ + PIN_ODR_HIGH(GPIOH_OSC_OUT) | \ + PIN_ODR_HIGH(GPIOH_FMC_SDCKE0) | \ + PIN_ODR_HIGH(GPIOH_FMC_SDNE0) | \ + PIN_ODR_HIGH(GPIOH_ULPI_NXT) | \ + PIN_ODR_HIGH(GPIOH_FMC_SDNWE) | \ + PIN_ODR_HIGH(GPIOH_ARD_D9) | \ + PIN_ODR_HIGH(GPIOH_EXT_RST) | \ + PIN_ODR_HIGH(GPIOH_FMC_D16) | \ + PIN_ODR_HIGH(GPIOH_FMC_D17) | \ + PIN_ODR_HIGH(GPIOH_FMC_D18) | \ + PIN_ODR_HIGH(GPIOH_FMC_D19) | \ + PIN_ODR_HIGH(GPIOH_FMC_D20) | \ + PIN_ODR_HIGH(GPIOH_FMC_D21) | \ + PIN_ODR_HIGH(GPIOH_FMC_D22) | \ + PIN_ODR_HIGH(GPIOH_FMC_D23)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0) | \ + PIN_AFIO_AF(GPIOH_OSC_OUT, 0) | \ + PIN_AFIO_AF(GPIOH_FMC_SDCKE0, 12) | \ + PIN_AFIO_AF(GPIOH_FMC_SDNE0, 12) | \ + PIN_AFIO_AF(GPIOH_ULPI_NXT, 10) | \ + PIN_AFIO_AF(GPIOH_FMC_SDNWE, 12) | \ + PIN_AFIO_AF(GPIOH_ARD_D9, 0) | \ + PIN_AFIO_AF(GPIOH_EXT_RST, 0)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_FMC_D16, 12) | \ + PIN_AFIO_AF(GPIOH_FMC_D17, 12) | \ + PIN_AFIO_AF(GPIOH_FMC_D18, 12) | \ + PIN_AFIO_AF(GPIOH_FMC_D19, 12) | \ + PIN_AFIO_AF(GPIOH_FMC_D20, 12) | \ + PIN_AFIO_AF(GPIOH_FMC_D21, 12) | \ + PIN_AFIO_AF(GPIOH_FMC_D22, 12) | \ + PIN_AFIO_AF(GPIOH_FMC_D23, 12)) + +/* + * GPIOI setup: + * + * PI0 - FMC_D24 (alternate 12). + * PI1 - FMC_D25 (alternate 12). + * PI2 - FMC_D26 (alternate 12). + * PI3 - FMC_D27 (alternate 12). + * PI4 - FMC_NBL2 (alternate 12). + * PI5 - FMC_NBL3 (alternate 12). + * PI6 - FMC_D28 (alternate 12). + * PI7 - FMC_D29 (alternate 12). + * PI8 - PIN8 (input pullup). + * PI9 - FMC_D30 (alternate 12). + * PI10 - FMC_D31 (alternate 12). + * PI11 - ULPI_DIR (alternate 10). + * PI12 - PIN12 (input pullup). + * PI13 - LCD_INT (alternate 14). + * PI14 - LCD_BL_CTRL (alternate 14). + * PI15 - SD_DETECT (input pullup). + */ +#define VAL_GPIOI_MODER (PIN_MODE_ALTERNATE(GPIOI_FMC_D24) | \ + PIN_MODE_ALTERNATE(GPIOI_FMC_D25) | \ + PIN_MODE_ALTERNATE(GPIOI_FMC_D26) | \ + PIN_MODE_ALTERNATE(GPIOI_FMC_D27) | \ + PIN_MODE_ALTERNATE(GPIOI_FMC_NBL2) | \ + PIN_MODE_ALTERNATE(GPIOI_FMC_NBL3) | \ + PIN_MODE_ALTERNATE(GPIOI_FMC_D28) | \ + PIN_MODE_ALTERNATE(GPIOI_FMC_D29) | \ + PIN_MODE_INPUT(GPIOI_PIN8) | \ + PIN_MODE_ALTERNATE(GPIOI_FMC_D30) | \ + PIN_MODE_ALTERNATE(GPIOI_FMC_D31) | \ + PIN_MODE_ALTERNATE(GPIOI_ULPI_DIR) | \ + PIN_MODE_INPUT(GPIOI_PIN12) | \ + PIN_MODE_ALTERNATE(GPIOI_LCD_INT) | \ + PIN_MODE_ALTERNATE(GPIOI_LCD_BL_CTRL) |\ + PIN_MODE_INPUT(GPIOI_SD_DETECT)) +#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_FMC_D24) | \ + PIN_OTYPE_PUSHPULL(GPIOI_FMC_D25) | \ + PIN_OTYPE_PUSHPULL(GPIOI_FMC_D26) | \ + PIN_OTYPE_PUSHPULL(GPIOI_FMC_D27) | \ + PIN_OTYPE_PUSHPULL(GPIOI_FMC_NBL2) | \ + PIN_OTYPE_PUSHPULL(GPIOI_FMC_NBL3) | \ + PIN_OTYPE_PUSHPULL(GPIOI_FMC_D28) | \ + PIN_OTYPE_PUSHPULL(GPIOI_FMC_D29) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOI_FMC_D30) | \ + PIN_OTYPE_PUSHPULL(GPIOI_FMC_D31) | \ + PIN_OTYPE_PUSHPULL(GPIOI_ULPI_DIR) | \ + PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOI_LCD_INT) | \ + PIN_OTYPE_PUSHPULL(GPIOI_LCD_BL_CTRL) |\ + PIN_OTYPE_PUSHPULL(GPIOI_SD_DETECT)) +#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_HIGH(GPIOI_FMC_D24) | \ + PIN_OSPEED_HIGH(GPIOI_FMC_D25) | \ + PIN_OSPEED_HIGH(GPIOI_FMC_D26) | \ + PIN_OSPEED_HIGH(GPIOI_FMC_D27) | \ + PIN_OSPEED_HIGH(GPIOI_FMC_NBL2) | \ + PIN_OSPEED_HIGH(GPIOI_FMC_NBL3) | \ + PIN_OSPEED_HIGH(GPIOI_FMC_D28) | \ + PIN_OSPEED_HIGH(GPIOI_FMC_D29) | \ + PIN_OSPEED_HIGH(GPIOI_PIN8) | \ + PIN_OSPEED_HIGH(GPIOI_FMC_D30) | \ + PIN_OSPEED_HIGH(GPIOI_FMC_D31) | \ + PIN_OSPEED_HIGH(GPIOI_ULPI_DIR) | \ + PIN_OSPEED_HIGH(GPIOI_PIN12) | \ + PIN_OSPEED_HIGH(GPIOI_LCD_INT) | \ + PIN_OSPEED_HIGH(GPIOI_LCD_BL_CTRL) | \ + PIN_OSPEED_HIGH(GPIOI_SD_DETECT)) +#define VAL_GPIOI_PUPDR (PIN_PUPDR_FLOATING(GPIOI_FMC_D24) | \ + PIN_PUPDR_FLOATING(GPIOI_FMC_D25) | \ + PIN_PUPDR_FLOATING(GPIOI_FMC_D26) | \ + PIN_PUPDR_FLOATING(GPIOI_FMC_D27) | \ + PIN_PUPDR_FLOATING(GPIOI_FMC_NBL2) | \ + PIN_PUPDR_FLOATING(GPIOI_FMC_NBL3) | \ + PIN_PUPDR_FLOATING(GPIOI_FMC_D28) | \ + PIN_PUPDR_FLOATING(GPIOI_FMC_D29) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOI_FMC_D30) | \ + PIN_PUPDR_FLOATING(GPIOI_FMC_D31) | \ + PIN_PUPDR_FLOATING(GPIOI_ULPI_DIR) | \ + PIN_PUPDR_PULLUP(GPIOI_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOI_LCD_INT) | \ + PIN_PUPDR_FLOATING(GPIOI_LCD_BL_CTRL) |\ + PIN_PUPDR_PULLUP(GPIOI_SD_DETECT)) +#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_FMC_D24) | \ + PIN_ODR_HIGH(GPIOI_FMC_D25) | \ + PIN_ODR_HIGH(GPIOI_FMC_D26) | \ + PIN_ODR_HIGH(GPIOI_FMC_D27) | \ + PIN_ODR_HIGH(GPIOI_FMC_NBL2) | \ + PIN_ODR_HIGH(GPIOI_FMC_NBL3) | \ + PIN_ODR_HIGH(GPIOI_FMC_D28) | \ + PIN_ODR_HIGH(GPIOI_FMC_D29) | \ + PIN_ODR_HIGH(GPIOI_PIN8) | \ + PIN_ODR_HIGH(GPIOI_FMC_D30) | \ + PIN_ODR_HIGH(GPIOI_FMC_D31) | \ + PIN_ODR_HIGH(GPIOI_ULPI_DIR) | \ + PIN_ODR_HIGH(GPIOI_PIN12) | \ + PIN_ODR_HIGH(GPIOI_LCD_INT) | \ + PIN_ODR_HIGH(GPIOI_LCD_BL_CTRL) | \ + PIN_ODR_HIGH(GPIOI_SD_DETECT)) +#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_FMC_D24, 12) | \ + PIN_AFIO_AF(GPIOI_FMC_D25, 12) | \ + PIN_AFIO_AF(GPIOI_FMC_D26, 12) | \ + PIN_AFIO_AF(GPIOI_FMC_D27, 12) | \ + PIN_AFIO_AF(GPIOI_FMC_NBL2, 12) | \ + PIN_AFIO_AF(GPIOI_FMC_NBL3, 12) | \ + PIN_AFIO_AF(GPIOI_FMC_D28, 12) | \ + PIN_AFIO_AF(GPIOI_FMC_D29, 12)) +#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0) | \ + PIN_AFIO_AF(GPIOI_FMC_D30, 12) | \ + PIN_AFIO_AF(GPIOI_FMC_D31, 12) | \ + PIN_AFIO_AF(GPIOI_ULPI_DIR, 10) | \ + PIN_AFIO_AF(GPIOI_PIN12, 0) | \ + PIN_AFIO_AF(GPIOI_LCD_INT, 14) | \ + PIN_AFIO_AF(GPIOI_LCD_BL_CTRL, 14) | \ + PIN_AFIO_AF(GPIOI_SD_DETECT, 0)) + +/* + * GPIOJ setup: + * + * PJ0 - ARD_D4 (input floating). + * PJ1 - ARD_D2 (input floating). + * PJ2 - DSI_TE (alternate 13). + * PJ3 - ARD_D7 (input floating). + * PJ4 - ARD_D8 (input floating). + * PJ5 - LED2_GREEN (output pushpull maximum). + * PJ6 - PIN6 (input floating). + * PJ7 - PIN7 (input floating). + * PJ8 - PIN8 (input floating). + * PJ9 - PIN9 (input floating). + * PJ10 - PIN10 (input floating). + * PJ11 - PIN11 (input floating). + * PJ12 - AUDIO_INT (input floating). + * PJ13 - LED1_RED (output pushpull maximum). + * PJ14 - WIFI_RST (input floating). + * PJ15 - DSI_RESET (input floating). + */ +#define VAL_GPIOJ_MODER (PIN_MODE_INPUT(GPIOJ_ARD_D4) | \ + PIN_MODE_INPUT(GPIOJ_ARD_D2) | \ + PIN_MODE_ALTERNATE(GPIOJ_DSI_TE) | \ + PIN_MODE_INPUT(GPIOJ_ARD_D7) | \ + PIN_MODE_INPUT(GPIOJ_ARD_D8) | \ + PIN_MODE_OUTPUT(GPIOJ_LED2_GREEN) | \ + PIN_MODE_INPUT(GPIOJ_PIN6) | \ + PIN_MODE_INPUT(GPIOJ_PIN7) | \ + PIN_MODE_INPUT(GPIOJ_PIN8) | \ + PIN_MODE_INPUT(GPIOJ_PIN9) | \ + PIN_MODE_INPUT(GPIOJ_PIN10) | \ + PIN_MODE_INPUT(GPIOJ_PIN11) | \ + PIN_MODE_INPUT(GPIOJ_AUDIO_INT) | \ + PIN_MODE_OUTPUT(GPIOJ_LED1_RED) | \ + PIN_MODE_INPUT(GPIOJ_WIFI_RST) | \ + PIN_MODE_INPUT(GPIOJ_DSI_RESET)) +#define VAL_GPIOJ_OTYPER (PIN_OTYPE_PUSHPULL(GPIOJ_ARD_D4) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_ARD_D2) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_DSI_TE) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_ARD_D7) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_ARD_D8) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_LED2_GREEN) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_AUDIO_INT) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_LED1_RED) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_WIFI_RST) | \ + PIN_OTYPE_PUSHPULL(GPIOJ_DSI_RESET)) +#define VAL_GPIOJ_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOJ_ARD_D4) | \ + PIN_OSPEED_VERYLOW(GPIOJ_ARD_D2) | \ + PIN_OSPEED_VERYLOW(GPIOJ_DSI_TE) | \ + PIN_OSPEED_VERYLOW(GPIOJ_ARD_D7) | \ + PIN_OSPEED_VERYLOW(GPIOJ_ARD_D8) | \ + PIN_OSPEED_HIGH(GPIOJ_LED2_GREEN) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOJ_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOJ_AUDIO_INT) | \ + PIN_OSPEED_HIGH(GPIOJ_LED1_RED) | \ + PIN_OSPEED_VERYLOW(GPIOJ_WIFI_RST) | \ + PIN_OSPEED_VERYLOW(GPIOJ_DSI_RESET)) +#define VAL_GPIOJ_PUPDR (PIN_PUPDR_FLOATING(GPIOJ_ARD_D4) | \ + PIN_PUPDR_FLOATING(GPIOJ_ARD_D2) | \ + PIN_PUPDR_FLOATING(GPIOJ_DSI_TE) | \ + PIN_PUPDR_FLOATING(GPIOJ_ARD_D7) | \ + PIN_PUPDR_FLOATING(GPIOJ_ARD_D8) | \ + PIN_PUPDR_FLOATING(GPIOJ_LED2_GREEN) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOJ_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOJ_AUDIO_INT) | \ + PIN_PUPDR_FLOATING(GPIOJ_LED1_RED) | \ + PIN_PUPDR_FLOATING(GPIOJ_WIFI_RST) | \ + PIN_PUPDR_FLOATING(GPIOJ_DSI_RESET)) +#define VAL_GPIOJ_ODR (PIN_ODR_HIGH(GPIOJ_ARD_D4) | \ + PIN_ODR_HIGH(GPIOJ_ARD_D2) | \ + PIN_ODR_HIGH(GPIOJ_DSI_TE) | \ + PIN_ODR_HIGH(GPIOJ_ARD_D7) | \ + PIN_ODR_HIGH(GPIOJ_ARD_D8) | \ + PIN_ODR_LOW(GPIOJ_LED2_GREEN) | \ + PIN_ODR_HIGH(GPIOJ_PIN6) | \ + PIN_ODR_HIGH(GPIOJ_PIN7) | \ + PIN_ODR_HIGH(GPIOJ_PIN8) | \ + PIN_ODR_HIGH(GPIOJ_PIN9) | \ + PIN_ODR_HIGH(GPIOJ_PIN10) | \ + PIN_ODR_HIGH(GPIOJ_PIN11) | \ + PIN_ODR_HIGH(GPIOJ_AUDIO_INT) | \ + PIN_ODR_LOW(GPIOJ_LED1_RED) | \ + PIN_ODR_HIGH(GPIOJ_WIFI_RST) | \ + PIN_ODR_HIGH(GPIOJ_DSI_RESET)) +#define VAL_GPIOJ_AFRL (PIN_AFIO_AF(GPIOJ_ARD_D4, 0) | \ + PIN_AFIO_AF(GPIOJ_ARD_D2, 0) | \ + PIN_AFIO_AF(GPIOJ_DSI_TE, 13) | \ + PIN_AFIO_AF(GPIOJ_ARD_D7, 0) | \ + PIN_AFIO_AF(GPIOJ_ARD_D8, 0) | \ + PIN_AFIO_AF(GPIOJ_LED2_GREEN, 0) | \ + PIN_AFIO_AF(GPIOJ_PIN6, 0) | \ + PIN_AFIO_AF(GPIOJ_PIN7, 0)) +#define VAL_GPIOJ_AFRH (PIN_AFIO_AF(GPIOJ_PIN8, 0) | \ + PIN_AFIO_AF(GPIOJ_PIN9, 0) | \ + PIN_AFIO_AF(GPIOJ_PIN10, 0) | \ + PIN_AFIO_AF(GPIOJ_PIN11, 0) | \ + PIN_AFIO_AF(GPIOJ_AUDIO_INT, 0) | \ + PIN_AFIO_AF(GPIOJ_LED1_RED, 0) | \ + PIN_AFIO_AF(GPIOJ_WIFI_RST, 0) | \ + PIN_AFIO_AF(GPIOJ_DSI_RESET, 0)) + +/* + * GPIOK setup: + * + * PK0 - PIN0 (input floating). + * PK1 - PIN1 (input floating). + * PK2 - PIN2 (input floating). + * PK3 - PIN3 (input floating). + * PK4 - PIN4 (input floating). + * PK5 - PIN5 (input floating). + * PK6 - PIN6 (input floating). + * PK7 - PIN7 (input floating). + * PK8 - PIN8 (input floating). + * PK9 - PIN9 (input floating). + * PK10 - PIN10 (input floating). + * PK11 - PIN11 (input floating). + * PK12 - PIN12 (input floating). + * PK13 - PIN13 (input floating). + * PK14 - PIN14 (input floating). + * PK15 - PIN15 (input floating). + */ +#define VAL_GPIOK_MODER (PIN_MODE_INPUT(GPIOK_PIN0) | \ + PIN_MODE_INPUT(GPIOK_PIN1) | \ + PIN_MODE_INPUT(GPIOK_PIN2) | \ + PIN_MODE_INPUT(GPIOK_PIN3) | \ + PIN_MODE_INPUT(GPIOK_PIN4) | \ + PIN_MODE_INPUT(GPIOK_PIN5) | \ + PIN_MODE_INPUT(GPIOK_PIN6) | \ + PIN_MODE_INPUT(GPIOK_PIN7) | \ + PIN_MODE_INPUT(GPIOK_PIN8) | \ + PIN_MODE_INPUT(GPIOK_PIN9) | \ + PIN_MODE_INPUT(GPIOK_PIN10) | \ + PIN_MODE_INPUT(GPIOK_PIN11) | \ + PIN_MODE_INPUT(GPIOK_PIN12) | \ + PIN_MODE_INPUT(GPIOK_PIN13) | \ + PIN_MODE_INPUT(GPIOK_PIN14) | \ + PIN_MODE_INPUT(GPIOK_PIN15)) +#define VAL_GPIOK_OTYPER (PIN_OTYPE_PUSHPULL(GPIOK_PIN0) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN1) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN2) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN3) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN4) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN5) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN6) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN7) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN8) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN9) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN10) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN11) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN12) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN13) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN14) | \ + PIN_OTYPE_PUSHPULL(GPIOK_PIN15)) +#define VAL_GPIOK_OSPEEDR (PIN_OSPEED_VERYLOW(GPIOK_PIN0) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN1) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN2) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN3) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN4) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN5) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN6) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN7) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN8) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN9) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN10) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN11) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN12) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN13) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN14) | \ + PIN_OSPEED_VERYLOW(GPIOK_PIN15)) +#define VAL_GPIOK_PUPDR (PIN_PUPDR_FLOATING(GPIOK_PIN0) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN1) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN2) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN3) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN4) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN5) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN6) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN7) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN8) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN9) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN10) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN11) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN12) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN13) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN14) | \ + PIN_PUPDR_FLOATING(GPIOK_PIN15)) +#define VAL_GPIOK_ODR (PIN_ODR_HIGH(GPIOK_PIN0) | \ + PIN_ODR_HIGH(GPIOK_PIN1) | \ + PIN_ODR_HIGH(GPIOK_PIN2) | \ + PIN_ODR_HIGH(GPIOK_PIN3) | \ + PIN_ODR_HIGH(GPIOK_PIN4) | \ + PIN_ODR_HIGH(GPIOK_PIN5) | \ + PIN_ODR_HIGH(GPIOK_PIN6) | \ + PIN_ODR_HIGH(GPIOK_PIN7) | \ + PIN_ODR_HIGH(GPIOK_PIN8) | \ + PIN_ODR_HIGH(GPIOK_PIN9) | \ + PIN_ODR_HIGH(GPIOK_PIN10) | \ + PIN_ODR_HIGH(GPIOK_PIN11) | \ + PIN_ODR_HIGH(GPIOK_PIN12) | \ + PIN_ODR_HIGH(GPIOK_PIN13) | \ + PIN_ODR_HIGH(GPIOK_PIN14) | \ + PIN_ODR_HIGH(GPIOK_PIN15)) +#define VAL_GPIOK_AFRL (PIN_AFIO_AF(GPIOK_PIN0, 0) | \ + PIN_AFIO_AF(GPIOK_PIN1, 0) | \ + PIN_AFIO_AF(GPIOK_PIN2, 0) | \ + PIN_AFIO_AF(GPIOK_PIN3, 0) | \ + PIN_AFIO_AF(GPIOK_PIN4, 0) | \ + PIN_AFIO_AF(GPIOK_PIN5, 0) | \ + PIN_AFIO_AF(GPIOK_PIN6, 0) | \ + PIN_AFIO_AF(GPIOK_PIN7, 0)) +#define VAL_GPIOK_AFRH (PIN_AFIO_AF(GPIOK_PIN8, 0) | \ + PIN_AFIO_AF(GPIOK_PIN9, 0) | \ + PIN_AFIO_AF(GPIOK_PIN10, 0) | \ + PIN_AFIO_AF(GPIOK_PIN11, 0) | \ + PIN_AFIO_AF(GPIOK_PIN12, 0) | \ + PIN_AFIO_AF(GPIOK_PIN13, 0) | \ + PIN_AFIO_AF(GPIOK_PIN14, 0) | \ + PIN_AFIO_AF(GPIOK_PIN15, 0)) + + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/os/hal/boards/ST_STM32F769I_DISCOVERY/board.mk b/os/hal/boards/ST_STM32F769I_DISCOVERY/board.mk new file mode 100644 index 000000000..1182a953a --- /dev/null +++ b/os/hal/boards/ST_STM32F769I_DISCOVERY/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = $(CHIBIOS)/os/hal/boards/ST_STM32F769I_DISCOVERY/board.c + +# Required include directories +BOARDINC = $(CHIBIOS)/os/hal/boards/ST_STM32F769I_DISCOVERY diff --git a/os/hal/boards/ST_STM32F769I_DISCOVERY/cfg/board.chcfg b/os/hal/boards/ST_STM32F769I_DISCOVERY/cfg/board.chcfg new file mode 100644 index 000000000..2e5a38e3c --- /dev/null +++ b/os/hal/boards/ST_STM32F769I_DISCOVERY/cfg/board.chcfg @@ -0,0 +1,1466 @@ + + + + + resources/gencfg/processors/boards/stm32f7xx/templates + .. + 3.0.x + + STMicroelectronics STM32F769I-Discovery + ST_STM32F769I_DISCOVERY + + + + + + MII_LAN8742A_ID + RMII + + + ULPI + + STM32F769xx + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/os/hal/ports/STM32/STM32F7xx/hal_lld.h b/os/hal/ports/STM32/STM32F7xx/hal_lld.h index 2a8f5a733..ea417132d 100644 --- a/os/hal/ports/STM32/STM32F7xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F7xx/hal_lld.h @@ -63,6 +63,9 @@ #elif defined(STM32F767xx) #define PLATFORM_NAME "STM32F767 Very High Performance with DSP and DP FPU" +#elif defined(STM32F769xx) +#define PLATFORM_NAME "STM32F769 Very High Performance with DSP and DP FPU" + #else #error "STM32F7xx device not specified" #endif diff --git a/os/hal/ports/STM32/STM32F7xx/stm32_registry.h b/os/hal/ports/STM32/STM32F7xx/stm32_registry.h index 709922066..4d2857b0f 100644 --- a/os/hal/ports/STM32/STM32F7xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F7xx/stm32_registry.h @@ -34,10 +34,10 @@ * @{ */ /*===========================================================================*/ -/* STM32F745xx, STM32F746xx, STM32F756xx, STM32F767xx. */ +/* STM32F745xx, STM32F746xx, STM32F756xx, STM32F767xx, STM32F769xx. */ /*===========================================================================*/ #if defined(STM32F745xx) || defined(STM32F746xx) || defined(STM32F756xx) || \ - defined(STM32F767xx) || defined(__DOXYGEN__) + defined(STM32F767xx) || defined(STM32F769xx) || defined(__DOXYGEN__) /* ADC attributes.*/ #define STM32_ADC_HANDLER Vector88 #define STM32_ADC_NUMBER 18 -- cgit v1.2.3