From 36d2323f50a42946f11d41f727dd8fe30b1084c5 Mon Sep 17 00:00:00 2001
From: acirillo87 <acirillo87@35acf78f-673a-0410-8e92-d51de3d6d3f4>
Date: Tue, 5 Mar 2013 15:56:22 +0000
Subject: git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@5365
 35acf78f-673a-0410-8e92-d51de3d6d3f4

---
 os/hal/platforms/SPC560Pxx/spc560p_registry.h |   9 +-
 os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.c  | 316 +++++++++++++-------------
 2 files changed, 161 insertions(+), 164 deletions(-)

diff --git a/os/hal/platforms/SPC560Pxx/spc560p_registry.h b/os/hal/platforms/SPC560Pxx/spc560p_registry.h
index 6a39541a6..2ebc3c9c2 100644
--- a/os/hal/platforms/SPC560Pxx/spc560p_registry.h
+++ b/os/hal/platforms/SPC560Pxx/spc560p_registry.h
@@ -64,7 +64,6 @@
 
 /* FlexPWM attributes.*/
 #define SPC5_HAS_FLEXPWM0                   TRUE
-#define SPC5_FLEXPWM0_CLK_SOURCE            SPC5_MCONTROL_CLK
 #define SPC5_FLEXPWM0_PCTL                  41
 #define SPC5_FLEXPWM0_RF0_HANDLER           vector179
 #define SPC5_FLEXPWM0_COF0_HANDLER          vector180
@@ -94,13 +93,12 @@
 #define SPC5_FLEXPWM0_CAF3_NUMBER           190
 #define SPC5_FLEXPWM0_FFLAG_NUMBER          191
 #define SPC5_FLEXPWM0_REF_NUMBER            192
-#define SPC5_FLEXPWM0_CLK                   SPC5_FLEXPWM0_CLK_SOURCE
+#define SPC5_FLEXPWM0_CLK                   SPC5_MCONTROL_CLK
 
 #define SPC5_HAS_FLEXPWM1                   FALSE
 
 /* eTimer attributes.*/
 #define SPC5_HAS_ETIMER0                    TRUE
-#define SPC5_ETIMER0_CLK_SOURCE             SPC5_MCONTROL_CLK
 #define SPC5_ETIMER0_PCTL                   38
 #define SPC5_ETIMER0_TC0IR_HANDLER          vector157
 #define SPC5_ETIMER0_TC1IR_HANDLER          vector158
@@ -118,10 +116,9 @@
 #define SPC5_ETIMER0_TC5IR_NUMBER           162
 #define SPC5_ETIMER0_WTIF_NUMBER            165
 #define SPC5_ETIMER0_RCF_NUMBER             167
-#define SPC5_ETIMER0_CLK                    SPC5_ETIMER0_CLK_SOURCE
+#define SPC5_ETIMER0_CLK                    SPC5_MCONTROL_CLK
 
 #define SPC5_HAS_ETIMER1                    TRUE
-#define SPC5_ETIMER1_CLK_SOURCE             SPC5_MCONTROL_CLK
 #define SPC5_ETIMER1_PCTL                   39
 #define SPC5_ETIMER1_TC0IR_HANDLER          vector168
 #define SPC5_ETIMER1_TC1IR_HANDLER          vector169
@@ -137,7 +134,7 @@
 #define SPC5_ETIMER1_TC4IR_NUMBER           172
 #define SPC5_ETIMER1_TC5IR_NUMBER           173
 #define SPC5_ETIMER1_RCF_NUMBER             178
-#define SPC5_ETIMER1_CLK                    SPC5_ETIMER1_CLK_SOURCE
+#define SPC5_ETIMER1_CLK                    SPC5_MCONTROL_CLK
 
 #endif /* _SPC560P_REGISTRY_H_ */
 
diff --git a/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.c b/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.c
index 6d7416a32..908d634b0 100644
--- a/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.c
+++ b/os/hal/platforms/SPC5xx/FlexPWM_v1/pwm_lld.c
@@ -86,41 +86,41 @@ void pwm_lld_start_submodule(PWMDriver *pwmp, uint8_t sid) {
   pwmp->flexpwmp->SUB[sid].STS.R = 0xFFFF;
 
   /* Clears LDOK and initializes the registers.*/
-  pwmp->flexpwmp->MCTRL.B.CLDOK |= ( 0b0000 | (1U << sid) );
+  pwmp->flexpwmp->MCTRL.B.CLDOK |= (0b0000 | (1U << sid));
   pwmp->flexpwmp->SUB[sid].OCTRL.R = 0x0000;
   pwmp->flexpwmp->SUB[sid].INTEN.R = 0x0000;
 
   /* Setting PWM clock frequency and submodule prescaler.*/
-  psc = ( SPC5_FLEXPWM0_CLK / pwmp->config->frequency );
-  chDbgAssert((psc <= 0xFFFF) &&                                             \
-             (((psc) * pwmp->config->frequency) == SPC5_FLEXPWM0_CLK) &&     \
-             ((psc == 1) || (psc == 2) || (psc == 4) || (psc == 8) ||        \
-             (psc == 16) || (psc == 32) ||                                   \
-             (psc == 64) || (psc == 128)),
-             "icu_lld_start(), #1", "invalid frequency");
-  switch(psc){
-  case 1:
+  psc = (SPC5_FLEXPWM0_CLK / pwmp->config->frequency);
+  chDbgAssert((psc <= 0xFFFF) &&
+      (((psc) * pwmp->config->frequency) == SPC5_FLEXPWM0_CLK) &&
+      ((psc == 1) || (psc == 2) || (psc == 4) || (psc == 8) ||
+          (psc == 16) || (psc == 32) ||
+          (psc == 64) || (psc == 128)),
+      "icu_lld_start(), #1", "invalid frequency");
+  switch(psc) {
+    case 1:
     pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = 0b000;
     break;
-  case 2:
+    case 2:
     pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = 0b001;
     break;
-  case 4:
+    case 4:
     pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = 0b010;
     break;
-  case 8:
+    case 8:
     pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = 0b011;
     break;
-  case 16:
+    case 16:
     pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = 0b100;
     break;
-  case 32:
+    case 32:
     pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = 0b101;
     break;
-  case 64:
+    case 64:
     pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = 0b110;
     break;
-  case 128:
+    case 128:
     pwmp->flexpwmp->SUB[sid].CTRL.B.PRSC = 0b111;
     break;
   }
@@ -138,126 +138,126 @@ void pwm_lld_start_submodule(PWMDriver *pwmp, uint8_t sid) {
 
   /* Sets the submodule channels.*/
   switch (pwmp->config->mode & PWM_OUTPUT_MASK) {
-  case EDGE_ALIGNED_PWM:
+    case EDGE_ALIGNED_PWM:
     /* Setting reloads.*/
     pwmp->flexpwmp->SUB[sid].CTRL.B.HALF = 0;
     pwmp->flexpwmp->SUB[sid].CTRL.B.FULL = 1;
 
     /* Setting active front of PWM channels.*/
-    pwmp->flexpwmp->SUB[sid].VAL[2].R =  ~(pwmperiod / 2) + 1U;
-    pwmp->flexpwmp->SUB[sid].VAL[4].R =  ~(pwmperiod / 2) + 1U;
+    pwmp->flexpwmp->SUB[sid].VAL[2].R = ~(pwmperiod / 2) + 1U;
+    pwmp->flexpwmp->SUB[sid].VAL[4].R = ~(pwmperiod / 2) + 1U;
     break;
-  case CENTER_ALIGNED_PWM:
+    case CENTER_ALIGNED_PWM:
     /* Setting reloads.*/
     pwmp->flexpwmp->SUB[sid].CTRL.B.HALF = 1;
     pwmp->flexpwmp->SUB[sid].CTRL.B.FULL = 0;
     break;
-  default:
+    default:
     ;
   }
 
   /* Polarities setup.*/
   switch (pwmp->config->channels[0].mode & PWM_OUTPUT_MASK) {
-  case PWM_OUTPUT_ACTIVE_LOW:
+    case PWM_OUTPUT_ACTIVE_LOW:
     pwmp->flexpwmp->SUB[sid].OCTRL.B.POLA = 1;
     /* Enables CHA mask.*/
-    pwmp->flexpwmp->MASK.B.MASKA |= ( 0b0000 | (1U << sid) );
+    pwmp->flexpwmp->MASK.B.MASKA |= (0b0000 | (1U << sid));
     /* Enables CHA.*/
-    pwmp->flexpwmp->OUTEN.B.PWMA_EN |= ( 0b0000 | (1U << sid) );
+    pwmp->flexpwmp->OUTEN.B.PWMA_EN |= (0b0000 | (1U << sid));
     break;
-  case PWM_OUTPUT_ACTIVE_HIGH:
+    case PWM_OUTPUT_ACTIVE_HIGH:
     pwmp->flexpwmp->SUB[sid].OCTRL.B.POLA = 0;
     /* Enables CHA mask.*/
-    pwmp->flexpwmp->MASK.B.MASKA |= ( 0b0000 | (1U << sid) );
+    pwmp->flexpwmp->MASK.B.MASKA |= (0b0000 | (1U << sid));
     /* Enables CHA.*/
-    pwmp->flexpwmp->OUTEN.B.PWMA_EN |= ( 0b0000 | (1U << sid) );
+    pwmp->flexpwmp->OUTEN.B.PWMA_EN |= (0b0000 | (1U << sid));
     break;
-  case PWM_OUTPUT_DISABLED:
+    case PWM_OUTPUT_DISABLED:
     /* Enables CHA mask.*/
-    pwmp->flexpwmp->MASK.B.MASKA |= ( 0b0000 | (1U << sid) );
+    pwmp->flexpwmp->MASK.B.MASKA |= (0b0000 | (1U << sid));
     break;
-  default:
+    default:
     ;
   }
   switch (pwmp->config->channels[1].mode & PWM_OUTPUT_MASK) {
-  case PWM_OUTPUT_ACTIVE_LOW:
+    case PWM_OUTPUT_ACTIVE_LOW:
     pwmp->flexpwmp->SUB[sid].OCTRL.B.POLB = 1;
     /* Enables CHB mask.*/
-    pwmp->flexpwmp->MASK.B.MASKB |= ( 0b0000 | (1U << sid) );
+    pwmp->flexpwmp->MASK.B.MASKB |= (0b0000 | (1U << sid));
     /* Enables CHB.*/
-    pwmp->flexpwmp->OUTEN.B.PWMB_EN |= ( 0b0000 | (1U << sid) );
+    pwmp->flexpwmp->OUTEN.B.PWMB_EN |= (0b0000 | (1U << sid));
     break;
-  case PWM_OUTPUT_ACTIVE_HIGH:
+    case PWM_OUTPUT_ACTIVE_HIGH:
     pwmp->flexpwmp->SUB[sid].OCTRL.B.POLB = 0;
     /* Enables CHB mask.*/
-    pwmp->flexpwmp->MASK.B.MASKB |= ( 0b0000 | (1U << sid) );
+    pwmp->flexpwmp->MASK.B.MASKB |= (0b0000 | (1U << sid));
     /* Enables CHB.*/
-    pwmp->flexpwmp->OUTEN.B.PWMB_EN |= ( 0b0000 | (1U << sid) );
+    pwmp->flexpwmp->OUTEN.B.PWMB_EN |= (0b0000 | (1U << sid));
     break;
-  case PWM_OUTPUT_DISABLED:
+    case PWM_OUTPUT_DISABLED:
     /* Enables CHB mask.*/
-      pwmp->flexpwmp->MASK.B.MASKB |= ( 0b0000 | (1U << sid) );
-      break;
-  default:
-    ;
-  }
-
-  /* Complementary output setup.*/
-/*  switch (pwmp->config->channels[0].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) {
-  case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW:
-    chDbgAssert(pwmp->config->channels[1].mode == PWM_OUTPUT_ACTIVE_LOW,
-                "pwm_lld_start(), #1",
-                "the PWM chB must be set in PWM_OUTPUT_ACTIVE_LOW");
-    //pwmp->flexpwmp->SUB[sid].OCTRL.B.POLA = 1;
-    pwmp->flexpwmp->SUB[sid].CTRL2.B.INDEP = 0;
-    pwmp->flexpwmp->MCTRL.B.IPOL |= ( 0b0000 | (1U << sid) );
-    pwmp->flexpwmp->MASK.B.MASKA |= ( 0b0000 | (1U << sid) );
-    pwmp->flexpwmp->OUTEN.B.PWMA_EN |= ( 0b0000 | (1U << sid) );
-    //pwmp->flexpwmp->SUB[0].OCTRL.B.POLB = 0;
+    pwmp->flexpwmp->MASK.B.MASKB |= (0b0000 | (1U << sid));
     break;
-  case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH:
-    chDbgAssert(pwmp->config->channels[1].mode == PWM_OUTPUT_ACTIVE_HIGH,
-                "pwm_lld_start(), #2",
-                "the PWM chB must be set in PWM_OUTPUT_ACTIVE_HIGH");
-    pwmp->flexpwmp->SUB[sid].CTRL2.B.INDEP = 0;
-    pwmp->flexpwmp->MCTRL.B.IPOL |= ( 0b0000 | (0U << sid) );
-    pwmp->flexpwmp->MASK.B.MASKA |= ( 0b0000 | (1U << sid) );
-    pwmp->flexpwmp->OUTEN.B.PWMA_EN |= ( 0b0000 | (1U << sid) );
-    // pwmp->flexpwmp->SUB[0].OCTRL.B.POLA = 0;
-    //pwmp->flexpwmp->SUB[0].OCTRL.B.POLB = 1;
-    break;
-  default:
+    default:
     ;
   }
 
-  switch (pwmp->config->channels[1].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) {
-  case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW:
-    chDbgAssert(pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_LOW,
-                "pwm_lld_start(), #3",
-                "the PWM chA must be set in PWM_OUTPUT_ACTIVE_LOW");
-    pwmp->flexpwmp->SUB[sid].CTRL2.B.INDEP = 0;
-    pwmp->flexpwmp->MCTRL.B.IPOL &= ~ ( 0b0000 | (1U << sid) );
-    //  pwmp->flexpwmp->SUB[0].OCTRL.B.POLA = 0;
-    pwmp->flexpwmp->SUB[sid].OCTRL.B.POLB = 1;
-    pwmp->flexpwmp->MASK.B.MASKB |= ( 0b0000 | (1U << sid) );
-    pwmp->flexpwmp->OUTEN.B.PWMB_EN |= ( 0b0000 | (1U << sid) );
-    break;
-  case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH:
-    chDbgAssert(pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_HIGH,
-                "pwm_lld_start(), #4",
-                "the PWM chA must be set in PWM_OUTPUT_ACTIVE_HIGH");
-    pwmp->flexpwmp->SUB[sid].CTRL2.B.INDEP = 0;
-    pwmp->flexpwmp->MCTRL.B.IPOL &= ~ ( 0b0000 | (1U << sid) );
-
-    pwmp->flexpwmp->MASK.B.MASKB |= ( 0b0000 | (1U << sid) );
-    pwmp->flexpwmp->OUTEN.B.PWMB_EN |= ( 0b0000 | (1U << sid) );
-    // pwmp->flexpwmp->SUB[0].OCTRL.B.POLA = 1;
-    // pwmp->flexpwmp->SUB[0].OCTRL.B.POLB = 0;
-    break;
-  default:
-    ;
-  }
-*/
+  /* Complementary output setup.*/
+  /*  switch (pwmp->config->channels[0].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) {
+   case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW:
+   chDbgAssert(pwmp->config->channels[1].mode == PWM_OUTPUT_ACTIVE_LOW,
+   "pwm_lld_start(), #1",
+   "the PWM chB must be set in PWM_OUTPUT_ACTIVE_LOW");
+   //pwmp->flexpwmp->SUB[sid].OCTRL.B.POLA = 1;
+   pwmp->flexpwmp->SUB[sid].CTRL2.B.INDEP = 0;
+   pwmp->flexpwmp->MCTRL.B.IPOL |= (0b0000 | (1U << sid));
+   pwmp->flexpwmp->MASK.B.MASKA |= (0b0000 | (1U << sid));
+   pwmp->flexpwmp->OUTEN.B.PWMA_EN |= (0b0000 | (1U << sid));
+   //pwmp->flexpwmp->SUB[0].OCTRL.B.POLB = 0;
+   break;
+   case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH:
+   chDbgAssert(pwmp->config->channels[1].mode == PWM_OUTPUT_ACTIVE_HIGH,
+   "pwm_lld_start(), #2",
+   "the PWM chB must be set in PWM_OUTPUT_ACTIVE_HIGH");
+   pwmp->flexpwmp->SUB[sid].CTRL2.B.INDEP = 0;
+   pwmp->flexpwmp->MCTRL.B.IPOL |= (0b0000 | (0U << sid));
+   pwmp->flexpwmp->MASK.B.MASKA |= (0b0000 | (1U << sid));
+   pwmp->flexpwmp->OUTEN.B.PWMA_EN |= (0b0000 | (1U << sid));
+   // pwmp->flexpwmp->SUB[0].OCTRL.B.POLA = 0;
+   //pwmp->flexpwmp->SUB[0].OCTRL.B.POLB = 1;
+   break;
+   default:
+   ;
+   }
+
+   switch (pwmp->config->channels[1].mode & PWM_COMPLEMENTARY_OUTPUT_MASK) {
+   case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_LOW:
+   chDbgAssert(pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_LOW,
+   "pwm_lld_start(), #3",
+   "the PWM chA must be set in PWM_OUTPUT_ACTIVE_LOW");
+   pwmp->flexpwmp->SUB[sid].CTRL2.B.INDEP = 0;
+   pwmp->flexpwmp->MCTRL.B.IPOL &= ~ (0b0000 | (1U << sid));
+   //  pwmp->flexpwmp->SUB[0].OCTRL.B.POLA = 0;
+   pwmp->flexpwmp->SUB[sid].OCTRL.B.POLB = 1;
+   pwmp->flexpwmp->MASK.B.MASKB |= (0b0000 | (1U << sid));
+   pwmp->flexpwmp->OUTEN.B.PWMB_EN |= (0b0000 | (1U << sid));
+   break;
+   case PWM_COMPLEMENTARY_OUTPUT_ACTIVE_HIGH:
+   chDbgAssert(pwmp->config->channels[0].mode == PWM_OUTPUT_ACTIVE_HIGH,
+   "pwm_lld_start(), #4",
+   "the PWM chA must be set in PWM_OUTPUT_ACTIVE_HIGH");
+   pwmp->flexpwmp->SUB[sid].CTRL2.B.INDEP = 0;
+   pwmp->flexpwmp->MCTRL.B.IPOL &= ~ (0b0000 | (1U << sid));
+
+   pwmp->flexpwmp->MASK.B.MASKB |= (0b0000 | (1U << sid));
+   pwmp->flexpwmp->OUTEN.B.PWMB_EN |= (0b0000 | (1U << sid));
+   // pwmp->flexpwmp->SUB[0].OCTRL.B.POLA = 1;
+   // pwmp->flexpwmp->SUB[0].OCTRL.B.POLB = 0;
+   break;
+   default:
+   ;
+   }
+   */
 
   /* Sets the INIT and MASK registers.*/
   pwmp->flexpwmp->SUB[sid].CTRL2.B.FRCEN = 1U;
@@ -265,8 +265,8 @@ void pwm_lld_start_submodule(PWMDriver *pwmp, uint8_t sid) {
   pwmp->flexpwmp->SUB[sid].CTRL2.B.FORCE = 1U;
 
   /* Updates SMOD registers and starts SMOD.*/
-  pwmp->flexpwmp->MCTRL.B.LDOK |= ( 0b0000 | (1U << sid) );
-  pwmp->flexpwmp->MCTRL.B.RUN |= ( 0b0000 | (1U << sid) );
+  pwmp->flexpwmp->MCTRL.B.LDOK |= (0b0000 | (1U << sid));
+  pwmp->flexpwmp->MCTRL.B.RUN |= (0b0000 | (1U << sid));
 }
 
 /**
@@ -280,8 +280,8 @@ void pwm_lld_start_submodule(PWMDriver *pwmp, uint8_t sid) {
  * @notapi
  */
 void pwm_lld_enable_submodule_channel(PWMDriver *pwmp,
-                                  pwmchannel_t channel,
-                                  pwmcnt_t width, uint8_t sid) {
+    pwmchannel_t channel,
+    pwmcnt_t width, uint8_t sid) {
 
   pwmcnt_t pwmperiod;
   int16_t nwidth;
@@ -289,7 +289,7 @@ void pwm_lld_enable_submodule_channel(PWMDriver *pwmp,
   nwidth = width - (pwmperiod / 2);
 
   /* Clears LDOK.*/
-  pwmp->flexpwmp->MCTRL.B.CLDOK |= ( 0b0000 | (1U << sid) );
+  pwmp->flexpwmp->MCTRL.B.CLDOK |= (0b0000 | (1U << sid));
 
   /* Active the width interrupt.*/
   if (channel == 0) {
@@ -301,23 +301,23 @@ void pwm_lld_enable_submodule_channel(PWMDriver *pwmp,
 
     /* Sets the channel width.*/
     switch (pwmp->config->mode & PWM_OUTPUT_MASK) {
-    case EDGE_ALIGNED_PWM:
-      if( nwidth >= 0 )
-        pwmp->flexpwmp->SUB[sid].VAL[3].R = nwidth;
+      case EDGE_ALIGNED_PWM:
+      if(nwidth >= 0)
+      pwmp->flexpwmp->SUB[sid].VAL[3].R = nwidth;
       else
-        pwmp->flexpwmp->SUB[sid].VAL[3].R = ~( (pwmperiod / 2) - width ) + 1U;
+      pwmp->flexpwmp->SUB[sid].VAL[3].R = ~((pwmperiod / 2) - width) + 1U;
       break;
-    case CENTER_ALIGNED_PWM:
+      case CENTER_ALIGNED_PWM:
       pwmp->flexpwmp->SUB[sid].VAL[3].R = width / 2;
-      pwmp->flexpwmp->SUB[sid].VAL[2].R = ~( width / 2 ) + 1U;
+      pwmp->flexpwmp->SUB[sid].VAL[2].R = ~(width / 2) + 1U;
       break;
-    default:
+      default:
       ;
     }
 
     /* Removes the channel mask if it is necessary.*/
-    if ( (pwmp->flexpwmp->MASK.B.MASKA & ( 0b0000 | (1U << sid))) == 1 )
-      pwmp->flexpwmp->MASK.B.MASKA &= ~ ( 0b0000 | (1U << sid) );
+    if ((pwmp->flexpwmp->MASK.B.MASKA & (0b0000 | (1U << sid))) == 1)
+    pwmp->flexpwmp->MASK.B.MASKA &= ~ (0b0000 | (1U << sid));
   }
   /* Active the width interrupt.*/
   else if (channel == 1) {
@@ -328,27 +328,27 @@ void pwm_lld_enable_submodule_channel(PWMDriver *pwmp,
     }
     /* Sets the channel width.*/
     switch (pwmp->config->mode & PWM_OUTPUT_MASK) {
-    case EDGE_ALIGNED_PWM:
-      if( nwidth >= 0 )
-        pwmp->flexpwmp->SUB[sid].VAL[5].R = nwidth;
+      case EDGE_ALIGNED_PWM:
+      if(nwidth >= 0)
+      pwmp->flexpwmp->SUB[sid].VAL[5].R = nwidth;
       else
-        pwmp->flexpwmp->SUB[sid].VAL[5].R = ~( (pwmperiod / 2) - width ) + 1U;
+      pwmp->flexpwmp->SUB[sid].VAL[5].R = ~((pwmperiod / 2) - width) + 1U;
       break;
-    case CENTER_ALIGNED_PWM:
+      case CENTER_ALIGNED_PWM:
       pwmp->flexpwmp->SUB[sid].VAL[5].R = width / 2;
-      pwmp->flexpwmp->SUB[sid].VAL[4].R = ~( width / 2 ) + 1U;
+      pwmp->flexpwmp->SUB[sid].VAL[4].R = ~(width / 2) + 1U;
       break;
-    default:
+      default:
       ;
     }
 
     /* Removes the channel mask if it is necessary.*/
-    if ( (pwmp->flexpwmp->MASK.B.MASKB & ( 0b0000 | (1U << sid))) == 1 )
-      pwmp->flexpwmp->MASK.B.MASKB &= ~ ( 0b0000 | (1U << sid) );
+    if ((pwmp->flexpwmp->MASK.B.MASKB & (0b0000 | (1U << sid))) == 1)
+    pwmp->flexpwmp->MASK.B.MASKB &= ~ (0b0000 | (1U << sid));
   }
 
   /* Active the periodic interrupt.*/
-  if ( pwmp->flexpwmp->SUB[sid].INTEN.B.RIE != 1U ) {
+  if (pwmp->flexpwmp->SUB[sid].INTEN.B.RIE != 1U) {
     if (pwmp->config->callback != NULL) {
       pwmp->flexpwmp->SUB[sid].INTEN.B.RIE = 1;
     }
@@ -360,7 +360,7 @@ void pwm_lld_enable_submodule_channel(PWMDriver *pwmp,
   pwmp->flexpwmp->SUB[sid].CTRL2.B.FORCE = 1U;
 
   /* Forces reload of the VALUE registers.*/
-  pwmp->flexpwmp->MCTRL.B.LDOK |= ( 0b0000 | (1U << sid) );
+  pwmp->flexpwmp->MCTRL.B.LDOK |= (0b0000 | (1U << sid));
 }
 
 /**
@@ -373,10 +373,10 @@ void pwm_lld_enable_submodule_channel(PWMDriver *pwmp,
  * @notapi
  */
 void pwm_lld_disable_submodule_channel(PWMDriver *pwmp,
-                                   pwmchannel_t channel,
-                                   uint8_t sid) {
+    pwmchannel_t channel,
+    uint8_t sid) {
 
-  pwmp->flexpwmp->MCTRL.B.CLDOK |= ( 0b0000 | (1U << sid) );
+  pwmp->flexpwmp->MCTRL.B.CLDOK |= (0b0000 | (1U << sid));
 
   /* Disable the width interrupt.*/
   if (channel == 0) {
@@ -387,7 +387,7 @@ void pwm_lld_disable_submodule_channel(PWMDriver *pwmp,
     }
 
     /* Active the channel mask.*/
-    pwmp->flexpwmp->MASK.B.MASKA |= ( 0b0000 | (1U << sid) );
+    pwmp->flexpwmp->MASK.B.MASKA |= (0b0000 | (1U << sid));
   }
   /* Disable the width interrupt.*/
   else if (channel == 1) {
@@ -398,7 +398,7 @@ void pwm_lld_disable_submodule_channel(PWMDriver *pwmp,
     }
 
     /* Active the channel mask.*/
-    pwmp->flexpwmp->MASK.B.MASKB |= ( 0b0000 | (1U << sid) );
+    pwmp->flexpwmp->MASK.B.MASKB |= (0b0000 | (1U << sid));
   }
 
   /* Sets the MASK registers.*/
@@ -407,14 +407,14 @@ void pwm_lld_disable_submodule_channel(PWMDriver *pwmp,
   pwmp->flexpwmp->SUB[sid].CTRL2.B.FORCE = 1U;
 
   /* Disable RIE interrupt to prevent reload interrupt.*/
-  if( (pwmp->flexpwmp->MASK.B.MASKA & ( 0b0000 | (1U << sid))) &&
-      (pwmp->flexpwmp->MASK.B.MASKB & ( 0b0000 | (1U << sid))) == 1 ) {
+  if((pwmp->flexpwmp->MASK.B.MASKA & (0b0000 | (1U << sid))) &&
+      (pwmp->flexpwmp->MASK.B.MASKB & (0b0000 | (1U << sid))) == 1) {
     pwmp->flexpwmp->SUB[sid].INTEN.B.RIE = 0;
     /* Clear the reload flag.*/
     pwmp->flexpwmp->SUB[sid].STS.B.RF = 1U;
-    }
+  }
 
-  pwmp->flexpwmp->MCTRL.B.LDOK |= ( 0b0000 | (1U << sid) );
+  pwmp->flexpwmp->MCTRL.B.LDOK |= (0b0000 | (1U << sid));
 }
 
 #if SPC5_PWM_USE_SMOD0 || SPC5_PWM_USE_SMOD1 || SPC5_PWM_USE_SMOD2 ||         \
@@ -724,19 +724,19 @@ void pwm_lld_start(PWMDriver *pwmp) {
 
 #if SPC5_PWM_USE_SMOD0
     if (PWMD1.state == PWM_READY)
-      SMOD0 = 1U;
+    SMOD0 = 1U;
 #endif
 #if SPC5_PWM_USE_SMOD1
     if (PWMD2.state == PWM_READY)
-      SMOD1 = 1U;
+    SMOD1 = 1U;
 #endif
 #if SPC5_PWM_USE_SMOD2
     if (PWMD3.state == PWM_READY)
-      SMOD2 = 1U;
+    SMOD2 = 1U;
 #endif
 #if SPC5_PWM_USE_SMOD3
     if (PWMD4.state == PWM_READY)
-      SMOD3 = 1U;
+    SMOD3 = 1U;
 #endif
 
     /* Set Peripheral Clock.*/
@@ -908,12 +908,12 @@ void pwm_lld_stop(PWMDriver *pwmp) {
 #endif
 
     /* Disable peripheral clock if there is not an activated module.*/
-    if ( (pwmp->flexpwmp->MCTRL.B.RUN & 0b0001) ||
-         (pwmp->flexpwmp->MCTRL.B.RUN & 0b0010) ||
-         (pwmp->flexpwmp->MCTRL.B.RUN & 0b0100) ||
-         (pwmp->flexpwmp->MCTRL.B.RUN & 0b1000) == 0 ) {
-        halSPCSetPeripheralClockMode(SPC5_FLEXPWM0_PCTL,
-                     SPC5_PWM_FLEXPWM0_STOP_PCTL);
+    if ((pwmp->flexpwmp->MCTRL.B.RUN & 0b0001) ||
+        (pwmp->flexpwmp->MCTRL.B.RUN & 0b0010) ||
+        (pwmp->flexpwmp->MCTRL.B.RUN & 0b0100) ||
+        (pwmp->flexpwmp->MCTRL.B.RUN & 0b1000) == 0) {
+      halSPCSetPeripheralClockMode(SPC5_FLEXPWM0_PCTL,
+          SPC5_PWM_FLEXPWM0_STOP_PCTL);
     }
   }
 }
@@ -931,8 +931,8 @@ void pwm_lld_stop(PWMDriver *pwmp) {
  * @notapi
  */
 void pwm_lld_enable_channel(PWMDriver *pwmp,
-                            pwmchannel_t channel,
-                            pwmcnt_t width) {
+    pwmchannel_t channel,
+    pwmcnt_t width) {
 
 #if SPC5_PWM_USE_SMOD0
   if (&PWMD1 == pwmp) {
@@ -1023,13 +1023,13 @@ void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period) {
     pwmp->flexpwmp->SUB[0].VAL[1].R = pwmperiod / 2;
 
     switch (pwmp->config->mode & PWM_OUTPUT_MASK) {
-    case EDGE_ALIGNED_PWM:
+      case EDGE_ALIGNED_PWM:
 
       /* Setting active front of PWM channels.*/
-      pwmp->flexpwmp->SUB[0].VAL[2].R =  ~(pwmperiod / 2) + 1U;
-      pwmp->flexpwmp->SUB[0].VAL[4].R =  ~(pwmperiod / 2) + 1U;
+      pwmp->flexpwmp->SUB[0].VAL[2].R = ~(pwmperiod / 2) + 1U;
+      pwmp->flexpwmp->SUB[0].VAL[4].R = ~(pwmperiod / 2) + 1U;
       break;
-    default:
+      default:
       ;
     }
     pwmp->flexpwmp->MCTRL.B.LDOK |= 0b0001;
@@ -1045,13 +1045,13 @@ void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period) {
     pwmp->flexpwmp->SUB[1].VAL[1].R = pwmperiod / 2;
 
     switch (pwmp->config->mode & PWM_OUTPUT_MASK) {
-    case EDGE_ALIGNED_PWM:
+      case EDGE_ALIGNED_PWM:
 
       /* Setting active front of PWM channels.*/
-      pwmp->flexpwmp->SUB[1].VAL[2].R =  ~(pwmperiod / 2) + 1U;
-      pwmp->flexpwmp->SUB[1].VAL[4].R =  ~(pwmperiod / 2) + 1U;
+      pwmp->flexpwmp->SUB[1].VAL[2].R = ~(pwmperiod / 2) + 1U;
+      pwmp->flexpwmp->SUB[1].VAL[4].R = ~(pwmperiod / 2) + 1U;
       break;
-    default:
+      default:
       ;
     }
     pwmp->flexpwmp->MCTRL.B.LDOK |= 0b0010;
@@ -1067,13 +1067,13 @@ void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period) {
     pwmp->flexpwmp->SUB[2].VAL[1].R = pwmperiod / 2;
 
     switch (pwmp->config->mode & PWM_OUTPUT_MASK) {
-    case EDGE_ALIGNED_PWM:
+      case EDGE_ALIGNED_PWM:
 
       /* Setting active front of PWM channels.*/
-      pwmp->flexpwmp->SUB[2].VAL[2].R =  ~(pwmperiod / 2) + 1U;
-      pwmp->flexpwmp->SUB[2].VAL[4].R =  ~(pwmperiod / 2) + 1U;
+      pwmp->flexpwmp->SUB[2].VAL[2].R = ~(pwmperiod / 2) + 1U;
+      pwmp->flexpwmp->SUB[2].VAL[4].R = ~(pwmperiod / 2) + 1U;
       break;
-    default:
+      default:
       ;
     }
     pwmp->flexpwmp->MCTRL.B.LDOK |= 0b0100;
@@ -1089,13 +1089,13 @@ void pwm_lld_change_period(PWMDriver *pwmp, pwmcnt_t period) {
     pwmp->flexpwmp->SUB[3].VAL[1].R = pwmperiod / 2;
 
     switch (pwmp->config->mode & PWM_OUTPUT_MASK) {
-    case EDGE_ALIGNED_PWM:
+      case EDGE_ALIGNED_PWM:
 
       /* Setting active front of PWM channels.*/
-      pwmp->flexpwmp->SUB[3].VAL[2].R =  ~(pwmperiod / 2) + 1U;
-      pwmp->flexpwmp->SUB[3].VAL[4].R =  ~(pwmperiod / 2) + 1U;
+      pwmp->flexpwmp->SUB[3].VAL[2].R = ~(pwmperiod / 2) + 1U;
+      pwmp->flexpwmp->SUB[3].VAL[4].R = ~(pwmperiod / 2) + 1U;
       break;
-    default:
+      default:
       ;
     }
     pwmp->flexpwmp->MCTRL.B.LDOK |= 0b1000;
-- 
cgit v1.2.3