From 1e076f0a0aecc26fc53496c2f275855d36de8382 Mon Sep 17 00:00:00 2001 From: edolomb Date: Fri, 16 Feb 2018 17:14:23 +0000 Subject: Added demo SPI with Flexcom git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@11505 35acf78f-673a-0410-8e92-d51de3d6d3f4 --- testhal/ATSAMA5D2/FLEX-SPI/.cproject | 50 ++ testhal/ATSAMA5D2/FLEX-SPI/.project | 38 ++ testhal/ATSAMA5D2/FLEX-SPI/Makefile | 252 +++++++++ testhal/ATSAMA5D2/FLEX-SPI/chconf.h | 615 +++++++++++++++++++++ .../FLEX-SPI/debug/SAMA5D2-FLEX-SPI (DDRAM).launch | 55 ++ .../debug/SAMA5D2-FLEX-SPI (Load and Run).launch | 58 ++ .../debug/SAMA5D2-FLEX-SPI (bootstrap).launch | 55 ++ testhal/ATSAMA5D2/FLEX-SPI/halconf.h | 408 ++++++++++++++ testhal/ATSAMA5D2/FLEX-SPI/main.c | 125 +++++ testhal/ATSAMA5D2/FLEX-SPI/mcuconf.h | 143 +++++ testhal/ATSAMA5D2/FLEX-SPI/readme.txt | 13 + 11 files changed, 1812 insertions(+) create mode 100644 testhal/ATSAMA5D2/FLEX-SPI/.cproject create mode 100644 testhal/ATSAMA5D2/FLEX-SPI/.project create mode 100644 testhal/ATSAMA5D2/FLEX-SPI/Makefile create mode 100644 testhal/ATSAMA5D2/FLEX-SPI/chconf.h create mode 100644 testhal/ATSAMA5D2/FLEX-SPI/debug/SAMA5D2-FLEX-SPI (DDRAM).launch create mode 100644 testhal/ATSAMA5D2/FLEX-SPI/debug/SAMA5D2-FLEX-SPI (Load and Run).launch create mode 100644 testhal/ATSAMA5D2/FLEX-SPI/debug/SAMA5D2-FLEX-SPI (bootstrap).launch create mode 100644 testhal/ATSAMA5D2/FLEX-SPI/halconf.h create mode 100644 testhal/ATSAMA5D2/FLEX-SPI/main.c create mode 100644 testhal/ATSAMA5D2/FLEX-SPI/mcuconf.h create mode 100644 testhal/ATSAMA5D2/FLEX-SPI/readme.txt diff --git a/testhal/ATSAMA5D2/FLEX-SPI/.cproject b/testhal/ATSAMA5D2/FLEX-SPI/.cproject new file mode 100644 index 000000000..2ed53745e --- /dev/null +++ b/testhal/ATSAMA5D2/FLEX-SPI/.cproject @@ -0,0 +1,50 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/ATSAMA5D2/FLEX-SPI/.project b/testhal/ATSAMA5D2/FLEX-SPI/.project new file mode 100644 index 000000000..b0f3c26e6 --- /dev/null +++ b/testhal/ATSAMA5D2/FLEX-SPI/.project @@ -0,0 +1,38 @@ + + + SAMA5D2-FLEX-SPI + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + CHIBIOS/os/hal/boards/ATSAMA5D2_XULT + + + os + 2 + CHIBIOS/os + + + diff --git a/testhal/ATSAMA5D2/FLEX-SPI/Makefile b/testhal/ATSAMA5D2/FLEX-SPI/Makefile new file mode 100644 index 000000000..d80992791 --- /dev/null +++ b/testhal/ATSAMA5D2/FLEX-SPI/Makefile @@ -0,0 +1,252 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO) +ifeq ($(USE_LTO),) + USE_LTO = yes +endif + +# If enabled, this option allows to compile the application in THUMB mode. +ifeq ($(USE_THUMB),) + USE_THUMB = no +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the ARM System/User stack. This +# stack is the stack used by the main() thread. +ifeq ($(USE_SYSTEM_STACKSIZE),) + USE_SYSTEM_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the ARM IRQ stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_IRQ_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the ARM FIQ stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_FIQ_STACKSIZE),) + USE_FIQ_STACKSIZE = 64 +endif + +# Stack size to the allocated to the ARM Supervisor stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_SUPERVISOR_STACKSIZE),) + USE_SUPERVISOR_STACKSIZE = 8 +endif + +# Stack size to the allocated to the ARM Undefined stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_UND_STACKSIZE),) + USE_UND_STACKSIZE = 8 +endif + +# Stack size to the allocated to the ARM Abort stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_ABT_STACKSIZE),) + USE_ABT_STACKSIZE = 8 +endif + +# Enables the use of FPU. +ifeq ($(USE_FPU),) + USE_FPU = no +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, sources and paths +# + +# Define project name here +PROJECT = ch + +# Imported source files and paths +CHIBIOS = ../../.. +# Startup files. +include $(CHIBIOS)/os/common/startup/ARMCAx-TZ/compilers/GCC/mk/startup_sama5d2.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/hal/ports/SAMA/SAMA5D2x/platform.mk +include $(CHIBIOS)/os/hal/boards/ATSAMA5D2_XULT/board.mk +include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMCAx-TZ/compilers/GCC/mk/port_generic.mk +# Other files (optional). +#include $(CHIBIOS)/test/lib/test.mk +#include $(CHIBIOS)/test/rt/rt_test.mk +#include $(CHIBIOS)/test/oslib/oslib_test.mk + +# Define linker script file here +#LDSCRIPT= $(STARTUPLD)/SAMA5D2.ld +# Only if SAMA_NO_INIT is TRUE +LDSCRIPT= $(STARTUPLD)/SAMA5D2ddr.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(STARTUPSRC) \ + $(KERNSRC) \ + $(PORTSRC) \ + $(OSALSRC) \ + $(HALSRC) \ + $(PLATFORMSRC) \ + $(BOARDSRC) \ + $(TESTSRC) \ + main.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = + +# C sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACSRC = + +# C++ sources to be compiled in ARM mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +ACPPSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCSRC = + +# C sources to be compiled in THUMB mode regardless of the global setting. +# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler +# option that results in lower performance and larger code size. +TCPPSRC = + +# List ASM source files here +ASMSRC = +ASMXSRC = $(STARTUPASM) $(PORTASM) $(OSALASM) + +INCDIR = $(CHIBIOS)/os/license \ + $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ + $(HALINC) $(PLATFORMINC) $(BOARDINC) $(TESTINC) \ + $(CHIBIOS)/os/various + +# +# Project, sources and paths +############################################################################## + +############################################################################## +# Compiler settings +# + +MCU = cortex-a5 + +#TRGT = arm-elf- +TRGT = arm-none-eabi- +CC = $(TRGT)gcc +CPPC = $(TRGT)g++ +# Enable loading with g++ only if you need C++ runtime support. +# NOTE: You can use C++ even without C++ support if you are careful. C++ +# runtime support makes code size explode. +LD = $(TRGT)gcc +#LD = $(TRGT)g++ +CP = $(TRGT)objcopy +AS = $(TRGT)gcc -x assembler-with-cpp +AR = $(TRGT)ar +OD = $(TRGT)objdump +SZ = $(TRGT)size +HEX = $(CP) -O ihex +BIN = $(CP) -O binary + +# ARM-specific options here +AOPT = + +# THUMB-specific options here +TOPT = -mthumb -DTHUMB + +# Define C warning options here +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here +CPPWARN = -Wall -Wextra -Wundef + +# +# Compiler settings +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user defines +############################################################################## + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCAx-TZ/compilers/GCC +include $(RULESPATH)/rules.mk + +############################################################################## +# MISRA check rule, requires PCLint and the setup files, not provided. +# +misra: + @lint-nt -v -w3 $(DEFS) pclint/co-gcc.lnt pclint/au-misra3.lnt pclint/waivers.lnt $(IINCDIR) $(CSRC) &> misra.txt diff --git a/testhal/ATSAMA5D2/FLEX-SPI/chconf.h b/testhal/ATSAMA5D2/FLEX-SPI/chconf.h new file mode 100644 index 000000000..49b16647b --- /dev/null +++ b/testhal/ATSAMA5D2/FLEX-SPI/chconf.h @@ -0,0 +1,615 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_5_0_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_ST_RESOLUTION 32 + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#define CH_CFG_ST_FREQUENCY 1000 + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#define CH_CFG_INTERVALS_SIZE 32 + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#define CH_CFG_TIME_TYPES_SIZE 32 + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#define CH_CFG_ST_TIMEDELTA 0 + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#define CH_CFG_TIME_QUANTUM 0 + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#define CH_CFG_MEMCORE_SIZE 0 + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#define CH_CFG_NO_IDLE_THREAD FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#define CH_CFG_OPTIMIZE_SPEED TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_TM FALSE + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_REGISTRY TRUE + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_WAITEXIT TRUE + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_SEMAPHORES TRUE + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MUTEXES TRUE + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#define CH_CFG_USE_CONDVARS TRUE + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_EVENTS TRUE + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MESSAGES TRUE + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#define CH_CFG_USE_MAILBOXES TRUE + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMCORE TRUE + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#define CH_CFG_USE_HEAP TRUE + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_MEMPOOLS TRUE + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#define CH_CFG_USE_OBJ_FIFOS TRUE + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#define CH_CFG_USE_DYNAMIC TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#define CH_CFG_USE_FACTORY TRUE + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 + +/** + * @brief Enables the registry of generic objects. + */ +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE + +/** + * @brief Enables factory for generic buffers. + */ +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE + +/** + * @brief Enables factory for semaphores. + */ +#define CH_CFG_FACTORY_SEMAPHORES TRUE + +/** + * @brief Enables factory for mailboxes. + */ +#define CH_CFG_FACTORY_MAILBOXES TRUE + +/** + * @brief Enables factory for objects FIFOs. + */ +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_STATISTICS FALSE + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_SYSTEM_STATE_CHECK FALSE + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_CHECKS FALSE + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_ENABLE_ASSERTS FALSE + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#define CH_DBG_TRACE_BUFFER_SIZE 128 + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#define CH_DBG_ENABLE_STACK_CHECK FALSE + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#define CH_DBG_FILL_THREADS FALSE + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#define CH_DBG_THREADS_PROFILING FALSE + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +/** + * @brief Trust zone configuration. + * @details If enabled the kernel is configured for the secure world + * and can access specific devices. + */ +#define CH_CFG_SEC_WORLD TRUE + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/testhal/ATSAMA5D2/FLEX-SPI/debug/SAMA5D2-FLEX-SPI (DDRAM).launch b/testhal/ATSAMA5D2/FLEX-SPI/debug/SAMA5D2-FLEX-SPI (DDRAM).launch new file mode 100644 index 000000000..d937e70b0 --- /dev/null +++ b/testhal/ATSAMA5D2/FLEX-SPI/debug/SAMA5D2-FLEX-SPI (DDRAM).launch @@ -0,0 +1,55 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/ATSAMA5D2/FLEX-SPI/debug/SAMA5D2-FLEX-SPI (Load and Run).launch b/testhal/ATSAMA5D2/FLEX-SPI/debug/SAMA5D2-FLEX-SPI (Load and Run).launch new file mode 100644 index 000000000..19c119c6b --- /dev/null +++ b/testhal/ATSAMA5D2/FLEX-SPI/debug/SAMA5D2-FLEX-SPI (Load and Run).launch @@ -0,0 +1,58 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/ATSAMA5D2/FLEX-SPI/debug/SAMA5D2-FLEX-SPI (bootstrap).launch b/testhal/ATSAMA5D2/FLEX-SPI/debug/SAMA5D2-FLEX-SPI (bootstrap).launch new file mode 100644 index 000000000..e218b45a0 --- /dev/null +++ b/testhal/ATSAMA5D2/FLEX-SPI/debug/SAMA5D2-FLEX-SPI (bootstrap).launch @@ -0,0 +1,55 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/testhal/ATSAMA5D2/FLEX-SPI/halconf.h b/testhal/ATSAMA5D2/FLEX-SPI/halconf.h new file mode 100644 index 000000000..6aedf8042 --- /dev/null +++ b/testhal/ATSAMA5D2/FLEX-SPI/halconf.h @@ -0,0 +1,408 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the EXT subsystem. + */ +#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__) +#define HAL_USE_EXT FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the QSPI subsystem. + */ +#if !defined(HAL_USE_QSPI) || defined(__DOXYGEN__) +#define HAL_USE_QSPI FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL FALSE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI TRUE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/testhal/ATSAMA5D2/FLEX-SPI/main.c b/testhal/ATSAMA5D2/FLEX-SPI/main.c new file mode 100644 index 000000000..7a2fbc2bf --- /dev/null +++ b/testhal/ATSAMA5D2/FLEX-SPI/main.c @@ -0,0 +1,125 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" + +#define BUFFER_SIZE 512 + +static uint8_t txbuf[BUFFER_SIZE]; +static uint8_t rxbuf[BUFFER_SIZE]; + +/* + * SPI high speed configuration (83MHz (MCK/3/2), CPHA=0, CPOL=0, MSb first). + */ +static const SPIConfig hs_spicfg = { + NULL, /* callback if present */ + 0, /* cs pad number */ + SPI_MR_MODFDIS | SPI_MR_LLB, /* mr register */ + SPI_CSR_SCBR(1) /* csr */ +}; + +/* + * SPI low speed configuration (83MHz / 166 = 500KHz, CPHA=0, CPOL=0, MSb first). + */ +static const SPIConfig ls_spicfg = { + NULL, /* callback if present */ + 0, /* cs pad number */ + SPI_MR_MODFDIS | SPI_MR_LLB, /* mr register */ + SPI_CSR_SCBR(166) /* csr */ +}; + +/* + * SPI bus contender 1. + */ +static THD_WORKING_AREA(spi_thread_1_wa, 256); +static THD_FUNCTION(spi_thread_1, p) { + + (void)p; + + chRegSetThreadName("SPI thread 1"); + while (true) { + spiAcquireBus(&FSPID2); /* Acquire ownership of the bus. */ + palClearLine(LINE_LED_RED); /* LED ON. */ + spiStart(&FSPID2, &hs_spicfg); /* Setup transfer parameters. */ + spiSelect(&FSPID2); + spiExchange(&FSPID2, BUFFER_SIZE, + txbuf, rxbuf); /* Atomic transfer operations. */ + cacheInvalidateRegion(&rxbuf, sizeof(rxbuf)); + spiUnselect(&FSPID2); + spiReleaseBus(&FSPID2); /* Ownership release. */ + } +} + +/* + * SPI bus contender 2. + */ +static THD_WORKING_AREA(spi_thread_2_wa, 256); +static THD_FUNCTION(spi_thread_2, p) { + + (void)p; + + chRegSetThreadName("SPI thread 2"); + while (true) { + spiAcquireBus(&FSPID2); /* Acquire ownership of the bus. */ + palSetLine(LINE_LED_RED); /* LED OFF. */ + spiStart(&FSPID2, &ls_spicfg); /* Setup transfer parameters. */ + spiSelect(&FSPID2); + spiExchange(&FSPID2, 512, + txbuf, rxbuf); /* Atomic transfer operations. */ + cacheInvalidateRegion(&rxbuf, sizeof(rxbuf)); + spiUnselect(&FSPID2); + spiReleaseBus(&FSPID2); /* Ownership release. */ + } +} + +/* + * Application entry point. + */ +int main(void) { + unsigned i; + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* Redirecting FLEXCOM 2 SPI pins. */ + palSetGroupMode(PIOD, PAL_PORT_BIT(26) | PAL_PORT_BIT(27) | + PAL_PORT_BIT(28) | PAL_PORT_BIT(29) , 0U, + PAL_SAMA_FUNC_PERIPH_C | PAL_MODE_SECURE); + + /* + * Prepare transmit pattern. + */ + for (i = 0; i < sizeof(txbuf); i++) + txbuf[i] = (uint8_t)i; + + chThdCreateStatic(spi_thread_1_wa, sizeof(spi_thread_1_wa), + NORMALPRIO + 1, spi_thread_1, NULL); + chThdCreateStatic(spi_thread_2_wa, sizeof(spi_thread_2_wa), + NORMALPRIO + 1, spi_thread_2, NULL); + + while (true) { + chThdSleepMilliseconds(500); + } + return 0; +} diff --git a/testhal/ATSAMA5D2/FLEX-SPI/mcuconf.h b/testhal/ATSAMA5D2/FLEX-SPI/mcuconf.h new file mode 100644 index 000000000..576041ebb --- /dev/null +++ b/testhal/ATSAMA5D2/FLEX-SPI/mcuconf.h @@ -0,0 +1,143 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +#define SAMA5D2x_MCUCONF + +/* + * HAL driver system settings. + */ +#define SAMA_HAL_IS_SECURE TRUE +#define SAMA_NO_INIT TRUE +#define SAMA_MOSCRC_ENABLED FALSE +#define SAMA_MOSCXT_ENABLED TRUE +#define SAMA_MOSC_SEL SAMA_MOSC_MOSCXT +#define SAMA_OSC_SEL SAMA_OSC_OSCXT +#define SAMA_MCK_SEL SAMA_MCK_PLLA_CLK +#define SAMA_MCK_PRES_VALUE 1 +#define SAMA_MCK_MDIV_VALUE 3 +#define SAMA_PLLA_MUL_VALUE 83 +#define SAMA_PLLADIV2_EN TRUE +#define SAMA_H64MX_H32MX_RATIO 2 + +/* + * SDMMC driver system settings. + */ +#define HAL_USE_SDMMC FALSE + +/* + * SECUMOD driver system settings. + */ +#define HAL_USE_SECUMOD FALSE + +/* + * SERIAL driver system settings. + */ +#define SAMA_SERIAL_USE_UART0 FALSE +#define SAMA_SERIAL_USE_UART1 FALSE +#define SAMA_SERIAL_USE_UART2 FALSE +#define SAMA_SERIAL_USE_UART3 FALSE +#define SAMA_SERIAL_USE_UART4 FALSE +#define SAMA_SERIAL_USE_FLEXCOM0 FALSE +#define SAMA_SERIAL_USE_FLEXCOM1 FALSE +#define SAMA_SERIAL_USE_FLEXCOM2 FALSE +#define SAMA_SERIAL_USE_FLEXCOM3 FALSE +#define SAMA_SERIAL_USE_FLEXCOM4 FALSE +#define SAMA_SERIAL_UART0_IRQ_PRIORITY 4 +#define SAMA_SERIAL_UART1_IRQ_PRIORITY 4 +#define SAMA_SERIAL_UART2_IRQ_PRIORITY 4 +#define SAMA_SERIAL_UART3_IRQ_PRIORITY 4 +#define SAMA_SERIAL_UART4_IRQ_PRIORITY 4 +#define SAMA_SERIAL_FLEXCOM0_IRQ_PRIORITY 4 +#define SAMA_SERIAL_FLEXCOM1_IRQ_PRIORITY 4 +#define SAMA_SERIAL_FLEXCOM2_IRQ_PRIORITY 4 +#define SAMA_SERIAL_FLEXCOM3_IRQ_PRIORITY 4 +#define SAMA_SERIAL_FLEXCOM4_IRQ_PRIORITY 4 + +/* + * SPI driver system settings. + */ +#define SAMA_SPI_USE_SPI0 FALSE +#define SAMA_SPI_USE_SPI1 FALSE +#define SAMA_SPI_USE_FLEXCOM0 FALSE +#define SAMA_SPI_USE_FLEXCOM1 FALSE +#define SAMA_SPI_USE_FLEXCOM2 TRUE +#define SAMA_SPI_USE_FLEXCOM3 FALSE +#define SAMA_SPI_USE_FLEXCOM4 FALSE +#define SAMA_SPI_SPI0_DMA_IRQ_PRIORITY 4 +#define SAMA_SPI_SPI1_DMA_IRQ_PRIORITY 4 +#define SAMA_SPI_FLEXCOM0_DMA_IRQ_PRIORITY 4 +#define SAMA_SPI_FLEXCOM1_DMA_IRQ_PRIORITY 4 +#define SAMA_SPI_FLEXCOM2_DMA_IRQ_PRIORITY 4 +#define SAMA_SPI_FLEXCOM3_DMA_IRQ_PRIORITY 4 +#define SAMA_SPI_FLEXCOM4_DMA_IRQ_PRIORITY 4 +#define SAMA_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") +#define SPI_SELECT_MODE SPI_SELECT_MODE_NONE + +/* + * ST driver settings. + */ +#define SAMA_ST_USE_PIT FALSE +#define SAMA_ST_USE_TC0 FALSE +#define SAMA_ST_USE_TC1 TRUE + +/* + * TC driver system settings. + */ +#define HAL_USE_TC FALSE +#define SAMA_USE_TC0 FALSE +#define SAMA_USE_TC1 FALSE +#define SAMA_TC0_IRQ_PRIORITY 2 +#define SAMA_TC1_IRQ_PRIORITY 2 + +/* + * UART driver system settings. + */ +#define SAMA_UART_USE_UART0 FALSE +#define SAMA_UART_USE_UART1 FALSE +#define SAMA_UART_USE_UART2 FALSE +#define SAMA_UART_USE_UART3 FALSE +#define SAMA_UART_USE_UART4 FALSE +#define SAMA_UART_USE_FLEXCOM0 FALSE +#define SAMA_UART_USE_FLEXCOM1 FALSE +#define SAMA_UART_USE_FLEXCOM2 FALSE +#define SAMA_UART_USE_FLEXCOM3 FALSE +#define SAMA_UART_USE_FLEXCOM4 FALSE +#define SAMA_UART_UART0_IRQ_PRIORITY 4 +#define SAMA_UART_UART1_IRQ_PRIORITY 4 +#define SAMA_UART_UART2_IRQ_PRIORITY 4 +#define SAMA_UART_UART3_IRQ_PRIORITY 4 +#define SAMA_UART_UART4_IRQ_PRIORITY 4 +#define SAMA_UART_FLEXCOM0_IRQ_PRIORITY 4 +#define SAMA_UART_FLEXCOM1_IRQ_PRIORITY 4 +#define SAMA_UART_FLEXCOM2_IRQ_PRIORITY 4 +#define SAMA_UART_FLEXCOM3_IRQ_PRIORITY 4 +#define SAMA_UART_FLEXCOM4_IRQ_PRIORITY 4 +#define SAMA_UART_UART0_DMA_IRQ_PRIORITY 4 +#define SAMA_UART_UART1_DMA_IRQ_PRIORITY 4 +#define SAMA_UART_UART2_DMA_IRQ_PRIORITY 4 +#define SAMA_UART_UART3_DMA_IRQ_PRIORITY 4 +#define SAMA_UART_UART4_DMA_IRQ_PRIORITY 4 +#define SAMA_UART_FLEXCOM0_DMA_IRQ_PRIORITY 4 +#define SAMA_UART_FLEXCOM1_DMA_IRQ_PRIORITY 4 +#define SAMA_UART_FLEXCOM2_DMA_IRQ_PRIORITY 4 +#define SAMA_UART_FLEXCOM3_DMA_IRQ_PRIORITY 4 +#define SAMA_UART_FLEXCOM4_DMA_IRQ_PRIORITY 4 +#define SAMA_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +#endif /* MCUCONF_H */ diff --git a/testhal/ATSAMA5D2/FLEX-SPI/readme.txt b/testhal/ATSAMA5D2/FLEX-SPI/readme.txt new file mode 100644 index 000000000..cc6e568f6 --- /dev/null +++ b/testhal/ATSAMA5D2/FLEX-SPI/readme.txt @@ -0,0 +1,13 @@ +***************************************************************************** +** ChibiOS/RT port for ARM-A5. ** +***************************************************************************** + +** TARGET ** + +The demo targets a generic ARM Cortex-A5 device without HAL support. + +** The Demo ** + +** Build Procedure ** + +** Notes ** -- cgit v1.2.3