diff options
Diffstat (limited to 'os')
4 files changed, 161 insertions, 180 deletions
diff --git a/os/hal/include/hal_wspi.h b/os/hal/include/hal_wspi.h index c54c9ca2a..c3f2ac248 100644 --- a/os/hal/include/hal_wspi.h +++ b/os/hal/include/hal_wspi.h @@ -200,6 +200,11 @@ typedef struct { #define WSPI_CFG_DQS_ENABLE (1LU << 29LU)
#define WSPI_CFG_SIOO (1LU << 31LU)
+
+#define WSPI_CFG_ALL_DTR (WSPI_CFG_CMD_DTR | \
+ WSPI_CFG_ADDR_DTR | \
+ WSPI_CFG_ALT_DTR | \
+ WSPI_CFG_DATA_DTR)
/** @} */
#endif /* WSPI_USE_DEFAULT_CFG_MASKS == TRUE */
diff --git a/os/hal/lib/complex/serial_nor/devices/macronix_mx25/hal_flash_device.c b/os/hal/lib/complex/serial_nor/devices/macronix_mx25/hal_flash_device.c index 81a15f869..176a7d524 100644 --- a/os/hal/lib/complex/serial_nor/devices/macronix_mx25/hal_flash_device.c +++ b/os/hal/lib/complex/serial_nor/devices/macronix_mx25/hal_flash_device.c @@ -69,38 +69,19 @@ const wspi_command_t snor_memmap_read = { #if MX25_BUS_MODE == MX25_BUS_MODE_SPI
.cmd = MX25_CMD_SPI_FAST_READ4B,
.dummy = 8, /* Note, always 8 for this command. */
- .cfg = WSPI_CFG_CMD_MODE_ONE_LINE |
- WSPI_CFG_ADDR_MODE_ONE_LINE |
- WSPI_CFG_ALT_MODE_NONE |
- WSPI_CFG_DATA_MODE_ONE_LINE |
- WSPI_CFG_CMD_SIZE_8 |
- WSPI_CFG_ADDR_SIZE_32
+ .cfg = MX25_CFG_C8_A32_DATA_SPI
#elif MX25_BUS_MODE == MX25_BUS_MODE_OPI_STR
.cmd = MX25_CMD_OPI_8READ,
.dummy = MX25_READ_DUMMY_CYCLES,
- .cfg = WSPI_CFG_CMD_MODE_EIGHT_LINES |
- WSPI_CFG_ADDR_MODE_EIGHT_LINES |
- WSPI_CFG_ALT_MODE_NONE |
- WSPI_CFG_DATA_MODE_EIGHT_LINES |
- WSPI_CFG_CMD_SIZE_16 |
- WSPI_CFG_ADDR_SIZE_32
+ .cfg = MX25_CFG_C16_A32_DATA_8STR
#elif MX25_BUS_MODE == MX25_BUS_MODE_OPI_DTR
.cmd = MX25_CMD_OPI_8DTRD,
.dummy = MX25_READ_DUMMY_CYCLES,
- .cfg = WSPI_CFG_CMD_MODE_EIGHT_LINES |
- WSPI_CFG_ADDR_MODE_EIGHT_LINES |
- WSPI_CFG_ALT_MODE_NONE |
- WSPI_CFG_DATA_MODE_EIGHT_LINES |
- WSPI_CFG_CMD_SIZE_16 |
- WSPI_CFG_ADDR_SIZE_32 |
- WSPI_CFG_CMD_DTR |
- WSPI_CFG_ADDR_DTR |
- WSPI_CFG_DATA_DTR |
- WSPI_CFG_DQS_ENABLE
+ .cfg = MX25_CFG_C16_A32_DATA_8DTR
#endif
};
-#endif
-#endif
+#endif /* WSPI_SUPPORTS_MEMMAP == TRUE */
+#endif /* SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI */
/*===========================================================================*/
/* Driver local variables and types. */
@@ -112,34 +93,20 @@ static const wspi_command_t mx25_cmd_read_id = { #if MX25_SWITCH_WIDTH == TRUE
.cmd = MX25_CMD_SPI_RDID,
- .cfg = WSPI_CFG_CMD_MODE_ONE_LINE |
- WSPI_CFG_DATA_MODE_ONE_LINE |
- WSPI_CFG_CMD_SIZE_8,
+ .cfg = MX25_CFG_C8_DATA_SPI,
.dummy = 0,
#else
#if MX25_BUS_MODE == MX25_BUS_MODE_SPI
.cmd = MX25_CMD_SPI_RDID,
- .cfg = WSPI_CFG_CMD_MODE_ONE_LINE |
- WSPI_CFG_DATA_MODE_ONE_LINE |
- WSPI_CFG_CMD_SIZE_8,
+ .cfg = MX25_CFG_C8_DATA_SPI,
.dummy = 0,
#elif MX25_BUS_MODE == MX25_BUS_MODE_OPI_STR
.cmd = MX25_CMD_OPI_RDID,
- .cfg = WSPI_CFG_CMD_MODE_EIGHT_LINES |
- WSPI_CFG_ADDR_MODE_EIGHT_LINES |
- WSPI_CFG_DATA_MODE_EIGHT_LINES |
- WSPI_CFG_ADDR_SIZE_32,
- WSPI_CFG_CMD_SIZE_16,
+ .cfg = MX25_CFG_C16_A32_DATA_8STR,
.dummy = 4U, /*Note: always 4 dummies. */
#elif MX25_BUS_MODE == MX25_BUS_MODE_OPI_DTR
.cmd = MX25_CMD_OPI_RDID,
- .cfg = WSPI_CFG_CMD_MODE_EIGHT_LINES |
- WSPI_CFG_ADDR_MODE_EIGHT_LINES |
- WSPI_CFG_DATA_MODE_EIGHT_LINES |
- WSPI_CFG_CMD_SIZE_16 |
- WSPI_CFG_ADDR_SIZE_32 |
- WSPI_CFG_CMD_DTR |
- WSPI_CFG_ADDR_DTR,
+ .cfg = MX25_CFG_C16_A32_DATA_8DTR
.dummy = 4U, /*Note: always 4 dummies. */
#endif
#endif
@@ -210,7 +177,7 @@ static void mx25_reset(SNORDriver *devp) { /* 1x MX25_CMD_SPI_RSTEN command.*/
static const wspi_command_t cmd_reset_enable_1 = {
.cmd = MX25_CMD_SPI_RSTEN,
- .cfg = WSPI_CFG_CMD_MODE_ONE_LINE | WSPI_CFG_CMD_SIZE_8,
+ .cfg = MX25_CFG_C8_SPI,
.addr = 0,
.alt = 0,
.dummy = 0
@@ -219,7 +186,7 @@ static void mx25_reset(SNORDriver *devp) { /* 1x MX25_CMD_SPI_RST command.*/
static const wspi_command_t cmd_reset_memory_1 = {
.cmd = MX25_CMD_SPI_RST,
- .cfg = WSPI_CFG_CMD_MODE_ONE_LINE | WSPI_CFG_CMD_SIZE_8,
+ .cfg = MX25_CFG_C8_SPI,
.addr = 0,
.alt = 0,
.dummy = 0
@@ -233,9 +200,7 @@ static void mx25_reset(SNORDriver *devp) { /* 8xDTR MX25_CMD_OPI_RSTEN command.*/
static const wspi_command_t cmd_reset_enable_8dtr = {
.cmd = MX25_CMD_OPI_RSTEN,
- .cfg = WSPI_CFG_CMD_MODE_EIGHT_LINES |
- WSPI_CFG_CMD_SIZE_16 |
- WSPI_CFG_CMD_DTR,
+ .cfg = MX25_CFG_C16_8DTR,
.addr = 0,
.alt = 0,
.dummy = 0
@@ -244,9 +209,7 @@ static void mx25_reset(SNORDriver *devp) { /* 8xDTR MX25_CMD_OPI_RST command.*/
static const wspi_command_t cmd_reset_memory_8dtr = {
.cmd = MX25_CMD_OPI_RST,
- .cfg = WSPI_CFG_CMD_MODE_EIGHT_LINES |
- WSPI_CFG_CMD_SIZE_16 |
- WSPI_CFG_CMD_DTR,
+ .cfg = MX25_CFG_C16_8DTR,
.addr = 0,
.alt = 0,
.dummy = 0
@@ -258,8 +221,7 @@ static void mx25_reset(SNORDriver *devp) { /* 8xSTR MX25_CMD_OPI_RSTEN command.*/
static const wspi_command_t cmd_reset_enable_8str = {
.cmd = MX25_CMD_OPI_RSTEN,
- .cfg = WSPI_CFG_CMD_MODE_EIGHT_LINES |
- WSPI_CFG_CMD_SIZE_16,
+ .cfg = MX25_CFG_C16_8STR,
.addr = 0,
.alt = 0,
.dummy = 0
@@ -268,8 +230,7 @@ static void mx25_reset(SNORDriver *devp) { /* 8xSTR MX25_CMD_OPI_RST command.*/
static const wspi_command_t cmd_reset_memory_8str = {
.cmd = MX25_CMD_OPI_RST,
- .cfg = WSPI_CFG_CMD_MODE_EIGHT_LINES |
- WSPI_CFG_CMD_SIZE_16,
+ .cfg = MX25_CFG_C16_8STR,
.addr = 0,
.alt = 0,
.dummy = 0
@@ -299,22 +260,17 @@ static void mx25_write_cr2(SNORDriver *devp, uint32_t addr, const uint8_t *value static const wspi_command_t cmd_write_enable = {
#if MX25_SWITCH_WIDTH == TRUE
.cmd = MX25_CMD_SPI_WREN,
- .cfg = WSPI_CFG_CMD_MODE_ONE_LINE |
- WSPI_CFG_CMD_SIZE_8,
+ .cfg = MX25_CFG_C8_SPI,
#else
#if MX25_BUS_MODE == MX25_BUS_MODE_SPI
.cmd = MX25_CMD_SPI_WREN,
- .cfg = WSPI_CFG_CMD_MODE_ONE_LINE |
- WSPI_CFG_CMD_SIZE_8,
+ .cfg = MX25_CFG_C8_SPI,
#elif MX25_BUS_MODE == MX25_BUS_MODE_OPI_STR
.cmd = MX25_CMD_OPI_WREN,
- .cfg = WSPI_CFG_CMD_MODE_EIGHT_LINES |
- WSPI_CFG_CMD_SIZE_16,
+ .cfg = MX25_CFG_C16_8STR,
#elif MX25_BUS_MODE == MX25_BUS_MODE_OPI_DTR
.cmd = MX25_CMD_OPI_WREN,
- .cfg = WSPI_CFG_CMD_MODE_EIGHT_LINES |
- WSPI_CFG_CMD_SIZE_16 |
- WSPI_CFG_CMD_DTR,
+ .cfg = MX25_CFG_C16_8DTR,
#endif
#endif
.addr = 0,
@@ -326,34 +282,17 @@ static void mx25_write_cr2(SNORDriver *devp, uint32_t addr, const uint8_t *value #if MX25_SWITCH_WIDTH == TRUE
.cmd = MX25_CMD_SPI_WRCR2,
- .cfg = WSPI_CFG_CMD_MODE_ONE_LINE |
- WSPI_CFG_ADDR_MODE_ONE_LINE |
- WSPI_CFG_DATA_MODE_ONE_LINE |
- WSPI_CFG_CMD_SIZE_8 |
- WSPI_CFG_ADDR_SIZE_32,
+ .cfg = MX25_CFG_C8_A32_DATA_SPI,
#else
#if MX25_BUS_MODE == MX25_BUS_MODE_SPI
.cmd = MX25_CMD_SPI_WRCR2,
- .cfg = WSPI_CFG_CMD_MODE_ONE_LINE |
- WSPI_CFG_ADDR_MODE_ONE_LINE |
- WSPI_CFG_DATA_MODE_ONE_LINE |
- WSPI_CFG_CMD_SIZE_8 |
- WSPI_CFG_ADDR_SIZE_32,
+ .cfg = MX25_CFG_C8_A32_DATA_SPI,
#elif MX25_BUS_MODE == MX25_BUS_MODE_OPI_STR
.cmd = MX25_CMD_OPI_WRCR2,
- .cfg = WSPI_CFG_CMD_MODE_EIGHT_LINES |
- WSPI_CFG_ADDR_MODE_EIGHT_LINES |
- WSPI_CFG_DATA_MODE_EIGHT_LINES |
- WSPI_CFG_CMD_SIZE_16 |
- WSPI_CFG_ADDR_SIZE_32,
+ .cfg = MX25_CFG_C16_A32_DATA_8STR,
#elif MX25_BUS_MODE == MX25_BUS_MODE_OPI_DTR
.cmd = MX25_CMD_OPI_WRCR2,
- .cfg = WSPI_CFG_CMD_MODE_EIGHT_LINES |
- WSPI_CFG_ADDR_MODE_EIGHT_LINES |
- WSPI_CFG_DATA_MODE_EIGHT_LINES |
- WSPI_CFG_CMD_SIZE_16 |
- WSPI_CFG_ADDR_SIZE_32 |
- WSPI_CFG_CMD_DTR,
+ .cfg = MX25_CFG_C16_A32_DATA_8DTR,
#endif
#endif
.addr = addr,
@@ -391,8 +330,9 @@ void snor_device_init(SNORDriver *devp) { mx25_reset(devp);
/* The device requires at least 10uS to recover after a reset, it could
- need up to 100mS in cause a reset occurred during a chip erase.*/
- osalThreadSleepMicroseconds(40);
+ need up to 100mS in cause a reset occurred during a chip erase, 50uS
+ covers most cases.*/
+ osalThreadSleepMicroseconds(50);
}
#endif
@@ -410,15 +350,11 @@ void snor_device_init(SNORDriver *devp) { devp->device_id[1]),
"invalid memory type id");
-
#if SNOR_BUS_DRIVER == SNOR_BUS_DRIVER_WSPI
/* Setting up the dummy cycles to be used for fast read operations.*/
{
- static const uint8_t regval[1] = {
- ~((MX25_READ_DUMMY_CYCLES - 6U) / 2U) & 7U
- };
-
- mx25_write_cr2(devp, 0x00000300U, regval);
+ static const uint8_t v[1] = {~((MX25_READ_DUMMY_CYCLES - 6U) / 2U) & 7U};
+ mx25_write_cr2(devp, 0x00000300U, v);
}
#endif
@@ -426,15 +362,15 @@ void snor_device_init(SNORDriver *devp) { {
uint8_t id[8];
#if MX25_BUS_MODE == MX25_BUS_MODE_SPI
- static const uint8_t regval[1] = {0x00};
+ static const uint8_t v[1] = {0x00};
#elif MX25_BUS_MODE == MX25_BUS_MODE_OPI_STR
- static const uint8_t regval[1] = {0x01};
+ static const uint8_t v[1] = {0x01};
#elif MX25_BUS_MODE == MX25_BUS_MODE_OPI_DTR
- static const uint8_t regval[1] = {0x02};
+ static const uint8_t v[1] = {0x02};
#endif
/* Setting up final bus width.*/
- mx25_write_cr2(devp, 0x00000000U, regval);
+ mx25_write_cr2(devp, 0x00000000U, v);
/* Reading ID again for confirmation, in DTR mode bytes are read twice,
it needs adjusting.*/
diff --git a/os/hal/lib/complex/serial_nor/devices/macronix_mx25/hal_flash_device.h b/os/hal/lib/complex/serial_nor/devices/macronix_mx25/hal_flash_device.h index f2a7ceb06..448728d59 100644 --- a/os/hal/lib/complex/serial_nor/devices/macronix_mx25/hal_flash_device.h +++ b/os/hal/lib/complex/serial_nor/devices/macronix_mx25/hal_flash_device.h @@ -170,6 +170,95 @@ #define MX25_BUS_MODE_OPI_DTR 2U
/** @} */
+/**
+ * @name MX25-required transfer modes
+ * @{
+ */
+#define MX25_CFG_C8_SPI (WSPI_CFG_CMD_SIZE_8 | \
+ WSPI_CFG_CMD_MODE_ONE_LINE | \
+ WSPI_CFG_ADDR_MODE_NONE | \
+ WSPI_CFG_ALT_MODE_NONE | \
+ WSPI_CFG_DATA_MODE_NONE)
+
+#define MX25_CFG_C16_8STR (WSPI_CFG_CMD_SIZE_16 | \
+ WSPI_CFG_CMD_MODE_EIGHT_LINES | \
+ WSPI_CFG_ADDR_MODE_NONE | \
+ WSPI_CFG_ALT_MODE_NONE | \
+ WSPI_CFG_DATA_MODE_NONE)
+
+#define MX25_CFG_C16_8DTR (WSPI_CFG_CMD_SIZE_16 | \
+ WSPI_CFG_CMD_MODE_EIGHT_LINES | \
+ WSPI_CFG_ADDR_MODE_NONE | \
+ WSPI_CFG_ALT_MODE_NONE | \
+ WSPI_CFG_DATA_MODE_NONE | \
+ WSPI_CFG_ALL_DTR)
+
+#define MX25_CFG_C8_A32_SPI (WSPI_CFG_CMD_SIZE_8 | \
+ WSPI_CFG_CMD_MODE_ONE_LINE | \
+ WSPI_CFG_ADDR_MODE_ONE_LINE | \
+ WSPI_CFG_ADDR_SIZE_32 | \
+ WSPI_CFG_ALT_MODE_NONE | \
+ WSPI_CFG_DATA_MODE_NONE
+
+#define MX25_CFG_C16_A32_8STR (WSPI_CFG_CMD_SIZE_16 | \
+ WSPI_CFG_CMD_MODE_EIGHT_LINES | \
+ WSPI_CFG_ADDR_MODE_EIGHT_LINES | \
+ WSPI_CFG_ADDR_SIZE_32 | \
+ WSPI_CFG_ALT_MODE_NONE | \
+ WSPI_CFG_DATA_MODE_NONE)
+
+#define MX25_CFG_C16_A32_8DTR (WSPI_CFG_CMD_SIZE_16 | \
+ WSPI_CFG_CMD_MODE_EIGHT_LINES | \
+ WSPI_CFG_ADDR_MODE_EIGHT_LINES | \
+ WSPI_CFG_ADDR_SIZE_32 | \
+ WSPI_CFG_ALT_MODE_NONE | \
+ WSPI_CFG_DATA_MODE_NONE | \
+ WSPI_CFG_ALL_DTR)
+
+#define MX25_CFG_C8_DATA_SPI (WSPI_CFG_CMD_SIZE_8 | \
+ WSPI_CFG_CMD_MODE_ONE_LINE | \
+ WSPI_CFG_ADDR_MODE_NONE | \
+ WSPI_CFG_ALT_MODE_NONE | \
+ WSPI_CFG_DATA_MODE_ONE_LINE)
+
+#define MX25_CFG_C16_DATA_8STR (WSPI_CFG_CMD_SIZE_16 | \
+ WSPI_CFG_CMD_MODE_EIGHT_LINES | \
+ WSPI_CFG_ADDR_MODE_NONE | \
+ WSPI_CFG_ALT_MODE_NONE | \
+ WSPI_CFG_DATA_MODE_EIGHT_LINES)
+
+#define MX25_CFG_C16_DATA_8DTR (WSPI_CFG_CMD_SIZE_16 | \
+ WSPI_CFG_CMD_MODE_EIGHT_LINES | \
+ WSPI_CFG_ADDR_MODE_NONE | \
+ WSPI_CFG_ALT_MODE_NONE | \
+ WSPI_CFG_DATA_MODE_EIGHT_LINES | \
+ WSPI_CFG_ALL_DTR | \
+ WSPI_CFG_DQS_ENABLE)
+
+#define MX25_CFG_C8_A32_DATA_SPI (WSPI_CFG_CMD_SIZE_8 | \
+ WSPI_CFG_CMD_MODE_ONE_LINE | \
+ WSPI_CFG_ADDR_MODE_ONE_LINE | \
+ WSPI_CFG_ADDR_SIZE_32 | \
+ WSPI_CFG_ALT_MODE_NONE | \
+ WSPI_CFG_DATA_MODE_ONE_LINE)
+
+#define MX25_CFG_C16_A32_DATA_8STR (WSPI_CFG_CMD_SIZE_16 | \
+ WSPI_CFG_CMD_MODE_EIGHT_LINES | \
+ WSPI_CFG_ADDR_MODE_EIGHT_LINES | \
+ WSPI_CFG_ADDR_SIZE_32 | \
+ WSPI_CFG_ALT_MODE_NONE | \
+ WSPI_CFG_DATA_MODE_EIGHT_LINES)
+
+#define MX25_CFG_C16_A32_DATA_8DTR (WSPI_CFG_CMD_SIZE_16 | \
+ WSPI_CFG_CMD_MODE_EIGHT_LINES | \
+ WSPI_CFG_ADDR_MODE_EIGHT_LINES | \
+ WSPI_CFG_ADDR_SIZE_32 | \
+ WSPI_CFG_ALT_MODE_NONE | \
+ WSPI_CFG_DATA_MODE_EIGHT_LINES | \
+ WSPI_CFG_ALL_DTR | \
+ WSPI_CFG_DQS_ENABLE)
+/** @} */
+
/*===========================================================================*/
/* Driver pre-compile time settings. */
/*===========================================================================*/
@@ -268,104 +357,34 @@ /**
* @brief WSPI settings for command only.
*/
-#define SNOR_WSPI_CFG_CMD (WSPI_CFG_CMD_MODE_EIGHT_LINES | \
- WSPI_CFG_ADDR_MODE_NONE | \
- WSPI_CFG_ALT_MODE_NONE | \
- WSPI_CFG_DATA_MODE_NONE | \
- WSPI_CFG_CMD_SIZE_16 | \
- WSPI_CFG_CMD_DTR)
+#define SNOR_WSPI_CFG_CMD MX25_CFG_C16_8DTR
/**
* @brief WSPI settings for command and address.
*/
-#define SNOR_WSPI_CFG_CMD_ADDR (WSPI_CFG_CMD_MODE_EIGHT_LINES | \
- WSPI_CFG_ADDR_MODE_EIGHT_LINES | \
- WSPI_CFG_ALT_MODE_NONE | \
- WSPI_CFG_DATA_MODE_NONE | \
- WSPI_CFG_CMD_SIZE_16 | \
- WSPI_CFG_ADDR_SIZE_32 | \
- WSPI_CFG_CMD_DTR | \
- WSPI_CFG_ADDR_DTR)
+#define SNOR_WSPI_CFG_CMD_ADDR MX25_CFG_C16_A32_8DTR
/**
* @brief WSPI settings for command and data.
*/
-#define SNOR_WSPI_CFG_CMD_DATA (WSPI_CFG_CMD_MODE_EIGHT_LINES | \
- WSPI_CFG_ADDR_MODE_NONE | \
- WSPI_CFG_ALT_MODE_NONE | \
- WSPI_CFG_DATA_MODE_EIGHT_LINES | \
- WSPI_CFG_CMD_SIZE_16 | \
- WSPI_CFG_CMD_DTR | \
- WSPI_CFG_DATA_DTR | \
- WSPI_CFG_DQS_ENABLE)
+#define SNOR_WSPI_CFG_CMD_DATA MX25_CFG_C16_DATA_8DTR
/**
* @brief WSPI settings for command, address and data.
*/
-#define SNOR_WSPI_CFG_CMD_ADDR_DATA (WSPI_CFG_CMD_MODE_EIGHT_LINES | \
- WSPI_CFG_ADDR_MODE_EIGHT_LINES | \
- WSPI_CFG_ALT_MODE_NONE | \
- WSPI_CFG_DATA_MODE_EIGHT_LINES | \
- WSPI_CFG_CMD_SIZE_16 | \
- WSPI_CFG_ADDR_SIZE_32 | \
- WSPI_CFG_CMD_DTR | \
- WSPI_CFG_ADDR_DTR | \
- WSPI_CFG_DATA_DTR | \
- WSPI_CFG_DQS_ENABLE)
+#define SNOR_WSPI_CFG_CMD_ADDR_DATA MX25_CFG_C16_A32_DATA_8DTR
#elif MX25_BUS_MODE == MX25_BUS_MODE_OPI_STR
-#define SNOR_WSPI_CFG_CMD (WSPI_CFG_CMD_MODE_EIGHT_LINES | \
- WSPI_CFG_ADDR_MODE_NONE | \
- WSPI_CFG_ALT_MODE_NONE | \
- WSPI_CFG_DATA_MODE_NONE | \
- WSPI_CFG_CMD_SIZE_16)
-
-#define SNOR_WSPI_CFG_CMD_ADDR (WSPI_CFG_CMD_MODE_EIGHT_LINES | \
- WSPI_CFG_ADDR_MODE_EIGHT_LINES | \
- WSPI_CFG_ALT_MODE_NONE | \
- WSPI_CFG_DATA_MODE_NONE | \
- WSPI_CFG_CMD_SIZE_16 | \
- WSPI_CFG_ADDR_SIZE_32)
-
-#define SNOR_WSPI_CFG_CMD_DATA (WSPI_CFG_CMD_MODE_EIGHT_LINES | \
- WSPI_CFG_ADDR_MODE_NONE | \
- WSPI_CFG_ALT_MODE_NONE | \
- WSPI_CFG_DATA_MODE_EIGHT_LINES | \
- WSPI_CFG_CMD_SIZE_16)
-
-#define SNOR_WSPI_CFG_CMD_ADDR_DATA (WSPI_CFG_CMD_MODE_EIGHT_LINES | \
- WSPI_CFG_ADDR_MODE_EIGHT_LINES | \
- WSPI_CFG_ALT_MODE_NONE | \
- WSPI_CFG_DATA_MODE_EIGHT_LINES | \
- WSPI_CFG_CMD_SIZE_16 | \
- WSPI_CFG_ADDR_SIZE_32)
+#define SNOR_WSPI_CFG_CMD MX25_CFG_C16_8STR
+#define SNOR_WSPI_CFG_CMD_ADDR MX25_CFG_C16_A32_8STR
+#define SNOR_WSPI_CFG_CMD_DATA MX25_CFG_C16_DATA_8STR
+#define SNOR_WSPI_CFG_CMD_ADDR_DATA MX25_CFG_C16_A32_DATA_8STR
#elif MX25_BUS_MODE == MX25_BUS_MODE_SPI
-#define SNOR_WSPI_CFG_CMD (WSPI_CFG_CMD_MODE_ONE_LINE | \
- WSPI_CFG_ADDR_MODE_NONE | \
- WSPI_CFG_ALT_MODE_NONE | \
- WSPI_CFG_DATA_MODE_NONE | \
- WSPI_CFG_CMD_SIZE_8)
-
-#define SNOR_WSPI_CFG_CMD_ADDR (WSPI_CFG_CMD_MODE_ONE_LINE | \
- WSPI_CFG_ADDR_MODE_ONE_LINE | \
- WSPI_CFG_ALT_MODE_NONE | \
- WSPI_CFG_DATA_MODE_NONE | \
- WSPI_CFG_CMD_SIZE_8 | \
- WSPI_CFG_ADDR_SIZE_32)
-
-#define SNOR_WSPI_CFG_CMD_DATA (WSPI_CFG_CMD_MODE_ONE_LINE | \
- WSPI_CFG_ADDR_MODE_NONE | \
- WSPI_CFG_ALT_MODE_NONE | \
- WSPI_CFG_DATA_MODE_ONE_LINE | \
- WSPI_CFG_CMD_SIZE_8)
-
-#define SNOR_WSPI_CFG_CMD_ADDR_DATA (WSPI_CFG_CMD_MODE_ONE_LINE | \
- WSPI_CFG_ADDR_MODE_ONE_LINE | \
- WSPI_CFG_ALT_MODE_NONE | \
- WSPI_CFG_DATA_MODE_ONE_LINE | \
- WSPI_CFG_CMD_SIZE_8 | \
- WSPI_CFG_ADDR_SIZE_32)
+#define SNOR_WSPI_CFG_CMD MX25_CFG_C8_SPI
+#define SNOR_WSPI_CFG_CMD_ADDR MX25_CFG_C8_A32_SPI
+#define SNOR_WSPI_CFG_CMD_DATA MX25_CFG_C8_DATA_SPI
+#define SNOR_WSPI_CFG_CMD_ADDR_DATA MX25_CFG_C8_A32_DATA_SPI
#else
#error "invalid MX25_BUS_MODE setting"
diff --git a/os/hal/ports/STM32/LLD/OCTOSPIv1/hal_wspi_lld.c b/os/hal/ports/STM32/LLD/OCTOSPIv1/hal_wspi_lld.c index 1b5088dc8..c7fad45f3 100644 --- a/os/hal/ports/STM32/LLD/OCTOSPIv1/hal_wspi_lld.c +++ b/os/hal/ports/STM32/LLD/OCTOSPIv1/hal_wspi_lld.c @@ -58,6 +58,15 @@ WSPIDriver WSPID2; /*===========================================================================*/
/**
+ * @brief Waits for completion of previous operation.
+ */
+static inline void wspi_lld_sync(WSPIDriver *wspip) {
+
+ while ((wspip->ospi->SR & OCTOSPI_SR_BUSY) != 0U) {
+ }
+}
+
+/**
* @brief Shared service routine.
*
* @param[in] wspip pointer to the @p WSPIDriver object
@@ -244,6 +253,9 @@ void wspi_lld_start(WSPIDriver *wspip) { */
void wspi_lld_stop(WSPIDriver *wspip) {
+ /* Waiting for the previous operation to complete, if any.*/
+ wspi_lld_sync(wspip);
+
/* If in ready state then disables the OCTOSPI clock.*/
if (wspip->state == WSPI_READY) {
@@ -273,6 +285,9 @@ void wspi_lld_stop(WSPIDriver *wspip) { */
void wspi_lld_command(WSPIDriver *wspip, const wspi_command_t *cmdp) {
+ /* Waiting for the previous operation to complete, if any.*/
+ wspi_lld_sync(wspip);
+
#if 0 //STM32_USE_STM32_D1_WORKAROUND == TRUE
/* If it is a command without address and alternate phases then the command
is sent as an alternate byte, the command phase is suppressed.*/
@@ -323,6 +338,9 @@ void wspi_lld_send(WSPIDriver *wspip, const wspi_command_t *cmdp, dmaStreamSetTransactionSize(wspip->dma, n);
dmaStreamSetMode(wspip->dma, wspip->dmamode | STM32_DMA_CR_DIR_M2P);
+ /* Waiting for the previous operation to complete, if any.*/
+ wspi_lld_sync(wspip);
+
wspip->ospi->CR &= ~OCTOSPI_CR_FMODE;
wspip->ospi->DLR = n - 1U;
wspip->ospi->TCR = cmdp->dummy;
@@ -363,6 +381,9 @@ void wspi_lld_receive(WSPIDriver *wspip, const wspi_command_t *cmdp, dmaStreamSetTransactionSize(wspip->dma, n);
dmaStreamSetMode(wspip->dma, wspip->dmamode | STM32_DMA_CR_DIR_P2M);
+ /* Waiting for the previous operation to complete, if any.*/
+ wspi_lld_sync(wspip);
+
wspip->ospi->CR = (wspip->ospi->CR & ~OCTOSPI_CR_FMODE) | OCTOSPI_CR_FMODE_0;
wspip->ospi->DLR = n - 1U;
wspip->ospi->TCR = cmdp->dummy;
@@ -393,8 +414,8 @@ void wspi_lld_map_flash(WSPIDriver *wspip, const wspi_command_t *cmdp,
uint8_t **addrp) {
- /* Disabling the DMA request while in memory mapped mode.*/
- wspip->ospi->CR &= ~OCTOSPI_CR_DMAEN;
+ /* Waiting for the previous operation to complete, if any.*/
+ wspi_lld_sync(wspip);
/* Starting memory mapped mode using the passed parameters.*/
wspip->ospi->CR = (wspip->ospi->CR & ~OCTOSPI_CR_FMODE) |
|