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-rw-r--r--os/common/ports/ARMCMx/devices/STM32F0xx/cmparams.h2
-rw-r--r--os/ext/CMSIS/ST/stm32f0xx.h91
-rw-r--r--os/ext/CMSIS/ST/system_stm32f0xx.h4
-rw-r--r--os/hal/boards/ST_STM32F0_DISCOVERY/board.h2
-rw-r--r--os/hal/boards/ST_STM32F0_DISCOVERY/cfg/board.chcfg1
-rw-r--r--os/hal/ports/STM32/GPIOv2/pal_lld.c19
-rw-r--r--os/hal/ports/STM32/GPIOv2/pal_lld.h18
-rw-r--r--os/hal/ports/STM32F0xx/hal_lld.h23
-rw-r--r--os/hal/ports/STM32F0xx/stm32_registry.h255
9 files changed, 370 insertions, 45 deletions
diff --git a/os/common/ports/ARMCMx/devices/STM32F0xx/cmparams.h b/os/common/ports/ARMCMx/devices/STM32F0xx/cmparams.h
index 608c7a159..8def2c0e0 100644
--- a/os/common/ports/ARMCMx/devices/STM32F0xx/cmparams.h
+++ b/os/common/ports/ARMCMx/devices/STM32F0xx/cmparams.h
@@ -66,7 +66,7 @@
/* If the device type is not externally defined, for example from the Makefile,
then a file named board.h is included. This file must contain a device
definition compatible with the vendor include file.*/
-#if !defined(STM32F0XX_LD) && !defined(STM32F0XX_MD)
+#if !defined(STM32F0030) && !defined(STM32F0XX_LD) && !defined(STM32F0XX_MD)
#include "board.h"
#endif
diff --git a/os/ext/CMSIS/ST/stm32f0xx.h b/os/ext/CMSIS/ST/stm32f0xx.h
index 09fb548e9..4f21be891 100644
--- a/os/ext/CMSIS/ST/stm32f0xx.h
+++ b/os/ext/CMSIS/ST/stm32f0xx.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file stm32f0xx.h
* @author MCD Application Team
- * @version V1.1.1
- * @date 31-July-2013
+ * @version V1.2.1
+ * @date 22-November-2013
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
* This file contains all the peripheral register's definitions, bits
* definitions and memory mapping for STM32F0xx devices.
@@ -65,22 +65,26 @@
application
*/
-#if !defined (STM32F0XX_LD) && !defined (STM32F0XX_MD)
- /* #define STM32F0XX_LD*/ /*!< STM32F0xx Low-density devices are STM32F050xx and STM32F060xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes */
- /* #define STM32F0XX_MD*/ /*!< STM32F0xx Medium-density devices are STM32F051xx and STM32F061xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes */
+#if !defined (STM32F0XX_LD) && !defined (STM32F0XX_MD) && !defined (STM32F030)
+ /* #define STM32F0XX_LD */ /*!< STM32F0xx Low-density devices are STM32F050xx and STM32F060xx microcontrollers where the Flash memory ranges between 16 and 32 Kbytes */
+ /* #define STM32F0XX_MD */ /*!< STM32F0xx Medium-density devices are STM32F051xx and STM32F061xx microcontrollers where the Flash memory ranges between 16 and 64 Kbytes */
+ #define STM32F030 /*!< STM32F030 devices are STM32F030xx value line microcontrollers */
#endif
/* Tip: To avoid modifying this file each time you need to switch between these
devices, you can define the device in your toolchain compiler preprocessor.
*/
-#ifdef STM32F0XX_MD
- #ifndef STM32F0XX
- /* Old STM32F0XX definition, maintained for legacy purpose */
- #define STM32F0XX STM32F0XX_MD
- #endif /* STM32F0XX */
-#endif /* STM32F0XX_MD */
+/* Old STM32F0XX definition, maintained for legacy purpose */
+#if defined(STM32F0XX)
+ #define STM32F0XX_MD
+#endif /* STM32F0XX */
+
+/* Old STM32F030X6/X8 definition, maintained for legacy purpose */
+#if defined (STM32F030X8) || defined (STM32F030X6)
+ #define STM32F030
+#endif /* STM32F030X8 or STM32F030X6 */
-#if !defined (STM32F0XX_LD) && !defined (STM32F0XX_MD)
+#if !defined (STM32F0XX_LD) && !defined (STM32F0XX_MD) && !defined (STM32F030)
#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
#endif
@@ -143,10 +147,10 @@
#endif /* LSE_VALUE */
/**
- * @brief STM32F0xx Standard Peripheral Library version number V1.1.1
+ * @brief STM32F0xx Standard Peripheral Library version number V1.2.1
*/
#define __STM32F0XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
-#define __STM32F0XX_STDPERIPH_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
+#define __STM32F0XX_STDPERIPH_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
#define __STM32F0XX_STDPERIPH_VERSION_SUB2 (0x01) /*!< [15:8] sub2 version */
#define __STM32F0XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F0XX_STDPERIPH_VERSION ((__STM32F0XX_STDPERIPH_VERSION_MAIN << 24)\
@@ -180,9 +184,8 @@ typedef enum IRQn
SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
-
-#ifdef STM32F0XX_MD
-/****** STM32F0XX_MD specific Interrupt Numbers *****************************************************/
+#if defined (STM32F0XX_MD)
+/****** STM32F0XX_MD specific Interrupt Numbers ****************************************************/
WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
@@ -191,7 +194,7 @@ typedef enum IRQn
EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
- TS_IRQn = 8, /*!< TS Interrupt */
+ TS_IRQn = 8, /*!< Touch sense controller Interrupt */
DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
@@ -235,7 +238,33 @@ typedef enum IRQn
TIM17_IRQn = 22, /*!< TIM17 Interrupt */
I2C1_IRQn = 23, /*!< I2C1 Interrupt */
SPI1_IRQn = 25, /*!< SPI1 Interrupt */
+ USART1_IRQn = 27 /*!< USART1 Interrupt */
+#elif defined (STM32F030)
+/****** STM32F030 specific Interrupt Numbers ********************************************************/
+ WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
+ RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
+ FLASH_IRQn = 3, /*!< FLASH Interrupt */
+ RCC_IRQn = 4, /*!< RCC Interrupt */
+ EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
+ EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
+ EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
+ DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
+ DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
+ DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
+ ADC1_IRQn = 12, /*!< ADC1 Interrupt */
+ TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
+ TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
+ TIM3_IRQn = 16, /*!< TIM3 Interrupt */
+ TIM14_IRQn = 19, /*!< TIM14 Interrupt */
+ TIM15_IRQn = 20, /*!< TIM15 Interrupt */
+ TIM16_IRQn = 21, /*!< TIM16 Interrupt */
+ TIM17_IRQn = 22, /*!< TIM17 Interrupt */
+ I2C1_IRQn = 23, /*!< I2C1 Interrupt */
+ I2C2_IRQn = 24, /*!< I2C2 Interrupt */
+ SPI1_IRQn = 25, /*!< SPI1 Interrupt */
+ SPI2_IRQn = 26, /*!< SPI2 Interrupt */
USART1_IRQn = 27, /*!< USART1 Interrupt */
+ USART2_IRQn = 28 /*!< USART2 Interrupt */
#endif /* STM32F0XX_MD */
} IRQn_Type;
@@ -2032,17 +2061,17 @@ typedef struct
#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
-#define RCC_CFGR_MCO_PRE ((uint32_t)0x70000000) /*!< MCO prescaler (only for STM32F0XX_LD devices)*/
-#define RCC_CFGR_MCO_PRE_1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 (only for STM32F0XX_LD devices)*/
-#define RCC_CFGR_MCO_PRE_2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 (only for STM32F0XX_LD devices)*/
-#define RCC_CFGR_MCO_PRE_4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 (only for STM32F0XX_LD devices)*/
-#define RCC_CFGR_MCO_PRE_8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 (only for STM32F0XX_LD devices)*/
-#define RCC_CFGR_MCO_PRE_16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 (only for STM32F0XX_LD devices)*/
-#define RCC_CFGR_MCO_PRE_32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 (only for STM32F0XX_LD devices)*/
-#define RCC_CFGR_MCO_PRE_64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 (only for STM32F0XX_LD devices)*/
-#define RCC_CFGR_MCO_PRE_128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 (only for STM32F0XX_LD devices)*/
+#define RCC_CFGR_MCO_PRE ((uint32_t)0x70000000) /*!< MCO prescaler (only for STM32F0XX_LD and STM32FO30X6 devices)*/
+#define RCC_CFGR_MCO_PRE_1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
+#define RCC_CFGR_MCO_PRE_2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
+#define RCC_CFGR_MCO_PRE_4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
+#define RCC_CFGR_MCO_PRE_8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
+#define RCC_CFGR_MCO_PRE_16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
+#define RCC_CFGR_MCO_PRE_32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
+#define RCC_CFGR_MCO_PRE_64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
+#define RCC_CFGR_MCO_PRE_128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 (only for STM32F0XX_LD and STM32FO30X6 devices)*/
-#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO (only for STM32F0XX_LD devices) */
+#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO (only for STM32F0XX_LD and STM32FO30X6 devices) */
/*!<****************** Bit definition for RCC_CIR register ********************/
#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
@@ -2587,9 +2616,9 @@ typedef struct
#define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
#define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
#define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
-#define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7(only for STM32F0XX_LD devices) */
-#define SYSCFG_CFGR1_I2C_FMP_PA9 ((uint32_t)0x00400000) /*!< Enable Fast Mode Plus on PA9 (only for STM32F0XX_LD devices) */
-#define SYSCFG_CFGR1_I2C_FMP_PA10 ((uint32_t)0x00800000) /*!< Enable Fast Mode Plus on PA10(only for STM32F0XX_LD devices) */
+#define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /*!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7(only for STM32F0XX_LD and STM32FO30X6 devices) */
+#define SYSCFG_CFGR1_I2C_FMP_PA9 ((uint32_t)0x00400000) /*!< Enable Fast Mode Plus on PA9 (only for STM32F0XX_LD and STM32FO30X6 devices) */
+#define SYSCFG_CFGR1_I2C_FMP_PA10 ((uint32_t)0x00800000) /*!< Enable Fast Mode Plus on PA10(only for STM32F0XX_LD and STM32FO30X6 devices) */
/***************** Bit definition for SYSCFG_EXTICR1 register ***************/
#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
diff --git a/os/ext/CMSIS/ST/system_stm32f0xx.h b/os/ext/CMSIS/ST/system_stm32f0xx.h
index 060bf6b1b..e9335b9c5 100644
--- a/os/ext/CMSIS/ST/system_stm32f0xx.h
+++ b/os/ext/CMSIS/ST/system_stm32f0xx.h
@@ -2,8 +2,8 @@
******************************************************************************
* @file system_stm32f0xx.h
* @author MCD Application Team
- * @version V1.1.1
- * @date 31-July-2013
+ * @version V1.2.1
+ * @date 22-November-2013
* @brief CMSIS Cortex-M0 Device Peripheral Access Layer System Header File.
******************************************************************************
* @attention
diff --git a/os/hal/boards/ST_STM32F0_DISCOVERY/board.h b/os/hal/boards/ST_STM32F0_DISCOVERY/board.h
index be690cc6a..578aa49b7 100644
--- a/os/hal/boards/ST_STM32F0_DISCOVERY/board.h
+++ b/os/hal/boards/ST_STM32F0_DISCOVERY/board.h
@@ -45,7 +45,7 @@
#define STM32_HSE_BYPASS
/*
- * MCU type as defined in the ST header file stm32f0xx.h.
+ * MCU type as defined in the ST header.
*/
#define STM32F0XX_MD
diff --git a/os/hal/boards/ST_STM32F0_DISCOVERY/cfg/board.chcfg b/os/hal/boards/ST_STM32F0_DISCOVERY/cfg/board.chcfg
index 3773f03d1..ec85130c7 100644
--- a/os/hal/boards/ST_STM32F0_DISCOVERY/cfg/board.chcfg
+++ b/os/hal/boards/ST_STM32F0_DISCOVERY/cfg/board.chcfg
@@ -10,6 +10,7 @@
<board_name>ST STM32F0-Discovery</board_name>
<board_id>ST_STM32F0_DISCOVERY</board_id>
<board_functions></board_functions>
+ <subtype>STM32F0XX_MD</subtype>
<clocks HSEFrequency="0" HSEBypass="true" LSEFrequency="0"
LSEBypass="false" LSEDrive="3 High Drive (default)" />
<ports>
diff --git a/os/hal/ports/STM32/GPIOv2/pal_lld.c b/os/hal/ports/STM32/GPIOv2/pal_lld.c
index 48290ae9c..957e51c61 100644
--- a/os/hal/ports/STM32/GPIOv2/pal_lld.c
+++ b/os/hal/ports/STM32/GPIOv2/pal_lld.c
@@ -35,21 +35,29 @@
RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \
RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOHEN)
#define AHB_LPEN_MASK AHB_EN_MASK
-#elif defined(STM32F0XX_LD) || defined(STM32F0XX_MD)
+
+#elif defined(STM32F030) || defined(STM32F0XX_MD)
#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \
RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \
RCC_AHBENR_GPIOFEN)
+
+#elif defined(STM32F0XX_LD)
+#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \
+ RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIOFEN)
+
#elif defined(STM32F2XX)
#define AHB1_EN_MASK (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | \
RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \
RCC_AHB1ENR_GPIOEEN | RCC_AHB1ENR_GPIOFEN | \
RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | \
RCC_AHB1ENR_GPIOIEN)
+
#define AHB1_LPEN_MASK AHB1_EN_MASK
#elif defined(STM32F30X) || defined(STM32F37X)
#define AHB_EN_MASK (RCC_AHBENR_GPIOAEN | RCC_AHBENR_GPIOBEN | \
RCC_AHBENR_GPIOCEN | RCC_AHBENR_GPIODEN | \
RCC_AHBENR_GPIOEEN | RCC_AHBENR_GPIOFEN)
+
#elif defined(STM32F4XX)
#define AHB1_EN_MASK (RCC_AHB1ENR_GPIOAEN | RCC_AHB1ENR_GPIOBEN | \
RCC_AHB1ENR_GPIOCEN | RCC_AHB1ENR_GPIODEN | \
@@ -57,6 +65,7 @@
RCC_AHB1ENR_GPIOGEN | RCC_AHB1ENR_GPIOHEN | \
RCC_AHB1ENR_GPIOIEN)
#define AHB1_LPEN_MASK AHB1_EN_MASK
+
#else
#error "missing or unsupported platform for GPIOv2 PAL driver"
#endif
@@ -120,10 +129,18 @@ void _pal_lld_init(const PALConfig *config) {
/*
* Initial GPIO setup.
*/
+#if STM32_HAS_GPIOA
initgpio(GPIOA, &config->PAData);
+#endif
+#if STM32_HAS_GPIOB
initgpio(GPIOB, &config->PBData);
+#endif
+#if STM32_HAS_GPIOC
initgpio(GPIOC, &config->PCData);
+#endif
+#if STM32_HAS_GPIOD
initgpio(GPIOD, &config->PDData);
+#endif
#if STM32_HAS_GPIOE
initgpio(GPIOE, &config->PEData);
#endif
diff --git a/os/hal/ports/STM32/GPIOv2/pal_lld.h b/os/hal/ports/STM32/GPIOv2/pal_lld.h
index ae20a4a70..42b9ba02d 100644
--- a/os/hal/ports/STM32/GPIOv2/pal_lld.h
+++ b/os/hal/ports/STM32/GPIOv2/pal_lld.h
@@ -215,31 +215,39 @@ typedef struct {
* or whole ports can be reprogrammed at later time.
*/
typedef struct {
+#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
/** @brief Port A setup data.*/
stm32_gpio_setup_t PAData;
+#endif
+#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
/** @brief Port B setup data.*/
stm32_gpio_setup_t PBData;
+#endif
+#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
/** @brief Port C setup data.*/
stm32_gpio_setup_t PCData;
+#endif
+#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
/** @brief Port D setup data.*/
stm32_gpio_setup_t PDData;
-#if STM32_HAS_GPIOE
+#endif
+#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
/** @brief Port E setup data.*/
stm32_gpio_setup_t PEData;
#endif
-#if STM32_HAS_GPIOF
+#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
/** @brief Port F setup data.*/
stm32_gpio_setup_t PFData;
#endif
-#if STM32_HAS_GPIOG
+#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
/** @brief Port G setup data.*/
stm32_gpio_setup_t PGData;
#endif
-#if STM32_HAS_GPIOH
+#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
/** @brief Port H setup data.*/
stm32_gpio_setup_t PHData;
#endif
-#if STM32_HAS_GPIOI
+#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
/** @brief Port I setup data.*/
stm32_gpio_setup_t PIData;
#endif
diff --git a/os/hal/ports/STM32F0xx/hal_lld.h b/os/hal/ports/STM32F0xx/hal_lld.h
index 99fb5bd28..044b13a37 100644
--- a/os/hal/ports/STM32F0xx/hal_lld.h
+++ b/os/hal/ports/STM32F0xx/hal_lld.h
@@ -26,8 +26,9 @@
* - STM32_HSE_BYPASS (optionally).
* .
* One of the following macros must also be defined:
- * - STM32F0XX_LD for Low Density Entry Level devices.
- * - STM32F0XX_MD for Medium Density Entry Level devices.
+ * - STM32F030 for Value Line devices.
+ * - STM32F0XX_LD for Low Density devices.
+ * - STM32F0XX_MD for Medium Density devices.
* .
*
* @addtogroup HAL
@@ -44,10 +45,24 @@
/*===========================================================================*/
/**
- * @name Platform identification
+ * @name Platform identification macros
* @{
*/
-#define PLATFORM_NAME "STM32F05x Entry Level"
+#if defined(STM32F0XX_MD) || defined(__DOXYGEN__)
+#define PLATFORM_NAME "STM32F051xx/F061xx Entry Level Medium Density devices"
+#define STM32F0XX
+
+#elif defined(STM32F0XX_LD)
+#define PLATFORM_NAME "STM32F050xx/F060xx Entry Level Low Density devices"
+#define STM32F0XX
+
+#elif defined(STM32F030)
+#define PLATFORM_NAME "STM32F050xx/F060xx Entry Level Value Line devices"
+#define STM32F0XX
+
+#else
+#error "STM32F0xx device not specified"
+#endif
/** @} */
/**
diff --git a/os/hal/ports/STM32F0xx/stm32_registry.h b/os/hal/ports/STM32F0xx/stm32_registry.h
index 599e7acfe..4f738859b 100644
--- a/os/hal/ports/STM32F0xx/stm32_registry.h
+++ b/os/hal/ports/STM32F0xx/stm32_registry.h
@@ -33,6 +33,8 @@
* @name STM32F0xx capabilities
* @{
*/
+#if defined(STM32F0XX_MD) || defined(__DOXYGEN__)
+
/* ADC attributes.*/
#define STM32_HAS_ADC1 TRUE
#define STM32_HAS_ADC2 FALSE
@@ -164,6 +166,259 @@
#define STM32_HAS_USB TRUE
#define STM32_HAS_OTG1 FALSE
#define STM32_HAS_OTG2 FALSE
+
+#elif defined(STM32F0XX_LD)
+
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 FALSE
+#define STM32_HAS_CAN2 FALSE
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+#define STM32_HAS_DMA1 TRUE
+#define STM32_HAS_DMA2 FALSE
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_CHANNELS 28
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD FALSE
+#define STM32_HAS_GPIOE FALSE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_I2C2 FALSE
+#define STM32_HAS_I2C3 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS FALSE
+#define STM32_RTC_IS_CALENDAR TRUE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2 FALSE
+#define STM32_HAS_SPI3 FALSE
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 4
+
+#define STM32_HAS_TIM2 TRUE
+#define STM32_TIM2_IS_32BITS TRUE
+#define STM32_TIM2_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM14 TRUE
+#define STM32_TIM14_IS_32BITS FALSE
+#define STM32_TIM14_CHANNELS 1
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 2
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 2
+
+#define STM32_HAS_TIM4 FALSE
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM6 FALSE
+#define STM32_HAS_TIM7 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM15 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_USART2 FALSE
+#define STM32_HAS_USART3 FALSE
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+#else /* STM32F030 */
+
+/* ADC attributes.*/
+#define STM32_HAS_ADC1 TRUE
+#define STM32_HAS_ADC2 FALSE
+#define STM32_HAS_ADC3 FALSE
+#define STM32_HAS_ADC4 FALSE
+
+/* CAN attributes.*/
+#define STM32_HAS_CAN1 FALSE
+#define STM32_HAS_CAN2 FALSE
+
+/* DAC attributes.*/
+#define STM32_HAS_DAC FALSE
+
+/* DMA attributes.*/
+#define STM32_ADVANCED_DMA FALSE
+#define STM32_HAS_DMA1 TRUE
+#define STM32_HAS_DMA2 FALSE
+
+/* ETH attributes.*/
+#define STM32_HAS_ETH FALSE
+
+/* EXTI attributes.*/
+#define STM32_EXTI_NUM_CHANNELS 28
+
+/* GPIO attributes.*/
+#define STM32_HAS_GPIOA TRUE
+#define STM32_HAS_GPIOB TRUE
+#define STM32_HAS_GPIOC TRUE
+#define STM32_HAS_GPIOD TRUE
+#define STM32_HAS_GPIOE FALSE
+#define STM32_HAS_GPIOF TRUE
+#define STM32_HAS_GPIOG FALSE
+#define STM32_HAS_GPIOH FALSE
+#define STM32_HAS_GPIOI FALSE
+
+/* I2C attributes.*/
+#define STM32_HAS_I2C1 TRUE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_I2C2 TRUE
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_I2C3 FALSE
+
+/* RTC attributes.*/
+#define STM32_HAS_RTC TRUE
+#define STM32_RTC_HAS_SUBSECONDS FALSE
+#define STM32_RTC_IS_CALENDAR TRUE
+
+/* SDIO attributes.*/
+#define STM32_HAS_SDIO FALSE
+
+/* SPI attributes.*/
+#define STM32_HAS_SPI1 TRUE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+
+#define STM32_HAS_SPI2 TRUE
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+
+#define STM32_HAS_SPI3 FALSE
+#define STM32_HAS_SPI4 FALSE
+#define STM32_HAS_SPI5 FALSE
+#define STM32_HAS_SPI6 FALSE
+
+/* TIM attributes.*/
+#define STM32_HAS_TIM1 TRUE
+#define STM32_TIM1_IS_32BITS FALSE
+#define STM32_TIM1_CHANNELS 4
+
+#define STM32_HAS_TIM3 TRUE
+#define STM32_TIM3_IS_32BITS FALSE
+#define STM32_TIM3_CHANNELS 4
+
+#define STM32_HAS_TIM6 TRUE
+#define STM32_TIM6_IS_32BITS FALSE
+#define STM32_TIM6_CHANNELS 0
+
+#define STM32_HAS_TIM14 TRUE
+#define STM32_TIM14_IS_32BITS FALSE
+#define STM32_TIM14_CHANNELS 1
+
+#define STM32_HAS_TIM15 TRUE
+#define STM32_TIM15_IS_32BITS FALSE
+#define STM32_TIM15_CHANNELS 2
+
+#define STM32_HAS_TIM16 TRUE
+#define STM32_TIM16_IS_32BITS FALSE
+#define STM32_TIM16_CHANNELS 2
+
+#define STM32_HAS_TIM17 TRUE
+#define STM32_TIM17_IS_32BITS FALSE
+#define STM32_TIM17_CHANNELS 2
+
+#define STM32_HAS_TIM2 FALSE
+#define STM32_HAS_TIM4 FALSE
+#define STM32_HAS_TIM5 FALSE
+#define STM32_HAS_TIM7 FALSE
+#define STM32_HAS_TIM8 FALSE
+#define STM32_HAS_TIM9 FALSE
+#define STM32_HAS_TIM10 FALSE
+#define STM32_HAS_TIM11 FALSE
+#define STM32_HAS_TIM12 FALSE
+#define STM32_HAS_TIM13 FALSE
+#define STM32_HAS_TIM18 FALSE
+#define STM32_HAS_TIM19 FALSE
+
+/* USART attributes.*/
+#define STM32_HAS_USART1 TRUE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+
+#define STM32_HAS_USART2 TRUE
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+
+#define STM32_HAS_USART3 FALSE
+#define STM32_HAS_UART4 FALSE
+#define STM32_HAS_UART5 FALSE
+#define STM32_HAS_USART6 FALSE
+
+/* USB attributes.*/
+#define STM32_HAS_USB FALSE
+#define STM32_HAS_OTG1 FALSE
+#define STM32_HAS_OTG2 FALSE
+
+#endif /* STM32F030 */
+
/** @} */
#endif /* _STM32_REGISTRY_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-22 19:16:40 +0000