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-rw-r--r--os/ext/CMSIS/ST/stm32f10x.h3
-rw-r--r--os/hal/ports/STM32/STM32F37x/hal_lld.h12
2 files changed, 9 insertions, 6 deletions
diff --git a/os/ext/CMSIS/ST/stm32f10x.h b/os/ext/CMSIS/ST/stm32f10x.h
index 8ca3fe29b..98de429b5 100644
--- a/os/ext/CMSIS/ST/stm32f10x.h
+++ b/os/ext/CMSIS/ST/stm32f10x.h
@@ -152,6 +152,9 @@
/**
* @brief Configuration of the Cortex-M3 Processor and Core Peripherals
*/
+/* CHIBIOS FIX */
+#define __CM3_REV 0x0201 /*!< Core revision r2p1, not sure it is right */
+/* END CHIBIOS FIX */
#ifdef STM32F10X_XL
#define __MPU_PRESENT 1 /*!< STM32 XL-density devices provide an MPU */
#else
diff --git a/os/hal/ports/STM32/STM32F37x/hal_lld.h b/os/hal/ports/STM32/STM32F37x/hal_lld.h
index 899e056e1..766b116e1 100644
--- a/os/hal/ports/STM32/STM32F37x/hal_lld.h
+++ b/os/hal/ports/STM32/STM32F37x/hal_lld.h
@@ -891,9 +891,9 @@
#define STM32_USART1CLK STM32_PCLK2
#elif STM32_USART1SW == STM32_USART1SW_SYSCLK
#define STM32_USART1CLK STM32_SYSCLK
-#elif STM32_USART1SW == STM32_USART1SW_LSECLK
+#elif STM32_USART1SW == STM32_USART1SW_LSE
#define STM32_USART1CLK STM32_LSECLK
-#elif STM32_USART1SW == STM32_USART1SW_HSICLK
+#elif STM32_USART1SW == STM32_USART1SW_HSI
#define STM32_USART1CLK STM32_HSICLK
#else
#error "invalid source selected for USART1 clock"
@@ -906,9 +906,9 @@
#define STM32_USART2CLK STM32_PCLK1
#elif STM32_USART2SW == STM32_USART2SW_SYSCLK
#define STM32_USART2CLK STM32_SYSCLK
-#elif STM32_USART2SW == STM32_USART2SW_LSECLK
+#elif STM32_USART2SW == STM32_USART2SW_LSE
#define STM32_USART2CLK STM32_LSECLK
-#elif STM32_USART2SW == STM32_USART2SW_HSICLK
+#elif STM32_USART2SW == STM32_USART2SW_HSI
#define STM32_USART2CLK STM32_HSICLK
#else
#error "invalid source selected for USART2 clock"
@@ -921,9 +921,9 @@
#define STM32_USART3CLK STM32_PCLK1
#elif STM32_USART3SW == STM32_USART3SW_SYSCLK
#define STM32_USART3CLK STM32_SYSCLK
-#elif STM32_USART3SW == STM32_USART3SW_LSECLK
+#elif STM32_USART3SW == STM32_USART3SW_LSE
#define STM32_USART3CLK STM32_LSECLK
-#elif STM32_USART3SW == STM32_USART3SW_HSICLK
+#elif STM32_USART3SW == STM32_USART3SW_HSI
#define STM32_USART3CLK STM32_HSICLK
#else
#error "invalid source selected for USART3 clock"