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-rw-r--r--os/ports/GCC/ARMCMx/chcore_v6m.c56
-rw-r--r--os/ports/GCC/ARMCMx/chcore_v6m.h8
-rw-r--r--os/ports/GCC/ARMCMx/chcore_v7m_test.c20
-rw-r--r--os/ports/GCC/ARMCMx/chcore_v7m_test.h42
4 files changed, 62 insertions, 64 deletions
diff --git a/os/ports/GCC/ARMCMx/chcore_v6m.c b/os/ports/GCC/ARMCMx/chcore_v6m.c
index 8c367daf8..58796eda9 100644
--- a/os/ports/GCC/ARMCMx/chcore_v6m.c
+++ b/os/ports/GCC/ARMCMx/chcore_v6m.c
@@ -64,13 +64,13 @@ __attribute__((naked))
#endif
void _port_switch_from_irq(void) {
/* Note, saves r4 to make space for the PC.*/
- asm volatile ("push {r0, r1, r2, r3, r4} \n\t" \
- "mrs r0, APSR \n\t" \
- "mov r1, r12 \n\t" \
- "push {r0, r1, lr} \n\t" \
- "ldr r0, =_port_saved_pc \n\t" \
- "ldr r0, [r0] \n\t" \
- "add r0, r0, #1 \n\t" \
+ asm volatile ("push {r0, r1, r2, r3, r4} \n\t"
+ "mrs r0, APSR \n\t"
+ "mov r1, r12 \n\t"
+ "push {r0, r1, lr} \n\t"
+ "ldr r0, =_port_saved_pc \n\t"
+ "ldr r0, [r0] \n\t"
+ "add r0, r0, #1 \n\t"
"str r0, [sp, #28]");
chSchDoRescheduleI();
@@ -80,30 +80,30 @@ void _port_switch_from_irq(void) {
possibility that the stack is filled by continuous and saturating
interrupts that would not allow that last words to be pulled out of
the stack.*/
- asm volatile ("pop {r0, r1, r2} \n\t" \
- "mov r12, r1 \n\t" \
- "msr APSR, r0 \n\t" \
- "mov lr, r2 \n\t" \
- "cpsie i \n\t" \
+ asm volatile ("pop {r0, r1, r2} \n\t"
+ "mov r12, r1 \n\t"
+ "msr APSR, r0 \n\t"
+ "mov lr, r2 \n\t"
+ "cpsie i \n\t"
"pop {r0, r1, r2, r3, pc}");
}
-#define PUSH_CONTEXT(sp) { \
- asm volatile ("push {r4, r5, r6, r7, lr} \n\t" \
- "mov r4, r8 \n\t" \
- "mov r5, r9 \n\t" \
- "mov r6, r10 \n\t" \
- "mov r7, r11 \n\t" \
- "push {r4, r5, r6, r7}"); \
+#define PUSH_CONTEXT(sp) { \
+ asm volatile ("push {r4, r5, r6, r7, lr} \n\t" \
+ "mov r4, r8 \n\t" \
+ "mov r5, r9 \n\t" \
+ "mov r6, r10 \n\t" \
+ "mov r7, r11 \n\t" \
+ "push {r4, r5, r6, r7}"); \
}
-#define POP_CONTEXT(sp) { \
- asm volatile ("pop {r4, r5, r6, r7} \n\t" \
- "mov r8, r4 \n\t" \
- "mov r9, r5 \n\t" \
- "mov r10, r6 \n\t" \
- "mov r11, r7 \n\t" \
- "pop {r4, r5, r6, r7, pc}" : : "r" (sp)); \
+#define POP_CONTEXT(sp) { \
+ asm volatile ("pop {r4, r5, r6, r7} \n\t" \
+ "mov r8, r4 \n\t" \
+ "mov r9, r5 \n\t" \
+ "mov r10, r6 \n\t" \
+ "mov r11, r7 \n\t" \
+ "pop {r4, r5, r6, r7, pc}" : : "r" (sp)); \
}
/**
@@ -145,8 +145,8 @@ void port_switch(Thread *ntp, Thread *otp) {
void _port_thread_start(void) {
port_unlock();
- asm volatile ("mov r0, r5 \n\t" \
- "blx r4 \n\t" \
+ asm volatile ("mov r0, r5 \n\t"
+ "blx r4 \n\t"
"bl chThdExit");
}
diff --git a/os/ports/GCC/ARMCMx/chcore_v6m.h b/os/ports/GCC/ARMCMx/chcore_v6m.h
index f031f6272..99e9c3138 100644
--- a/os/ports/GCC/ARMCMx/chcore_v6m.h
+++ b/os/ports/GCC/ARMCMx/chcore_v6m.h
@@ -129,9 +129,9 @@ struct intctx {
* enabled to invoke system APIs.
*/
#define PORT_IRQ_PROLOGUE() { \
- chSysLockFromIsr(); \
+ port_lock_from_isr(); \
_port_irq_nesting++; \
- chSysUnlockFromIsr(); \
+ port_unlock_from_isr(); \
}
/**
@@ -140,7 +140,7 @@ struct intctx {
* enabled to invoke system APIs.
*/
#define PORT_IRQ_EPILOGUE() { \
- chSysLockFromIsr(); \
+ port_lock_from_isr(); \
if ((--_port_irq_nesting == 0) && chSchIsRescRequiredExI()) { \
register struct cmxctx *ctxp; \
\
@@ -149,7 +149,7 @@ struct intctx {
ctxp->pc = _port_switch_from_irq; \
return; \
} \
- chSysUnlockFromIsr(); \
+ port_unlock_from_isr(); \
}
/**
diff --git a/os/ports/GCC/ARMCMx/chcore_v7m_test.c b/os/ports/GCC/ARMCMx/chcore_v7m_test.c
index e5178cf52..4df46f065 100644
--- a/os/ports/GCC/ARMCMx/chcore_v7m_test.c
+++ b/os/ports/GCC/ARMCMx/chcore_v7m_test.c
@@ -63,7 +63,7 @@ CH_IRQ_HANDLER(SysTickVector) {
void SVCallVector(void) {
register struct extctx *ctxp;
- /* Discardig the current exception context and positioning the stack to
+ /* Discarding the current exception context and positioning the stack to
point to the real one.*/
asm volatile ("mrs %0, PSP" : "=r" (ctxp) : );
ctxp++;
@@ -94,9 +94,7 @@ void _port_irq_epilogue(void) {
/**
* @brief Post-IRQ switch code.
- * @details On entry the stack and the registers are restored by the exception
- * return, the PC value is stored in @p _port_saved_pc, the interrupts
- * are disabled.
+ * @details Exception handlers return here for context switching.
*/
#if !defined(__DOXYGEN__)
__attribute__((naked))
@@ -107,13 +105,13 @@ void _port_switch_from_isr(void) {
asm volatile ("svc #0");
}
-#define PUSH_CONTEXT(sp) { \
- asm volatile ("push {r4, r5, r6, r7, r8, r9, r10, r11, lr}"); \
+#define PUSH_CONTEXT(sp) { \
+ asm volatile ("push {r4, r5, r6, r7, r8, r9, r10, r11, lr}"); \
}
-#define POP_CONTEXT(sp) { \
- asm volatile ("pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}" \
- : : "r" (sp)); \
+#define POP_CONTEXT(sp) { \
+ asm volatile ("pop {r4, r5, r6, r7, r8, r9, r10, r11, pc}" \
+ : : "r" (sp)); \
}
/**
@@ -155,8 +153,8 @@ void port_switch(Thread *ntp, Thread *otp) {
void _port_thread_start(void) {
port_unlock();
- asm volatile ("mov r0, r5 \n\t" \
- "blx r4 \n\t" \
+ asm volatile ("mov r0, r5 \n\t"
+ "blx r4 \n\t"
"bl chThdExit");
}
diff --git a/os/ports/GCC/ARMCMx/chcore_v7m_test.h b/os/ports/GCC/ARMCMx/chcore_v7m_test.h
index 45a5d11d1..5323cee73 100644
--- a/os/ports/GCC/ARMCMx/chcore_v7m_test.h
+++ b/os/ports/GCC/ARMCMx/chcore_v7m_test.h
@@ -150,13 +150,13 @@ struct intctx {
* @note In this port this it raises the base priority to kernel level.
*/
#if CH_OPTIMIZE_SPEED
-#define port_lock() { \
- register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \
- asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); \
+#define port_lock() { \
+ register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \
+ asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); \
}
#else
-#define port_lock() { \
- asm volatile ("bl _port_lock" : : : "r3", "lr"); \
+#define port_lock() { \
+ asm volatile ("bl _port_lock" : : : "r3", "lr"); \
}
#endif
@@ -164,16 +164,16 @@ struct intctx {
* @brief Kernel-unlock action.
* @details Usually this function just disables interrupts but may perform
* more actions.
- * @note In this port this it lowers the base priority to kernel level.
+ * @note In this port this it lowers the base priority to user level.
*/
#if CH_OPTIMIZE_SPEED
-#define port_unlock() { \
- register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED; \
- asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); \
+#define port_unlock() { \
+ register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED; \
+ asm volatile ("msr BASEPRI, %0" : : "r" (tmp)); \
}
#else
-#define port_unlock() { \
- asm volatile ("bl _port_unlock" : : : "r3", "lr"); \
+#define port_unlock() { \
+ asm volatile ("bl _port_unlock" : : : "r3", "lr"); \
}
#endif
@@ -208,20 +208,20 @@ struct intctx {
* @note Interrupt sources above kernel level remains enabled.
* @note In this port it raises/lowers the base priority to kernel level.
*/
-#define port_suspend() { \
- register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \
- asm volatile ("msr BASEPRI, %0 \n\t" \
- "cpsie i" : : "r" (tmp)); \
+#define port_suspend() { \
+ register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_KERNEL; \
+ asm volatile ("msr BASEPRI, %0 \n\t" \
+ "cpsie i" : : "r" (tmp)); \
}
/**
* @brief Enables all the interrupt sources.
* @note In this port it lowers the base priority to user level.
*/
-#define port_enable() { \
- register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED; \
- asm volatile ("msr BASEPRI, %0 \n\t" \
- "cpsie i" : : "r" (tmp)); \
+#define port_enable() { \
+ register uint32_t tmp asm ("r3") = CORTEX_BASEPRI_DISABLED; \
+ asm volatile ("msr BASEPRI, %0 \n\t" \
+ "cpsie i" : : "r" (tmp)); \
}
/**
@@ -233,8 +233,8 @@ struct intctx {
* @note Implemented as an inlined @p WFI instruction.
*/
#if CORTEX_ENABLE_WFI_IDLE || defined(__DOXYGEN__)
-#define port_wait_for_interrupt() { \
- asm volatile ("wfi"); \
+#define port_wait_for_interrupt() { \
+ asm volatile ("wfi"); \
}
#else
#define port_wait_for_interrupt()
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 08:24:03 +0000