diff options
Diffstat (limited to 'os/hal')
-rw-r--r-- | os/hal/platforms/Posix/hal_lld.c | 8 | ||||
-rw-r--r-- | os/hal/platforms/STM32/i2c_lld.c | 10 | ||||
-rw-r--r-- | os/hal/platforms/STM32F1xx/platform.dox | 144 | ||||
-rw-r--r-- | os/hal/platforms/STM32F1xx/stm32f10x.h | 8 | ||||
-rw-r--r-- | os/hal/platforms/STM32F2xx/hal_lld.h | 11 | ||||
-rw-r--r-- | os/hal/platforms/STM32L1xx/platform.dox | 254 | ||||
-rw-r--r-- | os/hal/platforms/Win32/hal_lld.c | 8 | ||||
-rw-r--r-- | os/hal/src/i2c.c | 16 |
8 files changed, 360 insertions, 99 deletions
diff --git a/os/hal/platforms/Posix/hal_lld.c b/os/hal/platforms/Posix/hal_lld.c index 1eb0af355..8b59d992b 100644 --- a/os/hal/platforms/Posix/hal_lld.c +++ b/os/hal/platforms/Posix/hal_lld.c @@ -78,8 +78,8 @@ void ChkIntSources(void) { #if HAL_USE_SERIAL
if (sd_lld_interrupt_pending()) {
- if (chSchIsRescRequiredExI())
- chSchDoRescheduleI();
+ if (chSchIsPreemptionRequired())
+ chSchDoReschedule();
return;
}
#endif
@@ -88,8 +88,8 @@ void ChkIntSources(void) { if (timercmp(&tv, &nextcnt, >=)) {
timeradd(&nextcnt, &tick, &nextcnt);
chSysTimerHandlerI();
- if (chSchIsRescRequiredExI())
- chSchDoRescheduleI();
+ if (chSchIsPreemptionRequired())
+ chSchDoReschedule();
}
}
diff --git a/os/hal/platforms/STM32/i2c_lld.c b/os/hal/platforms/STM32/i2c_lld.c index a93e2f0a1..77d4b7829 100644 --- a/os/hal/platforms/STM32/i2c_lld.c +++ b/os/hal/platforms/STM32/i2c_lld.c @@ -514,10 +514,6 @@ void i2c_lld_init(void) { * @param[in] i2cp pointer to the @p I2CDriver object */ void i2c_lld_start(I2CDriver *i2cp) { -#if (!(STM32_I2C_I2C2_USE_POLLING_WAIT) && I2C_SUPPORTS_CALLBACKS) - gptStart(i2cp->timer, i2cp->timer_cfg); -#endif /* !(STM32_I2C_I2C2_USE_POLLING_WAIT) */ - if (i2cp->id_state == I2C_STOP) { /* If in stopped state then enables the I2C clock.*/ #if STM32_I2C_USE_I2C1 if (&I2CD1 == i2cp) { @@ -726,7 +722,7 @@ void i2c_lld_master_transmit(I2CDriver *i2cp, uint16_t slave_addr, #else chDbgAssert(!(i2cp->flags & I2C_FLG_TIMER_ARMED), "i2c_lld_master_transmit(), #1", "time to STOP is out"); if ((i2cp->id_i2c->CR1 & I2C_CR1_STOP) && i2cp->timer != NULL && i2cp->timer_cfg != NULL){ - gptStartOneShot(i2cp->timer, I2C_STOP_GPT_TIMEOUT); + gptStartOneShotI(i2cp->timer, I2C_STOP_GPT_TIMEOUT); i2cp->flags |= I2C_FLG_TIMER_ARMED; return; } @@ -784,7 +780,7 @@ void i2c_lld_master_receive(I2CDriver *i2cp, uint16_t slave_addr, #else chDbgAssert(!(i2cp->flags & I2C_FLG_TIMER_ARMED), "i2c_lld_master_receive(), #1", "time to STOP is out"); if ((i2cp->id_i2c->CR1 & I2C_CR1_STOP) && i2cp->timer != NULL && i2cp->timer_cfg != NULL){ - gptStartOneShot(i2cp->timer, I2C_STOP_GPT_TIMEOUT); + gptStartOneShotI(i2cp->timer, I2C_STOP_GPT_TIMEOUT); i2cp->flags |= I2C_FLG_TIMER_ARMED; return; } @@ -850,7 +846,7 @@ void i2c_lld_master_transceive(I2CDriver *i2cp){ #else chDbgAssert(!(i2cp->flags & I2C_FLG_TIMER_ARMED), "i2c_lld_master_transceive(), #1", "time to START is out"); if ((i2cp->id_i2c->CR1 & I2C_CR1_START) && i2cp->timer != NULL && i2cp->timer_cfg != NULL){ - gptStartOneShot(i2cp->timer, I2C_START_GPT_TIMEOUT); + gptStartOneShotI(i2cp->timer, I2C_START_GPT_TIMEOUT); i2cp->flags |= I2C_FLG_TIMER_ARMED; return; } diff --git a/os/hal/platforms/STM32F1xx/platform.dox b/os/hal/platforms/STM32F1xx/platform.dox index 50ab84f38..83c33a868 100644 --- a/os/hal/platforms/STM32F1xx/platform.dox +++ b/os/hal/platforms/STM32F1xx/platform.dox @@ -19,24 +19,24 @@ */
/**
- * @defgroup STM32_DRIVERS STM32 Drivers
- * @details This section describes all the supported drivers on the STM32
+ * @defgroup STM32F1xx_DRIVERS STM32F1xx Drivers
+ * @details This section describes all the supported drivers on the STM32F1xx
* platform and the implementation details of the single drivers.
*
* @ingroup platforms
*/
/**
- * @defgroup STM32_HAL STM32 Initialization Support
- * @details The STM32 HAL support is responsible for system initialization.
+ * @defgroup STM32F1xx_HAL STM32F1xx Initialization Support
+ * @details The STM32F1xx HAL support is responsible for system initialization.
*
- * @section stm32_hal_1 Supported HW resources
+ * @section stm32f1xx_hal_1 Supported HW resources
* - PLL1.
* - PLL2 (where present).
* - RCC.
* - Flash.
* .
- * @section stm32_hal_2 STM32 HAL driver implementation features
+ * @section stm32f1xx_hal_2 STM32F1xx HAL driver implementation features
* - PLLs startup and stabilization.
* - Clock tree initialization.
* - Clock source selection.
@@ -44,19 +44,19 @@ * - SYSTICK initialization based on current clock and kernel required rate.
* - DMA support initialization.
* .
- * @ingroup STM32_DRIVERS
+ * @ingroup STM32F1xx_DRIVERS
*/
/**
- * @defgroup STM32_ADC STM32 ADC Support
- * @details The STM32 ADC driver supports the ADC peripherals using DMA
+ * @defgroup STM32F1xx_ADC STM32F1xx ADC Support
+ * @details The STM32F1xx ADC driver supports the ADC peripherals using DMA
* channels for maximum performance.
*
- * @section stm32_adc_1 Supported HW resources
+ * @section stm32f1xx_adc_1 Supported HW resources
* - ADC1.
* - DMA1.
* .
- * @section stm32_adc_2 STM32 ADC driver implementation features
+ * @section stm32f1xx_adc_2 STM32F1xx ADC driver implementation features
* - Clock stop for reduced power usage when the driver is in stop state.
* - Streaming conversion using DMA for maximum performance.
* - Programmable ADC interrupt priority level.
@@ -64,85 +64,85 @@ * - Programmable DMA interrupt priority for each DMA channel.
* - Programmable DMA error hook.
* .
- * @ingroup STM32_DRIVERS
+ * @ingroup STM32F1xx_DRIVERS
*/
/**
- * @defgroup STM32_CAN STM32 CAN Support
- * @details The STM32 CAN driver uses the CAN peripherals.
+ * @defgroup STM32F1xx_CAN STM32F1xx CAN Support
+ * @details The STM32F1xx CAN driver uses the CAN peripherals.
*
- * @section stm32_can_1 Supported HW resources
+ * @section stm32f1xx_can_1 Supported HW resources
* - bxCAN1.
* .
- * @section stm32_can_2 STM32 CAN driver implementation features
+ * @section stm32f1xx_can_2 STM32F1xx CAN driver implementation features
* - Clock stop for reduced power usage when the driver is in stop state.
* - Support for bxCAN sleep mode.
* - Programmable bxCAN interrupts priority level.
* .
- * @ingroup STM32_DRIVERS
+ * @ingroup STM32F1xx_DRIVERS
*/
/**
- * @defgroup STM32_DMA STM32 DMA Support
+ * @defgroup STM32F1xx_DMA STM32F1xx DMA Support
* @details This DMA helper driver is used by the other drivers in order to
* access the shared DMA resources in a consistent way.
*
- * @section stm32_dma_1 Supported HW resources
+ * @section stm32f1xx_dma_1 Supported HW resources
* The DMA driver can support any of the following hardware resources:
* - DMA1.
* - DMA2 (where present).
* .
- * @section stm32_dma_2 STM32 DMA driver implementation features
+ * @section stm32f1xx_dma_2 STM32F1xx DMA driver implementation features
* - Automatic DMA clock stop when not in use by other drivers.
* - Exports helper functions/macros to the other drivers that share the
* DMA resource.
* .
- * @ingroup STM32_DRIVERS
+ * @ingroup STM32F1xx_DRIVERS
*/
/**
- * @defgroup STM32_GPT STM32 GPT Support
- * @details The STM32 GPT driver uses the TIMx peripherals.
+ * @defgroup STM32F1xx_GPT STM32F1xx GPT Support
+ * @details The STM32F1xx GPT driver uses the TIMx peripherals.
*
- * @section stm32_gpt_1 Supported HW resources
+ * @section stm32f1xx_gpt_1 Supported HW resources
* - TIM1.
* - TIM2.
* - TIM3.
* - TIM4.
* - TIM5.
* .
- * @section stm32_gpt_2 STM32 GPT driver implementation features
+ * @section stm32f1xx_gpt_2 STM32F1xx GPT driver implementation features
* - Each timer can be independently enabled and programmed. Unused
* peripherals are left in low power mode.
* - Programmable TIMx interrupts priority level.
* .
- * @ingroup STM32_DRIVERS
+ * @ingroup STM32F1xx_DRIVERS
*/
/**
- * @defgroup STM32_ICU STM32 ICU Support
- * @details The STM32 ICU driver uses the TIMx peripherals.
+ * @defgroup STM32F1xx_ICU STM32F1xx ICU Support
+ * @details The STM32F1xx ICU driver uses the TIMx peripherals.
*
- * @section stm32_icu_1 Supported HW resources
+ * @section stm32f1xx_icu_1 Supported HW resources
* - TIM1.
* - TIM2.
* - TIM3.
* - TIM4.
* - TIM5.
* .
- * @section stm32_icu_2 STM32 ICU driver implementation features
+ * @section stm32f1xx_icu_2 STM32F1xx ICU driver implementation features
* - Each timer can be independently enabled and programmed. Unused
* peripherals are left in low power mode.
* - Programmable TIMx interrupts priority level.
* .
- * @ingroup STM32_DRIVERS
+ * @ingroup STM32F1xx_DRIVERS
*/
/**
- * @defgroup STM32_PAL STM32 PAL Support
- * @details The STM32 PAL driver uses the GPIO peripherals.
+ * @defgroup STM32F1xx_PAL STM32F1xx PAL Support
+ * @details The STM32F1xx PAL driver uses the GPIO peripherals.
*
- * @section stm32_pal_1 Supported HW resources
+ * @section stm32f1xx_pal_1 Supported HW resources
* - AFIO.
* - GPIOA.
* - GPIOB.
@@ -152,7 +152,7 @@ * - GPIOF (where present).
* - GPIOG (where present).
* .
- * @section stm32_pal_2 STM32 PAL driver implementation features
+ * @section stm32f1xx_pal_2 STM32F1xx PAL driver implementation features
* The PAL driver implementation fully supports the following hardware
* capabilities:
* - 16 bits wide ports.
@@ -161,8 +161,8 @@ * - Output latched regardless of the pad setting.
* - Direct read of input pads regardless of the pad setting.
* .
- * @section stm32_pal_3 Supported PAL setup modes
- * The STM32 PAL driver supports the following I/O modes:
+ * @section stm32f1xx_pal_3 Supported PAL setup modes
+ * The STM32F1xx PAL driver supports the following I/O modes:
* - @p PAL_MODE_RESET.
* - @p PAL_MODE_UNCONNECTED.
* - @p PAL_MODE_INPUT.
@@ -171,13 +171,13 @@ * - @p PAL_MODE_INPUT_ANALOG.
* - @p PAL_MODE_OUTPUT_PUSHPULL.
* - @p PAL_MODE_OUTPUT_OPENDRAIN.
- * - @p PAL_MODE_STM32_ALTERNATE_PUSHPULL (non standard).
- * - @p PAL_MODE_STM32_ALTERNATE_OPENDRAIN (non standard).
+ * - @p PAL_MODE_STM32F1xx_ALTERNATE_PUSHPULL (non standard).
+ * - @p PAL_MODE_STM32F1xx_ALTERNATE_OPENDRAIN (non standard).
* .
* Any attempt to setup an invalid mode is ignored.
*
- * @section stm32_pal_4 Suboptimal behavior
- * The STM32 GPIO is less than optimal in several areas, the limitations
+ * @section stm32f1xx_pal_4 Suboptimal behavior
+ * The STM32F1xx GPIO is less than optimal in several areas, the limitations
* should be taken in account while using the PAL driver:
* - Pad/port toggling operations are not atomic.
* - Pad/group mode setup is not atomic.
@@ -185,52 +185,52 @@ * resistor can change the resistor setting because the output latch is
* used for resistor selection.
* .
- * @ingroup STM32_DRIVERS
+ * @ingroup STM32F1xx_DRIVERS
*/
/**
- * @defgroup STM32_PWM STM32 PWM Support
- * @details The STM32 PWM driver uses the TIMx peripherals.
+ * @defgroup STM32F1xx_PWM STM32F1xx PWM Support
+ * @details The STM32F1xx PWM driver uses the TIMx peripherals.
*
- * @section stm32_pwm_1 Supported HW resources
+ * @section stm32f1xx_pwm_1 Supported HW resources
* - TIM1.
* - TIM2.
* - TIM3.
* - TIM4.
* - TIM5.
* .
- * @section stm32_pwm_2 STM32 PWM driver implementation features
+ * @section stm32f1xx_pwm_2 STM32F1xx PWM driver implementation features
* - Each timer can be independently enabled and programmed. Unused
* peripherals are left in low power mode.
* - Four independent PWM channels per timer.
* - Programmable TIMx interrupts priority level.
* .
- * @ingroup STM32_DRIVERS
+ * @ingroup STM32F1xx_DRIVERS
*/
/**
- * @defgroup STM32_SDC STM32 SDC Support
- * @details The STM32 SDC driver uses the SDIO peripheral.
+ * @defgroup STM32F1xx_SDC STM32F1xx SDC Support
+ * @details The STM32F1xx SDC driver uses the SDIO peripheral.
*
- * @section stm32_sdc_1 Supported HW resources
+ * @section stm32f1xx_sdc_1 Supported HW resources
* - SDIO.
* - DMA2.
* .
- * @section stm32_sdc_2 STM32 SDC driver implementation features
+ * @section stm32f1xx_sdc_2 STM32F1xx SDC driver implementation features
* - Clock stop for reduced power usage when the driver is in stop state.
* - Programmable interrupt priority.
* - DMA is used for receiving and transmitting.
* - Programmable DMA bus priority for each DMA channel.
* .
- * @ingroup STM32_DRIVERS
+ * @ingroup STM32F1xx_DRIVERS
*/
/**
- * @defgroup STM32_SERIAL STM32 Serial Support
- * @details The STM32 Serial driver uses the USART/UART peripherals in a
+ * @defgroup STM32F1xx_SERIAL STM32F1xx Serial Support
+ * @details The STM32F1xx Serial driver uses the USART/UART peripherals in a
* buffered, interrupt driven, implementation.
*
- * @section stm32_serial_1 Supported HW resources
+ * @section stm32f1xx_serial_1 Supported HW resources
* The serial driver can support any of the following hardware resources:
* - USART1.
* - USART2.
@@ -238,29 +238,29 @@ * - UART4 (where present).
* - UART5 (where present).
* .
- * @section stm32_serial_2 STM32 Serial driver implementation features
+ * @section stm32f1xx_serial_2 STM32F1xx Serial driver implementation features
* - Clock stop for reduced power usage when the driver is in stop state.
* - Each UART/USART can be independently enabled and programmed. Unused
* peripherals are left in low power mode.
* - Fully interrupt driven.
* - Programmable priority levels for each UART/USART.
* .
- * @ingroup STM32_DRIVERS
+ * @ingroup STM32F1xx_DRIVERS
*/
/**
- * @defgroup STM32_SPI STM32 SPI Support
- * @details The SPI driver supports the STM32 SPI peripherals using DMA
+ * @defgroup STM32F1xx_SPI STM32F1xx SPI Support
+ * @details The SPI driver supports the STM32F1xx SPI peripherals using DMA
* channels for maximum performance.
*
- * @section stm32_spi_1 Supported HW resources
+ * @section stm32f1xx_spi_1 Supported HW resources
* - SPI1.
* - SPI2.
* - SPI3 (where present).
* - DMA1.
* - DMA2 (where present).
* .
- * @section stm32_spi_2 STM32 SPI driver implementation features
+ * @section stm32f1xx_spi_2 STM32F1xx SPI driver implementation features
* - Clock stop for reduced power usage when the driver is in stop state.
* - Each SPI can be independently enabled and programmed. Unused
* peripherals are left in low power mode.
@@ -270,15 +270,15 @@ * - Programmable DMA interrupt priority for each DMA channel.
* - Programmable DMA error hook.
* .
- * @ingroup STM32_DRIVERS
+ * @ingroup STM32F1xx_DRIVERS
*/
/**
- * @defgroup STM32_UART STM32 UART Support
- * @details The UART driver supports the STM32 USART peripherals using DMA
+ * @defgroup STM32F1xx_UART STM32F1xx UART Support
+ * @details The UART driver supports the STM32F1xx USART peripherals using DMA
* channels for maximum performance.
*
- * @section stm32_uart_1 Supported HW resources
+ * @section stm32f1xx_uart_1 Supported HW resources
* The UART driver can support any of the following hardware resources:
* - USART1.
* - USART2.
@@ -287,7 +287,7 @@ * - DMA1.
* - DMA2 (where present).
* .
- * @section stm32_uart_2 STM32 UART driver implementation features
+ * @section stm32f1xx_uart_2 STM32F1xx UART driver implementation features
* - Clock stop for reduced power usage when the driver is in stop state.
* - Each UART/USART can be independently enabled and programmed. Unused
* peripherals are left in low power mode.
@@ -297,21 +297,21 @@ * - Programmable DMA interrupt priority for each DMA channel.
* - Programmable DMA error hook.
* .
- * @ingroup STM32_DRIVERS
+ * @ingroup STM32F1xx_DRIVERS
*/
/**
- * @defgroup STM32_USB STM32 USB Support
- * @details The USB driver supports the STM32 USB peripheral.
+ * @defgroup STM32F1xx_USB STM32F1xx USB Support
+ * @details The USB driver supports the STM32F1xx USB peripheral.
*
- * @section stm32_usb_1 Supported HW resources
+ * @section stm32f1xx_usb_1 Supported HW resources
* The USB driver can support any of the following hardware resources:
* - USB.
* .
- * @section stm32_usb_2 STM32 USB driver implementation features
+ * @section stm32f1xx_usb_2 STM32F1xx USB driver implementation features
* - Clock stop for reduced power usage when the driver is in stop state.
* - Programmable interrupt priority levels.
* - Each endpoint programmable in Control, Bulk and Interrupt modes.
* .
- * @ingroup STM32_DRIVERS
+ * @ingroup STM32F1xx_DRIVERS
*/
diff --git a/os/hal/platforms/STM32F1xx/stm32f10x.h b/os/hal/platforms/STM32F1xx/stm32f10x.h index 8773ef453..c7f447d18 100644 --- a/os/hal/platforms/STM32F1xx/stm32f10x.h +++ b/os/hal/platforms/STM32F1xx/stm32f10x.h @@ -15,15 +15,15 @@ * is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The device used in the target application
- * - To use or not the peripheral’s drivers in application code(i.e.
- * code will be based on direct access to peripheral’s registers
+ * - To use or not the peripheral�s drivers in application code(i.e.
+ * code will be based on direct access to peripheral�s registers
* rather than drivers API), this option is controlled by
* "#define USE_STDPERIPH_DRIVER"
* - To change few application-specific parameters such as the HSE
* crystal frequency
* - Data structures and the address mapping for all peripherals
* - Peripheral's registers declarations and bits definition
- * - Macros to access peripheral’s registers hardware
+ * - Macros to access peripheral�s registers hardware
*
******************************************************************************
* @attention
@@ -63,6 +63,8 @@ */
#if !defined (STM32F10X_LD) && !defined (STM32F10X_LD_VL) && !defined (STM32F10X_MD) && !defined (STM32F10X_MD_VL) && !defined (STM32F10X_HD) && !defined (STM32F10X_HD_VL) && !defined (STM32F10X_XL) && !defined (STM32F10X_CL)
+ /* CHIBIOS FIX */
+#include "board.h"
/* #define STM32F10X_LD */ /*!< STM32F10X_LD: STM32 Low density devices */
/* #define STM32F10X_LD_VL */ /*!< STM32F10X_LD_VL: STM32 Low density Value Line devices */
/* #define STM32F10X_MD */ /*!< STM32F10X_MD: STM32 Medium density devices */
diff --git a/os/hal/platforms/STM32F2xx/hal_lld.h b/os/hal/platforms/STM32F2xx/hal_lld.h index 0cdfc69c9..764f58529 100644 --- a/os/hal/platforms/STM32F2xx/hal_lld.h +++ b/os/hal/platforms/STM32F2xx/hal_lld.h @@ -153,6 +153,7 @@ #define STM32_HAS_GPIOF TRUE
#define STM32_HAS_GPIOG TRUE
#define STM32_HAS_GPIOH TRUE
+#define STM32_HAS_GPIOI TRUE
#define STM32_HAS_I2C1 TRUE
#define STM32_HAS_I2C2 TRUE
@@ -277,12 +278,12 @@ #define I2C3_ER_IRQHandler Vector164 /**< I2C3 Error. */
#define OTG_HS_EP1_OUT_IRQHandler Vector168 /**< USB OTG HS End Point 1 Out.*/
#define OTG_HS_EP1_IN_IRQHandler Vector16C /**< USB OTG HS End Point 1 In. */
-#define OTG_HS_WKUP_IRQHandler Vector168 /**< USB OTG HS Wakeup through
+#define OTG_HS_WKUP_IRQHandler Vector170 /**< USB OTG HS Wakeup through
EXTI line. */
-#define OTG_HS_IRQHandler Vector16C /**< USB OTG HS. */
-#define DCMI_IRQHandler Vector16C /**< DCMI. */
-#define CRYP_IRQHandler Vector16C /**< CRYP. */
-#define HASH_RNG_IRQHandler Vector16C /**< Hash and Rng. */
+#define OTG_HS_IRQHandler Vector174 /**< USB OTG HS. */
+#define DCMI_IRQHandler Vector178 /**< DCMI. */
+#define CRYP_IRQHandler Vector17C /**< CRYP. */
+#define HASH_RNG_IRQHandler Vector180 /**< Hash and Rng. */
/*===========================================================================*/
/* Driver pre-compile time settings. */
diff --git a/os/hal/platforms/STM32L1xx/platform.dox b/os/hal/platforms/STM32L1xx/platform.dox new file mode 100644 index 000000000..7abe18e5e --- /dev/null +++ b/os/hal/platforms/STM32L1xx/platform.dox @@ -0,0 +1,254 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @defgroup STM32L1xx_DRIVERS STM32L1xx Drivers
+ * @details This section describes all the supported drivers on the STM32F1xx
+ * platform and the implementation details of the single drivers.
+ *
+ * @ingroup platforms
+ */
+
+/**
+ * @defgroup STM32L1xx_HAL STM32L1xx Initialization Support
+ * @details The STM32L1xx HAL support is responsible for system initialization.
+ *
+ * @section stm32l1xx_hal_1 Supported HW resources
+ * - PLL1.
+ * - RCC.
+ * - Flash.
+ * .
+ * @section stm32l1xx_hal_2 STM32L1xx HAL driver implementation features
+ * - PLL startup and stabilization.
+ * - Clock tree initialization.
+ * - Clock source selection.
+ * - Flash wait states initialization based on the selected clock options.
+ * - SYSTICK initialization based on current clock and kernel required rate.
+ * - DMA support initialization.
+ * .
+ * @ingroup STM32L1xx_DRIVERS
+ */
+
+/**
+ * @defgroup STM32L1xx_DMA STM32L1xx DMA Support
+ * @details This DMA helper driver is used by the other drivers in order to
+ * access the shared DMA resources in a consistent way.
+ *
+ * @section stm32l1xx_dma_1 Supported HW resources
+ * The DMA driver can support any of the following hardware resources:
+ * - DMA1.
+ * .
+ * @section stm32l1xx_dma_2 STM32L1xx DMA driver implementation features
+ * - Automatic DMA clock stop when not in use by other drivers.
+ * - Exports helper functions/macros to the other drivers that share the
+ * DMA resource.
+ * .
+ * @ingroup STM32L1xx_DRIVERS
+ */
+
+/**
+ * @defgroup STM32L1xx_GPT STM32L1xx GPT Support
+ * @details The STM32L1xx GPT driver uses the TIMx peripherals.
+ *
+ * @section stm32l1xx_gpt_1 Supported HW resources
+ * - TIM2.
+ * - TIM3.
+ * - TIM4.
+ * .
+ * @section stm32l1xx_gpt_2 STM32L1xx GPT driver implementation features
+ * - Each timer can be independently enabled and programmed. Unused
+ * peripherals are left in low power mode.
+ * - Programmable TIMx interrupts priority level.
+ * .
+ * @ingroup STM32L1xx_DRIVERS
+ */
+
+/**
+ * @defgroup STM32L1xx_ICU STM32L1xx ICU Support
+ * @details The STM32L1xx ICU driver uses the TIMx peripherals.
+ *
+ * @section stm32l1xx_icu_1 Supported HW resources
+ * - TIM2.
+ * - TIM3.
+ * - TIM4.
+ * .
+ * @section stm32l1xx_icu_2 STM32L1xx ICU driver implementation features
+ * - Each timer can be independently enabled and programmed. Unused
+ * peripherals are left in low power mode.
+ * - Programmable TIMx interrupts priority level.
+ * .
+ * @ingroup STM32L1xx_DRIVERS
+ */
+
+/**
+ * @defgroup STM32L1xx_PAL STM32L1xx PAL Support
+ * @details The STM32L1xx PAL driver uses the GPIO peripherals.
+ *
+ * @section stm32l1xx_pal_1 Supported HW resources
+ * - GPIOA.
+ * - GPIOB.
+ * - GPIOC.
+ * - GPIOD.
+ * - GPIOE.
+ * - GPIOH.
+ * .
+ * @section stm32l1xx_pal_2 STM32L1xx PAL driver implementation features
+ * The PAL driver implementation fully supports the following hardware
+ * capabilities:
+ * - 16 bits wide ports.
+ * - Atomic set/reset functions.
+ * - Atomic set+reset function (atomic bus operations).
+ * - Output latched regardless of the pad setting.
+ * - Direct read of input pads regardless of the pad setting.
+ * .
+ * @section stm32l1xx_pal_3 Supported PAL setup modes
+ * The STM32L1xx PAL driver supports the following I/O modes:
+ * - @p PAL_MODE_RESET.
+ * - @p PAL_MODE_UNCONNECTED.
+ * - @p PAL_MODE_INPUT.
+ * - @p PAL_MODE_INPUT_PULLUP.
+ * - @p PAL_MODE_INPUT_PULLDOWN.
+ * - @p PAL_MODE_INPUT_ANALOG.
+ * - @p PAL_MODE_OUTPUT_PUSHPULL.
+ * - @p PAL_MODE_OUTPUT_OPENDRAIN.
+ * - @p PAL_MODE_STM32L1xx_ALTERNATE_PUSHPULL (non standard).
+ * - @p PAL_MODE_STM32L1xx_ALTERNATE_OPENDRAIN (non standard).
+ * .
+ * Any attempt to setup an invalid mode is ignored.
+ *
+ * @section stm32l1xx_pal_4 Suboptimal behavior
+ * The STM32L1xx GPIO is less than optimal in several areas, the limitations
+ * should be taken in account while using the PAL driver:
+ * - Pad/port toggling operations are not atomic.
+ * - Pad/group mode setup is not atomic.
+ * .
+ * @ingroup STM32L1xx_DRIVERS
+ */
+
+/**
+ * @defgroup STM32L1xx_PWM STM32L1xx PWM Support
+ * @details The STM32L1xx PWM driver uses the TIMx peripherals.
+ *
+ * @section stm32l1xx_pwm_1 Supported HW resources
+ * - TIM1.
+ * - TIM2.
+ * - TIM3.
+ * - TIM4.
+ * - TIM5.
+ * .
+ * @section stm32l1xx_pwm_2 STM32L1xx PWM driver implementation features
+ * - Each timer can be independently enabled and programmed. Unused
+ * peripherals are left in low power mode.
+ * - Four independent PWM channels per timer.
+ * - Programmable TIMx interrupts priority level.
+ * .
+ * @ingroup STM32L1xx_DRIVERS
+ */
+
+/**
+ * @defgroup STM32L1xx_SERIAL STM32L1xx Serial Support
+ * @details The STM32L1xx Serial driver uses the USART/UART peripherals in a
+ * buffered, interrupt driven, implementation.
+ *
+ * @section stm32l1xx_serial_1 Supported HW resources
+ * The serial driver can support any of the following hardware resources:
+ * - USART1.
+ * - USART2.
+ * - USART3 (where present).
+ * - UART4 (where present).
+ * - UART5 (where present).
+ * .
+ * @section stm32l1xx_serial_2 STM32L1xx Serial driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Each UART/USART can be independently enabled and programmed. Unused
+ * peripherals are left in low power mode.
+ * - Fully interrupt driven.
+ * - Programmable priority levels for each UART/USART.
+ * .
+ * @ingroup STM32L1xx_DRIVERS
+ */
+
+/**
+ * @defgroup STM32L1xx_SPI STM32L1xx SPI Support
+ * @details The SPI driver supports the STM32L1xx SPI peripherals using DMA
+ * channels for maximum performance.
+ *
+ * @section stm32l1xx_spi_1 Supported HW resources
+ * - SPI1.
+ * - SPI2.
+ * - SPI3 (where present).
+ * - DMA1.
+ * - DMA2 (where present).
+ * .
+ * @section stm32l1xx_spi_2 STM32L1xx SPI driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Each SPI can be independently enabled and programmed. Unused
+ * peripherals are left in low power mode.
+ * - Programmable interrupt priority levels for each SPI.
+ * - DMA is used for receiving and transmitting.
+ * - Programmable DMA bus priority for each DMA channel.
+ * - Programmable DMA interrupt priority for each DMA channel.
+ * - Programmable DMA error hook.
+ * .
+ * @ingroup STM32L1xx_DRIVERS
+ */
+
+/**
+ * @defgroup STM32L1xx_UART STM32L1xx UART Support
+ * @details The UART driver supports the STM32L1xx USART peripherals using DMA
+ * channels for maximum performance.
+ *
+ * @section stm32l1xx_uart_1 Supported HW resources
+ * The UART driver can support any of the following hardware resources:
+ * - USART1.
+ * - USART2.
+ * - USART3 (where present).
+ * - UART4 (where present).
+ * - DMA1.
+ * - DMA2 (where present).
+ * .
+ * @section stm32l1xx_uart_2 STM32L1xx UART driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Each UART/USART can be independently enabled and programmed. Unused
+ * peripherals are left in low power mode.
+ * - Programmable interrupt priority levels for each UART/USART.
+ * - DMA is used for receiving and transmitting.
+ * - Programmable DMA bus priority for each DMA channel.
+ * - Programmable DMA interrupt priority for each DMA channel.
+ * - Programmable DMA error hook.
+ * .
+ * @ingroup STM32L1xx_DRIVERS
+ */
+
+/**
+ * @defgroup STM32L1xx_USB STM32L1xx USB Support
+ * @details The USB driver supports the STM32L1xx USB peripheral.
+ *
+ * @section stm32l1xx_usb_1 Supported HW resources
+ * The USB driver can support any of the following hardware resources:
+ * - USB.
+ * .
+ * @section stm32l1xx_usb_2 STM32L1xx USB driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Programmable interrupt priority levels.
+ * - Each endpoint programmable in Control, Bulk and Interrupt modes.
+ * .
+ * @ingroup STM32L1xx_DRIVERS
+ */
diff --git a/os/hal/platforms/Win32/hal_lld.c b/os/hal/platforms/Win32/hal_lld.c index 24a11f51c..5906e372c 100644 --- a/os/hal/platforms/Win32/hal_lld.c +++ b/os/hal/platforms/Win32/hal_lld.c @@ -83,8 +83,8 @@ void ChkIntSources(void) { #if HAL_USE_SERIAL
if (sd_lld_interrupt_pending()) {
- if (chSchIsRescRequiredExI())
- chSchDoRescheduleI();
+ if (chSchIsPreemptionRequired())
+ chSchDoReschedule();
return;
}
#endif
@@ -94,8 +94,8 @@ void ChkIntSources(void) { if (n.QuadPart > nextcnt.QuadPart) {
nextcnt.QuadPart += slice.QuadPart;
chSysTimerHandlerI();
- if (chSchIsRescRequiredExI())
- chSchDoRescheduleI();
+ if (chSchIsPreemptionRequired())
+ chSchDoReschedule();
}
}
diff --git a/os/hal/src/i2c.c b/os/hal/src/i2c.c index 9676a3250..974f65a08 100644 --- a/os/hal/src/i2c.c +++ b/os/hal/src/i2c.c @@ -103,11 +103,15 @@ void i2cObjectInit(I2CDriver *i2cp) { void i2cStart(I2CDriver *i2cp, const I2CConfig *config) {
chDbgCheck((i2cp != NULL) && (config != NULL), "i2cStart");
-
- chSysLock();
chDbgAssert((i2cp->id_state == I2C_STOP) || (i2cp->id_state == I2C_READY),
"i2cStart(), #1",
"invalid state");
+
+#if (!(STM32_I2C_I2C2_USE_POLLING_WAIT) && I2C_SUPPORTS_CALLBACKS)
+ gptStart(i2cp->timer, i2cp->timer_cfg);
+#endif /* !(STM32_I2C_I2C2_USE_POLLING_WAIT) */
+
+ chSysLock();
i2cp->id_config = config;
i2c_lld_start(i2cp);
i2cp->id_state = I2C_READY;
@@ -124,11 +128,15 @@ void i2cStart(I2CDriver *i2cp, const I2CConfig *config) { void i2cStop(I2CDriver *i2cp) {
chDbgCheck(i2cp != NULL, "i2cStop");
-
- chSysLock();
chDbgAssert((i2cp->id_state == I2C_STOP) || (i2cp->id_state == I2C_READY),
"i2cStop(), #1",
"invalid state");
+
+#if (!(STM32_I2C_I2C2_USE_POLLING_WAIT) && I2C_SUPPORTS_CALLBACKS)
+ gptStop(i2cp->timer);
+#endif /* !(STM32_I2C_I2C2_USE_POLLING_WAIT) */
+
+ chSysLock();
i2c_lld_stop(i2cp);
i2cp->id_state = I2C_STOP;
chSysUnlock();
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