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-rw-r--r--os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c36
-rw-r--r--os/hal/ports/STM32/STM32F0xx/hal_lld.c6
-rw-r--r--os/hal/ports/STM32/STM32F37x/hal_lld.c6
-rw-r--r--os/hal/ports/STM32/STM32F3xx/hal_lld.c6
-rw-r--r--os/hal/ports/STM32/STM32F4xx/hal_lld.c7
-rw-r--r--os/hal/ports/STM32/STM32F7xx/hal_lld.c2
-rw-r--r--os/hal/ports/STM32/STM32L0xx/hal_lld.c2
-rw-r--r--os/hal/ports/STM32/STM32L0xx/stm32_rcc.h40
-rw-r--r--os/hal/ports/STM32/STM32L1xx/hal_lld.c6
9 files changed, 62 insertions, 49 deletions
diff --git a/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c b/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c
index a1f7af755..85d16a375 100644
--- a/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c
+++ b/os/hal/ports/STM32/LLD/GPIOv2/hal_pal_lld.c
@@ -30,22 +30,6 @@
/* Driver local definitions. */
/*===========================================================================*/
-#if defined(STM32L0XX) || defined(STM32L1XX)
-#define AHB_EN_MASK STM32_GPIO_EN_MASK
-#define AHB_LPEN_MASK AHB_EN_MASK
-
-#elif defined(STM32F0XX) || defined(STM32F3XX) || defined(STM32F37X)
-#define AHB_EN_MASK STM32_GPIO_EN_MASK
-#define AHB_LPEN_MASK 0
-
-#elif defined(STM32F2XX) || defined(STM32F4XX) || defined(STM32F7XX)
-#define AHB1_EN_MASK STM32_GPIO_EN_MASK
-#define AHB1_LPEN_MASK AHB1_EN_MASK
-
-#else
-#error "missing or unsupported platform for GPIOv2 PAL driver"
-#endif
-
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
@@ -85,26 +69,6 @@ void _pal_lld_init(void) {
_pal_init_event(i);
}
#endif
-
-#if 0
- /*
- * Enables the GPIO related clocks.
- */
-#if defined(STM32L0XX)
- RCC->IOPENR |= AHB_EN_MASK;
- RCC->IOPSMENR |= AHB_LPEN_MASK;
-#elif defined(STM32L1XX)
- rccEnableAHB(AHB_EN_MASK, TRUE);
- RCC->AHBLPENR |= AHB_LPEN_MASK;
-#elif defined(STM32F0XX)
- rccEnableAHB(AHB_EN_MASK, TRUE);
-#elif defined(STM32F3XX) || defined(STM32F37X)
- rccEnableAHB(AHB_EN_MASK, TRUE);
-#elif defined(STM32F2XX) || defined(STM32F4XX) || defined(STM32F7XX)
- RCC->AHB1ENR |= AHB1_EN_MASK;
- RCC->AHB1LPENR |= AHB1_LPEN_MASK;
-#endif
-#endif
}
/**
diff --git a/os/hal/ports/STM32/STM32F0xx/hal_lld.c b/os/hal/ports/STM32/STM32F0xx/hal_lld.c
index 664bf8a2c..73ca9552a 100644
--- a/os/hal/ports/STM32/STM32F0xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F0xx/hal_lld.c
@@ -226,8 +226,10 @@ OSAL_IRQ_HANDLER(STM32_DMA12_CH4567_CH345_HANDLER) {
*/
void hal_lld_init(void) {
- /* Reset of all peripherals.*/
- rccResetAHB(0xFFFFFFFF);
+ /* Reset of all peripherals.
+ Note, GPIOs are not reset because initialized before this point in
+ board files.*/
+ rccResetAHB(~STM32_GPIO_EN_MASK);
rccResetAPB1(0xFFFFFFFF);
rccResetAPB2(~RCC_APB2RSTR_DBGMCURST);
diff --git a/os/hal/ports/STM32/STM32F37x/hal_lld.c b/os/hal/ports/STM32/STM32F37x/hal_lld.c
index 51dd71cc7..bc5d27e96 100644
--- a/os/hal/ports/STM32/STM32F37x/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F37x/hal_lld.c
@@ -104,8 +104,10 @@ static void hal_lld_backup_domain_init(void) {
*/
void hal_lld_init(void) {
- /* Reset of all peripherals.*/
- rccResetAHB(0xFFFFFFFF);
+ /* Reset of all peripherals.
+ Note, GPIOs are not reset because initialized before this point in
+ board files.*/
+ rccResetAHB(~STM32_GPIO_EN_MASK);
rccResetAPB1(0xFFFFFFFF);
rccResetAPB2(0xFFFFFFFF);
diff --git a/os/hal/ports/STM32/STM32F3xx/hal_lld.c b/os/hal/ports/STM32/STM32F3xx/hal_lld.c
index 06e80c0fd..33424ae05 100644
--- a/os/hal/ports/STM32/STM32F3xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F3xx/hal_lld.c
@@ -104,8 +104,10 @@ static void hal_lld_backup_domain_init(void) {
*/
void hal_lld_init(void) {
- /* Reset of all peripherals.*/
- rccResetAHB(0xFFFFFFFF);
+ /* Reset of all peripherals.
+ Note, GPIOs are not reset because initialized before this point in
+ board files.*/
+ rccResetAHB(~STM32_GPIO_EN_MASK);
rccResetAPB1(0xFFFFFFFF);
rccResetAPB2(0xFFFFFFFF);
diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.c b/os/hal/ports/STM32/STM32F4xx/hal_lld.c
index eecd50e93..f71160961 100644
--- a/os/hal/ports/STM32/STM32F4xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.c
@@ -114,9 +114,10 @@ static void hal_lld_backup_domain_init(void) {
void hal_lld_init(void) {
/* Reset of all peripherals. AHB3 is not reseted because it could have
- been initialized in the board initialization file (board.c) and AHB2 is not
- present in STM32F410. */
- rccResetAHB1(~0);
+ been initialized in the board initialization file (board.c).
+ Note, GPIOs are not reset because initialized before this point in
+ board files.*/
+ rccResetAHB1(~STM32_GPIO_EN_MASK);
#if !defined(STM32F410xx)
rccResetAHB2(~0);
#endif
diff --git a/os/hal/ports/STM32/STM32F7xx/hal_lld.c b/os/hal/ports/STM32/STM32F7xx/hal_lld.c
index 16595bdc0..87698308f 100644
--- a/os/hal/ports/STM32/STM32F7xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32F7xx/hal_lld.c
@@ -115,7 +115,7 @@ void hal_lld_init(void) {
/* Reset of all peripherals. AHB3 is not reseted because it could have
been initialized in the board initialization file (board.c).
- Note, GPIO are not reset because initialized before this point in
+ Note, GPIOs are not reset because initialized before this point in
board files.*/
rccResetAHB1(~STM32_GPIO_EN_MASK);
rccResetAHB2(~0);
diff --git a/os/hal/ports/STM32/STM32L0xx/hal_lld.c b/os/hal/ports/STM32/STM32L0xx/hal_lld.c
index a0766c9a0..d4d625aad 100644
--- a/os/hal/ports/STM32/STM32L0xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32L0xx/hal_lld.c
@@ -150,7 +150,7 @@ OSAL_IRQ_HANDLER(STM32_DMA1_CH4567_HANDLER) {
*/
void hal_lld_init(void) {
- /* Reset of all peripherals.*/
+ /* Reset of all peripherals except those on IOP.*/
rccResetAHB(~RCC_AHBRSTR_MIFRST);
rccResetAPB1(~RCC_APB1RSTR_PWRRST);
rccResetAPB2(~0);
diff --git a/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h b/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h
index 5396fe1b1..ff76739dd 100644
--- a/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h
+++ b/os/hal/ports/STM32/STM32L0xx/stm32_rcc.h
@@ -170,6 +170,46 @@
RCC->AHBRSTR |= (mask); \
RCC->AHBRSTR = 0; \
}
+
+/**
+ * @brief Enables the clock of one or more peripheral on the IOP bus.
+ *
+ * @param[in] mask IOP peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableIOP(mask, lp) { \
+ RCC->IOPENR |= (mask); \
+ if (lp) \
+ RCC->IOPSMENR |= (mask); \
+}
+
+/**
+ * @brief Disables the clock of one or more peripheral on the IOP bus.
+ *
+ * @param[in] mask IOP peripherals mask
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableIOP(mask, lp) { \
+ RCC->IOPENR &= ~(mask); \
+ if (lp) \
+ RCC->IOPSMENR &= ~(mask); \
+}
+
+/**
+ * @brief Resets one or more peripheral on the IOP bus.
+ *
+ * @param[in] mask IOP peripherals mask
+ *
+ * @api
+ */
+#define rccResetIOP(mask) { \
+ RCC->IOPRSTR |= (mask); \
+ RCC->IOPRSTR = 0; \
+}
/** @} */
/**
diff --git a/os/hal/ports/STM32/STM32L1xx/hal_lld.c b/os/hal/ports/STM32/STM32L1xx/hal_lld.c
index 78559a2b1..3f4c04329 100644
--- a/os/hal/ports/STM32/STM32L1xx/hal_lld.c
+++ b/os/hal/ports/STM32/STM32L1xx/hal_lld.c
@@ -98,8 +98,10 @@ static void hal_lld_backup_domain_init(void) {
*/
void hal_lld_init(void) {
- /* Reset of all peripherals.*/
- rccResetAHB(~RCC_AHBRSTR_FLITFRST);
+ /* Reset of all peripherals.
+ Note, GPIOs are not reset because initialized before this point in
+ board files.*/
+ rccResetAHB(~(RCC_AHBRSTR_FLITFRST | STM32_GPIO_EN_MASK));
rccResetAPB1(~RCC_APB1RSTR_PWRRST);
rccResetAPB2(~0);
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-30 22:03:46 +0000