diff options
Diffstat (limited to 'os/hal/ports')
-rw-r--r-- | os/hal/ports/STM32/LLD/FSMCv1/fsmc.c (renamed from os/hal/ports/STM32/LLD/emc_lld.c) | 99 | ||||
-rw-r--r-- | os/hal/ports/STM32/LLD/FSMCv1/fsmc.h (renamed from os/hal/ports/STM32/LLD/emc_lld.h) | 75 | ||||
-rw-r--r-- | os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c | 547 | ||||
-rw-r--r-- | os/hal/ports/STM32/LLD/FSMCv1/nand_lld.h (renamed from os/hal/ports/STM32/LLD/emcnand_lld.h) | 178 | ||||
-rw-r--r-- | os/hal/ports/STM32/LLD/emcnand_lld.c | 545 | ||||
-rw-r--r-- | os/hal/ports/STM32/STM32F4xx/platform.mk | 7 | ||||
-rw-r--r-- | os/hal/ports/STM32/STM32F4xx/stm32_registry.h | 20 |
7 files changed, 739 insertions, 732 deletions
diff --git a/os/hal/ports/STM32/LLD/emc_lld.c b/os/hal/ports/STM32/LLD/FSMCv1/fsmc.c index 885a12965..a19919582 100644 --- a/os/hal/ports/STM32/LLD/emc_lld.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/fsmc.c @@ -19,16 +19,16 @@ */ /** - * @file emc_lld.c - * @brief EMC Driver subsystem low level driver source template. + * @file fsmc.c + * @brief FSMC Driver subsystem low level driver source template. * - * @addtogroup EMC + * @addtogroup FSMC * @{ */ #include "hal.h" -#if HAL_USE_EMC || defined(__DOXYGEN__) +#if HAL_USE_NAND || defined(__DOXYGEN__) /*===========================================================================*/ /* Driver local definitions. */ @@ -39,10 +39,10 @@ /*===========================================================================*/ /** - * @brief EMC1 driver identifier. + * @brief FSMC1 driver identifier. */ -#if STM32_EMC_USE_FSMC1 || defined(__DOXYGEN__) -EMCDriver EMCD1; +#if STM32_FSMC_USE_FSMC1 || defined(__DOXYGEN__) +FSMCDriver FSMCD1; #endif /*===========================================================================*/ @@ -66,89 +66,90 @@ EMCDriver EMCD1; /*===========================================================================*/ /** - * @brief Low level EMC driver initialization. + * @brief Low level FSMC driver initialization. * * @notapi */ -void emc_lld_init(void) { +void fsmc_lld_init(void) { -#if STM32_EMC_USE_FSMC1 - emcObjectInit(&EMCD1); + FSMCD1.state = FSMC_STOP; -#if STM32_EMCNAND_USE_EMCNAND1 - EMCD1.nand1 = (FSMC_NAND_TypeDef *)FSMC_Bank2_R_BASE; +#if STM32_NAND_USE_FSMC_NAND1 + FSMCD1.nand1 = (FSMC_NAND_TypeDef *)FSMC_Bank2_R_BASE; #endif -#if STM32_EMCNAND_USE_EMCNAND2 - EMCD1.nand2 = (FSMC_NAND_TypeDef *)FSMC_Bank3_R_BASE; +#if STM32_NAND_USE_FSMC_NAND2 + FSMCD1.nand2 = (FSMC_NAND_TypeDef *)FSMC_Bank3_R_BASE; #endif -#if STM32_USE_EMC_PCCARD - EMCD1.pccard = (FSMC_PCCARD_TypeDef *)FSMC_Bank4_R_BASE; +#if STM32_USE_FSMC_PCCARD + FSMCD1.pccard = (FSMC_PCCARD_TypeDef *)FSMC_Bank4_R_BASE; #endif - -#endif /* STM32_EMC_USE_EMC1 */ } /** - * @brief Configures and activates the EMC peripheral. + * @brief Configures and activates the FSMC peripheral. * - * @param[in] emcp pointer to the @p EMCDriver object + * @param[in] fsmcp pointer to the @p FSMCDriver object * * @notapi */ -void emc_lld_start(EMCDriver *emcp) { +void fsmc_lld_start(FSMCDriver *fsmcp) { + - if (emcp->state == EMC_STOP) { + osalDbgAssert((fsmcp->state == FSMC_STOP) || (fsmcp->state == FSMC_READY), + "invalid state"); + + if (fsmcp->state == FSMC_STOP) { /* Enables the peripheral.*/ -#if STM32_EMC_USE_FSMC1 - if (&EMCD1 == emcp) { +#if STM32_FSMC_USE_FSMC1 + if (&FSMCD1 == fsmcp) { rccResetFSMC(); rccEnableFSMC(FALSE); - #if STM32_EMC_USE_INT - nvicEnableVector(FSMC_IRQn, STM32_EMC_FSMC1_IRQ_PRIORITY); - #endif /* STM32_EMC_USE_INT */ + #if STM32_NAND_USE_FSMC_INT + nvicEnableVector(FSMC_IRQn, STM32_FSMC_FSMC1_IRQ_PRIORITY); + #endif } -#endif /* PLATFORM_STM32_USE_EMC1 */ +#endif /* STM32_FSMC_USE_FSMC1 */ - emcp->state = EMC_READY; + fsmcp->state = FSMC_READY; } } /** - * @brief Deactivates the EMC peripheral. + * @brief Deactivates the FSMC peripheral. * - * @param[in] emcp pointer to the @p EMCDriver object + * @param[in] emcp pointer to the @p FSMCDriver object * * @notapi */ -void emc_lld_stop(EMCDriver *emcp) { +void fsmc_lld_stop(FSMCDriver *fsmcp) { - if (emcp->state == EMC_READY) { + if (fsmcp->state == FSMC_READY) { /* Resets the peripheral.*/ rccResetFSMC(); /* Disables the peripheral.*/ -#if STM32_EMC_USE_FSMC1 - if (&EMCD1 == emcp) { - #if STM32_EMC_USE_INT +#if STM32_FSMC_USE_FSMC1 + if (&FSMCD1 == fsmcp) { + #if STM32_NAND_USE_FSMC_INT nvicDisableVector(FSMC_IRQn); #endif rccDisableFSMC(FALSE); } -#endif /* PLATFORM_STM32_USE_EMC1 */ +#endif /* PLATFORM_STM32_USE_FSMC1 */ - emcp->state = EMC_STOP; + fsmcp->state = FSMC_STOP; } } -#if STM32_EMC_USE_INT +#if STM32_NAND_USE_FSMC_INT /** * @brief Serve common interrupt. * * @notapi */ -void emc_lld_serve_interrupt(void) { +void fsmc_lld_serve_interrupt(void) { osalSysHalt("Unrealized"); } @@ -162,20 +163,20 @@ CH_IRQ_HANDLER(FSMC_IRQHandler) { osalSysHalt("This functionality untested"); CH_IRQ_PROLOGUE(); -#if STM32_EMCNAND_USE_EMCNAND1 - if (EMCD1.nand1->SR & FSMC_SR_ISR_MASK){ - EMCNANDD1.isr_handler(&EMCNANDD1, EMCD1.nand1->SR); +#if STM32_NAND_USE_FSMC_NAND1 + if (FSMCD1.nand1->SR & FSMC_SR_ISR_MASK){ + NANDD1.isr_handler(&NANDD1, FSMCD1.nand1->SR); } #endif -#if STM32_EMCNAND_USE_EMCNAND2 - if (EMCD1.nand2->SR & FSMC_SR_ISR_MASK){ - EMCNANDD2.isr_handler(&EMCNANDD2, EMCD1.nand2->SR); +#if STM32_NAND_USE_FSMC_NAND2 + if (FSMCD1.nand2->SR & FSMC_SR_ISR_MASK){ + NANDD2.isr_handler(&NANDD2, FSMCD1.nand2->SR); } #endif CH_IRQ_EPILOGUE(); } -#endif /* STM32_EMC_USE_INT */ +#endif /* STM32_FSMC_USE_INT */ -#endif /* HAL_USE_EMC */ +#endif /* HAL_USE_FSMC */ /** @} */ diff --git a/os/hal/ports/STM32/LLD/emc_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/fsmc.h index bb3b8a538..32245e9e4 100644 --- a/os/hal/ports/STM32/LLD/emc_lld.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/fsmc.h @@ -19,18 +19,18 @@ */ /** - * @file emc_lld.h - * @brief EMC Driver subsystem low level driver header template. + * @file fsmc.h + * @brief FSMC Driver subsystem low level driver header template. * - * @addtogroup EMC + * @addtogroup FSMC * @{ */ -#ifndef _EMC_LLD_H_ -#define _EMC_LLD_H_ +#ifndef _FSMC_H_ +#define _FSMC_H_ -#if HAL_USE_EMC || defined(__DOXYGEN__) +#if HAL_USE_NAND || defined(__DOXYGEN__) /*===========================================================================*/ /* Driver constants. */ @@ -146,11 +146,11 @@ typedef struct { * @{ */ /** - * @brief EMC driver enable switch. - * @details If set to @p TRUE the support for EMC is included. + * @brief FSMC driver enable switch. + * @details If set to @p TRUE the support for FSMC is included. */ -#if !defined(STM32_EMC_USE_FSMC1) || defined(__DOXYGEN__) -#define STM32_EMC_USE_FSMC1 FALSE +#if !defined(STM32_FSMC_USE_FSMC1) || defined(__DOXYGEN__) +#define STM32_FSMC_USE_FSMC1 FALSE #endif /** @@ -158,10 +158,8 @@ typedef struct { * @details MCUs in 100-pin package has no dedicated interrupt pin for FSMC. * You have to use EXTI module instead to workaround this issue. */ -#if STM32_EMC_EMCNAND_USE_FSMC_INT -#define STM32_EMC_USE_INT TRUE -#else -#define STM32_EMC_USE_INT FALSE +#if !defined(STM32_NAND_USE_FSMC_INT) || defined(__DOXYGEN__) +#define STM32_NAND_USE_FSMC_INT FALSE #endif /** @} */ @@ -169,8 +167,8 @@ typedef struct { /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ -#if !STM32_EMC_USE_FSMC1 -#error "EMC driver activated but no EMC peripheral assigned" +#if !STM32_FSMC_USE_FSMC1 +#error "FSMC driver activated but no FSMC peripheral assigned" #endif /*===========================================================================*/ @@ -178,9 +176,18 @@ typedef struct { /*===========================================================================*/ /** - * @brief Type of a structure representing an EMC driver. + * @brief Type of a structure representing an FSMC driver. */ -typedef struct EMCDriver EMCDriver; +typedef struct FSMCDriver FSMCDriver; + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + FSMC_UNINIT = 0, /**< Not initialized. */ + FSMC_STOP = 1, /**< Stopped. */ + FSMC_READY = 2, /**< Ready. */ +} fsmcstate_t; /** * @brief Driver configuration structure. @@ -188,28 +195,24 @@ typedef struct EMCDriver EMCDriver; */ typedef struct { -} EMCConfig; +} FSMCConfig; /** - * @brief Structure representing an EMC driver. + * @brief Structure representing an FSMC driver. */ -struct EMCDriver { +struct FSMCDriver { /** * @brief Driver state. */ - emcstate_t state; - /** - * @brief Current configuration data. - */ - const EMCConfig *config; + fsmcstate_t state; /* End of the mandatory fields.*/ -#if STM32_EMCNAND_USE_EMCNAND1 +#if STM32_NAND_USE_FSMC_NAND1 FSMC_NAND_TypeDef *nand1; #endif -#if STM32_EMCNAND_USE_EMCNAND2 +#if STM32_NAND_USE_FSMC_NAND2 FSMC_NAND_TypeDef *nand2; #endif -#if STM32_USE_EMC_PCCARD +#if STM32_USE_FSMC_PCCARD FSMC_PCCard_TypeDef *pccard; #endif }; @@ -222,22 +225,22 @@ struct EMCDriver { /* External declarations. */ /*===========================================================================*/ -#if STM32_EMC_USE_FSMC1 && !defined(__DOXYGEN__) -extern EMCDriver EMCD1; +#if STM32_FSMC_USE_FSMC1 && !defined(__DOXYGEN__) +extern FSMCDriver FSMCD1; #endif #ifdef __cplusplus extern "C" { #endif - void emc_lld_init(void); - void emc_lld_start(EMCDriver *emcp); - void emc_lld_stop(EMCDriver *emcp); + void fsmc_lld_init(void); + void fsmc_lld_start(FSMCDriver *fsmcp); + void fsmc_lld_stop(FSMCDriver *fsmcp); #ifdef __cplusplus } #endif -#endif /* HAL_USE_EMC */ +#endif /* HAL_USE_NAND */ -#endif /* _EMC_LLD_H_ */ +#endif /* _FSMC_H_ */ /** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c b/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c new file mode 100644 index 000000000..aa324343d --- /dev/null +++ b/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c @@ -0,0 +1,547 @@ +/* + ChibiOS/HAL - Copyright (C) 2006-2014 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + Concepts and parts of this file have been contributed by Uladzimir Pylinsky + aka barthess. + */ + +/** + * @file nand_lld.c + * @brief NAND Driver subsystem low level driver source template. + * + * @addtogroup NAND + * @{ + */ + +#include "hal.h" + +#if HAL_USE_NAND || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ +#define NAND_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_NAND_DMA_STREAM, \ + STM32_FSMC_DMA_CHN) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief NAND1 driver identifier. + */ +#if STM32_NAND_USE_FSMC_NAND1 || defined(__DOXYGEN__) +NANDDriver NANDD1; +#endif + +/** + * @brief NAND2 driver identifier. + */ +#if STM32_NAND_USE_FSMC_NAND2 || defined(__DOXYGEN__) +NANDDriver NANDD2; +#endif + +/*===========================================================================*/ +/* Driver local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ +/** + * @brief Wakes up the waiting thread. + * + * @param[in] nandp pointer to the @p NANDDriver object + * @param[in] msg wakeup message + * + * @notapi + */ +static void wakeup_isr(NANDDriver *nandp){ + + osalDbgCheck(nandp->thread != NULL); + osalThreadResumeI(&nandp->thread, MSG_OK); +} + +/** + * @brief Put calling thread in suspend and switch driver state + * + * @param[in] nandp pointer to the @p NANDDriver object + */ +static void nand_lld_suspend_thread(NANDDriver *nandp) { + + //nandp->thread = chThdGetSelfX(); + osalThreadSuspendS(&nandp->thread); +} + +/** + * @brief Caclulate ECCPS register value + * + * @param[in] nandp pointer to the @p NANDDriver object + */ +static uint32_t calc_eccps(NANDDriver *nandp){ + + uint32_t i = 0; + uint32_t eccps = nandp->config->page_data_size; + + eccps = eccps >> 9; + while (eccps > 0){ + i++; + eccps >>= 1; + } + + return i << 17; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if STM32_NAND_USE_FSMC_INT +/** + * @brief Enable interrupts from FSMC + * + * @param[in] nandp pointer to the @p NANDDriver object + * + * @notapi + */ +static void nand_ready_isr_enable(NANDDriver *nandp) { + nandp->nand->SR |= FSMC_SR_IREN; + osalSysHalt("Function untested"); +} + +/** + * @brief Disable interrupts from FSMC + * + * @param[in] nandp pointer to the @p NANDDriver object + * + * @notapi + */ +static void nand_ready_isr_disable(NANDDriver *nandp) { + nandp->nand->SR &= ~FSMC_SR_IREN; + osalSysHalt("Function untested"); +} + +/** + * @brief Ready interrupt handler + * + * @param[in] nandp pointer to the @p NANDDriver object + * @param[in] flags flags passed from FSMC intrrupt handler + * + * @notapi + */ +static void nand_isr_handler (NANDDriver *nandp, + nandflags_t flags){ + (void)nandp; + (void)flags; + + osalSysHalt("Unrealized"); +} +#else /* STM32_NAND_USE_FSMC_INT */ +/** + * @brief Disable interrupts from EXTI + * + * @param[in] nandp pointer to the @p NANDDriver object + * + * @notapi + */ +static void nand_ready_isr_enable(NANDDriver *nandp) { + nandp->config->ext_isr_enable(); +} + +/** + * @brief Enable interrupts from EXTI + * + * @param[in] nandp pointer to the @p NANDDriver object + * + * @notapi + */ +static void nand_ready_isr_disable(NANDDriver *nandp) { + nandp->config->ext_isr_disable(); +} + +/** + * @brief Ready pin interrupt handler. + * + * @param[in] nandp pointer to the @p NANDDriver object + * + * @notapi + */ +static void nand_isr_handler(NANDDriver *nandp){ + + osalSysLockFromISR(); + + switch (nandp->state){ + case NAND_READ: + nandp->state = NAND_DMA_RX; + dmaStartMemCopy(nandp->dma, nandp->dmamode, + nandp->map_data, nandp->rxdata, nandp->datalen); + /* thread will be woked up from DMA ISR */ + break; + + case NAND_ERASE: + /* NAND reports about erase finish */ + nandp->state = NAND_READY; + wakeup_isr(nandp); + break; + + case NAND_PROGRAM: + /* NAND reports about page programming finish */ + nandp->state = NAND_READY; + wakeup_isr(nandp); + break; + + default: + osalSysHalt("Unhandled case"); + break; + } + + osalSysUnlockFromISR(); +} +#endif /* STM32_NAND_USE_FSMC_INT */ + +/** + * @brief DMA RX end IRQ handler. + * + * @param[in] nandp pointer to the @p NANDDriver object + * @param[in] flags pre-shifted content of the ISR register + * + * @notapi + */ +static void nand_lld_serve_transfer_end_irq(NANDDriver *nandp, + uint32_t flags) { + /* DMA errors handling.*/ +#if defined(STM32_NAND_DMA_ERROR_HOOK) + if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { + STM32_NAND_DMA_ERROR_HOOK(nandp); + } +#else + (void)flags; +#endif + + osalSysLockFromISR(); + + dmaStreamDisable(nandp->dma); + + switch (nandp->state){ + case NAND_DMA_TX: + nandp->state = NAND_PROGRAM; + nandp->map_cmd[0] = NAND_CMD_PAGEPROG; + /* thread will be woken from ready_isr() */ + break; + + case NAND_DMA_RX: + nandp->state = NAND_READY; + nandp->rxdata = NULL; + nandp->datalen = 0; + wakeup_isr(nandp); + break; + + default: + osalSysHalt("Unhandled case"); + break; + } + + osalSysUnlockFromISR(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level NAND driver initialization. + * + * @notapi + */ +void nand_lld_init(void) { + +#if STM32_NAND_USE_FSMC_NAND1 + /* Driver initialization.*/ + nandObjectInit(&NANDD1); + NANDD1.rxdata = NULL; + NANDD1.datalen = 0; + NANDD1.thread = NULL; + NANDD1.dma = STM32_DMA_STREAM(STM32_NAND_NAND1_DMA_STREAM); + NANDD1.nand = (FSMC_NAND_TypeDef *)FSMC_Bank2_R_BASE; + NANDD1.map_data = (uint8_t*)FSMC_Bank2_MAP_COMMON_DATA; + NANDD1.map_cmd = (uint8_t*)FSMC_Bank2_MAP_COMMON_CMD; + NANDD1.map_addr = (uint8_t*)FSMC_Bank2_MAP_COMMON_ADDR; +#endif /* STM32_NAND_USE_FSMC_NAND1 */ + +#if STM32_NAND_USE_FSMC_NAND2 + /* Driver initialization.*/ + nandObjectInit(&NANDD2); + NANDD2.rxdata = NULL; + NANDD2.datalen = 0; + NANDD2.thread = NULL; + NANDD2.dma = STM32_DMA_STREAM(STM32_NAND_NAND2_DMA_STREAM); + NANDD2.nand = (FSMC_NAND_TypeDef *)FSMC_Bank3_R_BASE; + NANDD2.map_data = (uint8_t*)FSMC_Bank3_MAP_COMMON_DATA; + NANDD2.map_cmd = (uint8_t*)FSMC_Bank3_MAP_COMMON_CMD; + NANDD2.map_addr = (uint8_t*)FSMC_Bank3_MAP_COMMON_ADDR; +#endif /* STM32_NAND_USE_FSMC_NAND2 */ +} + +/** + * @brief Configures and activates the NAND peripheral. + * + * @param[in] nandp pointer to the @p NANDDriver object + * + * @notapi + */ +void nand_lld_start(NANDDriver *nandp) { + + bool b; + + if (FSMCD1.state == FSMC_STOP) + fsmc_lld_start(&FSMCD1); + + if (nandp->state == NAND_STOP) { + b = dmaStreamAllocate(nandp->dma, + STM32_EMC_FSMC1_IRQ_PRIORITY, + (stm32_dmaisr_t)nand_lld_serve_transfer_end_irq, + (void *)nandp); + osalDbgAssert(!b, "stream already allocated"); + nandp->dmamode = STM32_DMA_CR_CHSEL(NAND_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_NAND_NAND1_DMA_PRIORITY) | + STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE | + STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | + STM32_DMA_CR_TCIE; + /* dmaStreamSetFIFO(nandp->dma, + STM32_DMA_FCR_DMDIS | NAND_STM32_DMA_FCR_FTH_LVL); */ + nandp->nand->PCR = calc_eccps(nandp) | FSMC_PCR_PTYP | FSMC_PCR_PBKEN; + nandp->nand->PMEM = nandp->config->pmem; + nandp->nand->PATT = nandp->config->pmem; + nandp->isr_handler = nand_isr_handler; + nand_ready_isr_enable(nandp); + } +} + +/** + * @brief Deactivates the NAND peripheral. + * + * @param[in] nandp pointer to the @p NANDDriver object + * + * @notapi + */ +void nand_lld_stop(NANDDriver *nandp) { + + if (nandp->state == NAND_READY) { + dmaStreamRelease(nandp->dma); + nandp->nand->PCR &= ~FSMC_PCR_PBKEN; + nand_ready_isr_disable(nandp); + nandp->isr_handler = NULL; + } +} + +/** + * @brief Read data from NAND. + * + * @param[in] nandp pointer to the @p NANDDriver object + * @param[out] data pointer to data buffer + * @param[in] datalen size of data buffer + * @param[in] addr pointer to address buffer + * @param[in] addrlen length of address + * @param[out] ecc pointer to store computed ECC. Ignored when NULL. + * + * @notapi + */ +void nand_lld_read_data(NANDDriver *nandp, uint8_t *data, + size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc){ + + nandp->state = NAND_READ; + nandp->rxdata = data; + nandp->datalen = datalen; + + nand_lld_write_cmd (nandp, NAND_CMD_READ0); + nand_lld_write_addr(nandp, addr, addrlen); + osalSysLock(); + nand_lld_write_cmd (nandp, NAND_CMD_READ0_CONFIRM); + + /* Here NAND asserts busy signal and starts transferring from memory + array to page buffer. After the end of transmission ready_isr functions + starts DMA transfer from page buffer to MCU's RAM.*/ + osalDbgAssert((nandp->nand->PCR & FSMC_PCR_ECCEN) == 0, + "State machine broken. ECCEN must be previously disabled."); + + if (NULL != ecc){ + nandp->nand->PCR |= FSMC_PCR_ECCEN; + } + + nand_lld_suspend_thread(nandp); + osalSysUnlock(); + + /* thread was woken up from DMA ISR */ + if (NULL != ecc){ + while (! (nandp->nand->SR & FSMC_SR_FEMPT)) + ; + *ecc = nandp->nand->ECCR; + nandp->nand->PCR &= ~FSMC_PCR_ECCEN; + } +} + +/** + * @brief Write data to NAND. + * + * @param[in] nandp pointer to the @p NANDDriver object + * @param[in] data buffer with data to be written + * @param[in] datalen size of data buffer + * @param[in] addr pointer to address buffer + * @param[in] addrlen length of address + * @param[out] ecc pointer to store computed ECC. Ignored when NULL. + * + * @return The operation status reported by NAND IC (0x70 command). + * + * @notapi + */ +uint8_t nand_lld_write_data(NANDDriver *nandp, const uint8_t *data, + size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc){ + + nandp->state = NAND_WRITE; + + nand_lld_write_cmd (nandp, NAND_CMD_WRITE); + osalSysLock(); + nand_lld_write_addr(nandp, addr, addrlen); + + /* Now start DMA transfer to NAND buffer and put thread in sleep state. + Tread will we woken up from ready ISR. */ + nandp->state = NAND_DMA_TX; + osalDbgAssert((nandp->nand->PCR & FSMC_PCR_ECCEN) == 0, + "State machine broken. ECCEN must be previously disabled."); + + if (NULL != ecc){ + nandp->nand->PCR |= FSMC_PCR_ECCEN; + } + + dmaStartMemCopy(nandp->dma, nandp->dmamode, + data, nandp->map_data, datalen); + + nand_lld_suspend_thread(nandp); + osalSysUnlock(); + + if (NULL != ecc){ + while (! (nandp->nand->SR & FSMC_SR_FEMPT)) + ; + *ecc = nandp->nand->ECCR; + nandp->nand->PCR &= ~FSMC_PCR_ECCEN; + } + + return nand_lld_read_status(nandp); +} + +/** + * @brief Erase block. + * + * @param[in] nandp pointer to the @p NANDDriver object + * @param[in] addr pointer to address buffer + * @param[in] addrlen length of address + * + * @return The operation status reported by NAND IC (0x70 command). + * + * @notapi + */ +uint8_t nand_lld_erase(NANDDriver *nandp, + uint8_t *addr, size_t addrlen){ + + nandp->state = NAND_ERASE; + + nand_lld_write_cmd (nandp, NAND_CMD_ERASE); + nand_lld_write_addr(nandp, addr, addrlen); + osalSysLock(); + nand_lld_write_cmd (nandp, NAND_CMD_ERASE_CONFIRM); + nand_lld_suspend_thread(nandp); + osalSysUnlock(); + + return nand_lld_read_status(nandp); +} + +/** + * @brief Read data from NAND using polling approach. + * + * @detatils Use this function to read data when no waiting expected. For + * Example read status word after 0x70 command + * + * @param[in] nandp pointer to the @p NANDDriver object + * @param[out] data pointer to output buffer + * @param[in] len length of data to be read + * + * @notapi + */ +void nand_lld_polled_read_data(NANDDriver *nandp, + uint8_t *data, size_t len){ + size_t i = 0; + + for (i=0; i<len; i++) + data[i] = nandp->map_data[i]; +} + +/** + * @brief Send addres to NAND. + * + * @param[in] nandp pointer to the @p NANDDriver object + * @param[in] len length of address array + * @param[in] addr pointer to address array + * + * @notapi + */ +void nand_lld_write_addr(NANDDriver *nandp, + const uint8_t *addr, size_t len){ + size_t i = 0; + + for (i=0; i<len; i++) + nandp->map_addr[i] = addr[i]; +} + +/** + * @brief Send command to NAND. + * + * @param[in] nandp pointer to the @p NANDDriver object + * @param[in] cmd command value + * + * @notapi + */ +void nand_lld_write_cmd(NANDDriver *nandp, uint8_t cmd){ + nandp->map_cmd[0] = cmd; +} + +/** + * @brief Read status byte from NAND. + * + * @param[in] nandp pointer to the @p NANDDriver object + * + * @return Status byte. + * + * @notapi + */ +uint8_t nand_lld_read_status(NANDDriver *nandp) { + + uint8_t status[1] = {0x01}; /* presume worse */ + + nand_lld_write_cmd(nandp, NAND_CMD_STATUS); + nand_lld_polled_read_data(nandp, status, 1); + + return status[0]; +} + +#endif /* HAL_USE_NAND */ + +/** @} */ + diff --git a/os/hal/ports/STM32/LLD/emcnand_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.h index bac7cea22..5e7ba90c5 100644 --- a/os/hal/ports/STM32/LLD/emcnand_lld.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.h @@ -19,24 +19,26 @@ */ /** - * @file emcnand_lld.h - * @brief EMCNAND Driver subsystem low level driver header template. + * @file nand_lld.h + * @brief NAND Driver subsystem low level driver header template. * - * @addtogroup EMCNAND + * @addtogroup NAND * @{ */ -#ifndef _EMCNAND_LLD_H_ -#define _EMCNAND_LLD_H_ +#ifndef _NAND_LLD_H_ +#define _NAND_LLD_H_ -#if HAL_USE_EMCNAND || defined(__DOXYGEN__) +#include "fsmc.h" + +#if HAL_USE_NAND || defined(__DOXYGEN__) /*===========================================================================*/ /* Driver constants. */ /*===========================================================================*/ -#define EMCNAND_MIN_PAGE_SIZE 256 -#define EMCNAND_MAX_PAGE_SIZE 8192 -#define EMCNAND_BAD_MAP_END_MARK ((uint16_t)0xFFFF) +#define NAND_MIN_PAGE_SIZE 256 +#define NAND_MAX_PAGE_SIZE 8192 +#define NAND_BAD_MAP_END_MARK ((uint16_t)0xFFFF) /*===========================================================================*/ /* Driver pre-compile time settings. */ @@ -54,66 +56,66 @@ #endif /** - * @brief EMCNAND driver enable switch. - * @details If set to @p TRUE the support for EMCNAND1 is included. + * @brief NAND driver enable switch. + * @details If set to @p TRUE the support for NAND1 is included. */ -#if !defined(STM32_EMCNAND_USE_EMCNAND1) || defined(__DOXYGEN__) -#define STM32_EMCNAND_USE_EMCNAND1 FALSE +#if !defined(STM32_NAND_USE_NAND1) || defined(__DOXYGEN__) +#define STM32_NAND_USE_NAND1 FALSE #endif /** - * @brief EMCNAND driver enable switch. - * @details If set to @p TRUE the support for EMCNAND2 is included. + * @brief NAND driver enable switch. + * @details If set to @p TRUE the support for NAND2 is included. */ -#if !defined(STM32_EMCNAND_USE_EMCNAND2) || defined(__DOXYGEN__) -#define STM32_EMCNAND_USE_EMCNAND2 FALSE +#if !defined(STM32_NAND_USE_NAND2) || defined(__DOXYGEN__) +#define STM32_NAND_USE_NAND2 FALSE #endif /** - * @brief EMCNAND DMA error hook. + * @brief NAND DMA error hook. * @note The default action for DMA errors is a system halt because DMA * error can only happen because programming errors. */ -#if !defined(STM32_EMCNAND_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_EMCNAND_DMA_ERROR_HOOK(emcnandp) osalSysHalt("DMA failure") +#if !defined(STM32_NAND_DMA_ERROR_HOOK) || defined(__DOXYGEN__) +#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure") #endif /** - * @brief EMCNAND interrupt enable switch. + * @brief NAND interrupt enable switch. * @details If set to @p TRUE the support for internal FSMC interrupt included. */ -#if !defined(STM32_EMCNAND_USE_INT) || defined(__DOXYGEN__) -#define STM32_EMCNAND_USE_INT FALSE +#if !defined(STM32_NAND_USE_INT) || defined(__DOXYGEN__) +#define STM32_NAND_USE_INT FALSE #endif /** -* @brief EMCNAND1 DMA priority (0..3|lowest..highest). +* @brief NAND1 DMA priority (0..3|lowest..highest). */ -#if !defined(STM32_EMCNAND_EMCNAND1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EMCNAND_EMCNAND1_DMA_PRIORITY 0 +#if !defined(STM32_NAND_NAND1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_NAND_NAND1_DMA_PRIORITY 0 #endif /** -* @brief EMCNAND2 DMA priority (0..3|lowest..highest). +* @brief NAND2 DMA priority (0..3|lowest..highest). */ -#if !defined(STM32_EMCNAND_EMCNAND2_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EMCNAND_EMCNAND2_DMA_PRIORITY 0 +#if !defined(STM32_NAND_NAND2_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_NAND_NAND2_DMA_PRIORITY 0 #endif /** - * @brief DMA stream used for EMCNAND1 operations. + * @brief DMA stream used for NAND1 operations. * @note This option is only available on platforms with enhanced DMA. */ -#if !defined(STM32_EMCNAND_EMCNAND1_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_EMCNAND_EMCNAND1_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#if !defined(STM32_NAND_NAND1_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_NAND_NAND1_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) #endif /** - * @brief DMA stream used for EMCNAND2 operations. + * @brief DMA stream used for NAND2 operations. * @note This option is only available on platforms with enhanced DMA. */ -#if !defined(STM32_EMCNAND_EMCNAND2_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_EMCNAND_EMCNAND2_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#if !defined(STM32_NAND_NAND2_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_NAND_NAND2_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #endif /** @} */ @@ -122,28 +124,26 @@ /* Derived constants and error checks. */ /*===========================================================================*/ -#if !STM32_EMCNAND_USE_EMCNAND1 && !STM32_EMCNAND_USE_EMCNAND2 -#error "EMCNAND driver activated but no EMCNAND peripheral assigned" +#if !STM32_NAND_USE_FSMC_NAND1 && !STM32_NAND_USE_FSMC_NAND2 +#error "NAND driver activated but no NAND peripheral assigned" #endif -#if STM32_EMCNAND_USE_EMCNAND1 && !STM32_HAS_EMC -#error "EMC not present in the selected device" +#if STM32_NAND_USE_FSMC_NAND1 && !STM32_HAS_FSMC +#error "FSMC not present in the selected device" #endif -#if !STM32_EMCNAND_USE_INT && !HAL_USE_EXT -#error "External interrupt controller must be enabled to use this feature" +#if STM32_NAND_USE_FSMC_NAND2 && !STM32_HAS_FSMC +#error "FSMC not present in the selected device" #endif -#if STM32_EMCNAND_USE_EMCNAND1 && \ - !STM32_DMA_IS_VALID_ID(STM32_EMCNAND_EMCNAND1_DMA_STREAM, \ - STM32_EMC_DMA_MSK) -#error "invalid DMA stream associated to EMCNAND" +#if !STM32_NAND_USE_FSMC_INT && !HAL_USE_EXT +#error "External interrupt controller must be enabled to use this feature" #endif -#if STM32_EMCNAND_USE_EMCNAND2 && \ - !STM32_DMA_IS_VALID_ID(STM32_EMCNAND_EMCNAND2_DMA_STREAM, \ - STM32_EMC_DMA_MSK) -#error "invalid DMA stream associated to EMCNAND" +#if (STM32_NAND_USE_FSMC_NAND2 || STM32_NAND_USE_FSMC_NAND1) && \ + !STM32_DMA_IS_VALID_ID(STM32_NAND_DMA_STREAM, \ + STM32_FSMC_DMA_MSK) +#error "invalid DMA stream associated to NAND" #endif #if !defined(STM32_DMA_REQUIRED) @@ -157,30 +157,30 @@ /** * @brief NAND driver condition flags type. */ -typedef uint32_t emcnandflags_t; +typedef uint32_t nandflags_t; /** - * @brief Type of a structure representing an EMCNAND driver. + * @brief Type of a structure representing an NAND driver. */ -typedef struct EMCNANDDriver EMCNANDDriver; +typedef struct NANDDriver NANDDriver; -#if STM32_EMC_USE_INT +#if STM32_NAND_USE_FSMC_INT /** * @brief Type of interrupt handler function */ -typedef void (*emcnandisrhandler_t) - (EMCNANDDriver *emcnandp, emcnandflags_t flags); +typedef void (*nandisrhandler_t) + (NANDDriver *nandp, nandflags_t flags); #else /** * @brief Type of interrupt handler function */ -typedef void (*emcnandisrhandler_t)(EMCNANDDriver *emcnandp); +typedef void (*nandisrhandler_t)(NANDDriver *nandp); /** * @brief Type of function switching external interrupts on and off. */ -typedef void (*emcnandisrswitch_t)(void); -#endif /* STM32_EMC_USE_INT */ +typedef void (*nandisrswitch_t)(void); +#endif /* STM32_NAND_USE_FSMC_INT */ /** * @brief Driver configuration structure. @@ -190,7 +190,7 @@ typedef struct { /** * @brief Pointer to lower level driver. */ - EMCDriver *emcp; + FSMCDriver *fsmcp; /** * @brief Number of erase blocks in NAND device. */ @@ -207,13 +207,13 @@ typedef struct { * @brief Number of pages in block. */ uint32_t pages_per_block; -#if EMCNAND_USE_BAD_MAP +#if NAND_USE_BAD_MAP /** * @brief Pointer to bad block map. * @details One bit per block. Memory for map must be allocated by user. */ uint32_t *bb_map; -#endif /* EMCNAND_USE_BAD_MAP */ +#endif /* NAND_USE_BAD_MAP */ /** * @brief Number of write cycles for row addressing. */ @@ -232,34 +232,34 @@ typedef struct { * from STMicroelectronics. */ uint32_t pmem; -#if !STM32_EMC_USE_INT +#if !STM32_NAND_USE_FSMC_INT /** * @brief Function enabling interrupts from EXTI */ - emcnandisrswitch_t ext_isr_enable; + nandisrswitch_t ext_isr_enable; /** * @brief Function disabling interrupts from EXTI */ - emcnandisrswitch_t ext_isr_disable; -#endif /* !STM32_EMC_USE_INT */ -} EMCNANDConfig; + nandisrswitch_t ext_isr_disable; +#endif /* !STM32_NAND_USE_FSMC_INT */ +} NANDConfig; /** - * @brief Structure representing an EMCNAND driver. + * @brief Structure representing an NAND driver. */ -struct EMCNANDDriver { +struct NANDDriver { /** * @brief Driver state. */ - emcnandstate_t state; + nandstate_t state; /** * @brief Current configuration data. */ - const EMCNANDConfig *config; + const NANDConfig *config; /** * @brief Array to store bad block map. */ -#if EMCNAND_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if NAND_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) #if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__) /** * @brief Mutex protecting the bus. @@ -268,12 +268,12 @@ struct EMCNANDDriver { #elif CH_CFG_USE_SEMAPHORES semaphore_t semaphore; #endif -#endif /* EMCNAND_USE_MUTUAL_EXCLUSION */ +#endif /* NAND_USE_MUTUAL_EXCLUSION */ /* End of the mandatory fields.*/ /** * @brief Function enabling interrupts from FSMC */ - emcnandisrhandler_t isr_handler; + nandisrhandler_t isr_handler; /** * @brief Pointer to current transaction buffer */ @@ -320,38 +320,38 @@ struct EMCNANDDriver { /* External declarations. */ /*===========================================================================*/ -#if STM32_EMCNAND_USE_EMCNAND1 && !defined(__DOXYGEN__) -extern EMCNANDDriver EMCNANDD1; +#if STM32_NAND_USE_FSMC_NAND1 && !defined(__DOXYGEN__) +extern NANDDriver NANDD1; #endif -#if STM32_EMCNAND_USE_EMCNAND2 && !defined(__DOXYGEN__) -extern EMCNANDDriver EMCNANDD2; +#if STM32_NAND_USE_FSMC_NAND2 && !defined(__DOXYGEN__) +extern NANDDriver NANDD2; #endif #ifdef __cplusplus extern "C" { #endif - void emcnand_lld_init(void); - void emcnand_lld_start(EMCNANDDriver *emcnandp); - void emcnand_lld_stop(EMCNANDDriver *emcnandp); - uint8_t emcnand_lld_write_data(EMCNANDDriver *emcnandp, const uint8_t *data, + void nand_lld_init(void); + void nand_lld_start(NANDDriver *nandp); + void nand_lld_stop(NANDDriver *nandp); + uint8_t nand_lld_write_data(NANDDriver *nandp, const uint8_t *data, size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc); - void emcnand_lld_read_data(EMCNANDDriver *emcnandp, uint8_t *data, + void nand_lld_read_data(NANDDriver *nandp, uint8_t *data, size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc); - void emcnand_lld_polled_read_data(EMCNANDDriver *emcnandp, uint8_t *data, + void nand_lld_polled_read_data(NANDDriver *nandp, uint8_t *data, size_t len); - uint8_t emcnand_lld_erase(EMCNANDDriver *emcnandp, uint8_t *addr, + uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen); - void emcnand_lld_write_addr(EMCNANDDriver *emcnandp, + void nand_lld_write_addr(NANDDriver *nandp, const uint8_t *addr, size_t len); - void emcnand_lld_write_cmd(EMCNANDDriver *emcnandp, uint8_t cmd); - uint8_t emcnand_lld_read_status(EMCNANDDriver *emcnandp); + void nand_lld_write_cmd(NANDDriver *nandp, uint8_t cmd); + uint8_t nand_lld_read_status(NANDDriver *nandp); #ifdef __cplusplus } #endif -#endif /* HAL_USE_EMCNAND */ +#endif /* HAL_USE_NAND */ -#endif /* _EMCNAND_LLD_H_ */ +#endif /* _NAND_LLD_H_ */ /** @} */ diff --git a/os/hal/ports/STM32/LLD/emcnand_lld.c b/os/hal/ports/STM32/LLD/emcnand_lld.c deleted file mode 100644 index 9ed6db9bd..000000000 --- a/os/hal/ports/STM32/LLD/emcnand_lld.c +++ /dev/null @@ -1,545 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2006-2014 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - Concepts and parts of this file have been contributed by Uladzimir Pylinsky - aka barthess. - */ - -/** - * @file emcnand_lld.c - * @brief EMCNAND Driver subsystem low level driver source template. - * - * @addtogroup EMCNAND - * @{ - */ - -#include "hal.h" - -#if HAL_USE_EMCNAND || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ -#define EMCNAND_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_EMCNAND_EMCNAND1_DMA_STREAM, \ - STM32_EMC_DMA_CHN) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief EMCNAND1 driver identifier. - */ -#if STM32_EMCNAND_USE_EMCNAND1 || defined(__DOXYGEN__) -EMCNANDDriver EMCNANDD1; -#endif - -/** - * @brief EMCNAND2 driver identifier. - */ -#if STM32_EMCNAND_USE_EMCNAND2 || defined(__DOXYGEN__) -EMCNANDDriver EMCNANDD2; -#endif - -/*===========================================================================*/ -/* Driver local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ -/** - * @brief Wakes up the waiting thread. - * - * @param[in] emcnandp pointer to the @p EMCNANDDriver object - * @param[in] msg wakeup message - * - * @notapi - */ -static void wakeup_isr(EMCNANDDriver *emcnandp){ - - osalDbgCheck(emcnandp->thread != NULL); - osalThreadResumeI(&emcnandp->thread, MSG_OK); -} - -/** - * @brief Put calling thread in suspend and switch driver state - * - * @param[in] emcnandp pointer to the @p EMCNANDDriver object - */ -static void emcnand_lld_suspend_thread(EMCNANDDriver *emcnandp) { - - //emcnandp->thread = chThdGetSelfX(); - osalThreadSuspendS(&emcnandp->thread); -} - -/** - * @brief Caclulate ECCPS register value - * - * @param[in] emcnandp pointer to the @p EMCNANDDriver object - */ -static uint32_t calc_eccps(EMCNANDDriver *emcnandp){ - - uint32_t i = 0; - uint32_t eccps = emcnandp->config->page_data_size; - - eccps = eccps >> 9; - while (eccps > 0){ - i++; - eccps >>= 1; - } - - return i << 17; -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if STM32_EMC_USE_INT -/** - * @brief Enable interrupts from FSMC - * - * @param[in] emcnandp pointer to the @p EMCNANDDriver object - * - * @notapi - */ -static void emcnand_ready_isr_enable(EMCNANDDriver *emcnandp) { - emcnandp->nand->SR |= FSMC_SR_IREN; - osalSysHalt("Function untested"); -} - -/** - * @brief Disable interrupts from FSMC - * - * @param[in] emcnandp pointer to the @p EMCNANDDriver object - * - * @notapi - */ -static void emcnand_ready_isr_disable(EMCNANDDriver *emcnandp) { - emcnandp->nand->SR &= ~FSMC_SR_IREN; - osalSysHalt("Function untested"); -} - -/** - * @brief Ready interrupt handler - * - * @param[in] emcnandp pointer to the @p EMCNANDDriver object - * @param[in] flags flags passed from FSMC intrrupt handler - * - * @notapi - */ -static void emcnand_isr_handler (EMCNANDDriver *emcnandp, - emcnandflags_t flags){ - (void)emcnandp; - (void)flags; - - osalSysHalt("Unrealized"); -} -#else /* STM32_EMC_USE_INT */ -/** - * @brief Disable interrupts from EXTI - * - * @param[in] emcnandp pointer to the @p EMCNANDDriver object - * - * @notapi - */ -static void emcnand_ready_isr_enable(EMCNANDDriver *emcnandp) { - emcnandp->config->ext_isr_enable(); -} - -/** - * @brief Enable interrupts from EXTI - * - * @param[in] emcnandp pointer to the @p EMCNANDDriver object - * - * @notapi - */ -static void emcnand_ready_isr_disable(EMCNANDDriver *emcnandp) { - emcnandp->config->ext_isr_disable(); -} - -/** - * @brief Ready pin interrupt handler. - * - * @param[in] emcnandp pointer to the @p EMCNANDDriver object - * - * @notapi - */ -static void emcnand_isr_handler(EMCNANDDriver *emcnandp){ - - osalSysLockFromISR(); - - switch (emcnandp->state){ - case EMCNAND_READ: - emcnandp->state = EMCNAND_DMA_RX; - dmaStartMemCopy(emcnandp->dma, emcnandp->dmamode, - emcnandp->map_data, emcnandp->rxdata, emcnandp->datalen); - /* thread will be woked up from DMA ISR */ - break; - - case EMCNAND_ERASE: - /* NAND reports about erase finish */ - emcnandp->state = EMCNAND_READY; - wakeup_isr(emcnandp); - break; - - case EMCNAND_PROGRAM: - /* NAND reports about page programming finish */ - emcnandp->state = EMCNAND_READY; - wakeup_isr(emcnandp); - break; - - default: - osalSysHalt("Unhandled case"); - break; - } - - osalSysUnlockFromISR(); -} -#endif /* STM32_EMC_USE_INT */ - -/** - * @brief DMA RX end IRQ handler. - * - * @param[in] emcnandp pointer to the @p EMCNANDDriver object - * @param[in] flags pre-shifted content of the ISR register - * - * @notapi - */ -static void emcnand_lld_serve_transfer_end_irq(EMCNANDDriver *emcnandp, - uint32_t flags) { - /* DMA errors handling.*/ -#if defined(STM32_EMCNAND_DMA_ERROR_HOOK) - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - STM32_EMCNAND_DMA_ERROR_HOOK(emcnandp); - } -#else - (void)flags; -#endif - - osalSysLockFromISR(); - - dmaStreamDisable(emcnandp->dma); - - switch (emcnandp->state){ - case EMCNAND_DMA_TX: - emcnandp->state = EMCNAND_PROGRAM; - emcnandp->map_cmd[0] = NAND_CMD_PAGEPROG; - /* thread will be woken from ready_isr() */ - break; - - case EMCNAND_DMA_RX: - emcnandp->state = EMCNAND_READY; - emcnandp->rxdata = NULL; - emcnandp->datalen = 0; - wakeup_isr(emcnandp); - break; - - default: - osalSysHalt("Unhandled case"); - break; - } - - osalSysUnlockFromISR(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level EMCNAND driver initialization. - * - * @notapi - */ -void emcnand_lld_init(void) { - -#if STM32_EMCNAND_USE_EMCNAND1 - /* Driver initialization.*/ - emcnandObjectInit(&EMCNANDD1); - EMCNANDD1.rxdata = NULL; - EMCNANDD1.datalen = 0; - EMCNANDD1.thread = NULL; - EMCNANDD1.dma = STM32_DMA_STREAM(STM32_EMCNAND_EMCNAND1_DMA_STREAM); - EMCNANDD1.nand = (FSMC_NAND_TypeDef *)FSMC_Bank2_R_BASE; - EMCNANDD1.map_data = (uint8_t*)FSMC_Bank2_MAP_COMMON_DATA; - EMCNANDD1.map_cmd = (uint8_t*)FSMC_Bank2_MAP_COMMON_CMD; - EMCNANDD1.map_addr = (uint8_t*)FSMC_Bank2_MAP_COMMON_ADDR; -#endif /* STM32_EMCNAND_USE_EMCNAND1 */ - -#if STM32_EMCNAND_USE_EMCNAND2 - /* Driver initialization.*/ - #warning "Untested" - emcnandObjectInit(&EMCNANDD1); - EMCNANDD2.rxdata = NULL; - EMCNANDD2.datalen = 0; - EMCNANDD2.thread = NULL; - EMCNANDD2.dma = STM32_DMA_STREAM(STM32_EMCNAND_EMCNAND2_DMA_STREAM); - EMCNANDD2.nand = (FSMC_NAND_TypeDef *)FSMC_Bank3_R_BASE; - EMCNANDD2.map_data = (uint8_t*)FSMC_Bank3_MAP_COMMON_DATA; - EMCNANDD2.map_cmd = (uint8_t*)FSMC_Bank3_MAP_COMMON_CMD; - EMCNANDD2.map_addr = (uint8_t*)FSMC_Bank3_MAP_COMMON_ADDR; -#endif /* STM32_EMCNAND_USE_EMCNAND2 */ -} - -/** - * @brief Configures and activates the EMCNAND peripheral. - * - * @param[in] emcnandp pointer to the @p EMCNANDDriver object - * - * @notapi - */ -void emcnand_lld_start(EMCNANDDriver *emcnandp) { - - bool_t b; - - if (emcnandp->state == EMCNAND_STOP) { - b = dmaStreamAllocate(emcnandp->dma, - STM32_EMC_FSMC1_IRQ_PRIORITY, - (stm32_dmaisr_t)emcnand_lld_serve_transfer_end_irq, - (void *)emcnandp); - osalDbgAssert(!b, "stream already allocated"); - emcnandp->dmamode = STM32_DMA_CR_CHSEL(EMCNAND_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_EMCNAND_EMCNAND1_DMA_PRIORITY) | - STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE | - STM32_DMA_CR_DMEIE | STM32_DMA_CR_TEIE | - STM32_DMA_CR_TCIE; - /* dmaStreamSetFIFO(emcnandp->dma, - STM32_DMA_FCR_DMDIS | EMCNAND_STM32_DMA_FCR_FTH_LVL); */ - emcnandp->nand->PCR = calc_eccps(emcnandp) | FSMC_PCR_PTYP | FSMC_PCR_PBKEN; - emcnandp->nand->PMEM = emcnandp->config->pmem; - emcnandp->nand->PATT = emcnandp->config->pmem; - emcnandp->isr_handler = emcnand_isr_handler; - emcnand_ready_isr_enable(emcnandp); - } -} - -/** - * @brief Deactivates the EMCNAND peripheral. - * - * @param[in] emcnandp pointer to the @p EMCNANDDriver object - * - * @notapi - */ -void emcnand_lld_stop(EMCNANDDriver *emcnandp) { - - if (emcnandp->state == EMCNAND_READY) { - dmaStreamRelease(emcnandp->dma); - emcnandp->nand->PCR &= ~FSMC_PCR_PBKEN; - emcnand_ready_isr_disable(emcnandp); - emcnandp->isr_handler = NULL; - } -} - -/** - * @brief Read data from NAND. - * - * @param[in] emcnandp pointer to the @p EMCNANDDriver object - * @param[out] data pointer to data buffer - * @param[in] datalen size of data buffer - * @param[in] addr pointer to address buffer - * @param[in] addrlen length of address - * @param[out] ecc pointer to store computed ECC. Ignored when NULL. - * - * @notapi - */ -void emcnand_lld_read_data(EMCNANDDriver *emcnandp, uint8_t *data, - size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc){ - - emcnandp->state = EMCNAND_READ; - emcnandp->rxdata = data; - emcnandp->datalen = datalen; - - emcnand_lld_write_cmd (emcnandp, NAND_CMD_READ0); - emcnand_lld_write_addr(emcnandp, addr, addrlen); - osalSysLock(); - emcnand_lld_write_cmd (emcnandp, NAND_CMD_READ0_CONFIRM); - - /* Here NAND asserts busy signal and starts transferring from memory - array to page buffer. After the end of transmission ready_isr functions - starts DMA transfer from page buffer to MCU's RAM.*/ - osalDbgAssert((emcnandp->nand->PCR & FSMC_PCR_ECCEN) == 0, - "State machine broken. ECCEN must be previously disabled."); - - if (NULL != ecc){ - emcnandp->nand->PCR |= FSMC_PCR_ECCEN; - } - - emcnand_lld_suspend_thread(emcnandp); - osalSysUnlock(); - - /* thread was woken up from DMA ISR */ - if (NULL != ecc){ - while (! (emcnandp->nand->SR & FSMC_SR_FEMPT)) - ; - *ecc = emcnandp->nand->ECCR; - emcnandp->nand->PCR &= ~FSMC_PCR_ECCEN; - } -} - -/** - * @brief Write data to NAND. - * - * @param[in] emcnandp pointer to the @p EMCNANDDriver object - * @param[in] data buffer with data to be written - * @param[in] datalen size of data buffer - * @param[in] addr pointer to address buffer - * @param[in] addrlen length of address - * @param[out] ecc pointer to store computed ECC. Ignored when NULL. - * - * @return The operation status reported by NAND IC (0x70 command). - * - * @notapi - */ -uint8_t emcnand_lld_write_data(EMCNANDDriver *emcnandp, const uint8_t *data, - size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc){ - - emcnandp->state = EMCNAND_WRITE; - - emcnand_lld_write_cmd (emcnandp, NAND_CMD_WRITE); - osalSysLock(); - emcnand_lld_write_addr(emcnandp, addr, addrlen); - - /* Now start DMA transfer to NAND buffer and put thread in sleep state. - Tread will we woken up from ready ISR. */ - emcnandp->state = EMCNAND_DMA_TX; - osalDbgAssert((emcnandp->nand->PCR & FSMC_PCR_ECCEN) == 0, - "State machine broken. ECCEN must be previously disabled."); - - if (NULL != ecc){ - emcnandp->nand->PCR |= FSMC_PCR_ECCEN; - } - - dmaStartMemCopy(emcnandp->dma, emcnandp->dmamode, - data, emcnandp->map_data, datalen); - - emcnand_lld_suspend_thread(emcnandp); - osalSysUnlock(); - - if (NULL != ecc){ - while (! (emcnandp->nand->SR & FSMC_SR_FEMPT)) - ; - *ecc = emcnandp->nand->ECCR; - emcnandp->nand->PCR &= ~FSMC_PCR_ECCEN; - } - - return emcnand_lld_read_status(emcnandp); -} - -/** - * @brief Erase block. - * - * @param[in] emcnandp pointer to the @p EMCNANDDriver object - * @param[in] addr pointer to address buffer - * @param[in] addrlen length of address - * - * @return The operation status reported by NAND IC (0x70 command). - * - * @notapi - */ -uint8_t emcnand_lld_erase(EMCNANDDriver *emcnandp, - uint8_t *addr, size_t addrlen){ - - emcnandp->state = EMCNAND_ERASE; - - emcnand_lld_write_cmd (emcnandp, NAND_CMD_ERASE); - emcnand_lld_write_addr(emcnandp, addr, addrlen); - osalSysLock(); - emcnand_lld_write_cmd (emcnandp, NAND_CMD_ERASE_CONFIRM); - emcnand_lld_suspend_thread(emcnandp); - osalSysUnlock(); - - return emcnand_lld_read_status(emcnandp); -} - -/** - * @brief Read data from NAND using polling approach. - * - * @detatils Use this function to read data when no waiting expected. For - * Example read status word after 0x70 command - * - * @param[in] emcnandp pointer to the @p EMCNANDDriver object - * @param[out] data pointer to output buffer - * @param[in] len length of data to be read - * - * @notapi - */ -void emcnand_lld_polled_read_data(EMCNANDDriver *emcnandp, - uint8_t *data, size_t len){ - size_t i = 0; - - for (i=0; i<len; i++) - data[i] = emcnandp->map_data[i]; -} - -/** - * @brief Send addres to NAND. - * - * @param[in] emcnandp pointer to the @p EMCNANDDriver object - * @param[in] len length of address array - * @param[in] addr pointer to address array - * - * @notapi - */ -void emcnand_lld_write_addr(EMCNANDDriver *emcnandp, - const uint8_t *addr, size_t len){ - size_t i = 0; - - for (i=0; i<len; i++) - emcnandp->map_addr[i] = addr[i]; -} - -/** - * @brief Send command to NAND. - * - * @param[in] emcnandp pointer to the @p EMCNANDDriver object - * @param[in] cmd command value - * - * @notapi - */ -void emcnand_lld_write_cmd(EMCNANDDriver *emcnandp, uint8_t cmd){ - emcnandp->map_cmd[0] = cmd; -} - -/** - * @brief Read status byte from NAND. - * - * @param[in] emcnandp pointer to the @p EMCNANDDriver object - * - * @return Status byte. - * - * @notapi - */ -uint8_t emcnand_lld_read_status(EMCNANDDriver *emcnandp) { - - uint8_t status[1] = {0x01}; /* presume worse */ - - emcnand_lld_write_cmd(emcnandp, NAND_CMD_STATUS); - emcnand_lld_polled_read_data(emcnandp, status, 1); - - return status[0]; -} - -#endif /* HAL_USE_EMCNAND */ - -/** @} */ - diff --git a/os/hal/ports/STM32/STM32F4xx/platform.mk b/os/hal/ports/STM32/STM32F4xx/platform.mk index 00dd5ccb4..a2f7e1257 100644 --- a/os/hal/ports/STM32/STM32F4xx/platform.mk +++ b/os/hal/ports/STM32/STM32F4xx/platform.mk @@ -21,8 +21,8 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \ ${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1/st_lld.c \
${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv1/serial_lld.c \
${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv1/uart_lld.c \
- ${CHIBIOS}/os/hal/ports/STM32/LLD/emc_lld.c \
- ${CHIBIOS}/os/hal/ports/STM32/LLD/emcnand_lld.c
+ ${CHIBIOS}/os/hal/ports/STM32/LLD/FSMCv1/fsmc.c \
+ ${CHIBIOS}/os/hal/ports/STM32/LLD/FSMCv1/nand_lld.c
# Required include directories
PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
@@ -35,4 +35,5 @@ PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \ ${CHIBIOS}/os/hal/ports/STM32/LLD/RTCv2 \
${CHIBIOS}/os/hal/ports/STM32/LLD/SPIv1 \
${CHIBIOS}/os/hal/ports/STM32/LLD/TIMv1 \
- ${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv1
+ ${CHIBIOS}/os/hal/ports/STM32/LLD/USARTv1 \
+ ${CHIBIOS}/os/hal/ports/STM32/LLD/FSMCv1
diff --git a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h index 816ae0353..8f2d9c442 100644 --- a/os/hal/ports/STM32/STM32F4xx/stm32_registry.h +++ b/os/hal/ports/STM32/STM32F4xx/stm32_registry.h @@ -327,16 +327,16 @@ #endif /* defined(STM32F401xx) */
/* EMC attributes.*/
-#define STM32_HAS_EMC TRUE
-#define STM32_EMC_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) | \
- STM32_DMA_STREAM_ID_MSK(2, 1) | \
- STM32_DMA_STREAM_ID_MSK(2, 2) | \
- STM32_DMA_STREAM_ID_MSK(2, 3) | \
- STM32_DMA_STREAM_ID_MSK(2, 4) | \
- STM32_DMA_STREAM_ID_MSK(2, 5) | \
- STM32_DMA_STREAM_ID_MSK(2, 6) | \
- STM32_DMA_STREAM_ID_MSK(2, 7))
-#define STM32_EMC_DMA_CHN 0x03010201
+#define STM32_HAS_FSMC TRUE
+#define STM32_FSMC_DMA_MSK (STM32_DMA_STREAM_ID_MSK(2, 0) |\
+ STM32_DMA_STREAM_ID_MSK(2, 1) |\
+ STM32_DMA_STREAM_ID_MSK(2, 2) |\
+ STM32_DMA_STREAM_ID_MSK(2, 3) |\
+ STM32_DMA_STREAM_ID_MSK(2, 4) |\
+ STM32_DMA_STREAM_ID_MSK(2, 5) |\
+ STM32_DMA_STREAM_ID_MSK(2, 6) |\
+ STM32_DMA_STREAM_ID_MSK(2, 7))
+#define STM32_FSMC_DMA_CHN 0x03010201
/** @} */
#endif /* _STM32_REGISTRY_H_ */
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