diff options
Diffstat (limited to 'os/hal/ports/STM32')
| -rw-r--r-- | os/hal/ports/STM32/STM32F3xx/hal_lld.h | 22 |
1 files changed, 11 insertions, 11 deletions
diff --git a/os/hal/ports/STM32/STM32F3xx/hal_lld.h b/os/hal/ports/STM32/STM32F3xx/hal_lld.h index 9cd53c61f..3b9db8474 100644 --- a/os/hal/ports/STM32/STM32F3xx/hal_lld.h +++ b/os/hal/ports/STM32/STM32F3xx/hal_lld.h @@ -905,7 +905,7 @@ /**
* @brief ADC34 frequency.
*/
-#if (STM32_ADC43PRES == STM32_ADC34PRES_NOCLOCK) || defined(__DOXYGEN__)
+#if (STM32_ADC34PRES == STM32_ADC34PRES_NOCLOCK) || defined(__DOXYGEN__)
#define STM32_ADC34CLK 0
#elif STM32_ADC34PRES == STM32_ADC34PRES_DIV1
#define STM32_ADC34CLK (STM32_PLLCLKOUT / 1)
@@ -974,9 +974,9 @@ #define STM32_USART1CLK STM32_PCLK2
#elif STM32_USART1SW == STM32_USART1SW_SYSCLK
#define STM32_USART1CLK STM32_SYSCLK
-#elif STM32_USART1SW == STM32_USART1SW_LSECLK
+#elif STM32_USART1SW == STM32_USART1SW_LSE
#define STM32_USART1CLK STM32_LSECLK
-#elif STM32_USART1SW == STM32_USART1SW_HSICLK
+#elif STM32_USART1SW == STM32_USART1SW_HSI
#define STM32_USART1CLK STM32_HSICLK
#else
#error "invalid source selected for USART1 clock"
@@ -989,9 +989,9 @@ #define STM32_USART2CLK STM32_PCLK1
#elif STM32_USART2SW == STM32_USART2SW_SYSCLK
#define STM32_USART2CLK STM32_SYSCLK
-#elif STM32_USART2SW == STM32_USART2SW_LSECLK
+#elif STM32_USART2SW == STM32_USART2SW_LSE
#define STM32_USART2CLK STM32_LSECLK
-#elif STM32_USART2SW == STM32_USART2SW_HSICLK
+#elif STM32_USART2SW == STM32_USART2SW_HSI
#define STM32_USART2CLK STM32_HSICLK
#else
#error "invalid source selected for USART2 clock"
@@ -1004,9 +1004,9 @@ #define STM32_USART3CLK STM32_PCLK1
#elif STM32_USART3SW == STM32_USART3SW_SYSCLK
#define STM32_USART3CLK STM32_SYSCLK
-#elif STM32_USART3SW == STM32_USART3SW_LSECLK
+#elif STM32_USART3SW == STM32_USART3SW_LSE
#define STM32_USART3CLK STM32_LSECLK
-#elif STM32_USART3SW == STM32_USART3SW_HSICLK
+#elif STM32_USART3SW == STM32_USART3SW_HSI
#define STM32_USART3CLK STM32_HSICLK
#else
#error "invalid source selected for USART3 clock"
@@ -1019,9 +1019,9 @@ #define STM32_UART4CLK STM32_PCLK1
#elif STM32_UART4SW == STM32_UART4SW_SYSCLK
#define STM32_UART4CLK STM32_SYSCLK
-#elif STM32_UART4SW == STM32_UART4SW_LSECLK
+#elif STM32_UART4SW == STM32_UART4SW_LSE
#define STM32_UART4CLK STM32_LSECLK
-#elif STM32_UART4SW == STM32_UART4SW_HSICLK
+#elif STM32_UART4SW == STM32_UART4SW_HSI
#define STM32_UART4CLK STM32_HSICLK
#else
#error "invalid source selected for UART4 clock"
@@ -1034,9 +1034,9 @@ #define STM32_UART5CLK STM32_PCLK1
#elif STM32_UART5SW == STM32_UART5SW_SYSCLK
#define STM32_UART5CLK STM32_SYSCLK
-#elif STM32_UART5SW == STM32_UART5SW_LSECLK
+#elif STM32_UART5SW == STM32_UART5SW_LSE
#define STM32_UART5CLK STM32_LSECLK
-#elif STM32_UART5SW == STM32_UART5SW_HSICLK
+#elif STM32_UART5SW == STM32_UART5SW_HSI
#define STM32_UART5CLK STM32_HSICLK
#else
#error "invalid source selected for UART5 clock"
|