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path: root/os/hal/ports/STM32/LLD/GPIOv3/hal_pal_lld.c
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Diffstat (limited to 'os/hal/ports/STM32/LLD/GPIOv3/hal_pal_lld.c')
-rw-r--r--os/hal/ports/STM32/LLD/GPIOv3/hal_pal_lld.c15
1 files changed, 8 insertions, 7 deletions
diff --git a/os/hal/ports/STM32/LLD/GPIOv3/hal_pal_lld.c b/os/hal/ports/STM32/LLD/GPIOv3/hal_pal_lld.c
index 65f76a609..018f85d7e 100644
--- a/os/hal/ports/STM32/LLD/GPIOv3/hal_pal_lld.c
+++ b/os/hal/ports/STM32/LLD/GPIOv3/hal_pal_lld.c
@@ -231,7 +231,7 @@ void _pal_lld_enablepadevent(ioportid_t port,
iopadid_t pad,
ioeventmode_t mode) {
- uint32_t padmask, cridx, crmask, portidx;
+ uint32_t padmask, cridx, croff, crmask, portidx;
/* Mask of the pad.*/
padmask = 1U << (uint32_t)pad;
@@ -244,14 +244,15 @@ void _pal_lld_enablepadevent(ioportid_t port,
/* Index and mask of the SYSCFG CR register to be used.*/
cridx = (uint32_t)pad >> 2U;
- crmask = ~(0xFU << (((uint32_t)pad & 3U) * 4U));
+ croff = ((uint32_t)pad & 3U) * 4U;
+ crmask = ~(0xFU << croff);
/* Port index is obtained assuming that GPIO ports are placed at regular
0x400 intervals in memory space. So far this is true for all devices.*/
- portidx = (uint32_t)port >> 10U;
+ portidx = ((uint32_t)port >> 10U) & 0xFU;
/* Port selection in SYSCFG.*/
- SYSCFG->EXTICR[cridx] = (SYSCFG->EXTICR[cridx] & crmask) | portidx;
+ SYSCFG->EXTICR[cridx] = (SYSCFG->EXTICR[cridx] & crmask) | (portidx << croff);
/* Programming edge registers.*/
if (mode & PAL_EVENT_MODE_RISING_EDGE)
@@ -280,8 +281,8 @@ void _pal_lld_enablepadevent(ioportid_t port,
void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) {
uint32_t padmask, rtsr1, ftsr1;
- rtsr1 = EXTI->RTSR1;
- ftsr1 = EXTI->FTSR1;
+ rtsr1 = EXTI->RTSR;
+ ftsr1 = EXTI->FTSR;
/* Mask of the pad.*/
padmask = 1U << (uint32_t)pad;
@@ -296,7 +297,7 @@ void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) {
/* Port index is obtained assuming that GPIO ports are placed at regular
0x400 intervals in memory space. So far this is true for all devices.*/
- portidx = (uint32_t)port >> 10U;
+ portidx = ((uint32_t)port >> 10U) & 0xFU;
crport = (SYSCFG->EXTICR[cridx] >> croff) & 0xFU;