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-rw-r--r--os/hal/platforms/STM32F0xx/hal_lld.c2
-rw-r--r--os/hal/platforms/STM32F3xx/hal_lld.c6
2 files changed, 6 insertions, 2 deletions
diff --git a/os/hal/platforms/STM32F0xx/hal_lld.c b/os/hal/platforms/STM32F0xx/hal_lld.c
index 7c76cb272..a8b73fd88 100644
--- a/os/hal/platforms/STM32F0xx/hal_lld.c
+++ b/os/hal/platforms/STM32F0xx/hal_lld.c
@@ -114,7 +114,7 @@ void hal_lld_init(void) {
SysTick_CTRL_ENABLE_Msk |
SysTick_CTRL_TICKINT_Msk;
- /* PWR and BD clocks enabled.*/
+ /* PWR clock enabled.*/
rccEnablePWRInterface(FALSE);
/* Initializes the backup domain.*/
diff --git a/os/hal/platforms/STM32F3xx/hal_lld.c b/os/hal/platforms/STM32F3xx/hal_lld.c
index afd6ec354..c0d9ad436 100644
--- a/os/hal/platforms/STM32F3xx/hal_lld.c
+++ b/os/hal/platforms/STM32F3xx/hal_lld.c
@@ -114,7 +114,11 @@ void hal_lld_init(void) {
SysTick_CTRL_ENABLE_Msk |
SysTick_CTRL_TICKINT_Msk;
- /* PWR and BD clocks enabled.*/
+ /* DWT cycle counter enable.*/
+ SCS_DEMCR |= SCS_DEMCR_TRCENA;
+ DWT_CTRL |= DWT_CTRL_CYCCNTENA;
+
+ /* PWR clock enabled.*/
rccEnablePWRInterface(FALSE);
/* Initializes the backup domain.*/