diff options
Diffstat (limited to 'os/hal/platforms/STM32L1xx')
-rw-r--r-- | os/hal/platforms/STM32L1xx/hal_lld.c | 6 | ||||
-rw-r--r-- | os/hal/platforms/STM32L1xx/hal_lld.h | 24 | ||||
-rw-r--r-- | os/hal/platforms/STM32L1xx/stm32_rcc.h | 32 |
3 files changed, 62 insertions, 0 deletions
diff --git a/os/hal/platforms/STM32L1xx/hal_lld.c b/os/hal/platforms/STM32L1xx/hal_lld.c index 54d67b9d0..69619dead 100644 --- a/os/hal/platforms/STM32L1xx/hal_lld.c +++ b/os/hal/platforms/STM32L1xx/hal_lld.c @@ -74,6 +74,12 @@ void hal_lld_init(void) { #if defined(STM32_DMA_REQUIRED)
dmaInit();
#endif
+
+ /* Programmable voltage detector enable. */
+#if STM32_PVD_ENABLE
+ rccEnablePWRInterface(FALSE);
+ PWR->CR |= PWR_CR_PVDE | (STM32_PLS & STM32_PLS_MASK);
+#endif /* STM32_PVD_ENABLE */
}
/**
diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h index 4bbe2fe76..c11c9ccd8 100644 --- a/os/hal/platforms/STM32L1xx/hal_lld.h +++ b/os/hal/platforms/STM32L1xx/hal_lld.h @@ -66,6 +66,16 @@ #define STM32_VOS_1P8 (1 << 11) /**< Core voltage 1.8 Volts. */
#define STM32_VOS_1P5 (2 << 11) /**< Core voltage 1.5 Volts. */
#define STM32_VOS_1P2 (3 << 11) /**< Core voltage 1.2 Volts. */
+
+#define STM32_PLS_MASK (7 << 5) /**< PLS bits mask. */
+#define STM32_PLS_LEV0 (0 << 5) /**< PVD level 0. */
+#define STM32_PLS_LEV1 (1 << 5) /**< PVD level 0. */
+#define STM32_PLS_LEV2 (2 << 5) /**< PVD level 0. */
+#define STM32_PLS_LEV3 (3 << 5) /**< PVD level 0. */
+#define STM32_PLS_LEV4 (4 << 5) /**< PVD level 0. */
+#define STM32_PLS_LEV5 (5 << 5) /**< PVD level 0. */
+#define STM32_PLS_LEV6 (6 << 5) /**< PVD level 0. */
+#define STM32_PLS_LEV7 (7 << 5) /**< PVD level 0. */
/** @} */
/**
@@ -387,6 +397,20 @@ #endif
/**
+ * @brief Enables or disables the programmable voltage detector.
+ */
+#if !defined(STM32_PVD_ENABLE) || defined(__DOXYGEN__)
+#define STM32_PVD_ENABLE FALSE
+#endif
+
+/**
+ * @brief Sets voltage level for programmable voltage detector.
+ */
+#if !defined(STM32_PLS) || defined(__DOXYGEN__)
+#define STM32_PLS STM32_PLS_LEV0
+#endif
+
+/**
* @brief Enables or disables the HSI clock source.
*/
#if !defined(STM32_HSI_ENABLED) || defined(__DOXYGEN__)
diff --git a/os/hal/platforms/STM32L1xx/stm32_rcc.h b/os/hal/platforms/STM32L1xx/stm32_rcc.h index 9ffcc07b4..9068adc5a 100644 --- a/os/hal/platforms/STM32L1xx/stm32_rcc.h +++ b/os/hal/platforms/STM32L1xx/stm32_rcc.h @@ -237,6 +237,38 @@ /** @} */
/**
+ * @brief PWR interface specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the PWR interface clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnablePWRInterface(lp) rccEnableAPB1(RCC_APB1ENR_PWREN, lp)
+
+/**
+ * @brief Disables PWR interface clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisablePWRInterface(lp) rccDisableAPB1(RCC_APB1ENR_BKPEN, lp)
+
+/**
+ * @brief Resets the PWR interface.
+ *
+ * @api
+ */
+#define rccResetPWRInterface() rccResetAPB1(RCC_APB1ENR_BKPRST)
+/** @} */
+
+/**
* @brief I2C peripherals specific RCC operations
* @{
*/
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