diff options
Diffstat (limited to 'os/hal/platforms/STM32L1xx')
| -rw-r--r-- | os/hal/platforms/STM32L1xx/hal_lld.h | 10 | ||||
| -rw-r--r-- | os/hal/platforms/STM32L1xx/platform.dox | 2 | ||||
| -rw-r--r-- | os/hal/platforms/STM32L1xx/stm32_dma.c | 2 | ||||
| -rw-r--r-- | os/hal/platforms/STM32L1xx/stm32l1xx.h | 8 |
4 files changed, 11 insertions, 11 deletions
diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h index f7402dfe6..38f910f2d 100644 --- a/os/hal/platforms/STM32L1xx/hal_lld.h +++ b/os/hal/platforms/STM32L1xx/hal_lld.h @@ -149,10 +149,10 @@ * @{
*/
#define STM32_MSIRANGE_MASK (7 << 13) /**< MSIRANGE field mask. */
-#define STM32_MSIRANGE_64K (0 << 13) /**< 64KHz nominal. */
-#define STM32_MSIRANGE_128K (1 << 13) /**< 128KHz nominal. */
-#define STM32_MSIRANGE_256K (2 << 13) /**< 256KHz nominal. */
-#define STM32_MSIRANGE_512K (3 << 13) /**< 512KHz nominal. */
+#define STM32_MSIRANGE_64K (0 << 13) /**< 64kHz nominal. */
+#define STM32_MSIRANGE_128K (1 << 13) /**< 128kHz nominal. */
+#define STM32_MSIRANGE_256K (2 << 13) /**< 256kHz nominal. */
+#define STM32_MSIRANGE_512K (3 << 13) /**< 512kHz nominal. */
#define STM32_MSIRANGE_1M (4 << 13) /**< 1MHz nominal. */
#define STM32_MSIRANGE_2M (5 << 13) /**< 2MHz nominal. */
#define STM32_MSIRANGE_4M (6 << 13) /**< 4MHz nominal */
@@ -678,7 +678,7 @@ #error "impossible to activate LSE"
#endif
#if (STM32_LSECLK < 1000) || (STM32_LSECLK > 1000000)
-#error "STM32_LSECLK outside acceptable range (1...1000KHz)"
+#error "STM32_LSECLK outside acceptable range (1...1000kHz)"
#endif
#else /* !STM32_LSE_ENABLED */
#if STM_RTCCLK == STM32_LSECLK
diff --git a/os/hal/platforms/STM32L1xx/platform.dox b/os/hal/platforms/STM32L1xx/platform.dox index 744f1b673..fe845811e 100644 --- a/os/hal/platforms/STM32L1xx/platform.dox +++ b/os/hal/platforms/STM32L1xx/platform.dox @@ -305,7 +305,7 @@ * @section stm32l1xx_rcc_2 STM32L1xx RCC driver implementation features
* - Peripherals reset.
* - Peripherals clock enable.
- * - Periplerals clock disable.
+ * - Peripherals clock disable.
* .
* @ingroup STM32L1xx_PLATFORM_DRIVERS
*/
diff --git a/os/hal/platforms/STM32L1xx/stm32_dma.c b/os/hal/platforms/STM32L1xx/stm32_dma.c index 85841ad9f..0e6d52404 100644 --- a/os/hal/platforms/STM32L1xx/stm32_dma.c +++ b/os/hal/platforms/STM32L1xx/stm32_dma.c @@ -29,7 +29,7 @@ * drivers to coordinate the access to the resource.
* @note The DMA ISR handlers are all declared into this module because
* sharing, the various device drivers can associate a callback to
- * IRSs when allocating streams.
+ * ISRs when allocating streams.
* @{
*/
diff --git a/os/hal/platforms/STM32L1xx/stm32l1xx.h b/os/hal/platforms/STM32L1xx/stm32l1xx.h index 9c665d29b..0870e768e 100644 --- a/os/hal/platforms/STM32L1xx/stm32l1xx.h +++ b/os/hal/platforms/STM32L1xx/stm32l1xx.h @@ -2602,10 +2602,10 @@ typedef struct #define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00) /*!< Internal High Speed clock trimming */
#define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000) /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000) /*!< Internal Multi Speed clock Range 65.536 KHz */
-#define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000) /*!< Internal Multi Speed clock Range 131.072 KHz */
-#define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000) /*!< Internal Multi Speed clock Range 262.144 KHz */
-#define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000) /*!< Internal Multi Speed clock Range 524.288 KHz */
+#define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000) /*!< Internal Multi Speed clock Range 65.536 kHz */
+#define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000) /*!< Internal Multi Speed clock Range 131.072 kHz */
+#define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000) /*!< Internal Multi Speed clock Range 262.144 kHz */
+#define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000) /*!< Internal Multi Speed clock Range 524.288 kHz */
#define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000) /*!< Internal Multi Speed clock Range 1.048 MHz */
#define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000) /*!< Internal Multi Speed clock Range 2.097 MHz */
#define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000) /*!< Internal Multi Speed clock Range 4.194 MHz */
|