3 files changed, 29 insertions, 16 deletions
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG.ld
index f955bd899..81fb0fb89 100644
--- a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG.ld
+++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG.ld
@@ -49,7 +49,10 @@ REGION_ALIAS("DATA_RAM", ram0);
 /* RAM region to be used for BSS segment.*/
 REGION_ALIAS("BSS_RAM", ram0);
 
-/* RAM region to be used for DMA segment.*/
-REGION_ALIAS("DMA_RAM", ram0);
+/* RAM region to be used for NOCACHE segment.*/
+REGION_ALIAS("NOCACHE_RAM", ram3);
+
+/* RAM region to be used for ETH segment.*/
+REGION_ALIAS("ETH_RAM", ram3);
 
 INCLUDE ld/rules_STM32F7xx.ld
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG_DMA.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG_DMA.ld
index 7abc1787e..a8e0626d2 100644
--- a/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG_DMA.ld
+++ b/os/common/ports/ARMCMx/compilers/GCC/ld/STM32F746xG_DMA.ld
@@ -48,7 +48,10 @@ REGION_ALIAS("DATA_RAM", ram1);
 /* RAM region to be used for BSS segment.*/
 REGION_ALIAS("BSS_RAM", ram1);
 
-/* RAM region to be used for DMA segment.*/
-REGION_ALIAS("DMA_RAM", ram2);
+/* RAM region to be used for NOCACHE segment.*/
+REGION_ALIAS("NOCACHE_RAM", ram3);
+
+/* RAM region to be used for ETH segment.*/
+REGION_ALIAS("ETH_RAM", ram2);
 
 INCLUDE rules_dma.ld
diff --git a/os/common/ports/ARMCMx/compilers/GCC/ld/rules_STM32F7xx.ld b/os/common/ports/ARMCMx/compilers/GCC/ld/rules_STM32F7xx.ld
index 93ed8af3a..39aad4419 100644
--- a/os/common/ports/ARMCMx/compilers/GCC/ld/rules_STM32F7xx.ld
+++ b/os/common/ports/ARMCMx/compilers/GCC/ld/rules_STM32F7xx.ld
@@ -109,20 +109,27 @@ SECTIONS
     _etext = .;
     _textdata = _etext;
 
-    /* Special section for DMA-accessible areas, it is desirable to have a
-       separate section of DMA-accessible areas for several reasons:
-       - On devices with cache, the whole region can be declared not cacheable
-         removing issues with cache consistency.
-       - DMA-accessible areas can be placed on a dedicated SRAM bank for
-         improved concurrent accesses.*/
-    .dma (NOLOAD) : ALIGN(4)
+    /* Special section for non cache-able areas.*/
+    .nocache (NOLOAD) : ALIGN(4)
     {
-        *(.dma)
-        *(.dma.*)
-        *(.bss.__dma_*)
+        __nocache_start__ = .;
+        *(.nocache)
+        *(.nocache.*)
+        *(.bss.__nocache_*)
         . = ALIGN(4);
-        __dma_free__ = .;
-    } > DMA_RAM
+        __nocache_end__ = .;
+    } > NOCACHE_RAM
+
+    /* Special section for Ethernet DMA non cache-able areas.*/
+    .ethram (NOLOAD) : ALIGN(4)
+    {
+        __ethram_start__ = .;
+        *(.ethram)
+        *(.ethram.*)
+        *(.bss.__ethram_*)
+        . = ALIGN(4);
+        __ethram_end__ = .;
+    } > ETH_RAM
 
     .mstack :
     {