diff options
Diffstat (limited to 'os/common/startup')
| -rw-r--r-- | os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S | 17 | ||||
| -rw-r--r-- | os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S | 16 | 
2 files changed, 33 insertions, 0 deletions
| diff --git a/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S b/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S index b313b611a..643783bc8 100644 --- a/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S +++ b/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S @@ -39,11 +39,22 @@  #define CONTROL_USE_MSP                     0
  #define CONTROL_USE_PSP                     2
 +#define SCB_VTOR                            0xE000ED08
 +
  /*===========================================================================*/
  /* Module pre-compile time settings.                                         */
  /*===========================================================================*/
  /**
 + * @brief   VTOR special register initialization.
 + * @details VTOR is initialized to point to the vectors table.
 + * @note    This option can only be enabled on Cortex-M0+ cores.
 + */
 +#if !defined(CRT0_VTOR_INIT) || defined(__DOXYGEN__)
 +#define CRT0_VTOR_INIT                      FALSE
 +#endif
 +
 +/**
   * @brief   Control special register initialization value.
   * @details The system is setup to run in privileged mode using the PSP
   *          stack (dual stack mode).
 @@ -140,6 +151,12 @@ Reset_Handler:                  msr     CONTROL, r0
                  isb
 +#if CRT0_VTOR_INIT == TRUE
 +                ldr     r0, =_vectors
 +                ldr     r1, =SCB_VTOR
 +                str     r0, [r1]
 +#endif
 +
  #if CRT0_INIT_CORE == TRUE
                  /* Core initialization.*/
                  bl      __core_init
 diff --git a/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S b/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S index 5f9668efb..3abfc1813 100644 --- a/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S +++ b/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S @@ -43,6 +43,7 @@  #define FPCCR_ASPEN                         (1 << 31)
  #define FPCCR_LSPEN                         (1 << 30)
 +#define SCB_VTOR                            0xE000ED08
  #define SCB_CPACR                           0xE000ED88
  #define SCB_FPCCR                           0xE000EF34
  #define SCB_FPDSCR                          0xE000EF3C
 @@ -52,6 +53,14 @@  /*===========================================================================*/
  /**
 + * @brief   VTOR special register initialization.
 + * @details VTOR is initialized to point to the vectors table.
 + */
 +#if !defined(CRT0_VTOR_INIT) || defined(__DOXYGEN__)
 +#define CRT0_VTOR_INIT                      TRUE
 +#endif
 +
 +/**
   * @brief   FPU initialization switch.
   */
  #if !defined(CRT0_INIT_FPU) || defined(__DOXYGEN__)
 @@ -175,6 +184,13 @@ Reset_Handler:                  ldr     r0, =__process_stack_end__
                  msr     PSP, r0
 +#if CRT0_VTOR_INIT == TRUE
 +                ldr     r0, =_vectors
 +                movw    r1, #SCB_VTOR & 0xFFFF
 +                movt    r1, #SCB_VTOR >> 16
 +                str     r0, [r1]
 +#endif
 +
  #if CRT0_INIT_FPU == TRUE
                  /* FPU FPCCR initialization.*/
                  movw    r0, #CRT0_FPCCR_INIT & 0xFFFF
 | 
