diff options
Diffstat (limited to 'os/common/startup/ARMCMx/compilers/GCC/ld/STM32F746xG.ld')
| -rw-r--r-- | os/common/startup/ARMCMx/compilers/GCC/ld/STM32F746xG.ld | 93 |
1 files changed, 81 insertions, 12 deletions
diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F746xG.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F746xG.ld index e10c6ce63..7e847b969 100644 --- a/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F746xG.ld +++ b/os/common/startup/ARMCMx/compilers/GCC/ld/STM32F746xG.ld @@ -25,20 +25,52 @@ */
MEMORY
{
- flash : org = 0x08000000, len = 1M
- flash_itcm : org = 0x00200000, len = 1M
- ram0 : org = 0x20010000, len = 256k /* SRAM1 + SRAM2 */
- ram1 : org = 0x20010000, len = 240k /* SRAM1 */
- ram2 : org = 0x2004C000, len = 16k /* SRAM2 */
- ram3 : org = 0x20000000, len = 64k /* DTCM-RAM */
- ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */
- ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */
- ram6 : org = 0x00000000, len = 0
- ram7 : org = 0x00000000, len = 0
+ flash0 : org = 0x08000000, len = 1M /* Flash as AXIM (writable) */
+ flash1 : org = 0x00200000, len = 1M /* Flash as ITCM */
+ flash2 : org = 0x00000000, len = 0
+ flash3 : org = 0x00000000, len = 0
+ flash4 : org = 0x00000000, len = 0
+ flash5 : org = 0x00000000, len = 0
+ flash6 : org = 0x00000000, len = 0
+ flash7 : org = 0x00000000, len = 0
+ ram0 : org = 0x20010000, len = 256k /* SRAM1 + SRAM2 */
+ ram1 : org = 0x20010000, len = 240k /* SRAM1 */
+ ram2 : org = 0x2004C000, len = 16k /* SRAM2 */
+ ram3 : org = 0x20000000, len = 64k /* DTCM-RAM */
+ ram4 : org = 0x00000000, len = 16k /* ITCM-RAM */
+ ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */
+ ram6 : org = 0x00000000, len = 0
+ ram7 : org = 0x00000000, len = 0
}
+/* For each data/text section two region are defined, a virtual region
+ and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash1);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash1);
+REGION_ALIAS("XTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash1);
+REGION_ALIAS("TEXT_FLASH_LMA", flash0);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash0);
+REGION_ALIAS("RODATA_FLASH_LMA", flash0);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash1);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
+
/* RAM region to be used for Main stack. This stack accommodates the processing
- of all exceptions and interrupts*/
+ of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram3);
/* RAM region to be used for the process stack. This is the stack used by
@@ -47,6 +79,7 @@ REGION_ALIAS("PROCESS_STACK_RAM", ram3); /* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash0);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram3);
@@ -54,10 +87,46 @@ REGION_ALIAS("BSS_RAM", ram3); /* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);
+/* Stack rules inclusion.*/
+INCLUDE rules_stacks.ld
+
+/*===========================================================================*/
+/* Custom sections for STM32F7xx. */
+/*===========================================================================*/
+
/* RAM region to be used for nocache segment.*/
REGION_ALIAS("NOCACHE_RAM", ram3);
/* RAM region to be used for eth segment.*/
REGION_ALIAS("ETH_RAM", ram3);
-INCLUDE ld/rules_STM32F7xx.ld
+SECTIONS
+{
+ /* Special section for non cache-able areas.*/
+ .nocache (NOLOAD) : ALIGN(4)
+ {
+ __nocache_base__ = .;
+ *(.nocache)
+ *(.nocache.*)
+ *(.bss.__nocache_*)
+ . = ALIGN(4);
+ __nocache_end__ = .;
+ } > NOCACHE_RAM
+
+ /* Special section for Ethernet DMA non cache-able areas.*/
+ .eth (NOLOAD) : ALIGN(4)
+ {
+ __eth_base__ = .;
+ *(.eth)
+ *(.eth.*)
+ *(.bss.__eth_*)
+ . = ALIGN(4);
+ __eth_end__ = .;
+ } > ETH_RAM
+}
+
+/* Code rules inclusion.*/
+INCLUDE rules_code.ld
+
+/* Data rules inclusion.*/
+INCLUDE rules_data.ld
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