1 files changed, 188 insertions, 0 deletions
diff --git a/demos/SPC5/RT-SPC56EL-EVB/UDE/stm_xpc56el_minimodule_lockstep_debug_jtag.cfg b/demos/SPC5/RT-SPC56EL-EVB/UDE/stm_xpc56el_minimodule_lockstep_debug_jtag.cfg
new file mode 100644
index 000000000..87117b43f
--- /dev/null
+++ b/demos/SPC5/RT-SPC56EL-EVB/UDE/stm_xpc56el_minimodule_lockstep_debug_jtag.cfg
@@ -0,0 +1,188 @@
+[Main]
+Signature=UDE_TARGINFO_2.0
+Description=STM XPC56XL Mini Module with SPC56EL60, Lockstep mode (Jtag)
+Description1=MMU preinitialized, memory mapping 1:1, VLE enabled
+Description2=FLASH programming prepared but not enabled
+Description2=PLL init sequence for 80MHz
+Description3=Write Filter for BAM Module
+MCUs=Controller0
+Architecture=PowerPC
+Vendor=STM
+Board=XPC56XL Mini Module
+
+[Controller0]
+Family=PowerPC
+Type=SPC56EL60
+Enabled=1
+IntClock=80000
+MemDevs=BAMWriteFilter
+ExtClock=40000
+
+[Controller0.Core]
+Protocol=PPCJTAG
+Enabled=1
+ExecuteOpcodeAddr=0x00000000
+
+[Controller0.Core.LoadedAddOn]
+UDEMemtool=1
+
+[Controller0.Core.PpcJtagTargIntf]
+PortType=FTDI
+ResetWaitTime=50
+MaxJtagClk=5000
+DoSramInit=1
+UseNexus=1
+AdaptiveJtagPhaseShift=1
+ConnOption=Reset
+ChangeJtagClk=-1
+HaltAfterReset=1
+SimioAddr=g_JtagSimioAccess
+FreezeTimers=1
+InvalidTlbOnReset=1
+InvalidateCache=1
+ForceCacheFlush=1
+IgnoreLockedLines=0
+ExecInitCmds=1
+JtagTapNumber=0
+JtagNumOfTaps=1
+JtagNumIrBefore=0
+JtagNumIrAfter=0
+SimioAddr=g_JtagSimioAccess
+FlushCache=0
+AllowMmuSetup=0
+UseExtReset=0
+HandleWdtBug=0
+ForceEndOfReset=0
+JtagViaPod=1
+AllowResetOnCheck=0
+TargetPort=Default
+ChangeMsr=0
+ChangeMsrValue=0x0
+ExecOnStartCmds=0
+ExecOnHaltCmds=0
+EnableProgramTimeMeasurement=0
+UseHwResetMode=1
+CommDevSel=PortType=USB,Type=FTDI
+HandleNexusAccessBug=0
+DoNotEnableTrapSwBrp=0
+BootPasswd0=0xFEEDFACE
+BootPasswd1=0xCAFEBEEF
+BootPasswd2=0xFFFFFFFF
+BootPasswd3=0xFFFFFFFF
+BootPasswd4=0xFFFFFFFF
+BootPasswd5=0xFFFFFFFF
+BootPasswd6=0xFFFFFFFF
+BootPasswd7=0xFFFFFFFF
+JtagIoType=Jtag
+ExecOnHaltCmdsWhileHalted=0
+TimerForPTM=Default
+AllowBreakOnUpdateBreakpoints=0
+ClearDebugStatusOnHalt=1
+HwResetMode=Simulate
+UseMasterNexusIfResetState=1
+UseLocalAddressTranslation=1
+Use64BitNexus=0
+InitSramOnlyWhenNotInitialized=0
+DisableE2EECC=0
+AllowHarrForUpdateDebugRegs=0
+UseCore0ForNexusMemoryAccessWhileRunning=0
+
+[Controller0.BAMWriteFilter]
+Description=BAM WriteAccess Filter
+Range0Start=0xFFFFC000
+Range0Size=0x4000
+Enabled=1
+Handler=AccessFilter
+Mode=ReadOnly
+
+[Controller0.PFLASH]
+Enabled=1
+EnableMemtoolByDefault=1
+
+[Controller0.Core.PpcJtagTargIntf.InitScript]
+// disable watchdog
+SET SWT_SR 0xC520
+SET SWT_SR 0xD928
+SET SWT_CR 0xFF00000A
+
+// select TLB 1
+SETSPR 0x274 0x10000108 0xFFFFFFFF
+
+// programm internal flash
+// TLB 1, entry 0
+SETSPR 0x270 0x10000000 0xFFFFFFFF
+// Valid, protect against invalidation, global entry, size=16MB
+SETSPR 0x271 0xC0000700 0xFFFFFFFF
+// effective page number 00000000, I,G
+SETSPR 0x272 0x00000028 0xFFFFFFFF
+// real page 00000000, UX,SX,UW,SW,UR,SR
+SETSPR 0x273 0x0000003F 0xFFFFFFFF
+// execute TLB write instruction
+EXECOPCODE 0x7C0007A4
+
+// programm internal SRAM
+// TLB 1, entry 1
+SETSPR 0x270 0x10010000 0xFFFFFFFF
+// Valid, protect against invalidation, global entry, size=16MB
+SETSPR 0x271 0xC0000700 0xFFFFFFFF
+// effective page number 40000000 I,G
+SETSPR 0x272 0x40000028 0xFFFFFFFF
+// real page 40000000, UX,SX,UW,SW,UR,SR
+SETSPR 0x273 0x4000003F 0xFFFFFFFF
+// execute TLB write instruction
+EXECOPCODE 0x7C0007A4
+
+// programm On plattform 1 peripherals
+// TLB 1, entry 2
+SETSPR 0x270 0x10020000 0xFFFFFFFF
+// Valid, protect against invalidation, global entry, size=1MB
+SETSPR 0x271 0xC0000500 0xFFFFFFFF
+// effective page number 8FF00000, I,G
+SETSPR 0x272 0x8FF00008 0xFFFFFFFF
+// real page 8FF00000, UX,SX,UW,SW,UR,SR
+SETSPR 0x273 0x8FF0003F 0xFFFFFFFF
+// execute TLB write instruction
+EXECOPCODE 0x7C0007A4
+
+// programm peripheral A modules
+// TLB 1, entry 3
+SETSPR 0x270 0x10030000 0xFFFFFFFF
+// Valid, protect against invalidation, global entry, size=1MB
+SETSPR 0x271 0xC0000500 0xFFFFFFFF
+// effective page number C3F00000, I
+SETSPR 0x272 0xC3F0000A 0xFFFFFFFF
+// real page C3F00000, UX,SX,UW,SW,UR,SR
+SETSPR 0x273 0xC3F0003F 0xFFFFFFFF
+// execute TLB write instruction
+EXECOPCODE 0x7C0007A4
+
+// programm Off plattform peripherals
+// TLB 1, entry 4
+SETSPR 0x270 0x10040000 0xFFFFFFFF
+// Valid, protect against invalidation, global entry, size=1MB
+SETSPR 0x271 0xC0000500 0xFFFFFFFF
+// effective page number FFE00000, I
+SETSPR 0x272 0xFFE00008 0xFFFFFFFF
+// real page FFE00000, UX,SX,UW,SW,UR,SR
+SETSPR 0x273 0xFFE0003F 0xFFFFFFFF
+// execute TLB write instruction
+EXECOPCODE 0x7C0007A4
+
+// programm On plattform 0 peripherals
+// TLB 1, entry 5
+SETSPR 0x270 0x10050000 0xFFFFFFFF
+// Valid, protect against invalidation, global entry, size=1MB
+SETSPR 0x271 0xC0000500 0xFFFFFFFF
+// effective page number FFF00000, I
+SETSPR 0x272 0xFFF00028 0xFFFFFFFF
+// real page FFF00000, UX,SX,UW,SW,UR,SR
+SETSPR 0x273 0xFFF0003F 0xFFFFFFFF
+// execute TLB write instruction
+EXECOPCODE 0x7C0007A4
+
+// clear fault status
+SET16 RGM_FES 0xFFFF
+[Controller0.Core.PpcJtagTargIntf.OnStartScript]
+
+[Controller0.Core.PpcJtagTargIntf.OnHaltScript]
+