1 files changed, 290 insertions, 0 deletions
diff --git a/demos/SPC5/RT-SPC56EC-EVB/UDE/stm_spc56ec74a256s_spc56ec74_minimodule_debug_jtag.cfg b/demos/SPC5/RT-SPC56EC-EVB/UDE/stm_spc56ec74a256s_spc56ec74_minimodule_debug_jtag.cfg
new file mode 100644
index 000000000..efb0181f4
--- /dev/null
+++ b/demos/SPC5/RT-SPC56EC-EVB/UDE/stm_spc56ec74a256s_spc56ec74_minimodule_debug_jtag.cfg
@@ -0,0 +1,290 @@
+[Main]
+Signature=UDE_TARGINFO_2.0
+Description=STM SPC56EC74A256S Mini Module with Dual Core SPC56EC74 (Jtag)
+Description1=MMU preinitialized, memory mapping 1:1, VLE enabled for SRAM and Flash
+Description2=PLL set for 120MHz
+Description3=FLASH programming prepared but not enabled
+Description4=Write Filter for BAM Module
+MCUs=Controller0
+Architecture=PowerPC
+Vendor=STM
+Board=SPC56EC74A256S Mini Module
+
+[Controller0]
+Family=PowerPC
+Type=SPC56EC74
+Enabled=1
+IntClock=120000
+MemDevs=BAMWriteFilter
+ExtClock=40000
+
+[Controller0.Core0]
+Protocol=PPCJTAG
+Enabled=1
+
+[Controller0.Core1]
+Protocol=PPCJTAG
+Enabled=1
+
+[Controller0.BAMWriteFilter]
+Description=BAM WriteAccess Filter
+Range0Start=0xFFFFC000
+Range0Size=0x4000
+Enabled=1
+Handler=AccessFilter
+Mode=ReadOnly
+
+[Controller0.PFLASH]
+Enabled=1
+EnableMemtoolByDefault=1
+
+[Controller0.PFLASH1]
+Enabled=1
+EnableMemtoolByDefault=1
+
+[Controller0.DFLASH]
+Enabled=1
+EnableMemtoolByDefault=1
+
+[Controller0.SHADOWFLASH]
+Enabled=1
+EnableMemtoolByDefault=0
+
+[Controller0.Core0.LoadedAddOn]
+UDEMemtool=1
+
+[Controller0.Core0.PpcJtagTargIntf]
+PortType=FTDI
+ResetWaitTime=500
+MaxJtagClk=5000
+DoSramInit=1
+UseNexus=1
+AdaptiveJtagPhaseShift=1
+ConnOption=Default
+ChangeJtagClk=-1
+HaltAfterReset=1
+SimioAddr=g_JtagSimioAccess
+FreezeTimers=1
+InvalidTlbOnReset=1
+InvalidateCache=1
+ForceCacheFlush=1
+IgnoreLockedLines=0
+ExecInitCmds=1
+JtagTapNumber=0
+JtagNumOfTaps=1
+JtagNumIrBefore=0
+JtagNumIrAfter=0
+SimioAddr=g_JtagSimioAccess
+FlushCache=0
+AllowMmuSetup=1
+UseExtReset=1
+HandleWdtBug=0
+ForceEndOfReset=0
+JtagViaPod=0
+AllowResetOnCheck=0
+ChangeMsr=0
+ChangeMsrValue=0x0
+ExecOnStartCmds=0
+ExecOnHaltCmds=0
+EnableProgramTimeMeasurement=0
+UseHwResetMode=0
+TargetPort=Default
+HandleNexusAccessBug=0
+DoNotEnableTrapSwBrp=0
+BootPasswd0=0xFEEDFACE
+BootPasswd1=0xCAFEBEEF
+BootPasswd2=0xFFFFFFFF
+BootPasswd3=0xFFFFFFFF
+BootPasswd4=0xFFFFFFFF
+BootPasswd5=0xFFFFFFFF
+BootPasswd6=0xFFFFFFFF
+BootPasswd7=0xFFFFFFFF
+CommDevSel=PortType=USB,Type=FTDI
+JtagIoType=Jtag
+ExecOnHaltCmdsWhileHalted=0
+TimerForPTM=Default
+AllowBreakOnUpdateBreakpoints=0
+ClearDebugStatusOnHalt=1
+HwResetMode=Simulate
+UseMasterNexusIfResetState=1
+UseLocalAddressTranslation=1
+Use64BitNexus=0
+InitSramOnlyWhenNotInitialized=0
+AllowHarrForUpdateDebugRegs=0
+DisableE2EECC=0
+UseCore0ForNexusMemoryAccessWhileRunning=0
+
+[Controller0.Core0.PpcJtagTargIntf.InitScript]
+
+// select TLB 1
+SETSPR 0x274 0x10000108 0xFFFFFFFF
+
+// programm internal Flash, no cache because of flash
+// TLB 1, entry 0
+SETSPR 0x270 0x10000000 0xFFFFFFFF
+// Valid, protect against invalidation, global entry, size=16MB
+SETSPR 0x271 0xC0000700 0xFFFFFFFF
+// effective page number 00000000
+SETSPR 0x272 0x28 0xFFFFFFFF
+// real page 00000000, UX,SX,UW,SW,UR,SR
+SETSPR 0x273 0x3F 0xFFFFFFFF
+// execute TLB write instruction
+EXECOPCODE 0x7C0007A4
+
+// programm internal SRAM
+// TLB 1, entry 1
+SETSPR 0x270 0x10010000 0xFFFFFFFF
+// Valid, protect against invalidation, global entry, size=16MB
+SETSPR 0x271 0xC0000700 0xFFFFFFFF
+// effective page number 40000000, I
+SETSPR 0x272 0x40000028 0xFFFFFFFF
+// real page 0x40000000, UX,SX,UW,SW,UR,SR
+SETSPR 0x273 0x4000003F 0xFFFFFFFF
+// execute TLB write instruction
+EXECOPCODE 0x7C0007A4
+
+// programm peripheral A modules
+// TLB 1, entry 2
+SETSPR 0x270 0x10020000 0xFFFFFFFF
+// Valid, protect against invalidation, global entry, size=1MB
+SETSPR 0x271 0xC0000500 0xFFFFFFFF
+// effective page number C3F00000, I
+SETSPR 0x272 0xC3F0000A 0xFFFFFFFF
+// real page C3F00000, UX,SX,UW,SW,UR,SR
+SETSPR 0x273 0xC3F0003F 0xFFFFFFFF
+// execute TLB write instruction
+EXECOPCODE 0x7C0007A4
+
+// programm off plattfrom modules
+// TLB 1, entry 3
+SETSPR 0x270 0x10030000 0xFFFFFFFF
+// Valid, protect against invalidation, global entry, size=1MB
+SETSPR 0x271 0xC0000500 0xFFFFFFFF
+// effective page number FFE00000, I,G
+SETSPR 0x272 0xFFE0000A 0xFFFFFFFF
+// real page FFE00000, UX,SX,UW,SW,UR,SR
+SETSPR 0x273 0xFFE0003F 0xFFFFFFFF
+// execute TLB write instruction
+EXECOPCODE 0x7C0007A4
+
+// programm on plattfrom modules
+// TLB 1, entry 4
+SETSPR 0x270 0x10040000 0xFFFFFFFF
+// Valid, protect against invalidation, global entry, size=1MB
+SETSPR 0x271 0xC0000500 0xFFFFFFFF
+// effective page number FFF00000, I,G
+SETSPR 0x272 0xFFF0000A 0xFFFFFFFF
+// real page FFF00000, UX,SX,UW,SW,UR,SR
+SETSPR 0x273 0xFFF0003F 0xFFFFFFFF
+// execute TLB write instruction
+EXECOPCODE 0x7C0007A4
+
+// setup IVOPR
+// points to internal memory at 0x40000000
+SETSPR 0x3F 0x40000000 0xFFFFFFFF
+
+// disable watchdog
+SET SWT_SR 0x0000C520
+SET SWT_SR 0x0000D928
+SET SWT_CR 0xFF00000A
+
+// setup pll and clocks
+// Oscillator select
+SET 0xC3FE0374 0x1000000
+SET 0xC3FE0370 0x1
+// enable all modes
+SET 0xC3FDC008 0x5FF
+// run mode
+SET 0xC3FDC02C 0x1F0032
+// enable peripherals in run and low power modes
+SET 0xC3FDC080 0xFE
+SET 0xC3FDC0A0 0x500
+// Z0 clock dividers -> 0.5 system clock
+//SET8 0xC3FE00C0 0x01
+// system clock dividers
+SET8 0xC3FE037C 0x80
+SET8 0xC3FE037D 0x80
+SET8 0xC3FE037E 0x80
+// enable auxiliary clocks
+SET16 0xC3FE0380 0x100
+SET16 0xC3FE0388 0x0
+SET8 0xC3FE038C 0x80
+// setup clock monitor
+SET 0xC3FE0100 0x6
+// Make DRUN configuration active
+SET 0xC3FDC004 0x30005AF0
+SET 0xC3FDC004 0x3000A50F
+WAIT 5
+// setup pll to 120MHz 40Mz external
+SET 0xC3FE00A0 0x0D300041
+// run mode
+SET 0xC3FDC02C 0x1F00F4
+// Make DRUN configuration active
+SET 0xC3FDC004 0x30005AF0
+SET 0xC3FDC004 0x3000A50F
+WAIT 5
+// setup SSCM erro cfg for debug
+SET 0xC3FD8006 0x3 0x3
+
+[Controller0.Core0.PpcJtagTargIntf.OnStartScript]
+
+[Controller0.Core0.PpcJtagTargIntf.OnHaltScript]
+
+[Controller0.Core1.PpcJtagTargIntf]
+PortType=Default
+ResetWaitTime=500
+MaxJtagClk=5000
+DoSramInit=1
+UseNexus=1
+AdaptiveJtagPhaseShift=1
+ConnOption=Break
+ChangeJtagClk=-1
+HaltAfterReset=0
+SimioAddr=g_JtagSimioAccess
+FreezeTimers=1
+InvalidTlbOnReset=0
+InvalidateCache=0
+ForceCacheFlush=0
+IgnoreLockedLines=0
+ExecInitCmds=0
+JtagTapNumber=0
+JtagNumOfTaps=1
+JtagNumIrBefore=0
+JtagNumIrAfter=0
+SimioAddr=g_JtagSimioAccess
+FlushCache=0
+AllowMmuSetup=0
+UseExtReset=0
+HandleWdtBug=0
+ForceEndOfReset=0
+JtagViaPod=0
+AllowResetOnCheck=0
+TargetPort=Default
+ChangeMsr=0
+ChangeMsrValue=0x0
+ExecOnStartCmds=0
+ExecOnHaltCmds=0
+EnableProgramTimeMeasurement=0
+UseHwResetMode=0
+HandleNexusAccessBug=0
+DoNotEnableTrapSwBrp=0
+BootPasswd0=0xFEEDFACE
+BootPasswd1=0xCAFEBEEF
+BootPasswd2=0xFFFFFFFF
+BootPasswd3=0xFFFFFFFF
+BootPasswd4=0xFFFFFFFF
+BootPasswd5=0xFFFFFFFF
+BootPasswd6=0xFFFFFFFF
+BootPasswd7=0xFFFFFFFF
+CommDevSel=
+
+[Controller0.Core1.PpcJtagTargIntf.InitScript]
+
+[Controller0.Core1.PpcJtagTargIntf.OnStartScript]
+
+[Controller0.Core1.PpcJtagTargIntf.OnHaltScript]
+
+[Controller0.Core0.DebugServer.DbgFramework]
+FRAMEWORK_COLOR=14804223
+[Controller0.Core1.DebugServer.DbgFramework]
+FRAMEWORK_COLOR=16777152