diff options
-rw-r--r-- | os/hal/platforms/SPC563/hal_lld.h | 63 |
1 files changed, 55 insertions, 8 deletions
diff --git a/os/hal/platforms/SPC563/hal_lld.h b/os/hal/platforms/SPC563/hal_lld.h index a9bc43ed8..52cd722a5 100644 --- a/os/hal/platforms/SPC563/hal_lld.h +++ b/os/hal/platforms/SPC563/hal_lld.h @@ -39,10 +39,51 @@ */
#define PLATFORM_NAME "SPC563M64"
-#define RFD_DIV2 0 /**< Divide VCO frequency by 2. */
-#define RFD_DIV4 1 /**< Divide VCO frequency by 4. */
-#define RFD_DIV8 2 /**< Divide VCO frequency by 8. */
-#define RFD_DIV16 3 /**< Divide VCO frequency by 16.*/
+#define RFD_DIV2 0 /**< Divide VCO frequency by 2. */
+#define RFD_DIV4 1 /**< Divide VCO frequency by 4. */
+#define RFD_DIV8 2 /**< Divide VCO frequency by 8. */
+#define RFD_DIV16 3 /**< Divide VCO frequency by 16.*/
+
+/* The following settings are related to the FLASH controller, performance
+ and stability depends on them, be careful.*/
+#define BIUCR_BANK1_TOO 0x01000000 /**< Use settings for bank1 too.*/
+#define BIUCR_MASTER7_PREFETCH 0x00800000 /**< Enable master 7 prefetch. */
+#define BIUCR_MASTER6_PREFETCH 0x00400000 /**< Enable master 6 prefetch. */
+#define BIUCR_MASTER5_PREFETCH 0x00200000 /**< Enable master 5 prefetch. */
+#define BIUCR_MASTER4_PREFETCH 0x00100000 /**< Enable master 4 prefetch. */
+#define BIUCR_MASTER3_PREFETCH 0x00080000 /**< Enable master 3 prefetch. */
+#define BIUCR_MASTER2_PREFETCH 0x00040000 /**< Enable master 2 prefetch. */
+#define BIUCR_MASTER1_PREFETCH 0x00020000 /**< Enable master 1 prefetch. */
+#define BIUCR_MASTER0_PREFETCH 0x00010000 /**< Enable master 0 prefetch. */
+#define BIUCR_APC_MASK 0x0000E000 /**< APC field mask. */
+#define BIUCR_APC_0 (0 << 13) /**< No additional hold cycles. */
+#define BIUCR_APC_1 (1 << 13) /**< 1 additional hold cycle. */
+#define BIUCR_APC_2 (2 << 13) /**< 2 additional hold cycles. */
+#define BIUCR_APC_3 (3 << 13) /**< 3 additional hold cycles. */
+#define BIUCR_APC_4 (4 << 13) /**< 4 additional hold cycles. */
+#define BIUCR_APC_5 (5 << 13) /**< 5 additional hold cycles. */
+#define BIUCR_APC_6 (6 << 13) /**< 6 additional hold cycles. */
+#define BIUCR_WWSC_MASK 0x00001800 /**< WWSC field mask. */
+#define BIUCR_WWSC_0 (0 << 11) /**< No write wait states. */
+#define BIUCR_WWSC_1 (1 << 11) /**< 1 write wait state. */
+#define BIUCR_WWSC_2 (2 << 11) /**< 2 write wait states. */
+#define BIUCR_WWSC_3 (3 << 11) /**< 3 write wait states. */
+#define BIUCR_RWSC_MASK 0x00001800 /**< RWSC field mask. */
+#define BIUCR_RWSC_0 (0 << 8) /**< No read wait states. */
+#define BIUCR_RWSC_1 (1 << 8) /**< 1 read wait state. */
+#define BIUCR_RWSC_2 (2 << 8) /**< 2 read wait states. */
+#define BIUCR_RWSC_3 (3 << 8) /**< 3 read wait states. */
+#define BIUCR_RWSC_4 (4 << 8) /**< 4 read wait states. */
+#define BIUCR_RWSC_5 (5 << 8) /**< 5 read wait states. */
+#define BIUCR_RWSC_6 (6 << 8) /**< 6 read wait states. */
+#define BIUCR_RWSC_7 (7 << 8) /**< 7 read wait states. */
+#define BIUCR_DPFEN 0x00000040 /**< Data prefetch enable. */
+#define BIUCR_IPFEN 0x00000010 /**< Instr. prefetch enable. */
+#define BIUCR_PFLIM_MASK 0x00000060 /**< PFLIM field mask. */
+#define BIUCR_PFLIM_NO (0 << 1) /**< No prefetching. */
+#define BIUCR_PFLIM_ON_MISS (1 << 1) /**< Prefetch on miss. */
+#define BIUCR_PFLIM_ON_HITMISS (2 << 1) /**< Prefetch on hit and miss. */
+#define BIUCR_BFEN 0x00000001 /**< Flash buffering enable. */
/*===========================================================================*/
/* Driver pre-compile time settings. */
@@ -98,7 +139,13 @@ * value.
*/
#if !defined(SPC563_FLASH_BIUCR) || defined(__DOXYGEN__)
-#define SPC563_FLASH_BIUCR (0x01110053 & 0xFFFF00FF)
+#define SPC563_FLASH_BIUCR (BIUCR_BANK1_TOO | \
+ BIUCR_MASTER4_PREFETCH | \
+ BIUCR_MASTER0_PREFETCH | \
+ BIUCR_DPFEN | \
+ BIUCR_IPFEN | \
+ BIUCR_PFLIM_ON_HITMISS | \
+ BIUCR_BFEN)
#endif
/*===========================================================================*/
@@ -144,11 +191,11 @@ * @brief Flash wait states are a function of the system clock.
*/
#if (SPC563_SYSCLK <= 30000000) || defined(__DOXYGEN__)
-#define SPC563_FLASH_WS 0x00000800 /* APC=0, RWSC=0, WWSC=1. */
+#define SPC563_FLASH_WS (BIUCR_APC_0 | BIUCR_RWSC_0 | BIUCR_WWSC_1)
#elif SPC563_SYSCLK <= 60000000
-#define SPC563_FLASH_WS 0x00002900 /* APC=1, RWSC=1, WWSC=1. */
+#define SPC563_FLASH_WS (BIUCR_APC_1 | BIUCR_RWSC_1 | BIUCR_WWSC_1)
#else
-#define SPC563_FLASH_WS 0x00004A00 /* APC=2, RWSC=2, WWSC=1. */
+#define SPC563_FLASH_WS (BIUCR_APC_2 | BIUCR_RWSC_2 | BIUCR_WWSC_1)
#endif
/*===========================================================================*/
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