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-rw-r--r--os/hal/boards/OLIMEX_STM32_E407/board.c41
-rw-r--r--os/hal/boards/OLIMEX_STM32_E407/board.h2
-rw-r--r--os/hal/boards/OLIMEX_STM32_E407/cfg/board.chcfg9
-rw-r--r--os/hal/boards/OLIMEX_STM32_H407/board.c43
-rw-r--r--os/hal/boards/OLIMEX_STM32_H407/board.h2
-rw-r--r--os/hal/boards/OLIMEX_STM32_H407/board.mk4
-rw-r--r--os/hal/boards/OLIMEX_STM32_H407/cfg/board.chcfg9
-rw-r--r--os/hal/boards/ST_NUCLEO_F030R8/board.c37
-rw-r--r--os/hal/boards/ST_NUCLEO_F030R8/board.h2
-rw-r--r--os/hal/boards/ST_NUCLEO_F030R8/cfg/board.chcfg3
-rw-r--r--os/hal/boards/ST_NUCLEO_F334R8/board.c249
-rw-r--r--os/hal/boards/ST_NUCLEO_F334R8/board.h2181
-rw-r--r--os/hal/boards/ST_NUCLEO_F334R8/board.mk10
-rw-r--r--os/hal/boards/ST_NUCLEO_F334R8/cfg/board.chcfg409
-rw-r--r--os/hal/boards/ST_NUCLEO_F401RE/board.c13
-rw-r--r--os/hal/boards/ST_NUCLEO_F401RE/board.h2
-rw-r--r--os/hal/boards/ST_NUCLEO_F401RE/cfg/board.chcfg3
-rw-r--r--os/hal/boards/ST_NUCLEO_L152RE/board.c12
-rw-r--r--os/hal/boards/ST_NUCLEO_L152RE/board.h2
-rw-r--r--os/hal/boards/ST_NUCLEO_L152RE/cfg/board.chcfg1
-rw-r--r--os/hal/boards/ST_STM32373C_EVAL/board.c39
-rw-r--r--os/hal/boards/ST_STM32373C_EVAL/board.h2
-rw-r--r--os/hal/boards/ST_STM32373C_EVAL/cfg/board.chcfg3
-rw-r--r--os/hal/boards/ST_STM32F072B_DISCOVERY/board.c2
-rw-r--r--os/hal/boards/ST_STM32F072B_DISCOVERY/board.h6
-rw-r--r--os/hal/boards/ST_STM32F072B_DISCOVERY/board.mk4
-rw-r--r--os/hal/boards/ST_STM32F072B_DISCOVERY/cfg/board.chcfg5
-rw-r--r--os/hal/boards/ST_STM32F0_DISCOVERY/board.c37
-rw-r--r--os/hal/boards/ST_STM32F0_DISCOVERY/board.h2
-rw-r--r--os/hal/boards/ST_STM32F0_DISCOVERY/cfg/board.chcfg3
-rw-r--r--os/hal/boards/ST_STM32F3_DISCOVERY/board.c39
-rw-r--r--os/hal/boards/ST_STM32F3_DISCOVERY/board.h2
-rw-r--r--os/hal/boards/ST_STM32F3_DISCOVERY/cfg/board.chcfg3
-rw-r--r--os/hal/boards/ST_STM32F429I_DISCOVERY/board.c39
-rw-r--r--os/hal/boards/ST_STM32F429I_DISCOVERY/board.h2
-rw-r--r--os/hal/boards/ST_STM32F429I_DISCOVERY/cfg/board.chcfg3
-rw-r--r--os/hal/boards/ST_STM32F4_DISCOVERY/board.c2
-rw-r--r--os/hal/boards/ST_STM32F4_DISCOVERY/cfg/board.chcfg1
-rw-r--r--os/hal/boards/ST_STM32L_DISCOVERY/board.c39
-rw-r--r--os/hal/boards/ST_STM32L_DISCOVERY/board.h2
-rw-r--r--os/hal/boards/ST_STM32L_DISCOVERY/cfg/board.chcfg2
41 files changed, 1329 insertions, 1942 deletions
diff --git a/os/hal/boards/OLIMEX_STM32_E407/board.c b/os/hal/boards/OLIMEX_STM32_E407/board.c
index 8edc49e5f..e2144859f 100644
--- a/os/hal/boards/OLIMEX_STM32_E407/board.c
+++ b/os/hal/boards/OLIMEX_STM32_E407/board.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -22,26 +22,43 @@
* @details Digital I/O ports static configuration as defined in @p board.h.
* This variable is used by the HAL when initializing the PAL driver.
*/
-const PALConfig pal_default_config =
-{
+const PALConfig pal_default_config = {
+#if STM32_HAS_GPIOA
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+#endif
+#if STM32_HAS_GPIOB
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+#endif
+#if STM32_HAS_GPIOC
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+#endif
+#if STM32_HAS_GPIOD
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+#endif
+#if STM32_HAS_GPIOE
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+#endif
+#if STM32_HAS_GPIOF
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
+#endif
+#if STM32_HAS_GPIOG
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
+#endif
+#if STM32_HAS_GPIOH
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
+#endif
+#if STM32_HAS_GPIOI
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
+#endif
};
#endif
@@ -60,10 +77,10 @@ void __early_init(void) {
* @brief SDC card detection.
*/
bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
- static bool last_status = FALSE;
-
- if (blkIsTransferring(sdcp))
- return last_status;
+ static bool last_status = false;
+
+ if (blkIsTransferring(sdcp))
+ return last_status;
return last_status = (bool)palReadPad(GPIOC, GPIOC_SD_D3);
}
@@ -71,9 +88,9 @@ bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
* @brief SDC card write protection detection.
*/
bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
-
- (void)sdcp;
- return FALSE;
+
+ (void)sdcp;
+ return false;
}
#endif /* HAL_USE_SDC */
@@ -85,7 +102,7 @@ bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
- return TRUE;
+ return true;
}
/**
@@ -95,7 +112,7 @@ bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
- return FALSE;
+ return false;
}
#endif
diff --git a/os/hal/boards/OLIMEX_STM32_E407/board.h b/os/hal/boards/OLIMEX_STM32_E407/board.h
index 1942b9975..af007213d 100644
--- a/os/hal/boards/OLIMEX_STM32_E407/board.h
+++ b/os/hal/boards/OLIMEX_STM32_E407/board.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
diff --git a/os/hal/boards/OLIMEX_STM32_E407/cfg/board.chcfg b/os/hal/boards/OLIMEX_STM32_E407/cfg/board.chcfg
index ff3ab4e3d..0818bbb3d 100644
--- a/os/hal/boards/OLIMEX_STM32_E407/cfg/board.chcfg
+++ b/os/hal/boards/OLIMEX_STM32_E407/cfg/board.chcfg
@@ -5,24 +5,25 @@
<configuration_settings>
<templates_path>resources/gencfg/processors/boards/stm32f4xx/templates</templates_path>
<output_path>..</output_path>
+ <hal_version>3.0.x</hal_version>
</configuration_settings>
<board_name>Olimex STM32-E407</board_name>
<board_id>OLIMEX_STM32_E407</board_id>
<board_functions>
- <sdc_lld_is_card_inserted><![CDATA[ static bool_t last_status = FALSE;
+ <sdc_lld_is_card_inserted><![CDATA[ static bool last_status = false;
if (blkIsTransferring(sdcp))
return last_status;
- return last_status = (bool_t)palReadPad(GPIOC, GPIOC_SD_D3);]]></sdc_lld_is_card_inserted>
+ return last_status = (bool)palReadPad(GPIOC, GPIOC_SD_D3);]]></sdc_lld_is_card_inserted>
<sdc_lld_is_write_protected>
<![CDATA[ (void)sdcp;
- return FALSE;]]></sdc_lld_is_write_protected>
+ return false;]]></sdc_lld_is_write_protected>
</board_functions>
<ethernet_phy>
<identifier>MII_KS8721_ID</identifier>
<bus_type>RMII</bus_type>
</ethernet_phy>
- <subtype>STM32F40_41xxx</subtype>
+ <subtype>STM32F407xx</subtype>
<clocks
HSEFrequency="12000000"
HSEBypass="false"
diff --git a/os/hal/boards/OLIMEX_STM32_H407/board.c b/os/hal/boards/OLIMEX_STM32_H407/board.c
index 7d1ab4d51..e2144859f 100644
--- a/os/hal/boards/OLIMEX_STM32_H407/board.c
+++ b/os/hal/boards/OLIMEX_STM32_H407/board.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -22,26 +22,43 @@
* @details Digital I/O ports static configuration as defined in @p board.h.
* This variable is used by the HAL when initializing the PAL driver.
*/
-const PALConfig pal_default_config =
-{
+const PALConfig pal_default_config = {
+#if STM32_HAS_GPIOA
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+#endif
+#if STM32_HAS_GPIOB
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+#endif
+#if STM32_HAS_GPIOC
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+#endif
+#if STM32_HAS_GPIOD
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+#endif
+#if STM32_HAS_GPIOE
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+#endif
+#if STM32_HAS_GPIOF
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
+#endif
+#if STM32_HAS_GPIOG
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
+#endif
+#if STM32_HAS_GPIOH
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
+#endif
+#if STM32_HAS_GPIOI
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
+#endif
};
#endif
@@ -60,20 +77,20 @@ void __early_init(void) {
* @brief SDC card detection.
*/
bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
- static bool_t last_status = FALSE;
-
- if (blkIsTransferring(sdcp))
- return last_status;
- return last_status = (bool_t)palReadPad(GPIOC, GPIOC_SD_D3);
+ static bool last_status = false;
+
+ if (blkIsTransferring(sdcp))
+ return last_status;
+ return last_status = (bool)palReadPad(GPIOC, GPIOC_SD_D3);
}
/**
* @brief SDC card write protection detection.
*/
bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
-
- (void)sdcp;
- return FALSE;
+
+ (void)sdcp;
+ return false;
}
#endif /* HAL_USE_SDC */
@@ -85,7 +102,7 @@ bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
- return TRUE;
+ return true;
}
/**
@@ -95,7 +112,7 @@ bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
- return FALSE;
+ return false;
}
#endif
diff --git a/os/hal/boards/OLIMEX_STM32_H407/board.h b/os/hal/boards/OLIMEX_STM32_H407/board.h
index e2c022694..deec1f73f 100644
--- a/os/hal/boards/OLIMEX_STM32_H407/board.h
+++ b/os/hal/boards/OLIMEX_STM32_H407/board.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
diff --git a/os/hal/boards/OLIMEX_STM32_H407/board.mk b/os/hal/boards/OLIMEX_STM32_H407/board.mk
index 8bd37d59d..6567ce031 100644
--- a/os/hal/boards/OLIMEX_STM32_H407/board.mk
+++ b/os/hal/boards/OLIMEX_STM32_H407/board.mk
@@ -1,5 +1,5 @@
# List of all the board related files.
-BOARDSRC = ${CHIBIOS}/boards/OLIMEX_STM32_H407/board.c
+BOARDSRC = ${CHIBIOS}/os/hal/boards/OLIMEX_STM32_H407/board.c
# Required include directories
-BOARDINC = ${CHIBIOS}/boards/OLIMEX_STM32_H407
+BOARDINC = ${CHIBIOS}/os/hal/boards/OLIMEX_STM32_H407
diff --git a/os/hal/boards/OLIMEX_STM32_H407/cfg/board.chcfg b/os/hal/boards/OLIMEX_STM32_H407/cfg/board.chcfg
index 8b4cda0b9..dfbd0f50b 100644
--- a/os/hal/boards/OLIMEX_STM32_H407/cfg/board.chcfg
+++ b/os/hal/boards/OLIMEX_STM32_H407/cfg/board.chcfg
@@ -5,24 +5,25 @@
<configuration_settings>
<templates_path>resources/gencfg/processors/boards/stm32f4xx/templates</templates_path>
<output_path>..</output_path>
+ <hal_version>3.0.x</hal_version>
</configuration_settings>
<board_name>Olimex STM32-H407</board_name>
<board_id>OLIMEX_STM32_H407</board_id>
<board_functions>
- <sdc_lld_is_card_inserted><![CDATA[ static bool_t last_status = FALSE;
+ <sdc_lld_is_card_inserted><![CDATA[ static bool last_status = false;
if (blkIsTransferring(sdcp))
return last_status;
- return last_status = (bool_t)palReadPad(GPIOC, GPIOC_SD_D3);]]></sdc_lld_is_card_inserted>
+ return last_status = (bool)palReadPad(GPIOC, GPIOC_SD_D3);]]></sdc_lld_is_card_inserted>
<sdc_lld_is_write_protected>
<![CDATA[ (void)sdcp;
- return FALSE;]]></sdc_lld_is_write_protected>
+ return false;]]></sdc_lld_is_write_protected>
</board_functions>
<ethernet_phy>
<identifier>MII_KS8721_ID</identifier>
<bus_type>RMII</bus_type>
</ethernet_phy>
- <subtype>STM32F40_41xxx</subtype>
+ <subtype>STM32F407xx</subtype>
<clocks
HSEFrequency="12000000"
HSEBypass="false"
diff --git a/os/hal/boards/ST_NUCLEO_F030R8/board.c b/os/hal/boards/ST_NUCLEO_F030R8/board.c
index 8ed20fcb4..dc058f60d 100644
--- a/os/hal/boards/ST_NUCLEO_F030R8/board.c
+++ b/os/hal/boards/ST_NUCLEO_F030R8/board.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -22,18 +22,43 @@
* @details Digital I/O ports static configuration as defined in @p board.h.
* This variable is used by the HAL when initializing the PAL driver.
*/
-const PALConfig pal_default_config =
-{
+const PALConfig pal_default_config = {
+#if STM32_HAS_GPIOA
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+#endif
+#if STM32_HAS_GPIOB
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+#endif
+#if STM32_HAS_GPIOC
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+#endif
+#if STM32_HAS_GPIOD
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+#endif
+#if STM32_HAS_GPIOE
+ {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+ VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+#endif
+#if STM32_HAS_GPIOF
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
- VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}
+ VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
+#endif
+#if STM32_HAS_GPIOG
+ {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+ VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
+#endif
+#if STM32_HAS_GPIOH
+ {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+ VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
+#endif
+#if STM32_HAS_GPIOI
+ {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+ VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
+#endif
};
#endif
@@ -55,7 +80,7 @@ bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
- return TRUE;
+ return true;
}
/**
@@ -65,7 +90,7 @@ bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
- return FALSE;
+ return false;
}
#endif
diff --git a/os/hal/boards/ST_NUCLEO_F030R8/board.h b/os/hal/boards/ST_NUCLEO_F030R8/board.h
index afcf89760..a2106020b 100644
--- a/os/hal/boards/ST_NUCLEO_F030R8/board.h
+++ b/os/hal/boards/ST_NUCLEO_F030R8/board.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
diff --git a/os/hal/boards/ST_NUCLEO_F030R8/cfg/board.chcfg b/os/hal/boards/ST_NUCLEO_F030R8/cfg/board.chcfg
index 60eebcd61..a6a3e54cf 100644
--- a/os/hal/boards/ST_NUCLEO_F030R8/cfg/board.chcfg
+++ b/os/hal/boards/ST_NUCLEO_F030R8/cfg/board.chcfg
@@ -6,11 +6,12 @@
<configuration_settings>
<templates_path>resources/gencfg/processors/boards/stm32f0xx/templates</templates_path>
<output_path>..</output_path>
+ <hal_version>3.0.x</hal_version>
</configuration_settings>
<board_name>STMicroelectronics NUCLEO-F030R8</board_name>
<board_id>ST_NUCLEO_F030R8</board_id>
<board_functions></board_functions>
- <subtype>STM32F030</subtype>
+ <subtype>STM32F030x8</subtype>
<clocks HSEFrequency="0" HSEBypass="true" LSEFrequency="0"
LSEBypass="false" LSEDrive="3 High Drive (default)" />
<ports>
diff --git a/os/hal/boards/ST_NUCLEO_F334R8/board.c b/os/hal/boards/ST_NUCLEO_F334R8/board.c
index c581d22b2..6eb610254 100644
--- a/os/hal/boards/ST_NUCLEO_F334R8/board.c
+++ b/os/hal/boards/ST_NUCLEO_F334R8/board.c
@@ -1,125 +1,124 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-/**
- * @brief PAL setup.
- * @details Digital I/O ports static configuration as defined in @p board.h.
- * This variable is used by the HAL when initializing the PAL driver.
- */
-const PALConfig pal_default_config =
-{
-#if STM32_HAS_GPIOA
- {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
- VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
-#endif
-#if STM32_HAS_GPIOB
- {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
- VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
-#endif
-#if STM32_HAS_GPIOC
- {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
- VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
-#endif
-#if STM32_HAS_GPIOD
- {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
- VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
-#endif
-#if STM32_HAS_GPIOE
- {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
- VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
-#endif
-#if STM32_HAS_GPIOF
- {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
- VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
-#endif
-#if STM32_HAS_GPIOG
- {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
- VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
-#endif
-#if STM32_HAS_GPIOH
- {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
- VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
-#endif
-#if STM32_HAS_GPIOI
- {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
- VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
-#endif
-};
-#endif
-
-/**
- * @brief Early initialization code.
- * @details This initialization must be performed just after stack setup
- * and before any other initialization.
- */
-void __early_init(void) {
-
- stm32_clock_init();
-}
-
-#if HAL_USE_SDC || defined(__DOXYGEN__)
-/**
- * @brief SDC card detection.
- */
-bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
-
- (void)sdcp;
- /* TODO: Fill the implementation.*/
- return TRUE;
-}
-
-/**
- * @brief SDC card write protection detection.
- */
-bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
-
- (void)sdcp;
- /* TODO: Fill the implementation.*/
- return FALSE;
-}
-#endif /* HAL_USE_SDC */
-
-#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
-/**
- * @brief MMC_SPI card detection.
- */
-bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
-
- (void)mmcp;
- /* TODO: Fill the implementation.*/
- return TRUE;
-}
-
-/**
- * @brief MMC_SPI card write protection detection.
- */
-bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
-
- (void)mmcp;
- /* TODO: Fill the implementation.*/
- return FALSE;
-}
-#endif
-
-/**
- * @brief Board-specific initialization code.
- * @todo Add your board-specific code, if any.
- */
-void boardInit(void) {
-}
+/*
+ ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config = {
+#if STM32_HAS_GPIOA
+ {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
+ VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+#endif
+#if STM32_HAS_GPIOB
+ {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
+ VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+#endif
+#if STM32_HAS_GPIOC
+ {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
+ VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+#endif
+#if STM32_HAS_GPIOD
+ {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
+ VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+#endif
+#if STM32_HAS_GPIOE
+ {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+ VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+#endif
+#if STM32_HAS_GPIOF
+ {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+ VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
+#endif
+#if STM32_HAS_GPIOG
+ {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+ VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
+#endif
+#if STM32_HAS_GPIOH
+ {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+ VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
+#endif
+#if STM32_HAS_GPIOI
+ {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+ VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
+#endif
+};
+#endif
+
+/**
+ * @brief Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ * and before any other initialization.
+ */
+void __early_init(void) {
+
+ stm32_clock_init();
+}
+
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief SDC card detection.
+ */
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* TODO: Fill the implementation.*/
+ return true;
+}
+
+/**
+ * @brief SDC card write protection detection.
+ */
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* TODO: Fill the implementation.*/
+ return false;
+}
+#endif /* HAL_USE_SDC */
+
+#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
+/**
+ * @brief MMC_SPI card detection.
+ */
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* TODO: Fill the implementation.*/
+ return true;
+}
+
+/**
+ * @brief MMC_SPI card write protection detection.
+ */
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
+
+ (void)mmcp;
+ /* TODO: Fill the implementation.*/
+ return false;
+}
+#endif
+
+/**
+ * @brief Board-specific initialization code.
+ * @todo Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/ST_NUCLEO_F334R8/board.h b/os/hal/boards/ST_NUCLEO_F334R8/board.h
index 8c9774d48..e334ac1c5 100644
--- a/os/hal/boards/ST_NUCLEO_F334R8/board.h
+++ b/os/hal/boards/ST_NUCLEO_F334R8/board.h
@@ -1,1291 +1,890 @@
-/*
- ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio
-
- Licensed under the Apache License, Version 2.0 (the "License");
- you may not use this file except in compliance with the License.
- You may obtain a copy of the License at
-
- http://www.apache.org/licenses/LICENSE-2.0
-
- Unless required by applicable law or agreed to in writing, software
- distributed under the License is distributed on an "AS IS" BASIS,
- WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- See the License for the specific language governing permissions and
- limitations under the License.
-*/
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-/*
- * Setup for STMicroelectronics NUCLEO-F334R8 board.
- */
-
-/*
- * Board identifier.
- */
-#define BOARD_ST_NUCLEO_F334R8
-#define BOARD_NAME "STMicroelectronics NUCLEO-F334R8"
-
-
-/*
- * Board oscillators-related settings.
- * NOTE: LSE not fitted.
- * NOTE: HSE not fitted.
- */
-#if !defined(STM32_LSECLK)
-#define STM32_LSECLK 0
-#endif
-
-#if !defined(STM32_HSECLK)
-#define STM32_HSECLK 0
-#endif
-
-/*
- * MCU type as defined in the ST header.
- */
-#define STM32F334x8
-
-/*
- * IO pins assignments.
- */
-#define GPIOA_PIN0 0
-#define GPIOA_PIN1 1
-#define GPIOA_USART_TX 2
-#define GPIOA_USART_RX 3
-#define GPIOA_PIN4 4
-#define GPIOA_LED_GREEN 5
-#define GPIOA_PIN6 6
-#define GPIOA_PIN7 7
-#define GPIOA_PIN8 8
-#define GPIOA_PIN9 9
-#define GPIOA_PIN10 10
-#define GPIOA_OTG_FS_DM 11
-#define GPIOA_OTG_FS_DP 12
-#define GPIOA_SWDIO 13
-#define GPIOA_SWCLK 14
-#define GPIOA_PIN15 15
-
-#define GPIOB_PIN0 0
-#define GPIOB_PIN1 1
-#define GPIOB_PIN2 2
-#define GPIOB_SWO 3
-#define GPIOB_PIN4 4
-#define GPIOB_PIN5 5
-#define GPIOB_PIN6 6
-#define GPIOB_PIN7 7
-#define GPIOB_PIN8 8
-#define GPIOB_PIN9 9
-#define GPIOB_PIN10 10
-#define GPIOB_PIN11 11
-#define GPIOB_PIN12 12
-#define GPIOB_PIN13 13
-#define GPIOB_PIN14 14
-#define GPIOB_PIN15 15
-
-#define GPIOC_PIN0 0
-#define GPIOC_PIN1 1
-#define GPIOC_PIN2 2
-#define GPIOC_PIN3 3
-#define GPIOC_PIN4 4
-#define GPIOC_PIN5 5
-#define GPIOC_PIN6 6
-#define GPIOC_PIN7 7
-#define GPIOC_PIN8 8
-#define GPIOC_PIN9 9
-#define GPIOC_PIN10 10
-#define GPIOC_PIN11 11
-#define GPIOC_PIN12 12
-#define GPIOC_BUTTON 13
-#define GPIOC_PIN14 14
-#define GPIOC_PIN15 15
-
-#define GPIOD_PIN0 0
-#define GPIOD_PIN1 1
-#define GPIOD_PIN2 2
-#define GPIOD_PIN3 3
-#define GPIOD_PIN4 4
-#define GPIOD_PIN5 5
-#define GPIOD_PIN6 6
-#define GPIOD_PIN7 7
-#define GPIOD_PIN8 8
-#define GPIOD_PIN9 9
-#define GPIOD_PIN10 10
-#define GPIOD_PIN11 11
-#define GPIOD_PIN12 12
-#define GPIOD_PIN13 13
-#define GPIOD_PIN14 14
-#define GPIOD_PIN15 15
-
-#define GPIOE_PIN0 0
-#define GPIOE_PIN1 1
-#define GPIOE_PIN2 2
-#define GPIOE_PIN3 3
-#define GPIOE_PIN4 4
-#define GPIOE_PIN5 5
-#define GPIOE_PIN6 6
-#define GPIOE_PIN7 7
-#define GPIOE_PIN8 8
-#define GPIOE_PIN9 9
-#define GPIOE_PIN10 10
-#define GPIOE_PIN11 11
-#define GPIOE_PIN12 12
-#define GPIOE_PIN13 13
-#define GPIOE_PIN14 14
-#define GPIOE_PIN15 15
-
-#define GPIOF_PIN0 0
-#define GPIOF_PIN1 1
-#define GPIOF_PIN2 2
-#define GPIOF_PIN3 3
-#define GPIOF_PIN4 4
-#define GPIOF_PIN5 5
-#define GPIOF_PIN6 6
-#define GPIOF_PIN7 7
-#define GPIOF_PIN8 8
-#define GPIOF_PIN9 9
-#define GPIOF_PIN10 10
-#define GPIOF_PIN11 11
-#define GPIOF_PIN12 12
-#define GPIOF_PIN13 13
-#define GPIOF_PIN14 14
-#define GPIOF_PIN15 15
-
-#define GPIOG_PIN0 0
-#define GPIOG_PIN1 1
-#define GPIOG_PIN2 2
-#define GPIOG_PIN3 3
-#define GPIOG_PIN4 4
-#define GPIOG_PIN5 5
-#define GPIOG_PIN6 6
-#define GPIOG_PIN7 7
-#define GPIOG_PIN8 8
-#define GPIOG_PIN9 9
-#define GPIOG_PIN10 10
-#define GPIOG_PIN11 11
-#define GPIOG_PIN12 12
-#define GPIOG_PIN13 13
-#define GPIOG_PIN14 14
-#define GPIOG_PIN15 15
-
-#define GPIOH_OSC_IN 0
-#define GPIOH_OSC_OUT 1
-#define GPIOH_PIN2 2
-#define GPIOH_PIN3 3
-#define GPIOH_PIN4 4
-#define GPIOH_PIN5 5
-#define GPIOH_PIN6 6
-#define GPIOH_PIN7 7
-#define GPIOH_PIN8 8
-#define GPIOH_PIN9 9
-#define GPIOH_PIN10 10
-#define GPIOH_PIN11 11
-#define GPIOH_PIN12 12
-#define GPIOH_PIN13 13
-#define GPIOH_PIN14 14
-#define GPIOH_PIN15 15
-
-#define GPIOI_PIN0 0
-#define GPIOI_PIN1 1
-#define GPIOI_PIN2 2
-#define GPIOI_PIN3 3
-#define GPIOI_PIN4 4
-#define GPIOI_PIN5 5
-#define GPIOI_PIN6 6
-#define GPIOI_PIN7 7
-#define GPIOI_PIN8 8
-#define GPIOI_PIN9 9
-#define GPIOI_PIN10 10
-#define GPIOI_PIN11 11
-#define GPIOI_PIN12 12
-#define GPIOI_PIN13 13
-#define GPIOI_PIN14 14
-#define GPIOI_PIN15 15
-
-/*
- * I/O ports initial setup, this configuration is established soon after reset
- * in the initialization code.
- * Please refer to the STM32 Reference Manual for details.
- */
-#define PIN_MODE_INPUT(n) (0U << ((n) * 2))
-#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2))
-#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2))
-#define PIN_MODE_ANALOG(n) (3U << ((n) * 2))
-#define PIN_ODR_LOW(n) (0U << (n))
-#define PIN_ODR_HIGH(n) (1U << (n))
-#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
-#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
-#define PIN_OSPEED_2M(n) (0U << ((n) * 2))
-#define PIN_OSPEED_25M(n) (1U << ((n) * 2))
-#define PIN_OSPEED_50M(n) (2U << ((n) * 2))
-#define PIN_OSPEED_100M(n) (3U << ((n) * 2))
-#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2))
-#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2))
-#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2))
-#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4))
-
-/*
- * GPIOA setup:
- *
- * PA0 - PIN0 (input pullup).
- * PA1 - PIN1 (input pullup).
- * PA2 - USART_TX (alternate 7).
- * PA3 - USART_RX (alternate 7).
- * PA4 - PIN4 (input pullup).
- * PA5 - LED_GREEN (output pushpull high).
- * PA6 - PIN6 (input pullup).
- * PA7 - PIN7 (input pullup).
- * PA8 - PIN8 (input pullup).
- * PA9 - PIN9 (input pullup).
- * PA10 - PIN10 (input pullup).
- * PA11 - OTG_FS_DM (alternate 10).
- * PA12 - OTG_FS_DP (alternate 10).
- * PA13 - SWDIO (alternate 0).
- * PA14 - SWCLK (alternate 0).
- * PA15 - PIN15 (input pullup).
- */
-#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_PIN0) | \
- PIN_MODE_INPUT(GPIOA_PIN1) | \
- PIN_MODE_ALTERNATE(GPIOA_USART_TX) | \
- PIN_MODE_ALTERNATE(GPIOA_USART_RX) | \
- PIN_MODE_INPUT(GPIOA_PIN4) | \
- PIN_MODE_OUTPUT(GPIOA_LED_GREEN) | \
- PIN_MODE_INPUT(GPIOA_PIN6) | \
- PIN_MODE_INPUT(GPIOA_PIN7) | \
- PIN_MODE_INPUT(GPIOA_PIN8) | \
- PIN_MODE_INPUT(GPIOA_PIN9) | \
- PIN_MODE_INPUT(GPIOA_PIN10) | \
- PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \
- PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \
- PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \
- PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \
- PIN_MODE_INPUT(GPIOA_PIN15))
-#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) | \
- PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \
- PIN_OTYPE_PUSHPULL(GPIOA_USART_TX) | \
- PIN_OTYPE_PUSHPULL(GPIOA_USART_RX) | \
- PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \
- PIN_OTYPE_PUSHPULL(GPIOA_LED_GREEN) | \
- PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \
- PIN_OTYPE_PUSHPULL(GPIOA_PIN7) | \
- PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \
- PIN_OTYPE_PUSHPULL(GPIOA_PIN9) | \
- PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | \
- PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \
- PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \
- PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \
- PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \
- PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
-#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_100M(GPIOA_PIN0) | \
- PIN_OSPEED_100M(GPIOA_PIN1) | \
- PIN_OSPEED_50M(GPIOA_USART_TX) | \
- PIN_OSPEED_50M(GPIOA_USART_RX) | \
- PIN_OSPEED_100M(GPIOA_PIN4) | \
- PIN_OSPEED_50M(GPIOA_LED_GREEN) | \
- PIN_OSPEED_100M(GPIOA_PIN6) | \
- PIN_OSPEED_100M(GPIOA_PIN7) | \
- PIN_OSPEED_100M(GPIOA_PIN8) | \
- PIN_OSPEED_100M(GPIOA_PIN9) | \
- PIN_OSPEED_100M(GPIOA_PIN10) | \
- PIN_OSPEED_100M(GPIOA_OTG_FS_DM) | \
- PIN_OSPEED_100M(GPIOA_OTG_FS_DP) | \
- PIN_OSPEED_100M(GPIOA_SWDIO) | \
- PIN_OSPEED_100M(GPIOA_SWCLK) | \
- PIN_OSPEED_100M(GPIOA_PIN15))
-#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_PIN0) | \
- PIN_PUPDR_PULLUP(GPIOA_PIN1) | \
- PIN_PUPDR_FLOATING(GPIOA_USART_TX) | \
- PIN_PUPDR_FLOATING(GPIOA_USART_RX) | \
- PIN_PUPDR_PULLUP(GPIOA_PIN4) | \
- PIN_PUPDR_FLOATING(GPIOA_LED_GREEN) | \
- PIN_PUPDR_PULLUP(GPIOA_PIN6) | \
- PIN_PUPDR_PULLUP(GPIOA_PIN7) | \
- PIN_PUPDR_PULLUP(GPIOA_PIN8) | \
- PIN_PUPDR_PULLUP(GPIOA_PIN9) | \
- PIN_PUPDR_PULLUP(GPIOA_PIN10) | \
- PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \
- PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \
- PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \
- PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \
- PIN_PUPDR_PULLUP(GPIOA_PIN15))
-#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_PIN0) | \
- PIN_ODR_HIGH(GPIOA_PIN1) | \
- PIN_ODR_HIGH(GPIOA_USART_TX) | \
- PIN_ODR_HIGH(GPIOA_USART_RX) | \
- PIN_ODR_HIGH(GPIOA_PIN4) | \
- PIN_ODR_LOW(GPIOA_LED_GREEN) | \
- PIN_ODR_HIGH(GPIOA_PIN6) | \
- PIN_ODR_HIGH(GPIOA_PIN7) | \
- PIN_ODR_HIGH(GPIOA_PIN8) | \
- PIN_ODR_HIGH(GPIOA_PIN9) | \
- PIN_ODR_HIGH(GPIOA_PIN10) | \
- PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \
- PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \
- PIN_ODR_HIGH(GPIOA_SWDIO) | \
- PIN_ODR_HIGH(GPIOA_SWCLK) | \
- PIN_ODR_HIGH(GPIOA_PIN15))
-#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PIN0, 0) | \
- PIN_AFIO_AF(GPIOA_PIN1, 0) | \
- PIN_AFIO_AF(GPIOA_USART_TX, 7) | \
- PIN_AFIO_AF(GPIOA_USART_RX, 7) | \
- PIN_AFIO_AF(GPIOA_PIN4, 0) | \
- PIN_AFIO_AF(GPIOA_LED_GREEN, 0) | \
- PIN_AFIO_AF(GPIOA_PIN6, 0) | \
- PIN_AFIO_AF(GPIOA_PIN7, 0))
-#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0) | \
- PIN_AFIO_AF(GPIOA_PIN9, 0) | \
- PIN_AFIO_AF(GPIOA_PIN10, 0) | \
- PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) | \
- PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) | \
- PIN_AFIO_AF(GPIOA_SWDIO, 0) | \
- PIN_AFIO_AF(GPIOA_SWCLK, 0) | \
- PIN_AFIO_AF(GPIOA_PIN15, 0))
-
-/*
- * GPIOB setup:
- *
- * PB0 - PIN0 (input pullup).
- * PB1 - PIN1 (input pullup).
- * PB2 - PIN2 (input pullup).
- * PB3 - SWO (alternate 0).
- * PB4 - PIN4 (input pullup).
- * PB5 - PIN5 (input pullup).
- * PB6 - PIN6 (input pullup).
- * PB7 - PIN7 (input pullup).
- * PB8 - PIN8 (input pullup).
- * PB9 - PIN9 (input pullup).
- * PB10 - PIN10 (input pullup).
- * PB11 - PIN11 (input pullup).
- * PB12 - PIN12 (input pullup).
- * PB13 - PIN13 (input pullup).
- * PB14 - PIN14 (input pullup).
- * PB15 - PIN15 (input pullup).
- */
-#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \
- PIN_MODE_INPUT(GPIOB_PIN1) | \
- PIN_MODE_INPUT(GPIOB_PIN2) | \
- PIN_MODE_ALTERNATE(GPIOB_SWO) | \
- PIN_MODE_INPUT(GPIOB_PIN4) | \
- PIN_MODE_INPUT(GPIOB_PIN5) | \
- PIN_MODE_INPUT(GPIOB_PIN6) | \
- PIN_MODE_INPUT(GPIOB_PIN7) | \
- PIN_MODE_INPUT(GPIOB_PIN8) | \
- PIN_MODE_INPUT(GPIOB_PIN9) | \
- PIN_MODE_INPUT(GPIOB_PIN10) | \
- PIN_MODE_INPUT(GPIOB_PIN11) | \
- PIN_MODE_INPUT(GPIOB_PIN12) | \
- PIN_MODE_INPUT(GPIOB_PIN13) | \
- PIN_MODE_INPUT(GPIOB_PIN14) | \
- PIN_MODE_INPUT(GPIOB_PIN15))
-#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \
- PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \
- PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
-#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_100M(GPIOB_PIN0) | \
- PIN_OSPEED_100M(GPIOB_PIN1) | \
- PIN_OSPEED_100M(GPIOB_PIN2) | \
- PIN_OSPEED_100M(GPIOB_SWO) | \
- PIN_OSPEED_100M(GPIOB_PIN4) | \
- PIN_OSPEED_100M(GPIOB_PIN5) | \
- PIN_OSPEED_100M(GPIOB_PIN6) | \
- PIN_OSPEED_100M(GPIOB_PIN7) | \
- PIN_OSPEED_100M(GPIOB_PIN8) | \
- PIN_OSPEED_100M(GPIOB_PIN9) | \
- PIN_OSPEED_100M(GPIOB_PIN10) | \
- PIN_OSPEED_100M(GPIOB_PIN11) | \
- PIN_OSPEED_100M(GPIOB_PIN12) | \
- PIN_OSPEED_100M(GPIOB_PIN13) | \
- PIN_OSPEED_100M(GPIOB_PIN14) | \
- PIN_OSPEED_100M(GPIOB_PIN15))
-#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN1) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN2) | \
- PIN_PUPDR_PULLUP(GPIOB_SWO) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN4) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN5) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN6) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN7) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN8) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN9) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN10) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN11) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN12) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN13) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN14) | \
- PIN_PUPDR_PULLUP(GPIOB_PIN15))
-#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \
- PIN_ODR_HIGH(GPIOB_PIN1) | \
- PIN_ODR_HIGH(GPIOB_PIN2) | \
- PIN_ODR_HIGH(GPIOB_SWO) | \
- PIN_ODR_HIGH(GPIOB_PIN4) | \
- PIN_ODR_HIGH(GPIOB_PIN5) | \
- PIN_ODR_HIGH(GPIOB_PIN6) | \
- PIN_ODR_HIGH(GPIOB_PIN7) | \
- PIN_ODR_HIGH(GPIOB_PIN8) | \
- PIN_ODR_HIGH(GPIOB_PIN9) | \
- PIN_ODR_HIGH(GPIOB_PIN10) | \
- PIN_ODR_HIGH(GPIOB_PIN11) | \
- PIN_ODR_HIGH(GPIOB_PIN12) | \
- PIN_ODR_HIGH(GPIOB_PIN13) | \
- PIN_ODR_HIGH(GPIOB_PIN14) | \
- PIN_ODR_HIGH(GPIOB_PIN15))
-#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0) | \
- PIN_AFIO_AF(GPIOB_PIN1, 0) | \
- PIN_AFIO_AF(GPIOB_PIN2, 0) | \
- PIN_AFIO_AF(GPIOB_SWO, 0) | \
- PIN_AFIO_AF(GPIOB_PIN4, 0) | \
- PIN_AFIO_AF(GPIOB_PIN5, 0) | \
- PIN_AFIO_AF(GPIOB_PIN6, 0) | \
- PIN_AFIO_AF(GPIOB_PIN7, 0))
-#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0) | \
- PIN_AFIO_AF(GPIOB_PIN9, 0) | \
- PIN_AFIO_AF(GPIOB_PIN10, 0) | \
- PIN_AFIO_AF(GPIOB_PIN11, 0) | \
- PIN_AFIO_AF(GPIOB_PIN12, 0) | \
- PIN_AFIO_AF(GPIOB_PIN13, 0) | \
- PIN_AFIO_AF(GPIOB_PIN14, 0) | \
- PIN_AFIO_AF(GPIOB_PIN15, 0))
-
-/*
- * GPIOC setup:
- *
- * PC0 - PIN0 (input pullup).
- * PC1 - PIN1 (input pullup).
- * PC2 - PIN2 (input pullup).
- * PC3 - PIN3 (input pullup).
- * PC4 - PIN4 (input pullup).
- * PC5 - PIN5 (input pullup).
- * PC6 - PIN6 (input pullup).
- * PC7 - PIN7 (input pullup).
- * PC8 - PIN8 (input pullup).
- * PC9 - PIN9 (input pullup).
- * PC10 - PIN10 (input pullup).
- * PC11 - PIN11 (input pullup).
- * PC12 - PIN12 (input pullup).
- * PC13 - BUTTON (input floating).
- * PC14 - PIN14 (input pullup).
- * PC15 - PIN15 (input pullup).
- */
-#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \
- PIN_MODE_INPUT(GPIOC_PIN1) | \
- PIN_MODE_INPUT(GPIOC_PIN2) | \
- PIN_MODE_INPUT(GPIOC_PIN3) | \
- PIN_MODE_INPUT(GPIOC_PIN4) | \
- PIN_MODE_INPUT(GPIOC_PIN5) | \
- PIN_MODE_INPUT(GPIOC_PIN6) | \
- PIN_MODE_INPUT(GPIOC_PIN7) | \
- PIN_MODE_INPUT(GPIOC_PIN8) | \
- PIN_MODE_INPUT(GPIOC_PIN9) | \
- PIN_MODE_INPUT(GPIOC_PIN10) | \
- PIN_MODE_INPUT(GPIOC_PIN11) | \
- PIN_MODE_INPUT(GPIOC_PIN12) | \
- PIN_MODE_INPUT(GPIOC_BUTTON) | \
- PIN_MODE_INPUT(GPIOC_PIN14) | \
- PIN_MODE_INPUT(GPIOC_PIN15))
-#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \
- PIN_OTYPE_PUSHPULL(GPIOC_BUTTON) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \
- PIN_OTYPE_PUSHPULL(GPIOC_PIN15))
-#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_100M(GPIOC_PIN0) | \
- PIN_OSPEED_100M(GPIOC_PIN1) | \
- PIN_OSPEED_100M(GPIOC_PIN2) | \
- PIN_OSPEED_100M(GPIOC_PIN3) | \
- PIN_OSPEED_100M(GPIOC_PIN4) | \
- PIN_OSPEED_100M(GPIOC_PIN5) | \
- PIN_OSPEED_100M(GPIOC_PIN6) | \
- PIN_OSPEED_100M(GPIOC_PIN7) | \
- PIN_OSPEED_100M(GPIOC_PIN8) | \
- PIN_OSPEED_100M(GPIOC_PIN9) | \
- PIN_OSPEED_100M(GPIOC_PIN10) | \
- PIN_OSPEED_100M(GPIOC_PIN11) | \
- PIN_OSPEED_100M(GPIOC_PIN12) | \
- PIN_OSPEED_100M(GPIOC_BUTTON) | \
- PIN_OSPEED_100M(GPIOC_PIN14) | \
- PIN_OSPEED_100M(GPIOC_PIN15))
-#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN1) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN2) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN3) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN4) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN5) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN6) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN7) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN8) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN9) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN10) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN11) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN12) | \
- PIN_PUPDR_FLOATING(GPIOC_BUTTON) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN14) | \
- PIN_PUPDR_PULLUP(GPIOC_PIN15))
-#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \
- PIN_ODR_HIGH(GPIOC_PIN1) | \
- PIN_ODR_HIGH(GPIOC_PIN2) | \
- PIN_ODR_HIGH(GPIOC_PIN3) | \
- PIN_ODR_HIGH(GPIOC_PIN4) | \
- PIN_ODR_HIGH(GPIOC_PIN5) | \
- PIN_ODR_HIGH(GPIOC_PIN6) | \
- PIN_ODR_HIGH(GPIOC_PIN7) | \
- PIN_ODR_HIGH(GPIOC_PIN8) | \
- PIN_ODR_HIGH(GPIOC_PIN9) | \
- PIN_ODR_HIGH(GPIOC_PIN10) | \
- PIN_ODR_HIGH(GPIOC_PIN11) | \
- PIN_ODR_HIGH(GPIOC_PIN12) | \
- PIN_ODR_HIGH(GPIOC_BUTTON) | \
- PIN_ODR_HIGH(GPIOC_PIN14) | \
- PIN_ODR_HIGH(GPIOC_PIN15))
-#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0) | \
- PIN_AFIO_AF(GPIOC_PIN1, 0) | \
- PIN_AFIO_AF(GPIOC_PIN2, 0) | \
- PIN_AFIO_AF(GPIOC_PIN3, 0) | \
- PIN_AFIO_AF(GPIOC_PIN4, 0) | \
- PIN_AFIO_AF(GPIOC_PIN5, 0) | \
- PIN_AFIO_AF(GPIOC_PIN6, 0) | \
- PIN_AFIO_AF(GPIOC_PIN7, 0))
-#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0) | \
- PIN_AFIO_AF(GPIOC_PIN9, 0) | \
- PIN_AFIO_AF(GPIOC_PIN10, 0) | \
- PIN_AFIO_AF(GPIOC_PIN11, 0) | \
- PIN_AFIO_AF(GPIOC_PIN12, 0) | \
- PIN_AFIO_AF(GPIOC_BUTTON, 0) | \
- PIN_AFIO_AF(GPIOC_PIN14, 0) | \
- PIN_AFIO_AF(GPIOC_PIN15, 0))
-
-/*
- * GPIOD setup:
- *
- * PD0 - PIN0 (input pullup).
- * PD1 - PIN1 (input pullup).
- * PD2 - PIN2 (input pullup).
- * PD3 - PIN3 (input pullup).
- * PD4 - PIN4 (input pullup).
- * PD5 - PIN5 (input pullup).
- * PD6 - PIN6 (input pullup).
- * PD7 - PIN7 (input pullup).
- * PD8 - PIN8 (input pullup).
- * PD9 - PIN9 (input pullup).
- * PD10 - PIN10 (input pullup).
- * PD11 - PIN11 (input pullup).
- * PD12 - PIN12 (input pullup).
- * PD13 - PIN13 (input pullup).
- * PD14 - PIN14 (input pullup).
- * PD15 - PIN15 (input pullup).
- */
-#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \
- PIN_MODE_INPUT(GPIOD_PIN1) | \
- PIN_MODE_INPUT(GPIOD_PIN2) | \
- PIN_MODE_INPUT(GPIOD_PIN3) | \
- PIN_MODE_INPUT(GPIOD_PIN4) | \
- PIN_MODE_INPUT(GPIOD_PIN5) | \
- PIN_MODE_INPUT(GPIOD_PIN6) | \
- PIN_MODE_INPUT(GPIOD_PIN7) | \
- PIN_MODE_INPUT(GPIOD_PIN8) | \
- PIN_MODE_INPUT(GPIOD_PIN9) | \
- PIN_MODE_INPUT(GPIOD_PIN10) | \
- PIN_MODE_INPUT(GPIOD_PIN11) | \
- PIN_MODE_INPUT(GPIOD_PIN12) | \
- PIN_MODE_INPUT(GPIOD_PIN13) | \
- PIN_MODE_INPUT(GPIOD_PIN14) | \
- PIN_MODE_INPUT(GPIOD_PIN15))
-#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \
- PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
-#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_100M(GPIOD_PIN0) | \
- PIN_OSPEED_100M(GPIOD_PIN1) | \
- PIN_OSPEED_100M(GPIOD_PIN2) | \
- PIN_OSPEED_100M(GPIOD_PIN3) | \
- PIN_OSPEED_100M(GPIOD_PIN4) | \
- PIN_OSPEED_100M(GPIOD_PIN5) | \
- PIN_OSPEED_100M(GPIOD_PIN6) | \
- PIN_OSPEED_100M(GPIOD_PIN7) | \
- PIN_OSPEED_100M(GPIOD_PIN8) | \
- PIN_OSPEED_100M(GPIOD_PIN9) | \
- PIN_OSPEED_100M(GPIOD_PIN10) | \
- PIN_OSPEED_100M(GPIOD_PIN11) | \
- PIN_OSPEED_100M(GPIOD_PIN12) | \
- PIN_OSPEED_100M(GPIOD_PIN13) | \
- PIN_OSPEED_100M(GPIOD_PIN14) | \
- PIN_OSPEED_100M(GPIOD_PIN15))
-#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN1) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN2) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN3) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN4) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN5) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN6) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN7) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN8) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN9) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN10) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN11) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN12) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN13) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN14) | \
- PIN_PUPDR_PULLUP(GPIOD_PIN15))
-#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \
- PIN_ODR_HIGH(GPIOD_PIN1) | \
- PIN_ODR_HIGH(GPIOD_PIN2) | \
- PIN_ODR_HIGH(GPIOD_PIN3) | \
- PIN_ODR_HIGH(GPIOD_PIN4) | \
- PIN_ODR_HIGH(GPIOD_PIN5) | \
- PIN_ODR_HIGH(GPIOD_PIN6) | \
- PIN_ODR_HIGH(GPIOD_PIN7) | \
- PIN_ODR_HIGH(GPIOD_PIN8) | \
- PIN_ODR_HIGH(GPIOD_PIN9) | \
- PIN_ODR_HIGH(GPIOD_PIN10) | \
- PIN_ODR_HIGH(GPIOD_PIN11) | \
- PIN_ODR_HIGH(GPIOD_PIN12) | \
- PIN_ODR_HIGH(GPIOD_PIN13) | \
- PIN_ODR_HIGH(GPIOD_PIN14) | \
- PIN_ODR_HIGH(GPIOD_PIN15))
-#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0) | \
- PIN_AFIO_AF(GPIOD_PIN1, 0) | \
- PIN_AFIO_AF(GPIOD_PIN2, 0) | \
- PIN_AFIO_AF(GPIOD_PIN3, 0) | \
- PIN_AFIO_AF(GPIOD_PIN4, 0) | \
- PIN_AFIO_AF(GPIOD_PIN5, 0) | \
- PIN_AFIO_AF(GPIOD_PIN6, 0) | \
- PIN_AFIO_AF(GPIOD_PIN7, 0))
-#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | \
- PIN_AFIO_AF(GPIOD_PIN9, 0) | \
- PIN_AFIO_AF(GPIOD_PIN10, 0) | \
- PIN_AFIO_AF(GPIOD_PIN11, 0) | \
- PIN_AFIO_AF(GPIOD_PIN12, 0) | \
- PIN_AFIO_AF(GPIOD_PIN13, 0) | \
- PIN_AFIO_AF(GPIOD_PIN14, 0) | \
- PIN_AFIO_AF(GPIOD_PIN15, 0))
-
-/*
- * GPIOE setup:
- *
- * PE0 - PIN0 (input pullup).
- * PE1 - PIN1 (input pullup).
- * PE2 - PIN2 (input floating).
- * PE3 - PIN3 (input pullup).
- * PE4 - PIN4 (input floating).
- * PE5 - PIN5 (input floating).
- * PE6 - PIN6 (input floating).
- * PE7 - PIN7 (input floating).
- * PE8 - PIN8 (input floating).
- * PE9 - PIN9 (input floating).
- * PE10 - PIN10 (input floating).
- * PE11 - PIN11 (input floating).
- * PE12 - PIN12 (input floating).
- * PE13 - PIN13 (input floating).
- * PE14 - PIN14 (input floating).
- * PE15 - PIN15 (input floating).
- */
-#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \
- PIN_MODE_INPUT(GPIOE_PIN1) | \
- PIN_MODE_INPUT(GPIOE_PIN2) | \
- PIN_MODE_INPUT(GPIOE_PIN3) | \
- PIN_MODE_INPUT(GPIOE_PIN4) | \
- PIN_MODE_INPUT(GPIOE_PIN5) | \
- PIN_MODE_INPUT(GPIOE_PIN6) | \
- PIN_MODE_INPUT(GPIOE_PIN7) | \
- PIN_MODE_INPUT(GPIOE_PIN8) | \
- PIN_MODE_INPUT(GPIOE_PIN9) | \
- PIN_MODE_INPUT(GPIOE_PIN10) | \
- PIN_MODE_INPUT(GPIOE_PIN11) | \
- PIN_MODE_INPUT(GPIOE_PIN12) | \
- PIN_MODE_INPUT(GPIOE_PIN13) | \
- PIN_MODE_INPUT(GPIOE_PIN14) | \
- PIN_MODE_INPUT(GPIOE_PIN15))
-#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \
- PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \
- PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \
- PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \
- PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \
- PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \
- PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \
- PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \
- PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \
- PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \
- PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \
- PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \
- PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \
- PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \
- PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \
- PIN_OTYPE_PUSHPULL(GPIOE_PIN15))
-#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_100M(GPIOE_PIN0) | \
- PIN_OSPEED_100M(GPIOE_PIN1) | \
- PIN_OSPEED_100M(GPIOE_PIN2) | \
- PIN_OSPEED_100M(GPIOE_PIN3) | \
- PIN_OSPEED_100M(GPIOE_PIN4) | \
- PIN_OSPEED_100M(GPIOE_PIN5) | \
- PIN_OSPEED_100M(GPIOE_PIN6) | \
- PIN_OSPEED_100M(GPIOE_PIN7) | \
- PIN_OSPEED_100M(GPIOE_PIN8) | \
- PIN_OSPEED_100M(GPIOE_PIN9) | \
- PIN_OSPEED_100M(GPIOE_PIN10) | \
- PIN_OSPEED_100M(GPIOE_PIN11) | \
- PIN_OSPEED_100M(GPIOE_PIN12) | \
- PIN_OSPEED_100M(GPIOE_PIN13) | \
- PIN_OSPEED_100M(GPIOE_PIN14) | \
- PIN_OSPEED_100M(GPIOE_PIN15))
-#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \
- PIN_PUPDR_PULLUP(GPIOE_PIN1) | \
- PIN_PUPDR_FLOATING(GPIOE_PIN2) | \
- PIN_PUPDR_PULLUP(GPIOE_PIN3) | \
- PIN_PUPDR_FLOATING(GPIOE_PIN4) | \
- PIN_PUPDR_FLOATING(GPIOE_PIN5) | \
- PIN_PUPDR_FLOATING(GPIOE_PIN6) | \
- PIN_PUPDR_FLOATING(GPIOE_PIN7) | \
- PIN_PUPDR_FLOATING(GPIOE_PIN8) | \
- PIN_PUPDR_FLOATING(GPIOE_PIN9) | \
- PIN_PUPDR_FLOATING(GPIOE_PIN10) | \
- PIN_PUPDR_FLOATING(GPIOE_PIN11) | \
- PIN_PUPDR_FLOATING(GPIOE_PIN12) | \
- PIN_PUPDR_FLOATING(GPIOE_PIN13) | \
- PIN_PUPDR_FLOATING(GPIOE_PIN14) | \
- PIN_PUPDR_FLOATING(GPIOE_PIN15))
-#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \
- PIN_ODR_HIGH(GPIOE_PIN1) | \
- PIN_ODR_HIGH(GPIOE_PIN2) | \
- PIN_ODR_HIGH(GPIOE_PIN3) | \
- PIN_ODR_HIGH(GPIOE_PIN4) | \
- PIN_ODR_HIGH(GPIOE_PIN5) | \
- PIN_ODR_HIGH(GPIOE_PIN6) | \
- PIN_ODR_HIGH(GPIOE_PIN7) | \
- PIN_ODR_HIGH(GPIOE_PIN8) | \
- PIN_ODR_HIGH(GPIOE_PIN9) | \
- PIN_ODR_HIGH(GPIOE_PIN10) | \
- PIN_ODR_HIGH(GPIOE_PIN11) | \
- PIN_ODR_HIGH(GPIOE_PIN12) | \
- PIN_ODR_HIGH(GPIOE_PIN13) | \
- PIN_ODR_HIGH(GPIOE_PIN14) | \
- PIN_ODR_HIGH(GPIOE_PIN15))
-#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0) | \
- PIN_AFIO_AF(GPIOE_PIN1, 0) | \
- PIN_AFIO_AF(GPIOE_PIN2, 0) | \
- PIN_AFIO_AF(GPIOE_PIN3, 0) | \
- PIN_AFIO_AF(GPIOE_PIN4, 0) | \
- PIN_AFIO_AF(GPIOE_PIN5, 0) | \
- PIN_AFIO_AF(GPIOE_PIN6, 0) | \
- PIN_AFIO_AF(GPIOE_PIN7, 0))
-#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0) | \
- PIN_AFIO_AF(GPIOE_PIN9, 0) | \
- PIN_AFIO_AF(GPIOE_PIN10, 0) | \
- PIN_AFIO_AF(GPIOE_PIN11, 0) | \
- PIN_AFIO_AF(GPIOE_PIN12, 0) | \
- PIN_AFIO_AF(GPIOE_PIN13, 0) | \
- PIN_AFIO_AF(GPIOE_PIN14, 0) | \
- PIN_AFIO_AF(GPIOE_PIN15, 0))
-
-/*
- * GPIOF setup:
- *
- * PF0 - PIN0 (input floating).
- * PF1 - PIN1 (input floating).
- * PF2 - PIN2 (input floating).
- * PF3 - PIN3 (input floating).
- * PF4 - PIN4 (input floating).
- * PF5 - PIN5 (input floating).
- * PF6 - PIN6 (input floating).
- * PF7 - PIN7 (input floating).
- * PF8 - PIN8 (input floating).
- * PF9 - PIN9 (input floating).
- * PF10 - PIN10 (input floating).
- * PF11 - PIN11 (input floating).
- * PF12 - PIN12 (input floating).
- * PF13 - PIN13 (input floating).
- * PF14 - PIN14 (input floating).
- * PF15 - PIN15 (input floating).
- */
-#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \
- PIN_MODE_INPUT(GPIOF_PIN1) | \
- PIN_MODE_INPUT(GPIOF_PIN2) | \
- PIN_MODE_INPUT(GPIOF_PIN3) | \
- PIN_MODE_INPUT(GPIOF_PIN4) | \
- PIN_MODE_INPUT(GPIOF_PIN5) | \
- PIN_MODE_INPUT(GPIOF_PIN6) | \
- PIN_MODE_INPUT(GPIOF_PIN7) | \
- PIN_MODE_INPUT(GPIOF_PIN8) | \
- PIN_MODE_INPUT(GPIOF_PIN9) | \
- PIN_MODE_INPUT(GPIOF_PIN10) | \
- PIN_MODE_INPUT(GPIOF_PIN11) | \
- PIN_MODE_INPUT(GPIOF_PIN12) | \
- PIN_MODE_INPUT(GPIOF_PIN13) | \
- PIN_MODE_INPUT(GPIOF_PIN14) | \
- PIN_MODE_INPUT(GPIOF_PIN15))
-#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \
- PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
-#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_100M(GPIOF_PIN0) | \
- PIN_OSPEED_100M(GPIOF_PIN1) | \
- PIN_OSPEED_100M(GPIOF_PIN2) | \
- PIN_OSPEED_100M(GPIOF_PIN3) | \
- PIN_OSPEED_100M(GPIOF_PIN4) | \
- PIN_OSPEED_100M(GPIOF_PIN5) | \
- PIN_OSPEED_100M(GPIOF_PIN6) | \
- PIN_OSPEED_100M(GPIOF_PIN7) | \
- PIN_OSPEED_100M(GPIOF_PIN8) | \
- PIN_OSPEED_100M(GPIOF_PIN9) | \
- PIN_OSPEED_100M(GPIOF_PIN10) | \
- PIN_OSPEED_100M(GPIOF_PIN11) | \
- PIN_OSPEED_100M(GPIOF_PIN12) | \
- PIN_OSPEED_100M(GPIOF_PIN13) | \
- PIN_OSPEED_100M(GPIOF_PIN14) | \
- PIN_OSPEED_100M(GPIOF_PIN15))
-#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_PIN0) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN1) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN2) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN3) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN4) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN5) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN6) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN7) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN8) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN9) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN10) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN11) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN12) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN13) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN14) | \
- PIN_PUPDR_FLOATING(GPIOF_PIN15))
-#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \
- PIN_ODR_HIGH(GPIOF_PIN1) | \
- PIN_ODR_HIGH(GPIOF_PIN2) | \
- PIN_ODR_HIGH(GPIOF_PIN3) | \
- PIN_ODR_HIGH(GPIOF_PIN4) | \
- PIN_ODR_HIGH(GPIOF_PIN5) | \
- PIN_ODR_HIGH(GPIOF_PIN6) | \
- PIN_ODR_HIGH(GPIOF_PIN7) | \
- PIN_ODR_HIGH(GPIOF_PIN8) | \
- PIN_ODR_HIGH(GPIOF_PIN9) | \
- PIN_ODR_HIGH(GPIOF_PIN10) | \
- PIN_ODR_HIGH(GPIOF_PIN11) | \
- PIN_ODR_HIGH(GPIOF_PIN12) | \
- PIN_ODR_HIGH(GPIOF_PIN13) | \
- PIN_ODR_HIGH(GPIOF_PIN14) | \
- PIN_ODR_HIGH(GPIOF_PIN15))
-#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0) | \
- PIN_AFIO_AF(GPIOF_PIN1, 0) | \
- PIN_AFIO_AF(GPIOF_PIN2, 0) | \
- PIN_AFIO_AF(GPIOF_PIN3, 0) | \
- PIN_AFIO_AF(GPIOF_PIN4, 0) | \
- PIN_AFIO_AF(GPIOF_PIN5, 0) | \
- PIN_AFIO_AF(GPIOF_PIN6, 0) | \
- PIN_AFIO_AF(GPIOF_PIN7, 0))
-#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \
- PIN_AFIO_AF(GPIOF_PIN9, 0) | \
- PIN_AFIO_AF(GPIOF_PIN10, 0) | \
- PIN_AFIO_AF(GPIOF_PIN11, 0) | \
- PIN_AFIO_AF(GPIOF_PIN12, 0) | \
- PIN_AFIO_AF(GPIOF_PIN13, 0) | \
- PIN_AFIO_AF(GPIOF_PIN14, 0) | \
- PIN_AFIO_AF(GPIOF_PIN15, 0))
-
-/*
- * GPIOG setup:
- *
- * PG0 - PIN0 (input floating).
- * PG1 - PIN1 (input floating).
- * PG2 - PIN2 (input floating).
- * PG3 - PIN3 (input floating).
- * PG4 - PIN4 (input floating).
- * PG5 - PIN5 (input floating).
- * PG6 - PIN6 (input floating).
- * PG7 - PIN7 (input floating).
- * PG8 - PIN8 (input floating).
- * PG9 - PIN9 (input floating).
- * PG10 - PIN10 (input floating).
- * PG11 - PIN11 (input floating).
- * PG12 - PIN12 (input floating).
- * PG13 - PIN13 (input floating).
- * PG14 - PIN14 (input floating).
- * PG15 - PIN15 (input floating).
- */
-#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_PIN0) | \
- PIN_MODE_INPUT(GPIOG_PIN1) | \
- PIN_MODE_INPUT(GPIOG_PIN2) | \
- PIN_MODE_INPUT(GPIOG_PIN3) | \
- PIN_MODE_INPUT(GPIOG_PIN4) | \
- PIN_MODE_INPUT(GPIOG_PIN5) | \
- PIN_MODE_INPUT(GPIOG_PIN6) | \
- PIN_MODE_INPUT(GPIOG_PIN7) | \
- PIN_MODE_INPUT(GPIOG_PIN8) | \
- PIN_MODE_INPUT(GPIOG_PIN9) | \
- PIN_MODE_INPUT(GPIOG_PIN10) | \
- PIN_MODE_INPUT(GPIOG_PIN11) | \
- PIN_MODE_INPUT(GPIOG_PIN12) | \
- PIN_MODE_INPUT(GPIOG_PIN13) | \
- PIN_MODE_INPUT(GPIOG_PIN14) | \
- PIN_MODE_INPUT(GPIOG_PIN15))
-#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(GPIOG_PIN0) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN1) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN2) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN3) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN4) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN5) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN6) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN7) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN8) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN9) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN10) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN11) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN12) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN13) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN14) | \
- PIN_OTYPE_PUSHPULL(GPIOG_PIN15))
-#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_100M(GPIOG_PIN0) | \
- PIN_OSPEED_100M(GPIOG_PIN1) | \
- PIN_OSPEED_100M(GPIOG_PIN2) | \
- PIN_OSPEED_100M(GPIOG_PIN3) | \
- PIN_OSPEED_100M(GPIOG_PIN4) | \
- PIN_OSPEED_100M(GPIOG_PIN5) | \
- PIN_OSPEED_100M(GPIOG_PIN6) | \
- PIN_OSPEED_100M(GPIOG_PIN7) | \
- PIN_OSPEED_100M(GPIOG_PIN8) | \
- PIN_OSPEED_100M(GPIOG_PIN9) | \
- PIN_OSPEED_100M(GPIOG_PIN10) | \
- PIN_OSPEED_100M(GPIOG_PIN11) | \
- PIN_OSPEED_100M(GPIOG_PIN12) | \
- PIN_OSPEED_100M(GPIOG_PIN13) | \
- PIN_OSPEED_100M(GPIOG_PIN14) | \
- PIN_OSPEED_100M(GPIOG_PIN15))
-#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_PIN0) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN1) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN2) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN3) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN4) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN5) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN6) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN7) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN8) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN9) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN10) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN11) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN12) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN13) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN14) | \
- PIN_PUPDR_FLOATING(GPIOG_PIN15))
-#define VAL_GPIOG_ODR (PIN_ODR_HIGH(GPIOG_PIN0) | \
- PIN_ODR_HIGH(GPIOG_PIN1) | \
- PIN_ODR_HIGH(GPIOG_PIN2) | \
- PIN_ODR_HIGH(GPIOG_PIN3) | \
- PIN_ODR_HIGH(GPIOG_PIN4) | \
- PIN_ODR_HIGH(GPIOG_PIN5) | \
- PIN_ODR_HIGH(GPIOG_PIN6) | \
- PIN_ODR_HIGH(GPIOG_PIN7) | \
- PIN_ODR_HIGH(GPIOG_PIN8) | \
- PIN_ODR_HIGH(GPIOG_PIN9) | \
- PIN_ODR_HIGH(GPIOG_PIN10) | \
- PIN_ODR_HIGH(GPIOG_PIN11) | \
- PIN_ODR_HIGH(GPIOG_PIN12) | \
- PIN_ODR_HIGH(GPIOG_PIN13) | \
- PIN_ODR_HIGH(GPIOG_PIN14) | \
- PIN_ODR_HIGH(GPIOG_PIN15))
-#define VAL_GPIOG_AFRL (PIN_AFIO_AF(GPIOG_PIN0, 0) | \
- PIN_AFIO_AF(GPIOG_PIN1, 0) | \
- PIN_AFIO_AF(GPIOG_PIN2, 0) | \
- PIN_AFIO_AF(GPIOG_PIN3, 0) | \
- PIN_AFIO_AF(GPIOG_PIN4, 0) | \
- PIN_AFIO_AF(GPIOG_PIN5, 0) | \
- PIN_AFIO_AF(GPIOG_PIN6, 0) | \
- PIN_AFIO_AF(GPIOG_PIN7, 0))
-#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_PIN8, 0) | \
- PIN_AFIO_AF(GPIOG_PIN9, 0) | \
- PIN_AFIO_AF(GPIOG_PIN10, 0) | \
- PIN_AFIO_AF(GPIOG_PIN11, 0) | \
- PIN_AFIO_AF(GPIOG_PIN12, 0) | \
- PIN_AFIO_AF(GPIOG_PIN13, 0) | \
- PIN_AFIO_AF(GPIOG_PIN14, 0) | \
- PIN_AFIO_AF(GPIOG_PIN15, 0))
-
-/*
- * GPIOH setup:
- *
- * PH0 - OSC_IN (input floating).
- * PH1 - OSC_OUT (input floating).
- * PH2 - PIN2 (input floating).
- * PH3 - PIN3 (input floating).
- * PH4 - PIN4 (input floating).
- * PH5 - PIN5 (input floating).
- * PH6 - PIN6 (input floating).
- * PH7 - PIN7 (input floating).
- * PH8 - PIN8 (input floating).
- * PH9 - PIN9 (input floating).
- * PH10 - PIN10 (input floating).
- * PH11 - PIN11 (input floating).
- * PH12 - PIN12 (input floating).
- * PH13 - PIN13 (input floating).
- * PH14 - PIN14 (input floating).
- * PH15 - PIN15 (input floating).
- */
-#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \
- PIN_MODE_INPUT(GPIOH_OSC_OUT) | \
- PIN_MODE_INPUT(GPIOH_PIN2) | \
- PIN_MODE_INPUT(GPIOH_PIN3) | \
- PIN_MODE_INPUT(GPIOH_PIN4) | \
- PIN_MODE_INPUT(GPIOH_PIN5) | \
- PIN_MODE_INPUT(GPIOH_PIN6) | \
- PIN_MODE_INPUT(GPIOH_PIN7) | \
- PIN_MODE_INPUT(GPIOH_PIN8) | \
- PIN_MODE_INPUT(GPIOH_PIN9) | \
- PIN_MODE_INPUT(GPIOH_PIN10) | \
- PIN_MODE_INPUT(GPIOH_PIN11) | \
- PIN_MODE_INPUT(GPIOH_PIN12) | \
- PIN_MODE_INPUT(GPIOH_PIN13) | \
- PIN_MODE_INPUT(GPIOH_PIN14) | \
- PIN_MODE_INPUT(GPIOH_PIN15))
-#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(GPIOH_OSC_IN) | \
- PIN_OTYPE_PUSHPULL(GPIOH_OSC_OUT) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN2) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN3) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN4) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN5) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN6) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN7) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN8) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN9) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN10) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN11) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN12) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN13) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN14) | \
- PIN_OTYPE_PUSHPULL(GPIOH_PIN15))
-#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_100M(GPIOH_OSC_IN) | \
- PIN_OSPEED_100M(GPIOH_OSC_OUT) | \
- PIN_OSPEED_100M(GPIOH_PIN2) | \
- PIN_OSPEED_100M(GPIOH_PIN3) | \
- PIN_OSPEED_100M(GPIOH_PIN4) | \
- PIN_OSPEED_100M(GPIOH_PIN5) | \
- PIN_OSPEED_100M(GPIOH_PIN6) | \
- PIN_OSPEED_100M(GPIOH_PIN7) | \
- PIN_OSPEED_100M(GPIOH_PIN8) | \
- PIN_OSPEED_100M(GPIOH_PIN9) | \
- PIN_OSPEED_100M(GPIOH_PIN10) | \
- PIN_OSPEED_100M(GPIOH_PIN11) | \
- PIN_OSPEED_100M(GPIOH_PIN12) | \
- PIN_OSPEED_100M(GPIOH_PIN13) | \
- PIN_OSPEED_100M(GPIOH_PIN14) | \
- PIN_OSPEED_100M(GPIOH_PIN15))
-#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(GPIOH_OSC_IN) | \
- PIN_PUPDR_FLOATING(GPIOH_OSC_OUT) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN2) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN3) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN4) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN5) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN6) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN7) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN8) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN9) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN10) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN11) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN12) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN13) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN14) | \
- PIN_PUPDR_FLOATING(GPIOH_PIN15))
-#define VAL_GPIOH_ODR (PIN_ODR_HIGH(GPIOH_OSC_IN) | \
- PIN_ODR_HIGH(GPIOH_OSC_OUT) | \
- PIN_ODR_HIGH(GPIOH_PIN2) | \
- PIN_ODR_HIGH(GPIOH_PIN3) | \
- PIN_ODR_HIGH(GPIOH_PIN4) | \
- PIN_ODR_HIGH(GPIOH_PIN5) | \
- PIN_ODR_HIGH(GPIOH_PIN6) | \
- PIN_ODR_HIGH(GPIOH_PIN7) | \
- PIN_ODR_HIGH(GPIOH_PIN8) | \
- PIN_ODR_HIGH(GPIOH_PIN9) | \
- PIN_ODR_HIGH(GPIOH_PIN10) | \
- PIN_ODR_HIGH(GPIOH_PIN11) | \
- PIN_ODR_HIGH(GPIOH_PIN12) | \
- PIN_ODR_HIGH(GPIOH_PIN13) | \
- PIN_ODR_HIGH(GPIOH_PIN14) | \
- PIN_ODR_HIGH(GPIOH_PIN15))
-#define VAL_GPIOH_AFRL (PIN_AFIO_AF(GPIOH_OSC_IN, 0) | \
- PIN_AFIO_AF(GPIOH_OSC_OUT, 0) | \
- PIN_AFIO_AF(GPIOH_PIN2, 0) | \
- PIN_AFIO_AF(GPIOH_PIN3, 0) | \
- PIN_AFIO_AF(GPIOH_PIN4, 0) | \
- PIN_AFIO_AF(GPIOH_PIN5, 0) | \
- PIN_AFIO_AF(GPIOH_PIN6, 0) | \
- PIN_AFIO_AF(GPIOH_PIN7, 0))
-#define VAL_GPIOH_AFRH (PIN_AFIO_AF(GPIOH_PIN8, 0) | \
- PIN_AFIO_AF(GPIOH_PIN9, 0) | \
- PIN_AFIO_AF(GPIOH_PIN10, 0) | \
- PIN_AFIO_AF(GPIOH_PIN11, 0) | \
- PIN_AFIO_AF(GPIOH_PIN12, 0) | \
- PIN_AFIO_AF(GPIOH_PIN13, 0) | \
- PIN_AFIO_AF(GPIOH_PIN14, 0) | \
- PIN_AFIO_AF(GPIOH_PIN15, 0))
-
-/*
- * GPIOI setup:
- *
- * PI0 - PIN0 (input floating).
- * PI1 - PIN1 (input floating).
- * PI2 - PIN2 (input floating).
- * PI3 - PIN3 (input floating).
- * PI4 - PIN4 (input floating).
- * PI5 - PIN5 (input floating).
- * PI6 - PIN6 (input floating).
- * PI7 - PIN7 (input floating).
- * PI8 - PIN8 (input floating).
- * PI9 - PIN9 (input floating).
- * PI10 - PIN10 (input floating).
- * PI11 - PIN11 (input floating).
- * PI12 - PIN12 (input floating).
- * PI13 - PIN13 (input floating).
- * PI14 - PIN14 (input floating).
- * PI15 - PIN15 (input floating).
- */
-#define VAL_GPIOI_MODER (PIN_MODE_INPUT(GPIOI_PIN0) | \
- PIN_MODE_INPUT(GPIOI_PIN1) | \
- PIN_MODE_INPUT(GPIOI_PIN2) | \
- PIN_MODE_INPUT(GPIOI_PIN3) | \
- PIN_MODE_INPUT(GPIOI_PIN4) | \
- PIN_MODE_INPUT(GPIOI_PIN5) | \
- PIN_MODE_INPUT(GPIOI_PIN6) | \
- PIN_MODE_INPUT(GPIOI_PIN7) | \
- PIN_MODE_INPUT(GPIOI_PIN8) | \
- PIN_MODE_INPUT(GPIOI_PIN9) | \
- PIN_MODE_INPUT(GPIOI_PIN10) | \
- PIN_MODE_INPUT(GPIOI_PIN11) | \
- PIN_MODE_INPUT(GPIOI_PIN12) | \
- PIN_MODE_INPUT(GPIOI_PIN13) | \
- PIN_MODE_INPUT(GPIOI_PIN14) | \
- PIN_MODE_INPUT(GPIOI_PIN15))
-#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(GPIOI_PIN0) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN1) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN2) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN3) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN4) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN5) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN6) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN7) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN8) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN9) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN10) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN11) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN12) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN13) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN14) | \
- PIN_OTYPE_PUSHPULL(GPIOI_PIN15))
-#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_100M(GPIOI_PIN0) | \
- PIN_OSPEED_100M(GPIOI_PIN1) | \
- PIN_OSPEED_100M(GPIOI_PIN2) | \
- PIN_OSPEED_100M(GPIOI_PIN3) | \
- PIN_OSPEED_100M(GPIOI_PIN4) | \
- PIN_OSPEED_100M(GPIOI_PIN5) | \
- PIN_OSPEED_100M(GPIOI_PIN6) | \
- PIN_OSPEED_100M(GPIOI_PIN7) | \
- PIN_OSPEED_100M(GPIOI_PIN8) | \
- PIN_OSPEED_100M(GPIOI_PIN9) | \
- PIN_OSPEED_100M(GPIOI_PIN10) | \
- PIN_OSPEED_100M(GPIOI_PIN11) | \
- PIN_OSPEED_100M(GPIOI_PIN12) | \
- PIN_OSPEED_100M(GPIOI_PIN13) | \
- PIN_OSPEED_100M(GPIOI_PIN14) | \
- PIN_OSPEED_100M(GPIOI_PIN15))
-#define VAL_GPIOI_PUPDR (PIN_PUPDR_FLOATING(GPIOI_PIN0) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN1) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN2) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN3) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN4) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN5) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN6) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN7) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN8) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN9) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN10) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN11) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN12) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN13) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN14) | \
- PIN_PUPDR_FLOATING(GPIOI_PIN15))
-#define VAL_GPIOI_ODR (PIN_ODR_HIGH(GPIOI_PIN0) | \
- PIN_ODR_HIGH(GPIOI_PIN1) | \
- PIN_ODR_HIGH(GPIOI_PIN2) | \
- PIN_ODR_HIGH(GPIOI_PIN3) | \
- PIN_ODR_HIGH(GPIOI_PIN4) | \
- PIN_ODR_HIGH(GPIOI_PIN5) | \
- PIN_ODR_HIGH(GPIOI_PIN6) | \
- PIN_ODR_HIGH(GPIOI_PIN7) | \
- PIN_ODR_HIGH(GPIOI_PIN8) | \
- PIN_ODR_HIGH(GPIOI_PIN9) | \
- PIN_ODR_HIGH(GPIOI_PIN10) | \
- PIN_ODR_HIGH(GPIOI_PIN11) | \
- PIN_ODR_HIGH(GPIOI_PIN12) | \
- PIN_ODR_HIGH(GPIOI_PIN13) | \
- PIN_ODR_HIGH(GPIOI_PIN14) | \
- PIN_ODR_HIGH(GPIOI_PIN15))
-#define VAL_GPIOI_AFRL (PIN_AFIO_AF(GPIOI_PIN0, 0) | \
- PIN_AFIO_AF(GPIOI_PIN1, 0) | \
- PIN_AFIO_AF(GPIOI_PIN2, 0) | \
- PIN_AFIO_AF(GPIOI_PIN3, 0) | \
- PIN_AFIO_AF(GPIOI_PIN4, 0) | \
- PIN_AFIO_AF(GPIOI_PIN5, 0) | \
- PIN_AFIO_AF(GPIOI_PIN6, 0) | \
- PIN_AFIO_AF(GPIOI_PIN7, 0))
-#define VAL_GPIOI_AFRH (PIN_AFIO_AF(GPIOI_PIN8, 0) | \
- PIN_AFIO_AF(GPIOI_PIN9, 0) | \
- PIN_AFIO_AF(GPIOI_PIN10, 0) | \
- PIN_AFIO_AF(GPIOI_PIN11, 0) | \
- PIN_AFIO_AF(GPIOI_PIN12, 0) | \
- PIN_AFIO_AF(GPIOI_PIN13, 0) | \
- PIN_AFIO_AF(GPIOI_PIN14, 0) | \
- PIN_AFIO_AF(GPIOI_PIN15, 0))
-
-
-#if !defined(_FROM_ASM_)
-#ifdef __cplusplus
-extern "C" {
-#endif
- void boardInit(void);
-#ifdef __cplusplus
-}
-#endif
-#endif /* _FROM_ASM_ */
-
-#endif /* _BOARD_H_ */
+/*
+ ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for STMicroelectronics NUCLEO-F334R8 board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_ST_NUCLEO_F334R8
+#define BOARD_NAME "STMicroelectronics NUCLEO-F334R8"
+
+/*
+ * Board oscillators-related settings.
+ * NOTE: LSE not fitted.
+ * NOTE: HSE not fitted.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK 0
+#endif
+
+#define STM32_LSEDRV (3 << 3)
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK 0
+#endif
+
+/*
+ * MCU type as defined in the ST header.
+ */
+#define STM32F334x8
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_PIN0 0
+#define GPIOA_PIN1 1
+#define GPIOA_USART_TX 2
+#define GPIOA_USART_RX 3
+#define GPIOA_PIN4 4
+#define GPIOA_LED_GREEN 5
+#define GPIOA_PIN6 6
+#define GPIOA_PIN7 7
+#define GPIOA_PIN8 8
+#define GPIOA_PIN9 9
+#define GPIOA_PIN10 10
+#define GPIOA_OTG_FS_DM 11
+#define GPIOA_OTG_FS_DP 12
+#define GPIOA_SWDIO 13
+#define GPIOA_SWCLK 14
+#define GPIOA_PIN15 15
+
+#define GPIOB_PIN0 0
+#define GPIOB_PIN1 1
+#define GPIOB_PIN2 2
+#define GPIOB_SWO 3
+#define GPIOB_PIN4 4
+#define GPIOB_PIN5 5
+#define GPIOB_PIN6 6
+#define GPIOB_PIN7 7
+#define GPIOB_PIN8 8
+#define GPIOB_PIN9 9
+#define GPIOB_PIN10 10
+#define GPIOB_PIN11 11
+#define GPIOB_PIN12 12
+#define GPIOB_PIN13 13
+#define GPIOB_PIN14 14
+#define GPIOB_PIN15 15
+
+#define GPIOC_PIN0 0
+#define GPIOC_PIN1 1
+#define GPIOC_PIN2 2
+#define GPIOC_PIN3 3
+#define GPIOC_PIN4 4
+#define GPIOC_PIN5 5
+#define GPIOC_PIN6 6
+#define GPIOC_PIN7 7
+#define GPIOC_PIN8 8
+#define GPIOC_PIN9 9
+#define GPIOC_PIN10 10
+#define GPIOC_PIN11 11
+#define GPIOC_PIN12 12
+#define GPIOC_BUTTON 13
+#define GPIOC_PIN14 14
+#define GPIOC_PIN15 15
+
+#define GPIOD_PIN0 0
+#define GPIOD_PIN1 1
+#define GPIOD_PIN2 2
+#define GPIOD_PIN3 3
+#define GPIOD_PIN4 4
+#define GPIOD_PIN5 5
+#define GPIOD_PIN6 6
+#define GPIOD_PIN7 7
+#define GPIOD_PIN8 8
+#define GPIOD_PIN9 9
+#define GPIOD_PIN10 10
+#define GPIOD_PIN11 11
+#define GPIOD_PIN12 12
+#define GPIOD_PIN13 13
+#define GPIOD_PIN14 14
+#define GPIOD_PIN15 15
+
+#define GPIOE_PIN0 0
+#define GPIOE_PIN1 1
+#define GPIOE_PIN2 2
+#define GPIOE_PIN3 3
+#define GPIOE_PIN4 4
+#define GPIOE_PIN5 5
+#define GPIOE_PIN6 6
+#define GPIOE_PIN7 7
+#define GPIOE_PIN8 8
+#define GPIOE_PIN9 9
+#define GPIOE_PIN10 10
+#define GPIOE_PIN11 11
+#define GPIOE_PIN12 12
+#define GPIOE_PIN13 13
+#define GPIOE_PIN14 14
+#define GPIOE_PIN15 15
+
+#define GPIOF_PIN0 0
+#define GPIOF_PIN1 1
+#define GPIOF_PIN2 2
+#define GPIOF_PIN3 3
+#define GPIOF_PIN4 4
+#define GPIOF_PIN5 5
+#define GPIOF_PIN6 6
+#define GPIOF_PIN7 7
+#define GPIOF_PIN8 8
+#define GPIOF_PIN9 9
+#define GPIOF_PIN10 10
+#define GPIOF_PIN11 11
+#define GPIOF_PIN12 12
+#define GPIOF_PIN13 13
+#define GPIOF_PIN14 14
+#define GPIOF_PIN15 15
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n) (0U << ((n) * 2))
+#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2))
+#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2))
+#define PIN_MODE_ANALOG(n) (3U << ((n) * 2))
+#define PIN_ODR_LOW(n) (0U << (n))
+#define PIN_ODR_HIGH(n) (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
+#define PIN_OSPEED_2M(n) (0U << ((n) * 2))
+#define PIN_OSPEED_25M(n) (1U << ((n) * 2))
+#define PIN_OSPEED_50M(n) (2U << ((n) * 2))
+#define PIN_OSPEED_100M(n) (3U << ((n) * 2))
+#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2))
+#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2))
+#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2))
+#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4))
+
+/*
+ * GPIOA setup:
+ *
+ * PA0 - PIN0 (input pullup).
+ * PA1 - PIN1 (input pullup).
+ * PA2 - USART_TX (alternate 7).
+ * PA3 - USART_RX (alternate 7).
+ * PA4 - PIN4 (input pullup).
+ * PA5 - LED_GREEN (output pushpull high).
+ * PA6 - PIN6 (input pullup).
+ * PA7 - PIN7 (input pullup).
+ * PA8 - PIN8 (input pullup).
+ * PA9 - PIN9 (input pullup).
+ * PA10 - PIN10 (input pullup).
+ * PA11 - OTG_FS_DM (alternate 10).
+ * PA12 - OTG_FS_DP (alternate 10).
+ * PA13 - SWDIO (alternate 0).
+ * PA14 - SWCLK (alternate 0).
+ * PA15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_PIN0) | \
+ PIN_MODE_INPUT(GPIOA_PIN1) | \
+ PIN_MODE_ALTERNATE(GPIOA_USART_TX) | \
+ PIN_MODE_ALTERNATE(GPIOA_USART_RX) | \
+ PIN_MODE_INPUT(GPIOA_PIN4) | \
+ PIN_MODE_OUTPUT(GPIOA_LED_GREEN) | \
+ PIN_MODE_INPUT(GPIOA_PIN6) | \
+ PIN_MODE_INPUT(GPIOA_PIN7) | \
+ PIN_MODE_INPUT(GPIOA_PIN8) | \
+ PIN_MODE_INPUT(GPIOA_PIN9) | \
+ PIN_MODE_INPUT(GPIOA_PIN10) | \
+ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \
+ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \
+ PIN_MODE_INPUT(GPIOA_PIN15))
+#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(GPIOA_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_USART_TX) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_USART_RX) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_LED_GREEN) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DM) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_OTG_FS_DP) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWDIO) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_SWCLK) | \
+ PIN_OTYPE_PUSHPULL(GPIOA_PIN15))
+#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_100M(GPIOA_PIN0) | \
+ PIN_OSPEED_100M(GPIOA_PIN1) | \
+ PIN_OSPEED_50M(GPIOA_USART_TX) | \
+ PIN_OSPEED_50M(GPIOA_USART_RX) | \
+ PIN_OSPEED_100M(GPIOA_PIN4) | \
+ PIN_OSPEED_50M(GPIOA_LED_GREEN) | \
+ PIN_OSPEED_100M(GPIOA_PIN6) | \
+ PIN_OSPEED_100M(GPIOA_PIN7) | \
+ PIN_OSPEED_100M(GPIOA_PIN8) | \
+ PIN_OSPEED_100M(GPIOA_PIN9) | \
+ PIN_OSPEED_100M(GPIOA_PIN10) | \
+ PIN_OSPEED_100M(GPIOA_OTG_FS_DM) | \
+ PIN_OSPEED_100M(GPIOA_OTG_FS_DP) | \
+ PIN_OSPEED_100M(GPIOA_SWDIO) | \
+ PIN_OSPEED_100M(GPIOA_SWCLK) | \
+ PIN_OSPEED_100M(GPIOA_PIN15))
+#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLUP(GPIOA_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOA_USART_TX) | \
+ PIN_PUPDR_FLOATING(GPIOA_USART_RX) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOA_LED_GREEN) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DM) | \
+ PIN_PUPDR_FLOATING(GPIOA_OTG_FS_DP) | \
+ PIN_PUPDR_PULLUP(GPIOA_SWDIO) | \
+ PIN_PUPDR_PULLDOWN(GPIOA_SWCLK) | \
+ PIN_PUPDR_PULLUP(GPIOA_PIN15))
+#define VAL_GPIOA_ODR (PIN_ODR_HIGH(GPIOA_PIN0) | \
+ PIN_ODR_HIGH(GPIOA_PIN1) | \
+ PIN_ODR_HIGH(GPIOA_USART_TX) | \
+ PIN_ODR_HIGH(GPIOA_USART_RX) | \
+ PIN_ODR_HIGH(GPIOA_PIN4) | \
+ PIN_ODR_LOW(GPIOA_LED_GREEN) | \
+ PIN_ODR_HIGH(GPIOA_PIN6) | \
+ PIN_ODR_HIGH(GPIOA_PIN7) | \
+ PIN_ODR_HIGH(GPIOA_PIN8) | \
+ PIN_ODR_HIGH(GPIOA_PIN9) | \
+ PIN_ODR_HIGH(GPIOA_PIN10) | \
+ PIN_ODR_HIGH(GPIOA_OTG_FS_DM) | \
+ PIN_ODR_HIGH(GPIOA_OTG_FS_DP) | \
+ PIN_ODR_HIGH(GPIOA_SWDIO) | \
+ PIN_ODR_HIGH(GPIOA_SWCLK) | \
+ PIN_ODR_HIGH(GPIOA_PIN15))
+#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOA_USART_TX, 7) | \
+ PIN_AFIO_AF(GPIOA_USART_RX, 7) | \
+ PIN_AFIO_AF(GPIOA_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOA_LED_GREEN, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN7, 0))
+#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) | \
+ PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) | \
+ PIN_AFIO_AF(GPIOA_SWDIO, 0) | \
+ PIN_AFIO_AF(GPIOA_SWCLK, 0) | \
+ PIN_AFIO_AF(GPIOA_PIN15, 0))
+
+/*
+ * GPIOB setup:
+ *
+ * PB0 - PIN0 (input pullup).
+ * PB1 - PIN1 (input pullup).
+ * PB2 - PIN2 (input pullup).
+ * PB3 - SWO (alternate 0).
+ * PB4 - PIN4 (input pullup).
+ * PB5 - PIN5 (input pullup).
+ * PB6 - PIN6 (input pullup).
+ * PB7 - PIN7 (input pullup).
+ * PB8 - PIN8 (input pullup).
+ * PB9 - PIN9 (input pullup).
+ * PB10 - PIN10 (input pullup).
+ * PB11 - PIN11 (input pullup).
+ * PB12 - PIN12 (input pullup).
+ * PB13 - PIN13 (input pullup).
+ * PB14 - PIN14 (input pullup).
+ * PB15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOB_MODER (PIN_MODE_INPUT(GPIOB_PIN0) | \
+ PIN_MODE_INPUT(GPIOB_PIN1) | \
+ PIN_MODE_INPUT(GPIOB_PIN2) | \
+ PIN_MODE_ALTERNATE(GPIOB_SWO) | \
+ PIN_MODE_INPUT(GPIOB_PIN4) | \
+ PIN_MODE_INPUT(GPIOB_PIN5) | \
+ PIN_MODE_INPUT(GPIOB_PIN6) | \
+ PIN_MODE_INPUT(GPIOB_PIN7) | \
+ PIN_MODE_INPUT(GPIOB_PIN8) | \
+ PIN_MODE_INPUT(GPIOB_PIN9) | \
+ PIN_MODE_INPUT(GPIOB_PIN10) | \
+ PIN_MODE_INPUT(GPIOB_PIN11) | \
+ PIN_MODE_INPUT(GPIOB_PIN12) | \
+ PIN_MODE_INPUT(GPIOB_PIN13) | \
+ PIN_MODE_INPUT(GPIOB_PIN14) | \
+ PIN_MODE_INPUT(GPIOB_PIN15))
+#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_SWO) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOB_PIN15))
+#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_100M(GPIOB_PIN0) | \
+ PIN_OSPEED_100M(GPIOB_PIN1) | \
+ PIN_OSPEED_100M(GPIOB_PIN2) | \
+ PIN_OSPEED_100M(GPIOB_SWO) | \
+ PIN_OSPEED_100M(GPIOB_PIN4) | \
+ PIN_OSPEED_100M(GPIOB_PIN5) | \
+ PIN_OSPEED_100M(GPIOB_PIN6) | \
+ PIN_OSPEED_100M(GPIOB_PIN7) | \
+ PIN_OSPEED_100M(GPIOB_PIN8) | \
+ PIN_OSPEED_100M(GPIOB_PIN9) | \
+ PIN_OSPEED_100M(GPIOB_PIN10) | \
+ PIN_OSPEED_100M(GPIOB_PIN11) | \
+ PIN_OSPEED_100M(GPIOB_PIN12) | \
+ PIN_OSPEED_100M(GPIOB_PIN13) | \
+ PIN_OSPEED_100M(GPIOB_PIN14) | \
+ PIN_OSPEED_100M(GPIOB_PIN15))
+#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLUP(GPIOB_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOB_SWO) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOB_PIN15))
+#define VAL_GPIOB_ODR (PIN_ODR_HIGH(GPIOB_PIN0) | \
+ PIN_ODR_HIGH(GPIOB_PIN1) | \
+ PIN_ODR_HIGH(GPIOB_PIN2) | \
+ PIN_ODR_HIGH(GPIOB_SWO) | \
+ PIN_ODR_HIGH(GPIOB_PIN4) | \
+ PIN_ODR_HIGH(GPIOB_PIN5) | \
+ PIN_ODR_HIGH(GPIOB_PIN6) | \
+ PIN_ODR_HIGH(GPIOB_PIN7) | \
+ PIN_ODR_HIGH(GPIOB_PIN8) | \
+ PIN_ODR_HIGH(GPIOB_PIN9) | \
+ PIN_ODR_HIGH(GPIOB_PIN10) | \
+ PIN_ODR_HIGH(GPIOB_PIN11) | \
+ PIN_ODR_HIGH(GPIOB_PIN12) | \
+ PIN_ODR_HIGH(GPIOB_PIN13) | \
+ PIN_ODR_HIGH(GPIOB_PIN14) | \
+ PIN_ODR_HIGH(GPIOB_PIN15))
+#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOB_SWO, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN7, 0))
+#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOB_PIN15, 0))
+
+/*
+ * GPIOC setup:
+ *
+ * PC0 - PIN0 (input pullup).
+ * PC1 - PIN1 (input pullup).
+ * PC2 - PIN2 (input pullup).
+ * PC3 - PIN3 (input pullup).
+ * PC4 - PIN4 (input pullup).
+ * PC5 - PIN5 (input pullup).
+ * PC6 - PIN6 (input pullup).
+ * PC7 - PIN7 (input pullup).
+ * PC8 - PIN8 (input pullup).
+ * PC9 - PIN9 (input pullup).
+ * PC10 - PIN10 (input pullup).
+ * PC11 - PIN11 (input pullup).
+ * PC12 - PIN12 (input pullup).
+ * PC13 - BUTTON (input floating).
+ * PC14 - PIN14 (input pullup).
+ * PC15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_PIN0) | \
+ PIN_MODE_INPUT(GPIOC_PIN1) | \
+ PIN_MODE_INPUT(GPIOC_PIN2) | \
+ PIN_MODE_INPUT(GPIOC_PIN3) | \
+ PIN_MODE_INPUT(GPIOC_PIN4) | \
+ PIN_MODE_INPUT(GPIOC_PIN5) | \
+ PIN_MODE_INPUT(GPIOC_PIN6) | \
+ PIN_MODE_INPUT(GPIOC_PIN7) | \
+ PIN_MODE_INPUT(GPIOC_PIN8) | \
+ PIN_MODE_INPUT(GPIOC_PIN9) | \
+ PIN_MODE_INPUT(GPIOC_PIN10) | \
+ PIN_MODE_INPUT(GPIOC_PIN11) | \
+ PIN_MODE_INPUT(GPIOC_PIN12) | \
+ PIN_MODE_INPUT(GPIOC_BUTTON) | \
+ PIN_MODE_INPUT(GPIOC_PIN14) | \
+ PIN_MODE_INPUT(GPIOC_PIN15))
+#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(GPIOC_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_BUTTON) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOC_PIN15))
+#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_100M(GPIOC_PIN0) | \
+ PIN_OSPEED_100M(GPIOC_PIN1) | \
+ PIN_OSPEED_100M(GPIOC_PIN2) | \
+ PIN_OSPEED_100M(GPIOC_PIN3) | \
+ PIN_OSPEED_100M(GPIOC_PIN4) | \
+ PIN_OSPEED_100M(GPIOC_PIN5) | \
+ PIN_OSPEED_100M(GPIOC_PIN6) | \
+ PIN_OSPEED_100M(GPIOC_PIN7) | \
+ PIN_OSPEED_100M(GPIOC_PIN8) | \
+ PIN_OSPEED_100M(GPIOC_PIN9) | \
+ PIN_OSPEED_100M(GPIOC_PIN10) | \
+ PIN_OSPEED_100M(GPIOC_PIN11) | \
+ PIN_OSPEED_100M(GPIOC_PIN12) | \
+ PIN_OSPEED_100M(GPIOC_BUTTON) | \
+ PIN_OSPEED_100M(GPIOC_PIN14) | \
+ PIN_OSPEED_100M(GPIOC_PIN15))
+#define VAL_GPIOC_PUPDR (PIN_PUPDR_PULLUP(GPIOC_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOC_BUTTON) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOC_PIN15))
+#define VAL_GPIOC_ODR (PIN_ODR_HIGH(GPIOC_PIN0) | \
+ PIN_ODR_HIGH(GPIOC_PIN1) | \
+ PIN_ODR_HIGH(GPIOC_PIN2) | \
+ PIN_ODR_HIGH(GPIOC_PIN3) | \
+ PIN_ODR_HIGH(GPIOC_PIN4) | \
+ PIN_ODR_HIGH(GPIOC_PIN5) | \
+ PIN_ODR_HIGH(GPIOC_PIN6) | \
+ PIN_ODR_HIGH(GPIOC_PIN7) | \
+ PIN_ODR_HIGH(GPIOC_PIN8) | \
+ PIN_ODR_HIGH(GPIOC_PIN9) | \
+ PIN_ODR_HIGH(GPIOC_PIN10) | \
+ PIN_ODR_HIGH(GPIOC_PIN11) | \
+ PIN_ODR_HIGH(GPIOC_PIN12) | \
+ PIN_ODR_HIGH(GPIOC_BUTTON) | \
+ PIN_ODR_HIGH(GPIOC_PIN14) | \
+ PIN_ODR_HIGH(GPIOC_PIN15))
+#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN7, 0))
+#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOC_BUTTON, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOC_PIN15, 0))
+
+/*
+ * GPIOD setup:
+ *
+ * PD0 - PIN0 (input pullup).
+ * PD1 - PIN1 (input pullup).
+ * PD2 - PIN2 (input pullup).
+ * PD3 - PIN3 (input pullup).
+ * PD4 - PIN4 (input pullup).
+ * PD5 - PIN5 (input pullup).
+ * PD6 - PIN6 (input pullup).
+ * PD7 - PIN7 (input pullup).
+ * PD8 - PIN8 (input pullup).
+ * PD9 - PIN9 (input pullup).
+ * PD10 - PIN10 (input pullup).
+ * PD11 - PIN11 (input pullup).
+ * PD12 - PIN12 (input pullup).
+ * PD13 - PIN13 (input pullup).
+ * PD14 - PIN14 (input pullup).
+ * PD15 - PIN15 (input pullup).
+ */
+#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_PIN0) | \
+ PIN_MODE_INPUT(GPIOD_PIN1) | \
+ PIN_MODE_INPUT(GPIOD_PIN2) | \
+ PIN_MODE_INPUT(GPIOD_PIN3) | \
+ PIN_MODE_INPUT(GPIOD_PIN4) | \
+ PIN_MODE_INPUT(GPIOD_PIN5) | \
+ PIN_MODE_INPUT(GPIOD_PIN6) | \
+ PIN_MODE_INPUT(GPIOD_PIN7) | \
+ PIN_MODE_INPUT(GPIOD_PIN8) | \
+ PIN_MODE_INPUT(GPIOD_PIN9) | \
+ PIN_MODE_INPUT(GPIOD_PIN10) | \
+ PIN_MODE_INPUT(GPIOD_PIN11) | \
+ PIN_MODE_INPUT(GPIOD_PIN12) | \
+ PIN_MODE_INPUT(GPIOD_PIN13) | \
+ PIN_MODE_INPUT(GPIOD_PIN14) | \
+ PIN_MODE_INPUT(GPIOD_PIN15))
+#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(GPIOD_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOD_PIN15))
+#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_100M(GPIOD_PIN0) | \
+ PIN_OSPEED_100M(GPIOD_PIN1) | \
+ PIN_OSPEED_100M(GPIOD_PIN2) | \
+ PIN_OSPEED_100M(GPIOD_PIN3) | \
+ PIN_OSPEED_100M(GPIOD_PIN4) | \
+ PIN_OSPEED_100M(GPIOD_PIN5) | \
+ PIN_OSPEED_100M(GPIOD_PIN6) | \
+ PIN_OSPEED_100M(GPIOD_PIN7) | \
+ PIN_OSPEED_100M(GPIOD_PIN8) | \
+ PIN_OSPEED_100M(GPIOD_PIN9) | \
+ PIN_OSPEED_100M(GPIOD_PIN10) | \
+ PIN_OSPEED_100M(GPIOD_PIN11) | \
+ PIN_OSPEED_100M(GPIOD_PIN12) | \
+ PIN_OSPEED_100M(GPIOD_PIN13) | \
+ PIN_OSPEED_100M(GPIOD_PIN14) | \
+ PIN_OSPEED_100M(GPIOD_PIN15))
+#define VAL_GPIOD_PUPDR (PIN_PUPDR_PULLUP(GPIOD_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN1) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN3) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN4) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN5) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN6) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN7) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN8) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN9) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN10) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN11) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN12) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN13) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN14) | \
+ PIN_PUPDR_PULLUP(GPIOD_PIN15))
+#define VAL_GPIOD_ODR (PIN_ODR_HIGH(GPIOD_PIN0) | \
+ PIN_ODR_HIGH(GPIOD_PIN1) | \
+ PIN_ODR_HIGH(GPIOD_PIN2) | \
+ PIN_ODR_HIGH(GPIOD_PIN3) | \
+ PIN_ODR_HIGH(GPIOD_PIN4) | \
+ PIN_ODR_HIGH(GPIOD_PIN5) | \
+ PIN_ODR_HIGH(GPIOD_PIN6) | \
+ PIN_ODR_HIGH(GPIOD_PIN7) | \
+ PIN_ODR_HIGH(GPIOD_PIN8) | \
+ PIN_ODR_HIGH(GPIOD_PIN9) | \
+ PIN_ODR_HIGH(GPIOD_PIN10) | \
+ PIN_ODR_HIGH(GPIOD_PIN11) | \
+ PIN_ODR_HIGH(GPIOD_PIN12) | \
+ PIN_ODR_HIGH(GPIOD_PIN13) | \
+ PIN_ODR_HIGH(GPIOD_PIN14) | \
+ PIN_ODR_HIGH(GPIOD_PIN15))
+#define VAL_GPIOD_AFRL (PIN_AFIO_AF(GPIOD_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN7, 0))
+#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOD_PIN15, 0))
+
+/*
+ * GPIOE setup:
+ *
+ * PE0 - PIN0 (input pullup).
+ * PE1 - PIN1 (input pullup).
+ * PE2 - PIN2 (input floating).
+ * PE3 - PIN3 (input pullup).
+ * PE4 - PIN4 (input floating).
+ * PE5 - PIN5 (input floating).
+ * PE6 - PIN6 (input floating).
+ * PE7 - PIN7 (input floating).
+ * PE8 - PIN8 (input floating).
+ * PE9 - PIN9 (input floating).
+ * PE10 - PIN10 (input floating).
+ * PE11 - PIN11 (input floating).
+ * PE12 - PIN12 (input floating).
+ * PE13 - PIN13 (input floating).
+ * PE14 - PIN14 (input floating).
+ * PE15 - PIN15 (input floating).
+ */
+#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_PIN0) | \
+ PIN_MODE_INPUT(GPIOE_PIN1) | \
+ PIN_MODE_INPUT(GPIOE_PIN2) | \
+ PIN_MODE_INPUT(GPIOE_PIN3) | \
+ PIN_MODE_INPUT(GPIOE_PIN4) | \
+ PIN_MODE_INPUT(GPIOE_PIN5) | \
+ PIN_MODE_INPUT(GPIOE_PIN6) | \
+ PIN_MODE_INPUT(GPIOE_PIN7) | \
+ PIN_MODE_INPUT(GPIOE_PIN8) | \
+ PIN_MODE_INPUT(GPIOE_PIN9) | \
+ PIN_MODE_INPUT(GPIOE_PIN10) | \
+ PIN_MODE_INPUT(GPIOE_PIN11) | \
+ PIN_MODE_INPUT(GPIOE_PIN12) | \
+ PIN_MODE_INPUT(GPIOE_PIN13) | \
+ PIN_MODE_INPUT(GPIOE_PIN14) | \
+ PIN_MODE_INPUT(GPIOE_PIN15))
+#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(GPIOE_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOE_PIN15))
+#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_100M(GPIOE_PIN0) | \
+ PIN_OSPEED_100M(GPIOE_PIN1) | \
+ PIN_OSPEED_100M(GPIOE_PIN2) | \
+ PIN_OSPEED_100M(GPIOE_PIN3) | \
+ PIN_OSPEED_100M(GPIOE_PIN4) | \
+ PIN_OSPEED_100M(GPIOE_PIN5) | \
+ PIN_OSPEED_100M(GPIOE_PIN6) | \
+ PIN_OSPEED_100M(GPIOE_PIN7) | \
+ PIN_OSPEED_100M(GPIOE_PIN8) | \
+ PIN_OSPEED_100M(GPIOE_PIN9) | \
+ PIN_OSPEED_100M(GPIOE_PIN10) | \
+ PIN_OSPEED_100M(GPIOE_PIN11) | \
+ PIN_OSPEED_100M(GPIOE_PIN12) | \
+ PIN_OSPEED_100M(GPIOE_PIN13) | \
+ PIN_OSPEED_100M(GPIOE_PIN14) | \
+ PIN_OSPEED_100M(GPIOE_PIN15))
+#define VAL_GPIOE_PUPDR (PIN_PUPDR_PULLUP(GPIOE_PIN0) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN2) | \
+ PIN_PUPDR_PULLUP(GPIOE_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOE_PIN15))
+#define VAL_GPIOE_ODR (PIN_ODR_HIGH(GPIOE_PIN0) | \
+ PIN_ODR_HIGH(GPIOE_PIN1) | \
+ PIN_ODR_HIGH(GPIOE_PIN2) | \
+ PIN_ODR_HIGH(GPIOE_PIN3) | \
+ PIN_ODR_HIGH(GPIOE_PIN4) | \
+ PIN_ODR_HIGH(GPIOE_PIN5) | \
+ PIN_ODR_HIGH(GPIOE_PIN6) | \
+ PIN_ODR_HIGH(GPIOE_PIN7) | \
+ PIN_ODR_HIGH(GPIOE_PIN8) | \
+ PIN_ODR_HIGH(GPIOE_PIN9) | \
+ PIN_ODR_HIGH(GPIOE_PIN10) | \
+ PIN_ODR_HIGH(GPIOE_PIN11) | \
+ PIN_ODR_HIGH(GPIOE_PIN12) | \
+ PIN_ODR_HIGH(GPIOE_PIN13) | \
+ PIN_ODR_HIGH(GPIOE_PIN14) | \
+ PIN_ODR_HIGH(GPIOE_PIN15))
+#define VAL_GPIOE_AFRL (PIN_AFIO_AF(GPIOE_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN7, 0))
+#define VAL_GPIOE_AFRH (PIN_AFIO_AF(GPIOE_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOE_PIN15, 0))
+
+/*
+ * GPIOF setup:
+ *
+ * PF0 - PIN0 (input floating).
+ * PF1 - PIN1 (input floating).
+ * PF2 - PIN2 (input floating).
+ * PF3 - PIN3 (input floating).
+ * PF4 - PIN4 (input floating).
+ * PF5 - PIN5 (input floating).
+ * PF6 - PIN6 (input floating).
+ * PF7 - PIN7 (input floating).
+ * PF8 - PIN8 (input floating).
+ * PF9 - PIN9 (input floating).
+ * PF10 - PIN10 (input floating).
+ * PF11 - PIN11 (input floating).
+ * PF12 - PIN12 (input floating).
+ * PF13 - PIN13 (input floating).
+ * PF14 - PIN14 (input floating).
+ * PF15 - PIN15 (input floating).
+ */
+#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_PIN0) | \
+ PIN_MODE_INPUT(GPIOF_PIN1) | \
+ PIN_MODE_INPUT(GPIOF_PIN2) | \
+ PIN_MODE_INPUT(GPIOF_PIN3) | \
+ PIN_MODE_INPUT(GPIOF_PIN4) | \
+ PIN_MODE_INPUT(GPIOF_PIN5) | \
+ PIN_MODE_INPUT(GPIOF_PIN6) | \
+ PIN_MODE_INPUT(GPIOF_PIN7) | \
+ PIN_MODE_INPUT(GPIOF_PIN8) | \
+ PIN_MODE_INPUT(GPIOF_PIN9) | \
+ PIN_MODE_INPUT(GPIOF_PIN10) | \
+ PIN_MODE_INPUT(GPIOF_PIN11) | \
+ PIN_MODE_INPUT(GPIOF_PIN12) | \
+ PIN_MODE_INPUT(GPIOF_PIN13) | \
+ PIN_MODE_INPUT(GPIOF_PIN14) | \
+ PIN_MODE_INPUT(GPIOF_PIN15))
+#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(GPIOF_PIN0) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN1) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN2) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN3) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN4) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN5) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN6) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN7) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN8) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN9) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN10) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN11) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN12) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN13) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN14) | \
+ PIN_OTYPE_PUSHPULL(GPIOF_PIN15))
+#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_100M(GPIOF_PIN0) | \
+ PIN_OSPEED_100M(GPIOF_PIN1) | \
+ PIN_OSPEED_100M(GPIOF_PIN2) | \
+ PIN_OSPEED_100M(GPIOF_PIN3) | \
+ PIN_OSPEED_100M(GPIOF_PIN4) | \
+ PIN_OSPEED_100M(GPIOF_PIN5) | \
+ PIN_OSPEED_100M(GPIOF_PIN6) | \
+ PIN_OSPEED_100M(GPIOF_PIN7) | \
+ PIN_OSPEED_100M(GPIOF_PIN8) | \
+ PIN_OSPEED_100M(GPIOF_PIN9) | \
+ PIN_OSPEED_100M(GPIOF_PIN10) | \
+ PIN_OSPEED_100M(GPIOF_PIN11) | \
+ PIN_OSPEED_100M(GPIOF_PIN12) | \
+ PIN_OSPEED_100M(GPIOF_PIN13) | \
+ PIN_OSPEED_100M(GPIOF_PIN14) | \
+ PIN_OSPEED_100M(GPIOF_PIN15))
+#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(GPIOF_PIN0) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN1) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN2) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN3) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN4) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN5) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN6) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN7) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN8) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN9) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN10) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN11) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN12) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN13) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN14) | \
+ PIN_PUPDR_FLOATING(GPIOF_PIN15))
+#define VAL_GPIOF_ODR (PIN_ODR_HIGH(GPIOF_PIN0) | \
+ PIN_ODR_HIGH(GPIOF_PIN1) | \
+ PIN_ODR_HIGH(GPIOF_PIN2) | \
+ PIN_ODR_HIGH(GPIOF_PIN3) | \
+ PIN_ODR_HIGH(GPIOF_PIN4) | \
+ PIN_ODR_HIGH(GPIOF_PIN5) | \
+ PIN_ODR_HIGH(GPIOF_PIN6) | \
+ PIN_ODR_HIGH(GPIOF_PIN7) | \
+ PIN_ODR_HIGH(GPIOF_PIN8) | \
+ PIN_ODR_HIGH(GPIOF_PIN9) | \
+ PIN_ODR_HIGH(GPIOF_PIN10) | \
+ PIN_ODR_HIGH(GPIOF_PIN11) | \
+ PIN_ODR_HIGH(GPIOF_PIN12) | \
+ PIN_ODR_HIGH(GPIOF_PIN13) | \
+ PIN_ODR_HIGH(GPIOF_PIN14) | \
+ PIN_ODR_HIGH(GPIOF_PIN15))
+#define VAL_GPIOF_AFRL (PIN_AFIO_AF(GPIOF_PIN0, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN1, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN2, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN3, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN4, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN5, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN6, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN7, 0))
+#define VAL_GPIOF_AFRH (PIN_AFIO_AF(GPIOF_PIN8, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN9, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN10, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN11, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN12, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN13, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN14, 0) | \
+ PIN_AFIO_AF(GPIOF_PIN15, 0))
+
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/ST_NUCLEO_F334R8/board.mk b/os/hal/boards/ST_NUCLEO_F334R8/board.mk
index a48f54f5c..299072cae 100644
--- a/os/hal/boards/ST_NUCLEO_F334R8/board.mk
+++ b/os/hal/boards/ST_NUCLEO_F334R8/board.mk
@@ -1,5 +1,5 @@
-# List of all the board related files.
-BOARDSRC = ${CHIBIOS}/os/hal/boards/ST_NUCLEO_F334R8/board.c
-
-# Required include directories
-BOARDINC = ${CHIBIOS}/os/hal/boards/ST_NUCLEO_F334R8
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/os/hal/boards/ST_NUCLEO_F334R8/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/os/hal/boards/ST_NUCLEO_F334R8
diff --git a/os/hal/boards/ST_NUCLEO_F334R8/cfg/board.chcfg b/os/hal/boards/ST_NUCLEO_F334R8/cfg/board.chcfg
index 3c1a61d51..1b15885e5 100644
--- a/os/hal/boards/ST_NUCLEO_F334R8/cfg/board.chcfg
+++ b/os/hal/boards/ST_NUCLEO_F334R8/cfg/board.chcfg
@@ -2,21 +2,18 @@
<!-- STM32F4xx board Template -->
<board
xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
- xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32f4xx_board.xsd">
+ xsi:noNamespaceSchemaLocation="http://www.chibios.org/xml/schema/boards/stm32f3xx_board.xsd">
<configuration_settings>
- <templates_path>resources/gencfg/processors/boards/stm32f4xx/templates</templates_path>
+ <templates_path>resources/gencfg/processors/boards/stm32f3xx/templates</templates_path>
<output_path>..</output_path>
+ <hal_version>3.0.x</hal_version>
</configuration_settings>
- <board_name>STMicroelectronics NUCLEO-F401RE</board_name>
- <board_id>ST_NUCLEO_F401RE</board_id>
+ <board_name>STMicroelectronics NUCLEO-F334R8</board_name>
+ <board_id>ST_NUCLEO_F334R8</board_id>
<board_functions></board_functions>
- <subtype>STM32F334xx</subtype>
- <clocks
- HSEFrequency="0"
- HSEBypass="false"
- LSEFrequency="0"
- LSEBypass="false"
- VDD="300" />
+ <subtype>STM32F334x8</subtype>
+ <clocks HSEFrequency="0" HSEBypass="false" LSEFrequency="0"
+ LSEBypass="false" LSEDrive="3 High Drive (default)" />
<ports>
<GPIOA>
<pin0
@@ -798,395 +795,5 @@
Mode="Input"
Alternate="0" />
</GPIOF>
- <GPIOG>
- <pin0
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin1
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin2
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin3
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin4
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin5
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin6
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin7
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin8
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin9
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin10
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin11
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin12
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin13
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin14
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin15
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- </GPIOG>
- <GPIOH>
- <pin0
- ID="OSC_IN"
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin1
- ID="OSC_OUT"
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin2
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" ></pin2>
- <pin3
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin4
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin5
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin6
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin7
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin8
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin9
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin10
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin11
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin12
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin13
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin14
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin15
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- </GPIOH>
- <GPIOI>
- <pin0
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin1
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin2
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin3
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin4
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin5
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin6
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin7
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin8
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin9
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin10
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin11
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin12
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin13
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin14
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- <pin15
- ID=""
- Type="PushPull"
- Level="High"
- Speed="Maximum"
- Resistor="Floating"
- Mode="Input"
- Alternate="0" />
- </GPIOI>
</ports>
</board>
diff --git a/os/hal/boards/ST_NUCLEO_F401RE/board.c b/os/hal/boards/ST_NUCLEO_F401RE/board.c
index 5ce2ac971..6eb610254 100644
--- a/os/hal/boards/ST_NUCLEO_F401RE/board.c
+++ b/os/hal/boards/ST_NUCLEO_F401RE/board.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -22,8 +22,7 @@
* @details Digital I/O ports static configuration as defined in @p board.h.
* This variable is used by the HAL when initializing the PAL driver.
*/
-const PALConfig pal_default_config =
-{
+const PALConfig pal_default_config = {
#if STM32_HAS_GPIOA
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
@@ -81,7 +80,7 @@ bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
(void)sdcp;
/* TODO: Fill the implementation.*/
- return TRUE;
+ return true;
}
/**
@@ -91,7 +90,7 @@ bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
(void)sdcp;
/* TODO: Fill the implementation.*/
- return FALSE;
+ return false;
}
#endif /* HAL_USE_SDC */
@@ -103,7 +102,7 @@ bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
- return TRUE;
+ return true;
}
/**
@@ -113,7 +112,7 @@ bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
- return FALSE;
+ return false;
}
#endif
diff --git a/os/hal/boards/ST_NUCLEO_F401RE/board.h b/os/hal/boards/ST_NUCLEO_F401RE/board.h
index 9d41a25b7..f63afbf81 100644
--- a/os/hal/boards/ST_NUCLEO_F401RE/board.h
+++ b/os/hal/boards/ST_NUCLEO_F401RE/board.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
diff --git a/os/hal/boards/ST_NUCLEO_F401RE/cfg/board.chcfg b/os/hal/boards/ST_NUCLEO_F401RE/cfg/board.chcfg
index 47c99fffd..e2a9ecc08 100644
--- a/os/hal/boards/ST_NUCLEO_F401RE/cfg/board.chcfg
+++ b/os/hal/boards/ST_NUCLEO_F401RE/cfg/board.chcfg
@@ -6,11 +6,12 @@
<configuration_settings>
<templates_path>resources/gencfg/processors/boards/stm32f4xx/templates</templates_path>
<output_path>..</output_path>
+ <hal_version>3.0.x</hal_version>
</configuration_settings>
<board_name>STMicroelectronics NUCLEO-F401RE</board_name>
<board_id>ST_NUCLEO_F401RE</board_id>
<board_functions></board_functions>
- <subtype>STM32F401xx</subtype>
+ <subtype>STM32F401xE</subtype>
<clocks
HSEFrequency="0"
HSEBypass="false"
diff --git a/os/hal/boards/ST_NUCLEO_L152RE/board.c b/os/hal/boards/ST_NUCLEO_L152RE/board.c
index 97045af60..6eb610254 100644
--- a/os/hal/boards/ST_NUCLEO_L152RE/board.c
+++ b/os/hal/boards/ST_NUCLEO_L152RE/board.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -53,7 +53,7 @@ const PALConfig pal_default_config = {
#endif
#if STM32_HAS_GPIOH
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
- VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}
+ VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
#endif
#if STM32_HAS_GPIOI
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
@@ -80,7 +80,7 @@ bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
(void)sdcp;
/* TODO: Fill the implementation.*/
- return TRUE;
+ return true;
}
/**
@@ -90,7 +90,7 @@ bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
(void)sdcp;
/* TODO: Fill the implementation.*/
- return FALSE;
+ return false;
}
#endif /* HAL_USE_SDC */
@@ -102,7 +102,7 @@ bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
- return TRUE;
+ return true;
}
/**
@@ -112,7 +112,7 @@ bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
- return FALSE;
+ return false;
}
#endif
diff --git a/os/hal/boards/ST_NUCLEO_L152RE/board.h b/os/hal/boards/ST_NUCLEO_L152RE/board.h
index 00c0dc1d5..19bd72fc6 100644
--- a/os/hal/boards/ST_NUCLEO_L152RE/board.h
+++ b/os/hal/boards/ST_NUCLEO_L152RE/board.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
diff --git a/os/hal/boards/ST_NUCLEO_L152RE/cfg/board.chcfg b/os/hal/boards/ST_NUCLEO_L152RE/cfg/board.chcfg
index 66cc63ecf..9d3aa869c 100644
--- a/os/hal/boards/ST_NUCLEO_L152RE/cfg/board.chcfg
+++ b/os/hal/boards/ST_NUCLEO_L152RE/cfg/board.chcfg
@@ -6,6 +6,7 @@
<configuration_settings>
<templates_path>resources/gencfg/processors/boards/stm32l1xx/templates</templates_path>
<output_path>..</output_path>
+ <hal_version>3.0.x</hal_version>
</configuration_settings>
<board_name>STMicroelectronics NUCLEO-L152RE</board_name>
<board_id>ST_NUCLEO_L152RE</board_id>
diff --git a/os/hal/boards/ST_STM32373C_EVAL/board.c b/os/hal/boards/ST_STM32373C_EVAL/board.c
index 4edfdb55c..6eb610254 100644
--- a/os/hal/boards/ST_STM32373C_EVAL/board.c
+++ b/os/hal/boards/ST_STM32373C_EVAL/board.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -22,20 +22,43 @@
* @details Digital I/O ports static configuration as defined in @p board.h.
* This variable is used by the HAL when initializing the PAL driver.
*/
-const PALConfig pal_default_config =
-{
+const PALConfig pal_default_config = {
+#if STM32_HAS_GPIOA
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+#endif
+#if STM32_HAS_GPIOB
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+#endif
+#if STM32_HAS_GPIOC
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+#endif
+#if STM32_HAS_GPIOD
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+#endif
+#if STM32_HAS_GPIOE
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+#endif
+#if STM32_HAS_GPIOF
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
- VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}
+ VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
+#endif
+#if STM32_HAS_GPIOG
+ {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+ VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
+#endif
+#if STM32_HAS_GPIOH
+ {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+ VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
+#endif
+#if STM32_HAS_GPIOI
+ {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+ VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
+#endif
};
#endif
@@ -57,7 +80,7 @@ bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
(void)sdcp;
/* TODO: Fill the implementation.*/
- return TRUE;
+ return true;
}
/**
@@ -67,7 +90,7 @@ bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
(void)sdcp;
/* TODO: Fill the implementation.*/
- return FALSE;
+ return false;
}
#endif /* HAL_USE_SDC */
@@ -79,7 +102,7 @@ bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
- return TRUE;
+ return true;
}
/**
@@ -89,7 +112,7 @@ bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
- return FALSE;
+ return false;
}
#endif
diff --git a/os/hal/boards/ST_STM32373C_EVAL/board.h b/os/hal/boards/ST_STM32373C_EVAL/board.h
index 863242331..95a842cae 100644
--- a/os/hal/boards/ST_STM32373C_EVAL/board.h
+++ b/os/hal/boards/ST_STM32373C_EVAL/board.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
diff --git a/os/hal/boards/ST_STM32373C_EVAL/cfg/board.chcfg b/os/hal/boards/ST_STM32373C_EVAL/cfg/board.chcfg
index 85f428ef8..d7c9f4e77 100644
--- a/os/hal/boards/ST_STM32373C_EVAL/cfg/board.chcfg
+++ b/os/hal/boards/ST_STM32373C_EVAL/cfg/board.chcfg
@@ -6,11 +6,12 @@
<configuration_settings>
<templates_path>resources/gencfg/processors/boards/stm32f3xx/templates</templates_path>
<output_path>..</output_path>
+ <hal_version>3.0.x</hal_version>
</configuration_settings>
<board_name>STMicroelectronics STM32373C-EVAL</board_name>
<board_id>ST_STM32373C_EVAL</board_id>
<board_functions></board_functions>
- <subtype>STM32F37X</subtype>
+ <subtype>STM32F373xC</subtype>
<clocks HSEFrequency="8000000" HSEBypass="false" LSEFrequency="32768"
LSEBypass="false" LSEDrive="3 High Drive (default)" />
<ports>
diff --git a/os/hal/boards/ST_STM32F072B_DISCOVERY/board.c b/os/hal/boards/ST_STM32F072B_DISCOVERY/board.c
index 6d473d2d7..dc058f60d 100644
--- a/os/hal/boards/ST_STM32F072B_DISCOVERY/board.c
+++ b/os/hal/boards/ST_STM32F072B_DISCOVERY/board.c
@@ -53,7 +53,7 @@ const PALConfig pal_default_config = {
#endif
#if STM32_HAS_GPIOH
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
- VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}
+ VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
#endif
#if STM32_HAS_GPIOI
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
diff --git a/os/hal/boards/ST_STM32F072B_DISCOVERY/board.h b/os/hal/boards/ST_STM32F072B_DISCOVERY/board.h
index 1ebab059b..e106b5bec 100644
--- a/os/hal/boards/ST_STM32F072B_DISCOVERY/board.h
+++ b/os/hal/boards/ST_STM32F072B_DISCOVERY/board.h
@@ -18,14 +18,14 @@
#define _BOARD_H_
/*
- * Setup for ST STM32F072-Discovery board.
+ * Setup for ST STM32F072B-Discovery board.
*/
/*
* Board identifier.
*/
-#define BOARD_ST_STM32F072_DISCOVERY
-#define BOARD_NAME "ST STM32F072-Discovery"
+#define BOARD_ST_STM32F072B_DISCOVERY
+#define BOARD_NAME "ST STM32F072B-Discovery"
/*
* Board oscillators-related settings.
diff --git a/os/hal/boards/ST_STM32F072B_DISCOVERY/board.mk b/os/hal/boards/ST_STM32F072B_DISCOVERY/board.mk
index 1b5c0aedb..dcdfcaa94 100644
--- a/os/hal/boards/ST_STM32F072B_DISCOVERY/board.mk
+++ b/os/hal/boards/ST_STM32F072B_DISCOVERY/board.mk
@@ -1,5 +1,5 @@
# List of all the board related files.
-BOARDSRC = ${CHIBIOS}/os/hal/boards/ST_STM32F072_DISCOVERY/board.c
+BOARDSRC = ${CHIBIOS}/os/hal/boards/ST_STM32F072B_DISCOVERY/board.c
# Required include directories
-BOARDINC = ${CHIBIOS}/os/hal/boards/ST_STM32F072_DISCOVERY
+BOARDINC = ${CHIBIOS}/os/hal/boards/ST_STM32F072B_DISCOVERY
diff --git a/os/hal/boards/ST_STM32F072B_DISCOVERY/cfg/board.chcfg b/os/hal/boards/ST_STM32F072B_DISCOVERY/cfg/board.chcfg
index 63b855a10..78f391780 100644
--- a/os/hal/boards/ST_STM32F072B_DISCOVERY/cfg/board.chcfg
+++ b/os/hal/boards/ST_STM32F072B_DISCOVERY/cfg/board.chcfg
@@ -6,9 +6,10 @@
<configuration_settings>
<templates_path>resources/gencfg/processors/boards/stm32f0xx/templates</templates_path>
<output_path>..</output_path>
+ <hal_version>3.0.x</hal_version>
</configuration_settings>
- <board_name>ST STM32F072-Discovery</board_name>
- <board_id>ST_STM32F072_DISCOVERY</board_id>
+ <board_name>ST STM32F072B-Discovery</board_name>
+ <board_id>ST_STM32F072B_DISCOVERY</board_id>
<board_functions></board_functions>
<subtype>STM32F072xB</subtype>
<clocks HSEFrequency="0" HSEBypass="true" LSEFrequency="0"
diff --git a/os/hal/boards/ST_STM32F0_DISCOVERY/board.c b/os/hal/boards/ST_STM32F0_DISCOVERY/board.c
index 8ed20fcb4..dc058f60d 100644
--- a/os/hal/boards/ST_STM32F0_DISCOVERY/board.c
+++ b/os/hal/boards/ST_STM32F0_DISCOVERY/board.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -22,18 +22,43 @@
* @details Digital I/O ports static configuration as defined in @p board.h.
* This variable is used by the HAL when initializing the PAL driver.
*/
-const PALConfig pal_default_config =
-{
+const PALConfig pal_default_config = {
+#if STM32_HAS_GPIOA
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+#endif
+#if STM32_HAS_GPIOB
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+#endif
+#if STM32_HAS_GPIOC
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+#endif
+#if STM32_HAS_GPIOD
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+#endif
+#if STM32_HAS_GPIOE
+ {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
+ VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+#endif
+#if STM32_HAS_GPIOF
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
- VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}
+ VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
+#endif
+#if STM32_HAS_GPIOG
+ {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+ VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
+#endif
+#if STM32_HAS_GPIOH
+ {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+ VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
+#endif
+#if STM32_HAS_GPIOI
+ {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+ VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
+#endif
};
#endif
@@ -55,7 +80,7 @@ bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
- return TRUE;
+ return true;
}
/**
@@ -65,7 +90,7 @@ bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
- return FALSE;
+ return false;
}
#endif
diff --git a/os/hal/boards/ST_STM32F0_DISCOVERY/board.h b/os/hal/boards/ST_STM32F0_DISCOVERY/board.h
index 5ae77a5a1..89b0a3b2d 100644
--- a/os/hal/boards/ST_STM32F0_DISCOVERY/board.h
+++ b/os/hal/boards/ST_STM32F0_DISCOVERY/board.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
diff --git a/os/hal/boards/ST_STM32F0_DISCOVERY/cfg/board.chcfg b/os/hal/boards/ST_STM32F0_DISCOVERY/cfg/board.chcfg
index ec85130c7..c01fcc480 100644
--- a/os/hal/boards/ST_STM32F0_DISCOVERY/cfg/board.chcfg
+++ b/os/hal/boards/ST_STM32F0_DISCOVERY/cfg/board.chcfg
@@ -6,11 +6,12 @@
<configuration_settings>
<templates_path>resources/gencfg/processors/boards/stm32f0xx/templates</templates_path>
<output_path>..</output_path>
+ <hal_version>3.0.x</hal_version>
</configuration_settings>
<board_name>ST STM32F0-Discovery</board_name>
<board_id>ST_STM32F0_DISCOVERY</board_id>
<board_functions></board_functions>
- <subtype>STM32F0XX_MD</subtype>
+ <subtype>STM32F051x8</subtype>
<clocks HSEFrequency="0" HSEBypass="true" LSEFrequency="0"
LSEBypass="false" LSEDrive="3 High Drive (default)" />
<ports>
diff --git a/os/hal/boards/ST_STM32F3_DISCOVERY/board.c b/os/hal/boards/ST_STM32F3_DISCOVERY/board.c
index 4edfdb55c..6eb610254 100644
--- a/os/hal/boards/ST_STM32F3_DISCOVERY/board.c
+++ b/os/hal/boards/ST_STM32F3_DISCOVERY/board.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -22,20 +22,43 @@
* @details Digital I/O ports static configuration as defined in @p board.h.
* This variable is used by the HAL when initializing the PAL driver.
*/
-const PALConfig pal_default_config =
-{
+const PALConfig pal_default_config = {
+#if STM32_HAS_GPIOA
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+#endif
+#if STM32_HAS_GPIOB
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+#endif
+#if STM32_HAS_GPIOC
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+#endif
+#if STM32_HAS_GPIOD
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+#endif
+#if STM32_HAS_GPIOE
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+#endif
+#if STM32_HAS_GPIOF
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
- VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}
+ VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
+#endif
+#if STM32_HAS_GPIOG
+ {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+ VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
+#endif
+#if STM32_HAS_GPIOH
+ {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
+ VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
+#endif
+#if STM32_HAS_GPIOI
+ {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+ VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
+#endif
};
#endif
@@ -57,7 +80,7 @@ bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
(void)sdcp;
/* TODO: Fill the implementation.*/
- return TRUE;
+ return true;
}
/**
@@ -67,7 +90,7 @@ bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
(void)sdcp;
/* TODO: Fill the implementation.*/
- return FALSE;
+ return false;
}
#endif /* HAL_USE_SDC */
@@ -79,7 +102,7 @@ bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
- return TRUE;
+ return true;
}
/**
@@ -89,7 +112,7 @@ bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
- return FALSE;
+ return false;
}
#endif
diff --git a/os/hal/boards/ST_STM32F3_DISCOVERY/board.h b/os/hal/boards/ST_STM32F3_DISCOVERY/board.h
index 84ba8fe1b..1c5767cba 100644
--- a/os/hal/boards/ST_STM32F3_DISCOVERY/board.h
+++ b/os/hal/boards/ST_STM32F3_DISCOVERY/board.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
diff --git a/os/hal/boards/ST_STM32F3_DISCOVERY/cfg/board.chcfg b/os/hal/boards/ST_STM32F3_DISCOVERY/cfg/board.chcfg
index cbd264d03..ea03565c7 100644
--- a/os/hal/boards/ST_STM32F3_DISCOVERY/cfg/board.chcfg
+++ b/os/hal/boards/ST_STM32F3_DISCOVERY/cfg/board.chcfg
@@ -6,11 +6,12 @@
<configuration_settings>
<templates_path>resources/gencfg/processors/boards/stm32f3xx/templates</templates_path>
<output_path>..</output_path>
+ <hal_version>3.0.x</hal_version>
</configuration_settings>
<board_name>STMicroelectronics STM32F3-Discovery</board_name>
<board_id>ST_STM32F3_DISCOVERY</board_id>
<board_functions></board_functions>
- <subtype>STM32F30X</subtype>
+ <subtype>STM32F303xC</subtype>
<clocks HSEFrequency="8000000" HSEBypass="true" LSEFrequency="0"
LSEBypass="false" LSEDrive="3 High Drive (default)" />
<ports>
diff --git a/os/hal/boards/ST_STM32F429I_DISCOVERY/board.c b/os/hal/boards/ST_STM32F429I_DISCOVERY/board.c
index 54113e913..6eb610254 100644
--- a/os/hal/boards/ST_STM32F429I_DISCOVERY/board.c
+++ b/os/hal/boards/ST_STM32F429I_DISCOVERY/board.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -22,26 +22,43 @@
* @details Digital I/O ports static configuration as defined in @p board.h.
* This variable is used by the HAL when initializing the PAL driver.
*/
-const PALConfig pal_default_config =
-{
+const PALConfig pal_default_config = {
+#if STM32_HAS_GPIOA
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+#endif
+#if STM32_HAS_GPIOB
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+#endif
+#if STM32_HAS_GPIOC
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+#endif
+#if STM32_HAS_GPIOD
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+#endif
+#if STM32_HAS_GPIOE
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+#endif
+#if STM32_HAS_GPIOF
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
+#endif
+#if STM32_HAS_GPIOG
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
+#endif
+#if STM32_HAS_GPIOH
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
+#endif
+#if STM32_HAS_GPIOI
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
+#endif
};
#endif
@@ -59,21 +76,21 @@ void __early_init(void) {
/**
* @brief SDC card detection.
*/
-bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
(void)sdcp;
/* TODO: Fill the implementation.*/
- return TRUE;
+ return true;
}
/**
* @brief SDC card write protection detection.
*/
-bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) {
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
(void)sdcp;
/* TODO: Fill the implementation.*/
- return FALSE;
+ return false;
}
#endif /* HAL_USE_SDC */
@@ -81,21 +98,21 @@ bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) {
/**
* @brief MMC_SPI card detection.
*/
-bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
- return TRUE;
+ return true;
}
/**
* @brief MMC_SPI card write protection detection.
*/
-bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) {
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
- return FALSE;
+ return false;
}
#endif
diff --git a/os/hal/boards/ST_STM32F429I_DISCOVERY/board.h b/os/hal/boards/ST_STM32F429I_DISCOVERY/board.h
index ef0aab7a7..542fca106 100644
--- a/os/hal/boards/ST_STM32F429I_DISCOVERY/board.h
+++ b/os/hal/boards/ST_STM32F429I_DISCOVERY/board.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
diff --git a/os/hal/boards/ST_STM32F429I_DISCOVERY/cfg/board.chcfg b/os/hal/boards/ST_STM32F429I_DISCOVERY/cfg/board.chcfg
index a4ec62ef3..9e668b10e 100644
--- a/os/hal/boards/ST_STM32F429I_DISCOVERY/cfg/board.chcfg
+++ b/os/hal/boards/ST_STM32F429I_DISCOVERY/cfg/board.chcfg
@@ -6,11 +6,12 @@
<configuration_settings>
<templates_path>resources/gencfg/processors/boards/stm32f4xx/templates</templates_path>
<output_path>..</output_path>
+ <hal_version>3.0.x</hal_version>
</configuration_settings>
<board_name>STMicroelectronics STM32F429I-Discovery</board_name>
<board_id>ST_STM32F429I_DISCOVERY</board_id>
<board_functions></board_functions>
- <subtype>STM32F429_439xx</subtype>
+ <subtype>STM32F429xx</subtype>
<clocks
HSEFrequency="8000000"
HSEBypass="false"
diff --git a/os/hal/boards/ST_STM32F4_DISCOVERY/board.c b/os/hal/boards/ST_STM32F4_DISCOVERY/board.c
index 30c36c748..6eb610254 100644
--- a/os/hal/boards/ST_STM32F4_DISCOVERY/board.c
+++ b/os/hal/boards/ST_STM32F4_DISCOVERY/board.c
@@ -53,7 +53,7 @@ const PALConfig pal_default_config = {
#endif
#if STM32_HAS_GPIOH
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
- VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}
+ VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
#endif
#if STM32_HAS_GPIOI
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
diff --git a/os/hal/boards/ST_STM32F4_DISCOVERY/cfg/board.chcfg b/os/hal/boards/ST_STM32F4_DISCOVERY/cfg/board.chcfg
index 7bfe58bc5..eaf5cffbe 100644
--- a/os/hal/boards/ST_STM32F4_DISCOVERY/cfg/board.chcfg
+++ b/os/hal/boards/ST_STM32F4_DISCOVERY/cfg/board.chcfg
@@ -6,6 +6,7 @@
<configuration_settings>
<templates_path>resources/gencfg/processors/boards/stm32f4xx/templates</templates_path>
<output_path>..</output_path>
+ <hal_version>3.0.x</hal_version>
</configuration_settings>
<board_name>STMicroelectronics STM32F4-Discovery</board_name>
<board_id>ST_STM32F4_DISCOVERY</board_id>
diff --git a/os/hal/boards/ST_STM32L_DISCOVERY/board.c b/os/hal/boards/ST_STM32L_DISCOVERY/board.c
index 9e88422e1..6eb610254 100644
--- a/os/hal/boards/ST_STM32L_DISCOVERY/board.c
+++ b/os/hal/boards/ST_STM32L_DISCOVERY/board.c
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -22,20 +22,43 @@
* @details Digital I/O ports static configuration as defined in @p board.h.
* This variable is used by the HAL when initializing the PAL driver.
*/
-const PALConfig pal_default_config =
-{
+const PALConfig pal_default_config = {
+#if STM32_HAS_GPIOA
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+#endif
+#if STM32_HAS_GPIOB
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+#endif
+#if STM32_HAS_GPIOC
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+#endif
+#if STM32_HAS_GPIOD
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+#endif
+#if STM32_HAS_GPIOE
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+#endif
+#if STM32_HAS_GPIOF
+ {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
+ VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
+#endif
+#if STM32_HAS_GPIOG
+ {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
+ VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
+#endif
+#if STM32_HAS_GPIOH
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
- VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}
+ VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
+#endif
+#if STM32_HAS_GPIOI
+ {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
+ VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
+#endif
};
#endif
@@ -57,7 +80,7 @@ bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
(void)sdcp;
/* TODO: Fill the implementation.*/
- return TRUE;
+ return true;
}
/**
@@ -67,7 +90,7 @@ bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
(void)sdcp;
/* TODO: Fill the implementation.*/
- return FALSE;
+ return false;
}
#endif /* HAL_USE_SDC */
@@ -79,7 +102,7 @@ bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
- return TRUE;
+ return true;
}
/**
@@ -89,7 +112,7 @@ bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
- return FALSE;
+ return false;
}
#endif
diff --git a/os/hal/boards/ST_STM32L_DISCOVERY/board.h b/os/hal/boards/ST_STM32L_DISCOVERY/board.h
index 016e44bdd..0bc333f31 100644
--- a/os/hal/boards/ST_STM32L_DISCOVERY/board.h
+++ b/os/hal/boards/ST_STM32L_DISCOVERY/board.h
@@ -1,5 +1,5 @@
/*
- ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
diff --git a/os/hal/boards/ST_STM32L_DISCOVERY/cfg/board.chcfg b/os/hal/boards/ST_STM32L_DISCOVERY/cfg/board.chcfg
index b0c6406f7..6b7e01085 100644
--- a/os/hal/boards/ST_STM32L_DISCOVERY/cfg/board.chcfg
+++ b/os/hal/boards/ST_STM32L_DISCOVERY/cfg/board.chcfg
@@ -6,10 +6,12 @@
<configuration_settings>
<templates_path>resources/gencfg/processors/boards/stm32l1xx/templates</templates_path>
<output_path>..</output_path>
+ <hal_version>3.0.x</hal_version>
</configuration_settings>
<board_name>ST STM32L-Discovery</board_name>
<board_id>ST_STM32L_DISCOVERY</board_id>
<board_functions></board_functions>
+ <subtype>STM32L1XX_MD</subtype>
<clocks
HSEFrequency="0"
HSEBypass="true"