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-rw-r--r--demos/STM32/RT-STM32F412ZG-NUCLEO144/mcuconf.h14
-rw-r--r--os/hal/ports/STM32/STM32F4xx/hal_lld.h210
-rw-r--r--os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h221
-rw-r--r--os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h244
4 files changed, 219 insertions, 470 deletions
diff --git a/demos/STM32/RT-STM32F412ZG-NUCLEO144/mcuconf.h b/demos/STM32/RT-STM32F412ZG-NUCLEO144/mcuconf.h
index 5dfea7cd2..19a9b5c8c 100644
--- a/demos/STM32/RT-STM32F412ZG-NUCLEO144/mcuconf.h
+++ b/demos/STM32/RT-STM32F412ZG-NUCLEO144/mcuconf.h
@@ -39,15 +39,16 @@
#define STM32_NO_INIT FALSE
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED TRUE
-#define STM32_HSE_ENABLED FALSE
+#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
#define STM32_CLOCK48_REQUIRED TRUE
#define STM32_SW STM32_SW_PLL
-#define STM32_PLLSRC STM32_PLLSRC_HSI
-#define STM32_PLLM_VALUE 16
+#define STM32_PLLSRC STM32_PLLSRC_HSE
+#define STM32_PLLM_VALUE 8
#define STM32_PLLN_VALUE 384
#define STM32_PLLP_VALUE 4
#define STM32_PLLQ_VALUE 8
+#define STM32_PLLR_VALUE 4
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV2
#define STM32_PPRE2 STM32_PPRE2_DIV1
@@ -57,9 +58,12 @@
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
-#define STM32_I2SSRC STM32_I2SSRC_CKIN
+#define STM32_PLLI2SSRC STM32_PLLI2SSRC_PLLSRC
+#define STM32_I2SCKIN_VALUE 0
+#define STM32_PLLI2SM_VALUE 8
#define STM32_PLLI2SN_VALUE 192
-#define STM32_PLLI2SR_VALUE 5
+#define STM32_PLLI2SR_VALUE 4
+#define STM32_PLLI2SQ_VALUE 4
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE FALSE
diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld.h b/os/hal/ports/STM32/STM32F4xx/hal_lld.h
index 32eecfd7c..1456029e2 100644
--- a/os/hal/ports/STM32/STM32F4xx/hal_lld.h
+++ b/os/hal/ports/STM32/STM32F4xx/hal_lld.h
@@ -53,6 +53,216 @@
/* Derived constants and error checks. */
/*===========================================================================*/
+/**
+ * @brief MCO1 divider clock.
+ */
+#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || defined(__DOXYGEN__)
+#define STM32_MCO1DIVCLK STM32_HSICLK
+
+#elif STM32_MCO1SEL == STM32_MCO1SEL_LSE
+#define STM32_MCO1DIVCLK STM32_LSECLK
+
+#elif STM32_MCO1SEL == STM32_MCO1SEL_HSE
+#define STM32_MCO1DIVCLK STM32_HSECLK
+
+#elif STM32_MCO1SEL == STM32_MCO1SEL_PLL
+#define STM32_MCO1DIVCLK STM32_PLLCLKOUT
+
+#else
+#error "invalid STM32_MCO1SEL value specified"
+#endif
+
+/**
+ * @brief MCO1 output pin clock.
+ */
+#if (STM32_MCO1PRE == STM32_MCO1PRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_MCO1CLK STM32_MCO1DIVCLK
+
+#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV2
+#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 2)
+
+#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV3
+#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 3)
+
+#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV4
+#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 4)
+
+#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV5
+#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 5)
+
+#else
+#error "invalid STM32_MCO1PRE value specified"
+#endif
+
+/**
+ * @brief MCO2 divider clock.
+ */
+#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || defined(__DOXYGEN__)
+#define STM32_MCO2DIVCLK STM32_HSECLK
+
+#elif STM32_MCO2SEL == STM32_MCO2SEL_PLL
+#define STM32_MCO2DIVCLK STM32_PLLCLKOUT
+
+#elif STM32_MCO2SEL == STM32_MCO2SEL_SYSCLK
+#define STM32_MCO2DIVCLK STM32_SYSCLK
+
+#elif STM32_MCO2SEL == STM32_MCO2SEL_PLLI2S
+#define STM32_MCO2DIVCLK STM32_PLLI2S
+
+#else
+#error "invalid STM32_MCO2SEL value specified"
+#endif
+
+/**
+ * @brief MCO2 output pin clock.
+ */
+#if (STM32_MCO2PRE == STM32_MCO2PRE_DIV1) || defined(__DOXYGEN__)
+#define STM32_MCO2CLK STM32_MCO2DIVCLK
+
+#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV2
+#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 2)
+
+#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV3
+#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 3)
+
+#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV4
+#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 4)
+
+#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV5
+#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 5)
+
+#else
+#error "invalid STM32_MCO2PRE value specified"
+#endif
+
+/**
+ * @brief RTC HSE divider setting.
+ */
+#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \
+ defined(__DOXYGEN__)
+#define STM32_RTCPRE (STM32_RTCPRE_VALUE << 16)
+#else
+#error "invalid STM32_RTCPRE value specified"
+#endif
+
+/**
+ * @brief HSE divider toward RTC clock.
+ */
+#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \
+ defined(__DOXYGEN__)
+#define STM32_HSEDIVCLK (STM32_HSECLK / STM32_RTCPRE_VALUE)
+#else
+#error "invalid STM32_RTCPRE value specified"
+#endif
+
+/**
+ * @brief RTC clock.
+ */
+#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__)
+#define STM32_RTCCLK 0
+
+#elif STM32_RTCSEL == STM32_RTCSEL_LSE
+#define STM32_RTCCLK STM32_LSECLK
+
+#elif STM32_RTCSEL == STM32_RTCSEL_LSI
+#define STM32_RTCCLK STM32_LSICLK
+
+#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
+#define STM32_RTCCLK STM32_HSEDIVCLK
+
+#else
+#error "invalid STM32_RTCSEL value specified"
+#endif
+
+/**
+ * @brief 48MHz frequency.
+ */
+#if STM32_CLOCK48_REQUIRED || defined(__DOXYGEN__)
+#if STM32_HAS_RCC_CK48MSEL || defined(__DOXYGEN__)
+#if (STM32_CK48MSEL == STM32_CK48MSEL_PLL) || defined(__DOXYGEN__)
+#define STM32_PLL48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE)
+#elif STM32_CK48MSEL == STM32_CK48MSEL_PLLI2S
+#if STM32_RCC_CK48MSEL_USES_I2S
+#define STM32_PLL48CLK STM32_PLLI2S_Q_CLKOUT
+#else
+#define STM32_PLL48CLK STM32_PLLSAI_Q_CLKOUT
+#endif
+#else
+#error "invalid source selected for PLL48CLK clock"
+#endif
+#else /* !STM32_HAS_RCC_CK48MSEL */
+#define STM32_PLL48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE)
+#endif /* !STM32_HAS_RCC_CK48MSEL */
+#else /* !STM32_CLOCK48_REQUIRED */
+#define STM32_PLL48CLK 0
+#endif /* STM32_CLOCK48_REQUIRED */
+
+#if !STM32_HAS_RCC_DCKCFGR || (STM32_TIMPRE == STM32_TIMPRE_PCLK) || \
+ defined(__DOXYGEN__)
+/**
+ * @brief Clock of timers connected to APB1
+ * (Timers 2, 3, 4, 5, 6, 7, 12, 13, 14).
+ */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK1 (STM32_PCLK1 * 1)
+#else
+#define STM32_TIMCLK1 (STM32_PCLK1 * 2)
+#endif
+
+/**
+ * @brief Clock of timers connected to APB2 (Timers 1, 8, 9, 10, 11).
+ */
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
+#define STM32_TIMCLK2 (STM32_PCLK2 * 1)
+#else
+#define STM32_TIMCLK2 (STM32_PCLK2 * 2)
+#endif
+
+#else /* STM32_HAS_RCC_DCKCFGR && (STM32_TIMPRE == STM32_TIMPRE_HCLK) */
+#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || \
+ (STM32_PPRE1 == STM32_PPRE1_DIV2) || \
+ (STM32_PPRE1 == STM32_PPRE1_DIV4) || \
+ defined(__DOXYGEN__)
+#define STM32_TIMCLK1 STM32_HCLK
+#else
+#define STM32_TIMCLK1 (STM32_PCLK1 * 4)
+#endif
+
+#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || \
+ (STM32_PPRE2 == STM32_PPRE2_DIV2) || \
+ (STM32_PPRE2 == STM32_PPRE2_DIV4) || \
+ defined(__DOXYGEN__)
+#define STM32_TIMCLK2 STM32_HCLK
+#else
+#define STM32_TIMCLK2 (STM32_PCLK2 * 4)
+#endif
+#endif /* STM32_HAS_RCC_DCKCFGR && (STM32_TIMPRE == STM32_TIMPRE_HCLK) */
+
+/**
+ * @brief Flash settings.
+ */
+#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)
+#define STM32_FLASHBITS 0x00000000
+#elif STM32_HCLK <= STM32_1WS_THRESHOLD
+#define STM32_FLASHBITS 0x00000001
+#elif STM32_HCLK <= STM32_2WS_THRESHOLD
+#define STM32_FLASHBITS 0x00000002
+#elif STM32_HCLK <= STM32_3WS_THRESHOLD
+#define STM32_FLASHBITS 0x00000003
+#elif STM32_HCLK <= STM32_4WS_THRESHOLD
+#define STM32_FLASHBITS 0x00000004
+#elif STM32_HCLK <= STM32_5WS_THRESHOLD
+#define STM32_FLASHBITS 0x00000005
+#elif STM32_HCLK <= STM32_6WS_THRESHOLD
+#define STM32_FLASHBITS 0x00000006
+#elif STM32_HCLK <= STM32_7WS_THRESHOLD
+#define STM32_FLASHBITS 0x00000007
+#elif STM32_HCLK <= STM32_8WS_THRESHOLD
+#define STM32_FLASHBITS 0x00000008
+#else
+#error "invalid frequency at specified VDD level"
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h b/os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h
index 531984060..16eff7b60 100644
--- a/os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h
+++ b/os/hal/ports/STM32/STM32F4xx/hal_lld_type1.h
@@ -1927,227 +1927,6 @@
*/
#define STM32_PLLSAI_R_CLKOUT (STM32_PLLSAIVCO / STM32_PLLSAIR_VALUE)
-/**
- * @brief MCO1 divider clock.
- */
-#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || defined(__DOXYGEN__)
-#define STM32_MCO1DIVCLK STM32_HSICLK
-
-#elif STM32_MCO1SEL == STM32_MCO1SEL_LSE
-#define STM32_MCO1DIVCLK STM32_LSECLK
-
-#elif STM32_MCO1SEL == STM32_MCO1SEL_HSE
-#define STM32_MCO1DIVCLK STM32_HSECLK
-
-#elif STM32_MCO1SEL == STM32_MCO1SEL_PLL
-#define STM32_MCO1DIVCLK STM32_PLLCLKOUT
-
-#else
-#error "invalid STM32_MCO1SEL value specified"
-#endif
-
-/**
- * @brief MCO1 output pin clock.
- */
-#if (STM32_MCO1PRE == STM32_MCO1PRE_DIV1) || defined(__DOXYGEN__)
-#define STM32_MCO1CLK STM32_MCO1DIVCLK
-
-#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV2
-#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 2)
-
-#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV3
-#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 3)
-
-#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV4
-#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 4)
-
-#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV5
-#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 5)
-
-#else
-#error "invalid STM32_MCO1PRE value specified"
-#endif
-
-/**
- * @brief MCO2 divider clock.
- */
-#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || defined(__DOXYGEN__)
-#define STM32_MCO2DIVCLK STM32_HSECLK
-
-#elif STM32_MCO2SEL == STM32_MCO2SEL_PLL
-#define STM32_MCO2DIVCLK STM32_PLLCLKOUT
-
-#elif STM32_MCO2SEL == STM32_MCO2SEL_SYSCLK
-#define STM32_MCO2DIVCLK STM32_SYSCLK
-
-#elif STM32_MCO2SEL == STM32_MCO2SEL_PLLI2S
-#define STM32_MCO2DIVCLK STM32_PLLI2S
-
-#else
-#error "invalid STM32_MCO2SEL value specified"
-#endif
-
-/**
- * @brief MCO2 output pin clock.
- */
-#if (STM32_MCO2PRE == STM32_MCO2PRE_DIV1) || defined(__DOXYGEN__)
-#define STM32_MCO2CLK STM32_MCO2DIVCLK
-
-#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV2
-#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 2)
-
-#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV3
-#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 3)
-
-#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV4
-#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 4)
-
-#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV5
-#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 5)
-
-#else
-#error "invalid STM32_MCO2PRE value specified"
-#endif
-
-/**
- * @brief RTC HSE divider setting.
- */
-#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \
- defined(__DOXYGEN__)
-#define STM32_RTCPRE (STM32_RTCPRE_VALUE << 16)
-#else
-#error "invalid STM32_RTCPRE value specified"
-#endif
-
-/**
- * @brief HSE divider toward RTC clock.
- */
-#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \
- defined(__DOXYGEN__)
-#define STM32_HSEDIVCLK (STM32_HSECLK / STM32_RTCPRE_VALUE)
-#else
-#error "invalid STM32_RTCPRE value specified"
-#endif
-
-/**
- * @brief RTC clock.
- */
-#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__)
-#define STM32_RTCCLK 0
-
-#elif STM32_RTCSEL == STM32_RTCSEL_LSE
-#define STM32_RTCCLK STM32_LSECLK
-
-#elif STM32_RTCSEL == STM32_RTCSEL_LSI
-#define STM32_RTCCLK STM32_LSICLK
-
-#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
-#define STM32_RTCCLK STM32_HSEDIVCLK
-
-#else
-#error "invalid STM32_RTCSEL value specified"
-#endif
-
-/**
- * @brief 48MHz frequency.
- */
-#if STM32_CLOCK48_REQUIRED || defined(__DOXYGEN__)
-#if STM32_HAS_RCC_CK48MSEL || defined(__DOXYGEN__)
-#if (STM32_CK48MSEL == STM32_CK48MSEL_PLL) || defined(__DOXYGEN__)
-#define STM32_PLL48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE)
-#elif STM32_CK48MSEL == STM32_CK48MSEL_PLLALT
-#if STM32_RCC_CK48MSEL_USES_I2S
-#define STM32_PLL48CLK STM32_PLLI2S_Q_CLKOUT
-#else
-#define STM32_PLL48CLK STM32_PLLSAI_Q_CLKOUT
-#endif
-#else
-#error "invalid source selected for PLL48CLK clock"
-#endif
-#else /* !STM32_HAS_RCC_CK48MSEL */
-#define STM32_PLL48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE)
-#endif /* !STM32_HAS_RCC_CK48MSEL */
-#else /* !STM32_CLOCK48_REQUIRED */
-#define STM32_PLL48CLK 0
-#endif /* STM32_CLOCK48_REQUIRED */
-
-#if !STM32_HAS_RCC_DCKCFGR || (STM32_TIMPRE == STM32_TIMPRE_PCLK) || \
- defined(__DOXYGEN__)
-/**
- * @brief Clock of timers connected to APB1
- * (Timers 2, 3, 4, 5, 6, 7, 12, 13, 14).
- */
-#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
-#define STM32_TIMCLK1 (STM32_PCLK1 * 1)
-#else
-#define STM32_TIMCLK1 (STM32_PCLK1 * 2)
-#endif
-
-/**
- * @brief Clock of timers connected to APB2 (Timers 1, 8, 9, 10, 11).
- */
-#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
-#define STM32_TIMCLK2 (STM32_PCLK2 * 1)
-#else
-#define STM32_TIMCLK2 (STM32_PCLK2 * 2)
-#endif
-
-#else /* STM32_HAS_RCC_DCKCFGR && (STM32_TIMPRE == STM32_TIMPRE_HCLK) */
-#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || \
- (STM32_PPRE1 == STM32_PPRE1_DIV2) || \
- (STM32_PPRE1 == STM32_PPRE1_DIV4) || \
- defined(__DOXYGEN__)
-#define STM32_TIMCLK1 STM32_HCLK
-#else
-#define STM32_TIMCLK1 (STM32_PCLK1 * 4)
-#endif
-
-#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || \
- (STM32_PPRE2 == STM32_PPRE2_DIV2) || \
- (STM32_PPRE2 == STM32_PPRE2_DIV4) || \
- defined(__DOXYGEN__)
-#define STM32_TIMCLK2 STM32_HCLK
-#else
-#define STM32_TIMCLK2 (STM32_PCLK2 * 4)
-#endif
-#endif /* STM32_HAS_RCC_DCKCFGR && (STM32_TIMPRE == STM32_TIMPRE_HCLK) */
-
-/**
- * @brief Flash settings.
- */
-#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)
-#define STM32_FLASHBITS 0x00000000
-#elif STM32_HCLK <= STM32_1WS_THRESHOLD
-#define STM32_FLASHBITS 0x00000001
-#elif STM32_HCLK <= STM32_2WS_THRESHOLD
-#define STM32_FLASHBITS 0x00000002
-#elif STM32_HCLK <= STM32_3WS_THRESHOLD
-#define STM32_FLASHBITS 0x00000003
-#elif STM32_HCLK <= STM32_4WS_THRESHOLD
-#define STM32_FLASHBITS 0x00000004
-#elif STM32_HCLK <= STM32_5WS_THRESHOLD
-#define STM32_FLASHBITS 0x00000005
-#elif STM32_HCLK <= STM32_6WS_THRESHOLD
-#define STM32_FLASHBITS 0x00000006
-#elif STM32_HCLK <= STM32_7WS_THRESHOLD
-#define STM32_FLASHBITS 0x00000007
-#elif STM32_HCLK <= STM32_8WS_THRESHOLD
-#define STM32_FLASHBITS 0x00000008
-#else
-#error "invalid frequency at specified VDD level"
-#endif
-
-/* There are differences in vector names in the various sub-families,
- normalizing.*/
-#if 0
-#define TIM1_BRK_IRQn TIM1_BRK_TIM9_IRQn
-#define TIM1_UP_IRQn TIM1_UP_TIM10_IRQn
-#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM11_IRQn
-#define TIM8_BRK_IRQn TIM8_BRK_TIM12_IRQn
-#define TIM8_UP_IRQn TIM8_UP_TIM13_IRQn
-#define TIM8_TRG_COM_IRQn TIM8_TRG_COM_TIM14_IRQn
-#endif
-
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
diff --git a/os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h b/os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h
index 607d3e7ab..a2831dc74 100644
--- a/os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h
+++ b/os/hal/ports/STM32/STM32F4xx/hal_lld_type2.h
@@ -1175,250 +1175,6 @@
*/
#define STM32_ACTIVATE_PLLSAI FALSE
-/**
- * @brief MCO1 divider clock.
- */
-#if (STM32_MCO1SEL == STM32_MCO1SEL_HSI) || defined(__DOXYGEN__)
-#define STM32_MCO1DIVCLK STM32_HSICLK
-
-#elif STM32_MCO1SEL == STM32_MCO1SEL_LSE
-#define STM32_MCO1DIVCLK STM32_LSECLK
-
-#elif STM32_MCO1SEL == STM32_MCO1SEL_HSE
-#define STM32_MCO1DIVCLK STM32_HSECLK
-
-#elif STM32_MCO1SEL == STM32_MCO1SEL_PLL
-#define STM32_MCO1DIVCLK STM32_PLLCLKOUT
-
-#else
-#error "invalid STM32_MCO1SEL value specified"
-#endif
-
-/**
- * @brief MCO1 output pin clock.
- */
-#if (STM32_MCO1PRE == STM32_MCO1PRE_DIV1) || defined(__DOXYGEN__)
-#define STM32_MCO1CLK STM32_MCO1DIVCLK
-
-#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV2
-#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 2)
-
-#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV3
-#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 3)
-
-#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV4
-#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 4)
-
-#elif STM32_MCO1PRE == STM32_MCO1PRE_DIV5
-#define STM32_MCO1CLK (STM32_MCO1DIVCLK / 5)
-
-#else
-#error "invalid STM32_MCO1PRE value specified"
-#endif
-
-/**
- * @brief MCO2 divider clock.
- */
-#if (STM32_MCO2SEL == STM32_MCO2SEL_HSE) || defined(__DOXYGEN__)
-#define STM32_MCO2DIVCLK STM32_HSECLK
-
-#elif STM32_MCO2SEL == STM32_MCO2SEL_PLL
-#define STM32_MCO2DIVCLK STM32_PLLCLKOUT
-
-#elif STM32_MCO2SEL == STM32_MCO2SEL_SYSCLK
-#define STM32_MCO2DIVCLK STM32_SYSCLK
-
-#elif STM32_MCO2SEL == STM32_MCO2SEL_PLLI2S
-#define STM32_MCO2DIVCLK STM32_PLLI2S
-
-#else
-#error "invalid STM32_MCO2SEL value specified"
-#endif
-
-/**
- * @brief MCO2 output pin clock.
- */
-#if (STM32_MCO2PRE == STM32_MCO2PRE_DIV1) || defined(__DOXYGEN__)
-#define STM32_MCO2CLK STM32_MCO2DIVCLK
-
-#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV2
-#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 2)
-
-#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV3
-#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 3)
-
-#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV4
-#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 4)
-
-#elif STM32_MCO2PRE == STM32_MCO2PRE_DIV5
-#define STM32_MCO2CLK (STM32_MCO2DIVCLK / 5)
-
-#else
-#error "invalid STM32_MCO2PRE value specified"
-#endif
-
-/**
- * @brief RTC HSE divider setting.
- */
-#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \
- defined(__DOXYGEN__)
-#define STM32_RTCPRE (STM32_RTCPRE_VALUE << 16)
-#else
-#error "invalid STM32_RTCPRE value specified"
-#endif
-
-/**
- * @brief HSE divider toward RTC clock.
- */
-#if ((STM32_RTCPRE_VALUE >= 2) && (STM32_RTCPRE_VALUE <= 31)) || \
- defined(__DOXYGEN__)
-#define STM32_HSEDIVCLK (STM32_HSECLK / STM32_RTCPRE_VALUE)
-#else
-#error "invalid STM32_RTCPRE value specified"
-#endif
-
-/**
- * @brief RTC clock.
- */
-#if (STM32_RTCSEL == STM32_RTCSEL_NOCLOCK) || defined(__DOXYGEN__)
-#define STM32_RTCCLK 0
-
-#elif STM32_RTCSEL == STM32_RTCSEL_LSE
-#define STM32_RTCCLK STM32_LSECLK
-
-#elif STM32_RTCSEL == STM32_RTCSEL_LSI
-#define STM32_RTCCLK STM32_LSICLK
-
-#elif STM32_RTCSEL == STM32_RTCSEL_HSEDIV
-#define STM32_RTCCLK STM32_HSEDIVCLK
-
-#else
-#error "invalid STM32_RTCSEL value specified"
-#endif
-
-/**
- * @brief 48MHz frequency.
- */
-#if STM32_CLOCK48_REQUIRED || defined(__DOXYGEN__)
-#if STM32_HAS_RCC_CK48MSEL || defined(__DOXYGEN__)
-#if (STM32_CK48MSEL == STM32_CK48MSEL_PLL) || defined(__DOXYGEN__)
-#define STM32_PLL48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE)
-#elif STM32_CK48MSEL == STM32_CK48MSEL_PLLI2S
-#if STM32_RCC_CK48MSEL_USES_I2S
-#define STM32_PLL48CLK STM32_PLLI2S_Q_CLKOUT
-#else
-#define STM32_PLL48CLK STM32_PLLSAI_Q_CLKOUT
-#endif
-#else
-#error "invalid source selected for PLL48CLK clock"
-#endif
-#else /* !STM32_HAS_RCC_CK48MSEL */
-#define STM32_PLL48CLK (STM32_PLLVCO / STM32_PLLQ_VALUE)
-#endif /* !STM32_HAS_RCC_CK48MSEL */
-#else /* !STM32_CLOCK48_REQUIRED */
-#define STM32_PLL48CLK 0
-#endif /* STM32_CLOCK48_REQUIRED */
-
-#if defined(STM32F413xx) || defined(STM32F446xx)
-#if STM32_TIMPRE == STM32_TIMPRE_HCLK
-/**
- * @brief Clock of timers connected to APB1
- * (Timers 2, 3, 4, 5, 6, 7, 12, 13, 14).
- */
-#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || \
- (STM32_PPRE1 == STM32_PPRE1_DIV2) || \
- (STM32_PPRE1 == STM32_PPRE1_DIV4 && defined(STM32F446xx)) || \
- defined(__DOXYGEN__)
-#define STM32_TIMCLK1 STM32_HCLK
-#else
-#define STM32_TIMCLK1 (STM32_PCLK1 * 4)
-#endif
-#else /* STM32_TIMPRE != STM32_TIMPRE_HCLK */
-#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
-#define STM32_TIMCLK1 STM32_HCLK
-#else /* !(STM32_TIMPRE_HCLK == STM32_TIMPRE_HCLK) */
-#define STM32_TIMCLK1 (STM32_PCLK1 * 2)
-#endif
-#endif /* STM32_TIMPRE == STM32_TIMPRE_HCLK */
-
-#if (STM32_TIMPRE == STM32_TIMPRE_HCLK) || defined(STM32F446xx)
-#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || \
- (STM32_PPRE1 == STM32_PPRE1_DIV2) || \
- (STM32_PPRE1 == STM32_PPRE1_DIV4 && defined(STM32F446xx)) || \
- defined(__DOXYGEN__)
-/**
- * @brief Clock of timers connected to APB2 (Timers 1, 8, 9, 10, 11).
- */
-#define STM32_TIMCLK2 STM32_HCLK
-#else
-#define STM32_TIMCLK2 (STM32_PCLK2 * 4)
-#endif
-#else /* STM32_TIMPRE != STM32_TIMPRE_HCLK */
-#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
-#define STM32_TIMCLK2 STM32_HCLK
-#else
-#define STM32_TIMCLK2 (STM32_PCLK2 * 2)
-#endif
-#endif /* STM32_TIMPRE != STM32_TIMPRE_HCLK */
-
-#else /* !(defined(STM32F413xx) || defined(STM32F446xx)) */
-
-/**
- * @brief Clock of timers connected to APB1
- * (Timers 2, 3, 4, 5, 6, 7, 12, 13, 14).
- */
-#if (STM32_PPRE1 == STM32_PPRE1_DIV1) || defined(__DOXYGEN__)
-#define STM32_TIMCLK1 (STM32_PCLK1 * 1)
-#else
-#define STM32_TIMCLK1 (STM32_PCLK1 * 2)
-#endif
-
-/**
- * @brief Clock of timers connected to APB2 (Timers 1, 8, 9, 10, 11).
- */
-#if (STM32_PPRE2 == STM32_PPRE2_DIV1) || defined(__DOXYGEN__)
-#define STM32_TIMCLK2 (STM32_PCLK2 * 1)
-#else
-#define STM32_TIMCLK2 (STM32_PCLK2 * 2)
-#endif
-#endif /* defined(STM32F413) */
-
-/**
- * @brief Flash settings.
- */
-#if (STM32_HCLK <= STM32_0WS_THRESHOLD) || defined(__DOXYGEN__)
-#define STM32_FLASHBITS 0x00000000
-#elif STM32_HCLK <= STM32_1WS_THRESHOLD
-#define STM32_FLASHBITS 0x00000001
-#elif STM32_HCLK <= STM32_2WS_THRESHOLD
-#define STM32_FLASHBITS 0x00000002
-#elif STM32_HCLK <= STM32_3WS_THRESHOLD
-#define STM32_FLASHBITS 0x00000003
-#elif STM32_HCLK <= STM32_4WS_THRESHOLD
-#define STM32_FLASHBITS 0x00000004
-#elif STM32_HCLK <= STM32_5WS_THRESHOLD
-#define STM32_FLASHBITS 0x00000005
-#elif STM32_HCLK <= STM32_6WS_THRESHOLD
-#define STM32_FLASHBITS 0x00000006
-#elif STM32_HCLK <= STM32_7WS_THRESHOLD
-#define STM32_FLASHBITS 0x00000007
-#elif STM32_HCLK <= STM32_8WS_THRESHOLD
-#define STM32_FLASHBITS 0x00000008
-#else
-#error "invalid frequency at specified VDD level"
-#endif
-
-/* There are differences in vector names in the various sub-families,
- normalizing.*/
-#if 0
-#define TIM1_BRK_IRQn TIM1_BRK_TIM9_IRQn
-#define TIM1_UP_IRQn TIM1_UP_TIM10_IRQn
-#define TIM1_TRG_COM_IRQn TIM1_TRG_COM_TIM11_IRQn
-#define TIM8_BRK_IRQn TIM8_BRK_TIM12_IRQn
-#define TIM8_UP_IRQn TIM8_UP_TIM13_IRQn
-#define TIM8_TRG_COM_IRQn TIM8_TRG_COM_TIM14_IRQn
-#endif
-
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
generated by cgit v1.2.3 (git 2.25.1) at 2024-07-01 06:10:55 +0000