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-rw-r--r--boards/ST_STM8S_DISCOVERY/board.c67
-rw-r--r--boards/ST_STM8S_DISCOVERY/board.h122
-rw-r--r--demos/STM8S-STM8S105-DISCOVERY-STVD/ChibiOS-RT.stw16
-rw-r--r--demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp2124
-rw-r--r--demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/vectors.c101
-rw-r--r--demos/STM8S-STM8S105-DISCOVERY-STVD/demo/chconf.h485
-rw-r--r--demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h152
-rw-r--r--demos/STM8S-STM8S105-DISCOVERY-STVD/demo/main.c75
-rw-r--r--demos/STM8S-STM8S105-DISCOVERY-STVD/demo/mcuconf.h40
-rw-r--r--demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp2145
-rw-r--r--docs/Doxyfile1
-rw-r--r--docs/reports/STM8S105-16-Cosmic.txt158
-rw-r--r--docs/reports/STM8S105-16-Raisonance.txt158
-rw-r--r--os/hal/platforms/STM8/hal_lld.c38
-rw-r--r--os/hal/platforms/STM8/pal_lld.h54
-rw-r--r--os/hal/platforms/STM8/platform.dox4
-rw-r--r--os/hal/platforms/STM8/serial_lld.c237
-rw-r--r--os/hal/platforms/STM8/serial_lld.h16
-rw-r--r--os/hal/platforms/STM8/stm8.h21
-rw-r--r--os/hal/platforms/STM8/stm8s.h2567
-rw-r--r--os/hal/platforms/STM8/stm8s_type.h103
-rw-r--r--os/kernel/include/chbsem.h13
-rw-r--r--os/ports/RC/STM8/chcore.c4
-rw-r--r--os/ports/RC/STM8/chcore.h23
-rw-r--r--os/ports/RC/STM8/chtypes.h10
-rw-r--r--os/ports/RC/STM8/port.dox20
-rw-r--r--os/ports/cosmic/STM8/chcore.c70
-rw-r--r--os/ports/cosmic/STM8/chcore.h320
-rw-r--r--os/ports/cosmic/STM8/chtypes.h130
-rw-r--r--os/ports/cosmic/STM8/port.dox86
-rw-r--r--os/ports/ports.dox11
-rw-r--r--readme.txt4
-rw-r--r--test/test.c6
-rw-r--r--test/test.h12
-rw-r--r--test/testbmk.c28
-rw-r--r--test/testbmk.h2
-rw-r--r--test/testdyn.c8
-rw-r--r--test/testdyn.h2
-rw-r--r--test/testevt.c10
-rw-r--r--test/testevt.h2
-rw-r--r--test/testheap.c4
-rw-r--r--test/testheap.h2
-rw-r--r--test/testmbox.c4
-rw-r--r--test/testmbox.h2
-rw-r--r--test/testmsg.c4
-rw-r--r--test/testmsg.h2
-rw-r--r--test/testmtx.c18
-rw-r--r--test/testmtx.h2
-rw-r--r--test/testpools.c4
-rw-r--r--test/testpools.h2
-rw-r--r--test/testqueues.c6
-rw-r--r--test/testqueues.h2
-rw-r--r--test/testsem.c8
-rw-r--r--test/testsem.h2
-rw-r--r--test/testthd.c10
-rw-r--r--test/testthd.h2
56 files changed, 9267 insertions, 252 deletions
diff --git a/boards/ST_STM8S_DISCOVERY/board.c b/boards/ST_STM8S_DISCOVERY/board.c
new file mode 100644
index 000000000..201a2b239
--- /dev/null
+++ b/boards/ST_STM8S_DISCOVERY/board.c
@@ -0,0 +1,67 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/*
+ * TIM 2 clock after the prescaler.
+ */
+#define TIM2_CLOCK (SYSCLK / 16)
+#define TIM2_ARR ((TIM2_CLOCK / CH_FREQUENCY) - 1)
+
+/*
+ * TIM2 interrupt handler.
+ */
+CH_IRQ_HANDLER(13) {
+
+ CH_IRQ_PROLOGUE();
+
+ chSysLockFromIsr();
+ chSysTimerHandlerI();
+ chSysUnlockFromIsr();
+
+ TIM2->SR1 = 0;
+
+ CH_IRQ_EPILOGUE();
+}
+
+/*
+ * Board initialization code.
+ */
+void hwinit(void) {
+
+ /*
+ * HAL initialization.
+ */
+ halInit();
+
+ /*
+ * TIM2 initialization as system tick.
+ */
+ CLK->PCKENR1 |= 32; /* PCKEN15, TIM2 clock source.*/
+ TIM2->PSCR = 4; /* Prescaler divide by 2^4=16.*/
+ TIM2->ARRH = (uint8_t)(TIM2_ARR >> 8);
+ TIM2->ARRL = (uint8_t)(TIM2_ARR);
+ TIM2->CNTRH = 0;
+ TIM2->CNTRL = 0;
+ TIM2->SR1 = 0;
+ TIM2->IER = 1; /* UIE */
+ TIM2->CR1 = 1; /* CEN */
+}
diff --git a/boards/ST_STM8S_DISCOVERY/board.h b/boards/ST_STM8S_DISCOVERY/board.h
new file mode 100644
index 000000000..943cd03bd
--- /dev/null
+++ b/boards/ST_STM8S_DISCOVERY/board.h
@@ -0,0 +1,122 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for Raisonance REva V3 + STM8S208RB daughter board.
+ */
+
+/*
+ * Board identifiers.
+ */
+#define BOARD_ST_STM8S_DISCOVERY
+#define BOARD_NAME "ST STM8S-Discovery"
+
+/*
+ * Board frequencies.
+ */
+#define HSECLK 16000000
+
+/*
+ * MCU model used on the board.
+ */
+#define STM8S105
+
+/*
+ * Pin definitions.
+ */
+#define PA_OSCIN 1
+#define PA_OSCOUT 2
+
+#define PC_TS_KEY 1
+#define PC_TS_LOADREF 2
+#define PC_TS_SHIELD 3
+
+#define PD_LD10 0
+#define PD_SWIM 1
+#define PD_TX 5
+#define PD_RX 6
+
+/*
+ * Port A initial setup.
+ */
+#define VAL_GPIOAODR 0
+#define VAL_GPIOADDR 0 /* All inputs. */
+#define VAL_GPIOACR1 0xFF /* All pull-up or push-pull. */
+#define VAL_GPIOACR2 0
+
+/*
+ * Port B initial setup.
+ */
+#define VAL_GPIOBODR 0
+#define VAL_GPIOBDDR 0 /* All inputs. */
+#define VAL_GPIOBCR1 0xFF /* All push-pull. */
+#define VAL_GPIOBCR2 0
+
+/*
+ * Port C initial setup.
+ */
+#define VAL_GPIOCODR 0
+#define VAL_GPIOCDDR 0 /* All inputs. */
+#define VAL_GPIOCCR1 0xFF /* All pull-up. */
+#define VAL_GPIOCCR2 0
+
+/*
+ * Port D initial setup.
+ */
+#define VAL_GPIODODR (1 << PD_LD10) | (1 << PD_TX)
+#define VAL_GPIODDDR (1 << PD_LD10) | (1 << PD_TX)
+#define VAL_GPIODCR1 0xFF /* All pull-up. */
+#define VAL_GPIODCR2 0
+
+/*
+ * Port E initial setup.
+ */
+#define VAL_GPIOEODR 0
+#define VAL_GPIOEDDR 0 /* All inputs. */
+#define VAL_GPIOECR1 0xFF /* All pull-up. */
+#define VAL_GPIOECR2 0
+
+/*
+ * Port F initial setup.
+ */
+#define VAL_GPIOFODR 0
+#define VAL_GPIOFDDR 0 /* All inputs. */
+#define VAL_GPIOFCR1 0xFF /* All pull-up. */
+#define VAL_GPIOFCR2 0
+
+/*
+ * Port G initial setup.
+ */
+#define VAL_GPIOGODR 0
+#define VAL_GPIOGDDR 0 /* All inputs. */
+#define VAL_GPIOGCR1 0xFF /* All pull-up or push-pull. */
+#define VAL_GPIOGCR2 0
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void hwinit(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _BOARD_H_ */
diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/ChibiOS-RT.stw b/demos/STM8S-STM8S105-DISCOVERY-STVD/ChibiOS-RT.stw
new file mode 100644
index 000000000..015f8e015
--- /dev/null
+++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/ChibiOS-RT.stw
@@ -0,0 +1,16 @@
+; STMicroelectronics Workspace file
+
+[Version]
+Keyword=ST7Workspace-V0.7
+
+[Project0]
+Filename=cosmic\cosmic.stp
+Dependencies=
+
+[Project1]
+Filename=raisonance\raisonance.stp
+Dependencies=
+[Options]
+ActiveProject=cosmic
+ActiveConfig=Debug
+AddSortedElements=0
diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp b/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp
new file mode 100644
index 000000000..b4667e94e
--- /dev/null
+++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/cosmic.stp
@@ -0,0 +1,2124 @@
+; STMicroelectronics Project file
+
+[Version]
+Keyword=ST7Project
+Number=1.3
+
+[Project]
+Name=cosmic
+Toolset=STM8 Cosmic
+
+[Config]
+0=Config.0
+1=Config.1
+
+[Config.0]
+ConfigName=Debug
+Target=$(ProjectSFile).elf
+OutputFolder=Debug
+Debug=$(TargetFName)
+
+[Config.1]
+ConfigName=Release
+Target=$(ProjectSFile).elf
+OutputFolder=Release
+Debug=$(TargetFName)
+
+[Root]
+ElemType=Project
+PathName=cosmic
+Child=Root.Source Files
+Config.0=Root.Config.0
+Config.1=Root.Config.1
+
+[Root.Config.0]
+Settings.0.0=Root.Config.0.Settings.0
+Settings.0.1=Root.Config.0.Settings.1
+Settings.0.2=Root.Config.0.Settings.2
+Settings.0.3=Root.Config.0.Settings.3
+Settings.0.4=Root.Config.0.Settings.4
+Settings.0.5=Root.Config.0.Settings.5
+Settings.0.6=Root.Config.0.Settings.6
+Settings.0.7=Root.Config.0.Settings.7
+Settings.0.8=Root.Config.0.Settings.8
+
+[Root.Config.1]
+Settings.1.0=Root.Config.1.Settings.0
+Settings.1.1=Root.Config.1.Settings.1
+Settings.1.2=Root.Config.1.Settings.2
+Settings.1.3=Root.Config.1.Settings.3
+Settings.1.4=Root.Config.1.Settings.4
+Settings.1.5=Root.Config.1.Settings.5
+Settings.1.6=Root.Config.1.Settings.6
+Settings.1.7=Root.Config.1.Settings.7
+Settings.1.8=Root.Config.1.Settings.8
+
+[Root.Config.0.Settings.0]
+String.6.0=2010,6,3,15,59,36
+String.100.0=ST Assembler Linker
+String.100.1=ST7 Cosmic
+String.100.2=STM8 Cosmic
+String.100.3=ST7 Metrowerks V1.1
+String.100.4=Raisonance
+String.101.0=STM8 Cosmic
+String.102.0=C:\Program Files\COSMIC\CXSTM8_32K
+String.103.0=
+String.104.0=Hstm8
+String.105.0=Lib
+String.106.0=Debug
+String.107.0=$(ProjectSFile).elf
+Int.108=0
+
+[Root.Config.0.Settings.1]
+String.6.0=2010,5,25,14,45,56
+String.100.0=$(TargetFName)
+String.101.0=
+String.102.0=
+String.103.0=.\;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\ports\cosmic\stm8;..\..\..\boards\st_stm8s_discovery;..\..\..\os\hal\platforms\stm8;..\..\..\os\hal\include;..\..\..\os\hal\src;..\..\..\test;..\demo;
+
+[Root.Config.0.Settings.2]
+String.2.0=
+String.6.0=2010,5,25,14,45,56
+String.100.0=STM8S105C6
+
+[Root.Config.0.Settings.3]
+String.2.0=Compiling $(InputFile)...
+String.3.0=cxstm8 +warn +modsl0 -customDebCompat -customOpt-no -customC-pp -customLst -l -i..\demo -i..\..\..\test -i..\..\..\os\hal\include -i..\..\..\os\hal\platforms\stm8 -i..\..\..\boards\st_stm8s_discovery -i..\..\..\os\ports\cosmic\stm8 -i..\..\..\os\kernel\include $(ToolsetIncOpts) -cl$(IntermPath) -co$(IntermPath) $(InputFile)
+String.4.0=$(IntermPath)$(InputName).$(ObjectExt)
+String.5.0=$(IntermPath)$(InputName).ls
+String.6.0=2010,6,5,11,53,48
+
+[Root.Config.0.Settings.4]
+String.2.0=Assembling $(InputFile)...
+String.3.0=castm8 -xx -l $(ToolsetIncOpts) -o$(IntermPath)$(InputName).$(ObjectExt) $(InputFile)
+String.4.0=$(IntermPath)$(InputName).$(ObjectExt)
+String.5.0=$(IntermPath)$(InputName).ls
+String.6.0=2010,5,25,14,45,56
+
+[Root.Config.0.Settings.5]
+String.2.0=Running Pre-Link step
+String.6.0=2010,5,25,14,45,56
+String.8.0=
+
+[Root.Config.0.Settings.6]
+String.2.0=Running Linker
+String.3.0=clnk $(ToolsetLibOpts) -o $(OutputPath)$(TargetSName).sm8 -fakeInteger -fakeOutFile$(ProjectSFile).elf -fakeRunConv -fakeStartupcrtsi0.sm8 -fakeSemiAutoGen -fakeVectFilevectors.c -fakeVectAddr0x8000 -customMapFile -customMapFile-m$(OutputPath)$(TargetSName).map -customMapAddress -customCfgFile$(OutputPath)$(TargetSName).lkf
+String.3.1=cvdwarf $(OutputPath)$(TargetSName).sm8
+String.4.0=$(OutputPath)$(TargetFName)
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+String.100.0=
+String.101.0=crtsi.st7
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+String.102.7=+seg .data -b 0x100 -m 0x700 -n .data
+String.102.8=+seg .bss -a .data -n .bss
+String.103.0=Code,Constants[0x8080-0xffff]=.const,.text
+String.103.1=Eeprom[0x4000-0x43ff]=.eeprom
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+String.103.3=Ram[0x100-0x7ff]=.data,.bss
+String.104.0=0x7ff
+String.105.0=libisl0.sm8;libm0.sm8
+Int.0=0
+Int.1=0
+
+[Root.Config.0.Settings.7]
+String.2.0=Running Post-Build step
+String.3.0=chex -o $(OutputPath)$(TargetSName).s19 $(OutputPath)$(TargetSName).sm8
+String.6.0=2010,5,25,14,45,56
+
+[Root.Config.0.Settings.8]
+String.2.0=Performing Custom Build on $(InputFile)
+String.6.0=2010,5,25,14,45,56
+
+[Root.Config.1.Settings.0]
+String.6.0=2010,6,3,15,59,36
+String.100.0=ST Assembler Linker
+String.100.1=ST7 Cosmic
+String.100.2=STM8 Cosmic
+String.100.3=ST7 Metrowerks V1.1
+String.100.4=Raisonance
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+
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+
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+String.2.0=
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+
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+
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+
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diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/vectors.c b/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/vectors.c
new file mode 100644
index 000000000..6ede94a3e
--- /dev/null
+++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/cosmic/vectors.c
@@ -0,0 +1,101 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief Exception handler type.
+ */
+typedef void @far @interrupt (*interrupt_handler_t)(void);
+
+/*
+ * Various external symbols.
+ */
+void _stext(void);
+@far @interrupt void vector13(void);
+@far @interrupt void vector17(void);
+@far @interrupt void vector18(void);
+@far @interrupt void vector20(void);
+@far @interrupt void vector21(void);
+
+/**
+ * @brief Exception vector type.
+ */
+typedef struct {
+ uint8_t ev_instruction;
+ interrupt_handler_t ev_handler;
+} exception_vector_t;
+
+/**
+ * @brief Undefined interrupt handler.
+ * @note It should never be invoked.
+ */
+@far @interrupt static void vector (void)
+{
+ return;
+}
+
+/**
+ * @brief Exceptions table.
+ */
+exception_vector_t const _vectab[] = {
+ {0x82, (interrupt_handler_t)_stext}, /* reset */
+ {0x82, vector}, /* trap */
+ {0x82, vector}, /* vector0 */
+ {0x82, vector}, /* vector1 */
+ {0x82, vector}, /* vector2 */
+ {0x82, vector}, /* vector3 */
+ {0x82, vector}, /* vector4 */
+ {0x82, vector}, /* vector5 */
+ {0x82, vector}, /* vector6 */
+ {0x82, vector}, /* vector7 */
+ {0x82, vector}, /* vector8 */
+ {0x82, vector}, /* vector9 */
+ {0x82, vector}, /* vector10 */
+ {0x82, vector}, /* vector11 */
+ {0x82, vector}, /* vector12 */
+ {0x82, vector13}, /* vector13 */
+ {0x82, vector}, /* vector14 */
+ {0x82, vector}, /* vector15 */
+ {0x82, vector}, /* vector16 */
+#if USE_STM8_UART1
+ {0x82, vector17}, /* vector17 */
+ {0x82, vector18}, /* vector18 */
+#else
+ {0x82, vector}, /* vector17 */
+ {0x82, vector}, /* vector18 */
+#endif
+ {0x82, vector}, /* vector19 */
+#if USE_STM8_UART2 || USE_STM8_UART3
+ {0x82, vector20}, /* vector20 */
+ {0x82, vector21}, /* vector21 */
+#else
+ {0x82, vector}, /* vector20 */
+ {0x82, vector}, /* vector21 */
+#endif
+ {0x82, vector}, /* vector22 */
+ {0x82, vector}, /* vector23 */
+ {0x82, vector}, /* vector24 */
+ {0x82, vector}, /* vector25 */
+ {0x82, vector}, /* vector26 */
+ {0x82, vector}, /* vector27 */
+ {0x82, vector}, /* vector28 */
+ {0x82, vector}, /* vector29 */
+};
diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/chconf.h b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/chconf.h
new file mode 100644
index 000000000..55036c05d
--- /dev/null
+++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/chconf.h
@@ -0,0 +1,485 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file templates/chconf.h
+ * @brief Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ * contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+/*===========================================================================*/
+/* Kernel parameters. */
+/*===========================================================================*/
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__)
+#define CH_FREQUENCY 100
+#endif
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ *
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ */
+#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__)
+#define CH_TIME_QUANTUM 10
+#endif
+
+/**
+ * @brief Nested locks.
+ * @details If enabled then the use of nested @p chSysLock() / @p chSysUnlock()
+ * operations is allowed.<br>
+ * For performance and code size reasons the recommended setting
+ * is to leave this option disabled.<br>
+ * You may use this option if you need to merge ChibiOS/RT with
+ * external libraries that require nested lock/unlock operations.
+ *
+ * @note T he default is @p FALSE.
+ */
+#if !defined(CH_USE_NESTED_LOCKS) || defined(__DOXYGEN__)
+#define CH_USE_NESTED_LOCKS FALSE
+#endif
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_USE_COREMEM.
+ */
+#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__)
+#define CH_MEMCORE_SIZE 128
+#endif
+
+/*===========================================================================*/
+/* Performance options. */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__)
+#define CH_OPTIMIZE_SPEED FALSE
+#endif
+
+/**
+ * @brief Exotic optimization.
+ * @details If defined then a CPU register is used as storage for the global
+ * @p currp variable. Caching this variable in a register greatly
+ * improves both space and time OS efficiency. A side effect is that
+ * one less register has to be saved during the context switch
+ * resulting in lower RAM usage and faster context switch.
+ *
+ * @note This option is only usable with the GCC compiler and is only useful
+ * on processors with many registers like ARM cores.
+ * @note If this option is enabled then ALL the libraries linked to the
+ * ChibiOS/RT code <b>must</b> be recompiled with the GCC option @p
+ * -ffixed-@<reg@>.
+ * @note This option must be enabled in the Makefile, it is listed here for
+ * documentation only.
+ */
+#if defined(__DOXYGEN__)
+#define CH_CURRP_REGISTER_CACHE "reg"
+#endif
+
+/*===========================================================================*/
+/* Subsystem options. */
+/*===========================================================================*/
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__)
+#define CH_USE_REGISTRY TRUE
+#endif
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__)
+#define CH_USE_WAITEXIT TRUE
+#endif
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__)
+#define CH_USE_SEMAPHORES TRUE
+#endif
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special requirements.
+ * @note Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)
+#define CH_USE_SEMAPHORES_PRIORITY FALSE
+#endif
+
+/**
+ * @brief Atomic semaphore API.
+ * @details If enabled then the semaphores the @p chSemSignalWait() API
+ * is included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
+#define CH_USE_SEMSW TRUE
+#endif
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__)
+#define CH_USE_MUTEXES TRUE
+#endif
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_MUTEXES.
+ */
+#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__)
+#define CH_USE_CONDVARS TRUE
+#endif
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_CONDVARS.
+ */
+#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)
+#define CH_USE_CONDVARS_TIMEOUT TRUE
+#endif
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__)
+#define CH_USE_EVENTS TRUE
+#endif
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_EVENTS.
+ */
+#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)
+#define CH_USE_EVENTS_TIMEOUT TRUE
+#endif
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__)
+#define CH_USE_MESSAGES TRUE
+#endif
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special requirements.
+ * @note Requires @p CH_USE_MESSAGES.
+ */
+#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)
+#define CH_USE_MESSAGES_PRIORITY FALSE
+#endif
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__)
+#define CH_USE_MAILBOXES TRUE
+#endif
+
+/**
+ * @brief I/O Queues APIs.
+ * @details If enabled then the I/O queues APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__)
+#define CH_USE_QUEUES TRUE
+#endif
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__)
+#define CH_USE_MEMCORE TRUE
+#endif
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_COREMEM and either @p CH_USE_MUTEXES or
+ * @p CH_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__)
+#define CH_USE_HEAP TRUE
+#endif
+
+/**
+ * @brief C-runtime allocator.
+ * @details If enabled the the heap allocator APIs just wrap the C-runtime
+ * @p malloc() and @p free() functions.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_USE_HEAP.
+ * @note The C-runtime may or may not require @p CH_USE_COREMEM, see the
+ * appropriate documentation.
+ */
+#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
+#define CH_USE_MALLOC_HEAP FALSE
+#endif
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__)
+#define CH_USE_MEMPOOLS TRUE
+#endif
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_WAITEXIT.
+ * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS.
+ */
+#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__)
+#define CH_USE_DYNAMIC TRUE
+#endif
+
+/*===========================================================================*/
+/* Debug options. */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_CHECKS FALSE
+#endif
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_ASSERTS FALSE
+#endif
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_TRACE FALSE
+#endif
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_STACK_CHECK FALSE
+#endif
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
+#define CH_DBG_FILL_THREADS FALSE
+#endif
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p Thread structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p TRUE.
+ * @note This debug option is defaulted to TRUE because it is required by
+ * some test cases into the test suite.
+ */
+#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
+#define CH_DBG_THREADS_PROFILING TRUE
+#endif
+
+/*===========================================================================*/
+/* Kernel hooks. */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure hook.
+ * @details User fields added to the end of the @p Thread structure.
+ */
+#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__)
+#define THREAD_EXT_FIELDS \
+ /* Add threads custom fields here.*/
+#endif
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitily from all
+ * the threads creation APIs.
+ */
+#if !defined(THREAD_EXT_INIT) || defined(__DOXYGEN__)
+#define THREAD_EXT_INIT(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+#endif
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#if !defined(THREAD_EXT_EXIT) || defined(__DOXYGEN__)
+#define THREAD_EXT_EXIT(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+#endif
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__)
+#define IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+#endif
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h
new file mode 100644
index 000000000..e68d87a79
--- /dev/null
+++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h
@@ -0,0 +1,152 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file templates/halconf.h
+ * @brief HAL configuration header.
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+/*
+ * HAL configuration file, this file allows to enable or disable the various
+ * device drivers from your application. You may also use this file in order
+ * to override the device drivers default settings.
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+/*
+ * Uncomment the following line in order to include a mcu-related
+ * settings file. This file can be used to include platform specific
+ * header files or to override the low level drivers settings.
+ */
+#include "mcuconf.h"
+
+/*===========================================================================*/
+/* PAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(CH_HAL_USE_PAL) || defined(__DOXYGEN__)
+#define CH_HAL_USE_PAL TRUE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(CH_HAL_USE_ADC) || defined(__DOXYGEN__)
+#define CH_HAL_USE_ADC FALSE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(CH_HAL_USE_CAN) || defined(__DOXYGEN__)
+#define CH_HAL_USE_CAN FALSE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(CH_HAL_USE_MAC) || defined(__DOXYGEN__)
+#define CH_HAL_USE_MAC FALSE
+#endif
+
+/*===========================================================================*/
+/* PWM driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(CH_HAL_USE_PWM) || defined(__DOXYGEN__)
+#define CH_HAL_USE_PWM FALSE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(CH_HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define CH_HAL_USE_SERIAL TRUE
+#endif
+
+/*
+ * Default SERIAL settings overrides (uncomment to override).
+ */
+/*#define SERIAL_DEFAULT_BITRATE 38400*/
+#define SERIAL_BUFFERS_SIZE 16
+
+/*===========================================================================*/
+/* SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(CH_HAL_USE_SPI) || defined(__DOXYGEN__)
+#define CH_HAL_USE_SPI FALSE
+#endif
+
+/*
+ * Default SPI settings overrides (uncomment to override).
+ */
+/*#define SPI_USE_MUTUAL_EXCLUSION TRUE*/
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(CH_HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define CH_HAL_USE_MMC_SPI FALSE
+#endif
+
+/*
+ * Default MMC_SPI settings overrides (uncomment to override).
+ */
+/*#define MMC_SECTOR_SIZE 512*/
+/*#define MMC_NICE_WAITING TRUE*/
+/*#define MMC_POLLING_INTERVAL 10*/
+/*#define MMC_POLLING_DELAY 10*/
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/main.c b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/main.c
new file mode 100644
index 000000000..35321bf62
--- /dev/null
+++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/main.c
@@ -0,0 +1,75 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#include "ch.h"
+#include "hal.h"
+#include "test.h"
+
+/*
+ * LEDs blinker thread, times are in milliseconds.
+ */
+static WORKING_AREA(waThread1, 64);
+static msg_t Thread1(void *arg) {
+
+ (void)arg;
+ while (TRUE) {
+ palClearPad(GPIOD, PD_LD10);
+ chThdSleepMilliseconds(500);
+ palSetPad(GPIOD, PD_LD10);
+ chThdSleepMilliseconds(500);
+ }
+ return 0;
+}
+
+/*
+ * Entry point.
+ */
+void main(void) {
+
+ /*
+ * Board/HAL initialization.
+ */
+ hwinit();
+
+ /*
+ * OS initialization.
+ */
+ chSysInit();
+
+ /*
+ * Activates the serial driver 1 using the driver default configuration.
+ */
+ sdStart(&SD2, NULL);
+
+ /*
+ * Creates the blinker thread.
+ */
+ chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL);
+
+ /*
+ * Normal main() thread activity.
+ */
+ while (TRUE) {
+ if (palReadPad(GPIOG, 0) == PAL_LOW)
+ TestThread(&SD2);
+ if (palReadPad(GPIOG, 1) == PAL_LOW)
+ sdWriteTimeout(&SD2, "Hello World!\r\n", 14, TIME_INFINITE);
+ chThdSleepMilliseconds(1000);
+ }
+}
diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/mcuconf.h b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/mcuconf.h
new file mode 100644
index 000000000..cf2ebd963
--- /dev/null
+++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/mcuconf.h
@@ -0,0 +1,40 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/*
+ * STM8 drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the driver
+ * is enabled in halconf.h.
+ */
+
+/*
+ * HAL general settings.
+ */
+#define STM8_CLOCK_SOURCE CLK_SOURCE_HSI
+#define STM8_HSI_DIVIDER CLK_HSI_DIV1
+#define STM8_CPU_DIVIDER CLK_CPU_DIV1
+
+/*
+ * SERIAL driver system settings.
+ */
+#define USE_STM8_UART1 FALSE
+#define USE_STM8_UART2 TRUE
+#define USE_STM8_UART3 FALSE
diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp b/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp
new file mode 100644
index 000000000..6ccb368b0
--- /dev/null
+++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/raisonance/raisonance.stp
@@ -0,0 +1,2145 @@
+; STMicroelectronics Project file
+
+[Version]
+Keyword=ST7Project
+Number=1.3
+
+[Project]
+Name=raisonance
+Toolset=Raisonance
+
+[Config]
+0=Config.0
+1=Config.1
+
+[Config.0]
+ConfigName=Debug
+Target=$(ProjectSFile).elf
+OutputFolder=Debug
+Debug=$(TargetFName)
+
+[Config.1]
+ConfigName=Release
+Target=$(ProjectSFile).elf
+OutputFolder=Release
+Debug=$(TargetFName)
+
+[Root]
+ElemType=Project
+PathName=raisonance
+Child=Root.Source Files
+Config.0=Root.Config.0
+Config.1=Root.Config.1
+
+[Root.Config.0]
+Settings.0.0=Root.Config.0.Settings.0
+Settings.0.1=Root.Config.0.Settings.1
+Settings.0.2=Root.Config.0.Settings.2
+Settings.0.3=Root.Config.0.Settings.3
+Settings.0.4=Root.Config.0.Settings.4
+Settings.0.5=Root.Config.0.Settings.5
+Settings.0.6=Root.Config.0.Settings.6
+Settings.0.7=Root.Config.0.Settings.7
+Settings.0.8=Root.Config.0.Settings.8
+
+[Root.Config.1]
+Settings.1.0=Root.Config.1.Settings.0
+Settings.1.1=Root.Config.1.Settings.1
+Settings.1.2=Root.Config.1.Settings.2
+Settings.1.3=Root.Config.1.Settings.3
+Settings.1.4=Root.Config.1.Settings.4
+Settings.1.5=Root.Config.1.Settings.5
+Settings.1.6=Root.Config.1.Settings.6
+Settings.1.7=Root.Config.1.Settings.7
+Settings.1.8=Root.Config.1.Settings.8
+
+[Root.Config.0.Settings.0]
+String.6.0=2010,6,4,10,30,46
+String.100.0=ST Assembler Linker
+String.100.1=ST7 Cosmic
+String.100.2=STM8 Cosmic
+String.100.3=ST7 Metrowerks V1.1
+String.100.4=Raisonance
+String.101.0=Raisonance
+String.102.0=C:\Program Files\Raisonance\Ride
+String.103.0=bin
+String.104.0=INC\ST7;INC
+String.105.0=LIB\ST7
+String.106.0=Debug
+String.107.0=$(ProjectSFile).elf
+Int.108=0
+
+[Root.Config.0.Settings.1]
+String.6.0=2010,6,4,10,10,40
+String.100.0=$(TargetFName)
+String.101.0=
+String.102.0=
+String.103.0=.\;..\demo;..\..\..\boards\st_stm8s_discovery;..\..\..\os\kernel\src;..\..\..\os\kernel\include;..\..\..\os\hal\include;..\..\..\os\hal\platforms\stm8;..\..\..\os\hal\src;..\..\..\test;..\..\..\os\ports\rc\stm8;
+
+[Root.Config.0.Settings.2]
+String.2.0=
+String.6.0=2010,6,4,10,10,40
+String.100.0=STM8S105C6
+
+[Root.Config.0.Settings.3]
+String.2.0=Compiling $(InputFile)...
+String.3.0=rcstm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) WRV(0) STM8(SMALL) DEBUG DGC(data) AUTO -customDebugOpt -CustomOptimOT(0) -CustomBasicLstPR($(IntermPath)$(InputName).lst) CD CO SB LAOB PIN(..\..\..\test) PIN(..\..\..\os\hal\include) PIN(..\..\..\os\hal\platforms\stm8) PIN(..\..\..\boards\st_stm8s_discovery) PIN(..\..\..\os\ports\RC\stm8) PIN(..\..\..\os\kernel\include) PIN(..\demo)
+String.4.0=$(IntermPath)$(InputName).$(ObjectExt)
+String.5.0=$(IntermPath)$(InputName).lst
+String.6.0=2010,6,4,11,38,46
+
+[Root.Config.0.Settings.4]
+String.2.0=Assembling $(InputFile)...
+String.3.0=mastm8 $(InputFile) OBJECT($(IntermPath)$(InputName).$(ObjectExt)) $(ToolsetIncOpts) QUIET DEBUG NOPR ERRORPRINT MODESTM8
+String.4.0=$(IntermPath)$(InputName).$(ObjectExt)
+String.5.0=$(IntermPath)$(InputName).lst
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+
+[Root.Config.0.Settings.5]
+String.2.0=Running Pre-Link step
+String.6.0=2010,6,4,10,10,40
+String.8.0=
+
+[Root.Config.0.Settings.6]
+String.2.0=Running Linker
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+String.3.1=omf2elf $(OutputPath)$(TargetSName).aof
+String.4.0=$(OutputPath)$(TargetFName)
+String.5.0=$(OutputPath)$(ProjectSFile).elf $(OutputPath)$(TargetSName).map
+String.6.0=2010,6,4,12,15,0
+String.100.0= DATASTART(0x0) RAMSIZE(0x800) CODESTART(0x8000) CODESIZE(0x8000) STACKTOP(0x800) STACKSIZE(0x100) EEPROMSTART(0x4000) EEPROMSIZE(0x400)
+String.101.0=
+String.102.0=
+Int.0=0
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+
+[Root.Config.0.Settings.7]
+String.2.0=Running Post-Build step
+String.3.0=omf2hex $(OutputPath)$(TargetSName).aof HEX
+String.6.0=2010,6,4,10,10,40
+
+[Root.Config.0.Settings.8]
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+
+[Root.Config.1.Settings.0]
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+String.107.0=$(ProjectSFile).elf
+Int.108=0
+
+[Root.Config.1.Settings.1]
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+String.100.0=$(TargetFName)
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+
+[Root.Config.1.Settings.2]
+String.2.0=
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+String.100.0=STM8S105C6
+
+[Root.Config.1.Settings.3]
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+String.4.0=$(IntermPath)$(InputName).$(ObjectExt)
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+
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+
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+String.8.0=
+
+[Root.Config.1.Settings.6]
+String.2.0=Running Linker
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+String.3.1=omf2elf $(OutputPath)$(TargetSName).aof
+String.4.0=$(OutputPath)$(TargetFName)
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+String.101.0=
+String.102.0=
+Int.0=0
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+
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+String.6.0=2010,6,4,10,10,40
+
+[Root.Config.1.Settings.8]
+String.2.0=Performing Custom Build on $(InputFile)
+String.6.0=2010,6,4,10,10,40
+
+[Root.Source Files]
+ElemType=Folder
+PathName=Source Files
+Child=Root.Source Files...\demo\main.c
+Next=Root.Include Files
+Config.0=Root.Source Files.Config.0
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+
+[Root.Source Files.Config.0]
+Settings.0.0=Root.Source Files.Config.0.Settings.0
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+PathName=..\..\..\test\testthd.h \ No newline at end of file
diff --git a/docs/Doxyfile b/docs/Doxyfile
index a36862b53..560912bd5 100644
--- a/docs/Doxyfile
+++ b/docs/Doxyfile
@@ -608,6 +608,7 @@ INPUT = ../docs/src \
../os/ports/GCC/PPC \
../os/ports/GCC/PPC/crt0.s \
../os/ports/GCC/MSP430 \
+ ../os/ports/cosmic/STM8 \
../os/ports/RC/STM8 \
../os/hal \
../os/hal/include \
diff --git a/docs/reports/STM8S105-16-Cosmic.txt b/docs/reports/STM8S105-16-Cosmic.txt
new file mode 100644
index 000000000..40926be0f
--- /dev/null
+++ b/docs/reports/STM8S105-16-Cosmic.txt
@@ -0,0 +1,158 @@
+***************************************************************************
+Options: Optimized for speed
+Settings: CPUCLK=16MHz (HSI)
+Compiler: Cosmic STM8 compiler 4.3.3.3.
+***************************************************************************
+
+*** ChibiOS/RT test suite
+***
+*** Kernel: 1.5.8unstable
+*** Architecture: STM8
+*** Platform: STM8x
+*** Test Board: ST STM8S-Discovery
+
+----------------------------------------------------------------------------
+--- Test Case 1.1 (Threads, enqueuing test #1)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 1.2 (Threads, enqueuing test #2)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 1.3 (Threads, priority change)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 1.4 (Threads, delays)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 2.1 (Semaphores, enqueuing)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 2.2 (Semaphores, timeout)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 2.3 (Semaphores, atomic signal-wait)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 3.1 (Mutexes, priority enqueuing test)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 3.2 (Mutexes, priority inheritance, simple case)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 3.3 (Mutexes, priority inheritance, complex case)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 3.4 (Mutexes, priority return)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 3.5 (Mutexes, status)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 3.6 (CondVar, signal test)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 3.7 (CondVar, broadcast test)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 3.8 (CondVar, boost test)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 4.1 (Messages, loop)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 5.1 (Mailboxes, queuing and timeouts)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 6.1 (Events, registration and dispatch)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 6.2 (Events, wait and broadcast)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 6.3 (Events, timeouts)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 7.1 (Heap, allocation and fragmentation test)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 8.1 (Memory Pools, queue/dequeue)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 9.1 (Dynamic APIs, threads creation from heap)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 9.3 (Dynamic APIs, registry and references)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 10.1 (Queues, input queues)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 10.2 (Queues, output queues)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 11.1 (Benchmark, messages #1)
+--- Score : 36081 msgs/S, 72162 ctxswc/S
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 11.2 (Benchmark, messages #2)
+--- Score : 28594 msgs/S, 57188 ctxswc/S
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 11.3 (Benchmark, messages #3)
+--- Score : 28594 msgs/S, 57188 ctxswc/S
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 11.4 (Benchmark, context switch)
+--- Score : 138392 ctxswc/S
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 11.5 (Benchmark, threads, full cycle)
+--- Score : 20867 threads/S
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 11.6 (Benchmark, threads, create only)
+--- Score : 32356 threads/S
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads)
+--- Score : 9234 reschedules/S, 55404 ctxswc/S
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 11.8 (Benchmark, round robin context switching)
+--- Score : 70960 ctxswc/S
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 11.9 (Benchmark, I/O Queues throughput)
+--- Score : 89420 bytes/S
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 11.10 (Benchmark, virtual timers set/reset)
+--- Score : 72654 timers/S
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 11.11 (Benchmark, semaphores wait/signal)
+--- Score : 291932 wait+signal/S
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 11.12 (Benchmark, mutexes lock/unlock)
+--- Score : 147316 lock+unlock/S
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 11.13 (Benchmark, RAM footprint)
+--- System: 218 bytes
+--- Thread: 32 bytes
+--- Timer : 10 bytes
+--- Semaph: 5 bytes
+--- EventS: 2 bytes
+--- EventL: 5 bytes
+--- Mutex : 8 bytes
+--- CondV.: 4 bytes
+--- Queue : 15 bytes
+--- MailB.: 18 bytes
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+
+Final result: SUCCESS
diff --git a/docs/reports/STM8S105-16-Raisonance.txt b/docs/reports/STM8S105-16-Raisonance.txt
new file mode 100644
index 000000000..e65e9014f
--- /dev/null
+++ b/docs/reports/STM8S105-16-Raisonance.txt
@@ -0,0 +1,158 @@
+***************************************************************************
+Options: Optimized for speed
+Settings: CPUCLK=16MHz (HSI)
+Compiler: Raisonance RKit-STM8_2.28.10.0092
+***************************************************************************
+
+*** ChibiOS/RT test suite
+***
+*** Kernel: 1.5.8unstable
+*** Architecture: STM8
+*** Platform: STM8x
+*** Test Board: ST STM8S-Discovery
+
+----------------------------------------------------------------------------
+--- Test Case 1.1 (Threads, enqueuing test #1)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 1.2 (Threads, enqueuing test #2)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 1.3 (Threads, priority change)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 1.4 (Threads, delays)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 2.1 (Semaphores, enqueuing)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 2.2 (Semaphores, timeout)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 2.3 (Semaphores, atomic signal-wait)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 3.1 (Mutexes, priority enqueuing test)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 3.2 (Mutexes, priority inheritance, simple case)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 3.3 (Mutexes, priority inheritance, complex case)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 3.4 (Mutexes, priority return)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 3.5 (Mutexes, status)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 3.6 (CondVar, signal test)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 3.7 (CondVar, broadcast test)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 3.8 (CondVar, boost test)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 4.1 (Messages, loop)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 5.1 (Mailboxes, queuing and timeouts)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 6.1 (Events, registration and dispatch)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 6.2 (Events, wait and broadcast)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 6.3 (Events, timeouts)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 7.1 (Heap, allocation and fragmentation test)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 8.1 (Memory Pools, queue/dequeue)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 9.1 (Dynamic APIs, threads creation from heap)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 9.2 (Dynamic APIs, threads creation from memory pool)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 9.3 (Dynamic APIs, registry and references)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 10.1 (Queues, input queues)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 10.2 (Queues, output queues)
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 11.1 (Benchmark, messages #1)
+--- Score : 31524 msgs/S, 63048 ctxswc/S
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 11.2 (Benchmark, messages #2)
+--- Score : 24143 msgs/S, 48286 ctxswc/S
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 11.3 (Benchmark, messages #3)
+--- Score : 24143 msgs/S, 48286 ctxswc/S
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 11.4 (Benchmark, context switch)
+--- Score : 110424 ctxswc/S
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 11.5 (Benchmark, threads, full cycle)
+--- Score : 17149 threads/S
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 11.6 (Benchmark, threads, create only)
+--- Score : 25946 threads/S
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads)
+--- Score : 6971 reschedules/S, 41826 ctxswc/S
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 11.8 (Benchmark, round robin context switching)
+--- Score : 54880 ctxswc/S
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 11.9 (Benchmark, I/O Queues throughput)
+--- Score : 63392 bytes/S
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 11.10 (Benchmark, virtual timers set/reset)
+--- Score : 55688 timers/S
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 11.11 (Benchmark, semaphores wait/signal)
+--- Score : 216712 wait+signal/S
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 11.12 (Benchmark, mutexes lock/unlock)
+--- Score : 114572 lock+unlock/S
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+--- Test Case 11.13 (Benchmark, RAM footprint)
+--- System: 214 bytes
+--- Thread: 32 bytes
+--- Timer : 10 bytes
+--- Semaph: 5 bytes
+--- EventS: 2 bytes
+--- EventL: 5 bytes
+--- Mutex : 8 bytes
+--- CondV.: 4 bytes
+--- Queue : 15 bytes
+--- MailB.: 18 bytes
+--- Result: SUCCESS
+----------------------------------------------------------------------------
+
+Final result: SUCCESS
diff --git a/os/hal/platforms/STM8/hal_lld.c b/os/hal/platforms/STM8/hal_lld.c
index b0d3883d6..77458da41 100644
--- a/os/hal/platforms/STM8/hal_lld.c
+++ b/os/hal/platforms/STM8/hal_lld.c
@@ -49,9 +49,13 @@ ROMCONST PALConfig pal_default_config =
{VAL_GPIODODR, 0, VAL_GPIODDDR, VAL_GPIODCR1, VAL_GPIODCR2},
{VAL_GPIOEODR, 0, VAL_GPIOEDDR, VAL_GPIOECR1, VAL_GPIOECR2},
{VAL_GPIOFODR, 0, VAL_GPIOFDDR, VAL_GPIOFCR1, VAL_GPIOFCR2},
+#if defined(STM8S207) || defined(STM8S208) || defined(STM8S105)
{VAL_GPIOGODR, 0, VAL_GPIOGDDR, VAL_GPIOGCR1, VAL_GPIOGCR2},
+#endif
+#if defined(STM8S207) || defined(STM8S208)
{VAL_GPIOHODR, 0, VAL_GPIOHDDR, VAL_GPIOHCR1, VAL_GPIOHCR2},
- {VAL_GPIOIODR, 0, VAL_GPIOIDDR, VAL_GPIOICR1, VAL_GPIOICR2}
+ {VAL_GPIOIODR, 0, VAL_GPIOIDDR, VAL_GPIOICR1, VAL_GPIOICR2},
+#endif
}
};
@@ -74,37 +78,37 @@ void hal_lld_init(void) {
#if STM8_CLOCK_SOURCE != CLK_SOURCE_DEFAULT
#if STM8_CLOCK_SOURCE == CLK_SOURCE_HSI
- CLK_ICKR = 1; /* HSIEN */
- while ((CLK_ICKR & 2) == 0) /* HSIRDY */
+ CLK->ICKR = 1; /* HSIEN */
+ while ((CLK->ICKR & 2) == 0) /* HSIRDY */
;
#elif STM8_CLOCK_SOURCE == CLK_SOURCE_LSI
- CLK_ICKR = 8; /* LSIEN */
- while ((CLK_ICKR & 16) == 0) /* LSIRDY */
+ CLK->ICKR = 8; /* LSIEN */
+ while ((CLK->ICKR & 16) == 0) /* LSIRDY */
;
#else /* STM8_CLOCK_SOURCE == CLK_SOURCE_HSE */
- CLK_ECKR = 1; /* HSEEN */
- while ((CLK_ECKR & 2) == 0) /* HSERDY */
+ CLK->ECKR = 1; /* HSEEN */
+ while ((CLK->ECKR & 2) == 0) /* HSERDY */
;
#endif
#if STM8_CLOCK_SOURCE != CLK_SOURCE_HSI
/* Switching clock (manual switch mode).*/
- CLK_SWCR = 0;
- CLK_SWR = STM8_CLOCK_SOURCE;
- while ((CLK_SWCR & 8) == 0) /* SWIF */
+ CLK->SWCR = 0;
+ CLK->SWR = STM8_CLOCK_SOURCE;
+ while ((CLK->SWCR & 8) == 0) /* SWIF */
;
- CLK_SWCR = 2; /* SWEN */
+ CLK->SWCR = 2; /* SWEN */
#endif
/* Setting up clock dividers.*/
- CLK_CKDIVR = (STM8_HSI_DIVIDER << 3) | (STM8_CPU_DIVIDER << 0);
+ CLK->CKDIVR = (STM8_HSI_DIVIDER << 3) | (STM8_CPU_DIVIDER << 0);
/* Clocks initially all disabled.*/
- CLK_PCKENR1 = 0;
- CLK_PCKENR2 = 0;
+ CLK->PCKENR1 = 0;
+ CLK->PCKENR2 = 0;
/* Other clock related initializations.*/
- CLK_CSSR = 0;
- CLK_CCOR = 0;
- CLK_CANCCR = 0;
+ CLK->CSSR = 0;
+ CLK->CCOR = 0;
+ CLK->CANCCR = 0;
#endif /* STM8_CLOCK_SOURCE != CLK_SOURCE_DEFAULT */
}
diff --git a/os/hal/platforms/STM8/pal_lld.h b/os/hal/platforms/STM8/pal_lld.h
index 41b2a2ace..cd819e7ef 100644
--- a/os/hal/platforms/STM8/pal_lld.h
+++ b/os/hal/platforms/STM8/pal_lld.h
@@ -51,17 +51,6 @@
/*===========================================================================*/
/**
- * @brief GPIO port representation.
- */
-typedef struct {
- volatile uint8_t ODR;
- volatile uint8_t IDR;
- volatile uint8_t DDR;
- volatile uint8_t CR1;
- volatile uint8_t CR2;
-} gpio_t;
-
-/**
* @brief Generic I/O ports static initializer.
* @details An instance of this structure must be passed to @p palInit() at
* system startup time in order to initialized the digital I/O
@@ -69,7 +58,14 @@ typedef struct {
* or whole ports can be reprogrammed at later time.
*/
typedef struct {
- gpio_t P[9];
+#if defined(STM8S207) || defined(STM8S208) || defined(STM8S105) || \
+ defined(__DOXYGEN__)
+ GPIO_TypeDef P[7];
+#elif defined(STM8S207) || defined(STM8S208)
+ GPIO_TypeDef P[9];
+#else
+ GPIO_TypeDef P[6];
+#endif
} PALConfig;
/**
@@ -91,7 +87,7 @@ typedef uint8_t ioportmask_t;
/**
* @brief Port Identifier.
*/
-typedef gpio_t *ioportid_t;
+typedef GPIO_TypeDef *ioportid_t;
/*===========================================================================*/
/* I/O Ports Identifiers. */
@@ -105,56 +101,52 @@ typedef gpio_t *ioportid_t;
/**
* @brief GPIO port A identifier.
*/
-#define IOPORT1 ((gpio_t *)0x5000)
-#define GPIOA IOPORT1
+#define IOPORT1 GPIOA
/**
* @brief GPIO port B identifier.
*/
-#define IOPORT2 ((gpio_t *)0x5005)
-#define GPIOB IOPORT2
+#define IOPORT2 GPIOB
/**
* @brief GPIO port C identifier.
*/
-#define IOPORT3 ((gpio_t *)0x500A)
-#define GPIOC IOPORT3
+#define IOPORT3 GPIOC
/**
* @brief GPIO port D identifier.
*/
-#define IOPORT4 ((gpio_t *)0x500F)
-#define GPIOD IOPORT4
+#define IOPORT4 GPIOD
/**
* @brief GPIO port E identifier.
*/
-#define IOPORT5 ((gpio_t *)0x5014)
-#define GPIOE IOPORT5
+#define IOPORT5 GPIOE
/**
* @brief GPIO port F identifier.
*/
-#define IOPORT6 ((gpio_t *)0x5019)
-#define GPIOF IOPORT6
+#define IOPORT6 GPIOF
+#if defined(STM8S207) || defined(STM8S208) || defined(STM8S105) || \
+ defined(__DOXYGEN__)
/**
* @brief GPIO port G identifier.
*/
-#define IOPORT7 ((gpio_t *)0x501E)
-#define GPIOG IOPORT7
+#define IOPORT7 GPIOG
+#endif
+#if defined(STM8S207) || defined(STM8S208) || defined(__DOXYGEN__)
/**
* @brief GPIO port H identifier.
*/
-#define IOPORT8 ((gpio_t *)0x5023)
-#define GPIOH IOPORT8
+#define IOPORT8 GPIOH
/**
* @brief GPIO port I identifier.
*/
-#define IOPORT9 ((gpio_t *)0x5028)
-#define GPIOI IOPORT9
+#define IOPORT9 GPIOI
+#endif
/*===========================================================================*/
/* Implementation, some of the following macros could be implemented as */
diff --git a/os/hal/platforms/STM8/platform.dox b/os/hal/platforms/STM8/platform.dox
index 20a2637af..0a6dbbb80 100644
--- a/os/hal/platforms/STM8/platform.dox
+++ b/os/hal/platforms/STM8/platform.dox
@@ -19,9 +19,9 @@
/**
* @defgroup STM8_DRIVERS STM8 Drivers
- * @brief STM8 specific support.
+ * @brief Device drivers included in the STM8 support.
*
- * @ingroup platforms
+ * @ingroup STM8
*/
/**
diff --git a/os/hal/platforms/STM8/serial_lld.c b/os/hal/platforms/STM8/serial_lld.c
index e1549de7c..a51c1b00e 100644
--- a/os/hal/platforms/STM8/serial_lld.c
+++ b/os/hal/platforms/STM8/serial_lld.c
@@ -28,30 +28,6 @@
#include "ch.h"
#include "hal.h"
-/* Because someone somewhere couldn't use the same name for the same thing.*/
-#if STM8_PLATFORM == PLATFORM_STM8AF51AA
-#define UART1_BRR1 USART_BRR1
-#define UART1_BRR2 USART_BRR2
-#define UART1_SR USART_SR
-#define UART1_DR USART_DR
-#define UART1_CR1 USART_CR1
-#define UART1_CR2 USART_CR2
-#define UART1_CR3 USART_CR3
-#define UART1_CR4 USART_CR4
-#define UART1_CR5 USART_CR5
-
-#define UART3_BRR1 LINUART_BRR1
-#define UART3_BRR2 LINUART_BRR2
-#define UART3_SR LINUART_SR
-#define UART3_DR LINUART_DR
-#define UART3_CR1 LINUART_CR1
-#define UART3_CR2 LINUART_CR2
-#define UART3_CR3 LINUART_CR3
-#define UART3_CR4 LINUART_CR4
-#define UART3_CR5 LINUART_CR5
-#define UART3_CR6 LINUART_CR6
-#endif
-
#if CH_HAL_USE_SERIAL || defined(__DOXYGEN__)
/*===========================================================================*/
@@ -66,6 +42,13 @@ SerialDriver SD1;
#endif
/**
+ * @brief UART2 serial driver identifier.
+ */
+#if USE_STM8_UART2 || defined(__DOXYGEN__)
+SerialDriver SD2;
+#endif
+
+/**
* @brief UART3 serial driver identifier.
*/
#if USE_STM8_UART3 || defined(__DOXYGEN__)
@@ -91,13 +74,15 @@ static ROMCONST SerialConfig default_config = {
static void set_error(SerialDriver *sdp, uint8_t sr) {
sdflags_t sts = 0;
- if (sr & 0x08) /* OR bit. */
+ /* Note, SR register bit definitions are equal for all UARTs so using
+ the UART1 definitions is fine.*/
+ if (sr & UART1_SR_OR)
sts |= SD_OVERRUN_ERROR;
- if (sr & 0x04) /* NF bit. */
+ if (sr & UART1_SR_NF)
sts |= SD_NOISE_ERROR;
- if (sr & 0x02) /* FE bit. */
+ if (sr & UART1_SR_FE)
sts |= SD_FRAMING_ERROR;
- if (sr & 0x01) /* PE bit. */
+ if (sr & UART1_SR_PE)
sts |= SD_PARITY_ERROR;
chSysLockFromIsr();
sdAddFlagsI(sdp, sts);
@@ -107,7 +92,7 @@ static void set_error(SerialDriver *sdp, uint8_t sr) {
#if USE_STM8_UART1 || defined(__DOXYGEN__)
static void notify1(void) {
- UART1_CR2 |= 0x80; /* TIEN bit. */
+ UART1->CR2 |= UART1_CR2_TIEN;
}
/**
@@ -117,18 +102,18 @@ static void notify1(void) {
*/
static void uart1_init(const SerialConfig *config) {
- UART1_BRR2 = ((uint8_t)(config->sc_brr >> 8) & (uint8_t)0xF0) |
- ((uint8_t)config->sc_brr & (uint8_t)0x0F);
- UART1_BRR1 = (uint8_t)(config->sc_brr >> 4);
- UART1_CR1 = config->sc_mode &
- SD_MODE_PARITY; /* PIEN included. */
- UART1_CR2 = 0x2C; /* RIEN | TEN | REN. */
- UART1_CR3 = config->sc_mode & SD_MODE_STOP;
- UART1_CR4 = 0;
- UART1_CR5 = 0;
- UART1_PSCR = 1;
- (void)UART1_SR;
- (void)UART1_DR;
+ UART1->BRR2 = (uint8_t)(((uint8_t)(config->sc_brr >> 8) & (uint8_t)0xF0) |
+ ((uint8_t)config->sc_brr & (uint8_t)0x0F));
+ UART1->BRR1 = (uint8_t)(config->sc_brr >> 4);
+ UART1->CR1 = (uint8_t)(config->sc_mode &
+ SD_MODE_PARITY); /* PIEN included. */
+ UART1->CR2 = UART1_CR2_RIEN | UART1_CR2_TEN | UART1_CR2_REN;
+ UART1->CR3 = (uint8_t)(config->sc_mode & SD_MODE_STOP);
+ UART1->CR4 = 0;
+ UART1->CR5 = 0;
+ UART1->PSCR = 1;
+ (void)UART1->SR;
+ (void)UART1->DR;
}
/**
@@ -136,19 +121,62 @@ static void uart1_init(const SerialConfig *config) {
*/
static void uart1_deinit(void) {
- UART1_CR1 = 0x20; /* UARTD (low power). */
- UART1_CR2 = 0;
- UART1_CR3 = 0;
- UART1_CR4 = 0;
- UART1_CR5 = 0;
- UART1_PSCR = 0;
+ UART1->CR1 = UART1_CR1_UARTD;
+ UART1->CR2 = 0;
+ UART1->CR3 = 0;
+ UART1->CR4 = 0;
+ UART1->CR5 = 0;
+ UART1->PSCR = 0;
+}
+#endif /* USE_STM8_UART1 */
+
+#if USE_STM8_UART2 || defined(__DOXYGEN__)
+static void notify2(void) {
+
+ UART2->CR2 |= UART2_CR2_TIEN;
+}
+
+/**
+ * @brief UART2 initialization.
+ *
+ * @param[in] config architecture-dependent serial driver configuration
+ */
+static void uart2_init(const SerialConfig *config) {
+
+ UART2->BRR2 = (uint8_t)(((uint8_t)(config->sc_brr >> 8) & (uint8_t)0xF0) |
+ ((uint8_t)config->sc_brr & (uint8_t)0x0F));
+ UART2->BRR1 = (uint8_t)(config->sc_brr >> 4);
+ UART2->CR1 = (uint8_t)(config->sc_mode &
+ SD_MODE_PARITY); /* PIEN included. */
+ UART2->CR2 = UART2_CR2_RIEN | UART2_CR2_TEN | UART2_CR2_REN;
+ UART2->CR3 = (uint8_t)(config->sc_mode & SD_MODE_STOP);
+ UART2->CR4 = 0;
+ UART2->CR5 = 0;
+ UART2->CR6 = 0;
+ UART2->PSCR = 1;
+ (void)UART2->SR;
+ (void)UART2->DR;
+}
+
+/**
+ * @brief UART1 de-initialization.
+ */
+static void uart2_deinit(void) {
+
+ UART2->CR1 = UART2_CR1_UARTD;
+ UART2->CR2 = 0;
+ UART2->CR3 = 0;
+ UART2->CR4 = 0;
+ UART2->CR5 = 0;
+ UART2->CR6 = 0;
+ UART2->PSCR = 0;
}
#endif /* USE_STM8_UART1 */
#if USE_STM8_UART3 || defined(__DOXYGEN__)
static void notify3(void) {
- UART3_CR2 |= 0x80; /* TIEN bit. */
+ UART3->CR2 |= UART3_CR2_TIEN;
}
/**
@@ -158,17 +186,17 @@ static void notify3(void) {
*/
static void uart3_init(const SerialConfig *config) {
- UART3_BRR2 = ((uint8_t)(config->sc_brr >> 8) & (uint8_t)0xF0) |
- ((uint8_t)config->sc_brr & (uint8_t)0x0F);
- UART3_BRR1 = (uint8_t)(config->sc_brr >> 4);
- UART3_CR1 = config->sc_mode &
- SD_MODE_PARITY; /* PIEN included. */
- UART3_CR2 = 0x2C; /* RIEN | TEN | REN. */
- UART3_CR3 = config->sc_mode & SD_MODE_STOP;
- UART3_CR4 = 0;
- UART3_CR6 = 0;
- (void)UART3_SR;
- (void)UART3_DR;
+ UART3->BRR2 = (uint8_t)(((uint8_t)(config->sc_brr >> 8) & (uint8_t)0xF0) |
+ ((uint8_t)config->sc_brr & (uint8_t)0x0F));
+ UART3->BRR1 = (uint8_t)(config->sc_brr >> 4);
+ UART3->CR1 = (uint8_t)(config->sc_mode &
+ SD_MODE_PARITY); /* PIEN included. */
+ UART3->CR2 = UART3_CR2_RIEN | UART3_CR2_TEN | UART3_CR2_REN;
+ UART3->CR3 = (uint8_t)(config->sc_mode & SD_MODE_STOP);
+ UART3->CR4 = 0;
+ UART3->CR6 = 0;
+ (void)UART3->SR;
+ (void)UART3->DR;
}
/**
@@ -176,11 +204,11 @@ static void uart3_init(const SerialConfig *config) {
*/
static void uart3_deinit(void) {
- UART3_CR1 = 0x20; /* UARTD (low power). */
- UART3_CR2 = 0;
- UART3_CR3 = 0;
- UART3_CR4 = 0;
- UART3_CR6 = 0;
+ UART3->CR1 = UART3_CR1_UARTD;
+ UART3->CR2 = 0;
+ UART3->CR3 = 0;
+ UART3->CR4 = 0;
+ UART3->CR6 = 0;
}
#endif /* USE_STM8_UART3 */
@@ -198,28 +226,62 @@ CH_IRQ_HANDLER(17) {
b = sdRequestDataI(&SD1);
chSysUnlockFromIsr();
if (b < Q_OK)
- UART1_CR2 &= ~0x80; /* TIEN. */
+ UART1->CR2 &= (uint8_t)~UART1_CR2_TIEN;
else
- UART1_DR = b;
+ UART1->DR = (uint8_t)b;
CH_IRQ_EPILOGUE();
}
CH_IRQ_HANDLER(18) {
- uint8_t sr = UART1_SR;
+ uint8_t sr = UART1->SR;
CH_IRQ_PROLOGUE();
- if ((sr = UART1_SR) & 0x0F) /* OR | BF | FE | PE. */
+ if ((sr = UART1->SR) & (UART1_SR_OR | UART1_SR_NF |
+ UART1_SR_FE | UART1_SR_PE))
set_error(&SD1, sr);
chSysLockFromIsr();
- sdIncomingDataI(&SD1, UART1_DR);
+ sdIncomingDataI(&SD1, UART1->DR);
chSysUnlockFromIsr();
CH_IRQ_EPILOGUE();
}
#endif /* USE_STM8_UART1 */
+#if USE_STM8_UART2 || defined(__DOXYGEN__)
+CH_IRQ_HANDLER(20) {
+ msg_t b;
+
+ CH_IRQ_PROLOGUE();
+
+ chSysLockFromIsr();
+ b = sdRequestDataI(&SD2);
+ chSysUnlockFromIsr();
+ if (b < Q_OK)
+ UART2->CR2 &= (uint8_t)~UART2_CR2_TIEN;
+ else
+ UART2->DR = (uint8_t)b;
+
+ CH_IRQ_EPILOGUE();
+}
+
+CH_IRQ_HANDLER(21) {
+ uint8_t sr = UART2->SR;
+
+ CH_IRQ_PROLOGUE();
+
+ if ((sr = UART2->SR) & (UART2_SR_OR | UART2_SR_NF |
+ UART2_SR_FE | UART2_SR_PE))
+ set_error(&SD2, sr);
+ chSysLockFromIsr();
+ sdIncomingDataI(&SD2, UART2->DR);
+ chSysUnlockFromIsr();
+
+ CH_IRQ_EPILOGUE();
+}
+#endif /* USE_STM8_UART2 */
+
#if USE_STM8_UART3 || defined(__DOXYGEN__)
CH_IRQ_HANDLER(20) {
msg_t b;
@@ -230,22 +292,23 @@ CH_IRQ_HANDLER(20) {
b = sdRequestDataI(&SD3);
chSysUnlockFromIsr();
if (b < Q_OK)
- UART3_CR2 &= ~0x80; /* TIEN. */
+ UART3->CR2 &= (uint8_t)~UART3_CR2_TIEN;
else
- UART3_DR = b;
+ UART3->DR = (uint8_t)b;
CH_IRQ_EPILOGUE();
}
CH_IRQ_HANDLER(21) {
- uint8_t sr = UART3_SR;
+ uint8_t sr = UART3->SR;
CH_IRQ_PROLOGUE();
- if ((sr = UART3_SR) & 0x0F) /* OR | BF | FE | PE. */
+ if ((sr = UART3->SR) & (UART3_SR_OR | UART3_SR_NF |
+ UART3_SR_FE | UART3_SR_PE))
set_error(&SD3, sr);
chSysLockFromIsr();
- sdIncomingDataI(&SD3, UART3_DR);
+ sdIncomingDataI(&SD3, UART3->DR);
chSysUnlockFromIsr();
CH_IRQ_EPILOGUE();
@@ -263,14 +326,20 @@ void sd_lld_init(void) {
#if USE_STM8_UART1
sdObjectInit(&SD1, NULL, notify1);
- CLK_PCKENR1 |= 4; /* PCKEN12, clock source. */
- UART1_CR1 = 0x20; /* UARTD (low power). */
+ CLK->PCKENR1 |= CLK_PCKENR1_UART1; /* PCKEN12, clock source. */
+ UART1->CR1 = UART1_CR1_UARTD; /* UARTD (low power). */
+#endif
+
+#if USE_STM8_UART2
+ sdObjectInit(&SD2, NULL, notify2);
+ CLK->PCKENR1 |= CLK_PCKENR1_UART2; /* PCKEN13, clock source. */
+ UART2->CR1 = UART2_CR1_UARTD; /* UARTD (low power). */
#endif
#if USE_STM8_UART3
sdObjectInit(&SD3, NULL, notify3);
- CLK_PCKENR1 |= 8; /* PCKEN13, clock source. */
- UART3_CR1 = 0x20; /* UARTD (low power). */
+ CLK->PCKENR1 |= CLK_PCKENR1_UART3; /* PCKEN13, clock source. */
+ UART3->CR1 = UART3_CR1_UARTD; /* UARTD (low power). */
#endif
}
@@ -293,6 +362,12 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
return;
}
#endif
+#if USE_STM8_UART2
+ if (&SD2 == sdp) {
+ uart2_init(config);
+ return;
+ }
+#endif
#if USE_STM8_UART3
if (&SD3 == sdp) {
uart3_init(config);
@@ -316,6 +391,12 @@ void sd_lld_stop(SerialDriver *sdp) {
return;
}
#endif
+#if USE_STM8_UART2
+ if (&SD2 == sdp) {
+ uart2_deinit();
+ return;
+ }
+#endif
#if USE_STM8_UART3
if (&SD3 == sdp) {
uart3_deinit();
diff --git a/os/hal/platforms/STM8/serial_lld.h b/os/hal/platforms/STM8/serial_lld.h
index 58b0df012..f0bea84f7 100644
--- a/os/hal/platforms/STM8/serial_lld.h
+++ b/os/hal/platforms/STM8/serial_lld.h
@@ -58,6 +58,15 @@
#endif
/**
+ * @brief UART2 driver enable switch.
+ * @details If set to @p TRUE the support for UART3 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(USE_STM8_UART2) || defined(__DOXYGEN__)
+#define USE_STM8_UART2 TRUE
+#endif
+
+/**
* @brief UART3 driver enable switch.
* @details If set to @p TRUE the support for UART3 is included.
* @note The default is @p TRUE.
@@ -70,6 +79,10 @@
/* Derived constants and error checks. */
/*===========================================================================*/
+#if USE_STM8_UART2 && USE_STM8_UART3
+#error "STM8 UART2 and UART3 cannot be used together"
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@@ -136,6 +149,9 @@ typedef struct {
#if USE_STM8_UART1 && !defined(__DOXYGEN__)
extern SerialDriver SD1;
#endif
+#if USE_STM8_UART2 && !defined(__DOXYGEN__)
+extern SerialDriver SD2;
+#endif
#if USE_STM8_UART3 && !defined(__DOXYGEN__)
extern SerialDriver SD3;
#endif
diff --git a/os/hal/platforms/STM8/stm8.h b/os/hal/platforms/STM8/stm8.h
index a91b3cbaf..d0ef215a4 100644
--- a/os/hal/platforms/STM8/stm8.h
+++ b/os/hal/platforms/STM8/stm8.h
@@ -20,22 +20,17 @@
#ifndef _STM8_H_
#define _STM8_H_
-/*
- * Supported platforms.
- */
-#define PLATFORM_STM8S208RB 1
-#define PLATFORM_STM8AF51AA 2
-
-#ifndef STM8_PLATFORM
-#error "STM8 platform not defined"
-#endif
+#undef FALSE
+#undef TRUE
-#if STM8_PLATFORM == PLATFORM_STM8S208RB
-#include "STM8/STM8S208RB.h"
-#elif STM8_PLATFORM == PLATFORM_STM8AF51AA
-#include "STM8/STM8AF51AA.h"
+#if defined(STM8S208) || defined(STM8S207) || defined(STM8S105) || \
+ defined(STM8S103) || defined (STM8S903)
+#include "stm8s.h"
#else
#error "unsupported or invalid STM8 platform"
#endif
+#define FALSE 0
+#define TRUE (!FALSE)
+
#endif /* _STM8_H_ */
diff --git a/os/hal/platforms/STM8/stm8s.h b/os/hal/platforms/STM8/stm8s.h
new file mode 100644
index 000000000..c210092c3
--- /dev/null
+++ b/os/hal/platforms/STM8/stm8s.h
@@ -0,0 +1,2567 @@
+/**
+ ******************************************************************************
+ * @file stm8s.h
+ * @brief This file contains all HW registers definitions and memory mapping.
+ * @author STMicroelectronics - MCD Application Team
+ * @version V1.1.1
+ * @date 06/05/2009
+ ******************************************************************************
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
+ * @image html logo.bmp
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM8S_H
+#define __STM8S_H
+
+/******************************************************************************/
+/* Library configuration section */
+/******************************************************************************/
+/* Check the used compiler */
+#if defined(__CSMC__)
+ #undef _RAISONANCE_
+ #define _COSMIC_
+#elif defined(__RCST7__)
+ #undef _COSMIC_
+ #define _RAISONANCE_
+#else
+ #error "Unsupported Compiler!" /* Compiler defines not found */
+#endif
+
+/* Uncomment the line below according to the target STM8S device used in your
+ application.
+ Tip: To avoid modifying this file each time you need to switch between these
+ devices, you can define the device in your toolchain compiler preprocessor. */
+#if !defined (STM8S208) && !defined (STM8S207) && !defined (STM8S105) && !defined (STM8S103) && !defined (STM8S903)
+ #define STM8S208
+ /* #define STM8S207 */
+ /* #define STM8S105 */
+ /* #define STM8S103 */
+ /* #define STM8S903 */
+#endif
+
+
+#if !defined USE_STDPERIPH_DRIVER
+/* Comment the line below if you will not use the peripherals drivers.
+ In this case, these drivers will not be included and the application code will be
+ based on direct access to peripherals registers */
+/* #define USE_STDPERIPH_DRIVER*/
+#endif
+
+/* For FLASH routines, select whether pointer will be declared as near (2 bytes, handle
+ code smaller than 64KB) or far (3 bytes, handle code larger than 64K) */
+/*#define PointerAttr_Near 1 */ /*!< Used with memory Models for code smaller than 64K */
+#define PointerAttr_Far 2 /*!< Used with memory Models for code larger than 64K */
+
+#ifdef _COSMIC_
+ #define FAR @far
+ #define NEAR @near
+ #define TINY @tiny
+ #define __CONST const
+#else /* __RCST7__ */
+ #define FAR far
+ #define NEAR data
+ #define TINY page0
+ #define __CONST code
+#endif /* __CSMC__ */
+
+#ifdef PointerAttr_Far
+ #define PointerAttr FAR
+#else /* PointerAttr_Near */
+ #define PointerAttr NEAR
+#endif /* PointerAttr_Far */
+
+
+/* Uncomment the line below to use the cosmic section */
+#if defined(_COSMIC_)
+/* #define USE_COSMIC_SECTIONS (1)*/
+#endif
+
+/******************************************************************************/
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm8s_type.h"
+
+/* Exported types and constants-----------------------------------------------*/
+/** @addtogroup MAP_FILE_Exported_Types_and_Constants
+ * @{
+ */
+
+/******************************************************************************/
+/* IP registers structures */
+/******************************************************************************/
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief General Purpose I/Os (GPIO)
+ */
+
+typedef struct GPIO_struct
+{
+ vu8 ODR; /*!< Output Data Register */
+ vu8 IDR; /*!< Input Data Register */
+ vu8 DDR; /*!< Data Direction Register */
+ vu8 CR1; /*!< Configuration Register 1 */
+ vu8 CR2; /*!< Configuration Register 2 */
+}
+GPIO_TypeDef;
+
+/** @addtogroup GPIO_Registers_Reset_Value
+ * @{
+ */
+
+#define GPIO_ODR_RESET_VALUE ((u8)0x00)
+#define GPIO_DDR_RESET_VALUE ((u8)0x00)
+#define GPIO_CR1_RESET_VALUE ((u8)0x00)
+#define GPIO_CR2_RESET_VALUE ((u8)0x00)
+
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+#if defined(STM8S105) || defined(STM8S103) || defined(STM8S903)
+/**
+ * @brief Analog to Digital Converter (ADC1)
+ */
+typedef struct ADC1_struct
+{
+ vu8 DB0RH; /*!< ADC1 Data Buffer Register (MSB) */
+ vu8 DB0RL; /*!< ADC1 Data Buffer Register (LSB) */
+ vu8 DB1RH; /*!< ADC1 Data Buffer Register (MSB) */
+ vu8 DB1RL; /*!< ADC1 Data Buffer Register (LSB) */
+ vu8 DB2RH; /*!< ADC1 Data Buffer Register (MSB) */
+ vu8 DB2RL; /*!< ADC1 Data Buffer Register (LSB) */
+ vu8 DB3RH; /*!< ADC1 Data Buffer Register (MSB) */
+ vu8 DB3RL; /*!< ADC1 Data Buffer Register (LSB) */
+ vu8 DB4RH; /*!< ADC1 Data Buffer Register (MSB) */
+ vu8 DB4RL; /*!< ADC1 Data Buffer Register (LSB) */
+ vu8 DB5RH; /*!< ADC1 Data Buffer Register (MSB) */
+ vu8 DB5RL; /*!< ADC1 Data Buffer Register (LSB) */
+ vu8 DB6RH; /*!< ADC1 Data Buffer Register (MSB) */
+ vu8 DB6RL; /*!< ADC1 Data Buffer Register (LSB) */
+ vu8 DB7RH; /*!< ADC1 Data Buffer Register (MSB) */
+ vu8 DB7RL; /*!< ADC1 Data Buffer Register (LSB) */
+ vu8 DB8RH; /*!< ADC1 Data Buffer Register (MSB) */
+ vu8 DB8RL; /*!< ADC1 Data Buffer Register (LSB) */
+ vu8 DB9RH; /*!< ADC1 Data Buffer Register (MSB) */
+ vu8 DB9RL; /*!< ADC1 Data Buffer Register (LSB) */
+ vu8 RESERVED[12]; /*!< Reserved byte */
+ vu8 CSR; /*!< ADC1 control status register */
+ vu8 CR1; /*!< ADC1 configuration register 1 */
+ vu8 CR2; /*!< ADC1 configuration register 2 */
+ vu8 CR3; /*!< ADC1 configuration register 3 */
+ vu8 DRH; /*!< ADC1 Data high */
+ vu8 DRL; /*!< ADC1 Data low */
+ vu8 TDRH; /*!< ADC1 Schmitt trigger disable register high */
+ vu8 TDRL; /*!< ADC1 Schmitt trigger disable register low */
+ vu8 HTRH; /*!< ADC1 high threshold register High*/
+ vu8 HTRL; /*!< ADC1 high threshold register Low*/
+ vu8 LTRH; /*!< ADC1 low threshold register high */
+ vu8 LTRL; /*!< ADC1 low threshold register low */
+ vu8 AWSRH; /*!< ADC1 watchdog status register high */
+ vu8 AWSRL; /*!< ADC1 watchdog status register low */
+ vu8 AWCRH; /*!< ADC1 watchdog control register high */
+ vu8 AWCRL; /*!< ADC1 watchdog control register low */
+}
+ADC1_TypeDef;
+
+/** @addtogroup ADC1_Registers_Reset_Value
+ * @{
+ */
+
+#define ADC1_CSR_RESET_VALUE ((u8)0x00)
+#define ADC1_CR1_RESET_VALUE ((u8)0x00)
+#define ADC1_CR2_RESET_VALUE ((u8)0x00)
+#define ADC1_CR3_RESET_VALUE ((u8)0x00)
+#define ADC1_TDRL_RESET_VALUE ((u8)0x00)
+#define ADC1_TDRH_RESET_VALUE ((u8)0x00)
+#define ADC1_HTRL_RESET_VALUE ((u8)0x03)
+#define ADC1_HTRH_RESET_VALUE ((u8)0xFF)
+#define ADC1_LTRH_RESET_VALUE ((u8)0x00)
+#define ADC1_LTRL_RESET_VALUE ((u8)0x00)
+#define ADC1_AWCRH_RESET_VALUE ((u8)0x00)
+#define ADC1_AWCRL_RESET_VALUE ((u8)0x00)
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC1_Registers_Bits_Definition
+ * @{
+ */
+
+#define ADC1_CSR_EOC ((u8)0x80) /*!< End of Conversion mask */
+#define ADC1_CSR_AWD ((u8)0x40) /*!< Analog Watch Dog Status mask */
+#define ADC1_CSR_EOCIE ((u8)0x20) /*!< Interrupt Enable for EOC mask */
+#define ADC1_CSR_AWDIE ((u8)0x10) /*!< Analog Watchdog interrupt enable mask */
+#define ADC1_CSR_CH ((u8)0x0F) /*!< Channel selection bits mask */
+
+#define ADC1_CR1_SPSEL ((u8)0x70) /*!< Prescaler selectiont mask */
+#define ADC1_CR1_CONT ((u8)0x02) /*!< Continuous conversion mask */
+#define ADC1_CR1_ADON ((u8)0x01) /*!< A/D Converter on/off mask */
+
+#define ADC1_CR2_EXTTRIG ((u8)0x40) /*!< External trigger enable mask */
+#define ADC1_CR2_EXTSEL ((u8)0x30) /*!< External event selection mask */
+#define ADC1_CR2_ALIGN ((u8)0x08) /*!< Data Alignment mask */
+#define ADC1_CR2_SCAN ((u8)0x02) /*!< Scan mode mask */
+
+#define ADC1_CR3_DBUF ((u8)0x80) /*!< Data Buffer Enable mask */
+#define ADC1_CR3_OVR ((u8)0x40) /*!< Overrun Status Flag mask */
+
+#endif /* (STM8S105) ||(STM8S103) || (STM8S903) */
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief Analog to Digital Converter (ADC2)
+ */
+#if defined(STM8S208) || defined(STM8S207)
+typedef struct ADC2_struct
+{
+ vu8 CSR; /*!< ADC2 control status register */
+ vu8 CR1; /*!< ADC2 configuration register 1 */
+ vu8 CR2; /*!< ADC2 configuration register 2 */
+ vu8 RESERVED; /*!< Reserved byte */
+ vu8 DRH; /*!< ADC2 Data high */
+ vu8 DRL; /*!< ADC2 Data low */
+ vu8 TDRH; /*!< ADC2 Schmitt trigger disable register high */
+ vu8 TDRL; /*!< ADC2 Schmitt trigger disable register low */
+}
+ADC2_TypeDef;
+
+/** @addtogroup ADC2_Registers_Reset_Value
+ * @{
+ */
+
+#define ADC2_CSR_RESET_VALUE ((u8)0x00)
+#define ADC2_CR1_RESET_VALUE ((u8)0x00)
+#define ADC2_CR2_RESET_VALUE ((u8)0x00)
+#define ADC2_TDRL_RESET_VALUE ((u8)0x00)
+#define ADC2_TDRH_RESET_VALUE ((u8)0x00)
+
+/**
+ * @}
+ */
+
+/** @addtogroup ADC2_Registers_Bits_Definition
+ * @{
+ */
+
+#define ADC2_CSR_EOC ((u8)0x80) /*!< End of Conversion mask */
+#define ADC2_CSR_EOCIE ((u8)0x20) /*!< Interrupt Enable for EOC mask */
+#define ADC2_CSR_CH ((u8)0x0F) /*!< Channel selection bits mask */
+
+#define ADC2_CR1_SPSEL ((u8)0x70) /*!< Prescaler selectiont mask */
+#define ADC2_CR1_CONT ((u8)0x02) /*!< Continuous conversion mask */
+#define ADC2_CR1_ADON ((u8)0x01) /*!< A/D Converter on/off mask */
+
+#define ADC2_CR2_EXTTRIG ((u8)0x40) /*!< External trigger enable mask */
+#define ADC2_CR2_EXTSEL ((u8)0x30) /*!< External event selection mask */
+#define ADC2_CR2_ALIGN ((u8)0x08) /*!< Data Alignment mask */
+
+#endif /* (STM8S208) ||(STM8S207) */
+/**
+ * @}
+ */
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief Auto Wake Up (AWU) peripheral registers.
+ */
+
+typedef struct AWU_struct
+{
+ vu8 CSR; /*!< AWU Control status register */
+ vu8 APR; /*!< AWU Asynchronous prescalar buffer */
+ vu8 TBR; /*!< AWU Time base selection register */
+}
+AWU_TypeDef;
+
+/** @addtogroup AWU_Registers_Reset_Value
+ * @{
+ */
+
+#define AWU_CSR_RESET_VALUE ((u8)0x00)
+#define AWU_APR_RESET_VALUE ((u8)0x3F)
+#define AWU_TBR_RESET_VALUE ((u8)0x00)
+
+/**
+ * @}
+ */
+
+/** @addtogroup AWU_Registers_Bits_Definition
+ * @{
+ */
+
+#define AWU_CSR_AWUF ((u8)0x20) /*!< Interrupt flag mask */
+#define AWU_CSR_AWUEN ((u8)0x10) /*!< Auto Wake-up enable mask */
+#define AWU_CSR_MR ((u8)0x02) /*!< Master Reset mask */
+#define AWU_CSR_MSR ((u8)0x01) /*!< Measurement enable mask */
+
+#define AWU_APR_APR ((u8)0x3F) /*!< Asynchronous Prescaler divider mask */
+
+#define AWU_TBR_AWUTB ((u8)0x0F) /*!< Timebase selection mask */
+
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief Beeper (BEEP) peripheral registers.
+ */
+
+typedef struct BEEP_struct
+{
+ vu8 CSR; /*!< BEEP Control status register */
+}
+BEEP_TypeDef;
+
+/** @addtogroup BEEP_Registers_Reset_Value
+ * @{
+ */
+
+#define BEEP_CSR_RESET_VALUE ((u8)0x1F)
+
+/**
+ * @}
+ */
+
+/** @addtogroup BEEP_Registers_Bits_Definition
+ * @{
+ */
+
+#define BEEP_CSR_BEEPSEL ((u8)0xC0) /*!< Beeper frequency selection mask */
+#define BEEP_CSR_BEEPEN ((u8)0x20) /*!< Beeper enable mask */
+#define BEEP_CSR_BEEPDIV ((u8)0x1F) /*!< Beeper Divider prescalar mask */
+
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief Clock Controller (CLK)
+ */
+
+typedef struct CLK_struct
+{
+ vu8 ICKR; /*!< Internal Clocks Control Register */
+ vu8 ECKR; /*!< External Clocks Control Register */
+ u8 RESERVED; /*!< Reserved byte */
+ vu8 CMSR; /*!< Clock Master Status Register */
+ vu8 SWR; /*!< Clock Master Switch Register */
+ vu8 SWCR; /*!< Switch Control Register */
+ vu8 CKDIVR; /*!< Clock Divider Register */
+ vu8 PCKENR1; /*!< Peripheral Clock Gating Register 1 */
+ vu8 CSSR; /*!< Clock Security Sytem Register */
+ vu8 CCOR; /*!< Configurable Clock Output Register */
+ vu8 PCKENR2; /*!< Peripheral Clock Gating Register 2 */
+ vu8 CANCCR; /*!< CAN external clock control Register (exist only in STM8S208 otherwise it is reserved) */
+ vu8 HSITRIMR; /*!< HSI Calibration Trimmer Register */
+ vu8 SWIMCCR; /*!< SWIM clock control register */
+}
+CLK_TypeDef;
+
+/** @addtogroup CLK_Registers_Reset_Value
+ * @{
+ */
+
+#define CLK_ICKR_RESET_VALUE ((u8)0x01)
+#define CLK_ECKR_RESET_VALUE ((u8)0x00)
+#define CLK_CMSR_RESET_VALUE ((u8)0xE1)
+#define CLK_SWR_RESET_VALUE ((u8)0xE1)
+#define CLK_SWCR_RESET_VALUE ((u8)0x00)
+#define CLK_CKDIVR_RESET_VALUE ((u8)0x18)
+#define CLK_PCKENR1_RESET_VALUE ((u8)0xFF)
+#define CLK_PCKENR2_RESET_VALUE ((u8)0xFF)
+#define CLK_CSSR_RESET_VALUE ((u8)0x00)
+#define CLK_CCOR_RESET_VALUE ((u8)0x00)
+#define CLK_CANCCR_RESET_VALUE ((u8)0x00)
+#define CLK_HSITRIMR_RESET_VALUE ((u8)0x00)
+#define CLK_SWIMCCR_RESET_VALUE ((u8)0x00)
+
+/**
+ * @}
+ */
+
+/** @addtogroup CLK_Registers_Bits_Definition
+ * @{
+ */
+
+#define CLK_ICKR_SWUAH ((u8)0x20) /*!< Slow Wake-up from Active Halt/Halt modes */
+#define CLK_ICKR_LSIRDY ((u8)0x10) /*!< Low speed internal oscillator ready */
+#define CLK_ICKR_LSIEN ((u8)0x08) /*!< Low speed internal RC oscillator enable */
+#define CLK_ICKR_FHWU ((u8)0x04) /*!< Fast Wake-up from Active Halt/Halt mode */
+#define CLK_ICKR_HSIRDY ((u8)0x02) /*!< High speed internal RC oscillator ready */
+#define CLK_ICKR_HSIEN ((u8)0x01) /*!< High speed internal RC oscillator enable */
+
+#define CLK_ECKR_HSERDY ((u8)0x02) /*!< High speed external crystal oscillator ready */
+#define CLK_ECKR_HSEEN ((u8)0x01) /*!< High speed external crystal oscillator enable */
+
+#define CLK_CMSR_CKM ((u8)0xFF) /*!< Clock master status bits */
+
+#define CLK_SWR_SWI ((u8)0xFF) /*!< Clock master selection bits */
+
+#define CLK_SWCR_SWIF ((u8)0x08) /*!< Clock switch interrupt flag */
+#define CLK_SWCR_SWIEN ((u8)0x04) /*!< Clock switch interrupt enable */
+#define CLK_SWCR_SWEN ((u8)0x02) /*!< Switch start/stop */
+#define CLK_SWCR_SWBSY ((u8)0x01) /*!< Switch busy */
+
+#define CLK_CKDIVR_HSIDIV ((u8)0x18) /*!< High speed internal clock prescaler */
+#define CLK_CKDIVR_CPUDIV ((u8)0x07) /*!< CPU clock prescaler */
+
+#define CLK_PCKENR1_TIM1 ((u8)0x80) /*!< Timer 1 clock enable */
+#define CLK_PCKENR1_TIM3 ((u8)0x40) /*!< Timer 3 clock enable */
+#define CLK_PCKENR1_TIM2 ((u8)0x20) /*!< Timer 2 clock enable */
+#define CLK_PCKENR1_TIM5 ((u8)0x20) /*!< Timer 5 clock enable */
+#define CLK_PCKENR1_TIM4 ((u8)0x10) /*!< Timer 4 clock enable */
+#define CLK_PCKENR1_TIM6 ((u8)0x10) /*!< Timer 6 clock enable */
+#define CLK_PCKENR1_UART3 ((u8)0x08) /*!< UART3 clock enable */
+#define CLK_PCKENR1_UART2 ((u8)0x08) /*!< UART2 clock enable */
+#define CLK_PCKENR1_UART1 ((u8)0x04) /*!< UART1 clock enable */
+#define CLK_PCKENR1_SPI ((u8)0x02) /*!< SPI clock enable */
+#define CLK_PCKENR1_I2C ((u8)0x01) /*!< I2C clock enable */
+
+#define CLK_PCKENR2_CAN ((u8)0x80) /*!< CAN clock enable */
+#define CLK_PCKENR2_ADC ((u8)0x08) /*!< ADC clock enable */
+#define CLK_PCKENR2_AWU ((u8)0x04) /*!< AWU clock enable */
+
+#define CLK_CSSR_CSSD ((u8)0x08) /*!< Clock security sytem detection */
+#define CLK_CSSR_CSSDIE ((u8)0x04) /*!< Clock security system detection interrupt enable */
+#define CLK_CSSR_AUX ((u8)0x02) /*!< Auxiliary oscillator connected to master clock */
+#define CLK_CSSR_CSSEN ((u8)0x01) /*!< Clock security system enable */
+
+#define CLK_CCOR_CCOBSY ((u8)0x40) /*!< Configurable clock output busy */
+#define CLK_CCOR_CCORDY ((u8)0x20) /*!< Configurable clock output ready */
+#define CLK_CCOR_CCOSEL ((u8)0x1E) /*!< Configurable clock output selection */
+#define CLK_CCOR_CCOEN ((u8)0x01) /*!< Configurable clock output enable */
+
+#define CLK_CANCCR_CANDIV ((u8)0x07) /*!< External CAN clock divider */
+
+#define CLK_HSITRIMR_HSITRIM ((u8)0x07) /*!< High speed internal oscillator trimmer */
+
+#define CLK_SWIMCCR_SWIMDIV ((u8)0x01) /*!< SWIM Clock Dividing Factor */
+
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief 16-bit timer with complementary PWM outputs (TIM1)
+ */
+
+typedef struct TIM1_struct
+{
+ vu8 CR1; /*!< control register 1 */
+ vu8 CR2; /*!< control register 2 */
+ vu8 SMCR; /*!< Synchro mode control register */
+ vu8 ETR; /*!< external trigger register */
+ vu8 IER; /*!< interrupt enable register*/
+ vu8 SR1; /*!< status register 1 */
+ vu8 SR2; /*!< status register 2 */
+ vu8 EGR; /*!< event generation register */
+ vu8 CCMR1; /*!< CC mode register 1 */
+ vu8 CCMR2; /*!< CC mode register 2 */
+ vu8 CCMR3; /*!< CC mode register 3 */
+ vu8 CCMR4; /*!< CC mode register 4 */
+ vu8 CCER1; /*!< CC enable register 1 */
+ vu8 CCER2; /*!< CC enable register 2 */
+ vu8 CNTRH; /*!< counter high */
+ vu8 CNTRL; /*!< counter low */
+ vu8 PSCRH; /*!< prescaler high */
+ vu8 PSCRL; /*!< prescaler low */
+ vu8 ARRH; /*!< auto-reload register high */
+ vu8 ARRL; /*!< auto-reload register low */
+ vu8 RCR; /*!< Repetition Counter register */
+ vu8 CCR1H; /*!< capture/compare register 1 high */
+ vu8 CCR1L; /*!< capture/compare register 1 low */
+ vu8 CCR2H; /*!< capture/compare register 2 high */
+ vu8 CCR2L; /*!< capture/compare register 2 low */
+ vu8 CCR3H; /*!< capture/compare register 3 high */
+ vu8 CCR3L; /*!< capture/compare register 3 low */
+ vu8 CCR4H; /*!< capture/compare register 3 high */
+ vu8 CCR4L; /*!< capture/compare register 3 low */
+ vu8 BKR; /*!< Break Register */
+ vu8 DTR; /*!< dead-time register */
+ vu8 OISR; /*!< Output idle register */
+}
+TIM1_TypeDef;
+
+/** @addtogroup TIM1_Registers_Reset_Value
+ * @{
+ */
+
+#define TIM1_CR1_RESET_VALUE ((u8)0x00)
+#define TIM1_CR2_RESET_VALUE ((u8)0x00)
+#define TIM1_SMCR_RESET_VALUE ((u8)0x00)
+#define TIM1_ETR_RESET_VALUE ((u8)0x00)
+#define TIM1_IER_RESET_VALUE ((u8)0x00)
+#define TIM1_SR1_RESET_VALUE ((u8)0x00)
+#define TIM1_SR2_RESET_VALUE ((u8)0x00)
+#define TIM1_EGR_RESET_VALUE ((u8)0x00)
+#define TIM1_CCMR1_RESET_VALUE ((u8)0x00)
+#define TIM1_CCMR2_RESET_VALUE ((u8)0x00)
+#define TIM1_CCMR3_RESET_VALUE ((u8)0x00)
+#define TIM1_CCMR4_RESET_VALUE ((u8)0x00)
+#define TIM1_CCER1_RESET_VALUE ((u8)0x00)
+#define TIM1_CCER2_RESET_VALUE ((u8)0x00)
+#define TIM1_CNTRH_RESET_VALUE ((u8)0x00)
+#define TIM1_CNTRL_RESET_VALUE ((u8)0x00)
+#define TIM1_PSCRH_RESET_VALUE ((u8)0x00)
+#define TIM1_PSCRL_RESET_VALUE ((u8)0x00)
+#define TIM1_ARRH_RESET_VALUE ((u8)0xFF)
+#define TIM1_ARRL_RESET_VALUE ((u8)0xFF)
+#define TIM1_RCR_RESET_VALUE ((u8)0x00)
+#define TIM1_CCR1H_RESET_VALUE ((u8)0x00)
+#define TIM1_CCR1L_RESET_VALUE ((u8)0x00)
+#define TIM1_CCR2H_RESET_VALUE ((u8)0x00)
+#define TIM1_CCR2L_RESET_VALUE ((u8)0x00)
+#define TIM1_CCR3H_RESET_VALUE ((u8)0x00)
+#define TIM1_CCR3L_RESET_VALUE ((u8)0x00)
+#define TIM1_CCR4H_RESET_VALUE ((u8)0x00)
+#define TIM1_CCR4L_RESET_VALUE ((u8)0x00)
+#define TIM1_BKR_RESET_VALUE ((u8)0x00)
+#define TIM1_DTR_RESET_VALUE ((u8)0x00)
+#define TIM1_OISR_RESET_VALUE ((u8)0x00)
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM1_Registers_Bits_Definition
+ * @{
+ */
+/* CR1*/
+#define TIM1_CR1_ARPE ((u8)0x80) /*!< Auto-Reload Preload Enable mask. */
+#define TIM1_CR1_CMS ((u8)0x60) /*!< Center-aligned Mode Selection mask. */
+#define TIM1_CR1_DIR ((u8)0x10) /*!< Direction mask. */
+#define TIM1_CR1_OPM ((u8)0x08) /*!< One Pulse Mode mask. */
+#define TIM1_CR1_URS ((u8)0x04) /*!< Update Request Source mask. */
+#define TIM1_CR1_UDIS ((u8)0x02) /*!< Update DIsable mask. */
+#define TIM1_CR1_CEN ((u8)0x01) /*!< Counter Enable mask. */
+/* CR2*/
+#define TIM1_CR2_TI1S ((u8)0x80) /*!< TI1S Selection mask. */
+#define TIM1_CR2_MMS ((u8)0x70) /*!< MMS Selection mask. */
+#define TIM1_CR2_COMS ((u8)0x04) /*!< Capture/Compare Control Update Selection mask. */
+#define TIM1_CR2_CCPC ((u8)0x01) /*!< Capture/Compare Preloaded Control mask. */
+/* SMCR*/
+#define TIM1_SMCR_MSM ((u8)0x80) /*!< Master/Slave Mode mask. */
+#define TIM1_SMCR_TS ((u8)0x70) /*!< Trigger Selection mask. */
+#define TIM1_SMCR_SMS ((u8)0x07) /*!< Slave Mode Selection mask. */
+/*ETR*/
+#define TIM1_ETR_ETP ((u8)0x80) /*!< External Trigger Polarity mask. */
+#define TIM1_ETR_ECE ((u8)0x40)/*!< External Clock mask. */
+#define TIM1_ETR_ETPS ((u8)0x30) /*!< External Trigger Prescaler mask. */
+#define TIM1_ETR_ETF ((u8)0x0F) /*!< External Trigger Filter mask. */
+/*IER*/
+#define TIM1_IER_BIE ((u8)0x80) /*!< Break Interrupt Enable mask. */
+#define TIM1_IER_TIE ((u8)0x40) /*!< Trigger Interrupt Enable mask. */
+#define TIM1_IER_COMIE ((u8)0x20) /*!< Commutation Interrupt Enable mask.*/
+#define TIM1_IER_CC4IE ((u8)0x10) /*!< Capture/Compare 4 Interrupt Enable mask. */
+#define TIM1_IER_CC3IE ((u8)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */
+#define TIM1_IER_CC2IE ((u8)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */
+#define TIM1_IER_CC1IE ((u8)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */
+#define TIM1_IER_UIE ((u8)0x01) /*!< Update Interrupt Enable mask. */
+/*SR1*/
+#define TIM1_SR1_BIF ((u8)0x80) /*!< Break Interrupt Flag mask. */
+#define TIM1_SR1_TIF ((u8)0x40) /*!< Trigger Interrupt Flag mask. */
+#define TIM1_SR1_COMIF ((u8)0x20) /*!< Commutation Interrupt Flag mask. */
+#define TIM1_SR1_CC4IF ((u8)0x10) /*!< Capture/Compare 4 Interrupt Flag mask. */
+#define TIM1_SR1_CC3IF ((u8)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */
+#define TIM1_SR1_CC2IF ((u8)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */
+#define TIM1_SR1_CC1IF ((u8)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */
+#define TIM1_SR1_UIF ((u8)0x01) /*!< Update Interrupt Flag mask. */
+/*SR2*/
+#define TIM1_SR2_CC4OF ((u8)0x10) /*!< Capture/Compare 4 Overcapture Flag mask. */
+#define TIM1_SR2_CC3OF ((u8)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */
+#define TIM1_SR2_CC2OF ((u8)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */
+#define TIM1_SR2_CC1OF ((u8)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */
+/*EGR*/
+#define TIM1_EGR_BG ((u8)0x80) /*!< Break Generation mask. */
+#define TIM1_EGR_TG ((u8)0x40) /*!< Trigger Generation mask. */
+#define TIM1_EGR_COMG ((u8)0x20) /*!< Capture/Compare Control Update Generation mask. */
+#define TIM1_EGR_CC4G ((u8)0x10) /*!< Capture/Compare 4 Generation mask. */
+#define TIM1_EGR_CC3G ((u8)0x08) /*!< Capture/Compare 3 Generation mask. */
+#define TIM1_EGR_CC2G ((u8)0x04) /*!< Capture/Compare 2 Generation mask. */
+#define TIM1_EGR_CC1G ((u8)0x02) /*!< Capture/Compare 1 Generation mask. */
+#define TIM1_EGR_UG ((u8)0x01) /*!< Update Generation mask. */
+/*CCMR*/
+#define TIM1_CCMR_ICxPSC ((u8)0x0C) /*!< Input Capture x Prescaler mask. */
+#define TIM1_CCMR_ICxF ((u8)0xF0) /*!< Input Capture x Filter mask. */
+#define TIM1_CCMR_OCM ((u8)0x70) /*!< Output Compare x Mode mask. */
+#define TIM1_CCMR_OCxPE ((u8)0x08) /*!< Output Compare x Preload Enable mask. */
+#define TIM1_CCMR_OCxFE ((u8)0x04) /*!< Output Compare x Fast Enable mask. */
+#define TIM1_CCMR_CCxS ((u8)0x03) /*!< Capture/Compare x Selection mask. */
+
+#define CCMR_TIxDirect_Set ((u8)0x01)
+/*CCER1*/
+#define TIM1_CCER1_CC2NP ((u8)0x80) /*!< Capture/Compare 2 Complementary output Polarity mask. */
+#define TIM1_CCER1_CC2NE ((u8)0x40) /*!< Capture/Compare 2 Complementary output enable mask. */
+#define TIM1_CCER1_CC2P ((u8)0x20) /*!< Capture/Compare 2 output Polarity mask. */
+#define TIM1_CCER1_CC2E ((u8)0x10) /*!< Capture/Compare 2 output enable mask. */
+#define TIM1_CCER1_CC1NP ((u8)0x08) /*!< Capture/Compare 1 Complementary output Polarity mask. */
+#define TIM1_CCER1_CC1NE ((u8)0x04) /*!< Capture/Compare 1 Complementary output enable mask. */
+#define TIM1_CCER1_CC1P ((u8)0x02) /*!< Capture/Compare 1 output Polarity mask. */
+#define TIM1_CCER1_CC1E ((u8)0x01) /*!< Capture/Compare 1 output enable mask. */
+/*CCER2*/
+#define TIM1_CCER2_CC4P ((u8)0x20) /*!< Capture/Compare 4 output Polarity mask. */
+#define TIM1_CCER2_CC4E ((u8)0x10) /*!< Capture/Compare 4 output enable mask. */
+#define TIM1_CCER2_CC3NP ((u8)0x08) /*!< Capture/Compare 3 Complementary output Polarity mask. */
+#define TIM1_CCER2_CC3NE ((u8)0x04) /*!< Capture/Compare 3 Complementary output enable mask. */
+#define TIM1_CCER2_CC3P ((u8)0x02) /*!< Capture/Compare 3 output Polarity mask. */
+#define TIM1_CCER2_CC3E ((u8)0x01) /*!< Capture/Compare 3 output enable mask. */
+/*CNTRH*/
+#define TIM1_CNTRH_CNT ((u8)0xFF) /*!< Counter Value (MSB) mask. */
+/*CNTRL*/
+#define TIM1_CNTRL_CNT ((u8)0xFF) /*!< Counter Value (LSB) mask. */
+/*PSCH*/
+#define TIM1_PSCH_PSC ((u8)0xFF) /*!< Prescaler Value (MSB) mask. */
+/*PSCL*/
+#define TIM1_PSCL_PSC ((u8)0xFF) /*!< Prescaler Value (LSB) mask. */
+/*ARR*/
+#define TIM1_ARRH_ARR ((u8)0xFF) /*!< Autoreload Value (MSB) mask. */
+#define TIM1_ARRL_ARR ((u8)0xFF) /*!< Autoreload Value (LSB) mask. */
+/*RCR*/
+#define TIM1_RCR_REP ((u8)0xFF) /*!< Repetition Counter Value mask. */
+/*CCR1*/
+#define TIM1_CCR1H_CCR1 ((u8)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */
+#define TIM1_CCR1L_CCR1 ((u8)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */
+/*CCR2*/
+#define TIM1_CCR2H_CCR2 ((u8)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */
+#define TIM1_CCR2L_CCR2 ((u8)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */
+/*CCR3*/
+#define TIM1_CCR3H_CCR3 ((u8)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */
+#define TIM1_CCR3L_CCR3 ((u8)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */
+/*CCR4*/
+#define TIM1_CCR4H_CCR4 ((u8)0xFF) /*!< Capture/Compare 4 Value (MSB) mask. */
+#define TIM1_CCR4L_CCR4 ((u8)0xFF) /*!< Capture/Compare 4 Value (LSB) mask. */
+/*BKR*/
+#define TIM1_BKR_MOE ((u8)0x80) /*!< Main Output Enable mask. */
+#define TIM1_BKR_AOE ((u8)0x40) /*!< Automatic Output Enable mask. */
+#define TIM1_BKR_BKP ((u8)0x20) /*!< Break Polarity mask. */
+#define TIM1_BKR_BKE ((u8)0x10) /*!< Break Enable mask. */
+#define TIM1_BKR_OSSR ((u8)0x08) /*!< Off-State Selection for Run mode mask. */
+#define TIM1_BKR_OSSI ((u8)0x04) /*!< Off-State Selection for Idle mode mask. */
+#define TIM1_BKR_LOCK ((u8)0x03) /*!< Lock Configuration mask. */
+/*DTR*/
+#define TIM1_DTR_DTG ((u8)0xFF) /*!< Dead-Time Generator set-up mask. */
+/*OISR*/
+#define TIM1_OISR_OIS4 ((u8)0x40) /*!< Output Idle state 4 (OC4 output) mask. */
+#define TIM1_OISR_OIS3N ((u8)0x20) /*!< Output Idle state 3 (OC3N output) mask. */
+#define TIM1_OISR_OIS3 ((u8)0x10) /*!< Output Idle state 3 (OC3 output) mask. */
+#define TIM1_OISR_OIS2N ((u8)0x08) /*!< Output Idle state 2 (OC2N output) mask. */
+#define TIM1_OISR_OIS2 ((u8)0x04) /*!< Output Idle state 2 (OC2 output) mask. */
+#define TIM1_OISR_OIS1N ((u8)0x02) /*!< Output Idle state 1 (OC1N output) mask. */
+#define TIM1_OISR_OIS1 ((u8)0x01) /*!< Output Idle state 1 (OC1 output) mask. */
+
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief 16-bit timer (TIM2)
+ */
+
+typedef struct TIM2_struct
+{
+ vu8 CR1; /*!< control register 1 */
+#if defined STM8S103
+ vu8 RESERVED1; /*!< Reserved register */
+ vu8 RESERVED2; /*!< Reserved register */
+#endif
+ vu8 IER; /*!< interrupt enable register */
+ vu8 SR1; /*!< status register 1 */
+ vu8 SR2; /*!< status register 2 */
+ vu8 EGR; /*!< event generation register */
+ vu8 CCMR1; /*!< CC mode register 1 */
+ vu8 CCMR2; /*!< CC mode register 2 */
+ vu8 CCMR3; /*!< CC mode register 3 */
+ vu8 CCER1; /*!< CC enable register 1 */
+ vu8 CCER2; /*!< CC enable register 2 */
+ vu8 CNTRH; /*!< counter high */
+ vu8 CNTRL; /*!< counter low */
+ vu8 PSCR; /*!< prescaler register */
+ vu8 ARRH; /*!< auto-reload register high */
+ vu8 ARRL; /*!< auto-reload register low */
+ vu8 CCR1H; /*!< capture/compare register 1 high */
+ vu8 CCR1L; /*!< capture/compare register 1 low */
+ vu8 CCR2H; /*!< capture/compare register 2 high */
+ vu8 CCR2L; /*!< capture/compare register 2 low */
+ vu8 CCR3H; /*!< capture/compare register 3 high */
+ vu8 CCR3L; /*!< capture/compare register 3 low */
+}
+TIM2_TypeDef;
+
+/** @addtogroup TIM2_Registers_Reset_Value
+ * @{
+ */
+
+#define TIM2_CR1_RESET_VALUE ((u8)0x00)
+#define TIM2_IER_RESET_VALUE ((u8)0x00)
+#define TIM2_SR1_RESET_VALUE ((u8)0x00)
+#define TIM2_SR2_RESET_VALUE ((u8)0x00)
+#define TIM2_EGR_RESET_VALUE ((u8)0x00)
+#define TIM2_CCMR1_RESET_VALUE ((u8)0x00)
+#define TIM2_CCMR2_RESET_VALUE ((u8)0x00)
+#define TIM2_CCMR3_RESET_VALUE ((u8)0x00)
+#define TIM2_CCER1_RESET_VALUE ((u8)0x00)
+#define TIM2_CCER2_RESET_VALUE ((u8)0x00)
+#define TIM2_CNTRH_RESET_VALUE ((u8)0x00)
+#define TIM2_CNTRL_RESET_VALUE ((u8)0x00)
+#define TIM2_PSCR_RESET_VALUE ((u8)0x00)
+#define TIM2_ARRH_RESET_VALUE ((u8)0xFF)
+#define TIM2_ARRL_RESET_VALUE ((u8)0xFF)
+#define TIM2_CCR1H_RESET_VALUE ((u8)0x00)
+#define TIM2_CCR1L_RESET_VALUE ((u8)0x00)
+#define TIM2_CCR2H_RESET_VALUE ((u8)0x00)
+#define TIM2_CCR2L_RESET_VALUE ((u8)0x00)
+#define TIM2_CCR3H_RESET_VALUE ((u8)0x00)
+#define TIM2_CCR3L_RESET_VALUE ((u8)0x00)
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM2_Registers_Bits_Definition
+ * @{
+ */
+/*CR1*/
+#define TIM2_CR1_ARPE ((u8)0x80) /*!< Auto-Reload Preload Enable mask. */
+#define TIM2_CR1_OPM ((u8)0x08) /*!< One Pulse Mode mask. */
+#define TIM2_CR1_URS ((u8)0x04) /*!< Update Request Source mask. */
+#define TIM2_CR1_UDIS ((u8)0x02) /*!< Update DIsable mask. */
+#define TIM2_CR1_CEN ((u8)0x01) /*!< Counter Enable mask. */
+/*IER*/
+#define TIM2_IER_CC3IE ((u8)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */
+#define TIM2_IER_CC2IE ((u8)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */
+#define TIM2_IER_CC1IE ((u8)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */
+#define TIM2_IER_UIE ((u8)0x01) /*!< Update Interrupt Enable mask. */
+/*SR1*/
+#define TIM2_SR1_CC3IF ((u8)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */
+#define TIM2_SR1_CC2IF ((u8)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */
+#define TIM2_SR1_CC1IF ((u8)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */
+#define TIM2_SR1_UIF ((u8)0x01) /*!< Update Interrupt Flag mask. */
+/*SR2*/
+#define TIM2_SR2_CC3OF ((u8)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */
+#define TIM2_SR2_CC2OF ((u8)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */
+#define TIM2_SR2_CC1OF ((u8)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */
+/*EGR*/
+#define TIM2_EGR_CC3G ((u8)0x08) /*!< Capture/Compare 3 Generation mask. */
+#define TIM2_EGR_CC2G ((u8)0x04) /*!< Capture/Compare 2 Generation mask. */
+#define TIM2_EGR_CC1G ((u8)0x02) /*!< Capture/Compare 1 Generation mask. */
+#define TIM2_EGR_UG ((u8)0x01) /*!< Update Generation mask. */
+/*CCMR*/
+#define TIM2_CCMR_ICxPSC ((u8)0x0C) /*!< Input Capture x Prescaler mask. */
+#define TIM2_CCMR_ICxF ((u8)0xF0) /*!< Input Capture x Filter mask. */
+#define TIM2_CCMR_OCM ((u8)0x70) /*!< Output Compare x Mode mask. */
+#define TIM2_CCMR_OCxPE ((u8)0x08) /*!< Output Compare x Preload Enable mask. */
+#define TIM2_CCMR_CCxS ((u8)0x03) /*!< Capture/Compare x Selection mask. */
+/*CCER1*/
+#define TIM2_CCER1_CC2P ((u8)0x20) /*!< Capture/Compare 2 output Polarity mask. */
+#define TIM2_CCER1_CC2E ((u8)0x10) /*!< Capture/Compare 2 output enable mask. */
+#define TIM2_CCER1_CC1P ((u8)0x02) /*!< Capture/Compare 1 output Polarity mask. */
+#define TIM2_CCER1_CC1E ((u8)0x01) /*!< Capture/Compare 1 output enable mask. */
+/*CCER2*/
+#define TIM2_CCER2_CC3P ((u8)0x02) /*!< Capture/Compare 3 output Polarity mask. */
+#define TIM2_CCER2_CC3E ((u8)0x01) /*!< Capture/Compare 3 output enable mask. */
+/*CNTR*/
+#define TIM2_CNTRH_CNT ((u8)0xFF) /*!< Counter Value (MSB) mask. */
+#define TIM2_CNTRL_CNT ((u8)0xFF) /*!< Counter Value (LSB) mask. */
+/*PSCR*/
+#define TIM2_PSCR_PSC ((u8)0xFF) /*!< Prescaler Value (MSB) mask. */
+/*ARR*/
+#define TIM2_ARRH_ARR ((u8)0xFF) /*!< Autoreload Value (MSB) mask. */
+#define TIM2_ARRL_ARR ((u8)0xFF) /*!< Autoreload Value (LSB) mask. */
+/*CCR1*/
+#define TIM2_CCR1H_CCR1 ((u8)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */
+#define TIM2_CCR1L_CCR1 ((u8)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */
+/*CCR2*/
+#define TIM2_CCR2H_CCR2 ((u8)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */
+#define TIM2_CCR2L_CCR2 ((u8)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */
+/*CCR3*/
+#define TIM2_CCR3H_CCR3 ((u8)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */
+#define TIM2_CCR3L_CCR3 ((u8)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */
+
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief 16-bit timer (TIM3)
+ */
+typedef struct TIM3_struct
+{
+ vu8 CR1; /*!< control register 1 */
+ vu8 IER; /*!< interrupt enable register */
+ vu8 SR1; /*!< status register 1 */
+ vu8 SR2; /*!< status register 2 */
+ vu8 EGR; /*!< event generation register */
+ vu8 CCMR1; /*!< CC mode register 1 */
+ vu8 CCMR2; /*!< CC mode register 2 */
+ vu8 CCER1; /*!< CC enable register 1 */
+ vu8 CNTRH; /*!< counter high */
+ vu8 CNTRL; /*!< counter low */
+ vu8 PSCR; /*!< prescaler register */
+ vu8 ARRH; /*!< auto-reload register high */
+ vu8 ARRL; /*!< auto-reload register low */
+ vu8 CCR1H; /*!< capture/compare register 1 high */
+ vu8 CCR1L; /*!< capture/compare register 1 low */
+ vu8 CCR2H; /*!< capture/compare register 2 high */
+ vu8 CCR2L; /*!< capture/compare register 2 low */
+}
+TIM3_TypeDef;
+
+/** @addtogroup TIM3_Registers_Reset_Value
+ * @{
+ */
+
+#define TIM3_CR1_RESET_VALUE ((u8)0x00)
+#define TIM3_IER_RESET_VALUE ((u8)0x00)
+#define TIM3_SR1_RESET_VALUE ((u8)0x00)
+#define TIM3_SR2_RESET_VALUE ((u8)0x00)
+#define TIM3_EGR_RESET_VALUE ((u8)0x00)
+#define TIM3_CCMR1_RESET_VALUE ((u8)0x00)
+#define TIM3_CCMR2_RESET_VALUE ((u8)0x00)
+#define TIM3_CCER1_RESET_VALUE ((u8)0x00)
+#define TIM3_CNTRH_RESET_VALUE ((u8)0x00)
+#define TIM3_CNTRL_RESET_VALUE ((u8)0x00)
+#define TIM3_PSCR_RESET_VALUE ((u8)0x00)
+#define TIM3_ARRH_RESET_VALUE ((u8)0xFF)
+#define TIM3_ARRL_RESET_VALUE ((u8)0xFF)
+#define TIM3_CCR1H_RESET_VALUE ((u8)0x00)
+#define TIM3_CCR1L_RESET_VALUE ((u8)0x00)
+#define TIM3_CCR2H_RESET_VALUE ((u8)0x00)
+#define TIM3_CCR2L_RESET_VALUE ((u8)0x00)
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM3_Registers_Bits_Definition
+ * @{
+ */
+/*CR1*/
+#define TIM3_CR1_ARPE ((u8)0x80) /*!< Auto-Reload Preload Enable mask. */
+#define TIM3_CR1_OPM ((u8)0x08) /*!< One Pulse Mode mask. */
+#define TIM3_CR1_URS ((u8)0x04) /*!< Update Request Source mask. */
+#define TIM3_CR1_UDIS ((u8)0x02) /*!< Update DIsable mask. */
+#define TIM3_CR1_CEN ((u8)0x01) /*!< Counter Enable mask. */
+/*IER*/
+#define TIM3_IER_CC2IE ((u8)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */
+#define TIM3_IER_CC1IE ((u8)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */
+#define TIM3_IER_UIE ((u8)0x01) /*!< Update Interrupt Enable mask. */
+/*SR1*/
+#define TIM3_SR1_CC2IF ((u8)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */
+#define TIM3_SR1_CC1IF ((u8)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */
+#define TIM3_SR1_UIF ((u8)0x01) /*!< Update Interrupt Flag mask. */
+/*SR2*/
+#define TIM3_SR2_CC2OF ((u8)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */
+#define TIM3_SR2_CC1OF ((u8)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */
+/*EGR*/
+#define TIM3_EGR_CC2G ((u8)0x04) /*!< Capture/Compare 2 Generation mask. */
+#define TIM3_EGR_CC1G ((u8)0x02) /*!< Capture/Compare 1 Generation mask. */
+#define TIM3_EGR_UG ((u8)0x01) /*!< Update Generation mask. */
+/*CCMR*/
+#define TIM3_CCMR_ICxPSC ((u8)0x0C) /*!< Input Capture x Prescaler mask. */
+#define TIM3_CCMR_ICxF ((u8)0xF0) /*!< Input Capture x Filter mask. */
+#define TIM3_CCMR_OCM ((u8)0x70) /*!< Output Compare x Mode mask. */
+#define TIM3_CCMR_OCxPE ((u8)0x08) /*!< Output Compare x Preload Enable mask. */
+#define TIM3_CCMR_CCxS ((u8)0x03) /*!< Capture/Compare x Selection mask. */
+/*CCER1*/
+#define TIM3_CCER1_CC2P ((u8)0x20) /*!< Capture/Compare 2 output Polarity mask. */
+#define TIM3_CCER1_CC2E ((u8)0x10) /*!< Capture/Compare 2 output enable mask. */
+#define TIM3_CCER1_CC1P ((u8)0x02) /*!< Capture/Compare 1 output Polarity mask. */
+#define TIM3_CCER1_CC1E ((u8)0x01) /*!< Capture/Compare 1 output enable mask. */
+/*CNTR*/
+#define TIM3_CNTRH_CNT ((u8)0xFF) /*!< Counter Value (MSB) mask. */
+#define TIM3_CNTRL_CNT ((u8)0xFF) /*!< Counter Value (LSB) mask. */
+/*PSCR*/
+#define TIM3_PSCR_PSC ((u8)0xFF) /*!< Prescaler Value (MSB) mask. */
+/*ARR*/
+#define TIM3_ARRH_ARR ((u8)0xFF) /*!< Autoreload Value (MSB) mask. */
+#define TIM3_ARRL_ARR ((u8)0xFF) /*!< Autoreload Value (LSB) mask. */
+/*CCR1*/
+#define TIM3_CCR1H_CCR1 ((u8)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */
+#define TIM3_CCR1L_CCR1 ((u8)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */
+/*CCR2*/
+#define TIM3_CCR2H_CCR2 ((u8)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */
+#define TIM3_CCR2L_CCR2 ((u8)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */
+
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief 8-bit system timer (TIM4)
+ */
+
+typedef struct TIM4_struct
+{
+ vu8 CR1; /*!< control register 1 */
+#if defined STM8S103
+ vu8 RESERVED1; /*!< Reserved register */
+ vu8 RESERVED2; /*!< Reserved register */
+#endif
+ vu8 IER; /*!< interrupt enable register */
+ vu8 SR1; /*!< status register 1 */
+ vu8 EGR; /*!< event generation register */
+ vu8 CNTR; /*!< counter register */
+ vu8 PSCR; /*!< prescaler register */
+ vu8 ARR; /*!< auto-reload register */
+}
+TIM4_TypeDef;
+
+/** @addtogroup TIM4_Registers_Reset_Value
+ * @{
+ */
+
+#define TIM4_CR1_RESET_VALUE ((u8)0x00)
+#define TIM4_IER_RESET_VALUE ((u8)0x00)
+#define TIM4_SR1_RESET_VALUE ((u8)0x00)
+#define TIM4_EGR_RESET_VALUE ((u8)0x00)
+#define TIM4_CNTR_RESET_VALUE ((u8)0x00)
+#define TIM4_PSCR_RESET_VALUE ((u8)0x00)
+#define TIM4_ARR_RESET_VALUE ((u8)0xFF)
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM4_Registers_Bits_Definition
+ * @{
+ */
+/*CR1*/
+#define TIM4_CR1_ARPE ((u8)0x80) /*!< Auto-Reload Preload Enable mask. */
+#define TIM4_CR1_OPM ((u8)0x08) /*!< One Pulse Mode mask. */
+#define TIM4_CR1_URS ((u8)0x04) /*!< Update Request Source mask. */
+#define TIM4_CR1_UDIS ((u8)0x02) /*!< Update DIsable mask. */
+#define TIM4_CR1_CEN ((u8)0x01) /*!< Counter Enable mask. */
+/*IER*/
+#define TIM4_IER_UIE ((u8)0x01) /*!< Update Interrupt Enable mask. */
+/*SR1*/
+#define TIM4_SR1_UIF ((u8)0x01) /*!< Update Interrupt Flag mask. */
+/*EGR*/
+#define TIM4_EGR_UG ((u8)0x01) /*!< Update Generation mask. */
+/*CNTR*/
+#define TIM4_CNTR_CNT ((u8)0xFF) /*!< Counter Value (LSB) mask. */
+/*PSCR*/
+#define TIM4_PSCR_PSC ((u8)0x07) /*!< Prescaler Value mask. */
+/*ARR*/
+#define TIM4_ARR_ARR ((u8)0xFF) /*!< Autoreload Value mask. */
+
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief 16-bit timer with synchro module (TIM5)
+ */
+
+typedef struct TIM5_struct
+{
+ vu8 CR1; /*!<TIM5 Control Register 1 */
+ vu8 CR2; /*!<TIM5 Control Register 2 */
+ vu8 SMCR; /*!<TIM5 Slave Mode Control Register */
+ vu8 IER; /*!<TIM5 Interrupt Enable Register */
+ vu8 SR1; /*!<TIM5 Status Register 1 */
+ vu8 SR2; /*!<TIM5 Status Register 2 */
+ vu8 EGR; /*!<TIM5 Event Generation Register */
+ vu8 CCMR1; /*!<TIM5 Capture/Compare Mode Register 1 */
+ vu8 CCMR2; /*!<TIM5 Capture/Compare Mode Register 2 */
+ vu8 CCMR3; /*!<TIM5 Capture/Compare Mode Register 3 */
+ vu8 CCER1; /*!<TIM5 Capture/Compare Enable Register 1 */
+ vu8 CCER2; /*!<TIM5 Capture/Compare Enable Register 2 */
+ vu8 CNTRH; /*!<TIM5 Counter High */
+ vu8 CNTRL; /*!<TIM5 Counter Low */
+ vu8 PSCR; /*!<TIM5 Prescaler Register */
+ vu8 ARRH; /*!<TIM5 Auto-Reload Register High */
+ vu8 ARRL; /*!<TIM5 Auto-Reload Register Low */
+ vu8 CCR1H; /*!<TIM5 Capture/Compare Register 1 High */
+ vu8 CCR1L; /*!<TIM5 Capture/Compare Register 1 Low */
+ vu8 CCR2H; /*!<TIM5 Capture/Compare Register 2 High */
+ vu8 CCR2L; /*!<TIM5 Capture/Compare Register 2 Low */
+ vu8 CCR3H; /*!<TIM5 Capture/Compare Register 3 High */
+ vu8 CCR3L; /*!<TIM5 Capture/Compare Register 3 Low */
+}TIM5_TypeDef;
+
+/** @addtogroup TIM5_Registers_Reset_Value
+ * @{
+ */
+
+#define TIM5_CR1_RESET_VALUE ((u8)0x00)
+#define TIM5_CR2_RESET_VALUE ((u8)0x00)
+#define TIM5_SMCR_RESET_VALUE ((u8)0x00)
+#define TIM5_IER_RESET_VALUE ((u8)0x00)
+#define TIM5_SR1_RESET_VALUE ((u8)0x00)
+#define TIM5_SR2_RESET_VALUE ((u8)0x00)
+#define TIM5_EGR_RESET_VALUE ((u8)0x00)
+#define TIM5_CCMR1_RESET_VALUE ((u8)0x00)
+#define TIM5_CCMR2_RESET_VALUE ((u8)0x00)
+#define TIM5_CCMR3_RESET_VALUE ((u8)0x00)
+#define TIM5_CCER1_RESET_VALUE ((u8)0x00)
+#define TIM5_CCER2_RESET_VALUE ((u8)0x00)
+#define TIM5_CNTRH_RESET_VALUE ((u8)0x00)
+#define TIM5_CNTRL_RESET_VALUE ((u8)0x00)
+#define TIM5_PSCR_RESET_VALUE ((u8)0x00)
+#define TIM5_ARRH_RESET_VALUE ((u8)0xFF)
+#define TIM5_ARRL_RESET_VALUE ((u8)0xFF)
+#define TIM5_CCR1H_RESET_VALUE ((u8)0x00)
+#define TIM5_CCR1L_RESET_VALUE ((u8)0x00)
+#define TIM5_CCR2H_RESET_VALUE ((u8)0x00)
+#define TIM5_CCR2L_RESET_VALUE ((u8)0x00)
+#define TIM5_CCR3H_RESET_VALUE ((u8)0x00)
+#define TIM5_CCR3L_RESET_VALUE ((u8)0x00)
+
+/**
+ * @}
+ */
+
+/** @addtogroup TIM5_Registers_Bits_Definition
+ * @{
+ */
+/* CR1*/
+#define TIM5_CR1_ARPE ((u8)0x80) /*!< Auto-Reload Preload Enable mask. */
+#define TIM5_CR1_OPM ((u8)0x08) /*!< One Pulse Mode mask. */
+#define TIM5_CR1_URS ((u8)0x04) /*!< Update Request Source mask. */
+#define TIM5_CR1_UDIS ((u8)0x02) /*!< Update DIsable mask. */
+#define TIM5_CR1_CEN ((u8)0x01) /*!< Counter Enable mask. */
+
+/* CR2*/
+#define TIM5_CR2_TI1S ((u8)0x80) /*!< TI1S Selection Mask. */
+#define TIM5_CR2_MMS ((u8)0x70) /*!< MMS Selection Mask. */
+
+/* SMCR*/
+#define TIM5_SMCR_MSM ((u8)0x80) /*!< Master/Slave Mode Mask. */
+#define TIM5_SMCR_TS ((u8)0x70) /*!< Trigger Selection Mask. */
+#define TIM5_SMCR_SMS ((u8)0x07) /*!< Slave Mode Selection Mask. */
+
+
+/*IER*/
+#define TIM5_IER_TIE ((u8)0x40) /*!< Trigger Interrupt Enable mask. */
+#define TIM5_IER_CC3IE ((u8)0x08) /*!< Capture/Compare 3 Interrupt Enable mask. */
+#define TIM5_IER_CC2IE ((u8)0x04) /*!< Capture/Compare 2 Interrupt Enable mask. */
+#define TIM5_IER_CC1IE ((u8)0x02) /*!< Capture/Compare 1 Interrupt Enable mask. */
+#define TIM5_IER_UIE ((u8)0x01) /*!< Update Interrupt Enable mask. */
+/*SR1*/
+#define TIM5_SR1_TIF ((u8)0x40) /*!< Trigger Interrupt Flag mask. */
+#define TIM5_SR1_CC3IF ((u8)0x08) /*!< Capture/Compare 3 Interrupt Flag mask. */
+#define TIM5_SR1_CC2IF ((u8)0x04) /*!< Capture/Compare 2 Interrupt Flag mask. */
+#define TIM5_SR1_CC1IF ((u8)0x02) /*!< Capture/Compare 1 Interrupt Flag mask. */
+#define TIM5_SR1_UIF ((u8)0x01) /*!< Update Interrupt Flag mask. */
+/*SR2*/
+#define TIM5_SR2_CC3OF ((u8)0x08) /*!< Capture/Compare 3 Overcapture Flag mask. */
+#define TIM5_SR2_CC2OF ((u8)0x04) /*!< Capture/Compare 2 Overcapture Flag mask. */
+#define TIM5_SR2_CC1OF ((u8)0x02) /*!< Capture/Compare 1 Overcapture Flag mask. */
+/*EGR*/
+#define TIM5_EGR_TG ((u8)0x40) /*!< Trigger Generation mask. */
+#define TIM5_EGR_CC3G ((u8)0x08) /*!< Capture/Compare 3 Generation mask. */
+#define TIM5_EGR_CC2G ((u8)0x04) /*!< Capture/Compare 2 Generation mask. */
+#define TIM5_EGR_CC1G ((u8)0x02) /*!< Capture/Compare 1 Generation mask. */
+#define TIM5_EGR_UG ((u8)0x01) /*!< Update Generation mask. */
+/*CCMR*/
+#define TIM5_CCMR_ICxPSC ((u8)0x0C) /*!< Input Capture x Prescaler mask. */
+#define TIM5_CCMR_ICxF ((u8)0xF0) /*!< Input Capture x Filter mask. */
+#define TIM5_CCMR_OCM ((u8)0x70) /*!< Output Compare x Mode mask. */
+#define TIM5_CCMR_OCxPE ((u8)0x08) /*!< Output Compare x Preload Enable mask. */
+#define TIM5_CCMR_CCxS ((u8)0x03) /*!< Capture/Compare x Selection mask. */
+/*CCER1*/
+#define TIM5_CCER1_CC2P ((u8)0x20) /*!< Capture/Compare 2 output Polarity mask. */
+#define TIM5_CCER1_CC2E ((u8)0x10) /*!< Capture/Compare 2 output enable mask. */
+#define TIM5_CCER1_CC1P ((u8)0x02) /*!< Capture/Compare 1 output Polarity mask. */
+#define TIM5_CCER1_CC1E ((u8)0x01) /*!< Capture/Compare 1 output enable mask. */
+/*CCER2*/
+#define TIM5_CCER2_CC3P ((u8)0x02) /*!< Capture/Compare 3 output Polarity mask. */
+#define TIM5_CCER2_CC3E ((u8)0x01) /*!< Capture/Compare 3 output enable mask. */
+/*CNTR*/
+#define TIM5_CNTRH_CNT ((u8)0xFF) /*!< Counter Value (MSB) mask. */
+#define TIM5_CNTRL_CNT ((u8)0xFF) /*!< Counter Value (LSB) mask. */
+/*PSCR*/
+#define TIM5_PSCR_PSC ((u8)0xFF) /*!< Prescaler Value (MSB) mask. */
+/*ARR*/
+#define TIM5_ARRH_ARR ((u8)0xFF) /*!< Autoreload Value (MSB) mask. */
+#define TIM5_ARRL_ARR ((u8)0xFF) /*!< Autoreload Value (LSB) mask. */
+/*CCR1*/
+#define TIM5_CCR1H_CCR1 ((u8)0xFF) /*!< Capture/Compare 1 Value (MSB) mask. */
+#define TIM5_CCR1L_CCR1 ((u8)0xFF) /*!< Capture/Compare 1 Value (LSB) mask. */
+/*CCR2*/
+#define TIM5_CCR2H_CCR2 ((u8)0xFF) /*!< Capture/Compare 2 Value (MSB) mask. */
+#define TIM5_CCR2L_CCR2 ((u8)0xFF) /*!< Capture/Compare 2 Value (LSB) mask. */
+/*CCR3*/
+#define TIM5_CCR3H_CCR3 ((u8)0xFF) /*!< Capture/Compare 3 Value (MSB) mask. */
+#define TIM5_CCR3L_CCR3 ((u8)0xFF) /*!< Capture/Compare 3 Value (LSB) mask. */
+/*CCMR*/
+#define TIM5_CCMR_TIxDirect_Set ((u8)0x01)
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief 8-bit system timer with synchro module(TIM6)
+ */
+
+typedef struct TIM6_struct
+{
+ vu8 CR1; /*!< control register 1 */
+ vu8 CR2; /*!< control register 2 */
+ vu8 SMCR; /*!< Synchro mode control register */
+ vu8 IER; /*!< interrupt enable register */
+ vu8 SR1; /*!< status register 1 */
+ vu8 EGR; /*!< event generation register */
+ vu8 CNTR; /*!< counter register */
+ vu8 PSCR; /*!< prescaler register */
+ vu8 ARR; /*!< auto-reload register */
+}
+TIM6_TypeDef;
+/** @addtogroup TIM6_Registers_Reset_Value
+ * @{
+ */
+#define TIM6_CR1_RESET_VALUE ((u8)0x00)
+#define TIM6_CR2_RESET_VALUE ((u8)0x00)
+#define TIM6_SMCR_RESET_VALUE ((u8)0x00)
+#define TIM6_IER_RESET_VALUE ((u8)0x00)
+#define TIM6_SR1_RESET_VALUE ((u8)0x00)
+#define TIM6_EGR_RESET_VALUE ((u8)0x00)
+#define TIM6_CNTR_RESET_VALUE ((u8)0x00)
+#define TIM6_PSCR_RESET_VALUE ((u8)0x00)
+#define TIM6_ARR_RESET_VALUE ((u8)0xFF)
+
+/**
+* @}
+*/
+
+/** @addtogroup TIM6_Registers_Bits_Definition
+ * @{
+ */
+/* CR1*/
+#define TIM6_CR1_ARPE ((u8)0x80) /*!< Auto-Reload Preload Enable Mask. */
+#define TIM6_CR1_OPM ((u8)0x08) /*!< One Pulse Mode Mask. */
+#define TIM6_CR1_URS ((u8)0x04) /*!< Update Request Source Mask. */
+#define TIM6_CR1_UDIS ((u8)0x02) /*!< Update DIsable Mask. */
+#define TIM6_CR1_CEN ((u8)0x01) /*!< Counter Enable Mask. */
+
+/* CR2*/
+
+#define TIM6_CR2_MMS ((u8)0x70) /*!< MMS Selection Mask. */
+
+/* SMCR*/
+#define TIM6_SMCR_MSM ((u8)0x80) /*!< Master/Slave Mode Mask. */
+#define TIM6_SMCR_TS ((u8)0x70) /*!< Trigger Selection Mask. */
+#define TIM6_SMCR_SMS ((u8)0x07) /*!< Slave Mode Selection Mask. */
+
+/* IER*/
+#define TIM6_IER_TIE ((u8)0x40) /*!< Trigger Interrupt Enable Mask. */
+#define TIM6_IER_UIE ((u8)0x01) /*!< Update Interrupt Enable Mask. */
+/* SR1*/
+#define TIM6_SR1_TIF ((u8)0x40) /*!< Trigger Interrupt Flag mask. */
+#define TIM6_SR1_UIF ((u8)0x01) /*!< Update Interrupt Flag Mask. */
+/* EGR*/
+#define TIM6_EGR_TG ((u8)0x40) /*!< Trigger Generation mask. */
+#define TIM6_EGR_UG ((u8)0x01) /*!< Update Generation Mask. */
+/* CNTR*/
+#define TIM6_CNTR_CNT ((u8)0xFF) /*!<Counter Value (LSB) Mask. */
+/* PSCR*/
+#define TIM6_PSCR_PSC ((u8)0x07) /*!<Prescaler Value Mask. */
+
+#define TIM6_ARR_ARR ((u8)0xFF) /*!<Autoreload Value Mask. */
+/**
+ * @}
+ */
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief Inter-Integrated Circuit (I2C)
+ */
+
+typedef struct I2C_struct
+{
+ vu8 CR1; /*!< I2C control register 1 */
+ vu8 CR2; /*!< I2C control register 2 */
+ vu8 FREQR; /*!< I2C frequency register */
+ vu8 OARL; /*!< I2C own address register LSB */
+ vu8 OARH; /*!< I2C own address register MSB */
+ vu8 RESERVED1; /*!< Reserved byte */
+ vu8 DR; /*!< I2C data register */
+ vu8 SR1; /*!< I2C status register 1 */
+ vu8 SR2; /*!< I2C status register 2 */
+ vu8 SR3; /*!< I2C status register 3 */
+ vu8 ITR; /*!< I2C interrupt register */
+ vu8 CCRL; /*!< I2C clock control register low */
+ vu8 CCRH; /*!< I2C clock control register high */
+ vu8 TRISER; /*!< I2C maximum rise time register */
+ vu8 RESERVED2; /*!< Reserved byte */
+}
+I2C_TypeDef;
+
+/** @addtogroup I2C_Registers_Reset_Value
+ * @{
+ */
+
+#define I2C_CR1_RESET_VALUE ((u8)0x00)
+#define I2C_CR2_RESET_VALUE ((u8)0x00)
+#define I2C_FREQR_RESET_VALUE ((u8)0x00)
+#define I2C_OARL_RESET_VALUE ((u8)0x00)
+#define I2C_OARH_RESET_VALUE ((u8)0x00)
+#define I2C_DR_RESET_VALUE ((u8)0x00)
+#define I2C_SR1_RESET_VALUE ((u8)0x00)
+#define I2C_SR2_RESET_VALUE ((u8)0x00)
+#define I2C_SR3_RESET_VALUE ((u8)0x00)
+#define I2C_ITR_RESET_VALUE ((u8)0x00)
+#define I2C_CCRL_RESET_VALUE ((u8)0x00)
+#define I2C_CCRH_RESET_VALUE ((u8)0x00)
+#define I2C_TRISER_RESET_VALUE ((u8)0x02)
+
+/**
+ * @}
+ */
+
+/** @addtogroup I2C_Registers_Bits_Definition
+ * @{
+ */
+
+#define I2C_CR1_NOSTRETCH ((u8)0x80) /*!< Clock Stretching Disable (Slave mode) */
+#define I2C_CR1_ENGC ((u8)0x40) /*!< General Call Enable */
+#define I2C_CR1_PE ((u8)0x01) /*!< Peripheral Enable */
+
+#define I2C_CR2_SWRST ((u8)0x80) /*!< Software Reset */
+#define I2C_CR2_POS ((u8)0x08) /*!< Acknowledge */
+#define I2C_CR2_ACK ((u8)0x04) /*!< Acknowledge Enable */
+#define I2C_CR2_STOP ((u8)0x02) /*!< Stop Generation */
+#define I2C_CR2_START ((u8)0x01) /*!< Start Generation */
+
+#define I2C_FREQR_FREQ ((u8)0x3F) /*!< Peripheral Clock Frequency */
+
+#define I2C_OARL_ADD ((u8)0xFE) /*!< Interface Address bits [7..1] */
+#define I2C_OARL_ADD0 ((u8)0x01) /*!< Interface Address bit0 */
+
+#define I2C_OARH_ADDMODE ((u8)0x80) /*!< Addressing Mode (Slave mode) */
+#define I2C_OARH_ADDCONF ((u8)0x40) /*!< Address Mode Configuration */
+#define I2C_OARH_ADD ((u8)0x06) /*!< Interface Address bits [9..8] */
+
+#define I2C_DR_DR ((u8)0xFF) /*!< Data Register */
+
+#define I2C_SR1_TXE ((u8)0x80) /*!< Data Register Empty (transmitters) */
+#define I2C_SR1_RXNE ((u8)0x40) /*!< Data Register not Empty (receivers) */
+#define I2C_SR1_STOPF ((u8)0x10) /*!< Stop detection (Slave mode) */
+#define I2C_SR1_ADD10 ((u8)0x08) /*!< 10-bit header sent (Master mode) */
+#define I2C_SR1_BTF ((u8)0x04) /*!< Byte Transfer Finished */
+#define I2C_SR1_ADDR ((u8)0x02) /*!< Address sent (master mode)/matched (slave mode) */
+#define I2C_SR1_SB ((u8)0x01) /*!< Start Bit (Master mode) */
+
+#define I2C_SR2_WUFH ((u8)0x20) /*!< Wake-up from Halt */
+#define I2C_SR2_OVR ((u8)0x08) /*!< Overrun/Underrun */
+#define I2C_SR2_AF ((u8)0x04) /*!< Acknowledge Failure */
+#define I2C_SR2_ARLO ((u8)0x02) /*!< Arbitration Lost (master mode) */
+#define I2C_SR2_BERR ((u8)0x01) /*!< Bus Error */
+
+#define I2C_SR3_GENCALL ((u8)0x10) /*!< General Call Header (Slave mode) */
+#define I2C_SR3_TRA ((u8)0x04) /*!< Transmitter/Receiver */
+#define I2C_SR3_BUSY ((u8)0x02) /*!< Bus Busy */
+#define I2C_SR3_MSL ((u8)0x01) /*!< Master/Slave */
+
+#define I2C_ITR_ITBUFEN ((u8)0x04) /*!< Buffer Interrupt Enable */
+#define I2C_ITR_ITEVTEN ((u8)0x02) /*!< Event Interrupt Enable */
+#define I2C_ITR_ITERREN ((u8)0x01) /*!< Error Interrupt Enable */
+
+#define I2C_CCRL_CCR ((u8)0xFF) /*!< Clock Control Register (Master mode) */
+
+#define I2C_CCRH_FS ((u8)0x80) /*!< Master Mode Selection */
+#define I2C_CCRH_DUTY ((u8)0x40) /*!< Fast Mode Duty Cycle */
+#define I2C_CCRH_CCR ((u8)0x0F) /*!< Clock Control Register in Fast/Standard mode (Master mode) bits [11..8] */
+
+#define I2C_TRISER_TRISE ((u8)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
+
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief Interrupt Controller (ITC)
+ */
+
+typedef struct ITC_struct
+{
+ vu8 ISPR1; /*!< Interrupt Software Priority register 1 */
+ vu8 ISPR2; /*!< Interrupt Software Priority register 2 */
+ vu8 ISPR3; /*!< Interrupt Software Priority register 3 */
+ vu8 ISPR4; /*!< Interrupt Software Priority register 4 */
+ vu8 ISPR5; /*!< Interrupt Software Priority register 5 */
+ vu8 ISPR6; /*!< Interrupt Software Priority register 6 */
+ vu8 ISPR7; /*!< Interrupt Software Priority register 7 */
+ vu8 ISPR8; /*!< Interrupt Software Priority register 8 */
+}
+ITC_TypeDef;
+
+/** @addtogroup ITC_Registers_Reset_Value
+ * @{
+ */
+
+#define ITC_SPRX_RESET_VALUE ((u8)0xFF) /*!< Reset value of Software Priority registers */
+
+/**
+ * @}
+ */
+
+/** @addtogroup CPU_Registers_Bits_Definition
+ * @{
+ */
+
+#define CPU_CC_I1I0 ((u8)0x28) /*!< Condition Code register, I1 and I0 bits mask */
+
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief External Interrupt Controller (EXTI)
+ */
+
+typedef struct EXTI_struct
+{
+ vu8 CR1; /*!< External Interrupt Control Register for PORTA to PORTD */
+ vu8 CR2; /*!< External Interrupt Control Register for PORTE and TLI */
+}
+EXTI_TypeDef;
+
+/** @addtogroup EXTI_Registers_Reset_Value
+ * @{
+ */
+
+#define EXTI_CR1_RESET_VALUE ((u8)0x00)
+#define EXTI_CR2_RESET_VALUE ((u8)0x00)
+
+/**
+ * @}
+ */
+
+/** @addtogroup EXTI_Registers_Bits_Definition
+ * @{
+ */
+
+#define EXTI_CR1_PDIS ((u8)0xC0) /*!< PORTD external interrupt sensitivity bits mask */
+#define EXTI_CR1_PCIS ((u8)0x30) /*!< PORTC external interrupt sensitivity bits mask */
+#define EXTI_CR1_PBIS ((u8)0x0C) /*!< PORTB external interrupt sensitivity bits mask */
+#define EXTI_CR1_PAIS ((u8)0x03) /*!< PORTA external interrupt sensitivity bits mask */
+
+#define EXTI_CR2_TLIS ((u8)0x04) /*!< Top level interrupt sensitivity bit mask */
+#define EXTI_CR2_PEIS ((u8)0x03) /*!< PORTE external interrupt sensitivity bits mask */
+
+/**
+ * @}
+ */
+
+
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief FLASH program and Data memory (FLASH)
+ */
+
+typedef struct FLASH_struct
+{
+ vu8 CR1; /*!< Flash control register 1 */
+ vu8 CR2; /*!< Flash control register 2 */
+ vu8 NCR2; /*!< Flash complementary control register 2 */
+ vu8 FPR; /*!< Flash protection register */
+ vu8 NFPR; /*!< Flash complementary protection register */
+ vu8 IAPSR; /*!< Flash in-application programming status register */
+ vu8 RESERVED1; /*!< Reserved byte */
+ vu8 RESERVED2; /*!< Reserved byte */
+ vu8 PUKR; /*!< Flash program memory unprotection register */
+ vu8 RESERVED3; /*!< Reserved byte */
+ vu8 DUKR; /*!< Data EEPROM unprotection register */
+}
+FLASH_TypeDef;
+
+/** @addtogroup FLASH_Registers_Reset_Value
+ * @{
+ */
+
+#define FLASH_CR1_RESET_VALUE ((u8)0x00)
+#define FLASH_CR2_RESET_VALUE ((u8)0x00)
+#define FLASH_NCR2_RESET_VALUE ((u8)0xFF)
+#define FLASH_IAPSR_RESET_VALUE ((u8)0x40)
+#define FLASH_PUKR_RESET_VALUE ((u8)0x00)
+#define FLASH_DUKR_RESET_VALUE ((u8)0x00)
+
+/**
+ * @}
+ */
+
+/** @addtogroup FLASH_Registers_Bits_Definition
+ * @{
+ */
+
+#define FLASH_CR1_HALT ((u8)0x08) /*!< Standby in Halt mode mask */
+#define FLASH_CR1_AHALT ((u8)0x04) /*!< Standby in Active Halt mode mask */
+#define FLASH_CR1_IE ((u8)0x02) /*!< Flash Interrupt enable mask */
+#define FLASH_CR1_FIX ((u8)0x01) /*!< Fix programming time mask */
+
+#define FLASH_CR2_OPT ((u8)0x80) /*!< Select option byte mask */
+#define FLASH_CR2_WPRG ((u8)0x40) /*!< Word Programming mask */
+#define FLASH_CR2_ERASE ((u8)0x20) /*!< Erase block mask */
+#define FLASH_CR2_FPRG ((u8)0x10) /*!< Fast programming mode mask */
+#define FLASH_CR2_PRG ((u8)0x01) /*!< Program block mask */
+
+#define FLASH_NCR2_NOPT ((u8)0x80) /*!< Select option byte mask */
+#define FLASH_NCR2_NWPRG ((u8)0x40) /*!< Word Programming mask */
+#define FLASH_NCR2_NERASE ((u8)0x20) /*!< Erase block mask */
+#define FLASH_NCR2_NFPRG ((u8)0x10) /*!< Fast programming mode mask */
+#define FLASH_NCR2_NPRG ((u8)0x01) /*!< Program block mask */
+
+#define FLASH_IAPSR_HVOFF ((u8)0x40) /*!< End of high voltage flag mask */
+#define FLASH_IAPSR_DUL ((u8)0x08) /*!< Data EEPROM unlocked flag mask */
+#define FLASH_IAPSR_EOP ((u8)0x04) /*!< End of operation flag mask */
+#define FLASH_IAPSR_PUL ((u8)0x02) /*!< Flash Program memory unlocked flag mask */
+#define FLASH_IAPSR_WR_PG_DIS ((u8)0x01) /*!< Write attempted to protected page mask */
+
+#define FLASH_PUKR_PUK ((u8)0xFF) /*!< Flash Program memory unprotection mask */
+
+#define FLASH_DUKR_DUK ((u8)0xFF) /*!< Data EEPROM unprotection mask */
+
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief Option Bytes (OPT)
+ */
+typedef struct OPT_struct
+{
+ vu8 OPT0; /*!< Option byte 0: Read-out protection (not accessible in IAP mode) */
+ vu8 OPT1; /*!< Option byte 1: User boot code */
+ vu8 NOPT1; /*!< Complementary Option byte 1 */
+ vu8 OPT2; /*!< Option byte 2: Alternate function remapping */
+ vu8 NOPT2; /*!< Complementary Option byte 2 */
+ vu8 OPT3; /*!< Option byte 3: Watchdog option */
+ vu8 NOPT3; /*!< Complementary Option byte 3 */
+ vu8 OPT4; /*!< Option byte 4: Clock option */
+ vu8 NOPT4; /*!< Complementary Option byte 4 */
+ vu8 OPT5; /*!< Option byte 5: HSE clock startup */
+ vu8 NOPT5; /*!< Complementary Option byte 5 */
+ vu8 RESERVED1; /*!< Reserved Option byte*/
+ vu8 RESERVED2; /*!< Reserved Option byte*/
+ vu8 OPT7; /*!< Option byte 7: flash wait states */
+ vu8 NOPT7; /*!< Complementary Option byte 7 */
+}
+OPT_TypeDef;
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief Independent Watchdog (IWDG)
+ */
+
+typedef struct IWDG_struct
+{
+ vu8 KR; /*!< Key Register */
+ vu8 PR; /*!< Prescaler Register */
+ vu8 RLR; /*!< Reload Register */
+}
+IWDG_TypeDef;
+
+/** @addtogroup IWDG_Registers_Reset_Value
+ * @{
+ */
+
+#define IWDG_PR_RESET_VALUE ((u8)0x00)
+#define IWDG_RLR_RESET_VALUE ((u8)0xFF)
+
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief Window Watchdog (WWDG)
+ */
+
+typedef struct WWDG_struct
+{
+ vu8 CR; /*!< Control Register */
+ vu8 WR; /*!< Window Register */
+}
+WWDG_TypeDef;
+
+/** @addtogroup WWDG_Registers_Reset_Value
+ * @{
+ */
+
+#define WWDG_CR_RESET_VALUE ((u8)0x7F)
+#define WWDG_WR_RESET_VALUE ((u8)0x7F)
+
+/**
+ * @}
+ */
+
+/** @addtogroup WWDG_Registers_Bits_Definition
+ * @{
+ */
+
+#define WWDG_CR_WDGA ((u8)0x80) /*!< WDGA bit mask */
+#define WWDG_CR_T6 ((u8)0x40) /*!< T6 bit mask */
+#define WWDG_CR_T ((u8)0x7F) /*!< T bits mask */
+
+#define WWDG_WR_MSB ((u8)0x80) /*!< MSB bit mask */
+#define WWDG_WR_W ((u8)0x7F) /*!< W bits mask */
+
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief Reset Controller (RST)
+ */
+
+typedef struct RST_struct
+{
+ vu8 SR; /*!< Reset status register */
+}
+RST_TypeDef;
+
+/** @addtogroup RST_Registers_Bits_Definition
+ * @{
+ */
+
+#define RST_SR_EMCF ((u8)0x10) /*!< EMC reset flag bit mask */
+#define RST_SR_SWIMF ((u8)0x08) /*!< SWIM reset flag bit mask */
+#define RST_SR_ILLOPF ((u8)0x04) /*!< Illegal opcode reset flag bit mask */
+#define RST_SR_IWDGF ((u8)0x02) /*!< IWDG reset flag bit mask */
+#define RST_SR_WWDGF ((u8)0x01) /*!< WWDG reset flag bit mask */
+
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief Serial Peripheral Interface (SPI)
+ */
+
+typedef struct SPI_struct
+{
+ vu8 CR1; /*!< SPI control register 1 */
+ vu8 CR2; /*!< SPI control register 2 */
+ vu8 ICR; /*!< SPI interrupt control register */
+ vu8 SR; /*!< SPI status register */
+ vu8 DR; /*!< SPI data I/O register */
+ vu8 CRCPR; /*!< SPI CRC polynomial register */
+ vu8 RXCRCR; /*!< SPI Rx CRC register */
+ vu8 TXCRCR; /*!< SPI Tx CRC register */
+}
+SPI_TypeDef;
+
+/** @addtogroup SPI_Registers_Reset_Value
+ * @{
+ */
+
+#define SPI_CR1_RESET_VALUE ((u8)0x00) /*!< Control Register 1 reset value */
+#define SPI_CR2_RESET_VALUE ((u8)0x00) /*!< Control Register 2 reset value */
+#define SPI_ICR_RESET_VALUE ((u8)0x00) /*!< Interrupt Control Register reset value */
+#define SPI_SR_RESET_VALUE ((u8)0x02) /*!< Status Register reset value */
+#define SPI_DR_RESET_VALUE ((u8)0x00) /*!< Data Register reset value */
+#define SPI_CRCPR_RESET_VALUE ((u8)0x07) /*!< Polynomial Register reset value */
+#define SPI_RXCRCR_RESET_VALUE ((u8)0x00) /*!< RX CRC Register reset value */
+#define SPI_TXCRCR_RESET_VALUE ((u8)0x00) /*!< TX CRC Register reset value */
+
+/**
+ * @}
+ */
+
+/** @addtogroup SPI_Registers_Bits_Definition
+ * @{
+ */
+
+#define SPI_CR1_LSBFIRST ((u8)0x80) /*!< Frame format mask */
+#define SPI_CR1_SPE ((u8)0x40) /*!< Enable bits mask */
+#define SPI_CR1_BR ((u8)0x38) /*!< Baud rate control mask */
+#define SPI_CR1_MSTR ((u8)0x04) /*!< Master Selection mask */
+#define SPI_CR1_CPOL ((u8)0x02) /*!< Clock Polarity mask */
+#define SPI_CR1_CPHA ((u8)0x01) /*!< Clock Phase mask */
+
+#define SPI_CR2_BDM ((u8)0x80) /*!< Bi-directional data mode enable mask */
+#define SPI_CR2_BDOE ((u8)0x40) /*!< Output enable in bi-directional mode mask */
+#define SPI_CR2_CRCEN ((u8)0x20) /*!< Hardware CRC calculation enable mask */
+#define SPI_CR2_CRCNEXT ((u8)0x10) /*!< Transmit CRC next mask */
+#define SPI_CR2_RXONLY ((u8)0x04) /*!< Receive only mask */
+#define SPI_CR2_SSM ((u8)0x02) /*!< Software slave management mask */
+#define SPI_CR2_SSI ((u8)0x01) /*!< Internal slave select mask */
+
+#define SPI_ICR_TXEI ((u8)0x80) /*!< Tx buffer empty interrupt enable mask */
+#define SPI_ICR_RXEI ((u8)0x40) /*!< Rx buffer empty interrupt enable mask */
+#define SPI_ICR_ERRIE ((u8)0x20) /*!< Error interrupt enable mask */
+#define SPI_ICR_WKIE ((u8)0x10) /*!< Wake-up interrupt enable mask */
+
+#define SPI_SR_BSY ((u8)0x80) /*!< Busy flag */
+#define SPI_SR_OVR ((u8)0x40) /*!< Overrun flag */
+#define SPI_SR_MODF ((u8)0x20) /*!< Mode fault */
+#define SPI_SR_CRCERR ((u8)0x10) /*!< CRC error flag */
+#define SPI_SR_WKUP ((u8)0x08) /*!< Wake-Up flag */
+#define SPI_SR_TXE ((u8)0x02) /*!< Transmit buffer empty */
+#define SPI_SR_RXNE ((u8)0x01) /*!< Receive buffer not empty */
+
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief Single Wire Interface Module (SWIM)
+ */
+typedef struct SWIM_struct
+{
+ vu8 CSR; /*!< Control/Status register */
+ vu8 DR; /*!< Data register */
+}
+SWIM_TypeDef;
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter (UART1)
+ */
+
+typedef struct UART1_struct
+{
+ vu8 SR; /*!< UART1 status register */
+ vu8 DR; /*!< UART1 data register */
+ vu8 BRR1; /*!< UART1 baud rate register */
+ vu8 BRR2; /*!< UART1 DIV mantissa[11:8] SCIDIV fraction */
+ vu8 CR1; /*!< UART1 control register 1 */
+ vu8 CR2; /*!< UART1 control register 2 */
+ vu8 CR3; /*!< UART1 control register 3 */
+ vu8 CR4; /*!< UART1 control register 4 */
+ vu8 CR5; /*!< UART1 control register 5 */
+ vu8 GTR; /*!< UART1 guard time register */
+ vu8 PSCR; /*!< UART1 prescaler register */
+}
+UART1_TypeDef;
+
+/** @addtogroup UART1_Registers_Reset_Value
+ * @{
+ */
+
+#define UART1_SR_RESET_VALUE ((u8)0xC0)
+#define UART1_BRR1_RESET_VALUE ((u8)0x00)
+#define UART1_BRR2_RESET_VALUE ((u8)0x00)
+#define UART1_CR1_RESET_VALUE ((u8)0x00)
+#define UART1_CR2_RESET_VALUE ((u8)0x00)
+#define UART1_CR3_RESET_VALUE ((u8)0x00)
+#define UART1_CR4_RESET_VALUE ((u8)0x00)
+#define UART1_CR5_RESET_VALUE ((u8)0x00)
+#define UART1_GTR_RESET_VALUE ((u8)0x00)
+#define UART1_PSCR_RESET_VALUE ((u8)0x00)
+
+/**
+ * @}
+ */
+
+/** @addtogroup UART1_Registers_Bits_Definition
+ * @{
+ */
+
+#define UART1_SR_TXE ((u8)0x80) /*!< Transmit Data Register Empty mask */
+#define UART1_SR_TC ((u8)0x40) /*!< Transmission Complete mask */
+#define UART1_SR_RXNE ((u8)0x20) /*!< Read Data Register Not Empty mask */
+#define UART1_SR_IDLE ((u8)0x10) /*!< IDLE line detected mask */
+#define UART1_SR_OR ((u8)0x08) /*!< OverRun error mask */
+#define UART1_SR_NF ((u8)0x04) /*!< Noise Flag mask */
+#define UART1_SR_FE ((u8)0x02) /*!< Framing Error mask */
+#define UART1_SR_PE ((u8)0x01) /*!< Parity Error mask */
+
+#define UART1_BRR1_DIVM ((u8)0xFF) /*!< LSB mantissa of UART1DIV [7:0] mask */
+
+#define UART1_BRR2_DIVM ((u8)0xF0) /*!< MSB mantissa of UART1DIV [11:8] mask */
+#define UART1_BRR2_DIVF ((u8)0x0F) /*!< Fraction bits of UART1DIV [3:0] mask */
+
+#define UART1_CR1_R8 ((u8)0x80) /*!< Receive Data bit 8 */
+#define UART1_CR1_T8 ((u8)0x40) /*!< Transmit data bit 8 */
+#define UART1_CR1_UARTD ((u8)0x20) /*!< UART1 Disable (for low power consumption) */
+#define UART1_CR1_M ((u8)0x10) /*!< Word length mask */
+#define UART1_CR1_WAKE ((u8)0x08) /*!< Wake-up method mask */
+#define UART1_CR1_PCEN ((u8)0x04) /*!< Parity Control Enable mask */
+#define UART1_CR1_PS ((u8)0x02) /*!< UART1 Parity Selection */
+#define UART1_CR1_PIEN ((u8)0x01) /*!< UART1 Parity Interrupt Enable mask */
+
+#define UART1_CR2_TIEN ((u8)0x80) /*!< Transmitter Interrupt Enable mask */
+#define UART1_CR2_TCIEN ((u8)0x40) /*!< TransmissionComplete Interrupt Enable mask */
+#define UART1_CR2_RIEN ((u8)0x20) /*!< Receiver Interrupt Enable mask */
+#define UART1_CR2_ILIEN ((u8)0x10) /*!< IDLE Line Interrupt Enable mask */
+#define UART1_CR2_TEN ((u8)0x08) /*!< Transmitter Enable mask */
+#define UART1_CR2_REN ((u8)0x04) /*!< Receiver Enable mask */
+#define UART1_CR2_RWU ((u8)0x02) /*!< Receiver Wake-Up mask */
+#define UART1_CR2_SBK ((u8)0x01) /*!< Send Break mask */
+
+#define UART1_CR3_LINEN ((u8)0x40) /*!< Alternate Function outpu mask */
+#define UART1_CR3_STOP ((u8)0x30) /*!< STOP bits [1:0] mask */
+#define UART1_CR3_CKEN ((u8)0x08) /*!< Clock Enable mask */
+#define UART1_CR3_CPOL ((u8)0x04) /*!< Clock Polarity mask */
+#define UART1_CR3_CPHA ((u8)0x02) /*!< Clock Phase mask */
+#define UART1_CR3_LBCL ((u8)0x01) /*!< Last Bit Clock pulse mask */
+
+#define UART1_CR4_LBDIEN ((u8)0x40) /*!< LIN Break Detection Interrupt Enable mask */
+#define UART1_CR4_LBDL ((u8)0x20) /*!< LIN Break Detection Length mask */
+#define UART1_CR4_LBDF ((u8)0x10) /*!< LIN Break Detection Flag mask */
+#define UART1_CR4_ADD ((u8)0x0F) /*!< Address of the UART1 node mask */
+
+#define UART1_CR5_SCEN ((u8)0x20) /*!< Smart Card Enable mask */
+#define UART1_CR5_NACK ((u8)0x10) /*!< Smart Card Nack Enable mask */
+#define UART1_CR5_HDSEL ((u8)0x08) /*!< Half-Duplex Selection mask */
+#define UART1_CR5_IRLP ((u8)0x04) /*!< Irda Low Power Selection mask */
+#define UART1_CR5_IREN ((u8)0x02) /*!< Irda Enable mask */
+
+/**
+ * @}
+ */
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief Universal Synchronous Asynchronous Receiver Transmitter (UART2)
+ */
+
+typedef struct UART2_struct
+{
+ vu8 SR; /*!< UART1 status register */
+ vu8 DR; /*!< UART1 data register */
+ vu8 BRR1; /*!< UART1 baud rate register */
+ vu8 BRR2; /*!< UART1 DIV mantissa[11:8] SCIDIV fraction */
+ vu8 CR1; /*!< UART1 control register 1 */
+ vu8 CR2; /*!< UART1 control register 2 */
+ vu8 CR3; /*!< UART1 control register 3 */
+ vu8 CR4; /*!< UART1 control register 4 */
+ vu8 CR5; /*!< UART1 control register 5 */
+ vu8 CR6; /*!< UART1 control register 6 */
+ vu8 GTR; /*!< UART1 guard time register */
+ vu8 PSCR; /*!< UART1 prescaler register */
+}
+UART2_TypeDef;
+
+/** @addtogroup UART2_Registers_Reset_Value
+ * @{
+ */
+
+#define UART2_SR_RESET_VALUE ((u8)0xC0)
+#define UART2_BRR1_RESET_VALUE ((u8)0x00)
+#define UART2_BRR2_RESET_VALUE ((u8)0x00)
+#define UART2_CR1_RESET_VALUE ((u8)0x00)
+#define UART2_CR2_RESET_VALUE ((u8)0x00)
+#define UART2_CR3_RESET_VALUE ((u8)0x00)
+#define UART2_CR4_RESET_VALUE ((u8)0x00)
+#define UART2_CR5_RESET_VALUE ((u8)0x00)
+#define UART2_CR6_RESET_VALUE ((u8)0x00)
+#define UART2_GTR_RESET_VALUE ((u8)0x00)
+#define UART2_PSCR_RESET_VALUE ((u8)0x00)
+
+/**
+ * @}
+ */
+
+/** @addtogroup UART2_Registers_Bits_Definition
+ * @{
+ */
+
+#define UART2_SR_TXE ((u8)0x80) /*!< Transmit Data Register Empty mask */
+#define UART2_SR_TC ((u8)0x40) /*!< Transmission Complete mask */
+#define UART2_SR_RXNE ((u8)0x20) /*!< Read Data Register Not Empty mask */
+#define UART2_SR_IDLE ((u8)0x10) /*!< IDLE line detected mask */
+#define UART2_SR_OR ((u8)0x08) /*!< OverRun error mask */
+#define UART2_SR_NF ((u8)0x04) /*!< Noise Flag mask */
+#define UART2_SR_FE ((u8)0x02) /*!< Framing Error mask */
+#define UART2_SR_PE ((u8)0x01) /*!< Parity Error mask */
+
+#define UART2_BRR1_DIVM ((u8)0xFF) /*!< LSB mantissa of UART2DIV [7:0] mask */
+
+#define UART2_BRR2_DIVM ((u8)0xF0) /*!< MSB mantissa of UART2DIV [11:8] mask */
+#define UART2_BRR2_DIVF ((u8)0x0F) /*!< Fraction bits of UART2DIV [3:0] mask */
+
+#define UART2_CR1_R8 ((u8)0x80) /*!< Receive Data bit 8 */
+#define UART2_CR1_T8 ((u8)0x40) /*!< Transmit data bit 8 */
+#define UART2_CR1_UARTD ((u8)0x20) /*!< UART2 Disable (for low power consumption) */
+#define UART2_CR1_M ((u8)0x10) /*!< Word length mask */
+#define UART2_CR1_WAKE ((u8)0x08) /*!< Wake-up method mask */
+#define UART2_CR1_PCEN ((u8)0x04) /*!< Parity Control Enable mask */
+#define UART2_CR1_PS ((u8)0x02) /*!< UART2 Parity Selection */
+#define UART2_CR1_PIEN ((u8)0x01) /*!< UART2 Parity Interrupt Enable mask */
+
+#define UART2_CR2_TIEN ((u8)0x80) /*!< Transmitter Interrupt Enable mask */
+#define UART2_CR2_TCIEN ((u8)0x40) /*!< TransmissionComplete Interrupt Enable mask */
+#define UART2_CR2_RIEN ((u8)0x20) /*!< Receiver Interrupt Enable mask */
+#define UART2_CR2_ILIEN ((u8)0x10) /*!< IDLE Line Interrupt Enable mask */
+#define UART2_CR2_TEN ((u8)0x08) /*!< Transmitter Enable mask */
+#define UART2_CR2_REN ((u8)0x04) /*!< Receiver Enable mask */
+#define UART2_CR2_RWU ((u8)0x02) /*!< Receiver Wake-Up mask */
+#define UART2_CR2_SBK ((u8)0x01) /*!< Send Break mask */
+
+#define UART2_CR3_LINEN ((u8)0x40) /*!< Alternate Function outpu mask */
+#define UART2_CR3_STOP ((u8)0x30) /*!< STOP bits [1:0] mask */
+#define UART2_CR3_CKEN ((u8)0x08) /*!< Clock Enable mask */
+#define UART2_CR3_CPOL ((u8)0x04) /*!< Clock Polarity mask */
+#define UART2_CR3_CPHA ((u8)0x02) /*!< Clock Phase mask */
+#define UART2_CR3_LBCL ((u8)0x01) /*!< Last Bit Clock pulse mask */
+
+#define UART2_CR4_LBDIEN ((u8)0x40) /*!< LIN Break Detection Interrupt Enable mask */
+#define UART2_CR4_LBDL ((u8)0x20) /*!< LIN Break Detection Length mask */
+#define UART2_CR4_LBDF ((u8)0x10) /*!< LIN Break Detection Flag mask */
+#define UART2_CR4_ADD ((u8)0x0F) /*!< Address of the UART2 node mask */
+
+#define UART2_CR5_SCEN ((u8)0x20) /*!< Smart Card Enable mask */
+#define UART2_CR5_NACK ((u8)0x10) /*!< Smart Card Nack Enable mask */
+#define UART2_CR5_HDSEL ((u8)0x08) /*!< Half-Duplex Selection mask */
+#define UART2_CR5_IRLP ((u8)0x04) /*!< Irda Low Power Selection mask */
+#define UART2_CR5_IREN ((u8)0x02) /*!< Irda Enable mask */
+
+#define UART2_CR6_LDUM ((u8)0x80) /*!< LIN Divider Update Method */
+#define UART2_CR6_LSLV ((u8)0x20) /*!< LIN Slave Enable */
+#define UART2_CR6_LASE ((u8)0x10) /*!< LIN Autosynchronization Enable */
+#define UART2_CR6_LHDIEN ((u8)0x04) /*!< LIN Header Detection Interrupt Enable */
+#define UART2_CR6_LHDF ((u8)0x02) /*!< LIN Header Detection Flag */
+#define UART2_CR6_LSF ((u8)0x01) /*!< LIN Synch Field */
+
+/**
+ * @}
+ */
+
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief LIN Universal Asynchronous Receiver Transmitter (UART3)
+ */
+
+typedef struct UART3_struct
+{
+ vu8 SR; /*!< status register */
+ vu8 DR; /*!< data register */
+ vu8 BRR1; /*!< baud rate register */
+ vu8 BRR2; /*!< DIV mantissa[11:8] SCIDIV fraction */
+ vu8 CR1; /*!< control register 1 */
+ vu8 CR2; /*!< control register 2 */
+ vu8 CR3; /*!< control register 3 */
+ vu8 CR4; /*!< control register 4 */
+ vu8 RESERVED; /*!< Reserved byte */
+ vu8 CR6; /*!< control register 5 */
+}
+UART3_TypeDef;
+
+/** @addtogroup UART3_Registers_Reset_Value
+ * @{
+ */
+
+#define UART3_SR_RESET_VALUE ((u8)0xC0)
+#define UART3_BRR1_RESET_VALUE ((u8)0x00)
+#define UART3_BRR2_RESET_VALUE ((u8)0x00)
+#define UART3_CR1_RESET_VALUE ((u8)0x00)
+#define UART3_CR2_RESET_VALUE ((u8)0x00)
+#define UART3_CR3_RESET_VALUE ((u8)0x00)
+#define UART3_CR4_RESET_VALUE ((u8)0x00)
+#define UART3_CR6_RESET_VALUE ((u8)0x00)
+
+/**
+ * @}
+ */
+
+/** @addtogroup UART3_Registers_Bits_Definition
+ * @{
+ */
+
+#define UART3_SR_TXE ((u8)0x80) /*!< Transmit Data Register Empty mask */
+#define UART3_SR_TC ((u8)0x40) /*!< Transmission Complete mask */
+#define UART3_SR_RXNE ((u8)0x20) /*!< Read Data Register Not Empty mask */
+#define UART3_SR_IDLE ((u8)0x10) /*!< IDLE line detected mask */
+#define UART3_SR_OR ((u8)0x08) /*!< OverRun error mask */
+#define UART3_SR_NF ((u8)0x04) /*!< Noise Flag mask */
+#define UART3_SR_FE ((u8)0x02) /*!< Framing Error mask */
+#define UART3_SR_PE ((u8)0x01) /*!< Parity Error mask */
+
+#define UART3_BRR1_DIVM ((u8)0xFF) /*!< LSB mantissa of UARTDIV [7:0] mask */
+
+#define UART3_BRR2_DIVM ((u8)0xF0) /*!< MSB mantissa of UARTDIV [11:8] mask */
+#define UART3_BRR2_DIVF ((u8)0x0F) /*!< Fraction bits of UARTDIV [3:0] mask */
+
+#define UART3_CR1_R8 ((u8)0x80) /*!< Receive Data bit 8 */
+#define UART3_CR1_T8 ((u8)0x40) /*!< Transmit data bit 8 */
+#define UART3_CR1_UARTD ((u8)0x20) /*!< UART Disable (for low power consumption) */
+#define UART3_CR1_M ((u8)0x10) /*!< Word length mask */
+#define UART3_CR1_WAKE ((u8)0x08) /*!< Wake-up method mask */
+#define UART3_CR1_PCEN ((u8)0x04) /*!< Parity control enable mask */
+#define UART3_CR1_PS ((u8)0x02) /*!< Parity selection bit mask */
+#define UART3_CR1_PIEN ((u8)0x01) /*!< Parity interrupt enable bit mask */
+
+#define UART3_CR2_TIEN ((u8)0x80) /*!< Transmitter Interrupt Enable mask */
+#define UART3_CR2_TCIEN ((u8)0x40) /*!< TransmissionComplete Interrupt Enable mask */
+#define UART3_CR2_RIEN ((u8)0x20) /*!< Receiver Interrupt Enable mask */
+#define UART3_CR2_ILIEN ((u8)0x10) /*!< IDLE Line Interrupt Enable mask */
+#define UART3_CR2_TEN ((u8)0x08) /*!< Transmitter Enable mask */
+#define UART3_CR2_REN ((u8)0x04) /*!< Receiver Enable mask */
+#define UART3_CR2_RWU ((u8)0x02) /*!< Receiver Wake-Up mask */
+#define UART3_CR2_SBK ((u8)0x01) /*!< Send Break mask */
+
+#define UART3_CR3_LINEN ((u8)0x40) /*!< Alternate Function outpu mask */
+#define UART3_CR3_STOP ((u8)0x30) /*!< STOP bits [1:0] mask */
+
+#define UART3_CR4_LBDIEN ((u8)0x40) /*!< LIN Break Detection Interrupt Enable mask */
+#define UART3_CR4_LBDL ((u8)0x20) /*!< LIN Break Detection Length mask */
+#define UART3_CR4_LBDF ((u8)0x10) /*!< LIN Break Detection Flag mask */
+#define UART3_CR4_ADD ((u8)0x0F) /*!< Address of the UART3 node mask */
+
+#define UART3_CR6_LDUM ((u8)0x80) /*!< LIN Divider Update Method */
+#define UART3_CR6_LSLV ((u8)0x20) /*!< LIN Slave Enable */
+#define UART3_CR6_LASE ((u8)0x10) /*!< LIN Autosynchronization Enable */
+#define UART3_CR6_LHDIEN ((u8)0x04) /*!< LIN Header Detection Interrupt Enable */
+#define UART3_CR6_LHDF ((u8)0x02) /*!< LIN Header Detection Flag */
+#define UART3_CR6_LSF ((u8)0x01) /*!< LIN Synch Field */
+
+/**
+ * @}
+ */
+
+
+/*----------------------------------------------------------------------------*/
+/**
+ * @brief Controller Area Network (CAN)
+ */
+
+typedef struct
+{
+ vu8 MCR; /*!< CAN master control register */
+ vu8 MSR; /*!< CAN master status register */
+ vu8 TSR; /*!< CAN transmit status register */
+ vu8 TPR; /*!< CAN transmit priority register */
+ vu8 RFR; /*!< CAN receive FIFO register */
+ vu8 IER; /*!< CAN interrupt enable register */
+ vu8 DGR; /*!< CAN diagnosis register */
+ vu8 PSR; /*!< CAN page selection register */
+
+ union
+ {
+ struct
+ {
+ vu8 MCSR;
+ vu8 MDLCR;
+ vu8 MIDR1;
+ vu8 MIDR2;
+ vu8 MIDR3;
+ vu8 MIDR4;
+ vu8 MDAR1;
+ vu8 MDAR2;
+ vu8 MDAR3;
+ vu8 MDAR4;
+ vu8 MDAR5;
+ vu8 MDAR6;
+ vu8 MDAR7;
+ vu8 MDAR8;
+ vu8 MTSRL;
+ vu8 MTSRH;
+ }
+ TxMailbox;
+
+ struct
+ {
+ vu8 FR01;
+ vu8 FR02;
+ vu8 FR03;
+ vu8 FR04;
+ vu8 FR05;
+ vu8 FR06;
+ vu8 FR07;
+ vu8 FR08;
+
+ vu8 FR09;
+ vu8 FR10;
+ vu8 FR11;
+ vu8 FR12;
+ vu8 FR13;
+ vu8 FR14;
+ vu8 FR15;
+ vu8 FR16;
+ }
+ Filter;
+
+
+ struct
+ {
+ vu8 F0R1;
+ vu8 F0R2;
+ vu8 F0R3;
+ vu8 F0R4;
+ vu8 F0R5;
+ vu8 F0R6;
+ vu8 F0R7;
+ vu8 F0R8;
+
+ vu8 F1R1;
+ vu8 F1R2;
+ vu8 F1R3;
+ vu8 F1R4;
+ vu8 F1R5;
+ vu8 F1R6;
+ vu8 F1R7;
+ vu8 F1R8;
+ }
+ Filter01;
+
+ struct
+ {
+ vu8 F2R1;
+ vu8 F2R2;
+ vu8 F2R3;
+ vu8 F2R4;
+ vu8 F2R5;
+ vu8 F2R6;
+ vu8 F2R7;
+ vu8 F2R8;
+
+ vu8 F3R1;
+ vu8 F3R2;
+ vu8 F3R3;
+ vu8 F3R4;
+ vu8 F3R5;
+ vu8 F3R6;
+ vu8 F3R7;
+ vu8 F3R8;
+ }
+ Filter23;
+
+ struct
+ {
+ vu8 F4R1;
+ vu8 F4R2;
+ vu8 F4R3;
+ vu8 F4R4;
+ vu8 F4R5;
+ vu8 F4R6;
+ vu8 F4R7;
+ vu8 F4R8;
+
+ vu8 F5R1;
+ vu8 F5R2;
+ vu8 F5R3;
+ vu8 F5R4;
+ vu8 F5R5;
+ vu8 F5R6;
+ vu8 F5R7;
+ vu8 F5R8;
+ }
+ Filter45;
+
+ struct
+ {
+ vu8 ESR;
+ vu8 EIER;
+ vu8 TECR;
+ vu8 RECR;
+ vu8 BTR1;
+ vu8 BTR2;
+ u8 Reserved1[2];
+ vu8 FMR1;
+ vu8 FMR2;
+ vu8 FCR1;
+ vu8 FCR2;
+ vu8 FCR3;
+ u8 Reserved2[3];
+ }
+ Config;
+
+ struct
+ {
+ vu8 MFMI;
+ vu8 MDLCR;
+ vu8 MIDR1;
+ vu8 MIDR2;
+ vu8 MIDR3;
+ vu8 MIDR4;
+ vu8 MDAR1;
+ vu8 MDAR2;
+ vu8 MDAR3;
+ vu8 MDAR4;
+ vu8 MDAR5;
+ vu8 MDAR6;
+ vu8 MDAR7;
+ vu8 MDAR8;
+ vu8 MTSRL;
+ vu8 MTSRH;
+ }
+ RxFIFO;
+ }Page;
+} CAN_TypeDef;
+/** @addtogroup CAN_Registers_Bits_Definition
+ * @{
+ */
+/*******************************Commun****************************************/
+/* CAN Master Control Register bits */
+#define CAN_MCR_INRQ ((u8)0x01)
+#define CAN_MCR_SLEEP ((u8)0x02)
+#define CAN_MCR_TXFP ((u8)0x04)
+#define CAN_MCR_RFLM ((u8)0x08)
+#define CAN_MCR_NART ((u8)0x10)
+#define CAN_MCR_AWUM ((u8)0x20)
+#define CAN_MCR_ABOM ((u8)0x40)
+#define CAN_MCR_TTCM ((u8)0x80)
+
+/* CAN Master Status Register bits */
+#define CAN_MSR_INAK ((u8)0x01)
+#define CAN_MSR_SLAK ((u8)0x02)
+#define CAN_MSR_ERRI ((u8)0x04)
+#define CAN_MSR_WKUI ((u8)0x08)
+#define CAN_MSR_TX ((u8)0x10)
+#define CAN_MSR_RX ((u8)0x20)
+
+/* CAN Transmit Status Register bits */
+#define CAN_TSR_RQCP0 ((u8)0x01)
+#define CAN_TSR_RQCP1 ((u8)0x02)
+#define CAN_TSR_RQCP2 ((u8)0x04)
+#define CAN_TSR_RQCP012 ((u8)0x07)
+#define CAN_TSR_TXOK0 ((u8)0x10)
+#define CAN_TSR_TXOK1 ((u8)0x20)
+#define CAN_TSR_TXOK2 ((u8)0x40)
+
+#define CAN_TPR_CODE0 ((u8)0x01)
+#define CAN_TPR_TME0 ((u8)0x04)
+#define CAN_TPR_TME1 ((u8)0x08)
+#define CAN_TPR_TME2 ((u8)0x10)
+#define CAN_TPR_LOW0 ((u8)0x20)
+#define CAN_TPR_LOW1 ((u8)0x40)
+#define CAN_TPR_LOW2 ((u8)0x80)
+/* CAN Receive FIFO Register bits */
+#define CAN_RFR_FMP01 ((u8)0x03)
+#define CAN_RFR_FULL ((u8)0x08)
+#define CAN_RFR_FOVR ((u8)0x10)
+#define CAN_RFR_RFOM ((u8)0x20)
+
+/* CAN Interrupt Register bits */
+#define CAN_IER_TMEIE ((u8)0x01)
+#define CAN_IER_FMPIE ((u8)0x02)
+#define CAN_IER_FFIE ((u8)0x04)
+#define CAN_IER_FOVIE ((u8)0x08)
+#define CAN_IER_WKUIE ((u8)0x80)
+
+
+/* CAN diagnostic Register bits */
+#define CAN_DGR_LBKM ((u8)0x01)
+#define CAN_DGR_SLIM ((u8)0x02)
+#define CAN_DGR_SAMP ((u8)0x04)
+#define CAN_DGR_RX ((u8)0x08)
+#define CAN_DGR_TXM2E ((u8)0x10)
+
+
+/* CAN page select Register bits */
+#define CAN_PSR_PS0 ((u8)0x01)
+#define CAN_PSR_PS1 ((u8)0x02)
+#define CAN_PSR_PS2 ((u8)0x04)
+
+/**************************Tx MailBox & Fifo Page cummun bits*****************************************/
+#define CAN_MCSR_TXRQ ((u8)0x01)
+#define CAN_MCSR_ABRQ ((u8)0x02)
+#define CAN_MCSR_RQCP ((u8)0x04)
+#define CAN_MCSR_TXOK ((u8)0x08)
+#define CAN_MCSR_ALST ((u8)0x10)
+#define CAN_MCSR_TERR ((u8)0x20)
+
+#define CAN_MDLCR_DLC ((u8)0x0F)
+#define CAN_MDLCR_TGT ((u8)0x80)
+
+#define CAN_MIDR1_RTR ((u8)0x20)
+#define CAN_MIDR1_IDE ((u8)0x40)
+
+
+/*************************Filter Page**********************************************/
+
+/* CAN Error Status Register bits */
+#define CAN_ESR_EWGF ((u8)0x01)
+#define CAN_ESR_EPVF ((u8)0x02)
+#define CAN_ESR_BOFF ((u8)0x04)
+#define CAN_ESR_LEC0 ((u8)0x10)
+#define CAN_ESR_LEC1 ((u8)0x20)
+#define CAN_ESR_LEC2 ((u8)0x40)
+#define CAN_ESR_LEC ((u8)0x70)
+
+/* CAN Error Status Register bits */
+#define CAN_EIER_EWGIE ((u8)0x01)
+#define CAN_EIER_EPVIE ((u8)0x02)
+#define CAN_EIER_BOFIE ((u8)0x04)
+#define CAN_EIER_LECIE ((u8)0x10)
+#define CAN_EIER_ERRIE ((u8)0x80)
+
+/* CAN transmit error counter Register bits(CAN_TECR) */
+#define CAN_TECR_TEC0 ((u8)0x01)
+#define CAN_TECR_TEC1 ((u8)0x02)
+#define CAN_TECR_TEC2 ((u8)0x04)
+#define CAN_TECR_TEC3 ((u8)0x08)
+#define CAN_TECR_TEC4 ((u8)0x10)
+#define CAN_TECR_TEC5 ((u8)0x20)
+#define CAN_TECR_TEC6 ((u8)0x40)
+#define CAN_TECR_TEC7 ((u8)0x80)
+
+/* CAN RECEIVE error counter Register bits(CAN_TECR) */
+#define CAN_RECR_REC0 ((u8)0x01)
+#define CAN_RECR_REC1 ((u8)0x02)
+#define CAN_RECR_REC2 ((u8)0x04)
+#define CAN_RECR_REC3 ((u8)0x08)
+#define CAN_RECR_REC4 ((u8)0x10)
+#define CAN_RECR_REC5 ((u8)0x20)
+#define CAN_RECR_REC6 ((u8)0x40)
+#define CAN_RECR_REC7 ((u8)0x80)
+
+/* CAN Bit Timing Register 2 bits(CAN_BTR2) */
+#define CAN_BTR2_CLKS ((u8)0x80)
+
+/* CAN filter mode register bits (CAN_FMR) */
+#define CAN_FMR1_FML0 ((u8)0x01)
+#define CAN_FMR1_FMH0 ((u8)0x02)
+#define CAN_FMR1_FML1 ((u8)0x04)
+#define CAN_FMR1_FMH1 ((u8)0x08)
+#define CAN_FMR1_FML2 ((u8)0x10)
+#define CAN_FMR1_FMH2 ((u8)0x20)
+#define CAN_FMR1_FML3 ((u8)0x40)
+#define CAN_FMR1_FMH3 ((u8)0x80)
+
+#define CAN_FMR2_FML4 ((u8)0x01)
+#define CAN_FMR2_FMH4 ((u8)0x02)
+#define CAN_FMR2_FML5 ((u8)0x04)
+#define CAN_FMR2_FMH5 ((u8)0x08)
+
+/* CAN filter Config register bits (CAN_FCR) */
+#define CAN_FCR1_FACT0 ((u8)0x01)
+#define CAN_FCR1_FACT1 ((u8)0x10)
+#define CAN_FCR2_FACT2 ((u8)0x01)
+#define CAN_FCR2_FACT3 ((u8)0x10)
+#define CAN_FCR3_FACT4 ((u8)0x01)
+#define CAN_FCR3_FACT5 ((u8)0x10)
+
+#define CAN_FCR1_FSC00 ((u8)0x02)
+#define CAN_FCR1_FSC01 ((u8)0x04)
+#define CAN_FCR1_FSC10 ((u8)0x20)
+#define CAN_FCR1_FSC11 ((u8)0x40)
+#define CAN_FCR2_FSC20 ((u8)0x02)
+#define CAN_FCR2_FSC21 ((u8)0x04)
+#define CAN_FCR2_FSC30 ((u8)0x20)
+#define CAN_FCR2_FSC31 ((u8)0x40)
+#define CAN_FCR3_FSC40 ((u8)0x02)
+#define CAN_FCR3_FSC41 ((u8)0x04)
+#define CAN_FCR3_FSC50 ((u8)0x20)
+#define CAN_FCR3_FSC51 ((u8)0x40)
+
+
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Registers_Reset_Value
+ * @{
+ */
+
+#define CAN_MCR_RESET_VALUE ((u8)0x02)
+#define CAN_MSR_RESET_VALUE ((u8)0x02)
+#define CAN_TSR_RESET_VALUE ((u8)0x00)
+#define CAN_TPR_RESET_VALUE ((u8)0x0C)
+#define CAN_RFR_RESET_VALUE ((u8)0x00)
+#define CAN_IER_RESET_VALUE ((u8)0x00)
+#define CAN_DGR_RESET_VALUE ((u8)0x0C)
+#define CAN_PSR_RESET_VALUE ((u8)0x00)
+
+#define CAN_ESR_RESET_VALUE ((u8)0x00)
+#define CAN_EIER_RESET_VALUE ((u8)0x00)
+#define CAN_TECR_RESET_VALUE ((u8)0x00)
+#define CAN_RECR_RESET_VALUE ((u8)0x00)
+#define CAN_BTR1_RESET_VALUE ((u8)0x40)
+#define CAN_BTR2_RESET_VALUE ((u8)0x23)
+#define CAN_FMR1_RESET_VALUE ((u8)0x00)
+#define CAN_FMR2_RESET_VALUE ((u8)0x00)
+#define CAN_FCR_RESET_VALUE ((u8)0x00)
+
+#define CAN_MFMI_RESET_VALUE ((u8)0x00)
+#define CAN_MDLC_RESET_VALUE ((u8)0x00)
+#define CAN_MCSR_RESET_VALUE ((u8)0x00)
+
+/**
+ * @}
+ */
+
+/**
+ * @brief Configuration Registers (CFG)
+ */
+
+typedef struct CFG_struct
+{
+ vu8 GCR; /*!< Global Configuration register */
+}
+CFG_TypeDef;
+
+/** @addtogroup CFG_Registers_Reset_Value
+ * @{
+ */
+
+#define CFG_GCR_RESET_VALUE ((u8)0x00)
+
+/**
+ * @}
+ */
+
+/** @addtogroup CFG_Registers_Bits_Definition
+ * @{
+ */
+
+#define CFG_GCR_SWD ((u8)0x01) /*!< Swim disable bit mask */
+#define CFG_GCR_AL ((u8)0x02) /*!< Activation Level bit mask */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/******************************************************************************/
+/* Peripherals Base Address */
+/******************************************************************************/
+
+/** @addtogroup MAP_FILE_Base_Addresses
+ * @{
+ */
+#define OPT_BaseAddress 0x4800
+#define GPIOA_BaseAddress 0x5000
+#define GPIOB_BaseAddress 0x5005
+#define GPIOC_BaseAddress 0x500A
+#define GPIOD_BaseAddress 0x500F
+#define GPIOE_BaseAddress 0x5014
+#define GPIOF_BaseAddress 0x5019
+#define GPIOG_BaseAddress 0x501E
+#define GPIOH_BaseAddress 0x5023
+#define GPIOI_BaseAddress 0x5028
+
+#define FLASH_BaseAddress 0x505A
+
+#define EXTI_BaseAddress 0x50A0
+#define RST_BaseAddress 0x50B3
+#define CLK_BaseAddress 0x50C0
+#define WWDG_BaseAddress 0x50D1
+#define IWDG_BaseAddress 0x50E0
+#define AWU_BaseAddress 0x50F0
+#define BEEP_BaseAddress 0x50F3
+#define SPI_BaseAddress 0x5200
+#define I2C_BaseAddress 0x5210
+#define UART1_BaseAddress 0x5230
+#define UART2_BaseAddress 0x5240
+#define UART3_BaseAddress 0x5240
+#define TIM1_BaseAddress 0x5250
+#define TIM2_BaseAddress 0x5300
+#define TIM3_BaseAddress 0x5320
+#define TIM4_BaseAddress 0x5340
+#define TIM5_BaseAddress 0x5300
+#define TIM6_BaseAddress 0x5340
+
+#define ADC1_BaseAddress 0x53E0
+#define ADC2_BaseAddress 0x5400
+#define CAN_BaseAddress 0x5420
+
+#define CFG_BaseAddress 0x7F60
+#define ITC_BaseAddress 0x7F70
+#define SWIM_BaseAddress 0x7F80
+#define DM_BaseAddress 0x7F90
+
+/**
+ * @}
+ */
+
+/******************************************************************************/
+/* Peripherals declarations */
+/******************************************************************************/
+
+#if defined(STM8S105) || defined(STM8S103) || defined(STM8S903)
+ #define ADC1 ((ADC1_TypeDef *) ADC1_BaseAddress)
+#endif /* (STM8S105) ||(STM8S103) || (STM8S903) */
+
+#if defined(STM8S208) || defined(STM8S207)
+#define ADC2 ((ADC2_TypeDef *) ADC2_BaseAddress)
+#endif /* (STM8S208) ||(STM8S207) */
+
+#define AWU ((AWU_TypeDef *) AWU_BaseAddress)
+
+#define BEEP ((BEEP_TypeDef *) BEEP_BaseAddress)
+
+#ifdef STM8S208
+ #define CAN ((CAN_TypeDef *) CAN_BaseAddress)
+#endif /* (STM8S208) */
+
+#define CLK ((CLK_TypeDef *) CLK_BaseAddress)
+
+#define EXTI ((EXTI_TypeDef *) EXTI_BaseAddress)
+
+#define FLASH ((FLASH_TypeDef *) FLASH_BaseAddress)
+
+#define OPT ((OPT_TypeDef *) OPT_BaseAddress)
+
+#define GPIOA ((GPIO_TypeDef *) GPIOA_BaseAddress)
+
+#define GPIOB ((GPIO_TypeDef *) GPIOB_BaseAddress)
+
+#define GPIOC ((GPIO_TypeDef *) GPIOC_BaseAddress)
+
+#define GPIOD ((GPIO_TypeDef *) GPIOD_BaseAddress)
+
+#define GPIOE ((GPIO_TypeDef *) GPIOE_BaseAddress)
+
+#define GPIOF ((GPIO_TypeDef *) GPIOF_BaseAddress)
+
+#if defined(STM8S207) || defined(STM8S208) || defined(STM8S105)
+ #define GPIOG ((GPIO_TypeDef *) GPIOG_BaseAddress)
+#endif /* (STM8S208) ||(STM8S207) || (STM8S105) */
+
+#if defined(STM8S207) || defined(STM8S208)
+ #define GPIOH ((GPIO_TypeDef *) GPIOH_BaseAddress)
+ #define GPIOI ((GPIO_TypeDef *) GPIOI_BaseAddress)
+#endif /* (STM8S208) ||(STM8S207) */
+
+#define RST ((RST_TypeDef *) RST_BaseAddress)
+
+#define WWDG ((WWDG_TypeDef *) WWDG_BaseAddress)
+#define IWDG ((IWDG_TypeDef *) IWDG_BaseAddress)
+
+#define SPI ((SPI_TypeDef *) SPI_BaseAddress)
+#define I2C ((I2C_TypeDef *) I2C_BaseAddress)
+
+#if defined(STM8S208) ||defined(STM8S207) ||defined(STM8S103) ||defined(STM8S903)
+ #define UART1 ((UART1_TypeDef *) UART1_BaseAddress)
+#endif /* (STM8S208) ||(STM8S207) || (STM8S103) || (STM8S903) */
+
+#ifdef STM8S105
+ #define UART2 ((UART2_TypeDef *) UART2_BaseAddress)
+#endif /* STM8S105 */
+
+#if defined(STM8S208) ||defined(STM8S207)
+ #define UART3 ((UART3_TypeDef *) UART3_BaseAddress)
+#endif /* (STM8S208) ||(STM8S207) */
+
+#define TIM1 ((TIM1_TypeDef *) TIM1_BaseAddress)
+
+#if defined(STM8S208) ||defined(STM8S207) ||defined(STM8S103) ||defined(STM8S105)
+ #define TIM2 ((TIM2_TypeDef *) TIM2_BaseAddress)
+#endif /* (STM8S208) ||(STM8S207) || (STM8S103) || (STM8S105) */
+
+#if defined(STM8S208) ||defined(STM8S207) ||defined(STM8S105)
+ #define TIM3 ((TIM3_TypeDef *) TIM3_BaseAddress)
+#endif /* (STM8S208) ||(STM8S207) || (STM8S105) */
+
+#if defined(STM8S208) ||defined(STM8S207) ||defined(STM8S103) ||defined(STM8S105)
+ #define TIM4 ((TIM4_TypeDef *) TIM4_BaseAddress)
+#endif /* (STM8S208) ||(STM8S207) || (STM8S103) || (STM8S105) */
+
+#ifdef STM8S903
+ #define TIM5 ((TIM5_TypeDef *) TIM5_BaseAddress)
+ #define TIM6 ((TIM6_TypeDef *) TIM6_BaseAddress)
+#endif /* STM8S903 */
+
+#define ITC ((ITC_TypeDef *) ITC_BaseAddress)
+
+#define CFG ((CFG_TypeDef *) CFG_BaseAddress)
+
+#define SWIM ((SWIM_TypeDef *) SWIM_BaseAddress)
+
+#define DM ((DM_TypeDef *) DM_BaseAddress)
+
+
+#ifdef USE_STDPERIPH_DRIVER
+ #include "stm8s_conf.h"
+#endif
+
+/* Exported macro --------------------------------------------------------------*/
+
+/*============================== Interrupts ====================================*/
+#ifdef _RAISONANCE_
+ #include <intrist7.h>
+ #define enableInterrupts() _rim_() /* enable interrupts */
+ #define disableInterrupts() _sim_() /* disable interrupts */
+ #define rim() _rim_() /* enable interrupts */
+ #define sim() _sim_() /* disable interrupts */
+ #define nop() _nop_() /* No Operation */
+ #define trap() _trap_() /* Trap (soft IT) */
+ #define wfi() _wfi_() /* Wait For Interrupt */
+ #define halt() _halt_() /* Halt */
+#else /* COSMIC */
+ #define enableInterrupts() {_asm("rim\n");} /* enable interrupts */
+ #define disableInterrupts() {_asm("sim\n");} /* disable interrupts */
+ #define rim() {_asm("rim\n");} /* enable interrupts */
+ #define sim() {_asm("sim\n");} /* disable interrupts */
+ #define nop() {_asm("nop\n");} /* No Operation */
+ #define trap() {_asm("trap\n");} /* Trap (soft IT) */
+ #define wfi() {_asm("wfi\n");} /* Wait For Interrupt */
+ #define halt() {_asm("halt\n");} /* Halt */
+#endif
+
+/*============================== Handling bits ====================================*/
+/*-----------------------------------------------------------------------------
+Method : I
+Description : Handle the bit from the character variables.
+Comments : The different parameters of commands are
+ - VAR : Name of the character variable where the bit is located.
+ - Place : Bit position in the variable (7 6 5 4 3 2 1 0)
+ - Value : Can be 0 (reset bit) or not 0 (set bit)
+ The "MskBit" command allows to select some bits in a source
+ variables and copy it in a destination var (return the value).
+ The "ValBit" command returns the value of a bit in a char
+ variable: the bit is reseted if it returns 0 else the bit is set.
+ This method generates not an optimised code yet.
+-----------------------------------------------------------------------------*/
+#define SetBit(VAR,Place) ( (VAR) |= (u8)((u8)1<<(u8)(Place)) )
+#define ClrBit(VAR,Place) ( (VAR) &= (u8)((u8)((u8)1<<(u8)(Place))^(u8)255) )
+
+#define ChgBit(VAR,Place) ( (VAR) ^= (u8)((u8)1<<(u8)(Place)) )
+#define AffBit(VAR,Place,Value) ((Value) ? \
+ ((VAR) |= ((u8)1<<(Place))) : \
+ ((VAR) &= (((u8)1<<(Place))^(u8)255)))
+#define MskBit(Dest,Msk,Src) ( (Dest) = ((Msk) & (Src)) | ((~(Msk)) & (Dest)) )
+
+#define ValBit(VAR,Place) ((u8)(VAR) & (u8)((u8)1<<(u8)(Place)))
+
+#define BYTE_0(n) ((u8)((n) & (u8)0xFF)) /*!< Returns the low byte of the 32-bit value */
+#define BYTE_1(n) ((u8)(BYTE_0((n) >> (u8)8))) /*!< Returns the second byte of the 32-bit value */
+#define BYTE_2(n) ((u8)(BYTE_0((n) >> (u8)16))) /*!< Returns the third byte of the 32-bit value */
+#define BYTE_3(n) ((u8)(BYTE_0((n) >> (u8)24))) /*!< Returns the high byte of the 32-bit value */
+
+/*============================== Assert Macros ====================================*/
+#define IS_STATE_VALUE_OK(SensitivityValue) \
+ (((SensitivityValue) == ENABLE) || \
+ ((SensitivityValue) == DISABLE))
+
+/*-----------------------------------------------------------------------------
+Method : II
+Description : Handle directly the bit.
+Comments : The idea is to handle directly with the bit name. For that, it is
+ necessary to have RAM area descriptions (example: HW register...)
+ and the following command line for each area.
+ This method generates the most optimized code.
+-----------------------------------------------------------------------------*/
+
+#define AREA 0x00 /* The area of bits begins at address 0x10. */
+
+#define BitClr(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) &= (~(1<<(7-(BIT)%8))) )
+#define BitSet(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) |= (1<<(7-(BIT)%8)) )
+#define BitVal(BIT) ( *((unsigned char *) (AREA+(BIT)/8)) & (1<<(7-(BIT)%8)) )
+
+/* Exported functions ------------------------------------------------------- */
+
+#endif /* __STM8S_H */
+
+/**
+ * @}
+ */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/os/hal/platforms/STM8/stm8s_type.h b/os/hal/platforms/STM8/stm8s_type.h
new file mode 100644
index 000000000..5c80f6687
--- /dev/null
+++ b/os/hal/platforms/STM8/stm8s_type.h
@@ -0,0 +1,103 @@
+/**
+ ******************************************************************************
+ * @file stm8s_type.h
+ * @brief This file contains all common data types.
+ * @author STMicroelectronics - MCD Application Team
+ * @version V1.1.1
+ * @date 06/05/2009
+ ******************************************************************************
+ *
+ * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+ * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+ * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+ * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+ * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+ * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+ *
+ * <h2><center>&copy; COPYRIGHT 2009 STMicroelectronics</center></h2>
+ * @image html logo.bmp
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM8S_TYPE_H
+#define __STM8S_TYPE_H
+
+/* Includes ------------------------------------------------------------------*/
+/* Exported types ------------------------------------------------------------*/
+typedef signed long s32;
+typedef signed short s16;
+typedef signed char s8;
+
+typedef signed long const sc32; /* Read Only */
+typedef signed short const sc16; /* Read Only */
+typedef signed char const sc8; /* Read Only */
+
+typedef volatile signed long vs32;
+typedef volatile signed short vs16;
+typedef volatile signed char vs8;
+
+typedef volatile signed long const vsc32; /* Read Only */
+typedef volatile signed short const vsc16; /* Read Only */
+typedef volatile signed char const vsc8; /* Read Only */
+
+typedef unsigned long u32;
+typedef unsigned short u16;
+typedef unsigned char u8;
+
+typedef unsigned long const uc32; /* Read Only */
+typedef unsigned short const uc16; /* Read Only */
+typedef unsigned char const uc8; /* Read Only */
+
+typedef volatile unsigned long vu32;
+typedef volatile unsigned short vu16;
+typedef volatile unsigned char vu8;
+
+typedef volatile unsigned long const vuc32; /* Read Only */
+typedef volatile unsigned short const vuc16; /* Read Only */
+typedef volatile unsigned char const vuc8; /* Read Only */
+
+typedef enum
+{
+ FALSE = 0,
+ TRUE = !FALSE
+}
+bool;
+
+typedef enum {
+ RESET = 0,
+ SET = !RESET
+}
+FlagStatus, ITStatus, BitStatus;
+
+typedef enum {
+ DISABLE = 0,
+ ENABLE = !DISABLE
+}
+FunctionalState;
+
+#define IS_FUNCTIONALSTATE_OK(VALUE) ( (VALUE == ENABLE) || (VALUE == DISABLE) )
+
+typedef enum {
+ ERROR = 0,
+ SUCCESS = !ERROR
+}
+ErrorStatus;
+
+#define U8_MAX ((u8)255)
+#define S8_MAX ((s8)127)
+#define S8_MIN ((s8)-128)
+#define U16_MAX ((u16)65535u)
+#define S16_MAX ((s16)32767)
+#define S16_MIN ((s16)-32768)
+#define U32_MAX ((u32)4294967295uL)
+#define S32_MAX ((s32)2147483647)
+#define S32_MIN ((s32)-2147483648)
+
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+#endif /* __STM8S_TYPE_H */
+
+/******************* (C) COPYRIGHT 2009 STMicroelectronics *****END OF FILE****/
diff --git a/os/kernel/include/chbsem.h b/os/kernel/include/chbsem.h
index b8cd08306..adbf1605f 100644
--- a/os/kernel/include/chbsem.h
+++ b/os/kernel/include/chbsem.h
@@ -67,10 +67,10 @@ typedef struct {
* that is part of a bigger structure.
*
* @param[in] name the name of the semaphore variable
- * @param[in] n the counter initial value, this value must be
- * non-negative
+ * @param[in] taken the semaphore initial state
*/
-#define _BSEMAPHORE_DATA(name, t) {_SEMAPHORE_DATA(name.bs_sem), ((t) ? 0 : 1)}
+#define _BSEMAPHORE_DATA(name, taken) \
+ {_SEMAPHORE_DATA(name.bs_sem), ((taken) ? 0 : 1)}
/**
* @brief Static semaphore initializer.
@@ -78,11 +78,10 @@ typedef struct {
* initialization using @p chSemInit().
*
* @param[in] name the name of the semaphore variable
- * @param[in] n the counter initial value, this value must be
- * non-negative
+ * @param[in] taken the semaphore initial state
*/
-#define BSEMAPHORE_DECL(name, t) Semaphore name = _BSEMAPHORE_DATA(name, t)
-
+#define BSEMAPHORE_DECL(name, taken) \
+ BinarySemaphore name = _BSEMAPHORE_DATA(name, taken)
/**
* @brief Initializes a binary semaphore.
diff --git a/os/ports/RC/STM8/chcore.c b/os/ports/RC/STM8/chcore.c
index 6aaa182af..c09e9f864 100644
--- a/os/ports/RC/STM8/chcore.c
+++ b/os/ports/RC/STM8/chcore.c
@@ -19,9 +19,9 @@
/**
* @file RC/STM8/chcore.c
- * @brief STM8 architecture port code.
+ * @brief STM8 (Raisonance) architecture port code.
*
- * @addtogroup STM8_CORE
+ * @addtogroup STM8_RAISONANCE_CORE
* @{
*/
#pragma SRC("tmp.asm")
diff --git a/os/ports/RC/STM8/chcore.h b/os/ports/RC/STM8/chcore.h
index bc6d43971..6c2848ec3 100644
--- a/os/ports/RC/STM8/chcore.h
+++ b/os/ports/RC/STM8/chcore.h
@@ -19,9 +19,9 @@
/**
* @file RC/STM8/chcore.h
- * @brief STM8 architecture port macros and structures.
+ * @brief STM8 (Raisonance) architecture port macros and structures.
*
- * @addtogroup STM8_CORE
+ * @addtogroup STM8_RAISONANCE_CORE
* @{
*/
@@ -53,7 +53,7 @@
/**
* @brief Name of the implemented architecture.
*/
-#define CH_ARCHITECTURE_NAME "STM8"
+#define CH_ARCHITECTURE_NAME "STM8"
/*===========================================================================*/
/* Port implementation part. */
@@ -155,19 +155,16 @@ struct stm8_startctx {
* by @p INT_REQUIRED_STACK.
*/
#ifndef IDLE_THREAD_STACK_SIZE
-#define IDLE_THREAD_STACK_SIZE 0
+#define IDLE_THREAD_STACK_SIZE 0
#endif
/**
* @brief Per-thread stack overhead for interrupts servicing.
- * @details This constant is used in the calculation of the correct working
- * area size.
- * This value can be zero on those architecture where there is a
- * separate interrupt stack and the stack space between @p intctx and
- * @p extctx is known to be zero.
+ * @details This is a safe value, you may trim it down after reading the
+ * right size in the map file.
*/
#ifndef INT_REQUIRED_STACK
-#define INT_REQUIRED_STACK 32
+#define INT_REQUIRED_STACK 48
#endif
/**
@@ -212,7 +209,7 @@ struct stm8_startctx {
* @note @p id can be a function name or a vector number depending on the
* port implementation.
*/
-#define PORT_IRQ_HANDLER(id) void irq##id(void) interrupt id
+#define PORT_IRQ_HANDLER(id) void vector##id(void) interrupt id
/**
* @brief Port-related initialization code.
@@ -289,9 +286,9 @@ struct stm8_startctx {
#ifdef __cplusplus
extern "C" {
#endif
- void port_halt(void);
void _port_switch(Thread *otp);
void _port_thread_start(void);
+ void port_halt(void);
#ifdef __cplusplus
}
#endif
@@ -318,7 +315,7 @@ typedef struct {
#endif
} ReadyList;
-extern page0 ReadyList rlist;
+page0 extern ReadyList rlist;
#endif /* _CHCORE_H_ */
diff --git a/os/ports/RC/STM8/chtypes.h b/os/ports/RC/STM8/chtypes.h
index fd3370563..4f2241b1f 100644
--- a/os/ports/RC/STM8/chtypes.h
+++ b/os/ports/RC/STM8/chtypes.h
@@ -18,10 +18,10 @@
*/
/**
- * @file STM8/chtypes.h
- * @brief STM8 port system types.
+ * @file RC/STM8/chtypes.h
+ * @brief STM8 (Raisonance) port system types.
*
- * @addtogroup STM8_CORE
+ * @addtogroup STM8_RAISONANCE_CORE
* @{
*/
@@ -94,7 +94,7 @@ typedef uint16_t systime_t;
/**
* @brief Counter, recommended fastest signed.
*/
-typedef int16_t cnt_t;
+typedef int8_t cnt_t;
/**
* @brief Inline function modifier.
@@ -103,7 +103,7 @@ typedef int16_t cnt_t;
/**
* @brief ROM constant modifier.
- * @note Uses the custom "code" keyword in this port.
+ * @note Uses the "const" keyword in this port.
*/
#define ROMCONST code
diff --git a/os/ports/RC/STM8/port.dox b/os/ports/RC/STM8/port.dox
index 66f88c427..2f6d55236 100644
--- a/os/ports/RC/STM8/port.dox
+++ b/os/ports/RC/STM8/port.dox
@@ -18,10 +18,10 @@
*/
/**
- * @defgroup STM8 STM8
+ * @defgroup STM8_RAISONANCE STM8
* @details STM8 port for the Raisonance C compiler.
*
- * @section STM8_STATES Mapping of the System States in the STM8 port
+ * @section STM8_RAISONANCE_STATES Mapping of the System States in the STM8 port
* The ChibiOS/RT logical @ref system_states are mapped as follow in the STM8
* port:
* - <b>Init</b>. This state is represented by the startup code and the
@@ -44,7 +44,7 @@
* maskable interrupt sources that can be associated to this state.
* - <b>Halted</b>. Implemented as an infinite loop with interrupts disabled.
* .
- * @section STM8_NOTES The STM8 port notes
+ * @section STM8_RAISONANCE_NOTES The STM8 port notes
* - The STM8 does not have a dedicated interrupt stack, make sure to reserve
* enough stack space for interrupts in each thread stack. This can be done
* by modifying the @p INT_REQUIRED_STACK macro into
@@ -61,7 +61,7 @@
*/
/**
- * @defgroup STM8_CONF Configuration Options
+ * @defgroup STM8_RAISONANCE_CONF Configuration Options
* @brief STM8 Configuration Options.
* @details The STM8 port allows some architecture-specific configurations
* settings that can be specified externally, as example on the compiler
@@ -72,15 +72,15 @@
* thread so be careful in order to not waste precious RAM space.<br>
* The default value is set into <b>./os/ports/RC/STM8/chcore.h</b>.
* .
- * @ingroup STM8
+ * @ingroup STM8_RAISONANCE
*/
/**
- * @defgroup STM8_CORE Core Port Implementation
+ * @defgroup STM8_RAISONANCE_CORE Core Port Implementation
* @brief STM8 specific port code, structures and macros.
*
- * @ingroup STM8
- * @file STM8/chtypes.h Port types.
- * @file STM8/chcore.h Port related structures and macros.
- * @file STM8/chcore.c Port related code.
+ * @ingroup STM8_RAISONANCE
+ * @file RC/STM8/chtypes.h Port types.
+ * @file RC/STM8/chcore.h Port related structures and macros.
+ * @file RC/STM8/chcore.c Port related code.
*/
diff --git a/os/ports/cosmic/STM8/chcore.c b/os/ports/cosmic/STM8/chcore.c
new file mode 100644
index 000000000..a9a340d4b
--- /dev/null
+++ b/os/ports/cosmic/STM8/chcore.c
@@ -0,0 +1,70 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file cosmic/STM8/chcore.c
+ * @brief STM8 (Cosmic) architecture port code.
+ *
+ * @addtogroup STM8_COSMIC_CORE
+ * @{
+ */
+
+#include "ch.h"
+
+@tiny ReadyList rlist;
+
+/**
+ * @brief Performs a context switch between two threads.
+ *
+ * @param otp the thread to be switched out
+ */
+void _port_switch(Thread *otp) {
+
+ _asm(" xref _rlist \n"
+ " ldw y,sp \n"
+ " ldw (5,x),y \n"
+ " ldw x,_rlist+5 \n"
+ " ldw x,(5,x) \n"
+ " ldw sp,x \n", otp);
+}
+
+/**
+ * @brief Thread start code.
+ */
+void _port_thread_start(void) {
+
+ _asm(" rim \n"
+ " popw x \n");
+}
+
+/**
+ * @brief Halts the system.
+ * @details This function is invoked by the operating system when an
+ * unrecoverable error is detected (as example because a programming
+ * error in the application code that triggers an assertion while in
+ * debug mode).
+ */
+void port_halt(void) {
+
+ port_disable();
+ while (TRUE) {
+ }
+}
+
+/** @} */
diff --git a/os/ports/cosmic/STM8/chcore.h b/os/ports/cosmic/STM8/chcore.h
new file mode 100644
index 000000000..e04341c2e
--- /dev/null
+++ b/os/ports/cosmic/STM8/chcore.h
@@ -0,0 +1,320 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file cosmic/STM8/chcore.h
+ * @brief STM8 (Cosmic) architecture port macros and structures.
+ *
+ * @addtogroup STM8_COSMIC_CORE
+ * @{
+ */
+
+#ifndef _CHCORE_H_
+#define _CHCORE_H_
+
+/*===========================================================================*/
+/* Port configurable parameters. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the use of the WFI instruction in the idle thread loop.
+ */
+#ifndef STM8_ENABLE_WFI_IDLE
+#define STM8_ENABLE_WFI_IDLE FALSE
+#endif
+
+/*===========================================================================*/
+/* Port exported info. */
+/*===========================================================================*/
+
+/**
+ * @brief Unique macro for the implemented architecture.
+ */
+#define CH_ARCHITECTURE_STM8
+
+/**
+ * @brief Name of the implemented architecture.
+ */
+#define CH_ARCHITECTURE_NAME "STM8"
+
+/*===========================================================================*/
+/* Port implementation part. */
+/*===========================================================================*/
+
+/**
+ * @brief Base type for stack alignment.
+ * @note No alignment constraints so uint8_t.
+ */
+typedef uint8_t stkalign_t;
+
+/**
+ * @brief Generic STM8 function pointer.
+ * @note It is used to allocate the proper size for return addresses in
+ * context-related structures.
+ */
+typedef void (*stm8func_t)(void);
+
+#if !defined(__DOXYGEN__)
+/**
+ * @brief Interrupt saved context.
+ * @details This structure represents the stack frame saved during a
+ * preemption-capable interrupt handler.
+ * @note The structure requires one dummy field at its start because the
+ * stack is handled as preincremented/postdecremented.
+ */
+struct extctx {
+ uint8_t _next;
+ uint8_t c_y[3];
+ uint8_t c_x[3];
+ uint8_t cc;
+ uint8_t a;
+ uint16_t x;
+ uint16_t y;
+ uint8_t pce;
+ uint8_t pch;
+ uint8_t pcl;
+};
+#endif
+
+#if !defined(__DOXYGEN__)
+/**
+ * @brief System saved context.
+ * @details This structure represents the inner stack frame during a context
+ * switching..
+ * @note The structure requires one dummy field at its start because the
+ * stack is handled as preincremented/postdecremented.
+ */
+struct intctx {
+ uint8_t _next;
+ stm8func_t pc; /* Function pointer sized return address. */
+};
+#endif
+
+#if !defined(__DOXYGEN__)
+/**
+ * @brief Platform dependent part of the @p Thread structure.
+ * @details This structure usually contains just the saved stack pointer
+ * defined as a pointer to a @p intctx structure.
+ */
+struct context {
+ struct intctx *sp;
+};
+#endif
+
+/**
+ * @brief Start context.
+ * @details This context is the stack organization for the trampoline code
+ * @p _port_thread_start().
+ */
+struct stm8_startctx {
+ uint8_t _next;
+ stm8func_t ts; /* Trampoline address. */
+ void *arg; /* Thread argument. */
+ stm8func_t pc; /* Thread function address. */
+ stm8func_t ret; /* chThdExit() address. */
+};
+
+/**
+ * @brief Platform dependent part of the @p chThdInit() API.
+ * @details This code usually setup the context switching frame represented
+ * by an @p intctx structure.
+ */
+#define SETUP_CONTEXT(workspace, wsize, pf, arg) { \
+ struct stm8_startctx *scp; \
+ scp = (struct stm8_startctx *)((uint8_t *)workspace + wsize - \
+ sizeof(struct stm8_startctx)); \
+ scp->ts = _port_thread_start; \
+ scp->arg = arg; \
+ scp->pc = (stm8func_t)pf; \
+ scp->ret = (stm8func_t)chThdExit; \
+ tp->p_ctx.sp = (struct intctx *)scp; \
+}
+
+/**
+ * @brief Stack size for the system idle thread.
+ * @details This size depends on the idle thread implementation, usually
+ * the idle thread should take no more space than those reserved
+ * by @p INT_REQUIRED_STACK.
+ */
+#ifndef IDLE_THREAD_STACK_SIZE
+#define IDLE_THREAD_STACK_SIZE 0
+#endif
+
+/**
+ * @brief Per-thread stack overhead for interrupts servicing.
+ * @details This is a safe value, you may trim it down after reading the
+ * right size in the map file.
+ */
+#ifndef INT_REQUIRED_STACK
+#define INT_REQUIRED_STACK 48
+#endif
+
+/**
+ * @brief Enforces a correct alignment for a stack area size value.
+ */
+#define STACK_ALIGN(n) ((((n) - 1) | (sizeof(stkalign_t) - 1)) + 1)
+
+/**
+ * @brief Computes the thread working area global size.
+ */
+#define THD_WA_SIZE(n) STACK_ALIGN(sizeof(Thread) + \
+ (sizeof(struct intctx) - 1) + \
+ (sizeof(struct extctx) - 1) + \
+ (n) + (INT_REQUIRED_STACK))
+
+/**
+ * @brief Static working area allocation.
+ * @details This macro is used to allocate a static thread working area
+ * aligned as both position and size.
+ */
+#define WORKING_AREA(s, n) stkalign_t s[THD_WA_SIZE(n) / sizeof(stkalign_t)]
+
+/**
+ * @brief IRQ prologue code.
+ * @details This macro must be inserted at the start of all IRQ handlers
+ * enabled to invoke system APIs.
+ */
+#define PORT_IRQ_PROLOGUE()
+
+/**
+ * @brief IRQ epilogue code.
+ * @details This macro must be inserted at the end of all IRQ handlers
+ * enabled to invoke system APIs.
+ */
+#define PORT_IRQ_EPILOGUE() { \
+ if (chSchIsRescRequiredExI()) \
+ chSchDoRescheduleI(); \
+}
+
+/**
+ * @brief IRQ handler function declaration.
+ * @note @p id can be a function name or a vector number depending on the
+ * port implementation.
+ */
+#define PORT_IRQ_HANDLER(id) @far @interrupt void vector##id(void)
+
+/**
+ * @brief Port-related initialization code.
+ * @note None in this port.
+ */
+#define port_init()
+
+/**
+ * @brief Kernel-lock action.
+ * @note Implemented as global interrupts disable.
+ */
+#define port_lock() _asm("sim")
+
+/**
+ * @brief Kernel-unlock action.
+ * @note Implemented as global interrupts enable.
+ */
+#define port_unlock() _asm("rim")
+
+/**
+ * @brief Kernel-lock action from an interrupt handler.
+ * @note This function is empty in this port.
+ */
+#define port_lock_from_isr()
+
+/**
+ * @brief Kernel-unlock action from an interrupt handler.
+ * @note This function is empty in this port.
+ */
+#define port_unlock_from_isr()
+
+/**
+ * @brief Disables all the interrupt sources.
+ * @note Implemented as global interrupts disable.
+ * @note Of course non maskable interrupt sources are not included.
+ */
+#define port_disable() _asm("sim")
+
+/**
+ * @brief Disables the interrupt sources that are not supposed to preempt
+ * the kernel.
+ * @note Same as @p port_disable() in this port, there is no difference
+ * between the two states.
+ */
+#define port_suspend() _asm("sim")
+
+/**
+ * @brief Enables all the interrupt sources.
+ * @note Implemented as global interrupt enable.
+ */
+#define port_enable() _asm("rim")
+
+/**
+ * @brief Enters an architecture-dependent halt mode.
+ * @note Implemented with the specific "wfi" instruction.
+ */
+#if STM8_ENABLE_WFI_IDLE || defined(__DOXYGEN__)
+#define port_wait_for_interrupt() _asm("wfi")
+#else
+#define port_wait_for_interrupt()
+#endif
+
+/**
+ * @brief Performs a context switch between two threads.
+ * @details This is the most critical code in any port, this function
+ * is responsible for the context switch between 2 threads.
+ * @note Implemented as a call to a low level assembler routine.
+ *
+ * @param ntp the thread to be switched in
+ * @param otp the thread to be switched out
+ */
+#define port_switch(ntp, otp) _port_switch(otp)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void _port_switch(Thread *otp);
+ void _port_thread_start(void);
+ void port_halt(void);
+#ifdef __cplusplus
+}
+#endif
+
+/*===========================================================================*/
+/* Scheduler captured code. */
+/*===========================================================================*/
+
+#define PORT_OPTIMIZED_RLIST_VAR
+#define PORT_OPTIMIZED_RLIST_EXT
+#define PORT_OPTIMIZED_READYLIST_STRUCT
+
+typedef struct {
+ ThreadsQueue r_queue;
+ tprio_t r_prio;
+ Thread *r_current;
+#if CH_USE_REGISTRY
+ Thread *r_newer;
+ Thread *r_older;
+#endif
+ /* End of the fields shared with the Thread structure.*/
+#if CH_TIME_QUANTUM > 0
+ cnt_t r_preempt;
+#endif
+} ReadyList;
+
+@tiny extern ReadyList rlist;
+
+#endif /* _CHCORE_H_ */
+
+/** @} */
diff --git a/os/ports/cosmic/STM8/chtypes.h b/os/ports/cosmic/STM8/chtypes.h
new file mode 100644
index 000000000..3fe35570d
--- /dev/null
+++ b/os/ports/cosmic/STM8/chtypes.h
@@ -0,0 +1,130 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file cosmic/STM8/chtypes.h
+ * @brief STM8 (Cosmic) port system types.
+ *
+ * @addtogroup STM8_COSMIC_CORE
+ * @{
+ */
+
+#ifndef _CHTYPES_H_
+#define _CHTYPES_H_
+
+#define __need_NULL
+#define __need_size_t
+#include <stddef.h>
+
+//#if !defined(_STDINT_H) && !defined(__STDINT_H_)
+//#include <stdint.h>
+//#endif
+
+typedef unsigned char uint8_t; /**< C99-style 8 bits unsigned. */
+typedef signed char int8_t; /**< C99-style 8 bits signed. */
+typedef unsigned int uint16_t; /**< C99-style 16 bits unsigned. */
+typedef signed int int16_t; /**< C99-style 16 bits signed. */
+typedef unsigned long uint32_t; /**< C99-style 32 bits unsigned. */
+typedef signed long int32_t; /**< C99-style 32 bits signed. */
+typedef uint8_t uint_fast8_t; /**< C99-style 8 bits unsigned. */
+typedef uint16_t uint_fast16_t; /**< C99-style 16 bits unsigned. */
+typedef uint32_t uint_fast32_t; /**< C99-style 32 bits unsigned. */
+
+/**
+ * @brief Boolean, recommended the fastest signed.
+ */
+typedef int8_t bool_t;
+
+/**
+ * @brief Thread mode flags, uint8_t is ok.
+ */
+typedef uint8_t tmode_t;
+
+/**
+ * @brief Thread state, uint8_t is ok.
+ */
+typedef uint8_t tstate_t;
+
+/**
+ * @brief Thread references counter, uint8_t is ok.
+ */
+typedef uint8_t trefs_t;
+
+/**
+ * @brief Priority, use the fastest unsigned type.
+ */
+typedef uint8_t tprio_t;
+
+/**
+ * @brief Message, use signed pointer equivalent.
+ */
+typedef int16_t msg_t;
+
+/**
+ * @brief Event Id, use fastest signed.
+ */
+typedef int8_t eventid_t;
+
+/**
+ * @brief Event Mask, recommended fastest unsigned.
+ */
+typedef uint8_t eventmask_t;
+
+/**
+ * @brief System Time, recommended fastest unsigned.
+ */
+typedef uint16_t systime_t;
+
+/**
+ * @brief Counter, recommended fastest signed.
+ */
+typedef int8_t cnt_t;
+
+/**
+ * @brief Inline function modifier.
+ */
+#define INLINE @inline
+
+/**
+ * @brief ROM constant modifier.
+ * @note Uses the "const" keyword in this port.
+ */
+#define ROMCONST const
+
+/**
+ * @brief Packed structure modifier (within).
+ * @note Empty in this port.
+ */
+#define PACK_STRUCT_STRUCT
+
+/**
+ * @brief Packed structure modifier (before).
+ * @note Empty in this port.
+ */
+#define PACK_STRUCT_BEGIN
+
+/**
+ * @brief Packed structure modifier (after).
+ * @note Empty in this port.
+ */
+#define PACK_STRUCT_END
+
+#endif /* _CHTYPES_H_ */
+
+/** @} */
diff --git a/os/ports/cosmic/STM8/port.dox b/os/ports/cosmic/STM8/port.dox
new file mode 100644
index 000000000..3fa2cdb39
--- /dev/null
+++ b/os/ports/cosmic/STM8/port.dox
@@ -0,0 +1,86 @@
+/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @defgroup STM8_COSMIC STM8
+ * @details STM8 port for the Cosmic C compiler.
+ *
+ * @section STM8_COSMIC_STATES Mapping of the System States in the STM8 port
+ * The ChibiOS/RT logical @ref system_states are mapped as follow in the STM8
+ * port:
+ * - <b>Init</b>. This state is represented by the startup code and the
+ * initialization code before @p chSysInit() is executed. It has not a
+ * special hardware state associated.
+ * - <b>Normal</b>. This is the state the system has after executing
+ * @p chSysInit(). Interrupts are enabled.
+ * - <b>Suspended</b>. Interrupts are disabled.
+ * - <b>Disabled</b>. Interrupts are enabled. This state is equivalent to the
+ * Suspended state because there are no fast interrupts in this architecture.
+ * - <b>Sleep</b>. Implemented with "wait" instruction insertion in the idle
+ * loop.
+ * - <b>S-Locked</b>. Interrupts are disabled.
+ * - <b>I-Locked</b>. This state is equivalent to the SRI state, the
+ * @p chSysLockI() and @p chSysUnlockI() APIs do nothing (still use them in
+ * order to formally change state because this may change).
+ * - <b>Serving Regular Interrupt</b>. Normal interrupt service code.
+ * - <b>Serving Fast Interrupt</b>. Not present in this architecture.
+ * - <b>Serving Non-Maskable Interrupt</b>. The STM8 ha non
+ * maskable interrupt sources that can be associated to this state.
+ * - <b>Halted</b>. Implemented as an infinite loop with interrupts disabled.
+ * .
+ * @section STM8_COSMIC_NOTES The STM8 port notes
+ * - The STM8 does not have a dedicated interrupt stack, make sure to reserve
+ * enough stack space for interrupts in each thread stack. This can be done
+ * by modifying the @p INT_REQUIRED_STACK macro into
+ * <b>./os/ports/RC/STM8/chcore.h</b>.
+ * - The kernel currently supports only the small memory model so the
+ * kernel files should be loaded in the first 64K. Note that this is not
+ * a problem because upper addresses can be used by the user code, the
+ * kernel can context switch code running there.
+ * - The configuration option @p CH_OPTIMIZE_SPEED is not currently supported
+ * because the missing support of the @p inline "C" keyword in the
+ * compiler.
+ * .
+ * @ingroup cosmic
+ */
+
+/**
+ * @defgroup STM8_COSMIC_CONF Configuration Options
+ * @brief STM8 Configuration Options.
+ * @details The STM8 port allows some architecture-specific configurations
+ * settings that can be specified externally, as example on the compiler
+ * command line:
+ * - @p INT_REQUIRED_STACK, this value represent the amount of stack space
+ * used by the interrupt handlers.<br>
+ * The default for this value is @p 32, this space is allocated for each
+ * thread so be careful in order to not waste precious RAM space.<br>
+ * The default value is set into <b>./os/ports/cosmic/STM8/chcore.h</b>.
+ * .
+ * @ingroup STM8_COSMIC
+ */
+
+/**
+ * @defgroup STM8_COSMIC_CORE Core Port Implementation
+ * @brief STM8 specific port code, structures and macros.
+ *
+ * @ingroup STM8_COSMIC
+ * @file cosmic/STM8/chtypes.h Port types.
+ * @file cosmic/STM8/chcore.h Port related structures and macros.
+ * @file cosmic/STM8/chcore.c Port related code.
+ */
diff --git a/os/ports/ports.dox b/os/ports/ports.dox
index e47c390fe..7c48feece 100644
--- a/os/ports/ports.dox
+++ b/os/ports/ports.dox
@@ -31,8 +31,15 @@
*/
/**
- * @defgroup raisonance Raisonance Ports
- * Ports for the Raisonance compiler or derivatives.
+ * @defgroup cosmic Cosmic Compiler Ports
+ * Ports for the Compiler compiler.
+ *
+ * @ingroup ports
+ */
+
+/**
+ * @defgroup raisonance Raisonance Compiler Ports
+ * Ports for the Raisonance compiler.
*
* @ingroup ports
*/
diff --git a/readme.txt b/readme.txt
index d33c731df..9b6e4e877 100644
--- a/readme.txt
+++ b/readme.txt
@@ -75,6 +75,10 @@
in 2.0.1).
- FIX: Fixed broken AVR port (bug 3016619)(backported in 2.0.0).
- FIX: Fixed assertion in adcStop() (bug 3015109)(backported in 2.0.0).
+- NEW: Merged the new unified STM8 port, now the port supports both the
+ Cosmic and Raisonance compilers.
+- NEW: Added an STM8-DISCOVERY demo, the demo can be compiled with both the
+ Cosmic and Raisonance compilers under the STDV IDE.
- NEW: Added timers clock macros to the STM32 clock tree HAL driver (backported
in 2.0.1).
- NEW: Added Binary Semaphores among the synchronization primitives. The new
diff --git a/test/test.c b/test/test.c
index 3a5c93edc..5f876e6b8 100644
--- a/test/test.c
+++ b/test/test.c
@@ -44,7 +44,7 @@
/*
* Array of all the test patterns.
*/
-static const struct testcase **patterns[] = {
+static ROMCONST struct testcase **patterns[] = {
patternthd,
patternsem,
patternmtx,
@@ -78,8 +78,8 @@ Thread *threads[MAX_THREADS];
/*
* Pointers to the working areas.
*/
-void * const wa[5] = {test.wa.T0, test.wa.T1, test.wa.T2,
- test.wa.T3, test.wa.T4};
+void * ROMCONST wa[5] = {test.wa.T0, test.wa.T1, test.wa.T2,
+ test.wa.T3, test.wa.T4};
/*
* Console output.
diff --git a/test/test.h b/test/test.h
index 2ab27847e..0815cfcfa 100644
--- a/test/test.h
+++ b/test/test.h
@@ -45,10 +45,10 @@
#define MAX_THREADS 5
#define MAX_TOKENS 16
-#if defined(CH_ARCHITECTURE_AVR) || \
- defined(CH_ARCHITECTURE_MSP430) || \
- defined(CH_ARCHITECTURE_STM8)
+#if defined(CH_ARCHITECTURE_AVR) || defined(CH_ARCHITECTURE_MSP430)
#define THREADS_STACK_SIZE 48
+#elif defined(CH_ARCHITECTURE_STM8)
+#define THREADS_STACK_SIZE 64
#elif defined(CH_ARCHITECTURE_SIMIA32)
#define THREADS_STACK_SIZE 512
#else
@@ -84,8 +84,8 @@ extern "C" {
#endif
msg_t TestThread(void *p);
void test_printn(uint32_t n);
- void test_print(const char *msgp);
- void test_println(const char *msgp);
+ void test_print(char *msgp);
+ void test_println(char *msgp);
void test_emit_token(char token);
bool_t _test_fail(unsigned point);
bool_t _test_assert(unsigned point, bool_t condition);
@@ -151,7 +151,7 @@ extern "C" {
#if !defined(__DOXYGEN__)
extern Thread *threads[MAX_THREADS];
extern union test_buffers test;
-extern void * const wa[];
+extern void * ROMCONST wa[];
extern bool_t test_timer_done;
#endif
diff --git a/test/testbmk.c b/test/testbmk.c
index a67c09af1..0f38eb78b 100644
--- a/test/testbmk.c
+++ b/test/testbmk.c
@@ -115,7 +115,7 @@ static void bmk1_execute(void) {
test_println(" ctxswc/S");
}
-const struct testcase testbmk1 = {
+ROMCONST struct testcase testbmk1 = {
"Benchmark, messages #1",
NULL,
NULL,
@@ -144,7 +144,7 @@ static void bmk2_execute(void) {
test_println(" ctxswc/S");
}
-const struct testcase testbmk2 = {
+ROMCONST struct testcase testbmk2 = {
"Benchmark, messages #2",
NULL,
NULL,
@@ -183,7 +183,7 @@ static void bmk3_execute(void) {
test_println(" ctxswc/S");
}
-const struct testcase testbmk3 = {
+ROMCONST struct testcase testbmk3 = {
"Benchmark, messages #3",
NULL,
NULL,
@@ -244,7 +244,7 @@ static void bmk4_execute(void) {
test_println(" ctxswc/S");
}
-const struct testcase testbmk4 = {
+ROMCONST struct testcase testbmk4 = {
"Benchmark, context switch",
NULL,
NULL,
@@ -281,7 +281,7 @@ static void bmk5_execute(void) {
test_println(" threads/S");
}
-const struct testcase testbmk5 = {
+ROMCONST struct testcase testbmk5 = {
"Benchmark, threads, full cycle",
NULL,
NULL,
@@ -320,7 +320,7 @@ static void bmk6_execute(void) {
test_println(" threads/S");
}
-const struct testcase testbmk6 = {
+ROMCONST struct testcase testbmk6 = {
"Benchmark, threads, create only",
NULL,
NULL,
@@ -381,7 +381,7 @@ static void bmk7_execute(void) {
test_println(" ctxswc/S");
}
-const struct testcase testbmk7 = {
+ROMCONST struct testcase testbmk7 = {
"Benchmark, mass reschedule, 5 threads",
bmk7_setup,
NULL,
@@ -434,7 +434,7 @@ static void bmk8_execute(void) {
test_println(" ctxswc/S");
}
-const struct testcase testbmk8 = {
+ROMCONST struct testcase testbmk8 = {
"Benchmark, round robin context switching",
NULL,
NULL,
@@ -479,7 +479,7 @@ static void bmk9_execute(void) {
test_println(" bytes/S");
}
-const struct testcase testbmk9 = {
+ROMCONST struct testcase testbmk9 = {
"Benchmark, I/O Queues throughput",
NULL,
NULL,
@@ -520,7 +520,7 @@ static void bmk10_execute(void) {
test_println(" timers/S");
}
-const struct testcase testbmk10 = {
+ROMCONST struct testcase testbmk10 = {
"Benchmark, virtual timers set/reset",
NULL,
NULL,
@@ -566,7 +566,7 @@ static void bmk11_execute(void) {
test_println(" wait+signal/S");
}
-const struct testcase testbmk11 = {
+ROMCONST struct testcase testbmk11 = {
"Benchmark, semaphores wait/signal",
bmk11_setup,
NULL,
@@ -613,7 +613,7 @@ static void bmk12_execute(void) {
test_println(" lock+unlock/S");
}
-const struct testcase testbmk12 = {
+ROMCONST struct testcase testbmk12 = {
"Benchmark, mutexes lock/unlock",
bmk12_setup,
NULL,
@@ -674,7 +674,7 @@ static void bmk13_execute(void) {
#endif
}
-const struct testcase testbmk13 = {
+ROMCONST struct testcase testbmk13 = {
"Benchmark, RAM footprint",
NULL,
NULL,
@@ -684,7 +684,7 @@ const struct testcase testbmk13 = {
/**
* @brief Test sequence for benchmarks.
*/
-const struct testcase * const patternbmk[] = {
+ROMCONST struct testcase * ROMCONST patternbmk[] = {
#if !TEST_NO_BENCHMARKS
&testbmk1,
&testbmk2,
diff --git a/test/testbmk.h b/test/testbmk.h
index 775ea4501..5dde9a60c 100644
--- a/test/testbmk.h
+++ b/test/testbmk.h
@@ -20,6 +20,6 @@
#ifndef _TESTBMK_H_
#define _TESTBMK_H_
-extern const struct testcase *patternbmk[];
+extern ROMCONST struct testcase * ROMCONST patternbmk[];
#endif /* _TESTBMK_H_ */
diff --git a/test/testdyn.c b/test/testdyn.c
index 4bd4ed06c..69a1c3312 100644
--- a/test/testdyn.c
+++ b/test/testdyn.c
@@ -117,7 +117,7 @@ static void dyn1_execute(void) {
test_assert(4, n == sz, "heap size changed");
}
-const struct testcase testdyn1 = {
+ROMCONST struct testcase testdyn1 = {
"Dynamic APIs, threads creation from heap",
dyn1_setup,
NULL,
@@ -173,7 +173,7 @@ static void dyn2_execute(void) {
test_assert(4, chPoolAlloc(&mp1) == NULL, "pool list not empty");
}
-const struct testcase testdyn2 = {
+ROMCONST struct testcase testdyn2 = {
"Dynamic APIs, threads creation from memory pool",
dyn2_setup,
NULL,
@@ -240,7 +240,7 @@ static void dyn3_execute(void) {
test_assert(7, n1 == n3, "unexpected threads count");
}
-const struct testcase testdyn3 = {
+ROMCONST struct testcase testdyn3 = {
"Dynamic APIs, registry and references",
dyn3_setup,
NULL,
@@ -252,7 +252,7 @@ const struct testcase testdyn3 = {
/**
* @brief Test sequence for dynamic APIs.
*/
-const struct testcase * const patterndyn[] = {
+ROMCONST struct testcase * ROMCONST patterndyn[] = {
#if CH_USE_DYNAMIC
#if CH_USE_HEAP
&testdyn1,
diff --git a/test/testdyn.h b/test/testdyn.h
index 676f0863c..efcd4dc1e 100644
--- a/test/testdyn.h
+++ b/test/testdyn.h
@@ -20,6 +20,6 @@
#ifndef _TESTDYN_H_
#define _TESTDYN_H_
-extern const struct testcase *patterndyn[];
+extern ROMCONST struct testcase * ROMCONST patterndyn[];
#endif /* _TESTDYN_H_ */
diff --git a/test/testevt.c b/test/testevt.c
index 7e3f4a405..677e06d44 100644
--- a/test/testevt.c
+++ b/test/testevt.c
@@ -83,7 +83,7 @@ static void evt1_setup(void) {
static void h1(eventid_t id) {(void)id;test_emit_token('A');}
static void h2(eventid_t id) {(void)id;test_emit_token('B');}
static void h3(eventid_t id) {(void)id;test_emit_token('C');}
-static const evhandler_t evhndl[] = {h1, h2, h3};
+static ROMCONST evhandler_t evhndl[] = {h1, h2, h3};
static void evt1_execute(void) {
EventListener el1, el2;
@@ -107,7 +107,7 @@ static void evt1_execute(void) {
test_assert_sequence(4, "ABC");
}
-const struct testcase testevt1 = {
+ROMCONST struct testcase testevt1 = {
"Events, registration and dispatch",
evt1_setup,
NULL,
@@ -224,7 +224,7 @@ static void evt2_execute(void) {
test_assert(15, !chEvtIsListening(&es2), "stuck listener");
}
-const struct testcase testevt2 = {
+ROMCONST struct testcase testevt2 = {
"Events, wait and broadcast",
evt2_setup,
NULL,
@@ -272,7 +272,7 @@ static void evt3_execute(void) {
test_assert(6, m == 0, "spurious event");
}
-const struct testcase testevt3 = {
+ROMCONST struct testcase testevt3 = {
"Events, timeouts",
evt3_setup,
NULL,
@@ -283,7 +283,7 @@ const struct testcase testevt3 = {
/**
* @brief Test sequence for events.
*/
-const struct testcase * const patternevt[] = {
+ROMCONST struct testcase * ROMCONST patternevt[] = {
#if CH_USE_EVENTS
&testevt1,
&testevt2,
diff --git a/test/testevt.h b/test/testevt.h
index 9fb501265..687b16912 100644
--- a/test/testevt.h
+++ b/test/testevt.h
@@ -20,6 +20,6 @@
#ifndef _TESTEVT_H_
#define _TESTEVT_H_
-extern const struct testcase *patternevt[];
+extern ROMCONST struct testcase * ROMCONST patternevt[];
#endif /* _TESTEVT_H_ */
diff --git a/test/testheap.c b/test/testheap.c
index 698a01861..94fb87bb9 100644
--- a/test/testheap.c
+++ b/test/testheap.c
@@ -142,7 +142,7 @@ static void heap1_execute(void) {
test_assert(12, n == sz, "size changed");
}
-const struct testcase testheap1 = {
+ROMCONST struct testcase testheap1 = {
"Heap, allocation and fragmentation test",
heap1_setup,
NULL,
@@ -154,7 +154,7 @@ const struct testcase testheap1 = {
/**
* @brief Test sequence for heap.
*/
-const struct testcase * const patternheap[] = {
+ROMCONST struct testcase * ROMCONST patternheap[] = {
#if CH_USE_HEAP
&testheap1,
#endif
diff --git a/test/testheap.h b/test/testheap.h
index c847036bf..d5ce66ce3 100644
--- a/test/testheap.h
+++ b/test/testheap.h
@@ -20,6 +20,6 @@
#ifndef _TESTHEAP_H_
#define _TESTHEAP_H_
-extern const struct testcase *patternheap[];
+extern ROMCONST struct testcase * ROMCONST patternheap[];
#endif /* _TESTHEAP_H_ */
diff --git a/test/testmbox.c b/test/testmbox.c
index 7926f3d06..33706b5f5 100644
--- a/test/testmbox.c
+++ b/test/testmbox.c
@@ -155,7 +155,7 @@ static void mbox1_execute(void) {
test_assert(21, mb1.mb_buffer == mb1.mb_rdptr, "read pointer not aligned to base");
}
-const struct testcase testmbox1 = {
+ROMCONST struct testcase testmbox1 = {
"Mailboxes, queuing and timeouts",
mbox1_setup,
NULL,
@@ -167,7 +167,7 @@ const struct testcase testmbox1 = {
/**
* @brief Test sequence for mailboxes.
*/
-const struct testcase * const patternmbox[] = {
+ROMCONST struct testcase * ROMCONST patternmbox[] = {
#if CH_USE_MAILBOXES
&testmbox1,
#endif
diff --git a/test/testmbox.h b/test/testmbox.h
index 5cd4ea8c7..fc75552a3 100644
--- a/test/testmbox.h
+++ b/test/testmbox.h
@@ -20,6 +20,6 @@
#ifndef _TESTMBOX_H_
#define _TESTMBOX_H_
-extern const struct testcase *patternmbox[];
+extern ROMCONST struct testcase * ROMCONST patternmbox[];
#endif /* _TESTMBOX_H_ */
diff --git a/test/testmsg.c b/test/testmsg.c
index 5db9614bb..881db167f 100644
--- a/test/testmsg.c
+++ b/test/testmsg.c
@@ -101,7 +101,7 @@ static void msg1_execute(void) {
test_assert(3, msg == 0, "unknown message");
}
-const struct testcase testmsg1 = {
+ROMCONST struct testcase testmsg1 = {
"Messages, loop",
NULL,
NULL,
@@ -113,7 +113,7 @@ const struct testcase testmsg1 = {
/**
* @brief Test sequence for messages.
*/
-const struct testcase * const patternmsg[] = {
+ROMCONST struct testcase * ROMCONST patternmsg[] = {
#if CH_USE_MESSAGES
&testmsg1,
#endif
diff --git a/test/testmsg.h b/test/testmsg.h
index 0b96557e0..d7817d427 100644
--- a/test/testmsg.h
+++ b/test/testmsg.h
@@ -20,6 +20,6 @@
#ifndef _TESTMSG_H_
#define _TESTMSG_H_
-extern const struct testcase *patternmsg[];
+extern ROMCONST struct testcase * ROMCONST patternmsg[];
#endif /* _TESTMSG_H_ */
diff --git a/test/testmtx.c b/test/testmtx.c
index 7337b1f14..339403127 100644
--- a/test/testmtx.c
+++ b/test/testmtx.c
@@ -112,7 +112,7 @@ static void mtx1_execute(void) {
test_assert_sequence(2, "ABCDE");
}
-const struct testcase testmtx1 = {
+ROMCONST struct testcase testmtx1 = {
"Mutexes, priority enqueuing test",
mtx1_setup,
NULL,
@@ -203,7 +203,7 @@ static void mtx2_execute(void) {
test_assert_time_window(2, time + MS2ST(100), time + MS2ST(100) + ALLOWED_DELAY);
}
-const struct testcase testmtx2 = {
+ROMCONST struct testcase testmtx2 = {
"Mutexes, priority inheritance, simple case",
mtx2_setup,
NULL,
@@ -323,7 +323,7 @@ static void mtx3_execute(void) {
test_assert_time_window(2, time + MS2ST(110), time + MS2ST(110) + ALLOWED_DELAY);
}
-const struct testcase testmtx3 = {
+ROMCONST struct testcase testmtx3 = {
"Mutexes, priority inheritance, complex case",
mtx3_setup,
NULL,
@@ -411,7 +411,7 @@ static void mtx4_execute(void) {
test_wait_threads();
}
-const struct testcase testmtx4 = {
+ROMCONST struct testcase testmtx4 = {
"Mutexes, priority return",
mtx4_setup,
NULL,
@@ -454,7 +454,7 @@ static void mtx5_execute(void) {
test_assert(5, chThdGetPriority() == prio, "wrong priority level");
}
-const struct testcase testmtx5 = {
+ROMCONST struct testcase testmtx5 = {
"Mutexes, status",
mtx5_setup,
NULL,
@@ -508,7 +508,7 @@ static void mtx6_execute(void) {
test_assert_sequence(1, "ABCDE");
}
-const struct testcase testmtx6 = {
+ROMCONST struct testcase testmtx6 = {
"CondVar, signal test",
mtx6_setup,
NULL,
@@ -545,7 +545,7 @@ static void mtx7_execute(void) {
test_assert_sequence(1, "ABCDE");
}
-const struct testcase testmtx7 = {
+ROMCONST struct testcase testmtx7 = {
"CondVar, broadcast test",
mtx7_setup,
NULL,
@@ -603,7 +603,7 @@ static void mtx8_execute(void) {
test_assert_sequence(1, "ABC");
}
-const struct testcase testmtx8 = {
+ROMCONST struct testcase testmtx8 = {
"CondVar, boost test",
mtx8_setup,
NULL,
@@ -615,7 +615,7 @@ const struct testcase testmtx8 = {
/**
* @brief Test sequence for mutexes.
*/
-const struct testcase * const patternmtx[] = {
+ROMCONST struct testcase * ROMCONST patternmtx[] = {
#if CH_USE_MUTEXES
&testmtx1,
#if CH_DBG_THREADS_PROFILING
diff --git a/test/testmtx.h b/test/testmtx.h
index b28837775..cd7ddf497 100644
--- a/test/testmtx.h
+++ b/test/testmtx.h
@@ -20,6 +20,6 @@
#ifndef _TESTMTX_H_
#define _TESTMTX_H_
-extern const struct testcase *patternmtx[];
+extern ROMCONST struct testcase * ROMCONST patternmtx[];
#endif /* _TESTMTX_H_ */
diff --git a/test/testpools.c b/test/testpools.c
index 2ed0e6b35..c503ecbda 100644
--- a/test/testpools.c
+++ b/test/testpools.c
@@ -90,7 +90,7 @@ static void pools1_execute(void) {
test_assert(3, chPoolAlloc(&mp1) == NULL, "provider returned memory");
}
-const struct testcase testpools1 = {
+ROMCONST struct testcase testpools1 = {
"Memory Pools, queue/dequeue",
pools1_setup,
NULL,
@@ -102,7 +102,7 @@ const struct testcase testpools1 = {
/*
* @brief Test sequence for pools.
*/
-const struct testcase * const patternpools[] = {
+ROMCONST struct testcase * ROMCONST patternpools[] = {
#if CH_USE_MEMPOOLS
&testpools1,
#endif
diff --git a/test/testpools.h b/test/testpools.h
index 1d9d3e0d9..5f526f1d6 100644
--- a/test/testpools.h
+++ b/test/testpools.h
@@ -20,6 +20,6 @@
#ifndef _TESTPOOLS_H_
#define _TESTPOOLS_H_
-extern const struct testcase *patternpools[];
+extern ROMCONST struct testcase * ROMCONST patternpools[];
#endif /* _TESTPOOLS_H_ */
diff --git a/test/testqueues.c b/test/testqueues.c
index 149c2a3c3..a9895a29a 100644
--- a/test/testqueues.c
+++ b/test/testqueues.c
@@ -129,7 +129,7 @@ static void queues1_execute(void) {
test_assert(12, chIQGetTimeout(&iq, 10) == Q_TIMEOUT, "wrong timeout return");
}
-const struct testcase testqueues1 = {
+ROMCONST struct testcase testqueues1 = {
"Queues, input queues",
queues1_setup,
NULL,
@@ -189,7 +189,7 @@ static void queues2_execute(void) {
test_assert(12, chOQPutTimeout(&oq, 0, 10) == Q_TIMEOUT, "wrong timeout return");
}
-const struct testcase testqueues2 = {
+ROMCONST struct testcase testqueues2 = {
"Queues, output queues",
queues2_setup,
NULL,
@@ -200,7 +200,7 @@ const struct testcase testqueues2 = {
/**
* @brief Test sequence for queues.
*/
-const struct testcase * const patternqueues[] = {
+ROMCONST struct testcase * ROMCONST patternqueues[] = {
#if CH_USE_QUEUES
&testqueues1,
&testqueues2,
diff --git a/test/testqueues.h b/test/testqueues.h
index c05d62641..1f86fc763 100644
--- a/test/testqueues.h
+++ b/test/testqueues.h
@@ -20,6 +20,6 @@
#ifndef _TESTQUEUES_H_
#define _TESTQUEUES_H_
-extern const struct testcase *patternqueues[];
+extern ROMCONST struct testcase * ROMCONST patternqueues[];
#endif /* _TESTQUEUES_H_ */
diff --git a/test/testsem.c b/test/testsem.c
index 58d4e5e35..798e3a65d 100644
--- a/test/testsem.c
+++ b/test/testsem.c
@@ -103,7 +103,7 @@ static void sem1_execute(void) {
#endif
}
-const struct testcase testsem1 = {
+ROMCONST struct testcase testsem1 = {
"Semaphores, enqueuing",
sem1_setup,
NULL,
@@ -177,7 +177,7 @@ static void sem2_execute(void) {
test_assert_time_window(11, target_time, target_time + ALLOWED_DELAY);
}
-const struct testcase testsem2 = {
+ROMCONST struct testcase testsem2 = {
"Semaphores, timeout",
sem2_setup,
NULL,
@@ -222,7 +222,7 @@ static void sem3_execute(void) {
test_assert(4, sem1.s_cnt == 0, "counter not zero");
}
-const struct testcase testsem3 = {
+ROMCONST struct testcase testsem3 = {
"Semaphores, atomic signal-wait",
sem3_setup,
NULL,
@@ -234,7 +234,7 @@ const struct testcase testsem3 = {
/**
* @brief Test sequence for semaphores.
*/
-const struct testcase * const patternsem[] = {
+ROMCONST struct testcase * ROMCONST patternsem[] = {
#if CH_USE_SEMAPHORES
&testsem1,
&testsem2,
diff --git a/test/testsem.h b/test/testsem.h
index 74a6f89bd..cfa3b6330 100644
--- a/test/testsem.h
+++ b/test/testsem.h
@@ -20,6 +20,6 @@
#ifndef _TESTSEM_H_
#define _TESTSEM_H_
-extern const struct testcase *patternsem[];
+extern ROMCONST struct testcase * ROMCONST patternsem[];
#endif /* _TESTSEM_H_ */
diff --git a/test/testthd.c b/test/testthd.c
index 232ea7008..b12378320 100644
--- a/test/testthd.c
+++ b/test/testthd.c
@@ -77,7 +77,7 @@ static void thd1_execute(void) {
test_assert_sequence(1, "ABCDE");
}
-const struct testcase testthd1 = {
+ROMCONST struct testcase testthd1 = {
"Threads, enqueuing test #1",
NULL,
NULL,
@@ -105,7 +105,7 @@ static void thd2_execute(void) {
test_assert_sequence(1, "ABCDE");
}
-const struct testcase testthd2 = {
+ROMCONST struct testcase testthd2 = {
"Threads, enqueuing test #2",
NULL,
NULL,
@@ -170,7 +170,7 @@ static void thd3_execute(void) {
#endif
}
-const struct testcase testthd3 = {
+ROMCONST struct testcase testthd3 = {
"Threads, priority change",
NULL,
NULL,
@@ -211,7 +211,7 @@ static void thd4_execute(void) {
test_assert_time_window(4, time, time + 1);
}
-const struct testcase testthd4 = {
+ROMCONST struct testcase testthd4 = {
"Threads, delays",
NULL,
NULL,
@@ -221,7 +221,7 @@ const struct testcase testthd4 = {
/**
* @brief Test sequence for threads.
*/
-const struct testcase * const patternthd[] = {
+ROMCONST struct testcase * ROMCONST patternthd[] = {
&testthd1,
&testthd2,
&testthd3,
diff --git a/test/testthd.h b/test/testthd.h
index 5b71c98fb..e355f63fb 100644
--- a/test/testthd.h
+++ b/test/testthd.h
@@ -20,6 +20,6 @@
#ifndef _TESTRDY_H_
#define _TESTRDY_H_
-extern const struct testcase *patternthd[];
+extern ROMCONST struct testcase * ROMCONST patternthd[];
#endif /* _TESTRDY_H_ */
generated by cgit v1.2.3 (git 2.25.1) at 2024-10-06 05:12:29 +0000