diff options
282 files changed, 10588 insertions, 460 deletions
diff --git a/boards/OLIMEX_STM32_P407/board.c b/boards/OLIMEX_STM32_P407/board.c new file mode 100644 index 000000000..59b6e9de6 --- /dev/null +++ b/boards/OLIMEX_STM32_P407/board.c @@ -0,0 +1,58 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#include "ch.h"
+#include "hal.h"
+
+/**
+ * @brief PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ * This variable is used by the HAL when initializing the PAL driver.
+ */
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+const PALConfig pal_default_config =
+{
+ {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
+ {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
+ {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
+ {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
+ {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
+ {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
+ {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
+ {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
+ {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
+};
+#endif
+
+/*
+ * Early initialization code.
+ * This initialization must be performed just after stack setup and before
+ * any other initialization.
+ */
+void __early_init(void) {
+
+ stm32_clock_init();
+}
+
+/*
+ * Board-specific initialization code.
+ */
+void boardInit(void) {
+}
diff --git a/boards/OLIMEX_STM32_P407/board.h b/boards/OLIMEX_STM32_P407/board.h new file mode 100644 index 000000000..9caafed6d --- /dev/null +++ b/boards/OLIMEX_STM32_P407/board.h @@ -0,0 +1,640 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for Olimex STM32-P407 board.
+ * NOTE: Part of JTAG signals are used for other functions, this board can be
+ * used using SWD only.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_OLIMEX_STM32_P407
+#define BOARD_NAME "Olimex STM32-P407"
+
+/*
+ * Ethernet PHY type.
+ */
+#define BOARD_PHY_ID MII_KS8721_ID
+#define BOARD_PHY_RMII
+
+/*
+ * Board frequencies.
+ * NOTE: The LSE crystal is not fitted by default on the board.
+ */
+#define STM32_LSECLK 32768
+#define STM32_HSECLK 25000000
+
+/*
+ * Board voltages.
+ * Required for performance limits calculation.
+ */
+#define STM32_VDD 330
+
+/*
+ * MCU type as defined in the ST header file stm32f4xx.h.
+ */
+#define STM32F4XX
+
+/*
+ * IO pins assignments.
+ */
+#define GPIOA_BUTTON_WKUP 0
+#define GPIOA_ETH_RMII_REF_CLK 1
+#define GPIOA_ETH_RMII_MDIO 2
+#define GPIOA_ETH_RMII_MDINT 3
+#define GPIOA_DCMI_HSYNC 4
+#define GPIOA_LCD_SCK 5
+#define GPIOA_DCMI_PIXCLK 6
+#define GPIOA_ETH_RMII_CRS_DV 7
+#define GPIOA_MCO1 8
+#define GPIOA_OTG_FS_VBUS 9
+#define GPIOA_DCMI_D1 10
+#define GPIOA_OTG_FS_DM 11
+#define GPIOA_OTG_FS_DP 12
+#define GPIOA_SWDIO 13
+#define GPIOA_SWCLK 14
+#define GPIOA_I2S3_WS 15
+
+#define GPIOB_LCD_BL 0
+#define GPIOB_BUZ 1
+#define GPIOB_CAM_ENB 2
+#define GPIOB_I2S3_CK 3
+#define GPIOB_LCD_MISO 4
+#define GPIOB_I2S3_SD 5
+#define GPIOB_DCMI_D5 6
+#define GPIOB_DCMI_VSYNC 7
+#define GPIOB_CAN1_RX 8
+#define GPIOB_CAN1_TX 9
+#define GPIOB_USB_FS_FAULT 10
+#define GPIOB_ETH_RMII_TX_EN 11
+#define GPIOB_OTG_HS_ID 12
+#define GPIOB_OTG_HS_VBUS 13
+#define GPIOB_OTG_HS_DM 14
+#define GPIOB_OTG_HS_DP 15
+
+#define GPIOC_TRIM 0
+#define GPIOC_ETH_RMII_MDC 1
+#define GPIOC_USB_FS_VBUSON 2
+#define GPIOC_LCD_MOSI 3
+#define GPIOC_ETH_RMII_RXD0 4
+#define GPIOC_ETH_RMII_RXD1 5
+#define GPIOC_DCMI_D0_US6_TX 6
+#define GPIOC_I2S3_MCK 7
+#define GPIOC_DCMI_D2 8
+#define GPIOC_DCMI_D3 9
+#define GPIOC_SPI3_SCK 10
+#define GPIOC_SPI3_MISO 11
+#define GPIOC_SPI3_MOSI 12
+#define GPIOC_SWITCH_TAMPER 13
+#define GPIOC_OSC32_IN 14
+#define GPIOC_OSC32_OUT 15
+
+#define GPIOD_USELESS0 0
+#define GPIOD_USELESS1 1
+#define GPIOD_SPI3_CS 2
+#define GPIOD_LCD_RST 3
+#define GPIOD_USELESS4 4
+#define GPIOD_USELESS5 5
+#define GPIOD_LCD_CS 6
+#define GPIOD_USELESS7 7
+#define GPIOD_USART3_TX 8
+#define GPIOD_USART3_RX 9
+#define GPIOD_USELESS10 10
+#define GPIOD_USART3_CTS 11
+#define GPIOD_USART3_RTS 12
+#define GPIOD_USB_HS_FAULT 13
+#define GPIOD_USELESS14 14
+#define GPIOD_USELESS15 15
+
+#define GPIOE_0 0
+#define GPIOE_1 1
+#define GPIOE_TEMP_ALERT 2
+#define GPIOE_USB_HS_VBUSON 3
+#define GPIOE_4 4
+#define GPIOE_5 5
+#define GPIOE_6 6
+#define GPIOE_7 7
+#define GPIOE_8 8
+#define GPIOE_9 9
+#define GPIOE_10 10
+#define GPIOE_11 11
+#define GPIOE_12 12
+#define GPIOE_13 13
+#define GPIOE_14 14
+#define GPIOE_15 15
+
+#define GPIOF_0 0
+#define GPIOF_1 1
+#define GPIOF_2 2
+#define GPIOF_3 3
+#define GPIOF_4 4
+#define GPIOF_5 5
+#define GPIOF_STAT1 6
+#define GPIOF_STAT2 7
+#define GPIOF_STAT3 8
+#define GPIOF_CAM_PWR 9
+#define GPIOF_10 10
+#define GPIOF_CAM_RS 11
+#define GPIOF_12 12
+#define GPIOF_13 13
+#define GPIOF_14 14
+#define GPIOF_15 15
+
+#define GPIOG_0 0
+#define GPIOG_1 1
+#define GPIOG_2 2
+#define GPIOG_3 3
+#define GPIOG_4 4
+#define GPIOG_5 5
+#define GPIOG_RIGHT 6
+#define GPIOG_UP 7
+#define GPIOG_DOWN 8
+#define GPIOG_USART6_RX 9
+#define GPIOG_10 10
+#define GPIOG_LEFT 11
+#define GPIOG_12 12
+#define GPIOG_ETH_RMII_TXD0 13
+#define GPIOG_ETH_RMII_TXD1 14
+#define GPIOG_CENT 15
+
+#define GPIOH_OSC_IN 0
+#define GPIOH_OSC_OUT 1
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n) (0U << ((n) * 2))
+#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2))
+#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2))
+#define PIN_MODE_ANALOG(n) (3U << ((n) * 2))
+#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
+#define PIN_OSPEED_2M(n) (0U << ((n) * 2))
+#define PIN_OSPEED_25M(n) (1U << ((n) * 2))
+#define PIN_OSPEED_50M(n) (2U << ((n) * 2))
+#define PIN_OSPEED_100M(n) (3U << ((n) * 2))
+#define PIN_PUDR_FLOATING(n) (0U << ((n) * 2))
+#define PIN_PUDR_PULLUP(n) (1U << ((n) * 2))
+#define PIN_PUDR_PULLDOWN(n) (2U << ((n) * 2))
+#define PIN_AFIO_AF(n, v) ((v##U) << ((n % 8) * 4))
+
+/*
+ * Port A setup.
+ *
+ * PA0 - GPIOA_BUTTON_WKUP (input floating).
+ * PA1 - GPIOA_ETH_RMII_REF_CLK(alternate 11).
+ * PA2 - GPIOA_ETH_RMII_MDIO (alternate 11).
+ * PA3 - GPIOA_ETH_RMII_MDINT (input floating).
+ * PA4 - GPIOA_DCMI_HSYNC (input pull-up).
+ * PA5 - GPIOA_LCD_SCK (output push-pull).
+ * PA6 - GPIOA_DCMI_PIXCLK (input pull-up).
+ * PA7 - GPIOA_ETH_RMII_CRS_DV (alternate 11).
+ * PA8 - GPIOA_MCO1 (alternate 0).
+ * PA9 - GPIOA_OTG_FS_VBUS (input pull-up).
+ * PA10 - GPIOA_DCMI_D1 (input pull-up).
+ * PA11 - GPIOA_OTG_FS_DM (alternate 10).
+ * PA12 - GPIOA_OTG_FS_DP (alternate 10).
+ * PA13 - GPIOA_SWDIO (alternate 0).
+ * PA14 - GPIOA_SWCLK (alternate 0, pull-down).
+ * PA15 - GPIOA_I2S3_WS (alternate 6).
+ */
+#define VAL_GPIOA_MODER (PIN_MODE_INPUT(GPIOA_BUTTON_WKUP) | \
+ PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_REF_CLK) | \
+ PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_MDIO) | \
+ PIN_MODE_INPUT(GPIOA_ETH_RMII_MDINT) | \
+ PIN_MODE_INPUT(GPIOA_DCMI_HSYNC) | \
+ PIN_MODE_OUTPUT(GPIOA_LCD_SCK) | \
+ PIN_MODE_INPUT(GPIOA_DCMI_PIXCLK) | \
+ PIN_MODE_ALTERNATE(GPIOA_ETH_RMII_CRS_DV) | \
+ PIN_MODE_ALTERNATE(GPIOA_MCO1) | \
+ PIN_MODE_INPUT(GPIOA_OTG_FS_VBUS) | \
+ PIN_MODE_INPUT(GPIOA_DCMI_D1) | \
+ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DM) | \
+ PIN_MODE_ALTERNATE(GPIOA_OTG_FS_DP) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWDIO) | \
+ PIN_MODE_ALTERNATE(GPIOA_SWCLK) | \
+ PIN_MODE_ALTERNATE(GPIOA_I2S3_WS))
+#define VAL_GPIOA_OTYPER 0x00000000
+#define VAL_GPIOA_OSPEEDR 0xFFFFFFFF
+#define VAL_GPIOA_PUPDR (PIN_PUDR_PULLUP(GPIOA_DCMI_HSYNC) | \
+ PIN_PUDR_PULLUP(GPIOA_DCMI_PIXCLK) | \
+ PIN_PUDR_PULLUP(GPIOA_OTG_FS_VBUS) | \
+ PIN_PUDR_PULLUP(GPIOA_DCMI_D1) | \
+ PIN_PUDR_PULLDOWN(GPIOA_SWCLK))
+#define VAL_GPIOA_ODR 0xFFFFFFDF
+#define VAL_GPIOA_AFRL (PIN_AFIO_AF(GPIOA_ETH_RMII_REF_CLK, 11) | \
+ PIN_AFIO_AF(GPIOA_ETH_RMII_MDIO, 11) | \
+ PIN_AFIO_AF(GPIOA_ETH_RMII_CRS_DV, 11))
+#define VAL_GPIOA_AFRH (PIN_AFIO_AF(GPIOA_MCO1, 0) | \
+ PIN_AFIO_AF(GPIOA_OTG_FS_DM, 10) | \
+ PIN_AFIO_AF(GPIOA_OTG_FS_DP, 10) | \
+ PIN_AFIO_AF(GPIOA_SWDIO, 0) | \
+ PIN_AFIO_AF(GPIOA_SWCLK, 0) | \
+ PIN_AFIO_AF(GPIOA_I2S3_WS, 6))
+
+/*
+ * Port B setup.
+ *
+ * PB0 - GPIOB_LCD_BL (output push-pull).
+ * PB1 - GPIOB_BUZ (output push-pull).
+ * PB2 - GPIOB_CAM_ENB (input floating).
+ * PB3 - GPIOB_I2S3_CK (alternate 6).
+ * PB4 - GPIOB_LCD_MISO (input floating).
+ * PB5 - GPIOB_I2S3_SD (alternate 6).
+ * PB6 - GPIOB_DCMI_D5 (input pull-up).
+ * PB7 - GPIOB_DCMI_VSYNC (input pull-up).
+ * PB8 - GPIOB_CAN1_RX (alternate 9).
+ * PB9 - GPIOB_CAN1_TX (alternate 9).
+ * PB10 - GPIOB_USB_FS_FAULT (input floating).
+ * PB11 - GPIOB_ETH_RMII_TX_EN (alternate 11).
+ * PB12 - GPIOB_OTG_HS_ID (alternate 12).
+ * PB13 - GPIOB_OTG_HS_VBUS (input pull-up).
+ * PB14 - GPIOB_OTG_HS_DM (alternate 12).
+ * PB15 - GPIOB_OTG_HS_DP (alternate 12).
+ */
+#define VAL_GPIOB_MODER (PIN_MODE_OUTPUT(GPIOB_LCD_BL) | \
+ PIN_MODE_OUTPUT(GPIOB_BUZ) | \
+ PIN_MODE_INPUT(GPIOB_CAM_ENB) | \
+ PIN_MODE_ALTERNATE(GPIOB_I2S3_CK) | \
+ PIN_MODE_INPUT(GPIOB_LCD_MISO) | \
+ PIN_MODE_ALTERNATE(GPIOB_I2S3_SD) | \
+ PIN_MODE_INPUT(GPIOB_DCMI_D5) | \
+ PIN_MODE_INPUT(GPIOB_DCMI_VSYNC) | \
+ PIN_MODE_ALTERNATE(GPIOB_CAN1_RX) | \
+ PIN_MODE_ALTERNATE(GPIOB_CAN1_TX) | \
+ PIN_MODE_INPUT(GPIOB_USB_FS_FAULT) | \
+ PIN_MODE_ALTERNATE(GPIOB_ETH_RMII_TX_EN) | \
+ PIN_MODE_ALTERNATE(GPIOB_OTG_HS_ID) | \
+ PIN_MODE_INPUT(GPIOB_OTG_HS_VBUS) | \
+ PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DM) | \
+ PIN_MODE_ALTERNATE(GPIOB_OTG_HS_DP))
+#define VAL_GPIOB_OTYPER 0x00000000
+#define VAL_GPIOB_OSPEEDR 0xFFFFFFFF
+#define VAL_GPIOB_PUPDR (PIN_PUDR_PULLUP(GPIOB_DCMI_D5) | \
+ PIN_PUDR_PULLUP(GPIOB_DCMI_VSYNC) | \
+ PIN_PUDR_PULLUP(GPIOB_OTG_HS_VBUS))
+#define VAL_GPIOB_ODR 0xFFFFFFFC
+#define VAL_GPIOB_AFRL (PIN_AFIO_AF(GPIOB_I2S3_CK, 6) | \
+ PIN_AFIO_AF(GPIOB_I2S3_SD, 6))
+#define VAL_GPIOB_AFRH (PIN_AFIO_AF(GPIOB_CAN1_RX, 9) | \
+ PIN_AFIO_AF(GPIOB_CAN1_TX, 9) | \
+ PIN_AFIO_AF(GPIOB_ETH_RMII_TX_EN, 11) | \
+ PIN_AFIO_AF(GPIOB_OTG_HS_ID, 12) | \
+ PIN_AFIO_AF(GPIOB_OTG_HS_DM, 12) | \
+ PIN_AFIO_AF(GPIOB_OTG_HS_DP, 12))
+
+/*
+ * Port C setup.
+ *
+ * PC0 - GPIOC_TRIM (input floating).
+ * PC1 - GPIOC_ETH_RMII_MDC (alternate 11).
+ * PC2 - GPIOC_USB_FS_VBUSON (output push-pull).
+ * PC3 - GPIOC_LCD_MOSI (output push-pull).
+ * PC4 - GPIOC_ETH_RMII_RXD0 (alternate 11).
+ * PC5 - GPIOC_ETH_RMII_RXD1 (alternate 11).
+ * PC6 - GPIOC_DCMI_D0_US6_TX (alternate 8).
+ * PC7 - GPIOC_I2S3_MCK (alternate 6).
+ * PC8 - GPIOC_DCMI_D2 (input pull-up).
+ * PC9 - GPIOC_DCMI_D3 (input pull-up).
+ * PC10 - GPIOC_SPI3_SCK (alternate 6).
+ * PC11 - GPIOC_SPI3_MISO (alternate 6).
+ * PC12 - GPIOC_SPI3_MOSI (alternate 6).
+ * PC13 - GPIOC_SWITCH_TAMPER (input floating).
+ * PC14 - GPIOC_OSC32_IN (input floating).
+ * PC15 - GPIOC_OSC32_OUT (input floating).
+ */
+#define VAL_GPIOC_MODER (PIN_MODE_INPUT(GPIOC_TRIM) | \
+ PIN_MODE_ALTERNATE(GPIOC_ETH_RMII_MDC) | \
+ PIN_MODE_OUTPUT(GPIOC_USB_FS_VBUSON) | \
+ PIN_MODE_OUTPUT(GPIOC_LCD_MOSI) | \
+ PIN_MODE_ALTERNATE(GPIOC_ETH_RMII_RXD0) | \
+ PIN_MODE_ALTERNATE(GPIOC_ETH_RMII_RXD1) | \
+ PIN_MODE_ALTERNATE(GPIOC_DCMI_D0_US6_TX) | \
+ PIN_MODE_ALTERNATE(GPIOC_I2S3_MCK) | \
+ PIN_MODE_INPUT(GPIOC_DCMI_D2) | \
+ PIN_MODE_INPUT(GPIOC_DCMI_D3) | \
+ PIN_MODE_ALTERNATE(GPIOC_SPI3_SCK) | \
+ PIN_MODE_ALTERNATE(GPIOC_SPI3_MISO) | \
+ PIN_MODE_ALTERNATE(GPIOC_SPI3_MOSI) | \
+ PIN_MODE_INPUT(GPIOC_SWITCH_TAMPER) | \
+ PIN_MODE_INPUT(GPIOC_OSC32_IN) | \
+ PIN_MODE_INPUT(GPIOC_OSC32_OUT))
+#define VAL_GPIOC_OTYPER 0x00000000
+#define VAL_GPIOC_OSPEEDR 0xFFFFFFFF
+#define VAL_GPIOC_PUPDR (PIN_PUDR_PULLUP(GPIOC_DCMI_D2) | \
+ PIN_PUDR_PULLUP(GPIOC_DCMI_D3))
+#define VAL_GPIOC_ODR 0xFFFFFFF3
+#define VAL_GPIOC_AFRL (PIN_AFIO_AF(GPIOC_ETH_RMII_MDC, 11) | \
+ PIN_AFIO_AF(GPIOC_ETH_RMII_RXD0, 11) | \
+ PIN_AFIO_AF(GPIOC_ETH_RMII_RXD1, 11) | \
+ PIN_AFIO_AF(GPIOC_DCMI_D0_US6_TX, 8) | \
+ PIN_AFIO_AF(GPIOC_I2S3_MCK, 6))
+#define VAL_GPIOC_AFRH (PIN_AFIO_AF(GPIOC_SPI3_SCK, 6) | \
+ PIN_AFIO_AF(GPIOC_SPI3_MISO, 6) | \
+ PIN_AFIO_AF(GPIOC_SPI3_MOSI, 6))
+
+/*
+ * Port D setup.
+ *
+ * PD0 - GPIOD_USELESS0 (input pull-up).
+ * PD1 - GPIOD_USELESS1 (input pull-up).
+ * PD2 - GPIOD_SPI3_CS (output push-pull).
+ * PD3 - GPIOD_LCD_RST (output push-pull).
+ * PD4 - GPIOD_USELESS4 (input pull-up).
+ * PD5 - GPIOD_USELESS5 (input pull-up).
+ * PD6 - GPIOD_LCD_CS (output push-pull).
+ * PD7 - GPIOD_USELESS7 (input pull-up).
+ * PD8 - GPIOD_USART3_TX (alternate 8).
+ * PD9 - GPIOD_USART3_RX (alternate 8).
+ * PD10 - GPIOD_USELESS10 (input pull-up).
+ * PD11 - GPIOD_USART3_CTS (alternate 8).
+ * PD12 - GPIOD_USART3_RTS (alternate 8).
+ * PD13 - GPIOD_USB_HS_FAULT (input floating).
+ * PD14 - GPIOD_USELESS14 (input pull-up).
+ * PD15 - GPIOD_USELESS15 (input pull-up).
+ */
+#define VAL_GPIOD_MODER (PIN_MODE_INPUT(GPIOD_USELESS0) | \
+ PIN_MODE_INPUT(GPIOD_USELESS1) | \
+ PIN_MODE_OUTPUT(GPIOD_SPI3_CS) | \
+ PIN_MODE_OUTPUT(GPIOD_LCD_RST) | \
+ PIN_MODE_INPUT(GPIOD_USELESS4) | \
+ PIN_MODE_INPUT(GPIOD_USELESS5) | \
+ PIN_MODE_OUTPUT(GPIOD_LCD_CS) | \
+ PIN_MODE_INPUT(GPIOD_USELESS7) | \
+ PIN_MODE_ALTERNATE(GPIOD_USART3_TX) | \
+ PIN_MODE_ALTERNATE(GPIOD_USART3_RX) | \
+ PIN_MODE_INPUT(GPIOD_USELESS10) | \
+ PIN_MODE_ALTERNATE(GPIOD_USART3_CTS) | \
+ PIN_MODE_ALTERNATE(GPIOD_USART3_RTS) | \
+ PIN_MODE_INPUT(GPIOD_USB_HS_FAULT) | \
+ PIN_MODE_INPUT(GPIOD_USELESS14) | \
+ PIN_MODE_INPUT(GPIOD_USELESS15))
+#define VAL_GPIOD_OTYPER 0x00000000
+#define VAL_GPIOD_OSPEEDR 0xFFFFFFFF
+#define VAL_GPIOD_PUPDR (PIN_PUDR_PULLUP(GPIOD_USELESS0) | \
+ PIN_PUDR_PULLUP(GPIOD_USELESS1) | \
+ PIN_PUDR_PULLUP(GPIOD_USELESS4) | \
+ PIN_PUDR_PULLUP(GPIOD_USELESS5) | \
+ PIN_PUDR_PULLUP(GPIOD_USELESS7) | \
+ PIN_PUDR_PULLUP(GPIOD_USELESS10) | \
+ PIN_PUDR_PULLUP(GPIOD_USELESS14) | \
+ PIN_PUDR_PULLUP(GPIOD_USELESS15))
+#define VAL_GPIOD_ODR 0xFFFFFFFF
+#define VAL_GPIOD_AFRL 0x00000000
+#define VAL_GPIOD_AFRH (PIN_AFIO_AF(GPIOD_USART3_TX, 8) | \
+ PIN_AFIO_AF(GPIOD_USART3_RX, 8) | \
+ PIN_AFIO_AF(GPIOD_USART3_CTS, 8) | \
+ PIN_AFIO_AF(GPIOD_USART3_RTS, 8))
+
+/*
+ * Port E setup.
+ *
+ * PE0 - GPIOE_0 (input pull-up).
+ * PE1 - GPIOE_1 (input pull-up).
+ * PE2 - GPIOE_TEMP_ALERT (input floating).
+ * PE3 - GPIOE_USB_HS_VBUSON (output push-pull).
+ * PE4 - GPIOE_4 (input pull-up).
+ * PE5 - GPIOE_5 (input pull-up).
+ * PE6 - GPIOE_6 (input pull-up).
+ * PE7 - GPIOE_7 (input pull-up).
+ * PE8 - GPIOE_8 (input pull-up).
+ * PE9 - GPIOE_9 (input pull-up).
+ * PE10 - GPIOE_10 (input pull-up).
+ * PE11 - GPIOE_11 (input pull-up).
+ * PE12 - GPIOE_12 (input pull-up).
+ * PE13 - GPIOE_13 (input pull-up).
+ * PE14 - GPIOE_14 (input pull-up).
+ * PE15 - GPIOE_15 (input pull-up).
+ */
+#define VAL_GPIOE_MODER (PIN_MODE_INPUT(GPIOE_0) | \
+ PIN_MODE_INPUT(GPIOE_1) | \
+ PIN_MODE_INPUT(GPIOE_TEMP_ALERT) | \
+ PIN_MODE_OUTPUT(GPIOE_USB_HS_VBUSON) | \
+ PIN_MODE_INPUT(GPIOE_4) | \
+ PIN_MODE_INPUT(GPIOE_5) | \
+ PIN_MODE_INPUT(GPIOE_6) | \
+ PIN_MODE_INPUT(GPIOE_7) | \
+ PIN_MODE_INPUT(GPIOE_8) | \
+ PIN_MODE_INPUT(GPIOE_9) | \
+ PIN_MODE_INPUT(GPIOE_10) | \
+ PIN_MODE_INPUT(GPIOE_11) | \
+ PIN_MODE_INPUT(GPIOE_12) | \
+ PIN_MODE_INPUT(GPIOE_13) | \
+ PIN_MODE_INPUT(GPIOE_14) | \
+ PIN_MODE_INPUT(GPIOE_15))
+#define VAL_GPIOE_OTYPER 0x00000000
+#define VAL_GPIOE_OSPEEDR 0xFFFFFFFF
+#define VAL_GPIOE_PUPDR (PIN_PUDR_PULLUP(GPIOE_0) | \
+ PIN_PUDR_PULLUP(GPIOE_1) | \
+ PIN_PUDR_PULLUP(GPIOE_4) | \
+ PIN_PUDR_PULLUP(GPIOE_5) | \
+ PIN_PUDR_PULLUP(GPIOE_6) | \
+ PIN_PUDR_PULLUP(GPIOE_7) | \
+ PIN_PUDR_PULLUP(GPIOE_8) | \
+ PIN_PUDR_PULLUP(GPIOE_9) | \
+ PIN_PUDR_PULLUP(GPIOE_10) | \
+ PIN_PUDR_PULLUP(GPIOE_11) | \
+ PIN_PUDR_PULLUP(GPIOE_12) | \
+ PIN_PUDR_PULLUP(GPIOE_13) | \
+ PIN_PUDR_PULLUP(GPIOE_14) | \
+ PIN_PUDR_PULLUP(GPIOE_15))
+#define VAL_GPIOE_ODR 0xFFFFFFF7
+#define VAL_GPIOE_AFRL 0x00000000
+#define VAL_GPIOE_AFRH 0x00000000
+
+/*
+ * Port F setup.
+ *
+ * PF0 - GPIOF_0 (input pull-up).
+ * PF1 - GPIOF_1 (input pull-up).
+ * PF2 - GPIOF_2 (input pull-up).
+ * PF3 - GPIOF_3 (input pull-up).
+ * PF4 - GPIOF_4 (input pull-up).
+ * PF5 - GPIOF_5 (input pull-up).
+ * PF6 - GPIOF_STAT1 (output push-pull).
+ * PF7 - GPIOF_STAT2 (output push-pull).
+ * PF8 - GPIOF_STAT3 (output push-pull).
+ * PF9 - GPIOF_CAM_PWR (output push-pull).
+ * PF10 - GPIOF_10 (input pull-up).
+ * PF11 - GPIOF_CAM_RS (output push-pull).
+ * PF12 - GPIOF_12 (input pull-up).
+ * PF13 - GPIOF_13 (input pull-up).
+ * PF14 - GPIOF_14 (input pull-up).
+ * PF15 - GPIOF_15 (input pull-up).
+ */
+#define VAL_GPIOF_MODER (PIN_MODE_INPUT(GPIOF_0) | \
+ PIN_MODE_INPUT(GPIOF_1) | \
+ PIN_MODE_INPUT(GPIOF_2) | \
+ PIN_MODE_INPUT(GPIOF_3) | \
+ PIN_MODE_INPUT(GPIOF_4) | \
+ PIN_MODE_INPUT(GPIOF_5) | \
+ PIN_MODE_OUTPUT(GPIOF_STAT1) | \
+ PIN_MODE_OUTPUT(GPIOF_STAT2) | \
+ PIN_MODE_OUTPUT(GPIOF_STAT3) | \
+ PIN_MODE_OUTPUT(GPIOF_CAM_PWR) | \
+ PIN_MODE_INPUT(GPIOF_10) | \
+ PIN_MODE_OUTPUT(GPIOF_CAM_RS) | \
+ PIN_MODE_INPUT(GPIOF_12) | \
+ PIN_MODE_INPUT(GPIOF_13) | \
+ PIN_MODE_INPUT(GPIOF_14) | \
+ PIN_MODE_INPUT(GPIOF_15))
+#define VAL_GPIOF_OTYPER 0x00000000
+#define VAL_GPIOF_OSPEEDR 0xFFFFFFFF
+#define VAL_GPIOF_PUPDR (PIN_PUDR_PULLUP(GPIOF_0) | \
+ PIN_PUDR_PULLUP(GPIOF_1) | \
+ PIN_PUDR_PULLUP(GPIOF_2) | \
+ PIN_PUDR_PULLUP(GPIOF_3) | \
+ PIN_PUDR_PULLUP(GPIOF_4) | \
+ PIN_PUDR_PULLUP(GPIOF_5) | \
+ PIN_PUDR_PULLUP(GPIOF_10) | \
+ PIN_PUDR_PULLUP(GPIOF_12) | \
+ PIN_PUDR_PULLUP(GPIOF_13) | \
+ PIN_PUDR_PULLUP(GPIOF_14) | \
+ PIN_PUDR_PULLUP(GPIOF_15))
+#define VAL_GPIOF_ODR 0xFFFFFC3F
+#define VAL_GPIOF_AFRL 0x00000000
+#define VAL_GPIOF_AFRH 0x00000000
+
+/*
+ * Port G setup.
+ *
+ * PG0 - GPIOG_0 (input pull-up).
+ * PG1 - GPIOG_1 (input pull-up).
+ * PG2 - GPIOG_2 (input pull-up).
+ * PG3 - GPIOG_3 (input pull-up).
+ * PG4 - GPIOG_4 (input pull-up).
+ * PG5 - GPIOG_5 (input pull-up).
+ * PG6 - GPIOG_RIGHT (input floating).
+ * PG7 - GPIOG_UP (input floating).
+ * PG8 - GPIOG_DOWN (input floating).
+ * PG9 - GPIOG_USART6_RX (alternate 8).
+ * PG10 - GPIOG_10 (input pull-up).
+ * PG11 - GPIOG_LEFT (input floating).
+ * PG12 - GPIOG_12 (input pull-up).
+ * PG13 - GPIOG_ETH_RMII_TXD0 (alternate 11).
+ * PG14 - GPIOG_ETH_RMII_TXD1 (alternate 11).
+ * PG15 - GPIOG_CENT (input pull-up).
+ */
+#define VAL_GPIOG_MODER (PIN_MODE_INPUT(GPIOG_0) | \
+ PIN_MODE_INPUT(GPIOG_1) | \
+ PIN_MODE_INPUT(GPIOG_2) | \
+ PIN_MODE_INPUT(GPIOG_3) | \
+ PIN_MODE_INPUT(GPIOG_4) | \
+ PIN_MODE_INPUT(GPIOG_5) | \
+ PIN_MODE_INPUT(GPIOG_RIGHT) | \
+ PIN_MODE_INPUT(GPIOG_UP) | \
+ PIN_MODE_INPUT(GPIOG_DOWN) | \
+ PIN_MODE_ALTERNATE(GPIOG_USART6_RX) | \
+ PIN_MODE_INPUT(GPIOG_10) | \
+ PIN_MODE_INPUT(GPIOG_LEFT) | \
+ PIN_MODE_INPUT(GPIOG_12) | \
+ PIN_MODE_ALTERNATE(GPIOG_ETH_RMII_TXD0) | \
+ PIN_MODE_ALTERNATE(GPIOG_ETH_RMII_TXD1) | \
+ PIN_MODE_INPUT(GPIOG_CENT))
+#define VAL_GPIOG_OTYPER 0x00000000
+#define VAL_GPIOG_OSPEEDR 0xFFFFFFFF
+#define VAL_GPIOG_PUPDR (PIN_PUDR_PULLUP(GPIOG_0) | \
+ PIN_PUDR_PULLUP(GPIOG_1) | \
+ PIN_PUDR_PULLUP(GPIOG_2) | \
+ PIN_PUDR_PULLUP(GPIOG_3) | \
+ PIN_PUDR_PULLUP(GPIOG_4) | \
+ PIN_PUDR_PULLUP(GPIOG_5) | \
+ PIN_PUDR_PULLUP(GPIOG_10) | \
+ PIN_PUDR_PULLUP(GPIOG_12))
+#define VAL_GPIOG_ODR 0xFFFFFFFF
+#define VAL_GPIOG_AFRL 0x00000000
+#define VAL_GPIOG_AFRH (PIN_AFIO_AF(GPIOG_USART6_RX, 8) | \
+ PIN_AFIO_AF(GPIOG_ETH_RMII_TXD0, 11) | \
+ PIN_AFIO_AF(GPIOG_ETH_RMII_TXD1, 11))
+
+/*
+ * Port H setup.
+ * All input with pull-up except:
+ * PH0 - GPIOH_OSC_IN (input floating).
+ * PH1 - GPIOH_OSC_OUT (input floating).
+ */
+#define VAL_GPIOH_MODER (PIN_MODE_INPUT(GPIOH_OSC_IN) | \
+ PIN_MODE_INPUT(GPIOH_OSC_OUT) | \
+ PIN_MODE_INPUT(2) | \
+ PIN_MODE_INPUT(3) | \
+ PIN_MODE_INPUT(4) | \
+ PIN_MODE_INPUT(5) | \
+ PIN_MODE_INPUT(6) | \
+ PIN_MODE_INPUT(7) | \
+ PIN_MODE_INPUT(8) | \
+ PIN_MODE_INPUT(9) | \
+ PIN_MODE_INPUT(10) | \
+ PIN_MODE_INPUT(11) | \
+ PIN_MODE_INPUT(12) | \
+ PIN_MODE_INPUT(13) | \
+ PIN_MODE_INPUT(14) | \
+ PIN_MODE_INPUT(15))
+#define VAL_GPIOH_OTYPER 0x00000000
+#define VAL_GPIOH_OSPEEDR 0xFFFFFFFF
+#define VAL_GPIOH_PUPDR (PIN_PUDR_FLOATING(GPIOH_OSC_IN) | \
+ PIN_PUDR_FLOATING(GPIOH_OSC_OUT) | \
+ PIN_PUDR_PULLUP(2) | \
+ PIN_PUDR_PULLUP(3) | \
+ PIN_PUDR_PULLUP(4) | \
+ PIN_PUDR_PULLUP(5) | \
+ PIN_PUDR_PULLUP(6) | \
+ PIN_PUDR_PULLUP(7) | \
+ PIN_PUDR_PULLUP(8) | \
+ PIN_PUDR_PULLUP(9) | \
+ PIN_PUDR_PULLUP(10) | \
+ PIN_PUDR_PULLUP(11) | \
+ PIN_PUDR_PULLUP(12) | \
+ PIN_PUDR_PULLUP(13) | \
+ PIN_PUDR_PULLUP(14) | \
+ PIN_PUDR_PULLUP(15))
+#define VAL_GPIOH_ODR 0xFFFFFFFF
+#define VAL_GPIOH_AFRL 0x00000000
+#define VAL_GPIOH_AFRH 0x00000000
+
+/*
+ * Port I setup.
+ * All input with pull-up.
+ */
+#define VAL_GPIOI_MODER 0x00000000
+#define VAL_GPIOI_OTYPER 0x00000000
+#define VAL_GPIOI_OSPEEDR 0xFFFFFFFF
+#define VAL_GPIOI_PUPDR 0xFFFFFFFF
+#define VAL_GPIOI_ODR 0xFFFFFFFF
+#define VAL_GPIOI_AFRL 0x00000000
+#define VAL_GPIOI_AFRH 0x00000000
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/boards/OLIMEX_STM32_P407/board.mk b/boards/OLIMEX_STM32_P407/board.mk new file mode 100644 index 000000000..b1e5aafe2 --- /dev/null +++ b/boards/OLIMEX_STM32_P407/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files.
+BOARDSRC = ${CHIBIOS}/boards/OLIMEX_STM32_P407/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS}/boards/OLIMEX_STM32_P407
diff --git a/demos/ARM7-AT91SAM7S-FATFS-GCC/chconf.h b/demos/ARM7-AT91SAM7S-FATFS-GCC/chconf.h index 4115636d6..b1f2cd62c 100644 --- a/demos/ARM7-AT91SAM7S-FATFS-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7S-FATFS-GCC/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h b/demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h index 3648e1cac..fe761053d 100644 --- a/demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7S-FATFS-GCC/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/demos/ARM7-AT91SAM7S-FATFS-GCC/main.c b/demos/ARM7-AT91SAM7S-FATFS-GCC/main.c index 2f4d11b1f..a6285bfef 100644 --- a/demos/ARM7-AT91SAM7S-FATFS-GCC/main.c +++ b/demos/ARM7-AT91SAM7S-FATFS-GCC/main.c @@ -53,7 +53,7 @@ static SPIConfig hs_spicfg = { (MAX_SPI_BITRATE << 8) | AT91C_SPI_NCPHA | AT91C_SPI_BITS_8
};
-/* Low speed SPI configuration (192KHz, NCPHA=1, CPOL=0).*/
+/* Low speed SPI configuration (192kHz, NCPHA=1, CPOL=0).*/
static SPIConfig ls_spicfg = {
NULL,
IOPORT1,
diff --git a/demos/ARM7-AT91SAM7S-GCC/chconf.h b/demos/ARM7-AT91SAM7S-GCC/chconf.h index 4115636d6..b1f2cd62c 100644 --- a/demos/ARM7-AT91SAM7S-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7S-GCC/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/demos/ARM7-AT91SAM7S-GCC/halconf.h b/demos/ARM7-AT91SAM7S-GCC/halconf.h index eb013c9a7..c9b3ad25a 100644 --- a/demos/ARM7-AT91SAM7S-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7S-GCC/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/chconf.h b/demos/ARM7-AT91SAM7X-FATFS-GCC/chconf.h index 4115636d6..b1f2cd62c 100644 --- a/demos/ARM7-AT91SAM7X-FATFS-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h b/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h index 3648e1cac..fe761053d 100644 --- a/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/demos/ARM7-AT91SAM7X-FATFS-GCC/main.c b/demos/ARM7-AT91SAM7X-FATFS-GCC/main.c index b25f98d42..2298b9d62 100644 --- a/demos/ARM7-AT91SAM7X-FATFS-GCC/main.c +++ b/demos/ARM7-AT91SAM7X-FATFS-GCC/main.c @@ -53,7 +53,7 @@ static SPIConfig hs_spicfg = { (MAX_SPI_BITRATE << 8) | AT91C_SPI_NCPHA | AT91C_SPI_BITS_8
};
-/* Low speed SPI configuration (192KHz, NCPHA=1, CPOL=0).*/
+/* Low speed SPI configuration (192kHz, NCPHA=1, CPOL=0).*/
static SPIConfig ls_spicfg = {
NULL,
IOPORT1,
diff --git a/demos/ARM7-AT91SAM7X-GCC/chconf.h b/demos/ARM7-AT91SAM7X-GCC/chconf.h index 4115636d6..b1f2cd62c 100644 --- a/demos/ARM7-AT91SAM7X-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/demos/ARM7-AT91SAM7X-GCC/halconf.h b/demos/ARM7-AT91SAM7X-GCC/halconf.h index eb013c9a7..c9b3ad25a 100644 --- a/demos/ARM7-AT91SAM7X-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-GCC/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h index 4115636d6..b1f2cd62c 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h b/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h index 51658417d..29957bd6d 100644 --- a/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-LWIP-GCC/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h b/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h index 4115636d6..b1f2cd62c 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h b/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h index 51658417d..29957bd6d 100644 --- a/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h +++ b/demos/ARM7-AT91SAM7X-UIP-GCC/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/demos/ARM7-LPC214x-FATFS-GCC/chconf.h b/demos/ARM7-LPC214x-FATFS-GCC/chconf.h index 4115636d6..b1f2cd62c 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/chconf.h +++ b/demos/ARM7-LPC214x-FATFS-GCC/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/demos/ARM7-LPC214x-FATFS-GCC/halconf.h b/demos/ARM7-LPC214x-FATFS-GCC/halconf.h index 3648e1cac..fe761053d 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/halconf.h +++ b/demos/ARM7-LPC214x-FATFS-GCC/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/demos/ARM7-LPC214x-FATFS-GCC/main.c b/demos/ARM7-LPC214x-FATFS-GCC/main.c index 4e4f11363..d541e4899 100644 --- a/demos/ARM7-LPC214x-FATFS-GCC/main.c +++ b/demos/ARM7-LPC214x-FATFS-GCC/main.c @@ -51,7 +51,7 @@ static SPIConfig hs_spicfg = { 2
};
-/* Low speed SPI configuration (281.250KHz, CPHA=0, CPOL=0).*/
+/* Low speed SPI configuration (281.250kHz, CPHA=0, CPOL=0).*/
static SPIConfig ls_spicfg = {
NULL,
IOPORT1,
diff --git a/demos/ARM7-LPC214x-G++/chconf.h b/demos/ARM7-LPC214x-G++/chconf.h index 4115636d6..b1f2cd62c 100644 --- a/demos/ARM7-LPC214x-G++/chconf.h +++ b/demos/ARM7-LPC214x-G++/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/demos/ARM7-LPC214x-G++/halconf.h b/demos/ARM7-LPC214x-G++/halconf.h index eb013c9a7..c9b3ad25a 100644 --- a/demos/ARM7-LPC214x-G++/halconf.h +++ b/demos/ARM7-LPC214x-G++/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/demos/ARM7-LPC214x-GCC/chconf.h b/demos/ARM7-LPC214x-GCC/chconf.h index 4115636d6..b1f2cd62c 100644 --- a/demos/ARM7-LPC214x-GCC/chconf.h +++ b/demos/ARM7-LPC214x-GCC/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/demos/ARM7-LPC214x-GCC/halconf.h b/demos/ARM7-LPC214x-GCC/halconf.h index eb013c9a7..c9b3ad25a 100644 --- a/demos/ARM7-LPC214x-GCC/halconf.h +++ b/demos/ARM7-LPC214x-GCC/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/demos/ARMCM0-LPC1114-LPCXPRESSO/chconf.h b/demos/ARMCM0-LPC1114-LPCXPRESSO/chconf.h index 4115636d6..b1f2cd62c 100644 --- a/demos/ARMCM0-LPC1114-LPCXPRESSO/chconf.h +++ b/demos/ARMCM0-LPC1114-LPCXPRESSO/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/demos/ARMCM0-LPC1114-LPCXPRESSO/halconf.h b/demos/ARMCM0-LPC1114-LPCXPRESSO/halconf.h index 1e289c26a..d3766e0fd 100644 --- a/demos/ARMCM0-LPC1114-LPCXPRESSO/halconf.h +++ b/demos/ARMCM0-LPC1114-LPCXPRESSO/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/demos/ARMCM3-GENERIC-KERNEL/chconf.h b/demos/ARMCM3-GENERIC-KERNEL/chconf.h index 4115636d6..b1f2cd62c 100644 --- a/demos/ARMCM3-GENERIC-KERNEL/chconf.h +++ b/demos/ARMCM3-GENERIC-KERNEL/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/demos/ARMCM3-LPC1343-LPCXPRESSO/chconf.h b/demos/ARMCM3-LPC1343-LPCXPRESSO/chconf.h index 4115636d6..b1f2cd62c 100644 --- a/demos/ARMCM3-LPC1343-LPCXPRESSO/chconf.h +++ b/demos/ARMCM3-LPC1343-LPCXPRESSO/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/demos/ARMCM3-LPC1343-LPCXPRESSO/halconf.h b/demos/ARMCM3-LPC1343-LPCXPRESSO/halconf.h index 1e289c26a..d3766e0fd 100644 --- a/demos/ARMCM3-LPC1343-LPCXPRESSO/halconf.h +++ b/demos/ARMCM3-LPC1343-LPCXPRESSO/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/demos/ARMCM3-LPC1343-OLIMEX/chconf.h b/demos/ARMCM3-LPC1343-OLIMEX/chconf.h index 4115636d6..b1f2cd62c 100644 --- a/demos/ARMCM3-LPC1343-OLIMEX/chconf.h +++ b/demos/ARMCM3-LPC1343-OLIMEX/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/demos/ARMCM3-LPC1343-OLIMEX/halconf.h b/demos/ARMCM3-LPC1343-OLIMEX/halconf.h index 6e472607f..91d295ccf 100644 --- a/demos/ARMCM3-LPC1343-OLIMEX/halconf.h +++ b/demos/ARMCM3-LPC1343-OLIMEX/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/demos/ARMCM3-STM32F100-DISCOVERY/chconf.h b/demos/ARMCM3-STM32F100-DISCOVERY/chconf.h index 4115636d6..b1f2cd62c 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY/chconf.h +++ b/demos/ARMCM3-STM32F100-DISCOVERY/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/demos/ARMCM3-STM32F100-DISCOVERY/halconf.h b/demos/ARMCM3-STM32F100-DISCOVERY/halconf.h index e90833f09..01ebaf505 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY/halconf.h +++ b/demos/ARMCM3-STM32F100-DISCOVERY/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/demos/ARMCM3-STM32F100-DISCOVERY/main.c b/demos/ARMCM3-STM32F100-DISCOVERY/main.c index 6191e271d..3c5079bd7 100644 --- a/demos/ARMCM3-STM32F100-DISCOVERY/main.c +++ b/demos/ARMCM3-STM32F100-DISCOVERY/main.c @@ -64,7 +64,7 @@ static const ADCConversionGroup adcgrpcfg = { * the active state is a logic one.
*/
static PWMConfig pwmcfg = {
- 10000, /* 10KHz PWM clock frequency. */
+ 10000, /* 10kHz PWM clock frequency. */
10000, /* PWM period 1S (in ticks). */
pwmpcb,
{
diff --git a/demos/ARMCM3-STM32F103-FATFS/chconf.h b/demos/ARMCM3-STM32F103-FATFS/chconf.h index 4115636d6..b1f2cd62c 100644 --- a/demos/ARMCM3-STM32F103-FATFS/chconf.h +++ b/demos/ARMCM3-STM32F103-FATFS/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/demos/ARMCM3-STM32F103-FATFS/halconf.h b/demos/ARMCM3-STM32F103-FATFS/halconf.h index 65a2134c0..40d5d756c 100644 --- a/demos/ARMCM3-STM32F103-FATFS/halconf.h +++ b/demos/ARMCM3-STM32F103-FATFS/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/demos/ARMCM3-STM32F103-FATFS/main.c b/demos/ARMCM3-STM32F103-FATFS/main.c index a0176686b..7cb6ca1da 100644 --- a/demos/ARMCM3-STM32F103-FATFS/main.c +++ b/demos/ARMCM3-STM32F103-FATFS/main.c @@ -49,7 +49,7 @@ static bool_t fs_ready = FALSE; /* Maximum speed SPI configuration (18MHz, CPHA=0, CPOL=0, MSb first).*/
static SPIConfig hs_spicfg = {NULL, IOPORT2, GPIOB_SPI2NSS, 0};
-/* Low speed SPI configuration (281.250KHz, CPHA=0, CPOL=0, MSb first).*/
+/* Low speed SPI configuration (281.250kHz, CPHA=0, CPOL=0, MSb first).*/
static SPIConfig ls_spicfg = {NULL, IOPORT2, GPIOB_SPI2NSS,
SPI_CR1_BR_2 | SPI_CR1_BR_1};
diff --git a/demos/ARMCM3-STM32F103-G++/chconf.h b/demos/ARMCM3-STM32F103-G++/chconf.h index 4115636d6..b1f2cd62c 100644 --- a/demos/ARMCM3-STM32F103-G++/chconf.h +++ b/demos/ARMCM3-STM32F103-G++/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/demos/ARMCM3-STM32F103-G++/halconf.h b/demos/ARMCM3-STM32F103-G++/halconf.h index 0751f2a7b..0b2461b61 100644 --- a/demos/ARMCM3-STM32F103-G++/halconf.h +++ b/demos/ARMCM3-STM32F103-G++/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/demos/ARMCM3-STM32F103/chconf.h b/demos/ARMCM3-STM32F103/chconf.h index 4115636d6..b1f2cd62c 100644 --- a/demos/ARMCM3-STM32F103/chconf.h +++ b/demos/ARMCM3-STM32F103/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/demos/ARMCM3-STM32F103/halconf.h b/demos/ARMCM3-STM32F103/halconf.h index 0751f2a7b..0b2461b61 100644 --- a/demos/ARMCM3-STM32F103/halconf.h +++ b/demos/ARMCM3-STM32F103/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/demos/ARMCM3-STM32F103ZG-FATFS/chconf.h b/demos/ARMCM3-STM32F103ZG-FATFS/chconf.h index 4115636d6..b1f2cd62c 100644 --- a/demos/ARMCM3-STM32F103ZG-FATFS/chconf.h +++ b/demos/ARMCM3-STM32F103ZG-FATFS/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/demos/ARMCM3-STM32F103ZG-FATFS/halconf.h b/demos/ARMCM3-STM32F103ZG-FATFS/halconf.h index 5818fbe72..63e37a04e 100644 --- a/demos/ARMCM3-STM32F103ZG-FATFS/halconf.h +++ b/demos/ARMCM3-STM32F103ZG-FATFS/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/demos/ARMCM3-STM32F107-LWIP/chconf.h b/demos/ARMCM3-STM32F107-LWIP/chconf.h index 4115636d6..b1f2cd62c 100644 --- a/demos/ARMCM3-STM32F107-LWIP/chconf.h +++ b/demos/ARMCM3-STM32F107-LWIP/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/demos/ARMCM3-STM32F107-LWIP/halconf.h b/demos/ARMCM3-STM32F107-LWIP/halconf.h index 54062b3c8..ea8a906e9 100644 --- a/demos/ARMCM3-STM32F107-LWIP/halconf.h +++ b/demos/ARMCM3-STM32F107-LWIP/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/demos/ARMCM3-STM32F107/chconf.h b/demos/ARMCM3-STM32F107/chconf.h index 4115636d6..b1f2cd62c 100644 --- a/demos/ARMCM3-STM32F107/chconf.h +++ b/demos/ARMCM3-STM32F107/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/demos/ARMCM3-STM32F107/halconf.h b/demos/ARMCM3-STM32F107/halconf.h index 0751f2a7b..0b2461b61 100644 --- a/demos/ARMCM3-STM32F107/halconf.h +++ b/demos/ARMCM3-STM32F107/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/chconf.h b/demos/ARMCM3-STM32L152-DISCOVERY/chconf.h index 4115636d6..b1f2cd62c 100644 --- a/demos/ARMCM3-STM32L152-DISCOVERY/chconf.h +++ b/demos/ARMCM3-STM32L152-DISCOVERY/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/halconf.h b/demos/ARMCM3-STM32L152-DISCOVERY/halconf.h index e90833f09..01ebaf505 100644 --- a/demos/ARMCM3-STM32L152-DISCOVERY/halconf.h +++ b/demos/ARMCM3-STM32L152-DISCOVERY/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/main.c b/demos/ARMCM3-STM32L152-DISCOVERY/main.c index 00ffb0516..e21b8a311 100644 --- a/demos/ARMCM3-STM32L152-DISCOVERY/main.c +++ b/demos/ARMCM3-STM32L152-DISCOVERY/main.c @@ -67,7 +67,7 @@ static const ADCConversionGroup adcgrpcfg = { * the active state is a logic one.
*/
static PWMConfig pwmcfg = {
- 10000, /* 10KHz PWM clock frequency. */
+ 10000, /* 10kHz PWM clock frequency. */
10000, /* PWM period 1S (in ticks). */
pwmpcb,
{
diff --git a/demos/ARMCM3-STM32L152-DISCOVERY/readme.txt b/demos/ARMCM3-STM32L152-DISCOVERY/readme.txt index ce8ade8fc..931d0ccca 100644 --- a/demos/ARMCM3-STM32L152-DISCOVERY/readme.txt +++ b/demos/ARMCM3-STM32L152-DISCOVERY/readme.txt @@ -1,5 +1,5 @@ *****************************************************************************
-** ChibiOS/RT port for ARM-Cortex-M3 STM32F100xB. **
+** ChibiOS/RT port for ARM-Cortex-M3 STM32L152. **
*****************************************************************************
** TARGET **
diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/Makefile b/demos/ARMCM4-STM32F407-DISCOVERY/Makefile index 975e5f999..0f32eeceb 100644 --- a/demos/ARMCM4-STM32F407-DISCOVERY/Makefile +++ b/demos/ARMCM4-STM32F407-DISCOVERY/Makefile @@ -5,7 +5,7 @@ # Compiler options here.
ifeq ($(USE_OPT),)
- USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 -mhard-float -mfpu=fpv4-sp-d16 -fsingle-precision-constant
+ USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
endif
# C specific options here (added to USE_OPT).
@@ -41,6 +41,12 @@ endif # Architecture or project specific options
#
+# Enables the use of FPU on Cortex-M4.
+# Enable this if you really want to use the STM FWLib.
+ifeq ($(USE_FPU),)
+ USE_FPU = no
+endif
+
# Enable this if you really want to use the STM FWLib.
ifeq ($(USE_FWLIB),)
USE_FWLIB = no
@@ -200,6 +206,13 @@ ULIBS = # End of user defines
##############################################################################
+ifeq ($(USE_FPU),yes)
+ USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant
+ DDEFS += -DCORTEX_USE_FPU=TRUE
+else
+ DDEFS += -DCORTEX_USE_FPU=FALSE
+endif
+
ifeq ($(USE_FWLIB),yes)
include $(CHIBIOS)/ext/stm32lib/stm32lib.mk
CSRC += $(STM32SRC)
diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/chconf.h b/demos/ARMCM4-STM32F407-DISCOVERY/chconf.h index 53f742da0..b1f2cd62c 100644 --- a/demos/ARMCM4-STM32F407-DISCOVERY/chconf.h +++ b/demos/ARMCM4-STM32F407-DISCOVERY/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
@@ -530,8 +530,6 @@ /* Port-specific settings (override port settings defaulted in chcore.h). */
/*===========================================================================*/
-#define CORTEX_USE_FPU FALSE
-
#endif /* _CHCONF_H_ */
/** @} */
diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/halconf.h b/demos/ARMCM4-STM32F407-DISCOVERY/halconf.h index 0a636d3ca..390f4b23e 100644 --- a/demos/ARMCM4-STM32F407-DISCOVERY/halconf.h +++ b/demos/ARMCM4-STM32F407-DISCOVERY/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/main.c b/demos/ARMCM4-STM32F407-DISCOVERY/main.c index f7c7e7fa1..101c1a4df 100644 --- a/demos/ARMCM4-STM32F407-DISCOVERY/main.c +++ b/demos/ARMCM4-STM32F407-DISCOVERY/main.c @@ -66,7 +66,7 @@ static const ADCConversionGroup adcgrpcfg = { * the active state is a logic one.
*/
static PWMConfig pwmcfg = {
- 10000, /* 10KHz PWM clock frequency. */
+ 10000, /* 10kHz PWM clock frequency. */
10000, /* PWM period 1S (in ticks). */
pwmpcb,
{
@@ -231,7 +231,7 @@ int main(void) { /*
* Initializes the ADC driver 1 and enable the thermal sensor.
- * The pin PC0 on the port GPIOC is programmed as analog input.
+ * The pin PC1 on the port GPIOC is programmed as analog input.
*/
adcStart(&ADCD1, NULL);
adcSTM32EnableTSVREFE();
diff --git a/demos/ARMCM4-STM32F407-DISCOVERY/readme.txt b/demos/ARMCM4-STM32F407-DISCOVERY/readme.txt index b82983548..7cd1132ec 100644 --- a/demos/ARMCM4-STM32F407-DISCOVERY/readme.txt +++ b/demos/ARMCM4-STM32F407-DISCOVERY/readme.txt @@ -1,5 +1,5 @@ *****************************************************************************
-** ChibiOS/RT port for ARM-Cortex-M3 STM32F100xB. **
+** ChibiOS/RT port for ARM-Cortex-M4 STM32F407. **
*****************************************************************************
** TARGET **
diff --git a/demos/ARMCM4-STM32F407-LWIP/Makefile b/demos/ARMCM4-STM32F407-LWIP/Makefile new file mode 100644 index 000000000..e8aec516a --- /dev/null +++ b/demos/ARMCM4-STM32F407-LWIP/Makefile @@ -0,0 +1,224 @@ +##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+ USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+ USE_COPT =
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+ USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data
+ifeq ($(USE_LINK_GC),)
+ USE_LINK_GC = yes
+endif
+
+# If enabled, this option allows to compile the application in THUMB mode.
+ifeq ($(USE_THUMB),)
+ USE_THUMB = yes
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+ USE_VERBOSE_COMPILE = no
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Architecture or project specific options
+#
+
+# Enables the use of FPU on Cortex-M4.
+# Enable this if you really want to use the STM FWLib.
+ifeq ($(USE_FPU),)
+ USE_FPU = no
+endif
+
+# Enable this if you really want to use the STM FWLib.
+ifeq ($(USE_FWLIB),)
+ USE_FWLIB = no
+endif
+
+#
+# Architecture or project specific options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = ch
+
+# Imported source files and paths
+CHIBIOS = ../..
+include $(CHIBIOS)/boards/OLIMEX_STM32_P407/board.mk
+include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk
+include $(CHIBIOS)/os/kernel/kernel.mk
+include $(CHIBIOS)/os/various/lwip_bindings/lwip.mk
+include $(CHIBIOS)/test/test.mk
+
+# Define linker script file here
+LDSCRIPT= $(PORTLD)/STM32F407xG.ld
+#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld
+
+# C sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CSRC = $(PORTSRC) \
+ $(KERNSRC) \
+ $(TESTSRC) \
+ $(HALSRC) \
+ $(PLATFORMSRC) \
+ $(BOARDSRC) \
+ $(LWSRC) \
+ $(CHIBIOS)/os/various/evtimer.c \
+ web/web.c main.c
+
+# C++ sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CPPSRC =
+
+# C sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACSRC =
+
+# C++ sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACPPSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCPPSRC =
+
+# List ASM source files here
+ASMSRC = $(PORTASM)
+
+INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
+ $(HALINC) $(PLATFORMINC) $(BOARDINC) $(LWINC) \
+ $(CHIBIOS)/os/various
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+MCU = cortex-m4
+
+#TRGT = arm-elf-
+TRGT = arm-none-eabi-
+CC = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+# runtime support makes code size explode.
+LD = $(TRGT)gcc
+#LD = $(TRGT)g++
+CP = $(TRGT)objcopy
+AS = $(TRGT)gcc -x assembler-with-cpp
+OD = $(TRGT)objdump
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+
+# ARM-specific options here
+AOPT =
+
+# THUMB-specific options here
+TOPT = -mthumb -DTHUMB
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of default section
+#
+
+# List all default C defines here, like -D_DEBUG=1
+DDEFS =
+
+# List all default ASM defines here, like -D_DEBUG=1
+DADEFS =
+
+# List all default directories to look for include files here
+DINCDIR =
+
+# List the default directory to look for the libraries here
+DLIBDIR =
+
+# List all default libraries here
+DLIBS =
+
+#
+# End of default section
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+ifeq ($(USE_FPU),yes)
+ USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant
+ DDEFS += -DCORTEX_USE_FPU=TRUE
+else
+ DDEFS += -DCORTEX_USE_FPU=FALSE
+endif
+
+ifeq ($(USE_FWLIB),yes)
+ include $(CHIBIOS)/ext/stm32lib/stm32lib.mk
+ CSRC += $(STM32SRC)
+ INCDIR += $(STM32INC)
+ USE_OPT += -DUSE_STDPERIPH_DRIVER
+endif
+
+include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk
diff --git a/demos/ARMCM4-STM32F407-LWIP/chconf.h b/demos/ARMCM4-STM32F407-LWIP/chconf.h new file mode 100644 index 000000000..b1f2cd62c --- /dev/null +++ b/demos/ARMCM4-STM32F407-LWIP/chconf.h @@ -0,0 +1,535 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file templates/chconf.h
+ * @brief Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ * contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__)
+#define CH_FREQUENCY 1000
+#endif
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ *
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ */
+#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__)
+#define CH_TIME_QUANTUM 20
+#endif
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_USE_MEMCORE.
+ */
+#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__)
+#define CH_MEMCORE_SIZE 0
+#endif
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread automatically. The application has
+ * then the responsibility to do one of the following:
+ * - Spawn a custom idle thread at priority @p IDLEPRIO.
+ * - Change the main() thread priority to @p IDLEPRIO then enter
+ * an endless loop. In this scenario the @p main() thread acts as
+ * the idle thread.
+ * .
+ * @note Unless an idle thread is spawned the @p main() thread must not
+ * enter a sleep state.
+ */
+#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)
+#define CH_NO_IDLE_THREAD FALSE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__)
+#define CH_OPTIMIZE_SPEED TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__)
+#define CH_USE_REGISTRY TRUE
+#endif
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__)
+#define CH_USE_WAITEXIT TRUE
+#endif
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__)
+#define CH_USE_SEMAPHORES TRUE
+#endif
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special requirements.
+ * @note Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)
+#define CH_USE_SEMAPHORES_PRIORITY FALSE
+#endif
+
+/**
+ * @brief Atomic semaphore API.
+ * @details If enabled then the semaphores the @p chSemSignalWait() API
+ * is included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
+#define CH_USE_SEMSW TRUE
+#endif
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__)
+#define CH_USE_MUTEXES TRUE
+#endif
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_MUTEXES.
+ */
+#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__)
+#define CH_USE_CONDVARS TRUE
+#endif
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_CONDVARS.
+ */
+#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)
+#define CH_USE_CONDVARS_TIMEOUT TRUE
+#endif
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__)
+#define CH_USE_EVENTS TRUE
+#endif
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_EVENTS.
+ */
+#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)
+#define CH_USE_EVENTS_TIMEOUT TRUE
+#endif
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__)
+#define CH_USE_MESSAGES TRUE
+#endif
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special requirements.
+ * @note Requires @p CH_USE_MESSAGES.
+ */
+#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)
+#define CH_USE_MESSAGES_PRIORITY FALSE
+#endif
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__)
+#define CH_USE_MAILBOXES TRUE
+#endif
+
+/**
+ * @brief I/O Queues APIs.
+ * @details If enabled then the I/O queues APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__)
+#define CH_USE_QUEUES TRUE
+#endif
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__)
+#define CH_USE_MEMCORE TRUE
+#endif
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or
+ * @p CH_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__)
+#define CH_USE_HEAP TRUE
+#endif
+
+/**
+ * @brief C-runtime allocator.
+ * @details If enabled the the heap allocator APIs just wrap the C-runtime
+ * @p malloc() and @p free() functions.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_USE_HEAP.
+ * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the
+ * appropriate documentation.
+ */
+#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
+#define CH_USE_MALLOC_HEAP FALSE
+#endif
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__)
+#define CH_USE_MEMPOOLS TRUE
+#endif
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_WAITEXIT.
+ * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS.
+ */
+#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__)
+#define CH_USE_DYNAMIC TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
+#define CH_DBG_SYSTEM_STATE_CHECK FALSE
+#endif
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_CHECKS FALSE
+#endif
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_ASSERTS FALSE
+#endif
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_TRACE FALSE
+#endif
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_STACK_CHECK FALSE
+#endif
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
+#define CH_DBG_FILL_THREADS FALSE
+#endif
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p Thread structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p TRUE.
+ * @note This debug option is defaulted to TRUE because it is required by
+ * some test cases into the test suite.
+ */
+#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
+#define CH_DBG_THREADS_PROFILING TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p Thread structure.
+ */
+#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__)
+#define THREAD_EXT_FIELDS \
+ /* Add threads custom fields here.*/
+#endif
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitly from all
+ * the threads creation APIs.
+ */
+#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
+#define THREAD_EXT_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+#endif
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__)
+#define THREAD_EXT_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+#endif
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__)
+#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* System halt code here.*/ \
+}
+#endif
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__)
+#define IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+#endif
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__)
+#define SYSTEM_TICK_EVENT_HOOK() { \
+ /* System tick event code here.*/ \
+}
+#endif
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
+#define SYSTEM_HALT_HOOK() { \
+ /* System halt code here.*/ \
+}
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/demos/ARMCM4-STM32F407-LWIP/halconf.h b/demos/ARMCM4-STM32F407-LWIP/halconf.h new file mode 100644 index 000000000..ea8a906e9 --- /dev/null +++ b/demos/ARMCM4-STM32F407-LWIP/halconf.h @@ -0,0 +1,342 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file templates/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the TM subsystem.
+ */
+#if !defined(HAL_USE_TM) || defined(__DOXYGEN__)
+#define HAL_USE_TM TRUE
+#endif
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC TRUE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM FALSE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL TRUE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB FALSE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB FALSE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS TRUE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Block size for MMC transfers.
+ */
+#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__)
+#define MMC_SECTOR_SIZE 512
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ * This option is recommended also if the SPI driver does not
+ * use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING TRUE
+#endif
+
+/**
+ * @brief Number of positive insertion queries before generating the
+ * insertion event.
+ */
+#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__)
+#define MMC_POLLING_INTERVAL 10
+#endif
+
+/**
+ * @brief Interval, in milliseconds, between insertion queries.
+ */
+#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__)
+#define MMC_POLLING_DELAY 10
+#endif
+
+/**
+ * @brief Uses the SPI polled API for small data transfers.
+ * @details Polled transfers usually improve performance because it
+ * saves two context switches and interrupt servicing. Note
+ * that this option has no effect on large transfers which
+ * are always performed using DMAs/IRQs.
+ */
+#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__)
+#define MMC_USE_SPI_POLLING TRUE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of initialization attempts before rejecting the card.
+ * @note Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY 100
+#endif
+
+/**
+ * @brief Include support for MMC cards.
+ * @note MMC support is not yet implemented so this option must be kept
+ * at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT FALSE
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ * default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE 38400
+#endif
+
+/**
+ * @brief Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ * buffers depending on the requirements of your application.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE 16
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/demos/ARMCM4-STM32F407-LWIP/lwipopts.h b/demos/ARMCM4-STM32F407-LWIP/lwipopts.h new file mode 100644 index 000000000..1bfbd1de6 --- /dev/null +++ b/demos/ARMCM4-STM32F407-LWIP/lwipopts.h @@ -0,0 +1,2030 @@ +/**
+ * @file
+ *
+ * lwIP Options Configuration
+ */
+
+/*
+ * Copyright (c) 2001-2004 Swedish Institute of Computer Science.
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. The name of the author may not be used to endorse or promote products
+ * derived from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT
+ * SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
+ * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
+ * OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
+ * OF SUCH DAMAGE.
+ *
+ * This file is part of the lwIP TCP/IP stack.
+ *
+ * Author: Adam Dunkels <adam@sics.se>
+ *
+ */
+#ifndef __LWIPOPT_H__
+#define __LWIPOPT_H__
+
+
+/*
+ -----------------------------------------------
+ ---------- Platform specific locking ----------
+ -----------------------------------------------
+*/
+
+/**
+ * SYS_LIGHTWEIGHT_PROT==1: if you want inter-task protection for certain
+ * critical regions during buffer allocation, deallocation and memory
+ * allocation and deallocation.
+ */
+#ifndef SYS_LIGHTWEIGHT_PROT
+#define SYS_LIGHTWEIGHT_PROT 0
+#endif
+
+/**
+ * NO_SYS==1: Provides VERY minimal functionality. Otherwise,
+ * use lwIP facilities.
+ */
+#ifndef NO_SYS
+#define NO_SYS 0
+#endif
+
+/**
+ * NO_SYS_NO_TIMERS==1: Drop support for sys_timeout when NO_SYS==1
+ * Mainly for compatibility to old versions.
+ */
+#ifndef NO_SYS_NO_TIMERS
+#define NO_SYS_NO_TIMERS 0
+#endif
+
+/**
+ * MEMCPY: override this if you have a faster implementation at hand than the
+ * one included in your C library
+ */
+#ifndef MEMCPY
+#define MEMCPY(dst,src,len) memcpy(dst,src,len)
+#endif
+
+/**
+ * SMEMCPY: override this with care! Some compilers (e.g. gcc) can inline a
+ * call to memcpy() if the length is known at compile time and is small.
+ */
+#ifndef SMEMCPY
+#define SMEMCPY(dst,src,len) memcpy(dst,src,len)
+#endif
+
+/*
+ ------------------------------------
+ ---------- Memory options ----------
+ ------------------------------------
+*/
+/**
+ * MEM_LIBC_MALLOC==1: Use malloc/free/realloc provided by your C-library
+ * instead of the lwip internal allocator. Can save code size if you
+ * already use it.
+ */
+#ifndef MEM_LIBC_MALLOC
+#define MEM_LIBC_MALLOC 0
+#endif
+
+/**
+* MEMP_MEM_MALLOC==1: Use mem_malloc/mem_free instead of the lwip pool allocator.
+* Especially useful with MEM_LIBC_MALLOC but handle with care regarding execution
+* speed and usage from interrupts!
+*/
+#ifndef MEMP_MEM_MALLOC
+#define MEMP_MEM_MALLOC 0
+#endif
+
+/**
+ * MEM_ALIGNMENT: should be set to the alignment of the CPU
+ * 4 byte alignment -> #define MEM_ALIGNMENT 4
+ * 2 byte alignment -> #define MEM_ALIGNMENT 2
+ */
+#ifndef MEM_ALIGNMENT
+#define MEM_ALIGNMENT 4
+#endif
+
+/**
+ * MEM_SIZE: the size of the heap memory. If the application will send
+ * a lot of data that needs to be copied, this should be set high.
+ */
+#ifndef MEM_SIZE
+#define MEM_SIZE 1600
+#endif
+
+/**
+ * MEMP_SEPARATE_POOLS: if defined to 1, each pool is placed in its own array.
+ * This can be used to individually change the location of each pool.
+ * Default is one big array for all pools
+ */
+#ifndef MEMP_SEPARATE_POOLS
+#define MEMP_SEPARATE_POOLS 0
+#endif
+
+/**
+ * MEMP_OVERFLOW_CHECK: memp overflow protection reserves a configurable
+ * amount of bytes before and after each memp element in every pool and fills
+ * it with a prominent default value.
+ * MEMP_OVERFLOW_CHECK == 0 no checking
+ * MEMP_OVERFLOW_CHECK == 1 checks each element when it is freed
+ * MEMP_OVERFLOW_CHECK >= 2 checks each element in every pool every time
+ * memp_malloc() or memp_free() is called (useful but slow!)
+ */
+#ifndef MEMP_OVERFLOW_CHECK
+#define MEMP_OVERFLOW_CHECK 0
+#endif
+
+/**
+ * MEMP_SANITY_CHECK==1: run a sanity check after each memp_free() to make
+ * sure that there are no cycles in the linked lists.
+ */
+#ifndef MEMP_SANITY_CHECK
+#define MEMP_SANITY_CHECK 0
+#endif
+
+/**
+ * MEM_USE_POOLS==1: Use an alternative to malloc() by allocating from a set
+ * of memory pools of various sizes. When mem_malloc is called, an element of
+ * the smallest pool that can provide the length needed is returned.
+ * To use this, MEMP_USE_CUSTOM_POOLS also has to be enabled.
+ */
+#ifndef MEM_USE_POOLS
+#define MEM_USE_POOLS 0
+#endif
+
+/**
+ * MEM_USE_POOLS_TRY_BIGGER_POOL==1: if one malloc-pool is empty, try the next
+ * bigger pool - WARNING: THIS MIGHT WASTE MEMORY but it can make a system more
+ * reliable. */
+#ifndef MEM_USE_POOLS_TRY_BIGGER_POOL
+#define MEM_USE_POOLS_TRY_BIGGER_POOL 0
+#endif
+
+/**
+ * MEMP_USE_CUSTOM_POOLS==1: whether to include a user file lwippools.h
+ * that defines additional pools beyond the "standard" ones required
+ * by lwIP. If you set this to 1, you must have lwippools.h in your
+ * inlude path somewhere.
+ */
+#ifndef MEMP_USE_CUSTOM_POOLS
+#define MEMP_USE_CUSTOM_POOLS 0
+#endif
+
+/**
+ * Set this to 1 if you want to free PBUF_RAM pbufs (or call mem_free()) from
+ * interrupt context (or another context that doesn't allow waiting for a
+ * semaphore).
+ * If set to 1, mem_malloc will be protected by a semaphore and SYS_ARCH_PROTECT,
+ * while mem_free will only use SYS_ARCH_PROTECT. mem_malloc SYS_ARCH_UNPROTECTs
+ * with each loop so that mem_free can run.
+ *
+ * ATTENTION: As you can see from the above description, this leads to dis-/
+ * enabling interrupts often, which can be slow! Also, on low memory, mem_malloc
+ * can need longer.
+ *
+ * If you don't want that, at least for NO_SYS=0, you can still use the following
+ * functions to enqueue a deallocation call which then runs in the tcpip_thread
+ * context:
+ * - pbuf_free_callback(p);
+ * - mem_free_callback(m);
+ */
+#ifndef LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT
+#define LWIP_ALLOW_MEM_FREE_FROM_OTHER_CONTEXT 0
+#endif
+
+/*
+ ------------------------------------------------
+ ---------- Internal Memory Pool Sizes ----------
+ ------------------------------------------------
+*/
+/**
+ * MEMP_NUM_PBUF: the number of memp struct pbufs (used for PBUF_ROM and PBUF_REF).
+ * If the application sends a lot of data out of ROM (or other static memory),
+ * this should be set high.
+ */
+#ifndef MEMP_NUM_PBUF
+#define MEMP_NUM_PBUF 16
+#endif
+
+/**
+ * MEMP_NUM_RAW_PCB: Number of raw connection PCBs
+ * (requires the LWIP_RAW option)
+ */
+#ifndef MEMP_NUM_RAW_PCB
+#define MEMP_NUM_RAW_PCB 4
+#endif
+
+/**
+ * MEMP_NUM_UDP_PCB: the number of UDP protocol control blocks. One
+ * per active UDP "connection".
+ * (requires the LWIP_UDP option)
+ */
+#ifndef MEMP_NUM_UDP_PCB
+#define MEMP_NUM_UDP_PCB 4
+#endif
+
+/**
+ * MEMP_NUM_TCP_PCB: the number of simulatenously active TCP connections.
+ * (requires the LWIP_TCP option)
+ */
+#ifndef MEMP_NUM_TCP_PCB
+#define MEMP_NUM_TCP_PCB 5
+#endif
+
+/**
+ * MEMP_NUM_TCP_PCB_LISTEN: the number of listening TCP connections.
+ * (requires the LWIP_TCP option)
+ */
+#ifndef MEMP_NUM_TCP_PCB_LISTEN
+#define MEMP_NUM_TCP_PCB_LISTEN 8
+#endif
+
+/**
+ * MEMP_NUM_TCP_SEG: the number of simultaneously queued TCP segments.
+ * (requires the LWIP_TCP option)
+ */
+#ifndef MEMP_NUM_TCP_SEG
+#define MEMP_NUM_TCP_SEG 16
+#endif
+
+/**
+ * MEMP_NUM_REASSDATA: the number of IP packets simultaneously queued for
+ * reassembly (whole packets, not fragments!)
+ */
+#ifndef MEMP_NUM_REASSDATA
+#define MEMP_NUM_REASSDATA 5
+#endif
+
+/**
+ * MEMP_NUM_FRAG_PBUF: the number of IP fragments simultaneously sent
+ * (fragments, not whole packets!).
+ * This is only used with IP_FRAG_USES_STATIC_BUF==0 and
+ * LWIP_NETIF_TX_SINGLE_PBUF==0 and only has to be > 1 with DMA-enabled MACs
+ * where the packet is not yet sent when netif->output returns.
+ */
+#ifndef MEMP_NUM_FRAG_PBUF
+#define MEMP_NUM_FRAG_PBUF 15
+#endif
+
+/**
+ * MEMP_NUM_ARP_QUEUE: the number of simulateously queued outgoing
+ * packets (pbufs) that are waiting for an ARP request (to resolve
+ * their destination address) to finish.
+ * (requires the ARP_QUEUEING option)
+ */
+#ifndef MEMP_NUM_ARP_QUEUE
+#define MEMP_NUM_ARP_QUEUE 30
+#endif
+
+/**
+ * MEMP_NUM_IGMP_GROUP: The number of multicast groups whose network interfaces
+ * can be members et the same time (one per netif - allsystems group -, plus one
+ * per netif membership).
+ * (requires the LWIP_IGMP option)
+ */
+#ifndef MEMP_NUM_IGMP_GROUP
+#define MEMP_NUM_IGMP_GROUP 8
+#endif
+
+/**
+ * MEMP_NUM_SYS_TIMEOUT: the number of simulateously active timeouts.
+ * (requires NO_SYS==0)
+ */
+#ifndef MEMP_NUM_SYS_TIMEOUT
+#define MEMP_NUM_SYS_TIMEOUT 3
+#endif
+
+/**
+ * MEMP_NUM_NETBUF: the number of struct netbufs.
+ * (only needed if you use the sequential API, like api_lib.c)
+ */
+#ifndef MEMP_NUM_NETBUF
+#define MEMP_NUM_NETBUF 2
+#endif
+
+/**
+ * MEMP_NUM_NETCONN: the number of struct netconns.
+ * (only needed if you use the sequential API, like api_lib.c)
+ */
+#ifndef MEMP_NUM_NETCONN
+#define MEMP_NUM_NETCONN 4
+#endif
+
+/**
+ * MEMP_NUM_TCPIP_MSG_API: the number of struct tcpip_msg, which are used
+ * for callback/timeout API communication.
+ * (only needed if you use tcpip.c)
+ */
+#ifndef MEMP_NUM_TCPIP_MSG_API
+#define MEMP_NUM_TCPIP_MSG_API 8
+#endif
+
+/**
+ * MEMP_NUM_TCPIP_MSG_INPKT: the number of struct tcpip_msg, which are used
+ * for incoming packets.
+ * (only needed if you use tcpip.c)
+ */
+#ifndef MEMP_NUM_TCPIP_MSG_INPKT
+#define MEMP_NUM_TCPIP_MSG_INPKT 8
+#endif
+
+/**
+ * MEMP_NUM_SNMP_NODE: the number of leafs in the SNMP tree.
+ */
+#ifndef MEMP_NUM_SNMP_NODE
+#define MEMP_NUM_SNMP_NODE 50
+#endif
+
+/**
+ * MEMP_NUM_SNMP_ROOTNODE: the number of branches in the SNMP tree.
+ * Every branch has one leaf (MEMP_NUM_SNMP_NODE) at least!
+ */
+#ifndef MEMP_NUM_SNMP_ROOTNODE
+#define MEMP_NUM_SNMP_ROOTNODE 30
+#endif
+
+/**
+ * MEMP_NUM_SNMP_VARBIND: the number of concurrent requests (does not have to
+ * be changed normally) - 2 of these are used per request (1 for input,
+ * 1 for output)
+ */
+#ifndef MEMP_NUM_SNMP_VARBIND
+#define MEMP_NUM_SNMP_VARBIND 2
+#endif
+
+/**
+ * MEMP_NUM_SNMP_VALUE: the number of OID or values concurrently used
+ * (does not have to be changed normally) - 3 of these are used per request
+ * (1 for the value read and 2 for OIDs - input and output)
+ */
+#ifndef MEMP_NUM_SNMP_VALUE
+#define MEMP_NUM_SNMP_VALUE 3
+#endif
+
+/**
+ * MEMP_NUM_NETDB: the number of concurrently running lwip_addrinfo() calls
+ * (before freeing the corresponding memory using lwip_freeaddrinfo()).
+ */
+#ifndef MEMP_NUM_NETDB
+#define MEMP_NUM_NETDB 1
+#endif
+
+/**
+ * MEMP_NUM_LOCALHOSTLIST: the number of host entries in the local host list
+ * if DNS_LOCAL_HOSTLIST_IS_DYNAMIC==1.
+ */
+#ifndef MEMP_NUM_LOCALHOSTLIST
+#define MEMP_NUM_LOCALHOSTLIST 1
+#endif
+
+/**
+ * MEMP_NUM_PPPOE_INTERFACES: the number of concurrently active PPPoE
+ * interfaces (only used with PPPOE_SUPPORT==1)
+ */
+#ifndef MEMP_NUM_PPPOE_INTERFACES
+#define MEMP_NUM_PPPOE_INTERFACES 1
+#endif
+
+/**
+ * PBUF_POOL_SIZE: the number of buffers in the pbuf pool.
+ */
+#ifndef PBUF_POOL_SIZE
+#define PBUF_POOL_SIZE 16
+#endif
+
+/*
+ ---------------------------------
+ ---------- ARP options ----------
+ ---------------------------------
+*/
+/**
+ * LWIP_ARP==1: Enable ARP functionality.
+ */
+#ifndef LWIP_ARP
+#define LWIP_ARP 1
+#endif
+
+/**
+ * ARP_TABLE_SIZE: Number of active MAC-IP address pairs cached.
+ */
+#ifndef ARP_TABLE_SIZE
+#define ARP_TABLE_SIZE 10
+#endif
+
+/**
+ * ARP_QUEUEING==1: Multiple outgoing packets are queued during hardware address
+ * resolution. By default, only the most recent packet is queued per IP address.
+ * This is sufficient for most protocols and mainly reduces TCP connection
+ * startup time. Set this to 1 if you know your application sends more than one
+ * packet in a row to an IP address that is not in the ARP cache.
+ */
+#ifndef ARP_QUEUEING
+#define ARP_QUEUEING 0
+#endif
+
+/**
+ * ETHARP_TRUST_IP_MAC==1: Incoming IP packets cause the ARP table to be
+ * updated with the source MAC and IP addresses supplied in the packet.
+ * You may want to disable this if you do not trust LAN peers to have the
+ * correct addresses, or as a limited approach to attempt to handle
+ * spoofing. If disabled, lwIP will need to make a new ARP request if
+ * the peer is not already in the ARP table, adding a little latency.
+ * The peer *is* in the ARP table if it requested our address before.
+ * Also notice that this slows down input processing of every IP packet!
+ */
+#ifndef ETHARP_TRUST_IP_MAC
+#define ETHARP_TRUST_IP_MAC 0
+#endif
+
+/**
+ * ETHARP_SUPPORT_VLAN==1: support receiving ethernet packets with VLAN header.
+ * Additionally, you can define ETHARP_VLAN_CHECK to an u16_t VLAN ID to check.
+ * If ETHARP_VLAN_CHECK is defined, only VLAN-traffic for this VLAN is accepted.
+ * If ETHARP_VLAN_CHECK is not defined, all traffic is accepted.
+ */
+#ifndef ETHARP_SUPPORT_VLAN
+#define ETHARP_SUPPORT_VLAN 0
+#endif
+
+/** LWIP_ETHERNET==1: enable ethernet support for PPPoE even though ARP
+ * might be disabled
+ */
+#ifndef LWIP_ETHERNET
+#define LWIP_ETHERNET (LWIP_ARP || PPPOE_SUPPORT)
+#endif
+
+/** ETH_PAD_SIZE: number of bytes added before the ethernet header to ensure
+ * alignment of payload after that header. Since the header is 14 bytes long,
+ * without this padding e.g. addresses in the IP header will not be aligned
+ * on a 32-bit boundary, so setting this to 2 can speed up 32-bit-platforms.
+ */
+#ifndef ETH_PAD_SIZE
+#define ETH_PAD_SIZE 0
+#endif
+
+/** ETHARP_SUPPORT_STATIC_ENTRIES==1: enable code to support static ARP table
+ * entries (using etharp_add_static_entry/etharp_remove_static_entry).
+ */
+#ifndef ETHARP_SUPPORT_STATIC_ENTRIES
+#define ETHARP_SUPPORT_STATIC_ENTRIES 0
+#endif
+
+
+/*
+ --------------------------------
+ ---------- IP options ----------
+ --------------------------------
+*/
+/**
+ * IP_FORWARD==1: Enables the ability to forward IP packets across network
+ * interfaces. If you are going to run lwIP on a device with only one network
+ * interface, define this to 0.
+ */
+#ifndef IP_FORWARD
+#define IP_FORWARD 0
+#endif
+
+/**
+ * IP_OPTIONS_ALLOWED: Defines the behavior for IP options.
+ * IP_OPTIONS_ALLOWED==0: All packets with IP options are dropped.
+ * IP_OPTIONS_ALLOWED==1: IP options are allowed (but not parsed).
+ */
+#ifndef IP_OPTIONS_ALLOWED
+#define IP_OPTIONS_ALLOWED 1
+#endif
+
+/**
+ * IP_REASSEMBLY==1: Reassemble incoming fragmented IP packets. Note that
+ * this option does not affect outgoing packet sizes, which can be controlled
+ * via IP_FRAG.
+ */
+#ifndef IP_REASSEMBLY
+#define IP_REASSEMBLY 1
+#endif
+
+/**
+ * IP_FRAG==1: Fragment outgoing IP packets if their size exceeds MTU. Note
+ * that this option does not affect incoming packet sizes, which can be
+ * controlled via IP_REASSEMBLY.
+ */
+#ifndef IP_FRAG
+#define IP_FRAG 1
+#endif
+
+/**
+ * IP_REASS_MAXAGE: Maximum time (in multiples of IP_TMR_INTERVAL - so seconds, normally)
+ * a fragmented IP packet waits for all fragments to arrive. If not all fragments arrived
+ * in this time, the whole packet is discarded.
+ */
+#ifndef IP_REASS_MAXAGE
+#define IP_REASS_MAXAGE 3
+#endif
+
+/**
+ * IP_REASS_MAX_PBUFS: Total maximum amount of pbufs waiting to be reassembled.
+ * Since the received pbufs are enqueued, be sure to configure
+ * PBUF_POOL_SIZE > IP_REASS_MAX_PBUFS so that the stack is still able to receive
+ * packets even if the maximum amount of fragments is enqueued for reassembly!
+ */
+#ifndef IP_REASS_MAX_PBUFS
+#define IP_REASS_MAX_PBUFS 10
+#endif
+
+/**
+ * IP_FRAG_USES_STATIC_BUF==1: Use a static MTU-sized buffer for IP
+ * fragmentation. Otherwise pbufs are allocated and reference the original
+ * packet data to be fragmented (or with LWIP_NETIF_TX_SINGLE_PBUF==1,
+ * new PBUF_RAM pbufs are used for fragments).
+ * ATTENTION: IP_FRAG_USES_STATIC_BUF==1 may not be used for DMA-enabled MACs!
+ */
+#ifndef IP_FRAG_USES_STATIC_BUF
+#define IP_FRAG_USES_STATIC_BUF 0
+#endif
+
+/**
+ * IP_FRAG_MAX_MTU: Assumed max MTU on any interface for IP frag buffer
+ * (requires IP_FRAG_USES_STATIC_BUF==1)
+ */
+#if IP_FRAG_USES_STATIC_BUF && !defined(IP_FRAG_MAX_MTU)
+#define IP_FRAG_MAX_MTU 1500
+#endif
+
+/**
+ * IP_DEFAULT_TTL: Default value for Time-To-Live used by transport layers.
+ */
+#ifndef IP_DEFAULT_TTL
+#define IP_DEFAULT_TTL 255
+#endif
+
+/**
+ * IP_SOF_BROADCAST=1: Use the SOF_BROADCAST field to enable broadcast
+ * filter per pcb on udp and raw send operations. To enable broadcast filter
+ * on recv operations, you also have to set IP_SOF_BROADCAST_RECV=1.
+ */
+#ifndef IP_SOF_BROADCAST
+#define IP_SOF_BROADCAST 0
+#endif
+
+/**
+ * IP_SOF_BROADCAST_RECV (requires IP_SOF_BROADCAST=1) enable the broadcast
+ * filter on recv operations.
+ */
+#ifndef IP_SOF_BROADCAST_RECV
+#define IP_SOF_BROADCAST_RECV 0
+#endif
+
+/*
+ ----------------------------------
+ ---------- ICMP options ----------
+ ----------------------------------
+*/
+/**
+ * LWIP_ICMP==1: Enable ICMP module inside the IP stack.
+ * Be careful, disable that make your product non-compliant to RFC1122
+ */
+#ifndef LWIP_ICMP
+#define LWIP_ICMP 1
+#endif
+
+/**
+ * ICMP_TTL: Default value for Time-To-Live used by ICMP packets.
+ */
+#ifndef ICMP_TTL
+#define ICMP_TTL (IP_DEFAULT_TTL)
+#endif
+
+/**
+ * LWIP_BROADCAST_PING==1: respond to broadcast pings (default is unicast only)
+ */
+#ifndef LWIP_BROADCAST_PING
+#define LWIP_BROADCAST_PING 0
+#endif
+
+/**
+ * LWIP_MULTICAST_PING==1: respond to multicast pings (default is unicast only)
+ */
+#ifndef LWIP_MULTICAST_PING
+#define LWIP_MULTICAST_PING 0
+#endif
+
+/*
+ ---------------------------------
+ ---------- RAW options ----------
+ ---------------------------------
+*/
+/**
+ * LWIP_RAW==1: Enable application layer to hook into the IP layer itself.
+ */
+#ifndef LWIP_RAW
+#define LWIP_RAW 1
+#endif
+
+/**
+ * LWIP_RAW==1: Enable application layer to hook into the IP layer itself.
+ */
+#ifndef RAW_TTL
+#define RAW_TTL (IP_DEFAULT_TTL)
+#endif
+
+/*
+ ----------------------------------
+ ---------- DHCP options ----------
+ ----------------------------------
+*/
+/**
+ * LWIP_DHCP==1: Enable DHCP module.
+ */
+#ifndef LWIP_DHCP
+#define LWIP_DHCP 0
+#endif
+
+/**
+ * DHCP_DOES_ARP_CHECK==1: Do an ARP check on the offered address.
+ */
+#ifndef DHCP_DOES_ARP_CHECK
+#define DHCP_DOES_ARP_CHECK ((LWIP_DHCP) && (LWIP_ARP))
+#endif
+
+/*
+ ------------------------------------
+ ---------- AUTOIP options ----------
+ ------------------------------------
+*/
+/**
+ * LWIP_AUTOIP==1: Enable AUTOIP module.
+ */
+#ifndef LWIP_AUTOIP
+#define LWIP_AUTOIP 0
+#endif
+
+/**
+ * LWIP_DHCP_AUTOIP_COOP==1: Allow DHCP and AUTOIP to be both enabled on
+ * the same interface at the same time.
+ */
+#ifndef LWIP_DHCP_AUTOIP_COOP
+#define LWIP_DHCP_AUTOIP_COOP 0
+#endif
+
+/**
+ * LWIP_DHCP_AUTOIP_COOP_TRIES: Set to the number of DHCP DISCOVER probes
+ * that should be sent before falling back on AUTOIP. This can be set
+ * as low as 1 to get an AutoIP address very quickly, but you should
+ * be prepared to handle a changing IP address when DHCP overrides
+ * AutoIP.
+ */
+#ifndef LWIP_DHCP_AUTOIP_COOP_TRIES
+#define LWIP_DHCP_AUTOIP_COOP_TRIES 9
+#endif
+
+/*
+ ----------------------------------
+ ---------- SNMP options ----------
+ ----------------------------------
+*/
+/**
+ * LWIP_SNMP==1: Turn on SNMP module. UDP must be available for SNMP
+ * transport.
+ */
+#ifndef LWIP_SNMP
+#define LWIP_SNMP 0
+#endif
+
+/**
+ * SNMP_CONCURRENT_REQUESTS: Number of concurrent requests the module will
+ * allow. At least one request buffer is required.
+ * Does not have to be changed unless external MIBs answer request asynchronously
+ */
+#ifndef SNMP_CONCURRENT_REQUESTS
+#define SNMP_CONCURRENT_REQUESTS 1
+#endif
+
+/**
+ * SNMP_TRAP_DESTINATIONS: Number of trap destinations. At least one trap
+ * destination is required
+ */
+#ifndef SNMP_TRAP_DESTINATIONS
+#define SNMP_TRAP_DESTINATIONS 1
+#endif
+
+/**
+ * SNMP_PRIVATE_MIB:
+ * When using a private MIB, you have to create a file 'private_mib.h' that contains
+ * a 'struct mib_array_node mib_private' which contains your MIB.
+ */
+#ifndef SNMP_PRIVATE_MIB
+#define SNMP_PRIVATE_MIB 0
+#endif
+
+/**
+ * Only allow SNMP write actions that are 'safe' (e.g. disabeling netifs is not
+ * a safe action and disabled when SNMP_SAFE_REQUESTS = 1).
+ * Unsafe requests are disabled by default!
+ */
+#ifndef SNMP_SAFE_REQUESTS
+#define SNMP_SAFE_REQUESTS 1
+#endif
+
+/**
+ * The maximum length of strings used. This affects the size of
+ * MEMP_SNMP_VALUE elements.
+ */
+#ifndef SNMP_MAX_OCTET_STRING_LEN
+#define SNMP_MAX_OCTET_STRING_LEN 127
+#endif
+
+/**
+ * The maximum depth of the SNMP tree.
+ * With private MIBs enabled, this depends on your MIB!
+ * This affects the size of MEMP_SNMP_VALUE elements.
+ */
+#ifndef SNMP_MAX_TREE_DEPTH
+#define SNMP_MAX_TREE_DEPTH 15
+#endif
+
+/**
+ * The size of the MEMP_SNMP_VALUE elements, normally calculated from
+ * SNMP_MAX_OCTET_STRING_LEN and SNMP_MAX_TREE_DEPTH.
+ */
+#ifndef SNMP_MAX_VALUE_SIZE
+#define SNMP_MAX_VALUE_SIZE LWIP_MAX((SNMP_MAX_OCTET_STRING_LEN)+1, sizeof(s32_t)*(SNMP_MAX_TREE_DEPTH))
+#endif
+
+/*
+ ----------------------------------
+ ---------- IGMP options ----------
+ ----------------------------------
+*/
+/**
+ * LWIP_IGMP==1: Turn on IGMP module.
+ */
+#ifndef LWIP_IGMP
+#define LWIP_IGMP 0
+#endif
+
+/*
+ ----------------------------------
+ ---------- DNS options -----------
+ ----------------------------------
+*/
+/**
+ * LWIP_DNS==1: Turn on DNS module. UDP must be available for DNS
+ * transport.
+ */
+#ifndef LWIP_DNS
+#define LWIP_DNS 0
+#endif
+
+/** DNS maximum number of entries to maintain locally. */
+#ifndef DNS_TABLE_SIZE
+#define DNS_TABLE_SIZE 4
+#endif
+
+/** DNS maximum host name length supported in the name table. */
+#ifndef DNS_MAX_NAME_LENGTH
+#define DNS_MAX_NAME_LENGTH 256
+#endif
+
+/** The maximum of DNS servers */
+#ifndef DNS_MAX_SERVERS
+#define DNS_MAX_SERVERS 2
+#endif
+
+/** DNS do a name checking between the query and the response. */
+#ifndef DNS_DOES_NAME_CHECK
+#define DNS_DOES_NAME_CHECK 1
+#endif
+
+/** DNS message max. size. Default value is RFC compliant. */
+#ifndef DNS_MSG_SIZE
+#define DNS_MSG_SIZE 512
+#endif
+
+/** DNS_LOCAL_HOSTLIST: Implements a local host-to-address list. If enabled,
+ * you have to define
+ * #define DNS_LOCAL_HOSTLIST_INIT {{"host1", 0x123}, {"host2", 0x234}}
+ * (an array of structs name/address, where address is an u32_t in network
+ * byte order).
+ *
+ * Instead, you can also use an external function:
+ * #define DNS_LOOKUP_LOCAL_EXTERN(x) extern u32_t my_lookup_function(const char *name)
+ * that returns the IP address or INADDR_NONE if not found.
+ */
+#ifndef DNS_LOCAL_HOSTLIST
+#define DNS_LOCAL_HOSTLIST 0
+#endif /* DNS_LOCAL_HOSTLIST */
+
+/** If this is turned on, the local host-list can be dynamically changed
+ * at runtime. */
+#ifndef DNS_LOCAL_HOSTLIST_IS_DYNAMIC
+#define DNS_LOCAL_HOSTLIST_IS_DYNAMIC 0
+#endif /* DNS_LOCAL_HOSTLIST_IS_DYNAMIC */
+
+/*
+ ---------------------------------
+ ---------- UDP options ----------
+ ---------------------------------
+*/
+/**
+ * LWIP_UDP==1: Turn on UDP.
+ */
+#ifndef LWIP_UDP
+#define LWIP_UDP 1
+#endif
+
+/**
+ * LWIP_UDPLITE==1: Turn on UDP-Lite. (Requires LWIP_UDP)
+ */
+#ifndef LWIP_UDPLITE
+#define LWIP_UDPLITE 0
+#endif
+
+/**
+ * UDP_TTL: Default Time-To-Live value.
+ */
+#ifndef UDP_TTL
+#define UDP_TTL (IP_DEFAULT_TTL)
+#endif
+
+/**
+ * LWIP_NETBUF_RECVINFO==1: append destination addr and port to every netbuf.
+ */
+#ifndef LWIP_NETBUF_RECVINFO
+#define LWIP_NETBUF_RECVINFO 0
+#endif
+
+/*
+ ---------------------------------
+ ---------- TCP options ----------
+ ---------------------------------
+*/
+/**
+ * LWIP_TCP==1: Turn on TCP.
+ */
+#ifndef LWIP_TCP
+#define LWIP_TCP 1
+#endif
+
+/**
+ * TCP_TTL: Default Time-To-Live value.
+ */
+#ifndef TCP_TTL
+#define TCP_TTL (IP_DEFAULT_TTL)
+#endif
+
+/**
+ * TCP_WND: The size of a TCP window. This must be at least
+ * (2 * TCP_MSS) for things to work well
+ */
+#ifndef TCP_WND
+#define TCP_WND (4 * TCP_MSS)
+#endif
+
+/**
+ * TCP_MAXRTX: Maximum number of retransmissions of data segments.
+ */
+#ifndef TCP_MAXRTX
+#define TCP_MAXRTX 12
+#endif
+
+/**
+ * TCP_SYNMAXRTX: Maximum number of retransmissions of SYN segments.
+ */
+#ifndef TCP_SYNMAXRTX
+#define TCP_SYNMAXRTX 6
+#endif
+
+/**
+ * TCP_QUEUE_OOSEQ==1: TCP will queue segments that arrive out of order.
+ * Define to 0 if your device is low on memory.
+ */
+#ifndef TCP_QUEUE_OOSEQ
+#define TCP_QUEUE_OOSEQ (LWIP_TCP)
+#endif
+
+/**
+ * TCP_MSS: TCP Maximum segment size. (default is 536, a conservative default,
+ * you might want to increase this.)
+ * For the receive side, this MSS is advertised to the remote side
+ * when opening a connection. For the transmit size, this MSS sets
+ * an upper limit on the MSS advertised by the remote host.
+ */
+#ifndef TCP_MSS
+#define TCP_MSS 536
+#endif
+
+/**
+ * TCP_CALCULATE_EFF_SEND_MSS: "The maximum size of a segment that TCP really
+ * sends, the 'effective send MSS,' MUST be the smaller of the send MSS (which
+ * reflects the available reassembly buffer size at the remote host) and the
+ * largest size permitted by the IP layer" (RFC 1122)
+ * Setting this to 1 enables code that checks TCP_MSS against the MTU of the
+ * netif used for a connection and limits the MSS if it would be too big otherwise.
+ */
+#ifndef TCP_CALCULATE_EFF_SEND_MSS
+#define TCP_CALCULATE_EFF_SEND_MSS 1
+#endif
+
+
+/**
+ * TCP_SND_BUF: TCP sender buffer space (bytes).
+ */
+#ifndef TCP_SND_BUF
+#define TCP_SND_BUF 256
+#endif
+
+/**
+ * TCP_SND_QUEUELEN: TCP sender buffer space (pbufs). This must be at least
+ * as much as (2 * TCP_SND_BUF/TCP_MSS) for things to work.
+ */
+#ifndef TCP_SND_QUEUELEN
+#define TCP_SND_QUEUELEN ((4 * (TCP_SND_BUF) + (TCP_MSS - 1))/(TCP_MSS))
+#endif
+
+/**
+ * TCP_SNDLOWAT: TCP writable space (bytes). This must be less than
+ * TCP_SND_BUF. It is the amount of space which must be available in the
+ * TCP snd_buf for select to return writable (combined with TCP_SNDQUEUELOWAT).
+ */
+#ifndef TCP_SNDLOWAT
+#define TCP_SNDLOWAT ((TCP_SND_BUF)/2)
+#endif
+
+/**
+ * TCP_SNDQUEUELOWAT: TCP writable bufs (pbuf count). This must be grater
+ * than TCP_SND_QUEUELEN. If the number of pbufs queued on a pcb drops below
+ * this number, select returns writable (combined with TCP_SNDLOWAT).
+ */
+#ifndef TCP_SNDQUEUELOWAT
+#define TCP_SNDQUEUELOWAT ((TCP_SND_QUEUELEN)/2)
+#endif
+
+/**
+ * TCP_LISTEN_BACKLOG: Enable the backlog option for tcp listen pcb.
+ */
+#ifndef TCP_LISTEN_BACKLOG
+#define TCP_LISTEN_BACKLOG 0
+#endif
+
+/**
+ * The maximum allowed backlog for TCP listen netconns.
+ * This backlog is used unless another is explicitly specified.
+ * 0xff is the maximum (u8_t).
+ */
+#ifndef TCP_DEFAULT_LISTEN_BACKLOG
+#define TCP_DEFAULT_LISTEN_BACKLOG 0xff
+#endif
+
+/**
+ * TCP_OVERSIZE: The maximum number of bytes that tcp_write may
+ * allocate ahead of time in an attempt to create shorter pbuf chains
+ * for transmission. The meaningful range is 0 to TCP_MSS. Some
+ * suggested values are:
+ *
+ * 0: Disable oversized allocation. Each tcp_write() allocates a new
+ pbuf (old behaviour).
+ * 1: Allocate size-aligned pbufs with minimal excess. Use this if your
+ * scatter-gather DMA requires aligned fragments.
+ * 128: Limit the pbuf/memory overhead to 20%.
+ * TCP_MSS: Try to create unfragmented TCP packets.
+ * TCP_MSS/4: Try to create 4 fragments or less per TCP packet.
+ */
+#ifndef TCP_OVERSIZE
+#define TCP_OVERSIZE TCP_MSS
+#endif
+
+/**
+ * LWIP_TCP_TIMESTAMPS==1: support the TCP timestamp option.
+ */
+#ifndef LWIP_TCP_TIMESTAMPS
+#define LWIP_TCP_TIMESTAMPS 0
+#endif
+
+/**
+ * TCP_WND_UPDATE_THRESHOLD: difference in window to trigger an
+ * explicit window update
+ */
+#ifndef TCP_WND_UPDATE_THRESHOLD
+#define TCP_WND_UPDATE_THRESHOLD (TCP_WND / 4)
+#endif
+
+/**
+ * LWIP_EVENT_API and LWIP_CALLBACK_API: Only one of these should be set to 1.
+ * LWIP_EVENT_API==1: The user defines lwip_tcp_event() to receive all
+ * events (accept, sent, etc) that happen in the system.
+ * LWIP_CALLBACK_API==1: The PCB callback function is called directly
+ * for the event.
+ */
+//#define LWIP_EVENT_API
+
+/*
+ ----------------------------------
+ ---------- Pbuf options ----------
+ ----------------------------------
+*/
+/**
+ * PBUF_LINK_HLEN: the number of bytes that should be allocated for a
+ * link level header. The default is 14, the standard value for
+ * Ethernet.
+ */
+#ifndef PBUF_LINK_HLEN
+#define PBUF_LINK_HLEN (14 + ETH_PAD_SIZE)
+#endif
+
+/**
+ * PBUF_POOL_BUFSIZE: the size of each pbuf in the pbuf pool. The default is
+ * designed to accomodate single full size TCP frame in one pbuf, including
+ * TCP_MSS, IP header, and link header.
+ */
+#ifndef PBUF_POOL_BUFSIZE
+#define PBUF_POOL_BUFSIZE LWIP_MEM_ALIGN_SIZE(TCP_MSS+40+PBUF_LINK_HLEN)
+#endif
+
+/*
+ ------------------------------------------------
+ ---------- Network Interfaces options ----------
+ ------------------------------------------------
+*/
+/**
+ * LWIP_NETIF_HOSTNAME==1: use DHCP_OPTION_HOSTNAME with netif's hostname
+ * field.
+ */
+#ifndef LWIP_NETIF_HOSTNAME
+#define LWIP_NETIF_HOSTNAME 0
+#endif
+
+/**
+ * LWIP_NETIF_API==1: Support netif api (in netifapi.c)
+ */
+#ifndef LWIP_NETIF_API
+#define LWIP_NETIF_API 0
+#endif
+
+/**
+ * LWIP_NETIF_STATUS_CALLBACK==1: Support a callback function whenever an interface
+ * changes its up/down status (i.e., due to DHCP IP acquistion)
+ */
+#ifndef LWIP_NETIF_STATUS_CALLBACK
+#define LWIP_NETIF_STATUS_CALLBACK 0
+#endif
+
+/**
+ * LWIP_NETIF_LINK_CALLBACK==1: Support a callback function from an interface
+ * whenever the link changes (i.e., link down)
+ */
+#ifndef LWIP_NETIF_LINK_CALLBACK
+#define LWIP_NETIF_LINK_CALLBACK 0
+#endif
+
+/**
+ * LWIP_NETIF_HWADDRHINT==1: Cache link-layer-address hints (e.g. table
+ * indices) in struct netif. TCP and UDP can make use of this to prevent
+ * scanning the ARP table for every sent packet. While this is faster for big
+ * ARP tables or many concurrent connections, it might be counterproductive
+ * if you have a tiny ARP table or if there never are concurrent connections.
+ */
+#ifndef LWIP_NETIF_HWADDRHINT
+#define LWIP_NETIF_HWADDRHINT 0
+#endif
+
+/**
+ * LWIP_NETIF_LOOPBACK==1: Support sending packets with a destination IP
+ * address equal to the netif IP address, looping them back up the stack.
+ */
+#ifndef LWIP_NETIF_LOOPBACK
+#define LWIP_NETIF_LOOPBACK 0
+#endif
+
+/**
+ * LWIP_LOOPBACK_MAX_PBUFS: Maximum number of pbufs on queue for loopback
+ * sending for each netif (0 = disabled)
+ */
+#ifndef LWIP_LOOPBACK_MAX_PBUFS
+#define LWIP_LOOPBACK_MAX_PBUFS 0
+#endif
+
+/**
+ * LWIP_NETIF_LOOPBACK_MULTITHREADING: Indicates whether threading is enabled in
+ * the system, as netifs must change how they behave depending on this setting
+ * for the LWIP_NETIF_LOOPBACK option to work.
+ * Setting this is needed to avoid reentering non-reentrant functions like
+ * tcp_input().
+ * LWIP_NETIF_LOOPBACK_MULTITHREADING==1: Indicates that the user is using a
+ * multithreaded environment like tcpip.c. In this case, netif->input()
+ * is called directly.
+ * LWIP_NETIF_LOOPBACK_MULTITHREADING==0: Indicates a polling (or NO_SYS) setup.
+ * The packets are put on a list and netif_poll() must be called in
+ * the main application loop.
+ */
+#ifndef LWIP_NETIF_LOOPBACK_MULTITHREADING
+#define LWIP_NETIF_LOOPBACK_MULTITHREADING (!NO_SYS)
+#endif
+
+/**
+ * LWIP_NETIF_TX_SINGLE_PBUF: if this is set to 1, lwIP tries to put all data
+ * to be sent into one single pbuf. This is for compatibility with DMA-enabled
+ * MACs that do not support scatter-gather.
+ * Beware that this might involve CPU-memcpy before transmitting that would not
+ * be needed without this flag! Use this only if you need to!
+ *
+ * @todo: TCP and IP-frag do not work with this, yet:
+ */
+#ifndef LWIP_NETIF_TX_SINGLE_PBUF
+#define LWIP_NETIF_TX_SINGLE_PBUF 0
+#endif /* LWIP_NETIF_TX_SINGLE_PBUF */
+
+/*
+ ------------------------------------
+ ---------- LOOPIF options ----------
+ ------------------------------------
+*/
+/**
+ * LWIP_HAVE_LOOPIF==1: Support loop interface (127.0.0.1) and loopif.c
+ */
+#ifndef LWIP_HAVE_LOOPIF
+#define LWIP_HAVE_LOOPIF 0
+#endif
+
+/*
+ ------------------------------------
+ ---------- SLIPIF options ----------
+ ------------------------------------
+*/
+/**
+ * LWIP_HAVE_SLIPIF==1: Support slip interface and slipif.c
+ */
+#ifndef LWIP_HAVE_SLIPIF
+#define LWIP_HAVE_SLIPIF 0
+#endif
+
+/*
+ ------------------------------------
+ ---------- Thread options ----------
+ ------------------------------------
+*/
+/**
+ * TCPIP_THREAD_NAME: The name assigned to the main tcpip thread.
+ */
+#ifndef TCPIP_THREAD_NAME
+#define TCPIP_THREAD_NAME "tcpip_thread"
+#endif
+
+/**
+ * TCPIP_THREAD_STACKSIZE: The stack size used by the main tcpip thread.
+ * The stack size value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef TCPIP_THREAD_STACKSIZE
+#define TCPIP_THREAD_STACKSIZE 1024
+#endif
+
+/**
+ * TCPIP_THREAD_PRIO: The priority assigned to the main tcpip thread.
+ * The priority value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef TCPIP_THREAD_PRIO
+#define TCPIP_THREAD_PRIO (LOWPRIO + 1)
+#endif
+
+/**
+ * TCPIP_MBOX_SIZE: The mailbox size for the tcpip thread messages
+ * The queue size value itself is platform-dependent, but is passed to
+ * sys_mbox_new() when tcpip_init is called.
+ */
+#ifndef TCPIP_MBOX_SIZE
+#define TCPIP_MBOX_SIZE 4
+#endif
+
+/**
+ * SLIPIF_THREAD_NAME: The name assigned to the slipif_loop thread.
+ */
+#ifndef SLIPIF_THREAD_NAME
+#define SLIPIF_THREAD_NAME "slipif_loop"
+#endif
+
+/**
+ * SLIP_THREAD_STACKSIZE: The stack size used by the slipif_loop thread.
+ * The stack size value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef SLIPIF_THREAD_STACKSIZE
+#define SLIPIF_THREAD_STACKSIZE 1024
+#endif
+
+/**
+ * SLIPIF_THREAD_PRIO: The priority assigned to the slipif_loop thread.
+ * The priority value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef SLIPIF_THREAD_PRIO
+#define SLIPIF_THREAD_PRIO (LOWPRIO + 1)
+#endif
+
+/**
+ * PPP_THREAD_NAME: The name assigned to the pppInputThread.
+ */
+#ifndef PPP_THREAD_NAME
+#define PPP_THREAD_NAME "pppInputThread"
+#endif
+
+/**
+ * PPP_THREAD_STACKSIZE: The stack size used by the pppInputThread.
+ * The stack size value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef PPP_THREAD_STACKSIZE
+#define PPP_THREAD_STACKSIZE 1024
+#endif
+
+/**
+ * PPP_THREAD_PRIO: The priority assigned to the pppInputThread.
+ * The priority value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef PPP_THREAD_PRIO
+#define PPP_THREAD_PRIO (LOWPRIO + 1)
+#endif
+
+/**
+ * DEFAULT_THREAD_NAME: The name assigned to any other lwIP thread.
+ */
+#ifndef DEFAULT_THREAD_NAME
+#define DEFAULT_THREAD_NAME "lwIP"
+#endif
+
+/**
+ * DEFAULT_THREAD_STACKSIZE: The stack size used by any other lwIP thread.
+ * The stack size value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef DEFAULT_THREAD_STACKSIZE
+#define DEFAULT_THREAD_STACKSIZE 1024
+#endif
+
+/**
+ * DEFAULT_THREAD_PRIO: The priority assigned to any other lwIP thread.
+ * The priority value itself is platform-dependent, but is passed to
+ * sys_thread_new() when the thread is created.
+ */
+#ifndef DEFAULT_THREAD_PRIO
+#define DEFAULT_THREAD_PRIO (LOWPRIO + 1)
+#endif
+
+/**
+ * DEFAULT_RAW_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
+ * NETCONN_RAW. The queue size value itself is platform-dependent, but is passed
+ * to sys_mbox_new() when the recvmbox is created.
+ */
+#ifndef DEFAULT_RAW_RECVMBOX_SIZE
+#define DEFAULT_RAW_RECVMBOX_SIZE 4
+#endif
+
+/**
+ * DEFAULT_UDP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
+ * NETCONN_UDP. The queue size value itself is platform-dependent, but is passed
+ * to sys_mbox_new() when the recvmbox is created.
+ */
+#ifndef DEFAULT_UDP_RECVMBOX_SIZE
+#define DEFAULT_UDP_RECVMBOX_SIZE 4
+#endif
+
+/**
+ * DEFAULT_TCP_RECVMBOX_SIZE: The mailbox size for the incoming packets on a
+ * NETCONN_TCP. The queue size value itself is platform-dependent, but is passed
+ * to sys_mbox_new() when the recvmbox is created.
+ */
+#ifndef DEFAULT_TCP_RECVMBOX_SIZE
+#define DEFAULT_TCP_RECVMBOX_SIZE 40
+#endif
+
+/**
+ * DEFAULT_ACCEPTMBOX_SIZE: The mailbox size for the incoming connections.
+ * The queue size value itself is platform-dependent, but is passed to
+ * sys_mbox_new() when the acceptmbox is created.
+ */
+#ifndef DEFAULT_ACCEPTMBOX_SIZE
+#define DEFAULT_ACCEPTMBOX_SIZE 4
+#endif
+
+/*
+ ----------------------------------------------
+ ---------- Sequential layer options ----------
+ ----------------------------------------------
+*/
+/**
+ * LWIP_TCPIP_CORE_LOCKING: (EXPERIMENTAL!)
+ * Don't use it if you're not an active lwIP project member
+ */
+#ifndef LWIP_TCPIP_CORE_LOCKING
+#define LWIP_TCPIP_CORE_LOCKING 0
+#endif
+
+/**
+ * LWIP_TCPIP_CORE_LOCKING_INPUT: (EXPERIMENTAL!)
+ * Don't use it if you're not an active lwIP project member
+ */
+#ifndef LWIP_TCPIP_CORE_LOCKING_INPUT
+#define LWIP_TCPIP_CORE_LOCKING_INPUT 0
+#endif
+
+/**
+ * LWIP_NETCONN==1: Enable Netconn API (require to use api_lib.c)
+ */
+#ifndef LWIP_NETCONN
+#define LWIP_NETCONN 1
+#endif
+
+/** LWIP_TCPIP_TIMEOUT==1: Enable tcpip_timeout/tcpip_untimeout tod create
+ * timers running in tcpip_thread from another thread.
+ */
+#ifndef LWIP_TCPIP_TIMEOUT
+#define LWIP_TCPIP_TIMEOUT 1
+#endif
+
+/*
+ ------------------------------------
+ ---------- Socket options ----------
+ ------------------------------------
+*/
+/**
+ * LWIP_SOCKET==1: Enable Socket API (require to use sockets.c)
+ */
+#ifndef LWIP_SOCKET
+#define LWIP_SOCKET 1
+#endif
+
+/**
+ * LWIP_COMPAT_SOCKETS==1: Enable BSD-style sockets functions names.
+ * (only used if you use sockets.c)
+ */
+#ifndef LWIP_COMPAT_SOCKETS
+#define LWIP_COMPAT_SOCKETS 1
+#endif
+
+/**
+ * LWIP_POSIX_SOCKETS_IO_NAMES==1: Enable POSIX-style sockets functions names.
+ * Disable this option if you use a POSIX operating system that uses the same
+ * names (read, write & close). (only used if you use sockets.c)
+ */
+#ifndef LWIP_POSIX_SOCKETS_IO_NAMES
+#define LWIP_POSIX_SOCKETS_IO_NAMES 1
+#endif
+
+/**
+ * LWIP_TCP_KEEPALIVE==1: Enable TCP_KEEPIDLE, TCP_KEEPINTVL and TCP_KEEPCNT
+ * options processing. Note that TCP_KEEPIDLE and TCP_KEEPINTVL have to be set
+ * in seconds. (does not require sockets.c, and will affect tcp.c)
+ */
+#ifndef LWIP_TCP_KEEPALIVE
+#define LWIP_TCP_KEEPALIVE 0
+#endif
+
+/**
+ * LWIP_SO_RCVTIMEO==1: Enable SO_RCVTIMEO processing.
+ */
+#ifndef LWIP_SO_RCVTIMEO
+#define LWIP_SO_RCVTIMEO 0
+#endif
+
+/**
+ * LWIP_SO_RCVBUF==1: Enable SO_RCVBUF processing.
+ */
+#ifndef LWIP_SO_RCVBUF
+#define LWIP_SO_RCVBUF 0
+#endif
+
+/**
+ * If LWIP_SO_RCVBUF is used, this is the default value for recv_bufsize.
+ */
+#ifndef RECV_BUFSIZE_DEFAULT
+#define RECV_BUFSIZE_DEFAULT INT_MAX
+#endif
+
+/**
+ * SO_REUSE==1: Enable SO_REUSEADDR option.
+ */
+#ifndef SO_REUSE
+#define SO_REUSE 0
+#endif
+
+/**
+ * SO_REUSE_RXTOALL==1: Pass a copy of incoming broadcast/multicast packets
+ * to all local matches if SO_REUSEADDR is turned on.
+ * WARNING: Adds a memcpy for every packet if passing to more than one pcb!
+ */
+#ifndef SO_REUSE_RXTOALL
+#define SO_REUSE_RXTOALL 0
+#endif
+
+/*
+ ----------------------------------------
+ ---------- Statistics options ----------
+ ----------------------------------------
+*/
+/**
+ * LWIP_STATS==1: Enable statistics collection in lwip_stats.
+ */
+#ifndef LWIP_STATS
+#define LWIP_STATS 1
+#endif
+
+#if LWIP_STATS
+
+/**
+ * LWIP_STATS_DISPLAY==1: Compile in the statistics output functions.
+ */
+#ifndef LWIP_STATS_DISPLAY
+#define LWIP_STATS_DISPLAY 0
+#endif
+
+/**
+ * LINK_STATS==1: Enable link stats.
+ */
+#ifndef LINK_STATS
+#define LINK_STATS 1
+#endif
+
+/**
+ * ETHARP_STATS==1: Enable etharp stats.
+ */
+#ifndef ETHARP_STATS
+#define ETHARP_STATS (LWIP_ARP)
+#endif
+
+/**
+ * IP_STATS==1: Enable IP stats.
+ */
+#ifndef IP_STATS
+#define IP_STATS 1
+#endif
+
+/**
+ * IPFRAG_STATS==1: Enable IP fragmentation stats. Default is
+ * on if using either frag or reass.
+ */
+#ifndef IPFRAG_STATS
+#define IPFRAG_STATS (IP_REASSEMBLY || IP_FRAG)
+#endif
+
+/**
+ * ICMP_STATS==1: Enable ICMP stats.
+ */
+#ifndef ICMP_STATS
+#define ICMP_STATS 1
+#endif
+
+/**
+ * IGMP_STATS==1: Enable IGMP stats.
+ */
+#ifndef IGMP_STATS
+#define IGMP_STATS (LWIP_IGMP)
+#endif
+
+/**
+ * UDP_STATS==1: Enable UDP stats. Default is on if
+ * UDP enabled, otherwise off.
+ */
+#ifndef UDP_STATS
+#define UDP_STATS (LWIP_UDP)
+#endif
+
+/**
+ * TCP_STATS==1: Enable TCP stats. Default is on if TCP
+ * enabled, otherwise off.
+ */
+#ifndef TCP_STATS
+#define TCP_STATS (LWIP_TCP)
+#endif
+
+/**
+ * MEM_STATS==1: Enable mem.c stats.
+ */
+#ifndef MEM_STATS
+#define MEM_STATS ((MEM_LIBC_MALLOC == 0) && (MEM_USE_POOLS == 0))
+#endif
+
+/**
+ * MEMP_STATS==1: Enable memp.c pool stats.
+ */
+#ifndef MEMP_STATS
+#define MEMP_STATS (MEMP_MEM_MALLOC == 0)
+#endif
+
+/**
+ * SYS_STATS==1: Enable system stats (sem and mbox counts, etc).
+ */
+#ifndef SYS_STATS
+#define SYS_STATS (NO_SYS == 0)
+#endif
+
+#else
+
+#define LINK_STATS 0
+#define IP_STATS 0
+#define IPFRAG_STATS 0
+#define ICMP_STATS 0
+#define IGMP_STATS 0
+#define UDP_STATS 0
+#define TCP_STATS 0
+#define MEM_STATS 0
+#define MEMP_STATS 0
+#define SYS_STATS 0
+#define LWIP_STATS_DISPLAY 0
+
+#endif /* LWIP_STATS */
+
+/*
+ ---------------------------------
+ ---------- PPP options ----------
+ ---------------------------------
+*/
+/**
+ * PPP_SUPPORT==1: Enable PPP.
+ */
+#ifndef PPP_SUPPORT
+#define PPP_SUPPORT 0
+#endif
+
+/**
+ * PPPOE_SUPPORT==1: Enable PPP Over Ethernet
+ */
+#ifndef PPPOE_SUPPORT
+#define PPPOE_SUPPORT 0
+#endif
+
+/**
+ * PPPOS_SUPPORT==1: Enable PPP Over Serial
+ */
+#ifndef PPPOS_SUPPORT
+#define PPPOS_SUPPORT PPP_SUPPORT
+#endif
+
+#if PPP_SUPPORT
+
+/**
+ * NUM_PPP: Max PPP sessions.
+ */
+#ifndef NUM_PPP
+#define NUM_PPP 1
+#endif
+
+/**
+ * PAP_SUPPORT==1: Support PAP.
+ */
+#ifndef PAP_SUPPORT
+#define PAP_SUPPORT 0
+#endif
+
+/**
+ * CHAP_SUPPORT==1: Support CHAP.
+ */
+#ifndef CHAP_SUPPORT
+#define CHAP_SUPPORT 0
+#endif
+
+/**
+ * MSCHAP_SUPPORT==1: Support MSCHAP. CURRENTLY NOT SUPPORTED! DO NOT SET!
+ */
+#ifndef MSCHAP_SUPPORT
+#define MSCHAP_SUPPORT 0
+#endif
+
+/**
+ * CBCP_SUPPORT==1: Support CBCP. CURRENTLY NOT SUPPORTED! DO NOT SET!
+ */
+#ifndef CBCP_SUPPORT
+#define CBCP_SUPPORT 0
+#endif
+
+/**
+ * CCP_SUPPORT==1: Support CCP. CURRENTLY NOT SUPPORTED! DO NOT SET!
+ */
+#ifndef CCP_SUPPORT
+#define CCP_SUPPORT 0
+#endif
+
+/**
+ * VJ_SUPPORT==1: Support VJ header compression.
+ */
+#ifndef VJ_SUPPORT
+#define VJ_SUPPORT 0
+#endif
+
+/**
+ * MD5_SUPPORT==1: Support MD5 (see also CHAP).
+ */
+#ifndef MD5_SUPPORT
+#define MD5_SUPPORT 0
+#endif
+
+/*
+ * Timeouts
+ */
+#ifndef FSM_DEFTIMEOUT
+#define FSM_DEFTIMEOUT 6 /* Timeout time in seconds */
+#endif
+
+#ifndef FSM_DEFMAXTERMREQS
+#define FSM_DEFMAXTERMREQS 2 /* Maximum Terminate-Request transmissions */
+#endif
+
+#ifndef FSM_DEFMAXCONFREQS
+#define FSM_DEFMAXCONFREQS 10 /* Maximum Configure-Request transmissions */
+#endif
+
+#ifndef FSM_DEFMAXNAKLOOPS
+#define FSM_DEFMAXNAKLOOPS 5 /* Maximum number of nak loops */
+#endif
+
+#ifndef UPAP_DEFTIMEOUT
+#define UPAP_DEFTIMEOUT 6 /* Timeout (seconds) for retransmitting req */
+#endif
+
+#ifndef UPAP_DEFREQTIME
+#define UPAP_DEFREQTIME 30 /* Time to wait for auth-req from peer */
+#endif
+
+#ifndef CHAP_DEFTIMEOUT
+#define CHAP_DEFTIMEOUT 6 /* Timeout time in seconds */
+#endif
+
+#ifndef CHAP_DEFTRANSMITS
+#define CHAP_DEFTRANSMITS 10 /* max # times to send challenge */
+#endif
+
+/* Interval in seconds between keepalive echo requests, 0 to disable. */
+#ifndef LCP_ECHOINTERVAL
+#define LCP_ECHOINTERVAL 0
+#endif
+
+/* Number of unanswered echo requests before failure. */
+#ifndef LCP_MAXECHOFAILS
+#define LCP_MAXECHOFAILS 3
+#endif
+
+/* Max Xmit idle time (in jiffies) before resend flag char. */
+#ifndef PPP_MAXIDLEFLAG
+#define PPP_MAXIDLEFLAG 100
+#endif
+
+/*
+ * Packet sizes
+ *
+ * Note - lcp shouldn't be allowed to negotiate stuff outside these
+ * limits. See lcp.h in the pppd directory.
+ * (XXX - these constants should simply be shared by lcp.c instead
+ * of living in lcp.h)
+ */
+#define PPP_MTU 1500 /* Default MTU (size of Info field) */
+#ifndef PPP_MAXMTU
+/* #define PPP_MAXMTU 65535 - (PPP_HDRLEN + PPP_FCSLEN) */
+#define PPP_MAXMTU 1500 /* Largest MTU we allow */
+#endif
+#define PPP_MINMTU 64
+#define PPP_MRU 1500 /* default MRU = max length of info field */
+#define PPP_MAXMRU 1500 /* Largest MRU we allow */
+#ifndef PPP_DEFMRU
+#define PPP_DEFMRU 296 /* Try for this */
+#endif
+#define PPP_MINMRU 128 /* No MRUs below this */
+
+#ifndef MAXNAMELEN
+#define MAXNAMELEN 256 /* max length of hostname or name for auth */
+#endif
+#ifndef MAXSECRETLEN
+#define MAXSECRETLEN 256 /* max length of password or secret */
+#endif
+
+#endif /* PPP_SUPPORT */
+
+/*
+ --------------------------------------
+ ---------- Checksum options ----------
+ --------------------------------------
+*/
+/**
+ * CHECKSUM_GEN_IP==1: Generate checksums in software for outgoing IP packets.
+ */
+#ifndef CHECKSUM_GEN_IP
+#define CHECKSUM_GEN_IP 1
+#endif
+
+/**
+ * CHECKSUM_GEN_UDP==1: Generate checksums in software for outgoing UDP packets.
+ */
+#ifndef CHECKSUM_GEN_UDP
+#define CHECKSUM_GEN_UDP 1
+#endif
+
+/**
+ * CHECKSUM_GEN_TCP==1: Generate checksums in software for outgoing TCP packets.
+ */
+#ifndef CHECKSUM_GEN_TCP
+#define CHECKSUM_GEN_TCP 1
+#endif
+
+/**
+ * CHECKSUM_CHECK_IP==1: Check checksums in software for incoming IP packets.
+ */
+#ifndef CHECKSUM_CHECK_IP
+#define CHECKSUM_CHECK_IP 1
+#endif
+
+/**
+ * CHECKSUM_CHECK_UDP==1: Check checksums in software for incoming UDP packets.
+ */
+#ifndef CHECKSUM_CHECK_UDP
+#define CHECKSUM_CHECK_UDP 1
+#endif
+
+/**
+ * CHECKSUM_CHECK_TCP==1: Check checksums in software for incoming TCP packets.
+ */
+#ifndef CHECKSUM_CHECK_TCP
+#define CHECKSUM_CHECK_TCP 1
+#endif
+
+/**
+ * LWIP_CHECKSUM_ON_COPY==1: Calculate checksum when copying data from
+ * application buffers to pbufs.
+ */
+#ifndef LWIP_CHECKSUM_ON_COPY
+#define LWIP_CHECKSUM_ON_COPY 0
+#endif
+
+/*
+ ---------------------------------------
+ ---------- Debugging options ----------
+ ---------------------------------------
+*/
+/**
+ * LWIP_DBG_MIN_LEVEL: After masking, the value of the debug is
+ * compared against this value. If it is smaller, then debugging
+ * messages are written.
+ */
+#ifndef LWIP_DBG_MIN_LEVEL
+#define LWIP_DBG_MIN_LEVEL LWIP_DBG_LEVEL_OFF
+#endif
+
+/**
+ * LWIP_DBG_TYPES_ON: A mask that can be used to globally enable/disable
+ * debug messages of certain types.
+ */
+#ifndef LWIP_DBG_TYPES_ON
+#define LWIP_DBG_TYPES_ON LWIP_DBG_ON
+#endif
+
+/**
+ * ETHARP_DEBUG: Enable debugging in etharp.c.
+ */
+#ifndef ETHARP_DEBUG
+#define ETHARP_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * NETIF_DEBUG: Enable debugging in netif.c.
+ */
+#ifndef NETIF_DEBUG
+#define NETIF_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * PBUF_DEBUG: Enable debugging in pbuf.c.
+ */
+#ifndef PBUF_DEBUG
+#define PBUF_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * API_LIB_DEBUG: Enable debugging in api_lib.c.
+ */
+#ifndef API_LIB_DEBUG
+#define API_LIB_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * API_MSG_DEBUG: Enable debugging in api_msg.c.
+ */
+#ifndef API_MSG_DEBUG
+#define API_MSG_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * SOCKETS_DEBUG: Enable debugging in sockets.c.
+ */
+#ifndef SOCKETS_DEBUG
+#define SOCKETS_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * ICMP_DEBUG: Enable debugging in icmp.c.
+ */
+#ifndef ICMP_DEBUG
+#define ICMP_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * IGMP_DEBUG: Enable debugging in igmp.c.
+ */
+#ifndef IGMP_DEBUG
+#define IGMP_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * INET_DEBUG: Enable debugging in inet.c.
+ */
+#ifndef INET_DEBUG
+#define INET_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * IP_DEBUG: Enable debugging for IP.
+ */
+#ifndef IP_DEBUG
+#define IP_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * IP_REASS_DEBUG: Enable debugging in ip_frag.c for both frag & reass.
+ */
+#ifndef IP_REASS_DEBUG
+#define IP_REASS_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * RAW_DEBUG: Enable debugging in raw.c.
+ */
+#ifndef RAW_DEBUG
+#define RAW_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * MEM_DEBUG: Enable debugging in mem.c.
+ */
+#ifndef MEM_DEBUG
+#define MEM_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * MEMP_DEBUG: Enable debugging in memp.c.
+ */
+#ifndef MEMP_DEBUG
+#define MEMP_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * SYS_DEBUG: Enable debugging in sys.c.
+ */
+#ifndef SYS_DEBUG
+#define SYS_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * TIMERS_DEBUG: Enable debugging in timers.c.
+ */
+#ifndef TIMERS_DEBUG
+#define TIMERS_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_DEBUG: Enable debugging for TCP.
+ */
+#ifndef TCP_DEBUG
+#define TCP_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_INPUT_DEBUG: Enable debugging in tcp_in.c for incoming debug.
+ */
+#ifndef TCP_INPUT_DEBUG
+#define TCP_INPUT_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_FR_DEBUG: Enable debugging in tcp_in.c for fast retransmit.
+ */
+#ifndef TCP_FR_DEBUG
+#define TCP_FR_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_RTO_DEBUG: Enable debugging in TCP for retransmit
+ * timeout.
+ */
+#ifndef TCP_RTO_DEBUG
+#define TCP_RTO_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_CWND_DEBUG: Enable debugging for TCP congestion window.
+ */
+#ifndef TCP_CWND_DEBUG
+#define TCP_CWND_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_WND_DEBUG: Enable debugging in tcp_in.c for window updating.
+ */
+#ifndef TCP_WND_DEBUG
+#define TCP_WND_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_OUTPUT_DEBUG: Enable debugging in tcp_out.c output functions.
+ */
+#ifndef TCP_OUTPUT_DEBUG
+#define TCP_OUTPUT_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_RST_DEBUG: Enable debugging for TCP with the RST message.
+ */
+#ifndef TCP_RST_DEBUG
+#define TCP_RST_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * TCP_QLEN_DEBUG: Enable debugging for TCP queue lengths.
+ */
+#ifndef TCP_QLEN_DEBUG
+#define TCP_QLEN_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * UDP_DEBUG: Enable debugging in UDP.
+ */
+#ifndef UDP_DEBUG
+#define UDP_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * TCPIP_DEBUG: Enable debugging in tcpip.c.
+ */
+#ifndef TCPIP_DEBUG
+#define TCPIP_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * PPP_DEBUG: Enable debugging for PPP.
+ */
+#ifndef PPP_DEBUG
+#define PPP_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * SLIP_DEBUG: Enable debugging in slipif.c.
+ */
+#ifndef SLIP_DEBUG
+#define SLIP_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * DHCP_DEBUG: Enable debugging in dhcp.c.
+ */
+#ifndef DHCP_DEBUG
+#define DHCP_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * AUTOIP_DEBUG: Enable debugging in autoip.c.
+ */
+#ifndef AUTOIP_DEBUG
+#define AUTOIP_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * SNMP_MSG_DEBUG: Enable debugging for SNMP messages.
+ */
+#ifndef SNMP_MSG_DEBUG
+#define SNMP_MSG_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * SNMP_MIB_DEBUG: Enable debugging for SNMP MIBs.
+ */
+#ifndef SNMP_MIB_DEBUG
+#define SNMP_MIB_DEBUG LWIP_DBG_OFF
+#endif
+
+/**
+ * DNS_DEBUG: Enable debugging for DNS.
+ */
+#ifndef DNS_DEBUG
+#define DNS_DEBUG LWIP_DBG_OFF
+#endif
+
+#endif /* __LWIPOPT_H__ */
diff --git a/demos/ARMCM4-STM32F407-LWIP/main.c b/demos/ARMCM4-STM32F407-LWIP/main.c new file mode 100644 index 000000000..39f94b9a1 --- /dev/null +++ b/demos/ARMCM4-STM32F407-LWIP/main.c @@ -0,0 +1,91 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#include "ch.h"
+#include "hal.h"
+#include "test.h"
+
+#include "lwipthread.h"
+
+#include "web/web.h"
+
+/*
+ * Green LED blinker thread, times are in milliseconds.
+ */
+static WORKING_AREA(waThread1, 128);
+static msg_t Thread1(void *arg) {
+
+ (void)arg;
+ chRegSetThreadName("blinker");
+ while (TRUE) {
+ palClearPad(GPIOF, GPIOF_STAT1);
+ chThdSleepMilliseconds(500);
+ palSetPad(GPIOF, GPIOF_STAT1);
+ chThdSleepMilliseconds(500);
+ }
+}
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ halInit();
+ chSysInit();
+
+ /*
+ * Activates the serial driver 3 using the driver default configuration.
+ */
+ sdStart(&SD6, NULL);
+
+ /*
+ * Creates the blinker thread.
+ */
+ chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL);
+
+ /*
+ * Creates the LWIP threads (it changes priority internally).
+ */
+ chThdCreateStatic(wa_lwip_thread, LWIP_THREAD_STACK_SIZE, NORMALPRIO + 1,
+ lwip_thread, NULL);
+
+ /*
+ * Creates the HTTP thread (it changes priority internally).
+ */
+ chThdCreateStatic(wa_http_server, sizeof(wa_http_server), NORMALPRIO + 1,
+ http_server, NULL);
+
+ /*
+ * Normal main() thread activity, in this demo it does nothing except
+ * sleeping in a loop and check the button state.
+ */
+ while (TRUE) {
+ if (palReadPad(GPIOC, GPIOC_SWITCH_TAMPER) == 0)
+ TestThread(&SD6);
+ chThdSleepMilliseconds(500);
+ }
+}
diff --git a/demos/ARMCM4-STM32F407-LWIP/mcuconf.h b/demos/ARMCM4-STM32F407-LWIP/mcuconf.h new file mode 100644 index 000000000..37ca75b9a --- /dev/null +++ b/demos/ARMCM4-STM32F407-LWIP/mcuconf.h @@ -0,0 +1,234 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/*
+ * STM32F4xx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 15...0 Lowest...Highest.
+ *
+ * DMA priorities:
+ * 0...3 Lowest...Highest.
+ */
+
+/*
+ * HAL driver system settings.
+ */
+#define STM32_NO_INIT FALSE
+#define STM32_HSI_ENABLED TRUE
+#define STM32_LSI_ENABLED TRUE
+#define STM32_HSE_ENABLED TRUE
+#define STM32_LSE_ENABLED FALSE
+#define STM32_CLOCK48_REQUIRED TRUE
+#define STM32_SW STM32_SW_PLL
+#define STM32_PLLSRC STM32_PLLSRC_HSE
+#define STM32_PLLM_VALUE 25
+#define STM32_PLLN_VALUE 336
+#define STM32_PLLP_VALUE 2
+#define STM32_PLLQ_VALUE 7
+#define STM32_HPRE STM32_HPRE_DIV1
+#define STM32_PPRE1 STM32_PPRE1_DIV4
+#define STM32_PPRE2 STM32_PPRE2_DIV2
+#define STM32_RTCSEL STM32_RTCSEL_LSI
+#define STM32_RTCPRE_VALUE 8
+#define STM32_MCO1SEL STM32_MCO1SEL_HSI
+#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
+#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
+#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
+#define STM32_I2SSRC STM32_I2SSRC_CKIN
+#define STM32_PLLI2SN_VALUE 192
+#define STM32_PLLI2SR_VALUE 5
+#define STM32_VOS STM32_VOS_HIGH
+#define STM32_PVD_ENABLE FALSE
+#define STM32_PLS STM32_PLS_LEV0
+
+/*
+ * ADC driver system settings.
+ */
+#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
+#define STM32_ADC_USE_ADC1 TRUE
+#define STM32_ADC_USE_ADC2 TRUE
+#define STM32_ADC_USE_ADC3 TRUE
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
+#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#define STM32_ADC_ADC2_DMA_PRIORITY 2
+#define STM32_ADC_ADC3_DMA_PRIORITY 2
+#define STM32_ADC_IRQ_PRIORITY 5
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
+
+/*
+ * CAN driver system settings.
+ */
+#define STM32_CAN_USE_CAN1 TRUE
+#define STM32_CAN_CAN1_IRQ_PRIORITY 11
+
+/*
+ * EXT driver system settings.
+ */
+#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI17_IRQ_PRIORITY 15
+#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI21_IRQ_PRIORITY 15
+#define STM32_EXT_EXTI22_IRQ_PRIORITY 15
+
+/*
+ * GPT driver system settings.
+ */
+#define STM32_GPT_USE_TIM1 FALSE
+#define STM32_GPT_USE_TIM2 FALSE
+#define STM32_GPT_USE_TIM3 FALSE
+#define STM32_GPT_USE_TIM4 FALSE
+#define STM32_GPT_USE_TIM5 FALSE
+#define STM32_GPT_USE_TIM8 FALSE
+#define STM32_GPT_TIM1_IRQ_PRIORITY 7
+#define STM32_GPT_TIM2_IRQ_PRIORITY 7
+#define STM32_GPT_TIM3_IRQ_PRIORITY 7
+#define STM32_GPT_TIM4_IRQ_PRIORITY 7
+#define STM32_GPT_TIM5_IRQ_PRIORITY 7
+#define STM32_GPT_TIM8_IRQ_PRIORITY 7
+
+/*
+ * ICU driver system settings.
+ */
+#define STM32_ICU_USE_TIM1 FALSE
+#define STM32_ICU_USE_TIM2 FALSE
+#define STM32_ICU_USE_TIM3 FALSE
+#define STM32_ICU_USE_TIM4 TRUE
+#define STM32_ICU_USE_TIM5 FALSE
+#define STM32_ICU_USE_TIM8 FALSE
+#define STM32_ICU_TIM1_IRQ_PRIORITY 7
+#define STM32_ICU_TIM2_IRQ_PRIORITY 7
+#define STM32_ICU_TIM3_IRQ_PRIORITY 7
+#define STM32_ICU_TIM4_IRQ_PRIORITY 7
+#define STM32_ICU_TIM5_IRQ_PRIORITY 7
+#define STM32_ICU_TIM8_IRQ_PRIORITY 7
+
+/*
+ * PWM driver system settings.
+ */
+#define STM32_PWM_USE_ADVANCED FALSE
+#define STM32_PWM_USE_TIM1 FALSE
+#define STM32_PWM_USE_TIM2 FALSE
+#define STM32_PWM_USE_TIM3 FALSE
+#define STM32_PWM_USE_TIM4 TRUE
+#define STM32_PWM_USE_TIM5 FALSE
+#define STM32_PWM_USE_TIM8 FALSE
+#define STM32_PWM_TIM1_IRQ_PRIORITY 7
+#define STM32_PWM_TIM2_IRQ_PRIORITY 7
+#define STM32_PWM_TIM3_IRQ_PRIORITY 7
+#define STM32_PWM_TIM4_IRQ_PRIORITY 7
+#define STM32_PWM_TIM5_IRQ_PRIORITY 7
+#define STM32_PWM_TIM8_IRQ_PRIORITY 7
+
+/*
+ * SERIAL driver system settings.
+ */
+#define STM32_SERIAL_USE_USART1 FALSE
+#define STM32_SERIAL_USE_USART2 FALSE
+#define STM32_SERIAL_USE_USART3 FALSE
+#define STM32_SERIAL_USE_UART4 FALSE
+#define STM32_SERIAL_USE_UART5 FALSE
+#define STM32_SERIAL_USE_USART6 TRUE
+#define STM32_SERIAL_USART1_PRIORITY 12
+#define STM32_SERIAL_USART2_PRIORITY 12
+#define STM32_SERIAL_USART3_PRIORITY 12
+#define STM32_SERIAL_UART4_PRIORITY 12
+#define STM32_SERIAL_UART5_PRIORITY 12
+#define STM32_SERIAL_USART6_PRIORITY 12
+
+/*
+ * SPI driver system settings.
+ */
+#define STM32_SPI_USE_SPI1 TRUE
+#define STM32_SPI_USE_SPI2 TRUE
+#define STM32_SPI_USE_SPI3 FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_SPI_SPI1_DMA_PRIORITY 1
+#define STM32_SPI_SPI2_DMA_PRIORITY 1
+#define STM32_SPI_SPI3_DMA_PRIORITY 1
+#define STM32_SPI_SPI1_IRQ_PRIORITY 10
+#define STM32_SPI_SPI2_IRQ_PRIORITY 10
+#define STM32_SPI_SPI3_IRQ_PRIORITY 10
+#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt()
+
+/*
+ * UART driver system settings.
+ */
+#define STM32_UART_USE_USART1 FALSE
+#define STM32_UART_USE_USART2 TRUE
+#define STM32_UART_USE_USART3 FALSE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART1_IRQ_PRIORITY 12
+#define STM32_UART_USART2_IRQ_PRIORITY 12
+#define STM32_UART_USART3_IRQ_PRIORITY 12
+#define STM32_UART_USART1_DMA_PRIORITY 0
+#define STM32_UART_USART2_DMA_PRIORITY 0
+#define STM32_UART_USART3_DMA_PRIORITY 0
+#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
+
+/*
+ * I2C driver system settings.
+ */
+#define STM32_I2C_USE_I2C1 TRUE
+#define STM32_I2C_USE_I2C2 FALSE
+#define STM32_I2C_USE_I2C3 FALSE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2C_I2C1_IRQ_PRIORITY 6
+#define STM32_I2C_I2C2_IRQ_PRIORITY 6
+#define STM32_I2C_I2C3_IRQ_PRIORITY 6
+#define STM32_I2C_I2C1_DMA_PRIORITY 1
+#define STM32_I2C_I2C2_DMA_PRIORITY 1
+#define STM32_I2C_I2C3_DMA_PRIORITY 1
+#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt()
+#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt()
+#define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt()
+
diff --git a/demos/ARMCM4-STM32F407-LWIP/readme.txt b/demos/ARMCM4-STM32F407-LWIP/readme.txt new file mode 100644 index 000000000..1bb7ebd1a --- /dev/null +++ b/demos/ARMCM4-STM32F407-LWIP/readme.txt @@ -0,0 +1,28 @@ +*****************************************************************************
+** ChibiOS/RT port for ARM-Cortex-M4 STM32F407. **
+*****************************************************************************
+
+** TARGET **
+
+The demo runs on an Olimex STM32-P407 board.
+
+** The Demo **
+
+The demo currently just flashes a LED using a thread and serves HTTP requests
+at address 192.168.1.20 on port 80.
+The button activates che ChibiOS/RT test suite, output on SD6.
+
+** Build Procedure **
+
+The demo has been tested by using the free Codesourcery GCC-based toolchain
+and YAGARTO.
+Just modify the TRGT line in the makefile in order to use different GCC ports.
+
+** Notes **
+
+Some files used by the demo are not part of ChibiOS/RT but are copyright of
+ST Microelectronics and are licensed under a different license.
+Also note that not all the files present in the ST library are distribited
+with ChibiOS/RT, you can find the whole library on the ST web site:
+
+ http://www.st.com
diff --git a/demos/ARMCM4-STM32F407-LWIP/web/web.c b/demos/ARMCM4-STM32F407-LWIP/web/web.c new file mode 100644 index 000000000..3a4a9b4f3 --- /dev/null +++ b/demos/ARMCM4-STM32F407-LWIP/web/web.c @@ -0,0 +1,125 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/*
+ * This file is a modified version of the lwIP web server demo. The original
+ * author is unknown because the file didn't contain any license information.
+ */
+
+/**
+ * @file web.c
+ * @brief HTTP server wrapper thread code.
+ * @addtogroup WEB_THREAD
+ * @{
+ */
+
+#include "ch.h"
+
+#include "lwip/opt.h"
+#include "lwip/arch.h"
+#include "lwip/api.h"
+
+#include "web.h"
+
+#if LWIP_NETCONN
+
+static const char http_html_hdr[] = "HTTP/1.1 200 OK\r\nContent-type: text/html\r\n\r\n";
+static const char http_index_html[] = "<html><head><title>Congrats!</title></head><body><h1>Welcome to our lwIP HTTP server!</h1><p>This is a small test page.</body></html>";
+
+static void http_server_serve(struct netconn *conn) {
+ struct netbuf *inbuf;
+ char *buf;
+ u16_t buflen;
+ err_t err;
+
+ /* Read the data from the port, blocking if nothing yet there.
+ We assume the request (the part we care about) is in one netbuf */
+ err = netconn_recv(conn, &inbuf);
+
+ if (err == ERR_OK) {
+ netbuf_data(inbuf, (void **)&buf, &buflen);
+
+ /* Is this an HTTP GET command? (only check the first 5 chars, since
+ there are other formats for GET, and we're keeping it very simple )*/
+ if (buflen>=5 &&
+ buf[0]=='G' &&
+ buf[1]=='E' &&
+ buf[2]=='T' &&
+ buf[3]==' ' &&
+ buf[4]=='/' ) {
+
+ /* Send the HTML header
+ * subtract 1 from the size, since we dont send the \0 in the string
+ * NETCONN_NOCOPY: our data is const static, so no need to copy it
+ */
+ netconn_write(conn, http_html_hdr, sizeof(http_html_hdr)-1, NETCONN_NOCOPY);
+
+ /* Send our HTML page */
+ netconn_write(conn, http_index_html, sizeof(http_index_html)-1, NETCONN_NOCOPY);
+ }
+ }
+ /* Close the connection (server closes in HTTP) */
+ netconn_close(conn);
+
+ /* Delete the buffer (netconn_recv gives us ownership,
+ so we have to make sure to deallocate the buffer) */
+ netbuf_delete(inbuf);
+}
+
+/**
+ * Stack area for the http thread.
+ */
+WORKING_AREA(wa_http_server, WEB_THREAD_STACK_SIZE);
+
+/**
+ * HTTP server thread.
+ */
+msg_t http_server(void *p) {
+ struct netconn *conn, *newconn;
+ err_t err;
+
+ (void)p;
+
+ /* Create a new TCP connection handle */
+ conn = netconn_new(NETCONN_TCP);
+ LWIP_ERROR("http_server: invalid conn", (conn != NULL), return RDY_RESET;);
+
+ /* Bind to port 80 (HTTP) with default IP address */
+ netconn_bind(conn, NULL, WEB_THREAD_PORT);
+
+ /* Put the connection into LISTEN state */
+ netconn_listen(conn);
+
+ /* Goes to the final priority after initialization.*/
+ chThdSetPriority(WEB_THREAD_PRIORITY);
+
+ while(1) {
+ err = netconn_accept(conn, &newconn);
+ if (err != ERR_OK)
+ continue;
+ http_server_serve(newconn);
+ netconn_delete(newconn);
+ }
+ return RDY_OK;
+}
+
+#endif /* LWIP_NETCONN */
+
+/** @} */
diff --git a/demos/ARMCM4-STM32F407-LWIP/web/web.h b/demos/ARMCM4-STM32F407-LWIP/web/web.h new file mode 100644 index 000000000..64c217afa --- /dev/null +++ b/demos/ARMCM4-STM32F407-LWIP/web/web.h @@ -0,0 +1,55 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file web.h
+ * @brief HTTP server wrapper thread macros and structures.
+ * @addtogroup WEB_THREAD
+ * @{
+ */
+
+#ifndef _WEB_H_
+#define _WEB_H_
+
+#ifndef WEB_THREAD_STACK_SIZE
+#define WEB_THREAD_STACK_SIZE 1024
+#endif
+
+#ifndef WEB_THREAD_PORT
+#define WEB_THREAD_PORT 80
+#endif
+
+#ifndef WEB_THREAD_PRIORITY
+#define WEB_THREAD_PRIORITY (LOWPRIO + 2)
+#endif
+
+extern WORKING_AREA(wa_http_server, WEB_THREAD_STACK_SIZE);
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ msg_t http_server(void *p);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _WEB_H_ */
+
+/** @} */
diff --git a/demos/AVR-AT90CANx-GCC/chconf.h b/demos/AVR-AT90CANx-GCC/chconf.h index 3733daac8..ec84e58af 100644 --- a/demos/AVR-AT90CANx-GCC/chconf.h +++ b/demos/AVR-AT90CANx-GCC/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/demos/AVR-AT90CANx-GCC/halconf.h b/demos/AVR-AT90CANx-GCC/halconf.h index eb013c9a7..c9b3ad25a 100644 --- a/demos/AVR-AT90CANx-GCC/halconf.h +++ b/demos/AVR-AT90CANx-GCC/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/demos/AVR-ATmega128-GCC/chconf.h b/demos/AVR-ATmega128-GCC/chconf.h index 3733daac8..ec84e58af 100644 --- a/demos/AVR-ATmega128-GCC/chconf.h +++ b/demos/AVR-ATmega128-GCC/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/demos/AVR-ATmega128-GCC/halconf.h b/demos/AVR-ATmega128-GCC/halconf.h index eb013c9a7..c9b3ad25a 100644 --- a/demos/AVR-ATmega128-GCC/halconf.h +++ b/demos/AVR-ATmega128-GCC/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/demos/MSP430-MSP430x1611-GCC/chconf.h b/demos/MSP430-MSP430x1611-GCC/chconf.h index d40ceb7d4..6159d83b8 100644 --- a/demos/MSP430-MSP430x1611-GCC/chconf.h +++ b/demos/MSP430-MSP430x1611-GCC/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/demos/MSP430-MSP430x1611-GCC/halconf.h b/demos/MSP430-MSP430x1611-GCC/halconf.h index eb013c9a7..c9b3ad25a 100644 --- a/demos/MSP430-MSP430x1611-GCC/halconf.h +++ b/demos/MSP430-MSP430x1611-GCC/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/demos/PPC-SPC563-GCC/chconf.h b/demos/PPC-SPC563-GCC/chconf.h index 4115636d6..b1f2cd62c 100644 --- a/demos/PPC-SPC563-GCC/chconf.h +++ b/demos/PPC-SPC563-GCC/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/demos/PPC-SPC563-GCC/halconf.h b/demos/PPC-SPC563-GCC/halconf.h index 4acf9f66c..83783d10f 100644 --- a/demos/PPC-SPC563-GCC/halconf.h +++ b/demos/PPC-SPC563-GCC/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/demos/Posix-GCC/chconf.h b/demos/Posix-GCC/chconf.h index de77658a9..e5794592e 100644 --- a/demos/Posix-GCC/chconf.h +++ b/demos/Posix-GCC/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/demos/Posix-GCC/halconf.h b/demos/Posix-GCC/halconf.h index 79e3cbd09..202137119 100644 --- a/demos/Posix-GCC/halconf.h +++ b/demos/Posix-GCC/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/chconf.h b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/chconf.h index df1b4a9f9..18b92af50 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/chconf.h +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h index eb013c9a7..c9b3ad25a 100644 --- a/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h +++ b/demos/STM8L-STM8L152-DISCOVERY-STVD/demo/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/chconf.h b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/chconf.h index df1b4a9f9..18b92af50 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/chconf.h +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h index eb013c9a7..c9b3ad25a 100644 --- a/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h +++ b/demos/STM8S-STM8S105-DISCOVERY-STVD/demo/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/demos/STM8S-STM8S208-RC/chconf.h b/demos/STM8S-STM8S208-RC/chconf.h index df1b4a9f9..18b92af50 100644 --- a/demos/STM8S-STM8S208-RC/chconf.h +++ b/demos/STM8S-STM8S208-RC/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/demos/STM8S-STM8S208-RC/halconf.h b/demos/STM8S-STM8S208-RC/halconf.h index eb013c9a7..c9b3ad25a 100644 --- a/demos/STM8S-STM8S208-RC/halconf.h +++ b/demos/STM8S-STM8S208-RC/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/demos/Win32-MinGW/chconf.h b/demos/Win32-MinGW/chconf.h index de77658a9..e5794592e 100644 --- a/demos/Win32-MinGW/chconf.h +++ b/demos/Win32-MinGW/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/demos/Win32-MinGW/halconf.h b/demos/Win32-MinGW/halconf.h index 79e3cbd09..202137119 100644 --- a/demos/Win32-MinGW/halconf.h +++ b/demos/Win32-MinGW/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/docs/reports/MSP430F1611-0.75.txt b/docs/reports/MSP430F1611-0.75.txt index 16e048f10..802d60e69 100644 --- a/docs/reports/MSP430F1611-0.75.txt +++ b/docs/reports/MSP430F1611-0.75.txt @@ -1,6 +1,6 @@ ***************************************************************************
Options: -O2 -fomit-frame-pointer
-Settings: MCLK=DCOCLK 750KHz
+Settings: MCLK=DCOCLK 750kHz
***************************************************************************
*** ChibiOS/RT test suite
diff --git a/docs/reports/STM32F407-168-GCC-FPU.txt b/docs/reports/STM32F407-168-GCC-FPU.txt index d2eccbd15..9b37d76f0 100644 --- a/docs/reports/STM32F407-168-GCC-FPU.txt +++ b/docs/reports/STM32F407-168-GCC-FPU.txt @@ -5,8 +5,8 @@ Settings: SYSCLK=168, ACR=0x705 (5 wait states) *** ChibiOS/RT test suite
***
-*** Kernel: 2.4.0
-*** Compiled: Jan 15 2012 - 20:12:59
+*** Kernel: 2.5.0
+*** Compiled: Apr 1 2012 - 14:19:33
*** Compiler: GCC 4.6.2
*** Architecture: ARMv7-ME
*** Core Variant: Cortex-M4F
@@ -100,55 +100,55 @@ Settings: SYSCLK=168, ACR=0x705 (5 wait states) --- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.1 (Benchmark, messages #1)
---- Score : 574777 msgs/S, 1149554 ctxswc/S
+--- Score : 576749 msgs/S, 1153498 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.2 (Benchmark, messages #2)
---- Score : 493631 msgs/S, 987262 ctxswc/S
+--- Score : 493633 msgs/S, 987266 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.3 (Benchmark, messages #3)
---- Score : 493627 msgs/S, 987254 ctxswc/S
+--- Score : 493631 msgs/S, 987262 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.4 (Benchmark, context switch)
---- Score : 1655616 ctxswc/S
+--- Score : 1672112 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.5 (Benchmark, threads, full cycle)
---- Score : 384066 threads/S
+--- Score : 382319 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.6 (Benchmark, threads, create only)
---- Score : 510142 threads/S
+--- Score : 510144 threads/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.7 (Benchmark, mass reschedule, 5 threads)
---- Score : 156416 reschedules/S, 938496 ctxswc/S
+--- Score : 156526 reschedules/S, 939156 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.8 (Benchmark, round robin context switching)
---- Score : 1070720 ctxswc/S
+--- Score : 1063936 ctxswc/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.9 (Benchmark, I/O Queues throughput)
---- Score : 1804688 bytes/S
+--- Score : 1804680 bytes/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.10 (Benchmark, virtual timers set/reset)
---- Score : 2124530 timers/S
+--- Score : 2124518 timers/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.11 (Benchmark, semaphores wait/signal)
---- Score : 2685380 wait+signal/S
+--- Score : 2685364 wait+signal/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.12 (Benchmark, mutexes lock/unlock)
---- Score : 1885800 lock+unlock/S
+--- Score : 1885792 lock+unlock/S
--- Result: SUCCESS
----------------------------------------------------------------------------
--- Test Case 11.13 (Benchmark, RAM footprint)
---- System: 648 bytes
+--- System: 644 bytes
--- Thread: 72 bytes
--- Timer : 20 bytes
--- Semaph: 12 bytes
diff --git a/docs/reports/STM32F407-168-GCC.txt b/docs/reports/STM32F407-168-GCC.txt index db5324e3c..e28a0a1f9 100644 --- a/docs/reports/STM32F407-168-GCC.txt +++ b/docs/reports/STM32F407-168-GCC.txt @@ -6,7 +6,7 @@ Settings: SYSCLK=168, ACR=0x705 (5 wait states) *** ChibiOS/RT test suite
***
*** Kernel: 2.5.0
-*** Compiled: Feb 8 2012 - 19:52:01
+*** Compiled: Apr 9 2012 - 15:07:48
*** Compiler: GCC 4.6.2
*** Architecture: ARMv7-ME
*** Core Variant: Cortex-M4
diff --git a/ext/fatfs-0.8b-patched.zip b/ext/fatfs-0.8b-patched.zip Binary files differindex ff7548985..d5f3d4f75 100644 --- a/ext/fatfs-0.8b-patched.zip +++ b/ext/fatfs-0.8b-patched.zip diff --git a/os/hal/dox/uart.dox b/os/hal/dox/uart.dox index 079237982..27c1494fb 100644 --- a/os/hal/dox/uart.dox +++ b/os/hal/dox/uart.dox @@ -39,7 +39,7 @@ * - Multipoint network drivers.
* - Serial protocol decoders.
* .
- * If your application requires a synchronoyus buffered driver then
+ * If your application requires a synchronous buffered driver then
* the @ref SERIAL should be used instead.
* @pre In order to use the UART driver the @p HAL_USE_UART option
* must be enabled in @p halconf.h.
diff --git a/os/hal/include/adc.h b/os/hal/include/adc.h index 137096609..8f829d386 100644 --- a/os/hal/include/adc.h +++ b/os/hal/include/adc.h @@ -282,13 +282,13 @@ extern "C" { void adcStart(ADCDriver *adcp, const ADCConfig *config);
void adcStop(ADCDriver *adcp);
void adcStartConversion(ADCDriver *adcp,
+ const ADCConversionGroup *grpp,
+ adcsample_t *samples,
+ size_t depth);
+ void adcStartConversionI(ADCDriver *adcp,
const ADCConversionGroup *grpp,
adcsample_t *samples,
size_t depth);
- void adcStartConversionI(ADCDriver *adcp,
- const ADCConversionGroup *grpp,
- adcsample_t *samples,
- size_t depth);
void adcStopConversion(ADCDriver *adcp);
void adcStopConversionI(ADCDriver *adcp);
#if ADC_USE_WAIT
diff --git a/os/hal/include/i2s.h b/os/hal/include/i2s.h new file mode 100644 index 000000000..d2dedf982 --- /dev/null +++ b/os/hal/include/i2s.h @@ -0,0 +1,148 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file i2s.h
+ * @brief I2S Driver macros and structures.
+ *
+ * @addtogroup I2S
+ * @{
+ */
+
+#ifndef _I2S_H_
+#define _I2S_H_
+
+#if HAL_USE_I2S || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @name I2S modes
+ * @{
+ */
+#define I2S_MODE_SLAVE 0
+#define I2S_MODE_MASTER 1
+#define I2S_MODE_TX 2
+#define I2S_MODE_RX 4
+#define I2S_MODE_TXRX (I2S_MODE_TX | I2S_MODE_RX)
+/** @} */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Driver state machine possible states.
+ */
+typedef enum {
+ I2S_UNINIT = 0, /**< Not initialized. */
+ I2S_STOP = 1, /**< Stopped. */
+ I2S_READY = 2, /**< Ready. */
+ I2S_ACTIVE = 3, /**< Active. */
+ I2S_COMPLETE = 4 /**< Transmission complete. */
+} i2sstate_t;
+
+/**
+ * @brief Type of a structure representing a I2S driver.
+ */
+typedef struct I2SDriver I2SDriver;
+
+#include "i2s_lld.h"
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @name Macro Functions
+ * @{
+ */
+/**
+ * @brief Starts a I2S data exchange.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ *
+ * @iclass
+ */
+#define i2sStartExchangeI(i2sp) { \
+ i2s_lld_start_exchange(i2sp); \
+ (i2sp)->state = I2S_ACTIVE; \
+}
+
+/**
+ * @brief Starts a I2S data exchange in continuous mode.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ *
+ * @iclass
+ */
+#define i2sStartExchangeContinuousI(i2sp) { \
+ i2s_lld_start_exchange_continuous(i2sp); \
+ (i2sp)->state = I2S_ACTIVE; \
+}
+
+/**
+ * @brief Stops the ongoing data exchange.
+ * @details The ongoing data exchange, if any, is stopped, if the driver
+ * was not active the function does nothing.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ *
+ * @iclass
+ */
+#define i2sStopExchangeI(i2sp) { \
+ i2s_lld_stop_exchange(i2sp); \
+ (i2sp)->state = I2S_READY; \
+}
+
+/** @} */
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void i2sInit(void);
+ void i2sObjectInit(I2SDriver *i2sp);
+ void i2sStart(I2SDriver *i2sp, const I2SConfig *config);
+ void i2sStop(I2SDriver *i2sp);
+ void i2sStartExchange(I2SDriver *i2sp);
+ void i2sStopExchange(I2SDriver *i2sp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_I2S */
+
+#endif /* _I2S_H_ */
+
+/** @} */
diff --git a/os/hal/include/icu.h b/os/hal/include/icu.h index 99cfc4e3c..15a9b2380 100644 --- a/os/hal/include/icu.h +++ b/os/hal/include/icu.h @@ -157,6 +157,17 @@ typedef void (*icucallback_t)(ICUDriver *icup); if (previous_state != ICU_WAITING) \
(icup)->config->period_cb(icup); \
}
+
+/**
+ * @brief Common ISR code, ICU timer overflow event.
+ *
+ * @param[in] icup pointer to the @p ICUDriver object
+ *
+ * @notapi
+ */
+#define _icu_isr_invoke_overflow_cb(icup) { \
+ (icup)->config->overflow_cb(icup); \
+}
/** @} */
/*===========================================================================*/
diff --git a/os/hal/include/mii.h b/os/hal/include/mii.h index 0ae3a9b30..ef4acbd26 100644 --- a/os/hal/include/mii.h +++ b/os/hal/include/mii.h @@ -40,9 +40,12 @@ #define MII_ADVERTISE 0x04 /**< Advertisement control reg. */
#define MII_LPA 0x05 /**< Link partner ability reg. */
#define MII_EXPANSION 0x06 /**< Expansion register. */
+#define MII_ANNPTR 0x07 /**< 1000BASE-T control. */
#define MII_CTRL1000 0x09 /**< 1000BASE-T control. */
#define MII_STAT1000 0x0a /**< 1000BASE-T status. */
#define MII_ESTATUS 0x0f /**< Extended Status. */
+#define MII_PHYSTS 0x10 /**< PHY Status register. */
+#define MII_MICR 0x11 /**< MII Interrupt ctrl register. */
#define MII_DCOUNTER 0x12 /**< Disconnect counter. */
#define MII_FCSCOUNTER 0x13 /**< False carrier counter. */
#define MII_NWAYTEST 0x14 /**< N-way auto-neg test reg. */
@@ -52,14 +55,13 @@ #define MII_LBRERROR 0x18 /**< Lpback, rx, bypass error. */
#define MII_PHYADDR 0x19 /**< PHY address. */
#define MII_RESV2 0x1a /**< Reserved. */
-#define MII_TPISTATUS 0x1b /**< TPI status for 10mbps. */
+#define MII_TPISTATUS 0x1b /**< TPI status for 10Mbps. */
#define MII_NCONFIG 0x1c /**< Network interface config. */
/*
* Basic mode control register.
*/
-#define BMCR_RESV 0x003f /**< Unused. */
-#define BMCR_SPEED1000 0x0040 /**< MSB of Speed (1000). */
+#define BMCR_RESV 0x007f /**< Unused. */
#define BMCR_CTST 0x0080 /**< Collision test. */
#define BMCR_FULLDPLX 0x0100 /**< Full duplex. */
#define BMCR_ANRESTART 0x0200 /**< Auto negotiation restart. */
@@ -67,7 +69,7 @@ #define BMCR_PDOWN 0x0800 /**< Powerdown. */
#define BMCR_ANENABLE 0x1000 /**< Enable auto negotiation. */
#define BMCR_SPEED100 0x2000 /**< Select 100Mbps. */
-#define BMCR_LOOPBACK 0x4000 /**< TXD loopback bits. */
+#define BMCR_LOOPBACK 0x4000 /**< TXD loopback bit. */
#define BMCR_RESET 0x8000 /**< Reset. */
/*
@@ -79,10 +81,8 @@ #define BMSR_ANEGCAPABLE 0x0008 /**< Able to do auto-negotiation. */
#define BMSR_RFAULT 0x0010 /**< Remote fault detected. */
#define BMSR_ANEGCOMPLETE 0x0020 /**< Auto-negotiation complete. */
-#define BMSR_RESV 0x00c0 /**< Unused. */
-#define BMSR_ESTATEN 0x0100 /**< Extended Status in R15. */
-#define BMSR_100HALF2 0x0200 /**< Can do 100BASE-T2 HDX. */
-#define BMSR_100FULL2 0x0400 /**< Can do 100BASE-T2 FDX. */
+#define BMSR_MFPRESUPPCAP 0x0040 /**< Able to suppress preamble. */
+#define BMSR_RESV 0x0780 /**< Unused. */
#define BMSR_10HALF 0x0800 /**< Can do 10mbps, half-duplex. */
#define BMSR_10FULL 0x1000 /**< Can do 10mbps, full-duplex. */
#define BMSR_100HALF 0x2000 /**< Can do 100mbps, half-duplex. */
@@ -95,13 +95,9 @@ #define ADVERTISE_SLCT 0x001f /**< Selector bits. */
#define ADVERTISE_CSMA 0x0001 /**< Only selector supported. */
#define ADVERTISE_10HALF 0x0020 /**< Try for 10mbps half-duplex. */
-#define ADVERTISE_1000XFULL 0x0020 /**< Try for 1000BASE-X full-duplex.*/
#define ADVERTISE_10FULL 0x0040 /**< Try for 10mbps full-duplex. */
-#define ADVERTISE_1000XHALF 0x0040 /**< Try for 1000BASE-X half-duplex.*/
#define ADVERTISE_100HALF 0x0080 /**< Try for 100mbps half-duplex. */
-#define ADVERTISE_1000XPAUSE 0x0080 /**< Try for 1000BASE-X pause. */
#define ADVERTISE_100FULL 0x0100 /**< Try for 100mbps full-duplex. */
-#define ADVERTISE_1000XPSE_ASYM 0x0100 /**< Try for 1000BASE-X asym pause. */
#define ADVERTISE_100BASE4 0x0200 /**< Try for 100mbps 4k packets. */
#define ADVERTISE_PAUSE_CAP 0x0400 /**< Try for pause. */
#define ADVERTISE_PAUSE_ASYM 0x0800 /**< Try for asymetric pause. */
@@ -120,13 +116,9 @@ */
#define LPA_SLCT 0x001f /**< Same as advertise selector. */
#define LPA_10HALF 0x0020 /**< Can do 10mbps half-duplex. */
-#define LPA_1000XFULL 0x0020 /**< Can do 1000BASE-X full-duplex. */
#define LPA_10FULL 0x0040 /**< Can do 10mbps full-duplex. */
-#define LPA_1000XHALF 0x0040 /**< Can do 1000BASE-X half-duplex. */
#define LPA_100HALF 0x0080 /**< Can do 100mbps half-duplex. */
-#define LPA_1000XPAUSE 0x0080 /**< Can do 1000BASE-X pause. */
#define LPA_100FULL 0x0100 /**< Can do 100mbps full-duplex. */
-#define LPA_1000XPAUSE_ASYM 0x0100 /**< Can do 1000BASE-X pause asym. */
#define LPA_100BASE4 0x0200 /**< Can do 100mbps 4k packets. */
#define LPA_PAUSE_CAP 0x0400 /**< Can pause. */
#define LPA_PAUSE_ASYM 0x0800 /**< Can pause asymetrically. */
@@ -148,9 +140,6 @@ #define EXPANSION_MFAULTS 0x0010 /**< Multiple faults detected. */
#define EXPANSION_RESV 0xffe0 /**< Unused. */
-#define ESTATUS_1000_TFULL 0x2000 /**< Can do 1000BT Full. */
-#define ESTATUS_1000_THALF 0x1000 /**< Can do 1000BT Half. */
-
/*
* N-way test register.
*/
@@ -159,26 +148,13 @@ #define NWAYTEST_RESV2 0xfe00 /**< Unused. */
/*
- * 1000BASE-T Control register.
- */
-#define ADVERTISE_1000FULL 0x0200 /**< Advertise 1000BASE-T full duplex.*/
-#define ADVERTISE_1000HALF 0x0100 /**< Advertise 1000BASE-T half duplex.*/
-
-/*
- * 1000BASE-T Status register.
- */
-#define LPA_1000LOCALRXOK 0x2000 /**< Link partner local receiver status.*/
-#define LPA_1000REMRXOK 0x1000 /**< Link partner remote receiver status.*/
-#define LPA_1000FULL 0x0800 /**< Link partner 1000BASE-T full duplex.*/
-#define LPA_1000HALF 0x0400 /**< Link partner 1000BASE-T half duplex.*/
-
-/*
* PHY identifiers.
*/
#define MII_DM9161_ID 0x0181b8a0
#define MII_AM79C875_ID 0x00225540
#define MII_KS8721_ID 0x00221610
#define MII_STE101P_ID 0x00061C50
+#define MII_DP83848I_ID 0x20005C90
#endif /* _MII_H_ */
diff --git a/os/hal/include/sdc.h b/os/hal/include/sdc.h index aa02e4f5b..0e44361ff 100644 --- a/os/hal/include/sdc.h +++ b/os/hal/include/sdc.h @@ -113,7 +113,7 @@ */
/**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
@@ -254,6 +254,16 @@ typedef enum { #define sdcIsWriteProtected(sdcp) (sdc_lld_is_write_protected(sdcp))
/**
+ * @brief Returns the card capacity in blocks.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @return The card capacity.
+ *
+ * @api
+ */
+#define sdcGetCardCapacity(sdcp) ((sdcp)->capacity)
+
+/**
* @brief Slice position of values in CSD register.
*/
/* CSD version 2.0 */
diff --git a/os/hal/include/usb.h b/os/hal/include/usb.h index e261e9486..9e5eb1b62 100644 --- a/os/hal/include/usb.h +++ b/os/hal/include/usb.h @@ -323,11 +323,15 @@ typedef const USBDescriptor * (*usbgetdescriptor_t)(USBDriver *usbp, */
/**
* @brief Connects the USB device.
+ *
+ * @api
*/
#define usbConnectBus(usbp) usb_lld_connect_bus(usbp)
/**
* @brief Disconnect the USB device.
+ *
+ * @api
*/
#define usbDisconnectBus(usbp) usb_lld_disconnect_bus(usbp)
@@ -369,7 +373,7 @@ typedef const USBDescriptor * (*usbgetdescriptor_t)(USBDriver *usbp, /**
* @brief Reads from a dedicated packet buffer.
- * @pre In order to use this function he endpoint must have been
+ * @pre In order to use this function the endpoint must have been
* initialized in packet mode.
* @note This function can be invoked both in thread and IRQ context.
*
@@ -389,7 +393,7 @@ typedef const USBDescriptor * (*usbgetdescriptor_t)(USBDriver *usbp, /**
* @brief Writes to a dedicated packet buffer.
- * @pre In order to use this function he endpoint must have been
+ * @pre In order to use this function the endpoint must have been
* initialized in packet mode.
* @note This function can be invoked both in thread and IRQ context.
*
@@ -406,7 +410,7 @@ typedef const USBDescriptor * (*usbgetdescriptor_t)(USBDriver *usbp, /**
* @brief Prepares for a receive transaction on an OUT endpoint.
- * @pre In order to use this function he endpoint must have been
+ * @pre In order to use this function the endpoint must have been
* initialized in transaction mode.
* @post The endpoint is ready for @p usbStartReceiveI().
*
@@ -422,7 +426,7 @@ typedef const USBDescriptor * (*usbgetdescriptor_t)(USBDriver *usbp, /**
* @brief Prepares for a transmit transaction on an IN endpoint.
- * @pre In order to use this function he endpoint must have been
+ * @pre In order to use this function the endpoint must have been
* initialized in transaction mode.
* @post The endpoint is ready for @p usbStartTransmitI().
*
diff --git a/os/hal/platforms/AT91SAM7/ext_lld.c b/os/hal/platforms/AT91SAM7/ext_lld.c index fc362235e..98f08c9b8 100644 --- a/os/hal/platforms/AT91SAM7/ext_lld.c +++ b/os/hal/platforms/AT91SAM7/ext_lld.c @@ -146,7 +146,7 @@ void ext_lld_init(void) { #if (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \
(SAM7_PLATFORM == SAM7X512)
- /* Aame for PIOB.*/
+ /* Same for PIOB.*/
extObjectInit(&EXTDB);
EXTDB.pio = AT91C_BASE_PIOB;
EXTDB.pid = AT91C_ID_PIOB;
diff --git a/os/hal/platforms/AT91SAM7/mac_lld.c b/os/hal/platforms/AT91SAM7/mac_lld.c index b4555194b..dd1d6c6bd 100644 --- a/os/hal/platforms/AT91SAM7/mac_lld.c +++ b/os/hal/platforms/AT91SAM7/mac_lld.c @@ -324,7 +324,7 @@ msg_t max_lld_get_transmit_descriptor(MACDriver *macp, * @brief Writes to a transmit descriptor's stream.
*
* @param[in] tdp pointer to a @p MACTransmitDescriptor structure
- * @param[in] buf pointer to the buffer cointaining the data to be
+ * @param[in] buf pointer to the buffer containing the data to be
* written
* @param[in] size number of bytes to be written
* @return The number of bytes written into the descriptor's
diff --git a/os/hal/platforms/AT91SAM7/serial_lld.c b/os/hal/platforms/AT91SAM7/serial_lld.c index 6f1bbb1bf..d23aa9b0e 100644 --- a/os/hal/platforms/AT91SAM7/serial_lld.c +++ b/os/hal/platforms/AT91SAM7/serial_lld.c @@ -31,7 +31,8 @@ #if HAL_USE_SERIAL || defined(__DOXYGEN__)
-#if SAM7_PLATFORM == SAM7S256
+#if (SAM7_PLATFORM == SAM7S64) || (SAM7_PLATFORM == SAM7S128) || \
+ (SAM7_PLATFORM == SAM7S256) || (SAM7_PLATFORM == SAM7S512)
#define SAM7_USART0_RX AT91C_PA5_RXD0
#define SAM7_USART0_TX AT91C_PA6_TXD0
@@ -40,7 +41,8 @@ #define SAM7_DBGU_RX AT91C_PA9_DRXD
#define SAM7_DBGU_TX AT91C_PA10_DTXD
-#elif SAM7_PLATFORM == SAM7X256
+#elif (SAM7_PLATFORM == SAM7X128) || (SAM7_PLATFORM == SAM7X256) || \
+ (SAM7_PLATFORM == SAM7X512)
#define SAM7_USART0_RX AT91C_PA0_RXD0
#define SAM7_USART0_TX AT91C_PA1_TXD0
diff --git a/os/hal/platforms/AVR/serial_lld.h b/os/hal/platforms/AVR/serial_lld.h index bcaea51c1..f7bea9568 100644 --- a/os/hal/platforms/AVR/serial_lld.h +++ b/os/hal/platforms/AVR/serial_lld.h @@ -109,7 +109,7 @@ typedef struct { #define UBRR(b) (((F_CPU / b) >> 4) - 1)
/**
- * @brief Macro for baud rate computationwhen U2Xn == 1.
+ * @brief Macro for baud rate computation when U2Xn == 1.
* @note Make sure the final baud rate is within tolerance.
*/
#define UBRR2(b) (((F_CPU / b) >> 3) - 1)
diff --git a/os/hal/platforms/SPC56x/hal_lld.c b/os/hal/platforms/SPC56x/hal_lld.c index 3b8e8bc93..f5dec4516 100644 --- a/os/hal/platforms/SPC56x/hal_lld.c +++ b/os/hal/platforms/SPC56x/hal_lld.c @@ -70,7 +70,7 @@ void hal_lld_init(void) { /* Optimal crossbar settings. The DMA priority is placed above the CPU
priority in order to not starve I/O activities while the CPU is
- excuting tight loops (FLASH and SRAM slave ports only).
+ executing tight loops (FLASH and SRAM slave ports only).
The SRAM is parked on the load/store port, for some unknown reason it
is defaulted on the instructions port and this kills performance.*/
XBAR.SGPCR3.B.PARK = 4; /* RAM slave on load/store port.*/
diff --git a/os/hal/platforms/STM32/GPIOv2/pal_lld.c b/os/hal/platforms/STM32/GPIOv2/pal_lld.c index dfaa8da2f..dfe29dd17 100644 --- a/os/hal/platforms/STM32/GPIOv2/pal_lld.c +++ b/os/hal/platforms/STM32/GPIOv2/pal_lld.c @@ -50,7 +50,7 @@ RCC_AHB1ENR_GPIOIEN)
#define AHB1_LPEN_MASK AHB1_EN_MASK
#else
-#error "missing or usupported platform for GPIOv2 PAL driver"
+#error "missing or unsupported platform for GPIOv2 PAL driver"
#endif
/*===========================================================================*/
diff --git a/os/hal/platforms/STM32/OTGv1/stm32_otg.h b/os/hal/platforms/STM32/OTGv1/stm32_otg.h new file mode 100644 index 000000000..083f868a5 --- /dev/null +++ b/os/hal/platforms/STM32/OTGv1/stm32_otg.h @@ -0,0 +1,886 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file stm32_otg.h
+ * @brief STM32 OTG registers layout header.
+ *
+ * @addtogroup USB
+ * @{
+ */
+
+#ifndef _STM32_OTG_H_
+#define _STM32_OTG_H_
+
+/**
+ * @brief Number of the implemented endpoints.
+ * @details This value does not include the endpoint 0 that is always present.
+ */
+#define STM32_OTG_ENDOPOINTS_NUMBER 3
+
+/**
+ * @brief FIFO memory size in words.
+ */
+#define STM32_OTG_FIFO_MEM_SIZE 384
+
+/**
+ * @brief Host channel registers group.
+ */
+typedef struct {
+ volatile uint32_t HCCHAR; /**< @brief Host channel characteristics
+ register. */
+ volatile uint32_t resvd8;
+ volatile uint32_t HCINT; /**< @brief Host channel interrupt register.*/
+ volatile uint32_t HCINTMSK; /**< @brief Host channel interrupt mask
+ register. */
+ volatile uint32_t HCTSIZ; /**< @brief Host channel transfer size
+ register. */
+ volatile uint32_t resvd14;
+ volatile uint32_t resvd18;
+ volatile uint32_t resvd1c;
+} stm32_otg_host_chn_t;
+
+/**
+ * @brief Device input endpoint registers group.
+ */
+typedef struct {
+ volatile uint32_t DIEPCTL; /**< @brief Device control IN endpoint
+ control register. */
+ volatile uint32_t resvd4;
+ volatile uint32_t DIEPINT; /**< @brief Device IN endpoint interrupt
+ register. */
+ volatile uint32_t resvdC;
+ volatile uint32_t DIEPTSIZ; /**< @brief Device IN endpoint transfer size
+ register. */
+ volatile uint32_t resvd14;
+ volatile uint32_t DTXFSTS; /**< @brief Device IN endpoint transmit FIFO
+ status register. */
+ volatile uint32_t resvd1C;
+} stm32_otg_in_ep_t;
+
+/**
+ * @brief Device output endpoint registers group.
+ */
+typedef struct {
+ volatile uint32_t DOEPCTL; /**< @brief Device control OUT endpoint
+ control register. */
+ volatile uint32_t resvd4;
+ volatile uint32_t DOEPINT; /**< @brief Device OUT endpoint interrupt
+ register. */
+ volatile uint32_t resvdC;
+ volatile uint32_t DOEPTSIZ; /**< @brief Device OUT endpoint transfer
+ size register. */
+ volatile uint32_t resvd14;
+ volatile uint32_t resvd18;
+ volatile uint32_t resvd1C;
+} stm32_otg_out_ep_t;
+
+/**
+ * @brief USB registers memory map.
+ */
+typedef struct {
+ volatile uint32_t GOTGCTL; /**< @brief OTG control and status register.*/
+ volatile uint32_t GOTGINT; /**< @brief OTG interrupt register. */
+ volatile uint32_t GAHBCFG; /**< @brief AHB configuration register. */
+ volatile uint32_t GUSBCFG; /**< @brief USB configuration register. */
+ volatile uint32_t GRSTCTL; /**< @brief Reset register size. */
+ volatile uint32_t GINTSTS; /**< @brief Interrupt register. */
+ volatile uint32_t GINTMSK; /**< @brief Interrupt mask register. */
+ volatile uint32_t GRXSTSR; /**< @brief Receive status debug read
+ register. */
+ volatile uint32_t GRXSTSP; /**< @brief Receive status read/pop
+ register. */
+ volatile uint32_t GRXFSIZ; /**< @brief Receive FIFO size register. */
+ volatile uint32_t DIEPTXF0; /**< @brief Endpoint 0 transmit FIFO size
+ register. */
+ volatile uint32_t HNPTXSTS; /**< @brief Non-periodic transmit FIFO/queue
+ status register. */
+ volatile uint32_t resvd30;
+ volatile uint32_t resvd34;
+ volatile uint32_t GCCFG; /**< @brief General core configuration. */
+ volatile uint32_t CID; /**< @brief Core ID register. */
+ volatile uint32_t resvd58[48];
+ volatile uint32_t HPTXFSIZ; /**< @brief Host periodic transmit FIFO size
+ register. */
+ volatile uint32_t DIEPTXF[15];/**< @brief Device IN endpoint transmit FIFO
+ size registers. */
+ volatile uint32_t resvd140[176];
+ volatile uint32_t HCFG; /**< @brief Host configuration register. */
+ volatile uint32_t HFIR; /**< @brief Host frame interval register. */
+ volatile uint32_t HFNUM; /**< @brief Host frame number/frame time
+ Remaining register. */
+ volatile uint32_t resvd40C;
+ volatile uint32_t HPTXSTS; /**< @brief Host periodic transmit FIFO/queue
+ status register. */
+ volatile uint32_t HAINT; /**< @brief Host all channels interrupt
+ register. */
+ volatile uint32_t HAINTMSK; /**< @brief Host all channels interrupt mask
+ register. */
+ volatile uint32_t resvd41C[9];
+ volatile uint32_t HPRT; /**< @brief Host port control and status
+ register. */
+ volatile uint32_t resvd444[47];
+ stm32_otg_host_chn_t hc[16]; /**< @brief Host channels array. */
+ volatile uint32_t resvd700[64];
+ volatile uint32_t DCFG; /**< @brief Device configuration register. */
+ volatile uint32_t DCTL; /**< @brief Device control register. */
+ volatile uint32_t DSTS; /**< @brief Device status register. */
+ volatile uint32_t resvd80C;
+ volatile uint32_t DIEPMSK; /**< @brief Device IN endpoint common
+ interrupt mask register. */
+ volatile uint32_t DOEPMSK; /**< @brief Device OUT endpoint common
+ interrupt mask register. */
+ volatile uint32_t DAINT; /**< @brief Device all endpoints interrupt
+ register. */
+ volatile uint32_t DAINTMSK; /**< @brief Device all endpoints interrupt
+ mask register. */
+ volatile uint32_t resvd820;
+ volatile uint32_t resvd824;
+ volatile uint32_t DVBUSDIS; /**< @brief Device VBUS discharge time
+ register. */
+ volatile uint32_t DVBUSPULSE; /**< @brief Device VBUS pulsing time
+ register. */
+ volatile uint32_t resvd830;
+ volatile uint32_t DIEPEMPMSK; /**< @brief Device IN endpoint FIFO empty
+ interrupt mask register. */
+ volatile uint32_t resvd838;
+ volatile uint32_t resvd83C;
+ volatile uint32_t resvd840[16];
+ volatile uint32_t resvd880[16];
+ volatile uint32_t resvd8C0[16];
+ stm32_otg_in_ep_t ie[16]; /**< @brief Input endpoints. */
+ stm32_otg_out_ep_t oe[16]; /**< @brief Output endpoints. */
+ volatile uint32_t resvdD00[64];
+ volatile uint32_t PCGCCTL; /**< @brief Power and clock gating control
+ register. */
+ volatile uint32_t resvdE04[127];
+} stm32_otg_t;
+
+/**
+ * @name GOTGCTL register bit definitions
+ * @{
+ */
+#define GOTGCTL_BSVLD (1U<<19) /**< B-Session Valid. */
+#define GOTGCTL_ASVLD (1U<<18) /**< A-Session Valid. */
+#define GOTGCTL_DBCT (1U<<17) /**< Long/Short debounce time. */
+#define GOTGCTL_CIDSTS (1U<<16) /**< Connector ID status. */
+#define GOTGCTL_DHNPEN (1U<<11) /**< Device HNP enabled. */
+#define GOTGCTL_HSHNPEN (1U<<10) /**< Host Set HNP enable. */
+#define GOTGCTL_HNPRQ (1U<<9) /**< HNP request. */
+#define GOTGCTL_HNGSCS (1U<<8) /**< Host negotiation success. */
+#define GOTGCTL_SRQ (1U<<1) /**< Session request. */
+#define GOTGCTL_SRQSCS (1U<<0) /**< Session request success. */
+/** @} */
+
+/**
+ * @name GOTGINT register bit definitions
+ * @{
+ */
+#define GOTGINT_DBCDNE (1U<<19) /**< Debounce done. */
+#define GOTGINT_ADTOCHG (1U<<18) /**< A-Device timeout change. */
+#define GOTGINT_HNGDET (1U<<17) /**< Host negotiation detected. */
+#define GOTGINT_HNSSCHG (1U<<9) /**< Host negotiation success
+ status change. */
+#define GOTGINT_SRSSCHG (1U<<8) /**< Session request success
+ status change. */
+#define GOTGINT_SEDET (1U<<2) /**< Session end detected. */
+/** @} */
+
+/**
+ * @name GAHBCFG register bit definitions
+ * @{
+ */
+#define GAHBCFG_PTXFELVL (1U<<8) /**< Periodic TxFIFO empty
+ level. */
+#define GAHBCFG_TXFELVL (1U<<7) /**< Non-periodic TxFIFO empty
+ level. */
+#define GAHBCFG_GINTMSK (1U<<0) /**< Global interrupt mask. */
+/** @} */
+
+/**
+ * @name GUSBCFG register bit definitions
+ * @{
+ */
+#define GUSBCFG_CTXPKT (1U<<31) /**< Corrupt Tx packet. */
+#define GUSBCFG_FDMOD (1U<<30) /**< Force Device Mode. */
+#define GUSBCFG_FHMOD (1U<<29) /**< Force Host Mode. */
+#define GUSBCFG_TRDT_MASK (15U<<10) /**< USB Turnaround time field
+ mask. */
+#define GUSBCFG_TRDT(n) ((n)<<10) /**< USB Turnaround time field
+ value. */
+#define GUSBCFG_HNPCAP (1U<<9) /**< HNP-Capable. */
+#define GUSBCFG_SRPCAP (1U<<8) /**< SRP-Capable. */
+#define GUSBCFG_PHYSEL (1U<<6) /**< USB 2.0 High-Speed PHY or
+ USB 1.1 Full-Speed serial
+ transceiver Select. */
+#define GUSBCFG_TOCAL_MASK (7U<<0) /**< HS/FS timeout calibration
+ field mask. */
+#define GUSBCFG_TOCAL(n) ((n)<<0) /**< HS/FS timeout calibration
+ field value. */
+/** @} */
+
+/**
+ * @name GRSTCTL register bit definitions
+ * @{
+ */
+#define GRSTCTL_AHBIDL (1U<<31) /**< AHB Master Idle. */
+#define GRSTCTL_TXFNUM_MASK (31U<<6) /**< TxFIFO number field mask. */
+#define GRSTCTL_TXFNUM(n) ((n)<<6) /**< TxFIFO number field value. */
+#define GRSTCTL_TXFFLSH (1U<<5) /**< TxFIFO flush. */
+#define GRSTCTL_RXFFLSH (1U<<4) /**< RxFIFO flush. */
+#define GRSTCTL_FCRST (1U<<2) /**< Host frame counter reset. */
+#define GRSTCTL_HSRST (1U<<1) /**< HClk soft reset. */
+#define GRSTCTL_CSRST (1U<<0) /**< Core soft reset. */
+/** @} */
+
+/**
+ * @name GINTSTS register bit definitions
+ * @{
+ */
+#define GINTSTS_WKUPINT (1U<<31) /**< Resume/Remote wakeup
+ detected interrupt. */
+#define GINTSTS_SRQINT (1U<<30) /**< Session request/New session
+ detected interrupt. */
+#define GINTSTS_DISCINT (1U<<29) /**< Disconnect detected
+ interrupt. */
+#define GINTSTS_CIDSCHG (1U<<28) /**< Connector ID status change.*/
+#define GINTSTS_PTXFE (1U<<26) /**< Periodic TxFIFO empty. */
+#define GINTSTS_HCINT (1U<<25) /**< Host channels interrupt. */
+#define GINTSTS_HPRTINT (1U<<24) /**< Host port interrupt. */
+#define GINTSTS_IPXFR (1U<<21) /**< Incomplete periodic
+ transfer. */
+#define GINTSTS_IISOOXFR (1U<<21) /**< Incomplete isochronous OUT
+ transfer. */
+#define GINTSTS_IISOIXFR (1U<<20) /**< Incomplete isochronous IN
+ transfer. */
+#define GINTSTS_OEPINT (1U<<19) /**< OUT endpoints interrupt. */
+#define GINTSTS_IEPINT (1U<<18) /**< IN endpoints interrupt. */
+#define GINTSTS_EOPF (1U<<15) /**< End of periodic frame
+ interrupt. */
+#define GINTSTS_ISOODRP (1U<<14) /**< Isochronous OUT packet
+ dropped interrupt. */
+#define GINTSTS_ENUMDNE (1U<<13) /**< Enumeration done. */
+#define GINTSTS_USBRST (1U<<12) /**< USB reset. */
+#define GINTSTS_USBSUSP (1U<<11) /**< USB suspend. */
+#define GINTSTS_ESUSP (1U<<10) /**< Early suspend. */
+#define GINTSTS_GONAKEFF (1U<<7) /**< Global OUT NAK effective. */
+#define GINTSTS_GINAKEFF (1U<<6) /**< Global IN non-periodic NAK
+ effective. */
+#define GINTSTS_NPTXFE (1U<<5) /**< Non-periodic TxFIFO empty. */
+#define GINTSTS_RXFLVL (1U<<4) /**< RxFIFO non-empty. */
+#define GINTSTS_SOF (1U<<3) /**< Start of frame. */
+#define GINTSTS_OTGINT (1U<<2) /**< OTG interrupt. */
+#define GINTSTS_MMIS (1U<<1) /**< Mode Mismatch interrupt. */
+#define GINTSTS_CMOD (1U<<0) /**< Current mode of operation. */
+/** @} */
+
+/**
+ * @name GINTMSK register bit definitions
+ * @{
+ */
+#define GINTMSK_WKUM (1U<<31) /**< Resume/remote wakeup
+ detected interrupt mask. */
+#define GINTMSK_SRQM (1U<<30) /**< Session request/New session
+ detected interrupt mask. */
+#define GINTMSK_DISCM (1U<<29) /**< Disconnect detected
+ interrupt mask. */
+#define GINTMSK_CIDSCHGM (1U<<28) /**< Connector ID status change
+ mask. */
+#define GINTMSK_PTXFEM (1U<<26) /**< Periodic TxFIFO empty mask.*/
+#define GINTMSK_HCM (1U<<25) /**< Host channels interrupt
+ mask. */
+#define GINTMSK_HPRTM (1U<<24) /**< Host port interrupt mask. */
+#define GINTMSK_IPXFRM (1U<<21) /**< Incomplete periodic
+ transfer mask. */
+#define GINTMSK_IISOOXFRM (1U<<21) /**< Incomplete isochronous OUT
+ transfer mask. */
+#define GINTMSK_IISOIXFRM (1U<<20) /**< Incomplete isochronous IN
+ transfer mask. */
+#define GINTMSK_OEPM (1U<<19) /**< OUT endpoints interrupt
+ mask. */
+#define GINTMSK_IEPM (1U<<18) /**< IN endpoints interrupt
+ mask. */
+#define GINTMSK_EOPFM (1U<<15) /**< End of periodic frame
+ interrupt mask. */
+#define GINTMSK_ISOODRPM (1U<<14) /**< Isochronous OUT packet
+ dropped interrupt mask. */
+#define GINTMSK_ENUMDNEM (1U<<13) /**< Enumeration done mask. */
+#define GINTMSK_USBRSTM (1U<<12) /**< USB reset mask. */
+#define GINTMSK_USBSUSPM (1U<<11) /**< USB suspend mask. */
+#define GINTMSK_ESUSPM (1U<<10) /**< Early suspend mask. */
+#define GINTMSK_GONAKEFFM (1U<<7) /**< Global OUT NAK effective
+ mask. */
+#define GINTMSK_GINAKEFFM (1U<<6) /**< Global non-periodic IN NAK
+ effective mask. */
+#define GINTMSK_NPTXFEM (1U<<5) /**< Non-periodic TxFIFO empty
+ mask. */
+#define GINTMSK_RXFLVLM (1U<<4) /**< Receive FIFO non-empty
+ mask. */
+#define GINTMSK_SOFM (1U<<3) /**< Start of (micro)frame mask.*/
+#define GINTMSK_OTGM (1U<<2) /**< OTG interrupt mask. */
+#define GINTMSK_MMISM (1U<<1) /**< Mode Mismatch interrupt
+ mask. */
+/** @} */
+
+/**
+ * @name GRXSTSR register bit definitions
+ * @{
+ */
+#define GRXSTSR_PKTSTS_MASK (15U<<17) /**< Packet status mask. */
+#define GRXSTSR_PKTSTS(n) ((n)<<17) /**< Packet status value. */
+#define GRXSTSR_OUT_GLOBAL_NAK GRXSTSR_PKTSTS(1)
+#define GRXSTSR_OUT_DATA GRXSTSR_PKTSTS(2)
+#define GRXSTSR_OUT_COMP GRXSTSR_PKTSTS(3)
+#define GRXSTSR_SETUP_COMP GRXSTSR_PKTSTS(4)
+#define GRXSTSR_SETUP_DATA GRXSTSR_PKTSTS(6)
+#define GRXSTSR_DPID_MASK (3U<<15) /**< Data PID mask. */
+#define GRXSTSR_DPID(n) ((n)<<15) /**< Data PID value. */
+#define GRXSTSR_BCNT_MASK (0x7FF<<4) /**< Byte count mask. */
+#define GRXSTSR_BCNT(n) ((n)<<4) /**< Byte count value. */
+#define GRXSTSR_CHNUM_MASK (15U<<0) /**< Channel number mask. */
+#define GRXSTSR_CHNUM(n) ((n)<<0) /**< Channel number value. */
+#define GRXSTSR_EPNUM_MASK (15U<<0) /**< Endpoint number mask. */
+#define GRXSTSR_EPNUM(n) ((n)<<0) /**< Endpoint number value. */
+/** @} */
+
+/**
+ * @name GRXSTSP register bit definitions
+ * @{
+ */
+#define GRXSTSP_PKTSTS_MASK (15<<17) /**< Packet status mask. */
+#define GRXSTSP_PKTSTS(n) ((n)<<17) /**< Packet status value. */
+#define GRXSTSP_OUT_GLOBAL_NAK GRXSTSP_PKTSTS(1)
+#define GRXSTSP_OUT_DATA GRXSTSP_PKTSTS(2)
+#define GRXSTSP_OUT_COMP GRXSTSP_PKTSTS(3)
+#define GRXSTSP_SETUP_COMP GRXSTSP_PKTSTS(4)
+#define GRXSTSP_SETUP_DATA GRXSTSP_PKTSTS(6)
+#define GRXSTSP_DPID_MASK (3U<<15) /**< Data PID mask. */
+#define GRXSTSP_DPID(n) ((n)<<15) /**< Data PID value. */
+#define GRXSTSP_BCNT_MASK (0x7FF<<4) /**< Byte count mask. */
+#define GRXSTSP_BCNT_OFF 4 /**< Byte count offset. */
+#define GRXSTSP_BCNT(n) ((n)<<4) /**< Byte count value. */
+#define GRXSTSP_CHNUM_MASK (15U<<0) /**< Channel number mask. */
+#define GRXSTSP_CHNUM(n) ((n)<<0) /**< Channel number value. */
+#define GRXSTSP_EPNUM_MASK (15U<<0) /**< Endpoint number mask. */
+#define GRXSTSP_EPNUM_OFF 0 /**< Endpoint number offset. */
+#define GRXSTSP_EPNUM(n) ((n)<<0) /**< Endpoint number value. */
+/** @} */
+
+/**
+ * @name GRXFSIZ register bit definitions
+ * @{
+ */
+#define GRXFSIZ_RXFD_MASK (0xFFFF<<0) /**< RxFIFO depth mask. */
+#define GRXFSIZ_RXFD(n) ((n)<<0) /**< RxFIFO depth value. */
+/** @} */
+
+/**
+ * @name DIEPTXFx register bit definitions
+ * @{
+ */
+#define DIEPTXF_INEPTXFD_MASK (0xFFFFU<<16)/**< IN endpoint TxFIFO depth
+ mask. */
+#define DIEPTXF_INEPTXFD(n) ((n)<<16) /**< IN endpoint TxFIFO depth
+ value. */
+#define DIEPTXF_INEPTXSA_MASK (0xFFFF<<0) /**< IN endpoint FIFOx transmit
+ RAM start address mask. */
+#define DIEPTXF_INEPTXSA(n) ((n)<<0) /**< IN endpoint FIFOx transmit
+ RAM start address value. */
+/** @} */
+
+/**
+ * @name GCCFG register bit definitions
+ * @{
+ */
+#define GCCFG_SOFOUTEN (1U<<20) /**< SOF output enable. */
+#define GCCFG_VBUSBSEN (1U<<19) /**< Enable the VBUS sensing "B"
+ device. */
+#define GCCFG_VBUSASEN (1U<<18) /**< Enable the VBUS sensing "A"
+ device. */
+#define GCCFG_PWRDWN (1U<<16) /**< Power down. */
+/** @} */
+
+/**
+ * @name HPTXFSIZ register bit definitions
+ * @{
+ */
+#define HPTXFSIZ_PTXFD_MASK (0xFFFFU<<16)/**< Host periodic TxFIFO
+ depth mask. */
+#define HPTXFSIZ_PTXFD(n) ((n)<<16) /**< Host periodic TxFIFO
+ depth value. */
+#define HPTXFSIZ_PTXSA_MASK (0xFFFFU<<0)/**< Host periodic TxFIFO
+ Start address mask. */
+#define HPTXFSIZ_PTXSA(n) ((n)<<0) /**< Host periodic TxFIFO
+ start address value. */
+/** @} */
+
+/**
+ * @name HCFG register bit definitions
+ * @{
+ */
+#define HCFG_FSLSS (1U<<2) /**< FS- and LS-only support. */
+#define HCFG_FSLSPCS_MASK (3U<<0) /**< FS/LS PHY clock select
+ mask. */
+#define HCFG_FSLSPCS_48 (1U<<0) /**< PHY clock is running at
+ 48 MHz. */
+#define HCFG_FSLSPCS_6 (2U<<0) /**< PHY clock is running at
+ 6 MHz. */
+/** @} */
+
+/**
+ * @name HFIR register bit definitions
+ * @{
+ */
+#define HFIR_FRIVL_MASK (0xFFFFU<<0)/**< Frame interval mask. */
+#define HFIR_FRIVL(n) ((n)<<0) /**< Frame interval value. */
+/** @} */
+
+/**
+ * @name HFNUM register bit definitions
+ * @{
+ */
+#define HFNUM_FTREM_MASK (0xFFFFU<<16)/**< Frame time Remaining mask.*/
+#define HFNUM_FTREM(n) ((n)<<16) /**< Frame time Remaining value.*/
+#define HFNUM_FRNUM_MASK (0xFFFFU<<0)/**< Frame number mask. */
+#define HFNUM_FRNUM(n) ((n)<<0) /**< Frame number value. */
+/** @} */
+
+/**
+ * @name HPTXSTS register bit definitions
+ * @{
+ */
+#define HPTXSTS_PTXQTOP_MASK (0xFFU<<24) /**< Top of the periodic
+ transmit request queue
+ mask. */
+#define HPTXSTS_PTXQTOP(n) ((n)<<24) /**< Top of the periodic
+ transmit request queue
+ value. */
+#define HPTXSTS_PTXQSAV_MASK (0xFF<<16) /**< Periodic transmit request
+ queue Space Available
+ mask. */
+#define HPTXSTS_PTXQSAV(n) ((n)<<16) /**< Periodic transmit request
+ queue Space Available
+ value. */
+#define HPTXSTS_PTXFSAVL_MASK (0xFFFF<<0) /**< Periodic transmit Data
+ FIFO Space Available
+ mask. */
+#define HPTXSTS_PTXFSAVL(n) ((n)<<0) /**< Periodic transmit Data
+ FIFO Space Available
+ value. */
+/** @} */
+
+/**
+ * @name HAINT register bit definitions
+ * @{
+ */
+#define HAINT_HAINT_MASK (0xFFFFU<<0)/**< Channel interrupts mask. */
+#define HAINT_HAINT(n) ((n)<<0) /**< Channel interrupts value. */
+/** @} */
+
+/**
+ * @name HAINTMSK register bit definitions
+ * @{
+ */
+#define HAINTMSK_HAINTM_MASK (0xFFFFU<<0)/**< Channel interrupt mask
+ mask. */
+#define HAINTMSK_HAINTM(n) ((n)<<0) /**< Channel interrupt mask
+ value. */
+/** @} */
+
+/**
+ * @name HPRT register bit definitions
+ * @{
+ */
+#define HPRT_PSPD_MASK (3U<<17) /**< Port speed mask. */
+#define HPRT_PSPD_FS (1U<<17) /**< Full speed value. */
+#define HPRT_PSPD_LS (2U<<17) /**< Low speed value. */
+#define HPRT_PTCTL_MASK (15<<13) /**< Port Test control mask. */
+#define HPRT_PTCTL(n) ((n)<<13) /**< Port Test control value. */
+#define HPRT_PPWR (1U<<12) /**< Port power. */
+#define HPRT_PLSTS_MASK (3U<<11) /**< Port Line status mask. */
+#define HPRT_PLSTS_DM (1U<<11) /**< Logic level of D-. */
+#define HPRT_PLSTS_DP (1U<<10) /**< Logic level of D+. */
+#define HPRT_PRST (1U<<8) /**< Port reset. */
+#define HPRT_PSUSP (1U<<7) /**< Port suspend. */
+#define HPRT_PRES (1U<<6) /**< Port Resume. */
+#define HPRT_POCCHNG (1U<<5) /**< Port overcurrent change. */
+#define HPRT_POCA (1U<<4) /**< Port overcurrent active. */
+#define HPRT_PENCHNG (1U<<3) /**< Port enable/disable change.*/
+#define HPRT_PENA (1U<<2) /**< Port enable. */
+#define HPRT_PCDET (1U<<1) /**< Port Connect detected. */
+#define HPRT_PCSTS (1U<<0) /**< Port connect status. */
+/** @} */
+
+/**
+ * @name HCCHAR register bit definitions
+ * @{
+ */
+#define HCCHAR_CHENA (1U<<31) /**< Channel enable. */
+#define HCCHAR_CHDIS (1U<<30) /**< Channel Disable. */
+#define HCCHAR_ODDFRM (1U<<29) /**< Odd frame. */
+#define HCCHAR_DAD_MASK (0x7FU<<22) /**< Device Address mask. */
+#define HCCHAR_DAD(n) ((n)<<22) /**< Device Address value. */
+#define HCCHAR_MCNT_MASK (3U<<20) /**< Multicount mask. */
+#define HCCHAR_MCNT(n) ((n)<<20) /**< Multicount value. */
+#define HCCHAR_EPTYP_MASK (3U<<18) /**< Endpoint type mask. */
+#define HCCHAR_EPTYP(n) ((n)<<18) /**< Endpoint type value. */
+#define HCCHAR_EPTYP_CTL (0U<<18) /**< Control endpoint value. */
+#define HCCHAR_EPTYP_ISO (1U<<18) /**< Isochronous endpoint value.*/
+#define HCCHAR_EPTYP_BULK (2U<<18) /**< Bulk endpoint value. */
+#define HCCHAR_EPTYP_INTR (3U<<18) /**< Interrupt endpoint value. */
+#define HCCHAR_LSDEV (1U<<17) /**< Low-Speed device. */
+#define HCCHAR_EPDIR (1U<<15) /**< Endpoint direction. */
+#define HCCHAR_EPNUM_MASK (15U<<11) /**< Endpoint number mask. */
+#define HCCHAR_EPNUM(n) ((n)<<11) /**< Endpoint number value. */
+#define HCCHAR_MPS_MASK (11U<<0) /**< Maximum packet size mask. */
+#define HCCHAR_MPS(n) (11U<<0) /**< Maximum packet size value. */
+/** @} */
+
+/**
+ * @name HCINT register bit definitions
+ * @{
+ */
+#define HCINT_DTERR (1U<<10) /**< Data toggle error. */
+#define HCINT_FRMOR (1U<<9) /**< Frame overrun. */
+#define HCINT_BBERR (1U<<8) /**< Babble error. */
+#define HCINT_TRERR (1U<<7) /**< Transaction Error. */
+#define HCINT_ACK (1U<<5) /**< ACK response
+ received/transmitted
+ interrupt. */
+#define HCINT_NAK (1U<<4) /**< NAK response received
+ interrupt. */
+#define HCINT_STALL (1U<<3) /**< STALL response received
+ interrupt. */
+#define HCINT_CHH (1U<<1) /**< Channel halted. */
+#define HCINT_XFRC (1U<<0) /**< Transfer completed. */
+/** @} */
+
+/**
+ * @name HCINTMSK register bit definitions
+ * @{
+ */
+#define HCINTMSK_DTERRM (1U<<10) /**< Data toggle error mask. */
+#define HCINTMSK_FRMORM (1U<<9) /**< Frame overrun mask. */
+#define HCINTMSK_BBERRM (1U<<8) /**< Babble error mask. */
+#define HCINTMSK_TRERRM (1U<<7) /**< Transaction error mask. */
+#define HCINTMSK_NYET (1U<<6) /**< NYET response received
+ interrupt mask. */
+#define HCINTMSK_ACKM (1U<<5) /**< ACK Response
+ received/transmitted
+ interrupt mask. */
+#define HCINTMSK_NAKM (1U<<4) /**< NAK response received
+ interrupt mask. */
+#define HCINTMSK_STALLM (1U<<3) /**< STALL response received
+ interrupt mask. */
+#define HCINTMSK_CHHM (1U<<1) /**< Channel halted mask. */
+#define HCINTMSK_XFRCM (1U<<0) /**< Transfer completed mask. */
+/** @} */
+
+/**
+ * @name HCTSIZ register bit definitions
+ * @{
+ */
+#define HCTSIZ_DPID_MASK (3U<<29) /**< PID mask. */
+#define HCTSIZ_DPID_DATA0 (0U<<29) /**< DATA0. */
+#define HCTSIZ_DPID_DATA2 (1U<<29) /**< DATA2. */
+#define HCTSIZ_DPID_DATA1 (2U<<29) /**< DATA1. */
+#define HCTSIZ_DPID_MDATA (3U<<29) /**< MDATA. */
+#define HCTSIZ_PKTCNT_MASK (0x3FFU<<19)/**< Packet count mask. */
+#define HCTSIZ_PKTCNT(n) ((n)<<19) /**< Packet count value. */
+#define HCTSIZ_XFRSIZ_MASK (0x7FFFF<<0)/**< Transfer size mask. */
+#define HCTSIZ_XFRSIZ(n) ((n)<<0) /**< Transfer size value. */
+/** @} */
+
+/**
+ * @name DCFG register bit definitions
+ * @{
+ */
+#define DCFG_PFIVL_MASK (3U<<11) /**< Periodic frame interval
+ mask. */
+#define DCFG_PFIVL(n) ((n)<<11) /**< Periodic frame interval
+ value. */
+#define DCFG_DAD_MASK (0x7FU<<4) /**< Device address mask. */
+#define DCFG_DAD(n) ((n)<<4) /**< Device address value. */
+#define DCFG_NZLSOHSK (1U<<2) /**< Non-Zero-Length status
+ OUT handshake. */
+#define DCFG_DSPD_MASK (3U<<0) /**< Device speed mask. */
+#define DCFG_DSPD_FS11 (3U<<0) /**< Full speed (USB 1.1
+ transceiver clock is 48
+ MHz). */
+/** @} */
+
+/**
+ * @name DCTL register bit definitions
+ * @{
+ */
+#define DCTL_POPRGDNE (1U<<11) /**< Power-on programming done. */
+#define DCTL_CGONAK (1U<<10) /**< Clear global OUT NAK. */
+#define DCTL_SGONAK (1U<<9) /**< Set global OUT NAK. */
+#define DCTL_CGINAK (1U<<8) /**< Clear global non-periodic
+ IN NAK. */
+#define DCTL_SGINAK (1U<<7) /**< Set global non-periodic
+ IN NAK. */
+#define DCTL_TCTL_MASK (7U<<4) /**< Test control mask. */
+#define DCTL_TCTL(n) ((n)<<4 /**< Test control value. */
+#define DCTL_GONSTS (1U<<3) /**< Global OUT NAK status. */
+#define DCTL_GINSTS (1U<<2) /**< Global non-periodic IN
+ NAK status. */
+#define DCTL_SDIS (1U<<1) /**< Soft disconnect. */
+#define DCTL_RWUSIG (1U<<0) /**< Remote wakeup signaling. */
+/** @} */
+
+/**
+ * @name DSTS register bit definitions
+ * @{
+ */
+#define DSTS_FNSOF_MASK (0x3FFU<<8) /**< Frame number of the received
+ SOF mask. */
+#define DSTS_FNSOF(n) ((n)<<8) /**< Frame number of the received
+ SOF value. */
+#define DSTS_EERR (1U<<3) /**< Erratic error. */
+#define DSTS_ENUMSPD_MASK (3U<<1) /**< Enumerated speed mask. */
+#define DSTS_ENUMSPD_FS_48 (3U<<1) /**< Full speed (PHY clock is
+ running at 48 MHz). */
+#define DSTS_SUSPSTS (1U<<0) /**< Suspend status. */
+/** @} */
+
+/**
+ * @name DIEPMSK register bit definitions
+ * @{
+ */
+#define DIEPMSK_TXFEM (1U<<6) /**< Transmit FIFO empty mask. */
+#define DIEPMSK_INEPNEM (1U<<6) /**< IN endpoint NAK effective
+ mask. */
+#define DIEPMSK_ITTXFEMSK (1U<<4) /**< IN token received when
+ TxFIFO empty mask. */
+#define DIEPMSK_TOCM (1U<<3) /**< Timeout condition mask. */
+#define DIEPMSK_EPDM (1U<<1) /**< Endpoint disabled
+ interrupt mask. */
+#define DIEPMSK_XFRCM (1U<<0) /**< Transfer completed
+ interrupt mask. */
+/** @} */
+
+/**
+ * @name DOEPMSK register bit definitions
+ * @{
+ */
+#define DOEPMSK_OTEPDM (1U<<4) /**< OUT token received when
+ endpoint disabled mask. */
+#define DOEPMSK_STUPM (1U<<3) /**< SETUP phase done mask. */
+#define DOEPMSK_EPDM (1U<<1) /**< Endpoint disabled
+ interrupt mask. */
+#define DOEPMSK_XFRCM (1U<<0) /**< Transfer completed
+ interrupt mask. */
+/** @} */
+
+/**
+ * @name DAINT register bit definitions
+ * @{
+ */
+#define DAINT_OEPINT_MASK (0xFFFFU<<16)/**< OUT endpoint interrupt
+ bits mask. */
+#define DAINT_OEPINT(n) ((n)<<16) /**< OUT endpoint interrupt
+ bits value. */
+#define DAINT_IEPINT_MASK (0xFFFFU<<0)/**< IN endpoint interrupt
+ bits mask. */
+#define DAINT_IEPINT(n) ((n)<<0) /**< IN endpoint interrupt
+ bits value. */
+/** @} */
+
+/**
+ * @name DAINTMSK register bit definitions
+ * @{
+ */
+#define DAINTMSK_OEPM_MASK (0xFFFFU<<16)/**< OUT EP interrupt mask
+ bits mask. */
+#define DAINTMSK_OEPM(n) (1U<<(16+(n)))/**< OUT EP interrupt mask
+ bits value. */
+#define DAINTMSK_IEPM_MASK (0xFFFFU<<0)/**< IN EP interrupt mask
+ bits mask. */
+#define DAINTMSK_IEPM(n) (1U<<(n)) /**< IN EP interrupt mask
+ bits value. */
+/** @} */
+
+/**
+ * @name DVBUSDIS register bit definitions
+ * @{
+ */
+#define DVBUSDIS_VBUSDT_MASK (0xFFFFU<<0)/**< Device VBUS discharge
+ time mask. */
+#define DVBUSDIS_VBUSDT(n) ((n)<<0) /**< Device VBUS discharge
+ time value. */
+/** @} */
+
+/**
+ * @name DVBUSPULSE register bit definitions
+ * @{
+ */
+#define DVBUSPULSE_DVBUSP_MASK (0xFFFU<<0) /**< Device VBUSpulsing time
+ mask. */
+#define DVBUSPULSE_DVBUSP(n) ((n)<<0) /**< Device VBUS pulsing time
+ value. */
+/** @} */
+
+/**
+ * @name DIEPEMPMSK register bit definitions
+ * @{
+ */
+#define DIEPEMPMSK_INEPTXFEM(n) (1U<<(n)) /**< IN EP Tx FIFO empty
+ interrupt mask bit. */
+/** @} */
+
+/**
+ * @name DIEPCTL register bit definitions
+ * @{
+ */
+#define DIEPCTL_EPENA (1U<<31) /**< Endpoint enable. */
+#define DIEPCTL_EPDIS (1U<<30) /**< Endpoint disable. */
+#define DIEPCTL_SD1PID (1U<<29) /**< Set DATA1 PID. */
+#define DIEPCTL_SODDFRM (1U<<29) /**< Set odd frame. */
+#define DIEPCTL_SD0PID (1U<<28) /**< Set DATA0 PID. */
+#define DIEPCTL_SEVNFRM (1U<<28) /**< Set even frame. */
+#define DIEPCTL_SNAK (1U<<27) /**< Set NAK. */
+#define DIEPCTL_CNAK (1U<<26) /**< Clear NAK. */
+#define DIEPCTL_TXFNUM_MASK (15U<<22) /**< TxFIFO number mask. */
+#define DIEPCTL_TXFNUM(n) ((n)<<22) /**< TxFIFO number value. */
+#define DIEPCTL_STALL (1U<<21) /**< STALL handshake. */
+#define DIEPCTL_SNPM (1U<<20) /**< Snoop mode. */
+#define DIEPCTL_EPTYP_MASK (3<<18) /**< Endpoint type mask. */
+#define DIEPCTL_EPTYP_CTRL (0U<<18) /**< Control. */
+#define DIEPCTL_EPTYP_ISO (1U<<18) /**< Isochronous. */
+#define DIEPCTL_EPTYP_BULK (2U<<18) /**< Bulk. */
+#define DIEPCTL_EPTYP_INTR (3U<<18) /**< Interrupt. */
+#define DIEPCTL_NAKSTS (1U<<17) /**< NAK status. */
+#define DIEPCTL_EONUM (1U<<16) /**< Even/odd frame. */
+#define DIEPCTL_DPID (1U<<16) /**< Endpoint data PID. */
+#define DIEPCTL_USBAEP (1U<<15) /**< USB active endpoint. */
+#define DIEPCTL_MPSIZ_MASK (0x3FFU<<0) /**< Maximum Packet size mask. */
+#define DIEPCTL_MPSIZ(n) ((n)<<0) /**< Maximum Packet size value. */
+/** @} */
+
+/**
+ * @name DIEPINT register bit definitions
+ * @{
+ */
+#define DIEPINT_TXFE (1U<<7) /**< Transmit FIFO empty. */
+#define DIEPINT_INEPNE (1U<<6) /**< IN endpoint NAK effective. */
+#define DIEPINT_ITTXFE (1U<<4) /**< IN Token received when
+ TxFIFO is empty. */
+#define DIEPINT_TOC (1U<<3) /**< Timeout condition. */
+#define DIEPINT_EPDISD (1U<<1) /**< Endpoint disabled
+ interrupt. */
+#define DIEPINT_XFRC (1U<<0) /**< Transfer completed. */
+/** @} */
+
+/**
+ * @name DIEPTSIZ register bit definitions
+ * @{
+ */
+#define DIEPTSIZ_MCNT_MASK (3U<<29) /**< Multi count mask. */
+#define DIEPTSIZ_MCNT(n) ((n)<<29) /**< Multi count value. */
+#define DIEPTSIZ_PKTCNT_MASK (0x3FF<<19) /**< Packet count mask. */
+#define DIEPTSIZ_PKTCNT(n) ((n)<<19) /**< Packet count value. */
+#define DIEPTSIZ_XFRSIZ_MASK (0x7FFFFU<<0)/**< Transfer size mask. */
+#define DIEPTSIZ_XFRSIZ(n) ((n)<<0) /**< Transfer size value. */
+/** @} */
+
+/**
+ * @name DOEPCTL register bit definitions.
+ * @{
+ */
+#define DOEPCTL_EPENA (1U<<31) /**< Endpoint enable. */
+#define DOEPCTL_EPDIS (1U<<30) /**< Endpoint disable. */
+#define DOEPCTL_SD1PID (1U<<29) /**< Set DATA1 PID. */
+#define DOEPCTL_SODDFRM (1U<<29) /**< Set odd frame. */
+#define DOEPCTL_SD0PID (1U<<28) /**< Set DATA0 PID. */
+#define DOEPCTL_SEVNFRM (1U<<28) /**< Set even frame. */
+#define DOEPCTL_SNAK (1U<<27) /**< Set NAK. */
+#define DOEPCTL_CNAK (1U<<26) /**< Clear NAK. */
+#define DOEPCTL_STALL (1U<<21) /**< STALL handshake. */
+#define DOEPCTL_SNPM (1U<<20) /**< Snoop mode. */
+#define DOEPCTL_EPTYP_MASK (3U<<18) /**< Endpoint type mask. */
+#define DOEPCTL_EPTYP_CTRL (0U<<18) /**< Control. */
+#define DOEPCTL_EPTYP_ISO (1U<<18) /**< Isochronous. */
+#define DOEPCTL_EPTYP_BULK (2U<<18) /**< Bulk. */
+#define DOEPCTL_EPTYP_INTR (3U<<18) /**< Interrupt. */
+#define DOEPCTL_NAKSTS (1U<<17) /**< NAK status. */
+#define DOEPCTL_EONUM (1U<<16) /**< Even/odd frame. */
+#define DOEPCTL_DPID (1U<<16) /**< Endpoint data PID. */
+#define DOEPCTL_USBAEP (1U<<15) /**< USB active endpoint. */
+#define DOEPCTL_MPSIZ_MASK (0x3FFU<<0) /**< Maximum Packet size mask. */
+#define DOEPCTL_MPSIZ(n) ((n)<<0) /**< Maximum Packet size value. */
+/** @} */
+
+/**
+ * @name DOEPINT register bit definitions
+ * @{
+ */
+#define DOEPINT_B2BSTUP (1U<<6) /**< Back-to-back SETUP packets
+ received. */
+#define DOEPINT_OTEPDIS (1U<<4) /**< OUT token received when
+ endpoint disabled. */
+#define DOEPINT_STUP (1U<<3) /**< SETUP phase done. */
+#define DOEPINT_EPDISD (1U<<1) /**< Endpoint disabled
+ interrupt. */
+#define DOEPINT_XFRC (1U<<0) /**< Transfer completed
+ interrupt. */
+/** @} */
+
+/**
+ * @name DOEPTSIZ register bit definitions
+ * @{
+ */
+#define DOEPTSIZ_RXDPID_MASK (3U<<29) /**< Received data PID mask. */
+#define DOEPTSIZ_RXDPID(n) ((n)<<29) /**< Received data PID value. */
+#define DOEPTSIZ_PKTCNT_MASK (0x3FFU<<19)/**< Packet count mask. */
+#define DOEPTSIZ_PKTCNT(n) ((n)<<19) /**< Packet count value. */
+#define DOEPTSIZ_XFRSIZ_MASK (0x7FFFFU<<0)/**< Transfer size mask. */
+#define DOEPTSIZ_XFRSIZ(n) ((n)<<0) /**< Transfer size value. */
+/** @} */
+
+/**
+ * @name PCGCCTL register bit definitions
+ * @{
+ */
+#define PCGCCTL_PHYSUSP (1U<<4) /**< PHY Suspended. */
+#define PCGCCTL_GATEHCLK (1U<<1) /**< Gate HCLK. */
+#define PCGCCTL_STPPCLK (1U<<0) /**< Stop PCLK. */
+/** @} */
+
+/**
+ * @brief OTG registers block memory address.
+ */
+#define OTG_ADDR 0x50000000
+
+/**
+ * @brief Accesses to the OTG registers block.
+ */
+#define OTG ((stm32_otg_t *)OTG_ADDR)
+
+/**
+ * @brief Returns a FIFO address.
+ */
+#define OTG_FIFO(n) ((volatile uint32_t *)(OTG_ADDR + \
+ 0x1000 + \
+ (0x1000 * (n))))
+
+#endif /* _STM32_OTG_H_ */
+
+/** @} */
diff --git a/os/hal/platforms/STM32/OTGv1/usb_lld.c b/os/hal/platforms/STM32/OTGv1/usb_lld.c new file mode 100644 index 000000000..009d9712c --- /dev/null +++ b/os/hal/platforms/STM32/OTGv1/usb_lld.c @@ -0,0 +1,899 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file STM32/OTGv1/usb_lld.c
+ * @brief STM32 USB subsystem low level driver source.
+ *
+ * @addtogroup USB
+ * @{
+ */
+
+#include <string.h>
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_USB || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+#define TRDT_VALUE 5
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/** @brief OTG1 driver identifier.*/
+#if STM32_USB_USE_OTG1 || defined(__DOXYGEN__)
+USBDriver USBD1;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables. */
+/*===========================================================================*/
+
+/**
+ * @brief EP0 state.
+ * @note It is an union because IN and OUT endpoints are never used at the
+ * same time for EP0.
+ */
+static union {
+ /**
+ * @brief IN EP0 state.
+ */
+ USBInEndpointState in;
+ /**
+ * @brief OUT EP0 state.
+ */
+ USBOutEndpointState out;
+} ep0_state;
+
+/**
+ * @brief Buffer for the EP0 setup packets.
+ */
+static uint8_t ep8setup_buffer[8];
+
+/**
+ * @brief EP0 initialization structure.
+ */
+static const USBEndpointConfig ep0config = {
+ USB_EP_MODE_TYPE_CTRL | USB_EP_MODE_TRANSACTION,
+ _usb_ep0setup,
+ _usb_ep0in,
+ _usb_ep0out,
+ 0x40,
+ 0x40,
+ &ep0_state.in,
+ &ep0_state.out,
+ ep8setup_buffer
+};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static void otg_core_reset(void) {
+
+ /* Wait AHB idle condition.*/
+ while ((OTG->GRSTCTL & GRSTCTL_AHBIDL) == 0)
+ ;
+ /* Core reset and delay of at least 3 PHY cycles.*/
+ OTG->GRSTCTL = GRSTCTL_CSRST;
+ while ((OTG->GRSTCTL & GRSTCTL_CSRST) != 0)
+ ;
+ halPolledDelay(12);
+}
+
+static void otg_disable_ep(void) {
+ unsigned i;
+
+ for (i = 0; i <= USB_MAX_ENDPOINTS; i++) {
+ /* Disable only if enabled because this sentence in the manual:
+ "The application must set this bit only if Endpoint Enable is
+ already set for this endpoint".*/
+ if ((OTG->ie[i].DIEPCTL & DIEPCTL_EPENA) != 0) {
+ OTG->ie[i].DIEPCTL = DIEPCTL_EPDIS;
+ /* Wait for endpoint disable.*/
+ while (!(OTG->ie[i].DIEPINT & DIEPINT_EPDISD))
+ ;
+ }
+ else
+ OTG->ie[i].DIEPCTL = 0;
+ OTG->ie[i].DIEPTSIZ = 0;
+ OTG->ie[i].DIEPINT = 0xFFFFFFFF;
+ /* Disable only if enabled because this sentence in the manual:
+ "The application must set this bit only if Endpoint Enable is
+ already set for this endpoint".
+ Note that the attempt to disable the OUT EP0 is ignored by the
+ hardware but the code is simpler this way.*/
+ if ((OTG->oe[i].DOEPCTL & DOEPCTL_EPENA) != 0) {
+ OTG->oe[i].DOEPCTL = DOEPCTL_EPDIS;
+ /* Wait for endpoint disable.*/
+ while (!(OTG->oe[i].DOEPINT & DOEPINT_OTEPDIS))
+ ;
+ }
+ else
+ OTG->oe[i].DOEPCTL = 0;
+ OTG->oe[i].DOEPTSIZ = 0;
+ OTG->oe[i].DOEPINT = 0xFFFFFFFF;
+ }
+}
+
+static void otg_rxfifo_flush(void) {
+
+ OTG->GRSTCTL = GRSTCTL_RXFFLSH;
+ while ((OTG->GRSTCTL & GRSTCTL_RXFFLSH) != 0)
+ ;
+}
+
+static void otg_txfifo_flush(uint32_t fifo) {
+
+ OTG->GRSTCTL = GRSTCTL_TXFNUM(fifo) | GRSTCTL_TXFFLSH;
+ while ((OTG->GRSTCTL & GRSTCTL_TXFFLSH) != 0)
+ ;
+}
+
+/**
+ * @brief Resets the FIFO RAM memory allocator.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+static void otg_ram_reset(USBDriver *usbp) {
+
+ usbp->pmnext = STM32_USB_OTG1_RX_FIFO_SIZE / 4;
+}
+
+/**
+ * @brief Allocates a block from the FIFO RAM memory.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] size size of the packet buffer to allocate in words
+ *
+ * @notapi
+ */
+static uint32_t otg_ram_alloc(USBDriver *usbp, size_t size) {
+ uint32_t next;
+
+ next = usbp->pmnext;
+ usbp->pmnext += size;
+ chDbgAssert(usbp->pmnext <= STM32_OTG_FIFO_MEM_SIZE,
+ "otg_fifo_alloc(), #1", "FIFO memory overflow");
+ return next;
+}
+
+/**
+ * @brief Writes to a TX FIFO.
+ *
+ * @param[in] ep endpoint number
+ * @param[in] buf buffer where to copy the endpoint data
+ * @param[in] n maximum number of bytes to copy
+ * @return the number of bytes that were effectively written
+ *
+ * @notapi
+ */
+static void otg_fifo_write(usbep_t ep, const uint8_t *buf, size_t n) {
+ volatile uint32_t *fifop;
+
+ fifop = OTG_FIFO(ep);
+ n = (n + 3) / 4;
+ while (n) {
+ uint32_t dw = (uint32_t)buf[0] |
+ ((uint32_t)buf[1] << 8) |
+ ((uint32_t)buf[2] << 16) |
+ ((uint32_t)buf[3] << 24);
+ *fifop = dw;
+ n--;
+ buf += 4;
+ }
+}
+
+/**
+ * @brief Reads a packet from the RXFIFO.
+ *
+ * @param[out] buf buffer where to copy the endpoint data
+ * @param[in] n number of bytes to pull from the FIFO
+ * @param[in] max number of bytes to copy into the buffer
+ *
+ * @notapi
+ */
+static void otg_fifo_read(uint8_t *buf, size_t n, size_t max) {
+ volatile uint32_t *fifop;
+
+ fifop = OTG_FIFO(0);
+ n = (n + 3) / 4;
+ max = (max + 3) / 4;
+ while (n) {
+ uint32_t dw = *fifop;
+ if (max) {
+ *buf++ = (uint8_t)dw;
+ *buf++ = (uint8_t)(dw >> 8);
+ *buf++ = (uint8_t)(dw >> 16);
+ *buf++ = (uint8_t)(dw >> 24);
+ max--;
+ }
+ n--;
+ }
+}
+
+/**
+ * @brief Incoming packets handler.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+static void otg_rxfifo_handler(USBDriver *usbp) {
+ uint32_t sts, cnt, ep;
+
+ sts = OTG->GRXSTSP;
+ switch (sts & GRXSTSP_PKTSTS_MASK) {
+ case GRXSTSP_SETUP_COMP:
+ break;
+ case GRXSTSP_SETUP_DATA:
+ cnt = (sts & GRXSTSP_BCNT_MASK) >> GRXSTSP_BCNT_OFF;
+ ep = (sts & GRXSTSP_EPNUM_MASK) >> GRXSTSP_EPNUM_OFF;
+ otg_fifo_read(usbp->epc[ep]->setup_buf, cnt, 8);
+ break;
+ case GRXSTSP_OUT_DATA:
+ cnt = (sts & GRXSTSP_BCNT_MASK) >> GRXSTSP_BCNT_OFF;
+ ep = (sts & GRXSTSP_EPNUM_MASK) >> GRXSTSP_EPNUM_OFF;
+ otg_fifo_read(usbp->epc[ep]->out_state->rxbuf, cnt,
+ usbp->epc[ep]->out_state->rxsize -
+ usbp->epc[ep]->out_state->rxcnt);
+ usbp->epc[ep]->out_state->rxbuf += cnt;
+ usbp->epc[ep]->out_state->rxcnt += cnt;
+ break;
+ case GRXSTSP_OUT_GLOBAL_NAK:
+ case GRXSTSP_OUT_COMP:
+ default:
+ ;
+ }
+}
+
+/**
+ * @brief Outgoing packets handler.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ *
+ * @notapi
+ */
+static void otg_txfifo_handler(USBDriver *usbp, usbep_t ep) {
+ uint32_t n;
+
+ n = usbp->epc[ep]->in_state->txsize - usbp->epc[ep]->in_state->txcnt;
+ if (n > usbp->epc[ep]->in_maxsize)
+ n = usbp->epc[ep]->in_maxsize;
+ OTG->ie[ep].DIEPCTL |= DIEPCTL_EPENA | DIEPCTL_CNAK;
+ otg_fifo_write(ep, usbp->epc[ep]->in_state->txbuf, n);
+ usbp->epc[ep]->in_state->txbuf += n;
+ usbp->epc[ep]->in_state->txcnt += n;
+ if (usbp->epc[ep]->in_state->txcnt >= usbp->epc[ep]->in_state->txsize) {
+ /* Transfer finished.*/
+ OTG->DIEPEMPMSK &= ~DIEPEMPMSK_INEPTXFEM(ep);
+ }
+}
+
+/**
+ * @brief Generic endpoint IN handler.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ *
+ * @notapi
+ */
+static void otg_epin_handler(USBDriver *usbp, usbep_t ep) {
+ uint32_t epint = OTG->ie[ep].DIEPINT;
+
+ if (epint & DIEPINT_TXFE) {
+ /* TX FIFO empty or emptying.*/
+ otg_txfifo_handler(usbp, ep);
+ }
+ if (epint & DIEPINT_XFRC) {
+ /* Transmit transfer complete.*/
+ _usb_isr_invoke_in_cb(usbp, ep);
+ }
+ if (epint & DIEPINT_TOC) {
+ /* Timeouts not handled yet, not sure how to handle.*/
+ }
+ OTG->ie[ep].DIEPINT = 0xFFFFFFFF;
+}
+
+/**
+ * @brief Generic endpoint OUT handler.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ *
+ * @notapi
+ */
+static void otg_epout_handler(USBDriver *usbp, usbep_t ep) {
+ uint32_t epint = OTG->oe[ep].DOEPINT;
+
+ /* Is it a setup packet?*/
+ if (epint & DOEPINT_STUP) {
+ /* Setup packets handling, setup packets are handled using a
+ specific callback.*/
+ _usb_isr_invoke_setup_cb(usbp, ep);
+ }
+ if (epint & DOEPINT_XFRC) {
+ /* Receive transfer complete.*/
+ _usb_isr_invoke_out_cb(usbp, ep);
+ }
+ OTG->oe[ep].DOEPINT = 0xFFFFFFFF;
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if STM32_USB_USE_OTG1 || defined(__DOXYGEN__)
+/**
+ * @brief OTG1 interrupt handler.
+ *
+ * @isr
+ */
+CH_IRQ_HANDLER(OTG_FS_IRQHandler) {
+ USBDriver *usbp = &USBD1;
+ uint32_t sts;
+
+ CH_IRQ_PROLOGUE();
+
+ sts = OTG->GINTSTS & OTG->GINTMSK;
+
+ /* Reset interrupt handling.*/
+ if (sts & GINTSTS_USBRST) {
+ _usb_reset(usbp);
+ _usb_isr_invoke_event_cb(usbp, USB_EVENT_RESET);
+ OTG->GINTSTS = GINTSTS_USBRST;
+ }
+
+ /* Enumeration done.*/
+ if (sts & GINTSTS_ENUMDNE) {
+ (void)OTG->DSTS;
+ OTG->GINTSTS = GINTSTS_ENUMDNE;
+ }
+
+ /* SOF interrupt handling.*/
+ if (sts & GINTSTS_SOF) {
+ _usb_isr_invoke_sof_cb(usbp);
+ OTG->GINTSTS = GINTSTS_SOF;
+ }
+
+ /* RX FIFO not empty handling.*/
+ if (sts & GINTMSK_RXFLVLM) {
+ otg_rxfifo_handler(usbp);
+ }
+
+ /* IN/OUT endpoints event handling, timeout and transfer complete events
+ are handled.*/
+ if (sts & (GINTSTS_IEPINT | GINTSTS_OEPINT)) {
+ uint32_t src = OTG->DAINT;
+ if (src & (1 << 0))
+ otg_epin_handler(usbp, 0);
+ if (src & (1 << 1))
+ otg_epin_handler(usbp, 1);
+ if (src & (1 << 2))
+ otg_epin_handler(usbp, 2);
+ if (src & (1 << 3))
+ otg_epin_handler(usbp, 3);
+ if (src & (1 << 16))
+ otg_epout_handler(usbp, 0);
+ if (src & (1 << 17))
+ otg_epout_handler(usbp, 1);
+ if (src & (1 << 18))
+ otg_epout_handler(usbp, 2);
+ if (src & (1 << 19))
+ otg_epout_handler(usbp, 3);
+ }
+
+ CH_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level USB driver initialization.
+ *
+ * @notapi
+ */
+void usb_lld_init(void) {
+
+ /* Driver initialization.*/
+ usbObjectInit(&USBD1);
+}
+
+/**
+ * @brief Configures and activates the USB peripheral.
+ * @note Starting the ORG cell can be a slow operation carried out with
+ * interrupts disabled, perform it before starting time-critical
+ * operations.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+void usb_lld_start(USBDriver *usbp) {
+
+ if (usbp->state == USB_STOP) {
+ /* Clock activation.*/
+#if STM32_USB_USE_OTG1
+ if (&USBD1 == usbp) {
+ /* OTG FS clock enable and reset.*/
+ rccEnableOTG_FS(FALSE);
+ rccResetOTG_FS();
+
+ /* Enables IRQ vector.*/
+ nvicEnableVector(OTG_FS_IRQn,
+ CORTEX_PRIORITY_MASK(STM32_USB_OTG1_IRQ_PRIORITY));
+ }
+#endif
+
+ /* Soft core reset.*/
+ otg_core_reset();
+
+ /* Internal FS PHY activation.*/
+ OTG->GCCFG = GCCFG_PWRDWN;
+
+ /* - Forced device mode.
+ - USB turn-around time = TRDT_VALUE.
+ - Full Speed 1.1 PHY.*/
+ OTG->GUSBCFG = GUSBCFG_FDMOD | GUSBCFG_TRDT(TRDT_VALUE) | GUSBCFG_PHYSEL;
+
+ /* Interrupt on TXFIFOs empty.*/
+ OTG->GAHBCFG = GAHBCFG_PTXFELVL | GAHBCFG_TXFELVL;
+
+ /* 48MHz 1.1 PHY.*/
+ OTG->DCFG = 0x02200000 | DCFG_PFIVL(0) | DCFG_DSPD_FS11;
+
+ /* PHY enabled.*/
+ OTG->PCGCCTL = 0;
+
+ /* Endpoints re-initialization.*/
+ otg_disable_ep();
+
+ /* Clear all pending Device Interrupts, only the USB Reset interrupt
+ is required initially.*/
+ OTG->DIEPMSK = 0;
+ OTG->DOEPMSK = 0;
+ OTG->DAINTMSK = 0;
+ OTG->GINTMSK = GINTMSK_ENUMDNEM | GINTMSK_USBRSTM | /*GINTMSK_USBSUSPM |
+ GINTMSK_ESUSPM |*/ GINTMSK_SOFM;
+ OTG->GINTSTS = 0xFFFFFFFF; /* Clears all pending IRQs, if any. */
+
+ /* Global interrupts enable.*/
+ OTG->GAHBCFG |= GAHBCFG_GINTMSK;
+ }
+}
+
+/**
+ * @brief Deactivates the USB peripheral.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+void usb_lld_stop(USBDriver *usbp) {
+
+ /* If in ready state then disables the USB clock.*/
+ if (usbp->state == USB_STOP) {
+#if STM32_USB_USE_USB1
+ if (&USBD1 == usbp) {
+ nvicDisableVector(OTG_FS_IRQn);
+ rccDisableOTG1(FALSE);
+ }
+#endif
+ }
+ OTG->GCCFG = 0;
+}
+
+/**
+ * @brief USB low level reset routine.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+void usb_lld_reset(USBDriver *usbp) {
+ unsigned i;
+
+ /* Endpoint interrupts all disabled and cleared.*/
+ OTG->DAINTMSK = 0;
+ OTG->DAINT = 0xFFFFFFFF;
+
+ /* All endpoints in NAK mode, interrupts cleared.*/
+ for (i = 0; i <= USB_MAX_ENDPOINTS; i++) {
+ OTG->ie[i].DIEPCTL = DIEPCTL_SNAK;
+ OTG->oe[i].DOEPCTL = DOEPCTL_SNAK;
+ OTG->ie[i].DIEPINT = 0xFFFFFFFF;
+ OTG->oe[i].DOEPINT = 0xFFFFFFFF;
+ }
+
+ /* Resets the FIFO memory allocator.*/
+ otg_ram_reset(usbp);
+
+ /* Receive FIFO size initialization, the address is always zero.*/
+ OTG->GRXFSIZ = STM32_USB_OTG1_RX_FIFO_SIZE / 4;
+ otg_rxfifo_flush();
+
+ /* Enables also EP-related interrupt sources.*/
+ OTG->GINTMSK |= GINTMSK_RXFLVLM | GINTMSK_OEPM | GINTMSK_IEPM;
+ OTG->DIEPMSK = DIEPMSK_TOCM | DIEPMSK_XFRCM;
+ OTG->DOEPMSK = DOEPMSK_STUPM | DOEPMSK_XFRCM;
+
+ /* EP0 initialization, it is a special case.*/
+ usbp->epc[0] = &ep0config;
+ OTG->oe[0].DOEPTSIZ = 0;
+ OTG->oe[0].DOEPCTL = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_CTRL |
+ DOEPCTL_MPSIZ(ep0config.out_maxsize);
+ OTG->ie[0].DIEPTSIZ = 0;
+ OTG->ie[0].DIEPCTL = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_CTRL |
+ DIEPCTL_TXFNUM(0) | DIEPCTL_MPSIZ(ep0config.in_maxsize);
+ OTG->DIEPTXF0 = DIEPTXF_INEPTXFD(ep0config.in_maxsize / 4) |
+ DIEPTXF_INEPTXSA(otg_ram_alloc(usbp,
+ ep0config.in_maxsize / 4));
+ otg_txfifo_flush(0);
+ OTG->DAINTMSK = DAINTMSK_IEPM(0) | DAINTMSK_IEPM(0);
+}
+
+/**
+ * @brief Sets the USB address.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+void usb_lld_set_address(USBDriver *usbp) {
+
+ OTG->DCFG = (OTG->DCFG & ~DCFG_DAD_MASK) | DCFG_DAD(usbp->address);
+}
+
+/**
+ * @brief Enables an endpoint.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep) {
+ uint32_t ctl, fsize;
+
+ /* IN and OUT common parameters.*/
+ switch (usbp->epc[ep]->ep_mode & USB_EP_MODE_TYPE) {
+ case USB_EP_MODE_TYPE_CTRL:
+ ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_CTRL;
+ break;
+ case USB_EP_MODE_TYPE_ISOC:
+ ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_ISO;
+ break;
+ case USB_EP_MODE_TYPE_BULK:
+ ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_BULK;
+ break;
+ case USB_EP_MODE_TYPE_INTR:
+ ctl = DIEPCTL_SD0PID | DIEPCTL_USBAEP | DIEPCTL_EPTYP_INTR;
+ break;
+ default:
+ return;
+ }
+
+ /* OUT endpoint activation or deactivation.*/
+ OTG->oe[ep].DOEPTSIZ = 0;
+ if (usbp->epc[ep]->out_cb != NULL)
+ OTG->oe[ep].DOEPCTL = ctl | DOEPCTL_MPSIZ(usbp->epc[ep]->out_maxsize);
+ else
+ OTG->oe[ep].DOEPCTL &= ~DOEPCTL_USBAEP;
+
+ /* IN endpoint activation or deactivation.*/
+ OTG->ie[ep].DIEPTSIZ = 0;
+ if (usbp->epc[ep]->in_cb != NULL) {
+ /* FIFO allocation for the IN endpoint.*/
+ fsize = usbp->epc[ep]->in_maxsize / 4;
+ OTG->DIEPTXF[ep - 1] = DIEPTXF_INEPTXFD(fsize) |
+ DIEPTXF_INEPTXSA(otg_ram_alloc(usbp, fsize));
+ otg_txfifo_flush(ep);
+
+ OTG->ie[ep].DIEPCTL = ctl |
+ DIEPCTL_TXFNUM(ep) |
+ DIEPCTL_MPSIZ(usbp->epc[ep]->in_maxsize);
+ }
+ else {
+ OTG->DIEPTXF[ep - 1] = 0x02000400; /* Reset value.*/
+ otg_txfifo_flush(ep);
+ OTG->ie[ep].DIEPCTL &= ~DIEPCTL_USBAEP;
+ }
+}
+
+/**
+ * @brief Disables all the active endpoints except the endpoint zero.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ *
+ * @notapi
+ */
+void usb_lld_disable_endpoints(USBDriver *usbp) {
+
+ /* Resets the FIFO memory allocator.*/
+ otg_ram_reset(usbp);
+
+ /* Disabling all endpoints.*/
+ otg_disable_ep();
+}
+
+/**
+ * @brief Returns the status of an OUT endpoint.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ * @return The endpoint status.
+ * @retval EP_STATUS_DISABLED The endpoint is not active.
+ * @retval EP_STATUS_STALLED The endpoint is stalled.
+ * @retval EP_STATUS_ACTIVE The endpoint is active.
+ *
+ * @notapi
+ */
+usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep) {
+
+ (void)usbp;
+ (void)ep;
+
+ return 0;
+}
+
+/**
+ * @brief Returns the status of an IN endpoint.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ * @return The endpoint status.
+ * @retval EP_STATUS_DISABLED The endpoint is not active.
+ * @retval EP_STATUS_STALLED The endpoint is stalled.
+ * @retval EP_STATUS_ACTIVE The endpoint is active.
+ *
+ * @notapi
+ */
+usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep) {
+
+ (void)usbp;
+ (void)ep;
+
+ return 0;
+}
+
+/**
+ * @brief Reads a setup packet from the dedicated packet buffer.
+ * @details This function must be invoked in the context of the @p setup_cb
+ * callback in order to read the received setup packet.
+ * @pre In order to use this function the endpoint must have been
+ * initialized as a control endpoint.
+ * @post The endpoint is ready to accept another packet.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ * @param[out] buf buffer where to copy the packet data
+ *
+ * @notapi
+ */
+void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) {
+
+ memcpy(buf, usbp->epc[ep]->setup_buf, 8);
+}
+
+/**
+ * @brief Reads from a dedicated packet buffer.
+ * @pre In order to use this function he endpoint must have been
+ * initialized in packet mode.
+ * @note This function can be invoked both in thread and IRQ context.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ * @param[out] buf buffer where to copy the packet data
+ * @param[in] n maximum number of bytes to copy. This value must
+ * not exceed the maximum packet size for this endpoint.
+ * @return The received packet size regardless the specified
+ * @p n parameter.
+ * @retval 0 Zero size packet received.
+ *
+ * @notapi
+ */
+size_t usb_lld_read_packet_buffer(USBDriver *usbp, usbep_t ep,
+ uint8_t *buf, size_t n) {
+
+ (void)usbp;
+ (void)ep;
+ (void)buf;
+ (void)n;
+
+ return 0;
+}
+
+/**
+ * @brief Writes to a dedicated packet buffer.
+ * @pre In order to use this function he endpoint must have been
+ * initialized in packet mode.
+ * @note This function can be invoked both in thread and IRQ context.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ * @param[in] buf buffer where to fetch the packet data
+ * @param[in] n maximum number of bytes to copy. This value must
+ * not exceed the maximum packet size for this endpoint.
+ *
+ * @notapi
+ */
+void usb_lld_write_packet_buffer(USBDriver *usbp, usbep_t ep,
+ const uint8_t *buf, size_t n) {
+
+ (void)usbp;
+ (void)ep;
+ (void)buf;
+ (void)n;
+}
+
+/**
+ * @brief Prepares for a receive operation.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ * @param[out] buf buffer where to copy the received data
+ * @param[in] n maximum number of bytes to copy
+ *
+ * @notapi
+ */
+void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep,
+ uint8_t *buf, size_t n) {
+
+ (void)usbp;
+ (void)ep;
+ (void)buf;
+ (void)n;
+}
+
+/**
+ * @brief Prepares for a transmit operation.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ * @param[in] buf buffer where to fetch the data to be transmitted
+ * @param[in] n maximum number of bytes to copy
+ *
+ * @notapi
+ */
+void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep,
+ const uint8_t *buf, size_t n) {
+ USBInEndpointState *isp = usbp->epc[ep]->in_state;
+
+ isp->txbuf = buf;
+ isp->txsize = n;
+ isp->txcnt = 0;
+
+ if (n == 0) {
+ /* Special case, sending zero size packet.*/
+ OTG->ie[ep].DIEPTSIZ = DIEPTSIZ_PKTCNT(1) | DIEPTSIZ_XFRSIZ(0);
+ }
+ else {
+ /* Transfer initialization.*/
+ uint32_t pcnt = (n + (usbp->epc[ep]->in_maxsize - 1) /
+ usbp->epc[ep]->in_maxsize);
+ OTG->ie[ep].DIEPTSIZ = DIEPTSIZ_PKTCNT(pcnt) |
+ DIEPTSIZ_XFRSIZ(usbp->epc[ep]->in_state->txsize);
+ }
+ OTG->DIEPEMPMSK |= DIEPEMPMSK_INEPTXFEM(ep);
+}
+
+/**
+ * @brief Starts a receive operation on an OUT endpoint.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_start_out(USBDriver *usbp, usbep_t ep) {
+
+ (void)usbp;
+ (void)ep;
+}
+
+/**
+ * @brief Starts a transmit operation on an IN endpoint.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_start_in(USBDriver *usbp, usbep_t ep) {
+
+ (void)usbp;
+ (void)ep;
+}
+
+/**
+ * @brief Brings an OUT endpoint in the stalled state.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_stall_out(USBDriver *usbp, usbep_t ep) {
+
+ (void)usbp;
+
+ OTG->oe[ep].DOEPCTL |= DOEPCTL_STALL;
+}
+
+/**
+ * @brief Brings an IN endpoint in the stalled state.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_stall_in(USBDriver *usbp, usbep_t ep) {
+
+ (void)usbp;
+
+ OTG->ie[ep].DIEPCTL |= DIEPCTL_STALL;
+}
+
+/**
+ * @brief Brings an OUT endpoint in the active state.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_clear_out(USBDriver *usbp, usbep_t ep) {
+
+ (void)usbp;
+
+ OTG->oe[ep].DOEPCTL &= ~DOEPCTL_STALL;
+}
+
+/**
+ * @brief Brings an IN endpoint in the active state.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ *
+ * @notapi
+ */
+void usb_lld_clear_in(USBDriver *usbp, usbep_t ep) {
+
+ (void)usbp;
+
+ OTG->ie[ep].DIEPCTL &= ~DIEPCTL_STALL;
+}
+
+#endif /* HAL_USE_USB */
+
+/** @} */
diff --git a/os/hal/platforms/STM32/OTGv1/usb_lld.h b/os/hal/platforms/STM32/OTGv1/usb_lld.h new file mode 100644 index 000000000..4cc18a05b --- /dev/null +++ b/os/hal/platforms/STM32/OTGv1/usb_lld.h @@ -0,0 +1,402 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file STM32/OTGv1/usb_lld.h
+ * @brief STM32 USB subsystem low level driver header.
+ *
+ * @addtogroup USB
+ * @{
+ */
+
+#ifndef _USB_LLD_H_
+#define _USB_LLD_H_
+
+#if HAL_USE_USB || defined(__DOXYGEN__)
+
+#include "stm32_otg.h"
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/**
+ * @brief Maximum endpoint address.
+ */
+#define USB_MAX_ENDPOINTS 3
+
+/**
+ * @brief The address can be changed immediately upon packet reception.
+ */
+#define USB_SET_ADDRESS_MODE USB_EARLY_SET_ADDRESS
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @brief OTG1 driver enable switch.
+ * @details If set to @p TRUE the support for USB1 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_USB_USE_OTG1) || defined(__DOXYGEN__)
+#define STM32_USB_USE_OTG1 TRUE
+#endif
+
+/**
+ * @brief OTG1 interrupt priority level setting.
+ */
+#if !defined(STM32_USB_OTG1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_USB_OTG1_IRQ_PRIORITY 6
+#endif
+
+/**
+ * @brief OTG1 RX shared FIFO size.
+ * @note Must be a multiple of 4.
+ */
+#if !defined(STM32_USB_OTG1_RX_FIFO_SIZE) || defined(__DOXYGEN__)
+#define STM32_USB_OTG1_RX_FIFO_SIZE 512
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if STM32_USB_USE_OTG1 && !STM32_HAS_OTG1
+#error "OTG1 not present in the selected device"
+#endif
+
+#if !STM32_USB_USE_OTG1
+#error "USB driver activated but no USB peripheral assigned"
+#endif
+
+#if (STM32_USB_OTG1_RX_FIFO_SIZE & 3) != 0
+#error "RX FIFO size must be a multiple of 4"
+#endif
+
+#if defined(STM32F4XX) || defined(STM32F2XX)
+#define STM32_USBCLK STM32_PLL48CLK
+#elif defined(STM32F10X_CL)
+#define STM32_USBCLK STM32_OTGFSCLK
+#else
+#error "unsupported STM32 platform for OTG functionality"
+#endif
+
+#if STM32_USBCLK != 48000000
+#error "the USB OTG driver requires a 48MHz clock"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of an endpoint state structure.
+ */
+typedef struct {
+ /**
+ * @brief Pointer to the transmission buffer.
+ */
+ const uint8_t *txbuf;
+ /**
+ * @brief Requested transmit transfer size.
+ */
+ size_t txsize;
+ /**
+ * @brief Transmitted bytes so far.
+ */
+ size_t txcnt;
+} USBInEndpointState;
+
+/**
+ * @brief Type of an endpoint state structure.
+ */
+typedef struct {
+ /**
+ * @brief Number of packets to receive.
+ */
+ uint16_t rxpkts;
+ /**
+ * @brief Pointer to the receive buffer.
+ */
+ uint8_t *rxbuf;
+ /**
+ * @brief Requested receive transfer size.
+ */
+ size_t rxsize;
+ /**
+ * @brief Received bytes so far.
+ */
+ size_t rxcnt;
+} USBOutEndpointState;
+
+/**
+ * @brief Type of an USB endpoint configuration structure.
+ * @note Platform specific restrictions may apply to endpoints.
+ */
+typedef struct {
+ /**
+ * @brief Type and mode of the endpoint.
+ */
+ uint32_t ep_mode;
+ /**
+ * @brief Setup packet notification callback.
+ * @details This callback is invoked when a setup packet has been
+ * received.
+ * @post The application must immediately call @p usbReadPacket() in
+ * order to access the received packet.
+ * @note This field is only valid for @p USB_EP_MODE_TYPE_CTRL
+ * endpoints, it should be set to @p NULL for other endpoint
+ * types.
+ */
+ usbepcallback_t setup_cb;
+ /**
+ * @brief IN endpoint notification callback.
+ * @details This field must be set to @p NULL if the IN endpoint is not
+ * used.
+ */
+ usbepcallback_t in_cb;
+ /**
+ * @brief OUT endpoint notification callback.
+ * @details This field must be set to @p NULL if the OUT endpoint is not
+ * used.
+ */
+ usbepcallback_t out_cb;
+ /**
+ * @brief IN endpoint maximum packet size.
+ * @details This field must be set to zero if the IN endpoint is not
+ * used.
+ */
+ uint16_t in_maxsize;
+ /**
+ * @brief OUT endpoint maximum packet size.
+ * @details This field must be set to zero if the OUT endpoint is not
+ * used.
+ */
+ uint16_t out_maxsize;
+ /**
+ * @brief @p USBEndpointState associated to the IN endpoint.
+ * @details This structure maintains the state of the IN endpoint when
+ * the endpoint is not in packet mode. Endpoints configured in
+ * packet mode must set this field to @p NULL.
+ */
+ USBInEndpointState *in_state;
+ /**
+ * @brief @p USBEndpointState associated to the OUT endpoint.
+ * @details This structure maintains the state of the OUT endpoint when
+ * the endpoint is not in packet mode. Endpoints configured in
+ * packet mode must set this field to @p NULL.
+ */
+ USBOutEndpointState *out_state;
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to a buffer for setup packets.
+ * @details Setup packets require a dedicated 8-bytes buffer, set this
+ * field to @p NULL for non-control endpoints.
+ */
+ uint8_t *setup_buf;
+} USBEndpointConfig;
+
+/**
+ * @brief Type of an USB driver configuration structure.
+ */
+typedef struct {
+ /**
+ * @brief USB events callback.
+ * @details This callback is invoked when an USB driver event is registered.
+ */
+ usbeventcb_t event_cb;
+ /**
+ * @brief Device GET_DESCRIPTOR request callback.
+ * @note This callback is mandatory and cannot be set to @p NULL.
+ */
+ usbgetdescriptor_t get_descriptor_cb;
+ /**
+ * @brief Requests hook callback.
+ * @details This hook allows to be notified of standard requests or to
+ * handle non standard requests.
+ */
+ usbreqhandler_t requests_hook_cb;
+ /**
+ * @brief Start Of Frame callback.
+ */
+ usbcallback_t sof_cb;
+ /* End of the mandatory fields.*/
+} USBConfig;
+
+/**
+ * @brief Structure representing an USB driver.
+ */
+struct USBDriver {
+ /**
+ * @brief Driver state.
+ */
+ usbstate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const USBConfig *config;
+ /**
+ * @brief Field available to user, it can be used to associate an
+ * application-defined handler to the USB driver.
+ */
+ void *param;
+ /**
+ * @brief Bit map of the transmitting IN endpoints.
+ */
+ uint16_t transmitting;
+ /**
+ * @brief Bit map of the receiving OUT endpoints.
+ */
+ uint16_t receiving;
+ /**
+ * @brief Active endpoints configurations.
+ */
+ const USBEndpointConfig *epc[USB_MAX_ENDPOINTS + 1];
+ /**
+ * @brief Endpoint 0 state.
+ */
+ usbep0state_t ep0state;
+ /**
+ * @brief Next position in the buffer to be transferred through endpoint 0.
+ */
+ uint8_t *ep0next;
+ /**
+ * @brief Number of bytes yet to be transferred through endpoint 0.
+ */
+ size_t ep0n;
+ /**
+ * @brief Endpoint 0 end transaction callback.
+ */
+ usbcallback_t ep0endcb;
+ /**
+ * @brief Setup packet buffer.
+ */
+ uint8_t setup[8];
+ /**
+ * @brief Current USB device status.
+ */
+ uint16_t status;
+ /**
+ * @brief Assigned USB address.
+ */
+ uint8_t address;
+ /**
+ * @brief Current USB device configuration.
+ */
+ uint8_t configuration;
+#if defined(USB_DRIVER_EXT_FIELDS)
+ USB_DRIVER_EXT_FIELDS
+#endif
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the next address in the packet memory.
+ */
+ uint32_t pmnext;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/**
+ * @brief Fetches a 16 bits word value from an USB message.
+ *
+ * @param[in] p pointer to the 16 bits word
+ *
+ * @notapi
+ */
+#define usb_lld_fetch_word(p) (*(uint16_t *)(p))
+
+/**
+ * @brief Returns the exact size of a receive transaction.
+ * @details The received size can be different from the size specified in
+ * @p usbStartReceiveI() because the last packet could have a size
+ * different from the expected one.
+ * @pre The OUT endpoint must have been configured in transaction mode
+ * in order to use this function.
+ *
+ * @param[in] usbp pointer to the @p USBDriver object
+ * @param[in] ep endpoint number
+ * @return Received data size.
+ *
+ * @notapi
+ */
+#define usb_lld_get_transaction_size(usbp, ep) \
+ ((usbp)->epc[ep]->out_state->rxcnt)
+
+/**
+ * @brief Connects the USB device.
+ *
+ * @api
+ */
+#define usb_lld_connect_bus(usbp) (OTG->GCCFG |= GCCFG_VBUSBSEN)
+
+/**
+ * @brief Disconnect the USB device.
+ *
+ * @api
+ */
+#define usb_lld_disconnect_bus(usbp) (OTG->GCCFG &= ~GCCFG_VBUSBSEN)
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if STM32_USB_USE_OTG1 && !defined(__DOXYGEN__)
+extern USBDriver USBD1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void usb_lld_init(void);
+ void usb_lld_start(USBDriver *usbp);
+ void usb_lld_stop(USBDriver *usbp);
+ void usb_lld_reset(USBDriver *usbp);
+ void usb_lld_set_address(USBDriver *usbp);
+ void usb_lld_init_endpoint(USBDriver *usbp, usbep_t ep);
+ void usb_lld_disable_endpoints(USBDriver *usbp);
+ usbepstatus_t usb_lld_get_status_in(USBDriver *usbp, usbep_t ep);
+ usbepstatus_t usb_lld_get_status_out(USBDriver *usbp, usbep_t ep);
+ void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf);
+ size_t usb_lld_read_packet_buffer(USBDriver *usbp, usbep_t ep,
+ uint8_t *buf, size_t n);
+ void usb_lld_write_packet_buffer(USBDriver *usbp, usbep_t ep,
+ const uint8_t *buf, size_t n);
+ void usb_lld_prepare_receive(USBDriver *usbp, usbep_t ep,
+ uint8_t *buf, size_t n);
+ void usb_lld_prepare_transmit(USBDriver *usbp, usbep_t ep,
+ const uint8_t *buf, size_t n);
+ void usb_lld_start_out(USBDriver *usbp, usbep_t ep);
+ void usb_lld_start_in(USBDriver *usbp, usbep_t ep);
+ void usb_lld_stall_out(USBDriver *usbp, usbep_t ep);
+ void usb_lld_stall_in(USBDriver *usbp, usbep_t ep);
+ void usb_lld_clear_out(USBDriver *usbp, usbep_t ep);
+ void usb_lld_clear_in(USBDriver *usbp, usbep_t ep);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_USB */
+
+#endif /* _USB_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/platforms/STM32/can_lld.h b/os/hal/platforms/STM32/can_lld.h index 6ab69efb2..d9bf3bb39 100644 --- a/os/hal/platforms/STM32/can_lld.h +++ b/os/hal/platforms/STM32/can_lld.h @@ -188,7 +188,7 @@ typedef struct { */
uint32_t mode:1;
/**
- * @brief Filter sclae.
+ * @brief Filter scale.
* @note This bit represent the CAN_FS1R register bit associated to this
* filter (0=16 bits mode, 1=32 bits mode).
*/
diff --git a/os/hal/platforms/STM32/i2s_lld.c b/os/hal/platforms/STM32/i2s_lld.c new file mode 100644 index 000000000..692988385 --- /dev/null +++ b/os/hal/platforms/STM32/i2s_lld.c @@ -0,0 +1,165 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file templates/i2s_lld.c
+ * @brief I2S Driver subsystem low level driver source template.
+ *
+ * @addtogroup I2S
+ * @{
+ */
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_I2S || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level I2S driver initialization.
+ *
+ * @notapi
+ */
+void i2s_lld_init(void) {
+
+#if STM32_I2S_USE_I2S2
+ spiObjectInit(&I2SD2);
+ I2SD2.spi = SPI2;
+#endif
+
+#if STM32_I2S_USE_I2S3
+ spiObjectInit(&I2SD3);
+ I2SD3.spi = SPI3;
+#endif
+}
+
+/**
+ * @brief Configures and activates the I2S peripheral.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ *
+ * @notapi
+ */
+void i2s_lld_start(I2SDriver *i2sp) {
+
+ /* If in stopped state then enables the SPI and DMA clocks.*/
+ if (i2sp->state == I2S_STOP) {
+#if STM32_SPI_USE_SPI2
+ if (&SPID2 == spip) {
+ bool_t b;
+ b = dmaStreamAllocate(spip->dma,
+ STM32_I2S_I2S2_IRQ_PRIORITY,
+ (stm32_dmaisr_t)i2s_lld_serve_rx_interrupt,
+ (void *)spip);
+ chDbgAssert(!b, "spi_lld_start(), #1", "stream already allocated");
+ rccEnableSPI2(FALSE);
+ }
+#endif
+#if STM32_SPI_USE_SPI3
+ if (&SPID3 == spip) {
+ bool_t b;
+ b = dmaStreamAllocate(spip->dma,
+ STM32_I2S_I2S3_IRQ_PRIORITY,
+ (stm32_dmaisr_t)i2s_lld_serve_rx_interrupt,
+ (void *)spip);
+ chDbgAssert(!b, "spi_lld_start(), #2", "stream already allocated");
+ rccEnableSPI3(FALSE);
+ }
+#endif
+ }
+ /* Configuration.*/
+}
+
+/**
+ * @brief Deactivates the I2S peripheral.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ *
+ * @notapi
+ */
+void i2s_lld_stop(I2SDriver *i2sp) {
+
+ if (i2sp->state == I2S_READY) {
+ /* Clock deactivation.*/
+
+ }
+}
+
+/**
+ * @brief Starts a I2S data exchange.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ *
+ * @notapi
+ */
+void i2s_lld_start_exchange(I2SDriver *i2sp) {
+
+}
+
+/**
+ * @brief Starts a I2S data exchange in continuous mode.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ *
+ * @notapi
+ */
+void i2s_lld_start_exchange_continuous(I2SDriver *i2sp) {
+
+}
+
+/**
+ * @brief Stops the ongoing data exchange.
+ * @details The ongoing data exchange, if any, is stopped, if the driver
+ * was not active the function does nothing.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ *
+ * @notapi
+ */
+void i2s_lld_stop_exchange(I2SDriver *i2sp) {
+
+}
+
+#endif /* HAL_USE_I2S */
+
+/** @} */
diff --git a/os/hal/platforms/STM32/i2s_lld.h b/os/hal/platforms/STM32/i2s_lld.h new file mode 100644 index 000000000..52f00d2b7 --- /dev/null +++ b/os/hal/platforms/STM32/i2s_lld.h @@ -0,0 +1,321 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file templates/i2s_lld.h
+ * @brief I2S Driver subsystem low level driver header template.
+ *
+ * @addtogroup I2S
+ * @{
+ */
+
+#ifndef _I2S_LLD_H_
+#define _I2S_LLD_H_
+
+#if HAL_USE_I2S || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name Configuration options
+ * @{
+ */
+/**
+ * @brief I2S2 driver enable switch.
+ * @details If set to @p TRUE the support for I2S2 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_I2S_USE_I2S2) || defined(__DOXYGEN__)
+#define STM32_I2S_USE_I2S2 TRUE
+#endif
+
+/**
+ * @brief I2S3 driver enable switch.
+ * @details If set to @p TRUE the support for I2S3 is included.
+ * @note The default is @p TRUE.
+ */
+#if !defined(STM32_I2S_USE_I2S3) || defined(__DOXYGEN__)
+#define STM32_I2S_USE_I2S3 TRUE
+#endif
+
+/**
+ * @brief I2S2 interrupt priority level setting.
+ */
+#if !defined(STM32_I2S_I2S2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2S_I2S2_IRQ_PRIORITY 10
+#endif
+
+/**
+ * @brief I2S3 interrupt priority level setting.
+ */
+#if !defined(STM32_I2S_I2S3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2S_I2S3_IRQ_PRIORITY 10
+#endif
+
+/**
+ * @brief I2S2 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_I2S_I2S2_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2S_I2S2_DMA_PRIORITY 1
+#endif
+
+/**
+ * @brief I2S3 DMA priority (0..3|lowest..highest).
+ */
+#if !defined(STM32_I2S_I2S2_DMA_PRIORITY) || defined(__DOXYGEN__)
+#define STM32_I2S_I2S2_DMA_PRIORITY 1
+#endif
+
+/**
+ * @brief I2S DMA error hook.
+ */
+#if !defined(STM32_I2S_DMA_ERROR_HOOK) || defined(__DOXYGEN__)
+#define STM32_I2S_DMA_ERROR_HOOK(i2sp) chSysHalt()
+#endif
+
+#if STM32_ADVANCED_DMA || defined(__DOXYGEN__)
+
+/**
+ * @brief DMA stream used for I2S2 RX operations.
+ * @note This option is only available on platforms with enhanced DMA.
+ */
+#if !defined(STM32_I2S_I2S2_RX_DMA_STREAM) || defined(__DOXYGEN__)
+#define STM32_I2S_I2S2_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
+#endif
+
+/**
+ * @brief DMA stream used for I2S2 TX operations.
+ * @note This option is only available on platforms with enhanced DMA.
+ */
+#if !defined(STM32_I2S_I2S2_TX_DMA_STREAM) || defined(__DOXYGEN__)
+#define STM32_I2S_I2S2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#endif
+
+/**
+ * @brief DMA stream used for I2S3 RX operations.
+ * @note This option is only available on platforms with enhanced DMA.
+ */
+#if !defined(STM32_I2S_I2S3_RX_DMA_STREAM) || defined(__DOXYGEN__)
+#define STM32_I2S_I2S3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#endif
+
+/**
+ * @brief DMA stream used for I2S3 TX operations.
+ * @note This option is only available on platforms with enhanced DMA.
+ */
+#if !defined(STM32_I2S_I2S3_TX_DMA_STREAM) || defined(__DOXYGEN__)
+#define STM32_I2S_I2S3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#endif
+
+#else /* !STM32_ADVANCED_DMA */
+
+/* Fixed streams for platforms using the old DMA peripheral, the values are
+ valid for both STM32F1xx and STM32L1xx.*/
+#define STM32_I2S_I2S2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2S_I2S2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_I2S_I2S3_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_I2S_I2S3_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+
+#endif /* !STM32_ADVANCED_DMA */
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+#if STM32_I2S_USE_I2S2 && !STM32_HAS_SPI2
+#error "SPI2 not present in the selected device"
+#endif
+
+#if STM32_I2S_USE_I2S3 && !STM32_HAS_SPI3
+#error "SPI3 not present in the selected device"
+#endif
+
+#if !STM32_I2S_USE_I2S2 && !STM32_I2S_USE_I2S3
+#error "I2S driver activated but no I2S peripheral assigned"
+#endif
+
+#if STM32_I2S_USE_I2S2 && \
+ !STM32_DMA_IS_VALID_ID(STM32_I2S_I2S2_RX_DMA_STREAM, STM32_SPI2_RX_DMA_MSK)
+#error "invalid DMA stream associated to I2S2 RX"
+#endif
+
+#if STM32_I2S_USE_I2S2 && \
+ !STM32_DMA_IS_VALID_ID(STM32_I2S_I2S2_TX_DMA_STREAM, STM32_SPI2_TX_DMA_MSK)
+#error "invalid DMA stream associated to I2S2 TX"
+#endif
+
+#if STM32_I2S_USE_I2S3 && \
+ !STM32_DMA_IS_VALID_ID(STM32_I2S_I2S3_RX_DMA_STREAM, STM32_SPI3_RX_DMA_MSK)
+#error "invalid DMA stream associated to I2S3 RX"
+#endif
+
+#if STM32_I2S_USE_I2S3 && \
+ !STM32_DMA_IS_VALID_ID(STM32_I2S_I2S3_TX_DMA_STREAM, STM32_SPI3_TX_DMA_MSK)
+#error "invalid DMA stream associated to I2S3 TX"
+#endif
+
+#if !defined(STM32_DMA_REQUIRED)
+#define STM32_DMA_REQUIRED
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief I2S mode type.
+ */
+typedef uint32_t i2smode_t;
+
+/**
+ * @brief Type of a structure representing an I2S driver.
+ */
+typedef struct I2SDriver I2SDriver;
+
+/**
+ * @brief I2S notification callback type.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ * @param[in] buffer pointer to the buffer
+ * @param[in] n number of sample positions starting from @p buffer
+ */
+typedef void (*i2scallback_t)(I2SDriver *i2sp, void *buffer, size_t n);
+
+/**
+ * @brief Driver configuration structure.
+ * @note It could be empty on some architectures.
+ */
+typedef struct {
+ /**
+ * @brief I2S mode selection.
+ */
+ i2smode_t mode;
+ /**
+ * @brief Transmission buffer pointer.
+ */
+ const void *tx_buffer;
+ /**
+ * @brief Transmission buffer size in number of samples.
+ */
+ size_t tx_size;
+ /**
+ * @brief Callback function associated to the transmission or @p NULL.
+ */
+ i2scallback_t tx_cb;
+ /**
+ * @brief Receive buffer pointer.
+ */
+ void *rx_buffer;
+ /**
+ * @brief Receive buffer size in number of samples.
+ */
+ size_t rx_size;
+ /**
+ * @brief Callback function associated to the reception or @p NULL.
+ */
+ i2scallback_t rx_cb;;
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Configuration of the I2SCFGR register.
+ * @details See the STM32 reference manual, this register is used for
+ * the I2S configuration, the following bits must not be
+ * specified because handled directly by the driver:
+ * - I2SMOD
+ * - I2SE
+ * - I2SCFG
+ * .
+ */
+ int16_t i2scfgr;
+ /**
+ * @brief Configuration of the I2SPR register.
+ * @details See the STM32 reference manual, this register is used for
+ * the I2S clock setup.
+ */
+ int16_t i2spr;
+} I2SConfig;
+
+/**
+ * @brief Structure representing an I2S driver.
+ */
+struct I2SDriver {
+ /**
+ * @brief Driver state.
+ */
+ i2sstate_t state;
+ /**
+ * @brief Current configuration data.
+ */
+ const I2SConfig *config;
+ /* End of the mandatory fields.*/
+ /**
+ * @brief Pointer to the SPIx registers block.
+ */
+ SPI_TypeDef *spi;
+ /**
+ * @brief DMA stream.
+ */
+ const stm32_dma_stream_t *dma;
+ /**
+ * @brief DMA mode bit mask.
+ */
+ uint32_t dmamode;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if STM32_I2S_USE_I2S2 && !defined(__DOXYGEN__)
+extern I2SDriver I2SD2;
+#endif
+
+#if STM32_I2S_USE_I2S3 && !defined(__DOXYGEN__)
+extern I2SDriver I2SD3;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void i2s_lld_init(void);
+ void i2s_lld_start(I2SDriver *i2sp);
+ void i2s_lld_stop(I2SDriver *i2sp);
+ void i2s_lld_start_exchange(I2SDriver *i2sp);
+ void i2s_lld_start_exchange_continuous(I2SDriver *i2sp);
+ void i2s_lld_stop_exchange(I2SDriver *i2sp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_I2S */
+
+#endif /* _I2S_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/platforms/STM32/icu_lld.c b/os/hal/platforms/STM32/icu_lld.c index 2bfffd3bd..d5511ec01 100644 --- a/os/hal/platforms/STM32/icu_lld.c +++ b/os/hal/platforms/STM32/icu_lld.c @@ -17,6 +17,10 @@ You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
+/*
+ Concepts and parts of this file have been contributed by Fabio Utzig and
+ Xo Wang.
+ */
/**
* @file STM32/icu_lld.c
@@ -112,6 +116,8 @@ static void icu_lld_serve_interrupt(ICUDriver *icup) { if ((sr & TIM_SR_CC2IF) != 0)
_icu_isr_invoke_period_cb(icup);
}
+ if ((sr & TIM_SR_UIF) != 0)
+ _icu_isr_invoke_overflow_cb(icup);
}
/*===========================================================================*/
@@ -276,7 +282,7 @@ void icu_lld_init(void) { #if STM32_ICU_USE_TIM8
/* Driver initialization.*/
icuObjectInit(&ICUD8);
- ICUD5.tim = STM32_TIM8;
+ ICUD8.tim = STM32_TIM8;
#endif
}
@@ -344,8 +350,8 @@ void icu_lld_start(ICUDriver *icup) { #endif
#if STM32_ICU_USE_TIM8
if (&ICUD8 == icup) {
- rccEnableTIM5(FALSE);
- rccResetTIM5();
+ rccEnableTIM8(FALSE);
+ rccResetTIM8();
nvicEnableVector(TIM8_CC_IRQn,
CORTEX_PRIORITY_MASK(STM32_ICU_TIM8_IRQ_PRIORITY));
icup->clock = STM32_TIMCLK2;
@@ -482,7 +488,7 @@ void icu_lld_stop(ICUDriver *icup) { */
void icu_lld_enable(ICUDriver *icup) {
- icup->tim->SR = 0; /* Clear pending IRQs (if any). */
+ icup->tim->SR = 0; /* Clear pending IRQs (if any). */
if (icup->config->channel == ICU_CHANNEL_1) {
if (icup->config->period_cb != NULL)
icup->tim->DIER |= TIM_DIER_CC1IE;
@@ -494,6 +500,8 @@ void icu_lld_enable(ICUDriver *icup) { if (icup->config->period_cb != NULL)
icup->tim->DIER |= TIM_DIER_CC2IE;
}
+ if (icup->config->overflow_cb != NULL)
+ icup->tim->DIER |= TIM_DIER_UIE;
icup->tim->CR1 = TIM_CR1_URS | TIM_CR1_CEN;
}
diff --git a/os/hal/platforms/STM32/icu_lld.h b/os/hal/platforms/STM32/icu_lld.h index 642de2a64..691b06a71 100644 --- a/os/hal/platforms/STM32/icu_lld.h +++ b/os/hal/platforms/STM32/icu_lld.h @@ -227,6 +227,10 @@ typedef struct { * @brief Callback for cycle period measurement.
*/
icucallback_t period_cb;
+ /**
+ * @brief Callback for timer overflow.
+ */
+ icucallback_t overflow_cb;
/* End of the mandatory fields.*/
/**
* @brief Timer input channel to be used.
diff --git a/os/hal/platforms/STM32/mac_lld.c b/os/hal/platforms/STM32/mac_lld.c index 849c7a39e..15f9cd13c 100644 --- a/os/hal/platforms/STM32/mac_lld.c +++ b/os/hal/platforms/STM32/mac_lld.c @@ -118,14 +118,22 @@ static uint32_t mii_read(MACDriver *macp, uint32_t reg) { static void mii_find_phy(MACDriver *macp) {
uint32_t i;
- for (i = 0; i < 31; i++) {
- macp->phyaddr = i << 11;
- ETH->MACMIIDR = (i << 6) | MACMIIDR_CR;
- if ((mii_read(macp, MII_PHYSID1) == (BOARD_PHY_ID >> 16)) &&
- ((mii_read(macp, MII_PHYSID2) & 0xFFF0) == (BOARD_PHY_ID & 0xFFF0))) {
- return;
+#if STM32_MAC_PHY_TIMEOUT > 0
+ halrtcnt_t start = halGetCounterValue();
+ halrtcnt_t timeout = start + MS2RTT(STM32_MAC_PHY_TIMEOUT);
+ while (halIsCounterWithin(start, timeout)) {
+#endif
+ for (i = 0; i < 31; i++) {
+ macp->phyaddr = i << 11;
+ ETH->MACMIIDR = (i << 6) | MACMIIDR_CR;
+ if ((mii_read(macp, MII_PHYSID1) == (BOARD_PHY_ID >> 16)) &&
+ ((mii_read(macp, MII_PHYSID2) & 0xFFF0) == (BOARD_PHY_ID & 0xFFF0))) {
+ return;
+ }
}
+#if STM32_MAC_PHY_TIMEOUT > 0
}
+#endif
/* Wrong or defective board.*/
chSysHalt();
}
@@ -242,7 +250,7 @@ void mac_lld_init(void) { /* PHY address setup.*/
#if defined(BOARD_PHY_ADDRESS)
- phyaddr = BOARD_PHY_ADDRESS << 11;
+ ETHD1.phyaddr = BOARD_PHY_ADDRESS << 11;
#else
mii_find_phy(ÐD1);
#endif
@@ -308,7 +316,11 @@ void mac_lld_start(MACDriver *macp) { /* Transmitter and receiver enabled.
Note that the complete setup of the MAC is performed when the link
status is detected.*/
+#if STM32_IP_CHECKSUM_OFFLOAD
ETH->MACCR = ETH_MACCR_IPCO | ETH_MACCR_RE | ETH_MACCR_TE;
+#else
+ ETH->MACCR = ETH_MACCR_RE | ETH_MACCR_TE;
+#endif
/* DMA configuration:
Descriptor chains pointers.*/
@@ -411,7 +423,7 @@ msg_t max_lld_get_transmit_descriptor(MACDriver *macp, * @brief Writes to a transmit descriptor's stream.
*
* @param[in] tdp pointer to a @p MACTransmitDescriptor structure
- * @param[in] buf pointer to the buffer cointaining the data to be
+ * @param[in] buf pointer to the buffer containing the data to be
* written
* @param[in] size number of bytes to be written
* @return The number of bytes written into the descriptor's
@@ -457,7 +469,8 @@ void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) { /* Unlocks the descriptor and returns it to the DMA engine.*/
tdp->physdesc->tdes1 = tdp->offset;
- tdp->physdesc->tdes0 = STM32_TDES0_IC | STM32_TDES0_LS | STM32_TDES0_FS |
+ tdp->physdesc->tdes0 = STM32_TDES0_CIC(STM32_IP_CHECKSUM_OFFLOAD) |
+ STM32_TDES0_IC | STM32_TDES0_LS | STM32_TDES0_FS |
STM32_TDES0_TCH | STM32_TDES0_OWN;
/* If the DMA engine is stalled then a restart request is issued.*/
@@ -492,8 +505,12 @@ msg_t max_lld_get_receive_descriptor(MACDriver *macp, /* Iterates through received frames until a valid one is found, invalid
frames are discarded.*/
while (!(rdes->rdes0 & STM32_RDES0_OWN)) {
- if (!(rdes->rdes0 & (STM32_RDES0_AFM | STM32_RDES0_ES)) &&
- (rdes->rdes0 & STM32_RDES0_FS) && (rdes->rdes0 & STM32_RDES0_LS)) {
+ if (!(rdes->rdes0 & (STM32_RDES0_AFM | STM32_RDES0_ES
+#if STM32_IP_CHECKSUM_OFFLOAD
+ | STM32_RDES0_IPHCE | STM32_RDES0_PCE
+#endif
+ )) && (rdes->rdes0 & STM32_RDES0_FS) &&
+ (rdes->rdes0 & STM32_RDES0_LS)) {
/* Found a valid one.*/
rdp->offset = 0;
rdp->size = ((rdes->rdes0 & STM32_RDES0_FL_MASK) >> 16) - 4;
diff --git a/os/hal/platforms/STM32/mac_lld.h b/os/hal/platforms/STM32/mac_lld.h index 077ddd2ec..3bedc38a2 100644 --- a/os/hal/platforms/STM32/mac_lld.h +++ b/os/hal/platforms/STM32/mac_lld.h @@ -84,6 +84,7 @@ #define STM32_TDES0_TTSE 0x02000000
#define STM32_TDES0_LOCKED 0x01000000 /* NOTE: Pseudo flag. */
#define STM32_TDES0_CIC_MASK 0x00C00000
+#define STM32_TDES0_CIC(n) ((n) << 22)
#define STM32_TDES0_TER 0x00200000
#define STM32_TDES0_TCH 0x00100000
#define STM32_TDES0_TTSS 0x00020000
@@ -141,17 +142,51 @@ #endif
/**
+ * @brief PHY detection timeout.
+ * @details Timeout, in milliseconds, for PHY address detection, if a PHY
+ * is not detected within the timeout then the driver halts during
+ * initialization. This setting applies only if the PHY address is
+ * not explicitly set in the board header file using
+ * @p BOARD_PHY_ADDRESS. A zero value disables the timeout and a
+ * single search path is performed.
+ */
+#if !defined(STM32_MAC_PHY_TIMEOUT) || defined(__DOXYGEN__)
+#define STM32_MAC_PHY_TIMEOUT 100
+#endif
+
+/**
* @brief ETHD1 interrupt priority level setting.
*/
#if !defined(STM32_ETH1_IRQ_PRIORITY) || defined(__DOXYGEN__)
#define STM32_ETH1_IRQ_PRIORITY 13
#endif
+
+/**
+ * @brief IP checksum offload.
+ * @details The following modes are available:
+ * - 0 Function disabled.
+ * - 1 Only IP header checksum calculation and insertion are enabled.
+ * - 2 IP header checksum and payload checksum calculation and
+ * insertion are enabled, but pseudo-header checksum is not
+ * calculated in hardware.
+ * - 3 IP Header checksum and payload checksum calculation and
+ * insertion are enabled, and pseudo-header checksum is
+ * calculated in hardware.
+ * .
+ */
+#if !defined(STM32_IP_CHECKSUM_OFFLOAD) || defined(__DOXYGEN__)
+#define STM32_IP_CHECKSUM_OFFLOAD 0
+#endif
/** @} */
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
+#if (STM32_MAC_PHY_TIMEOUT > 0) && !HAL_IMPLEMENTS_COUNTERS
+#error "STM32_MAC_PHY_TIMEOUT requires the realtime counter service"
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
diff --git a/os/hal/platforms/STM32/sdc_lld.c b/os/hal/platforms/STM32/sdc_lld.c index 61d91b044..d3f251b99 100644 --- a/os/hal/platforms/STM32/sdc_lld.c +++ b/os/hal/platforms/STM32/sdc_lld.c @@ -374,7 +374,7 @@ void sdc_lld_stop(SDCDriver *sdcp) { }
/**
- * @brief Starts the SDIO clock and sets it to init mode (400KHz or less).
+ * @brief Starts the SDIO clock and sets it to init mode (400kHz or less).
*
* @param[in] sdcp pointer to the @p SDCDriver object
*
@@ -383,7 +383,7 @@ void sdc_lld_stop(SDCDriver *sdcp) { void sdc_lld_start_clk(SDCDriver *sdcp) {
(void)sdcp;
- /* Initial clock setting: 400KHz, 1bit mode.*/
+ /* Initial clock setting: 400kHz, 1bit mode.*/
SDIO->CLKCR = STM32_SDIO_DIV_LS;
SDIO->POWER |= SDIO_POWER_PWRCTRL_0 | SDIO_POWER_PWRCTRL_1;
SDIO->CLKCR |= SDIO_CLKCR_CLKEN;
diff --git a/os/hal/platforms/STM32/serial_lld.h b/os/hal/platforms/STM32/serial_lld.h index 41d10c080..7589da600 100644 --- a/os/hal/platforms/STM32/serial_lld.h +++ b/os/hal/platforms/STM32/serial_lld.h @@ -108,7 +108,7 @@ * @brief USART2 interrupt priority level setting.
*/
#if !defined(STM32_SERIAL_USART2_PRIORITY) || defined(__DOXYGEN__)
-#define STM32_SERIAL_USART2_PRIORITY 12)
+#define STM32_SERIAL_USART2_PRIORITY 12
#endif
/**
diff --git a/os/hal/platforms/STM32F1xx/platform.dox b/os/hal/platforms/STM32F1xx/platform.dox index c9e9bf1a3..0dc3a988b 100644 --- a/os/hal/platforms/STM32F1xx/platform.dox +++ b/os/hal/platforms/STM32F1xx/platform.dox @@ -388,7 +388,7 @@ * @section stm32f1xx_rcc_2 STM32F1xx RCC driver implementation features
* - Peripherals reset.
* - Peripherals clock enable.
- * - Periplerals clock disable.
+ * - Peripherals clock disable.
* .
* @ingroup STM32F1xx_PLATFORM_DRIVERS
*/
diff --git a/os/hal/platforms/STM32F1xx/stm32_dma.c b/os/hal/platforms/STM32F1xx/stm32_dma.c index 59987cd82..8e0622218 100644 --- a/os/hal/platforms/STM32F1xx/stm32_dma.c +++ b/os/hal/platforms/STM32F1xx/stm32_dma.c @@ -29,7 +29,7 @@ * drivers to coordinate the access to the resource.
* @note The DMA ISR handlers are all declared into this module because
* sharing, the various device drivers can associate a callback to
- * IRSs when allocating streams.
+ * ISRs when allocating streams.
* @{
*/
diff --git a/os/hal/platforms/STM32F2xx/adc_lld.h b/os/hal/platforms/STM32F2xx/adc_lld.h index 737fa05c9..0ed939462 100644 --- a/os/hal/platforms/STM32F2xx/adc_lld.h +++ b/os/hal/platforms/STM32F2xx/adc_lld.h @@ -40,12 +40,12 @@ * @{
*/
/**
- * @brief Maximum HSE clock frequency.
+ * @brief Minimum ADC clock frequency.
*/
#define STM32_ADCCLK_MIN 600000
/**
- * @brief Maximum HSE clock frequency.
+ * @brief Maximum ADC clock frequency.
*/
#define STM32_ADCCLK_MAX 30000000
/** @} */
diff --git a/os/hal/platforms/STM32F2xx/hal_lld.h b/os/hal/platforms/STM32F2xx/hal_lld.h index 165a10448..c93aa29a7 100644 --- a/os/hal/platforms/STM32F2xx/hal_lld.h +++ b/os/hal/platforms/STM32F2xx/hal_lld.h @@ -400,10 +400,10 @@ #define STM32_HAS_USART3 TRUE
#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))
-#define STM32_USART3_RX_DMA_CHN 0x00400400
+#define STM32_USART3_RX_DMA_CHN 0x00000040
#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) | \
STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART3_TX_DMA_CHN 0x00074040
+#define STM32_USART3_TX_DMA_CHN 0x00074000
#define STM32_HAS_UART4 TRUE
#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
diff --git a/os/hal/platforms/STM32F2xx/platform.dox b/os/hal/platforms/STM32F2xx/platform.dox index e247a1779..536a9780a 100644 --- a/os/hal/platforms/STM32F2xx/platform.dox +++ b/os/hal/platforms/STM32F2xx/platform.dox @@ -306,7 +306,7 @@ * @section stm32f2xx_rcc_2 STM32F2xx RCC driver implementation features
* - Peripherals reset.
* - Peripherals clock enable.
- * - Periplerals clock disable.
+ * - Peripherals clock disable.
* .
* @ingroup STM32F2xx_PLATFORM_DRIVERS
*/
diff --git a/os/hal/platforms/STM32F2xx/platform.mk b/os/hal/platforms/STM32F2xx/platform.mk index 37b37bc93..92dca2228 100644 --- a/os/hal/platforms/STM32F2xx/platform.mk +++ b/os/hal/platforms/STM32F2xx/platform.mk @@ -6,17 +6,18 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F2xx/stm32_dma.c \ ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/i2c_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \
+ ${CHIBIOS}/os/hal/platforms/STM32/mac_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/uart_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
+ ${CHIBIOS}/os/hal/platforms/STM32/OTGv1/usb_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/RTCv2/rtc_lld.c
# Required include directories
PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F2xx \
${CHIBIOS}/os/hal/platforms/STM32 \
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \
- ${CHIBIOS}/os/hal/platforms/STM32/RTCv2 \
-
-
+ ${CHIBIOS}/os/hal/platforms/STM32/OTGv1 \
+ ${CHIBIOS}/os/hal/platforms/STM32/RTCv2
diff --git a/os/hal/platforms/STM32F2xx/stm32_dma.c b/os/hal/platforms/STM32F2xx/stm32_dma.c index 3c1aac444..8e0226747 100644 --- a/os/hal/platforms/STM32F2xx/stm32_dma.c +++ b/os/hal/platforms/STM32F2xx/stm32_dma.c @@ -29,7 +29,7 @@ * drivers to coordinate the access to the resource.
* @note The DMA ISR handlers are all declared into this module because
* sharing, the various device drivers can associate a callback to
- * IRSs when allocating streams.
+ * ISRs when allocating streams.
* @{
*/
diff --git a/os/hal/platforms/STM32F2xx/stm32_rcc.h b/os/hal/platforms/STM32F2xx/stm32_rcc.h index c624279ea..af070d814 100644 --- a/os/hal/platforms/STM32F2xx/stm32_rcc.h +++ b/os/hal/platforms/STM32F2xx/stm32_rcc.h @@ -423,6 +423,42 @@ /** @} */
/**
+ * @name ETH peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the ETH peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableETH(lp) rccEnableAHB1(RCC_AHB1ENR_ETHMACEN | \
+ RCC_AHB1ENR_ETHMACTXEN | \
+ RCC_AHB1ENR_ETHMACRXEN, lp)
+
+/**
+ * @brief Disables the ETH peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableETH(lp) rccDisableAHB1(RCC_AHB1ENR_ETHMACEN | \
+ RCC_AHB1ENR_ETHMACTXEN | \
+ RCC_AHB1ENR_ETHMACRXEN, lp)
+
+/**
+ * @brief Resets the ETH peripheral.
+ *
+ * @api
+ */
+#define rccResetETH() rccResetAHB1(RCC_AHB1RSTR_ETHMACRST)
+/** @} */
+
+/**
* @name I2C peripherals specific RCC operations
* @{
*/
@@ -503,6 +539,36 @@ /** @} */
/**
+ * @name OTG peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the OTG_FS peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableOTG_FS(lp) rccEnableAHB2(RCC_AHB2LPENR_OTGFSLPEN, lp)
+
+/**
+ * @brief Disables the OTG_FS peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableOTG_FS(lp) rccEnableAHB2(RCC_AHB2LPENR_OTGFSLPEN, lp)
+
+/**
+ * @brief Resets the OTG_FS peripheral.
+ *
+ * @api
+ */
+#define rccResetOTG_FS() rccResetAHB2(RCC_AHB2RSTR_OTGFSRST)
+/** @} */
+
+/**
* @name SPI peripherals specific RCC operations
* @{
*/
diff --git a/os/hal/platforms/STM32F4xx/adc_lld.h b/os/hal/platforms/STM32F4xx/adc_lld.h index 21723bd70..5f8a8d179 100644 --- a/os/hal/platforms/STM32F4xx/adc_lld.h +++ b/os/hal/platforms/STM32F4xx/adc_lld.h @@ -40,12 +40,12 @@ * @{
*/
/**
- * @brief Maximum HSE clock frequency.
+ * @brief Minimum ADC clock frequency.
*/
#define STM32_ADCCLK_MIN 600000
/**
- * @brief Maximum HSE clock frequency.
+ * @brief Maximum ADC clock frequency.
*/
#define STM32_ADCCLK_MAX 36000000
/** @} */
diff --git a/os/hal/platforms/STM32F4xx/hal_lld.h b/os/hal/platforms/STM32F4xx/hal_lld.h index 3585379e4..06bd3e198 100644 --- a/os/hal/platforms/STM32F4xx/hal_lld.h +++ b/os/hal/platforms/STM32F4xx/hal_lld.h @@ -402,10 +402,10 @@ #define STM32_HAS_USART3 TRUE
#define STM32_USART3_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 1))
-#define STM32_USART3_RX_DMA_CHN 0x00400400
+#define STM32_USART3_RX_DMA_CHN 0x00000040
#define STM32_USART3_TX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 3) | \
STM32_DMA_STREAM_ID_MSK(1, 4))
-#define STM32_USART3_TX_DMA_CHN 0x00074040
+#define STM32_USART3_TX_DMA_CHN 0x00074000
#define STM32_HAS_UART4 TRUE
#define STM32_UART4_RX_DMA_MSK (STM32_DMA_STREAM_ID_MSK(1, 2))
diff --git a/os/hal/platforms/STM32F4xx/platform.dox b/os/hal/platforms/STM32F4xx/platform.dox index 7b847ee0b..386924d42 100644 --- a/os/hal/platforms/STM32F4xx/platform.dox +++ b/os/hal/platforms/STM32F4xx/platform.dox @@ -306,7 +306,7 @@ * @section stm32f4xx_rcc_2 STM32F4xx RCC driver implementation features
* - Peripherals reset.
* - Peripherals clock enable.
- * - Periplerals clock disable.
+ * - Peripherals clock disable.
* .
* @ingroup STM32F4xx_PLATFORM_DRIVERS
*/
diff --git a/os/hal/platforms/STM32F4xx/platform.mk b/os/hal/platforms/STM32F4xx/platform.mk index fa9caef41..5194488b8 100644 --- a/os/hal/platforms/STM32F4xx/platform.mk +++ b/os/hal/platforms/STM32F4xx/platform.mk @@ -6,16 +6,19 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/platforms/STM32F4xx/stm32_dma.c \ ${CHIBIOS}/os/hal/platforms/STM32/gpt_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/i2c_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/icu_lld.c \
+ ${CHIBIOS}/os/hal/platforms/STM32/mac_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/pwm_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/serial_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/spi_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/uart_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2/pal_lld.c \
+ ${CHIBIOS}/os/hal/platforms/STM32/OTGv1/usb_lld.c \
${CHIBIOS}/os/hal/platforms/STM32/RTCv2/rtc_lld.c \
- ${CHIBIOS}/os/hal/platforms/STM32/RTCv2/sdc_lld.c
+ ${CHIBIOS}/os/hal/platforms/STM32/sdc_lld.c
# Required include directories
PLATFORMINC = ${CHIBIOS}/os/hal/platforms/STM32F4xx \
${CHIBIOS}/os/hal/platforms/STM32 \
${CHIBIOS}/os/hal/platforms/STM32/GPIOv2 \
- ${CHIBIOS}/os/hal/platforms/STM32/RTCv2
+ ${CHIBIOS}/os/hal/platforms/STM32/OTGv1 \
+ ${CHIBIOS}/os/hal/platforms/STM32/RTCv2
\ No newline at end of file diff --git a/os/hal/platforms/STM32F4xx/stm32_dma.c b/os/hal/platforms/STM32F4xx/stm32_dma.c index 46a68a8e1..32d7eafcf 100644 --- a/os/hal/platforms/STM32F4xx/stm32_dma.c +++ b/os/hal/platforms/STM32F4xx/stm32_dma.c @@ -29,7 +29,7 @@ * drivers to coordinate the access to the resource.
* @note The DMA ISR handlers are all declared into this module because
* sharing, the various device drivers can associate a callback to
- * IRSs when allocating streams.
+ * ISRs when allocating streams.
* @{
*/
diff --git a/os/hal/platforms/STM32F4xx/stm32_rcc.h b/os/hal/platforms/STM32F4xx/stm32_rcc.h index 181a2547c..0ba4a392d 100644 --- a/os/hal/platforms/STM32F4xx/stm32_rcc.h +++ b/os/hal/platforms/STM32F4xx/stm32_rcc.h @@ -423,6 +423,42 @@ /** @} */
/**
+ * @name ETH peripheral specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the ETH peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableETH(lp) rccEnableAHB1(RCC_AHB1ENR_ETHMACEN | \
+ RCC_AHB1ENR_ETHMACTXEN | \
+ RCC_AHB1ENR_ETHMACRXEN, lp)
+
+/**
+ * @brief Disables the ETH peripheral clock.
+ * @note The @p lp parameter is ignored in this family.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableETH(lp) rccDisableAHB1(RCC_AHB1ENR_ETHMACEN | \
+ RCC_AHB1ENR_ETHMACTXEN | \
+ RCC_AHB1ENR_ETHMACRXEN, lp)
+
+/**
+ * @brief Resets the ETH peripheral.
+ *
+ * @api
+ */
+#define rccResetETH() rccResetAHB1(RCC_AHB1RSTR_ETHMACRST)
+/** @} */
+
+/**
* @name I2C peripherals specific RCC operations
* @{
*/
@@ -503,6 +539,36 @@ /** @} */
/**
+ * @name OTG peripherals specific RCC operations
+ * @{
+ */
+/**
+ * @brief Enables the OTG_FS peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccEnableOTG_FS(lp) rccEnableAHB2(RCC_AHB2LPENR_OTGFSLPEN, lp)
+
+/**
+ * @brief Disables the OTG_FS peripheral clock.
+ *
+ * @param[in] lp low power enable flag
+ *
+ * @api
+ */
+#define rccDisableOTG_FS(lp) rccEnableAHB2(RCC_AHB2LPENR_OTGFSLPEN, lp)
+
+/**
+ * @brief Resets the OTG_FS peripheral.
+ *
+ * @api
+ */
+#define rccResetOTG_FS() rccResetAHB2(RCC_AHB2RSTR_OTGFSRST)
+/** @} */
+
+/**
* @name SDIO peripheral specific RCC operations
* @{
*/
diff --git a/os/hal/platforms/STM32L1xx/hal_lld.h b/os/hal/platforms/STM32L1xx/hal_lld.h index f7402dfe6..38f910f2d 100644 --- a/os/hal/platforms/STM32L1xx/hal_lld.h +++ b/os/hal/platforms/STM32L1xx/hal_lld.h @@ -149,10 +149,10 @@ * @{
*/
#define STM32_MSIRANGE_MASK (7 << 13) /**< MSIRANGE field mask. */
-#define STM32_MSIRANGE_64K (0 << 13) /**< 64KHz nominal. */
-#define STM32_MSIRANGE_128K (1 << 13) /**< 128KHz nominal. */
-#define STM32_MSIRANGE_256K (2 << 13) /**< 256KHz nominal. */
-#define STM32_MSIRANGE_512K (3 << 13) /**< 512KHz nominal. */
+#define STM32_MSIRANGE_64K (0 << 13) /**< 64kHz nominal. */
+#define STM32_MSIRANGE_128K (1 << 13) /**< 128kHz nominal. */
+#define STM32_MSIRANGE_256K (2 << 13) /**< 256kHz nominal. */
+#define STM32_MSIRANGE_512K (3 << 13) /**< 512kHz nominal. */
#define STM32_MSIRANGE_1M (4 << 13) /**< 1MHz nominal. */
#define STM32_MSIRANGE_2M (5 << 13) /**< 2MHz nominal. */
#define STM32_MSIRANGE_4M (6 << 13) /**< 4MHz nominal */
@@ -678,7 +678,7 @@ #error "impossible to activate LSE"
#endif
#if (STM32_LSECLK < 1000) || (STM32_LSECLK > 1000000)
-#error "STM32_LSECLK outside acceptable range (1...1000KHz)"
+#error "STM32_LSECLK outside acceptable range (1...1000kHz)"
#endif
#else /* !STM32_LSE_ENABLED */
#if STM_RTCCLK == STM32_LSECLK
diff --git a/os/hal/platforms/STM32L1xx/platform.dox b/os/hal/platforms/STM32L1xx/platform.dox index 744f1b673..fe845811e 100644 --- a/os/hal/platforms/STM32L1xx/platform.dox +++ b/os/hal/platforms/STM32L1xx/platform.dox @@ -305,7 +305,7 @@ * @section stm32l1xx_rcc_2 STM32L1xx RCC driver implementation features
* - Peripherals reset.
* - Peripherals clock enable.
- * - Periplerals clock disable.
+ * - Peripherals clock disable.
* .
* @ingroup STM32L1xx_PLATFORM_DRIVERS
*/
diff --git a/os/hal/platforms/STM32L1xx/stm32_dma.c b/os/hal/platforms/STM32L1xx/stm32_dma.c index 85841ad9f..0e6d52404 100644 --- a/os/hal/platforms/STM32L1xx/stm32_dma.c +++ b/os/hal/platforms/STM32L1xx/stm32_dma.c @@ -29,7 +29,7 @@ * drivers to coordinate the access to the resource.
* @note The DMA ISR handlers are all declared into this module because
* sharing, the various device drivers can associate a callback to
- * IRSs when allocating streams.
+ * ISRs when allocating streams.
* @{
*/
diff --git a/os/hal/platforms/STM32L1xx/stm32l1xx.h b/os/hal/platforms/STM32L1xx/stm32l1xx.h index 9c665d29b..0870e768e 100644 --- a/os/hal/platforms/STM32L1xx/stm32l1xx.h +++ b/os/hal/platforms/STM32L1xx/stm32l1xx.h @@ -2602,10 +2602,10 @@ typedef struct #define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00) /*!< Internal High Speed clock trimming */
#define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000) /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000) /*!< Internal Multi Speed clock Range 65.536 KHz */
-#define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000) /*!< Internal Multi Speed clock Range 131.072 KHz */
-#define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000) /*!< Internal Multi Speed clock Range 262.144 KHz */
-#define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000) /*!< Internal Multi Speed clock Range 524.288 KHz */
+#define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000) /*!< Internal Multi Speed clock Range 65.536 kHz */
+#define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000) /*!< Internal Multi Speed clock Range 131.072 kHz */
+#define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000) /*!< Internal Multi Speed clock Range 262.144 kHz */
+#define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000) /*!< Internal Multi Speed clock Range 524.288 kHz */
#define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000) /*!< Internal Multi Speed clock Range 1.048 MHz */
#define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000) /*!< Internal Multi Speed clock Range 2.097 MHz */
#define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000) /*!< Internal Multi Speed clock Range 4.194 MHz */
diff --git a/os/hal/platforms/STM8L/hal_lld.c b/os/hal/platforms/STM8L/hal_lld.c index 5cfc5b0cd..4ba2076a7 100644 --- a/os/hal/platforms/STM8L/hal_lld.c +++ b/os/hal/platforms/STM8L/hal_lld.c @@ -108,7 +108,7 @@ void hal_lld_init(void) { #endif
/* Clocks initially all disabled, note the boot ROM clock is disabled
- because the boot loader is no more required and it draws pretious uAs.*/
+ because the boot loader is no more required and it draws precious uAs.*/
CLK->PCKENR1 = 0;
CLK->PCKENR2 = 0;
CLK->PCKENR3 = 0;
diff --git a/os/hal/src/i2s.c b/os/hal/src/i2s.c new file mode 100644 index 000000000..99e4246ad --- /dev/null +++ b/os/hal/src/i2s.c @@ -0,0 +1,179 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file i2s.c
+ * @brief I2S Driver code.
+ *
+ * @addtogroup I2S
+ * @{
+ */
+
+#include "ch.h"
+#include "hal.h"
+
+#if HAL_USE_I2S || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief I2S Driver initialization.
+ * @note This function is implicitly invoked by @p halInit(), there is
+ * no need to explicitly initialize the driver.
+ *
+ * @init
+ */
+void i2sInit(void) {
+
+ i2s_lld_init();
+}
+
+/**
+ * @brief Initializes the standard part of a @p I2SDriver structure.
+ *
+ * @param[out] i2sp pointer to the @p I2SDriver object
+ *
+ * @init
+ */
+void i2sObjectInit(I2SDriver *i2sp) {
+
+ i2sp->state = I2S_STOP;
+ i2sp->config = NULL;
+}
+
+/**
+ * @brief Configures and activates the I2S peripheral.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ * @param[in] config pointer to the @p I2SConfig object
+ *
+ * @api
+ */
+void i2sStart(I2SDriver *i2sp, const I2SConfig *config) {
+
+ chDbgCheck((i2sp != NULL) && (config != NULL), "i2sStart");
+
+ chSysLock();
+ chDbgAssert((i2sp->state == I2S_STOP) || (i2sp->state == I2S_READY),
+ "i2sStart(), #1", "invalid state");
+ i2sp->config = config;
+ i2s_lld_start(i2sp);
+ i2sp->state = I2S_READY;
+ chSysUnlock();
+}
+
+/**
+ * @brief Deactivates the I2S peripheral.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ *
+ * @api
+ */
+void i2sStop(I2SDriver *i2sp) {
+
+ chDbgCheck(i2sp != NULL, "i2sStop");
+
+ chSysLock();
+ chDbgAssert((i2sp->state == I2S_STOP) || (i2sp->state == I2S_READY),
+ "i2sStop(), #1", "invalid state");
+ i2s_lld_stop(i2sp);
+ i2sp->state = I2S_STOP;
+ chSysUnlock();
+}
+
+/**
+ * @brief Starts a I2S data exchange.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ *
+ * @api
+ */
+void i2sStartExchange(I2SDriver *i2sp) {
+
+ chDbgCheck(i2sp != NULL "i2sStartExchange");
+
+ chSysLock();
+ chDbgAssert(i2sp->state == I2S_READY,
+ "i2sStartExchange(), #1", "not ready");
+ i2sStartExchangeI(i2sp);
+ chSysUnlock();
+}
+
+/**
+ * @brief Starts a I2S data exchange in continuous mode.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ *
+ * @api
+ */
+void i2sStartExchangeContinuous(I2SDriver *i2sp) {
+
+ chDbgCheck(i2sp != NULL "i2sStartExchangeContinuous");
+
+ chSysLock();
+ chDbgAssert(i2sp->state == I2S_READY,
+ "i2sStartExchangeContinuous(), #1", "not ready");
+ i2sStartExchangeContinuousI(i2sp);
+ chSysUnlock();
+}
+
+/**
+ * @brief Stops the ongoing data exchange.
+ * @details The ongoing data exchange, if any, is stopped, if the driver
+ * was not active the function does nothing.
+ *
+ * @param[in] i2sp pointer to the @p I2SDriver object
+ *
+ * @api
+ */
+void i2sStopExchange(I2SDriver *i2sp) {
+
+ chDbgCheck((i2sp != NULL), "i2sStopExchange");
+
+ chSysLock();
+ chDbgAssert((i2sp->state == I2S_READY) ||
+ (i2sp->state == I2S_ACTIVE) ||
+ (i2sp->state == I2S_COMPLETE),
+ "i2sStopExchange(), #1", "not ready");
+ i2sStopExchangeI(i2sp);
+ chSysUnlock();
+}
+
+#endif /* HAL_USE_I2S */
+
+/** @} */
diff --git a/os/hal/src/mmc_spi.c b/os/hal/src/mmc_spi.c index c7b3372f2..c022e4a68 100644 --- a/os/hal/src/mmc_spi.c +++ b/os/hal/src/mmc_spi.c @@ -96,7 +96,7 @@ static uint8_t crc7(uint8_t crc, const uint8_t *buffer, size_t len) { }
/**
- * @brief Inserion monitor timer callback function.
+ * @brief Insertion monitor timer callback function.
*
* @param[in] p pointer to the @p MMCDriver object
*
diff --git a/os/hal/templates/halconf.h b/os/hal/templates/halconf.h index 6f4279ec4..f28d8f030 100644 --- a/os/hal/templates/halconf.h +++ b/os/hal/templates/halconf.h @@ -292,7 +292,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/os/hal/templates/icu_lld.h b/os/hal/templates/icu_lld.h index 4b0568102..56ce3af98 100644 --- a/os/hal/templates/icu_lld.h +++ b/os/hal/templates/icu_lld.h @@ -17,6 +17,10 @@ You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
+/*
+ Concepts and parts of this file have been contributed by Fabio Utzig and
+ Xo Wang.
+ */
/**
* @file templates/icu_lld.h
@@ -88,6 +92,10 @@ typedef struct { * @brief Callback for cycle period measurement.
*/
icucallback_t period_cb;
+ /**
+ * @brief Callback for timer overflow.
+ */
+ icucallback_t overflow_cb;
/* End of the mandatory fields.*/
} ICUConfig;
diff --git a/os/hal/templates/mac_lld.c b/os/hal/templates/mac_lld.c index f8d99e330..41c8f331a 100644 --- a/os/hal/templates/mac_lld.c +++ b/os/hal/templates/mac_lld.c @@ -114,7 +114,7 @@ msg_t max_lld_get_transmit_descriptor(MACDriver *macp, * @brief Writes to a transmit descriptor's stream.
*
* @param[in] tdp pointer to a @p MACTransmitDescriptor structure
- * @param[in] buf pointer to the buffer cointaining the data to be
+ * @param[in] buf pointer to the buffer containing the data to be
* written
* @param[in] size number of bytes to be written
* @return The number of bytes written into the descriptor's
diff --git a/os/kernel/include/chioch.h b/os/kernel/include/chioch.h index e9c1044ce..27e2abbb4 100644 --- a/os/kernel/include/chioch.h +++ b/os/kernel/include/chioch.h @@ -317,7 +317,7 @@ typedef struct { /**
* @brief Adds status flags to the channel's mask.
- * @details This function is usually called from the I/O ISTs in order to
+ * @details This function is usually called from the I/O ISRs in order to
* notify I/O conditions such as data events, errors, signal
* changes etc.
*
diff --git a/os/kernel/include/chmempools.h b/os/kernel/include/chmempools.h index 8a0d6f47d..a920e2579 100644 --- a/os/kernel/include/chmempools.h +++ b/os/kernel/include/chmempools.h @@ -75,10 +75,50 @@ typedef struct { #define MEMORYPOOL_DECL(name, size, provider) \
MemoryPool name = _MEMORYPOOL_DATA(name, size, provider)
+/**
+ * @name Macro Functions
+ * @{
+ */
+/**
+ * @brief Adds an object to a memory pool.
+ * @pre The memory pool must be already been initialized.
+ * @pre The added object must be of the right size for the specified
+ * memory pool.
+ * @pre The added object must be memory aligned to the size of
+ * @p stkalign_t type.
+ * @note This function is just an alias for @p chPoolFree() and has been
+ * added for clarity.
+ *
+ * @param[in] mp pointer to a @p MemoryPool structure
+ * @param[in] objp the pointer to the object to be added
+ *
+ * @api
+ */
+#define chPoolAdd(mp, objp) chPoolFree(mp, objp)
+
+/**
+ * @brief Adds an object to a memory pool.
+ * @pre The memory pool must be already been initialized.
+ * @pre The added object must be of the right size for the specified
+ * memory pool.
+ * @pre The added object must be memory aligned to the size of
+ * @p stkalign_t type.
+ * @note This function is just an alias for @p chPoolFree() and has been
+ * added for clarity.
+ *
+ * @param[in] mp pointer to a @p MemoryPool structure
+ * @param[in] objp the pointer to the object to be added
+ *
+ * @iclass
+ */
+#define chPoolAddI(mp, objp) chPoolFreeI(mp, objp)
+/** @} */
+
#ifdef __cplusplus
extern "C" {
#endif
void chPoolInit(MemoryPool *mp, size_t size, memgetfunc_t provider);
+ void chPoolLoadArray(MemoryPool *mp, void *p, size_t n);
void *chPoolAllocI(MemoryPool *mp);
void *chPoolAlloc(MemoryPool *mp);
void chPoolFreeI(MemoryPool *mp, void *objp);
diff --git a/os/kernel/include/chschd.h b/os/kernel/include/chschd.h index 215398659..3d1d37f7c 100644 --- a/os/kernel/include/chschd.h +++ b/os/kernel/include/chschd.h @@ -205,7 +205,7 @@ extern "C" { #endif /* !defined(PORT_OPTIMIZED_DOYIELDS) */
/**
- * @brief Inlineable preemption code.
+ * @brief Inline-able preemption code.
* @details This is the common preemption code, this function must be invoked
* exclusively from the port layer.
*
diff --git a/os/kernel/include/chvt.h b/os/kernel/include/chvt.h index 355f66064..5d4f674fc 100644 --- a/os/kernel/include/chvt.h +++ b/os/kernel/include/chvt.h @@ -46,7 +46,7 @@ #define S2ST(sec) ((systime_t)((sec) * CH_FREQUENCY))
/**
- * @brief Milliseconds t0 system ticks.
+ * @brief Milliseconds to system ticks.
* @details Converts from milliseconds to system ticks number.
* @note The result is rounded upward to the next tick boundary.
*
diff --git a/os/kernel/src/chevents.c b/os/kernel/src/chevents.c index 6749255e8..2b3247543 100644 --- a/os/kernel/src/chevents.c +++ b/os/kernel/src/chevents.c @@ -376,7 +376,7 @@ eventmask_t chEvtWaitAll(eventmask_t mask) { * This means that Event Listeners with a lower event identifier have
* an higher priority.
*
- * @param[in] mask mask of the event flagss that the function should wait
+ * @param[in] mask mask of the event flags that the function should wait
* for, @p ALL_EVENTS enables all the events
* @param[in] time the number of ticks before the operation timeouts,
* the following special values are allowed:
diff --git a/os/kernel/src/chheap.c b/os/kernel/src/chheap.c index f84276779..1e7f99dce 100644 --- a/os/kernel/src/chheap.c +++ b/os/kernel/src/chheap.c @@ -31,7 +31,7 @@ * are guaranteed to be thread safe.<br>
* By enabling the @p CH_USE_MALLOC_HEAP option the heap manager
* will use the runtime-provided @p malloc() and @p free() as
- * backend for the heap APIs instead of the system provided
+ * back end for the heap APIs instead of the system provided
* allocator.
* @pre In order to use the heap APIs the @p CH_USE_HEAP option must
* be enabled in @p chconf.h.
diff --git a/os/kernel/src/chmboxes.c b/os/kernel/src/chmboxes.c index 86f88dce7..163f93f20 100644 --- a/os/kernel/src/chmboxes.c +++ b/os/kernel/src/chmboxes.c @@ -364,6 +364,7 @@ msg_t chMBFetchI(Mailbox *mbp, msg_t *msgp) { if (chSemGetCounterI(&mbp->mb_fullsem) <= 0)
return RDY_TIMEOUT;
+ chSemFastWaitI(&mbp->mb_fullsem);
*msgp = *mbp->mb_rdptr++;
if (mbp->mb_rdptr >= mbp->mb_top)
mbp->mb_rdptr = mbp->mb_buffer;
diff --git a/os/kernel/src/chmempools.c b/os/kernel/src/chmempools.c index 6d1f7e866..8ef5cc403 100644 --- a/os/kernel/src/chmempools.c +++ b/os/kernel/src/chmempools.c @@ -61,7 +61,33 @@ void chPoolInit(MemoryPool *mp, size_t size, memgetfunc_t provider) { }
/**
+ * @brief Loads a memory pool with an array of static objects.
+ * @pre The memory pool must be already been initialized.
+ * @pre The array elements must be of the right size for the specified
+ * memory pool.
+ * @post The memory pool contains the elements of the input array.
+ *
+ * @param[in] mp pointer to a @p MemoryPool structure
+ * @param[in] p pointer to the array first element
+ * @param[in] n number of elements in the array
+ *
+ * @api
+ */
+void chPoolLoadArray(MemoryPool *mp, void *p, size_t n) {
+
+ chDbgCheck((mp != NULL) && MEM_IS_ALIGNED(p) && (n != 0),
+ "chPoolLoadArray");
+
+ while (n) {
+ chPoolAdd(mp, p);
+ p = (void *)(((uint8_t *)p) + mp->mp_object_size);
+ n--;
+ }
+}
+
+/**
* @brief Allocates an object from a memory pool.
+ * @pre The memory pool must be already been initialized.
*
* @param[in] mp pointer to a @p MemoryPool structure
* @return The pointer to the allocated object.
@@ -84,6 +110,7 @@ void *chPoolAllocI(MemoryPool *mp) { /**
* @brief Allocates an object from a memory pool.
+ * @pre The memory pool must be already been initialized.
*
* @param[in] mp pointer to a @p MemoryPool structure
* @return The pointer to the allocated object.
@@ -101,14 +128,15 @@ void *chPoolAlloc(MemoryPool *mp) { }
/**
- * @brief Releases (or adds) an object into (to) a memory pool.
+ * @brief Releases an object into a memory pool.
+ * @pre The memory pool must be already been initialized.
* @pre The freed object must be of the right size for the specified
* memory pool.
* @pre The freed object must be memory aligned to the size of
* @p stkalign_t type.
*
* @param[in] mp pointer to a @p MemoryPool structure
- * @param[in] objp the pointer to the object to be released or added
+ * @param[in] objp the pointer to the object to be released
*
* @iclass
*/
@@ -124,14 +152,15 @@ void chPoolFreeI(MemoryPool *mp, void *objp) { }
/**
- * @brief Releases (or adds) an object into (to) a memory pool.
+ * @brief Releases an object into a memory pool.
+ * @pre The memory pool must be already been initialized.
* @pre The freed object must be of the right size for the specified
* memory pool.
* @pre The freed object must be memory aligned to the size of
* @p stkalign_t type.
*
* @param[in] mp pointer to a @p MemoryPool structure
- * @param[in] objp the pointer to the object to be released or added
+ * @param[in] objp the pointer to the object to be released
*
* @api
*/
@@ -141,6 +170,7 @@ void chPoolFree(MemoryPool *mp, void *objp) { chPoolFreeI(mp, objp);
chSysUnlock();
}
+
#endif /* CH_USE_MEMPOOLS */
/** @} */
diff --git a/os/kernel/src/chmtx.c b/os/kernel/src/chmtx.c index 975a63094..20a4700fe 100644 --- a/os/kernel/src/chmtx.c +++ b/os/kernel/src/chmtx.c @@ -117,14 +117,14 @@ void chMtxLockS(Mutex *mp) { chDbgCheckClassS();
chDbgCheck(mp != NULL, "chMtxLockS");
- /* Ia the mutex already locked? */
+ /* Is the mutex already locked? */
if (mp->m_owner != NULL) {
/* Priority inheritance protocol; explores the thread-mutex dependencies
boosting the priority of all the affected threads to equal the priority
of the running thread requesting the mutex.*/
Thread *tp = mp->m_owner;
/* Does the running thread have higher priority than the mutex
- ownning thread? */
+ owning thread? */
while (tp->p_prio < ctp->p_prio) {
/* Make priority of thread tp match the running thread's priority.*/
tp->p_prio = ctp->p_prio;
@@ -258,7 +258,7 @@ Mutex *chMtxUnlock(void) { chDbgAssert(ctp->p_mtxlist->m_owner == ctp,
"chMtxUnlock(), #2",
"ownership failure");
- /* Removes the top Mutex from the Threads's owned mutexes list and matk it
+ /* Removes the top Mutex from the Thread's owned mutexes list and matk it
as not owned.*/
ump = ctp->p_mtxlist;
ctp->p_mtxlist = ump->m_next;
diff --git a/os/kernel/src/chthreads.c b/os/kernel/src/chthreads.c index eccf466d0..0be671c16 100644 --- a/os/kernel/src/chthreads.c +++ b/os/kernel/src/chthreads.c @@ -149,7 +149,7 @@ void _thread_memfill(uint8_t *startp, uint8_t *endp, uint8_t v) { */
Thread *chThdCreateI(void *wsp, size_t size,
tprio_t prio, tfunc_t pf, void *arg) {
- /* Thread structure is layed out in the lower part of the thread workspace */
+ /* Thread structure is layed out in the lower part of the thread workspace.*/
Thread *tp = wsp;
chDbgCheckClassI();
diff --git a/os/kernel/templates/chconf.h b/os/kernel/templates/chconf.h index 4115636d6..b1f2cd62c 100644 --- a/os/kernel/templates/chconf.h +++ b/os/kernel/templates/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/os/kernel/templates/chcore.c b/os/kernel/templates/chcore.c index 8115dd0cd..2fa1a234c 100644 --- a/os/kernel/templates/chcore.c +++ b/os/kernel/templates/chcore.c @@ -76,7 +76,7 @@ void port_unlock_from_isr(void) { /**
* @brief Disables all the interrupt sources.
- * @note Of course non maskable interrupt sources are not included.
+ * @note Of course non-maskable interrupt sources are not included.
*/
void port_disable(void) {
}
diff --git a/os/ports/GCC/ARM/chcore.h b/os/ports/GCC/ARM/chcore.h index 7629aea41..47fca447e 100644 --- a/os/ports/GCC/ARM/chcore.h +++ b/os/ports/GCC/ARM/chcore.h @@ -379,7 +379,7 @@ struct context { /**
* @brief Disables all the interrupt sources.
- * @note Of course non maskable interrupt sources are not included.
+ * @note Of course non-maskable interrupt sources are not included.
* @note In this port it disables both the IRQ and FIQ sources.
* @note Implements a workaround for spurious interrupts taken from the NXP
* LPC214x datasheet.
diff --git a/os/ports/GCC/ARM/rules.mk b/os/ports/GCC/ARM/rules.mk index 78841034d..40fa8c9e2 100644 --- a/os/ports/GCC/ARM/rules.mk +++ b/os/ports/GCC/ARM/rules.mk @@ -28,7 +28,7 @@ else endif
ASRC = $(ACSRC)$(ACPPSRC)
TSRC = $(TCSRC)$(TCPPSRC)
-SRCPATHS = $(sort $(dir $(ASMSRC)) $(dir $(ASRC)) $(dir $(TSRC)))
+SRCPATHS = $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(ASRC)) $(dir $(TSRC)))
# Various directories
OBJDIR = $(BUILDDIR)/obj
@@ -40,7 +40,8 @@ ACPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ACPPSRC:.cpp=.o))) TCOBJS = $(addprefix $(OBJDIR)/, $(notdir $(TCSRC:.c=.o)))
TCPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(TCPPSRC:.cpp=.o)))
ASMOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o)))
-OBJS = $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS)
+ASMXOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMXSRC:.S=.o)))
+OBJS = $(ASMXOBJS) $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS)
# Paths
IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR))
@@ -57,6 +58,7 @@ LIBS = $(DLIBS) $(ULIBS) MCFLAGS = -mcpu=$(MCU)
ODFLAGS = -x --syms
ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS)
+ASXFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS)
CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS)
CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS)
ifeq ($(USE_LINK_GC),yes)
@@ -162,6 +164,15 @@ else @$(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
endif
+$(ASMXOBJS) : $(OBJDIR)/%.o : %.S Makefile
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CC) -c $(ASXFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $<
+ @$(CC) -c $(ASXFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+endif
+
%.elf: $(OBJS) $(LDSCRIPT)
ifeq ($(USE_VERBOSE_COMPILE),yes)
@echo
diff --git a/os/ports/GCC/ARMCMx/chcore_v6m.h b/os/ports/GCC/ARMCMx/chcore_v6m.h index 644f73d79..84005f162 100644 --- a/os/ports/GCC/ARMCMx/chcore_v6m.h +++ b/os/ports/GCC/ARMCMx/chcore_v6m.h @@ -66,15 +66,13 @@ * @brief Per-thread stack overhead for interrupts servicing.
* @details This constant is used in the calculation of the correct working
* area size.
- * This value can be zero on those architecture where there is a
- * separate interrupt stack and the stack space between @p intctx and
- * @p extctx is known to be zero.
- * @note In this port it is conservatively set to 16 because the function
- * @p chSchDoReschedule() can have a stack frame, especially with
- * compiler optimizations disabled.
+ * @note In this port this value is conservatively set to 32 because the
+ * function @p chSchDoReschedule() can have a stack frame, especially
+ * with compiler optimizations disabled. The value can be reduced
+ * when compiler optimizations are enabled.
*/
#if !defined(PORT_INT_REQUIRED_STACK)
-#define PORT_INT_REQUIRED_STACK 16
+#define PORT_INT_REQUIRED_STACK 32
#endif
/**
diff --git a/os/ports/GCC/ARMCMx/chcore_v7m.c b/os/ports/GCC/ARMCMx/chcore_v7m.c index 13f78bb60..8c650a202 100644 --- a/os/ports/GCC/ARMCMx/chcore_v7m.c +++ b/os/ports/GCC/ARMCMx/chcore_v7m.c @@ -114,28 +114,6 @@ void _port_init(void) { SCB_VTOR = CORTEX_VTOR_INIT;
SCB_AIRCR = AIRCR_VECTKEY | AIRCR_PRIGROUP(0);
-#if CORTEX_USE_FPU
- {
- uint32_t reg;
-
- /* Initializing the FPU context save in lazy mode.*/
- SCB_FPCCR = FPCCR_ASPEN | FPCCR_LSPEN;
-
- /* CP10 and CP11 set to full access.*/
- SCB_CPACR |= 0x00F00000;
-
- /* Enables FPU context save/restore on exception entry/exit (FPCA bit).*/
- asm volatile ("mrs %0, CONTROL" : "=r" (reg) : : "memory");
- reg |= 4;
- asm volatile ("msr CONTROL, %0" : : "r" (reg) : "memory");
-
- /* FPSCR and FPDSCR initially zero.*/
- reg = 0;
- asm volatile ("vmsr FPSCR, %0" : : "r" (reg) : "memory");
- SCB_FPDSCR = reg;
- }
-#endif
-
/* Initialization of the system vectors used by the port.*/
nvicSetSystemHandlerPriority(HANDLER_SVCALL,
CORTEX_PRIORITY_MASK(CORTEX_PRIORITY_SVCALL));
diff --git a/os/ports/GCC/ARMCMx/chcore_v7m.h b/os/ports/GCC/ARMCMx/chcore_v7m.h index e6b616dd6..10edcc45b 100644 --- a/os/ports/GCC/ARMCMx/chcore_v7m.h +++ b/os/ports/GCC/ARMCMx/chcore_v7m.h @@ -63,15 +63,13 @@ * @brief Per-thread stack overhead for interrupts servicing.
* @details This constant is used in the calculation of the correct working
* area size.
- * This value can be zero on those architecture where there is a
- * separate interrupt stack and the stack space between @p intctx and
- * @p extctx is known to be zero.
- * @note In this port it is conservatively set to 16 because the function
- * @p chSchDoReschedule() can have a stack frame, especially with
- * compiler optimizations disabled.
+ * @note In this port this value is conservatively set to 32 because the
+ * function @p chSchDoReschedule() can have a stack frame, especially
+ * with compiler optimizations disabled. The value can be reduced
+ * when compiler optimizations are enabled.
*/
#if !defined(PORT_INT_REQUIRED_STACK)
-#define PORT_INT_REQUIRED_STACK 16
+#define PORT_INT_REQUIRED_STACK 32
#endif
/**
@@ -414,7 +412,7 @@ struct context { /**
* @brief Disables all the interrupt sources.
- * @note Of course non maskable interrupt sources are not included.
+ * @note Of course non-maskable interrupt sources are not included.
* @note In this port it disables all the interrupt sources by raising
* the priority mask to level 0.
*/
diff --git a/os/ports/GCC/ARMCMx/crt0.c b/os/ports/GCC/ARMCMx/crt0.c index fbff66fb0..bb8d3830d 100644 --- a/os/ports/GCC/ARMCMx/crt0.c +++ b/os/ports/GCC/ARMCMx/crt0.c @@ -26,10 +26,7 @@ * @{
*/
-#include <stdint.h>
-
-#define FALSE 0
-#define TRUE (!FALSE)
+#include "ch.h"
typedef void (*funcp_t)(void);
typedef funcp_t * funcpp_t;
@@ -250,7 +247,7 @@ static void fill32(uint32_t *start, uint32_t *end, uint32_t filler) { __attribute__((naked))
#endif
void ResetHandler(void) {
- uint32_t psp, ctl;
+ uint32_t psp, reg;
/* Process Stack initialization, it is allocated starting from the
symbol __process_stack_end__ and its lower limit is the symbol
@@ -259,9 +256,25 @@ void ResetHandler(void) { psp = SYMVAL(__process_stack_end__);
asm volatile ("msr PSP, %0" : : "r" (psp));
+#if CORTEX_USE_FPU
+ /* Initializing the FPU context save in lazy mode.*/
+ SCB_FPCCR = FPCCR_ASPEN | FPCCR_LSPEN;
+
+ /* CP10 and CP11 set to full access.*/
+ SCB_CPACR |= 0x00F00000;
+
+ /* FPSCR and FPDSCR initially zero.*/
+ reg = 0;
+ asm volatile ("vmsr FPSCR, %0" : : "r" (reg) : "memory");
+ SCB_FPDSCR = reg;
+
+ /* CPU mode initialization, enforced FPCA bit.*/
+ reg = CRT0_CONTROL_INIT | 4;
+#else
/* CPU mode initialization.*/
- ctl = CRT0_CONTROL_INIT;
- asm volatile ("msr CONTROL, %0" : : "r" (ctl));
+ reg = CRT0_CONTROL_INIT;
+#endif
+ asm volatile ("msr CONTROL, %0" : : "r" (reg));
asm volatile ("isb");
/* Early initialization hook invocation.*/
diff --git a/os/ports/GCC/ARMCMx/rules.mk b/os/ports/GCC/ARMCMx/rules.mk index e592683d8..111669fde 100644 --- a/os/ports/GCC/ARMCMx/rules.mk +++ b/os/ports/GCC/ARMCMx/rules.mk @@ -28,7 +28,7 @@ else endif
ASRC = $(ACSRC)$(ACPPSRC)
TSRC = $(TCSRC)$(TCPPSRC)
-SRCPATHS = $(sort $(dir $(ASMSRC)) $(dir $(ASRC)) $(dir $(TSRC)))
+SRCPATHS = $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(ASRC)) $(dir $(TSRC)))
# Various directories
OBJDIR = $(BUILDDIR)/obj
@@ -40,7 +40,8 @@ ACPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ACPPSRC:.cpp=.o))) TCOBJS = $(addprefix $(OBJDIR)/, $(notdir $(TCSRC:.c=.o)))
TCPPOBJS = $(addprefix $(OBJDIR)/, $(notdir $(TCPPSRC:.cpp=.o)))
ASMOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMSRC:.s=.o)))
-OBJS = $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS)
+ASMXOBJS = $(addprefix $(OBJDIR)/, $(notdir $(ASMXSRC:.S=.o)))
+OBJS = $(ASMXOBJS) $(ASMOBJS) $(ACOBJS) $(TCOBJS) $(ACPPOBJS) $(TCPPOBJS)
# Paths
IINCDIR = $(patsubst %,-I%,$(INCDIR) $(DINCDIR) $(UINCDIR))
@@ -57,6 +58,7 @@ LIBS = $(DLIBS) $(ULIBS) MCFLAGS = -mcpu=$(MCU)
ODFLAGS = -x --syms
ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS)
+ASXFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS)
CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS)
CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS)
ifeq ($(USE_LINK_GC),yes)
@@ -162,6 +164,15 @@ else @$(AS) -c $(ASFLAGS) -I. $(IINCDIR) $< -o $@
endif
+$(ASMXOBJS) : $(OBJDIR)/%.o : %.S Makefile
+ifeq ($(USE_VERBOSE_COMPILE),yes)
+ @echo
+ $(CC) -c $(ASXFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+else
+ @echo Compiling $<
+ @$(CC) -c $(ASXFLAGS) $(TOPT) -I. $(IINCDIR) $< -o $@
+endif
+
%.elf: $(OBJS) $(LDSCRIPT)
ifeq ($(USE_VERBOSE_COMPILE),yes)
@echo
diff --git a/os/ports/GCC/AVR/chcore.h b/os/ports/GCC/AVR/chcore.h index 18273c0d4..7f11de61b 100644 --- a/os/ports/GCC/AVR/chcore.h +++ b/os/ports/GCC/AVR/chcore.h @@ -274,7 +274,7 @@ struct context { /**
* @brief Disables all the interrupt sources.
- * @note Of course non maskable interrupt sources are not included.
+ * @note Of course non-maskable interrupt sources are not included.
* @note Implemented as global interrupt disable.
*/
#define port_disable() asm volatile ("cli" : : : "memory")
diff --git a/os/ports/GCC/MSP430/chcore.h b/os/ports/GCC/MSP430/chcore.h index 6a94f7394..d5cc1f512 100644 --- a/os/ports/GCC/MSP430/chcore.h +++ b/os/ports/GCC/MSP430/chcore.h @@ -247,7 +247,7 @@ struct context { /**
* @brief Disables all the interrupt sources.
- * @note Of course non maskable interrupt sources are not included.
+ * @note Of course non-maskable interrupt sources are not included.
* @note Implemented as global interrupt disable.
*/
#define port_disable() asm volatile ("dint" : : : "memory")
diff --git a/os/ports/IAR/ARMCMx/chcore_v6m.h b/os/ports/IAR/ARMCMx/chcore_v6m.h index 9087f3dd8..8a2ef48e5 100644 --- a/os/ports/IAR/ARMCMx/chcore_v6m.h +++ b/os/ports/IAR/ARMCMx/chcore_v6m.h @@ -66,15 +66,13 @@ * @brief Per-thread stack overhead for interrupts servicing.
* @details This constant is used in the calculation of the correct working
* area size.
- * This value can be zero on those architecture where there is a
- * separate interrupt stack and the stack space between @p intctx and
- * @p extctx is known to be zero.
- * @note In this port it is conservatively set to 16 because the function
- * @p chSchDoReschedule() can have a stack frame, especially with
- * compiler optimizations disabled.
+ * @note In this port this value is conservatively set to 32 because the
+ * function @p chSchDoReschedule() can have a stack frame, especially
+ * with compiler optimizations disabled. The value can be reduced
+ * when compiler optimizations are enabled.
*/
#if !defined(PORT_INT_REQUIRED_STACK)
-#define PORT_INT_REQUIRED_STACK 16
+#define PORT_INT_REQUIRED_STACK 32
#endif
/**
diff --git a/os/ports/IAR/ARMCMx/chcore_v7m.h b/os/ports/IAR/ARMCMx/chcore_v7m.h index c8b7f67ff..b46ef22f0 100644 --- a/os/ports/IAR/ARMCMx/chcore_v7m.h +++ b/os/ports/IAR/ARMCMx/chcore_v7m.h @@ -63,15 +63,13 @@ * @brief Per-thread stack overhead for interrupts servicing.
* @details This constant is used in the calculation of the correct working
* area size.
- * This value can be zero on those architecture where there is a
- * separate interrupt stack and the stack space between @p intctx and
- * @p extctx is known to be zero.
- * @note In this port it is conservatively set to 16 because the function
- * @p chSchDoReschedule() can have a stack frame, especially with
- * compiler optimizations disabled.
+ * @note In this port this value is conservatively set to 32 because the
+ * function @p chSchDoReschedule() can have a stack frame, especially
+ * with compiler optimizations disabled. The value can be reduced
+ * when compiler optimizations are enabled.
*/
#if !defined(PORT_INT_REQUIRED_STACK)
-#define PORT_INT_REQUIRED_STACK 16
+#define PORT_INT_REQUIRED_STACK 32
#endif
/**
@@ -402,7 +400,7 @@ struct context { /**
* @brief Disables all the interrupt sources.
- * @note Of course non maskable interrupt sources are not included.
+ * @note Of course non-maskable interrupt sources are not included.
* @note In this port it disables all the interrupt sources by raising
* the priority mask to level 0.
*/
diff --git a/os/ports/RC/STM8/chcore.h b/os/ports/RC/STM8/chcore.h index e3e853467..b72f066c4 100644 --- a/os/ports/RC/STM8/chcore.h +++ b/os/ports/RC/STM8/chcore.h @@ -256,7 +256,7 @@ struct stm8_startctx { /**
* @brief Disables all the interrupt sources.
* @note Implemented as global interrupts disable.
- * @note Of course non maskable interrupt sources are not included.
+ * @note Of course non-maskable interrupt sources are not included.
*/
#define port_disable() _sim_()
diff --git a/os/ports/RVCT/ARMCMx/chcore_v6m.h b/os/ports/RVCT/ARMCMx/chcore_v6m.h index 89ab92640..5de576a21 100644 --- a/os/ports/RVCT/ARMCMx/chcore_v6m.h +++ b/os/ports/RVCT/ARMCMx/chcore_v6m.h @@ -66,15 +66,13 @@ * @brief Per-thread stack overhead for interrupts servicing.
* @details This constant is used in the calculation of the correct working
* area size.
- * This value can be zero on those architecture where there is a
- * separate interrupt stack and the stack space between @p intctx and
- * @p extctx is known to be zero.
- * @note In this port it is conservatively set to 16 because the function
- * @p chSchDoReschedule() can have a stack frame, especially with
- * compiler optimizations disabled.
+ * @note In this port this value is conservatively set to 32 because the
+ * function @p chSchDoReschedule() can have a stack frame, especially
+ * with compiler optimizations disabled. The value can be reduced
+ * when compiler optimizations are enabled.
*/
#if !defined(PORT_INT_REQUIRED_STACK)
-#define PORT_INT_REQUIRED_STACK 16
+#define PORT_INT_REQUIRED_STACK 32
#endif
/**
diff --git a/os/ports/RVCT/ARMCMx/chcore_v7m.h b/os/ports/RVCT/ARMCMx/chcore_v7m.h index 6feaf3af5..98bbb6358 100644 --- a/os/ports/RVCT/ARMCMx/chcore_v7m.h +++ b/os/ports/RVCT/ARMCMx/chcore_v7m.h @@ -63,15 +63,13 @@ * @brief Per-thread stack overhead for interrupts servicing.
* @details This constant is used in the calculation of the correct working
* area size.
- * This value can be zero on those architecture where there is a
- * separate interrupt stack and the stack space between @p intctx and
- * @p extctx is known to be zero.
- * @note In this port it is conservatively set to 16 because the function
- * @p chSchDoReschedule() can have a stack frame, especially with
- * compiler optimizations disabled.
+ * @note In this port this value is conservatively set to 32 because the
+ * function @p chSchDoReschedule() can have a stack frame, especially
+ * with compiler optimizations disabled. The value can be reduced
+ * when compiler optimizations are enabled.
*/
#if !defined(PORT_INT_REQUIRED_STACK)
-#define PORT_INT_REQUIRED_STACK 16
+#define PORT_INT_REQUIRED_STACK 32
#endif
/**
@@ -408,7 +406,7 @@ struct context { /**
* @brief Disables all the interrupt sources.
- * @note Of course non maskable interrupt sources are not included.
+ * @note Of course non-maskable interrupt sources are not included.
* @note In this port it disables all the interrupt sources by raising
* the priority mask to level 0.
*/
diff --git a/os/ports/cosmic/STM8/chcore.h b/os/ports/cosmic/STM8/chcore.h index 5a06eea3a..895dc717e 100644 --- a/os/ports/cosmic/STM8/chcore.h +++ b/os/ports/cosmic/STM8/chcore.h @@ -253,7 +253,7 @@ struct stm8_startctx { /**
* @brief Disables all the interrupt sources.
* @note Implemented as global interrupts disable.
- * @note Of course non maskable interrupt sources are not included.
+ * @note Of course non-maskable interrupt sources are not included.
*/
#define port_disable() _asm("sim")
diff --git a/os/various/chprintf.c b/os/various/chprintf.c index 3936226c1..1b2c3329c 100644 --- a/os/various/chprintf.c +++ b/os/various/chprintf.c @@ -17,25 +17,42 @@ You should have received a copy of the GNU General Public License
along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
+/*
+ Concepts and parts of this file have been contributed by Fabio Utzig.
+ */
#include <stdarg.h>
#include "ch.h"
+#include "chprintf.h"
#define MAX_FILLER 11
+#define FLOAT_PRECISION 100000
-static char *ltoa(char *p, long num, unsigned radix) {
+static char *long_to_string_with_divisor(char *p,
+ long num,
+ unsigned radix,
+ long divisor) {
int i;
char *q;
+ long l, ll;
+
+ l = num;
+ if (divisor == 0) {
+ ll = num;
+ } else {
+ ll = divisor;
+ }
q = p + MAX_FILLER;
do {
- i = (int)(num % radix);
+ i = (int)(l % radix);
i += '0';
if (i > '9')
i += 'A' - '0' - 10;
*--q = i;
- } while ((num /= radix) != 0);
+ l /= radix;
+ } while ((ll /= radix) != 0);
i = (int)(p + MAX_FILLER - q);
do
@@ -45,6 +62,24 @@ static char *ltoa(char *p, long num, unsigned radix) { return p;
}
+static char *ltoa(char *p, long num, unsigned radix) {
+
+ return long_to_string_with_divisor(p, num, radix, 0);
+}
+
+#if CHPRINTF_USE_FLOAT
+static char *ftoa(char *p, double num) {
+ long l;
+ unsigned long precision = FLOAT_PRECISION;
+
+ l = num;
+ p = long_to_string_with_divisor(p, l, 10, 0);
+ *p++ = '.';
+ l = (num - l) * precision;
+ return long_to_string_with_divisor(p, l, 10, precision / 10);
+}
+#endif
+
/**
* @brief System formatted output function.
* @details This function implements a minimal @p printf() like functionality
@@ -62,8 +97,6 @@ static char *ltoa(char *p, long num, unsigned radix) { * - <b>c</b> character.
* - <b>s</b> string.
* .
- * @note Floating point types are not implemented, this function is meant
- * as a system utility and not a full implementation.
*
* @param[in] chp pointer to a @p BaseChannel implementing object
* @param[in] fmt formatting string
@@ -75,6 +108,9 @@ void chprintf(BaseChannel *chp, const char *fmt, ...) { int i, precision, width;
bool_t is_long, left_align;
long l;
+#if CHPRINTF_USE_FLOAT
+ float f;
+#endif
va_start(ap, fmt);
while (TRUE) {
@@ -160,6 +196,16 @@ void chprintf(BaseChannel *chp, const char *fmt, ...) { }
p = ltoa(p, l, 10);
break;
+#if CHPRINTF_USE_FLOAT
+ case 'f':
+ f = (float) va_arg(ap, double);
+ if (f < 0) {
+ *p++ = '-';
+ f = -f;
+ }
+ p = ftoa(p, f);
+ break;
+#endif
case 'X':
case 'x':
c = 16;
diff --git a/os/various/chprintf.h b/os/various/chprintf.h index 929da639e..866dfa067 100644 --- a/os/various/chprintf.h +++ b/os/various/chprintf.h @@ -29,6 +29,13 @@ #ifndef _CHPRINTF_H_
#define _CHPRINTF_H_
+/**
+ * @brief Float type support.
+ */
+#if !defined(CHPRINTF_USE_FLOAT) || defined(__DOXYGEN__)
+#define CHPRINTF_USE_FLOAT FALSE
+#endif
+
#ifdef __cplusplus
extern "C" {
#endif
diff --git a/os/various/chrtclib.c b/os/various/chrtclib.c index 38f5a3627..38f5a3627 100755..100644 --- a/os/various/chrtclib.c +++ b/os/various/chrtclib.c diff --git a/os/various/chrtclib.h b/os/various/chrtclib.h index 7831be83d..7831be83d 100755..100644 --- a/os/various/chrtclib.h +++ b/os/various/chrtclib.h diff --git a/os/various/diskio.c b/os/various/diskio.c new file mode 100755 index 000000000..07d44db49 --- /dev/null +++ b/os/various/diskio.c @@ -0,0 +1,244 @@ +/*-----------------------------------------------------------------------*/
+/* Low level disk I/O module skeleton for FatFs (C)ChaN, 2007 */
+/*-----------------------------------------------------------------------*/
+/* This is a stub disk I/O module that acts as front end of the existing */
+/* disk I/O modules and attach it to FatFs module with common interface. */
+/*-----------------------------------------------------------------------*/
+
+#include "ch.h"
+#include "hal.h"
+
+#include "diskio.h"
+
+#if HAL_USE_MMC_SPI && HAL_USE_SDC
+#error "cannot specify both MMC_SPI and SDC drivers"
+#endif
+
+#if HAL_USE_MMC_SPI
+extern MMCDriver MMCD1;
+#elif HAL_USE_SDC
+extern SDCDriver SDCD1;
+#else
+#error "MMC_SPI or SDC driver must be specified"
+#endif
+
+#if HAL_USE_RTC
+#include "chrtclib.h"
+extern RTCDriver RTCD1;
+#endif
+
+/*-----------------------------------------------------------------------*/
+/* Correspondence between physical drive number and physical drive. */
+
+#define MMC 0
+#define SDC 0
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Inidialize a Drive */
+
+DSTATUS disk_initialize (
+ BYTE drv /* Physical drive nmuber (0..) */
+)
+{
+ DSTATUS stat;
+
+ switch (drv) {
+#if HAL_USE_MMC_SPI
+ case MMC:
+ stat = 0;
+ /* It is initialized externally, just reads the status.*/
+ if (mmcGetDriverState(&MMCD1) != MMC_READY)
+ stat |= STA_NOINIT;
+ if (mmcIsWriteProtected(&MMCD1))
+ stat |= STA_PROTECT;
+ return stat;
+#else
+ case SDC:
+ stat = 0;
+ /* It is initialized externally, just reads the status.*/
+ if (sdcGetDriverState(&SDCD1) != SDC_ACTIVE)
+ stat |= STA_NOINIT;
+ if (sdcIsWriteProtected(&SDCD1))
+ stat |= STA_PROTECT;
+ return stat;
+#endif
+ }
+ return STA_NODISK;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Return Disk Status */
+
+DSTATUS disk_status (
+ BYTE drv /* Physical drive nmuber (0..) */
+)
+{
+ DSTATUS stat;
+
+ switch (drv) {
+#if HAL_USE_MMC_SPI
+ case MMC:
+ stat = 0;
+ /* It is initialized externally, just reads the status.*/
+ if (mmcGetDriverState(&MMCD1) != MMC_READY)
+ stat |= STA_NOINIT;
+ if (mmcIsWriteProtected(&MMCD1))
+ stat |= STA_PROTECT;
+ return stat;
+#else
+ case SDC:
+ stat = 0;
+ /* It is initialized externally, just reads the status.*/
+ if (sdcGetDriverState(&SDCD1) != SDC_ACTIVE)
+ stat |= STA_NOINIT;
+ if (sdcIsWriteProtected(&SDCD1))
+ stat |= STA_PROTECT;
+ return stat;
+#endif
+ }
+ return STA_NODISK;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Read Sector(s) */
+
+DRESULT disk_read (
+ BYTE drv, /* Physical drive nmuber (0..) */
+ BYTE *buff, /* Data buffer to store read data */
+ DWORD sector, /* Sector address (LBA) */
+ BYTE count /* Number of sectors to read (1..255) */
+)
+{
+ switch (drv) {
+#if HAL_USE_MMC_SPI
+ case MMC:
+ if (mmcGetDriverState(&MMCD1) != MMC_READY)
+ return RES_NOTRDY;
+ if (mmcStartSequentialRead(&MMCD1, sector))
+ return RES_ERROR;
+ while (count > 0) {
+ if (mmcSequentialRead(&MMCD1, buff))
+ return RES_ERROR;
+ buff += MMC_SECTOR_SIZE;
+ count--;
+ }
+ if (mmcStopSequentialRead(&MMCD1))
+ return RES_ERROR;
+ return RES_OK;
+#else
+ case SDC:
+ if (sdcGetDriverState(&SDCD1) != SDC_ACTIVE)
+ return RES_NOTRDY;
+ if (sdcRead(&SDCD1, sector, buff, count))
+ return RES_ERROR;
+ return RES_OK;
+#endif
+ }
+ return RES_PARERR;
+}
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Write Sector(s) */
+
+#if _READONLY == 0
+DRESULT disk_write (
+ BYTE drv, /* Physical drive nmuber (0..) */
+ const BYTE *buff, /* Data to be written */
+ DWORD sector, /* Sector address (LBA) */
+ BYTE count /* Number of sectors to write (1..255) */
+)
+{
+ switch (drv) {
+#if HAL_USE_MMC_SPI
+ case MMC:
+ if (mmcGetDriverState(&MMCD1) != MMC_READY)
+ return RES_NOTRDY;
+ if (mmcIsWriteProtected(&MMCD1))
+ return RES_WRPRT;
+ if (mmcStartSequentialWrite(&MMCD1, sector))
+ return RES_ERROR;
+ while (count > 0) {
+ if (mmcSequentialWrite(&MMCD1, buff))
+ return RES_ERROR;
+ buff += MMC_SECTOR_SIZE;
+ count--;
+ }
+ if (mmcStopSequentialWrite(&MMCD1))
+ return RES_ERROR;
+ return RES_OK;
+#else
+ case SDC:
+ if (sdcGetDriverState(&SDCD1) != SDC_ACTIVE)
+ return RES_NOTRDY;
+ if (sdcWrite(&SDCD1, sector, buff, count))
+ return RES_ERROR;
+ return RES_OK;
+#endif
+ }
+ return RES_PARERR;
+}
+#endif /* _READONLY */
+
+
+
+/*-----------------------------------------------------------------------*/
+/* Miscellaneous Functions */
+
+DRESULT disk_ioctl (
+ BYTE drv, /* Physical drive nmuber (0..) */
+ BYTE ctrl, /* Control code */
+ void *buff /* Buffer to send/receive control data */
+)
+{
+ switch (drv) {
+#if HAL_USE_MMC_SPI
+ case MMC:
+ switch (ctrl) {
+ case CTRL_SYNC:
+ return RES_OK;
+ case GET_SECTOR_SIZE:
+ *((WORD *)buff) = MMC_SECTOR_SIZE;
+ return RES_OK;
+ default:
+ return RES_PARERR;
+ }
+#else
+ case SDC:
+ switch (ctrl) {
+ case CTRL_SYNC:
+ return RES_OK;
+ case GET_SECTOR_COUNT:
+ *((DWORD *)buff) = sdcGetCardCapacity(&SDCD1);
+ return RES_OK;
+ case GET_SECTOR_SIZE:
+ *((WORD *)buff) = SDC_BLOCK_SIZE;
+ return RES_OK;
+ case GET_BLOCK_SIZE:
+ *((DWORD *)buff) = 256; /* 512b blocks in one erase block */
+ return RES_OK;
+ default:
+ return RES_PARERR;
+ }
+#endif
+ }
+ return RES_PARERR;
+}
+
+DWORD get_fattime(void) {
+#if HAL_USE_RTC
+ return rtcGetTimeFat(&RTCD1);
+#else
+ return ((uint32_t)0 | (1 << 16)) | (1 << 21); /* wrong but valid time */
+#endif
+}
+
+
+
diff --git a/os/various/evtimer.h b/os/various/evtimer.h index 7d54d446b..695a3851e 100644 --- a/os/various/evtimer.h +++ b/os/various/evtimer.h @@ -29,6 +29,14 @@ #ifndef _EVTIMER_H_
#define _EVTIMER_H_
+
+/*
+ * Module dependencies check.
+ */
+#if !CH_USE_EVENTS
+#error "Event Timers require CH_USE_EVENTS"
+#endif
+
/**
* @brief Event timer structure.
*/
diff --git a/os/various/mail.c b/os/various/mail.c new file mode 100644 index 000000000..cebd44457 --- /dev/null +++ b/os/various/mail.c @@ -0,0 +1,96 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file mail.c
+ * @brief Threads mail code.
+ *
+ * @addtogroup mail
+ * @{
+ */
+
+#include "ch.h"
+#include "mail.h"
+
+/**
+ * @brief Initializes a Mail Pool.
+ * @note The number of the mail objects in the mail pool should be at
+ * least <b>2+size(mailbox)<b>, this considering one writer and
+ * one reader, add one element for each extra reader or writer in
+ * order to avoid waiting on the mail pool. A smaller number of
+ * elements can be specified if waiting on the pool is acceptable.
+ *
+ * @param[out] mlp pointer to a @p MailPool structure
+ * @param[in] size the size of the mail objects to be placed in the pool
+ * @param[in] p pointer to the mail objects array first element
+ * @param[in] n number of elements in the mail objects array
+ *
+ * @init
+ */
+void mailInit(MailPool *mlp, size_t size, void *p, size_t n) {
+
+ chPoolInit(&mlp->pool, size, NULL);
+ chPoolLoadArray(&mlp->pool, p, n);
+ chSemInit(&mlp->sem, (cnt_t)n);
+}
+
+/**
+ * @brief Allocates a mail object from a mail pool.
+ * @pre The mail pool must be already been initialized.
+ *
+ * @param[in] mlp pointer to a @p MailPool structure
+ * @param[in] time the number of ticks before the operation timeouts,
+ * the following special values are allowed:
+ * - @a TIME_IMMEDIATE immediate timeout.
+ * - @a TIME_INFINITE no timeout.
+ * .
+ * @return The mail object.
+ * @retval NULL timeout expired.
+ *
+ * @api
+ */
+void *mailCreate(MailPool *mlp, systime_t time) {
+ msg_t msg;
+ void *mailp;
+
+ msg = chSemWaitTimeout(&mlp->sem, time);
+ if (msg != RDY_OK)
+ return NULL;
+ mailp = chPoolAlloc(&mlp->pool);
+ chDbgAssert(mailp != NULL, "mailCreate(), #1", "empty pool");
+ return mailp;
+}
+
+/**
+ * @brief Releases a mail object into a mail pool.
+ * @pre The mail pool must be already been initialized.
+ *
+ * @param[in] mlp pointer to a @p MailPool structure
+ * @param[in] mailp the pointer to the mail object to be released
+ *
+ * @api
+ */
+void mailDelete(MailPool *mlp, void *mailp) {
+
+ chPoolFree(&mlp->pool, mailp);
+ chSemSignal(&mlp->sem);
+}
+
+/** @} */
diff --git a/os/various/mail.h b/os/various/mail.h new file mode 100644 index 000000000..1786494e6 --- /dev/null +++ b/os/various/mail.h @@ -0,0 +1,59 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file mail.h
+ * @brief Threads mail macros and structures.
+ *
+ * @addtogroup mail
+ * @{
+ */
+
+#ifndef _MAIL_H_
+#define _MAIL_H_
+
+/*
+ * Module dependencies check.
+ */
+#if !CH_USE_SEMAPHORES || !CH_USE_MEMPOOLS
+#error "Mail Pools require CH_USE_SEMAPHORES and CH_USE_MEMPOOLS"
+#endif
+
+/**
+ * @brief Mail Pool descriptor.
+ */
+typedef struct {
+ MemoryPool pool; /**< @brief Available mail objects. */
+ Semaphore sem; /**< @brief Semaphore guard. */
+} MailPool;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void mailInit(MailPool *mlp, size_t size, void *p, size_t n);
+ void *mailCreate(MailPool *mlp, systime_t time);
+ void mailDelete(MailPool *mlp, void *mailp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _MAIL_H_ */
+
+/** @} */
diff --git a/readme.txt b/readme.txt index 4258925ad..28a3bd26d 100644 --- a/readme.txt +++ b/readme.txt @@ -79,6 +79,19 @@ *****************************************************************************
*** 2.5.0 ***
+- FIX: Fixed missing serial driver functionality for SAM7S64, SAM7S128 and
+ SAM7S512 (bug 3517648)(backported to 2.2.10 and 2.4.1).
+- FIX: Fixed spurious ) char in STM32 serial_lld.h (bug 3514138)(backported
+ to 2.2.10 and 2.4.1).
+- FIX: Fixed problem with FPU initialization in GCC Cortex-M4 port (bug
+ 3513897)(backported to 2.4.1).
+- FIX: Spelling fixes (bug 3510812)(backported to 2.4.1).
+- FIX: Fixed STM32 ICUD8 not functional because wrong initialization (bug
+ 3508758)(backported to 2.4.1).
+- FIX: Fixed chMBFetchI does not decrement mb_fullsem (bug 3504450)(backported
+ to 2.2.9 and 2.4.1).
+- FIX: Fixed USART3 not working on STM32F2/F4 UART driver (bug 3496981)
+ (backported to 2.4.1).
- FIX: Fixed stack misalignment on Posix-MacOSX (bug 3495487)(backported
to 2.4.1).
- FIX: Fixed STM8S HSI clock initialization error (bug 3489727)(backported to
@@ -95,6 +108,16 @@ 3484947)(backported to 2.4.1).
- FIX: Fixed various minor documentation errors (bug 3484942)(backported
to 2.4.1).
+- NEW: Added support for pools of generic "mail" objects under ./os/various,
+ mail objects are meant to be used together with mailboxes.
+- NEW: Added a new function chPoolLoadArray() to the Memory Pools subsystem,
+ it allows to load an entire array element's into a pool with a single
+ operation.
+- NEW: Addes support for .S patch in the GCC ARM ports, by Ayman El-Khashab.
+- NEW: Added a switch to the STM32F4 Makefile files in order to enable or
+ disable the FPU support in a single place.
+- NEW: Added float support (optional) to chprintf(), by Fabio Utzig.
+- NEW: Added overflow handling in the ICU driver (contributed by Xo).
- NEW: Updated debug plugin 1.0.8 (backported to 2.4.0).
- NEW: Added more accurate UBRR calculation in AVR serial driver (backported
to 2.4.0).
@@ -108,11 +131,16 @@ Johnny Halfmoon).
- NEW: Added handling of input 2 to the STM32 ICU driver (contributed by
Fabio).
-- NEW: STM32 Ethernet driver completed, only partially tested on STM32F107.
- Added an STM32 lwIP demo.
+- NEW: STM32 Ethernet driver completed. Added STM32F107 and STM32F407
+ lwIP demos.
- NEW: lwIP related code is not centralized into a single place, no need to
duplicate the code in each application or demo.
-- CHANGE: Macros icuGetWidthI() and icuGetPeriodI() renemed to icuGetWidth()
+- CHANGE: The PORT_INT_REQUIRED_STACK parameter for the Cortex-Mx ports has
+ been increased to 32 from 16 because the stack frame sizes are increased
+ when compiling with optimizations disabled, which is common during
+ debugging. In order to save RAM trim back this value when compilung with
+ optimizations enabled.
+- CHANGE: Macros icuGetWidthI() and icuGetPeriodI() renamed to icuGetWidth()
and icuGetPeriod().
- CHANGE: Renamed Ethernet driver in AT91 HAL ETHD1.
diff --git a/test/coverage/chconf.h b/test/coverage/chconf.h index d514e822d..9db485f52 100644 --- a/test/coverage/chconf.h +++ b/test/coverage/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/test/coverage/halconf.h b/test/coverage/halconf.h index 5b49950cd..991f7cd1b 100644 --- a/test/coverage/halconf.h +++ b/test/coverage/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/test/testmbox.c b/test/testmbox.c index 5271752d2..9c0bc08fa 100644 --- a/test/testmbox.c +++ b/test/testmbox.c @@ -180,30 +180,34 @@ static void mbox1_execute(void) { test_emit_token(msg2);
}
test_assert_sequence(29, "ABCDE");
- test_assert(30, mb1.mb_rdptr == mb1.mb_wrptr, "pointers not aligned");
+ test_assert_lock(30, chMBGetFreeCountI(&mb1) == MB_SIZE, "not empty");
+ test_assert_lock(31, chMBGetUsedCountI(&mb1) == 0, "still full");
+ test_assert(32, mb1.mb_rdptr == mb1.mb_wrptr, "pointers not aligned");
chSysLock();
msg1 = chMBPostAheadI(&mb1, 'E');
- test_assert(31, msg1 == RDY_OK, "wrong wake-up message");
+ test_assert(33, msg1 == RDY_OK, "wrong wake-up message");
msg1 = chMBPostAheadI(&mb1, 'D');
- test_assert(32, msg1 == RDY_OK, "wrong wake-up message");
+ test_assert(34, msg1 == RDY_OK, "wrong wake-up message");
msg1 = chMBPostAheadI(&mb1, 'C');
- test_assert(33, msg1 == RDY_OK, "wrong wake-up message");
+ test_assert(35, msg1 == RDY_OK, "wrong wake-up message");
msg1 = chMBPostAheadI(&mb1, 'B');
- test_assert(34, msg1 == RDY_OK, "wrong wake-up message");
+ test_assert(36, msg1 == RDY_OK, "wrong wake-up message");
msg1 = chMBPostAheadI(&mb1, 'A');
chSysUnlock();
- test_assert(35, msg1 == RDY_OK, "wrong wake-up message");
- test_assert(36, mb1.mb_rdptr == mb1.mb_wrptr, "pointers not aligned");
+ test_assert(37, msg1 == RDY_OK, "wrong wake-up message");
+ test_assert(38, mb1.mb_rdptr == mb1.mb_wrptr, "pointers not aligned");
for (i = 0; i < MB_SIZE; i++) {
chSysLock();
msg1 = chMBFetchI(&mb1, &msg2);
chSysUnlock();
- test_assert(37, msg1 == RDY_OK, "wrong wake-up message");
+ test_assert(39, msg1 == RDY_OK, "wrong wake-up message");
test_emit_token(msg2);
}
- test_assert_sequence(38, "ABCDE");
- test_assert(39, mb1.mb_rdptr == mb1.mb_wrptr, "pointers not aligned");
+ test_assert_sequence(40, "ABCDE");
+ test_assert_lock(41, chMBGetFreeCountI(&mb1) == MB_SIZE, "not empty");
+ test_assert_lock(42, chMBGetUsedCountI(&mb1) == 0, "still full");
+ test_assert(43, mb1.mb_rdptr == mb1.mb_wrptr, "pointers not aligned");
/*
* Testing reset.
@@ -213,10 +217,10 @@ static void mbox1_execute(void) { /*
* Re-testing final conditions.
*/
- test_assert_lock(40, chMBGetFreeCountI(&mb1) == MB_SIZE, "not empty");
- test_assert_lock(41, chMBGetUsedCountI(&mb1) == 0, "still full");
- test_assert_lock(42, mb1.mb_buffer == mb1.mb_wrptr, "write pointer not aligned to base");
- test_assert_lock(43, mb1.mb_buffer == mb1.mb_rdptr, "read pointer not aligned to base");
+ test_assert_lock(44, chMBGetFreeCountI(&mb1) == MB_SIZE, "not empty");
+ test_assert_lock(45, chMBGetUsedCountI(&mb1) == 0, "still full");
+ test_assert_lock(46, mb1.mb_buffer == mb1.mb_wrptr, "write pointer not aligned to base");
+ test_assert_lock(47, mb1.mb_buffer == mb1.mb_rdptr, "read pointer not aligned to base");
}
ROMCONST struct testcase testmbox1 = {
diff --git a/test/testpools.c b/test/testpools.c index 1c864d973..2583170fd 100644 --- a/test/testpools.c +++ b/test/testpools.c @@ -75,20 +75,30 @@ static void pools1_setup(void) { static void pools1_execute(void) {
int i;
- /* Adding the WAs to the pool. */
- for (i = 0; i < MAX_THREADS; i++)
- chPoolFree(&mp1, wa[i]);
+ /* Adding the WAs to the pool.*/
+ chPoolLoadArray(&mp1, wa[0], MAX_THREADS);
- /* Empting the pool again. */
+ /* Emptying the pool.*/
for (i = 0; i < MAX_THREADS; i++)
test_assert(1, chPoolAlloc(&mp1) != NULL, "list empty");
- /* Now must be empty. */
+ /* Now must be empty.*/
test_assert(2, chPoolAlloc(&mp1) == NULL, "list not empty");
+ /* Adding the WAs to the pool, one by one this time.*/
+ for (i = 0; i < MAX_THREADS; i++)
+ chPoolFree(&mp1, wa[i]);
+
+ /* Emptying the pool again.*/
+ for (i = 0; i < MAX_THREADS; i++)
+ test_assert(3, chPoolAlloc(&mp1) != NULL, "list empty");
+
+ /* Now must be empty again.*/
+ test_assert(4, chPoolAlloc(&mp1) == NULL, "list not empty");
+
/* Covering the case where a provider is unable to return more memory.*/
chPoolInit(&mp1, 16, null_provider);
- test_assert(3, chPoolAlloc(&mp1) == NULL, "provider returned memory");
+ test_assert(5, chPoolAlloc(&mp1) == NULL, "provider returned memory");
}
ROMCONST struct testcase testpools1 = {
diff --git a/testhal/LPC11xx/IRQ_STORM/chconf.h b/testhal/LPC11xx/IRQ_STORM/chconf.h index 4115636d6..b1f2cd62c 100644 --- a/testhal/LPC11xx/IRQ_STORM/chconf.h +++ b/testhal/LPC11xx/IRQ_STORM/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/LPC11xx/IRQ_STORM/halconf.h b/testhal/LPC11xx/IRQ_STORM/halconf.h index eb013c9a7..c9b3ad25a 100644 --- a/testhal/LPC11xx/IRQ_STORM/halconf.h +++ b/testhal/LPC11xx/IRQ_STORM/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/LPC13xx/IRQ_STORM/chconf.h b/testhal/LPC13xx/IRQ_STORM/chconf.h index 4115636d6..b1f2cd62c 100644 --- a/testhal/LPC13xx/IRQ_STORM/chconf.h +++ b/testhal/LPC13xx/IRQ_STORM/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/LPC13xx/IRQ_STORM/halconf.h b/testhal/LPC13xx/IRQ_STORM/halconf.h index 73bd593e1..08b919c73 100644 --- a/testhal/LPC13xx/IRQ_STORM/halconf.h +++ b/testhal/LPC13xx/IRQ_STORM/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/STM32F1xx/ADC/chconf.h b/testhal/STM32F1xx/ADC/chconf.h index c0181fef5..290044421 100644 --- a/testhal/STM32F1xx/ADC/chconf.h +++ b/testhal/STM32F1xx/ADC/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM32F1xx/ADC/halconf.h b/testhal/STM32F1xx/ADC/halconf.h index 2c6d2beaf..545241783 100644 --- a/testhal/STM32F1xx/ADC/halconf.h +++ b/testhal/STM32F1xx/ADC/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/STM32F1xx/CAN/chconf.h b/testhal/STM32F1xx/CAN/chconf.h index 4115636d6..b1f2cd62c 100644 --- a/testhal/STM32F1xx/CAN/chconf.h +++ b/testhal/STM32F1xx/CAN/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM32F1xx/CAN/halconf.h b/testhal/STM32F1xx/CAN/halconf.h index 3479e2851..52296c173 100644 --- a/testhal/STM32F1xx/CAN/halconf.h +++ b/testhal/STM32F1xx/CAN/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/STM32F1xx/EXT/chconf.h b/testhal/STM32F1xx/EXT/chconf.h index c0181fef5..290044421 100644 --- a/testhal/STM32F1xx/EXT/chconf.h +++ b/testhal/STM32F1xx/EXT/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM32F1xx/EXT/halconf.h b/testhal/STM32F1xx/EXT/halconf.h index f583f94e6..5a1e5c050 100644 --- a/testhal/STM32F1xx/EXT/halconf.h +++ b/testhal/STM32F1xx/EXT/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/STM32F1xx/EXT_WAKEUP/chconf.h b/testhal/STM32F1xx/EXT_WAKEUP/chconf.h index c0181fef5..290044421 100644 --- a/testhal/STM32F1xx/EXT_WAKEUP/chconf.h +++ b/testhal/STM32F1xx/EXT_WAKEUP/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM32F1xx/EXT_WAKEUP/halconf.h b/testhal/STM32F1xx/EXT_WAKEUP/halconf.h index ed48056c7..e2ac49536 100644 --- a/testhal/STM32F1xx/EXT_WAKEUP/halconf.h +++ b/testhal/STM32F1xx/EXT_WAKEUP/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/STM32F1xx/GPT/chconf.h b/testhal/STM32F1xx/GPT/chconf.h index 4115636d6..b1f2cd62c 100644 --- a/testhal/STM32F1xx/GPT/chconf.h +++ b/testhal/STM32F1xx/GPT/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM32F1xx/GPT/halconf.h b/testhal/STM32F1xx/GPT/halconf.h index 1b9896157..ad048e08f 100644 --- a/testhal/STM32F1xx/GPT/halconf.h +++ b/testhal/STM32F1xx/GPT/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/STM32F1xx/GPT/main.c b/testhal/STM32F1xx/GPT/main.c index 5a72b4e16..0fa26564f 100644 --- a/testhal/STM32F1xx/GPT/main.c +++ b/testhal/STM32F1xx/GPT/main.c @@ -46,7 +46,7 @@ static void gpt2cb(GPTDriver *gptp) { * GPT1 configuration.
*/
static const GPTConfig gpt1cfg = {
- 10000, /* 10KHz timer clock.*/
+ 10000, /* 10kHz timer clock.*/
gpt1cb /* Timer callback.*/
};
@@ -54,7 +54,7 @@ static const GPTConfig gpt1cfg = { * GPT2 configuration.
*/
static const GPTConfig gpt2cfg = {
- 10000, /* 10KHz timer clock.*/
+ 10000, /* 10kHz timer clock.*/
gpt2cb /* Timer callback.*/
};
diff --git a/testhal/STM32F1xx/I2C/chconf.h b/testhal/STM32F1xx/I2C/chconf.h index 8a03a42fd..c860ec4a2 100644 --- a/testhal/STM32F1xx/I2C/chconf.h +++ b/testhal/STM32F1xx/I2C/chconf.h @@ -435,7 +435,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM32F1xx/I2C/halconf.h b/testhal/STM32F1xx/I2C/halconf.h index 3ed2554e4..3837caff1 100644 --- a/testhal/STM32F1xx/I2C/halconf.h +++ b/testhal/STM32F1xx/I2C/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/STM32F1xx/IRQ_STORM/chconf.h b/testhal/STM32F1xx/IRQ_STORM/chconf.h index 4115636d6..b1f2cd62c 100644 --- a/testhal/STM32F1xx/IRQ_STORM/chconf.h +++ b/testhal/STM32F1xx/IRQ_STORM/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM32F1xx/IRQ_STORM/halconf.h b/testhal/STM32F1xx/IRQ_STORM/halconf.h index 1ad8f74ce..4e5a16796 100644 --- a/testhal/STM32F1xx/IRQ_STORM/halconf.h +++ b/testhal/STM32F1xx/IRQ_STORM/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/STM32F1xx/MAC/chconf.h b/testhal/STM32F1xx/MAC/chconf.h index c0181fef5..290044421 100644 --- a/testhal/STM32F1xx/MAC/chconf.h +++ b/testhal/STM32F1xx/MAC/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM32F1xx/MAC/halconf.h b/testhal/STM32F1xx/MAC/halconf.h index 8b8cec346..8964b02df 100644 --- a/testhal/STM32F1xx/MAC/halconf.h +++ b/testhal/STM32F1xx/MAC/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/STM32F1xx/PVD/chconf.h b/testhal/STM32F1xx/PVD/chconf.h index c0181fef5..290044421 100644 --- a/testhal/STM32F1xx/PVD/chconf.h +++ b/testhal/STM32F1xx/PVD/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM32F1xx/PVD/halconf.h b/testhal/STM32F1xx/PVD/halconf.h index f583f94e6..5a1e5c050 100644 --- a/testhal/STM32F1xx/PVD/halconf.h +++ b/testhal/STM32F1xx/PVD/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/STM32F1xx/PWM-ICU/chconf.h b/testhal/STM32F1xx/PWM-ICU/chconf.h index 4115636d6..b1f2cd62c 100644 --- a/testhal/STM32F1xx/PWM-ICU/chconf.h +++ b/testhal/STM32F1xx/PWM-ICU/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM32F1xx/PWM-ICU/halconf.h b/testhal/STM32F1xx/PWM-ICU/halconf.h index 539b810db..9e7b5b6fe 100644 --- a/testhal/STM32F1xx/PWM-ICU/halconf.h +++ b/testhal/STM32F1xx/PWM-ICU/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/STM32F1xx/PWM-ICU/main.c b/testhal/STM32F1xx/PWM-ICU/main.c index ab9cd8be2..fd8fb581f 100644 --- a/testhal/STM32F1xx/PWM-ICU/main.c +++ b/testhal/STM32F1xx/PWM-ICU/main.c @@ -34,7 +34,7 @@ static void pwmc1cb(PWMDriver *pwmp) { }
static PWMConfig pwmcfg = {
- 10000, /* 10KHz PWM clock frequency. */
+ 10000, /* 10kHz PWM clock frequency. */
10000, /* Initial PWM period 1S. */
pwmpcb,
{
@@ -63,9 +63,10 @@ static void icuperiodcb(ICUDriver *icup) { static ICUConfig icucfg = {
ICU_INPUT_ACTIVE_HIGH,
- 10000, /* 10KHz ICU clock frequency. */
+ 10000, /* 10kHz ICU clock frequency. */
icuwidthcb,
icuperiodcb,
+ NULL,
ICU_CHANNEL_1
};
diff --git a/testhal/STM32F1xx/RTC/chconf.h b/testhal/STM32F1xx/RTC/chconf.h index 8a03a42fd..c860ec4a2 100644 --- a/testhal/STM32F1xx/RTC/chconf.h +++ b/testhal/STM32F1xx/RTC/chconf.h @@ -435,7 +435,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM32F1xx/RTC/halconf.h b/testhal/STM32F1xx/RTC/halconf.h index b9bf9a63d..bf07df92b 100644 --- a/testhal/STM32F1xx/RTC/halconf.h +++ b/testhal/STM32F1xx/RTC/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/STM32F1xx/SDC/chconf.h b/testhal/STM32F1xx/SDC/chconf.h index c0181fef5..290044421 100644 --- a/testhal/STM32F1xx/SDC/chconf.h +++ b/testhal/STM32F1xx/SDC/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM32F1xx/SDC/halconf.h b/testhal/STM32F1xx/SDC/halconf.h index 5818fbe72..63e37a04e 100644 --- a/testhal/STM32F1xx/SDC/halconf.h +++ b/testhal/STM32F1xx/SDC/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/STM32F1xx/SPI/chconf.h b/testhal/STM32F1xx/SPI/chconf.h index c0181fef5..290044421 100644 --- a/testhal/STM32F1xx/SPI/chconf.h +++ b/testhal/STM32F1xx/SPI/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM32F1xx/SPI/halconf.h b/testhal/STM32F1xx/SPI/halconf.h index 84a220f12..d176ad1a7 100644 --- a/testhal/STM32F1xx/SPI/halconf.h +++ b/testhal/STM32F1xx/SPI/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/STM32F1xx/SPI/main.c b/testhal/STM32F1xx/SPI/main.c index 5aec3a965..be129980a 100644 --- a/testhal/STM32F1xx/SPI/main.c +++ b/testhal/STM32F1xx/SPI/main.c @@ -32,7 +32,7 @@ static const SPIConfig hs_spicfg = { };
/*
- * Low speed SPI configuration (281.250KHz, CPHA=0, CPOL=0, MSb first).
+ * Low speed SPI configuration (281.250kHz, CPHA=0, CPOL=0, MSb first).
*/
static const SPIConfig ls_spicfg = {
NULL,
diff --git a/testhal/STM32F1xx/UART/chconf.h b/testhal/STM32F1xx/UART/chconf.h index c0181fef5..290044421 100644 --- a/testhal/STM32F1xx/UART/chconf.h +++ b/testhal/STM32F1xx/UART/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM32F1xx/UART/halconf.h b/testhal/STM32F1xx/UART/halconf.h index 5f667087c..60af9dec0 100644 --- a/testhal/STM32F1xx/UART/halconf.h +++ b/testhal/STM32F1xx/UART/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/STM32F1xx/USB_CDC/chconf.h b/testhal/STM32F1xx/USB_CDC/chconf.h index c0181fef5..290044421 100644 --- a/testhal/STM32F1xx/USB_CDC/chconf.h +++ b/testhal/STM32F1xx/USB_CDC/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM32F1xx/USB_CDC/halconf.h b/testhal/STM32F1xx/USB_CDC/halconf.h index ff1b5a6cd..7d1f492f8 100644 --- a/testhal/STM32F1xx/USB_CDC/halconf.h +++ b/testhal/STM32F1xx/USB_CDC/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/STM32F1xx/USB_MSC/chconf.h b/testhal/STM32F1xx/USB_MSC/chconf.h index 4115636d6..b1f2cd62c 100644 --- a/testhal/STM32F1xx/USB_MSC/chconf.h +++ b/testhal/STM32F1xx/USB_MSC/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM32F1xx/USB_MSC/halconf.h b/testhal/STM32F1xx/USB_MSC/halconf.h index f9456f6b0..9669ff278 100644 --- a/testhal/STM32F1xx/USB_MSC/halconf.h +++ b/testhal/STM32F1xx/USB_MSC/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/STM32F4xx/ADC/Makefile b/testhal/STM32F4xx/ADC/Makefile index de1ac051f..86de6d81c 100644 --- a/testhal/STM32F4xx/ADC/Makefile +++ b/testhal/STM32F4xx/ADC/Makefile @@ -5,7 +5,7 @@ # Compiler options here.
ifeq ($(USE_OPT),)
- USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 -mhard-float -mfpu=fpv4-sp-d16 -fsingle-precision-constant
+ USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
endif
# C specific options here (added to USE_OPT).
@@ -41,6 +41,12 @@ endif # Architecture or project specific options
#
+# Enables the use of FPU on Cortex-M4.
+# Enable this if you really want to use the STM FWLib.
+ifeq ($(USE_FPU),)
+ USE_FPU = no
+endif
+
# Enable this if you really want to use the STM FWLib.
ifeq ($(USE_FWLIB),)
USE_FWLIB = no
@@ -64,10 +70,11 @@ include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk
include $(CHIBIOS)/os/kernel/kernel.mk
-#include $(CHIBIOS)/test/test.mk
+include $(CHIBIOS)/test/test.mk
# Define linker script file here
LDSCRIPT= $(PORTLD)/STM32F407xG.ld
+#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
@@ -77,6 +84,7 @@ CSRC = $(PORTSRC) \ $(HALSRC) \
$(PLATFORMSRC) \
$(BOARDSRC) \
+ $(CHIBIOS)/os/various/chprintf.c \
main.c
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
@@ -197,6 +205,13 @@ ULIBS = # End of user defines
##############################################################################
+ifeq ($(USE_FPU),yes)
+ USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant
+ DDEFS += -DCORTEX_USE_FPU=TRUE
+else
+ DDEFS += -DCORTEX_USE_FPU=FALSE
+endif
+
ifeq ($(USE_FWLIB),yes)
include $(CHIBIOS)/ext/stm32lib/stm32lib.mk
CSRC += $(STM32SRC)
diff --git a/testhal/STM32F4xx/ADC/chconf.h b/testhal/STM32F4xx/ADC/chconf.h index c0181fef5..290044421 100644 --- a/testhal/STM32F4xx/ADC/chconf.h +++ b/testhal/STM32F4xx/ADC/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM32F4xx/ADC/halconf.h b/testhal/STM32F4xx/ADC/halconf.h index 2c6d2beaf..545241783 100644 --- a/testhal/STM32F4xx/ADC/halconf.h +++ b/testhal/STM32F4xx/ADC/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/STM32F4xx/DMA_STORM/Makefile b/testhal/STM32F4xx/DMA_STORM/Makefile index 425e5f6c5..86de6d81c 100644 --- a/testhal/STM32F4xx/DMA_STORM/Makefile +++ b/testhal/STM32F4xx/DMA_STORM/Makefile @@ -5,7 +5,7 @@ # Compiler options here.
ifeq ($(USE_OPT),)
- USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 -mhard-float -mfpu=fpv4-sp-d16 -fsingle-precision-constant
+ USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
endif
# C specific options here (added to USE_OPT).
@@ -41,6 +41,12 @@ endif # Architecture or project specific options
#
+# Enables the use of FPU on Cortex-M4.
+# Enable this if you really want to use the STM FWLib.
+ifeq ($(USE_FPU),)
+ USE_FPU = no
+endif
+
# Enable this if you really want to use the STM FWLib.
ifeq ($(USE_FWLIB),)
USE_FWLIB = no
@@ -64,10 +70,11 @@ include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk
include $(CHIBIOS)/os/kernel/kernel.mk
-#include $(CHIBIOS)/test/test.mk
+include $(CHIBIOS)/test/test.mk
# Define linker script file here
LDSCRIPT= $(PORTLD)/STM32F407xG.ld
+#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
@@ -77,8 +84,7 @@ CSRC = $(PORTSRC) \ $(HALSRC) \
$(PLATFORMSRC) \
$(BOARDSRC) \
- $(CHIBIOS)/os/various/evtimer.c \
- $(CHIBIOS)/os/various/syscalls.c \
+ $(CHIBIOS)/os/various/chprintf.c \
main.c
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
@@ -199,6 +205,13 @@ ULIBS = # End of user defines
##############################################################################
+ifeq ($(USE_FPU),yes)
+ USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant
+ DDEFS += -DCORTEX_USE_FPU=TRUE
+else
+ DDEFS += -DCORTEX_USE_FPU=FALSE
+endif
+
ifeq ($(USE_FWLIB),yes)
include $(CHIBIOS)/ext/stm32lib/stm32lib.mk
CSRC += $(STM32SRC)
diff --git a/testhal/STM32F4xx/DMA_STORM/chconf.h b/testhal/STM32F4xx/DMA_STORM/chconf.h index c0181fef5..290044421 100644 --- a/testhal/STM32F4xx/DMA_STORM/chconf.h +++ b/testhal/STM32F4xx/DMA_STORM/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM32F4xx/DMA_STORM/halconf.h b/testhal/STM32F4xx/DMA_STORM/halconf.h index bf08af58a..1d37e3c14 100644 --- a/testhal/STM32F4xx/DMA_STORM/halconf.h +++ b/testhal/STM32F4xx/DMA_STORM/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/STM32F4xx/EXT/Makefile b/testhal/STM32F4xx/EXT/Makefile index de1ac051f..86de6d81c 100644 --- a/testhal/STM32F4xx/EXT/Makefile +++ b/testhal/STM32F4xx/EXT/Makefile @@ -5,7 +5,7 @@ # Compiler options here.
ifeq ($(USE_OPT),)
- USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 -mhard-float -mfpu=fpv4-sp-d16 -fsingle-precision-constant
+ USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
endif
# C specific options here (added to USE_OPT).
@@ -41,6 +41,12 @@ endif # Architecture or project specific options
#
+# Enables the use of FPU on Cortex-M4.
+# Enable this if you really want to use the STM FWLib.
+ifeq ($(USE_FPU),)
+ USE_FPU = no
+endif
+
# Enable this if you really want to use the STM FWLib.
ifeq ($(USE_FWLIB),)
USE_FWLIB = no
@@ -64,10 +70,11 @@ include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk
include $(CHIBIOS)/os/kernel/kernel.mk
-#include $(CHIBIOS)/test/test.mk
+include $(CHIBIOS)/test/test.mk
# Define linker script file here
LDSCRIPT= $(PORTLD)/STM32F407xG.ld
+#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
@@ -77,6 +84,7 @@ CSRC = $(PORTSRC) \ $(HALSRC) \
$(PLATFORMSRC) \
$(BOARDSRC) \
+ $(CHIBIOS)/os/various/chprintf.c \
main.c
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
@@ -197,6 +205,13 @@ ULIBS = # End of user defines
##############################################################################
+ifeq ($(USE_FPU),yes)
+ USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant
+ DDEFS += -DCORTEX_USE_FPU=TRUE
+else
+ DDEFS += -DCORTEX_USE_FPU=FALSE
+endif
+
ifeq ($(USE_FWLIB),yes)
include $(CHIBIOS)/ext/stm32lib/stm32lib.mk
CSRC += $(STM32SRC)
diff --git a/testhal/STM32F4xx/EXT/chconf.h b/testhal/STM32F4xx/EXT/chconf.h index c0181fef5..290044421 100644 --- a/testhal/STM32F4xx/EXT/chconf.h +++ b/testhal/STM32F4xx/EXT/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM32F4xx/EXT/halconf.h b/testhal/STM32F4xx/EXT/halconf.h index f583f94e6..5a1e5c050 100644 --- a/testhal/STM32F4xx/EXT/halconf.h +++ b/testhal/STM32F4xx/EXT/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/STM32F4xx/GPT/Makefile b/testhal/STM32F4xx/GPT/Makefile index de1ac051f..86de6d81c 100644 --- a/testhal/STM32F4xx/GPT/Makefile +++ b/testhal/STM32F4xx/GPT/Makefile @@ -5,7 +5,7 @@ # Compiler options here.
ifeq ($(USE_OPT),)
- USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 -mhard-float -mfpu=fpv4-sp-d16 -fsingle-precision-constant
+ USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
endif
# C specific options here (added to USE_OPT).
@@ -41,6 +41,12 @@ endif # Architecture or project specific options
#
+# Enables the use of FPU on Cortex-M4.
+# Enable this if you really want to use the STM FWLib.
+ifeq ($(USE_FPU),)
+ USE_FPU = no
+endif
+
# Enable this if you really want to use the STM FWLib.
ifeq ($(USE_FWLIB),)
USE_FWLIB = no
@@ -64,10 +70,11 @@ include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk
include $(CHIBIOS)/os/kernel/kernel.mk
-#include $(CHIBIOS)/test/test.mk
+include $(CHIBIOS)/test/test.mk
# Define linker script file here
LDSCRIPT= $(PORTLD)/STM32F407xG.ld
+#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
@@ -77,6 +84,7 @@ CSRC = $(PORTSRC) \ $(HALSRC) \
$(PLATFORMSRC) \
$(BOARDSRC) \
+ $(CHIBIOS)/os/various/chprintf.c \
main.c
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
@@ -197,6 +205,13 @@ ULIBS = # End of user defines
##############################################################################
+ifeq ($(USE_FPU),yes)
+ USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant
+ DDEFS += -DCORTEX_USE_FPU=TRUE
+else
+ DDEFS += -DCORTEX_USE_FPU=FALSE
+endif
+
ifeq ($(USE_FWLIB),yes)
include $(CHIBIOS)/ext/stm32lib/stm32lib.mk
CSRC += $(STM32SRC)
diff --git a/testhal/STM32F4xx/GPT/chconf.h b/testhal/STM32F4xx/GPT/chconf.h index c0181fef5..290044421 100644 --- a/testhal/STM32F4xx/GPT/chconf.h +++ b/testhal/STM32F4xx/GPT/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM32F4xx/GPT/halconf.h b/testhal/STM32F4xx/GPT/halconf.h index 1b9896157..ad048e08f 100644 --- a/testhal/STM32F4xx/GPT/halconf.h +++ b/testhal/STM32F4xx/GPT/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/STM32F4xx/GPT/main.c b/testhal/STM32F4xx/GPT/main.c index 82342a6ef..e751d0a4f 100644 --- a/testhal/STM32F4xx/GPT/main.c +++ b/testhal/STM32F4xx/GPT/main.c @@ -46,7 +46,7 @@ static void gpt3cb(GPTDriver *gptp) { * GPT2 configuration.
*/
static const GPTConfig gpt2cfg = {
- 10000, /* 10KHz timer clock.*/
+ 10000, /* 10kHz timer clock.*/
gpt2cb /* Timer callback.*/
};
@@ -54,7 +54,7 @@ static const GPTConfig gpt2cfg = { * GPT3 configuration.
*/
static const GPTConfig gpt3cfg = {
- 10000, /* 10KHz timer clock.*/
+ 10000, /* 10kHz timer clock.*/
gpt3cb /* Timer callback.*/
};
diff --git a/testhal/STM32F4xx/I2C/Makefile b/testhal/STM32F4xx/I2C/Makefile index 2fbf2d17e..d52f5d4e8 100644 --- a/testhal/STM32F4xx/I2C/Makefile +++ b/testhal/STM32F4xx/I2C/Makefile @@ -5,7 +5,7 @@ # Compiler options here.
ifeq ($(USE_OPT),)
- USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 -mhard-float -mfpu=fpv4-sp-d16 -fsingle-precision-constant
+ USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
endif
# C specific options here (added to USE_OPT).
@@ -41,6 +41,12 @@ endif # Architecture or project specific options
#
+# Enables the use of FPU on Cortex-M4.
+# Enable this if you really want to use the STM FWLib.
+ifeq ($(USE_FPU),)
+ USE_FPU = no
+endif
+
# Enable this if you really want to use the STM FWLib.
ifeq ($(USE_FWLIB),)
USE_FWLIB = no
@@ -64,10 +70,11 @@ include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk
include $(CHIBIOS)/os/kernel/kernel.mk
-#include $(CHIBIOS)/test/test.mk
+include $(CHIBIOS)/test/test.mk
# Define linker script file here
LDSCRIPT= $(PORTLD)/STM32F407xG.ld
+#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
@@ -77,6 +84,7 @@ CSRC = $(PORTSRC) \ $(HALSRC) \
$(PLATFORMSRC) \
$(BOARDSRC) \
+ $(CHIBIOS)/os/various/chprintf.c \
main.c
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
@@ -197,6 +205,13 @@ ULIBS = # End of user defines
##############################################################################
+ifeq ($(USE_FPU),yes)
+ USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant
+ DDEFS += -DCORTEX_USE_FPU=TRUE
+else
+ DDEFS += -DCORTEX_USE_FPU=FALSE
+endif
+
ifeq ($(USE_FWLIB),yes)
include $(CHIBIOS)/ext/stm32lib/stm32lib.mk
CSRC += $(STM32SRC)
diff --git a/testhal/STM32F4xx/I2C/chconf.h b/testhal/STM32F4xx/I2C/chconf.h index 7044bba0e..d99c26773 100644 --- a/testhal/STM32F4xx/I2C/chconf.h +++ b/testhal/STM32F4xx/I2C/chconf.h @@ -439,7 +439,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM32F4xx/I2C/halconf.h b/testhal/STM32F4xx/I2C/halconf.h index ed48056c7..e2ac49536 100644 --- a/testhal/STM32F4xx/I2C/halconf.h +++ b/testhal/STM32F4xx/I2C/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/STM32F4xx/IRQ_STORM/Makefile b/testhal/STM32F4xx/IRQ_STORM/Makefile index de1ac051f..86de6d81c 100644 --- a/testhal/STM32F4xx/IRQ_STORM/Makefile +++ b/testhal/STM32F4xx/IRQ_STORM/Makefile @@ -5,7 +5,7 @@ # Compiler options here.
ifeq ($(USE_OPT),)
- USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 -mhard-float -mfpu=fpv4-sp-d16 -fsingle-precision-constant
+ USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
endif
# C specific options here (added to USE_OPT).
@@ -41,6 +41,12 @@ endif # Architecture or project specific options
#
+# Enables the use of FPU on Cortex-M4.
+# Enable this if you really want to use the STM FWLib.
+ifeq ($(USE_FPU),)
+ USE_FPU = no
+endif
+
# Enable this if you really want to use the STM FWLib.
ifeq ($(USE_FWLIB),)
USE_FWLIB = no
@@ -64,10 +70,11 @@ include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk
include $(CHIBIOS)/os/kernel/kernel.mk
-#include $(CHIBIOS)/test/test.mk
+include $(CHIBIOS)/test/test.mk
# Define linker script file here
LDSCRIPT= $(PORTLD)/STM32F407xG.ld
+#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
@@ -77,6 +84,7 @@ CSRC = $(PORTSRC) \ $(HALSRC) \
$(PLATFORMSRC) \
$(BOARDSRC) \
+ $(CHIBIOS)/os/various/chprintf.c \
main.c
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
@@ -197,6 +205,13 @@ ULIBS = # End of user defines
##############################################################################
+ifeq ($(USE_FPU),yes)
+ USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant
+ DDEFS += -DCORTEX_USE_FPU=TRUE
+else
+ DDEFS += -DCORTEX_USE_FPU=FALSE
+endif
+
ifeq ($(USE_FWLIB),yes)
include $(CHIBIOS)/ext/stm32lib/stm32lib.mk
CSRC += $(STM32SRC)
diff --git a/testhal/STM32F4xx/IRQ_STORM/chconf.h b/testhal/STM32F4xx/IRQ_STORM/chconf.h index 72e15af3b..89d0405b8 100644 --- a/testhal/STM32F4xx/IRQ_STORM/chconf.h +++ b/testhal/STM32F4xx/IRQ_STORM/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM32F4xx/IRQ_STORM/halconf.h b/testhal/STM32F4xx/IRQ_STORM/halconf.h index 1ad8f74ce..4e5a16796 100644 --- a/testhal/STM32F4xx/IRQ_STORM/halconf.h +++ b/testhal/STM32F4xx/IRQ_STORM/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/STM32F4xx/IRQ_STORM_FPU/Makefile b/testhal/STM32F4xx/IRQ_STORM_FPU/Makefile index aa109bff9..8391b78dc 100644 --- a/testhal/STM32F4xx/IRQ_STORM_FPU/Makefile +++ b/testhal/STM32F4xx/IRQ_STORM_FPU/Makefile @@ -5,7 +5,7 @@ # Compiler options here.
ifeq ($(USE_OPT),)
- USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 -mhard-float -mfpu=fpv4-sp-d16 -fsingle-precision-constant
+ USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
endif
# C specific options here (added to USE_OPT).
@@ -41,6 +41,12 @@ endif # Architecture or project specific options
#
+# Enables the use of FPU on Cortex-M4.
+# Enable this if you really want to use the STM FWLib.
+ifeq ($(USE_FPU),)
+ USE_FPU = yes
+endif
+
# Enable this if you really want to use the STM FWLib.
ifeq ($(USE_FWLIB),)
USE_FWLIB = no
@@ -64,10 +70,11 @@ include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk
include $(CHIBIOS)/os/kernel/kernel.mk
-#include $(CHIBIOS)/test/test.mk
+include $(CHIBIOS)/test/test.mk
# Define linker script file here
LDSCRIPT= $(PORTLD)/STM32F407xG.ld
+#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
@@ -77,6 +84,7 @@ CSRC = $(PORTSRC) \ $(HALSRC) \
$(PLATFORMSRC) \
$(BOARDSRC) \
+ $(CHIBIOS)/os/various/chprintf.c \
extfunc.c main.c
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
@@ -197,6 +205,13 @@ ULIBS = # End of user defines
##############################################################################
+ifeq ($(USE_FPU),yes)
+ USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant
+ DDEFS += -DCORTEX_USE_FPU=TRUE
+else
+ DDEFS += -DCORTEX_USE_FPU=FALSE
+endif
+
ifeq ($(USE_FWLIB),yes)
include $(CHIBIOS)/ext/stm32lib/stm32lib.mk
CSRC += $(STM32SRC)
diff --git a/testhal/STM32F4xx/IRQ_STORM_FPU/chconf.h b/testhal/STM32F4xx/IRQ_STORM_FPU/chconf.h index 4115636d6..b1f2cd62c 100644 --- a/testhal/STM32F4xx/IRQ_STORM_FPU/chconf.h +++ b/testhal/STM32F4xx/IRQ_STORM_FPU/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM32F4xx/IRQ_STORM_FPU/halconf.h b/testhal/STM32F4xx/IRQ_STORM_FPU/halconf.h index 1ad8f74ce..4e5a16796 100644 --- a/testhal/STM32F4xx/IRQ_STORM_FPU/halconf.h +++ b/testhal/STM32F4xx/IRQ_STORM_FPU/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/STM32F4xx/PVD/Makefile b/testhal/STM32F4xx/PVD/Makefile index fd78e3d83..86de6d81c 100644 --- a/testhal/STM32F4xx/PVD/Makefile +++ b/testhal/STM32F4xx/PVD/Makefile @@ -5,7 +5,7 @@ # Compiler options here.
ifeq ($(USE_OPT),)
- USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16 -mhard-float -mfpu=fpv4-sp-d16 -fsingle-precision-constant
+ USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
endif
# C specific options here (added to USE_OPT).
@@ -41,6 +41,12 @@ endif # Architecture or project specific options
#
+# Enables the use of FPU on Cortex-M4.
+# Enable this if you really want to use the STM FWLib.
+ifeq ($(USE_FPU),)
+ USE_FPU = no
+endif
+
# Enable this if you really want to use the STM FWLib.
ifeq ($(USE_FWLIB),)
USE_FWLIB = no
@@ -59,14 +65,16 @@ PROJECT = ch # Imported source files and paths
CHIBIOS = ../../..
-include $(CHIBIOS)/boards/NONSTANDARD_STM32F4_BARTHESS1/board.mk
+include $(CHIBIOS)/boards/ST_STM32F4_DISCOVERY/board.mk
include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk
include $(CHIBIOS)/os/kernel/kernel.mk
+include $(CHIBIOS)/test/test.mk
# Define linker script file here
LDSCRIPT= $(PORTLD)/STM32F407xG.ld
+#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
@@ -76,7 +84,8 @@ CSRC = $(PORTSRC) \ $(HALSRC) \
$(PLATFORMSRC) \
$(BOARDSRC) \
- main.c + $(CHIBIOS)/os/various/chprintf.c \
+ main.c
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
@@ -196,6 +205,13 @@ ULIBS = # End of user defines
##############################################################################
+ifeq ($(USE_FPU),yes)
+ USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant
+ DDEFS += -DCORTEX_USE_FPU=TRUE
+else
+ DDEFS += -DCORTEX_USE_FPU=FALSE
+endif
+
ifeq ($(USE_FWLIB),yes)
include $(CHIBIOS)/ext/stm32lib/stm32lib.mk
CSRC += $(STM32SRC)
diff --git a/testhal/STM32F4xx/PVD/chconf.h b/testhal/STM32F4xx/PVD/chconf.h index c0181fef5..290044421 100644 --- a/testhal/STM32F4xx/PVD/chconf.h +++ b/testhal/STM32F4xx/PVD/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM32F4xx/PVD/halconf.h b/testhal/STM32F4xx/PVD/halconf.h index f583f94e6..5a1e5c050 100644 --- a/testhal/STM32F4xx/PVD/halconf.h +++ b/testhal/STM32F4xx/PVD/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/STM32F4xx/PWM-ICU/Makefile b/testhal/STM32F4xx/PWM-ICU/Makefile index de1ac051f..86de6d81c 100644 --- a/testhal/STM32F4xx/PWM-ICU/Makefile +++ b/testhal/STM32F4xx/PWM-ICU/Makefile @@ -5,7 +5,7 @@ # Compiler options here.
ifeq ($(USE_OPT),)
- USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 -mhard-float -mfpu=fpv4-sp-d16 -fsingle-precision-constant
+ USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
endif
# C specific options here (added to USE_OPT).
@@ -41,6 +41,12 @@ endif # Architecture or project specific options
#
+# Enables the use of FPU on Cortex-M4.
+# Enable this if you really want to use the STM FWLib.
+ifeq ($(USE_FPU),)
+ USE_FPU = no
+endif
+
# Enable this if you really want to use the STM FWLib.
ifeq ($(USE_FWLIB),)
USE_FWLIB = no
@@ -64,10 +70,11 @@ include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk
include $(CHIBIOS)/os/kernel/kernel.mk
-#include $(CHIBIOS)/test/test.mk
+include $(CHIBIOS)/test/test.mk
# Define linker script file here
LDSCRIPT= $(PORTLD)/STM32F407xG.ld
+#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
@@ -77,6 +84,7 @@ CSRC = $(PORTSRC) \ $(HALSRC) \
$(PLATFORMSRC) \
$(BOARDSRC) \
+ $(CHIBIOS)/os/various/chprintf.c \
main.c
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
@@ -197,6 +205,13 @@ ULIBS = # End of user defines
##############################################################################
+ifeq ($(USE_FPU),yes)
+ USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant
+ DDEFS += -DCORTEX_USE_FPU=TRUE
+else
+ DDEFS += -DCORTEX_USE_FPU=FALSE
+endif
+
ifeq ($(USE_FWLIB),yes)
include $(CHIBIOS)/ext/stm32lib/stm32lib.mk
CSRC += $(STM32SRC)
diff --git a/testhal/STM32F4xx/PWM-ICU/chconf.h b/testhal/STM32F4xx/PWM-ICU/chconf.h index c0181fef5..290044421 100644 --- a/testhal/STM32F4xx/PWM-ICU/chconf.h +++ b/testhal/STM32F4xx/PWM-ICU/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM32F4xx/PWM-ICU/halconf.h b/testhal/STM32F4xx/PWM-ICU/halconf.h index 539b810db..9e7b5b6fe 100644 --- a/testhal/STM32F4xx/PWM-ICU/halconf.h +++ b/testhal/STM32F4xx/PWM-ICU/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/STM32F4xx/PWM-ICU/main.c b/testhal/STM32F4xx/PWM-ICU/main.c index af3caa109..de2818a15 100644 --- a/testhal/STM32F4xx/PWM-ICU/main.c +++ b/testhal/STM32F4xx/PWM-ICU/main.c @@ -34,7 +34,7 @@ static void pwmc1cb(PWMDriver *pwmp) { }
static PWMConfig pwmcfg = {
- 10000, /* 10KHz PWM clock frequency. */
+ 10000, /* 10kHz PWM clock frequency. */
10000, /* Initial PWM period 1S. */
pwmpcb,
{
@@ -51,20 +51,22 @@ icucnt_t last_width, last_period; static void icuwidthcb(ICUDriver *icup) {
palSetPad(GPIOD, GPIOD_LED4);
- last_width = icuGetWidthI(icup);
+ last_width = icuGetWidth(icup);
}
static void icuperiodcb(ICUDriver *icup) {
palClearPad(GPIOD, GPIOD_LED4);
- last_period = icuGetPeriodI(icup);
+ last_period = icuGetPeriod(icup);
}
static ICUConfig icucfg = {
ICU_INPUT_ACTIVE_HIGH,
- 10000, /* 10KHz ICU clock frequency. */
+ 10000, /* 10kHz ICU clock frequency. */
icuwidthcb,
- icuperiodcb
+ icuperiodcb,
+ NULL,
+ ICU_CHANNEL_1
};
/*
diff --git a/testhal/STM32F4xx/RTC/Makefile b/testhal/STM32F4xx/RTC/Makefile index 82511a750..3b57b683a 100644 --- a/testhal/STM32F4xx/RTC/Makefile +++ b/testhal/STM32F4xx/RTC/Makefile @@ -5,7 +5,7 @@ # Compiler options here.
ifeq ($(USE_OPT),)
- USE_OPT = -O0 -ggdb -fomit-frame-pointer -falign-functions=16
+ USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
endif
# C specific options here (added to USE_OPT).
@@ -41,6 +41,12 @@ endif # Architecture or project specific options
#
+# Enables the use of FPU on Cortex-M4.
+# Enable this if you really want to use the STM FWLib.
+ifeq ($(USE_FPU),)
+ USE_FPU = no
+endif
+
# Enable this if you really want to use the STM FWLib.
ifeq ($(USE_FWLIB),)
USE_FWLIB = no
@@ -57,17 +63,18 @@ endif # Define project name here
PROJECT = ch
-# Imported source files
+# Imported source files and paths
CHIBIOS = ../../..
include $(CHIBIOS)/boards/NONSTANDARD_STM32F4_BARTHESS1/board.mk
include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk
include $(CHIBIOS)/os/kernel/kernel.mk
-#include $(CHIBIOS)/test/test.mk
+include $(CHIBIOS)/test/test.mk
# Define linker script file here
LDSCRIPT= $(PORTLD)/STM32F407xG.ld
+#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
@@ -132,8 +139,7 @@ CPPC = $(TRGT)g++ # Enable loading with g++ only if you need C++ runtime support.
# NOTE: You can use C++ even without C++ support if you are careful. C++
# runtime support makes code size explode.
-
-LD = $(TRGT)gcc
+LD = $(TRGT)gcc
#LD = $(TRGT)g++
CP = $(TRGT)objcopy
AS = $(TRGT)gcc -x assembler-with-cpp
@@ -142,13 +148,13 @@ HEX = $(CP) -O ihex BIN = $(CP) -O binary
# ARM-specific options here
-AOPT =
+AOPT =
# THUMB-specific options here
TOPT = -mthumb -DTHUMB
# Define C warning options here
-CWARN = -Wall -Wextra -Wstrict-prototypes
+CWARN = -Wall -Wextra -Wstrict-prototypes
# Define C++ warning options here
CPPWARN = -Wall -Wextra
@@ -194,7 +200,7 @@ UADEFS = UINCDIR =
# List the user directory to look for the libraries here
-ULIBDIR =
+ULIBDIR =
# List all user libraries here
ULIBS =
@@ -203,6 +209,13 @@ ULIBS = # End of user defines
##############################################################################
+ifeq ($(USE_FPU),yes)
+ USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant
+ DDEFS += -DCORTEX_USE_FPU=TRUE
+else
+ DDEFS += -DCORTEX_USE_FPU=FALSE
+endif
+
ifeq ($(USE_FWLIB),yes)
include $(CHIBIOS)/ext/stm32lib/stm32lib.mk
CSRC += $(STM32SRC)
diff --git a/testhal/STM32F4xx/RTC/chconf.h b/testhal/STM32F4xx/RTC/chconf.h index 5569fa3f2..f0b22f246 100644 --- a/testhal/STM32F4xx/RTC/chconf.h +++ b/testhal/STM32F4xx/RTC/chconf.h @@ -438,7 +438,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM32F4xx/RTC/halconf.h b/testhal/STM32F4xx/RTC/halconf.h index 0f9c5163a..db9b18ed8 100644 --- a/testhal/STM32F4xx/RTC/halconf.h +++ b/testhal/STM32F4xx/RTC/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
@@ -303,7 +303,7 @@ * default configuration.
*/
#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
-#define SERIAL_DEFAULT_BITRATE 9600
+#define SERIAL_DEFAULT_BITRATE 38400
#endif
/**
diff --git a/testhal/STM32F4xx/SDC/main.c b/testhal/STM32F4xx/SDC/main.c index e641aa555..4a1711eff 100755 --- a/testhal/STM32F4xx/SDC/main.c +++ b/testhal/STM32F4xx/SDC/main.c @@ -27,7 +27,7 @@ #include "ff.h"
-#define SDC_DATA_DESTRUCTIVE_TEST FALSE
+#define SDC_DATA_DESTRUCTIVE_TEST TRUE
#define SDC_BURST_SIZE 8 /* how many sectors reads at once */
static uint8_t outbuf[SDC_BLOCK_SIZE * SDC_BURST_SIZE + 1];
diff --git a/testhal/STM32F4xx/SPI/Makefile b/testhal/STM32F4xx/SPI/Makefile index 425e5f6c5..86de6d81c 100644 --- a/testhal/STM32F4xx/SPI/Makefile +++ b/testhal/STM32F4xx/SPI/Makefile @@ -5,7 +5,7 @@ # Compiler options here.
ifeq ($(USE_OPT),)
- USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 -mhard-float -mfpu=fpv4-sp-d16 -fsingle-precision-constant
+ USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
endif
# C specific options here (added to USE_OPT).
@@ -41,6 +41,12 @@ endif # Architecture or project specific options
#
+# Enables the use of FPU on Cortex-M4.
+# Enable this if you really want to use the STM FWLib.
+ifeq ($(USE_FPU),)
+ USE_FPU = no
+endif
+
# Enable this if you really want to use the STM FWLib.
ifeq ($(USE_FWLIB),)
USE_FWLIB = no
@@ -64,10 +70,11 @@ include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk
include $(CHIBIOS)/os/kernel/kernel.mk
-#include $(CHIBIOS)/test/test.mk
+include $(CHIBIOS)/test/test.mk
# Define linker script file here
LDSCRIPT= $(PORTLD)/STM32F407xG.ld
+#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
@@ -77,8 +84,7 @@ CSRC = $(PORTSRC) \ $(HALSRC) \
$(PLATFORMSRC) \
$(BOARDSRC) \
- $(CHIBIOS)/os/various/evtimer.c \
- $(CHIBIOS)/os/various/syscalls.c \
+ $(CHIBIOS)/os/various/chprintf.c \
main.c
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
@@ -199,6 +205,13 @@ ULIBS = # End of user defines
##############################################################################
+ifeq ($(USE_FPU),yes)
+ USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant
+ DDEFS += -DCORTEX_USE_FPU=TRUE
+else
+ DDEFS += -DCORTEX_USE_FPU=FALSE
+endif
+
ifeq ($(USE_FWLIB),yes)
include $(CHIBIOS)/ext/stm32lib/stm32lib.mk
CSRC += $(STM32SRC)
diff --git a/testhal/STM32F4xx/SPI/chconf.h b/testhal/STM32F4xx/SPI/chconf.h index c0181fef5..290044421 100644 --- a/testhal/STM32F4xx/SPI/chconf.h +++ b/testhal/STM32F4xx/SPI/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM32F4xx/SPI/halconf.h b/testhal/STM32F4xx/SPI/halconf.h index 84a220f12..d176ad1a7 100644 --- a/testhal/STM32F4xx/SPI/halconf.h +++ b/testhal/STM32F4xx/SPI/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/STM32F4xx/SPI/main.c b/testhal/STM32F4xx/SPI/main.c index 156cc2dd5..cd7d46804 100644 --- a/testhal/STM32F4xx/SPI/main.c +++ b/testhal/STM32F4xx/SPI/main.c @@ -32,7 +32,7 @@ static const SPIConfig hs_spicfg = { };
/*
- * Low speed SPI configuration (328.125KHz, CPHA=0, CPOL=0, MSb first).
+ * Low speed SPI configuration (328.125kHz, CPHA=0, CPOL=0, MSb first).
*/
static const SPIConfig ls_spicfg = {
NULL,
diff --git a/testhal/STM32F4xx/UART/Makefile b/testhal/STM32F4xx/UART/Makefile index de1ac051f..86de6d81c 100644 --- a/testhal/STM32F4xx/UART/Makefile +++ b/testhal/STM32F4xx/UART/Makefile @@ -5,7 +5,7 @@ # Compiler options here.
ifeq ($(USE_OPT),)
- USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16 -mhard-float -mfpu=fpv4-sp-d16 -fsingle-precision-constant
+ USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
endif
# C specific options here (added to USE_OPT).
@@ -41,6 +41,12 @@ endif # Architecture or project specific options
#
+# Enables the use of FPU on Cortex-M4.
+# Enable this if you really want to use the STM FWLib.
+ifeq ($(USE_FPU),)
+ USE_FPU = no
+endif
+
# Enable this if you really want to use the STM FWLib.
ifeq ($(USE_FWLIB),)
USE_FWLIB = no
@@ -64,10 +70,11 @@ include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk
include $(CHIBIOS)/os/kernel/kernel.mk
-#include $(CHIBIOS)/test/test.mk
+include $(CHIBIOS)/test/test.mk
# Define linker script file here
LDSCRIPT= $(PORTLD)/STM32F407xG.ld
+#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld
# C sources that can be compiled in ARM or THUMB mode depending on the global
# setting.
@@ -77,6 +84,7 @@ CSRC = $(PORTSRC) \ $(HALSRC) \
$(PLATFORMSRC) \
$(BOARDSRC) \
+ $(CHIBIOS)/os/various/chprintf.c \
main.c
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
@@ -197,6 +205,13 @@ ULIBS = # End of user defines
##############################################################################
+ifeq ($(USE_FPU),yes)
+ USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant
+ DDEFS += -DCORTEX_USE_FPU=TRUE
+else
+ DDEFS += -DCORTEX_USE_FPU=FALSE
+endif
+
ifeq ($(USE_FWLIB),yes)
include $(CHIBIOS)/ext/stm32lib/stm32lib.mk
CSRC += $(STM32SRC)
diff --git a/testhal/STM32F4xx/UART/chconf.h b/testhal/STM32F4xx/UART/chconf.h index c0181fef5..290044421 100644 --- a/testhal/STM32F4xx/UART/chconf.h +++ b/testhal/STM32F4xx/UART/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM32F4xx/UART/halconf.h b/testhal/STM32F4xx/UART/halconf.h index 5f667087c..60af9dec0 100644 --- a/testhal/STM32F4xx/UART/halconf.h +++ b/testhal/STM32F4xx/UART/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/STM32F4xx/USB_CDC/Makefile b/testhal/STM32F4xx/USB_CDC/Makefile new file mode 100644 index 000000000..1a6ac2d74 --- /dev/null +++ b/testhal/STM32F4xx/USB_CDC/Makefile @@ -0,0 +1,223 @@ +##############################################################################
+# Build global options
+# NOTE: Can be overridden externally.
+#
+
+# Compiler options here.
+ifeq ($(USE_OPT),)
+ USE_OPT = -O2 -ggdb -fomit-frame-pointer -falign-functions=16
+endif
+
+# C specific options here (added to USE_OPT).
+ifeq ($(USE_COPT),)
+ USE_COPT =
+endif
+
+# C++ specific options here (added to USE_OPT).
+ifeq ($(USE_CPPOPT),)
+ USE_CPPOPT = -fno-rtti
+endif
+
+# Enable this if you want the linker to remove unused code and data
+ifeq ($(USE_LINK_GC),)
+ USE_LINK_GC = yes
+endif
+
+# If enabled, this option allows to compile the application in THUMB mode.
+ifeq ($(USE_THUMB),)
+ USE_THUMB = yes
+endif
+
+# Enable this if you want to see the full log while compiling.
+ifeq ($(USE_VERBOSE_COMPILE),)
+ USE_VERBOSE_COMPILE = no
+endif
+
+#
+# Build global options
+##############################################################################
+
+##############################################################################
+# Architecture or project specific options
+#
+
+# Enables the use of FPU on Cortex-M4.
+# Enable this if you really want to use the STM FWLib.
+ifeq ($(USE_FPU),)
+ USE_FPU = no
+endif
+
+# Enable this if you really want to use the STM FWLib.
+ifeq ($(USE_FWLIB),)
+ USE_FWLIB = no
+endif
+
+#
+# Architecture or project specific options
+##############################################################################
+
+##############################################################################
+# Project, sources and paths
+#
+
+# Define project name here
+PROJECT = ch
+
+# Imported source files and paths
+CHIBIOS = ../../..
+include $(CHIBIOS)/boards/ST_STM32F4_DISCOVERY/board.mk
+include $(CHIBIOS)/os/hal/platforms/STM32F4xx/platform.mk
+include $(CHIBIOS)/os/hal/hal.mk
+include $(CHIBIOS)/os/ports/GCC/ARMCMx/STM32F4xx/port.mk
+include $(CHIBIOS)/os/kernel/kernel.mk
+include $(CHIBIOS)/test/test.mk
+
+# Define linker script file here
+LDSCRIPT= $(PORTLD)/STM32F407xG.ld
+#LDSCRIPT= $(PORTLD)/STM32F407xG_CCM.ld
+
+# C sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CSRC = $(PORTSRC) \
+ $(KERNSRC) \
+ $(TESTSRC) \
+ $(HALSRC) \
+ $(PLATFORMSRC) \
+ $(BOARDSRC) \
+ $(CHIBIOS)/os/various/shell.c \
+ $(CHIBIOS)/os/various/chprintf.c \
+ main.c
+
+# C++ sources that can be compiled in ARM or THUMB mode depending on the global
+# setting.
+CPPSRC =
+
+# C sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACSRC =
+
+# C++ sources to be compiled in ARM mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+ACPPSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCSRC =
+
+# C sources to be compiled in THUMB mode regardless of the global setting.
+# NOTE: Mixing ARM and THUMB mode enables the -mthumb-interwork compiler
+# option that results in lower performance and larger code size.
+TCPPSRC =
+
+# List ASM source files here
+ASMSRC = $(PORTASM)
+
+INCDIR = $(PORTINC) $(KERNINC) $(TESTINC) \
+ $(HALINC) $(PLATFORMINC) $(BOARDINC) \
+ $(CHIBIOS)/os/various
+
+#
+# Project, sources and paths
+##############################################################################
+
+##############################################################################
+# Compiler settings
+#
+
+MCU = cortex-m4
+
+#TRGT = arm-elf-
+TRGT = arm-none-eabi-
+CC = $(TRGT)gcc
+CPPC = $(TRGT)g++
+# Enable loading with g++ only if you need C++ runtime support.
+# NOTE: You can use C++ even without C++ support if you are careful. C++
+# runtime support makes code size explode.
+LD = $(TRGT)gcc
+#LD = $(TRGT)g++
+CP = $(TRGT)objcopy
+AS = $(TRGT)gcc -x assembler-with-cpp
+OD = $(TRGT)objdump
+HEX = $(CP) -O ihex
+BIN = $(CP) -O binary
+
+# ARM-specific options here
+AOPT =
+
+# THUMB-specific options here
+TOPT = -mthumb -DTHUMB
+
+# Define C warning options here
+CWARN = -Wall -Wextra -Wstrict-prototypes
+
+# Define C++ warning options here
+CPPWARN = -Wall -Wextra
+
+#
+# Compiler settings
+##############################################################################
+
+##############################################################################
+# Start of default section
+#
+
+# List all default C defines here, like -D_DEBUG=1
+DDEFS =
+
+# List all default ASM defines here, like -D_DEBUG=1
+DADEFS =
+
+# List all default directories to look for include files here
+DINCDIR =
+
+# List the default directory to look for the libraries here
+DLIBDIR =
+
+# List all default libraries here
+DLIBS =
+
+#
+# End of default section
+##############################################################################
+
+##############################################################################
+# Start of user section
+#
+
+# List all user C define here, like -D_DEBUG=1
+UDEFS =
+
+# Define ASM defines here
+UADEFS =
+
+# List all user directories here
+UINCDIR =
+
+# List the user directory to look for the libraries here
+ULIBDIR =
+
+# List all user libraries here
+ULIBS =
+
+#
+# End of user defines
+##############################################################################
+
+ifeq ($(USE_FPU),yes)
+ USE_OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant
+ DDEFS += -DCORTEX_USE_FPU=TRUE
+else
+ DDEFS += -DCORTEX_USE_FPU=FALSE
+endif
+
+ifeq ($(USE_FWLIB),yes)
+ include $(CHIBIOS)/ext/stm32lib/stm32lib.mk
+ CSRC += $(STM32SRC)
+ INCDIR += $(STM32INC)
+ USE_OPT += -DUSE_STDPERIPH_DRIVER
+endif
+
+include $(CHIBIOS)/os/ports/GCC/ARMCMx/rules.mk
diff --git a/testhal/STM32F4xx/USB_CDC/chconf.h b/testhal/STM32F4xx/USB_CDC/chconf.h new file mode 100644 index 000000000..290044421 --- /dev/null +++ b/testhal/STM32F4xx/USB_CDC/chconf.h @@ -0,0 +1,535 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file templates/chconf.h
+ * @brief Configuration file template.
+ * @details A copy of this file must be placed in each project directory, it
+ * contains the application specific kernel settings.
+ *
+ * @addtogroup config
+ * @details Kernel related settings and hooks.
+ * @{
+ */
+
+#ifndef _CHCONF_H_
+#define _CHCONF_H_
+
+/*===========================================================================*/
+/**
+ * @name Kernel parameters and options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief System tick frequency.
+ * @details Frequency of the system timer that drives the system ticks. This
+ * setting also defines the system tick time unit.
+ */
+#if !defined(CH_FREQUENCY) || defined(__DOXYGEN__)
+#define CH_FREQUENCY 1000
+#endif
+
+/**
+ * @brief Round robin interval.
+ * @details This constant is the number of system ticks allowed for the
+ * threads before preemption occurs. Setting this value to zero
+ * disables the preemption for threads with equal priority and the
+ * round robin becomes cooperative. Note that higher priority
+ * threads can still preempt, the kernel is always preemptive.
+ *
+ * @note Disabling the round robin preemption makes the kernel more compact
+ * and generally faster.
+ */
+#if !defined(CH_TIME_QUANTUM) || defined(__DOXYGEN__)
+#define CH_TIME_QUANTUM 20
+#endif
+
+/**
+ * @brief Managed RAM size.
+ * @details Size of the RAM area to be managed by the OS. If set to zero
+ * then the whole available RAM is used. The core memory is made
+ * available to the heap allocator and/or can be used directly through
+ * the simplified core memory allocator.
+ *
+ * @note In order to let the OS manage the whole RAM the linker script must
+ * provide the @p __heap_base__ and @p __heap_end__ symbols.
+ * @note Requires @p CH_USE_MEMCORE.
+ */
+#if !defined(CH_MEMCORE_SIZE) || defined(__DOXYGEN__)
+#define CH_MEMCORE_SIZE 0
+#endif
+
+/**
+ * @brief Idle thread automatic spawn suppression.
+ * @details When this option is activated the function @p chSysInit()
+ * does not spawn the idle thread automatically. The application has
+ * then the responsibility to do one of the following:
+ * - Spawn a custom idle thread at priority @p IDLEPRIO.
+ * - Change the main() thread priority to @p IDLEPRIO then enter
+ * an endless loop. In this scenario the @p main() thread acts as
+ * the idle thread.
+ * .
+ * @note Unless an idle thread is spawned the @p main() thread must not
+ * enter a sleep state.
+ */
+#if !defined(CH_NO_IDLE_THREAD) || defined(__DOXYGEN__)
+#define CH_NO_IDLE_THREAD FALSE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Performance options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief OS optimization.
+ * @details If enabled then time efficient rather than space efficient code
+ * is used when two possible implementations exist.
+ *
+ * @note This is not related to the compiler optimization options.
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_OPTIMIZE_SPEED) || defined(__DOXYGEN__)
+#define CH_OPTIMIZE_SPEED TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Subsystem options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads registry APIs.
+ * @details If enabled then the registry APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_REGISTRY) || defined(__DOXYGEN__)
+#define CH_USE_REGISTRY TRUE
+#endif
+
+/**
+ * @brief Threads synchronization APIs.
+ * @details If enabled then the @p chThdWait() function is included in
+ * the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_WAITEXIT) || defined(__DOXYGEN__)
+#define CH_USE_WAITEXIT TRUE
+#endif
+
+/**
+ * @brief Semaphores APIs.
+ * @details If enabled then the Semaphores APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_SEMAPHORES) || defined(__DOXYGEN__)
+#define CH_USE_SEMAPHORES TRUE
+#endif
+
+/**
+ * @brief Semaphores queuing mode.
+ * @details If enabled then the threads are enqueued on semaphores by
+ * priority rather than in FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special requirements.
+ * @note Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_SEMAPHORES_PRIORITY) || defined(__DOXYGEN__)
+#define CH_USE_SEMAPHORES_PRIORITY FALSE
+#endif
+
+/**
+ * @brief Atomic semaphore API.
+ * @details If enabled then the semaphores the @p chSemSignalWait() API
+ * is included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_SEMSW) || defined(__DOXYGEN__)
+#define CH_USE_SEMSW TRUE
+#endif
+
+/**
+ * @brief Mutexes APIs.
+ * @details If enabled then the mutexes APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_MUTEXES) || defined(__DOXYGEN__)
+#define CH_USE_MUTEXES TRUE
+#endif
+
+/**
+ * @brief Conditional Variables APIs.
+ * @details If enabled then the conditional variables APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_MUTEXES.
+ */
+#if !defined(CH_USE_CONDVARS) || defined(__DOXYGEN__)
+#define CH_USE_CONDVARS TRUE
+#endif
+
+/**
+ * @brief Conditional Variables APIs with timeout.
+ * @details If enabled then the conditional variables APIs with timeout
+ * specification are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_CONDVARS.
+ */
+#if !defined(CH_USE_CONDVARS_TIMEOUT) || defined(__DOXYGEN__)
+#define CH_USE_CONDVARS_TIMEOUT TRUE
+#endif
+
+/**
+ * @brief Events Flags APIs.
+ * @details If enabled then the event flags APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_EVENTS) || defined(__DOXYGEN__)
+#define CH_USE_EVENTS TRUE
+#endif
+
+/**
+ * @brief Events Flags APIs with timeout.
+ * @details If enabled then the events APIs with timeout specification
+ * are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_EVENTS.
+ */
+#if !defined(CH_USE_EVENTS_TIMEOUT) || defined(__DOXYGEN__)
+#define CH_USE_EVENTS_TIMEOUT TRUE
+#endif
+
+/**
+ * @brief Synchronous Messages APIs.
+ * @details If enabled then the synchronous messages APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_MESSAGES) || defined(__DOXYGEN__)
+#define CH_USE_MESSAGES TRUE
+#endif
+
+/**
+ * @brief Synchronous Messages queuing mode.
+ * @details If enabled then messages are served by priority rather than in
+ * FIFO order.
+ *
+ * @note The default is @p FALSE. Enable this if you have special requirements.
+ * @note Requires @p CH_USE_MESSAGES.
+ */
+#if !defined(CH_USE_MESSAGES_PRIORITY) || defined(__DOXYGEN__)
+#define CH_USE_MESSAGES_PRIORITY FALSE
+#endif
+
+/**
+ * @brief Mailboxes APIs.
+ * @details If enabled then the asynchronous messages (mailboxes) APIs are
+ * included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_SEMAPHORES.
+ */
+#if !defined(CH_USE_MAILBOXES) || defined(__DOXYGEN__)
+#define CH_USE_MAILBOXES TRUE
+#endif
+
+/**
+ * @brief I/O Queues APIs.
+ * @details If enabled then the I/O queues APIs are included in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_QUEUES) || defined(__DOXYGEN__)
+#define CH_USE_QUEUES TRUE
+#endif
+
+/**
+ * @brief Core Memory Manager APIs.
+ * @details If enabled then the core memory manager APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_MEMCORE) || defined(__DOXYGEN__)
+#define CH_USE_MEMCORE TRUE
+#endif
+
+/**
+ * @brief Heap Allocator APIs.
+ * @details If enabled then the memory heap allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_MEMCORE and either @p CH_USE_MUTEXES or
+ * @p CH_USE_SEMAPHORES.
+ * @note Mutexes are recommended.
+ */
+#if !defined(CH_USE_HEAP) || defined(__DOXYGEN__)
+#define CH_USE_HEAP TRUE
+#endif
+
+/**
+ * @brief C-runtime allocator.
+ * @details If enabled the the heap allocator APIs just wrap the C-runtime
+ * @p malloc() and @p free() functions.
+ *
+ * @note The default is @p FALSE.
+ * @note Requires @p CH_USE_HEAP.
+ * @note The C-runtime may or may not require @p CH_USE_MEMCORE, see the
+ * appropriate documentation.
+ */
+#if !defined(CH_USE_MALLOC_HEAP) || defined(__DOXYGEN__)
+#define CH_USE_MALLOC_HEAP FALSE
+#endif
+
+/**
+ * @brief Memory Pools Allocator APIs.
+ * @details If enabled then the memory pools allocator APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ */
+#if !defined(CH_USE_MEMPOOLS) || defined(__DOXYGEN__)
+#define CH_USE_MEMPOOLS TRUE
+#endif
+
+/**
+ * @brief Dynamic Threads APIs.
+ * @details If enabled then the dynamic threads creation APIs are included
+ * in the kernel.
+ *
+ * @note The default is @p TRUE.
+ * @note Requires @p CH_USE_WAITEXIT.
+ * @note Requires @p CH_USE_HEAP and/or @p CH_USE_MEMPOOLS.
+ */
+#if !defined(CH_USE_DYNAMIC) || defined(__DOXYGEN__)
+#define CH_USE_DYNAMIC TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Debug options
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Debug option, system state check.
+ * @details If enabled the correct call protocol for system APIs is checked
+ * at runtime.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_SYSTEM_STATE_CHECK) || defined(__DOXYGEN__)
+#define CH_DBG_SYSTEM_STATE_CHECK TRUE
+#endif
+
+/**
+ * @brief Debug option, parameters checks.
+ * @details If enabled then the checks on the API functions input
+ * parameters are activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_CHECKS) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_CHECKS TRUE
+#endif
+
+/**
+ * @brief Debug option, consistency checks.
+ * @details If enabled then all the assertions in the kernel code are
+ * activated. This includes consistency checks inside the kernel,
+ * runtime anomalies and port-defined checks.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_ASSERTS) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_ASSERTS TRUE
+#endif
+
+/**
+ * @brief Debug option, trace buffer.
+ * @details If enabled then the context switch circular trace buffer is
+ * activated.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_ENABLE_TRACE) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_TRACE TRUE
+#endif
+
+/**
+ * @brief Debug option, stack checks.
+ * @details If enabled then a runtime stack check is performed.
+ *
+ * @note The default is @p FALSE.
+ * @note The stack check is performed in a architecture/port dependent way.
+ * It may not be implemented or some ports.
+ * @note The default failure mode is to halt the system with the global
+ * @p panic_msg variable set to @p NULL.
+ */
+#if !defined(CH_DBG_ENABLE_STACK_CHECK) || defined(__DOXYGEN__)
+#define CH_DBG_ENABLE_STACK_CHECK TRUE
+#endif
+
+/**
+ * @brief Debug option, stacks initialization.
+ * @details If enabled then the threads working area is filled with a byte
+ * value when a thread is created. This can be useful for the
+ * runtime measurement of the used stack.
+ *
+ * @note The default is @p FALSE.
+ */
+#if !defined(CH_DBG_FILL_THREADS) || defined(__DOXYGEN__)
+#define CH_DBG_FILL_THREADS TRUE
+#endif
+
+/**
+ * @brief Debug option, threads profiling.
+ * @details If enabled then a field is added to the @p Thread structure that
+ * counts the system ticks occurred while executing the thread.
+ *
+ * @note The default is @p TRUE.
+ * @note This debug option is defaulted to TRUE because it is required by
+ * some test cases into the test suite.
+ */
+#if !defined(CH_DBG_THREADS_PROFILING) || defined(__DOXYGEN__)
+#define CH_DBG_THREADS_PROFILING TRUE
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/**
+ * @name Kernel hooks
+ * @{
+ */
+/*===========================================================================*/
+
+/**
+ * @brief Threads descriptor structure extension.
+ * @details User fields added to the end of the @p Thread structure.
+ */
+#if !defined(THREAD_EXT_FIELDS) || defined(__DOXYGEN__)
+#define THREAD_EXT_FIELDS \
+ /* Add threads custom fields here.*/
+#endif
+
+/**
+ * @brief Threads initialization hook.
+ * @details User initialization code added to the @p chThdInit() API.
+ *
+ * @note It is invoked from within @p chThdInit() and implicitly from all
+ * the threads creation APIs.
+ */
+#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
+#define THREAD_EXT_INIT_HOOK(tp) { \
+ /* Add threads initialization code here.*/ \
+}
+#endif
+
+/**
+ * @brief Threads finalization hook.
+ * @details User finalization code added to the @p chThdExit() API.
+ *
+ * @note It is inserted into lock zone.
+ * @note It is also invoked when the threads simply return in order to
+ * terminate.
+ */
+#if !defined(THREAD_EXT_EXIT_HOOK) || defined(__DOXYGEN__)
+#define THREAD_EXT_EXIT_HOOK(tp) { \
+ /* Add threads finalization code here.*/ \
+}
+#endif
+
+/**
+ * @brief Context switch hook.
+ * @details This hook is invoked just before switching between threads.
+ */
+#if !defined(THREAD_CONTEXT_SWITCH_HOOK) || defined(__DOXYGEN__)
+#define THREAD_CONTEXT_SWITCH_HOOK(ntp, otp) { \
+ /* System halt code here.*/ \
+}
+#endif
+
+/**
+ * @brief Idle Loop hook.
+ * @details This hook is continuously invoked by the idle thread loop.
+ */
+#if !defined(IDLE_LOOP_HOOK) || defined(__DOXYGEN__)
+#define IDLE_LOOP_HOOK() { \
+ /* Idle loop code here.*/ \
+}
+#endif
+
+/**
+ * @brief System tick event hook.
+ * @details This hook is invoked in the system tick handler immediately
+ * after processing the virtual timers queue.
+ */
+#if !defined(SYSTEM_TICK_EVENT_HOOK) || defined(__DOXYGEN__)
+#define SYSTEM_TICK_EVENT_HOOK() { \
+ /* System tick event code here.*/ \
+}
+#endif
+
+/**
+ * @brief System halt hook.
+ * @details This hook is invoked in case to a system halting error before
+ * the system is halted.
+ */
+#if !defined(SYSTEM_HALT_HOOK) || defined(__DOXYGEN__)
+#define SYSTEM_HALT_HOOK() { \
+ /* System halt code here.*/ \
+}
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Port-specific settings (override port settings defaulted in chcore.h). */
+/*===========================================================================*/
+
+#endif /* _CHCONF_H_ */
+
+/** @} */
diff --git a/testhal/STM32F4xx/USB_CDC/halconf.h b/testhal/STM32F4xx/USB_CDC/halconf.h new file mode 100644 index 000000000..7d1f492f8 --- /dev/null +++ b/testhal/STM32F4xx/USB_CDC/halconf.h @@ -0,0 +1,342 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file templates/halconf.h
+ * @brief HAL configuration header.
+ * @details HAL configuration file, this file allows to enable or disable the
+ * various device drivers from your application. You may also use
+ * this file in order to override the device drivers default settings.
+ *
+ * @addtogroup HAL_CONF
+ * @{
+ */
+
+#ifndef _HALCONF_H_
+#define _HALCONF_H_
+
+#include "mcuconf.h"
+
+/**
+ * @brief Enables the TM subsystem.
+ */
+#if !defined(HAL_USE_TM) || defined(__DOXYGEN__)
+#define HAL_USE_TM TRUE
+#endif
+
+/**
+ * @brief Enables the PAL subsystem.
+ */
+#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__)
+#define HAL_USE_PAL TRUE
+#endif
+
+/**
+ * @brief Enables the ADC subsystem.
+ */
+#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__)
+#define HAL_USE_ADC FALSE
+#endif
+
+/**
+ * @brief Enables the CAN subsystem.
+ */
+#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__)
+#define HAL_USE_CAN FALSE
+#endif
+
+/**
+ * @brief Enables the EXT subsystem.
+ */
+#if !defined(HAL_USE_EXT) || defined(__DOXYGEN__)
+#define HAL_USE_EXT FALSE
+#endif
+
+/**
+ * @brief Enables the GPT subsystem.
+ */
+#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__)
+#define HAL_USE_GPT FALSE
+#endif
+
+/**
+ * @brief Enables the I2C subsystem.
+ */
+#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
+#define HAL_USE_I2C FALSE
+#endif
+
+/**
+ * @brief Enables the ICU subsystem.
+ */
+#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
+#define HAL_USE_ICU FALSE
+#endif
+
+/**
+ * @brief Enables the MAC subsystem.
+ */
+#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__)
+#define HAL_USE_MAC FALSE
+#endif
+
+/**
+ * @brief Enables the MMC_SPI subsystem.
+ */
+#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_MMC_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the PWM subsystem.
+ */
+#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__)
+#define HAL_USE_PWM FALSE
+#endif
+
+/**
+ * @brief Enables the RTC subsystem.
+ */
+#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__)
+#define HAL_USE_RTC FALSE
+#endif
+
+/**
+ * @brief Enables the SDC subsystem.
+ */
+#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__)
+#define HAL_USE_SDC FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL subsystem.
+ */
+#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL FALSE
+#endif
+
+/**
+ * @brief Enables the SERIAL over USB subsystem.
+ */
+#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__)
+#define HAL_USE_SERIAL_USB TRUE
+#endif
+
+/**
+ * @brief Enables the SPI subsystem.
+ */
+#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__)
+#define HAL_USE_SPI FALSE
+#endif
+
+/**
+ * @brief Enables the UART subsystem.
+ */
+#if !defined(HAL_USE_UART) || defined(__DOXYGEN__)
+#define HAL_USE_UART FALSE
+#endif
+
+/**
+ * @brief Enables the USB subsystem.
+ */
+#if !defined(HAL_USE_USB) || defined(__DOXYGEN__)
+#define HAL_USE_USB TRUE
+#endif
+
+/*===========================================================================*/
+/* ADC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__)
+#define ADC_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define ADC_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* CAN driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Sleep mode related APIs inclusion switch.
+ */
+#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__)
+#define CAN_USE_SLEEP_MODE TRUE
+#endif
+
+/*===========================================================================*/
+/* I2C driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables the mutual exclusion APIs on the I2C bus.
+ */
+#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define I2C_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+/*===========================================================================*/
+/* MAC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables an event sources for incoming packets.
+ */
+#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__)
+#define MAC_USE_EVENTS TRUE
+#endif
+
+/*===========================================================================*/
+/* MMC_SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Block size for MMC transfers.
+ */
+#if !defined(MMC_SECTOR_SIZE) || defined(__DOXYGEN__)
+#define MMC_SECTOR_SIZE 512
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ * This option is recommended also if the SPI driver does not
+ * use a DMA channel and heavily loads the CPU.
+ */
+#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__)
+#define MMC_NICE_WAITING TRUE
+#endif
+
+/**
+ * @brief Number of positive insertion queries before generating the
+ * insertion event.
+ */
+#if !defined(MMC_POLLING_INTERVAL) || defined(__DOXYGEN__)
+#define MMC_POLLING_INTERVAL 10
+#endif
+
+/**
+ * @brief Interval, in milliseconds, between insertion queries.
+ */
+#if !defined(MMC_POLLING_DELAY) || defined(__DOXYGEN__)
+#define MMC_POLLING_DELAY 10
+#endif
+
+/**
+ * @brief Uses the SPI polled API for small data transfers.
+ * @details Polled transfers usually improve performance because it
+ * saves two context switches and interrupt servicing. Note
+ * that this option has no effect on large transfers which
+ * are always performed using DMAs/IRQs.
+ */
+#if !defined(MMC_USE_SPI_POLLING) || defined(__DOXYGEN__)
+#define MMC_USE_SPI_POLLING TRUE
+#endif
+
+/*===========================================================================*/
+/* SDC driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Number of initialization attempts before rejecting the card.
+ * @note Attempts are performed at 10mS intervals.
+ */
+#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
+#define SDC_INIT_RETRY 100
+#endif
+
+/**
+ * @brief Include support for MMC cards.
+ * @note MMC support is not yet implemented so this option must be kept
+ * at @p FALSE.
+ */
+#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__)
+#define SDC_MMC_SUPPORT FALSE
+#endif
+
+/**
+ * @brief Delays insertions.
+ * @details If enabled this options inserts delays into the MMC waiting
+ * routines releasing some extra CPU time for the threads with
+ * lower priority, this may slow down the driver a bit however.
+ */
+#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__)
+#define SDC_NICE_WAITING TRUE
+#endif
+
+/*===========================================================================*/
+/* SERIAL driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Default bit rate.
+ * @details Configuration parameter, this is the baud rate selected for the
+ * default configuration.
+ */
+#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__)
+#define SERIAL_DEFAULT_BITRATE 38400
+#endif
+
+/**
+ * @brief Serial buffers size.
+ * @details Configuration parameter, you can change the depth of the queue
+ * buffers depending on the requirements of your application.
+ * @note The default is 64 bytes for both the transmission and receive
+ * buffers.
+ */
+#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__)
+#define SERIAL_BUFFERS_SIZE 16
+#endif
+
+/*===========================================================================*/
+/* SPI driver related settings. */
+/*===========================================================================*/
+
+/**
+ * @brief Enables synchronous APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__)
+#define SPI_USE_WAIT TRUE
+#endif
+
+/**
+ * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs.
+ * @note Disabling this option saves both code and data space.
+ */
+#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
+#define SPI_USE_MUTUAL_EXCLUSION TRUE
+#endif
+
+#endif /* _HALCONF_H_ */
+
+/** @} */
diff --git a/testhal/STM32F4xx/USB_CDC/main.c b/testhal/STM32F4xx/USB_CDC/main.c new file mode 100644 index 000000000..ff6b2e15b --- /dev/null +++ b/testhal/STM32F4xx/USB_CDC/main.c @@ -0,0 +1,451 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+#include <stdio.h>
+#include <string.h>
+
+#include "ch.h"
+#include "hal.h"
+#include "test.h"
+
+#include "usb_cdc.h"
+#include "shell.h"
+#include "chprintf.h"
+
+/*===========================================================================*/
+/* USB related stuff. */
+/*===========================================================================*/
+
+/*
+ * USB Driver structure.
+ */
+static SerialUSBDriver SDU1;
+
+/*
+ * USB Device Descriptor.
+ */
+static const uint8_t vcom_device_descriptor_data[18] = {
+ USB_DESC_DEVICE (0x0110, /* bcdUSB (1.1). */
+ 0x02, /* bDeviceClass (CDC). */
+ 0x00, /* bDeviceSubClass. */
+ 0x00, /* bDeviceProtocol. */
+ 0x40, /* bMaxPacketSize. */
+ 0x0483, /* idVendor (ST). */
+ 0x5740, /* idProduct. */
+ 0x0200, /* bcdDevice. */
+ 1, /* iManufacturer. */
+ 2, /* iProduct. */
+ 3, /* iSerialNumber. */
+ 1) /* bNumConfigurations. */
+};
+
+/*
+ * Device Descriptor wrapper.
+ */
+static const USBDescriptor vcom_device_descriptor = {
+ sizeof vcom_device_descriptor_data,
+ vcom_device_descriptor_data
+};
+
+/* Configuration Descriptor tree for a CDC.*/
+static const uint8_t vcom_configuration_descriptor_data[67] = {
+ /* Configuration Descriptor.*/
+ USB_DESC_CONFIGURATION(67, /* wTotalLength. */
+ 0x02, /* bNumInterfaces. */
+ 0x01, /* bConfigurationValue. */
+ 0, /* iConfiguration. */
+ 0xC0, /* bmAttributes (self powered). */
+ 50), /* bMaxPower (100mA). */
+ /* Interface Descriptor.*/
+ USB_DESC_INTERFACE (0x00, /* bInterfaceNumber. */
+ 0x00, /* bAlternateSetting. */
+ 0x01, /* bNumEndpoints. */
+ 0x02, /* bInterfaceClass (Communications
+ Interface Class, CDC section
+ 4.2). */
+ 0x02, /* bInterfaceSubClass (Abstract
+ Control Model, CDC section 4.3). */
+ 0x01, /* bInterfaceProtocol (AT commands,
+ CDC section 4.4). */
+ 0), /* iInterface. */
+ /* Header Functional Descriptor (CDC section 5.2.3).*/
+ USB_DESC_BYTE (5), /* bLength. */
+ USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
+ USB_DESC_BYTE (0x00), /* bDescriptorSubtype (Header
+ Functional Descriptor. */
+ USB_DESC_BCD (0x0110), /* bcdCDC. */
+ /* Call Management Functional Descriptor. */
+ USB_DESC_BYTE (5), /* bFunctionLength. */
+ USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
+ USB_DESC_BYTE (0x01), /* bDescriptorSubtype (Call Management
+ Functional Descriptor). */
+ USB_DESC_BYTE (0x00), /* bmCapabilities (D0+D1). */
+ USB_DESC_BYTE (0x01), /* bDataInterface. */
+ /* ACM Functional Descriptor.*/
+ USB_DESC_BYTE (4), /* bFunctionLength. */
+ USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
+ USB_DESC_BYTE (0x02), /* bDescriptorSubtype (Abstract
+ Control Management Descriptor). */
+ USB_DESC_BYTE (0x02), /* bmCapabilities. */
+ /* Union Functional Descriptor.*/
+ USB_DESC_BYTE (5), /* bFunctionLength. */
+ USB_DESC_BYTE (0x24), /* bDescriptorType (CS_INTERFACE). */
+ USB_DESC_BYTE (0x06), /* bDescriptorSubtype (Union
+ Functional Descriptor). */
+ USB_DESC_BYTE (0x00), /* bMasterInterface (Communication
+ Class Interface). */
+ USB_DESC_BYTE (0x01), /* bSlaveInterface0 (Data Class
+ Interface). */
+ /* Endpoint 2 Descriptor.*/
+ USB_DESC_ENDPOINT (USB_CDC_INTERRUPT_REQUEST_EP|0x80,
+ 0x03, /* bmAttributes (Interrupt). */
+ 0x0008, /* wMaxPacketSize. */
+ 0xFF), /* bInterval. */
+ /* Interface Descriptor.*/
+ USB_DESC_INTERFACE (0x01, /* bInterfaceNumber. */
+ 0x00, /* bAlternateSetting. */
+ 0x02, /* bNumEndpoints. */
+ 0x0A, /* bInterfaceClass (Data Class
+ Interface, CDC section 4.5). */
+ 0x00, /* bInterfaceSubClass (CDC section
+ 4.6). */
+ 0x00, /* bInterfaceProtocol (CDC section
+ 4.7). */
+ 0x00), /* iInterface. */
+ /* Endpoint 3 Descriptor.*/
+ USB_DESC_ENDPOINT (USB_CDC_DATA_AVAILABLE_EP, /* bEndpointAddress.*/
+ 0x02, /* bmAttributes (Bulk). */
+ 0x0040, /* wMaxPacketSize. */
+ 0x00), /* bInterval. */
+ /* Endpoint 1 Descriptor.*/
+ USB_DESC_ENDPOINT (USB_CDC_DATA_REQUEST_EP|0x80, /* bEndpointAddress.*/
+ 0x02, /* bmAttributes (Bulk). */
+ 0x0040, /* wMaxPacketSize. */
+ 0x00) /* bInterval. */
+};
+
+/*
+ * Configuration Descriptor wrapper.
+ */
+static const USBDescriptor vcom_configuration_descriptor = {
+ sizeof vcom_configuration_descriptor_data,
+ vcom_configuration_descriptor_data
+};
+
+/*
+ * U.S. English language identifier.
+ */
+static const uint8_t vcom_string0[] = {
+ USB_DESC_BYTE(4), /* bLength. */
+ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
+ USB_DESC_WORD(0x0409) /* wLANGID (U.S. English). */
+};
+
+/*
+ * Vendor string.
+ */
+static const uint8_t vcom_string1[] = {
+ USB_DESC_BYTE(38), /* bLength. */
+ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
+ 'S', 0, 'T', 0, 'M', 0, 'i', 0, 'c', 0, 'r', 0, 'o', 0, 'e', 0,
+ 'l', 0, 'e', 0, 'c', 0, 't', 0, 'r', 0, 'o', 0, 'n', 0, 'i', 0,
+ 'c', 0, 's', 0
+};
+
+/*
+ * Device Description string.
+ */
+static const uint8_t vcom_string2[] = {
+ USB_DESC_BYTE(56), /* bLength. */
+ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
+ 'C', 0, 'h', 0, 'i', 0, 'b', 0, 'i', 0, 'O', 0, 'S', 0, '/', 0,
+ 'R', 0, 'T', 0, ' ', 0, 'V', 0, 'i', 0, 'r', 0, 't', 0, 'u', 0,
+ 'a', 0, 'l', 0, ' ', 0, 'C', 0, 'O', 0, 'M', 0, ' ', 0, 'P', 0,
+ 'o', 0, 'r', 0, 't', 0
+};
+
+/*
+ * Serial Number string.
+ */
+static const uint8_t vcom_string3[] = {
+ USB_DESC_BYTE(8), /* bLength. */
+ USB_DESC_BYTE(USB_DESCRIPTOR_STRING), /* bDescriptorType. */
+ '0' + CH_KERNEL_MAJOR, 0,
+ '0' + CH_KERNEL_MINOR, 0,
+ '0' + CH_KERNEL_PATCH, 0
+};
+
+/*
+ * Strings wrappers array.
+ */
+static const USBDescriptor vcom_strings[] = {
+ {sizeof vcom_string0, vcom_string0},
+ {sizeof vcom_string1, vcom_string1},
+ {sizeof vcom_string2, vcom_string2},
+ {sizeof vcom_string3, vcom_string3}
+};
+
+/*
+ * Handles the GET_DESCRIPTOR callback. All required descriptors must be
+ * handled here.
+ */
+static const USBDescriptor *get_descriptor(USBDriver *usbp,
+ uint8_t dtype,
+ uint8_t dindex,
+ uint16_t lang) {
+
+ (void)usbp;
+ (void)lang;
+ switch (dtype) {
+ case USB_DESCRIPTOR_DEVICE:
+ return &vcom_device_descriptor;
+ case USB_DESCRIPTOR_CONFIGURATION:
+ return &vcom_configuration_descriptor;
+ case USB_DESCRIPTOR_STRING:
+ if (dindex < 4)
+ return &vcom_strings[dindex];
+ }
+ return NULL;
+}
+
+/**
+ * @brief EP1 initialization structure (IN only).
+ */
+static const USBEndpointConfig ep1config = {
+ USB_EP_MODE_TYPE_BULK | USB_EP_MODE_PACKET,
+ NULL,
+ sduDataTransmitted,
+ NULL,
+ 0x0040,
+ 0x0000,
+ NULL,
+ NULL
+};
+
+/**
+ * @brief EP2 initialization structure (IN only).
+ */
+static const USBEndpointConfig ep2config = {
+ USB_EP_MODE_TYPE_INTR | USB_EP_MODE_PACKET,
+ NULL,
+ sduInterruptTransmitted,
+ NULL,
+ 0x0010,
+ 0x0000,
+ NULL,
+ NULL
+};
+
+/**
+ * @brief EP3 initialization structure (OUT only).
+ */
+static const USBEndpointConfig ep3config = {
+ USB_EP_MODE_TYPE_BULK | USB_EP_MODE_PACKET,
+ NULL,
+ NULL,
+ sduDataReceived,
+ 0x0000,
+ 0x0040,
+ NULL,
+ NULL
+};
+
+/*
+ * Handles the USB driver global events.
+ */
+static void usb_event(USBDriver *usbp, usbevent_t event) {
+
+ switch (event) {
+ case USB_EVENT_RESET:
+ return;
+ case USB_EVENT_ADDRESS:
+ return;
+ case USB_EVENT_CONFIGURED:
+ /* Enables the endpoints specified into the configuration.
+ Note, this callback is invoked from an ISR so I-Class functions
+ must be used.*/
+ chSysLockFromIsr();
+ usbInitEndpointI(usbp, USB_CDC_DATA_REQUEST_EP, &ep1config);
+ usbInitEndpointI(usbp, USB_CDC_INTERRUPT_REQUEST_EP, &ep2config);
+ usbInitEndpointI(usbp, USB_CDC_DATA_AVAILABLE_EP, &ep3config);
+ chSysUnlockFromIsr();
+ return;
+ case USB_EVENT_SUSPEND:
+ return;
+ case USB_EVENT_WAKEUP:
+ return;
+ case USB_EVENT_STALLED:
+ return;
+ }
+ return;
+}
+
+/*
+ * Serial over USB driver configuration.
+ */
+static const SerialUSBConfig serusbcfg = {
+ &USBD1,
+ {
+ usb_event,
+ get_descriptor,
+ sduRequestsHook,
+ NULL
+ }
+};
+
+/*===========================================================================*/
+/* Command line related. */
+/*===========================================================================*/
+
+#define SHELL_WA_SIZE THD_WA_SIZE(2048)
+#define TEST_WA_SIZE THD_WA_SIZE(256)
+
+static void cmd_mem(BaseChannel *chp, int argc, char *argv[]) {
+ size_t n, size;
+
+ (void)argv;
+ if (argc > 0) {
+ chprintf(chp, "Usage: mem\r\n");
+ return;
+ }
+ n = chHeapStatus(NULL, &size);
+ chprintf(chp, "core free memory : %u bytes\r\n", chCoreStatus());
+ chprintf(chp, "heap fragments : %u\r\n", n);
+ chprintf(chp, "heap free total : %u bytes\r\n", size);
+}
+
+static void cmd_threads(BaseChannel *chp, int argc, char *argv[]) {
+ static const char *states[] = {THD_STATE_NAMES};
+ Thread *tp;
+
+ (void)argv;
+ if (argc > 0) {
+ chprintf(chp, "Usage: threads\r\n");
+ return;
+ }
+ chprintf(chp, " addr stack prio refs state time\r\n");
+ tp = chRegFirstThread();
+ do {
+ chprintf(chp, "%.8lx %.8lx %4lu %4lu %9s %lu\r\n",
+ (uint32_t)tp, (uint32_t)tp->p_ctx.r13,
+ (uint32_t)tp->p_prio, (uint32_t)(tp->p_refs - 1),
+ states[tp->p_state], (uint32_t)tp->p_time);
+ tp = chRegNextThread(tp);
+ } while (tp != NULL);
+}
+
+static void cmd_test(BaseChannel *chp, int argc, char *argv[]) {
+ Thread *tp;
+
+ (void)argv;
+ if (argc > 0) {
+ chprintf(chp, "Usage: test\r\n");
+ return;
+ }
+ tp = chThdCreateFromHeap(NULL, TEST_WA_SIZE, chThdGetPriority(),
+ TestThread, chp);
+ if (tp == NULL) {
+ chprintf(chp, "out of memory\r\n");
+ return;
+ }
+ chThdWait(tp);
+}
+
+static const ShellCommand commands[] = {
+ {"mem", cmd_mem},
+ {"threads", cmd_threads},
+ {"test", cmd_test},
+ {NULL, NULL}
+};
+
+static const ShellConfig shell_cfg1 = {
+ (BaseChannel *)&SDU1,
+ commands
+};
+
+/*===========================================================================*/
+/* Generic code. */
+/*===========================================================================*/
+
+/*
+ * Red LED blinker thread, times are in milliseconds.
+ */
+static WORKING_AREA(waThread1, 128);
+static msg_t Thread1(void *arg) {
+
+ (void)arg;
+ chRegSetThreadName("blinker");
+ while (TRUE) {
+ palClearPad(GPIOD, GPIOD_LED6);
+ chThdSleepMilliseconds(500);
+ palSetPad(GPIOD, GPIOD_LED6);
+ chThdSleepMilliseconds(500);
+ }
+}
+
+/*
+ * Application entry point.
+ */
+int main(void) {
+ Thread *shelltp = NULL;
+
+ /*
+ * System initializations.
+ * - HAL initialization, this also initializes the configured device drivers
+ * and performs the board-specific initializations.
+ * - Kernel initialization, the main() function becomes a thread and the
+ * RTOS is active.
+ */
+ halInit();
+ chSysInit();
+
+ /*
+ * Activates the USB driver and then the USB bus pull-up on D+.
+ */
+ sduObjectInit(&SDU1);
+ sduStart(&SDU1, &serusbcfg);
+ usbDisconnectBus(serusbcfg.usbp);
+ chThdSleepMilliseconds(100);
+ usbConnectBus(serusbcfg.usbp);
+
+ /*
+ * Shell manager initialization.
+ */
+ shellInit();
+
+ /*
+ * Creates the blinker thread.
+ */
+ chThdCreateStatic(waThread1, sizeof(waThread1), NORMALPRIO, Thread1, NULL);
+
+ /*
+ * Normal main() thread activity, in this demo it does nothing except
+ * sleeping in a loop and check the button state.
+ */
+ while (TRUE) {
+ if (!shelltp && (SDU1.config->usbp->state == USB_ACTIVE))
+ shelltp = shellCreate(&shell_cfg1, SHELL_WA_SIZE, NORMALPRIO);
+ else if (chThdTerminated(shelltp)) {
+ chThdRelease(shelltp); /* Recovers memory of the previous shell. */
+ shelltp = NULL; /* Triggers spawning of a new shell. */
+ }
+ chThdSleepMilliseconds(1000);
+ }
+}
diff --git a/testhal/STM32F4xx/USB_CDC/mcuconf.h b/testhal/STM32F4xx/USB_CDC/mcuconf.h new file mode 100644 index 000000000..4f1755c10 --- /dev/null +++ b/testhal/STM32F4xx/USB_CDC/mcuconf.h @@ -0,0 +1,234 @@ +/*
+ ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
+ 2011,2012 Giovanni Di Sirio.
+
+ This file is part of ChibiOS/RT.
+
+ ChibiOS/RT is free software; you can redistribute it and/or modify
+ it under the terms of the GNU General Public License as published by
+ the Free Software Foundation; either version 3 of the License, or
+ (at your option) any later version.
+
+ ChibiOS/RT is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ GNU General Public License for more details.
+
+ You should have received a copy of the GNU General Public License
+ along with this program. If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/*
+ * STM32F4xx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 15...0 Lowest...Highest.
+ *
+ * DMA priorities:
+ * 0...3 Lowest...Highest.
+ */
+
+/*
+ * HAL driver system settings.
+ */
+#define STM32_NO_INIT FALSE
+#define STM32_HSI_ENABLED TRUE
+#define STM32_LSI_ENABLED TRUE
+#define STM32_HSE_ENABLED TRUE
+#define STM32_LSE_ENABLED FALSE
+#define STM32_CLOCK48_REQUIRED TRUE
+#define STM32_SW STM32_SW_PLL
+#define STM32_PLLSRC STM32_PLLSRC_HSE
+#define STM32_PLLM_VALUE 8
+#define STM32_PLLN_VALUE 336
+#define STM32_PLLP_VALUE 2
+#define STM32_PLLQ_VALUE 7
+#define STM32_HPRE STM32_HPRE_DIV1
+#define STM32_PPRE1 STM32_PPRE1_DIV4
+#define STM32_PPRE2 STM32_PPRE2_DIV2
+#define STM32_RTCSEL STM32_RTCSEL_LSI
+#define STM32_RTCPRE_VALUE 8
+#define STM32_MCO1SEL STM32_MCO1SEL_HSI
+#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
+#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
+#define STM32_MCO2PRE STM32_MCO2PRE_DIV5
+#define STM32_I2SSRC STM32_I2SSRC_CKIN
+#define STM32_PLLI2SN_VALUE 192
+#define STM32_PLLI2SR_VALUE 5
+#define STM32_VOS STM32_VOS_HIGH
+#define STM32_PVD_ENABLE FALSE
+#define STM32_PLS STM32_PLS_LEV0
+
+/*
+ * ADC driver system settings.
+ */
+#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
+#define STM32_ADC_USE_ADC1 TRUE
+#define STM32_ADC_USE_ADC2 TRUE
+#define STM32_ADC_USE_ADC3 TRUE
+#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
+#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
+#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
+#define STM32_ADC_ADC1_DMA_PRIORITY 2
+#define STM32_ADC_ADC2_DMA_PRIORITY 2
+#define STM32_ADC_ADC3_DMA_PRIORITY 2
+#define STM32_ADC_IRQ_PRIORITY 5
+#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 5
+
+/*
+ * CAN driver system settings.
+ */
+#define STM32_CAN_USE_CAN1 TRUE
+#define STM32_CAN_CAN1_IRQ_PRIORITY 11
+
+/*
+ * EXT driver system settings.
+ */
+#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI17_IRQ_PRIORITY 15
+#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
+#define STM32_EXT_EXTI21_IRQ_PRIORITY 15
+#define STM32_EXT_EXTI22_IRQ_PRIORITY 15
+
+/*
+ * GPT driver system settings.
+ */
+#define STM32_GPT_USE_TIM1 TRUE
+#define STM32_GPT_USE_TIM2 TRUE
+#define STM32_GPT_USE_TIM3 TRUE
+#define STM32_GPT_USE_TIM4 TRUE
+#define STM32_GPT_USE_TIM5 TRUE
+#define STM32_GPT_USE_TIM8 TRUE
+#define STM32_GPT_TIM1_IRQ_PRIORITY 7
+#define STM32_GPT_TIM2_IRQ_PRIORITY 7
+#define STM32_GPT_TIM3_IRQ_PRIORITY 7
+#define STM32_GPT_TIM4_IRQ_PRIORITY 7
+#define STM32_GPT_TIM5_IRQ_PRIORITY 7
+#define STM32_GPT_TIM8_IRQ_PRIORITY 7
+
+/*
+ * ICU driver system settings.
+ */
+#define STM32_ICU_USE_TIM1 FALSE
+#define STM32_ICU_USE_TIM2 FALSE
+#define STM32_ICU_USE_TIM3 FALSE
+#define STM32_ICU_USE_TIM4 FALSE
+#define STM32_ICU_USE_TIM5 FALSE
+#define STM32_ICU_USE_TIM8 FALSE
+#define STM32_ICU_TIM1_IRQ_PRIORITY 7
+#define STM32_ICU_TIM2_IRQ_PRIORITY 7
+#define STM32_ICU_TIM3_IRQ_PRIORITY 7
+#define STM32_ICU_TIM4_IRQ_PRIORITY 7
+#define STM32_ICU_TIM5_IRQ_PRIORITY 7
+#define STM32_ICU_TIM8_IRQ_PRIORITY 7
+
+/*
+ * PWM driver system settings.
+ */
+#define STM32_PWM_USE_ADVANCED FALSE
+#define STM32_PWM_USE_TIM1 FALSE
+#define STM32_PWM_USE_TIM2 FALSE
+#define STM32_PWM_USE_TIM3 FALSE
+#define STM32_PWM_USE_TIM4 FALSE
+#define STM32_PWM_USE_TIM5 FALSE
+#define STM32_PWM_USE_TIM8 FALSE
+#define STM32_PWM_TIM1_IRQ_PRIORITY 7
+#define STM32_PWM_TIM2_IRQ_PRIORITY 7
+#define STM32_PWM_TIM3_IRQ_PRIORITY 7
+#define STM32_PWM_TIM4_IRQ_PRIORITY 7
+#define STM32_PWM_TIM5_IRQ_PRIORITY 7
+#define STM32_PWM_TIM8_IRQ_PRIORITY 7
+
+/*
+ * SERIAL driver system settings.
+ */
+#define STM32_SERIAL_USE_USART1 FALSE
+#define STM32_SERIAL_USE_USART2 TRUE
+#define STM32_SERIAL_USE_USART3 FALSE
+#define STM32_SERIAL_USE_UART4 FALSE
+#define STM32_SERIAL_USE_UART5 FALSE
+#define STM32_SERIAL_USE_USART6 FALSE
+#define STM32_SERIAL_USART1_PRIORITY 12
+#define STM32_SERIAL_USART2_PRIORITY 12
+#define STM32_SERIAL_USART3_PRIORITY 12
+#define STM32_SERIAL_UART4_PRIORITY 12
+#define STM32_SERIAL_UART5_PRIORITY 12
+#define STM32_SERIAL_USART6_PRIORITY 12
+
+/*
+ * SPI driver system settings.
+ */
+#define STM32_SPI_USE_SPI1 TRUE
+#define STM32_SPI_USE_SPI2 TRUE
+#define STM32_SPI_USE_SPI3 TRUE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_SPI_SPI1_DMA_PRIORITY 1
+#define STM32_SPI_SPI2_DMA_PRIORITY 1
+#define STM32_SPI_SPI3_DMA_PRIORITY 1
+#define STM32_SPI_SPI1_IRQ_PRIORITY 10
+#define STM32_SPI_SPI2_IRQ_PRIORITY 10
+#define STM32_SPI_SPI3_IRQ_PRIORITY 10
+#define STM32_SPI_DMA_ERROR_HOOK(spip) chSysHalt()
+
+/*
+ * UART driver system settings.
+ */
+#define STM32_UART_USE_USART1 FALSE
+#define STM32_UART_USE_USART2 TRUE
+#define STM32_UART_USE_USART3 FALSE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
+#define STM32_UART_USART1_IRQ_PRIORITY 12
+#define STM32_UART_USART2_IRQ_PRIORITY 12
+#define STM32_UART_USART3_IRQ_PRIORITY 12
+#define STM32_UART_USART1_DMA_PRIORITY 0
+#define STM32_UART_USART2_DMA_PRIORITY 0
+#define STM32_UART_USART3_DMA_PRIORITY 0
+#define STM32_UART_DMA_ERROR_HOOK(uartp) chSysHalt()
+
+/*
+ * I2C driver system settings.
+ */
+#define STM32_I2C_USE_I2C1 FALSE
+#define STM32_I2C_USE_I2C2 FALSE
+#define STM32_I2C_USE_I2C3 FALSE
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
+#define STM32_I2C_I2C1_IRQ_PRIORITY 6
+#define STM32_I2C_I2C2_IRQ_PRIORITY 6
+#define STM32_I2C_I2C3_IRQ_PRIORITY 6
+#define STM32_I2C_I2C1_DMA_PRIORITY 1
+#define STM32_I2C_I2C2_DMA_PRIORITY 1
+#define STM32_I2C_I2C3_DMA_PRIORITY 1
+#define STM32_I2C_I2C1_DMA_ERROR_HOOK() chSysHalt()
+#define STM32_I2C_I2C2_DMA_ERROR_HOOK() chSysHalt()
+#define STM32_I2C_I2C3_DMA_ERROR_HOOK() chSysHalt()
+
diff --git a/testhal/STM32L1xx/ADC/chconf.h b/testhal/STM32L1xx/ADC/chconf.h index c0181fef5..290044421 100644 --- a/testhal/STM32L1xx/ADC/chconf.h +++ b/testhal/STM32L1xx/ADC/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM32L1xx/ADC/halconf.h b/testhal/STM32L1xx/ADC/halconf.h index 2c6d2beaf..545241783 100644 --- a/testhal/STM32L1xx/ADC/halconf.h +++ b/testhal/STM32L1xx/ADC/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/STM32L1xx/EXT/chconf.h b/testhal/STM32L1xx/EXT/chconf.h index c0181fef5..290044421 100644 --- a/testhal/STM32L1xx/EXT/chconf.h +++ b/testhal/STM32L1xx/EXT/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM32L1xx/EXT/halconf.h b/testhal/STM32L1xx/EXT/halconf.h index f583f94e6..5a1e5c050 100644 --- a/testhal/STM32L1xx/EXT/halconf.h +++ b/testhal/STM32L1xx/EXT/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/STM32L1xx/GPT/chconf.h b/testhal/STM32L1xx/GPT/chconf.h index c0181fef5..290044421 100644 --- a/testhal/STM32L1xx/GPT/chconf.h +++ b/testhal/STM32L1xx/GPT/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM32L1xx/GPT/halconf.h b/testhal/STM32L1xx/GPT/halconf.h index 1b9896157..ad048e08f 100644 --- a/testhal/STM32L1xx/GPT/halconf.h +++ b/testhal/STM32L1xx/GPT/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/STM32L1xx/GPT/main.c b/testhal/STM32L1xx/GPT/main.c index ea48f2545..e263c4813 100644 --- a/testhal/STM32L1xx/GPT/main.c +++ b/testhal/STM32L1xx/GPT/main.c @@ -46,7 +46,7 @@ static void gpt3cb(GPTDriver *gptp) { * GPT2 configuration.
*/
static const GPTConfig gpt2cfg = {
- 10000, /* 10KHz timer clock.*/
+ 10000, /* 10kHz timer clock.*/
gpt2cb /* Timer callback.*/
};
@@ -54,7 +54,7 @@ static const GPTConfig gpt2cfg = { * GPT3 configuration.
*/
static const GPTConfig gpt3cfg = {
- 10000, /* 10KHz timer clock.*/
+ 10000, /* 10kHz timer clock.*/
gpt3cb /* Timer callback.*/
};
diff --git a/testhal/STM32L1xx/IRQ_STORM/chconf.h b/testhal/STM32L1xx/IRQ_STORM/chconf.h index 4115636d6..b1f2cd62c 100644 --- a/testhal/STM32L1xx/IRQ_STORM/chconf.h +++ b/testhal/STM32L1xx/IRQ_STORM/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM32L1xx/IRQ_STORM/halconf.h b/testhal/STM32L1xx/IRQ_STORM/halconf.h index 1ad8f74ce..4e5a16796 100644 --- a/testhal/STM32L1xx/IRQ_STORM/halconf.h +++ b/testhal/STM32L1xx/IRQ_STORM/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/STM32L1xx/PVD/chconf.h b/testhal/STM32L1xx/PVD/chconf.h index c0181fef5..290044421 100644 --- a/testhal/STM32L1xx/PVD/chconf.h +++ b/testhal/STM32L1xx/PVD/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM32L1xx/PVD/halconf.h b/testhal/STM32L1xx/PVD/halconf.h index f583f94e6..5a1e5c050 100644 --- a/testhal/STM32L1xx/PVD/halconf.h +++ b/testhal/STM32L1xx/PVD/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/STM32L1xx/PWM-ICU/chconf.h b/testhal/STM32L1xx/PWM-ICU/chconf.h index c0181fef5..290044421 100644 --- a/testhal/STM32L1xx/PWM-ICU/chconf.h +++ b/testhal/STM32L1xx/PWM-ICU/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM32L1xx/PWM-ICU/halconf.h b/testhal/STM32L1xx/PWM-ICU/halconf.h index 539b810db..9e7b5b6fe 100644 --- a/testhal/STM32L1xx/PWM-ICU/halconf.h +++ b/testhal/STM32L1xx/PWM-ICU/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/STM32L1xx/PWM-ICU/main.c b/testhal/STM32L1xx/PWM-ICU/main.c index 22d31a379..c4fddb65f 100644 --- a/testhal/STM32L1xx/PWM-ICU/main.c +++ b/testhal/STM32L1xx/PWM-ICU/main.c @@ -34,7 +34,7 @@ static void pwmc1cb(PWMDriver *pwmp) { }
static PWMConfig pwmcfg = {
- 10000, /* 10KHz PWM clock frequency. */
+ 10000, /* 10kHz PWM clock frequency. */
10000, /* Initial PWM period 1S. */
pwmpcb,
{
@@ -51,20 +51,22 @@ icucnt_t last_width, last_period; static void icuwidthcb(ICUDriver *icup) {
palSetPad(GPIOB, GPIOB_LED3);
- last_width = icuGetWidthI(icup);
+ last_width = icuGetWidth(icup);
}
static void icuperiodcb(ICUDriver *icup) {
palClearPad(GPIOB, GPIOB_LED3);
- last_period = icuGetPeriodI(icup);
+ last_period = icuGetPeriod(icup);
}
static ICUConfig icucfg = {
ICU_INPUT_ACTIVE_HIGH,
- 10000, /* 10KHz ICU clock frequency. */
+ 10000, /* 10kHz ICU clock frequency. */
icuwidthcb,
- icuperiodcb
+ icuperiodcb,
+ NULL,
+ ICU_CHANNEL_1
};
/*
diff --git a/testhal/STM32L1xx/SPI/chconf.h b/testhal/STM32L1xx/SPI/chconf.h index c0181fef5..290044421 100644 --- a/testhal/STM32L1xx/SPI/chconf.h +++ b/testhal/STM32L1xx/SPI/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM32L1xx/SPI/halconf.h b/testhal/STM32L1xx/SPI/halconf.h index 84a220f12..d176ad1a7 100644 --- a/testhal/STM32L1xx/SPI/halconf.h +++ b/testhal/STM32L1xx/SPI/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/STM32L1xx/SPI/main.c b/testhal/STM32L1xx/SPI/main.c index b466b9819..e9fed979a 100644 --- a/testhal/STM32L1xx/SPI/main.c +++ b/testhal/STM32L1xx/SPI/main.c @@ -32,7 +32,7 @@ static const SPIConfig hs_spicfg = { };
/*
- * Low speed SPI configuration (256KHz, CPHA=0, CPOL=0, MSb first).
+ * Low speed SPI configuration (256kHz, CPHA=0, CPOL=0, MSb first).
*/
static const SPIConfig ls_spicfg = {
NULL,
diff --git a/testhal/STM32L1xx/UART/chconf.h b/testhal/STM32L1xx/UART/chconf.h index c0181fef5..290044421 100644 --- a/testhal/STM32L1xx/UART/chconf.h +++ b/testhal/STM32L1xx/UART/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM32L1xx/UART/halconf.h b/testhal/STM32L1xx/UART/halconf.h index 5f667087c..60af9dec0 100644 --- a/testhal/STM32L1xx/UART/halconf.h +++ b/testhal/STM32L1xx/UART/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
diff --git a/testhal/STM8S/SPI/demo/chconf.h b/testhal/STM8S/SPI/demo/chconf.h index 4115636d6..b1f2cd62c 100644 --- a/testhal/STM8S/SPI/demo/chconf.h +++ b/testhal/STM8S/SPI/demo/chconf.h @@ -459,7 +459,7 @@ * @brief Threads initialization hook.
* @details User initialization code added to the @p chThdInit() API.
*
- * @note It is invoked from within @p chThdInit() and implicitily from all
+ * @note It is invoked from within @p chThdInit() and implicitly from all
* the threads creation APIs.
*/
#if !defined(THREAD_EXT_INIT_HOOK) || defined(__DOXYGEN__)
diff --git a/testhal/STM8S/SPI/demo/halconf.h b/testhal/STM8S/SPI/demo/halconf.h index 80a557d8d..f70fd1b9d 100644 --- a/testhal/STM8S/SPI/demo/halconf.h +++ b/testhal/STM8S/SPI/demo/halconf.h @@ -268,7 +268,7 @@ /**
* @brief Number of initialization attempts before rejecting the card.
- * @note Attempts are performed at 10mS intevals.
+ * @note Attempts are performed at 10mS intervals.
*/
#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__)
#define SDC_INIT_RETRY 100
@@ -6,10 +6,10 @@ X = In progress, some work done. N = Decided against.
Version 2.4.1
+* MAC driver for STM32F107, STM32F2xx, STM32F4xx.
X STM32F2 validation (so far testing done on STM32F4 only).
X Revision of the RTCv2 driver implementation.
X SDC driver port to STM32F2 and STM32F4.
-X MAC driver for STM32F107, STM32F2xx, STM32F4xx.
- CAN2 support and CAN driver test on STM32F2/F4.
Within 2.5.x:
@@ -18,7 +18,7 @@ Within 2.5.x: * Add normal API (not iclass) variants of the VT functions.
* MMC_SPI driver speedup.
- USB driver model revision.
-- STM32 OTG USB cell support for CL, F2, F4 devices.
+X STM32 OTG USB cell support for CL, F2, F4 devices.
- Add option to use another counter instead of the systick counter into the
trace buffer.
- Add a chSysIntegrityCheck() API to the kernel.
|