git-svn-id: svn://svn.code.sf.net/p/chibios/svn/trunk@8602 35acf78f-673a-0410-8e92-d51de3d6d3f4

1 files changed, 45 insertions, 17 deletions

diff --git a/os/ext/CMSIS/ST/STM32F4xx/stm32f401xe.h b/os/ext/CMSIS/ST/STM32F4xx/stm32f401xe.h
index f6dc4af1f..d8ac4fd22 100644
--- a/os/ext/CMSIS/ST/STM32F4xx/stm32f401xe.h
+++ b/os/ext/CMSIS/ST/STM32F4xx/stm32f401xe.h
@@ -2,8 +2,8 @@
   ******************************************************************************

   * @file    stm32f401xe.h

   * @author  MCD Application Team

-  * @version V2.1.0

-  * @date    19-June-2014

+  * @version V2.4.2

+  * @date    13-November-2015

   * @brief   CMSIS STM32F401xExx Device Peripheral Access Layer Header File. 

   *

   *          This file contains:

@@ -14,7 +14,7 @@
   ******************************************************************************

   * @attention

   *

-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>

+  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>

   *

   * Redistribution and use in source and binary forms, with or without modification,

   * are permitted provided that the following conditions are met:

@@ -290,8 +290,7 @@ typedef struct
   __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */

   __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */

   __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */

-  __IO uint16_t BSRRL;    /*!< GPIO port bit set/reset low register,  Address offset: 0x18      */

-  __IO uint16_t BSRRH;    /*!< GPIO port bit set/reset high register, Address offset: 0x1A      */

+  __IO uint32_t BSRR;     /*!< GPIO port bit set/reset register,      Address offset: 0x18      */

   __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */

   __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x20-0x24 */

 } GPIO_TypeDef;

@@ -666,15 +665,12 @@ USB_OTG_HostChannelTypeDef;
 #define CCMDATARAM_BASE       ((uint32_t)0x10000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the alias region  */

 #define SRAM1_BASE            ((uint32_t)0x20000000) /*!< SRAM1(112 KB) base address in the alias region                             */

 #define SRAM2_BASE            ((uint32_t)0x2001C000) /*!< SRAM2(16 KB) base address in the alias region                              */

-#define SRAM3_BASE            ((uint32_t)0x20020000) /*!< SRAM3(64 KB) base address in the alias region                              */

 #define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region                                */

 #define BKPSRAM_BASE          ((uint32_t)0x40024000) /*!< Backup SRAM(4 KB) base address in the alias region                         */

-#define CCMDATARAM_BB_BASE    ((uint32_t)0x12000000) /*!< CCM(core coupled memory) data RAM(64 KB) base address in the bit-band region  */

 #define SRAM1_BB_BASE         ((uint32_t)0x22000000) /*!< SRAM1(112 KB) base address in the bit-band region                             */

-#define SRAM2_BB_BASE         ((uint32_t)0x2201C000) /*!< SRAM2(16 KB) base address in the bit-band region                              */

-#define SRAM3_BB_BASE         ((uint32_t)0x22020000) /*!< SRAM3(64 KB) base address in the bit-band region                              */

+#define SRAM2_BB_BASE         ((uint32_t)0x22380000) /*!< SRAM2(16 KB) base address in the bit-band region                              */

 #define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region                                */

-#define BKPSRAM_BB_BASE       ((uint32_t)0x42024000) /*!< Backup SRAM(4 KB) base address in the bit-band region                         */

+#define BKPSRAM_BB_BASE       ((uint32_t)0x42480000) /*!< Backup SRAM(4 KB) base address in the bit-band region                         */

 #define FLASH_END             ((uint32_t)0x0807FFFF) /*!< FLASH end address */

 

 /* Legacy defines */

@@ -1423,6 +1419,9 @@ USB_OTG_HostChannelTypeDef;
 #define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */

 #define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */

 #define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */

+#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000)        /*!< Interrupt Mask on line 20 */

+#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000)        /*!< Interrupt Mask on line 21 */

+#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000)        /*!< Interrupt Mask on line 22 */

 

 /*******************  Bit definition for EXTI_EMR register  *******************/

 #define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */

@@ -1445,6 +1444,9 @@ USB_OTG_HostChannelTypeDef;
 #define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */

 #define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */

 #define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */

+#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000)        /*!< Event Mask on line 20 */

+#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000)        /*!< Event Mask on line 21 */

+#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000)        /*!< Event Mask on line 22 */

 

 /******************  Bit definition for EXTI_RTSR register  *******************/

 #define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */

@@ -1467,6 +1469,9 @@ USB_OTG_HostChannelTypeDef;
 #define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */

 #define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */

 #define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */

+#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000)        /*!< Rising trigger event configuration bit of line 20 */

+#define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000)        /*!< Rising trigger event configuration bit of line 21 */

+#define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000)        /*!< Rising trigger event configuration bit of line 22 */

 

 /******************  Bit definition for EXTI_FTSR register  *******************/

 #define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */

@@ -1489,6 +1494,9 @@ USB_OTG_HostChannelTypeDef;
 #define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */

 #define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */

 #define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */

+#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000)        /*!< Falling trigger event configuration bit of line 20 */

+#define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000)        /*!< Falling trigger event configuration bit of line 21 */

+#define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000)        /*!< Falling trigger event configuration bit of line 22 */

 

 /******************  Bit definition for EXTI_SWIER register  ******************/

 #define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */

@@ -1511,6 +1519,9 @@ USB_OTG_HostChannelTypeDef;
 #define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */

 #define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */

 #define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */

+#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000)        /*!< Software Interrupt on line 20 */

+#define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000)        /*!< Software Interrupt on line 21 */

+#define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000)        /*!< Software Interrupt on line 22 */

 

 /*******************  Bit definition for EXTI_PR register  ********************/

 #define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit for line 0 */

@@ -1533,6 +1544,9 @@ USB_OTG_HostChannelTypeDef;
 #define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit for line 17 */

 #define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit for line 18 */

 #define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit for line 19 */

+#define  EXTI_PR_PR20                        ((uint32_t)0x00100000)        /*!< Pending bit for line 20 */

+#define  EXTI_PR_PR21                        ((uint32_t)0x00200000)        /*!< Pending bit for line 21 */

+#define  EXTI_PR_PR22                        ((uint32_t)0x00400000)        /*!< Pending bit for line 22 */

 

 /******************************************************************************/

 /*                                                                            */

@@ -2430,7 +2444,6 @@ USB_OTG_HostChannelTypeDef;
 #define  RCC_AHB1LPENR_SRAM1LPEN             ((uint32_t)0x00010000)

 #define  RCC_AHB1LPENR_SRAM2LPEN             ((uint32_t)0x00020000)

 #define  RCC_AHB1LPENR_BKPSRAMLPEN           ((uint32_t)0x00040000)

-#define  RCC_AHB1LPENR_SRAM3LPEN             ((uint32_t)0x00080000)

 #define  RCC_AHB1LPENR_DMA1LPEN              ((uint32_t)0x00200000)

 #define  RCC_AHB1LPENR_DMA2LPEN              ((uint32_t)0x00400000)

 

@@ -2626,7 +2639,7 @@ USB_OTG_HostChannelTypeDef;
 

 /********************  Bits definition for RTC_PRER register  *****************/

 #define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)

-#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00001FFF)

+#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFF)

 

 /********************  Bits definition for RTC_WUTR register  *****************/

 #define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)

@@ -4511,14 +4524,14 @@ USB_OTG_HostChannelTypeDef;
                                        ((INSTANCE) == I2C3))

 

 /******************************** I2S Instances *******************************/

-#define IS_I2S_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \

+#define IS_I2S_ALL_INSTANCE(INSTANCE)  (((INSTANCE) == SPI2) || \

                                     ((INSTANCE) == SPI3))

 

 /*************************** I2S Extended Instances ***************************/

-#define IS_I2S_INSTANCE_EXT(PERIPH)  (((INSTANCE) == SPI2)    || \

-                                      ((INSTANCE) == SPI3)    || \

-                                      ((INSTANCE) == I2S2ext) || \

-                                      ((INSTANCE) == I2S3ext))

+#define IS_I2S_ALL_INSTANCE_EXT(PERIPH)  (((INSTANCE) == SPI2)    || \

+                                          ((INSTANCE) == SPI3)    || \

+                                          ((INSTANCE) == I2S2ext) || \

+                                          ((INSTANCE) == I2S3ext))

 

 /****************************** RTC Instances *********************************/

 #define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)

@@ -4722,12 +4735,27 @@ USB_OTG_HostChannelTypeDef;
                                     ((INSTANCE) == USART2) || \

                                     ((INSTANCE) == USART6))     

 

+

+/*********************** PCD Instances ****************************************/

+#define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))

+

+/*********************** HCD Instances ****************************************/

+#define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS))

+

 /****************************** IWDG Instances ********************************/

 #define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)

 

 /****************************** WWDG Instances ********************************/

 #define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)

 

+/****************************** SDIO Instances ********************************/

+#define IS_SDIO_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SDIO)

+

+/****************************** USB Exported Constants ************************/

+#define USB_OTG_FS_HOST_MAX_CHANNEL_NBR                8

+#define USB_OTG_FS_MAX_IN_ENDPOINTS                    4    /* Including EP0 */

+#define USB_OTG_FS_MAX_OUT_ENDPOINTS                   4    /* Including EP0 */

+#define USB_OTG_FS_TOTAL_FIFO_SIZE                     1280 /* in Bytes */

 

 /**

   * @}