/* ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License. */ /* Concepts and parts of this file have been contributed by Fabio Utzig and Xo Wang. */ /* Rewritten by Emil Fresk (1/5 - 2014) for extended input capture functionality. And fix for spurious callbacks in the interrupt handler. */ /* * Hardware Abstraction Layer for Extended Input Capture Unit */ #include "hal.h" #if HAL_USE_EICU || defined(__DOXYGEN__) /*===========================================================================*/ /* Driver local definitions. */ /*===========================================================================*/ /** * @brief Inverts the polarity for the given channel. * * @param[in] eicup Pointer to the EICUDriver object. * @param[in] channel The timer channel to invert. * * @notapi */ #define eicu_lld_invert_polarity(eicup, channel) \ (eicup)->tim->CCER ^= ((uint16_t)(STM32_TIM_CCER_CC1P << ((channel) * 4))) /*===========================================================================*/ /* Driver exported variables. */ /*===========================================================================*/ /** * @brief EICUD1 driver identifier. * @note The driver EICUD1 allocates the complex timer TIM1 when enabled. */ #if STM32_EICU_USE_TIM1 && !defined(__DOXYGEN__) EICUDriver EICUD1; #endif /** * @brief EICUD2 driver identifier. * @note The driver EICUD2 allocates the timer TIM2 when enabled. */ #if STM32_EICU_USE_TIM2 && !defined(__DOXYGEN__) EICUDriver EICUD2; #endif /** * @brief EICUD3 driver identifier. * @note The driver EICUD3 allocates the timer TIM3 when enabled. */ #if STM32_EICU_USE_TIM3 && !defined(__DOXYGEN__) EICUDriver EICUD3; #endif /** * @brief EICUD4 driver identifier. * @note The driver EICUD4 allocates the timer TIM4 when enabled. */ #if STM32_EICU_USE_TIM4 && !defined(__DOXYGEN__) EICUDriver EICUD4; #endif /** * @brief EICUD5 driver identifier. * @note The driver EICUD5 allocates the timer TIM5 when enabled. */ #if STM32_EICU_USE_TIM5 && !defined(__DOXYGEN__) EICUDriver EICUD5; #endif /** * @brief EICUD8 driver identifier. * @note The driver EICUD8 allocates the timer TIM8 when enabled. */ #if STM32_EICU_USE_TIM8 && !defined(__DOXYGEN__) EICUDriver EICUD8; #endif /** * @brief EICUD9 driver identifier. * @note The driver EICUD9 allocates the timer TIM9 when enabled. */ #if STM32_EICU_USE_TIM9 && !defined(__DOXYGEN__) EICUDriver EICUD9; #endif /** * @brief EICUD12 driver identifier. * @note The driver EICUD12 allocates the timer TIM12 when enabled. */ #if STM32_EICU_USE_TIM12 && !defined(__DOXYGEN__) EICUDriver EICUD12; #endif /*===========================================================================*/ /* Driver local variables and types. */ /*===========================================================================*/ /*===========================================================================*/ /* Driver local functions. */ /*===========================================================================*/ /** * @brief Returns the time between latest 2 capture events. * @details The time is defined as number of ticks. * * @param[in] eicup Pointer to the EICUDriver object. * @param[in] channel The timer channel that fired the interrupt. * @return The number of ticks. * * @notapi */ static eicuresult_t eicu_lld_get_both(EICUDriver *eicup, eicuchannel_t channel, eicucnt_t compare) { const EICUChannelDriver *chp = &eicup->channel[channel]; eicuresult_t ret; /* Note! there is no overflow check because it handles under the hood of unsigned subtraction math.*/ /* 16-bit timer */ if (0xFFFF == eicup->tim->ARR) { uint16_t cmp = compare; uint16_t la = chp->last_active; uint16_t li = chp->last_idle; uint16_t w = li - la; uint16_t p = cmp - la; ret.width = w; ret.period = p; } /* 32-bit timer */ else if (0xFFFFFFFF == eicup->tim->ARR) { ret.width = chp->last_idle - chp->last_active; ret.period = compare - chp->last_active; return ret; } /* error trap */ else { osalSysHalt("ARR register must be loaded with maximum possible value"); } return ret; } /** * */ static eicucnt_t eicu_lld_get_width(EICUDriver *eicup, eicuchannel_t channel, eicucnt_t compare) { const EICUChannelDriver *chp = &eicup->channel[channel]; /* Note! there is no overflow check because it handles under the hood of unsigned subtraction math.*/ /* 16-bit timer */ if (0xFFFF == eicup->tim->ARR) { uint16_t cmp = compare; uint16_t la = chp->last_active; uint16_t ret = cmp - la; return ret; } /* 32-bit timer */ else if (0xFFFFFFFF == eicup->tim->ARR) { return compare - chp->last_active; } /* error trap */ else { osalSysHalt("ARR register must be loaded with maximum possible value"); return 0; } } /** * */ static eicucnt_t eicu_lld_get_period(EICUDriver *eicup, eicuchannel_t channel, eicucnt_t compare) { const EICUChannelDriver *chp = &eicup->channel[channel]; /* Note! there is no overflow check because it handles under the hood of unsigned subtraction math.*/ /* 16-bit timer */ if (0xFFFF == eicup->tim->ARR) { uint16_t cmp = compare; uint16_t li = chp->last_idle; uint16_t ret = cmp - li; return ret; } /* 32-bit timer */ else if (0xFFFFFFFF == eicup->tim->ARR) { return compare - chp->last_idle; } /* error trap */ else { osalSysHalt("ARR register must be loaded with maximum possible value"); return 0; } } /** * @brief EICU width or (width + period) event. * @note Needs special care since it needs to invert the * correct polarity bit to detect pulses. * @note Assumes that the polarity is not changed by some * external user. It must only be changed using the HAL. * * @param[in] eicup Pointer to the @p EICUDriver object * @param[in] channel The timer channel that fired the interrupt. * * @notapi */ static void isr_invoke_pulse_cb(EICUDriver *eicup, eicuchannel_t channel) { EICUChannelDriver *chp = &eicup->channel[channel]; eicucnt_t compare = eicu_lld_get_compare(chp); if (EICU_CH_ACTIVE == chp->state) { chp->state = EICU_CH_IDLE; eicu_lld_invert_polarity(eicup, channel); if (EICU_INPUT_PULSE == chp->config->mode) { uint32_t width = eicu_lld_get_width(eicup, channel, compare); chp->config->capture_cb(eicup, channel, width, 0); } chp->last_idle = compare; } else { chp->state = EICU_CH_ACTIVE; eicu_lld_invert_polarity(eicup, channel); if (EICU_INPUT_BOTH == chp->config->mode) { eicuresult_t both = eicu_lld_get_both(eicup, channel, compare); chp->config->capture_cb(eicup, channel, both.width, both.period); } chp->last_active = compare; } } /** * @brief EICU Edge detect event. * * @param[in] eicup Pointer to the @p EICUDriver object * @param[in] channel The timer channel that fired the interrupt. * * @notapi */ static void isr_invoke_edge_cb(EICUDriver *eicup, eicuchannel_t channel) { EICUChannelDriver *chp = &eicup->channel[channel]; eicucnt_t compare = eicu_lld_get_compare(chp); uint32_t period = eicu_lld_get_period(eicup, channel, compare); chp->config->capture_cb(eicup, channel, 0, period); chp->last_idle = compare; } /** * @brief Common ISR call. * * @param[in] eicup Pointer to the @p EICUDriver object * @param[in] channel The timer channel that fired the interrupt. * * @notapi */ static void eicu_isr_invoke_cb(EICUDriver *eicup, eicuchannel_t channel) { if (EICU_INPUT_EDGE == eicup->channel[channel].config->mode) isr_invoke_edge_cb(eicup, channel); else /* EICU_INPUT_PULSE || EICU_INPUT_BOTH */ isr_invoke_pulse_cb(eicup, channel); } /** * */ static void slow_mode_isr_handler(EICUDriver *eicup, uint16_t sr) { if ((sr & STM32_TIM_SR_CC1IF) != 0) eicu_isr_invoke_cb(eicup, EICU_CHANNEL_1); if ((sr & STM32_TIM_SR_CC2IF) != 0) eicu_isr_invoke_cb(eicup, EICU_CHANNEL_2); if ((sr & STM32_TIM_SR_CC3IF) != 0) eicu_isr_invoke_cb(eicup, EICU_CHANNEL_3); if ((sr & STM32_TIM_SR_CC4IF) != 0) eicu_isr_invoke_cb(eicup, EICU_CHANNEL_4); } /** * */ static void fast_mode_handler(EICUDriver *eicup, uint16_t sr) { if (eicup->config->iccfgp[0] != NULL) { if ((sr & STM32_TIM_SR_CC1IF) != 0) _eicu_isr_invoke_pwm_period_cb(eicup,EICU_CHANNEL_1); if ((sr & STM32_TIM_SR_CC2IF) != 0) _eicu_isr_invoke_pwm_width_cb(eicup, EICU_CHANNEL_1); } else { if ((sr & STM32_TIM_SR_CC1IF) != 0) _eicu_isr_invoke_pwm_width_cb(eicup, EICU_CHANNEL_2); if ((sr & STM32_TIM_SR_CC2IF) != 0) _eicu_isr_invoke_pwm_period_cb(eicup,EICU_CHANNEL_2); } } /** * @brief Shared IRQ handler. * * @param[in] eicup Pointer to the @p EICUDriver object */ static void eicu_lld_serve_interrupt(EICUDriver *eicup) { uint16_t sr; sr = eicup->tim->SR; /* Pick out the interrupts we are interested in by using the interrupt enable bits as mask */ sr &= (eicup->tim->DIER & STM32_TIM_DIER_IRQ_MASK); /* Clear interrupts */ eicup->tim->SR = ~sr; if (EICU_FAST == eicup->config->mode) fast_mode_handler(eicup, sr); else slow_mode_isr_handler(eicup, sr); if ((sr & STM32_TIM_SR_UIF) != 0) _eicu_isr_invoke_overflow_cb(eicup); } static void eicu_lld_fast_start(EICUDriver *eicup) { (void)eicup; osalSysHalt("unrealized yet"); #if 0 if (eicup->config->iccfgp[0] != NULL) { /* Selected input 1. CCMR1_CC1S = 01 = CH1 Input on TI1. CCMR1_CC2S = 10 = CH2 Input on TI1.*/ eicup->tim->CCMR1 = STM32_TIM_CCMR1_CC1S(1) | STM32_TIM_CCMR1_CC2S(2); /* SMCR_TS = 101, input is TI1FP1. SMCR_SMS = 100, reset on rising edge.*/ eicup->tim->SMCR = STM32_TIM_SMCR_TS(5) | STM32_TIM_SMCR_SMS(4); /* The CCER settings depend on the selected trigger mode. EICU_INPUT_ACTIVE_HIGH: Active on rising edge, idle on falling edge. EICU_INPUT_ACTIVE_LOW: Active on falling edge, idle on rising edge. */ if (eicup->config->iccfgp[0]->alvl == EICU_INPUT_ACTIVE_HIGH) { eicup->tim->CCER = STM32_TIM_CCER_CC1E | STM32_TIM_CCER_CC2E | STM32_TIM_CCER_CC2P; } else { eicup->tim->CCER = STM32_TIM_CCER_CC1E | STM32_TIM_CCER_CC1P | STM32_TIM_CCER_CC2E; } /* Direct pointers to the capture registers in order to make reading data faster from within callbacks.*/ eicup->wccrp[0] = &eicup->tim->CCR[1]; eicup->pccrp = &eicup->tim->CCR[0]; } else { /* Selected input 2. CCMR1_CC1S = 10 = CH1 Input on TI2. CCMR1_CC2S = 01 = CH2 Input on TI2.*/ eicup->tim->CCMR1 = STM32_TIM_CCMR1_CC1S(2) | STM32_TIM_CCMR1_CC2S(1); /* SMCR_TS = 110, input is TI2FP2. SMCR_SMS = 100, reset on rising edge.*/ eicup->tim->SMCR = STM32_TIM_SMCR_TS(6) | STM32_TIM_SMCR_SMS(4); /* The CCER settings depend on the selected trigger mode. EICU_INPUT_ACTIVE_HIGH: Active on rising edge, idle on falling edge. EICU_INPUT_ACTIVE_LOW: Active on falling edge, idle on rising edge. */ if (eicup->config->iccfgp[1]->alvl == EICU_INPUT_ACTIVE_HIGH) { eicup->tim->CCER = STM32_TIM_CCER_CC1E | STM32_TIM_CCER_CC1P | STM32_TIM_CCER_CC2E; } else { eicup->tim->CCER = STM32_TIM_CCER_CC1E | STM32_TIM_CCER_CC2E | STM32_TIM_CCER_CC2P; } /* Direct pointers to the capture registers in order to make reading data faster from within callbacks.*/ eicup->wccrp[1] = &eicup->tim->CCR[0]; eicup->pccrp = &eicup->tim->CCR[1]; } #endif } static void eicu_lld_slow_start(EICUDriver *eicup) { /* Set each input channel that is used as: a normal input capture channel, link the corresponding CCR register and set polarity. */ /* Input capture channel 1 */ if (eicup->config->iccfgp[0] != NULL) { /* Normal capture input input */ eicup->tim->CCMR1 |= STM32_TIM_CCMR1_CC1S(1); /* Link CCR register */ eicup->channel[0].wccrp = &eicup->tim->CCR[0]; /* Set input polarity */ if (eicup->config->iccfgp[0]->alvl == EICU_INPUT_ACTIVE_HIGH) eicup->tim->CCER |= STM32_TIM_CCER_CC1E; else eicup->tim->CCER |= STM32_TIM_CCER_CC1E | STM32_TIM_CCER_CC1P; } /* Input capture channel 2 */ if (eicup->config->iccfgp[1] != NULL) { /* Normal capture input input */ eicup->tim->CCMR1 |= STM32_TIM_CCMR1_CC2S(1); /* Link CCR register */ eicup->channel[1].wccrp = &eicup->tim->CCR[1]; /* Set input polarity */ if (eicup->config->iccfgp[1]->alvl == EICU_INPUT_ACTIVE_HIGH) eicup->tim->CCER |= STM32_TIM_CCER_CC2E; else eicup->tim->CCER |= STM32_TIM_CCER_CC2E | STM32_TIM_CCER_CC2P; } /* Input capture channel 3 (not for TIM 9 and 12) */ if (eicup->config->iccfgp[2] != NULL) { /* Normal capture input input */ eicup->tim->CCMR2 |= STM32_TIM_CCMR2_CC3S(1); /* Link CCR register */ eicup->channel[2].wccrp = &eicup->tim->CCR[2]; /* Set input polarity */ if (eicup->config->iccfgp[2]->alvl == EICU_INPUT_ACTIVE_HIGH) eicup->tim->CCER |= STM32_TIM_CCER_CC3E; else eicup->tim->CCER |= STM32_TIM_CCER_CC3E | STM32_TIM_CCER_CC3P; } /* Input capture channel 4 (not for TIM 9 and 12) */ if (eicup->config->iccfgp[3] != NULL) { /* Normal capture input input */ eicup->tim->CCMR2 |= STM32_TIM_CCMR2_CC4S(1); /* Link CCR register */ eicup->channel[3].wccrp = &eicup->tim->CCR[3]; /* Set input polarity */ if (eicup->config->iccfgp[3]->alvl == EICU_INPUT_ACTIVE_HIGH) eicup->tim->CCER |= STM32_TIM_CCER_CC4E; else eicup->tim->CCER |= STM32_TIM_CCER_CC4E | STM32_TIM_CCER_CC4P; } } static void eicu_lld_enable_fast(EICUDriver *eicup) { (void)eicup; osalSysHalt("urealized"); #if 0 if (eicup->config->iccfgp[0] != NULL) { if (eicup->config->period_cb != NULL) eicup->tim->DIER |= STM32_TIM_DIER_CC1IE; if ((eicup->config->iccfgp[EICU_CHANNEL_1] != NULL) && (eicup->config->iccfgp[EICU_CHANNEL_1]->capture_cb != NULL)) eicup->tim->DIER |= STM32_TIM_DIER_CC2IE; } else { if ((eicup->config->iccfgp[EICU_CHANNEL_2] != NULL) && (eicup->config->iccfgp[EICU_CHANNEL_2]->capture_cb != NULL)) eicup->tim->DIER |= STM32_TIM_DIER_CC1IE; if (eicup->config->period_cb != NULL) eicup->tim->DIER |= STM32_TIM_DIER_CC2IE; } #endif } static void eicu_lld_enable_slow(EICUDriver *eicup) { if ((eicup->config->iccfgp[EICU_CHANNEL_1] != NULL) && (eicup->config->iccfgp[EICU_CHANNEL_1]->capture_cb != NULL)) eicup->tim->DIER |= STM32_TIM_DIER_CC1IE; if ((eicup->config->iccfgp[EICU_CHANNEL_2] != NULL) && (eicup->config->iccfgp[EICU_CHANNEL_2]->capture_cb != NULL)) eicup->tim->DIER |= STM32_TIM_DIER_CC2IE; if ((eicup->config->iccfgp[EICU_CHANNEL_3] != NULL) && (eicup->config->iccfgp[EICU_CHANNEL_3]->capture_cb != NULL)) eicup->tim->DIER |= STM32_TIM_DIER_CC3IE; if ((eicup->config->iccfgp[EICU_CHANNEL_4] != NULL) && (eicup->config->iccfgp[EICU_CHANNEL_4]->capture_cb != NULL)) eicup->tim->DIER |= STM32_TIM_DIER_CC4IE; } /*===========================================================================*/ /* Driver interrupt handlers. */ /*===========================================================================*/ #if STM32_EICU_USE_TIM1 #if !defined(STM32_TIM1_UP_HANDLER) #error "STM32_TIM1_UP_HANDLER not defined" #endif /** * @brief TIM1 compare interrupt handler. * @note It is assumed that the various sources are only activated if the * associated callback pointer is not equal to @p NULL in order to not * perform an extra check in a potentially critical interrupt handler. * * @isr */ OSAL_IRQ_HANDLER(STM32_TIM1_UP_HANDLER) { OSAL_IRQ_PROLOGUE(); eicu_lld_serve_interrupt(&EICUD1); OSAL_IRQ_EPILOGUE(); } #if !defined(STM32_TIM1_CC_HANDLER) #error "STM32_TIM1_CC_HANDLER not defined" #endif /** * @brief TIM1 compare interrupt handler. * @note It is assumed that the various sources are only activated if the * associated callback pointer is not equal to @p NULL in order to not * perform an extra check in a potentially critical interrupt handler. * * @isr */ OSAL_IRQ_HANDLER(STM32_TIM1_CC_HANDLER) { OSAL_IRQ_PROLOGUE(); eicu_lld_serve_interrupt(&EICUD1); OSAL_IRQ_EPILOGUE(); } #endif /* STM32_EICU_USE_TIM1 */ #if STM32_EICU_USE_TIM2 #if !defined(STM32_TIM2_HANDLER) #error "STM32_TIM2_HANDLER not defined" #endif /** * @brief TIM2 interrupt handler. * @note It is assumed that the various sources are only activated if the * associated callback pointer is not equal to @p NULL in order to not * perform an extra check in a potentially critical interrupt handler. * * @isr */ OSAL_IRQ_HANDLER(STM32_TIM2_HANDLER) { OSAL_IRQ_PROLOGUE(); eicu_lld_serve_interrupt(&EICUD2); OSAL_IRQ_EPILOGUE(); } #endif /* STM32_EICU_USE_TIM2 */ #if STM32_EICU_USE_TIM3 #if !defined(STM32_TIM3_HANDLER) #error "STM32_TIM3_HANDLER not defined" #endif /** * @brief TIM3 interrupt handler. * @note It is assumed that the various sources are only activated if the * associated callback pointer is not equal to @p NULL in order to not * perform an extra check in a potentially critical interrupt handler. * * @isr */ OSAL_IRQ_HANDLER(STM32_TIM3_HANDLER) { OSAL_IRQ_PROLOGUE(); eicu_lld_serve_interrupt(&EICUD3); OSAL_IRQ_EPILOGUE(); } #endif /* STM32_EICU_USE_TIM3 */ #if STM32_EICU_USE_TIM4 #if !defined(STM32_TIM4_HANDLER) #error "STM32_TIM4_HANDLER not defined" #endif /** * @brief TIM4 interrupt handler. * @note It is assumed that the various sources are only activated if the * associated callback pointer is not equal to @p NULL in order to not * perform an extra check in a potentially critical interrupt handler. * * @isr */ OSAL_IRQ_HANDLER(STM32_TIM4_HANDLER) { OSAL_IRQ_PROLOGUE(); eicu_lld_serve_interrupt(&EICUD4); OSAL_IRQ_EPILOGUE(); } #endif /* STM32_EICU_USE_TIM4 */ #if STM32_EICU_USE_TIM5 #if !defined(STM32_TIM5_HANDLER) #error "STM32_TIM5_HANDLER not defined" #endif /** * @brief TIM5 interrupt handler. * @note It is assumed that the various sources are only activated if the * associated callback pointer is not equal to @p NULL in order to not * perform an extra check in a potentially critical interrupt handler. * * @isr */ OSAL_IRQ_HANDLER(STM32_TIM5_HANDLER) { OSAL_IRQ_PROLOGUE(); eicu_lld_serve_interrupt(&EICUD5); OSAL_IRQ_EPILOGUE(); } #endif /* STM32_EICU_USE_TIM5 */ #if STM32_EICU_USE_TIM8 #if !defined(STM32_TIM8_UP_HANDLER) #error "STM32_TIM8_UP_HANDLER not defined" #endif /** * @brief TIM8 compare interrupt handler. * @note It is assumed that the various sources are only activated if the * associated callback pointer is not equal to @p NULL in order to not * perform an extra check in a potentially critical interrupt handler. * * @isr */ OSAL_IRQ_HANDLER(STM32_TIM8_UP_HANDLER) { OSAL_IRQ_PROLOGUE(); eicu_lld_serve_interrupt(&EICUD8); OSAL_IRQ_EPILOGUE(); } #if !defined(STM32_TIM8_CC_HANDLER) #error "STM32_TIM8_CC_HANDLER not defined" #endif /** * @brief TIM8 compare interrupt handler. * @note It is assumed that the various sources are only activated if the * associated callback pointer is not equal to @p NULL in order to not * perform an extra check in a potentially critical interrupt handler. * * @isr */ OSAL_IRQ_HANDLER(STM32_TIM8_CC_HANDLER) { OSAL_IRQ_PROLOGUE(); eicu_lld_serve_interrupt(&EICUD8); OSAL_IRQ_EPILOGUE(); } #endif /* STM32_EICU_USE_TIM8 */ #if STM32_EICU_USE_TIM9 #if !defined(STM32_TIM9_HANDLER) #error "STM32_TIM9_HANDLER not defined" #endif /** * @brief TIM9 interrupt handler. * @note It is assumed that the various sources are only activated if the * associated callback pointer is not equal to @p NULL in order to not * perform an extra check in a potentially critical interrupt handler. * * @isr */ OSAL_IRQ_HANDLER(STM32_TIM9_HANDLER) { OSAL_IRQ_PROLOGUE(); eicu_lld_serve_interrupt(&EICUD9); OSAL_IRQ_EPILOGUE(); } #endif /* STM32_EICU_USE_TIM9 */ #if STM32_EICU_USE_TIM12 #if !defined(STM32_TIM12_HANDLER) #error "STM32_TIM12_HANDLER not defined" #endif /** * @brief TIM12 interrupt handler. * @note It is assumed that the various sources are only activated if the * associated callback pointer is not equal to @p NULL in order to not * perform an extra check in a potentially critical interrupt handler. * * @isr */ OSAL_IRQ_HANDLER(STM32_TIM12_HANDLER) { OSAL_IRQ_PROLOGUE(); eicu_lld_serve_interrupt(&EICUD12); OSAL_IRQ_EPILOGUE(); } #endif /* STM32_EICU_USE_TIM12 */ /*===========================================================================*/ /* Driver exported functions. */ /*===========================================================================*/ /** * @brief Low level EICU driver initialization. * * @notapi */ void eicu_lld_init(void) { #if STM32_EICU_USE_TIM1 /* Driver initialization.*/ eicuObjectInit(&EICUD1); EICUD1.tim = STM32_TIM1; #endif #if STM32_EICU_USE_TIM2 /* Driver initialization.*/ eicuObjectInit(&EICUD2); EICUD2.tim = STM32_TIM2; #endif #if STM32_EICU_USE_TIM3 /* Driver initialization.*/ eicuObjectInit(&EICUD3); EICUD3.tim = STM32_TIM3; #endif #if STM32_EICU_USE_TIM4 /* Driver initialization.*/ eicuObjectInit(&EICUD4); EICUD4.tim = STM32_TIM4; #endif #if STM32_EICU_USE_TIM5 /* Driver initialization.*/ eicuObjectInit(&EICUD5); EICUD5.tim = STM32_TIM5; #endif #if STM32_EICU_USE_TIM8 /* Driver initialization.*/ eicuObjectInit(&EICUD8); EICUD8.tim = STM32_TIM8; #endif #if STM32_EICU_USE_TIM9 /* Driver initialization.*/ eicuObjectInit(&EICUD9); EICUD9.tim = STM32_TIM9; #endif #if STM32_EICU_USE_TIM12 /* Driver initialization.*/ eicuObjectInit(&EICUD12); EICUD12.tim = STM32_TIM12; #endif } /** * @brief Configures and activates the EICU peripheral. * * @param[in] eicup Pointer to the @p EICUDriver object * * @notapi */ void eicu_lld_start(EICUDriver *eicup) { uint32_t psc; size_t ch; osalDbgAssert((eicup->config->iccfgp[0] != NULL) || (eicup->config->iccfgp[1] != NULL) || (eicup->config->iccfgp[2] != NULL) || (eicup->config->iccfgp[3] != NULL), "invalid input configuration"); if (eicup->state == EICU_STOP) { /* Clock activation and timer reset.*/ #if STM32_EICU_USE_TIM1 if (&EICUD1 == eicup) { rccEnableTIM1(FALSE); rccResetTIM1(); nvicEnableVector(STM32_TIM1_UP_NUMBER, STM32_EICU_TIM1_IRQ_PRIORITY); nvicEnableVector(STM32_TIM1_CC_NUMBER, STM32_EICU_TIM1_IRQ_PRIORITY); #if defined(STM32_TIM1CLK) eicup->clock = STM32_TIM1CLK; #else eicup->clock = STM32_TIMCLK2; #endif } #endif #if STM32_EICU_USE_TIM2 if (&EICUD2 == eicup) { rccEnableTIM2(FALSE); rccResetTIM2(); nvicEnableVector(STM32_TIM2_NUMBER, STM32_EICU_TIM2_IRQ_PRIORITY); eicup->clock = STM32_TIMCLK1; } #endif #if STM32_EICU_USE_TIM3 if (&EICUD3 == eicup) { rccEnableTIM3(FALSE); rccResetTIM3(); nvicEnableVector(STM32_TIM3_NUMBER, STM32_EICU_TIM3_IRQ_PRIORITY); eicup->clock = STM32_TIMCLK1; } #endif #if STM32_EICU_USE_TIM4 if (&EICUD4 == eicup) { rccEnableTIM4(FALSE); rccResetTIM4(); nvicEnableVector(STM32_TIM4_NUMBER, STM32_EICU_TIM4_IRQ_PRIORITY); eicup->clock = STM32_TIMCLK1; } #endif #if STM32_EICU_USE_TIM5 if (&EICUD5 == eicup) { rccEnableTIM5(FALSE); rccResetTIM5(); nvicEnableVector(STM32_TIM5_NUMBER, STM32_EICU_TIM5_IRQ_PRIORITY); eicup->clock = STM32_TIMCLK1; } #endif #if STM32_EICU_USE_TIM8 if (&EICUD8 == eicup) { rccEnableTIM8(FALSE); rccResetTIM8(); nvicEnableVector(STM32_TIM8_UP_NUMBER, STM32_EICU_TIM8_IRQ_PRIORITY); nvicEnableVector(STM32_TIM8_CC_NUMBER, STM32_EICU_TIM8_IRQ_PRIORITY); #if defined(STM32_TIM8CLK) eicup->clock = STM32_TIM8CLK; #else eicup->clock = STM32_TIMCLK2; #endif } #endif #if STM32_EICU_USE_TIM9 if (&EICUD9 == eicup) { rccEnableTIM9(FALSE); rccResetTIM9(); nvicEnableVector(STM32_TIM9_NUMBER, STM32_EICU_TIM9_IRQ_PRIORITY); eicup->clock = STM32_TIMCLK2; } #endif #if STM32_EICU_USE_TIM12 if (&EICUD12 == eicup) { rccEnableTIM12(FALSE); rccResetTIM12(); nvicEnableVector(STM32_TIM12_NUMBER, STM32_EICU_TIM12_IRQ_PRIORITY); eicup->clock = STM32_TIMCLK1; } #endif } else { /* Driver re-configuration scenario, it must be stopped first.*/ eicup->tim->CR1 = 0; /* Timer disabled. */ eicup->tim->DIER = eicup->config->dier &/* DMA-related DIER settings. */ ~STM32_TIM_DIER_IRQ_MASK; eicup->tim->SR = 0; /* Clear eventual pending IRQs. */ eicup->tim->CCR[0] = 0; /* Comparator 1 disabled. */ eicup->tim->CCR[1] = 0; /* Comparator 2 disabled. */ eicup->tim->CNT = 0; /* Counter reset to zero. */ } /* Timer configuration.*/ psc = (eicup->clock / eicup->config->frequency) - 1; chDbgAssert((psc <= 0xFFFF) && ((psc + 1) * eicup->config->frequency) == eicup->clock, "invalid frequency"); eicup->tim->PSC = (uint16_t)psc; eicup->tim->ARR = (eicucnt_t)-1; /* Reset registers */ eicup->tim->SMCR = 0; eicup->tim->CCMR1 = 0; /* clean channel structures and set pointers to channel configs */ for (ch=0; chchannel[ch].last_active = 0; eicup->channel[ch].last_idle = 0; eicup->channel[ch].config = eicup->config->iccfgp[ch]; eicup->channel[ch].state = EICU_CH_IDLE; } #if STM32_EICU_USE_TIM9 && !STM32_EICU_USE_TIM12 if (eicup != &EICUD9) eicup->tim->CCMR2 = 0; #elif !STM32_EICU_USE_TIM9 && STM32_EICU_USE_TIM12 if (eicup != &EICUD12) eicup->tim->CCMR2 = 0; #elif STM32_EICU_USE_TIM9 && STM32_EICU_USE_TIM12 if ((eicup != &EICUD9) && (eicup != &EICUD12)) eicup->tim->CCMR2 = 0; #else eicup->tim->CCMR2 = 0; #endif /* TIM9 and TIM12 have only 2 channels.*/ #if STM32_EICU_USE_TIM9 if (eicup == &EICUD9) { osalDbgCheck((eicup->config->iccfgp[2] == NULL) && (eicup->config->iccfgp[3] == NULL)); } #endif #if STM32_EICU_USE_TIM12 if (eicup == &EICUD12) { osalDbgCheck((eicup->config->iccfgp[2] == NULL) && (eicup->config->iccfgp[3] == NULL)); } #endif if (eicup->config->mode == EICU_FAST) eicu_lld_fast_start(eicup); else eicu_lld_slow_start(eicup); } /** * @brief Deactivates the EICU peripheral. * * @param[in] eicup Pointer to the @p EICUDriver object * * @notapi */ void eicu_lld_stop(EICUDriver *eicup) { if (eicup->state == EICU_READY) { /* Clock deactivation.*/ eicup->tim->CR1 = 0; /* Timer disabled. */ eicup->tim->DIER = 0; /* All IRQs disabled. */ eicup->tim->SR = 0; /* Clear eventual pending IRQs. */ #if STM32_EICU_USE_TIM1 if (&EICUD1 == eicup) { nvicDisableVector(STM32_TIM1_UP_NUMBER); nvicDisableVector(STM32_TIM1_CC_NUMBER); rccDisableTIM1(FALSE); } #endif #if STM32_EICU_USE_TIM2 if (&EICUD2 == eicup) { nvicDisableVector(STM32_TIM2_NUMBER); rccDisableTIM2(FALSE); } #endif #if STM32_EICU_USE_TIM3 if (&EICUD3 == eicup) { nvicDisableVector(STM32_TIM3_NUMBER); rccDisableTIM3(FALSE); } #endif #if STM32_EICU_USE_TIM4 if (&EICUD4 == eicup) { nvicDisableVector(STM32_TIM4_NUMBER); rccDisableTIM4(FALSE); } #endif #if STM32_EICU_USE_TIM5 if (&EICUD5 == eicup) { nvicDisableVector(STM32_TIM5_NUMBER); rccDisableTIM5(FALSE); } #endif #if STM32_EICU_USE_TIM8 if (&EICUD8 == eicup) { nvicDisableVector(STM32_TIM8_UP_NUMBER); nvicDisableVector(STM32_TIM8_CC_NUMBER); rccDisableTIM8(FALSE); } #endif #if STM32_EICU_USE_TIM9 if (&EICUD9 == eicup) { nvicDisableVector(STM32_TIM9_NUMBER); rccDisableTIM9(FALSE); } #endif #if STM32_EICU_USE_TIM12 if (&EICUD12 == eicup) { nvicDisableVector(STM32_TIM12_NUMBER); rccDisableTIM12(FALSE); } #endif } } /** * @brief Enables the EICU. * * @param[in] eicup Pointer to the @p EICUDriver object * * @notapi */ void eicu_lld_enable(EICUDriver *eicup) { eicup->tim->EGR = STM32_TIM_EGR_UG; eicup->tim->SR = 0; /* Clear pending IRQs (if any). */ if (eicup->config->mode == EICU_FAST) eicu_lld_enable_fast(eicup); else eicu_lld_enable_slow(eicup); if (eicup->config->overflow_cb != NULL) eicup->tim->DIER |= STM32_TIM_DIER_UIE; eicup->tim->CR1 = STM32_TIM_CR1_URS | STM32_TIM_CR1_CEN; } /** * @brief Disables the EICU. * * @param[in] eicup Pointer to the @p EICUDriver object * * @notapi */ void eicu_lld_disable(EICUDriver *eicup) { eicup->tim->CR1 = 0; /* Initially stopped. */ eicup->tim->SR = 0; /* Clear pending IRQs (if any). */ /* All interrupts disabled.*/ eicup->tim->DIER &= ~STM32_TIM_DIER_IRQ_MASK; } #endif /* HAL_USE_EICU */