/* * Copyright (C) 2014-2016 Fabio Utzig, http://fabioutzig.com * * Permission is hereby granted, free of charge, to any person obtaining * a copy of this software and associated documentation files (the "Software"), * to deal in the Software without restriction, including without limitation * the rights to use, copy, modify, merge, publish, distribute, sublicense, * and/or sell copies of the Software, and to permit persons to whom the * Software is furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. */ #ifndef _K20xx_H_ #define _K20xx_H_ /* * ============================================================== * ---------- Interrupt Number Definition ----------------------- * ============================================================== */ /* Device dependent */ /* * ========================================================================== * ----------- Processor and Core Peripheral Section ------------------------ * ========================================================================== */ /** * @brief K20x Interrupt Number Definition, according to the selected device * in @ref Library_configuration_section */ #define __MPU_PRESENT 0 #define __NVIC_PRIO_BITS 4 #define __Vendor_SysTickConfig 0 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */ /* Device dependent typedef struct { __IO uint32_t SOPT1; __IO uint32_t SOPT1CFG; uint32_t RESERVED0[1023]; __IO uint32_t SOPT2; uint32_t RESERVED1[1]; __IO uint32_t SOPT4; __IO uint32_t SOPT5; uint32_t RESERVED2[1]; __IO uint32_t SOPT7; uint32_t RESERVED3[2]; __I uint32_t SDID; uint32_t RESERVED4[3]; __IO uint32_t SCGC4; __IO uint32_t SCGC5; __IO uint32_t SCGC6; __IO uint32_t SCGC7; __IO uint32_t CLKDIV1; __IO uint32_t CLKDIV2; __I uint32_t FCFG1; __I uint32_t FCFG2; __I uint32_t UIDH; __I uint32_t UIDMH; __I uint32_t UIDML; __I uint32_t UIDL; } SIM_TypeDef; */ typedef struct { __IO uint8_t PE1; __IO uint8_t PE2; __IO uint8_t PE3; __IO uint8_t PE4; __IO uint8_t ME; __IO uint8_t F1; __IO uint8_t F2; __I uint8_t F3; __IO uint8_t FILT1; __IO uint8_t FILT2; } LLWU_TypeDef; typedef struct { __IO uint32_t PCR[32]; __O uint32_t GPCLR; __O uint32_t GPCHR; uint32_t RESERVED0[6]; __IO uint32_t ISFR; } PORT_TypeDef; typedef struct { __IO uint8_t C1; __IO uint8_t C2; __IO uint8_t C3; __IO uint8_t C4; __IO uint8_t C5; __IO uint8_t C6; __I uint8_t S; uint8_t RESERVED0[1]; __IO uint8_t SC; uint8_t RESERVED1[1]; __IO uint8_t ATCVH; __IO uint8_t ATCVL; __IO uint8_t C7; __IO uint8_t C8; } MCG_TypeDef; typedef struct { __IO uint8_t CR; } OSC_TypeDef; typedef struct { uint32_t SADDR; /* TCD Source Address */ uint16_t SOFF; /* TCD Signed Source Address Offset */ uint16_t ATTR; /* TCD Transfer Attributes */ union { uint32_t NBYTES_MLNO; /* TCD Minor Byte Count (Minor Loop Disabled) */ uint32_t NBYTES_MLOFFNO; /* TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) */ uint32_t NBYTES_MLOFFYES; /* TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) */ }; uint32_t SLAST; /* TCD Last Source Address Adjustment */ uint32_t DADDR; /* TCD Destination Address */ uint16_t DOFF; /* TCD Signed Destination Address Offset */ union { uint16_t CITER_ELINKNO; /* TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ uint16_t CITER_ELINKYES; /* TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ }; uint32_t DLASTSGA; /* TCD Last Destination Address Adjustment/Scatter Gather Address */ uint16_t CSR; /* TCD Control and Status */ union { uint16_t BITER_ELINKNO; /* TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */ uint16_t BITER_ELINKYES; /* TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */ }; } DMA_TCD_TypeDef; /** DMA - Peripheral register structure */ typedef struct { __IO uint32_t CR; /* Control Register */ __IO uint32_t ES; /* Error Status Register */ __IO uint8_t RESERVED_0[4]; __IO uint32_t ERQ; /* Enable Request Register */ __IO uint8_t RESERVED_1[4]; __IO uint32_t EEI; /* Enable Error Interrupt Register */ __IO uint8_t CEEI; /* Clear Enable Error Interrupt Register */ __IO uint8_t SEEI; /* Set Enable Error Interrupt Register */ __IO uint8_t CERQ; /* Clear Enable Request Register */ __IO uint8_t SERQ; /* Set Enable Request Register */ __IO uint8_t CDNE; /* Clear DONE Status Bit Register */ __IO uint8_t SSRT; /* Set START Bit Register */ __IO uint8_t CERR; /* Clear Error Register */ __IO uint8_t CINT; /* Clear Interrupt Request Register */ __IO uint8_t RESERVED_2[4]; __IO uint32_t INT; /* Interrupt Request Register */ __IO uint8_t RESERVED_3[4]; __IO uint32_t ERR; /* Error Register */ __IO uint8_t RESERVED_4[4]; __IO uint32_t HRS; /* Hardware Request Status Register */ __IO uint8_t RESERVED_5[200]; __IO uint8_t DCHPRI3; /* Channel 3 Priority Register */ __IO uint8_t DCHPRI2; /* Channel 2 Priority Register */ __IO uint8_t DCHPRI1; /* Channel 1 Priority Register */ __IO uint8_t DCHPRI0; /* Channel 0 Priority Register */ __IO uint8_t RESERVED_6[3836]; DMA_TCD_TypeDef TCD[4]; } DMA_TypeDef; typedef struct { __IO uint8_t CHCFG[4]; } DMAMUX_TypeDef; /** PIT - Peripheral register structure */ typedef struct { __IO uint32_t MCR; /* PIT Module Control Register */ uint8_t RESERVED0[252]; struct PIT_CHANNEL { __IO uint32_t LDVAL; /* Timer Load Value Register */ __IO uint32_t CVAL; /* Current Timer Value Register */ __IO uint32_t TCTRL; /* Timer Control Register */ __IO uint32_t TFLG; /* Timer Flag Register */ } CHANNEL[4]; } PIT_TypeDef; typedef struct { __IO uint32_t SC; /* Status and Control */ __IO uint32_t CNT; /* Counter */ __IO uint32_t MOD; /* Modulo */ struct FTM_Channel { __IO uint32_t CnSC; /* Channel Status and Control */ __IO uint32_t CnV; /* Channel Value */ } CHANNEL[8]; __IO uint32_t CNTIN; /* Counter Initial Value */ __IO uint32_t STATUS; /* Capture and Compare Status */ __IO uint32_t MODE; /* Features Mode Selection */ __IO uint32_t SYNC; /* Synchronization */ __IO uint32_t OUTINIT; /* Initial State for Channels Output */ __IO uint32_t OUTMASK; /* Output Mask */ __IO uint32_t COMBINE; /* Function for Linked Channels */ __IO uint32_t DEADTIME; /* Deadtime Insertion Control */ __IO uint32_t EXTTRIG; /* FTM External Trigger */ __IO uint32_t POL; /* Channels Polarity */ __IO uint32_t FMS; /* Fault Mode Status */ __IO uint32_t FILTER; /* Input Capture Filter Control */ __IO uint32_t FLTCTRL; /* Fault Control */ __IO uint32_t QDCTRL; /* Quadrature Decode Control and Status */ __IO uint32_t CONF; /* Configuration */ __IO uint32_t FTLPOL; /* FTM Fault Input Polarity */ __IO uint32_t SYNCONF; /* Synchronization Configuration */ __IO uint32_t INVCTRL; /* FTM Inverting Control */ __IO uint32_t SWOCTRL; /* FTM Software Output Control */ __IO uint32_t PWMLOAD; /* FTM PWM Load */ } FTM_TypeDef; typedef struct { __IO uint32_t SC1A; // offset: 0x00 __IO uint32_t SC1B; // offset: 0x04 __IO uint32_t CFG1; // offset: 0x08 __IO uint32_t CFG2; // offset: 0x0C __I uint32_t RA; // offset: 0x10 __I uint32_t RB; // offset: 0x14 __IO uint32_t CV1; // offset: 0x18 __IO uint32_t CV2; // offset: 0x1C __IO uint32_t SC2; // offset: 0x20 __IO uint32_t SC3; // offset: 0x24 __IO uint32_t OFS; // offset: 0x28 __IO uint32_t PG; // offset: 0x2C __IO uint32_t MG; // offset: 0x30 __IO uint32_t CLPD; // offset: 0x34 __IO uint32_t CLPS; // offset: 0x38 __IO uint32_t CLP4; // offset: 0x3C __IO uint32_t CLP3; // offset: 0x40 __IO uint32_t CLP2; // offset: 0x44 __IO uint32_t CLP1; // offset: 0x48 __IO uint32_t CLP0; // offset: 0x4C uint32_t RESERVED0[1]; // offset: 0x50 __IO uint32_t CLMD; // offset: 0x54 __IO uint32_t CLMS; // offset: 0x58 __IO uint32_t CLM4; // offset: 0x5C __IO uint32_t CLM3; // offset: 0x60 __IO uint32_t CLM2; // offset: 0x64 __IO uint32_t CLM1; // offset: 0x68 __IO uint32_t CLM0; // offset: 0x6C } ADC_TypeDef; typedef struct { __IO uint32_t CSR; __IO uint32_t PSR; __IO uint32_t CMR; __I uint32_t CNR; } LPTMR_TypeDef; typedef struct { __IO uint32_t GENCS; __IO uint32_t DATA; __IO uint32_t TSHD; } TSI_TypeDef; typedef struct { __IO uint32_t PDOR; __IO uint32_t PSOR; __IO uint32_t PCOR; __IO uint32_t PTOR; __IO uint32_t PDIR; __IO uint32_t PDDR; } GPIO_TypeDef; /** SPI - Peripheral register structure */ typedef struct { __IO uint32_t MCR; /**< DSPI Module Configuration Register, offset: 0x0 */ uint32_t RESERVED0[1]; __IO uint32_t TCR; /**< DSPI Transfer Count Register, offset: 0x8 */ union { /* offset: 0xC */ __IO uint32_t CTAR[2]; /**< DSPI Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */ __IO uint32_t CTAR_SLAVE[1]; /**< DSPI Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */ }; uint32_t RESERVED1[6]; __IO uint32_t SR; /**< DSPI Status Register, offset: 0x2C */ __IO uint32_t RSER; /**< DSPI DMA/Interrupt Request Select and Enable Register, offset: 0x30 */ union { /* offset: 0x34 */ __IO uint32_t PUSHR; /**< DSPI PUSH TX FIFO Register In Master Mode, offset: 0x34 */ __IO uint32_t PUSHR_SLAVE; /**< DSPI PUSH TX FIFO Register In Slave Mode, offset: 0x34 */ }; __I uint32_t POPR; /**< DSPI POP RX FIFO Register, offset: 0x38 */ __I uint32_t TXFR[4]; /**< DSPI Transmit FIFO Registers, offset: 0x3C */ uint32_t RESERVED2[12]; __I uint32_t RXFR[4]; /**< DSPI Receive FIFO Registers, offset: 0x7C */ } SPI_TypeDef; typedef struct { __IO uint8_t A1; __IO uint8_t F; __IO uint8_t C1; __IO uint8_t S; __IO uint8_t D; __IO uint8_t C2; __IO uint8_t FLT; __IO uint8_t RA; __IO uint8_t SMB; __IO uint8_t A2; __IO uint8_t SLTH; __IO uint8_t SLTL; } I2C_TypeDef; typedef struct { __IO uint8_t BDH; __IO uint8_t BDL; __IO uint8_t C1; __IO uint8_t C2; __I uint8_t S1; __IO uint8_t S2; __IO uint8_t C3; __IO uint8_t D; __IO uint8_t MA1; __IO uint8_t MA2; __IO uint8_t C4; __IO uint8_t C5; __I uint8_t ED; __IO uint8_t MODEM; __IO uint8_t IR; uint8_t RESERVED0[1]; __IO uint8_t PFIFO; __IO uint8_t CFIFO; __IO uint8_t SFIFO; __IO uint8_t TWFIFO; __I uint8_t TCFIFO; __IO uint8_t RWFIFO; __I uint8_t RCFIFO; uint8_t RESERVED1[1]; __IO uint8_t C7816; __IO uint8_t IE7816; __IO uint8_t IS7816; union { __IO uint8_t WP7816T0; __IO uint8_t WP7816T1; }; __IO uint8_t WN7816; __IO uint8_t WF7816; __IO uint8_t ET7816; __IO uint8_t TL7816; uint8_t RESERVED2[2]; __IO uint8_t C6; __IO uint8_t PCTH; __IO uint8_t PCTL; __IO uint8_t B1T; __IO uint8_t SDTH; __IO uint8_t SDTL; __IO uint8_t PRE; __IO uint8_t TPL; __IO uint8_t IE; __IO uint8_t WB; __IO uint8_t S3; __IO uint8_t S4; __I uint8_t RPL; __I uint8_t RPREL; __IO uint8_t CPW; __IO uint8_t RIDT; __IO uint8_t TIDT; } UART_TypeDef; typedef struct { __IO uint8_t LVDSC1; __IO uint8_t LVDSC2; __IO uint8_t REGSC; } PMC_TypeDef; typedef struct { __IO uint16_t STCTRLH; __IO uint16_t STCTRLL; __IO uint16_t TOVALH; __IO uint16_t TOVALL; __IO uint16_t WINH; __IO uint16_t WINL; __IO uint16_t REFRESH; __IO uint16_t UNLOCK; __IO uint16_t TMROUTH; __IO uint16_t TMROUTL; __IO uint16_t RSTCNT; __IO uint16_t PRESC; } WDOG_TypeDef; typedef struct { __I uint8_t PERID; // 0x00 uint8_t RESERVED0[3]; __I uint8_t IDCOMP; // 0x04 uint8_t RESERVED1[3]; __I uint8_t REV; // 0x08 uint8_t RESERVED2[3]; __I uint8_t ADDINFO; // 0x0C uint8_t RESERVED3[3]; __IO uint8_t OTGISTAT; // 0x10 uint8_t RESERVED4[3]; __IO uint8_t OTGICR; // 0x14 uint8_t RESERVED5[3]; __IO uint8_t OTGSTAT; // 0x18 uint8_t RESERVED6[3]; __IO uint8_t OTGCTL; // 0x1C uint8_t RESERVED7[99]; __IO uint8_t ISTAT; // 0x80 uint8_t RESERVED8[3]; __IO uint8_t INTEN; // 0x84 uint8_t RESERVED9[3]; __IO uint8_t ERRSTAT; // 0x88 uint8_t RESERVED10[3]; __IO uint8_t ERREN; // 0x8C uint8_t RESERVED11[3]; __I uint8_t STAT; // 0x90 uint8_t RESERVED12[3]; __IO uint8_t CTL; // 0x94 uint8_t RESERVED13[3]; __IO uint8_t ADDR; // 0x98 uint8_t RESERVED14[3]; __IO uint8_t BDTPAGE1; // 0x9C uint8_t RESERVED15[3]; __IO uint8_t FRMNUML; // 0xA0 uint8_t RESERVED16[3]; __IO uint8_t FRMNUMH; // 0xA4 uint8_t RESERVED17[3]; __IO uint8_t TOKEN; // 0xA8 uint8_t RESERVED18[3]; __IO uint8_t SOFTHLD; // 0xAC uint8_t RESERVED19[3]; __IO uint8_t BDTPAGE2; // 0xB0 uint8_t RESERVED20[3]; __IO uint8_t BDTPAGE3; // 0xB4 uint8_t RESERVED21[11]; struct { __IO uint8_t V; // 0xC0 uint8_t RESERVED[3]; } ENDPT[16]; __IO uint8_t USBCTRL; // 0x100 uint8_t RESERVED22[3]; __I uint8_t OBSERVE; // 0x104 uint8_t RESERVED23[3]; __IO uint8_t CONTROL; // 0x108 uint8_t RESERVED24[3]; __IO uint8_t USBTRC0; // 0x10C uint8_t RESERVED25[7]; __IO uint8_t USBFRMADJUST; // 0x114 } USBOTG_TypeDef; typedef struct { __IO uint8_t FSTAT; __IO uint8_t FCNFG; __I uint8_t FSEC; __I uint8_t FOPT; __IO uint8_t FCCOB3; __IO uint8_t FCCOB2; __IO uint8_t FCCOB1; __IO uint8_t FCCOB0; __IO uint8_t FCCOB7; __IO uint8_t FCCOB6; __IO uint8_t FCCOB5; __IO uint8_t FCCOB4; __IO uint8_t FCCOBB; __IO uint8_t FCCOBA; __IO uint8_t FCCOB9; __IO uint8_t FCCOB8; __IO uint8_t FPROT3; __IO uint8_t FPROT2; __IO uint8_t FPROT1; __IO uint8_t FPROT0; uint8_t RESERVED0[2]; __IO uint8_t FEPROT; __IO uint8_t FDPROT; } FTFL_TypeDef; /****************************************************************/ /* Peripheral memory map */ /****************************************************************/ /* Device dependent */ /****************************************************************/ /* Peripheral declaration */ /****************************************************************/ /* Device dependent */ /****************************************************************/ /* Peripheral Registers Bits Definition */ /****************************************************************/ /****************************************************************/ /* */ /* System Integration Module (SIM) */ /* */ /****************************************************************/ /* Device dependent */ /****************************************************************/ /* */ /* Low-Leakage Wakeup Unit (LLWU) */ /* */ /****************************************************************/ /********** Bits definition for LLWU_PE1 register *************/ #define LLWU_PE1_WUPE3_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P3 (shift) */ #define LLWU_PE1_WUPE3_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE3_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P3 (mask) */ #define LLWU_PE1_WUPE3(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE3_SHIFT) & LLWU_PE1_WUPE3_MASK)) /*!< Wakeup Pin Enable for LLWU_P3 */ #define LLWU_PE1_WUPE2_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P2 (shift) */ #define LLWU_PE1_WUPE2_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE2_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P2 (mask) */ #define LLWU_PE1_WUPE2(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE2_SHIFT) & LLWU_PE1_WUPE2_MASK)) /*!< Wakeup Pin Enable for LLWU_P2 */ #define LLWU_PE1_WUPE1_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P1 (shift) */ #define LLWU_PE1_WUPE1_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE1_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P1 (mask) */ #define LLWU_PE1_WUPE1(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE1_SHIFT) & LLWU_PE1_WUPE1_MASK)) /*!< Wakeup Pin Enable for LLWU_P1 */ #define LLWU_PE1_WUPE0_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P0 (shift) */ #define LLWU_PE1_WUPE0_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE1_WUPE0_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P0 (mask) */ #define LLWU_PE1_WUPE0(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE1_WUPE0_SHIFT) & LLWU_PE1_WUPE0_MASK)) /*!< Wakeup Pin Enable for LLWU_P0 */ /********** Bits definition for LLWU_PE2 register *************/ #define LLWU_PE2_WUPE7_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P7 (shift) */ #define LLWU_PE2_WUPE7_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE7_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P7 (mask) */ #define LLWU_PE2_WUPE7(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE7_SHIFT) & LLWU_PE2_WUPE7_MASK)) /*!< Wakeup Pin Enable for LLWU_P7 */ #define LLWU_PE2_WUPE6_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P6 (shift) */ #define LLWU_PE2_WUPE6_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE6_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P6 (mask) */ #define LLWU_PE2_WUPE6(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE6_SHIFT) & LLWU_PE2_WUPE6_MASK)) /*!< Wakeup Pin Enable for LLWU_P6 */ #define LLWU_PE2_WUPE5_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P5 (shift) */ #define LLWU_PE2_WUPE5_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE5_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P5 (mask) */ #define LLWU_PE2_WUPE5(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE5_SHIFT) & LLWU_PE2_WUPE5_MASK)) /*!< Wakeup Pin Enable for LLWU_P5 */ #define LLWU_PE2_WUPE4_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P4 (shift) */ #define LLWU_PE2_WUPE4_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE2_WUPE4_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P4 (mask) */ #define LLWU_PE2_WUPE4(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE2_WUPE4_SHIFT) & LLWU_PE2_WUPE4_MASK)) /*!< Wakeup Pin Enable for LLWU_P4 */ /********** Bits definition for LLWU_PE3 register *************/ #define LLWU_PE3_WUPE11_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P11 (shift) */ #define LLWU_PE3_WUPE11_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE11_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P11 (mask) */ #define LLWU_PE3_WUPE11(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE11_SHIFT) & LLWU_PE3_WUPE11_MASK)) /*!< Wakeup Pin Enable for LLWU_P11 */ #define LLWU_PE3_WUPE10_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P10 (shift) */ #define LLWU_PE3_WUPE10_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE10_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P10 (mask) */ #define LLWU_PE3_WUPE10(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE10_SHIFT) & LLWU_PE3_WUPE10_MASK)) /*!< Wakeup Pin Enable for LLWU_P10 */ #define LLWU_PE3_WUPE13_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P9 (shift) */ #define LLWU_PE3_WUPE13_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE13_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P9 (mask) */ #define LLWU_PE3_WUPE13(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE13_SHIFT) & LLWU_PE3_WUPE13_MASK)) /*!< Wakeup Pin Enable for LLWU_P9 */ #define LLWU_PE3_WUPE8_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P8 (shift) */ #define LLWU_PE3_WUPE8_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE3_WUPE8_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P8 (mask) */ #define LLWU_PE3_WUPE8(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE3_WUPE8_SHIFT) & LLWU_PE3_WUPE8_MASK)) /*!< Wakeup Pin Enable for LLWU_P8 */ /********** Bits definition for LLWU_PE4 register *************/ #define LLWU_PE4_WUPE15_SHIFT 6 /*!< Wakeup Pin Enable for LLWU_P15 (shift) */ #define LLWU_PE4_WUPE15_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE15_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P15 (mask) */ #define LLWU_PE4_WUPE15(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE15_SHIFT) & LLWU_PE4_WUPE15_MASK)) /*!< Wakeup Pin Enable for LLWU_P15 */ #define LLWU_PE4_WUPE14_SHIFT 4 /*!< Wakeup Pin Enable for LLWU_P14 (shift) */ #define LLWU_PE4_WUPE14_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE14_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P14 (mask) */ #define LLWU_PE4_WUPE14(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE14_SHIFT) & LLWU_PE4_WUPE14_MASK)) /*!< Wakeup Pin Enable for LLWU_P14 */ #define LLWU_PE4_WUPE13_SHIFT 2 /*!< Wakeup Pin Enable for LLWU_P13 (shift) */ #define LLWU_PE4_WUPE13_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE13_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P13 (mask) */ #define LLWU_PE4_WUPE13(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE13_SHIFT) & LLWU_PE4_WUPE13_MASK)) /*!< Wakeup Pin Enable for LLWU_P13 */ #define LLWU_PE4_WUPE12_SHIFT 0 /*!< Wakeup Pin Enable for LLWU_P12 (shift) */ #define LLWU_PE4_WUPE12_MASK ((uint8_t)((uint8_t)0x03 << LLWU_PE4_WUPE12_SHIFT)) /*!< Wakeup Pin Enable for LLWU_P12 (mask) */ #define LLWU_PE4_WUPE12(x) ((uint8_t)(((uint8_t)(x) << LLWU_PE4_WUPE12_SHIFT) & LLWU_PE4_WUPE12_MASK)) /*!< Wakeup Pin Enable for LLWU_P12 */ /********** Bits definition for LLWU_ME register *************/ #define LLWU_ME_WUME7 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Module Enable for Module 7 */ #define LLWU_ME_WUME6 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Module Enable for Module 6 */ #define LLWU_ME_WUME5 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Module Enable for Module 5 */ #define LLWU_ME_WUME4 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Module Enable for Module 4 */ #define LLWU_ME_WUME3 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Module Enable for Module 3 */ #define LLWU_ME_WUME2 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Module Enable for Module 2 */ #define LLWU_ME_WUME1 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Module Enable for Module 1 */ #define LLWU_ME_WUME0 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Module Enable for Module 0 */ /********** Bits definition for LLWU_F1 register *************/ #define LLWU_F1_WUF7 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Flag for LLWU_P7 */ #define LLWU_F1_WUF6 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Flag for LLWU_P6 */ #define LLWU_F1_WUF5 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Flag for LLWU_P5 */ #define LLWU_F1_WUF4 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Flag for LLWU_P4 */ #define LLWU_F1_WUF3 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Flag for LLWU_P3 */ #define LLWU_F1_WUF2 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Flag for LLWU_P2 */ #define LLWU_F1_WUF1 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Flag for LLWU_P1 */ #define LLWU_F1_WUF0 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Flag for LLWU_P0 */ /********** Bits definition for LLWU_F2 register *************/ #define LLWU_F2_WUF15 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Flag for LLWU_P15 */ #define LLWU_F2_WUF14 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Flag for LLWU_P14 */ #define LLWU_F2_WUF13 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Flag for LLWU_P13 */ #define LLWU_F2_WUF12 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Flag for LLWU_P12 */ #define LLWU_F2_WUF11 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Flag for LLWU_P11 */ #define LLWU_F2_WUF10 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Flag for LLWU_P10 */ #define LLWU_F2_WUF9 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Flag for LLWU_P9 */ #define LLWU_F2_WUF8 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Flag for LLWU_P8 */ /********** Bits definition for LLWU_F3 register *************/ #define LLWU_F3_MWUF7 ((uint8_t)((uint8_t)1 << 7)) /*!< Wakeup Flag for Module 7 */ #define LLWU_F3_MWUF6 ((uint8_t)((uint8_t)1 << 6)) /*!< Wakeup Flag for Module 6 */ #define LLWU_F3_MWUF5 ((uint8_t)((uint8_t)1 << 5)) /*!< Wakeup Flag for Module 5 */ #define LLWU_F3_MWUF4 ((uint8_t)((uint8_t)1 << 4)) /*!< Wakeup Flag for Module 4 */ #define LLWU_F3_MWUF3 ((uint8_t)((uint8_t)1 << 3)) /*!< Wakeup Flag for Module 3 */ #define LLWU_F3_MWUF2 ((uint8_t)((uint8_t)1 << 2)) /*!< Wakeup Flag for Module 2 */ #define LLWU_F3_MWUF1 ((uint8_t)((uint8_t)1 << 1)) /*!< Wakeup Flag for Module 1 */ #define LLWU_F3_MWUF0 ((uint8_t)((uint8_t)1 << 0)) /*!< Wakeup Flag for Module 0 */ /********** Bits definition for LLWU_FILT1 register *************/ #define LLWU_FILT1_FILTF ((uint8_t)((uint8_t)1 << 7)) /*!< Filter Detect Flag */ #define LLWU_FILT1_FILTE_SHIFT 5 /*!< Digital Filter on External Pin (shift) */ #define LLWU_FILT1_FILTE_MASK ((uint8_t)((uint8_t)0x03 << LLWU_FILT1_FILTE_SHIFT)) /*!< Digital Filter on External Pin (mask) */ #define LLWU_FILT1_FILTE(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT1_FILTE_SHIFT) & LLWU_FILT1_FILTE_MASK)) /*!< Digital Filter on External Pin */ #define LLWU_FILT1_FILTE_DISABLED LLWU_FILT1_FILTE(0) /*!< Filter disabled */ #define LLWU_FILT1_FILTE_POSEDGE LLWU_FILT1_FILTE(1) /*!< Filter posedge detect enabled */ #define LLWU_FILT1_FILTE_NEGEDGE LLWU_FILT1_FILTE(2) /*!< Filter negedge detect enabled */ #define LLWU_FILT1_FILTE_ANYEDGE LLWU_FILT1_FILTE(3) /*!< Filter any edge detect enabled */ #define LLWU_FILT1_FILTSEL_SHIFT 0 /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (shift) */ #define LLWU_FILT1_FILTSEL_MASK ((uint8_t)((uint8_t)0x0F << LLWU_FILT1_FILTSEL_SHIFT)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (mask) */ #define LLWU_FILT1_FILTSEL(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT1_FILTSEL_SHIFT) & LLWU_FILT1_FILTSEL_MASK)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) */ /********** Bits definition for LLWU_FILT2 register *************/ #define LLWU_FILT2_FILTF ((uint8_t)((uint8_t)1 << 7)) /*!< Filter Detect Flag */ #define LLWU_FILT2_FILTE_SHIFT 5 /*!< Digital Filter on External Pin (shift) */ #define LLWU_FILT2_FILTE_MASK ((uint8_t)((uint8_t)0x03 << LLWU_FILT2_FILTE_SHIFT)) /*!< Digital Filter on External Pin (mask) */ #define LLWU_FILT2_FILTE(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT2_FILTE_SHIFT) & LLWU_FILT2_FILTE_MASK)) /*!< Digital Filter on External Pin */ #define LLWU_FILT2_FILTE_DISABLED LLWU_FILT2_FILTE(0) /*!< Filter disabled */ #define LLWU_FILT2_FILTE_POSEDGE LLWU_FILT2_FILTE(1) /*!< Filter posedge detect enabled */ #define LLWU_FILT2_FILTE_NEGEDGE LLWU_FILT2_FILTE(2) /*!< Filter negedge detect enabled */ #define LLWU_FILT2_FILTE_ANYEDGE LLWU_FILT2_FILTE(3) /*!< Filter any edge detect enabled */ #define LLWU_FILT2_FILTSEL_SHIFT 0 /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (shift) */ #define LLWU_FILT2_FILTSEL_MASK ((uint8_t)((uint8_t)0x0F << LLWU_FILT2_FILTSEL_SHIFT)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) (mask) */ #define LLWU_FILT2_FILTSEL(x) ((uint8_t)(((uint8_t)(x) << LLWU_FILT2_FILTSEL_SHIFT) & LLWU_FILT2_FILTSEL_MASK)) /*!< Filter Pin Select (LLWU_P0 ... LLWU_P15) */ /****************************************************************/ /* */ /* Port Control and interrupts (PORT) */ /* */ /****************************************************************/ /******** Bits definition for PORTx_PCRn register *************/ #define PORTx_PCRn_ISF ((uint32_t)0x01000000) /*!< Interrupt Status Flag */ #define PORTx_PCRn_IRQC_SHIFT 16 #define PORTx_PCRn_IRQC_MASK ((uint32_t)((uint32_t)0xF << PORTx_PCRn_IRQC_SHIFT)) #define PORTx_PCRn_IRQC(x) ((uint32_t)(((uint32_t)(x) << PORTx_PCRn_IRQC_SHIFT) & PORTx_PCRn_IRQC_MASK)) #define PORTx_PCRn_LK ((uint32_t)0x00008000) /*!< Lock Register */ #define PORTx_PCRn_MUX_SHIFT 8 /*!< Pin Mux Control (shift) */ #define PORTx_PCRn_MUX_MASK ((uint32_t)((uint32_t)0x7 << PORTx_PCRn_MUX_SHIFT)) /*!< Pin Mux Control (mask) */ #define PORTx_PCRn_MUX(x) ((uint32_t)(((uint32_t)(x) << PORTx_PCRn_MUX_SHIFT) & PORTx_PCRn_MUX_MASK)) /*!< Pin Mux Control */ #define PORTx_PCRn_DSE ((uint32_t)0x00000040) /*!< Drive Strength Enable */ #define PORTx_PCRn_ODE ((uint32_t)0x00000020) /*!< Open Drain Enable */ #define PORTx_PCRn_PFE ((uint32_t)0x00000010) /*!< Passive Filter Enable */ #define PORTx_PCRn_SRE ((uint32_t)0x00000004) /*!< Slew Rate Enable */ #define PORTx_PCRn_PE ((uint32_t)0x00000002) /*!< Pull Enable */ #define PORTx_PCRn_PS ((uint32_t)0x00000001) /*!< Pull Select */ /****************************************************************/ /* */ /* Oscillator (OSC) */ /* */ /****************************************************************/ /*********** Bits definition for OSC_CR register **************/ #define OSC_CR_ERCLKEN ((uint8_t)0x80) /*!< External Reference Enable */ #define OSC_CR_EREFSTEN ((uint8_t)0x20) /*!< External Reference Stop Enable */ #define OSC_CR_SC2P ((uint8_t)0x08) /*!< Oscillator 2pF Capacitor Load Configure */ #define OSC_CR_SC4P ((uint8_t)0x04) /*!< Oscillator 4pF Capacitor Load Configure */ #define OSC_CR_SC8P ((uint8_t)0x02) /*!< Oscillator 8pF Capacitor Load Configure */ #define OSC_CR_SC16P ((uint8_t)0x01) /*!< Oscillator 16pF Capacitor Load Configure */ /****************************************************************/ /* */ /* Direct Memory Access (DMA) */ /* */ /****************************************************************/ /* ---------------------------------------------------------------------------- -- DMA - Register accessor macros ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_Register_Accessor_Macros DMA - Register accessor macros * @{ */ /* DMA - Register accessors */ #define DMA_CR_REG(base) ((base)->CR) #define DMA_ES_REG(base) ((base)->ES) #define DMA_ERQ_REG(base) ((base)->ERQ) #define DMA_EEI_REG(base) ((base)->EEI) #define DMA_CEEI_REG(base) ((base)->CEEI) #define DMA_SEEI_REG(base) ((base)->SEEI) #define DMA_CERQ_REG(base) ((base)->CERQ) #define DMA_SERQ_REG(base) ((base)->SERQ) #define DMA_CDNE_REG(base) ((base)->CDNE) #define DMA_SSRT_REG(base) ((base)->SSRT) #define DMA_CERR_REG(base) ((base)->CERR) #define DMA_CINT_REG(base) ((base)->CINT) #define DMA_INT_REG(base) ((base)->INT) #define DMA_ERR_REG(base) ((base)->ERR) #define DMA_HRS_REG(base) ((base)->HRS) #define DMA_DCHPRI3_REG(base) ((base)->DCHPRI3) #define DMA_DCHPRI2_REG(base) ((base)->DCHPRI2) #define DMA_DCHPRI1_REG(base) ((base)->DCHPRI1) #define DMA_DCHPRI0_REG(base) ((base)->DCHPRI0) #define DMA_SADDR_REG(base,index) ((base)->TCD[index].SADDR) #define DMA_SOFF_REG(base,index) ((base)->TCD[index].SOFF) #define DMA_ATTR_REG(base,index) ((base)->TCD[index].ATTR) #define DMA_NBYTES_MLNO_REG(base,index) ((base)->TCD[index].NBYTES_MLNO) #define DMA_NBYTES_MLOFFNO_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFNO) #define DMA_NBYTES_MLOFFYES_REG(base,index) ((base)->TCD[index].NBYTES_MLOFFYES) #define DMA_SLAST_REG(base,index) ((base)->TCD[index].SLAST) #define DMA_DADDR_REG(base,index) ((base)->TCD[index].DADDR) #define DMA_DOFF_REG(base,index) ((base)->TCD[index].DOFF) #define DMA_CITER_ELINKNO_REG(base,index) ((base)->TCD[index].CITER_ELINKNO) #define DMA_CITER_ELINKYES_REG(base,index) ((base)->TCD[index].CITER_ELINKYES) #define DMA_DLAST_SGA_REG(base,index) ((base)->TCD[index].DLAST_SGA) #define DMA_CSR_REG(base,index) ((base)->TCD[index].CSR) #define DMA_BITER_ELINKNO_REG(base,index) ((base)->TCD[index].BITER_ELINKNO) #define DMA_BITER_ELINKYES_REG(base,index) ((base)->TCD[index].BITER_ELINKYES) /*! * @} */ /* end of group DMA_Register_Accessor_Macros */ /* ---------------------------------------------------------------------------- -- DMA Register Masks ---------------------------------------------------------------------------- */ /*! * @addtogroup DMA_Register_Masks DMA Register Masks * @{ */ /* CR Bit Fields */ #define DMA_CR_EDBG_MASK 0x2u #define DMA_CR_EDBG_SHIFT 1 #define DMA_CR_ERCA_MASK 0x4u #define DMA_CR_ERCA_SHIFT 2 #define DMA_CR_HOE_MASK 0x10u #define DMA_CR_HOE_SHIFT 4 #define DMA_CR_HALT_MASK 0x20u #define DMA_CR_HALT_SHIFT 5 #define DMA_CR_CLM_MASK 0x40u #define DMA_CR_CLM_SHIFT 6 #define DMA_CR_EMLM_MASK 0x80u #define DMA_CR_EMLM_SHIFT 7 #define DMA_CR_ECX_MASK 0x10000u #define DMA_CR_ECX_SHIFT 16 #define DMA_CR_CX_MASK 0x20000u #define DMA_CR_CX_SHIFT 17 /* ES Bit Fields */ #define DMA_ES_DBE_MASK 0x1u #define DMA_ES_DBE_SHIFT 0 #define DMA_ES_SBE_MASK 0x2u #define DMA_ES_SBE_SHIFT 1 #define DMA_ES_SGE_MASK 0x4u #define DMA_ES_SGE_SHIFT 2 #define DMA_ES_NCE_MASK 0x8u #define DMA_ES_NCE_SHIFT 3 #define DMA_ES_DOE_MASK 0x10u #define DMA_ES_DOE_SHIFT 4 #define DMA_ES_DAE_MASK 0x20u #define DMA_ES_DAE_SHIFT 5 #define DMA_ES_SOE_MASK 0x40u #define DMA_ES_SOE_SHIFT 6 #define DMA_ES_SAE_MASK 0x80u #define DMA_ES_SAE_SHIFT 7 #define DMA_ES_ERRCHN_MASK 0xF00u #define DMA_ES_ERRCHN_SHIFT 8 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x))<