From 5d77abe7f22bb8df86f09ec4684a5c3f7e2b8ae7 Mon Sep 17 00:00:00 2001
From: marcoveeneman <marco-veeneman@hotmail.com>
Date: Sun, 10 Sep 2017 19:43:04 +0200
Subject: Initial version of the Tiva UART driver.

---
 os/hal/ports/TIVA/LLD/UART/driver.mk      |   4 +
 os/hal/ports/TIVA/LLD/UART/hal_uart_lld.c | 826 ++++++++++++++++++++++++++++++
 os/hal/ports/TIVA/LLD/UART/hal_uart_lld.h | 471 +++++++++++++++++
 3 files changed, 1301 insertions(+)
 create mode 100644 os/hal/ports/TIVA/LLD/UART/hal_uart_lld.c
 create mode 100644 os/hal/ports/TIVA/LLD/UART/hal_uart_lld.h

(limited to 'os')

diff --git a/os/hal/ports/TIVA/LLD/UART/driver.mk b/os/hal/ports/TIVA/LLD/UART/driver.mk
index e23dc82..e42f34a 100644
--- a/os/hal/ports/TIVA/LLD/UART/driver.mk
+++ b/os/hal/ports/TIVA/LLD/UART/driver.mk
@@ -2,8 +2,12 @@ ifeq ($(USE_SMART_BUILD),yes)
 ifneq ($(findstring HAL_USE_SERIAL TRUE,$(HALCONF)),)
 PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c
 endif
+ifneq ($(findstring HAL_USE_UART TRUE,$(HALCONF)),)
+PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.c
+endif
 else
 PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c
+PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.c
 endif
 
 PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART
diff --git a/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.c b/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.c
new file mode 100644
index 0000000..374ea6d
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.c
@@ -0,0 +1,826 @@
+/*
+    Copyright (C) 2014..2017 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    UART/hal_uart_lld.c
+ * @brief   Tiva low level UART driver code.
+ *
+ * @addtogroup UART
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_UART || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/** @brief UART0 UART driver identifier.*/
+#if TIVA_UART_USE_UART0 || defined(__DOXYGEN__)
+UARTDriver UARTD1;
+#endif
+
+/** @brief UART1 UART driver identifier.*/
+#if TIVA_UART_USE_UART1 || defined(__DOXYGEN__)
+UARTDriver UARTD2;
+#endif
+
+/** @brief UART2 UART driver identifier.*/
+#if TIVA_UART_USE_UART2 || defined(__DOXYGEN__)
+UARTDriver UARTD3;
+#endif
+
+/** @brief UART3 UART driver identifier.*/
+#if TIVA_UART_USE_UART3 || defined(__DOXYGEN__)
+UARTDriver UARTD4;
+#endif
+
+/** @brief UART4 UART driver identifier.*/
+#if TIVA_UART_USE_UART4 || defined(__DOXYGEN__)
+UARTDriver UARTD5;
+#endif
+
+/** @brief UART5 UART driver identifier.*/
+#if TIVA_UART_USE_UART5 || defined(__DOXYGEN__)
+UARTDriver UARTD6;
+#endif
+
+/** @brief UART6 UART driver identifier.*/
+#if TIVA_UART_USE_UART6 || defined(__DOXYGEN__)
+UARTDriver UARTD7;
+#endif
+
+/** @brief UART7 UART driver identifier.*/
+#if TIVA_UART_USE_UART7 || defined(__DOXYGEN__)
+UARTDriver UARTD8;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/**
+ * @brief   Status bits translation.
+ *
+ * @param[in] err       UART LSR register value
+ *
+ * @return  The error flags.
+ */
+static uartflags_t translate_errors(uint32_t err)
+{
+  uartflags_t sts = 0;
+
+  if (err & UART_MIS_FEMIS)
+    sts |= UART_FRAMING_ERROR;
+  if (err & UART_MIS_PEMIS)
+    sts |= UART_PARITY_ERROR;
+  if (err & UART_MIS_BEMIS)
+    sts |= UART_BREAK_DETECTED;
+  if (err & UART_MIS_OEMIS)
+    sts |= UART_OVERRUN_ERROR;
+
+  return sts;
+}
+
+/**
+ * @brief   Puts the receiver in the UART_RX_IDLE state.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ */
+static void uart_enter_rx_idle_loop(UARTDriver *uartp)
+{
+  tiva_udma_table_entry_t *primary = udmaControlTable.primary;
+
+  dmaChannelDisable(uartp->dmarxnr);
+
+  /* Configure for 8-bit transfers.*/
+  primary[uartp->dmarxnr].srcendp = (void *)(uartp->uart + UART_O_DR);
+  primary[uartp->dmarxnr].dstendp = (volatile void *)&uartp->rxbuf;
+  primary[uartp->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_8 |
+                                  UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE |
+                                  UDMA_CHCTL_ARBSIZE_4 |
+                                  UDMA_CHCTL_XFERSIZE(1) |
+                                  UDMA_CHCTL_XFERMODE_BASIC;
+
+  dmaChannelSingleBurst(uartp->dmarxnr);
+  dmaChannelPrimary(uartp->dmarxnr);
+  dmaChannelPriorityDefault(uartp->dmarxnr);
+  dmaChannelEnableRequest(uartp->dmarxnr);
+
+  /* Enable DMA channel, transfer starts immediately.*/
+  dmaChannelEnable(uartp->dmarxnr);
+}
+
+/**
+ * @brief   UART de-initialization.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ */
+static void uart_stop(UARTDriver *uartp)
+{
+  /* Stops RX and TX DMA channels.*/
+  dmaChannelDisable(uartp->dmarxnr);
+  dmaChannelDisable(uartp->dmatxnr);
+
+  /* Stops USART operations.*/
+  HWREG(uartp->uart + UART_O_CTL) &= ~UART_CTL_UARTEN;
+}
+
+/**
+ * @brief   UART initialization.
+ *
+ * @param[in] uartp     pointer to a @p UARTDriver object
+ */
+static void uart_init(UARTDriver *uartp)
+{
+  uint32_t u = uartp->uart;
+  const UARTConfig *config = uartp->config;
+  uint32_t brd;
+  uint32_t speed = config->speed;
+  uint32_t clock_source;
+
+  if (uartp->config->ctl & UART_CTL_HSE) {
+    /* High speed mode is enabled, half the baud rate to compensate
+     * for high speed mode.*/
+    speed = (speed + 1) / 2;
+  }
+
+  if ((config->cc & UART_CC_CS_M) == UART_CC_CS_SYSCLK) {
+    /* UART is clocked using the SYSCLK.*/
+    clock_source = TIVA_SYSCLK * 8;
+  }
+  else {
+    /* UART is clocked using the PIOSC.*/
+    clock_source = 16000000 * 8;
+  }
+
+  /* Calculate the baud rate divisor */
+  brd = ((clock_source / speed) + 1) / 2;
+
+  /* Disable UART.*/
+  HWREG(u + UART_O_CTL) &= ~UART_CTL_UARTEN;
+
+  /* Set baud rate.*/
+  HWREG(u + UART_O_IBRD) = brd / 64;
+  HWREG(u + UART_O_FBRD) = brd % 64;
+
+  /* Line control/*/
+  HWREG(u + UART_O_LCRH) = config->lcrh;
+
+  /* Select clock source.*/
+  HWREG(u + UART_O_CC) = config->cc & UART_CC_CS_M;
+
+  /* FIFO configuration.*/
+  HWREG(u + UART_O_IFLS) = config->ifls & (UART_IFLS_RX_M | UART_IFLS_TX_M);
+
+  /* Enable interrupts.*/
+  HWREG(u + UART_O_IM) = UART_IM_TXIM | UART_IM_OEIM | UART_IM_BEIM | UART_IM_PEIM | UART_IM_FEIM;
+
+  /* Enable DMA for the UART */
+  HWREG(u + UART_O_DMACTL) = UART_DMACTL_TXDMAE | UART_DMACTL_RXDMAE | UART_DMACTL_DMAERR;
+
+  /* Note that some bits are enforced.*/
+  HWREG(u + UART_O_CTL)  = config->ctl | UART_CTL_RXE | UART_CTL_TXE | UART_CTL_UARTEN | UART_CTL_EOT;
+
+  /* Starting the receiver idle loop.*/
+  uart_enter_rx_idle_loop(uartp);
+}
+
+/**
+ * @brief   UART common service routine.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ */
+static void uart_serve_interrupt(UARTDriver *uartp)
+{
+  uint32_t dmachis = HWREG(UDMA_CHIS);
+  uint32_t mis = HWREG(uartp->uart + UART_O_MIS);
+
+  if (mis & UART_MIS_TXMIS) {
+    /* End of transfer */
+    _uart_tx2_isr_code(uartp);
+  }
+
+  if (mis & (UART_MIS_OEMIS | UART_MIS_BEMIS | UART_MIS_PEMIS | UART_MIS_FEMIS)) {
+    /* Error occurred */
+    _uart_rx_error_isr_code(uartp, translate_errors(mis));
+  }
+
+  if (dmachis & (1 << uartp->dmarxnr)) {
+    if (uartp->rxstate == UART_RX_IDLE) {
+      /* Receiver in idle state, a callback is generated, if enabled, for each
+         received character and then the driver stays in the same state.*/
+      _uart_rx_idle_code(uartp);
+      uart_enter_rx_idle_loop(uartp);
+    }
+    else {
+      /* Receiver in active state, a callback is generated, if enabled, after
+         a completed transfer.*/
+      _uart_rx_complete_isr_code(uartp);
+    }
+  }
+
+  if (dmachis & (1 << uartp->dmatxnr)) {
+    /* A callback is generated, if enabled, after a completed transfer.*/
+    _uart_tx1_isr_code(uartp);
+  }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if TIVA_UART_USE_UART0 || defined(__DOXYGEN__)
+#if !defined(TIVA_UART0_HANDLER)
+#error "TIVA_UART0_HANDLER not defined"
+#endif
+/**
+ * @brief   UART0 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_UART0_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  uart_serve_interrupt(&UARTD1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_UART_USE_UART1 || defined(__DOXYGEN__)
+#if !defined(TIVA_UART1_HANDLER)
+#error "TIVA_UART1_HANDLER not defined"
+#endif
+/**
+ * @brief   UART1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_UART1_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  uart_serve_interrupt(&UARTD2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_UART_USE_UART2 || defined(__DOXYGEN__)
+#if !defined(TIVA_UART2_HANDLER)
+#error "TIVA_UART2_HANDLER not defined"
+#endif
+/**
+ * @brief   UART2 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_UART2_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  uart_serve_interrupt(&UARTD3);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_UART_USE_UART3 || defined(__DOXYGEN__)
+#if !defined(TIVA_UART3_HANDLER)
+#error "TIVA_UART3_HANDLER not defined"
+#endif
+/**
+ * @brief   UART3 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_UART3_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  uart_serve_interrupt(&UARTD4);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_UART_USE_UART4 || defined(__DOXYGEN__)
+#if !defined(TIVA_UART4_HANDLER)
+#error "TIVA_UART4_HANDLER not defined"
+#endif
+/**
+ * @brief   UART4 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_UART4_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  uart_serve_interrupt(&UARTD5);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_UART_USE_UART5 || defined(__DOXYGEN__)
+#if !defined(TIVA_UART5_HANDLER)
+#error "TIVA_UART5_HANDLER not defined"
+#endif
+/**
+ * @brief   UART5 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_UART5_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  uart_serve_interrupt(&UARTD6);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_UART_USE_UART6 || defined(__DOXYGEN__)
+#if !defined(TIVA_UART6_HANDLER)
+#error "TIVA_UART6_HANDLER not defined"
+#endif
+/**
+ * @brief   UART6 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_UART6_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  uart_serve_interrupt(&UARTD7);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_UART_USE_UART7 || defined(__DOXYGEN__)
+#if !defined(TIVA_UART7_HANDLER)
+#error "TIVA_UART7_HANDLER not defined"
+#endif
+/**
+ * @brief   UART7 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_UART7_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  uart_serve_interrupt(&UARTD8);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level UART driver initialization.
+ *
+ * @notapi
+ */
+void uart_lld_init(void)
+{
+#if TIVA_UART_USE_UART0
+  uartObjectInit(&UARTD1);
+  UARTD1.uart    = UART0_BASE;
+  UARTD1.dmarxnr = TIVA_UART_UART0_RX_UDMA_CHANNEL;
+  UARTD1.dmatxnr = TIVA_UART_UART0_TX_UDMA_CHANNEL;
+  UARTD1.rxchnmap = TIVA_UART_UART0_RX_UDMA_MAPPING;
+  UARTD1.txchnmap = TIVA_UART_UART0_TX_UDMA_MAPPING;
+#endif
+#if TIVA_UART_USE_UART1
+  uartObjectInit(&UARTD2);
+  UARTD2.uart    = UART1_BASE;
+  UARTD2.dmarxnr = TIVA_UART_UART1_RX_UDMA_CHANNEL;
+  UARTD2.dmatxnr = TIVA_UART_UART1_TX_UDMA_CHANNEL;
+  UARTD2.rxchnmap = TIVA_UART_UART1_RX_UDMA_MAPPING;
+  UARTD2.txchnmap = TIVA_UART_UART1_TX_UDMA_MAPPING;
+#endif
+#if TIVA_UART_USE_UART2
+  uartObjectInit(&UARTD3);
+  UARTD2.uart    = UART2_BASE;
+  UARTD2.dmarxnr = TIVA_UART_UART2_RX_UDMA_CHANNEL;
+  UARTD2.dmatxnr = TIVA_UART_UART2_TX_UDMA_CHANNEL;
+  UARTD2.rxchnmap = TIVA_UART_UART2_RX_UDMA_MAPPING;
+  UARTD2.txchnmap = TIVA_UART_UART2_TX_UDMA_MAPPING;
+#endif
+#if TIVA_UART_USE_UART3
+  uartObjectInit(&UARTD4);
+  UARTD4.uart    = UART3_BASE;
+  UARTD4.dmarxnr = TIVA_UART_UART3_RX_UDMA_CHANNEL;
+  UARTD4.dmatxnr = TIVA_UART_UART3_TX_UDMA_CHANNEL;
+  UARTD4.rxchnmap = TIVA_UART_UART3_RX_UDMA_MAPPING;
+  UARTD4.txchnmap = TIVA_UART_UART3_TX_UDMA_MAPPING;
+#endif
+#if TIVA_UART_USE_UART4
+  uartObjectInit(&UARTD5);
+  UARTD5.uart    = UART4_BASE;
+  UARTD5.dmarxnr = TIVA_UART_UART4_RX_UDMA_CHANNEL;
+  UARTD5.dmatxnr = TIVA_UART_UART4_TX_UDMA_CHANNEL;
+  UARTD5.rxchnmap = TIVA_UART_UART4_RX_UDMA_MAPPING;
+  UARTD5.txchnmap = TIVA_UART_UART4_TX_UDMA_MAPPING;
+#endif
+#if TIVA_UART_USE_UART5
+  uartObjectInit(&UARTD6);
+  UARTD6.uart    = UART5_BASE;
+  UARTD6.dmarxnr = TIVA_UART_UART5_RX_UDMA_CHANNEL;
+  UARTD6.dmatxnr = TIVA_UART_UART5_TX_UDMA_CHANNEL;
+  UARTD6.rxchnmap = TIVA_UART_UART5_RX_UDMA_MAPPING;
+  UARTD6.txchnmap = TIVA_UART_UART5_TX_UDMA_MAPPING;
+#endif
+#if TIVA_UART_USE_UART6
+  uartObjectInit(&UARTD7);
+  UARTD7.uart    = UART6_BASE;
+  UARTD7.dmarxnr = TIVA_UART_UART6_RX_UDMA_CHANNEL;
+  UARTD7.dmatxnr = TIVA_UART_UART6_TX_UDMA_CHANNEL;
+  UARTD7.rxchnmap = TIVA_UART_UART6_RX_UDMA_MAPPING;
+  UARTD7.txchnmap = TIVA_UART_UART6_TX_UDMA_MAPPING;
+#endif
+#if TIVA_UART_USE_UART7
+  uartObjectInit(&UARTD8);
+  UARTD8.uart    = UART7_BASE;
+  UARTD8.dmarxnr = TIVA_UART_UART7_RX_UDMA_CHANNEL;
+  UARTD8.dmatxnr = TIVA_UART_UART7_TX_UDMA_CHANNEL;
+  UARTD8.rxchnmap = TIVA_UART_UART7_RX_UDMA_MAPPING;
+  UARTD8.txchnmap = TIVA_UART_UART7_TX_UDMA_MAPPING;
+#endif
+}
+
+/**
+ * @brief   Configures and activates the UART peripheral.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ *
+ * @notapi
+ */
+void uart_lld_start(UARTDriver *uartp) {
+
+  if (uartp->state == UART_STOP) {
+#if TIVA_UART_USE_UART0
+    if (&UARTD1 == uartp) {
+      bool b;
+      b = udmaChannelAllocate(uartp->dmarxnr);
+      osalDbgAssert(!b, "channel already allocated");
+      b = udmaChannelAllocate(uartp->dmatxnr);
+      osalDbgAssert(!b, "channel already allocated");
+
+      HWREG(SYSCTL_RCGCUART) |= (1 << 0);
+
+      while (!(HWREG(SYSCTL_PRUART) & (1 << 0)))
+        ;
+
+      nvicEnableVector(TIVA_UART0_NUMBER, TIVA_UART_UART0_PRIORITY);
+    }
+#endif
+#if TIVA_UART_USE_UART1
+    if (&UARTD2 == uartp) {
+      bool b;
+      b = udmaChannelAllocate(uartp->dmarxnr);
+      osalDbgAssert(!b, "channel already allocated");
+      b = udmaChannelAllocate(uartp->dmatxnr);
+      osalDbgAssert(!b, "channel already allocated");
+
+      HWREG(SYSCTL_RCGCUART) |= (1 << 1);
+
+      while (!(HWREG(SYSCTL_PRUART) & (1 << 1)))
+        ;
+
+      nvicEnableVector(TIVA_UART1_NUMBER, TIVA_UART_UART1_PRIORITY);
+    }
+#endif
+#if TIVA_UART_USE_UART2
+    if (&UARTD3 == uartp) {
+      bool b;
+      b = udmaChannelAllocate(uartp->dmarxnr);
+      osalDbgAssert(!b, "channel already allocated");
+      b = udmaChannelAllocate(uartp->dmatxnr);
+      osalDbgAssert(!b, "channel already allocated");
+
+      HWREG(SYSCTL_RCGCUART) |= (1 << 2);
+
+      while (!(HWREG(SYSCTL_PRUART) & (1 << 2)))
+        ;
+
+      nvicEnableVector(TIVA_UART2_NUMBER, TIVA_UART_UART2_PRIORITY);
+    }
+#endif
+#if TIVA_UART_USE_UART3
+    if (&UARTD4 == uartp) {
+      bool b;
+      b = udmaChannelAllocate(uartp->dmarxnr);
+      osalDbgAssert(!b, "channel already allocated");
+      b = udmaChannelAllocate(uartp->dmatxnr);
+      osalDbgAssert(!b, "channel already allocated");
+
+      HWREG(SYSCTL_RCGCUART) |= (1 << 3);
+
+      while (!(HWREG(SYSCTL_PRUART) & (1 << 3)))
+        ;
+
+      nvicEnableVector(TIVA_UART3_NUMBER, TIVA_UART_UART3_PRIORITY);
+    }
+#endif
+#if TIVA_UART_USE_UART4
+    if (&UARTD5 == uartp) {
+      bool b;
+      b = udmaChannelAllocate(uartp->dmarxnr);
+      osalDbgAssert(!b, "channel already allocated");
+      b = udmaChannelAllocate(uartp->dmatxnr);
+      osalDbgAssert(!b, "channel already allocated");
+
+      HWREG(SYSCTL_RCGCUART) |= (1 << 4);
+
+      while (!(HWREG(SYSCTL_PRUART) & (1 << 4)))
+        ;
+
+      nvicEnableVector(TIVA_UART4_NUMBER, TIVA_UART_UART4_PRIORITY);
+    }
+#endif
+#if TIVA_UART_USE_UART5
+    if (&UARTD6 == uartp) {
+      bool b;
+      b = udmaChannelAllocate(uartp->dmarxnr);
+      osalDbgAssert(!b, "channel already allocated");
+      b = udmaChannelAllocate(uartp->dmatxnr);
+      osalDbgAssert(!b, "channel already allocated");
+
+      HWREG(SYSCTL_RCGCUART) |= (1 << 5);
+
+      while (!(HWREG(SYSCTL_PRUART) & (1 << 5)))
+        ;
+
+      nvicEnableVector(TIVA_UART5_NUMBER, TIVA_UART_UART5_PRIORITY);
+    }
+#endif
+#if TIVA_UART_USE_UART6
+    if (&UARTD7 == uartp) {
+      bool b;
+      b = udmaChannelAllocate(uartp->dmarxnr);
+      osalDbgAssert(!b, "channel already allocated");
+      b = udmaChannelAllocate(uartp->dmatxnr);
+      osalDbgAssert(!b, "channel already allocated");
+
+      HWREG(SYSCTL_RCGCUART) |= (1 << 6);
+
+      while (!(HWREG(SYSCTL_PRUART) & (1 << 6)))
+        ;
+
+      nvicEnableVector(TIVA_UART6_NUMBER, TIVA_UART_UART6_PRIORITY);
+    }
+#endif
+#if TIVA_UART_USE_UART7
+    if (&UARTD8 == uartp) {
+      bool b;
+      b = udmaChannelAllocate(uartp->dmarxnr);
+      osalDbgAssert(!b, "channel already allocated");
+      b = udmaChannelAllocate(uartp->dmatxnr);
+      osalDbgAssert(!b, "channel already allocated");
+
+      HWREG(SYSCTL_RCGCUART) |= (1 << 7);
+
+      while (!(HWREG(SYSCTL_PRUART) & (1 << 7)))
+        ;
+
+      nvicEnableVector(TIVA_UART7_NUMBER, TIVA_UART_UART7_PRIORITY);
+    }
+#endif
+
+    uartp->rxbuf = 0;
+
+    HWREG(UDMA_CHMAP0 + (uartp->dmarxnr / 8) * 4) |= (uartp->rxchnmap << (uartp->dmarxnr % 8));
+    HWREG(UDMA_CHMAP0 + (uartp->dmatxnr / 8) * 4) |= (uartp->txchnmap << (uartp->dmatxnr % 8));
+  }
+
+  uartp->rxstate = UART_RX_IDLE;
+  uartp->txstate = UART_TX_IDLE;
+  uart_init(uartp);
+}
+
+/**
+ * @brief   Deactivates the UART peripheral.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ *
+ * @notapi
+ */
+void uart_lld_stop(UARTDriver *uartp) {
+
+  if (uartp->state == UART_READY) {
+    uart_stop(uartp);
+    udmaChannelRelease(uartp->dmarxnr);
+    udmaChannelRelease(uartp->dmatxnr);
+
+#if TIVA_UART_USE_UART0
+    if (&UARTD1 == uartp) {
+      HWREG(SYSCTL_RCGCUART) &= ~(1 << 0);
+      return;
+    }
+#endif
+#if TIVA_UART_USE_UART1
+    if (&UARTD2 == uartp) {
+      HWREG(SYSCTL_RCGCUART) &= ~(1 << 1);
+      return;
+    }
+#endif
+#if TIVA_UART_USE_UART2
+    if (&UARTD3 == uartp) {
+      HWREG(SYSCTL_RCGCUART) &= ~(1 << 2);
+      return;
+    }
+#endif
+#if TIVA_UART_USE_UART3
+    if (&UARTD4 == uartp) {
+      HWREG(SYSCTL_RCGCUART) &= ~(1 << 3);
+      return;
+    }
+#endif
+#if TIVA_UART_USE_UART4
+    if (&UARTD5 == uartp) {
+      HWREG(SYSCTL_RCGCUART) &= ~(1 << 4);
+      return;
+    }
+#endif
+#if TIVA_UART_USE_UART5
+    if (&UARTD6 == uartp) {
+      HWREG(SYSCTL_RCGCUART) &= ~(1 << 5);
+      return;
+    }
+#endif
+#if TIVA_UART_USE_UART6
+    if (&UARTD7 == uartp) {
+      HWREG(SYSCTL_RCGCUART) &= ~(1 << 6);
+      return;
+    }
+#endif
+#if TIVA_UART_USE_UART7
+    if (&UARTD8 == uartp) {
+      HWREG(SYSCTL_RCGCUART) &= ~(1 << 7);
+      return;
+    }
+#endif
+  }
+}
+
+/**
+ * @brief   Starts a transmission on the UART peripheral.
+ * @note    The buffers are organized as uint8_t arrays for data sizes below
+ *          or equal to 8 bits else it is organized as uint16_t arrays.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ * @param[in] n         number of data frames to send
+ * @param[in] txbuf     the pointer to the transmit buffer
+ *
+ * @notapi
+ */
+void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf)
+{
+  tiva_udma_table_entry_t *primary = udmaControlTable.primary;
+
+  /* TODO: This assert should be moved to the dma helper driver */
+  osalDbgAssert((uint32_t)txbuf >= SRAM_BASE, "txbuf should be in SRAM region.");
+
+  dmaChannelDisable(uartp->dmatxnr);
+
+  /* Configure for 8-bit transfers.*/
+  primary[uartp->dmatxnr].srcendp = (volatile void *)txbuf+n-1;
+  primary[uartp->dmatxnr].dstendp = (void *)(uartp->uart + UART_O_DR);
+  primary[uartp->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_NONE |
+                                  UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_8 |
+                                  UDMA_CHCTL_ARBSIZE_4 |
+                                  UDMA_CHCTL_XFERSIZE(n) |
+                                  UDMA_CHCTL_XFERMODE_BASIC;
+
+  dmaChannelSingleBurst(uartp->dmatxnr);
+  dmaChannelPrimary(uartp->dmatxnr);
+  dmaChannelPriorityDefault(uartp->dmatxnr);
+  dmaChannelEnableRequest(uartp->dmatxnr);
+
+  /* Enable DMA channel, transfer starts immediately.*/
+  dmaChannelEnable(uartp->dmatxnr);
+}
+
+/**
+ * @brief   Stops any ongoing transmission.
+ * @note    Stopping a transmission also suppresses the transmission callbacks.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ *
+ * @return              The number of data frames not transmitted by the
+ *                      stopped transmit operation.
+ *
+ * @notapi
+ */
+size_t uart_lld_stop_send(UARTDriver *uartp)
+{
+  tiva_udma_table_entry_t *primary = udmaControlTable.primary;
+  uint16_t left;
+
+  dmaChannelDisable(uartp->dmatxnr);
+
+  left = ((primary[uartp->dmatxnr].chctl & UDMA_CHCTL_XFERSIZE_M) + 1) >> 4;
+
+  return left;
+}
+
+/**
+ * @brief   Starts a receive operation on the UART peripheral.
+ * @note    The buffers are organized as uint8_t arrays for data sizes below
+ *          or equal to 8 bits else it is organized as uint16_t arrays.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ * @param[in] n         number of data frames to send
+ * @param[out] rxbuf    the pointer to the receive buffer
+ *
+ * @notapi
+ */
+void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf)
+{
+  tiva_udma_table_entry_t *primary = udmaControlTable.primary;
+
+  /* TODO: This assert should be moved to the dma helper driver */
+  osalDbgAssert((uint32_t)rxbuf >= SRAM_BASE, "rxbuf should be in SRAM region.");
+
+  dmaChannelDisable(uartp->dmarxnr);
+
+  /* Configure for 8-bit transfers.*/
+  primary[uartp->dmarxnr].srcendp = (void *)(uartp->uart + UART_O_DR);
+  primary[uartp->dmarxnr].dstendp = (volatile void *)rxbuf+n-1;
+  primary[uartp->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_8 |
+                                  UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_NONE |
+                                  UDMA_CHCTL_ARBSIZE_4 |
+                                  UDMA_CHCTL_XFERSIZE(n) |
+                                  UDMA_CHCTL_XFERMODE_BASIC;
+
+  dmaChannelSingleBurst(uartp->dmarxnr);
+  dmaChannelPrimary(uartp->dmarxnr);
+  dmaChannelPriorityDefault(uartp->dmarxnr);
+  dmaChannelEnableRequest(uartp->dmarxnr);
+
+  /* Enable DMA channel, transfer starts immediately.*/
+  dmaChannelEnable(uartp->dmarxnr);
+}
+
+/**
+ * @brief   Stops any ongoing receive operation.
+ * @note    Stopping a receive operation also suppresses the receive callbacks.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ *
+ * @return              The number of data frames not received by the
+ *                      stopped receive operation.
+ *
+ * @notapi
+ */
+size_t uart_lld_stop_receive(UARTDriver *uartp)
+{
+  tiva_udma_table_entry_t *primary = udmaControlTable.primary;
+  uint16_t left;
+
+  dmaChannelDisable(uartp->dmatxnr);
+
+  left = ((primary[uartp->dmatxnr].chctl & UDMA_CHCTL_XFERSIZE_M) + 1) >> 4;
+
+  uart_enter_rx_idle_loop(uartp);
+
+  return left;
+}
+
+#endif /* HAL_USE_UART */
+
+/** @} */
diff --git a/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.h b/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.h
new file mode 100644
index 0000000..1dc743b
--- /dev/null
+++ b/os/hal/ports/TIVA/LLD/UART/hal_uart_lld.h
@@ -0,0 +1,471 @@
+/*
+    Copyright (C) 2014..2017 Marco Veeneman
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    UART/hal_uart_lld.h
+ * @brief   Tiva low level UART driver header.
+ *
+ * @addtogroup UART
+ * @{
+ */
+
+#ifndef HAL_UART_LLD_H
+#define HAL_UART_LLD_H
+
+#if HAL_USE_UART || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   UART driver on UART0 enable switch.
+ * @details If set to @p TRUE the support for UART0 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_UART_USE_UART0) || defined(__DOXYGEN__)
+#define TIVA_UART_USE_UART0               FALSE
+#endif
+
+/**
+ * @brief   UART driver on UART1 enable switch.
+ * @details If set to @p TRUE the support for UART1 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_UART_USE_UART1) || defined(__DOXYGEN__)
+#define TIVA_UART_USE_UART1               FALSE
+#endif
+
+/**
+ * @brief   UART driver on UART2 enable switch.
+ * @details If set to @p TRUE the support for UART2 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_UART_USE_UART2) || defined(__DOXYGEN__)
+#define TIVA_UART_USE_UART2               FALSE
+#endif
+
+/**
+ * @brief   UART driver on UART3 enable switch.
+ * @details If set to @p TRUE the support for UART3 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_UART_USE_UART3) || defined(__DOXYGEN__)
+#define TIVA_UART_USE_UART3               FALSE
+#endif
+
+/**
+ * @brief   UART driver on UART4 enable switch.
+ * @details If set to @p TRUE the support for UART4 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_UART_USE_UART4) || defined(__DOXYGEN__)
+#define TIVA_UART_USE_UART4               FALSE
+#endif
+
+/**
+ * @brief   UART driver on UART5 enable switch.
+ * @details If set to @p TRUE the support for UART5 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_UART_USE_UART5) || defined(__DOXYGEN__)
+#define TIVA_UART_USE_UART5               FALSE
+#endif
+
+/**
+ * @brief   UART driver on UART6 enable switch.
+ * @details If set to @p TRUE the support for UART6 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_UART_USE_UART6) || defined(__DOXYGEN__)
+#define TIVA_UART_USE_UART6               FALSE
+#endif
+
+/**
+ * @brief   UART driver on UART7 enable switch.
+ * @details If set to @p TRUE the support for UART7 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(TIVA_UART_USE_UART7) || defined(__DOXYGEN__)
+#define TIVA_UART_USE_UART7               FALSE
+#endif
+
+/**
+ * @brief   UART0 interrupt priority level setting.
+ */
+#if !defined(TIVA_UART_UART0_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_UART_UART0_IRQ_PRIORITY      5
+#endif
+
+/**
+ * @brief   UART1 interrupt priority level setting.
+ */
+#if !defined(TIVA_UART_UART1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_UART_UART1_IRQ_PRIORITY      5
+#endif
+
+/**
+ * @brief   UART2 interrupt priority level setting.
+ */
+#if !defined(TIVA_UART_UART2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_UART_UART2_IRQ_PRIORITY      5
+#endif
+
+/**
+ * @brief   UART3 interrupt priority level setting.
+ */
+#if !defined(TIVA_UART_UART3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_UART_UART3_IRQ_PRIORITY      5
+#endif
+
+/**
+ * @brief   UART4 interrupt priority level setting.
+ */
+#if !defined(TIVA_UART_UART4_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_UART_UART4_IRQ_PRIORITY      5
+#endif
+
+/**
+ * @brief   UART5 interrupt priority level setting.
+ */
+#if !defined(TIVA_UART_UART5_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_UART_UART5_IRQ_PRIORITY      5
+#endif
+
+/**
+ * @brief   UART6 interrupt priority level setting.
+ */
+#if !defined(TIVA_UART_UART6_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_UART_UART6_IRQ_PRIORITY      5
+#endif
+
+/**
+ * @brief   UART7 interrupt priority level setting.
+ */
+#if !defined(TIVA_UART_UART7_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_UART_UART7_IRQ_PRIORITY      5
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if TIVA_UART_USE_UART0 && !TIVA_HAS_UART0
+#error "UART0 not present in the selected device"
+#endif
+
+#if TIVA_UART_USE_UART1 && !TIVA_HAS_UART1
+#error "UART1 not present in the selected device"
+#endif
+
+#if TIVA_UART_USE_UART2 && !TIVA_HAS_UART2
+#error "UART2 not present in the selected device"
+#endif
+
+#if TIVA_UART_USE_UART3 && !TIVA_HAS_UART3
+#error "UART3 not present in the selected device"
+#endif
+
+#if TIVA_UART_USE_UART4 && !TIVA_HAS_UART4
+#error "UART4 not present in the selected device"
+#endif
+
+#if TIVA_UART_USE_UART5 && !TIVA_HAS_UART5
+#error "UART5 not present in the selected device"
+#endif
+
+#if TIVA_UART_USE_UART6 && !TIVA_HAS_UART6
+#error "UART6 not present in the selected device"
+#endif
+
+#if TIVA_UART_USE_UART7 && !TIVA_HAS_UART7
+#error "UART7 not present in the selected device"
+#endif
+
+#if !TIVA_UART_USE_UART0 && !TIVA_UART_USE_UART1 && !TIVA_UART_USE_UART2 && \
+    !TIVA_UART_USE_UART3 && !TIVA_UART_USE_UART4 && !TIVA_UART_USE_UART5 && \
+    !TIVA_UART_USE_UART6 && !TIVA_UART_USE_UART7
+#error "UART driver activated but no UART peripheral assigned"
+#endif
+
+#if TIVA_UART_USE_UART0 &&                                                \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART0_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to UART0"
+#endif
+
+#if TIVA_UART_USE_UART1 &&                                                \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to UART1"
+#endif
+
+#if TIVA_UART_USE_UART2 &&                                                \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to UART2"
+#endif
+
+#if TIVA_UART_USE_UART3 &&                                                \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART3_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to UART3"
+#endif
+
+#if TIVA_UART_USE_UART4 &&                                                \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART4_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to UART4"
+#endif
+
+#if TIVA_UART_USE_UART5 &&                                                \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART5_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to UART5"
+#endif
+
+#if TIVA_UART_USE_UART6 &&                                                \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART6_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to UART6"
+#endif
+
+#if TIVA_UART_USE_UART7 &&                                                \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_UART_UART7_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to UART7"
+#endif
+
+#if !defined(TIVA_UDMA_REQUIRED)
+#define TIVA_UDMA_REQUIRED
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   UART driver condition flags type.
+ */
+typedef uint32_t uartflags_t;
+
+/**
+ * @brief   Structure representing an UART driver.
+ */
+typedef struct UARTDriver UARTDriver;
+
+/**
+ * @brief   Generic UART notification callback type.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ */
+typedef void (*uartcb_t)(UARTDriver *uartp);
+
+/**
+ * @brief   Character received UART notification callback type.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ * @param[in] c         received character
+ */
+typedef void (*uartccb_t)(UARTDriver *uartp, uint16_t c);
+
+/**
+ * @brief   Receive error UART notification callback type.
+ *
+ * @param[in] uartp     pointer to the @p UARTDriver object
+ * @param[in] e         receive error mask
+ */
+typedef void (*uartecb_t)(UARTDriver *uartp, uartflags_t e);
+
+/**
+ * @brief   Driver configuration structure.
+ * @note    It could be empty on some architectures.
+ */
+typedef struct {
+  /**
+   * @brief   End of transmission buffer callback.
+   */
+  uartcb_t                  txend1_cb;
+  /**
+   * @brief   Physical end of transmission callback.
+   */
+  uartcb_t                  txend2_cb;
+  /**
+   * @brief   Receive buffer filled callback.
+   */
+  uartcb_t                  rxend_cb;
+  /**
+   * @brief   Character received while out if the @p UART_RECEIVE state.
+   */
+  uartccb_t                 rxchar_cb;
+  /**
+   * @brief   Receive error callback.
+   */
+  uartecb_t                 rxerr_cb;
+  /* End of the mandatory fields.*/
+  /**
+   * @brief Bit rate.
+   */
+  uint32_t                  speed;
+  /* End of the mandatory fields. */
+  /**
+   * @brief Initialization value for the CTL register.
+   */
+  uint16_t                  ctl;
+  /**
+   * @brief Initialization value for the LCRH register.
+   */
+  uint8_t                   lcrh;
+  /**
+   * @brief Initialization value for the IFLS register.
+   */
+  uint8_t                   ifls;
+  /**
+   * @brief Initialization value for the CC register.
+   */
+  uint8_t                   cc;
+} UARTConfig;
+
+/**
+ * @brief   Structure representing an UART driver.
+ */
+struct UARTDriver {
+  /**
+   * @brief   Driver state.
+   */
+  uartstate_t               state;
+  /**
+   * @brief   Transmitter state.
+   */
+  uarttxstate_t             txstate;
+  /**
+   * @brief   Receiver state.
+   */
+  uartrxstate_t             rxstate;
+  /**
+   * @brief   Current configuration data.
+   */
+  const UARTConfig          *config;
+#if (UART_USE_WAIT == TRUE) || defined(__DOXYGEN__)
+  /**
+   * @brief   Synchronization flag for transmit operations.
+   */
+  bool                      early;
+  /**
+   * @brief   Waiting thread on RX.
+   */
+  thread_reference_t        threadrx;
+  /**
+   * @brief   Waiting thread on TX.
+   */
+  thread_reference_t        threadtx;
+#endif /* UART_USE_WAIT */
+#if (UART_USE_MUTUAL_EXCLUSION == TRUE) || defined(__DOXYGEN__)
+  /**
+   * @brief   Mutex protecting the peripheral.
+   */
+  mutex_t                   mutex;
+#endif /* UART_USE_MUTUAL_EXCLUSION */
+#if defined(UART_DRIVER_EXT_FIELDS)
+  UART_DRIVER_EXT_FIELDS
+#endif
+  /* End of the mandatory fields.*/
+  /**
+   * @brief Pointer to the UART registers block.
+   */
+  uint32_t                  uart;
+  /**
+   * @brief Receive DMA channel number.
+   */
+  uint8_t                   dmarxnr;
+  /**
+   * @brief Transmit DMA channel number.
+   */
+  uint8_t                   dmatxnr;
+  /**
+   * @brief Receive DMA channel map.
+   */
+  uint8_t                   rxchnmap;
+  /**
+   * @brief Transmit DMA channel map.
+   */
+  uint8_t                   txchnmap;
+  /**
+   * @brief   Default receive buffer while into @p UART_RX_IDLE state.
+   */
+  volatile uint16_t         rxbuf;
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if TIVA_UART_USE_UART0 && !defined(__DOXYGEN__)
+extern UARTDriver UARTD1;
+#endif
+
+#if TIVA_UART_USE_UART1 && !defined(__DOXYGEN__)
+extern UARTDriver UARTD2;
+#endif
+
+#if TIVA_UART_USE_UART2 && !defined(__DOXYGEN__)
+extern UARTDriver UARTD3;
+#endif
+
+#if TIVA_UART_USE_UART3 && !defined(__DOXYGEN__)
+extern UARTDriver UARTD4;
+#endif
+
+#if TIVA_UART_USE_UART4 && !defined(__DOXYGEN__)
+extern UARTDriver UARTD5;
+#endif
+
+#if TIVA_UART_USE_UART5 && !defined(__DOXYGEN__)
+extern UARTDriver UARTD6;
+#endif
+
+#if TIVA_UART_USE_UART6 && !defined(__DOXYGEN__)
+extern UARTDriver UARTD7;
+#endif
+
+#if TIVA_UART_USE_UART7 && !defined(__DOXYGEN__)
+extern UARTDriver UARTD8;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void uart_lld_init(void);
+  void uart_lld_start(UARTDriver *uartp);
+  void uart_lld_stop(UARTDriver *uartp);
+  void uart_lld_start_send(UARTDriver *uartp, size_t n, const void *txbuf);
+  size_t uart_lld_stop_send(UARTDriver *uartp);
+  void uart_lld_start_receive(UARTDriver *uartp, size_t n, void *rxbuf);
+  size_t uart_lld_stop_receive(UARTDriver *uartp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_UART */
+
+#endif /* HAL_UART_LLD_H */
+
+/** @} */
-- 
cgit v1.2.3


From 96413f3767eeae21534946e4fb8b732cc1074039 Mon Sep 17 00:00:00 2001
From: Kaleb Elwert <belak@coded.io>
Date: Sat, 4 Nov 2017 10:41:06 -0700
Subject: Fix for K20x startup

---
 os/hal/ports/KINETIS/K20x/hal_lld.c | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

(limited to 'os')

diff --git a/os/hal/ports/KINETIS/K20x/hal_lld.c b/os/hal/ports/KINETIS/K20x/hal_lld.c
index e6eeed8..594f7af 100644
--- a/os/hal/ports/KINETIS/K20x/hal_lld.c
+++ b/os/hal/ports/KINETIS/K20x/hal_lld.c
@@ -148,11 +148,10 @@ void k20x_clock_init(void) {
    *       frequency, which would required other registers to be modified.
    */
   /* Enable OSC, low power mode */
-  MCG->C2 = MCG_C2_LOCRE0 | MCG_C2_EREFS0;
   if (KINETIS_XTAL_FREQUENCY > 8000000UL)
-    MCG->C2 |= MCG_C2_RANGE0(2);
+    MCG->C2 = MCG_C2_LOCRE0 | MCG_C2_EREFS0 | MCG_C2_RANGE0(2);
   else
-    MCG->C2 |= MCG_C2_RANGE0(1);
+    MCG->C2 = MCG_C2_LOCRE0 | MCG_C2_EREFS0 | MCG_C2_RANGE0(1);
 
   frdiv = 7;
   ratio = KINETIS_XTAL_FREQUENCY / 31250UL;
-- 
cgit v1.2.3


From 77bf52e0428392acc83bc12c4699b61dae43467e Mon Sep 17 00:00:00 2001
From: marcoveeneman <marco-veeneman@hotmail.com>
Date: Thu, 23 Nov 2017 21:47:09 +0100
Subject: Updated startup makefiles with new path to CMSIS Core headers

---
 os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk | 2 +-
 os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'os')

diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk
index 263338a..6464c5e 100644
--- a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk
+++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk
@@ -6,7 +6,7 @@ STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S
 
 STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
              $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/TM4C123x \
-             $(CHIBIOS)/os/common/ext/CMSIS/include \
+             $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
              $(CHIBIOS_CONTRIB)/os/common/ext/TivaWare
 
 STARTUPLD  = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk
index 6cf42f7..5cc9a1f 100644
--- a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk
+++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk
@@ -6,7 +6,7 @@ STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S
 
 STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
              $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/TM4C129x \
-             $(CHIBIOS)/os/common/ext/CMSIS/include \
+             $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
              $(CHIBIOS_CONTRIB)/os/common/ext/TivaWare
 
 STARTUPLD  = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
-- 
cgit v1.2.3


From 19efef2f4a09244023a25086fd8ebabd4c38d982 Mon Sep 17 00:00:00 2001
From: marcoveeneman <marco-veeneman@hotmail.com>
Date: Fri, 24 Nov 2017 22:25:12 +0100
Subject: Fixed hal_i2c_lld.c

---
 os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

(limited to 'os')

diff --git a/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c
index fd7395f..7ba7bad 100644
--- a/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c
+++ b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c
@@ -778,7 +778,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
 
   /* Calculating the time window for the timeout on the busy bus condition.*/
   start = osalOsGetSystemTimeX();
-  end = start + OSAL_MS2ST(TIVA_I2C_BUSY_TIMEOUT);
+  end = start + OSAL_MS2I(TIVA_I2C_BUSY_TIMEOUT);
 
   /* Waits until BUSY flag is reset or, alternatively, for a timeout
      condition.*/
@@ -792,7 +792,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr,
 
     /* If the system time went outside the allowed window then a timeout
        condition is returned.*/
-    if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), start, end))
+    if (!osalTimeIsInRangeX(osalOsGetSystemTimeX(), start, end))
       return MSG_TIMEOUT;
 
     osalSysUnlock();
@@ -852,7 +852,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
 
   /* Calculating the time window for the timeout on the busy bus condition.*/
   start = osalOsGetSystemTimeX();
-  end = start + OSAL_MS2ST(TIVA_I2C_BUSY_TIMEOUT);
+  end = start + OSAL_MS2I(TIVA_I2C_BUSY_TIMEOUT);
 
   /* Waits until BUSY flag is reset or, alternatively, for a timeout
      condition.*/
@@ -866,7 +866,8 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr,
 
     /* If the system time went outside the allowed window then a timeout
        condition is returned.*/
-    if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), start, end))
+    if (!osalTimeIsInRangeX(osalOsGetSystemTimeX(), start, end))
+
       return MSG_TIMEOUT;
 
     osalSysUnlock();
-- 
cgit v1.2.3


From c4eb6b4901da49fa69f2d5778ee9b32d7b9a126f Mon Sep 17 00:00:00 2001
From: Wim Lewis <wiml@hhhh.org>
Date: Fri, 8 Dec 2017 19:42:13 -0800
Subject: Added support for additional UARTs (up to six on the K64F). Also
 moved some code that is duplicated per-UART into local functions to reduce
 the amount of duplication.

---
 os/hal/ports/KINETIS/LLD/hal_serial_lld.c | 251 +++++++++++++++++++++---------
 os/hal/ports/KINETIS/LLD/hal_serial_lld.h |  69 +++++++-
 2 files changed, 248 insertions(+), 72 deletions(-)

(limited to 'os')

diff --git a/os/hal/ports/KINETIS/LLD/hal_serial_lld.c b/os/hal/ports/KINETIS/LLD/hal_serial_lld.c
index c80cf22..c92fa5c 100644
--- a/os/hal/ports/KINETIS/LLD/hal_serial_lld.c
+++ b/os/hal/ports/KINETIS/LLD/hal_serial_lld.c
@@ -1,5 +1,6 @@
 /*
     ChibiOS - Copyright (C) 2013-2015 Fabio Utzig
+              Copyright (C) 2017 Wim Lewis
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -50,6 +51,18 @@ SerialDriver SD2;
 SerialDriver SD3;
 #endif
 
+#if KINETIS_SERIAL_USE_UART3 || defined(__DOXYGEN__)
+SerialDriver SD4;
+#endif
+
+#if KINETIS_SERIAL_USE_UART4 || defined(__DOXYGEN__)
+SerialDriver SD5;
+#endif
+
+#if KINETIS_SERIAL_USE_UART5 || defined(__DOXYGEN__)
+SerialDriver SD6;
+#endif
+
 /*===========================================================================*/
 /* Driver local variables and types.                                         */
 /*===========================================================================*/
@@ -95,33 +108,37 @@ static void serve_error_interrupt(SerialDriver *sdp) {
   UART_w_TypeDef *u = &(sdp->uart);
   uint8_t s1 = *(u->s1_p);
 
-  /* S1 bits are write-1-to-clear for UART0 on KL2x. */
-  /* Clearing on K20x and KL2x/UART>0 is done by reading S1 and
+  /* Clearing on K20x, K60x, and KL2x/UART>0 is done by reading S1 and
    * then reading D.*/
 
-#if defined(KL2x) && KINETIS_SERIAL_USE_UART0
-  if(sdp == &SD1) {
-    if(s1 & UARTx_S1_IDLE) {
-      *(u->s1_p) |= UARTx_S1_IDLE;
-    }
+  if(s1 & UARTx_S1_IDLE) {
+    (void)*(u->d_p);
+  }
 
-    if(s1 & (UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF)) {
-      set_error(sdp, s1);
-      *(u->s1_p) |= UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF;
-    }
-    return;
+  if(s1 & (UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF)) {
+    set_error(sdp, s1);
+    (void)*(u->d_p);
   }
-#endif /* KL2x && KINETIS_SERIAL_USE_UART0 */
+}
+
+#if defined(KL2x) && KINETIS_SERIAL_USE_UART0
+static void serve_error_interrupt_uart0(void) {
+  SerialDriver *sdp = &SD1;
+  UART_w_TypeDef *u = &(sdp->uart);
+  uint8_t s1 = *(u->s1_p);
+
+  /* S1 bits are write-1-to-clear for UART0 on KL2x. */
 
   if(s1 & UARTx_S1_IDLE) {
-    (void)*(u->d_p);
+    *(u->s1_p) |= UARTx_S1_IDLE;
   }
 
   if(s1 & (UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF)) {
     set_error(sdp, s1);
-    (void)*(u->d_p);
+    *(u->s1_p) |= UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF;
   }
 }
+#endif /* KL2x && KINETIS_SERIAL_USE_UART0 */
 
 /**
  * @brief   Common IRQ handler.
@@ -161,6 +178,12 @@ static void serve_interrupt(SerialDriver *sdp) {
     }
   }
 
+#if defined(KL2x) && KINETIS_SERIAL_USE_UART0
+  if (sdp == &SD1) {
+    serve_error_interrupt_uart0();
+    return;
+  }
+#endif
   serve_error_interrupt(sdp);
 }
 
@@ -184,29 +207,28 @@ static void preload(SerialDriver *sdp) {
 /**
  * @brief   Driver output notification.
  */
-#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-static void notify1(io_queue_t *qp)
+static void notify(io_queue_t *qp)
 {
-  (void)qp;
-  preload(&SD1);
+  preload(qp->q_link);
 }
-#endif
 
-#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
-static void notify2(io_queue_t *qp)
-{
-  (void)qp;
-  preload(&SD2);
-}
-#endif
-
-#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
-static void notify3(io_queue_t *qp)
-{
-  (void)qp;
-  preload(&SD3);
+/**
+ * @brief   Common driver initialization, except LP.
+ */
+static void sd_lld_init_driver(SerialDriver *SDn, UART_TypeDef *UARTn) {
+  /* Driver initialization.*/
+  sdObjectInit(SDn, NULL, notify);
+  SDn->uart.bdh_p = &(UARTn->BDH);
+  SDn->uart.bdl_p = &(UARTn->BDL);
+  SDn->uart.c1_p =  &(UARTn->C1);
+  SDn->uart.c2_p =  &(UARTn->C2);
+  SDn->uart.c3_p =  &(UARTn->C3);
+  SDn->uart.c4_p =  &(UARTn->C4);
+  SDn->uart.s1_p =  (volatile uint8_t *)&(UARTn->S1);
+  SDn->uart.s2_p =  &(UARTn->S2);
+  SDn->uart.d_p =   &(UARTn->D);
+  SDn->uart.uart_p = UARTn;
 }
-#endif
 
 /**
  * @brief   Common UART configuration.
@@ -240,9 +262,9 @@ static void configure_uart(SerialDriver *sdp, const SerialConfig *config) {
   }
 #endif /* KINETIS_SERIAL_USE_UART0 */
 
-#elif defined(K20x) /* KL2x */
+#elif defined(K20x) || defined(K60x) /* KL2x */
 
-  /* UARTs 0 and 1 are clocked from SYSCLK, others from BUSCLK on K20x. */
+  /* UARTs 0 and 1 are clocked from SYSCLK, others from BUSCLK on K20x and K60x. */
 #if KINETIS_SERIAL_USE_UART0
   if(sdp == &SD1)
     divisor = KINETIS_SYSCLK_FREQUENCY;
@@ -260,9 +282,9 @@ static void configure_uart(SerialDriver *sdp, const SerialConfig *config) {
 
   *(uart->bdh_p) = UARTx_BDH_SBR(divisor >> 13) | (*(uart->bdh_p) & ~UARTx_BDH_SBR_MASK);
   *(uart->bdl_p) = UARTx_BDL_SBR(divisor >> 5);
-#if defined(K20x)
+#if defined(K20x) || defined(K60x)
   *(uart->c4_p) = UARTx_C4_BRFA(divisor) | (*(uart->c4_p) & ~UARTx_C4_BRFA_MASK);
-#endif /* K20x */
+#endif /* K20x, K60x */
 
   /* Line settings. */
   *(uart->c1_p) = 0;
@@ -300,12 +322,40 @@ OSAL_IRQ_HANDLER(KINETIS_SERIAL2_IRQ_VECTOR) {
 }
 #endif
 
+#if KINETIS_SERIAL_USE_UART3 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL3_IRQ_VECTOR) {
+  OSAL_IRQ_PROLOGUE();
+  serve_interrupt(&SD4);
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART4 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL4_IRQ_VECTOR) {
+  OSAL_IRQ_PROLOGUE();
+  serve_interrupt(&SD5);
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART5 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL5_IRQ_VECTOR) {
+  OSAL_IRQ_PROLOGUE();
+  serve_interrupt(&SD6);
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
 #if KINETIS_HAS_SERIAL_ERROR_IRQ
 
 #if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
 OSAL_IRQ_HANDLER(KINETIS_SERIAL0_ERROR_IRQ_VECTOR) {
   OSAL_IRQ_PROLOGUE();
+#if defined(KL2x)
+  serve_error_interrupt_uart0();
+#else
   serve_error_interrupt(&SD1);
+#endif
   OSAL_IRQ_EPILOGUE();
 }
 #endif
@@ -326,6 +376,30 @@ OSAL_IRQ_HANDLER(KINETIS_SERIAL2_ERROR_IRQ_VECTOR) {
 }
 #endif
 
+#if KINETIS_SERIAL_USE_UART3 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL3_ERROR_IRQ_VECTOR) {
+  OSAL_IRQ_PROLOGUE();
+  serve_error_interrupt(&SD4);
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART4 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL4_ERROR_IRQ_VECTOR) {
+  OSAL_IRQ_PROLOGUE();
+  serve_error_interrupt(&SD5);
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART5 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL5_ERROR_IRQ_VECTOR) {
+  OSAL_IRQ_PROLOGUE();
+  serve_error_interrupt(&SD6);
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
 #endif /* KINETIS_HAS_SERIAL_ERROR_IRQ */
 
 /*===========================================================================*/
@@ -341,19 +415,11 @@ void sd_lld_init(void) {
 
 #if KINETIS_SERIAL_USE_UART0
   /* Driver initialization.*/
-  sdObjectInit(&SD1, NULL, notify1);
 #if ! KINETIS_SERIAL0_IS_LPUART
-  SD1.uart.bdh_p = &(UART0->BDH);
-  SD1.uart.bdl_p = &(UART0->BDL);
-  SD1.uart.c1_p =  &(UART0->C1);
-  SD1.uart.c2_p =  &(UART0->C2);
-  SD1.uart.c3_p =  &(UART0->C3);
-  SD1.uart.c4_p =  &(UART0->C4);
-  SD1.uart.s1_p =  (volatile uint8_t *)&(UART0->S1);
-  SD1.uart.s2_p =  &(UART0->S2);
-  SD1.uart.d_p =   &(UART0->D);
+  sd_lld_init_driver(&SD1, UART0);
 #else /* ! KINETIS_SERIAL0_IS_LPUART */
   /* little endian! */
+  sdObjectInit(&SD1, NULL, notify);
   SD1.uart.bdh_p = ((uint8_t *)&(LPUART0->BAUD)) + 1; /* BDH: BAUD, byte 3 */
   SD1.uart.bdl_p = ((uint8_t *)&(LPUART0->BAUD)) + 0; /* BDL: BAUD, byte 4 */
   SD1.uart.c1_p =  ((uint8_t *)&(LPUART0->CTRL)) + 0; /* C1: CTRL, byte 4 */
@@ -377,20 +443,11 @@ void sd_lld_init(void) {
 
 #if KINETIS_SERIAL_USE_UART1
   /* Driver initialization.*/
-  sdObjectInit(&SD2, NULL, notify2);
 #if ! KINETIS_SERIAL1_IS_LPUART
-  SD2.uart.bdh_p = &(UART1->BDH);
-  SD2.uart.bdl_p = &(UART1->BDL);
-  SD2.uart.c1_p =  &(UART1->C1);
-  SD2.uart.c2_p =  &(UART1->C2);
-  SD2.uart.c3_p =  &(UART1->C3);
-  SD2.uart.c4_p =  &(UART1->C4);
-  SD2.uart.s1_p =  (volatile uint8_t *)&(UART1->S1);
-  SD2.uart.s2_p =  &(UART1->S2);
-  SD2.uart.d_p =   &(UART1->D);
-  SD2.uart.uart_p = UART1;
+  sd_lld_init_driver(&SD2, UART1);
 #else /* ! KINETIS_SERIAL1_IS_LPUART */
   /* little endian! */
+  sdObjectInit(&SD2, NULL, notify);
   SD2.uart.bdh_p = ((uint8_t *)&(LPUART1->BAUD)) + 1; /* BDH: BAUD, byte 3 */
   SD2.uart.bdl_p = ((uint8_t *)&(LPUART1->BAUD)) + 0; /* BDL: BAUD, byte 4 */
   SD2.uart.c1_p =  ((uint8_t *)&(LPUART1->CTRL)) + 0; /* C1: CTRL, byte 4 */
@@ -406,19 +463,20 @@ void sd_lld_init(void) {
 #endif /* KINETIS_SERIAL_USE_UART1 */
 
 #if KINETIS_SERIAL_USE_UART2
-  /* Driver initialization.*/
-  sdObjectInit(&SD3, NULL, notify3);
-  SD3.uart.bdh_p = &(UART2->BDH);
-  SD3.uart.bdl_p = &(UART2->BDL);
-  SD3.uart.c1_p =  &(UART2->C1);
-  SD3.uart.c2_p =  &(UART2->C2);
-  SD3.uart.c3_p =  &(UART2->C3);
-  SD3.uart.c4_p =  &(UART2->C4);
-  SD3.uart.s1_p =  (volatile uint8_t *)&(UART2->S1);
-  SD3.uart.s2_p =  &(UART2->S2);
-  SD3.uart.d_p =   &(UART2->D);
-  SD3.uart.uart_p = UART2;
+  sd_lld_init_driver(&SD3, UART2);
 #endif /* KINETIS_SERIAL_USE_UART2 */
+
+#if KINETIS_SERIAL_USE_UART3
+  sd_lld_init_driver(&SD4, UART3);
+#endif /* KINETIS_SERIAL_USE_UART3 */
+
+#if KINETIS_SERIAL_USE_UART4
+  sd_lld_init_driver(&SD5, UART4);
+#endif /* KINETIS_SERIAL_USE_UART4 */
+
+#if KINETIS_SERIAL_USE_UART5
+  sd_lld_init_driver(&SD6, UART5);
+#endif /* KINETIS_SERIAL_USE_UART5 */
 }
 
 /**
@@ -505,6 +563,33 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) {
     }
 #endif /* KINETIS_SERIAL_USE_UART2 */
 
+#if KINETIS_SERIAL_USE_UART3
+    if (sdp == &SD4) {
+      SIM->SCGC4 |= SIM_SCGC4_UART3;
+      configure_uart(sdp, config);
+      nvicEnableVector(UART3Status_IRQn, KINETIS_SERIAL_UART3_PRIORITY);
+      nvicEnableVector(UART3Error_IRQn, KINETIS_SERIAL_UART3_PRIORITY);
+    }
+#endif /* KINETIS_SERIAL_USE_UART3 */
+
+#if KINETIS_SERIAL_USE_UART4
+    if (sdp == &SD5) {
+      SIM->SCGC1 |= SIM_SCGC1_UART4;
+      configure_uart(sdp, config);
+      nvicEnableVector(UART4Status_IRQn, KINETIS_SERIAL_UART4_PRIORITY);
+      nvicEnableVector(UART4Error_IRQn, KINETIS_SERIAL_UART4_PRIORITY);
+    }
+#endif /* KINETIS_SERIAL_USE_UART4 */
+
+#if KINETIS_SERIAL_USE_UART5
+    if (sdp == &SD6) {
+      SIM->SCGC1 |= SIM_SCGC1_UART5;
+      configure_uart(sdp, config);
+      nvicEnableVector(UART5Status_IRQn, KINETIS_SERIAL_UART5_PRIORITY);
+      nvicEnableVector(UART5Error_IRQn, KINETIS_SERIAL_UART5_PRIORITY);
+    }
+#endif /* KINETIS_SERIAL_USE_UART5 */
+
   }
   /* Configures the peripheral.*/
 
@@ -575,6 +660,30 @@ void sd_lld_stop(SerialDriver *sdp) {
       SIM->SCGC4 &= ~SIM_SCGC4_UART2;
     }
 #endif
+
+#if KINETIS_SERIAL_USE_UART3
+    if (sdp == &SD4) {
+      nvicDisableVector(UART3Status_IRQn);
+      nvicDisableVector(UART3Error_IRQn);
+      SIM->SCGC4 &= ~SIM_SCGC4_UART3;
+    }
+#endif
+
+#if KINETIS_SERIAL_USE_UART4
+    if (sdp == &SD5) {
+      nvicDisableVector(UART4Status_IRQn);
+      nvicDisableVector(UART4Error_IRQn);
+      SIM->SCGC1 &= ~SIM_SCGC1_UART4;
+    }
+#endif
+
+#if KINETIS_SERIAL_USE_UART5
+    if (sdp == &SD6) {
+      nvicDisableVector(UART5Status_IRQn);
+      nvicDisableVector(UART5Error_IRQn);
+      SIM->SCGC1 &= ~SIM_SCGC1_UART5;
+    }
+#endif
   }
 }
 
diff --git a/os/hal/ports/KINETIS/LLD/hal_serial_lld.h b/os/hal/ports/KINETIS/LLD/hal_serial_lld.h
index f11c063..3cb6d2b 100644
--- a/os/hal/ports/KINETIS/LLD/hal_serial_lld.h
+++ b/os/hal/ports/KINETIS/LLD/hal_serial_lld.h
@@ -60,6 +60,27 @@
 #if !defined(KINETIS_SERIAL_USE_UART2) || defined(__DOXYGEN__)
 #define KINETIS_SERIAL_USE_UART2             FALSE
 #endif
+/**
+ * @brief   SD4 driver enable switch.
+ * @details If set to @p TRUE the support for SD4 is included.
+ */
+#if !defined(KINETIS_SERIAL_USE_UART3) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_USE_UART3             FALSE
+#endif
+/**
+ * @brief   SD5 driver enable switch.
+ * @details If set to @p TRUE the support for SD5 is included.
+ */
+#if !defined(KINETIS_SERIAL_USE_UART4) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_USE_UART4             FALSE
+#endif
+/**
+ * @brief   SD6 driver enable switch.
+ * @details If set to @p TRUE the support for SD6 is included.
+ */
+#if !defined(KINETIS_SERIAL_USE_UART5) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_USE_UART5             FALSE
+#endif
 
 /**
  * @brief   UART0 interrupt priority level setting.
@@ -82,6 +103,27 @@
 #define KINETIS_SERIAL_UART2_PRIORITY        12
 #endif
 
+/**
+ * @brief   UART3 interrupt priority level setting.
+ */
+#if !defined(KINETIS_SERIAL_UART3_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_UART3_PRIORITY        12
+#endif
+
+/**
+ * @brief   UART4 interrupt priority level setting.
+ */
+#if !defined(KINETIS_SERIAL_UART4_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_UART4_PRIORITY        12
+#endif
+
+/**
+ * @brief   UART5 interrupt priority level setting.
+ */
+#if !defined(KINETIS_SERIAL_UART5_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_UART5_PRIORITY        12
+#endif
+
 /**
  * @brief   UART0 clock source.
  */
@@ -115,8 +157,21 @@
 #error "UART2 not present in the selected device"
 #endif
 
+#if KINETIS_SERIAL_USE_UART3 && !KINETIS_HAS_SERIAL3
+#error "UART3 not present in the selected device"
+#endif
+
+#if KINETIS_SERIAL_USE_UART4 && !KINETIS_HAS_SERIAL4
+#error "UART4 not present in the selected device"
+#endif
+
+#if KINETIS_SERIAL_USE_UART5 && !KINETIS_HAS_SERIAL5
+#error "UART5 not present in the selected device"
+#endif
+
 #if !(KINETIS_SERIAL_USE_UART0 || KINETIS_SERIAL_USE_UART1 || \
-      KINETIS_SERIAL_USE_UART2)
+      KINETIS_SERIAL_USE_UART2 || KINETIS_SERIAL_USE_UART3 || \
+      KINETIS_SERIAL_USE_UART4 || KINETIS_SERIAL_USE_UART5)
 #error "Serial driver activated but no UART peripheral assigned"
 #endif
 
@@ -203,6 +258,18 @@ extern SerialDriver SD2;
 extern SerialDriver SD3;
 #endif
 
+#if KINETIS_SERIAL_USE_UART3 && !defined(__DOXYGEN__)
+extern SerialDriver SD4;
+#endif
+
+#if KINETIS_SERIAL_USE_UART4 && !defined(__DOXYGEN__)
+extern SerialDriver SD5;
+#endif
+
+#if KINETIS_SERIAL_USE_UART5 && !defined(__DOXYGEN__)
+extern SerialDriver SD6;
+#endif
+
 #ifdef __cplusplus
 extern "C" {
 #endif
-- 
cgit v1.2.3


From 5cc37ffd322f4b699eaa488dd467741ef2bab054 Mon Sep 17 00:00:00 2001
From: Dave Flogeras <dflogeras2@gmail.com>
Date: Thu, 14 Dec 2017 16:25:15 -0400
Subject: Add STM32F769 to FSMCv1 sdram driver

---
 os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h       | 2 +-
 os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c | 3 ++-
 os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h | 3 ++-
 3 files changed, 5 insertions(+), 3 deletions(-)

(limited to 'os')

diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h
index 51b9428..2bc267f 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h
+++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h
@@ -36,7 +36,7 @@
  */
 #if (defined(STM32F427xx) || defined(STM32F437xx) || \
      defined(STM32F429xx) || defined(STM32F439xx) || \
-     defined(STM32F7))
+     defined(STM32F769xx))
   #if !defined(FSMC_Bank1_R_BASE)
   #define FSMC_Bank1_R_BASE               (FMC_R_BASE + 0x0000)
   #endif
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c
index ac83477..ea1be4c 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c
+++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c
@@ -28,7 +28,8 @@
 #include "hal.h"
 
 #if (defined(STM32F427xx) || defined(STM32F437xx) || \
-     defined(STM32F429xx) || defined(STM32F439xx))
+     defined(STM32F429xx) || defined(STM32F439xx) || \
+     defined(STM32F769xx))
 
 #if (STM32_USE_FSMC_SDRAM == TRUE) || defined(__DOXYGEN__)
 
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h
index b419168..fdf3268 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h
+++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h
@@ -29,7 +29,8 @@
 #define HAL_FMC_SDRAM_H_
 
 #if (defined(STM32F427xx) || defined(STM32F437xx) || \
-     defined(STM32F429xx) || defined(STM32F439xx))
+     defined(STM32F429xx) || defined(STM32F439xx) || \
+     defined(STM32F769xx))
 
 #include "hal_fsmc.h"
 
-- 
cgit v1.2.3


From 0df335ce458085b0ca5910980855ecb0975dff6f Mon Sep 17 00:00:00 2001
From: Wim Lewis <wiml@hhhh.org>
Date: Sat, 6 Jan 2018 03:09:58 -0800
Subject: Basic support for the (Motorola/Freescale/NXP) Kinetis MK64FX512
 chip, partially copied from the existing K20 support.

---
 os/common/ext/CMSIS/KINETIS/k64f.h                 | 8107 ++++++++++++++++++++
 .../startup/ARMCMx/compilers/GCC/ld/MK64FX512.ld   |   97 +
 .../ARMCMx/compilers/GCC/mk/startup_k60x.mk        |   12 +
 os/common/startup/ARMCMx/devices/K60x/cmparams.h   |   81 +
 os/hal/ports/KINETIS/K60x/hal_lld.c                |  237 +
 os/hal/ports/KINETIS/K60x/hal_lld.h                |  302 +
 os/hal/ports/KINETIS/K60x/kinetis_registry.h       |  198 +
 os/hal/ports/KINETIS/K60x/platform.mk              |   19 +
 8 files changed, 9053 insertions(+)
 create mode 100644 os/common/ext/CMSIS/KINETIS/k64f.h
 create mode 100644 os/common/startup/ARMCMx/compilers/GCC/ld/MK64FX512.ld
 create mode 100644 os/common/startup/ARMCMx/compilers/GCC/mk/startup_k60x.mk
 create mode 100644 os/common/startup/ARMCMx/devices/K60x/cmparams.h
 create mode 100644 os/hal/ports/KINETIS/K60x/hal_lld.c
 create mode 100644 os/hal/ports/KINETIS/K60x/hal_lld.h
 create mode 100644 os/hal/ports/KINETIS/K60x/kinetis_registry.h
 create mode 100644 os/hal/ports/KINETIS/K60x/platform.mk

(limited to 'os')

diff --git a/os/common/ext/CMSIS/KINETIS/k64f.h b/os/common/ext/CMSIS/KINETIS/k64f.h
new file mode 100644
index 0000000..2a313d1
--- /dev/null
+++ b/os/common/ext/CMSIS/KINETIS/k64f.h
@@ -0,0 +1,8107 @@
+/*
+** ###################################################################
+**     Processors:          MK64FN1M0CAJ12
+**                          MK64FN1M0VDC12
+**                          MK64FN1M0VLL12
+**                          MK64FN1M0VLQ12
+**                          MK64FN1M0VMD12
+**                          MK64FX512VDC12
+**                          MK64FX512VLL12
+**                          MK64FX512VLQ12
+**                          MK64FX512VMD12
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**
+**     Reference manual:    K64P144M120SF5RM, Rev.2, January 2014
+**     Version:             rev. 2.9, 2016-03-21
+**     Build:               b160321
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for MK64F12
+**
+**     Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc.
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without modification,
+**     are permitted provided that the following conditions are met:
+**
+**     o Redistributions of source code must retain the above copyright notice, this list
+**       of conditions and the following disclaimer.
+**
+**     o Redistributions in binary form must reproduce the above copyright notice, this
+**       list of conditions and the following disclaimer in the documentation and/or
+**       other materials provided with the distribution.
+**
+**     o Neither the name of Freescale Semiconductor, Inc. nor the names of its
+**       contributors may be used to endorse or promote products derived from this
+**       software without specific prior written permission.
+**
+**     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+**     ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+**     WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+**     ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+**     (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+**     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+**     ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+**     (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+**     SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.freescale.com
+**     mail:                 support@freescale.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-08-12)
+**         Initial version.
+**     - rev. 2.0 (2013-10-29)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         System initialization updated.
+**         MCG - registers updated.
+**         PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
+**     - rev. 2.1 (2013-10-30)
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**     - rev. 2.2 (2013-12-09)
+**         DMA - EARS register removed.
+**         AIPS0, AIPS1 - MPRA register updated.
+**     - rev. 2.3 (2014-01-24)
+**         Update according to reference manual rev. 2
+**         ENET, MCG, MCM, SIM, USB - registers updated
+**     - rev. 2.4 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.5 (2014-02-10)
+**         The declaration of clock configurations has been moved to separate header file system_MK64F12.h
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**         Module access macro module_BASES replaced by module_BASE_PTRS.
+**     - rev. 2.6 (2014-08-28)
+**         Update of system files - default clock configuration changed.
+**         Update of startup files - possibility to override DefaultISR added.
+**     - rev. 2.7 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.8 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**     - rev. 2.9 (2016-03-21)
+**         Added MK64FN1M0CAJ12 part.
+**         GPIO - renamed port instances: PTx -> GPIOx.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK64F12.h
+ * @version 2.9
+ * @date 2016-03-21
+ * @brief CMSIS Peripheral Access Layer for MK64F12
+ *
+ * CMSIS Peripheral Access Layer for MK64F12
+ */
+
+#ifndef _MK64F12_H_
+#define _MK64F12_H_                              /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0200U
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0009U
+
+/**
+ * @brief Macro to calculate address of an aliased word in the peripheral
+ *        bitband area for a peripheral register and bit (bit band region 0x40000000 to
+ *        0x400FFFFF).
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return  Address of the aliased word in the peripheral bitband area.
+ */
+#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ *        be used for peripherals with 32bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
+#define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit)))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ *        be used for peripherals with 16bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ *        be used for peripherals with 8bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
+
+/* ----------------------------------------------------------------------------
+   -- Interrupt vector numbers
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 102                /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+  /* Auxiliary constants */
+  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
+
+  /* Core interrupts */
+  NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
+  HardFault_IRQn               = -13,              /**< Cortex-M4 SV Hard Fault Interrupt */
+  MemoryManagement_IRQn        = -12,              /**< Cortex-M4 Memory Management Interrupt */
+  BusFault_IRQn                = -11,              /**< Cortex-M4 Bus Fault Interrupt */
+  UsageFault_IRQn              = -10,              /**< Cortex-M4 Usage Fault Interrupt */
+  SVCall_IRQn                  = -5,               /**< Cortex-M4 SV Call Interrupt */
+  DebugMonitor_IRQn            = -4,               /**< Cortex-M4 Debug Monitor Interrupt */
+  PendSV_IRQn                  = -2,               /**< Cortex-M4 Pend SV Interrupt */
+  SysTick_IRQn                 = -1,               /**< Cortex-M4 System Tick Interrupt */
+
+  /* Device specific interrupts */
+  DMA0_IRQn                    = 0,                /**< DMA Channel 0 Transfer Complete */
+  DMA1_IRQn                    = 1,                /**< DMA Channel 1 Transfer Complete */
+  DMA2_IRQn                    = 2,                /**< DMA Channel 2 Transfer Complete */
+  DMA3_IRQn                    = 3,                /**< DMA Channel 3 Transfer Complete */
+  DMA4_IRQn                    = 4,                /**< DMA Channel 4 Transfer Complete */
+  DMA5_IRQn                    = 5,                /**< DMA Channel 5 Transfer Complete */
+  DMA6_IRQn                    = 6,                /**< DMA Channel 6 Transfer Complete */
+  DMA7_IRQn                    = 7,                /**< DMA Channel 7 Transfer Complete */
+  DMA8_IRQn                    = 8,                /**< DMA Channel 8 Transfer Complete */
+  DMA9_IRQn                    = 9,                /**< DMA Channel 9 Transfer Complete */
+  DMA10_IRQn                   = 10,               /**< DMA Channel 10 Transfer Complete */
+  DMA11_IRQn                   = 11,               /**< DMA Channel 11 Transfer Complete */
+  DMA12_IRQn                   = 12,               /**< DMA Channel 12 Transfer Complete */
+  DMA13_IRQn                   = 13,               /**< DMA Channel 13 Transfer Complete */
+  DMA14_IRQn                   = 14,               /**< DMA Channel 14 Transfer Complete */
+  DMA15_IRQn                   = 15,               /**< DMA Channel 15 Transfer Complete */
+  DMA_Error_IRQn               = 16,               /**< DMA Error Interrupt */
+  MCM_IRQn                     = 17,               /**< Normal Interrupt */
+  FTFE_IRQn                    = 18,               /**< FTFE Command complete interrupt */
+  Read_Collision_IRQn          = 19,               /**< Read Collision Interrupt */
+  LVD_LVW_IRQn                 = 20,               /**< Low Voltage Detect, Low Voltage Warning */
+  LLWU_IRQn                    = 21,               /**< Low Leakage Wakeup Unit */
+  WDOG_EWM_IRQn                = 22,               /**< WDOG Interrupt */
+  RNG_IRQn                     = 23,               /**< RNG Interrupt */
+  I2C0_IRQn                    = 24,               /**< I2C0 interrupt */
+  I2C1_IRQn                    = 25,               /**< I2C1 interrupt */
+  SPI0_IRQn                    = 26,               /**< SPI0 Interrupt */
+  SPI1_IRQn                    = 27,               /**< SPI1 Interrupt */
+  I2S0_Tx_IRQn                 = 28,               /**< I2S0 transmit interrupt */
+  I2S0_Rx_IRQn                 = 29,               /**< I2S0 receive interrupt */
+  UART0_LON_IRQn               = 30,               /**< UART0 LON interrupt */
+  UART0Status_IRQn             = 31,               /**< UART0 Receive/Transmit interrupt */
+  UART0Error_IRQn              = 32,               /**< UART0 Error interrupt */
+  UART1Status_IRQn             = 33,               /**< UART1 Receive/Transmit interrupt */
+  UART1Error_IRQn              = 34,               /**< UART1 Error interrupt */
+  UART2Status_IRQn             = 35,               /**< UART2 Receive/Transmit interrupt */
+  UART2Error_IRQn              = 36,               /**< UART2 Error interrupt */
+  UART3Status_IRQn             = 37,               /**< UART3 Receive/Transmit interrupt */
+  UART3Error_IRQn              = 38,               /**< UART3 Error interrupt */
+  ADC0_IRQn                    = 39,               /**< ADC0 interrupt */
+  CMP0_IRQn                    = 40,               /**< CMP0 interrupt */
+  CMP1_IRQn                    = 41,               /**< CMP1 interrupt */
+  FTM0_IRQn                    = 42,               /**< FTM0 fault, overflow and channels interrupt */
+  FTM1_IRQn                    = 43,               /**< FTM1 fault, overflow and channels interrupt */
+  FTM2_IRQn                    = 44,               /**< FTM2 fault, overflow and channels interrupt */
+  CMT_IRQn                     = 45,               /**< CMT interrupt */
+  RTC_IRQn                     = 46,               /**< RTC interrupt */
+  RTC_Seconds_IRQn             = 47,               /**< RTC seconds interrupt */
+  PIT0_IRQn                    = 48,               /**< PIT timer channel 0 interrupt */
+  PIT1_IRQn                    = 49,               /**< PIT timer channel 1 interrupt */
+  PIT2_IRQn                    = 50,               /**< PIT timer channel 2 interrupt */
+  PIT3_IRQn                    = 51,               /**< PIT timer channel 3 interrupt */
+  PDB0_IRQn                    = 52,               /**< PDB0 Interrupt */
+  USB0_IRQn                    = 53,               /**< USB0 interrupt */
+  USBDCD_IRQn                  = 54,               /**< USBDCD Interrupt */
+  Reserved71_IRQn              = 55,               /**< Reserved interrupt 71 */
+  DAC0_IRQn                    = 56,               /**< DAC0 interrupt */
+  MCG_IRQn                     = 57,               /**< MCG Interrupt */
+  LPTMR0_IRQn                  = 58,               /**< LPTimer interrupt */
+  PORTA_IRQn                   = 59,               /**< Port A interrupt */
+  PORTB_IRQn                   = 60,               /**< Port B interrupt */
+  PORTC_IRQn                   = 61,               /**< Port C interrupt */
+  PORTD_IRQn                   = 62,               /**< Port D interrupt */
+  PORTE_IRQn                   = 63,               /**< Port E interrupt */
+  SWI_IRQn                     = 64,               /**< Software interrupt */
+  SPI2_IRQn                    = 65,               /**< SPI2 Interrupt */
+  UART4Status_IRQn             = 66,               /**< UART4 Receive/Transmit interrupt */
+  UART4Error_IRQn              = 67,               /**< UART4 Error interrupt */
+  UART5Status_IRQn             = 68,               /**< UART5 Receive/Transmit interrupt */
+  UART5Error_IRQn              = 69,               /**< UART5 Error interrupt */
+  CMP2_IRQn                    = 70,               /**< CMP2 interrupt */
+  FTM3_IRQn                    = 71,               /**< FTM3 fault, overflow and channels interrupt */
+  DAC1_IRQn                    = 72,               /**< DAC1 interrupt */
+  ADC1_IRQn                    = 73,               /**< ADC1 interrupt */
+  I2C2_IRQn                    = 74,               /**< I2C2 interrupt */
+  CAN0_ORed_Message_buffer_IRQn = 75,              /**< CAN0 OR'd message buffers interrupt */
+  CAN0_Bus_Off_IRQn            = 76,               /**< CAN0 bus off interrupt */
+  CAN0_Error_IRQn              = 77,               /**< CAN0 error interrupt */
+  CAN0_Tx_Warning_IRQn         = 78,               /**< CAN0 Tx warning interrupt */
+  CAN0_Rx_Warning_IRQn         = 79,               /**< CAN0 Rx warning interrupt */
+  CAN0_Wake_Up_IRQn            = 80,               /**< CAN0 wake up interrupt */
+  SDHC_IRQn                    = 81,               /**< SDHC interrupt */
+  ENET_1588_Timer_IRQn         = 82,               /**< Ethernet MAC IEEE 1588 Timer Interrupt */
+  ENET_Transmit_IRQn           = 83,               /**< Ethernet MAC Transmit Interrupt */
+  ENET_Receive_IRQn            = 84,               /**< Ethernet MAC Receive Interrupt */
+  ENET_Error_IRQn              = 85                /**< Ethernet MAC Error and miscelaneous Interrupt */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+   -- Cortex M4 Core Configuration
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT                  0         /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS               4         /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
+
+#include "core_cm4.h"                  /* Core Peripheral Access Layer */
+/* #include "system_MK64F12.h"         /+ Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+   -- Mapping Information
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+
+/** Mapping Information */
+/*!
+ * @addtogroup edma_request
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Structure for the DMA hardware request
+ *
+ * Defines the structure for the DMA hardware request collections. The user can configure the
+ * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
+ * of the hardware request varies according  to the to SoC.
+ */
+typedef enum _dma_request_source
+{
+    kDmaRequestMux0Disable          = 0|0x100U,    /**< DMAMUX TriggerDisabled. */
+    kDmaRequestMux0Reserved1        = 1|0x100U,    /**< Reserved1 */
+    kDmaRequestMux0UART0Rx          = 2|0x100U,    /**< UART0 Receive. */
+    kDmaRequestMux0UART0Tx          = 3|0x100U,    /**< UART0 Transmit. */
+    kDmaRequestMux0UART1Rx          = 4|0x100U,    /**< UART1 Receive. */
+    kDmaRequestMux0UART1Tx          = 5|0x100U,    /**< UART1 Transmit. */
+    kDmaRequestMux0UART2Rx          = 6|0x100U,    /**< UART2 Receive. */
+    kDmaRequestMux0UART2Tx          = 7|0x100U,    /**< UART2 Transmit. */
+    kDmaRequestMux0UART3Rx          = 8|0x100U,    /**< UART3 Receive. */
+    kDmaRequestMux0UART3Tx          = 9|0x100U,    /**< UART3 Transmit. */
+    kDmaRequestMux0UART4            = 10|0x100U,   /**< UART4 Transmit or Receive. */
+    kDmaRequestMux0UART5            = 11|0x100U,   /**< UART5 Transmit or Receive. */
+    kDmaRequestMux0I2S0Rx           = 12|0x100U,   /**< I2S0 Receive. */
+    kDmaRequestMux0I2S0Tx           = 13|0x100U,   /**< I2S0 Transmit. */
+    kDmaRequestMux0SPI0Rx           = 14|0x100U,   /**< SPI0 Receive. */
+    kDmaRequestMux0SPI0Tx           = 15|0x100U,   /**< SPI0 Transmit. */
+    kDmaRequestMux0SPI1             = 16|0x100U,   /**< SPI1 Transmit or Receive. */
+    kDmaRequestMux0SPI2             = 17|0x100U,   /**< SPI2 Transmit or Receive. */
+    kDmaRequestMux0I2C0             = 18|0x100U,   /**< I2C0. */
+    kDmaRequestMux0I2C1I2C2         = 19|0x100U,   /**< I2C1 and I2C2. */
+    kDmaRequestMux0I2C1             = 19|0x100U,   /**< I2C1 and I2C2. */
+    kDmaRequestMux0I2C2             = 19|0x100U,   /**< I2C1 and I2C2. */
+    kDmaRequestMux0FTM0Channel0     = 20|0x100U,   /**< FTM0 C0V. */
+    kDmaRequestMux0FTM0Channel1     = 21|0x100U,   /**< FTM0 C1V. */
+    kDmaRequestMux0FTM0Channel2     = 22|0x100U,   /**< FTM0 C2V. */
+    kDmaRequestMux0FTM0Channel3     = 23|0x100U,   /**< FTM0 C3V. */
+    kDmaRequestMux0FTM0Channel4     = 24|0x100U,   /**< FTM0 C4V. */
+    kDmaRequestMux0FTM0Channel5     = 25|0x100U,   /**< FTM0 C5V. */
+    kDmaRequestMux0FTM0Channel6     = 26|0x100U,   /**< FTM0 C6V. */
+    kDmaRequestMux0FTM0Channel7     = 27|0x100U,   /**< FTM0 C7V. */
+    kDmaRequestMux0FTM1Channel0     = 28|0x100U,   /**< FTM1 C0V. */
+    kDmaRequestMux0FTM1Channel1     = 29|0x100U,   /**< FTM1 C1V. */
+    kDmaRequestMux0FTM2Channel0     = 30|0x100U,   /**< FTM2 C0V. */
+    kDmaRequestMux0FTM2Channel1     = 31|0x100U,   /**< FTM2 C1V. */
+    kDmaRequestMux0FTM3Channel0     = 32|0x100U,   /**< FTM3 C0V. */
+    kDmaRequestMux0FTM3Channel1     = 33|0x100U,   /**< FTM3 C1V. */
+    kDmaRequestMux0FTM3Channel2     = 34|0x100U,   /**< FTM3 C2V. */
+    kDmaRequestMux0FTM3Channel3     = 35|0x100U,   /**< FTM3 C3V. */
+    kDmaRequestMux0FTM3Channel4     = 36|0x100U,   /**< FTM3 C4V. */
+    kDmaRequestMux0FTM3Channel5     = 37|0x100U,   /**< FTM3 C5V. */
+    kDmaRequestMux0FTM3Channel6     = 38|0x100U,   /**< FTM3 C6V. */
+    kDmaRequestMux0FTM3Channel7     = 39|0x100U,   /**< FTM3 C7V. */
+    kDmaRequestMux0ADC0             = 40|0x100U,   /**< ADC0. */
+    kDmaRequestMux0ADC1             = 41|0x100U,   /**< ADC1. */
+    kDmaRequestMux0CMP0             = 42|0x100U,   /**< CMP0. */
+    kDmaRequestMux0CMP1             = 43|0x100U,   /**< CMP1. */
+    kDmaRequestMux0CMP2             = 44|0x100U,   /**< CMP2. */
+    kDmaRequestMux0DAC0             = 45|0x100U,   /**< DAC0. */
+    kDmaRequestMux0DAC1             = 46|0x100U,   /**< DAC1. */
+    kDmaRequestMux0CMT              = 47|0x100U,   /**< CMT. */
+    kDmaRequestMux0PDB              = 48|0x100U,   /**< PDB0. */
+    kDmaRequestMux0PortA            = 49|0x100U,   /**< PTA. */
+    kDmaRequestMux0PortB            = 50|0x100U,   /**< PTB. */
+    kDmaRequestMux0PortC            = 51|0x100U,   /**< PTC. */
+    kDmaRequestMux0PortD            = 52|0x100U,   /**< PTD. */
+    kDmaRequestMux0PortE            = 53|0x100U,   /**< PTE. */
+    kDmaRequestMux0IEEE1588Timer0   = 54|0x100U,   /**< ENET IEEE 1588 timer 0. */
+    kDmaRequestMux0IEEE1588Timer1   = 55|0x100U,   /**< ENET IEEE 1588 timer 1. */
+    kDmaRequestMux0IEEE1588Timer2   = 56|0x100U,   /**< ENET IEEE 1588 timer 2. */
+    kDmaRequestMux0IEEE1588Timer3   = 57|0x100U,   /**< ENET IEEE 1588 timer 3. */
+    kDmaRequestMux0AlwaysOn58       = 58|0x100U,   /**< DMAMUX Always Enabled slot. */
+    kDmaRequestMux0AlwaysOn59       = 59|0x100U,   /**< DMAMUX Always Enabled slot. */
+    kDmaRequestMux0AlwaysOn60       = 60|0x100U,   /**< DMAMUX Always Enabled slot. */
+    kDmaRequestMux0AlwaysOn61       = 61|0x100U,   /**< DMAMUX Always Enabled slot. */
+    kDmaRequestMux0AlwaysOn62       = 62|0x100U,   /**< DMAMUX Always Enabled slot. */
+    kDmaRequestMux0AlwaysOn63       = 63|0x100U,   /**< DMAMUX Always Enabled slot. */
+} dma_request_source_t;
+
+/* @} */
+
+
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #pragma push
+  #pragma anon_unions
+#elif defined(__CWCC__)
+  #pragma push
+  #pragma cpp_extensions on
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- ADC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC1[2];                            /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
+  __IO uint32_t CFG1;                              /**< ADC Configuration Register 1, offset: 0x8 */
+  __IO uint32_t CFG2;                              /**< ADC Configuration Register 2, offset: 0xC */
+  __I  uint32_t R[2];                              /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
+  __IO uint32_t CV1;                               /**< Compare Value Registers, offset: 0x18 */
+  __IO uint32_t CV2;                               /**< Compare Value Registers, offset: 0x1C */
+  __IO uint32_t SC2;                               /**< Status and Control Register 2, offset: 0x20 */
+  __IO uint32_t SC3;                               /**< Status and Control Register 3, offset: 0x24 */
+  __IO uint32_t OFS;                               /**< ADC Offset Correction Register, offset: 0x28 */
+  __IO uint32_t PG;                                /**< ADC Plus-Side Gain Register, offset: 0x2C */
+  __IO uint32_t MG;                                /**< ADC Minus-Side Gain Register, offset: 0x30 */
+  __IO uint32_t CLPD;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
+  __IO uint32_t CLPS;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
+  __IO uint32_t CLP4;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
+  __IO uint32_t CLP3;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
+  __IO uint32_t CLP2;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
+  __IO uint32_t CLP1;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
+  __IO uint32_t CLP0;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t CLMD;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
+  __IO uint32_t CLMS;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
+  __IO uint32_t CLM4;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
+  __IO uint32_t CLM3;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
+  __IO uint32_t CLM2;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
+  __IO uint32_t CLM1;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
+  __IO uint32_t CLM0;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
+} ADC_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- ADC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/*! @name SC1 - ADC Status and Control Registers 1 */
+#define ADCx_SC1n_ADCH_MASK                      (0x1FU)
+#define ADCx_SC1n_ADCH_SHIFT                     (0U)
+#define ADCx_SC1n_ADCH(x)                        (((uint32_t)(((uint32_t)(x)) << ADCx_SC1n_ADCH_SHIFT)) & ADCx_SC1n_ADCH_MASK)
+#define ADCx_SC1n_DIFF                           (0x20U)
+#define ADCx_SC1n_AIEN                           (0x40U)
+#define ADCx_SC1n_COCO                           (0x80U)
+
+/* The count of ADC_SC1 */
+#define ADCx_SC1_COUNT                           (2U)
+
+/*! @name CFG1 - ADC Configuration Register 1 */
+#define ADCx_CFG1_ADICLK_MASK                    (0x3U)
+#define ADCx_CFG1_ADICLK_SHIFT                   (0U)
+#define ADCx_CFG1_ADICLK(x)                      (((uint32_t)(((uint32_t)(x)) << ADCx_CFG1_ADICLK_SHIFT)) & ADCx_CFG1_ADICLK_MASK)
+#define ADCx_CFG1_MODE_MASK                      (0xCU)
+#define ADCx_CFG1_MODE_SHIFT                     (2U)
+#define ADCx_CFG1_MODE(x)                        (((uint32_t)(((uint32_t)(x)) << ADCx_CFG1_MODE_SHIFT)) & ADCx_CFG1_MODE_MASK)
+#define ADCx_CFG1_ADLSMP                         (0x10U)
+#define ADCx_CFG1_ADIV_MASK                      (0x60U)
+#define ADCx_CFG1_ADIV_SHIFT                     (5U)
+#define ADCx_CFG1_ADIV(x)                        (((uint32_t)(((uint32_t)(x)) << ADCx_CFG1_ADIV_SHIFT)) & ADCx_CFG1_ADIV_MASK)
+#define ADCx_CFG1_ADLPC                          (0x80U)
+
+/*! @name CFG2 - ADC Configuration Register 2 */
+#define ADCx_CFG2_ADLSTS_MASK                    (0x3U)
+#define ADCx_CFG2_ADLSTS_SHIFT                   (0U)
+#define ADCx_CFG2_ADLSTS(x)                      (((uint32_t)(((uint32_t)(x)) << ADCx_CFG2_ADLSTS_SHIFT)) & ADCx_CFG2_ADLSTS_MASK)
+#define ADCx_CFG2_ADHSC                          (0x4U)
+#define ADCx_CFG2_ADACKEN                        (0x8U)
+#define ADCx_CFG2_MUXSEL                         (0x10U)
+
+/*! @name R - ADC Data Result Register */
+#define ADCx_Rn_D_MASK                           (0xFFFFU)
+#define ADCx_Rn_D_SHIFT                          (0U)
+#define ADCx_Rn_D(x)                             (((uint32_t)(((uint32_t)(x)) << ADCx_R_D_SHIFT)) & ADCx_R_D_MASK)
+
+/* The count of ADC_R */
+#define ADCx_R_COUNT                             (2U)
+
+/*! @name CV1 - Compare Value Registers */
+#define ADCx_CV1_CV_MASK                         (0xFFFFU)
+#define ADCx_CV1_CV_SHIFT                        (0U)
+#define ADCx_CV1_CV(x)                           (((uint32_t)(((uint32_t)(x)) << ADCx_CV1_CV_SHIFT)) & ADCx_CV1_CV_MASK)
+
+/*! @name CV2 - Compare Value Registers */
+#define ADCx_CV2_CV_MASK                         (0xFFFFU)
+#define ADCx_CV2_CV_SHIFT                        (0U)
+#define ADCx_CV2_CV(x)                           (((uint32_t)(((uint32_t)(x)) << ADCx_CV2_CV_SHIFT)) & ADCx_CV2_CV_MASK)
+
+/*! @name SC2 - Status and Control Register 2 */
+#define ADCx_SC2_REFSEL_MASK                     (0x3U)
+#define ADCx_SC2_REFSEL_SHIFT                    (0U)
+#define ADCx_SC2_REFSEL(x)                       (((uint32_t)(((uint32_t)(x)) << ADCx_SC2_REFSEL_SHIFT)) & ADCx_SC2_REFSEL_MASK)
+#define ADCx_SC2_DMAEN                           (0x4U)
+#define ADCx_SC2_ACREN                           (0x8U)
+#define ADCx_SC2_ACFGT                           (0x10U)
+#define ADCx_SC2_ACFE                            (0x20U)
+#define ADCx_SC2_ADTRG                           (0x40U)
+#define ADCx_SC2_ADACT                           (0x80U)
+
+/*! @name SC3 - Status and Control Register 3 */
+#define ADCx_SC3_AVGS_MASK                       (0x3U)
+#define ADCx_SC3_AVGS_SHIFT                      (0U)
+#define ADCx_SC3_AVGS(x)                         (((uint32_t)(((uint32_t)(x)) << ADCx_SC3_AVGS_SHIFT)) & ADCx_SC3_AVGS_MASK)
+#define ADCx_SC3_AVGE                            (0x4U)
+#define ADCx_SC3_ADCO                            (0x8U)
+#define ADCx_SC3_CALF                            (0x40U)
+#define ADCx_SC3_CAL                             (0x80U)
+
+/*! @name OFS - ADC Offset Correction Register */
+#define ADCx_OFS_OFS_MASK                        (0xFFFFU)
+#define ADCx_OFS_OFS_SHIFT                       (0U)
+#define ADCx_OFS_OFS(x)                          (((uint32_t)(((uint32_t)(x)) << ADCx_OFS_OFS_SHIFT)) & ADCx_OFS_OFS_MASK)
+
+/*! @name PG - ADC Plus-Side Gain Register */
+#define ADCx_PG_PG_MASK                          (0xFFFFU)
+#define ADCx_PG_PG_SHIFT                         (0U)
+#define ADCx_PG_PG(x)                            (((uint32_t)(((uint32_t)(x)) << ADCx_PG_PG_SHIFT)) & ADCx_PG_PG_MASK)
+
+/*! @name MG - ADC Minus-Side Gain Register */
+#define ADCx_MG_MG_MASK                          (0xFFFFU)
+#define ADCx_MG_MG_SHIFT                         (0U)
+#define ADCx_MG_MG(x)                            (((uint32_t)(((uint32_t)(x)) << ADCx_MG_MG_SHIFT)) & ADCx_MG_MG_MASK)
+
+/*! @name CLPD - ADC Plus-Side General Calibration Value Register */
+#define ADCx_CLPD_CLPD_MASK                      (0x3FU)
+#define ADCx_CLPD_CLPD_SHIFT                     (0U)
+#define ADCx_CLPD_CLPD(x)                        (((uint32_t)(((uint32_t)(x)) << ADCx_CLPD_CLPD_SHIFT)) & ADCx_CLPD_CLPD_MASK)
+
+/*! @name CLPS - ADC Plus-Side General Calibration Value Register */
+#define ADCx_CLPS_CLPS_MASK                      (0x3FU)
+#define ADCx_CLPS_CLPS_SHIFT                     (0U)
+#define ADCx_CLPS_CLPS(x)                        (((uint32_t)(((uint32_t)(x)) << ADCx_CLPS_CLPS_SHIFT)) & ADCx_CLPS_CLPS_MASK)
+
+/*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
+#define ADCx_CLP4_CLP4_MASK                      (0x3FFU)
+#define ADCx_CLP4_CLP4_SHIFT                     (0U)
+#define ADCx_CLP4_CLP4(x)                        (((uint32_t)(((uint32_t)(x)) << ADCx_CLP4_CLP4_SHIFT)) & ADCx_CLP4_CLP4_MASK)
+
+/*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
+#define ADCx_CLP3_CLP3_MASK                      (0x1FFU)
+#define ADCx_CLP3_CLP3_SHIFT                     (0U)
+#define ADCx_CLP3_CLP3(x)                        (((uint32_t)(((uint32_t)(x)) << ADCx_CLP3_CLP3_SHIFT)) & ADCx_CLP3_CLP3_MASK)
+
+/*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
+#define ADCx_CLP2_CLP2_MASK                      (0xFFU)
+#define ADCx_CLP2_CLP2_SHIFT                     (0U)
+#define ADCx_CLP2_CLP2(x)                        (((uint32_t)(((uint32_t)(x)) << ADCx_CLP2_CLP2_SHIFT)) & ADCx_CLP2_CLP2_MASK)
+
+/*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
+#define ADCx_CLP1_CLP1_MASK                      (0x7FU)
+#define ADCx_CLP1_CLP1_SHIFT                     (0U)
+#define ADCx_CLP1_CLP1(x)                        (((uint32_t)(((uint32_t)(x)) << ADCx_CLP1_CLP1_SHIFT)) & ADCx_CLP1_CLP1_MASK)
+
+/*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
+#define ADCx_CLP0_CLP0_MASK                      (0x3FU)
+#define ADCx_CLP0_CLP0_SHIFT                     (0U)
+#define ADCx_CLP0_CLP0(x)                        (((uint32_t)(((uint32_t)(x)) << ADCx_CLP0_CLP0_SHIFT)) & ADCx_CLP0_CLP0_MASK)
+
+/*! @name CLMD - ADC Minus-Side General Calibration Value Register */
+#define ADCx_CLMD_CLMD_MASK                      (0x3FU)
+#define ADCx_CLMD_CLMD_SHIFT                     (0U)
+#define ADCx_CLMD_CLMD(x)                        (((uint32_t)(((uint32_t)(x)) << ADCx_CLMD_CLMD_SHIFT)) & ADCx_CLMD_CLMD_MASK)
+
+/*! @name CLMS - ADC Minus-Side General Calibration Value Register */
+#define ADCx_CLMS_CLMS_MASK                      (0x3FU)
+#define ADCx_CLMS_CLMS_SHIFT                     (0U)
+#define ADCx_CLMS_CLMS(x)                        (((uint32_t)(((uint32_t)(x)) << ADCx_CLMS_CLMS_SHIFT)) & ADCx_CLMS_CLMS_MASK)
+
+/*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
+#define ADCx_CLM4_CLM4_MASK                      (0x3FFU)
+#define ADCx_CLM4_CLM4_SHIFT                     (0U)
+#define ADCx_CLM4_CLM4(x)                        (((uint32_t)(((uint32_t)(x)) << ADCx_CLM4_CLM4_SHIFT)) & ADCx_CLM4_CLM4_MASK)
+
+/*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
+#define ADCx_CLM3_CLM3_MASK                      (0x1FFU)
+#define ADCx_CLM3_CLM3_SHIFT                     (0U)
+#define ADCx_CLM3_CLM3(x)                        (((uint32_t)(((uint32_t)(x)) << ADCx_CLM3_CLM3_SHIFT)) & ADCx_CLM3_CLM3_MASK)
+
+/*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
+#define ADCx_CLM2_CLM2_MASK                      (0xFFU)
+#define ADCx_CLM2_CLM2_SHIFT                     (0U)
+#define ADCx_CLM2_CLM2(x)                        (((uint32_t)(((uint32_t)(x)) << ADCx_CLM2_CLM2_SHIFT)) & ADCx_CLM2_CLM2_MASK)
+
+/*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
+#define ADCx_CLM1_CLM1_MASK                      (0x7FU)
+#define ADCx_CLM1_CLM1_SHIFT                     (0U)
+#define ADCx_CLM1_CLM1(x)                        (((uint32_t)(((uint32_t)(x)) << ADCx_CLM1_CLM1_SHIFT)) & ADCx_CLM1_CLM1_MASK)
+
+/*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
+#define ADCx_CLM0_CLM0_MASK                      (0x3FU)
+#define ADCx_CLM0_CLM0_SHIFT                     (0U)
+#define ADCx_CLM0_CLM0(x)                        (((uint32_t)(((uint32_t)(x)) << ADCx_CLM0_CLM0_SHIFT)) & ADCx_CLM0_CLM0_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE                                (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0                                     ((ADC_TypeDef *)ADC0_BASE)
+/** Peripheral ADC1 base address */
+#define ADC1_BASE                                (0x400BB000u)
+/** Peripheral ADC1 base pointer */
+#define ADC1                                     ((ADC_TypeDef *)ADC1_BASE)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS                           { ADC0_BASE, ADC1_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS                            { ADC0, ADC1 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_IRQS                                 { ADC0_IRQn, ADC1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- AIPS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
+ * @{
+ */
+
+/** AIPS - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MPRA;                              /**< Master Privilege Register A, offset: 0x0 */
+       uint8_t RESERVED_0[28];
+  __IO uint32_t PACRA;                             /**< Peripheral Access Control Register, offset: 0x20 */
+  __IO uint32_t PACRB;                             /**< Peripheral Access Control Register, offset: 0x24 */
+  __IO uint32_t PACRC;                             /**< Peripheral Access Control Register, offset: 0x28 */
+  __IO uint32_t PACRD;                             /**< Peripheral Access Control Register, offset: 0x2C */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t PACRE;                             /**< Peripheral Access Control Register, offset: 0x40 */
+  __IO uint32_t PACRF;                             /**< Peripheral Access Control Register, offset: 0x44 */
+  __IO uint32_t PACRG;                             /**< Peripheral Access Control Register, offset: 0x48 */
+  __IO uint32_t PACRH;                             /**< Peripheral Access Control Register, offset: 0x4C */
+  __IO uint32_t PACRI;                             /**< Peripheral Access Control Register, offset: 0x50 */
+  __IO uint32_t PACRJ;                             /**< Peripheral Access Control Register, offset: 0x54 */
+  __IO uint32_t PACRK;                             /**< Peripheral Access Control Register, offset: 0x58 */
+  __IO uint32_t PACRL;                             /**< Peripheral Access Control Register, offset: 0x5C */
+  __IO uint32_t PACRM;                             /**< Peripheral Access Control Register, offset: 0x60 */
+  __IO uint32_t PACRN;                             /**< Peripheral Access Control Register, offset: 0x64 */
+  __IO uint32_t PACRO;                             /**< Peripheral Access Control Register, offset: 0x68 */
+  __IO uint32_t PACRP;                             /**< Peripheral Access Control Register, offset: 0x6C */
+       uint8_t RESERVED_2[16];
+  __IO uint32_t PACRU;                             /**< Peripheral Access Control Register, offset: 0x80 */
+} AIPS_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- AIPS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Masks AIPS Register Masks
+ * @{
+ */
+
+/*! @name MPRA - Master Privilege Register A */
+#define AIPS_MPRA_MPL5                           (0x100U)
+#define AIPS_MPRA_MTW5                           (0x200U)
+#define AIPS_MPRA_MTR5                           (0x400U)
+#define AIPS_MPRA_MPL4                           (0x1000U)
+#define AIPS_MPRA_MTW4                           (0x2000U)
+#define AIPS_MPRA_MTR4                           (0x4000U)
+#define AIPS_MPRA_MPL3                           (0x10000U)
+#define AIPS_MPRA_MTW3                           (0x20000U)
+#define AIPS_MPRA_MTR3                           (0x40000U)
+#define AIPS_MPRA_MPL2                           (0x100000U)
+#define AIPS_MPRA_MTW2                           (0x200000U)
+#define AIPS_MPRA_MTR2                           (0x400000U)
+#define AIPS_MPRA_MPL1                           (0x1000000U)
+#define AIPS_MPRA_MTW1                           (0x2000000U)
+#define AIPS_MPRA_MTR1                           (0x4000000U)
+#define AIPS_MPRA_MPL0                           (0x10000000U)
+#define AIPS_MPRA_MTW0                           (0x20000000U)
+#define AIPS_MPRA_MTR0                           (0x40000000U)
+
+/*! @name PACRA - Peripheral Access Control Register */
+#define AIPS_PACRA_TP7                           (0x1U)
+#define AIPS_PACRA_WP7                           (0x2U)
+#define AIPS_PACRA_SP7                           (0x4U)
+#define AIPS_PACRA_TP6                           (0x10U)
+#define AIPS_PACRA_WP6                           (0x20U)
+#define AIPS_PACRA_SP6                           (0x40U)
+#define AIPS_PACRA_TP5                           (0x100U)
+#define AIPS_PACRA_WP5                           (0x200U)
+#define AIPS_PACRA_SP5                           (0x400U)
+#define AIPS_PACRA_TP4                           (0x1000U)
+#define AIPS_PACRA_WP4                           (0x2000U)
+#define AIPS_PACRA_SP4                           (0x4000U)
+#define AIPS_PACRA_TP3                           (0x10000U)
+#define AIPS_PACRA_WP3                           (0x20000U)
+#define AIPS_PACRA_SP3                           (0x40000U)
+#define AIPS_PACRA_TP2                           (0x100000U)
+#define AIPS_PACRA_WP2                           (0x200000U)
+#define AIPS_PACRA_SP2                           (0x400000U)
+#define AIPS_PACRA_TP1                           (0x1000000U)
+#define AIPS_PACRA_WP1                           (0x2000000U)
+#define AIPS_PACRA_SP1                           (0x4000000U)
+#define AIPS_PACRA_TP0                           (0x10000000U)
+#define AIPS_PACRA_WP0                           (0x20000000U)
+#define AIPS_PACRA_SP0                           (0x40000000U)
+
+/*! @name PACRB - Peripheral Access Control Register */
+#define AIPS_PACRB_TP7                           (0x1U)
+#define AIPS_PACRB_WP7                           (0x2U)
+#define AIPS_PACRB_SP7                           (0x4U)
+#define AIPS_PACRB_TP6                           (0x10U)
+#define AIPS_PACRB_WP6                           (0x20U)
+#define AIPS_PACRB_SP6                           (0x40U)
+#define AIPS_PACRB_TP5                           (0x100U)
+#define AIPS_PACRB_WP5                           (0x200U)
+#define AIPS_PACRB_SP5                           (0x400U)
+#define AIPS_PACRB_TP4                           (0x1000U)
+#define AIPS_PACRB_WP4                           (0x2000U)
+#define AIPS_PACRB_SP4                           (0x4000U)
+#define AIPS_PACRB_TP3                           (0x10000U)
+#define AIPS_PACRB_WP3                           (0x20000U)
+#define AIPS_PACRB_SP3                           (0x40000U)
+#define AIPS_PACRB_TP2                           (0x100000U)
+#define AIPS_PACRB_WP2                           (0x200000U)
+#define AIPS_PACRB_SP2                           (0x400000U)
+#define AIPS_PACRB_TP1                           (0x1000000U)
+#define AIPS_PACRB_WP1                           (0x2000000U)
+#define AIPS_PACRB_SP1                           (0x4000000U)
+#define AIPS_PACRB_TP0                           (0x10000000U)
+#define AIPS_PACRB_WP0                           (0x20000000U)
+#define AIPS_PACRB_SP0                           (0x40000000U)
+
+/*! @name PACRC - Peripheral Access Control Register */
+#define AIPS_PACRC_TP7                           (0x1U)
+#define AIPS_PACRC_WP7                           (0x2U)
+#define AIPS_PACRC_SP7                           (0x4U)
+#define AIPS_PACRC_TP6                           (0x10U)
+#define AIPS_PACRC_WP6                           (0x20U)
+#define AIPS_PACRC_SP6                           (0x40U)
+#define AIPS_PACRC_TP5                           (0x100U)
+#define AIPS_PACRC_WP5                           (0x200U)
+#define AIPS_PACRC_SP5                           (0x400U)
+#define AIPS_PACRC_TP4                           (0x1000U)
+#define AIPS_PACRC_WP4                           (0x2000U)
+#define AIPS_PACRC_SP4                           (0x4000U)
+#define AIPS_PACRC_TP3                           (0x10000U)
+#define AIPS_PACRC_WP3                           (0x20000U)
+#define AIPS_PACRC_SP3                           (0x40000U)
+#define AIPS_PACRC_TP2                           (0x100000U)
+#define AIPS_PACRC_WP2                           (0x200000U)
+#define AIPS_PACRC_SP2                           (0x400000U)
+#define AIPS_PACRC_TP1                           (0x1000000U)
+#define AIPS_PACRC_WP1                           (0x2000000U)
+#define AIPS_PACRC_SP1                           (0x4000000U)
+#define AIPS_PACRC_TP0                           (0x10000000U)
+#define AIPS_PACRC_WP0                           (0x20000000U)
+#define AIPS_PACRC_SP0                           (0x40000000U)
+
+/*! @name PACRD - Peripheral Access Control Register */
+#define AIPS_PACRD_TP7                           (0x1U)
+#define AIPS_PACRD_WP7                           (0x2U)
+#define AIPS_PACRD_SP7                           (0x4U)
+#define AIPS_PACRD_TP6                           (0x10U)
+#define AIPS_PACRD_WP6                           (0x20U)
+#define AIPS_PACRD_SP6                           (0x40U)
+#define AIPS_PACRD_TP5                           (0x100U)
+#define AIPS_PACRD_WP5                           (0x200U)
+#define AIPS_PACRD_SP5                           (0x400U)
+#define AIPS_PACRD_TP4                           (0x1000U)
+#define AIPS_PACRD_WP4                           (0x2000U)
+#define AIPS_PACRD_SP4                           (0x4000U)
+#define AIPS_PACRD_TP3                           (0x10000U)
+#define AIPS_PACRD_WP3                           (0x20000U)
+#define AIPS_PACRD_SP3                           (0x40000U)
+#define AIPS_PACRD_TP2                           (0x100000U)
+#define AIPS_PACRD_WP2                           (0x200000U)
+#define AIPS_PACRD_SP2                           (0x400000U)
+#define AIPS_PACRD_TP1                           (0x1000000U)
+#define AIPS_PACRD_WP1                           (0x2000000U)
+#define AIPS_PACRD_SP1                           (0x4000000U)
+#define AIPS_PACRD_TP0                           (0x10000000U)
+#define AIPS_PACRD_WP0                           (0x20000000U)
+#define AIPS_PACRD_SP0                           (0x40000000U)
+
+/*! @name PACRE - Peripheral Access Control Register */
+#define AIPS_PACRE_TP7                           (0x1U)
+#define AIPS_PACRE_WP7                           (0x2U)
+#define AIPS_PACRE_SP7                           (0x4U)
+#define AIPS_PACRE_TP6                           (0x10U)
+#define AIPS_PACRE_WP6                           (0x20U)
+#define AIPS_PACRE_SP6                           (0x40U)
+#define AIPS_PACRE_TP5                           (0x100U)
+#define AIPS_PACRE_WP5                           (0x200U)
+#define AIPS_PACRE_SP5                           (0x400U)
+#define AIPS_PACRE_TP4                           (0x1000U)
+#define AIPS_PACRE_WP4                           (0x2000U)
+#define AIPS_PACRE_SP4                           (0x4000U)
+#define AIPS_PACRE_TP3                           (0x10000U)
+#define AIPS_PACRE_WP3                           (0x20000U)
+#define AIPS_PACRE_SP3                           (0x40000U)
+#define AIPS_PACRE_TP2                           (0x100000U)
+#define AIPS_PACRE_WP2                           (0x200000U)
+#define AIPS_PACRE_SP2                           (0x400000U)
+#define AIPS_PACRE_TP1                           (0x1000000U)
+#define AIPS_PACRE_WP1                           (0x2000000U)
+#define AIPS_PACRE_SP1                           (0x4000000U)
+#define AIPS_PACRE_TP0                           (0x10000000U)
+#define AIPS_PACRE_WP0                           (0x20000000U)
+#define AIPS_PACRE_SP0                           (0x40000000U)
+
+/*! @name PACRF - Peripheral Access Control Register */
+#define AIPS_PACRF_TP7                           (0x1U)
+#define AIPS_PACRF_WP7                           (0x2U)
+#define AIPS_PACRF_SP7                           (0x4U)
+#define AIPS_PACRF_TP6                           (0x10U)
+#define AIPS_PACRF_WP6                           (0x20U)
+#define AIPS_PACRF_SP6                           (0x40U)
+#define AIPS_PACRF_TP5                           (0x100U)
+#define AIPS_PACRF_WP5                           (0x200U)
+#define AIPS_PACRF_SP5                           (0x400U)
+#define AIPS_PACRF_TP4                           (0x1000U)
+#define AIPS_PACRF_WP4                           (0x2000U)
+#define AIPS_PACRF_SP4                           (0x4000U)
+#define AIPS_PACRF_TP3                           (0x10000U)
+#define AIPS_PACRF_WP3                           (0x20000U)
+#define AIPS_PACRF_SP3                           (0x40000U)
+#define AIPS_PACRF_TP2                           (0x100000U)
+#define AIPS_PACRF_WP2                           (0x200000U)
+#define AIPS_PACRF_SP2                           (0x400000U)
+#define AIPS_PACRF_TP1                           (0x1000000U)
+#define AIPS_PACRF_WP1                           (0x2000000U)
+#define AIPS_PACRF_SP1                           (0x4000000U)
+#define AIPS_PACRF_TP0                           (0x10000000U)
+#define AIPS_PACRF_WP0                           (0x20000000U)
+#define AIPS_PACRF_SP0                           (0x40000000U)
+
+/*! @name PACRG - Peripheral Access Control Register */
+#define AIPS_PACRG_TP7                           (0x1U)
+#define AIPS_PACRG_WP7                           (0x2U)
+#define AIPS_PACRG_SP7                           (0x4U)
+#define AIPS_PACRG_TP6                           (0x10U)
+#define AIPS_PACRG_WP6                           (0x20U)
+#define AIPS_PACRG_SP6                           (0x40U)
+#define AIPS_PACRG_TP5                           (0x100U)
+#define AIPS_PACRG_WP5                           (0x200U)
+#define AIPS_PACRG_SP5                           (0x400U)
+#define AIPS_PACRG_TP4                           (0x1000U)
+#define AIPS_PACRG_WP4                           (0x2000U)
+#define AIPS_PACRG_SP4                           (0x4000U)
+#define AIPS_PACRG_TP3                           (0x10000U)
+#define AIPS_PACRG_WP3                           (0x20000U)
+#define AIPS_PACRG_SP3                           (0x40000U)
+#define AIPS_PACRG_TP2                           (0x100000U)
+#define AIPS_PACRG_WP2                           (0x200000U)
+#define AIPS_PACRG_SP2                           (0x400000U)
+#define AIPS_PACRG_TP1                           (0x1000000U)
+#define AIPS_PACRG_WP1                           (0x2000000U)
+#define AIPS_PACRG_SP1                           (0x4000000U)
+#define AIPS_PACRG_TP0                           (0x10000000U)
+#define AIPS_PACRG_WP0                           (0x20000000U)
+#define AIPS_PACRG_SP0                           (0x40000000U)
+
+/*! @name PACRH - Peripheral Access Control Register */
+#define AIPS_PACRH_TP7                           (0x1U)
+#define AIPS_PACRH_WP7                           (0x2U)
+#define AIPS_PACRH_SP7                           (0x4U)
+#define AIPS_PACRH_TP6                           (0x10U)
+#define AIPS_PACRH_WP6                           (0x20U)
+#define AIPS_PACRH_SP6                           (0x40U)
+#define AIPS_PACRH_TP5                           (0x100U)
+#define AIPS_PACRH_WP5                           (0x200U)
+#define AIPS_PACRH_SP5                           (0x400U)
+#define AIPS_PACRH_TP4                           (0x1000U)
+#define AIPS_PACRH_WP4                           (0x2000U)
+#define AIPS_PACRH_SP4                           (0x4000U)
+#define AIPS_PACRH_TP3                           (0x10000U)
+#define AIPS_PACRH_WP3                           (0x20000U)
+#define AIPS_PACRH_SP3                           (0x40000U)
+#define AIPS_PACRH_TP2                           (0x100000U)
+#define AIPS_PACRH_WP2                           (0x200000U)
+#define AIPS_PACRH_SP2                           (0x400000U)
+#define AIPS_PACRH_TP1                           (0x1000000U)
+#define AIPS_PACRH_WP1                           (0x2000000U)
+#define AIPS_PACRH_SP1                           (0x4000000U)
+#define AIPS_PACRH_TP0                           (0x10000000U)
+#define AIPS_PACRH_WP0                           (0x20000000U)
+#define AIPS_PACRH_SP0                           (0x40000000U)
+
+/*! @name PACRI - Peripheral Access Control Register */
+#define AIPS_PACRI_TP7                           (0x1U)
+#define AIPS_PACRI_WP7                           (0x2U)
+#define AIPS_PACRI_SP7                           (0x4U)
+#define AIPS_PACRI_TP6                           (0x10U)
+#define AIPS_PACRI_WP6                           (0x20U)
+#define AIPS_PACRI_SP6                           (0x40U)
+#define AIPS_PACRI_TP5                           (0x100U)
+#define AIPS_PACRI_WP5                           (0x200U)
+#define AIPS_PACRI_SP5                           (0x400U)
+#define AIPS_PACRI_TP4                           (0x1000U)
+#define AIPS_PACRI_WP4                           (0x2000U)
+#define AIPS_PACRI_SP4                           (0x4000U)
+#define AIPS_PACRI_TP3                           (0x10000U)
+#define AIPS_PACRI_WP3                           (0x20000U)
+#define AIPS_PACRI_SP3                           (0x40000U)
+#define AIPS_PACRI_TP2                           (0x100000U)
+#define AIPS_PACRI_WP2                           (0x200000U)
+#define AIPS_PACRI_SP2                           (0x400000U)
+#define AIPS_PACRI_TP1                           (0x1000000U)
+#define AIPS_PACRI_WP1                           (0x2000000U)
+#define AIPS_PACRI_SP1                           (0x4000000U)
+#define AIPS_PACRI_TP0                           (0x10000000U)
+#define AIPS_PACRI_WP0                           (0x20000000U)
+#define AIPS_PACRI_SP0                           (0x40000000U)
+
+/*! @name PACRJ - Peripheral Access Control Register */
+#define AIPS_PACRJ_TP7                           (0x1U)
+#define AIPS_PACRJ_WP7                           (0x2U)
+#define AIPS_PACRJ_SP7                           (0x4U)
+#define AIPS_PACRJ_TP6                           (0x10U)
+#define AIPS_PACRJ_WP6                           (0x20U)
+#define AIPS_PACRJ_SP6                           (0x40U)
+#define AIPS_PACRJ_TP5                           (0x100U)
+#define AIPS_PACRJ_WP5                           (0x200U)
+#define AIPS_PACRJ_SP5                           (0x400U)
+#define AIPS_PACRJ_TP4                           (0x1000U)
+#define AIPS_PACRJ_WP4                           (0x2000U)
+#define AIPS_PACRJ_SP4                           (0x4000U)
+#define AIPS_PACRJ_TP3                           (0x10000U)
+#define AIPS_PACRJ_WP3                           (0x20000U)
+#define AIPS_PACRJ_SP3                           (0x40000U)
+#define AIPS_PACRJ_TP2                           (0x100000U)
+#define AIPS_PACRJ_WP2                           (0x200000U)
+#define AIPS_PACRJ_SP2                           (0x400000U)
+#define AIPS_PACRJ_TP1                           (0x1000000U)
+#define AIPS_PACRJ_WP1                           (0x2000000U)
+#define AIPS_PACRJ_SP1                           (0x4000000U)
+#define AIPS_PACRJ_TP0                           (0x10000000U)
+#define AIPS_PACRJ_WP0                           (0x20000000U)
+#define AIPS_PACRJ_SP0                           (0x40000000U)
+
+/*! @name PACRK - Peripheral Access Control Register */
+#define AIPS_PACRK_TP7                           (0x1U)
+#define AIPS_PACRK_WP7                           (0x2U)
+#define AIPS_PACRK_SP7                           (0x4U)
+#define AIPS_PACRK_TP6                           (0x10U)
+#define AIPS_PACRK_WP6                           (0x20U)
+#define AIPS_PACRK_SP6                           (0x40U)
+#define AIPS_PACRK_TP5                           (0x100U)
+#define AIPS_PACRK_WP5                           (0x200U)
+#define AIPS_PACRK_SP5                           (0x400U)
+#define AIPS_PACRK_TP4                           (0x1000U)
+#define AIPS_PACRK_WP4                           (0x2000U)
+#define AIPS_PACRK_SP4                           (0x4000U)
+#define AIPS_PACRK_TP3                           (0x10000U)
+#define AIPS_PACRK_WP3                           (0x20000U)
+#define AIPS_PACRK_SP3                           (0x40000U)
+#define AIPS_PACRK_TP2                           (0x100000U)
+#define AIPS_PACRK_WP2                           (0x200000U)
+#define AIPS_PACRK_SP2                           (0x400000U)
+#define AIPS_PACRK_TP1                           (0x1000000U)
+#define AIPS_PACRK_WP1                           (0x2000000U)
+#define AIPS_PACRK_SP1                           (0x4000000U)
+#define AIPS_PACRK_TP0                           (0x10000000U)
+#define AIPS_PACRK_WP0                           (0x20000000U)
+#define AIPS_PACRK_SP0                           (0x40000000U)
+
+/*! @name PACRL - Peripheral Access Control Register */
+#define AIPS_PACRL_TP7                           (0x1U)
+#define AIPS_PACRL_WP7                           (0x2U)
+#define AIPS_PACRL_SP7                           (0x4U)
+#define AIPS_PACRL_TP6                           (0x10U)
+#define AIPS_PACRL_WP6                           (0x20U)
+#define AIPS_PACRL_SP6                           (0x40U)
+#define AIPS_PACRL_TP5                           (0x100U)
+#define AIPS_PACRL_WP5                           (0x200U)
+#define AIPS_PACRL_SP5                           (0x400U)
+#define AIPS_PACRL_TP4                           (0x1000U)
+#define AIPS_PACRL_WP4                           (0x2000U)
+#define AIPS_PACRL_SP4                           (0x4000U)
+#define AIPS_PACRL_TP3                           (0x10000U)
+#define AIPS_PACRL_WP3                           (0x20000U)
+#define AIPS_PACRL_SP3                           (0x40000U)
+#define AIPS_PACRL_TP2                           (0x100000U)
+#define AIPS_PACRL_WP2                           (0x200000U)
+#define AIPS_PACRL_SP2                           (0x400000U)
+#define AIPS_PACRL_TP1                           (0x1000000U)
+#define AIPS_PACRL_WP1                           (0x2000000U)
+#define AIPS_PACRL_SP1                           (0x4000000U)
+#define AIPS_PACRL_TP0                           (0x10000000U)
+#define AIPS_PACRL_WP0                           (0x20000000U)
+#define AIPS_PACRL_SP0                           (0x40000000U)
+
+/*! @name PACRM - Peripheral Access Control Register */
+#define AIPS_PACRM_TP7                           (0x1U)
+#define AIPS_PACRM_WP7                           (0x2U)
+#define AIPS_PACRM_SP7                           (0x4U)
+#define AIPS_PACRM_TP6                           (0x10U)
+#define AIPS_PACRM_WP6                           (0x20U)
+#define AIPS_PACRM_SP6                           (0x40U)
+#define AIPS_PACRM_TP5                           (0x100U)
+#define AIPS_PACRM_WP5                           (0x200U)
+#define AIPS_PACRM_SP5                           (0x400U)
+#define AIPS_PACRM_TP4                           (0x1000U)
+#define AIPS_PACRM_WP4                           (0x2000U)
+#define AIPS_PACRM_SP4                           (0x4000U)
+#define AIPS_PACRM_TP3                           (0x10000U)
+#define AIPS_PACRM_WP3                           (0x20000U)
+#define AIPS_PACRM_SP3                           (0x40000U)
+#define AIPS_PACRM_TP2                           (0x100000U)
+#define AIPS_PACRM_WP2                           (0x200000U)
+#define AIPS_PACRM_SP2                           (0x400000U)
+#define AIPS_PACRM_TP1                           (0x1000000U)
+#define AIPS_PACRM_WP1                           (0x2000000U)
+#define AIPS_PACRM_SP1                           (0x4000000U)
+#define AIPS_PACRM_TP0                           (0x10000000U)
+#define AIPS_PACRM_WP0                           (0x20000000U)
+#define AIPS_PACRM_SP0                           (0x40000000U)
+
+/*! @name PACRN - Peripheral Access Control Register */
+#define AIPS_PACRN_TP7                           (0x1U)
+#define AIPS_PACRN_WP7                           (0x2U)
+#define AIPS_PACRN_SP7                           (0x4U)
+#define AIPS_PACRN_TP6                           (0x10U)
+#define AIPS_PACRN_WP6                           (0x20U)
+#define AIPS_PACRN_SP6                           (0x40U)
+#define AIPS_PACRN_TP5                           (0x100U)
+#define AIPS_PACRN_WP5                           (0x200U)
+#define AIPS_PACRN_SP5                           (0x400U)
+#define AIPS_PACRN_TP4                           (0x1000U)
+#define AIPS_PACRN_WP4                           (0x2000U)
+#define AIPS_PACRN_SP4                           (0x4000U)
+#define AIPS_PACRN_TP3                           (0x10000U)
+#define AIPS_PACRN_WP3                           (0x20000U)
+#define AIPS_PACRN_SP3                           (0x40000U)
+#define AIPS_PACRN_TP2                           (0x100000U)
+#define AIPS_PACRN_WP2                           (0x200000U)
+#define AIPS_PACRN_SP2                           (0x400000U)
+#define AIPS_PACRN_TP1                           (0x1000000U)
+#define AIPS_PACRN_WP1                           (0x2000000U)
+#define AIPS_PACRN_SP1                           (0x4000000U)
+#define AIPS_PACRN_TP0                           (0x10000000U)
+#define AIPS_PACRN_WP0                           (0x20000000U)
+#define AIPS_PACRN_SP0                           (0x40000000U)
+
+/*! @name PACRO - Peripheral Access Control Register */
+#define AIPS_PACRO_TP7                           (0x1U)
+#define AIPS_PACRO_WP7                           (0x2U)
+#define AIPS_PACRO_SP7                           (0x4U)
+#define AIPS_PACRO_TP6                           (0x10U)
+#define AIPS_PACRO_WP6                           (0x20U)
+#define AIPS_PACRO_SP6                           (0x40U)
+#define AIPS_PACRO_TP5                           (0x100U)
+#define AIPS_PACRO_WP5                           (0x200U)
+#define AIPS_PACRO_SP5                           (0x400U)
+#define AIPS_PACRO_TP4                           (0x1000U)
+#define AIPS_PACRO_WP4                           (0x2000U)
+#define AIPS_PACRO_SP4                           (0x4000U)
+#define AIPS_PACRO_TP3                           (0x10000U)
+#define AIPS_PACRO_WP3                           (0x20000U)
+#define AIPS_PACRO_SP3                           (0x40000U)
+#define AIPS_PACRO_TP2                           (0x100000U)
+#define AIPS_PACRO_WP2                           (0x200000U)
+#define AIPS_PACRO_SP2                           (0x400000U)
+#define AIPS_PACRO_TP1                           (0x1000000U)
+#define AIPS_PACRO_WP1                           (0x2000000U)
+#define AIPS_PACRO_SP1                           (0x4000000U)
+#define AIPS_PACRO_TP0                           (0x10000000U)
+#define AIPS_PACRO_WP0                           (0x20000000U)
+#define AIPS_PACRO_SP0                           (0x40000000U)
+
+/*! @name PACRP - Peripheral Access Control Register */
+#define AIPS_PACRP_TP7                           (0x1U)
+#define AIPS_PACRP_WP7                           (0x2U)
+#define AIPS_PACRP_SP7                           (0x4U)
+#define AIPS_PACRP_TP6                           (0x10U)
+#define AIPS_PACRP_WP6                           (0x20U)
+#define AIPS_PACRP_SP6                           (0x40U)
+#define AIPS_PACRP_TP5                           (0x100U)
+#define AIPS_PACRP_WP5                           (0x200U)
+#define AIPS_PACRP_SP5                           (0x400U)
+#define AIPS_PACRP_TP4                           (0x1000U)
+#define AIPS_PACRP_WP4                           (0x2000U)
+#define AIPS_PACRP_SP4                           (0x4000U)
+#define AIPS_PACRP_TP3                           (0x10000U)
+#define AIPS_PACRP_WP3                           (0x20000U)
+#define AIPS_PACRP_SP3                           (0x40000U)
+#define AIPS_PACRP_TP2                           (0x100000U)
+#define AIPS_PACRP_WP2                           (0x200000U)
+#define AIPS_PACRP_SP2                           (0x400000U)
+#define AIPS_PACRP_TP1                           (0x1000000U)
+#define AIPS_PACRP_WP1                           (0x2000000U)
+#define AIPS_PACRP_SP1                           (0x4000000U)
+#define AIPS_PACRP_TP0                           (0x10000000U)
+#define AIPS_PACRP_WP0                           (0x20000000U)
+#define AIPS_PACRP_SP0                           (0x40000000U)
+
+/*! @name PACRU - Peripheral Access Control Register */
+#define AIPS_PACRU_TP1                           (0x1000000U)
+#define AIPS_PACRU_WP1                           (0x2000000U)
+#define AIPS_PACRU_SP1                           (0x4000000U)
+#define AIPS_PACRU_TP0                           (0x10000000U)
+#define AIPS_PACRU_WP0                           (0x20000000U)
+#define AIPS_PACRU_SP0                           (0x40000000U)
+
+
+/*!
+ * @}
+ */ /* end of group AIPS_Register_Masks */
+
+
+/* AIPS - Peripheral instance base addresses */
+/** Peripheral AIPS0 base address */
+#define AIPS0_BASE                               (0x40000000u)
+/** Peripheral AIPS0 base pointer */
+#define AIPS0                                    ((AIPS_TypeDef *)AIPS0_BASE)
+/** Peripheral AIPS1 base address */
+#define AIPS1_BASE                               (0x40080000u)
+/** Peripheral AIPS1 base pointer */
+#define AIPS1                                    ((AIPS_TypeDef *)AIPS1_BASE)
+/** Array initializer of AIPS peripheral base addresses */
+#define AIPS_BASE_ADDRS                          { AIPS0_BASE, AIPS1_BASE }
+/** Array initializer of AIPS peripheral base pointers */
+#define AIPS_BASE_PTRS                           { AIPS0, AIPS1 }
+
+/*!
+ * @}
+ */ /* end of group AIPS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- AXBS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
+ * @{
+ */
+
+/** AXBS - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x100 */
+    __IO uint32_t PRS;                               /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
+         uint8_t RESERVED_0[12];
+    __IO uint32_t CRS;                               /**< Control Register, array offset: 0x10, array step: 0x100 */
+         uint8_t RESERVED_1[236];
+  } SLAVE[5];
+       uint8_t RESERVED_0[768];
+  __IO uint32_t MGPCR0;                            /**< Master General Purpose Control Register, offset: 0x800 */
+       uint8_t RESERVED_1[252];
+  __IO uint32_t MGPCR1;                            /**< Master General Purpose Control Register, offset: 0x900 */
+       uint8_t RESERVED_2[252];
+  __IO uint32_t MGPCR2;                            /**< Master General Purpose Control Register, offset: 0xA00 */
+       uint8_t RESERVED_3[252];
+  __IO uint32_t MGPCR3;                            /**< Master General Purpose Control Register, offset: 0xB00 */
+       uint8_t RESERVED_4[252];
+  __IO uint32_t MGPCR4;                            /**< Master General Purpose Control Register, offset: 0xC00 */
+       uint8_t RESERVED_5[252];
+  __IO uint32_t MGPCR5;                            /**< Master General Purpose Control Register, offset: 0xD00 */
+} AXBS_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- AXBS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Register_Masks AXBS Register Masks
+ * @{
+ */
+
+/*! @name PRS - Priority Registers Slave */
+#define AXBS_PRS_M0_MASK                         (0x7U)
+#define AXBS_PRS_M0_SHIFT                        (0U)
+#define AXBS_PRS_M0(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)
+#define AXBS_PRS_M1_MASK                         (0x70U)
+#define AXBS_PRS_M1_SHIFT                        (4U)
+#define AXBS_PRS_M1(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)
+#define AXBS_PRS_M2_MASK                         (0x700U)
+#define AXBS_PRS_M2_SHIFT                        (8U)
+#define AXBS_PRS_M2(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)
+#define AXBS_PRS_M3_MASK                         (0x7000U)
+#define AXBS_PRS_M3_SHIFT                        (12U)
+#define AXBS_PRS_M3(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK)
+#define AXBS_PRS_M4_MASK                         (0x70000U)
+#define AXBS_PRS_M4_SHIFT                        (16U)
+#define AXBS_PRS_M4(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK)
+#define AXBS_PRS_M5_MASK                         (0x700000U)
+#define AXBS_PRS_M5_SHIFT                        (20U)
+#define AXBS_PRS_M5(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK)
+
+/* The count of AXBS_PRS */
+#define AXBS_PRS_COUNT                           (5U)
+
+/*! @name CRS - Control Register */
+#define AXBS_CRS_PARK_MASK                       (0x7U)
+#define AXBS_CRS_PARK_SHIFT                      (0U)
+#define AXBS_CRS_PARK(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)
+#define AXBS_CRS_PCTL_MASK                       (0x30U)
+#define AXBS_CRS_PCTL_SHIFT                      (4U)
+#define AXBS_CRS_PCTL(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)
+#define AXBS_CRS_ARB_MASK                        (0x300U)
+#define AXBS_CRS_ARB_SHIFT                       (8U)
+#define AXBS_CRS_ARB(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)
+#define AXBS_CRS_HLP                             (0x40000000U)
+#define AXBS_CRS_RO                              (0x80000000U)
+
+/* The count of AXBS_CRS */
+#define AXBS_CRS_COUNT                           (5U)
+
+/*! @name MGPCR0 - Master General Purpose Control Register */
+#define AXBS_MGPCR0_AULB_MASK                    (0x7U)
+#define AXBS_MGPCR0_AULB_SHIFT                   (0U)
+#define AXBS_MGPCR0_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK)
+
+/*! @name MGPCR1 - Master General Purpose Control Register */
+#define AXBS_MGPCR1_AULB_MASK                    (0x7U)
+#define AXBS_MGPCR1_AULB_SHIFT                   (0U)
+#define AXBS_MGPCR1_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK)
+
+/*! @name MGPCR2 - Master General Purpose Control Register */
+#define AXBS_MGPCR2_AULB_MASK                    (0x7U)
+#define AXBS_MGPCR2_AULB_SHIFT                   (0U)
+#define AXBS_MGPCR2_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK)
+
+/*! @name MGPCR3 - Master General Purpose Control Register */
+#define AXBS_MGPCR3_AULB_MASK                    (0x7U)
+#define AXBS_MGPCR3_AULB_SHIFT                   (0U)
+#define AXBS_MGPCR3_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK)
+
+/*! @name MGPCR4 - Master General Purpose Control Register */
+#define AXBS_MGPCR4_AULB_MASK                    (0x7U)
+#define AXBS_MGPCR4_AULB_SHIFT                   (0U)
+#define AXBS_MGPCR4_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK)
+
+/*! @name MGPCR5 - Master General Purpose Control Register */
+#define AXBS_MGPCR5_AULB_MASK                    (0x7U)
+#define AXBS_MGPCR5_AULB_SHIFT                   (0U)
+#define AXBS_MGPCR5_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group AXBS_Register_Masks */
+
+
+/* AXBS - Peripheral instance base addresses */
+/** Peripheral AXBS base address */
+#define AXBS_BASE                                (0x40004000u)
+/** Peripheral AXBS base pointer */
+#define AXBS                                     ((AXBS_TypeDef *)AXBS_BASE)
+/** Array initializer of AXBS peripheral base addresses */
+#define AXBS_BASE_ADDRS                          { AXBS_BASE }
+/** Array initializer of AXBS peripheral base pointers */
+#define AXBS_BASE_PTRS                           { AXBS }
+
+/*!
+ * @}
+ */ /* end of group AXBS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAN Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
+ * @{
+ */
+
+/** CAN - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< Module Configuration Register, offset: 0x0 */
+  __IO uint32_t CTRL1;                             /**< Control 1 register, offset: 0x4 */
+  __IO uint32_t TIMER;                             /**< Free Running Timer, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t RXMGMASK;                          /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
+  __IO uint32_t RX14MASK;                          /**< Rx 14 Mask register, offset: 0x14 */
+  __IO uint32_t RX15MASK;                          /**< Rx 15 Mask register, offset: 0x18 */
+  __IO uint32_t ECR;                               /**< Error Counter, offset: 0x1C */
+  __IO uint32_t ESR1;                              /**< Error and Status 1 register, offset: 0x20 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t IMASK1;                            /**< Interrupt Masks 1 register, offset: 0x28 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t IFLAG1;                            /**< Interrupt Flags 1 register, offset: 0x30 */
+  __IO uint32_t CTRL2;                             /**< Control 2 register, offset: 0x34 */
+  __I  uint32_t ESR2;                              /**< Error and Status 2 register, offset: 0x38 */
+       uint8_t RESERVED_3[8];
+  __I  uint32_t CRCR;                              /**< CRC Register, offset: 0x44 */
+  __IO uint32_t RXFGMASK;                          /**< Rx FIFO Global Mask register, offset: 0x48 */
+  __I  uint32_t RXFIR;                             /**< Rx FIFO Information Register, offset: 0x4C */
+       uint8_t RESERVED_4[48];
+  struct {                                         /* offset: 0x80, array step: 0x10 */
+    __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
+    __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
+    __IO uint32_t WORD0;                             /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
+    __IO uint32_t WORD1;                             /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
+  } MB[16];
+       uint8_t RESERVED_5[1792];
+  __IO uint32_t RXIMR[16];                         /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
+} CAN_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- CAN Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Masks CAN Register Masks
+ * @{
+ */
+
+/*! @name MCR - Module Configuration Register */
+#define CAN_MCR_MAXMB_MASK                       (0x7FU)
+#define CAN_MCR_MAXMB_SHIFT                      (0U)
+#define CAN_MCR_MAXMB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
+#define CAN_MCR_IDAM_MASK                        (0x300U)
+#define CAN_MCR_IDAM_SHIFT                       (8U)
+#define CAN_MCR_IDAM(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
+#define CAN_MCR_AEN                              (0x1000U)
+#define CAN_MCR_LPRIOEN                          (0x2000U)
+#define CAN_MCR_IRMQ                             (0x10000U)
+#define CAN_MCR_SRXDIS                           (0x20000U)
+#define CAN_MCR_WAKSRC                           (0x80000U)
+#define CAN_MCR_LPMACK                           (0x100000U)
+#define CAN_MCR_WRNEN                            (0x200000U)
+#define CAN_MCR_SLFWAK                           (0x400000U)
+#define CAN_MCR_SUPV                             (0x800000U)
+#define CAN_MCR_FRZACK                           (0x1000000U)
+#define CAN_MCR_SOFTRST                          (0x2000000U)
+#define CAN_MCR_WAKMSK                           (0x4000000U)
+#define CAN_MCR_NOTRDY                           (0x8000000U)
+#define CAN_MCR_HALT                             (0x10000000U)
+#define CAN_MCR_RFEN                             (0x20000000U)
+#define CAN_MCR_FRZ                              (0x40000000U)
+#define CAN_MCR_MDIS                             (0x80000000U)
+
+/*! @name CTRL1 - Control 1 register */
+#define CAN_CTRL1_PROPSEG_MASK                   (0x7U)
+#define CAN_CTRL1_PROPSEG_SHIFT                  (0U)
+#define CAN_CTRL1_PROPSEG(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
+#define CAN_CTRL1_LOM                            (0x8U)
+#define CAN_CTRL1_LBUF                           (0x10U)
+#define CAN_CTRL1_TSYN                           (0x20U)
+#define CAN_CTRL1_BOFFREC                        (0x40U)
+#define CAN_CTRL1_SMP                            (0x80U)
+#define CAN_CTRL1_RWRNMSK                        (0x400U)
+#define CAN_CTRL1_TWRNMSK                        (0x800U)
+#define CAN_CTRL1_LPB                            (0x1000U)
+#define CAN_CTRL1_CLKSRC                         (0x2000U)
+#define CAN_CTRL1_ERRMSK                         (0x4000U)
+#define CAN_CTRL1_BOFFMSK                        (0x8000U)
+#define CAN_CTRL1_PSEG2_MASK                     (0x70000U)
+#define CAN_CTRL1_PSEG2_SHIFT                    (16U)
+#define CAN_CTRL1_PSEG2(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
+#define CAN_CTRL1_PSEG1_MASK                     (0x380000U)
+#define CAN_CTRL1_PSEG1_SHIFT                    (19U)
+#define CAN_CTRL1_PSEG1(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
+#define CAN_CTRL1_RJW_MASK                       (0xC00000U)
+#define CAN_CTRL1_RJW_SHIFT                      (22U)
+#define CAN_CTRL1_RJW(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
+#define CAN_CTRL1_PRESDIV_MASK                   (0xFF000000U)
+#define CAN_CTRL1_PRESDIV_SHIFT                  (24U)
+#define CAN_CTRL1_PRESDIV(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
+
+/*! @name TIMER - Free Running Timer */
+#define CAN_TIMER_TIMER_MASK                     (0xFFFFU)
+#define CAN_TIMER_TIMER_SHIFT                    (0U)
+#define CAN_TIMER_TIMER(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
+
+/*! @name ECR - Error Counter */
+#define CAN_ECR_TXERRCNT_MASK                    (0xFFU)
+#define CAN_ECR_TXERRCNT_SHIFT                   (0U)
+#define CAN_ECR_TXERRCNT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
+#define CAN_ECR_RXERRCNT_MASK                    (0xFF00U)
+#define CAN_ECR_RXERRCNT_SHIFT                   (8U)
+#define CAN_ECR_RXERRCNT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
+
+/*! @name ESR1 - Error and Status 1 register */
+#define CAN_ESR1_WAKINT                          (0x1U)
+#define CAN_ESR1_ERRINT                          (0x2U)
+#define CAN_ESR1_BOFFINT                         (0x4U)
+#define CAN_ESR1_RX                              (0x8U)
+#define CAN_ESR1_FLTCONF_MASK                    (0x30U)
+#define CAN_ESR1_FLTCONF_SHIFT                   (4U)
+#define CAN_ESR1_FLTCONF(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
+#define CAN_ESR1_TX                              (0x40U)
+#define CAN_ESR1_IDLE                            (0x80U)
+#define CAN_ESR1_RXWRN                           (0x100U)
+#define CAN_ESR1_TXWRN                           (0x200U)
+#define CAN_ESR1_STFERR                          (0x400U)
+#define CAN_ESR1_FRMERR                          (0x800U)
+#define CAN_ESR1_CRCERR                          (0x1000U)
+#define CAN_ESR1_ACKERR                          (0x2000U)
+#define CAN_ESR1_BIT0ERR                         (0x4000U)
+#define CAN_ESR1_BIT1ERR                         (0x8000U)
+#define CAN_ESR1_RWRNINT                         (0x10000U)
+#define CAN_ESR1_TWRNINT                         (0x20000U)
+#define CAN_ESR1_SYNCH                           (0x40000U)
+
+/*! @name IFLAG1 - Interrupt Flags 1 register */
+#define CAN_IFLAG1_BUF0I                         (0x1U)
+#define CAN_IFLAG1_BUF4TO1I_MASK                 (0x1EU)
+#define CAN_IFLAG1_BUF4TO1I_SHIFT                (1U)
+#define CAN_IFLAG1_BUF4TO1I(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
+#define CAN_IFLAG1_BUF5I                         (0x20U)
+#define CAN_IFLAG1_BUF6I                         (0x40U)
+#define CAN_IFLAG1_BUF7I                         (0x80U)
+#define CAN_IFLAG1_BUF31TO8I_MASK                (0xFFFFFF00U)
+#define CAN_IFLAG1_BUF31TO8I_SHIFT               (8U)
+#define CAN_IFLAG1_BUF31TO8I(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
+
+/*! @name CTRL2 - Control 2 register */
+#define CAN_CTRL2_EACEN                          (0x10000U)
+#define CAN_CTRL2_RRS                            (0x20000U)
+#define CAN_CTRL2_MRP                            (0x40000U)
+#define CAN_CTRL2_TASD_MASK                      (0xF80000U)
+#define CAN_CTRL2_TASD_SHIFT                     (19U)
+#define CAN_CTRL2_TASD(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
+#define CAN_CTRL2_RFFN_MASK                      (0xF000000U)
+#define CAN_CTRL2_RFFN_SHIFT                     (24U)
+#define CAN_CTRL2_RFFN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
+#define CAN_CTRL2_WRMFRZ                         (0x10000000U)
+
+/*! @name ESR2 - Error and Status 2 register */
+#define CAN_ESR2_IMB                             (0x2000U)
+#define CAN_ESR2_VPS                             (0x4000U)
+#define CAN_ESR2_LPTM_MASK                       (0x7F0000U)
+#define CAN_ESR2_LPTM_SHIFT                      (16U)
+#define CAN_ESR2_LPTM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
+
+/*! @name CRCR - CRC Register */
+#define CAN_CRCR_TXCRC_MASK                      (0x7FFFU)
+#define CAN_CRCR_TXCRC_SHIFT                     (0U)
+#define CAN_CRCR_TXCRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
+#define CAN_CRCR_MBCRC_MASK                      (0x7F0000U)
+#define CAN_CRCR_MBCRC_SHIFT                     (16U)
+#define CAN_CRCR_MBCRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
+
+/*! @name RXFIR - Rx FIFO Information Register */
+#define CAN_RXFIR_IDHIT_MASK                     (0x1FFU)
+#define CAN_RXFIR_IDHIT_SHIFT                    (0U)
+#define CAN_RXFIR_IDHIT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
+
+/*! @name CS - Message Buffer 0 CS Register..Message Buffer 15 CS Register */
+#define CAN_CS_TIME_STAMP_MASK                   (0xFFFFU)
+#define CAN_CS_TIME_STAMP_SHIFT                  (0U)
+#define CAN_CS_TIME_STAMP(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
+#define CAN_CS_DLC_MASK                          (0xF0000U)
+#define CAN_CS_DLC_SHIFT                         (16U)
+#define CAN_CS_DLC(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
+#define CAN_CS_RTR                               (0x100000U)
+#define CAN_CS_IDE                               (0x200000U)
+#define CAN_CS_SRR                               (0x400000U)
+#define CAN_CS_CODE_MASK                         (0xF000000U)
+#define CAN_CS_CODE_SHIFT                        (24U)
+#define CAN_CS_CODE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
+
+/* The count of CAN_CS */
+#define CAN_CS_COUNT                             (16U)
+
+/*! @name ID - Message Buffer 0 ID Register..Message Buffer 15 ID Register */
+#define CAN_ID_EXT_MASK                          (0x3FFFFU)
+#define CAN_ID_EXT_SHIFT                         (0U)
+#define CAN_ID_EXT(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
+#define CAN_ID_STD_MASK                          (0x1FFC0000U)
+#define CAN_ID_STD_SHIFT                         (18U)
+#define CAN_ID_STD(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
+#define CAN_ID_PRIO_MASK                         (0xE0000000U)
+#define CAN_ID_PRIO_SHIFT                        (29U)
+#define CAN_ID_PRIO(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
+
+/* The count of CAN_ID */
+#define CAN_ID_COUNT                             (16U)
+
+/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register */
+#define CAN_WORD0_DATA_BYTE_3_MASK               (0xFFU)
+#define CAN_WORD0_DATA_BYTE_3_SHIFT              (0U)
+#define CAN_WORD0_DATA_BYTE_3(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
+#define CAN_WORD0_DATA_BYTE_2_MASK               (0xFF00U)
+#define CAN_WORD0_DATA_BYTE_2_SHIFT              (8U)
+#define CAN_WORD0_DATA_BYTE_2(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
+#define CAN_WORD0_DATA_BYTE_1_MASK               (0xFF0000U)
+#define CAN_WORD0_DATA_BYTE_1_SHIFT              (16U)
+#define CAN_WORD0_DATA_BYTE_1(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
+#define CAN_WORD0_DATA_BYTE_0_MASK               (0xFF000000U)
+#define CAN_WORD0_DATA_BYTE_0_SHIFT              (24U)
+#define CAN_WORD0_DATA_BYTE_0(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
+
+/* The count of CAN_WORD0 */
+#define CAN_WORD0_COUNT                          (16U)
+
+/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register */
+#define CAN_WORD1_DATA_BYTE_7_MASK               (0xFFU)
+#define CAN_WORD1_DATA_BYTE_7_SHIFT              (0U)
+#define CAN_WORD1_DATA_BYTE_7(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
+#define CAN_WORD1_DATA_BYTE_6_MASK               (0xFF00U)
+#define CAN_WORD1_DATA_BYTE_6_SHIFT              (8U)
+#define CAN_WORD1_DATA_BYTE_6(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
+#define CAN_WORD1_DATA_BYTE_5_MASK               (0xFF0000U)
+#define CAN_WORD1_DATA_BYTE_5_SHIFT              (16U)
+#define CAN_WORD1_DATA_BYTE_5(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
+#define CAN_WORD1_DATA_BYTE_4_MASK               (0xFF000000U)
+#define CAN_WORD1_DATA_BYTE_4_SHIFT              (24U)
+#define CAN_WORD1_DATA_BYTE_4(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
+
+/* The count of CAN_WORD1 */
+#define CAN_WORD1_COUNT                          (16U)
+
+/* The count of CAN_RXIMR */
+#define CAN_RXIMR_COUNT                          (16U)
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Masks */
+
+
+/* CAN - Peripheral instance base addresses */
+/** Peripheral CAN0 base address */
+#define CAN0_BASE                                (0x40024000u)
+/** Peripheral CAN0 base pointer */
+#define CAN0                                     ((CAN_TypeDef *)CAN0_BASE)
+/** Array initializer of CAN peripheral base addresses */
+#define CAN_BASE_ADDRS                           { CAN0_BASE }
+/** Array initializer of CAN peripheral base pointers */
+#define CAN_BASE_PTRS                            { CAN0 }
+/** Interrupt vectors for the CAN peripheral type */
+#define CAN_Rx_Warning_IRQS                      { CAN0_Rx_Warning_IRQn }
+#define CAN_Tx_Warning_IRQS                      { CAN0_Tx_Warning_IRQn }
+#define CAN_Wake_Up_IRQS                         { CAN0_Wake_Up_IRQn }
+#define CAN_Error_IRQS                           { CAN0_Error_IRQn }
+#define CAN_Bus_Off_IRQS                         { CAN0_Bus_Off_IRQn }
+#define CAN_ORed_Message_buffer_IRQS             { CAN0_ORed_Message_buffer_IRQn }
+
+/*!
+ * @}
+ */ /* end of group CAN_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
+ * @{
+ */
+
+/** CAU - Register Layout Typedef */
+typedef struct {
+  __O  uint32_t DIRECT[16];                        /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
+       uint8_t RESERVED_0[2048];
+  __O  uint32_t LDR_CASR;                          /**< Status register - Load Register command, offset: 0x840 */
+  __O  uint32_t LDR_CAA;                           /**< Accumulator register - Load Register command, offset: 0x844 */
+  __O  uint32_t LDR_CA[9];                         /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
+       uint8_t RESERVED_1[20];
+  __I  uint32_t STR_CASR;                          /**< Status register - Store Register command, offset: 0x880 */
+  __I  uint32_t STR_CAA;                           /**< Accumulator register - Store Register command, offset: 0x884 */
+  __I  uint32_t STR_CA[9];                         /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
+       uint8_t RESERVED_2[20];
+  __O  uint32_t ADR_CASR;                          /**< Status register - Add Register command, offset: 0x8C0 */
+  __O  uint32_t ADR_CAA;                           /**< Accumulator register - Add to register command, offset: 0x8C4 */
+  __O  uint32_t ADR_CA[9];                         /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
+       uint8_t RESERVED_3[20];
+  __O  uint32_t RADR_CASR;                         /**< Status register - Reverse and Add to Register command, offset: 0x900 */
+  __O  uint32_t RADR_CAA;                          /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
+  __O  uint32_t RADR_CA[9];                        /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
+       uint8_t RESERVED_4[84];
+  __O  uint32_t XOR_CASR;                          /**< Status register - Exclusive Or command, offset: 0x980 */
+  __O  uint32_t XOR_CAA;                           /**< Accumulator register - Exclusive Or command, offset: 0x984 */
+  __O  uint32_t XOR_CA[9];                         /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
+       uint8_t RESERVED_5[20];
+  __O  uint32_t ROTL_CASR;                         /**< Status register - Rotate Left command, offset: 0x9C0 */
+  __O  uint32_t ROTL_CAA;                          /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
+  __O  uint32_t ROTL_CA[9];                        /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
+       uint8_t RESERVED_6[276];
+  __O  uint32_t AESC_CASR;                         /**< Status register - AES Column Operation command, offset: 0xB00 */
+  __O  uint32_t AESC_CAA;                          /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
+  __O  uint32_t AESC_CA[9];                        /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
+       uint8_t RESERVED_7[20];
+  __O  uint32_t AESIC_CASR;                        /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
+  __O  uint32_t AESIC_CAA;                         /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
+  __O  uint32_t AESIC_CA[9];                       /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
+} CAU_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- CAU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Register_Masks CAU Register Masks
+ * @{
+ */
+
+/* The count of CAU_DIRECT */
+#define CAU_DIRECT_COUNT                         (16U)
+
+/*! @name LDR_CASR - Status register - Load Register command */
+#define CAU_LDR_CASR_IC                          (0x1U)
+#define CAU_LDR_CASR_DPE                         (0x2U)
+#define CAU_LDR_CASR_VER_MASK                    (0xF0000000U)
+#define CAU_LDR_CASR_VER_SHIFT                   (28U)
+#define CAU_LDR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK)
+
+/* The count of CAU_LDR_CA */
+#define CAU_LDR_CA_COUNT                         (9U)
+
+/*! @name STR_CASR - Status register - Store Register command */
+#define CAU_STR_CASR_IC                          (0x1U)
+#define CAU_STR_CASR_DPE                         (0x2U)
+#define CAU_STR_CASR_VER_MASK                    (0xF0000000U)
+#define CAU_STR_CASR_VER_SHIFT                   (28U)
+#define CAU_STR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK)
+
+/* The count of CAU_STR_CA */
+#define CAU_STR_CA_COUNT                         (9U)
+
+/*! @name ADR_CASR - Status register - Add Register command */
+#define CAU_ADR_CASR_IC                          (0x1U)
+#define CAU_ADR_CASR_DPE                         (0x2U)
+#define CAU_ADR_CASR_VER_MASK                    (0xF0000000U)
+#define CAU_ADR_CASR_VER_SHIFT                   (28U)
+#define CAU_ADR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK)
+
+/* The count of CAU_ADR_CA */
+#define CAU_ADR_CA_COUNT                         (9U)
+
+/*! @name RADR_CASR - Status register - Reverse and Add to Register command */
+#define CAU_RADR_CASR_IC                         (0x1U)
+#define CAU_RADR_CASR_DPE                        (0x2U)
+#define CAU_RADR_CASR_VER_MASK                   (0xF0000000U)
+#define CAU_RADR_CASR_VER_SHIFT                  (28U)
+#define CAU_RADR_CASR_VER(x)                     (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK)
+
+/* The count of CAU_RADR_CA */
+#define CAU_RADR_CA_COUNT                        (9U)
+
+/*! @name XOR_CASR - Status register - Exclusive Or command */
+#define CAU_XOR_CASR_IC                          (0x1U)
+#define CAU_XOR_CASR_DPE                         (0x2U)
+#define CAU_XOR_CASR_VER_MASK                    (0xF0000000U)
+#define CAU_XOR_CASR_VER_SHIFT                   (28U)
+#define CAU_XOR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK)
+
+/* The count of CAU_XOR_CA */
+#define CAU_XOR_CA_COUNT                         (9U)
+
+/*! @name ROTL_CASR - Status register - Rotate Left command */
+#define CAU_ROTL_CASR_IC                         (0x1U)
+#define CAU_ROTL_CASR_DPE                        (0x2U)
+#define CAU_ROTL_CASR_VER_MASK                   (0xF0000000U)
+#define CAU_ROTL_CASR_VER_SHIFT                  (28U)
+#define CAU_ROTL_CASR_VER(x)                     (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK)
+
+/* The count of CAU_ROTL_CA */
+#define CAU_ROTL_CA_COUNT                        (9U)
+
+/*! @name AESC_CASR - Status register - AES Column Operation command */
+#define CAU_AESC_CASR_IC                         (0x1U)
+#define CAU_AESC_CASR_DPE                        (0x2U)
+#define CAU_AESC_CASR_VER_MASK                   (0xF0000000U)
+#define CAU_AESC_CASR_VER_SHIFT                  (28U)
+#define CAU_AESC_CASR_VER(x)                     (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK)
+
+/* The count of CAU_AESC_CA */
+#define CAU_AESC_CA_COUNT                        (9U)
+
+/*! @name AESIC_CASR - Status register - AES Inverse Column Operation command */
+#define CAU_AESIC_CASR_IC                        (0x1U)
+#define CAU_AESIC_CASR_DPE                       (0x2U)
+#define CAU_AESIC_CASR_VER_MASK                  (0xF0000000U)
+#define CAU_AESIC_CASR_VER_SHIFT                 (28U)
+#define CAU_AESIC_CASR_VER(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK)
+
+/* The count of CAU_AESIC_CA */
+#define CAU_AESIC_CA_COUNT                       (9U)
+
+
+/*!
+ * @}
+ */ /* end of group CAU_Register_Masks */
+
+
+/* CAU - Peripheral instance base addresses */
+/** Peripheral CAU base address */
+#define CAU_BASE                                 (0xE0081000u)
+/** Peripheral CAU base pointer */
+#define CAU                                      ((CAU_TypeDef *)CAU_BASE)
+/** Array initializer of CAU peripheral base addresses */
+#define CAU_BASE_ADDRS                           { CAU_BASE }
+/** Array initializer of CAU peripheral base pointers */
+#define CAU_BASE_PTRS                            { CAU }
+
+/*!
+ * @}
+ */ /* end of group CAU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMP Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CR0;                                /**< CMP Control Register 0, offset: 0x0 */
+  __IO uint8_t CR1;                                /**< CMP Control Register 1, offset: 0x1 */
+  __IO uint8_t FPR;                                /**< CMP Filter Period Register, offset: 0x2 */
+  __IO uint8_t SCR;                                /**< CMP Status and Control Register, offset: 0x3 */
+  __IO uint8_t DACCR;                              /**< DAC Control Register, offset: 0x4 */
+  __IO uint8_t MUXCR;                              /**< MUX Control Register, offset: 0x5 */
+} CMP_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- CMP Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/*! @name CR0 - CMP Control Register 0 */
+#define CMP_CR0_HYSTCTR_MASK                     (0x3U)
+#define CMP_CR0_HYSTCTR_SHIFT                    (0U)
+#define CMP_CR0_HYSTCTR(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK                  (0x70U)
+#define CMP_CR0_FILTER_CNT_SHIFT                 (4U)
+#define CMP_CR0_FILTER_CNT(x)                    (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
+
+/*! @name CR1 - CMP Control Register 1 */
+#define CMP_CR1_EN                               (0x1U)
+#define CMP_CR1_OPE                              (0x2U)
+#define CMP_CR1_COS                              (0x4U)
+#define CMP_CR1_INV                              (0x8U)
+#define CMP_CR1_PMODE                            (0x10U)
+#define CMP_CR1_WE                               (0x40U)
+#define CMP_CR1_SE                               (0x80U)
+
+/*! @name FPR - CMP Filter Period Register */
+#define CMP_FPR_FILT_PER_MASK                    (0xFFU)
+#define CMP_FPR_FILT_PER_SHIFT                   (0U)
+#define CMP_FPR_FILT_PER(x)                      (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
+
+/*! @name SCR - CMP Status and Control Register */
+#define CMP_SCR_COUT                             (0x1U)
+#define CMP_SCR_CFF                              (0x2U)
+#define CMP_SCR_CFR                              (0x4U)
+#define CMP_SCR_IEF                              (0x8U)
+#define CMP_SCR_IER                              (0x10U)
+#define CMP_SCR_DMAEN                            (0x40U)
+
+/*! @name DACCR - DAC Control Register */
+#define CMP_DACCR_VOSEL_MASK                     (0x3FU)
+#define CMP_DACCR_VOSEL_SHIFT                    (0U)
+#define CMP_DACCR_VOSEL(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL                          (0x40U)
+#define CMP_DACCR_DACEN                          (0x80U)
+
+/*! @name MUXCR - MUX Control Register */
+#define CMP_MUXCR_MSEL_MASK                      (0x7U)
+#define CMP_MUXCR_MSEL_SHIFT                     (0U)
+#define CMP_MUXCR_MSEL(x)                        (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK                      (0x38U)
+#define CMP_MUXCR_PSEL_SHIFT                     (3U)
+#define CMP_MUXCR_PSEL(x)                        (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
+#define CMP_MUXCR_PSTM                           (0x80U)
+
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE                                (0x40073000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0                                     ((CMP_TypeDef *)CMP0_BASE)
+/** Peripheral CMP1 base address */
+#define CMP1_BASE                                (0x40073008u)
+/** Peripheral CMP1 base pointer */
+#define CMP1                                     ((CMP_TypeDef *)CMP1_BASE)
+/** Peripheral CMP2 base address */
+#define CMP2_BASE                                (0x40073010u)
+/** Peripheral CMP2 base pointer */
+#define CMP2                                     ((CMP_TypeDef *)CMP2_BASE)
+/** Array initializer of CMP peripheral base addresses */
+#define CMP_BASE_ADDRS                           { CMP0_BASE, CMP1_BASE, CMP2_BASE }
+/** Array initializer of CMP peripheral base pointers */
+#define CMP_BASE_PTRS                            { CMP0, CMP1, CMP2 }
+/** Interrupt vectors for the CMP peripheral type */
+#define CMP_IRQS                                 { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn }
+
+/*!
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
+ * @{
+ */
+
+/** CMT - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CGH1;                               /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
+  __IO uint8_t CGL1;                               /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
+  __IO uint8_t CGH2;                               /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
+  __IO uint8_t CGL2;                               /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
+  __IO uint8_t OC;                                 /**< CMT Output Control Register, offset: 0x4 */
+  __IO uint8_t MSC;                                /**< CMT Modulator Status and Control Register, offset: 0x5 */
+  __IO uint8_t CMD1;                               /**< CMT Modulator Data Register Mark High, offset: 0x6 */
+  __IO uint8_t CMD2;                               /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
+  __IO uint8_t CMD3;                               /**< CMT Modulator Data Register Space High, offset: 0x8 */
+  __IO uint8_t CMD4;                               /**< CMT Modulator Data Register Space Low, offset: 0x9 */
+  __IO uint8_t PPS;                                /**< CMT Primary Prescaler Register, offset: 0xA */
+  __IO uint8_t DMA;                                /**< CMT Direct Memory Access Register, offset: 0xB */
+} CMT_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- CMT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Register_Masks CMT Register Masks
+ * @{
+ */
+
+/*! @name CGH1 - CMT Carrier Generator High Data Register 1 */
+#define CMT_CGH1_PH_MASK                         (0xFFU)
+#define CMT_CGH1_PH_SHIFT                        (0U)
+#define CMT_CGH1_PH(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK)
+
+/*! @name CGL1 - CMT Carrier Generator Low Data Register 1 */
+#define CMT_CGL1_PL_MASK                         (0xFFU)
+#define CMT_CGL1_PL_SHIFT                        (0U)
+#define CMT_CGL1_PL(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK)
+
+/*! @name CGH2 - CMT Carrier Generator High Data Register 2 */
+#define CMT_CGH2_SH_MASK                         (0xFFU)
+#define CMT_CGH2_SH_SHIFT                        (0U)
+#define CMT_CGH2_SH(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK)
+
+/*! @name CGL2 - CMT Carrier Generator Low Data Register 2 */
+#define CMT_CGL2_SL_MASK                         (0xFFU)
+#define CMT_CGL2_SL_SHIFT                        (0U)
+#define CMT_CGL2_SL(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK)
+
+/*! @name OC - CMT Output Control Register */
+#define CMT_OC_IROPEN                            (0x20U)
+#define CMT_OC_CMTPOL                            (0x40U)
+#define CMT_OC_IROL                              (0x80U)
+
+/*! @name MSC - CMT Modulator Status and Control Register */
+#define CMT_MSC_MCGEN                            (0x1U)
+#define CMT_MSC_EOCIE                            (0x2U)
+#define CMT_MSC_FSK                              (0x4U)
+#define CMT_MSC_BASE                             (0x8U)
+#define CMT_MSC_EXSPC                            (0x10U)
+#define CMT_MSC_CMTDIV_MASK                      (0x60U)
+#define CMT_MSC_CMTDIV_SHIFT                     (5U)
+#define CMT_MSC_CMTDIV(x)                        (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK)
+#define CMT_MSC_EOCF                             (0x80U)
+
+/*! @name CMD1 - CMT Modulator Data Register Mark High */
+#define CMT_CMD1_MB_MASK                         (0xFFU)
+#define CMT_CMD1_MB_SHIFT                        (0U)
+#define CMT_CMD1_MB(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK)
+
+/*! @name CMD2 - CMT Modulator Data Register Mark Low */
+#define CMT_CMD2_MB_MASK                         (0xFFU)
+#define CMT_CMD2_MB_SHIFT                        (0U)
+#define CMT_CMD2_MB(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK)
+
+/*! @name CMD3 - CMT Modulator Data Register Space High */
+#define CMT_CMD3_SB_MASK                         (0xFFU)
+#define CMT_CMD3_SB_SHIFT                        (0U)
+#define CMT_CMD3_SB(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK)
+
+/*! @name CMD4 - CMT Modulator Data Register Space Low */
+#define CMT_CMD4_SB_MASK                         (0xFFU)
+#define CMT_CMD4_SB_SHIFT                        (0U)
+#define CMT_CMD4_SB(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK)
+
+/*! @name PPS - CMT Primary Prescaler Register */
+#define CMT_PPS_PPSDIV_MASK                      (0xFU)
+#define CMT_PPS_PPSDIV_SHIFT                     (0U)
+#define CMT_PPS_PPSDIV(x)                        (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK)
+
+/*! @name DMA - CMT Direct Memory Access Register */
+#define CMT_DMA_DMA                              (0x1U)
+
+
+/*!
+ * @}
+ */ /* end of group CMT_Register_Masks */
+
+
+/* CMT - Peripheral instance base addresses */
+/** Peripheral CMT base address */
+#define CMT_BASE                                 (0x40062000u)
+/** Peripheral CMT base pointer */
+#define CMT                                      ((CMT_TypeDef *)CMT_BASE)
+/** Array initializer of CMT peripheral base addresses */
+#define CMT_BASE_ADDRS                           { CMT_BASE }
+/** Array initializer of CMT peripheral base pointers */
+#define CMT_BASE_PTRS                            { CMT }
+/** Interrupt vectors for the CMT peripheral type */
+#define CMT_IRQS                                 { CMT_IRQn }
+
+/*!
+ * @}
+ */ /* end of group CMT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CRC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+  union {                                          /* offset: 0x0 */
+    struct {                                         /* offset: 0x0 */
+      __IO uint16_t DATAL;                             /**< CRC_DATAL register., offset: 0x0 */
+      __IO uint16_t DATAH;                             /**< CRC_DATAH register., offset: 0x2 */
+    } ACCESS16BIT;
+    __IO uint32_t DATA;                              /**< CRC Data register, offset: 0x0 */
+    struct {                                         /* offset: 0x0 */
+      __IO uint8_t DATALL;                             /**< CRC_DATALL register., offset: 0x0 */
+      __IO uint8_t DATALU;                             /**< CRC_DATALU register., offset: 0x1 */
+      __IO uint8_t DATAHL;                             /**< CRC_DATAHL register., offset: 0x2 */
+      __IO uint8_t DATAHU;                             /**< CRC_DATAHU register., offset: 0x3 */
+    } ACCESS8BIT;
+  };
+  union {                                          /* offset: 0x4 */
+    struct {                                         /* offset: 0x4 */
+      __IO uint16_t GPOLYL;                            /**< CRC_GPOLYL register., offset: 0x4 */
+      __IO uint16_t GPOLYH;                            /**< CRC_GPOLYH register., offset: 0x6 */
+    } GPOLY_ACCESS16BIT;
+    __IO uint32_t GPOLY;                             /**< CRC Polynomial register, offset: 0x4 */
+    struct {                                         /* offset: 0x4 */
+      __IO uint8_t GPOLYLL;                            /**< CRC_GPOLYLL register., offset: 0x4 */
+      __IO uint8_t GPOLYLU;                            /**< CRC_GPOLYLU register., offset: 0x5 */
+      __IO uint8_t GPOLYHL;                            /**< CRC_GPOLYHL register., offset: 0x6 */
+      __IO uint8_t GPOLYHU;                            /**< CRC_GPOLYHU register., offset: 0x7 */
+    } GPOLY_ACCESS8BIT;
+  };
+  union {                                          /* offset: 0x8 */
+    __IO uint32_t CTRL;                              /**< CRC Control register, offset: 0x8 */
+    struct {                                         /* offset: 0x8 */
+           uint8_t RESERVED_0[3];
+      __IO uint8_t CTRLHU;                             /**< CRC_CTRLHU register., offset: 0xB */
+    } CTRL_ACCESS8BIT;
+  };
+} CRC_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- CRC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/*! @name DATAL - CRC_DATAL register. */
+#define CRC_DATAL_DATAL_MASK                     (0xFFFFU)
+#define CRC_DATAL_DATAL_SHIFT                    (0U)
+#define CRC_DATAL_DATAL(x)                       (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
+
+/*! @name DATAH - CRC_DATAH register. */
+#define CRC_DATAH_DATAH_MASK                     (0xFFFFU)
+#define CRC_DATAH_DATAH_SHIFT                    (0U)
+#define CRC_DATAH_DATAH(x)                       (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
+
+/*! @name DATA - CRC Data register */
+#define CRC_DATA_LL_MASK                         (0xFFU)
+#define CRC_DATA_LL_SHIFT                        (0U)
+#define CRC_DATA_LL(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
+#define CRC_DATA_LU_MASK                         (0xFF00U)
+#define CRC_DATA_LU_SHIFT                        (8U)
+#define CRC_DATA_LU(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
+#define CRC_DATA_HL_MASK                         (0xFF0000U)
+#define CRC_DATA_HL_SHIFT                        (16U)
+#define CRC_DATA_HL(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
+#define CRC_DATA_HU_MASK                         (0xFF000000U)
+#define CRC_DATA_HU_SHIFT                        (24U)
+#define CRC_DATA_HU(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
+
+/*! @name DATALL - CRC_DATALL register. */
+#define CRC_DATALL_DATALL_MASK                   (0xFFU)
+#define CRC_DATALL_DATALL_SHIFT                  (0U)
+#define CRC_DATALL_DATALL(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
+
+/*! @name DATALU - CRC_DATALU register. */
+#define CRC_DATALU_DATALU_MASK                   (0xFFU)
+#define CRC_DATALU_DATALU_SHIFT                  (0U)
+#define CRC_DATALU_DATALU(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
+
+/*! @name DATAHL - CRC_DATAHL register. */
+#define CRC_DATAHL_DATAHL_MASK                   (0xFFU)
+#define CRC_DATAHL_DATAHL_SHIFT                  (0U)
+#define CRC_DATAHL_DATAHL(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
+
+/*! @name DATAHU - CRC_DATAHU register. */
+#define CRC_DATAHU_DATAHU_MASK                   (0xFFU)
+#define CRC_DATAHU_DATAHU_SHIFT                  (0U)
+#define CRC_DATAHU_DATAHU(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
+
+/*! @name GPOLYL - CRC_GPOLYL register. */
+#define CRC_GPOLYL_GPOLYL_MASK                   (0xFFFFU)
+#define CRC_GPOLYL_GPOLYL_SHIFT                  (0U)
+#define CRC_GPOLYL_GPOLYL(x)                     (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
+
+/*! @name GPOLYH - CRC_GPOLYH register. */
+#define CRC_GPOLYH_GPOLYH_MASK                   (0xFFFFU)
+#define CRC_GPOLYH_GPOLYH_SHIFT                  (0U)
+#define CRC_GPOLYH_GPOLYH(x)                     (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
+
+/*! @name GPOLY - CRC Polynomial register */
+#define CRC_GPOLY_LOW_MASK                       (0xFFFFU)
+#define CRC_GPOLY_LOW_SHIFT                      (0U)
+#define CRC_GPOLY_LOW(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
+#define CRC_GPOLY_HIGH_MASK                      (0xFFFF0000U)
+#define CRC_GPOLY_HIGH_SHIFT                     (16U)
+#define CRC_GPOLY_HIGH(x)                        (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
+
+/*! @name GPOLYLL - CRC_GPOLYLL register. */
+#define CRC_GPOLYLL_GPOLYLL_MASK                 (0xFFU)
+#define CRC_GPOLYLL_GPOLYLL_SHIFT                (0U)
+#define CRC_GPOLYLL_GPOLYLL(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
+
+/*! @name GPOLYLU - CRC_GPOLYLU register. */
+#define CRC_GPOLYLU_GPOLYLU_MASK                 (0xFFU)
+#define CRC_GPOLYLU_GPOLYLU_SHIFT                (0U)
+#define CRC_GPOLYLU_GPOLYLU(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
+
+/*! @name GPOLYHL - CRC_GPOLYHL register. */
+#define CRC_GPOLYHL_GPOLYHL_MASK                 (0xFFU)
+#define CRC_GPOLYHL_GPOLYHL_SHIFT                (0U)
+#define CRC_GPOLYHL_GPOLYHL(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
+
+/*! @name GPOLYHU - CRC_GPOLYHU register. */
+#define CRC_GPOLYHU_GPOLYHU_MASK                 (0xFFU)
+#define CRC_GPOLYHU_GPOLYHU_SHIFT                (0U)
+#define CRC_GPOLYHU_GPOLYHU(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
+
+/*! @name CTRL - CRC Control register */
+#define CRC_CTRL_TCRC                            (0x1000000U)
+#define CRC_CTRL_WAS                             (0x2000000U)
+#define CRC_CTRL_FXOR                            (0x4000000U)
+#define CRC_CTRL_TOTR_MASK                       (0x30000000U)
+#define CRC_CTRL_TOTR_SHIFT                      (28U)
+#define CRC_CTRL_TOTR(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
+#define CRC_CTRL_TOT_MASK                        (0xC0000000U)
+#define CRC_CTRL_TOT_SHIFT                       (30U)
+#define CRC_CTRL_TOT(x)                          (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
+
+/*! @name CTRLHU - CRC_CTRLHU register. */
+#define CRC_CTRLHU_TCRC                          (0x1U)
+#define CRC_CTRLHU_WAS                           (0x2U)
+#define CRC_CTRLHU_FXOR                          (0x4U)
+#define CRC_CTRLHU_TOTR_MASK                     (0x30U)
+#define CRC_CTRLHU_TOTR_SHIFT                    (4U)
+#define CRC_CTRLHU_TOTR(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
+#define CRC_CTRLHU_TOT_MASK                      (0xC0U)
+#define CRC_CTRLHU_TOT_SHIFT                     (6U)
+#define CRC_CTRLHU_TOT(x)                        (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC base address */
+#define CRC_BASE                                 (0x40032000u)
+/** Peripheral CRC base pointer */
+#define CRC0                                     ((CRC_TypeDef *)CRC_BASE)
+/** Array initializer of CRC peripheral base addresses */
+#define CRC_BASE_ADDRS                           { CRC_BASE }
+/** Array initializer of CRC peripheral base pointers */
+#define CRC_BASE_PTRS                            { CRC0 }
+
+/*!
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DAC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
+ * @{
+ */
+
+/** DAC - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x2 */
+    __IO uint8_t DATL;                               /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
+    __IO uint8_t DATH;                               /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
+  } DAT[16];
+  __IO uint8_t SR;                                 /**< DAC Status Register, offset: 0x20 */
+  __IO uint8_t C0;                                 /**< DAC Control Register, offset: 0x21 */
+  __IO uint8_t C1;                                 /**< DAC Control Register 1, offset: 0x22 */
+  __IO uint8_t C2;                                 /**< DAC Control Register 2, offset: 0x23 */
+} DAC_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- DAC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Masks DAC Register Masks
+ * @{
+ */
+
+/*! @name DATL - DAC Data Low Register */
+#define DAC_DATL_DATA0_MASK                      (0xFFU)
+#define DAC_DATL_DATA0_SHIFT                     (0U)
+#define DAC_DATL_DATA0(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
+
+/* The count of DAC_DATL */
+#define DAC_DATL_COUNT                           (16U)
+
+/*! @name DATH - DAC Data High Register */
+#define DAC_DATH_DATA1_MASK                      (0xFU)
+#define DAC_DATH_DATA1_SHIFT                     (0U)
+#define DAC_DATH_DATA1(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
+
+/* The count of DAC_DATH */
+#define DAC_DATH_COUNT                           (16U)
+
+/*! @name SR - DAC Status Register */
+#define DAC_SR_DACBFRPBF                         (0x1U)
+#define DAC_SR_DACBFRPTF                         (0x2U)
+#define DAC_SR_DACBFWMF                          (0x4U)
+
+/*! @name C0 - DAC Control Register */
+#define DAC_C0_DACBBIEN                          (0x1U)
+#define DAC_C0_DACBTIEN                          (0x2U)
+#define DAC_C0_DACBWIEN                          (0x4U)
+#define DAC_C0_LPEN                              (0x8U)
+#define DAC_C0_DACSWTRG                          (0x10U)
+#define DAC_C0_DACTRGSEL                         (0x20U)
+#define DAC_C0_DACRFS                            (0x40U)
+#define DAC_C0_DACEN                             (0x80U)
+
+/*! @name C1 - DAC Control Register 1 */
+#define DAC_C1_DACBFEN                           (0x1U)
+#define DAC_C1_DACBFMD_MASK                      (0x6U)
+#define DAC_C1_DACBFMD_SHIFT                     (1U)
+#define DAC_C1_DACBFMD(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
+#define DAC_C1_DACBFWM_MASK                      (0x18U)
+#define DAC_C1_DACBFWM_SHIFT                     (3U)
+#define DAC_C1_DACBFWM(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK)
+#define DAC_C1_DMAEN                             (0x80U)
+
+/*! @name C2 - DAC Control Register 2 */
+#define DAC_C2_DACBFUP_MASK                      (0xFU)
+#define DAC_C2_DACBFUP_SHIFT                     (0U)
+#define DAC_C2_DACBFUP(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
+#define DAC_C2_DACBFRP_MASK                      (0xF0U)
+#define DAC_C2_DACBFRP_SHIFT                     (4U)
+#define DAC_C2_DACBFRP(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Masks */
+
+
+/* DAC - Peripheral instance base addresses */
+/** Peripheral DAC0 base address */
+#define DAC0_BASE                                (0x400CC000u)
+/** Peripheral DAC0 base pointer */
+#define DAC0                                     ((DAC_TypeDef *)DAC0_BASE)
+/** Peripheral DAC1 base address */
+#define DAC1_BASE                                (0x400CD000u)
+/** Peripheral DAC1 base pointer */
+#define DAC1                                     ((DAC_TypeDef *)DAC1_BASE)
+/** Array initializer of DAC peripheral base addresses */
+#define DAC_BASE_ADDRS                           { DAC0_BASE, DAC1_BASE }
+/** Array initializer of DAC peripheral base pointers */
+#define DAC_BASE_PTRS                            { DAC0, DAC1 }
+/** Interrupt vectors for the DAC peripheral type */
+#define DAC_IRQS                                 { DAC0_IRQn, DAC1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMA Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CR;                                /**< Control Register, offset: 0x0 */
+  __I  uint32_t ES;                                /**< Error Status Register, offset: 0x4 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t ERQ;                               /**< Enable Request Register, offset: 0xC */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t EEI;                               /**< Enable Error Interrupt Register, offset: 0x14 */
+  __O  uint8_t CEEI;                               /**< Clear Enable Error Interrupt Register, offset: 0x18 */
+  __O  uint8_t SEEI;                               /**< Set Enable Error Interrupt Register, offset: 0x19 */
+  __O  uint8_t CERQ;                               /**< Clear Enable Request Register, offset: 0x1A */
+  __O  uint8_t SERQ;                               /**< Set Enable Request Register, offset: 0x1B */
+  __O  uint8_t CDNE;                               /**< Clear DONE Status Bit Register, offset: 0x1C */
+  __O  uint8_t SSRT;                               /**< Set START Bit Register, offset: 0x1D */
+  __O  uint8_t CERR;                               /**< Clear Error Register, offset: 0x1E */
+  __O  uint8_t CINT;                               /**< Clear Interrupt Request Register, offset: 0x1F */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t INT;                               /**< Interrupt Request Register, offset: 0x24 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t ERR;                               /**< Error Register, offset: 0x2C */
+       uint8_t RESERVED_4[4];
+  __I  uint32_t HRS;                               /**< Hardware Request Status Register, offset: 0x34 */
+       uint8_t RESERVED_5[200];
+  __IO uint8_t DCHPRI3;                            /**< Channel n Priority Register, offset: 0x100 */
+  __IO uint8_t DCHPRI2;                            /**< Channel n Priority Register, offset: 0x101 */
+  __IO uint8_t DCHPRI1;                            /**< Channel n Priority Register, offset: 0x102 */
+  __IO uint8_t DCHPRI0;                            /**< Channel n Priority Register, offset: 0x103 */
+  __IO uint8_t DCHPRI7;                            /**< Channel n Priority Register, offset: 0x104 */
+  __IO uint8_t DCHPRI6;                            /**< Channel n Priority Register, offset: 0x105 */
+  __IO uint8_t DCHPRI5;                            /**< Channel n Priority Register, offset: 0x106 */
+  __IO uint8_t DCHPRI4;                            /**< Channel n Priority Register, offset: 0x107 */
+  __IO uint8_t DCHPRI11;                           /**< Channel n Priority Register, offset: 0x108 */
+  __IO uint8_t DCHPRI10;                           /**< Channel n Priority Register, offset: 0x109 */
+  __IO uint8_t DCHPRI9;                            /**< Channel n Priority Register, offset: 0x10A */
+  __IO uint8_t DCHPRI8;                            /**< Channel n Priority Register, offset: 0x10B */
+  __IO uint8_t DCHPRI15;                           /**< Channel n Priority Register, offset: 0x10C */
+  __IO uint8_t DCHPRI14;                           /**< Channel n Priority Register, offset: 0x10D */
+  __IO uint8_t DCHPRI13;                           /**< Channel n Priority Register, offset: 0x10E */
+  __IO uint8_t DCHPRI12;                           /**< Channel n Priority Register, offset: 0x10F */
+       uint8_t RESERVED_6[3824];
+  struct {                                         /* offset: 0x1000, array step: 0x20 */
+    __IO uint32_t SADDR;                             /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
+    __IO uint16_t SOFF;                              /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
+    __IO uint16_t ATTR;                              /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
+    union {                                          /* offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLNO;                       /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLOFFNO;                    /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLOFFYES;                   /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
+    };
+    __IO uint32_t SLAST;                             /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
+    __IO uint32_t DADDR;                             /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
+    __IO uint16_t DOFF;                              /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
+    union {                                          /* offset: 0x1016, array step: 0x20 */
+      __IO uint16_t CITER_ELINKNO;                     /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
+      __IO uint16_t CITER_ELINKYES;                    /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
+    };
+    __IO uint32_t DLAST_SGA;                         /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
+    __IO uint16_t CSR;                               /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
+    union {                                          /* offset: 0x101E, array step: 0x20 */
+      __IO uint16_t BITER_ELINKNO;                     /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
+      __IO uint16_t BITER_ELINKYES;                    /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
+    };
+  } TCD[16];
+} DMA_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- DMA Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/*! @name CR - Control Register */
+#define DMA_CR_EDBG                              (0x2U)
+#define DMA_CR_ERCA                              (0x4U)
+#define DMA_CR_HOE                               (0x10U)
+#define DMA_CR_HALT                              (0x20U)
+#define DMA_CR_CLM                               (0x40U)
+#define DMA_CR_EMLM                              (0x80U)
+#define DMA_CR_ECX                               (0x10000U)
+#define DMA_CR_CX                                (0x20000U)
+
+/*! @name ES - Error Status Register */
+#define DMA_ES_DBE                               (0x1U)
+#define DMA_ES_SBE                               (0x2U)
+#define DMA_ES_SGE                               (0x4U)
+#define DMA_ES_NCE                               (0x8U)
+#define DMA_ES_DOE                               (0x10U)
+#define DMA_ES_DAE                               (0x20U)
+#define DMA_ES_SOE                               (0x40U)
+#define DMA_ES_SAE                               (0x80U)
+#define DMA_ES_ERRCHN_MASK                       (0xF00U)
+#define DMA_ES_ERRCHN_SHIFT                      (8U)
+#define DMA_ES_ERRCHN(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
+#define DMA_ES_CPE                               (0x4000U)
+#define DMA_ES_ECX                               (0x10000U)
+#define DMA_ES_VLD                               (0x80000000U)
+
+/*! @name CEEI - Clear Enable Error Interrupt Register */
+#define DMA_CEEI_CEEI_MASK                       (0xFU)
+#define DMA_CEEI_CEEI_SHIFT                      (0U)
+#define DMA_CEEI_CEEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
+#define DMA_CEEI_CAEE                            (0x40U)
+#define DMA_CEEI_NOP                             (0x80U)
+
+/*! @name SEEI - Set Enable Error Interrupt Register */
+#define DMA_SEEI_SEEI_MASK                       (0xFU)
+#define DMA_SEEI_SEEI_SHIFT                      (0U)
+#define DMA_SEEI_SEEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
+#define DMA_SEEI_SAEE                            (0x40U)
+#define DMA_SEEI_NOP                             (0x80U)
+
+/*! @name CERQ - Clear Enable Request Register */
+#define DMA_CERQ_CERQ_MASK                       (0xFU)
+#define DMA_CERQ_CERQ_SHIFT                      (0U)
+#define DMA_CERQ_CERQ(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
+#define DMA_CERQ_CAER                            (0x40U)
+#define DMA_CERQ_NOP                             (0x80U)
+
+/*! @name SERQ - Set Enable Request Register */
+#define DMA_SERQ_SERQ_MASK                       (0xFU)
+#define DMA_SERQ_SERQ_SHIFT                      (0U)
+#define DMA_SERQ_SERQ(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
+#define DMA_SERQ_SAER                            (0x40U)
+#define DMA_SERQ_NOP                             (0x80U)
+
+/*! @name CDNE - Clear DONE Status Bit Register */
+#define DMA_CDNE_CDNE_MASK                       (0xFU)
+#define DMA_CDNE_CDNE_SHIFT                      (0U)
+#define DMA_CDNE_CDNE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
+#define DMA_CDNE_CADN                            (0x40U)
+#define DMA_CDNE_NOP                             (0x80U)
+
+/*! @name SSRT - Set START Bit Register */
+#define DMA_SSRT_SSRT_MASK                       (0xFU)
+#define DMA_SSRT_SSRT_SHIFT                      (0U)
+#define DMA_SSRT_SSRT(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
+#define DMA_SSRT_SAST                            (0x40U)
+#define DMA_SSRT_NOP                             (0x80U)
+
+/*! @name CERR - Clear Error Register */
+#define DMA_CERR_CERR_MASK                       (0xFU)
+#define DMA_CERR_CERR_SHIFT                      (0U)
+#define DMA_CERR_CERR(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
+#define DMA_CERR_CAEI                            (0x40U)
+#define DMA_CERR_NOP                             (0x80U)
+
+/*! @name CINT - Clear Interrupt Request Register */
+#define DMA_CINT_CINT_MASK                       (0xFU)
+#define DMA_CINT_CINT_SHIFT                      (0U)
+#define DMA_CINT_CINT(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
+#define DMA_CINT_CAIR                            (0x40U)
+#define DMA_CINT_NOP                             (0x80U)
+
+/*! @name DCHPRIn - Channel n Priority Register */
+#define DMA_DCHPRIn_CHPRI_MASK                   (0xFU)
+#define DMA_DCHPRIn_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI3_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
+#define DMA_DCHPRIn_DPA                          (0x40U)
+#define DMA_DCHPRIn_ECP                          (0x80U)
+
+/*! @name SOFF - TCD Signed Source Address Offset */
+#define DMA_SOFF_SOFF_MASK                       (0xFFFFU)
+#define DMA_SOFF_SOFF_SHIFT                      (0U)
+#define DMA_SOFF_SOFF(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
+
+/*! @name ATTR - TCD Transfer Attributes */
+#define DMA_ATTR_DSIZE_MASK                      (0x7U)
+#define DMA_ATTR_DSIZE_SHIFT                     (0U)
+#define DMA_ATTR_DSIZE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
+#define DMA_ATTR_DMOD_MASK                       (0xF8U)
+#define DMA_ATTR_DMOD_SHIFT                      (3U)
+#define DMA_ATTR_DMOD(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
+#define DMA_ATTR_SSIZE_MASK                      (0x700U)
+#define DMA_ATTR_SSIZE_SHIFT                     (8U)
+#define DMA_ATTR_SSIZE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
+#define DMA_ATTR_SMOD_MASK                       (0xF800U)
+#define DMA_ATTR_SMOD_SHIFT                      (11U)
+#define DMA_ATTR_SMOD(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
+
+/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) */
+#define DMA_NBYTES_MLOFFNO_NBYTES_MASK           (0x3FFFFFFFU)
+#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT          (0U)
+#define DMA_NBYTES_MLOFFNO_NBYTES(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFNO_DMLOE                 (0x40000000U)
+#define DMA_NBYTES_MLOFFNO_SMLOE                 (0x80000000U)
+
+/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) */
+#define DMA_NBYTES_MLOFFYES_NBYTES_MASK          (0x3FFU)
+#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT         (0U)
+#define DMA_NBYTES_MLOFFYES_NBYTES(x)            (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFYES_MLOFF_MASK           (0x3FFFFC00U)
+#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT          (10U)
+#define DMA_NBYTES_MLOFFYES_MLOFF(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
+#define DMA_NBYTES_MLOFFYES_DMLOE                (0x40000000U)
+#define DMA_NBYTES_MLOFFYES_SMLOE                (0x80000000U)
+
+/*! @name DOFF - TCD Signed Destination Address Offset */
+#define DMA_DOFF_DOFF_MASK                       (0xFFFFU)
+#define DMA_DOFF_DOFF_SHIFT                      (0U)
+#define DMA_DOFF_DOFF(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
+
+/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
+#define DMA_CITER_ELINKNO_CITER_MASK             (0x7FFFU)
+#define DMA_CITER_ELINKNO_CITER_SHIFT            (0U)
+#define DMA_CITER_ELINKNO_CITER(x)               (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
+#define DMA_CITER_ELINKNO_ELINK                  (0x8000U)
+
+/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
+#define DMA_CITER_ELINKYES_CITER_MASK            (0x1FFU)
+#define DMA_CITER_ELINKYES_CITER_SHIFT           (0U)
+#define DMA_CITER_ELINKYES_CITER(x)              (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
+#define DMA_CITER_ELINKYES_LINKCH_MASK           (0x1E00U)
+#define DMA_CITER_ELINKYES_LINKCH_SHIFT          (9U)
+#define DMA_CITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
+#define DMA_CITER_ELINKYES_ELINK                 (0x8000U)
+
+/*! @name CSR - TCD Control and Status */
+#define DMA_CSR_START                            (0x1U)
+#define DMA_CSR_INTMAJOR                         (0x2U)
+#define DMA_CSR_INTHALF                          (0x4U)
+#define DMA_CSR_DREQ                             (0x8U)
+#define DMA_CSR_ESG                              (0x10U)
+#define DMA_CSR_MAJORELINK                       (0x20U)
+#define DMA_CSR_ACTIVE                           (0x40U)
+#define DMA_CSR_DONE                             (0x80U)
+#define DMA_CSR_MAJORLINKCH_MASK                 (0xF00U)
+#define DMA_CSR_MAJORLINKCH_SHIFT                (8U)
+#define DMA_CSR_MAJORLINKCH(x)                   (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
+#define DMA_CSR_BWC_MASK                         (0xC000U)
+#define DMA_CSR_BWC_SHIFT                        (14U)
+#define DMA_CSR_BWC(x)                           (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
+
+/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
+#define DMA_BITER_ELINKNO_BITER_MASK             (0x7FFFU)
+#define DMA_BITER_ELINKNO_BITER_SHIFT            (0U)
+#define DMA_BITER_ELINKNO_BITER(x)               (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
+#define DMA_BITER_ELINKNO_ELINK                  (0x8000U)
+
+/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
+#define DMA_BITER_ELINKYES_BITER_MASK            (0x1FFU)
+#define DMA_BITER_ELINKYES_BITER_SHIFT           (0U)
+#define DMA_BITER_ELINKYES_BITER(x)              (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
+#define DMA_BITER_ELINKYES_LINKCH_MASK           (0x1E00U)
+#define DMA_BITER_ELINKYES_LINKCH_SHIFT          (9U)
+#define DMA_BITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
+#define DMA_BITER_ELINKYES_ELINK                 (0x8000U)
+
+/* The count of DMA_TCD */
+#define DMA_TCD_COUNT                            (16U)
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA base address */
+#define DMA_BASE                                 (0x40008000u)
+/** Peripheral DMA base pointer */
+#define DMA0                                     ((DMA_TypeDef *)DMA_BASE)
+/** Array initializer of DMA peripheral base addresses */
+#define DMA_BASE_ADDRS                           { DMA_BASE }
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASE_PTRS                            { DMA0 }
+/** Interrupt vectors for the DMA peripheral type */
+#define DMA_CHN_IRQS                             { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn }
+#define DMA_ERROR_IRQS                           { DMA_Error_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CHCFG[16];                          /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
+} DMAMUX_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/*! @name CHCFG - Channel Configuration register */
+#define DMAMUX_CHCFG_SOURCE_MASK                 (0x3FU)
+#define DMAMUX_CHCFG_SOURCE_SHIFT                (0U)
+#define DMAMUX_CHCFG_SOURCE(x)                   (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG                        (0x40U)
+#define DMAMUX_CHCFG_ENBL                        (0x80U)
+
+/* The count of DMAMUX_CHCFG */
+#define DMAMUX_CHCFG_COUNT                       (16U)
+
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX base address */
+#define DMAMUX_BASE                              (0x40021000u)
+/** Peripheral DMAMUX base pointer */
+#define DMAMUX                                   ((DMAMUX_TypeDef *)DMAMUX_BASE)
+/** Array initializer of DMAMUX peripheral base addresses */
+#define DMAMUX_BASE_ADDRS                        { DMAMUX_BASE }
+/** Array initializer of DMAMUX peripheral base pointers */
+#define DMAMUX_BASE_PTRS                         { DMAMUX }
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ENET Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
+ * @{
+ */
+
+/** ENET - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[4];
+  __IO uint32_t EIR;                               /**< Interrupt Event Register, offset: 0x4 */
+  __IO uint32_t EIMR;                              /**< Interrupt Mask Register, offset: 0x8 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t RDAR;                              /**< Receive Descriptor Active Register, offset: 0x10 */
+  __IO uint32_t TDAR;                              /**< Transmit Descriptor Active Register, offset: 0x14 */
+       uint8_t RESERVED_2[12];
+  __IO uint32_t ECR;                               /**< Ethernet Control Register, offset: 0x24 */
+       uint8_t RESERVED_3[24];
+  __IO uint32_t MMFR;                              /**< MII Management Frame Register, offset: 0x40 */
+  __IO uint32_t MSCR;                              /**< MII Speed Control Register, offset: 0x44 */
+       uint8_t RESERVED_4[28];
+  __IO uint32_t MIBC;                              /**< MIB Control Register, offset: 0x64 */
+       uint8_t RESERVED_5[28];
+  __IO uint32_t RCR;                               /**< Receive Control Register, offset: 0x84 */
+       uint8_t RESERVED_6[60];
+  __IO uint32_t TCR;                               /**< Transmit Control Register, offset: 0xC4 */
+       uint8_t RESERVED_7[28];
+  __IO uint32_t PALR;                              /**< Physical Address Lower Register, offset: 0xE4 */
+  __IO uint32_t PAUR;                              /**< Physical Address Upper Register, offset: 0xE8 */
+  __IO uint32_t OPD;                               /**< Opcode/Pause Duration Register, offset: 0xEC */
+       uint8_t RESERVED_8[40];
+  __IO uint32_t IAUR;                              /**< Descriptor Individual Upper Address Register, offset: 0x118 */
+  __IO uint32_t IALR;                              /**< Descriptor Individual Lower Address Register, offset: 0x11C */
+  __IO uint32_t GAUR;                              /**< Descriptor Group Upper Address Register, offset: 0x120 */
+  __IO uint32_t GALR;                              /**< Descriptor Group Lower Address Register, offset: 0x124 */
+       uint8_t RESERVED_9[28];
+  __IO uint32_t TFWR;                              /**< Transmit FIFO Watermark Register, offset: 0x144 */
+       uint8_t RESERVED_10[56];
+  __IO uint32_t RDSR;                              /**< Receive Descriptor Ring Start Register, offset: 0x180 */
+  __IO uint32_t TDSR;                              /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */
+  __IO uint32_t MRBR;                              /**< Maximum Receive Buffer Size Register, offset: 0x188 */
+       uint8_t RESERVED_11[4];
+  __IO uint32_t RSFL;                              /**< Receive FIFO Section Full Threshold, offset: 0x190 */
+  __IO uint32_t RSEM;                              /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
+  __IO uint32_t RAEM;                              /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
+  __IO uint32_t RAFL;                              /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
+  __IO uint32_t TSEM;                              /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
+  __IO uint32_t TAEM;                              /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
+  __IO uint32_t TAFL;                              /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
+  __IO uint32_t TIPG;                              /**< Transmit Inter-Packet Gap, offset: 0x1AC */
+  __IO uint32_t FTRL;                              /**< Frame Truncation Length, offset: 0x1B0 */
+       uint8_t RESERVED_12[12];
+  __IO uint32_t TACC;                              /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
+  __IO uint32_t RACC;                              /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
+       uint8_t RESERVED_13[60];
+  __I  uint32_t RMON_T_PACKETS;                    /**< Tx Packet Count Statistic Register, offset: 0x204 */
+  __I  uint32_t RMON_T_BC_PKT;                     /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
+  __I  uint32_t RMON_T_MC_PKT;                     /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
+  __I  uint32_t RMON_T_CRC_ALIGN;                  /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
+  __I  uint32_t RMON_T_UNDERSIZE;                  /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
+  __I  uint32_t RMON_T_OVERSIZE;                   /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
+  __I  uint32_t RMON_T_FRAG;                       /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
+  __I  uint32_t RMON_T_JAB;                        /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
+  __I  uint32_t RMON_T_COL;                        /**< Tx Collision Count Statistic Register, offset: 0x224 */
+  __I  uint32_t RMON_T_P64;                        /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
+  __I  uint32_t RMON_T_P65TO127;                   /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
+  __I  uint32_t RMON_T_P128TO255;                  /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
+  __I  uint32_t RMON_T_P256TO511;                  /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
+  __I  uint32_t RMON_T_P512TO1023;                 /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
+  __I  uint32_t RMON_T_P1024TO2047;                /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
+  __I  uint32_t RMON_T_P_GTE2048;                  /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
+  __I  uint32_t RMON_T_OCTETS;                     /**< Tx Octets Statistic Register, offset: 0x244 */
+       uint8_t RESERVED_14[4];
+  __I  uint32_t IEEE_T_FRAME_OK;                   /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
+  __I  uint32_t IEEE_T_1COL;                       /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
+  __I  uint32_t IEEE_T_MCOL;                       /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
+  __I  uint32_t IEEE_T_DEF;                        /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
+  __I  uint32_t IEEE_T_LCOL;                       /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
+  __I  uint32_t IEEE_T_EXCOL;                      /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
+  __I  uint32_t IEEE_T_MACERR;                     /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
+  __I  uint32_t IEEE_T_CSERR;                      /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
+       uint8_t RESERVED_15[4];
+  __I  uint32_t IEEE_T_FDXFC;                      /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
+  __I  uint32_t IEEE_T_OCTETS_OK;                  /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
+       uint8_t RESERVED_16[12];
+  __I  uint32_t RMON_R_PACKETS;                    /**< Rx Packet Count Statistic Register, offset: 0x284 */
+  __I  uint32_t RMON_R_BC_PKT;                     /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
+  __I  uint32_t RMON_R_MC_PKT;                     /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
+  __I  uint32_t RMON_R_CRC_ALIGN;                  /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
+  __I  uint32_t RMON_R_UNDERSIZE;                  /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
+  __I  uint32_t RMON_R_OVERSIZE;                   /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
+  __I  uint32_t RMON_R_FRAG;                       /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
+  __I  uint32_t RMON_R_JAB;                        /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
+       uint8_t RESERVED_17[4];
+  __I  uint32_t RMON_R_P64;                        /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
+  __I  uint32_t RMON_R_P65TO127;                   /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
+  __I  uint32_t RMON_R_P128TO255;                  /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
+  __I  uint32_t RMON_R_P256TO511;                  /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
+  __I  uint32_t RMON_R_P512TO1023;                 /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
+  __I  uint32_t RMON_R_P1024TO2047;                /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
+  __I  uint32_t RMON_R_P_GTE2048;                  /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
+  __I  uint32_t RMON_R_OCTETS;                     /**< Rx Octets Statistic Register, offset: 0x2C4 */
+  __I  uint32_t IEEE_R_DROP;                       /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
+  __I  uint32_t IEEE_R_FRAME_OK;                   /**< Frames Received OK Statistic Register, offset: 0x2CC */
+  __I  uint32_t IEEE_R_CRC;                        /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
+  __I  uint32_t IEEE_R_ALIGN;                      /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
+  __I  uint32_t IEEE_R_MACERR;                     /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
+  __I  uint32_t IEEE_R_FDXFC;                      /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
+  __I  uint32_t IEEE_R_OCTETS_OK;                  /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
+       uint8_t RESERVED_18[284];
+  __IO uint32_t ATCR;                              /**< Adjustable Timer Control Register, offset: 0x400 */
+  __IO uint32_t ATVR;                              /**< Timer Value Register, offset: 0x404 */
+  __IO uint32_t ATOFF;                             /**< Timer Offset Register, offset: 0x408 */
+  __IO uint32_t ATPER;                             /**< Timer Period Register, offset: 0x40C */
+  __IO uint32_t ATCOR;                             /**< Timer Correction Register, offset: 0x410 */
+  __IO uint32_t ATINC;                             /**< Time-Stamping Clock Period Register, offset: 0x414 */
+  __I  uint32_t ATSTMP;                            /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
+       uint8_t RESERVED_19[488];
+  __IO uint32_t TGSR;                              /**< Timer Global Status Register, offset: 0x604 */
+  struct {                                         /* offset: 0x608, array step: 0x8 */
+    __IO uint32_t TCSR;                              /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
+    __IO uint32_t TCCR;                              /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
+  } CHANNEL[4];
+} ENET_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- ENET Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Masks ENET Register Masks
+ * @{
+ */
+
+/*! @name EIR - Interrupt Event Register */
+#define ENET_EIR_TS_TIMER                        (0x8000U)
+#define ENET_EIR_TS_AVAIL                        (0x10000U)
+#define ENET_EIR_WAKEUP                          (0x20000U)
+#define ENET_EIR_PLR                             (0x40000U)
+#define ENET_EIR_UN                              (0x80000U)
+#define ENET_EIR_RL                              (0x100000U)
+#define ENET_EIR_LC                              (0x200000U)
+#define ENET_EIR_EBERR                           (0x400000U)
+#define ENET_EIR_MII                             (0x800000U)
+#define ENET_EIR_RXB                             (0x1000000U)
+#define ENET_EIR_RXF                             (0x2000000U)
+#define ENET_EIR_TXB                             (0x4000000U)
+#define ENET_EIR_TXF                             (0x8000000U)
+#define ENET_EIR_GRA                             (0x10000000U)
+#define ENET_EIR_BABT                            (0x20000000U)
+#define ENET_EIR_BABR                            (0x40000000U)
+
+/*! @name EIMR - Interrupt Mask Register */
+#define ENET_EIMR_TS_TIMER                       (0x8000U)
+#define ENET_EIMR_TS_AVAIL                       (0x10000U)
+#define ENET_EIMR_WAKEUP                         (0x20000U)
+#define ENET_EIMR_PLR                            (0x40000U)
+#define ENET_EIMR_UN                             (0x80000U)
+#define ENET_EIMR_RL                             (0x100000U)
+#define ENET_EIMR_LC                             (0x200000U)
+#define ENET_EIMR_EBERR                          (0x400000U)
+#define ENET_EIMR_MII                            (0x800000U)
+#define ENET_EIMR_RXB                            (0x1000000U)
+#define ENET_EIMR_RXF                            (0x2000000U)
+#define ENET_EIMR_TXB                            (0x4000000U)
+#define ENET_EIMR_TXF                            (0x8000000U)
+#define ENET_EIMR_GRA                            (0x10000000U)
+#define ENET_EIMR_BABT                           (0x20000000U)
+#define ENET_EIMR_BABR                           (0x40000000U)
+
+/*! @name RDAR - Receive Descriptor Active Register */
+#define ENET_RDAR_RDAR                           (0x1000000U)
+
+/*! @name TDAR - Transmit Descriptor Active Register */
+#define ENET_TDAR_TDAR                           (0x1000000U)
+
+/*! @name ECR - Ethernet Control Register */
+#define ENET_ECR_RESET                           (0x1U)
+#define ENET_ECR_ETHEREN                         (0x2U)
+#define ENET_ECR_MAGICEN                         (0x4U)
+#define ENET_ECR_SLEEP                           (0x8U)
+#define ENET_ECR_EN1588                          (0x10U)
+#define ENET_ECR_DBGEN                           (0x40U)
+#define ENET_ECR_STOPEN                          (0x80U)
+#define ENET_ECR_DBSWP                           (0x100U)
+
+/*! @name MMFR - MII Management Frame Register */
+#define ENET_MMFR_DATA_MASK                      (0xFFFFU)
+#define ENET_MMFR_DATA_SHIFT                     (0U)
+#define ENET_MMFR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
+#define ENET_MMFR_TA_MASK                        (0x30000U)
+#define ENET_MMFR_TA_SHIFT                       (16U)
+#define ENET_MMFR_TA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
+#define ENET_MMFR_RA_MASK                        (0x7C0000U)
+#define ENET_MMFR_RA_SHIFT                       (18U)
+#define ENET_MMFR_RA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
+#define ENET_MMFR_PA_MASK                        (0xF800000U)
+#define ENET_MMFR_PA_SHIFT                       (23U)
+#define ENET_MMFR_PA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
+#define ENET_MMFR_OP_MASK                        (0x30000000U)
+#define ENET_MMFR_OP_SHIFT                       (28U)
+#define ENET_MMFR_OP(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
+#define ENET_MMFR_ST_MASK                        (0xC0000000U)
+#define ENET_MMFR_ST_SHIFT                       (30U)
+#define ENET_MMFR_ST(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
+
+/*! @name MSCR - MII Speed Control Register */
+#define ENET_MSCR_MII_SPEED_MASK                 (0x7EU)
+#define ENET_MSCR_MII_SPEED_SHIFT                (1U)
+#define ENET_MSCR_MII_SPEED(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
+#define ENET_MSCR_DIS_PRE                        (0x80U)
+#define ENET_MSCR_HOLDTIME_MASK                  (0x700U)
+#define ENET_MSCR_HOLDTIME_SHIFT                 (8U)
+#define ENET_MSCR_HOLDTIME(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
+
+/*! @name MIBC - MIB Control Register */
+#define ENET_MIBC_MIB_CLEAR                      (0x20000000U)
+#define ENET_MIBC_MIB_IDLE                       (0x40000000U)
+#define ENET_MIBC_MIB_DIS                        (0x80000000U)
+
+/*! @name RCR - Receive Control Register */
+#define ENET_RCR_LOOP                            (0x1U)
+#define ENET_RCR_DRT                             (0x2U)
+#define ENET_RCR_MII_MODE                        (0x4U)
+#define ENET_RCR_PROM                            (0x8U)
+#define ENET_RCR_BC_REJ                          (0x10U)
+#define ENET_RCR_FCE                             (0x20U)
+#define ENET_RCR_RMII_MODE                       (0x100U)
+#define ENET_RCR_RMII_10T                        (0x200U)
+#define ENET_RCR_PADEN                           (0x1000U)
+#define ENET_RCR_PAUFWD                          (0x2000U)
+#define ENET_RCR_CRCFWD                          (0x4000U)
+#define ENET_RCR_CFEN                            (0x8000U)
+#define ENET_RCR_MAX_FL_MASK                     (0x3FFF0000U)
+#define ENET_RCR_MAX_FL_SHIFT                    (16U)
+#define ENET_RCR_MAX_FL(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
+#define ENET_RCR_NLC                             (0x40000000U)
+#define ENET_RCR_GRS                             (0x80000000U)
+
+/*! @name TCR - Transmit Control Register */
+#define ENET_TCR_GTS                             (0x1U)
+#define ENET_TCR_FDEN                            (0x4U)
+#define ENET_TCR_TFC_PAUSE                       (0x8U)
+#define ENET_TCR_RFC_PAUSE                       (0x10U)
+#define ENET_TCR_ADDSEL_MASK                     (0xE0U)
+#define ENET_TCR_ADDSEL_SHIFT                    (5U)
+#define ENET_TCR_ADDSEL(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
+#define ENET_TCR_ADDINS                          (0x100U)
+#define ENET_TCR_CRCFWD                          (0x200U)
+
+/*! @name PAUR - Physical Address Upper Register */
+#define ENET_PAUR_TYPE_MASK                      (0xFFFFU)
+#define ENET_PAUR_TYPE_SHIFT                     (0U)
+#define ENET_PAUR_TYPE(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
+#define ENET_PAUR_PADDR2_MASK                    (0xFFFF0000U)
+#define ENET_PAUR_PADDR2_SHIFT                   (16U)
+#define ENET_PAUR_PADDR2(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
+
+/*! @name OPD - Opcode/Pause Duration Register */
+#define ENET_OPD_PAUSE_DUR_MASK                  (0xFFFFU)
+#define ENET_OPD_PAUSE_DUR_SHIFT                 (0U)
+#define ENET_OPD_PAUSE_DUR(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
+#define ENET_OPD_OPCODE_MASK                     (0xFFFF0000U)
+#define ENET_OPD_OPCODE_SHIFT                    (16U)
+#define ENET_OPD_OPCODE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
+
+/*! @name TFWR - Transmit FIFO Watermark Register */
+#define ENET_TFWR_TFWR_MASK                      (0x3FU)
+#define ENET_TFWR_TFWR_SHIFT                     (0U)
+#define ENET_TFWR_TFWR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
+#define ENET_TFWR_STRFWD                         (0x100U)
+
+/*! @name RDSR - Receive Descriptor Ring Start Register */
+#define ENET_RDSR_R_DES_START_MASK               (0xFFFFFFF8U)
+#define ENET_RDSR_R_DES_START_SHIFT              (3U)
+#define ENET_RDSR_R_DES_START(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
+
+/*! @name TDSR - Transmit Buffer Descriptor Ring Start Register */
+#define ENET_TDSR_X_DES_START_MASK               (0xFFFFFFF8U)
+#define ENET_TDSR_X_DES_START_SHIFT              (3U)
+#define ENET_TDSR_X_DES_START(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
+
+/*! @name MRBR - Maximum Receive Buffer Size Register */
+#define ENET_MRBR_R_BUF_SIZE_MASK                (0x3FF0U)
+#define ENET_MRBR_R_BUF_SIZE_SHIFT               (4U)
+#define ENET_MRBR_R_BUF_SIZE(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)
+
+/*! @name RSFL - Receive FIFO Section Full Threshold */
+#define ENET_RSFL_RX_SECTION_FULL_MASK           (0xFFU)
+#define ENET_RSFL_RX_SECTION_FULL_SHIFT          (0U)
+#define ENET_RSFL_RX_SECTION_FULL(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)
+
+/*! @name RSEM - Receive FIFO Section Empty Threshold */
+#define ENET_RSEM_RX_SECTION_EMPTY_MASK          (0xFFU)
+#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT         (0U)
+#define ENET_RSEM_RX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
+#define ENET_RSEM_STAT_SECTION_EMPTY_MASK        (0x1F0000U)
+#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT       (16U)
+#define ENET_RSEM_STAT_SECTION_EMPTY(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
+
+/*! @name RAEM - Receive FIFO Almost Empty Threshold */
+#define ENET_RAEM_RX_ALMOST_EMPTY_MASK           (0xFFU)
+#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT          (0U)
+#define ENET_RAEM_RX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)
+
+/*! @name RAFL - Receive FIFO Almost Full Threshold */
+#define ENET_RAFL_RX_ALMOST_FULL_MASK            (0xFFU)
+#define ENET_RAFL_RX_ALMOST_FULL_SHIFT           (0U)
+#define ENET_RAFL_RX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)
+
+/*! @name TSEM - Transmit FIFO Section Empty Threshold */
+#define ENET_TSEM_TX_SECTION_EMPTY_MASK          (0xFFU)
+#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT         (0U)
+#define ENET_TSEM_TX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)
+
+/*! @name TAEM - Transmit FIFO Almost Empty Threshold */
+#define ENET_TAEM_TX_ALMOST_EMPTY_MASK           (0xFFU)
+#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT          (0U)
+#define ENET_TAEM_TX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)
+
+/*! @name TAFL - Transmit FIFO Almost Full Threshold */
+#define ENET_TAFL_TX_ALMOST_FULL_MASK            (0xFFU)
+#define ENET_TAFL_TX_ALMOST_FULL_SHIFT           (0U)
+#define ENET_TAFL_TX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)
+
+/*! @name TIPG - Transmit Inter-Packet Gap */
+#define ENET_TIPG_IPG_MASK                       (0x1FU)
+#define ENET_TIPG_IPG_SHIFT                      (0U)
+#define ENET_TIPG_IPG(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
+
+/*! @name FTRL - Frame Truncation Length */
+#define ENET_FTRL_TRUNC_FL_MASK                  (0x3FFFU)
+#define ENET_FTRL_TRUNC_FL_SHIFT                 (0U)
+#define ENET_FTRL_TRUNC_FL(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
+
+/*! @name TACC - Transmit Accelerator Function Configuration */
+#define ENET_TACC_SHIFT16                        (0x1U)
+#define ENET_TACC_IPCHK                          (0x8U)
+#define ENET_TACC_PROCHK                         (0x10U)
+
+/*! @name RACC - Receive Accelerator Function Configuration */
+#define ENET_RACC_PADREM                         (0x1U)
+#define ENET_RACC_IPDIS                          (0x2U)
+#define ENET_RACC_PRODIS                         (0x4U)
+#define ENET_RACC_LINEDIS                        (0x40U)
+#define ENET_RACC_SHIFT16                        (0x80U)
+
+/*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */
+#define ENET_RMON_T_PACKETS_TXPKTS_MASK          (0xFFFFU)
+#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT         (0U)
+#define ENET_RMON_T_PACKETS_TXPKTS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
+
+/*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */
+#define ENET_RMON_T_BC_PKT_TXPKTS_MASK           (0xFFFFU)
+#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT          (0U)
+#define ENET_RMON_T_BC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
+
+/*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */
+#define ENET_RMON_T_MC_PKT_TXPKTS_MASK           (0xFFFFU)
+#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT          (0U)
+#define ENET_RMON_T_MC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
+
+/*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK        (0xFFFFU)
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT       (0U)
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
+
+/*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */
+#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK        (0xFFFFU)
+#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT       (0U)
+#define ENET_RMON_T_UNDERSIZE_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
+
+/*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */
+#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK         (0xFFFFU)
+#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT        (0U)
+#define ENET_RMON_T_OVERSIZE_TXPKTS(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
+
+/*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
+#define ENET_RMON_T_FRAG_TXPKTS_MASK             (0xFFFFU)
+#define ENET_RMON_T_FRAG_TXPKTS_SHIFT            (0U)
+#define ENET_RMON_T_FRAG_TXPKTS(x)               (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
+
+/*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */
+#define ENET_RMON_T_JAB_TXPKTS_MASK              (0xFFFFU)
+#define ENET_RMON_T_JAB_TXPKTS_SHIFT             (0U)
+#define ENET_RMON_T_JAB_TXPKTS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
+
+/*! @name RMON_T_COL - Tx Collision Count Statistic Register */
+#define ENET_RMON_T_COL_TXPKTS_MASK              (0xFFFFU)
+#define ENET_RMON_T_COL_TXPKTS_SHIFT             (0U)
+#define ENET_RMON_T_COL_TXPKTS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
+
+/*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */
+#define ENET_RMON_T_P64_TXPKTS_MASK              (0xFFFFU)
+#define ENET_RMON_T_P64_TXPKTS_SHIFT             (0U)
+#define ENET_RMON_T_P64_TXPKTS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
+
+/*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */
+#define ENET_RMON_T_P65TO127_TXPKTS_MASK         (0xFFFFU)
+#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT        (0U)
+#define ENET_RMON_T_P65TO127_TXPKTS(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
+
+/*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */
+#define ENET_RMON_T_P128TO255_TXPKTS_MASK        (0xFFFFU)
+#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT       (0U)
+#define ENET_RMON_T_P128TO255_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
+
+/*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */
+#define ENET_RMON_T_P256TO511_TXPKTS_MASK        (0xFFFFU)
+#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT       (0U)
+#define ENET_RMON_T_P256TO511_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
+
+/*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */
+#define ENET_RMON_T_P512TO1023_TXPKTS_MASK       (0xFFFFU)
+#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT      (0U)
+#define ENET_RMON_T_P512TO1023_TXPKTS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
+
+/*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */
+#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK      (0xFFFFU)
+#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT     (0U)
+#define ENET_RMON_T_P1024TO2047_TXPKTS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
+
+/*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */
+#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK        (0xFFFFU)
+#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT       (0U)
+#define ENET_RMON_T_P_GTE2048_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
+
+/*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */
+#define ENET_IEEE_T_FRAME_OK_COUNT_MASK          (0xFFFFU)
+#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT         (0U)
+#define ENET_IEEE_T_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
+
+/*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */
+#define ENET_IEEE_T_1COL_COUNT_MASK              (0xFFFFU)
+#define ENET_IEEE_T_1COL_COUNT_SHIFT             (0U)
+#define ENET_IEEE_T_1COL_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
+
+/*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */
+#define ENET_IEEE_T_MCOL_COUNT_MASK              (0xFFFFU)
+#define ENET_IEEE_T_MCOL_COUNT_SHIFT             (0U)
+#define ENET_IEEE_T_MCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
+
+/*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */
+#define ENET_IEEE_T_DEF_COUNT_MASK               (0xFFFFU)
+#define ENET_IEEE_T_DEF_COUNT_SHIFT              (0U)
+#define ENET_IEEE_T_DEF_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
+
+/*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */
+#define ENET_IEEE_T_LCOL_COUNT_MASK              (0xFFFFU)
+#define ENET_IEEE_T_LCOL_COUNT_SHIFT             (0U)
+#define ENET_IEEE_T_LCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
+
+/*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */
+#define ENET_IEEE_T_EXCOL_COUNT_MASK             (0xFFFFU)
+#define ENET_IEEE_T_EXCOL_COUNT_SHIFT            (0U)
+#define ENET_IEEE_T_EXCOL_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
+
+/*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */
+#define ENET_IEEE_T_MACERR_COUNT_MASK            (0xFFFFU)
+#define ENET_IEEE_T_MACERR_COUNT_SHIFT           (0U)
+#define ENET_IEEE_T_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
+
+/*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */
+#define ENET_IEEE_T_CSERR_COUNT_MASK             (0xFFFFU)
+#define ENET_IEEE_T_CSERR_COUNT_SHIFT            (0U)
+#define ENET_IEEE_T_CSERR_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
+
+/*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */
+#define ENET_IEEE_T_FDXFC_COUNT_MASK             (0xFFFFU)
+#define ENET_IEEE_T_FDXFC_COUNT_SHIFT            (0U)
+#define ENET_IEEE_T_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
+
+/*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */
+#define ENET_RMON_R_PACKETS_COUNT_MASK           (0xFFFFU)
+#define ENET_RMON_R_PACKETS_COUNT_SHIFT          (0U)
+#define ENET_RMON_R_PACKETS_COUNT(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
+
+/*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */
+#define ENET_RMON_R_BC_PKT_COUNT_MASK            (0xFFFFU)
+#define ENET_RMON_R_BC_PKT_COUNT_SHIFT           (0U)
+#define ENET_RMON_R_BC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
+
+/*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */
+#define ENET_RMON_R_MC_PKT_COUNT_MASK            (0xFFFFU)
+#define ENET_RMON_R_MC_PKT_COUNT_SHIFT           (0U)
+#define ENET_RMON_R_MC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
+
+/*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */
+#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK         (0xFFFFU)
+#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT        (0U)
+#define ENET_RMON_R_CRC_ALIGN_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
+
+/*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */
+#define ENET_RMON_R_UNDERSIZE_COUNT_MASK         (0xFFFFU)
+#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT        (0U)
+#define ENET_RMON_R_UNDERSIZE_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
+
+/*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */
+#define ENET_RMON_R_OVERSIZE_COUNT_MASK          (0xFFFFU)
+#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT         (0U)
+#define ENET_RMON_R_OVERSIZE_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
+
+/*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
+#define ENET_RMON_R_FRAG_COUNT_MASK              (0xFFFFU)
+#define ENET_RMON_R_FRAG_COUNT_SHIFT             (0U)
+#define ENET_RMON_R_FRAG_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
+
+/*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */
+#define ENET_RMON_R_JAB_COUNT_MASK               (0xFFFFU)
+#define ENET_RMON_R_JAB_COUNT_SHIFT              (0U)
+#define ENET_RMON_R_JAB_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
+
+/*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */
+#define ENET_RMON_R_P64_COUNT_MASK               (0xFFFFU)
+#define ENET_RMON_R_P64_COUNT_SHIFT              (0U)
+#define ENET_RMON_R_P64_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
+
+/*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */
+#define ENET_RMON_R_P65TO127_COUNT_MASK          (0xFFFFU)
+#define ENET_RMON_R_P65TO127_COUNT_SHIFT         (0U)
+#define ENET_RMON_R_P65TO127_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
+
+/*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */
+#define ENET_RMON_R_P128TO255_COUNT_MASK         (0xFFFFU)
+#define ENET_RMON_R_P128TO255_COUNT_SHIFT        (0U)
+#define ENET_RMON_R_P128TO255_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
+
+/*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */
+#define ENET_RMON_R_P256TO511_COUNT_MASK         (0xFFFFU)
+#define ENET_RMON_R_P256TO511_COUNT_SHIFT        (0U)
+#define ENET_RMON_R_P256TO511_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
+
+/*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */
+#define ENET_RMON_R_P512TO1023_COUNT_MASK        (0xFFFFU)
+#define ENET_RMON_R_P512TO1023_COUNT_SHIFT       (0U)
+#define ENET_RMON_R_P512TO1023_COUNT(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
+
+/*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */
+#define ENET_RMON_R_P1024TO2047_COUNT_MASK       (0xFFFFU)
+#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT      (0U)
+#define ENET_RMON_R_P1024TO2047_COUNT(x)         (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
+
+/*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */
+#define ENET_RMON_R_P_GTE2048_COUNT_MASK         (0xFFFFU)
+#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT        (0U)
+#define ENET_RMON_R_P_GTE2048_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
+
+/*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */
+#define ENET_IEEE_R_DROP_COUNT_MASK              (0xFFFFU)
+#define ENET_IEEE_R_DROP_COUNT_SHIFT             (0U)
+#define ENET_IEEE_R_DROP_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
+
+/*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */
+#define ENET_IEEE_R_FRAME_OK_COUNT_MASK          (0xFFFFU)
+#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT         (0U)
+#define ENET_IEEE_R_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
+
+/*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */
+#define ENET_IEEE_R_CRC_COUNT_MASK               (0xFFFFU)
+#define ENET_IEEE_R_CRC_COUNT_SHIFT              (0U)
+#define ENET_IEEE_R_CRC_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
+
+/*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */
+#define ENET_IEEE_R_ALIGN_COUNT_MASK             (0xFFFFU)
+#define ENET_IEEE_R_ALIGN_COUNT_SHIFT            (0U)
+#define ENET_IEEE_R_ALIGN_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
+
+/*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */
+#define ENET_IEEE_R_MACERR_COUNT_MASK            (0xFFFFU)
+#define ENET_IEEE_R_MACERR_COUNT_SHIFT           (0U)
+#define ENET_IEEE_R_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
+
+/*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */
+#define ENET_IEEE_R_FDXFC_COUNT_MASK             (0xFFFFU)
+#define ENET_IEEE_R_FDXFC_COUNT_SHIFT            (0U)
+#define ENET_IEEE_R_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
+
+/*! @name ATCR - Adjustable Timer Control Register */
+#define ENET_ATCR_EN                             (0x1U)
+#define ENET_ATCR_OFFEN                          (0x4U)
+#define ENET_ATCR_OFFRST                         (0x8U)
+#define ENET_ATCR_PEREN                          (0x10U)
+#define ENET_ATCR_PINPER                         (0x80U)
+#define ENET_ATCR_RESTART                        (0x200U)
+#define ENET_ATCR_CAPTURE                        (0x800U)
+#define ENET_ATCR_SLAVE                          (0x2000U)
+
+/*! @name ATCOR - Timer Correction Register */
+#define ENET_ATCOR_COR_MASK                      (0x7FFFFFFFU)
+#define ENET_ATCOR_COR_SHIFT                     (0U)
+#define ENET_ATCOR_COR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
+
+/*! @name ATINC - Time-Stamping Clock Period Register */
+#define ENET_ATINC_INC_MASK                      (0x7FU)
+#define ENET_ATINC_INC_SHIFT                     (0U)
+#define ENET_ATINC_INC(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
+#define ENET_ATINC_INC_CORR_MASK                 (0x7F00U)
+#define ENET_ATINC_INC_CORR_SHIFT                (8U)
+#define ENET_ATINC_INC_CORR(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
+
+/*! @name TGSR - Timer Global Status Register */
+#define ENET_TGSR_TF0                            (0x1U)
+#define ENET_TGSR_TF1                            (0x2U)
+#define ENET_TGSR_TF2                            (0x4U)
+#define ENET_TGSR_TF3                            (0x8U)
+
+/*! @name TCSR - Timer Control Status Register */
+#define ENET_TCSR_TDRE                           (0x1U)
+#define ENET_TCSR_TMODE_MASK                     (0x3CU)
+#define ENET_TCSR_TMODE_SHIFT                    (2U)
+#define ENET_TCSR_TMODE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
+#define ENET_TCSR_TIE                            (0x40U)
+#define ENET_TCSR_TF                             (0x80U)
+
+/* The count of ENET_TCSR */
+#define ENET_TCSR_COUNT                          (4U)
+
+/* The count of ENET_TCCR */
+#define ENET_TCCR_COUNT                          (4U)
+
+
+/*!
+ * @}
+ */ /* end of group ENET_Register_Masks */
+
+
+/* ENET - Peripheral instance base addresses */
+/** Peripheral ENET base address */
+#define ENET_BASE                                (0x400C0000u)
+/** Peripheral ENET base pointer */
+#define ENET                                     ((ENET_TypeDef *)ENET_BASE)
+/** Array initializer of ENET peripheral base addresses */
+#define ENET_BASE_ADDRS                          { ENET_BASE }
+/** Array initializer of ENET peripheral base pointers */
+#define ENET_BASE_PTRS                           { ENET }
+/** Interrupt vectors for the ENET peripheral type */
+#define ENET_Transmit_IRQS                       { ENET_Transmit_IRQn }
+#define ENET_Receive_IRQS                        { ENET_Receive_IRQn }
+#define ENET_Error_IRQS                          { ENET_Error_IRQn }
+#define ENET_1588_Timer_IRQS                     { ENET_1588_Timer_IRQn }
+
+/*!
+ * @}
+ */ /* end of group ENET_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- EWM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
+ * @{
+ */
+
+/** EWM - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CTRL;                               /**< Control Register, offset: 0x0 */
+  __O  uint8_t SERV;                               /**< Service Register, offset: 0x1 */
+  __IO uint8_t CMPL;                               /**< Compare Low Register, offset: 0x2 */
+  __IO uint8_t CMPH;                               /**< Compare High Register, offset: 0x3 */
+} EWM_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- EWM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Masks EWM Register Masks
+ * @{
+ */
+
+/*! @name CTRL - Control Register */
+#define EWM_CTRL_EWMEN                           (0x1U)
+#define EWM_CTRL_ASSIN                           (0x2U)
+#define EWM_CTRL_INEN                            (0x4U)
+#define EWM_CTRL_INTEN                           (0x8U)
+
+/*! @name SERV - Service Register */
+#define EWM_SERV_SERVICE_MASK                    (0xFFU)
+#define EWM_SERV_SERVICE_SHIFT                   (0U)
+#define EWM_SERV_SERVICE(x)                      (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
+
+/*! @name CMPL - Compare Low Register */
+#define EWM_CMPL_COMPAREL_MASK                   (0xFFU)
+#define EWM_CMPL_COMPAREL_SHIFT                  (0U)
+#define EWM_CMPL_COMPAREL(x)                     (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
+
+/*! @name CMPH - Compare High Register */
+#define EWM_CMPH_COMPAREH_MASK                   (0xFFU)
+#define EWM_CMPH_COMPAREH_SHIFT                  (0U)
+#define EWM_CMPH_COMPAREH(x)                     (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Masks */
+
+
+/* EWM - Peripheral instance base addresses */
+/** Peripheral EWM base address */
+#define EWM_BASE                                 (0x40061000u)
+/** Peripheral EWM base pointer */
+#define EWM                                      ((EWM_TypeDef *)EWM_BASE)
+/** Array initializer of EWM peripheral base addresses */
+#define EWM_BASE_ADDRS                           { EWM_BASE }
+/** Array initializer of EWM peripheral base pointers */
+#define EWM_BASE_PTRS                            { EWM }
+/** Interrupt vectors for the EWM peripheral type */
+#define EWM_IRQS                                 { WDOG_EWM_IRQn }
+
+/*!
+ * @}
+ */ /* end of group EWM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
+ * @{
+ */
+
+/** FB - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0xC */
+    __IO uint32_t CSAR;                              /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
+    __IO uint32_t CSMR;                              /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
+    __IO uint32_t CSCR;                              /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
+  } CS[6];
+       uint8_t RESERVED_0[24];
+  __IO uint32_t CSPMCR;                            /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
+} FB_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- FB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Masks FB Register Masks
+ * @{
+ */
+
+/*! @name CSAR - Chip Select Address Register */
+#define FB_CSAR_BA_MASK                          (0xFFFF0000U)
+#define FB_CSAR_BA_SHIFT                         (16U)
+#define FB_CSAR_BA(x)                            (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK)
+
+/* The count of FB_CSAR */
+#define FB_CSAR_COUNT                            (6U)
+
+/*! @name CSMR - Chip Select Mask Register */
+#define FB_CSMR_V                                (0x1U)
+#define FB_CSMR_WP                               (0x100U)
+#define FB_CSMR_BAM_MASK                         (0xFFFF0000U)
+#define FB_CSMR_BAM_SHIFT                        (16U)
+#define FB_CSMR_BAM(x)                           (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK)
+
+/* The count of FB_CSMR */
+#define FB_CSMR_COUNT                            (6U)
+
+/*! @name CSCR - Chip Select Control Register */
+#define FB_CSCR_BSTW                             (0x8U)
+#define FB_CSCR_BSTR                             (0x10U)
+#define FB_CSCR_BEM                              (0x20U)
+#define FB_CSCR_PS_MASK                          (0xC0U)
+#define FB_CSCR_PS_SHIFT                         (6U)
+#define FB_CSCR_PS(x)                            (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK)
+#define FB_CSCR_AA                               (0x100U)
+#define FB_CSCR_BLS                              (0x200U)
+#define FB_CSCR_WS_MASK                          (0xFC00U)
+#define FB_CSCR_WS_SHIFT                         (10U)
+#define FB_CSCR_WS(x)                            (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK)
+#define FB_CSCR_WRAH_MASK                        (0x30000U)
+#define FB_CSCR_WRAH_SHIFT                       (16U)
+#define FB_CSCR_WRAH(x)                          (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK)
+#define FB_CSCR_RDAH_MASK                        (0xC0000U)
+#define FB_CSCR_RDAH_SHIFT                       (18U)
+#define FB_CSCR_RDAH(x)                          (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK)
+#define FB_CSCR_ASET_MASK                        (0x300000U)
+#define FB_CSCR_ASET_SHIFT                       (20U)
+#define FB_CSCR_ASET(x)                          (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK)
+#define FB_CSCR_EXTS                             (0x400000U)
+#define FB_CSCR_SWSEN                            (0x800000U)
+#define FB_CSCR_SWS_MASK                         (0xFC000000U)
+#define FB_CSCR_SWS_SHIFT                        (26U)
+#define FB_CSCR_SWS(x)                           (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK)
+
+/* The count of FB_CSCR */
+#define FB_CSCR_COUNT                            (6U)
+
+/*! @name CSPMCR - Chip Select port Multiplexing Control Register */
+#define FB_CSPMCR_GROUP5_MASK                    (0xF000U)
+#define FB_CSPMCR_GROUP5_SHIFT                   (12U)
+#define FB_CSPMCR_GROUP5(x)                      (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK)
+#define FB_CSPMCR_GROUP4_MASK                    (0xF0000U)
+#define FB_CSPMCR_GROUP4_SHIFT                   (16U)
+#define FB_CSPMCR_GROUP4(x)                      (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK)
+#define FB_CSPMCR_GROUP3_MASK                    (0xF00000U)
+#define FB_CSPMCR_GROUP3_SHIFT                   (20U)
+#define FB_CSPMCR_GROUP3(x)                      (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK)
+#define FB_CSPMCR_GROUP2_MASK                    (0xF000000U)
+#define FB_CSPMCR_GROUP2_SHIFT                   (24U)
+#define FB_CSPMCR_GROUP2(x)                      (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK)
+#define FB_CSPMCR_GROUP1_MASK                    (0xF0000000U)
+#define FB_CSPMCR_GROUP1_SHIFT                   (28U)
+#define FB_CSPMCR_GROUP1(x)                      (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Masks */
+
+
+/* FB - Peripheral instance base addresses */
+/** Peripheral FB base address */
+#define FB_BASE                                  (0x4000C000u)
+/** Peripheral FB base pointer */
+#define FB                                       ((FB_TypeDef *)FB_BASE)
+/** Array initializer of FB peripheral base addresses */
+#define FB_BASE_ADDRS                            { FB_BASE }
+/** Array initializer of FB peripheral base pointers */
+#define FB_BASE_PTRS                             { FB }
+
+/*!
+ * @}
+ */ /* end of group FB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
+ * @{
+ */
+
+/** FMC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PFAPR;                             /**< Flash Access Protection Register, offset: 0x0 */
+  __IO uint32_t PFB0CR;                            /**< Flash Bank 0 Control Register, offset: 0x4 */
+  __IO uint32_t PFB1CR;                            /**< Flash Bank 1 Control Register, offset: 0x8 */
+       uint8_t RESERVED_0[244];
+  __IO uint32_t TAGVDW0S[4];                       /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
+  __IO uint32_t TAGVDW1S[4];                       /**< Cache Tag Storage, array offset: 0x110, array step: 0x4 */
+  __IO uint32_t TAGVDW2S[4];                       /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
+  __IO uint32_t TAGVDW3S[4];                       /**< Cache Tag Storage, array offset: 0x130, array step: 0x4 */
+       uint8_t RESERVED_1[192];
+  struct {                                         /* offset: 0x200, array step: index*0x20, index2*0x8 */
+    __IO uint32_t DATA_U;                            /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x20, index2*0x8 */
+    __IO uint32_t DATA_L;                            /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x20, index2*0x8 */
+  } SET[4][4];
+} FMC_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- FMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Masks FMC Register Masks
+ * @{
+ */
+
+/*! @name PFAPR - Flash Access Protection Register */
+#define FMC_PFAPR_M0AP_MASK                      (0x3U)
+#define FMC_PFAPR_M0AP_SHIFT                     (0U)
+#define FMC_PFAPR_M0AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)
+#define FMC_PFAPR_M1AP_MASK                      (0xCU)
+#define FMC_PFAPR_M1AP_SHIFT                     (2U)
+#define FMC_PFAPR_M1AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)
+#define FMC_PFAPR_M2AP_MASK                      (0x30U)
+#define FMC_PFAPR_M2AP_SHIFT                     (4U)
+#define FMC_PFAPR_M2AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)
+#define FMC_PFAPR_M3AP_MASK                      (0xC0U)
+#define FMC_PFAPR_M3AP_SHIFT                     (6U)
+#define FMC_PFAPR_M3AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)
+#define FMC_PFAPR_M4AP_MASK                      (0x300U)
+#define FMC_PFAPR_M4AP_SHIFT                     (8U)
+#define FMC_PFAPR_M4AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK)
+#define FMC_PFAPR_M5AP_MASK                      (0xC00U)
+#define FMC_PFAPR_M5AP_SHIFT                     (10U)
+#define FMC_PFAPR_M5AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK)
+#define FMC_PFAPR_M6AP_MASK                      (0x3000U)
+#define FMC_PFAPR_M6AP_SHIFT                     (12U)
+#define FMC_PFAPR_M6AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK)
+#define FMC_PFAPR_M7AP_MASK                      (0xC000U)
+#define FMC_PFAPR_M7AP_SHIFT                     (14U)
+#define FMC_PFAPR_M7AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK)
+#define FMC_PFAPR_M0PFD                          (0x10000U)
+#define FMC_PFAPR_M1PFD                          (0x20000U)
+#define FMC_PFAPR_M2PFD                          (0x40000U)
+#define FMC_PFAPR_M3PFD                          (0x80000U)
+#define FMC_PFAPR_M4PFD                          (0x100000U)
+#define FMC_PFAPR_M5PFD                          (0x200000U)
+#define FMC_PFAPR_M6PFD                          (0x400000U)
+#define FMC_PFAPR_M7PFD                          (0x800000U)
+
+/*! @name PFB0CR - Flash Bank 0 Control Register */
+#define FMC_PFB0CR_B0SEBE                        (0x1U)
+#define FMC_PFB0CR_B0IPE                         (0x2U)
+#define FMC_PFB0CR_B0DPE                         (0x4U)
+#define FMC_PFB0CR_B0ICE                         (0x8U)
+#define FMC_PFB0CR_B0DCE                         (0x10U)
+#define FMC_PFB0CR_CRC_MASK                      (0xE0U)
+#define FMC_PFB0CR_CRC_SHIFT                     (5U)
+#define FMC_PFB0CR_CRC(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CRC_SHIFT)) & FMC_PFB0CR_CRC_MASK)
+#define FMC_PFB0CR_B0MW_MASK                     (0x60000U)
+#define FMC_PFB0CR_B0MW_SHIFT                    (17U)
+#define FMC_PFB0CR_B0MW(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0MW_SHIFT)) & FMC_PFB0CR_B0MW_MASK)
+#define FMC_PFB0CR_S_B_INV                       (0x80000U)
+#define FMC_PFB0CR_CINV_WAY_MASK                 (0xF00000U)
+#define FMC_PFB0CR_CINV_WAY_SHIFT                (20U)
+#define FMC_PFB0CR_CINV_WAY(x)                   (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CINV_WAY_SHIFT)) & FMC_PFB0CR_CINV_WAY_MASK)
+#define FMC_PFB0CR_CLCK_WAY_MASK                 (0xF000000U)
+#define FMC_PFB0CR_CLCK_WAY_SHIFT                (24U)
+#define FMC_PFB0CR_CLCK_WAY(x)                   (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CLCK_WAY_SHIFT)) & FMC_PFB0CR_CLCK_WAY_MASK)
+#define FMC_PFB0CR_B0RWSC_MASK                   (0xF0000000U)
+#define FMC_PFB0CR_B0RWSC_SHIFT                  (28U)
+#define FMC_PFB0CR_B0RWSC(x)                     (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0RWSC_SHIFT)) & FMC_PFB0CR_B0RWSC_MASK)
+
+/*! @name PFB1CR - Flash Bank 1 Control Register */
+#define FMC_PFB1CR_B1SEBE                        (0x1U)
+#define FMC_PFB1CR_B1IPE                         (0x2U)
+#define FMC_PFB1CR_B1DPE                         (0x4U)
+#define FMC_PFB1CR_B1ICE                         (0x8U)
+#define FMC_PFB1CR_B1DCE                         (0x10U)
+#define FMC_PFB1CR_B1MW_MASK                     (0x60000U)
+#define FMC_PFB1CR_B1MW_SHIFT                    (17U)
+#define FMC_PFB1CR_B1MW(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1MW_SHIFT)) & FMC_PFB1CR_B1MW_MASK)
+#define FMC_PFB1CR_B1RWSC_MASK                   (0xF0000000U)
+#define FMC_PFB1CR_B1RWSC_SHIFT                  (28U)
+#define FMC_PFB1CR_B1RWSC(x)                     (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1RWSC_SHIFT)) & FMC_PFB1CR_B1RWSC_MASK)
+
+/*! @name TAGVDW0S - Cache Tag Storage */
+#define FMC_TAGVDW0S_valid                       (0x1U)
+#define FMC_TAGVDW0S_tag_MASK                    (0x7FFE0U)
+#define FMC_TAGVDW0S_tag_SHIFT                   (5U)
+#define FMC_TAGVDW0S_tag(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_tag_SHIFT)) & FMC_TAGVDW0S_tag_MASK)
+
+/* The count of FMC_TAGVDW0S */
+#define FMC_TAGVDW0S_COUNT                       (4U)
+
+/*! @name TAGVDW1S - Cache Tag Storage */
+#define FMC_TAGVDW1S_valid                       (0x1U)
+#define FMC_TAGVDW1S_tag_MASK                    (0x7FFE0U)
+#define FMC_TAGVDW1S_tag_SHIFT                   (5U)
+#define FMC_TAGVDW1S_tag(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_tag_SHIFT)) & FMC_TAGVDW1S_tag_MASK)
+
+/* The count of FMC_TAGVDW1S */
+#define FMC_TAGVDW1S_COUNT                       (4U)
+
+/*! @name TAGVDW2S - Cache Tag Storage */
+#define FMC_TAGVDW2S_valid                       (0x1U)
+#define FMC_TAGVDW2S_tag_MASK                    (0x7FFE0U)
+#define FMC_TAGVDW2S_tag_SHIFT                   (5U)
+#define FMC_TAGVDW2S_tag(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_tag_SHIFT)) & FMC_TAGVDW2S_tag_MASK)
+
+/* The count of FMC_TAGVDW2S */
+#define FMC_TAGVDW2S_COUNT                       (4U)
+
+/*! @name TAGVDW3S - Cache Tag Storage */
+#define FMC_TAGVDW3S_valid                       (0x1U)
+#define FMC_TAGVDW3S_tag_MASK                    (0x7FFE0U)
+#define FMC_TAGVDW3S_tag_SHIFT                   (5U)
+#define FMC_TAGVDW3S_tag(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_tag_SHIFT)) & FMC_TAGVDW3S_tag_MASK)
+
+/* The count of FMC_TAGVDW3S */
+#define FMC_TAGVDW3S_COUNT                       (4U)
+
+/* The count of FMC_DATA_U */
+#define FMC_DATA_U_COUNT                         (4U)
+
+/* The count of FMC_DATA_U */
+#define FMC_DATA_U_COUNT2                        (4U)
+
+/* The count of FMC_DATA_L */
+#define FMC_DATA_L_COUNT                         (4U)
+
+/* The count of FMC_DATA_L */
+#define FMC_DATA_L_COUNT2                        (4U)
+
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Masks */
+
+
+/* FMC - Peripheral instance base addresses */
+/** Peripheral FMC base address */
+#define FMC_BASE                                 (0x4001F000u)
+/** Peripheral FMC base pointer */
+#define FMC                                      ((FMC_TypeDef *)FMC_BASE)
+/** Array initializer of FMC peripheral base addresses */
+#define FMC_BASE_ADDRS                           { FMC_BASE }
+/** Array initializer of FMC peripheral base pointers */
+#define FMC_BASE_PTRS                            { FMC }
+
+/*!
+ * @}
+ */ /* end of group FMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTFE Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer
+ * @{
+ */
+
+/** FTFE - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t FSTAT;                              /**< Flash Status Register, offset: 0x0 */
+  __IO uint8_t FCNFG;                              /**< Flash Configuration Register, offset: 0x1 */
+  __I  uint8_t FSEC;                               /**< Flash Security Register, offset: 0x2 */
+  __I  uint8_t FOPT;                               /**< Flash Option Register, offset: 0x3 */
+  __IO uint8_t FCCOB3;                             /**< Flash Common Command Object Registers, offset: 0x4 */
+  __IO uint8_t FCCOB2;                             /**< Flash Common Command Object Registers, offset: 0x5 */
+  __IO uint8_t FCCOB1;                             /**< Flash Common Command Object Registers, offset: 0x6 */
+  __IO uint8_t FCCOB0;                             /**< Flash Common Command Object Registers, offset: 0x7 */
+  __IO uint8_t FCCOB7;                             /**< Flash Common Command Object Registers, offset: 0x8 */
+  __IO uint8_t FCCOB6;                             /**< Flash Common Command Object Registers, offset: 0x9 */
+  __IO uint8_t FCCOB5;                             /**< Flash Common Command Object Registers, offset: 0xA */
+  __IO uint8_t FCCOB4;                             /**< Flash Common Command Object Registers, offset: 0xB */
+  __IO uint8_t FCCOBB;                             /**< Flash Common Command Object Registers, offset: 0xC */
+  __IO uint8_t FCCOBA;                             /**< Flash Common Command Object Registers, offset: 0xD */
+  __IO uint8_t FCCOB9;                             /**< Flash Common Command Object Registers, offset: 0xE */
+  __IO uint8_t FCCOB8;                             /**< Flash Common Command Object Registers, offset: 0xF */
+  __IO uint8_t FPROT3;                             /**< Program Flash Protection Registers, offset: 0x10 */
+  __IO uint8_t FPROT2;                             /**< Program Flash Protection Registers, offset: 0x11 */
+  __IO uint8_t FPROT1;                             /**< Program Flash Protection Registers, offset: 0x12 */
+  __IO uint8_t FPROT0;                             /**< Program Flash Protection Registers, offset: 0x13 */
+       uint8_t RESERVED_0[2];
+  __IO uint8_t FEPROT;                             /**< EEPROM Protection Register, offset: 0x16 */
+  __IO uint8_t FDPROT;                             /**< Data Flash Protection Register, offset: 0x17 */
+} FTFE_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- FTFE Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Register_Masks FTFE Register Masks
+ * @{
+ */
+
+/*! @name FSTAT - Flash Status Register */
+#define FTFE_FSTAT_MGSTAT0                       (0x1U)
+#define FTFE_FSTAT_FPVIOL                        (0x10U)
+#define FTFE_FSTAT_ACCERR                        (0x20U)
+#define FTFE_FSTAT_RDCOLERR                      (0x40U)
+#define FTFE_FSTAT_CCIF                          (0x80U)
+
+/*! @name FCNFG - Flash Configuration Register */
+#define FTFE_FCNFG_EEERDY                        (0x1U)
+#define FTFE_FCNFG_RAMRDY                        (0x2U)
+#define FTFE_FCNFG_PFLSH                         (0x4U)
+#define FTFE_FCNFG_SWAP                          (0x8U)
+#define FTFE_FCNFG_ERSSUSP                       (0x10U)
+#define FTFE_FCNFG_ERSAREQ                       (0x20U)
+#define FTFE_FCNFG_RDCOLLIE                      (0x40U)
+#define FTFE_FCNFG_CCIE                          (0x80U)
+
+/*! @name FSEC - Flash Security Register */
+#define FTFE_FSEC_SEC_MASK                       (0x3U)
+#define FTFE_FSEC_SEC_SHIFT                      (0U)
+#define FTFE_FSEC_SEC(x)                         (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_SEC_SHIFT)) & FTFE_FSEC_SEC_MASK)
+#define FTFE_FSEC_FSLACC_MASK                    (0xCU)
+#define FTFE_FSEC_FSLACC_SHIFT                   (2U)
+#define FTFE_FSEC_FSLACC(x)                      (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_FSLACC_SHIFT)) & FTFE_FSEC_FSLACC_MASK)
+#define FTFE_FSEC_MEEN_MASK                      (0x30U)
+#define FTFE_FSEC_MEEN_SHIFT                     (4U)
+#define FTFE_FSEC_MEEN(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_MEEN_SHIFT)) & FTFE_FSEC_MEEN_MASK)
+#define FTFE_FSEC_KEYEN_MASK                     (0xC0U)
+#define FTFE_FSEC_KEYEN_SHIFT                    (6U)
+#define FTFE_FSEC_KEYEN(x)                       (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_KEYEN_SHIFT)) & FTFE_FSEC_KEYEN_MASK)
+
+/*! @name FOPT - Flash Option Register */
+#define FTFE_FOPT_OPT_MASK                       (0xFFU)
+#define FTFE_FOPT_OPT_SHIFT                      (0U)
+#define FTFE_FOPT_OPT(x)                         (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT_OPT_SHIFT)) & FTFE_FOPT_OPT_MASK)
+
+/*! @name FCCOB3 - Flash Common Command Object Registers */
+#define FTFE_FCCOB3_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB3_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB3_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB3_CCOBn_SHIFT)) & FTFE_FCCOB3_CCOBn_MASK)
+
+/*! @name FCCOB2 - Flash Common Command Object Registers */
+#define FTFE_FCCOB2_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB2_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB2_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB2_CCOBn_SHIFT)) & FTFE_FCCOB2_CCOBn_MASK)
+
+/*! @name FCCOB1 - Flash Common Command Object Registers */
+#define FTFE_FCCOB1_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB1_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB1_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB1_CCOBn_SHIFT)) & FTFE_FCCOB1_CCOBn_MASK)
+
+/*! @name FCCOB0 - Flash Common Command Object Registers */
+#define FTFE_FCCOB0_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB0_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB0_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB0_CCOBn_SHIFT)) & FTFE_FCCOB0_CCOBn_MASK)
+
+/*! @name FCCOB7 - Flash Common Command Object Registers */
+#define FTFE_FCCOB7_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB7_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB7_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB7_CCOBn_SHIFT)) & FTFE_FCCOB7_CCOBn_MASK)
+
+/*! @name FCCOB6 - Flash Common Command Object Registers */
+#define FTFE_FCCOB6_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB6_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB6_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB6_CCOBn_SHIFT)) & FTFE_FCCOB6_CCOBn_MASK)
+
+/*! @name FCCOB5 - Flash Common Command Object Registers */
+#define FTFE_FCCOB5_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB5_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB5_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB5_CCOBn_SHIFT)) & FTFE_FCCOB5_CCOBn_MASK)
+
+/*! @name FCCOB4 - Flash Common Command Object Registers */
+#define FTFE_FCCOB4_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB4_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB4_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB4_CCOBn_SHIFT)) & FTFE_FCCOB4_CCOBn_MASK)
+
+/*! @name FCCOBB - Flash Common Command Object Registers */
+#define FTFE_FCCOBB_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOBB_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOBB_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBB_CCOBn_SHIFT)) & FTFE_FCCOBB_CCOBn_MASK)
+
+/*! @name FCCOBA - Flash Common Command Object Registers */
+#define FTFE_FCCOBA_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOBA_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOBA_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBA_CCOBn_SHIFT)) & FTFE_FCCOBA_CCOBn_MASK)
+
+/*! @name FCCOB9 - Flash Common Command Object Registers */
+#define FTFE_FCCOB9_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB9_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB9_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB9_CCOBn_SHIFT)) & FTFE_FCCOB9_CCOBn_MASK)
+
+/*! @name FCCOB8 - Flash Common Command Object Registers */
+#define FTFE_FCCOB8_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB8_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB8_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB8_CCOBn_SHIFT)) & FTFE_FCCOB8_CCOBn_MASK)
+
+/*! @name FPROT3 - Program Flash Protection Registers */
+#define FTFE_FPROT3_PROT_MASK                    (0xFFU)
+#define FTFE_FPROT3_PROT_SHIFT                   (0U)
+#define FTFE_FPROT3_PROT(x)                      (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT3_PROT_SHIFT)) & FTFE_FPROT3_PROT_MASK)
+
+/*! @name FPROT2 - Program Flash Protection Registers */
+#define FTFE_FPROT2_PROT_MASK                    (0xFFU)
+#define FTFE_FPROT2_PROT_SHIFT                   (0U)
+#define FTFE_FPROT2_PROT(x)                      (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT2_PROT_SHIFT)) & FTFE_FPROT2_PROT_MASK)
+
+/*! @name FPROT1 - Program Flash Protection Registers */
+#define FTFE_FPROT1_PROT_MASK                    (0xFFU)
+#define FTFE_FPROT1_PROT_SHIFT                   (0U)
+#define FTFE_FPROT1_PROT(x)                      (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT1_PROT_SHIFT)) & FTFE_FPROT1_PROT_MASK)
+
+/*! @name FPROT0 - Program Flash Protection Registers */
+#define FTFE_FPROT0_PROT_MASK                    (0xFFU)
+#define FTFE_FPROT0_PROT_SHIFT                   (0U)
+#define FTFE_FPROT0_PROT(x)                      (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT0_PROT_SHIFT)) & FTFE_FPROT0_PROT_MASK)
+
+/*! @name FEPROT - EEPROM Protection Register */
+#define FTFE_FEPROT_EPROT_MASK                   (0xFFU)
+#define FTFE_FEPROT_EPROT_SHIFT                  (0U)
+#define FTFE_FEPROT_EPROT(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FEPROT_EPROT_SHIFT)) & FTFE_FEPROT_EPROT_MASK)
+
+/*! @name FDPROT - Data Flash Protection Register */
+#define FTFE_FDPROT_DPROT_MASK                   (0xFFU)
+#define FTFE_FDPROT_DPROT_SHIFT                  (0U)
+#define FTFE_FDPROT_DPROT(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FDPROT_DPROT_SHIFT)) & FTFE_FDPROT_DPROT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group FTFE_Register_Masks */
+
+
+/* FTFE - Peripheral instance base addresses */
+/** Peripheral FTFE base address */
+#define FTFE_BASE                                (0x40020000u)
+/** Peripheral FTFE base pointer */
+#define FTFE                                     ((FTFE_TypeDef *)FTFE_BASE)
+/** Array initializer of FTFE peripheral base addresses */
+#define FTFE_BASE_ADDRS                          { FTFE_BASE }
+/** Array initializer of FTFE peripheral base pointers */
+#define FTFE_BASE_PTRS                           { FTFE }
+/** Interrupt vectors for the FTFE peripheral type */
+#define FTFE_COMMAND_COMPLETE_IRQS               { FTFE_IRQn }
+#define FTFE_READ_COLLISION_IRQS                 { Read_Collision_IRQn }
+
+/*!
+ * @}
+ */ /* end of group FTFE_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
+ * @{
+ */
+
+/** FTM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC;                                /**< Status And Control, offset: 0x0 */
+  __IO uint32_t CNT;                               /**< Counter, offset: 0x4 */
+  __IO uint32_t MOD;                               /**< Modulo, offset: 0x8 */
+  struct {                                         /* offset: 0xC, array step: 0x8 */
+    __IO uint32_t CnSC;                              /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
+    __IO uint32_t CnV;                               /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+  } CONTROLS[8];
+  __IO uint32_t CNTIN;                             /**< Counter Initial Value, offset: 0x4C */
+  __IO uint32_t STATUS;                            /**< Capture And Compare Status, offset: 0x50 */
+  __IO uint32_t MODE;                              /**< Features Mode Selection, offset: 0x54 */
+  __IO uint32_t SYNC;                              /**< Synchronization, offset: 0x58 */
+  __IO uint32_t OUTINIT;                           /**< Initial State For Channels Output, offset: 0x5C */
+  __IO uint32_t OUTMASK;                           /**< Output Mask, offset: 0x60 */
+  __IO uint32_t COMBINE;                           /**< Function For Linked Channels, offset: 0x64 */
+  __IO uint32_t DEADTIME;                          /**< Deadtime Insertion Control, offset: 0x68 */
+  __IO uint32_t EXTTRIG;                           /**< FTM External Trigger, offset: 0x6C */
+  __IO uint32_t POL;                               /**< Channels Polarity, offset: 0x70 */
+  __IO uint32_t FMS;                               /**< Fault Mode Status, offset: 0x74 */
+  __IO uint32_t FILTER;                            /**< Input Capture Filter Control, offset: 0x78 */
+  __IO uint32_t FLTCTRL;                           /**< Fault Control, offset: 0x7C */
+  __IO uint32_t QDCTRL;                            /**< Quadrature Decoder Control And Status, offset: 0x80 */
+  __IO uint32_t CONF;                              /**< Configuration, offset: 0x84 */
+  __IO uint32_t FLTPOL;                            /**< FTM Fault Input Polarity, offset: 0x88 */
+  __IO uint32_t SYNCONF;                           /**< Synchronization Configuration, offset: 0x8C */
+  __IO uint32_t INVCTRL;                           /**< FTM Inverting Control, offset: 0x90 */
+  __IO uint32_t SWOCTRL;                           /**< FTM Software Output Control, offset: 0x94 */
+  __IO uint32_t PWMLOAD;                           /**< FTM PWM Load, offset: 0x98 */
+} FTM_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- FTM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Masks FTM Register Masks
+ * @{
+ */
+
+/*! @name SC - Status And Control */
+#define FTM_SC_PS_MASK                           (0x7U)
+#define FTM_SC_PS_SHIFT                          (0U)
+#define FTM_SC_PS(x)                             (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)
+#define FTM_SC_CLKS_MASK                         (0x18U)
+#define FTM_SC_CLKS_SHIFT                        (3U)
+#define FTM_SC_CLKS(x)                           (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)
+#define FTM_SC_CPWMS                             (0x20U)
+#define FTM_SC_TOIE                              (0x40U)
+#define FTM_SC_TOF                               (0x80U)
+
+/*! @name CNT - Counter */
+#define FTM_CNT_COUNT_MASK                       (0xFFFFU)
+#define FTM_CNT_COUNT_SHIFT                      (0U)
+#define FTM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
+
+/*! @name MOD - Modulo */
+#define FTM_MOD_MOD_MASK                         (0xFFFFU)
+#define FTM_MOD_MOD_SHIFT                        (0U)
+#define FTM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
+
+/*! @name CnSC - Channel (n) Status And Control */
+#define FTM_CnSC_DMA                             (0x1U)
+#define FTM_CnSC_ELSA                            (0x4U)
+#define FTM_CnSC_ELSB                            (0x8U)
+#define FTM_CnSC_MSA                             (0x10U)
+#define FTM_CnSC_MSB                             (0x20U)
+#define FTM_CnSC_CHIE                            (0x40U)
+#define FTM_CnSC_CHF                             (0x80U)
+
+/* The count of FTM_CnSC */
+#define FTM_CnSC_COUNT                           (8U)
+
+/*! @name CnV - Channel (n) Value */
+#define FTM_CnV_VAL_MASK                         (0xFFFFU)
+#define FTM_CnV_VAL_SHIFT                        (0U)
+#define FTM_CnV_VAL(x)                           (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
+
+/* The count of FTM_CnV */
+#define FTM_CnV_COUNT                            (8U)
+
+/*! @name CNTIN - Counter Initial Value */
+#define FTM_CNTIN_INIT_MASK                      (0xFFFFU)
+#define FTM_CNTIN_INIT_SHIFT                     (0U)
+#define FTM_CNTIN_INIT(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
+
+/*! @name STATUS - Capture And Compare Status */
+#define FTM_STATUS_CH0F                          (0x1U)
+#define FTM_STATUS_CH1F                          (0x2U)
+#define FTM_STATUS_CH2F                          (0x4U)
+#define FTM_STATUS_CH3F                          (0x8U)
+#define FTM_STATUS_CH4F                          (0x10U)
+#define FTM_STATUS_CH5F                          (0x20U)
+#define FTM_STATUS_CH6F                          (0x40U)
+#define FTM_STATUS_CH7F                          (0x80U)
+
+/*! @name MODE - Features Mode Selection */
+#define FTM_MODE_FTMEN                           (0x1U)
+#define FTM_MODE_INIT                            (0x2U)
+#define FTM_MODE_WPDIS                           (0x4U)
+#define FTM_MODE_PWMSYNC                         (0x8U)
+#define FTM_MODE_CAPTEST                         (0x10U)
+#define FTM_MODE_FAULTM_MASK                     (0x60U)
+#define FTM_MODE_FAULTM_SHIFT                    (5U)
+#define FTM_MODE_FAULTM(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
+#define FTM_MODE_FAULTIE                         (0x80U)
+
+/*! @name SYNC - Synchronization */
+#define FTM_SYNC_CNTMIN                          (0x1U)
+#define FTM_SYNC_CNTMAX                          (0x2U)
+#define FTM_SYNC_REINIT                          (0x4U)
+#define FTM_SYNC_SYNCHOM                         (0x8U)
+#define FTM_SYNC_TRIG0                           (0x10U)
+#define FTM_SYNC_TRIG1                           (0x20U)
+#define FTM_SYNC_TRIG2                           (0x40U)
+#define FTM_SYNC_SWSYNC                          (0x80U)
+
+/*! @name OUTINIT - Initial State For Channels Output */
+#define FTM_OUTINIT_CH0OI                        (0x1U)
+#define FTM_OUTINIT_CH1OI                        (0x2U)
+#define FTM_OUTINIT_CH2OI                        (0x4U)
+#define FTM_OUTINIT_CH3OI                        (0x8U)
+#define FTM_OUTINIT_CH4OI                        (0x10U)
+#define FTM_OUTINIT_CH5OI                        (0x20U)
+#define FTM_OUTINIT_CH6OI                        (0x40U)
+#define FTM_OUTINIT_CH7OI                        (0x80U)
+
+/*! @name OUTMASK - Output Mask */
+#define FTM_OUTMASK_CH0OM                        (0x1U)
+#define FTM_OUTMASK_CH1OM                        (0x2U)
+#define FTM_OUTMASK_CH2OM                        (0x4U)
+#define FTM_OUTMASK_CH3OM                        (0x8U)
+#define FTM_OUTMASK_CH4OM                        (0x10U)
+#define FTM_OUTMASK_CH5OM                        (0x20U)
+#define FTM_OUTMASK_CH6OM                        (0x40U)
+#define FTM_OUTMASK_CH7OM                        (0x80U)
+
+/*! @name COMBINE - Function For Linked Channels */
+#define FTM_COMBINE_COMBINE0                     (0x1U)
+#define FTM_COMBINE_COMP0                        (0x2U)
+#define FTM_COMBINE_DECAPEN0                     (0x4U)
+#define FTM_COMBINE_DECAP0                       (0x8U)
+#define FTM_COMBINE_DTEN0                        (0x10U)
+#define FTM_COMBINE_SYNCEN0                      (0x20U)
+#define FTM_COMBINE_FAULTEN0                     (0x40U)
+#define FTM_COMBINE_COMBINE1                     (0x100U)
+#define FTM_COMBINE_COMP1                        (0x200U)
+#define FTM_COMBINE_DECAPEN1                     (0x400U)
+#define FTM_COMBINE_DECAP1                       (0x800U)
+#define FTM_COMBINE_DTEN1                        (0x1000U)
+#define FTM_COMBINE_SYNCEN1                      (0x2000U)
+#define FTM_COMBINE_FAULTEN1                     (0x4000U)
+#define FTM_COMBINE_COMBINE2                     (0x10000U)
+#define FTM_COMBINE_COMP2                        (0x20000U)
+#define FTM_COMBINE_DECAPEN2                     (0x40000U)
+#define FTM_COMBINE_DECAP2                       (0x80000U)
+#define FTM_COMBINE_DTEN2                        (0x100000U)
+#define FTM_COMBINE_SYNCEN2                      (0x200000U)
+#define FTM_COMBINE_FAULTEN2                     (0x400000U)
+#define FTM_COMBINE_COMBINE3                     (0x1000000U)
+#define FTM_COMBINE_COMP3                        (0x2000000U)
+#define FTM_COMBINE_DECAPEN3                     (0x4000000U)
+#define FTM_COMBINE_DECAP3                       (0x8000000U)
+#define FTM_COMBINE_DTEN3                        (0x10000000U)
+#define FTM_COMBINE_SYNCEN3                      (0x20000000U)
+#define FTM_COMBINE_FAULTEN3                     (0x40000000U)
+
+/*! @name DEADTIME - Deadtime Insertion Control */
+#define FTM_DEADTIME_DTVAL_MASK                  (0x3FU)
+#define FTM_DEADTIME_DTVAL_SHIFT                 (0U)
+#define FTM_DEADTIME_DTVAL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
+#define FTM_DEADTIME_DTPS_MASK                   (0xC0U)
+#define FTM_DEADTIME_DTPS_SHIFT                  (6U)
+#define FTM_DEADTIME_DTPS(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
+
+/*! @name EXTTRIG - FTM External Trigger */
+#define FTM_EXTTRIG_CH2TRIG                      (0x1U)
+#define FTM_EXTTRIG_CH3TRIG                      (0x2U)
+#define FTM_EXTTRIG_CH4TRIG                      (0x4U)
+#define FTM_EXTTRIG_CH5TRIG                      (0x8U)
+#define FTM_EXTTRIG_CH0TRIG                      (0x10U)
+#define FTM_EXTTRIG_CH1TRIG                      (0x20U)
+#define FTM_EXTTRIG_INITTRIGEN                   (0x40U)
+#define FTM_EXTTRIG_TRIGF                        (0x80U)
+
+/*! @name POL - Channels Polarity */
+#define FTM_POL_POL0                             (0x1U)
+#define FTM_POL_POL1                             (0x2U)
+#define FTM_POL_POL2                             (0x4U)
+#define FTM_POL_POL3                             (0x8U)
+#define FTM_POL_POL4                             (0x10U)
+#define FTM_POL_POL5                             (0x20U)
+#define FTM_POL_POL6                             (0x40U)
+#define FTM_POL_POL7                             (0x80U)
+
+/*! @name FMS - Fault Mode Status */
+#define FTM_FMS_FAULTF0                          (0x1U)
+#define FTM_FMS_FAULTF1                          (0x2U)
+#define FTM_FMS_FAULTF2                          (0x4U)
+#define FTM_FMS_FAULTF3                          (0x8U)
+#define FTM_FMS_FAULTIN                          (0x20U)
+#define FTM_FMS_WPEN                             (0x40U)
+#define FTM_FMS_FAULTF                           (0x80U)
+
+/*! @name FILTER - Input Capture Filter Control */
+#define FTM_FILTER_CH0FVAL_MASK                  (0xFU)
+#define FTM_FILTER_CH0FVAL_SHIFT                 (0U)
+#define FTM_FILTER_CH0FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
+#define FTM_FILTER_CH1FVAL_MASK                  (0xF0U)
+#define FTM_FILTER_CH1FVAL_SHIFT                 (4U)
+#define FTM_FILTER_CH1FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
+#define FTM_FILTER_CH2FVAL_MASK                  (0xF00U)
+#define FTM_FILTER_CH2FVAL_SHIFT                 (8U)
+#define FTM_FILTER_CH2FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
+#define FTM_FILTER_CH3FVAL_MASK                  (0xF000U)
+#define FTM_FILTER_CH3FVAL_SHIFT                 (12U)
+#define FTM_FILTER_CH3FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
+
+/*! @name FLTCTRL - Fault Control */
+#define FTM_FLTCTRL_FAULT0EN                     (0x1U)
+#define FTM_FLTCTRL_FAULT1EN                     (0x2U)
+#define FTM_FLTCTRL_FAULT2EN                     (0x4U)
+#define FTM_FLTCTRL_FAULT3EN                     (0x8U)
+#define FTM_FLTCTRL_FFLTR0EN                     (0x10U)
+#define FTM_FLTCTRL_FFLTR1EN                     (0x20U)
+#define FTM_FLTCTRL_FFLTR2EN                     (0x40U)
+#define FTM_FLTCTRL_FFLTR3EN                     (0x80U)
+#define FTM_FLTCTRL_FFVAL_MASK                   (0xF00U)
+#define FTM_FLTCTRL_FFVAL_SHIFT                  (8U)
+#define FTM_FLTCTRL_FFVAL(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
+
+/*! @name QDCTRL - Quadrature Decoder Control And Status */
+#define FTM_QDCTRL_QUADEN                        (0x1U)
+#define FTM_QDCTRL_TOFDIR                        (0x2U)
+#define FTM_QDCTRL_QUADIR                        (0x4U)
+#define FTM_QDCTRL_QUADMODE                      (0x8U)
+#define FTM_QDCTRL_PHBPOL                        (0x10U)
+#define FTM_QDCTRL_PHAPOL                        (0x20U)
+#define FTM_QDCTRL_PHBFLTREN                     (0x40U)
+#define FTM_QDCTRL_PHAFLTREN                     (0x80U)
+
+/*! @name CONF - Configuration */
+#define FTM_CONF_NUMTOF_MASK                     (0x1FU)
+#define FTM_CONF_NUMTOF_SHIFT                    (0U)
+#define FTM_CONF_NUMTOF(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK)
+#define FTM_CONF_BDMMODE_MASK                    (0xC0U)
+#define FTM_CONF_BDMMODE_SHIFT                   (6U)
+#define FTM_CONF_BDMMODE(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
+#define FTM_CONF_GTBEEN                          (0x200U)
+#define FTM_CONF_GTBEOUT                         (0x400U)
+
+/*! @name FLTPOL - FTM Fault Input Polarity */
+#define FTM_FLTPOL_FLT0POL                       (0x1U)
+#define FTM_FLTPOL_FLT1POL                       (0x2U)
+#define FTM_FLTPOL_FLT2POL                       (0x4U)
+#define FTM_FLTPOL_FLT3POL                       (0x8U)
+
+/*! @name SYNCONF - Synchronization Configuration */
+#define FTM_SYNCONF_HWTRIGMODE                   (0x1U)
+#define FTM_SYNCONF_CNTINC                       (0x4U)
+#define FTM_SYNCONF_INVC                         (0x10U)
+#define FTM_SYNCONF_SWOC                         (0x20U)
+#define FTM_SYNCONF_SYNCMODE                     (0x80U)
+#define FTM_SYNCONF_SWRSTCNT                     (0x100U)
+#define FTM_SYNCONF_SWWRBUF                      (0x200U)
+#define FTM_SYNCONF_SWOM                         (0x400U)
+#define FTM_SYNCONF_SWINVC                       (0x800U)
+#define FTM_SYNCONF_SWSOC                        (0x1000U)
+#define FTM_SYNCONF_HWRSTCNT                     (0x10000U)
+#define FTM_SYNCONF_HWWRBUF                      (0x20000U)
+#define FTM_SYNCONF_HWOM                         (0x40000U)
+#define FTM_SYNCONF_HWINVC                       (0x80000U)
+#define FTM_SYNCONF_HWSOC                        (0x100000U)
+
+/*! @name INVCTRL - FTM Inverting Control */
+#define FTM_INVCTRL_INV0EN                       (0x1U)
+#define FTM_INVCTRL_INV1EN                       (0x2U)
+#define FTM_INVCTRL_INV2EN                       (0x4U)
+#define FTM_INVCTRL_INV3EN                       (0x8U)
+
+/*! @name SWOCTRL - FTM Software Output Control */
+#define FTM_SWOCTRL_CH0OC                        (0x1U)
+#define FTM_SWOCTRL_CH1OC                        (0x2U)
+#define FTM_SWOCTRL_CH2OC                        (0x4U)
+#define FTM_SWOCTRL_CH3OC                        (0x8U)
+#define FTM_SWOCTRL_CH4OC                        (0x10U)
+#define FTM_SWOCTRL_CH5OC                        (0x20U)
+#define FTM_SWOCTRL_CH6OC                        (0x40U)
+#define FTM_SWOCTRL_CH7OC                        (0x80U)
+#define FTM_SWOCTRL_CH0OCV                       (0x100U)
+#define FTM_SWOCTRL_CH1OCV                       (0x200U)
+#define FTM_SWOCTRL_CH2OCV                       (0x400U)
+#define FTM_SWOCTRL_CH3OCV                       (0x800U)
+#define FTM_SWOCTRL_CH4OCV                       (0x1000U)
+#define FTM_SWOCTRL_CH5OCV                       (0x2000U)
+#define FTM_SWOCTRL_CH6OCV                       (0x4000U)
+#define FTM_SWOCTRL_CH7OCV                       (0x8000U)
+
+/*! @name PWMLOAD - FTM PWM Load */
+#define FTM_PWMLOAD_CH0SEL                       (0x1U)
+#define FTM_PWMLOAD_CH1SEL                       (0x2U)
+#define FTM_PWMLOAD_CH2SEL                       (0x4U)
+#define FTM_PWMLOAD_CH3SEL                       (0x8U)
+#define FTM_PWMLOAD_CH4SEL                       (0x10U)
+#define FTM_PWMLOAD_CH5SEL                       (0x20U)
+#define FTM_PWMLOAD_CH6SEL                       (0x40U)
+#define FTM_PWMLOAD_CH7SEL                       (0x80U)
+#define FTM_PWMLOAD_LDOK                         (0x200U)
+
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Masks */
+
+
+/* FTM - Peripheral instance base addresses */
+/** Peripheral FTM0 base address */
+#define FTM0_BASE                                (0x40038000u)
+/** Peripheral FTM0 base pointer */
+#define FTM0                                     ((FTM_TypeDef *)FTM0_BASE)
+/** Peripheral FTM1 base address */
+#define FTM1_BASE                                (0x40039000u)
+/** Peripheral FTM1 base pointer */
+#define FTM1                                     ((FTM_TypeDef *)FTM1_BASE)
+/** Peripheral FTM2 base address */
+#define FTM2_BASE                                (0x4003A000u)
+/** Peripheral FTM2 base pointer */
+#define FTM2                                     ((FTM_TypeDef *)FTM2_BASE)
+/** Peripheral FTM3 base address */
+#define FTM3_BASE                                (0x400B9000u)
+/** Peripheral FTM3 base pointer */
+#define FTM3                                     ((FTM_TypeDef *)FTM3_BASE)
+/** Array initializer of FTM peripheral base addresses */
+#define FTM_BASE_ADDRS                           { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
+/** Array initializer of FTM peripheral base pointers */
+#define FTM_BASE_PTRS                            { FTM0, FTM1, FTM2, FTM3 }
+/** Interrupt vectors for the FTM peripheral type */
+#define FTM_IRQS                                 { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }
+
+/*!
+ * @}
+ */ /* end of group FTM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x0 */
+  __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x4 */
+  __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x8 */
+  __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0xC */
+  __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x10 */
+  __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x14 */
+} GPIO_TypeDef;
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral GPIOA base address */
+#define GPIOA_BASE                               (0x400FF000u)
+/** Peripheral GPIOA base pointer */
+#define GPIOA                                    ((GPIO_TypeDef *)GPIOA_BASE)
+/** Peripheral GPIOB base address */
+#define GPIOB_BASE                               (0x400FF040u)
+/** Peripheral GPIOB base pointer */
+#define GPIOB                                    ((GPIO_TypeDef *)GPIOB_BASE)
+/** Peripheral GPIOC base address */
+#define GPIOC_BASE                               (0x400FF080u)
+/** Peripheral GPIOC base pointer */
+#define GPIOC                                    ((GPIO_TypeDef *)GPIOC_BASE)
+/** Peripheral GPIOD base address */
+#define GPIOD_BASE                               (0x400FF0C0u)
+/** Peripheral GPIOD base pointer */
+#define GPIOD                                    ((GPIO_TypeDef *)GPIOD_BASE)
+/** Peripheral GPIOE base address */
+#define GPIOE_BASE                               (0x400FF100u)
+/** Peripheral GPIOE base pointer */
+#define GPIOE                                    ((GPIO_TypeDef *)GPIOE_BASE)
+/** Array initializer of GPIO peripheral base addresses */
+#define GPIO_BASE_ADDRS                          { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASE_PTRS                           { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2C Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t A1;                                 /**< I2C Address Register 1, offset: 0x0 */
+  __IO uint8_t F;                                  /**< I2C Frequency Divider register, offset: 0x1 */
+  __IO uint8_t C1;                                 /**< I2C Control Register 1, offset: 0x2 */
+  __IO uint8_t S;                                  /**< I2C Status register, offset: 0x3 */
+  __IO uint8_t D;                                  /**< I2C Data I/O register, offset: 0x4 */
+  __IO uint8_t C2;                                 /**< I2C Control Register 2, offset: 0x5 */
+  __IO uint8_t FLT;                                /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
+  __IO uint8_t RA;                                 /**< I2C Range Address register, offset: 0x7 */
+  __IO uint8_t SMB;                                /**< I2C SMBus Control and Status register, offset: 0x8 */
+  __IO uint8_t A2;                                 /**< I2C Address Register 2, offset: 0x9 */
+  __IO uint8_t SLTH;                               /**< I2C SCL Low Timeout Register High, offset: 0xA */
+  __IO uint8_t SLTL;                               /**< I2C SCL Low Timeout Register Low, offset: 0xB */
+} I2C_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- I2C Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/*! @name A1 - I2C Address Register 1 */
+#define I2C_A1_AD_MASK                           (0xFEU)
+#define I2C_A1_AD_SHIFT                          (1U)
+#define I2C_A1_AD(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
+
+/*! @name F - I2C Frequency Divider register */
+#define I2C_F_ICR_MASK                           (0x3FU)
+#define I2C_F_ICR_SHIFT                          (0U)
+#define I2C_F_ICR(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK                          (0xC0U)
+#define I2C_F_MULT_SHIFT                         (6U)
+#define I2C_F_MULT(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
+
+/*! @name C1 - I2C Control Register 1 */
+#define I2C_C1_DMAEN                             (0x1U)
+#define I2C_C1_WUEN                              (0x2U)
+#define I2C_C1_RSTA                              (0x4U)
+#define I2C_C1_TXAK                              (0x8U)
+#define I2C_C1_TX                                (0x10U)
+#define I2C_C1_MST                               (0x20U)
+#define I2C_C1_IICIE                             (0x40U)
+#define I2C_C1_IICEN                             (0x80U)
+
+/*! @name S - I2C Status register */
+#define I2C_S_RXAK                               (0x1U)
+#define I2C_S_IICIF                              (0x2U)
+#define I2C_S_SRW                                (0x4U)
+#define I2C_S_RAM                                (0x8U)
+#define I2C_S_ARBL                               (0x10U)
+#define I2C_S_BUSY                               (0x20U)
+#define I2C_S_IAAS                               (0x40U)
+#define I2C_S_TCF                                (0x80U)
+
+/*! @name C2 - I2C Control Register 2 */
+#define I2C_C2_AD_MASK                           (0x7U)
+#define I2C_C2_AD_SHIFT                          (0U)
+#define I2C_C2_AD(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
+#define I2C_C2_RMEN                              (0x8U)
+#define I2C_C2_SBRC                              (0x10U)
+#define I2C_C2_HDRS                              (0x20U)
+#define I2C_C2_ADEXT                             (0x40U)
+#define I2C_C2_GCAEN                             (0x80U)
+
+/*! @name FLT - I2C Programmable Input Glitch Filter register */
+#define I2C_FLT_FLT_MASK                         (0xFU)
+#define I2C_FLT_FLT_SHIFT                        (0U)
+#define I2C_FLT_FLT(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
+#define I2C_FLT_STARTF                           (0x10U)
+#define I2C_FLT_SSIE                             (0x20U)
+#define I2C_FLT_STOPF                            (0x40U)
+#define I2C_FLT_SHEN                             (0x80U)
+
+/*! @name RA - I2C Range Address register */
+#define I2C_RA_RAD_MASK                          (0xFEU)
+#define I2C_RA_RAD_SHIFT                         (1U)
+#define I2C_RA_RAD(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
+
+/*! @name SMB - I2C SMBus Control and Status register */
+#define I2C_SMB_SHTF2IE                          (0x1U)
+#define I2C_SMB_SHTF2                            (0x2U)
+#define I2C_SMB_SHTF1                            (0x4U)
+#define I2C_SMB_SLTF                             (0x8U)
+#define I2C_SMB_TCKSEL                           (0x10U)
+#define I2C_SMB_SIICAEN                          (0x20U)
+#define I2C_SMB_ALERTEN                          (0x40U)
+#define I2C_SMB_FACK                             (0x80U)
+
+/*! @name A2 - I2C Address Register 2 */
+#define I2C_A2_SAD_MASK                          (0xFEU)
+#define I2C_A2_SAD_SHIFT                         (1U)
+#define I2C_A2_SAD(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE                                (0x40066000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0                                     ((I2C_TypeDef *)I2C0_BASE)
+/** Peripheral I2C1 base address */
+#define I2C1_BASE                                (0x40067000u)
+/** Peripheral I2C1 base pointer */
+#define I2C1                                     ((I2C_TypeDef *)I2C1_BASE)
+/** Peripheral I2C2 base address */
+#define I2C2_BASE                                (0x400E6000u)
+/** Peripheral I2C2 base pointer */
+#define I2C2                                     ((I2C_TypeDef *)I2C2_BASE)
+/** Array initializer of I2C peripheral base addresses */
+#define I2C_BASE_ADDRS                           { I2C0_BASE, I2C1_BASE, I2C2_BASE }
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASE_PTRS                            { I2C0, I2C1, I2C2 }
+/** Interrupt vectors for the I2C peripheral type */
+#define I2C_IRQS                                 { I2C0_IRQn, I2C1_IRQn, I2C2_IRQn }
+
+/*!
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2S Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t TCSR;                              /**< SAI Transmit Control Register, offset: 0x0 */
+  __IO uint32_t TCR1;                              /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
+  __IO uint32_t TCR2;                              /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
+  __IO uint32_t TCR3;                              /**< SAI Transmit Configuration 3 Register, offset: 0xC */
+  __IO uint32_t TCR4;                              /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
+  __IO uint32_t TCR5;                              /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
+       uint8_t RESERVED_0[8];
+  __O  uint32_t TDR[2];                            /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
+       uint8_t RESERVED_1[24];
+  __I  uint32_t TFR[2];                            /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
+       uint8_t RESERVED_2[24];
+  __IO uint32_t TMR;                               /**< SAI Transmit Mask Register, offset: 0x60 */
+       uint8_t RESERVED_3[28];
+  __IO uint32_t RCSR;                              /**< SAI Receive Control Register, offset: 0x80 */
+  __IO uint32_t RCR1;                              /**< SAI Receive Configuration 1 Register, offset: 0x84 */
+  __IO uint32_t RCR2;                              /**< SAI Receive Configuration 2 Register, offset: 0x88 */
+  __IO uint32_t RCR3;                              /**< SAI Receive Configuration 3 Register, offset: 0x8C */
+  __IO uint32_t RCR4;                              /**< SAI Receive Configuration 4 Register, offset: 0x90 */
+  __IO uint32_t RCR5;                              /**< SAI Receive Configuration 5 Register, offset: 0x94 */
+       uint8_t RESERVED_4[8];
+  __I  uint32_t RDR[2];                            /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
+       uint8_t RESERVED_5[24];
+  __I  uint32_t RFR[2];                            /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
+       uint8_t RESERVED_6[24];
+  __IO uint32_t RMR;                               /**< SAI Receive Mask Register, offset: 0xE0 */
+       uint8_t RESERVED_7[28];
+  __IO uint32_t MCR;                               /**< SAI MCLK Control Register, offset: 0x100 */
+  __IO uint32_t MDR;                               /**< SAI MCLK Divide Register, offset: 0x104 */
+} I2S_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- I2S Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/*! @name TCSR - SAI Transmit Control Register */
+#define I2S_TCSR_FRDE                            (0x1U)
+#define I2S_TCSR_FWDE                            (0x2U)
+#define I2S_TCSR_FRIE                            (0x100U)
+#define I2S_TCSR_FWIE                            (0x200U)
+#define I2S_TCSR_FEIE                            (0x400U)
+#define I2S_TCSR_SEIE                            (0x800U)
+#define I2S_TCSR_WSIE                            (0x1000U)
+#define I2S_TCSR_FRF                             (0x10000U)
+#define I2S_TCSR_FWF                             (0x20000U)
+#define I2S_TCSR_FEF                             (0x40000U)
+#define I2S_TCSR_SEF                             (0x80000U)
+#define I2S_TCSR_WSF                             (0x100000U)
+#define I2S_TCSR_SR                              (0x1000000U)
+#define I2S_TCSR_FR                              (0x2000000U)
+#define I2S_TCSR_BCE                             (0x10000000U)
+#define I2S_TCSR_DBGE                            (0x20000000U)
+#define I2S_TCSR_STOPE                           (0x40000000U)
+#define I2S_TCSR_TE                              (0x80000000U)
+
+/*! @name TCR1 - SAI Transmit Configuration 1 Register */
+#define I2S_TCR1_TFW_MASK                        (0x7U)
+#define I2S_TCR1_TFW_SHIFT                       (0U)
+#define I2S_TCR1_TFW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
+
+/*! @name TCR2 - SAI Transmit Configuration 2 Register */
+#define I2S_TCR2_DIV_MASK                        (0xFFU)
+#define I2S_TCR2_DIV_SHIFT                       (0U)
+#define I2S_TCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
+#define I2S_TCR2_BCD                             (0x1000000U)
+#define I2S_TCR2_BCP                             (0x2000000U)
+#define I2S_TCR2_MSEL_MASK                       (0xC000000U)
+#define I2S_TCR2_MSEL_SHIFT                      (26U)
+#define I2S_TCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
+#define I2S_TCR2_BCI                             (0x10000000U)
+#define I2S_TCR2_BCS                             (0x20000000U)
+#define I2S_TCR2_SYNC_MASK                       (0xC0000000U)
+#define I2S_TCR2_SYNC_SHIFT                      (30U)
+#define I2S_TCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
+
+/*! @name TCR3 - SAI Transmit Configuration 3 Register */
+#define I2S_TCR3_WDFL_MASK                       (0x1FU)
+#define I2S_TCR3_WDFL_SHIFT                      (0U)
+#define I2S_TCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
+#define I2S_TCR3_TCE_MASK                        (0x30000U)
+#define I2S_TCR3_TCE_SHIFT                       (16U)
+#define I2S_TCR3_TCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
+
+/*! @name TCR4 - SAI Transmit Configuration 4 Register */
+#define I2S_TCR4_FSD                             (0x1U)
+#define I2S_TCR4_FSP                             (0x2U)
+#define I2S_TCR4_FSE                             (0x8U)
+#define I2S_TCR4_MF                              (0x10U)
+#define I2S_TCR4_SYWD_MASK                       (0x1F00U)
+#define I2S_TCR4_SYWD_SHIFT                      (8U)
+#define I2S_TCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
+#define I2S_TCR4_FRSZ_MASK                       (0x1F0000U)
+#define I2S_TCR4_FRSZ_SHIFT                      (16U)
+#define I2S_TCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
+
+/*! @name TCR5 - SAI Transmit Configuration 5 Register */
+#define I2S_TCR5_FBT_MASK                        (0x1F00U)
+#define I2S_TCR5_FBT_SHIFT                       (8U)
+#define I2S_TCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
+#define I2S_TCR5_W0W_MASK                        (0x1F0000U)
+#define I2S_TCR5_W0W_SHIFT                       (16U)
+#define I2S_TCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
+#define I2S_TCR5_WNW_MASK                        (0x1F000000U)
+#define I2S_TCR5_WNW_SHIFT                       (24U)
+#define I2S_TCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
+
+/* The count of I2S_TDR */
+#define I2S_TDR_COUNT                            (2U)
+
+/*! @name TFR - SAI Transmit FIFO Register */
+#define I2S_TFR_RFP_MASK                         (0xFU)
+#define I2S_TFR_RFP_SHIFT                        (0U)
+#define I2S_TFR_RFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
+#define I2S_TFR_WFP_MASK                         (0xF0000U)
+#define I2S_TFR_WFP_SHIFT                        (16U)
+#define I2S_TFR_WFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
+
+/* The count of I2S_TFR */
+#define I2S_TFR_COUNT                            (2U)
+
+/*! @name RCSR - SAI Receive Control Register */
+#define I2S_RCSR_FRDE                            (0x1U)
+#define I2S_RCSR_FWDE                            (0x2U)
+#define I2S_RCSR_FRIE                            (0x100U)
+#define I2S_RCSR_FWIE                            (0x200U)
+#define I2S_RCSR_FEIE                            (0x400U)
+#define I2S_RCSR_SEIE                            (0x800U)
+#define I2S_RCSR_WSIE                            (0x1000U)
+#define I2S_RCSR_FRF                             (0x10000U)
+#define I2S_RCSR_FWF                             (0x20000U)
+#define I2S_RCSR_FEF                             (0x40000U)
+#define I2S_RCSR_SEF                             (0x80000U)
+#define I2S_RCSR_WSF                             (0x100000U)
+#define I2S_RCSR_SR                              (0x1000000U)
+#define I2S_RCSR_FR                              (0x2000000U)
+#define I2S_RCSR_BCE                             (0x10000000U)
+#define I2S_RCSR_DBGE                            (0x20000000U)
+#define I2S_RCSR_STOPE                           (0x40000000U)
+#define I2S_RCSR_RE                              (0x80000000U)
+
+/*! @name RCR1 - SAI Receive Configuration 1 Register */
+#define I2S_RCR1_RFW_MASK                        (0x7U)
+#define I2S_RCR1_RFW_SHIFT                       (0U)
+#define I2S_RCR1_RFW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
+
+/*! @name RCR2 - SAI Receive Configuration 2 Register */
+#define I2S_RCR2_DIV_MASK                        (0xFFU)
+#define I2S_RCR2_DIV_SHIFT                       (0U)
+#define I2S_RCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
+#define I2S_RCR2_BCD                             (0x1000000U)
+#define I2S_RCR2_BCP                             (0x2000000U)
+#define I2S_RCR2_MSEL_MASK                       (0xC000000U)
+#define I2S_RCR2_MSEL_SHIFT                      (26U)
+#define I2S_RCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
+#define I2S_RCR2_BCI                             (0x10000000U)
+#define I2S_RCR2_BCS                             (0x20000000U)
+#define I2S_RCR2_SYNC_MASK                       (0xC0000000U)
+#define I2S_RCR2_SYNC_SHIFT                      (30U)
+#define I2S_RCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
+
+/*! @name RCR3 - SAI Receive Configuration 3 Register */
+#define I2S_RCR3_WDFL_MASK                       (0x1FU)
+#define I2S_RCR3_WDFL_SHIFT                      (0U)
+#define I2S_RCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
+#define I2S_RCR3_RCE_MASK                        (0x30000U)
+#define I2S_RCR3_RCE_SHIFT                       (16U)
+#define I2S_RCR3_RCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
+
+/*! @name RCR4 - SAI Receive Configuration 4 Register */
+#define I2S_RCR4_FSD                             (0x1U)
+#define I2S_RCR4_FSP                             (0x2U)
+#define I2S_RCR4_FSE                             (0x8U)
+#define I2S_RCR4_MF                              (0x10U)
+#define I2S_RCR4_SYWD_MASK                       (0x1F00U)
+#define I2S_RCR4_SYWD_SHIFT                      (8U)
+#define I2S_RCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
+#define I2S_RCR4_FRSZ_MASK                       (0x1F0000U)
+#define I2S_RCR4_FRSZ_SHIFT                      (16U)
+#define I2S_RCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
+
+/*! @name RCR5 - SAI Receive Configuration 5 Register */
+#define I2S_RCR5_FBT_MASK                        (0x1F00U)
+#define I2S_RCR5_FBT_SHIFT                       (8U)
+#define I2S_RCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
+#define I2S_RCR5_W0W_MASK                        (0x1F0000U)
+#define I2S_RCR5_W0W_SHIFT                       (16U)
+#define I2S_RCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
+#define I2S_RCR5_WNW_MASK                        (0x1F000000U)
+#define I2S_RCR5_WNW_SHIFT                       (24U)
+#define I2S_RCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
+
+/* The count of I2S_RDR */
+#define I2S_RDR_COUNT                            (2U)
+
+/*! @name RFR - SAI Receive FIFO Register */
+#define I2S_RFR_RFP_MASK                         (0xFU)
+#define I2S_RFR_RFP_SHIFT                        (0U)
+#define I2S_RFR_RFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
+#define I2S_RFR_WFP_MASK                         (0xF0000U)
+#define I2S_RFR_WFP_SHIFT                        (16U)
+#define I2S_RFR_WFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
+
+/* The count of I2S_RFR */
+#define I2S_RFR_COUNT                            (2U)
+
+/*! @name MCR - SAI MCLK Control Register */
+#define I2S_MCR_MICS_MASK                        (0x3000000U)
+#define I2S_MCR_MICS_SHIFT                       (24U)
+#define I2S_MCR_MICS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)
+#define I2S_MCR_MOE                              (0x40000000U)
+#define I2S_MCR_DUF                              (0x80000000U)
+
+/*! @name MDR - SAI MCLK Divide Register */
+#define I2S_MDR_DIVIDE_MASK                      (0xFFFU)
+#define I2S_MDR_DIVIDE_SHIFT                     (0U)
+#define I2S_MDR_DIVIDE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK)
+#define I2S_MDR_FRACT_MASK                       (0xFF000U)
+#define I2S_MDR_FRACT_SHIFT                      (12U)
+#define I2S_MDR_FRACT(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/** Peripheral I2S0 base address */
+#define I2S0_BASE                                (0x4002F000u)
+/** Peripheral I2S0 base pointer */
+#define I2S0                                     ((I2S_TypeDef *)I2S0_BASE)
+/** Array initializer of I2S peripheral base addresses */
+#define I2S_BASE_ADDRS                           { I2S0_BASE }
+/** Array initializer of I2S peripheral base pointers */
+#define I2S_BASE_PTRS                            { I2S0 }
+/** Interrupt vectors for the I2S peripheral type */
+#define I2S_RX_IRQS                              { I2S0_Rx_IRQn }
+#define I2S_TX_IRQS                              { I2S0_Tx_IRQn }
+
+/*!
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LLWU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
+ * @{
+ */
+
+/** LLWU - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t PE1;                                /**< LLWU Pin Enable 1 register, offset: 0x0 */
+  __IO uint8_t PE2;                                /**< LLWU Pin Enable 2 register, offset: 0x1 */
+  __IO uint8_t PE3;                                /**< LLWU Pin Enable 3 register, offset: 0x2 */
+  __IO uint8_t PE4;                                /**< LLWU Pin Enable 4 register, offset: 0x3 */
+  __IO uint8_t ME;                                 /**< LLWU Module Enable register, offset: 0x4 */
+  __IO uint8_t F1;                                 /**< LLWU Flag 1 register, offset: 0x5 */
+  __IO uint8_t F2;                                 /**< LLWU Flag 2 register, offset: 0x6 */
+  __I  uint8_t F3;                                 /**< LLWU Flag 3 register, offset: 0x7 */
+  __IO uint8_t FILT1;                              /**< LLWU Pin Filter 1 register, offset: 0x8 */
+  __IO uint8_t FILT2;                              /**< LLWU Pin Filter 2 register, offset: 0x9 */
+  __IO uint8_t RST;                                /**< LLWU Reset Enable register, offset: 0xA */
+} LLWU_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- LLWU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/*! @name PE1 - LLWU Pin Enable 1 register */
+#define LLWU_PE1_WUPE0_MASK                      (0x3U)
+#define LLWU_PE1_WUPE0_SHIFT                     (0U)
+#define LLWU_PE1_WUPE0(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK                      (0xCU)
+#define LLWU_PE1_WUPE1_SHIFT                     (2U)
+#define LLWU_PE1_WUPE1(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK                      (0x30U)
+#define LLWU_PE1_WUPE2_SHIFT                     (4U)
+#define LLWU_PE1_WUPE2(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK                      (0xC0U)
+#define LLWU_PE1_WUPE3_SHIFT                     (6U)
+#define LLWU_PE1_WUPE3(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
+
+/*! @name PE2 - LLWU Pin Enable 2 register */
+#define LLWU_PE2_WUPE4_MASK                      (0x3U)
+#define LLWU_PE2_WUPE4_SHIFT                     (0U)
+#define LLWU_PE2_WUPE4(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK                      (0xCU)
+#define LLWU_PE2_WUPE5_SHIFT                     (2U)
+#define LLWU_PE2_WUPE5(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK                      (0x30U)
+#define LLWU_PE2_WUPE6_SHIFT                     (4U)
+#define LLWU_PE2_WUPE6(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK                      (0xC0U)
+#define LLWU_PE2_WUPE7_SHIFT                     (6U)
+#define LLWU_PE2_WUPE7(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
+
+/*! @name PE3 - LLWU Pin Enable 3 register */
+#define LLWU_PE3_WUPE8_MASK                      (0x3U)
+#define LLWU_PE3_WUPE8_SHIFT                     (0U)
+#define LLWU_PE3_WUPE8(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE9_MASK                      (0xCU)
+#define LLWU_PE3_WUPE9_SHIFT                     (2U)
+#define LLWU_PE3_WUPE9(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE10_MASK                     (0x30U)
+#define LLWU_PE3_WUPE10_SHIFT                    (4U)
+#define LLWU_PE3_WUPE10(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE11_MASK                     (0xC0U)
+#define LLWU_PE3_WUPE11_SHIFT                    (6U)
+#define LLWU_PE3_WUPE11(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
+
+/*! @name PE4 - LLWU Pin Enable 4 register */
+#define LLWU_PE4_WUPE12_MASK                     (0x3U)
+#define LLWU_PE4_WUPE12_SHIFT                    (0U)
+#define LLWU_PE4_WUPE12(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE13_MASK                     (0xCU)
+#define LLWU_PE4_WUPE13_SHIFT                    (2U)
+#define LLWU_PE4_WUPE13(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE14_MASK                     (0x30U)
+#define LLWU_PE4_WUPE14_SHIFT                    (4U)
+#define LLWU_PE4_WUPE14(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE15_MASK                     (0xC0U)
+#define LLWU_PE4_WUPE15_SHIFT                    (6U)
+#define LLWU_PE4_WUPE15(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
+
+/*! @name ME - LLWU Module Enable register */
+#define LLWU_ME_WUME0                            (0x1U)
+#define LLWU_ME_WUME1                            (0x2U)
+#define LLWU_ME_WUME2                            (0x4U)
+#define LLWU_ME_WUME3                            (0x8U)
+#define LLWU_ME_WUME4                            (0x10U)
+#define LLWU_ME_WUME5                            (0x20U)
+#define LLWU_ME_WUME6                            (0x40U)
+#define LLWU_ME_WUME7                            (0x80U)
+
+/*! @name F1 - LLWU Flag 1 register */
+#define LLWU_F1_WUF0                             (0x1U)
+#define LLWU_F1_WUF1                             (0x2U)
+#define LLWU_F1_WUF2                             (0x4U)
+#define LLWU_F1_WUF3                             (0x8U)
+#define LLWU_F1_WUF4                             (0x10U)
+#define LLWU_F1_WUF5                             (0x20U)
+#define LLWU_F1_WUF6                             (0x40U)
+#define LLWU_F1_WUF7                             (0x80U)
+
+/*! @name F2 - LLWU Flag 2 register */
+#define LLWU_F2_WUF8                             (0x1U)
+#define LLWU_F2_WUF9                             (0x2U)
+#define LLWU_F2_WUF10                            (0x4U)
+#define LLWU_F2_WUF11                            (0x8U)
+#define LLWU_F2_WUF12                            (0x10U)
+#define LLWU_F2_WUF13                            (0x20U)
+#define LLWU_F2_WUF14                            (0x40U)
+#define LLWU_F2_WUF15                            (0x80U)
+
+/*! @name F3 - LLWU Flag 3 register */
+#define LLWU_F3_MWUF0                            (0x1U)
+#define LLWU_F3_MWUF1                            (0x2U)
+#define LLWU_F3_MWUF2                            (0x4U)
+#define LLWU_F3_MWUF3                            (0x8U)
+#define LLWU_F3_MWUF4                            (0x10U)
+#define LLWU_F3_MWUF5                            (0x20U)
+#define LLWU_F3_MWUF6                            (0x40U)
+#define LLWU_F3_MWUF7                            (0x80U)
+
+/*! @name FILT1 - LLWU Pin Filter 1 register */
+#define LLWU_FILT1_FILTSEL_MASK                  (0xFU)
+#define LLWU_FILT1_FILTSEL_SHIFT                 (0U)
+#define LLWU_FILT1_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK                    (0x60U)
+#define LLWU_FILT1_FILTE_SHIFT                   (5U)
+#define LLWU_FILT1_FILTE(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF                         (0x80U)
+
+/*! @name FILT2 - LLWU Pin Filter 2 register */
+#define LLWU_FILT2_FILTSEL_MASK                  (0xFU)
+#define LLWU_FILT2_FILTSEL_SHIFT                 (0U)
+#define LLWU_FILT2_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK                    (0x60U)
+#define LLWU_FILT2_FILTE_SHIFT                   (5U)
+#define LLWU_FILT2_FILTE(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF                         (0x80U)
+
+/*! @name RST - LLWU Reset Enable register */
+#define LLWU_RST_RSTFILT                         (0x1U)
+#define LLWU_RST_LLRSTE                          (0x2U)
+
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/** Peripheral LLWU base address */
+#define LLWU_BASE                                (0x4007C000u)
+/** Peripheral LLWU base pointer */
+#define LLWU                                     ((LLWU_TypeDef *)LLWU_BASE)
+/** Array initializer of LLWU peripheral base addresses */
+#define LLWU_BASE_ADDRS                          { LLWU_BASE }
+/** Array initializer of LLWU peripheral base pointers */
+#define LLWU_BASE_PTRS                           { LLWU }
+/** Interrupt vectors for the LLWU peripheral type */
+#define LLWU_IRQS                                { LLWU_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CSR;                               /**< Low Power Timer Control Status Register, offset: 0x0 */
+  __IO uint32_t PSR;                               /**< Low Power Timer Prescale Register, offset: 0x4 */
+  __IO uint32_t CMR;                               /**< Low Power Timer Compare Register, offset: 0x8 */
+  __IO uint32_t CNR;                               /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/*! @name CSR - Low Power Timer Control Status Register */
+#define LPTMR_CSR_TEN                            (0x1U)
+#define LPTMR_CSR_TMS                            (0x2U)
+#define LPTMR_CSR_TFC                            (0x4U)
+#define LPTMR_CSR_TPP                            (0x8U)
+#define LPTMR_CSR_TPS_MASK                       (0x30U)
+#define LPTMR_CSR_TPS_SHIFT                      (4U)
+#define LPTMR_CSR_TPS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE                            (0x40U)
+#define LPTMR_CSR_TCF                            (0x80U)
+
+/*! @name PSR - Low Power Timer Prescale Register */
+#define LPTMR_PSR_PCS_MASK                       (0x3U)
+#define LPTMR_PSR_PCS_SHIFT                      (0U)
+#define LPTMR_PSR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP                           (0x4U)
+#define LPTMR_PSR_PRESCALE_MASK                  (0x78U)
+#define LPTMR_PSR_PRESCALE_SHIFT                 (3U)
+#define LPTMR_PSR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
+
+/*! @name CMR - Low Power Timer Compare Register */
+#define LPTMR_CMR_COMPARE_MASK                   (0xFFFFU)
+#define LPTMR_CMR_COMPARE_SHIFT                  (0U)
+#define LPTMR_CMR_COMPARE(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
+
+/*! @name CNR - Low Power Timer Counter Register */
+#define LPTMR_CNR_COUNTER_MASK                   (0xFFFFU)
+#define LPTMR_CNR_COUNTER_SHIFT                  (0U)
+#define LPTMR_CNR_COUNTER(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE                              (0x40040000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0                                   ((LPTMR_TypeDef *)LPTMR0_BASE)
+/** Array initializer of LPTMR peripheral base addresses */
+#define LPTMR_BASE_ADDRS                         { LPTMR0_BASE }
+/** Array initializer of LPTMR peripheral base pointers */
+#define LPTMR_BASE_PTRS                          { LPTMR0 }
+/** Interrupt vectors for the LPTMR peripheral type */
+#define LPTMR_IRQS                               { LPTMR0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
+ * @{
+ */
+
+/** MCG - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t C1;                                 /**< MCG Control 1 Register, offset: 0x0 */
+  __IO uint8_t C2;                                 /**< MCG Control 2 Register, offset: 0x1 */
+  __IO uint8_t C3;                                 /**< MCG Control 3 Register, offset: 0x2 */
+  __IO uint8_t C4;                                 /**< MCG Control 4 Register, offset: 0x3 */
+  __IO uint8_t C5;                                 /**< MCG Control 5 Register, offset: 0x4 */
+  __IO uint8_t C6;                                 /**< MCG Control 6 Register, offset: 0x5 */
+  __IO uint8_t S;                                  /**< MCG Status Register, offset: 0x6 */
+       uint8_t RESERVED_0[1];
+  __IO uint8_t SC;                                 /**< MCG Status and Control Register, offset: 0x8 */
+       uint8_t RESERVED_1[1];
+  __IO uint8_t ATCVH;                              /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
+  __IO uint8_t ATCVL;                              /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
+  __IO uint8_t C7;                                 /**< MCG Control 7 Register, offset: 0xC */
+  __IO uint8_t C8;                                 /**< MCG Control 8 Register, offset: 0xD */
+} MCG_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- MCG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Masks MCG Register Masks
+ * @{
+ */
+
+/*! @name C1 - MCG Control 1 Register */
+#define MCG_C1_IREFSTEN                          (0x1U)
+#define MCG_C1_IRCLKEN                           (0x2U)
+#define MCG_C1_IREFS                             (0x4U)
+#define MCG_C1_FRDIV_MASK                        (0x38U)
+#define MCG_C1_FRDIV_SHIFT                       (3U)
+#define MCG_C1_FRDIV(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
+#define MCG_C1_CLKS_MASK                         (0xC0U)
+#define MCG_C1_CLKS_SHIFT                        (6U)
+#define MCG_C1_CLKS(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
+
+/*! @name C2 - MCG Control 2 Register */
+#define MCG_C2_IRCS                              (0x1U)
+#define MCG_C2_LP                                (0x2U)
+#define MCG_C2_EREFS                             (0x4U)
+#define MCG_C2_EREFS0                            MCG_C2_EREFS
+#define MCG_C2_HGO                               (0x8U)
+#define MCG_C2_RANGE_MASK                        (0x30U)
+#define MCG_C2_RANGE_SHIFT                       (4U)
+#define MCG_C2_RANGE(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK)
+#define MCG_C2_FCFTRIM                           (0x40U)
+#define MCG_C2_LOCRE0                            (0x80U)
+
+/*! @name C3 - MCG Control 3 Register */
+#define MCG_C3_SCTRIM_MASK                       (0xFFU)
+#define MCG_C3_SCTRIM_SHIFT                      (0U)
+#define MCG_C3_SCTRIM(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
+
+/*! @name C4 - MCG Control 4 Register */
+#define MCG_C4_SCFTRIM                           (0x1U)
+#define MCG_C4_FCTRIM_MASK                       (0x1EU)
+#define MCG_C4_FCTRIM_SHIFT                      (1U)
+#define MCG_C4_FCTRIM(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
+#define MCG_C4_DRST_DRS_MASK                     (0x60U)
+#define MCG_C4_DRST_DRS_SHIFT                    (5U)
+#define MCG_C4_DRST_DRS(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
+#define MCG_C4_DMX32                             (0x80U)
+
+/*! @name C5 - MCG Control 5 Register */
+#define MCG_C5_PRDIV0_MASK                       (0x1FU)
+#define MCG_C5_PRDIV0_SHIFT                      (0U)
+#define MCG_C5_PRDIV0(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK)
+#define MCG_C5_PLLSTEN0                          (0x20U)
+#define MCG_C5_PLLCLKEN0                         (0x40U)
+
+/*! @name C6 - MCG Control 6 Register */
+#define MCG_C6_VDIV0_MASK                        (0x1FU)
+#define MCG_C6_VDIV0_SHIFT                       (0U)
+#define MCG_C6_VDIV0(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK)
+#define MCG_C6_CME0                              (0x20U)
+#define MCG_C6_PLLS                              (0x40U)
+#define MCG_C6_LOLIE0                            (0x80U)
+
+/*! @name S - MCG Status Register */
+#define MCG_S_IRCST                              (0x1U)
+#define MCG_S_OSCINIT0                           (0x2U)
+#define MCG_S_CLKST_MASK                         (0xCU)
+#define MCG_S_CLKST_SHIFT                        (2U)
+#define MCG_S_CLKST(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
+#define MCG_S_CLKST_FLL                          MCG_S_CLKST(0)
+#define MCG_S_CLKST_INT                          MCG_S_CLKST(1)
+#define MCG_S_CLKST_EXT                          MCG_S_CLKST(2)
+#define MCG_S_CLKST_PLL                          MCG_S_CLKST(3)
+#define MCG_S_IREFST                             (0x10U)
+#define MCG_S_PLLST                              (0x20U)
+#define MCG_S_LOCK0                              (0x40U)
+#define MCG_S_LOLS0                              (0x80U)
+
+/*! @name SC - MCG Status and Control Register */
+#define MCG_SC_LOCS0                             (0x1U)
+#define MCG_SC_FCRDIV_MASK                       (0xEU)
+#define MCG_SC_FCRDIV_SHIFT                      (1U)
+#define MCG_SC_FCRDIV(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
+#define MCG_SC_FLTPRSRV                          (0x10U)
+#define MCG_SC_ATMF                              (0x20U)
+#define MCG_SC_ATMS                              (0x40U)
+#define MCG_SC_ATME                              (0x80U)
+
+/*! @name ATCVH - MCG Auto Trim Compare Value High Register */
+#define MCG_ATCVH_ATCVH_MASK                     (0xFFU)
+#define MCG_ATCVH_ATCVH_SHIFT                    (0U)
+#define MCG_ATCVH_ATCVH(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
+
+/*! @name ATCVL - MCG Auto Trim Compare Value Low Register */
+#define MCG_ATCVL_ATCVL_MASK                     (0xFFU)
+#define MCG_ATCVL_ATCVL_SHIFT                    (0U)
+#define MCG_ATCVL_ATCVL(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
+
+/*! @name C7 - MCG Control 7 Register */
+#define MCG_C7_OSCSEL_MASK                       (0x3U)
+#define MCG_C7_OSCSEL_SHIFT                      (0U)
+#define MCG_C7_OSCSEL(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
+
+/*! @name C8 - MCG Control 8 Register */
+#define MCG_C8_LOCS1                             (0x1U)
+#define MCG_C8_CME1                              (0x20U)
+#define MCG_C8_LOLRE                             (0x40U)
+#define MCG_C8_LOCRE1                            (0x80U)
+
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Masks */
+
+
+/* MCG - Peripheral instance base addresses */
+/** Peripheral MCG base address */
+#define MCG_BASE                                 (0x40064000u)
+/** Peripheral MCG base pointer */
+#define MCG                                      ((MCG_TypeDef *)MCG_BASE)
+/** Array initializer of MCG peripheral base addresses */
+#define MCG_BASE_ADDRS                           { MCG_BASE }
+/** Array initializer of MCG peripheral base pointers */
+#define MCG_BASE_PTRS                            { MCG }
+
+/*!
+ * @}
+ */ /* end of group MCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
+ * @{
+ */
+
+/** MCM - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[8];
+  __I  uint16_t PLASC;                             /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
+  __I  uint16_t PLAMC;                             /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
+  __IO uint32_t CR;                                /**< Control Register, offset: 0xC */
+  __IO uint32_t ISCR;                              /**< Interrupt Status Register, offset: 0x10 */
+  __IO uint32_t ETBCC;                             /**< ETB Counter Control register, offset: 0x14 */
+  __IO uint32_t ETBRL;                             /**< ETB Reload register, offset: 0x18 */
+  __I  uint32_t ETBCNT;                            /**< ETB Counter Value register, offset: 0x1C */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t PID;                               /**< Process ID register, offset: 0x30 */
+} MCM_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- MCM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Masks MCM Register Masks
+ * @{
+ */
+
+/*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
+#define MCM_PLASC_ASC_MASK                       (0xFFU)
+#define MCM_PLASC_ASC_SHIFT                      (0U)
+#define MCM_PLASC_ASC(x)                         (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
+
+/*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
+#define MCM_PLAMC_AMC_MASK                       (0xFFU)
+#define MCM_PLAMC_AMC_SHIFT                      (0U)
+#define MCM_PLAMC_AMC(x)                         (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
+
+/*! @name CR - Control Register */
+#define MCM_CR_SRAMUAP_MASK                      (0x3000000U)
+#define MCM_CR_SRAMUAP_SHIFT                     (24U)
+#define MCM_CR_SRAMUAP(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUAP_SHIFT)) & MCM_CR_SRAMUAP_MASK)
+#define MCM_CR_SRAMUWP                           (0x4000000U)
+#define MCM_CR_SRAMLAP_MASK                      (0x30000000U)
+#define MCM_CR_SRAMLAP_SHIFT                     (28U)
+#define MCM_CR_SRAMLAP(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLAP_SHIFT)) & MCM_CR_SRAMLAP_MASK)
+#define MCM_CR_SRAMLWP                           (0x40000000U)
+
+/*! @name ISCR - Interrupt Status Register */
+#define MCM_ISCR_IRQ                             (0x2U)
+#define MCM_ISCR_NMI                             (0x4U)
+#define MCM_ISCR_DHREQ                           (0x8U)
+#define MCM_ISCR_FIOC                            (0x100U)
+#define MCM_ISCR_FDZC                            (0x200U)
+#define MCM_ISCR_FOFC                            (0x400U)
+#define MCM_ISCR_FUFC                            (0x800U)
+#define MCM_ISCR_FIXC                            (0x1000U)
+#define MCM_ISCR_FIDC                            (0x8000U)
+#define MCM_ISCR_FIOCE                           (0x1000000U)
+#define MCM_ISCR_FDZCE                           (0x2000000U)
+#define MCM_ISCR_FOFCE                           (0x4000000U)
+#define MCM_ISCR_FUFCE                           (0x8000000U)
+#define MCM_ISCR_FIXCE                           (0x10000000U)
+#define MCM_ISCR_FIDCE                           (0x80000000U)
+
+/*! @name ETBCC - ETB Counter Control register */
+#define MCM_ETBCC_CNTEN                          (0x1U)
+#define MCM_ETBCC_RSPT_MASK                      (0x6U)
+#define MCM_ETBCC_RSPT_SHIFT                     (1U)
+#define MCM_ETBCC_RSPT(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RSPT_SHIFT)) & MCM_ETBCC_RSPT_MASK)
+#define MCM_ETBCC_RLRQ                           (0x8U)
+#define MCM_ETBCC_ETDIS                          (0x10U)
+#define MCM_ETBCC_ITDIS                          (0x20U)
+
+/*! @name ETBRL - ETB Reload register */
+#define MCM_ETBRL_RELOAD_MASK                    (0x7FFU)
+#define MCM_ETBRL_RELOAD_SHIFT                   (0U)
+#define MCM_ETBRL_RELOAD(x)                      (((uint32_t)(((uint32_t)(x)) << MCM_ETBRL_RELOAD_SHIFT)) & MCM_ETBRL_RELOAD_MASK)
+
+/*! @name ETBCNT - ETB Counter Value register */
+#define MCM_ETBCNT_COUNTER_MASK                  (0x7FFU)
+#define MCM_ETBCNT_COUNTER_SHIFT                 (0U)
+#define MCM_ETBCNT_COUNTER(x)                    (((uint32_t)(((uint32_t)(x)) << MCM_ETBCNT_COUNTER_SHIFT)) & MCM_ETBCNT_COUNTER_MASK)
+
+/*! @name PID - Process ID register */
+#define MCM_PID_PID_MASK                         (0xFFU)
+#define MCM_PID_PID_SHIFT                        (0U)
+#define MCM_PID_PID(x)                           (((uint32_t)(((uint32_t)(x)) << MCM_PID_PID_SHIFT)) & MCM_PID_PID_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Masks */
+
+
+/* MCM - Peripheral instance base addresses */
+/** Peripheral MCM base address */
+#define MCM_BASE                                 (0xE0080000u)
+/** Peripheral MCM base pointer */
+#define MCM                                      ((MCM_TypeDef *)MCM_BASE)
+/** Array initializer of MCM peripheral base addresses */
+#define MCM_BASE_ADDRS                           { MCM_BASE }
+/** Array initializer of MCM peripheral base pointers */
+#define MCM_BASE_PTRS                            { MCM }
+/** Interrupt vectors for the MCM peripheral type */
+#define MCM_IRQS                                 { MCM_IRQn }
+
+/*!
+ * @}
+ */ /* end of group MCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MPU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Peripheral_Access_Layer MPU Peripheral Access Layer
+ * @{
+ */
+
+/** MPU - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CESR;                              /**< Control/Error Status Register, offset: 0x0 */
+       uint8_t RESERVED_0[12];
+  struct {                                         /* offset: 0x10, array step: 0x8 */
+    __I  uint32_t EAR;                               /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
+    __I  uint32_t EDR;                               /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
+  } SP[5];
+       uint8_t RESERVED_1[968];
+  __IO uint32_t WORD[12][4];                       /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
+       uint8_t RESERVED_2[832];
+  __IO uint32_t RGDAAC[12];                        /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
+} MPU_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- MPU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MPU_Register_Masks MPU Register Masks
+ * @{
+ */
+
+/*! @name CESR - Control/Error Status Register */
+#define MPU_CESR_VLD                             (0x1U)
+#define MPU_CESR_NRGD_MASK                       (0xF00U)
+#define MPU_CESR_NRGD_SHIFT                      (8U)
+#define MPU_CESR_NRGD(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_CESR_NRGD_SHIFT)) & MPU_CESR_NRGD_MASK)
+#define MPU_CESR_NSP_MASK                        (0xF000U)
+#define MPU_CESR_NSP_SHIFT                       (12U)
+#define MPU_CESR_NSP(x)                          (((uint32_t)(((uint32_t)(x)) << MPU_CESR_NSP_SHIFT)) & MPU_CESR_NSP_MASK)
+#define MPU_CESR_HRL_MASK                        (0xF0000U)
+#define MPU_CESR_HRL_SHIFT                       (16U)
+#define MPU_CESR_HRL(x)                          (((uint32_t)(((uint32_t)(x)) << MPU_CESR_HRL_SHIFT)) & MPU_CESR_HRL_MASK)
+#define MPU_CESR_SPERR_MASK                      (0xF8000000U)
+#define MPU_CESR_SPERR_SHIFT                     (27U)
+#define MPU_CESR_SPERR(x)                        (((uint32_t)(((uint32_t)(x)) << MPU_CESR_SPERR_SHIFT)) & MPU_CESR_SPERR_MASK)
+
+/* The count of MPU_EAR */
+#define MPU_EAR_COUNT                            (5U)
+
+/*! @name EDR - Error Detail Register, slave port n */
+#define MPU_EDR_ERW                              (0x1U)
+#define MPU_EDR_EATTR_MASK                       (0xEU)
+#define MPU_EDR_EATTR_SHIFT                      (1U)
+#define MPU_EDR_EATTR(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EATTR_SHIFT)) & MPU_EDR_EATTR_MASK)
+#define MPU_EDR_EMN_MASK                         (0xF0U)
+#define MPU_EDR_EMN_SHIFT                        (4U)
+#define MPU_EDR_EMN(x)                           (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EMN_SHIFT)) & MPU_EDR_EMN_MASK)
+#define MPU_EDR_EPID_MASK                        (0xFF00U)
+#define MPU_EDR_EPID_SHIFT                       (8U)
+#define MPU_EDR_EPID(x)                          (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EPID_SHIFT)) & MPU_EDR_EPID_MASK)
+#define MPU_EDR_EACD_MASK                        (0xFFFF0000U)
+#define MPU_EDR_EACD_SHIFT                       (16U)
+#define MPU_EDR_EACD(x)                          (((uint32_t)(((uint32_t)(x)) << MPU_EDR_EACD_SHIFT)) & MPU_EDR_EACD_MASK)
+
+/* The count of MPU_EDR */
+#define MPU_EDR_COUNT                            (5U)
+
+/*! @name WORD - Region Descriptor n, Word 0..Region Descriptor n, Word 3 */
+#define MPU_WORD_VLD                             (0x1U)
+#define MPU_WORD_M0UM_MASK                       (0x7U)
+#define MPU_WORD_M0UM_SHIFT                      (0U)
+#define MPU_WORD_M0UM(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0UM_SHIFT)) & MPU_WORD_M0UM_MASK)
+#define MPU_WORD_M0SM_MASK                       (0x18U)
+#define MPU_WORD_M0SM_SHIFT                      (3U)
+#define MPU_WORD_M0SM(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M0SM_SHIFT)) & MPU_WORD_M0SM_MASK)
+#define MPU_WORD_M0PE                            (0x20U)
+#define MPU_WORD_ENDADDR_MASK                    (0xFFFFFFE0U)
+#define MPU_WORD_ENDADDR_SHIFT                   (5U)
+#define MPU_WORD_ENDADDR(x)                      (((uint32_t)(((uint32_t)(x)) << MPU_WORD_ENDADDR_SHIFT)) & MPU_WORD_ENDADDR_MASK)
+#define MPU_WORD_SRTADDR_MASK                    (0xFFFFFFE0U)
+#define MPU_WORD_SRTADDR_SHIFT                   (5U)
+#define MPU_WORD_SRTADDR(x)                      (((uint32_t)(((uint32_t)(x)) << MPU_WORD_SRTADDR_SHIFT)) & MPU_WORD_SRTADDR_MASK)
+#define MPU_WORD_M1UM_MASK                       (0x1C0U)
+#define MPU_WORD_M1UM_SHIFT                      (6U)
+#define MPU_WORD_M1UM(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1UM_SHIFT)) & MPU_WORD_M1UM_MASK)
+#define MPU_WORD_M1SM_MASK                       (0x600U)
+#define MPU_WORD_M1SM_SHIFT                      (9U)
+#define MPU_WORD_M1SM(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M1SM_SHIFT)) & MPU_WORD_M1SM_MASK)
+#define MPU_WORD_M1PE                            (0x800U)
+#define MPU_WORD_M2UM_MASK                       (0x7000U)
+#define MPU_WORD_M2UM_SHIFT                      (12U)
+#define MPU_WORD_M2UM(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2UM_SHIFT)) & MPU_WORD_M2UM_MASK)
+#define MPU_WORD_M2SM_MASK                       (0x18000U)
+#define MPU_WORD_M2SM_SHIFT                      (15U)
+#define MPU_WORD_M2SM(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M2SM_SHIFT)) & MPU_WORD_M2SM_MASK)
+#define MPU_WORD_PIDMASK_MASK                    (0xFF0000U)
+#define MPU_WORD_PIDMASK_SHIFT                   (16U)
+#define MPU_WORD_PIDMASK(x)                      (((uint32_t)(((uint32_t)(x)) << MPU_WORD_PIDMASK_SHIFT)) & MPU_WORD_PIDMASK_MASK)
+#define MPU_WORD_M2PE                            (0x20000U)
+#define MPU_WORD_M3UM_MASK                       (0x1C0000U)
+#define MPU_WORD_M3UM_SHIFT                      (18U)
+#define MPU_WORD_M3UM(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3UM_SHIFT)) & MPU_WORD_M3UM_MASK)
+#define MPU_WORD_M3SM_MASK                       (0x600000U)
+#define MPU_WORD_M3SM_SHIFT                      (21U)
+#define MPU_WORD_M3SM(x)                         (((uint32_t)(((uint32_t)(x)) << MPU_WORD_M3SM_SHIFT)) & MPU_WORD_M3SM_MASK)
+#define MPU_WORD_M3PE                            (0x800000U)
+#define MPU_WORD_PID_MASK                        (0xFF000000U)
+#define MPU_WORD_PID_SHIFT                       (24U)
+#define MPU_WORD_PID(x)                          (((uint32_t)(((uint32_t)(x)) << MPU_WORD_PID_SHIFT)) & MPU_WORD_PID_MASK)
+#define MPU_WORD_M4WE                            (0x1000000U)
+#define MPU_WORD_M4RE                            (0x2000000U)
+#define MPU_WORD_M5WE                            (0x4000000U)
+#define MPU_WORD_M5RE                            (0x8000000U)
+#define MPU_WORD_M6WE                            (0x10000000U)
+#define MPU_WORD_M6RE                            (0x20000000U)
+#define MPU_WORD_M7WE                            (0x40000000U)
+#define MPU_WORD_M7RE                            (0x80000000U)
+
+/* The count of MPU_WORD */
+#define MPU_WORD_COUNT                           (12U)
+
+/* The count of MPU_WORD */
+#define MPU_WORD_COUNT2                          (4U)
+
+/*! @name RGDAAC - Region Descriptor Alternate Access Control n */
+#define MPU_RGDAAC_M0UM_MASK                     (0x7U)
+#define MPU_RGDAAC_M0UM_SHIFT                    (0U)
+#define MPU_RGDAAC_M0UM(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0UM_SHIFT)) & MPU_RGDAAC_M0UM_MASK)
+#define MPU_RGDAAC_M0SM_MASK                     (0x18U)
+#define MPU_RGDAAC_M0SM_SHIFT                    (3U)
+#define MPU_RGDAAC_M0SM(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M0SM_SHIFT)) & MPU_RGDAAC_M0SM_MASK)
+#define MPU_RGDAAC_M0PE                          (0x20U)
+#define MPU_RGDAAC_M1UM_MASK                     (0x1C0U)
+#define MPU_RGDAAC_M1UM_SHIFT                    (6U)
+#define MPU_RGDAAC_M1UM(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1UM_SHIFT)) & MPU_RGDAAC_M1UM_MASK)
+#define MPU_RGDAAC_M1SM_MASK                     (0x600U)
+#define MPU_RGDAAC_M1SM_SHIFT                    (9U)
+#define MPU_RGDAAC_M1SM(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M1SM_SHIFT)) & MPU_RGDAAC_M1SM_MASK)
+#define MPU_RGDAAC_M1PE                          (0x800U)
+#define MPU_RGDAAC_M2UM_MASK                     (0x7000U)
+#define MPU_RGDAAC_M2UM_SHIFT                    (12U)
+#define MPU_RGDAAC_M2UM(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2UM_SHIFT)) & MPU_RGDAAC_M2UM_MASK)
+#define MPU_RGDAAC_M2SM_MASK                     (0x18000U)
+#define MPU_RGDAAC_M2SM_SHIFT                    (15U)
+#define MPU_RGDAAC_M2SM(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M2SM_SHIFT)) & MPU_RGDAAC_M2SM_MASK)
+#define MPU_RGDAAC_M2PE                          (0x20000U)
+#define MPU_RGDAAC_M3UM_MASK                     (0x1C0000U)
+#define MPU_RGDAAC_M3UM_SHIFT                    (18U)
+#define MPU_RGDAAC_M3UM(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3UM_SHIFT)) & MPU_RGDAAC_M3UM_MASK)
+#define MPU_RGDAAC_M3SM_MASK                     (0x600000U)
+#define MPU_RGDAAC_M3SM_SHIFT                    (21U)
+#define MPU_RGDAAC_M3SM(x)                       (((uint32_t)(((uint32_t)(x)) << MPU_RGDAAC_M3SM_SHIFT)) & MPU_RGDAAC_M3SM_MASK)
+#define MPU_RGDAAC_M3PE                          (0x800000U)
+#define MPU_RGDAAC_M4WE                          (0x1000000U)
+#define MPU_RGDAAC_M4RE                          (0x2000000U)
+#define MPU_RGDAAC_M5WE                          (0x4000000U)
+#define MPU_RGDAAC_M5RE                          (0x8000000U)
+#define MPU_RGDAAC_M6WE                          (0x10000000U)
+#define MPU_RGDAAC_M6RE                          (0x20000000U)
+#define MPU_RGDAAC_M7WE                          (0x40000000U)
+#define MPU_RGDAAC_M7RE                          (0x80000000U)
+
+/* The count of MPU_RGDAAC */
+#define MPU_RGDAAC_COUNT                         (12U)
+
+
+/*!
+ * @}
+ */ /* end of group MPU_Register_Masks */
+
+
+/* MPU - Peripheral instance base addresses */
+/** Peripheral MPU base address */
+#define MPU_BASE                                 (0x4000D000u)
+/** Peripheral MPU base pointer */
+#define MPU                                      ((MPU_TypeDef *)MPU_BASE)
+/** Array initializer of MPU peripheral base addresses */
+#define MPU_BASE_ADDRS                           { MPU_BASE }
+/** Array initializer of MPU peripheral base pointers */
+#define MPU_BASE_PTRS                            { MPU }
+
+/*!
+ * @}
+ */ /* end of group MPU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- NV Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
+ * @{
+ */
+
+/** NV - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t BACKKEY3;                           /**< Backdoor Comparison Key 3., offset: 0x0 */
+  __I  uint8_t BACKKEY2;                           /**< Backdoor Comparison Key 2., offset: 0x1 */
+  __I  uint8_t BACKKEY1;                           /**< Backdoor Comparison Key 1., offset: 0x2 */
+  __I  uint8_t BACKKEY0;                           /**< Backdoor Comparison Key 0., offset: 0x3 */
+  __I  uint8_t BACKKEY7;                           /**< Backdoor Comparison Key 7., offset: 0x4 */
+  __I  uint8_t BACKKEY6;                           /**< Backdoor Comparison Key 6., offset: 0x5 */
+  __I  uint8_t BACKKEY5;                           /**< Backdoor Comparison Key 5., offset: 0x6 */
+  __I  uint8_t BACKKEY4;                           /**< Backdoor Comparison Key 4., offset: 0x7 */
+  __I  uint8_t FPROT3;                             /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
+  __I  uint8_t FPROT2;                             /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
+  __I  uint8_t FPROT1;                             /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
+  __I  uint8_t FPROT0;                             /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
+  __I  uint8_t FSEC;                               /**< Non-volatile Flash Security Register, offset: 0xC */
+  __I  uint8_t FOPT;                               /**< Non-volatile Flash Option Register, offset: 0xD */
+  __I  uint8_t FEPROT;                             /**< Non-volatile EERAM Protection Register, offset: 0xE */
+  __I  uint8_t FDPROT;                             /**< Non-volatile D-Flash Protection Register, offset: 0xF */
+} NV_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- NV Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/*! @name FSEC - Non-volatile Flash Security Register */
+#define NV_FSEC_SEC_MASK                         (0x3U)
+#define NV_FSEC_SEC_SHIFT                        (0U)
+#define NV_FSEC_SEC(x)                           (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK                      (0xCU)
+#define NV_FSEC_FSLACC_SHIFT                     (2U)
+#define NV_FSEC_FSLACC(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK                        (0x30U)
+#define NV_FSEC_MEEN_SHIFT                       (4U)
+#define NV_FSEC_MEEN(x)                          (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK                       (0xC0U)
+#define NV_FSEC_KEYEN_SHIFT                      (6U)
+#define NV_FSEC_KEYEN(x)                         (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
+
+/*! @name FOPT - Non-volatile Flash Option Register */
+#define NV_FOPT_LPBOOT                           (0x1U)
+#define NV_FOPT_EZPORT_DIS                       (0x2U)
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/** Peripheral FTFE_FlashConfig base address */
+#define FTFE_FlashConfig_BASE                    (0x400u)
+/** Peripheral FTFE_FlashConfig base pointer */
+#define FTFE_FlashConfig                         ((NV_TypeDef *)FTFE_FlashConfig_BASE)
+/** Array initializer of NV peripheral base addresses */
+#define NV_BASE_ADDRS                            { FTFE_FlashConfig_BASE }
+/** Array initializer of NV peripheral base pointers */
+#define NV_BASE_PTRS                             { FTFE_FlashConfig }
+
+/*!
+ * @}
+ */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- OSC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
+ * @{
+ */
+
+/** OSC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CR;                                 /**< OSC Control Register, offset: 0x0 */
+} OSC_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- OSC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/*! @name CR - OSC Control Register */
+#define OSC_CR_SC16P                             (0x1U)
+#define OSC_CR_SC8P                              (0x2U)
+#define OSC_CR_SC4P                              (0x4U)
+#define OSC_CR_SC2P                              (0x8U)
+#define OSC_CR_EREFSTEN                          (0x20U)
+#define OSC_CR_ERCLKEN                           (0x80U)
+
+
+/*!
+ * @}
+ */ /* end of group OSC_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC base address */
+#define OSC_BASE                                 (0x40065000u)
+#define OSC0_BASE                                OSC_BASE
+/** Peripheral OSC base pointer */
+#define OSC                                      ((OSC_TypeDef *)OSC_BASE)
+#define OSC0                                     OSC
+/** Array initializer of OSC peripheral base addresses */
+#define OSC_BASE_ADDRS                           { OSC_BASE }
+/** Array initializer of OSC peripheral base pointers */
+#define OSC_BASE_PTRS                            { OSC }
+
+/*!
+ * @}
+ */ /* end of group OSC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PDB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
+ * @{
+ */
+
+/** PDB - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC;                                /**< Status and Control register, offset: 0x0 */
+  __IO uint32_t MOD;                               /**< Modulus register, offset: 0x4 */
+  __I  uint32_t CNT;                               /**< Counter register, offset: 0x8 */
+  __IO uint32_t IDLY;                              /**< Interrupt Delay register, offset: 0xC */
+  struct {                                         /* offset: 0x10, array step: 0x28 */
+    __IO uint32_t C1;                                /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
+    __IO uint32_t S;                                 /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
+    __IO uint32_t DLY[2];                            /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
+         uint8_t RESERVED_0[24];
+  } CH[2];
+       uint8_t RESERVED_0[240];
+  struct {                                         /* offset: 0x150, array step: 0x8 */
+    __IO uint32_t INTC;                              /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
+    __IO uint32_t INT;                               /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
+  } DAC[2];
+       uint8_t RESERVED_1[48];
+  __IO uint32_t POEN;                              /**< Pulse-Out n Enable register, offset: 0x190 */
+  __IO uint32_t PODLY[3];                          /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
+} PDB_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- PDB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Masks PDB Register Masks
+ * @{
+ */
+
+/*! @name SC - Status and Control register */
+#define PDB_SC_LDOK                              (0x1U)
+#define PDB_SC_CONT                              (0x2U)
+#define PDB_SC_MULT_MASK                         (0xCU)
+#define PDB_SC_MULT_SHIFT                        (2U)
+#define PDB_SC_MULT(x)                           (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK)
+#define PDB_SC_PDBIE                             (0x20U)
+#define PDB_SC_PDBIF                             (0x40U)
+#define PDB_SC_PDBEN                             (0x80U)
+#define PDB_SC_TRGSEL_MASK                       (0xF00U)
+#define PDB_SC_TRGSEL_SHIFT                      (8U)
+#define PDB_SC_TRGSEL(x)                         (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK)
+#define PDB_SC_PRESCALER_MASK                    (0x7000U)
+#define PDB_SC_PRESCALER_SHIFT                   (12U)
+#define PDB_SC_PRESCALER(x)                      (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK)
+#define PDB_SC_DMAEN                             (0x8000U)
+#define PDB_SC_SWTRIG                            (0x10000U)
+#define PDB_SC_PDBEIE                            (0x20000U)
+#define PDB_SC_LDMOD_MASK                        (0xC0000U)
+#define PDB_SC_LDMOD_SHIFT                       (18U)
+#define PDB_SC_LDMOD(x)                          (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK)
+
+/*! @name MOD - Modulus register */
+#define PDB_MOD_MOD_MASK                         (0xFFFFU)
+#define PDB_MOD_MOD_SHIFT                        (0U)
+#define PDB_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK)
+
+/*! @name CNT - Counter register */
+#define PDB_CNT_CNT_MASK                         (0xFFFFU)
+#define PDB_CNT_CNT_SHIFT                        (0U)
+#define PDB_CNT_CNT(x)                           (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK)
+
+/*! @name IDLY - Interrupt Delay register */
+#define PDB_IDLY_IDLY_MASK                       (0xFFFFU)
+#define PDB_IDLY_IDLY_SHIFT                      (0U)
+#define PDB_IDLY_IDLY(x)                         (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK)
+
+/*! @name C1 - Channel n Control register 1 */
+#define PDB_C1_EN_MASK                           (0xFFU)
+#define PDB_C1_EN_SHIFT                          (0U)
+#define PDB_C1_EN(x)                             (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK)
+#define PDB_C1_TOS_MASK                          (0xFF00U)
+#define PDB_C1_TOS_SHIFT                         (8U)
+#define PDB_C1_TOS(x)                            (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK)
+#define PDB_C1_BB_MASK                           (0xFF0000U)
+#define PDB_C1_BB_SHIFT                          (16U)
+#define PDB_C1_BB(x)                             (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK)
+
+/* The count of PDB_C1 */
+#define PDB_C1_COUNT                             (2U)
+
+/*! @name S - Channel n Status register */
+#define PDB_S_ERR_MASK                           (0xFFU)
+#define PDB_S_ERR_SHIFT                          (0U)
+#define PDB_S_ERR(x)                             (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK)
+#define PDB_S_CF_MASK                            (0xFF0000U)
+#define PDB_S_CF_SHIFT                           (16U)
+#define PDB_S_CF(x)                              (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK)
+
+/* The count of PDB_S */
+#define PDB_S_COUNT                              (2U)
+
+/*! @name DLY - Channel n Delay 0 register..Channel n Delay 1 register */
+#define PDB_DLY_DLY_MASK                         (0xFFFFU)
+#define PDB_DLY_DLY_SHIFT                        (0U)
+#define PDB_DLY_DLY(x)                           (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK)
+
+/* The count of PDB_DLY */
+#define PDB_DLY_COUNT                            (2U)
+
+/* The count of PDB_DLY */
+#define PDB_DLY_COUNT2                           (2U)
+
+/*! @name INTC - DAC Interval Trigger n Control register */
+#define PDB_INTC_TOE                             (0x1U)
+#define PDB_INTC_EXT                             (0x2U)
+
+/* The count of PDB_INTC */
+#define PDB_INTC_COUNT                           (2U)
+
+/*! @name INT - DAC Interval n register */
+#define PDB_INT_INT_MASK                         (0xFFFFU)
+#define PDB_INT_INT_SHIFT                        (0U)
+#define PDB_INT_INT(x)                           (((uint32_t)(((uint32_t)(x)) << PDB_INT_INT_SHIFT)) & PDB_INT_INT_MASK)
+
+/* The count of PDB_INT */
+#define PDB_INT_COUNT                            (2U)
+
+/*! @name POEN - Pulse-Out n Enable register */
+#define PDB_POEN_POEN_MASK                       (0xFFU)
+#define PDB_POEN_POEN_SHIFT                      (0U)
+#define PDB_POEN_POEN(x)                         (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK)
+
+/*! @name PODLY - Pulse-Out n Delay register */
+#define PDB_PODLY_DLY2_MASK                      (0xFFFFU)
+#define PDB_PODLY_DLY2_SHIFT                     (0U)
+#define PDB_PODLY_DLY2(x)                        (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK)
+#define PDB_PODLY_DLY1_MASK                      (0xFFFF0000U)
+#define PDB_PODLY_DLY1_SHIFT                     (16U)
+#define PDB_PODLY_DLY1(x)                        (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK)
+
+/* The count of PDB_PODLY */
+#define PDB_PODLY_COUNT                          (3U)
+
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Masks */
+
+
+/* PDB - Peripheral instance base addresses */
+/** Peripheral PDB0 base address */
+#define PDB0_BASE                                (0x40036000u)
+/** Peripheral PDB0 base pointer */
+#define PDB0                                     ((PDB_TypeDef *)PDB0_BASE)
+/** Array initializer of PDB peripheral base addresses */
+#define PDB_BASE_ADDRS                           { PDB0_BASE }
+/** Array initializer of PDB peripheral base pointers */
+#define PDB_BASE_PTRS                            { PDB0 }
+/** Interrupt vectors for the PDB peripheral type */
+#define PDB_IRQS                                 { PDB0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group PDB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PIT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
+ * @{
+ */
+
+/** PIT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< PIT Module Control Register, offset: 0x0 */
+       uint8_t RESERVED_0[252];
+  struct {                                         /* offset: 0x100, array step: 0x10 */
+    __IO uint32_t LDVAL;                             /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
+    __I  uint32_t CVAL;                              /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
+    __IO uint32_t TCTRL;                             /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
+    __IO uint32_t TFLG;                              /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
+  } CHANNEL[4];
+} PIT_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- PIT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/*! @name MCR - PIT Module Control Register */
+#define PIT_MCR_FRZ                              (0x1U)
+#define PIT_MCR_MDIS                             (0x2U)
+
+/* The count of PIT_LDVAL */
+#define PIT_LDVAL_COUNT                          (4U)
+
+/* The count of PIT_CVAL */
+#define PIT_CVAL_COUNT                           (4U)
+
+/*! @name TCTRL - Timer Control Register */
+#define PIT_TCTRL_TEN                            (0x1U)
+#define PIT_TCTRL_TIE                            (0x2U)
+#define PIT_TCTRL_CHN                            (0x4U)
+
+/* The count of PIT_TCTRL */
+#define PIT_TCTRL_COUNT                          (4U)
+
+/*! @name TFLG - Timer Flag Register */
+#define PIT_TFLG_TIF                             (0x1U)
+
+/* The count of PIT_TFLG */
+#define PIT_TFLG_COUNT                           (4U)
+
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/** Peripheral PIT base address */
+#define PIT_BASE                                 (0x40037000u)
+/** Peripheral PIT base pointer */
+#define PIT                                      ((PIT_TypeDef *)PIT_BASE)
+/** Array initializer of PIT peripheral base addresses */
+#define PIT_BASE_ADDRS                           { PIT_BASE }
+/** Array initializer of PIT peripheral base pointers */
+#define PIT_BASE_PTRS                            { PIT }
+/** Interrupt vectors for the PIT peripheral type */
+#define PIT_IRQS                                 { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn }
+
+/*!
+ * @}
+ */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t LVDSC1;                             /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
+  __IO uint8_t LVDSC2;                             /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
+  __IO uint8_t REGSC;                              /**< Regulator Status And Control register, offset: 0x2 */
+} PMC_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- PMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */
+#define PMC_LVDSC1_LVDV_MASK                     (0x3U)
+#define PMC_LVDSC1_LVDV_SHIFT                    (0U)
+#define PMC_LVDSC1_LVDV(x)                       (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE                         (0x10U)
+#define PMC_LVDSC1_LVDIE                         (0x20U)
+#define PMC_LVDSC1_LVDACK                        (0x40U)
+#define PMC_LVDSC1_LVDF                          (0x80U)
+
+/*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */
+#define PMC_LVDSC2_LVWV_MASK                     (0x3U)
+#define PMC_LVDSC2_LVWV_SHIFT                    (0U)
+#define PMC_LVDSC2_LVWV(x)                       (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE                         (0x20U)
+#define PMC_LVDSC2_LVWACK                        (0x40U)
+#define PMC_LVDSC2_LVWF                          (0x80U)
+
+/*! @name REGSC - Regulator Status And Control register */
+#define PMC_REGSC_BGBE                           (0x1U)
+#define PMC_REGSC_REGONS                         (0x4U)
+#define PMC_REGSC_ACKISO                         (0x8U)
+#define PMC_REGSC_BGEN                           (0x10U)
+
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/** Peripheral PMC base address */
+#define PMC_BASE                                 (0x4007D000u)
+/** Peripheral PMC base pointer */
+#define PMC                                      ((PMC_TypeDef *)PMC_BASE)
+/** Array initializer of PMC peripheral base addresses */
+#define PMC_BASE_ADDRS                           { PMC_BASE }
+/** Array initializer of PMC peripheral base pointers */
+#define PMC_BASE_PTRS                            { PMC }
+/** Interrupt vectors for the PMC peripheral type */
+#define PMC_IRQS                                 { LVD_LVW_IRQn }
+
+/*!
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PORT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PCR[32];                           /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
+  __O  uint32_t GPCLR;                             /**< Global Pin Control Low Register, offset: 0x80 */
+  __O  uint32_t GPCHR;                             /**< Global Pin Control High Register, offset: 0x84 */
+       uint8_t RESERVED_0[24];
+  __IO uint32_t ISFR;                              /**< Interrupt Status Flag Register, offset: 0xA0 */
+       uint8_t RESERVED_1[28];
+  __IO uint32_t DFER;                              /**< Digital Filter Enable Register, offset: 0xC0 */
+  __IO uint32_t DFCR;                              /**< Digital Filter Clock Register, offset: 0xC4 */
+  __IO uint32_t DFWR;                              /**< Digital Filter Width Register, offset: 0xC8 */
+} PORT_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- PORT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/*! @name PCR - Pin Control Register n */
+#define PORTx_PCRn_PS                           (0x1U)
+#define PORTx_PCRn_PE                           (0x2U)
+#define PORTx_PCRn_SRE                          (0x4U)
+#define PORTx_PCRn_PFE                          (0x10U)
+#define PORTx_PCRn_ODE                          (0x20U)
+#define PORTx_PCRn_DSE                          (0x40U)
+#define PORTx_PCRn_MUX_MASK                     (0x700U)
+#define PORTx_PCRn_MUX_SHIFT                    (8U)
+#define PORTx_PCRn_MUX(x)                       (((uint32_t)(((uint32_t)(x)) << PORTx_PCRn_MUX_SHIFT)) & PORTx_PCRn_MUX_MASK)
+#define PORTx_PCRn_LK                           (0x8000U)
+#define PORTx_PCRn_IRQC_MASK                    (0xF0000U)
+#define PORTx_PCRn_IRQC_SHIFT                   (16U)
+#define PORTx_PCRn_IRQC(x)                      (((uint32_t)(((uint32_t)(x)) << PORTx_PCRn_IRQC_SHIFT)) & PORTx_PCRn_IRQC_MASK)
+#define PORTx_PCRn_ISF                          (0x1000000U)
+
+/* The count of PORT_PCR */
+#define PORT_PCR_COUNT                           (32U)
+
+/*! @name GPCLR - Global Pin Control Low Register */
+#define PORT_GPCLR_GPWD_MASK                     (0xFFFFU)
+#define PORT_GPCLR_GPWD_SHIFT                    (0U)
+#define PORT_GPCLR_GPWD(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK                     (0xFFFF0000U)
+#define PORT_GPCLR_GPWE_SHIFT                    (16U)
+#define PORT_GPCLR_GPWE(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
+
+/*! @name GPCHR - Global Pin Control High Register */
+#define PORT_GPCHR_GPWD_MASK                     (0xFFFFU)
+#define PORT_GPCHR_GPWD_SHIFT                    (0U)
+#define PORT_GPCHR_GPWD(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK                     (0xFFFF0000U)
+#define PORT_GPCHR_GPWE_SHIFT                    (16U)
+#define PORT_GPCHR_GPWE(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
+
+/*! @name DFCR - Digital Filter Clock Register */
+#define PORT_DFCR_CS                             (0x1U)
+
+/*! @name DFWR - Digital Filter Width Register */
+#define PORT_DFWR_FILT_MASK                      (0x1FU)
+#define PORT_DFWR_FILT_SHIFT                     (0U)
+#define PORT_DFWR_FILT(x)                        (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE                               (0x40049000u)
+/** Peripheral PORTA base pointer */
+#define PORTA                                    ((PORT_TypeDef *)PORTA_BASE)
+/** Peripheral PORTB base address */
+#define PORTB_BASE                               (0x4004A000u)
+/** Peripheral PORTB base pointer */
+#define PORTB                                    ((PORT_TypeDef *)PORTB_BASE)
+/** Peripheral PORTC base address */
+#define PORTC_BASE                               (0x4004B000u)
+/** Peripheral PORTC base pointer */
+#define PORTC                                    ((PORT_TypeDef *)PORTC_BASE)
+/** Peripheral PORTD base address */
+#define PORTD_BASE                               (0x4004C000u)
+/** Peripheral PORTD base pointer */
+#define PORTD                                    ((PORT_TypeDef *)PORTD_BASE)
+/** Peripheral PORTE base address */
+#define PORTE_BASE                               (0x4004D000u)
+/** Peripheral PORTE base pointer */
+#define PORTE                                    ((PORT_TypeDef *)PORTE_BASE)
+/** Array initializer of PORT peripheral base addresses */
+#define PORT_BASE_ADDRS                          { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
+/** Array initializer of PORT peripheral base pointers */
+#define PORT_BASE_PTRS                           { PORTA, PORTB, PORTC, PORTD, PORTE }
+/** Interrupt vectors for the PORT peripheral type */
+#define PORT_IRQS                                { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
+
+/*!
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RCM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
+ * @{
+ */
+
+/** RCM - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t SRS0;                               /**< System Reset Status Register 0, offset: 0x0 */
+  __I  uint8_t SRS1;                               /**< System Reset Status Register 1, offset: 0x1 */
+       uint8_t RESERVED_0[2];
+  __IO uint8_t RPFC;                               /**< Reset Pin Filter Control register, offset: 0x4 */
+  __IO uint8_t RPFW;                               /**< Reset Pin Filter Width register, offset: 0x5 */
+       uint8_t RESERVED_1[1];
+  __I  uint8_t MR;                                 /**< Mode Register, offset: 0x7 */
+} RCM_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- RCM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Masks RCM Register Masks
+ * @{
+ */
+
+/*! @name SRS0 - System Reset Status Register 0 */
+#define RCM_SRS0_WAKEUP                          (0x1U)
+#define RCM_SRS0_LVD                             (0x2U)
+#define RCM_SRS0_LOC                             (0x4U)
+#define RCM_SRS0_LOL                             (0x8U)
+#define RCM_SRS0_WDOG                            (0x20U)
+#define RCM_SRS0_PIN                             (0x40U)
+#define RCM_SRS0_POR                             (0x80U)
+
+/*! @name SRS1 - System Reset Status Register 1 */
+#define RCM_SRS1_JTAG                            (0x1U)
+#define RCM_SRS1_LOCKUP                          (0x2U)
+#define RCM_SRS1_SW                              (0x4U)
+#define RCM_SRS1_MDM_AP                          (0x8U)
+#define RCM_SRS1_EZPT                            (0x10U)
+#define RCM_SRS1_SACKERR                         (0x20U)
+
+/*! @name RPFC - Reset Pin Filter Control register */
+#define RCM_RPFC_RSTFLTSRW_MASK                  (0x3U)
+#define RCM_RPFC_RSTFLTSRW_SHIFT                 (0U)
+#define RCM_RPFC_RSTFLTSRW(x)                    (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS                        (0x4U)
+
+/*! @name RPFW - Reset Pin Filter Width register */
+#define RCM_RPFW_RSTFLTSEL_MASK                  (0x1FU)
+#define RCM_RPFW_RSTFLTSEL_SHIFT                 (0U)
+#define RCM_RPFW_RSTFLTSEL(x)                    (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
+
+/*! @name MR - Mode Register */
+#define RCM_MR_EZP_MS                            (0x2U)
+
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Masks */
+
+
+/* RCM - Peripheral instance base addresses */
+/** Peripheral RCM base address */
+#define RCM_BASE                                 (0x4007F000u)
+/** Peripheral RCM base pointer */
+#define RCM                                      ((RCM_TypeDef *)RCM_BASE)
+/** Array initializer of RCM peripheral base addresses */
+#define RCM_BASE_ADDRS                           { RCM_BASE }
+/** Array initializer of RCM peripheral base pointers */
+#define RCM_BASE_PTRS                            { RCM }
+
+/*!
+ * @}
+ */ /* end of group RCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
+ * @{
+ */
+
+/** RFSYS - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t REG[8];                            /**< Register file register, array offset: 0x0, array step: 0x4 */
+} RFSYS_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
+ * @{
+ */
+
+/*! @name REG - Register file register */
+#define RFSYS_REG_LL_MASK                        (0xFFU)
+#define RFSYS_REG_LL_SHIFT                       (0U)
+#define RFSYS_REG_LL(x)                          (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
+#define RFSYS_REG_LH_MASK                        (0xFF00U)
+#define RFSYS_REG_LH_SHIFT                       (8U)
+#define RFSYS_REG_LH(x)                          (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
+#define RFSYS_REG_HL_MASK                        (0xFF0000U)
+#define RFSYS_REG_HL_SHIFT                       (16U)
+#define RFSYS_REG_HL(x)                          (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
+#define RFSYS_REG_HH_MASK                        (0xFF000000U)
+#define RFSYS_REG_HH_SHIFT                       (24U)
+#define RFSYS_REG_HH(x)                          (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
+
+/* The count of RFSYS_REG */
+#define RFSYS_REG_COUNT                          (8U)
+
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Masks */
+
+
+/* RFSYS - Peripheral instance base addresses */
+/** Peripheral RFSYS base address */
+#define RFSYS_BASE                               (0x40041000u)
+/** Peripheral RFSYS base pointer */
+#define RFSYS                                    ((RFSYS_TypeDef *)RFSYS_BASE)
+/** Array initializer of RFSYS peripheral base addresses */
+#define RFSYS_BASE_ADDRS                         { RFSYS_BASE }
+/** Array initializer of RFSYS peripheral base pointers */
+#define RFSYS_BASE_PTRS                          { RFSYS }
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFVBAT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
+ * @{
+ */
+
+/** RFVBAT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t REG[8];                            /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
+} RFVBAT_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- RFVBAT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
+ * @{
+ */
+
+/*! @name REG - VBAT register file register */
+#define RFVBAT_REG_LL_MASK                       (0xFFU)
+#define RFVBAT_REG_LL_SHIFT                      (0U)
+#define RFVBAT_REG_LL(x)                         (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LL_SHIFT)) & RFVBAT_REG_LL_MASK)
+#define RFVBAT_REG_LH_MASK                       (0xFF00U)
+#define RFVBAT_REG_LH_SHIFT                      (8U)
+#define RFVBAT_REG_LH(x)                         (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LH_SHIFT)) & RFVBAT_REG_LH_MASK)
+#define RFVBAT_REG_HL_MASK                       (0xFF0000U)
+#define RFVBAT_REG_HL_SHIFT                      (16U)
+#define RFVBAT_REG_HL(x)                         (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HL_SHIFT)) & RFVBAT_REG_HL_MASK)
+#define RFVBAT_REG_HH_MASK                       (0xFF000000U)
+#define RFVBAT_REG_HH_SHIFT                      (24U)
+#define RFVBAT_REG_HH(x)                         (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HH_SHIFT)) & RFVBAT_REG_HH_MASK)
+
+/* The count of RFVBAT_REG */
+#define RFVBAT_REG_COUNT                         (8U)
+
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Masks */
+
+
+/* RFVBAT - Peripheral instance base addresses */
+/** Peripheral RFVBAT base address */
+#define RFVBAT_BASE                              (0x4003E000u)
+/** Peripheral RFVBAT base pointer */
+#define RFVBAT                                   ((RFVBAT_TypeDef *)RFVBAT_BASE)
+/** Array initializer of RFVBAT peripheral base addresses */
+#define RFVBAT_BASE_ADDRS                        { RFVBAT_BASE }
+/** Array initializer of RFVBAT peripheral base pointers */
+#define RFVBAT_BASE_PTRS                         { RFVBAT }
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RNG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
+ * @{
+ */
+
+/** RNG - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CR;                                /**< RNGA Control Register, offset: 0x0 */
+  __I  uint32_t SR;                                /**< RNGA Status Register, offset: 0x4 */
+  __O  uint32_t ER;                                /**< RNGA Entropy Register, offset: 0x8 */
+  __I  uint32_t OR;                                /**< RNGA Output Register, offset: 0xC */
+} RNG_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- RNG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Masks RNG Register Masks
+ * @{
+ */
+
+/*! @name CR - RNGA Control Register */
+#define RNG_CR_GO                                (0x1U)
+#define RNG_CR_HA                                (0x2U)
+#define RNG_CR_INTM                              (0x4U)
+#define RNG_CR_CLRI                              (0x8U)
+#define RNG_CR_SLP                               (0x10U)
+
+/*! @name SR - RNGA Status Register */
+#define RNG_SR_SECV                              (0x1U)
+#define RNG_SR_LRS                               (0x2U)
+#define RNG_SR_ORU                               (0x4U)
+#define RNG_SR_ERRI                              (0x8U)
+#define RNG_SR_SLP                               (0x10U)
+#define RNG_SR_OREG_LVL_MASK                     (0xFF00U)
+#define RNG_SR_OREG_LVL_SHIFT                    (8U)
+#define RNG_SR_OREG_LVL(x)                       (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_LVL_SHIFT)) & RNG_SR_OREG_LVL_MASK)
+#define RNG_SR_OREG_SIZE_MASK                    (0xFF0000U)
+#define RNG_SR_OREG_SIZE_SHIFT                   (16U)
+#define RNG_SR_OREG_SIZE(x)                      (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_SIZE_SHIFT)) & RNG_SR_OREG_SIZE_MASK)
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Masks */
+
+
+/* RNG - Peripheral instance base addresses */
+/** Peripheral RNG base address */
+#define RNG_BASE                                 (0x40029000u)
+/** Peripheral RNG base pointer */
+#define RNG                                      ((RNG_TypeDef *)RNG_BASE)
+/** Array initializer of RNG peripheral base addresses */
+#define RNG_BASE_ADDRS                           { RNG_BASE }
+/** Array initializer of RNG peripheral base pointers */
+#define RNG_BASE_PTRS                            { RNG }
+/** Interrupt vectors for the RNG peripheral type */
+#define RNG_IRQS                                 { RNG_IRQn }
+
+/*!
+ * @}
+ */ /* end of group RNG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RTC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t TSR;                               /**< RTC Time Seconds Register, offset: 0x0 */
+  __IO uint32_t TPR;                               /**< RTC Time Prescaler Register, offset: 0x4 */
+  __IO uint32_t TAR;                               /**< RTC Time Alarm Register, offset: 0x8 */
+  __IO uint32_t TCR;                               /**< RTC Time Compensation Register, offset: 0xC */
+  __IO uint32_t CR;                                /**< RTC Control Register, offset: 0x10 */
+  __IO uint32_t SR;                                /**< RTC Status Register, offset: 0x14 */
+  __IO uint32_t LR;                                /**< RTC Lock Register, offset: 0x18 */
+  __IO uint32_t IER;                               /**< RTC Interrupt Enable Register, offset: 0x1C */
+       uint8_t RESERVED_0[2016];
+  __IO uint32_t WAR;                               /**< RTC Write Access Register, offset: 0x800 */
+  __IO uint32_t RAR;                               /**< RTC Read Access Register, offset: 0x804 */
+} RTC_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- RTC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/*! @name TPR - RTC Time Prescaler Register */
+#define RTC_TPR_TPR_MASK                         (0xFFFFU)
+#define RTC_TPR_TPR_SHIFT                        (0U)
+#define RTC_TPR_TPR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
+
+/*! @name TCR - RTC Time Compensation Register */
+#define RTC_TCR_TCR_MASK                         (0xFFU)
+#define RTC_TCR_TCR_SHIFT                        (0U)
+#define RTC_TCR_TCR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK                         (0xFF00U)
+#define RTC_TCR_CIR_SHIFT                        (8U)
+#define RTC_TCR_CIR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK                         (0xFF0000U)
+#define RTC_TCR_TCV_SHIFT                        (16U)
+#define RTC_TCR_TCV(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK                         (0xFF000000U)
+#define RTC_TCR_CIC_SHIFT                        (24U)
+#define RTC_TCR_CIC(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
+
+/*! @name CR - RTC Control Register */
+#define RTC_CR_SWR                               (0x1U)
+#define RTC_CR_WPE                               (0x2U)
+#define RTC_CR_SUP                               (0x4U)
+#define RTC_CR_UM                                (0x8U)
+#define RTC_CR_WPS                               (0x10U)
+#define RTC_CR_OSCE                              (0x100U)
+#define RTC_CR_CLKO                              (0x200U)
+#define RTC_CR_SC16P                             (0x400U)
+#define RTC_CR_SC8P                              (0x800U)
+#define RTC_CR_SC4P                              (0x1000U)
+#define RTC_CR_SC2P                              (0x2000U)
+
+/*! @name SR - RTC Status Register */
+#define RTC_SR_TIF                               (0x1U)
+#define RTC_SR_TOF                               (0x2U)
+#define RTC_SR_TAF                               (0x4U)
+#define RTC_SR_TCE                               (0x10U)
+
+/*! @name LR - RTC Lock Register */
+#define RTC_LR_TCL                               (0x8U)
+#define RTC_LR_CRL                               (0x10U)
+#define RTC_LR_SRL                               (0x20U)
+#define RTC_LR_LRL                               (0x40U)
+
+/*! @name IER - RTC Interrupt Enable Register */
+#define RTC_IER_TIIE                             (0x1U)
+#define RTC_IER_TOIE                             (0x2U)
+#define RTC_IER_TAIE                             (0x4U)
+#define RTC_IER_TSIE                             (0x10U)
+#define RTC_IER_WPON                             (0x80U)
+
+/*! @name WAR - RTC Write Access Register */
+#define RTC_WAR_TSRW                             (0x1U)
+#define RTC_WAR_TPRW                             (0x2U)
+#define RTC_WAR_TARW                             (0x4U)
+#define RTC_WAR_TCRW                             (0x8U)
+#define RTC_WAR_CRW                              (0x10U)
+#define RTC_WAR_SRW                              (0x20U)
+#define RTC_WAR_LRW                              (0x40U)
+#define RTC_WAR_IERW                             (0x80U)
+
+/*! @name RAR - RTC Read Access Register */
+#define RTC_RAR_TSRR                             (0x1U)
+#define RTC_RAR_TPRR                             (0x2U)
+#define RTC_RAR_TARR                             (0x4U)
+#define RTC_RAR_TCRR                             (0x8U)
+#define RTC_RAR_CRR                              (0x10U)
+#define RTC_RAR_SRR                              (0x20U)
+#define RTC_RAR_LRR                              (0x40U)
+#define RTC_RAR_IERR                             (0x80U)
+
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE                                 (0x4003D000u)
+/** Peripheral RTC base pointer */
+#define RTC                                      ((RTC_TypeDef *)RTC_BASE)
+/** Array initializer of RTC peripheral base addresses */
+#define RTC_BASE_ADDRS                           { RTC_BASE }
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASE_PTRS                            { RTC }
+/** Interrupt vectors for the RTC peripheral type */
+#define RTC_IRQS                                 { RTC_IRQn }
+#define RTC_SECONDS_IRQS                         { RTC_Seconds_IRQn }
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDHC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer
+ * @{
+ */
+
+/** SDHC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t DSADDR;                            /**< DMA System Address register, offset: 0x0 */
+  __IO uint32_t BLKATTR;                           /**< Block Attributes register, offset: 0x4 */
+  __IO uint32_t CMDARG;                            /**< Command Argument register, offset: 0x8 */
+  __IO uint32_t XFERTYP;                           /**< Transfer Type register, offset: 0xC */
+  __I  uint32_t CMDRSP[4];                         /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */
+  __IO uint32_t DATPORT;                           /**< Buffer Data Port register, offset: 0x20 */
+  __I  uint32_t PRSSTAT;                           /**< Present State register, offset: 0x24 */
+  __IO uint32_t PROCTL;                            /**< Protocol Control register, offset: 0x28 */
+  __IO uint32_t SYSCTL;                            /**< System Control register, offset: 0x2C */
+  __IO uint32_t IRQSTAT;                           /**< Interrupt Status register, offset: 0x30 */
+  __IO uint32_t IRQSTATEN;                         /**< Interrupt Status Enable register, offset: 0x34 */
+  __IO uint32_t IRQSIGEN;                          /**< Interrupt Signal Enable register, offset: 0x38 */
+  __I  uint32_t AC12ERR;                           /**< Auto CMD12 Error Status Register, offset: 0x3C */
+  __I  uint32_t HTCAPBLT;                          /**< Host Controller Capabilities, offset: 0x40 */
+  __IO uint32_t WML;                               /**< Watermark Level Register, offset: 0x44 */
+       uint8_t RESERVED_0[8];
+  __O  uint32_t FEVT;                              /**< Force Event register, offset: 0x50 */
+  __I  uint32_t ADMAES;                            /**< ADMA Error Status register, offset: 0x54 */
+  __IO uint32_t ADSADDR;                           /**< ADMA System Addressregister, offset: 0x58 */
+       uint8_t RESERVED_1[100];
+  __IO uint32_t VENDOR;                            /**< Vendor Specific register, offset: 0xC0 */
+  __IO uint32_t MMCBOOT;                           /**< MMC Boot register, offset: 0xC4 */
+       uint8_t RESERVED_2[52];
+  __I  uint32_t HOSTVER;                           /**< Host Controller Version, offset: 0xFC */
+} SDHC_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- SDHC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Register_Masks SDHC Register Masks
+ * @{
+ */
+
+/*! @name BLKATTR - Block Attributes register */
+#define SDHC_BLKATTR_BLKSIZE_MASK                (0x1FFFU)
+#define SDHC_BLKATTR_BLKSIZE_SHIFT               (0U)
+#define SDHC_BLKATTR_BLKSIZE(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKSIZE_SHIFT)) & SDHC_BLKATTR_BLKSIZE_MASK)
+#define SDHC_BLKATTR_BLKCNT_MASK                 (0xFFFF0000U)
+#define SDHC_BLKATTR_BLKCNT_SHIFT                (16U)
+#define SDHC_BLKATTR_BLKCNT(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKCNT_SHIFT)) & SDHC_BLKATTR_BLKCNT_MASK)
+
+/*! @name XFERTYP - Transfer Type register */
+#define SDHC_XFERTYP_DMAEN                       (0x1U)
+#define SDHC_XFERTYP_BCEN                        (0x2U)
+#define SDHC_XFERTYP_AC12EN                      (0x4U)
+#define SDHC_XFERTYP_DTDSEL                      (0x10U)
+#define SDHC_XFERTYP_MSBSEL                      (0x20U)
+#define SDHC_XFERTYP_RSPTYP_MASK                 (0x30000U)
+#define SDHC_XFERTYP_RSPTYP_SHIFT                (16U)
+#define SDHC_XFERTYP_RSPTYP(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_RSPTYP_SHIFT)) & SDHC_XFERTYP_RSPTYP_MASK)
+#define SDHC_XFERTYP_CCCEN                       (0x80000U)
+#define SDHC_XFERTYP_CICEN                       (0x100000U)
+#define SDHC_XFERTYP_DPSEL                       (0x200000U)
+#define SDHC_XFERTYP_CMDTYP_MASK                 (0xC00000U)
+#define SDHC_XFERTYP_CMDTYP_SHIFT                (22U)
+#define SDHC_XFERTYP_CMDTYP(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDTYP_SHIFT)) & SDHC_XFERTYP_CMDTYP_MASK)
+#define SDHC_XFERTYP_CMDINX_MASK                 (0x3F000000U)
+#define SDHC_XFERTYP_CMDINX_SHIFT                (24U)
+#define SDHC_XFERTYP_CMDINX(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDINX_SHIFT)) & SDHC_XFERTYP_CMDINX_MASK)
+
+/* The count of SDHC_CMDRSP */
+#define SDHC_CMDRSP_COUNT                        (4U)
+
+/*! @name PRSSTAT - Present State register */
+#define SDHC_PRSSTAT_CIHB                        (0x1U)
+#define SDHC_PRSSTAT_CDIHB                       (0x2U)
+#define SDHC_PRSSTAT_DLA                         (0x4U)
+#define SDHC_PRSSTAT_SDSTB                       (0x8U)
+#define SDHC_PRSSTAT_IPGOFF                      (0x10U)
+#define SDHC_PRSSTAT_HCKOFF                      (0x20U)
+#define SDHC_PRSSTAT_PEROFF                      (0x40U)
+#define SDHC_PRSSTAT_SDOFF                       (0x80U)
+#define SDHC_PRSSTAT_WTA                         (0x100U)
+#define SDHC_PRSSTAT_RTA                         (0x200U)
+#define SDHC_PRSSTAT_BWEN                        (0x400U)
+#define SDHC_PRSSTAT_BREN                        (0x800U)
+#define SDHC_PRSSTAT_CINS                        (0x10000U)
+#define SDHC_PRSSTAT_CLSL                        (0x800000U)
+#define SDHC_PRSSTAT_DLSL_MASK                   (0xFF000000U)
+#define SDHC_PRSSTAT_DLSL_SHIFT                  (24U)
+#define SDHC_PRSSTAT_DLSL(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLSL_SHIFT)) & SDHC_PRSSTAT_DLSL_MASK)
+
+/*! @name PROCTL - Protocol Control register */
+#define SDHC_PROCTL_LCTL                         (0x1U)
+#define SDHC_PROCTL_DTW_MASK                     (0x6U)
+#define SDHC_PROCTL_DTW_SHIFT                    (1U)
+#define SDHC_PROCTL_DTW(x)                       (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DTW_SHIFT)) & SDHC_PROCTL_DTW_MASK)
+#define SDHC_PROCTL_D3CD                         (0x8U)
+#define SDHC_PROCTL_EMODE_MASK                   (0x30U)
+#define SDHC_PROCTL_EMODE_SHIFT                  (4U)
+#define SDHC_PROCTL_EMODE(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_EMODE_SHIFT)) & SDHC_PROCTL_EMODE_MASK)
+#define SDHC_PROCTL_CDTL                         (0x40U)
+#define SDHC_PROCTL_CDSS                         (0x80U)
+#define SDHC_PROCTL_DMAS_MASK                    (0x300U)
+#define SDHC_PROCTL_DMAS_SHIFT                   (8U)
+#define SDHC_PROCTL_DMAS(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DMAS_SHIFT)) & SDHC_PROCTL_DMAS_MASK)
+#define SDHC_PROCTL_SABGREQ                      (0x10000U)
+#define SDHC_PROCTL_CREQ                         (0x20000U)
+#define SDHC_PROCTL_RWCTL                        (0x40000U)
+#define SDHC_PROCTL_IABG                         (0x80000U)
+#define SDHC_PROCTL_WECINT                       (0x1000000U)
+#define SDHC_PROCTL_WECINS                       (0x2000000U)
+#define SDHC_PROCTL_WECRM                        (0x4000000U)
+
+/*! @name SYSCTL - System Control register */
+#define SDHC_SYSCTL_IPGEN                        (0x1U)
+#define SDHC_SYSCTL_HCKEN                        (0x2U)
+#define SDHC_SYSCTL_PEREN                        (0x4U)
+#define SDHC_SYSCTL_SDCLKEN                      (0x8U)
+#define SDHC_SYSCTL_DVS_MASK                     (0xF0U)
+#define SDHC_SYSCTL_DVS_SHIFT                    (4U)
+#define SDHC_SYSCTL_DVS(x)                       (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DVS_SHIFT)) & SDHC_SYSCTL_DVS_MASK)
+#define SDHC_SYSCTL_SDCLKFS_MASK                 (0xFF00U)
+#define SDHC_SYSCTL_SDCLKFS_SHIFT                (8U)
+#define SDHC_SYSCTL_SDCLKFS(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKFS_SHIFT)) & SDHC_SYSCTL_SDCLKFS_MASK)
+#define SDHC_SYSCTL_DTOCV_MASK                   (0xF0000U)
+#define SDHC_SYSCTL_DTOCV_SHIFT                  (16U)
+#define SDHC_SYSCTL_DTOCV(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DTOCV_SHIFT)) & SDHC_SYSCTL_DTOCV_MASK)
+#define SDHC_SYSCTL_RSTA                         (0x1000000U)
+#define SDHC_SYSCTL_RSTC                         (0x2000000U)
+#define SDHC_SYSCTL_RSTD                         (0x4000000U)
+#define SDHC_SYSCTL_INITA                        (0x8000000U)
+
+/*! @name IRQSTAT - Interrupt Status register */
+#define SDHC_IRQSTAT_CC                          (0x1U)
+#define SDHC_IRQSTAT_TC                          (0x2U)
+#define SDHC_IRQSTAT_BGE                         (0x4U)
+#define SDHC_IRQSTAT_DINT                        (0x8U)
+#define SDHC_IRQSTAT_BWR                         (0x10U)
+#define SDHC_IRQSTAT_BRR                         (0x20U)
+#define SDHC_IRQSTAT_CINS                        (0x40U)
+#define SDHC_IRQSTAT_CRM                         (0x80U)
+#define SDHC_IRQSTAT_CINT                        (0x100U)
+#define SDHC_IRQSTAT_CTOE                        (0x10000U)
+#define SDHC_IRQSTAT_CCE                         (0x20000U)
+#define SDHC_IRQSTAT_CEBE                        (0x40000U)
+#define SDHC_IRQSTAT_CIE                         (0x80000U)
+#define SDHC_IRQSTAT_DTOE                        (0x100000U)
+#define SDHC_IRQSTAT_DCE                         (0x200000U)
+#define SDHC_IRQSTAT_DEBE                        (0x400000U)
+#define SDHC_IRQSTAT_AC12E                       (0x1000000U)
+#define SDHC_IRQSTAT_DMAE                        (0x10000000U)
+
+/*! @name IRQSTATEN - Interrupt Status Enable register */
+#define SDHC_IRQSTATEN_CCSEN                     (0x1U)
+#define SDHC_IRQSTATEN_TCSEN                     (0x2U)
+#define SDHC_IRQSTATEN_BGESEN                    (0x4U)
+#define SDHC_IRQSTATEN_DINTSEN                   (0x8U)
+#define SDHC_IRQSTATEN_BWRSEN                    (0x10U)
+#define SDHC_IRQSTATEN_BRRSEN                    (0x20U)
+#define SDHC_IRQSTATEN_CINSEN                    (0x40U)
+#define SDHC_IRQSTATEN_CRMSEN                    (0x80U)
+#define SDHC_IRQSTATEN_CINTSEN                   (0x100U)
+#define SDHC_IRQSTATEN_CTOESEN                   (0x10000U)
+#define SDHC_IRQSTATEN_CCESEN                    (0x20000U)
+#define SDHC_IRQSTATEN_CEBESEN                   (0x40000U)
+#define SDHC_IRQSTATEN_CIESEN                    (0x80000U)
+#define SDHC_IRQSTATEN_DTOESEN                   (0x100000U)
+#define SDHC_IRQSTATEN_DCESEN                    (0x200000U)
+#define SDHC_IRQSTATEN_DEBESEN                   (0x400000U)
+#define SDHC_IRQSTATEN_AC12ESEN                  (0x1000000U)
+#define SDHC_IRQSTATEN_DMAESEN                   (0x10000000U)
+
+/*! @name IRQSIGEN - Interrupt Signal Enable register */
+#define SDHC_IRQSIGEN_CCIEN                      (0x1U)
+#define SDHC_IRQSIGEN_TCIEN                      (0x2U)
+#define SDHC_IRQSIGEN_BGEIEN                     (0x4U)
+#define SDHC_IRQSIGEN_DINTIEN                    (0x8U)
+#define SDHC_IRQSIGEN_BWRIEN                     (0x10U)
+#define SDHC_IRQSIGEN_BRRIEN                     (0x20U)
+#define SDHC_IRQSIGEN_CINSIEN                    (0x40U)
+#define SDHC_IRQSIGEN_CRMIEN                     (0x80U)
+#define SDHC_IRQSIGEN_CINTIEN                    (0x100U)
+#define SDHC_IRQSIGEN_CTOEIEN                    (0x10000U)
+#define SDHC_IRQSIGEN_CCEIEN                     (0x20000U)
+#define SDHC_IRQSIGEN_CEBEIEN                    (0x40000U)
+#define SDHC_IRQSIGEN_CIEIEN                     (0x80000U)
+#define SDHC_IRQSIGEN_DTOEIEN                    (0x100000U)
+#define SDHC_IRQSIGEN_DCEIEN                     (0x200000U)
+#define SDHC_IRQSIGEN_DEBEIEN                    (0x400000U)
+#define SDHC_IRQSIGEN_AC12EIEN                   (0x1000000U)
+#define SDHC_IRQSIGEN_DMAEIEN                    (0x10000000U)
+
+/*! @name AC12ERR - Auto CMD12 Error Status Register */
+#define SDHC_AC12ERR_AC12NE                      (0x1U)
+#define SDHC_AC12ERR_AC12TOE                     (0x2U)
+#define SDHC_AC12ERR_AC12EBE                     (0x4U)
+#define SDHC_AC12ERR_AC12CE                      (0x8U)
+#define SDHC_AC12ERR_AC12IE                      (0x10U)
+#define SDHC_AC12ERR_CNIBAC12E                   (0x80U)
+
+/*! @name HTCAPBLT - Host Controller Capabilities */
+#define SDHC_HTCAPBLT_MBL_MASK                   (0x70000U)
+#define SDHC_HTCAPBLT_MBL_SHIFT                  (16U)
+#define SDHC_HTCAPBLT_MBL(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_MBL_SHIFT)) & SDHC_HTCAPBLT_MBL_MASK)
+#define SDHC_HTCAPBLT_ADMAS                      (0x100000U)
+#define SDHC_HTCAPBLT_HSS                        (0x200000U)
+#define SDHC_HTCAPBLT_DMAS                       (0x400000U)
+#define SDHC_HTCAPBLT_SRS                        (0x800000U)
+#define SDHC_HTCAPBLT_VS33                       (0x1000000U)
+
+/*! @name WML - Watermark Level Register */
+#define SDHC_WML_RDWML_MASK                      (0xFFU)
+#define SDHC_WML_RDWML_SHIFT                     (0U)
+#define SDHC_WML_RDWML(x)                        (((uint32_t)(((uint32_t)(x)) << SDHC_WML_RDWML_SHIFT)) & SDHC_WML_RDWML_MASK)
+#define SDHC_WML_WRWML_MASK                      (0xFF0000U)
+#define SDHC_WML_WRWML_SHIFT                     (16U)
+#define SDHC_WML_WRWML(x)                        (((uint32_t)(((uint32_t)(x)) << SDHC_WML_WRWML_SHIFT)) & SDHC_WML_WRWML_MASK)
+
+/*! @name FEVT - Force Event register */
+#define SDHC_FEVT_AC12NE                         (0x1U)
+#define SDHC_FEVT_AC12TOE                        (0x2U)
+#define SDHC_FEVT_AC12CE                         (0x4U)
+#define SDHC_FEVT_AC12EBE                        (0x8U)
+#define SDHC_FEVT_AC12IE                         (0x10U)
+#define SDHC_FEVT_CNIBAC12E                      (0x80U)
+#define SDHC_FEVT_CTOE                           (0x10000U)
+#define SDHC_FEVT_CCE                            (0x20000U)
+#define SDHC_FEVT_CEBE                           (0x40000U)
+#define SDHC_FEVT_CIE                            (0x80000U)
+#define SDHC_FEVT_DTOE                           (0x100000U)
+#define SDHC_FEVT_DCE                            (0x200000U)
+#define SDHC_FEVT_DEBE                           (0x400000U)
+#define SDHC_FEVT_AC12E                          (0x1000000U)
+#define SDHC_FEVT_DMAE                           (0x10000000U)
+#define SDHC_FEVT_CINT                           (0x80000000U)
+
+/*! @name ADMAES - ADMA Error Status register */
+#define SDHC_ADMAES_ADMAES_MASK                  (0x3U)
+#define SDHC_ADMAES_ADMAES_SHIFT                 (0U)
+#define SDHC_ADMAES_ADMAES(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMAES_SHIFT)) & SDHC_ADMAES_ADMAES_MASK)
+#define SDHC_ADMAES_ADMALME                      (0x4U)
+#define SDHC_ADMAES_ADMADCE                      (0x8U)
+
+/*! @name VENDOR - Vendor Specific register */
+#define SDHC_VENDOR_EXTDMAEN                     (0x1U)
+#define SDHC_VENDOR_EXBLKNU                      (0x2U)
+#define SDHC_VENDOR_INTSTVAL_MASK                (0xFF0000U)
+#define SDHC_VENDOR_INTSTVAL_SHIFT               (16U)
+#define SDHC_VENDOR_INTSTVAL(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_INTSTVAL_SHIFT)) & SDHC_VENDOR_INTSTVAL_MASK)
+
+/*! @name MMCBOOT - MMC Boot register */
+#define SDHC_MMCBOOT_DTOCVACK_MASK               (0xFU)
+#define SDHC_MMCBOOT_DTOCVACK_SHIFT              (0U)
+#define SDHC_MMCBOOT_DTOCVACK(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_DTOCVACK_SHIFT)) & SDHC_MMCBOOT_DTOCVACK_MASK)
+#define SDHC_MMCBOOT_BOOTACK                     (0x10U)
+#define SDHC_MMCBOOT_BOOTMODE                    (0x20U)
+#define SDHC_MMCBOOT_BOOTEN                      (0x40U)
+#define SDHC_MMCBOOT_AUTOSABGEN                  (0x80U)
+#define SDHC_MMCBOOT_BOOTBLKCNT_MASK             (0xFFFF0000U)
+#define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT            (16U)
+#define SDHC_MMCBOOT_BOOTBLKCNT(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTBLKCNT_SHIFT)) & SDHC_MMCBOOT_BOOTBLKCNT_MASK)
+
+/*! @name HOSTVER - Host Controller Version */
+#define SDHC_HOSTVER_SVN_MASK                    (0xFFU)
+#define SDHC_HOSTVER_SVN_SHIFT                   (0U)
+#define SDHC_HOSTVER_SVN(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_SVN_SHIFT)) & SDHC_HOSTVER_SVN_MASK)
+#define SDHC_HOSTVER_VVN_MASK                    (0xFF00U)
+#define SDHC_HOSTVER_VVN_SHIFT                   (8U)
+#define SDHC_HOSTVER_VVN(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_VVN_SHIFT)) & SDHC_HOSTVER_VVN_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group SDHC_Register_Masks */
+
+
+/* SDHC - Peripheral instance base addresses */
+/** Peripheral SDHC base address */
+#define SDHC_BASE                                (0x400B1000u)
+/** Peripheral SDHC base pointer */
+#define SDHC                                     ((SDHC_TypeDef *)SDHC_BASE)
+/** Array initializer of SDHC peripheral base addresses */
+#define SDHC_BASE_ADDRS                          { SDHC_BASE }
+/** Array initializer of SDHC peripheral base pointers */
+#define SDHC_BASE_PTRS                           { SDHC }
+/** Interrupt vectors for the SDHC peripheral type */
+#define SDHC_IRQS                                { SDHC_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SDHC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SIM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SOPT1;                             /**< System Options Register 1, offset: 0x0 */
+  __IO uint32_t SOPT1CFG;                          /**< SOPT1 Configuration Register, offset: 0x4 */
+       uint8_t RESERVED_0[4092];
+  __IO uint32_t SOPT2;                             /**< System Options Register 2, offset: 0x1004 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t SOPT4;                             /**< System Options Register 4, offset: 0x100C */
+  __IO uint32_t SOPT5;                             /**< System Options Register 5, offset: 0x1010 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t SOPT7;                             /**< System Options Register 7, offset: 0x1018 */
+       uint8_t RESERVED_3[8];
+  __I  uint32_t SDID;                              /**< System Device Identification Register, offset: 0x1024 */
+  __IO uint32_t SCGC1;                             /**< System Clock Gating Control Register 1, offset: 0x1028 */
+  __IO uint32_t SCGC2;                             /**< System Clock Gating Control Register 2, offset: 0x102C */
+  __IO uint32_t SCGC3;                             /**< System Clock Gating Control Register 3, offset: 0x1030 */
+  __IO uint32_t SCGC4;                             /**< System Clock Gating Control Register 4, offset: 0x1034 */
+  __IO uint32_t SCGC5;                             /**< System Clock Gating Control Register 5, offset: 0x1038 */
+  __IO uint32_t SCGC6;                             /**< System Clock Gating Control Register 6, offset: 0x103C */
+  __IO uint32_t SCGC7;                             /**< System Clock Gating Control Register 7, offset: 0x1040 */
+  __IO uint32_t CLKDIV1;                           /**< System Clock Divider Register 1, offset: 0x1044 */
+  __IO uint32_t CLKDIV2;                           /**< System Clock Divider Register 2, offset: 0x1048 */
+  __IO uint32_t FCFG1;                             /**< Flash Configuration Register 1, offset: 0x104C */
+  __I  uint32_t FCFG2;                             /**< Flash Configuration Register 2, offset: 0x1050 */
+  __I  uint32_t UIDH;                              /**< Unique Identification Register High, offset: 0x1054 */
+  __I  uint32_t UIDMH;                             /**< Unique Identification Register Mid-High, offset: 0x1058 */
+  __I  uint32_t UIDML;                             /**< Unique Identification Register Mid Low, offset: 0x105C */
+  __I  uint32_t UIDL;                              /**< Unique Identification Register Low, offset: 0x1060 */
+} SIM_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- SIM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/*! @name SOPT1 - System Options Register 1 */
+#define SIM_SOPT1_RAMSIZE_MASK                   (0xF000U)
+#define SIM_SOPT1_RAMSIZE_SHIFT                  (12U)
+#define SIM_SOPT1_RAMSIZE(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)
+#define SIM_SOPT1_OSC32KSEL_MASK                 (0xC0000U)
+#define SIM_SOPT1_OSC32KSEL_SHIFT                (18U)
+#define SIM_SOPT1_OSC32KSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
+#define SIM_SOPT1_USBVSTBY                       (0x20000000U)
+#define SIM_SOPT1_USBSSTBY                       (0x40000000U)
+#define SIM_SOPT1_USBREGEN                       (0x80000000U)
+
+/*! @name SOPT1CFG - SOPT1 Configuration Register */
+#define SIM_SOPT1CFG_URWE                        (0x1000000U)
+#define SIM_SOPT1CFG_UVSWE                       (0x2000000U)
+#define SIM_SOPT1CFG_USSWE                       (0x4000000U)
+
+/*! @name SOPT2 - System Options Register 2 */
+#define SIM_SOPT2_RTCCLKOUTSEL                   (0x10U)
+#define SIM_SOPT2_CLKOUTSEL_MASK                 (0xE0U)
+#define SIM_SOPT2_CLKOUTSEL_SHIFT                (5U)
+#define SIM_SOPT2_CLKOUTSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_FBSL_MASK                      (0x300U)
+#define SIM_SOPT2_FBSL_SHIFT                     (8U)
+#define SIM_SOPT2_FBSL(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FBSL_SHIFT)) & SIM_SOPT2_FBSL_MASK)
+#define SIM_SOPT2_PTD7PAD                        (0x800U)
+#define SIM_SOPT2_TRACECLKSEL                    (0x1000U)
+#define SIM_SOPT2_PLLFLLSEL_MASK                 (0x30000U)
+#define SIM_SOPT2_PLLFLLSEL_SHIFT                (16U)
+#define SIM_SOPT2_PLLFLLSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
+#define SIM_SOPT2_PLLFLLSEL_MCGFLL               SIM_SOPT2_PLLFLLSEL(0)
+#define SIM_SOPT2_PLLFLLSEL_MCGPLL               SIM_SOPT2_PLLFLLSEL(1)
+#define SIM_SOPT2_PLLFLLSEL_IRC48M               SIM_SOPT2_PLLFLLSEL(3)
+#define SIM_SOPT2_USBSRC                         (0x40000U)
+#define SIM_SOPT2_RMIISRC                        (0x80000U)
+#define SIM_SOPT2_TIMESRC_MASK                   (0x300000U)
+#define SIM_SOPT2_TIMESRC_SHIFT                  (20U)
+#define SIM_SOPT2_TIMESRC(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TIMESRC_SHIFT)) & SIM_SOPT2_TIMESRC_MASK)
+#define SIM_SOPT2_SDHCSRC_MASK                   (0x30000000U)
+#define SIM_SOPT2_SDHCSRC_SHIFT                  (28U)
+#define SIM_SOPT2_SDHCSRC(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_SDHCSRC_SHIFT)) & SIM_SOPT2_SDHCSRC_MASK)
+
+/*! @name SOPT4 - System Options Register 4 */
+#define SIM_SOPT4_FTM0FLT0                       (0x1U)
+#define SIM_SOPT4_FTM0FLT1                       (0x2U)
+#define SIM_SOPT4_FTM0FLT2                       (0x4U)
+#define SIM_SOPT4_FTM1FLT0                       (0x10U)
+#define SIM_SOPT4_FTM2FLT0                       (0x100U)
+#define SIM_SOPT4_FTM3FLT0                       (0x1000U)
+#define SIM_SOPT4_FTM1CH0SRC_MASK                (0xC0000U)
+#define SIM_SOPT4_FTM1CH0SRC_SHIFT               (18U)
+#define SIM_SOPT4_FTM1CH0SRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK)
+#define SIM_SOPT4_FTM2CH0SRC_MASK                (0x300000U)
+#define SIM_SOPT4_FTM2CH0SRC_SHIFT               (20U)
+#define SIM_SOPT4_FTM2CH0SRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK)
+#define SIM_SOPT4_FTM0CLKSEL                     (0x1000000U)
+#define SIM_SOPT4_FTM1CLKSEL                     (0x2000000U)
+#define SIM_SOPT4_FTM2CLKSEL                     (0x4000000U)
+#define SIM_SOPT4_FTM3CLKSEL                     (0x8000000U)
+#define SIM_SOPT4_FTM0TRG0SRC                    (0x10000000U)
+#define SIM_SOPT4_FTM0TRG1SRC                    (0x20000000U)
+#define SIM_SOPT4_FTM3TRG0SRC                    (0x40000000U)
+#define SIM_SOPT4_FTM3TRG1SRC                    (0x80000000U)
+
+/*! @name SOPT5 - System Options Register 5 */
+#define SIM_SOPT5_UART0TXSRC_MASK                (0x3U)
+#define SIM_SOPT5_UART0TXSRC_SHIFT               (0U)
+#define SIM_SOPT5_UART0TXSRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
+#define SIM_SOPT5_UART0RXSRC_MASK                (0xCU)
+#define SIM_SOPT5_UART0RXSRC_SHIFT               (2U)
+#define SIM_SOPT5_UART0RXSRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
+#define SIM_SOPT5_UART1TXSRC_MASK                (0x30U)
+#define SIM_SOPT5_UART1TXSRC_SHIFT               (4U)
+#define SIM_SOPT5_UART1TXSRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
+#define SIM_SOPT5_UART1RXSRC_MASK                (0xC0U)
+#define SIM_SOPT5_UART1RXSRC_SHIFT               (6U)
+#define SIM_SOPT5_UART1RXSRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
+
+/*! @name SOPT7 - System Options Register 7 */
+#define SIM_SOPT7_ADC0TRGSEL_MASK                (0xFU)
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT               (0U)
+#define SIM_SOPT7_ADC0TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL                  (0x10U)
+#define SIM_SOPT7_ADC0ALTTRGEN                   (0x80U)
+#define SIM_SOPT7_ADC1TRGSEL_MASK                (0xF00U)
+#define SIM_SOPT7_ADC1TRGSEL_SHIFT               (8U)
+#define SIM_SOPT7_ADC1TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1TRGSEL_SHIFT)) & SIM_SOPT7_ADC1TRGSEL_MASK)
+#define SIM_SOPT7_ADC1PRETRGSEL                  (0x1000U)
+#define SIM_SOPT7_ADC1ALTTRGEN                   (0x8000U)
+
+/*! @name SDID - System Device Identification Register */
+#define SIM_SDID_PINID_MASK                      (0xFU)
+#define SIM_SDID_PINID_SHIFT                     (0U)
+#define SIM_SDID_PINID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
+#define SIM_SDID_FAMID_MASK                      (0x70U)
+#define SIM_SDID_FAMID_SHIFT                     (4U)
+#define SIM_SDID_FAMID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
+#define SIM_SDID_DIEID_MASK                      (0xF80U)
+#define SIM_SDID_DIEID_SHIFT                     (7U)
+#define SIM_SDID_DIEID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
+#define SIM_SDID_REVID_MASK                      (0xF000U)
+#define SIM_SDID_REVID_SHIFT                     (12U)
+#define SIM_SDID_REVID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
+#define SIM_SDID_SERIESID_MASK                   (0xF00000U)
+#define SIM_SDID_SERIESID_SHIFT                  (20U)
+#define SIM_SDID_SERIESID(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
+#define SIM_SDID_SUBFAMID_MASK                   (0xF000000U)
+#define SIM_SDID_SUBFAMID_SHIFT                  (24U)
+#define SIM_SDID_SUBFAMID(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
+#define SIM_SDID_FAMILYID_MASK                   (0xF0000000U)
+#define SIM_SDID_FAMILYID_SHIFT                  (28U)
+#define SIM_SDID_FAMILYID(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK)
+
+/*! @name SCGC1 - System Clock Gating Control Register 1 */
+#define SIM_SCGC1_I2C2                           (0x40U)
+#define SIM_SCGC1_UART4                          (0x400U)
+#define SIM_SCGC1_UART5                          (0x800U)
+
+/*! @name SCGC2 - System Clock Gating Control Register 2 */
+#define SIM_SCGC2_ENET                           (0x1U)
+#define SIM_SCGC2_DAC0                           (0x1000U)
+#define SIM_SCGC2_DAC1                           (0x2000U)
+
+/*! @name SCGC3 - System Clock Gating Control Register 3 */
+#define SIM_SCGC3_RNGA                           (0x1U)
+#define SIM_SCGC3_SPI2                           (0x1000U)
+#define SIM_SCGC3_SDHC                           (0x20000U)
+#define SIM_SCGC3_FTM2                           (0x1000000U)
+#define SIM_SCGC3_FTM3                           (0x2000000U)
+#define SIM_SCGC3_ADC1                           (0x8000000U)
+
+/*! @name SCGC4 - System Clock Gating Control Register 4 */
+#define SIM_SCGC4_EWM                            (0x2U)
+#define SIM_SCGC4_CMT                            (0x4U)
+#define SIM_SCGC4_I2C0                           (0x40U)
+#define SIM_SCGC4_I2C1                           (0x80U)
+#define SIM_SCGC4_UART0                          (0x400U)
+#define SIM_SCGC4_UART1                          (0x800U)
+#define SIM_SCGC4_UART2                          (0x1000U)
+#define SIM_SCGC4_UART3                          (0x2000U)
+#define SIM_SCGC4_USBOTG                         (0x40000U)
+#define SIM_SCGC4_CMP                            (0x80000U)
+#define SIM_SCGC4_VREF                           (0x100000U)
+
+/*! @name SCGC5 - System Clock Gating Control Register 5 */
+#define SIM_SCGC5_LPTMR                          (0x1U)
+#define SIM_SCGC5_PORTA                          (0x200U)
+#define SIM_SCGC5_PORTB                          (0x400U)
+#define SIM_SCGC5_PORTC                          (0x800U)
+#define SIM_SCGC5_PORTD                          (0x1000U)
+#define SIM_SCGC5_PORTE                          (0x2000U)
+
+/*! @name SCGC6 - System Clock Gating Control Register 6 */
+#define SIM_SCGC6_FTF                            (0x1U)
+#define SIM_SCGC6_DMAMUX                         (0x2U)
+#define SIM_SCGC6_FLEXCAN0                       (0x10U)
+#define SIM_SCGC6_RNGA                           (0x200U)
+#define SIM_SCGC6_SPI0                           (0x1000U)
+#define SIM_SCGC6_SPI1                           (0x2000U)
+#define SIM_SCGC6_I2S                            (0x8000U)
+#define SIM_SCGC6_CRC                            (0x40000U)
+#define SIM_SCGC6_USBDCD                         (0x200000U)
+#define SIM_SCGC6_PDB                            (0x400000U)
+#define SIM_SCGC6_PIT                            (0x800000U)
+#define SIM_SCGC6_FTM0                           (0x1000000U)
+#define SIM_SCGC6_FTM1                           (0x2000000U)
+#define SIM_SCGC6_FTM2                           (0x4000000U)
+#define SIM_SCGC6_ADC0                           (0x8000000U)
+#define SIM_SCGC6_RTC                            (0x20000000U)
+#define SIM_SCGC6_DAC0                           (0x80000000U)
+
+/*! @name SCGC7 - System Clock Gating Control Register 7 */
+#define SIM_SCGC7_FLEXBUS                        (0x1U)
+#define SIM_SCGC7_DMA                            (0x2U)
+#define SIM_SCGC7_MPU                            (0x4U)
+
+/*! @name CLKDIV1 - System Clock Divider Register 1 */
+#define SIM_CLKDIV1_OUTDIV4_MASK                 (0xF0000U)
+#define SIM_CLKDIV1_OUTDIV4_SHIFT                (16U)
+#define SIM_CLKDIV1_OUTDIV4(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV3_MASK                 (0xF00000U)
+#define SIM_CLKDIV1_OUTDIV3_SHIFT                (20U)
+#define SIM_CLKDIV1_OUTDIV3(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV3_SHIFT)) & SIM_CLKDIV1_OUTDIV3_MASK)
+#define SIM_CLKDIV1_OUTDIV2_MASK                 (0xF000000U)
+#define SIM_CLKDIV1_OUTDIV2_SHIFT                (24U)
+#define SIM_CLKDIV1_OUTDIV2(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK                 (0xF0000000U)
+#define SIM_CLKDIV1_OUTDIV1_SHIFT                (28U)
+#define SIM_CLKDIV1_OUTDIV1(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
+
+/*! @name CLKDIV2 - System Clock Divider Register 2 */
+#define SIM_CLKDIV2_USBFRAC                      (0x1U)
+#define SIM_CLKDIV2_USBDIV_MASK                  (0xEU)
+#define SIM_CLKDIV2_USBDIV_SHIFT                 (1U)
+#define SIM_CLKDIV2_USBDIV(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK)
+
+/*! @name FCFG1 - Flash Configuration Register 1 */
+#define SIM_FCFG1_FLASHDIS                       (0x1U)
+#define SIM_FCFG1_FLASHDOZE                      (0x2U)
+#define SIM_FCFG1_DEPART_MASK                    (0xF00U)
+#define SIM_FCFG1_DEPART_SHIFT                   (8U)
+#define SIM_FCFG1_DEPART(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_DEPART_SHIFT)) & SIM_FCFG1_DEPART_MASK)
+#define SIM_FCFG1_EESIZE_MASK                    (0xF0000U)
+#define SIM_FCFG1_EESIZE_SHIFT                   (16U)
+#define SIM_FCFG1_EESIZE(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EESIZE_SHIFT)) & SIM_FCFG1_EESIZE_MASK)
+#define SIM_FCFG1_PFSIZE_MASK                    (0xF000000U)
+#define SIM_FCFG1_PFSIZE_SHIFT                   (24U)
+#define SIM_FCFG1_PFSIZE(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
+#define SIM_FCFG1_NVMSIZE_MASK                   (0xF0000000U)
+#define SIM_FCFG1_NVMSIZE_SHIFT                  (28U)
+#define SIM_FCFG1_NVMSIZE(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_NVMSIZE_SHIFT)) & SIM_FCFG1_NVMSIZE_MASK)
+
+/*! @name FCFG2 - Flash Configuration Register 2 */
+#define SIM_FCFG2_MAXADDR1_MASK                  (0x7F0000U)
+#define SIM_FCFG2_MAXADDR1_SHIFT                 (16U)
+#define SIM_FCFG2_MAXADDR1(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
+#define SIM_FCFG2_PFLSH                          (0x800000U)
+#define SIM_FCFG2_MAXADDR0_MASK                  (0x7F000000U)
+#define SIM_FCFG2_MAXADDR0_SHIFT                 (24U)
+#define SIM_FCFG2_MAXADDR0(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE                                 (0x40047000u)
+/** Peripheral SIM base pointer */
+#define SIM                                      ((SIM_TypeDef *)SIM_BASE)
+/** Array initializer of SIM peripheral base addresses */
+#define SIM_BASE_ADDRS                           { SIM_BASE }
+/** Array initializer of SIM peripheral base pointers */
+#define SIM_BASE_PTRS                            { SIM }
+
+/*!
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
+ * @{
+ */
+
+/** SMC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t PMPROT;                             /**< Power Mode Protection register, offset: 0x0 */
+  __IO uint8_t PMCTRL;                             /**< Power Mode Control register, offset: 0x1 */
+  __IO uint8_t VLLSCTRL;                           /**< VLLS Control register, offset: 0x2 */
+  __I  uint8_t PMSTAT;                             /**< Power Mode Status register, offset: 0x3 */
+} SMC_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- SMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/*! @name PMPROT - Power Mode Protection register */
+#define SMC_PMPROT_AVLLS                         (0x2U)
+#define SMC_PMPROT_ALLS                          (0x8U)
+#define SMC_PMPROT_AVLP                          (0x20U)
+
+/*! @name PMCTRL - Power Mode Control register */
+#define SMC_PMCTRL_STOPM_MASK                    (0x7U)
+#define SMC_PMCTRL_STOPM_SHIFT                   (0U)
+#define SMC_PMCTRL_STOPM(x)                      (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA                         (0x8U)
+#define SMC_PMCTRL_RUNM_MASK                     (0x60U)
+#define SMC_PMCTRL_RUNM_SHIFT                    (5U)
+#define SMC_PMCTRL_RUNM(x)                       (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
+#define SMC_PMCTRL_LPWUI                         (0x80U)
+
+/*! @name VLLSCTRL - VLLS Control register */
+#define SMC_VLLSCTRL_VLLSM_MASK                  (0x7U)
+#define SMC_VLLSCTRL_VLLSM_SHIFT                 (0U)
+#define SMC_VLLSCTRL_VLLSM(x)                    (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_VLLSM_SHIFT)) & SMC_VLLSCTRL_VLLSM_MASK)
+#define SMC_VLLSCTRL_PORPO                       (0x20U)
+
+/*! @name PMSTAT - Power Mode Status register */
+#define SMC_PMSTAT_PMSTAT_MASK                   (0x7FU)
+#define SMC_PMSTAT_PMSTAT_SHIFT                  (0U)
+#define SMC_PMSTAT_PMSTAT(x)                     (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Masks */
+
+
+/* SMC - Peripheral instance base addresses */
+/** Peripheral SMC base address */
+#define SMC_BASE                                 (0x4007E000u)
+/** Peripheral SMC base pointer */
+#define SMC                                      ((SMC_TypeDef *)SMC_BASE)
+/** Array initializer of SMC peripheral base addresses */
+#define SMC_BASE_ADDRS                           { SMC_BASE }
+/** Array initializer of SMC peripheral base pointers */
+#define SMC_BASE_PTRS                            { SMC }
+
+/*!
+ * @}
+ */ /* end of group SMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SPI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< Module Configuration Register, offset: 0x0 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t TCR;                               /**< Transfer Count Register, offset: 0x8 */
+  union {                                          /* offset: 0xC */
+    __IO uint32_t CTAR[2];                           /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
+    __IO uint32_t CTAR_SLAVE[1];                     /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
+  };
+       uint8_t RESERVED_1[24];
+  __IO uint32_t SR;                                /**< Status Register, offset: 0x2C */
+  __IO uint32_t RSER;                              /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
+  union {                                          /* offset: 0x34 */
+    __IO uint32_t PUSHR;                             /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
+    __IO uint32_t PUSHR_SLAVE;                       /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
+  };
+  __I  uint32_t POPR;                              /**< POP RX FIFO Register, offset: 0x38 */
+  __I  uint32_t TXFR0;                             /**< Transmit FIFO Registers, offset: 0x3C */
+  __I  uint32_t TXFR1;                             /**< Transmit FIFO Registers, offset: 0x40 */
+  __I  uint32_t TXFR2;                             /**< Transmit FIFO Registers, offset: 0x44 */
+  __I  uint32_t TXFR3;                             /**< Transmit FIFO Registers, offset: 0x48 */
+       uint8_t RESERVED_2[48];
+  __I  uint32_t RXFR0;                             /**< Receive FIFO Registers, offset: 0x7C */
+  __I  uint32_t RXFR1;                             /**< Receive FIFO Registers, offset: 0x80 */
+  __I  uint32_t RXFR2;                             /**< Receive FIFO Registers, offset: 0x84 */
+  __I  uint32_t RXFR3;                             /**< Receive FIFO Registers, offset: 0x88 */
+} SPI_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- SPI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/*! @name MCR - Module Configuration Register */
+#define SPI_MCR_HALT                             (0x1U)
+#define SPI_MCR_SMPL_PT_MASK                     (0x300U)
+#define SPI_MCR_SMPL_PT_SHIFT                    (8U)
+#define SPI_MCR_SMPL_PT(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
+#define SPI_MCR_CLR_RXF                          (0x400U)
+#define SPI_MCR_CLR_TXF                          (0x800U)
+#define SPI_MCR_DIS_RXF                          (0x1000U)
+#define SPI_MCR_DIS_TXF                          (0x2000U)
+#define SPI_MCR_MDIS                             (0x4000U)
+#define SPI_MCR_DOZE                             (0x8000U)
+#define SPI_MCR_PCSIS_MASK                       (0x3F0000U)
+#define SPI_MCR_PCSIS_SHIFT                      (16U)
+#define SPI_MCR_PCSIS(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
+#define SPI_MCR_ROOE                             (0x1000000U)
+#define SPI_MCR_PCSSE                            (0x2000000U)
+#define SPI_MCR_MTFE                             (0x4000000U)
+#define SPI_MCR_FRZ                              (0x8000000U)
+#define SPI_MCR_DCONF_MASK                       (0x30000000U)
+#define SPI_MCR_DCONF_SHIFT                      (28U)
+#define SPI_MCR_DCONF(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
+#define SPI_MCR_CONT_SCKE                        (0x40000000U)
+#define SPI_MCR_MSTR                             (0x80000000U)
+
+/*! @name TCR - Transfer Count Register */
+#define SPI_TCR_SPI_TCNT_MASK                    (0xFFFF0000U)
+#define SPI_TCR_SPI_TCNT_SHIFT                   (16U)
+#define SPI_TCR_SPI_TCNT(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK)
+
+/*! @name CTAR - Clock and Transfer Attributes Register (In Master Mode) */
+#define SPI_CTAR_BR_MASK                         (0xFU)
+#define SPI_CTAR_BR_SHIFT                        (0U)
+#define SPI_CTAR_BR(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK)
+#define SPI_CTAR_DT_MASK                         (0xF0U)
+#define SPI_CTAR_DT_SHIFT                        (4U)
+#define SPI_CTAR_DT(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK)
+#define SPI_CTAR_ASC_MASK                        (0xF00U)
+#define SPI_CTAR_ASC_SHIFT                       (8U)
+#define SPI_CTAR_ASC(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK)
+#define SPI_CTAR_CSSCK_MASK                      (0xF000U)
+#define SPI_CTAR_CSSCK_SHIFT                     (12U)
+#define SPI_CTAR_CSSCK(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK)
+#define SPI_CTAR_PBR_MASK                        (0x30000U)
+#define SPI_CTAR_PBR_SHIFT                       (16U)
+#define SPI_CTAR_PBR(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)
+#define SPI_CTAR_PDT_MASK                        (0xC0000U)
+#define SPI_CTAR_PDT_SHIFT                       (18U)
+#define SPI_CTAR_PDT(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)
+#define SPI_CTAR_PASC_MASK                       (0x300000U)
+#define SPI_CTAR_PASC_SHIFT                      (20U)
+#define SPI_CTAR_PASC(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)
+#define SPI_CTAR_PCSSCK_MASK                     (0xC00000U)
+#define SPI_CTAR_PCSSCK_SHIFT                    (22U)
+#define SPI_CTAR_PCSSCK(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
+#define SPI_CTAR_LSBFE                           (0x1000000U)
+#define SPI_CTAR_CPHA                            (0x2000000U)
+#define SPI_CTAR_CPOL                            (0x4000000U)
+#define SPI_CTAR_FMSZ_MASK                       (0x78000000U)
+#define SPI_CTAR_FMSZ_SHIFT                      (27U)
+#define SPI_CTAR_FMSZ(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK)
+#define SPI_CTAR_DBR                             (0x80000000U)
+
+/* The count of SPI_CTAR */
+#define SPI_CTAR_COUNT                           (2U)
+
+/*! @name CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) */
+#define SPI_CTAR_SLAVE_CPHA                      (0x2000000U)
+#define SPI_CTAR_SLAVE_CPOL                      (0x4000000U)
+#define SPI_CTAR_SLAVE_FMSZ_MASK                 (0xF8000000U)
+#define SPI_CTAR_SLAVE_FMSZ_SHIFT                (27U)
+#define SPI_CTAR_SLAVE_FMSZ(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK)
+
+/* The count of SPI_CTAR_SLAVE */
+#define SPI_CTAR_SLAVE_COUNT                     (1U)
+
+/*! @name SR - Status Register */
+#define SPI_SR_POPNXTPTR_MASK                    (0xFU)
+#define SPI_SR_POPNXTPTR_SHIFT                   (0U)
+#define SPI_SR_POPNXTPTR(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK)
+#define SPI_SR_RXCTR_MASK                        (0xF0U)
+#define SPI_SR_RXCTR_SHIFT                       (4U)
+#define SPI_SR_RXCTR(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK)
+#define SPI_SR_TXNXTPTR_MASK                     (0xF00U)
+#define SPI_SR_TXNXTPTR_SHIFT                    (8U)
+#define SPI_SR_TXNXTPTR(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK)
+#define SPI_SR_TXCTR_MASK                        (0xF000U)
+#define SPI_SR_TXCTR_SHIFT                       (12U)
+#define SPI_SR_TXCTR(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK)
+#define SPI_SR_RFDF                              (0x20000U)
+#define SPI_SR_RFOF                              (0x80000U)
+#define SPI_SR_TFFF                              (0x2000000U)
+#define SPI_SR_TFUF                              (0x8000000U)
+#define SPI_SR_EOQF                              (0x10000000U)
+#define SPI_SR_TXRXS                             (0x40000000U)
+#define SPI_SR_TCF                               (0x80000000U)
+
+/*! @name RSER - DMA/Interrupt Request Select and Enable Register */
+#define SPI_RSER_RFDF_DIRS                       (0x10000U)
+#define SPI_RSER_RFDF_RE                         (0x20000U)
+#define SPI_RSER_RFOF_RE                         (0x80000U)
+#define SPI_RSER_TFFF_DIRS                       (0x1000000U)
+#define SPI_RSER_TFFF_RE                         (0x2000000U)
+#define SPI_RSER_TFUF_RE                         (0x8000000U)
+#define SPI_RSER_EOQF_RE                         (0x10000000U)
+#define SPI_RSER_TCF_RE                          (0x80000000U)
+
+/*! @name PUSHR - PUSH TX FIFO Register In Master Mode */
+#define SPI_PUSHR_TXDATA_MASK                    (0xFFFFU)
+#define SPI_PUSHR_TXDATA_SHIFT                   (0U)
+#define SPI_PUSHR_TXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK)
+#define SPI_PUSHR_PCS_MASK                       (0x3F0000U)
+#define SPI_PUSHR_PCS_SHIFT                      (16U)
+#define SPI_PUSHR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)
+#define SPI_PUSHR_CTCNT                          (0x4000000U)
+#define SPI_PUSHR_EOQ                            (0x8000000U)
+#define SPI_PUSHR_CTAS_MASK                      (0x70000000U)
+#define SPI_PUSHR_CTAS_SHIFT                     (28U)
+#define SPI_PUSHR_CTAS(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)
+#define SPI_PUSHR_CONT                           (0x80000000U)
+
+/*! @name TXFR0 - Transmit FIFO Registers */
+#define SPI_TXFR0_TXDATA_MASK                    (0xFFFFU)
+#define SPI_TXFR0_TXDATA_SHIFT                   (0U)
+#define SPI_TXFR0_TXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK)
+#define SPI_TXFR0_TXCMD_TXDATA_MASK              (0xFFFF0000U)
+#define SPI_TXFR0_TXCMD_TXDATA_SHIFT             (16U)
+#define SPI_TXFR0_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK)
+
+/*! @name TXFR1 - Transmit FIFO Registers */
+#define SPI_TXFR1_TXDATA_MASK                    (0xFFFFU)
+#define SPI_TXFR1_TXDATA_SHIFT                   (0U)
+#define SPI_TXFR1_TXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK)
+#define SPI_TXFR1_TXCMD_TXDATA_MASK              (0xFFFF0000U)
+#define SPI_TXFR1_TXCMD_TXDATA_SHIFT             (16U)
+#define SPI_TXFR1_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK)
+
+/*! @name TXFR2 - Transmit FIFO Registers */
+#define SPI_TXFR2_TXDATA_MASK                    (0xFFFFU)
+#define SPI_TXFR2_TXDATA_SHIFT                   (0U)
+#define SPI_TXFR2_TXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK)
+#define SPI_TXFR2_TXCMD_TXDATA_MASK              (0xFFFF0000U)
+#define SPI_TXFR2_TXCMD_TXDATA_SHIFT             (16U)
+#define SPI_TXFR2_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK)
+
+/*! @name TXFR3 - Transmit FIFO Registers */
+#define SPI_TXFR3_TXDATA_MASK                    (0xFFFFU)
+#define SPI_TXFR3_TXDATA_SHIFT                   (0U)
+#define SPI_TXFR3_TXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK)
+#define SPI_TXFR3_TXCMD_TXDATA_MASK              (0xFFFF0000U)
+#define SPI_TXFR3_TXCMD_TXDATA_SHIFT             (16U)
+#define SPI_TXFR3_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK)
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE                                (0x4002C000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0                                     ((SPI_TypeDef *)SPI0_BASE)
+/** Peripheral SPI1 base address */
+#define SPI1_BASE                                (0x4002D000u)
+/** Peripheral SPI1 base pointer */
+#define SPI1                                     ((SPI_TypeDef *)SPI1_BASE)
+/** Peripheral SPI2 base address */
+#define SPI2_BASE                                (0x400AC000u)
+/** Peripheral SPI2 base pointer */
+#define SPI2                                     ((SPI_TypeDef *)SPI2_BASE)
+/** Array initializer of SPI peripheral base addresses */
+#define SPI_BASE_ADDRS                           { SPI0_BASE, SPI1_BASE, SPI2_BASE }
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASE_PTRS                            { SPI0, SPI1, SPI2 }
+/** Interrupt vectors for the SPI peripheral type */
+#define SPI_IRQS                                 { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- UART Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
+ * @{
+ */
+
+/** UART - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t BDH;                                /**< UART Baud Rate Registers: High, offset: 0x0 */
+  __IO uint8_t BDL;                                /**< UART Baud Rate Registers: Low, offset: 0x1 */
+  __IO uint8_t C1;                                 /**< UART Control Register 1, offset: 0x2 */
+  __IO uint8_t C2;                                 /**< UART Control Register 2, offset: 0x3 */
+  __I  uint8_t S1;                                 /**< UART Status Register 1, offset: 0x4 */
+  __IO uint8_t S2;                                 /**< UART Status Register 2, offset: 0x5 */
+  __IO uint8_t C3;                                 /**< UART Control Register 3, offset: 0x6 */
+  __IO uint8_t D;                                  /**< UART Data Register, offset: 0x7 */
+  __IO uint8_t MA1;                                /**< UART Match Address Registers 1, offset: 0x8 */
+  __IO uint8_t MA2;                                /**< UART Match Address Registers 2, offset: 0x9 */
+  __IO uint8_t C4;                                 /**< UART Control Register 4, offset: 0xA */
+  __IO uint8_t C5;                                 /**< UART Control Register 5, offset: 0xB */
+  __I  uint8_t ED;                                 /**< UART Extended Data Register, offset: 0xC */
+  __IO uint8_t MODEM;                              /**< UART Modem Register, offset: 0xD */
+  __IO uint8_t IR;                                 /**< UART Infrared Register, offset: 0xE */
+       uint8_t RESERVED_0[1];
+  __IO uint8_t PFIFO;                              /**< UART FIFO Parameters, offset: 0x10 */
+  __IO uint8_t CFIFO;                              /**< UART FIFO Control Register, offset: 0x11 */
+  __IO uint8_t SFIFO;                              /**< UART FIFO Status Register, offset: 0x12 */
+  __IO uint8_t TWFIFO;                             /**< UART FIFO Transmit Watermark, offset: 0x13 */
+  __I  uint8_t TCFIFO;                             /**< UART FIFO Transmit Count, offset: 0x14 */
+  __IO uint8_t RWFIFO;                             /**< UART FIFO Receive Watermark, offset: 0x15 */
+  __I  uint8_t RCFIFO;                             /**< UART FIFO Receive Count, offset: 0x16 */
+       uint8_t RESERVED_1[1];
+  __IO uint8_t C7816;                              /**< UART 7816 Control Register, offset: 0x18 */
+  __IO uint8_t IE7816;                             /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
+  __IO uint8_t IS7816;                             /**< UART 7816 Interrupt Status Register, offset: 0x1A */
+  union {                                          /* offset: 0x1B */
+    __IO uint8_t WP7816T0;                           /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+    __IO uint8_t WP7816T1;                           /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+  };
+  __IO uint8_t WN7816;                             /**< UART 7816 Wait N Register, offset: 0x1C */
+  __IO uint8_t WF7816;                             /**< UART 7816 Wait FD Register, offset: 0x1D */
+  __IO uint8_t ET7816;                             /**< UART 7816 Error Threshold Register, offset: 0x1E */
+  __IO uint8_t TL7816;                             /**< UART 7816 Transmit Length Register, offset: 0x1F */
+} UART_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- UART Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Masks UART Register Masks
+ * @{
+ */
+
+/*! @name BDH - UART Baud Rate Registers: High */
+#define UARTx_BDH_SBR_MASK                       (0x1FU)
+#define UARTx_BDH_SBR_SHIFT                      (0U)
+#define UARTx_BDH_SBR(x)                         (((uint8_t)(((uint8_t)(x)) << UARTx_BDH_SBR_SHIFT)) & UARTx_BDH_SBR_MASK)
+#define UARTx_BDH_SBNS                           (0x20U)
+#define UARTx_BDH_RXEDGIE                        (0x40U)
+#define UARTx_BDH_LBKDIE                         (0x80U)
+
+/*! @name BDL - UART Baud Rate Registers: Low */
+#define UARTx_BDL_SBR_MASK                       (0xFFU)
+#define UARTx_BDL_SBR_SHIFT                      (0U)
+#define UARTx_BDL_SBR(x)                         (((uint8_t)(((uint8_t)(x)) << UARTx_BDL_SBR_SHIFT)) & UARTx_BDL_SBR_MASK)
+
+/*! @name C1 - UART Control Register 1 */
+#define UARTx_C1_PT                              (0x1U)
+#define UARTx_C1_PE                              (0x2U)
+#define UARTx_C1_ILT                             (0x4U)
+#define UARTx_C1_WAKE                            (0x8U)
+#define UARTx_C1_M                               (0x10U)
+#define UARTx_C1_RSRC                            (0x20U)
+#define UARTx_C1_UARTSWAI                        (0x40U)
+#define UARTx_C1_LOOPS                           (0x80U)
+
+/*! @name C2 - UART Control Register 2 */
+#define UARTx_C2_SBK                             (0x1U)
+#define UARTx_C2_RWU                             (0x2U)
+#define UARTx_C2_RE                              (0x4U)
+#define UARTx_C2_TE                              (0x8U)
+#define UARTx_C2_ILIE                            (0x10U)
+#define UARTx_C2_RIE                             (0x20U)
+#define UARTx_C2_TCIE                            (0x40U)
+#define UARTx_C2_TIE                             (0x80U)
+
+/*! @name S1 - UART Status Register 1 */
+#define UARTx_S1_PF                              (0x1U)
+#define UARTx_S1_FE                              (0x2U)
+#define UARTx_S1_NF                              (0x4U)
+#define UARTx_S1_OR                              (0x8U)
+#define UARTx_S1_IDLE                            (0x10U)
+#define UARTx_S1_RDRF                            (0x20U)
+#define UARTx_S1_TC                              (0x40U)
+#define UARTx_S1_TDRE                            (0x80U)
+
+/*! @name S2 - UART Status Register 2 */
+#define UARTx_S2_RAF                             (0x1U)
+#define UARTx_S2_LBKDE                           (0x2U)
+#define UARTx_S2_BRK13                           (0x4U)
+#define UARTx_S2_RWUID                           (0x8U)
+#define UARTx_S2_RXINV                           (0x10U)
+#define UARTx_S2_MSBF                            (0x20U)
+#define UARTx_S2_RXEDGIF                         (0x40U)
+#define UARTx_S2_LBKDIF                          (0x80U)
+
+/*! @name C3 - UART Control Register 3 */
+#define UARTx_C3_PEIE                            (0x1U)
+#define UARTx_C3_FEIE                            (0x2U)
+#define UARTx_C3_NEIE                            (0x4U)
+#define UARTx_C3_ORIE                            (0x8U)
+#define UARTx_C3_TXINV                           (0x10U)
+#define UARTx_C3_TXDIR                           (0x20U)
+#define UARTx_C3_T8                              (0x40U)
+#define UARTx_C3_R8                              (0x80U)
+
+/*! @name C4 - UART Control Register 4 */
+#define UARTx_C4_BRFA_MASK                       (0x1FU)
+#define UARTx_C4_BRFA_SHIFT                      (0U)
+#define UARTx_C4_BRFA(x)                         (((uint8_t)(((uint8_t)(x)) << UARTx_C4_BRFA_SHIFT)) & UARTx_C4_BRFA_MASK)
+#define UARTx_C4_M10                             (0x20U)
+#define UARTx_C4_MAEN2                           (0x40U)
+#define UARTx_C4_MAEN1                           (0x80U)
+
+/*! @name C5 - UART Control Register 5 */
+#define UARTx_C5_LBKDDMAS                        (0x8U)
+#define UARTx_C5_ILDMAS                          (0x10U)
+#define UARTx_C5_RDMAS                           (0x20U)
+#define UARTx_C5_TCDMAS                          (0x40U)
+#define UARTx_C5_TDMAS                           (0x80U)
+
+/*! @name ED - UART Extended Data Register */
+#define UARTx_ED_PARITYE                         (0x40U)
+#define UARTx_ED_NOISY                           (0x80U)
+
+/*! @name MODEM - UART Modem Register */
+#define UARTx_MODEM_TXCTSE                       (0x1U)
+#define UARTx_MODEM_TXRTSE                       (0x2U)
+#define UARTx_MODEM_TXRTSPOL                     (0x4U)
+#define UARTx_MODEM_RXRTSE                       (0x8U)
+
+/*! @name IR - UART Infrared Register */
+#define UART_IR_TNP_MASK                         (0x3U)
+#define UART_IR_TNP_SHIFT                        (0U)
+#define UART_IR_TNP(x)                           (((uint8_t)(((uint8_t)(x)) << UART_IR_TNP_SHIFT)) & UART_IR_TNP_MASK)
+#define UART_IR_IREN                             (0x4U)
+
+/*! @name PFIFO - UART FIFO Parameters */
+#define UART_PFIFO_RXFIFOSIZE_MASK               (0x7U)
+#define UART_PFIFO_RXFIFOSIZE_SHIFT              (0U)
+#define UART_PFIFO_RXFIFOSIZE(x)                 (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFIFOSIZE_SHIFT)) & UART_PFIFO_RXFIFOSIZE_MASK)
+#define UART_PFIFO_RXFE                          (0x8U)
+#define UART_PFIFO_TXFIFOSIZE_MASK               (0x70U)
+#define UART_PFIFO_TXFIFOSIZE_SHIFT              (4U)
+#define UART_PFIFO_TXFIFOSIZE(x)                 (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFIFOSIZE_SHIFT)) & UART_PFIFO_TXFIFOSIZE_MASK)
+#define UART_PFIFO_TXFE                          (0x80U)
+
+/*! @name CFIFO - UART FIFO Control Register */
+#define UART_CFIFO_RXUFE                         (0x1U)
+#define UART_CFIFO_TXOFE                         (0x2U)
+#define UART_CFIFO_RXOFE                         (0x4U)
+#define UART_CFIFO_RXFLUSH                       (0x40U)
+#define UART_CFIFO_TXFLUSH                       (0x80U)
+
+/*! @name SFIFO - UART FIFO Status Register */
+#define UART_SFIFO_RXUF                          (0x1U)
+#define UART_SFIFO_TXOF                          (0x2U)
+#define UART_SFIFO_RXOF                          (0x4U)
+#define UART_SFIFO_RXEMPT                        (0x40U)
+#define UART_SFIFO_TXEMPT                        (0x80U)
+
+/*! @name TWFIFO - UART FIFO Transmit Watermark */
+#define UART_TWFIFO_TXWATER_MASK                 (0xFFU)
+#define UART_TWFIFO_TXWATER_SHIFT                (0U)
+#define UART_TWFIFO_TXWATER(x)                   (((uint8_t)(((uint8_t)(x)) << UART_TWFIFO_TXWATER_SHIFT)) & UART_TWFIFO_TXWATER_MASK)
+
+/*! @name TCFIFO - UART FIFO Transmit Count */
+#define UART_TCFIFO_TXCOUNT_MASK                 (0xFFU)
+#define UART_TCFIFO_TXCOUNT_SHIFT                (0U)
+#define UART_TCFIFO_TXCOUNT(x)                   (((uint8_t)(((uint8_t)(x)) << UART_TCFIFO_TXCOUNT_SHIFT)) & UART_TCFIFO_TXCOUNT_MASK)
+
+/*! @name RWFIFO - UART FIFO Receive Watermark */
+#define UART_RWFIFO_RXWATER_MASK                 (0xFFU)
+#define UART_RWFIFO_RXWATER_SHIFT                (0U)
+#define UART_RWFIFO_RXWATER(x)                   (((uint8_t)(((uint8_t)(x)) << UART_RWFIFO_RXWATER_SHIFT)) & UART_RWFIFO_RXWATER_MASK)
+
+/*! @name RCFIFO - UART FIFO Receive Count */
+#define UART_RCFIFO_RXCOUNT_MASK                 (0xFFU)
+#define UART_RCFIFO_RXCOUNT_SHIFT                (0U)
+#define UART_RCFIFO_RXCOUNT(x)                   (((uint8_t)(((uint8_t)(x)) << UART_RCFIFO_RXCOUNT_SHIFT)) & UART_RCFIFO_RXCOUNT_MASK)
+
+/*! @name C7816 - UART 7816 Control Register */
+#define UART_C7816_ISO_7816E                     (0x1U)
+#define UART_C7816_TTYPE                         (0x2U)
+#define UART_C7816_INIT                          (0x4U)
+#define UART_C7816_ANACK                         (0x8U)
+#define UART_C7816_ONACK                         (0x10U)
+
+/*! @name IE7816 - UART 7816 Interrupt Enable Register */
+#define UART_IE7816_RXTE                         (0x1U)
+#define UART_IE7816_TXTE                         (0x2U)
+#define UART_IE7816_GTVE                         (0x4U)
+#define UART_IE7816_INITDE                       (0x10U)
+#define UART_IE7816_BWTE                         (0x20U)
+#define UART_IE7816_CWTE                         (0x40U)
+#define UART_IE7816_WTE                          (0x80U)
+
+/*! @name IS7816 - UART 7816 Interrupt Status Register */
+#define UART_IS7816_RXT                          (0x1U)
+#define UART_IS7816_TXT                          (0x2U)
+#define UART_IS7816_GTV                          (0x4U)
+#define UART_IS7816_INITD                        (0x10U)
+#define UART_IS7816_BWT                          (0x20U)
+#define UART_IS7816_CWT                          (0x40U)
+#define UART_IS7816_WT                           (0x80U)
+
+/*! @name WP7816T0 - UART 7816 Wait Parameter Register */
+#define UART_WP7816T0_WI_MASK                    (0xFFU)
+#define UART_WP7816T0_WI_SHIFT                   (0U)
+#define UART_WP7816T0_WI(x)                      (((uint8_t)(((uint8_t)(x)) << UART_WP7816T0_WI_SHIFT)) & UART_WP7816T0_WI_MASK)
+
+/*! @name WP7816T1 - UART 7816 Wait Parameter Register */
+#define UART_WP7816T1_BWI_MASK                   (0xFU)
+#define UART_WP7816T1_BWI_SHIFT                  (0U)
+#define UART_WP7816T1_BWI(x)                     (((uint8_t)(((uint8_t)(x)) << UART_WP7816T1_BWI_SHIFT)) & UART_WP7816T1_BWI_MASK)
+#define UART_WP7816T1_CWI_MASK                   (0xF0U)
+#define UART_WP7816T1_CWI_SHIFT                  (4U)
+#define UART_WP7816T1_CWI(x)                     (((uint8_t)(((uint8_t)(x)) << UART_WP7816T1_CWI_SHIFT)) & UART_WP7816T1_CWI_MASK)
+
+/*! @name WN7816 - UART 7816 Wait N Register */
+#define UART_WN7816_GTN_MASK                     (0xFFU)
+#define UART_WN7816_GTN_SHIFT                    (0U)
+#define UART_WN7816_GTN(x)                       (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK)
+
+/*! @name WF7816 - UART 7816 Wait FD Register */
+#define UART_WF7816_GTFD_MASK                    (0xFFU)
+#define UART_WF7816_GTFD_SHIFT                   (0U)
+#define UART_WF7816_GTFD(x)                      (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK)
+
+/*! @name ET7816 - UART 7816 Error Threshold Register */
+#define UART_ET7816_RXTHRESHOLD_MASK             (0xFU)
+#define UART_ET7816_RXTHRESHOLD_SHIFT            (0U)
+#define UART_ET7816_RXTHRESHOLD(x)               (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK)
+#define UART_ET7816_TXTHRESHOLD_MASK             (0xF0U)
+#define UART_ET7816_TXTHRESHOLD_SHIFT            (4U)
+#define UART_ET7816_TXTHRESHOLD(x)               (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK)
+
+/*! @name TL7816 - UART 7816 Transmit Length Register */
+#define UART_TL7816_TLEN_MASK                    (0xFFU)
+#define UART_TL7816_TLEN_SHIFT                   (0U)
+#define UART_TL7816_TLEN(x)                      (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Masks */
+
+
+/* UART - Peripheral instance base addresses */
+/** Peripheral UART0 base address */
+#define UART0_BASE                               (0x4006A000u)
+/** Peripheral UART0 base pointer */
+#define UART0                                    ((UART_TypeDef *)UART0_BASE)
+/** Peripheral UART1 base address */
+#define UART1_BASE                               (0x4006B000u)
+/** Peripheral UART1 base pointer */
+#define UART1                                    ((UART_TypeDef *)UART1_BASE)
+/** Peripheral UART2 base address */
+#define UART2_BASE                               (0x4006C000u)
+/** Peripheral UART2 base pointer */
+#define UART2                                    ((UART_TypeDef *)UART2_BASE)
+/** Peripheral UART3 base address */
+#define UART3_BASE                               (0x4006D000u)
+/** Peripheral UART3 base pointer */
+#define UART3                                    ((UART_TypeDef *)UART3_BASE)
+/** Peripheral UART4 base address */
+#define UART4_BASE                               (0x400EA000u)
+/** Peripheral UART4 base pointer */
+#define UART4                                    ((UART_TypeDef *)UART4_BASE)
+/** Peripheral UART5 base address */
+#define UART5_BASE                               (0x400EB000u)
+/** Peripheral UART5 base pointer */
+#define UART5                                    ((UART_TypeDef *)UART5_BASE)
+/** Array initializer of UART peripheral base addresses */
+#define UART_BASE_ADDRS                          { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE, UART5_BASE }
+/** Array initializer of UART peripheral base pointers */
+#define UART_BASE_PTRS                           { UART0, UART1, UART2, UART3, UART4, UART5 }
+/** Interrupt vectors for the UART peripheral type */
+#define UARTStatus_IRQS                          { UART0Status_IRQn, UART1Status_IRQn, UART2Status_IRQn, UART3Status_IRQn, UART4Status_IRQn, UART5Status_IRQn }
+#define UARTError_IRQS                           { UART0Error_IRQn, UART1Error_IRQn, UART2Error_IRQn, UART3Error_IRQn, UART4Error_IRQn, UART5Error_IRQn }
+#define UART_LON_IRQS                            { UART0_LON_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }
+
+/*!
+ * @}
+ */ /* end of group UART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t PERID;                              /**< Peripheral ID register, offset: 0x0 */
+       uint8_t RESERVED_0[3];
+  __I  uint8_t IDCOMP;                             /**< Peripheral ID Complement register, offset: 0x4 */
+       uint8_t RESERVED_1[3];
+  __I  uint8_t REV;                                /**< Peripheral Revision register, offset: 0x8 */
+       uint8_t RESERVED_2[3];
+  __I  uint8_t ADDINFO;                            /**< Peripheral Additional Info register, offset: 0xC */
+       uint8_t RESERVED_3[3];
+  __IO uint8_t OTGISTAT;                           /**< OTG Interrupt Status register, offset: 0x10 */
+       uint8_t RESERVED_4[3];
+  __IO uint8_t OTGICR;                             /**< OTG Interrupt Control register, offset: 0x14 */
+       uint8_t RESERVED_5[3];
+  __IO uint8_t OTGSTAT;                            /**< OTG Status register, offset: 0x18 */
+       uint8_t RESERVED_6[3];
+  __IO uint8_t OTGCTL;                             /**< OTG Control register, offset: 0x1C */
+       uint8_t RESERVED_7[99];
+  __IO uint8_t ISTAT;                              /**< Interrupt Status register, offset: 0x80 */
+       uint8_t RESERVED_8[3];
+  __IO uint8_t INTEN;                              /**< Interrupt Enable register, offset: 0x84 */
+       uint8_t RESERVED_9[3];
+  __IO uint8_t ERRSTAT;                            /**< Error Interrupt Status register, offset: 0x88 */
+       uint8_t RESERVED_10[3];
+  __IO uint8_t ERREN;                              /**< Error Interrupt Enable register, offset: 0x8C */
+       uint8_t RESERVED_11[3];
+  __I  uint8_t STAT;                               /**< Status register, offset: 0x90 */
+       uint8_t RESERVED_12[3];
+  __IO uint8_t CTL;                                /**< Control register, offset: 0x94 */
+       uint8_t RESERVED_13[3];
+  __IO uint8_t ADDR;                               /**< Address register, offset: 0x98 */
+       uint8_t RESERVED_14[3];
+  __IO uint8_t BDTPAGE1;                           /**< BDT Page register 1, offset: 0x9C */
+       uint8_t RESERVED_15[3];
+  __IO uint8_t FRMNUML;                            /**< Frame Number register Low, offset: 0xA0 */
+       uint8_t RESERVED_16[3];
+  __IO uint8_t FRMNUMH;                            /**< Frame Number register High, offset: 0xA4 */
+       uint8_t RESERVED_17[3];
+  __IO uint8_t TOKEN;                              /**< Token register, offset: 0xA8 */
+       uint8_t RESERVED_18[3];
+  __IO uint8_t SOFTHLD;                            /**< SOF Threshold register, offset: 0xAC */
+       uint8_t RESERVED_19[3];
+  __IO uint8_t BDTPAGE2;                           /**< BDT Page Register 2, offset: 0xB0 */
+       uint8_t RESERVED_20[3];
+  __IO uint8_t BDTPAGE3;                           /**< BDT Page Register 3, offset: 0xB4 */
+       uint8_t RESERVED_21[11];
+  struct {                                         /* offset: 0xC0, array step: 0x4 */
+    __IO uint8_t ENDPT;                              /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
+         uint8_t RESERVED_0[3];
+  } ENDPOINT[16];
+  __IO uint8_t USBCTRL;                            /**< USB Control register, offset: 0x100 */
+       uint8_t RESERVED_22[3];
+  __I  uint8_t OBSERVE;                            /**< USB OTG Observe register, offset: 0x104 */
+       uint8_t RESERVED_23[3];
+  __IO uint8_t CONTROL;                            /**< USB OTG Control register, offset: 0x108 */
+       uint8_t RESERVED_24[3];
+  __IO uint8_t USBTRC0;                            /**< USB Transceiver Control register 0, offset: 0x10C */
+       uint8_t RESERVED_25[7];
+  __IO uint8_t USBFRMADJUST;                       /**< Frame Adjust Register, offset: 0x114 */
+       uint8_t RESERVED_26[43];
+  __IO uint8_t CLK_RECOVER_CTRL;                   /**< USB Clock recovery control, offset: 0x140 */
+       uint8_t RESERVED_27[3];
+  __IO uint8_t CLK_RECOVER_IRC_EN;                 /**< IRC48M oscillator enable register, offset: 0x144 */
+       uint8_t RESERVED_28[23];
+  __IO uint8_t CLK_RECOVER_INT_STATUS;             /**< Clock recovery separated interrupt status, offset: 0x15C */
+} USB_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- USB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/*! @name PERID - Peripheral ID register */
+#define USB_PERID_ID_MASK                        (0x3FU)
+#define USB_PERID_ID_SHIFT                       (0U)
+#define USB_PERID_ID(x)                          (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
+
+/*! @name IDCOMP - Peripheral ID Complement register */
+#define USB_IDCOMP_NID_MASK                      (0x3FU)
+#define USB_IDCOMP_NID_SHIFT                     (0U)
+#define USB_IDCOMP_NID(x)                        (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
+
+/*! @name REV - Peripheral Revision register */
+#define USB_REV_REV_MASK                         (0xFFU)
+#define USB_REV_REV_SHIFT                        (0U)
+#define USB_REV_REV(x)                           (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
+
+/*! @name ADDINFO - Peripheral Additional Info register */
+#define USB_ADDINFO_IEHOST                       (0x1U)
+#define USB_ADDINFO_IRQNUM_MASK                  (0xF8U)
+#define USB_ADDINFO_IRQNUM_SHIFT                 (3U)
+#define USB_ADDINFO_IRQNUM(x)                    (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IRQNUM_SHIFT)) & USB_ADDINFO_IRQNUM_MASK)
+
+/*! @name OTGISTAT - OTG Interrupt Status register */
+#define USB_OTGISTAT_AVBUSCHG                    (0x1U)
+#define USB_OTGISTAT_B_SESS_CHG                  (0x4U)
+#define USB_OTGISTAT_SESSVLDCHG                  (0x8U)
+#define USB_OTGISTAT_LINE_STATE_CHG              (0x20U)
+#define USB_OTGISTAT_ONEMSEC                     (0x40U)
+#define USB_OTGISTAT_IDCHG                       (0x80U)
+
+/*! @name OTGICR - OTG Interrupt Control register */
+#define USB_OTGICR_AVBUSEN                       (0x1U)
+#define USB_OTGICR_BSESSEN                       (0x4U)
+#define USB_OTGICR_SESSVLDEN                     (0x8U)
+#define USB_OTGICR_LINESTATEEN                   (0x20U)
+#define USB_OTGICR_ONEMSECEN                     (0x40U)
+#define USB_OTGICR_IDEN                          (0x80U)
+
+/*! @name OTGSTAT - OTG Status register */
+#define USB_OTGSTAT_AVBUSVLD                     (0x1U)
+#define USB_OTGSTAT_BSESSEND                     (0x4U)
+#define USB_OTGSTAT_SESS_VLD                     (0x8U)
+#define USB_OTGSTAT_LINESTATESTABLE              (0x20U)
+#define USB_OTGSTAT_ONEMSECEN                    (0x40U)
+#define USB_OTGSTAT_ID                           (0x80U)
+
+/*! @name OTGCTL - OTG Control register */
+#define USB_OTGCTL_OTGEN                         (0x4U)
+#define USB_OTGCTL_DMLOW                         (0x10U)
+#define USB_OTGCTL_DPLOW                         (0x20U)
+#define USB_OTGCTL_DPHIGH                        (0x80U)
+
+/*! @name ISTAT - Interrupt Status register */
+#define USB_ISTAT_USBRST                         (0x1U)
+#define USB_ISTAT_ERROR                          (0x2U)
+#define USB_ISTAT_SOFTOK                         (0x4U)
+#define USB_ISTAT_TOKDNE                         (0x8U)
+#define USB_ISTAT_SLEEP                          (0x10U)
+#define USB_ISTAT_RESUME                         (0x20U)
+#define USB_ISTAT_ATTACH                         (0x40U)
+#define USB_ISTAT_STALL                          (0x80U)
+
+/*! @name INTEN - Interrupt Enable register */
+#define USB_INTEN_USBRSTEN                       (0x1U)
+#define USB_INTEN_ERROREN                        (0x2U)
+#define USB_INTEN_SOFTOKEN                       (0x4U)
+#define USB_INTEN_TOKDNEEN                       (0x8U)
+#define USB_INTEN_SLEEPEN                        (0x10U)
+#define USB_INTEN_RESUMEEN                       (0x20U)
+#define USB_INTEN_ATTACHEN                       (0x40U)
+#define USB_INTEN_STALLEN                        (0x80U)
+
+/*! @name ERRSTAT - Error Interrupt Status register */
+#define USB_ERRSTAT_PIDERR                       (0x1U)
+#define USB_ERRSTAT_CRC5EOF                      (0x2U)
+#define USB_ERRSTAT_CRC16                        (0x4U)
+#define USB_ERRSTAT_DFN8                         (0x8U)
+#define USB_ERRSTAT_BTOERR                       (0x10U)
+#define USB_ERRSTAT_DMAERR                       (0x20U)
+#define USB_ERRSTAT_BTSERR                       (0x80U)
+
+/*! @name ERREN - Error Interrupt Enable register */
+#define USB_ERREN_PIDERREN                       (0x1U)
+#define USB_ERREN_CRC5EOFEN                      (0x2U)
+#define USB_ERREN_CRC16EN                        (0x4U)
+#define USB_ERREN_DFN8EN                         (0x8U)
+#define USB_ERREN_BTOERREN                       (0x10U)
+#define USB_ERREN_DMAERREN                       (0x20U)
+#define USB_ERREN_BTSERREN                       (0x80U)
+
+/*! @name STAT - Status register */
+#define USB_STAT_ODD                             (0x4U)
+#define USB_STAT_TX                              (0x8U)
+#define USB_STAT_ENDP_MASK                       (0xF0U)
+#define USB_STAT_ENDP_SHIFT                      (4U)
+#define USB_STAT_ENDP(x)                         (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
+
+/*! @name CTL - Control register */
+#define USB_CTL_USBENSOFEN                       (0x1U)
+#define USB_CTL_ODDRST                           (0x2U)
+#define USB_CTL_RESUME                           (0x4U)
+#define USB_CTL_HOSTMODEEN                       (0x8U)
+#define USB_CTL_RESET                            (0x10U)
+#define USB_CTL_TXSUSPENDTOKENBUSY               (0x20U)
+#define USB_CTL_SE0                              (0x40U)
+#define USB_CTL_JSTATE                           (0x80U)
+
+/*! @name ADDR - Address register */
+#define USB_ADDR_ADDR_MASK                       (0x7FU)
+#define USB_ADDR_ADDR_SHIFT                      (0U)
+#define USB_ADDR_ADDR(x)                         (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
+#define USB_ADDR_LSEN                            (0x80U)
+
+/*! @name BDTPAGE1 - BDT Page register 1 */
+#define USB_BDTPAGE1_BDTBA_MASK                  (0xFEU)
+#define USB_BDTPAGE1_BDTBA_SHIFT                 (1U)
+#define USB_BDTPAGE1_BDTBA(x)                    (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
+
+/*! @name FRMNUML - Frame Number register Low */
+#define USB_FRMNUML_FRM_MASK                     (0xFFU)
+#define USB_FRMNUML_FRM_SHIFT                    (0U)
+#define USB_FRMNUML_FRM(x)                       (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
+
+/*! @name FRMNUMH - Frame Number register High */
+#define USB_FRMNUMH_FRM_MASK                     (0x7U)
+#define USB_FRMNUMH_FRM_SHIFT                    (0U)
+#define USB_FRMNUMH_FRM(x)                       (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
+
+/*! @name TOKEN - Token register */
+#define USB_TOKEN_TOKENENDPT_MASK                (0xFU)
+#define USB_TOKEN_TOKENENDPT_SHIFT               (0U)
+#define USB_TOKEN_TOKENENDPT(x)                  (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK)
+#define USB_TOKEN_TOKENPID_MASK                  (0xF0U)
+#define USB_TOKEN_TOKENPID_SHIFT                 (4U)
+#define USB_TOKEN_TOKENPID(x)                    (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK)
+
+/*! @name SOFTHLD - SOF Threshold register */
+#define USB_SOFTHLD_CNT_MASK                     (0xFFU)
+#define USB_SOFTHLD_CNT_SHIFT                    (0U)
+#define USB_SOFTHLD_CNT(x)                       (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK)
+
+/*! @name BDTPAGE2 - BDT Page Register 2 */
+#define USB_BDTPAGE2_BDTBA_MASK                  (0xFFU)
+#define USB_BDTPAGE2_BDTBA_SHIFT                 (0U)
+#define USB_BDTPAGE2_BDTBA(x)                    (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
+
+/*! @name BDTPAGE3 - BDT Page Register 3 */
+#define USB_BDTPAGE3_BDTBA_MASK                  (0xFFU)
+#define USB_BDTPAGE3_BDTBA_SHIFT                 (0U)
+#define USB_BDTPAGE3_BDTBA(x)                    (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
+
+/*! @name ENDPT - Endpoint Control register */
+#define USB_ENDPT_EPHSHK                         (0x1U)
+#define USB_ENDPT_EPSTALL                        (0x2U)
+#define USB_ENDPT_EPTXEN                         (0x4U)
+#define USB_ENDPT_EPRXEN                         (0x8U)
+#define USB_ENDPT_EPCTLDIS                       (0x10U)
+#define USB_ENDPT_RETRYDIS                       (0x40U)
+#define USB_ENDPT_HOSTWOHUB                      (0x80U)
+
+/* The count of USB_ENDPT */
+#define USB_ENDPT_COUNT                          (16U)
+
+/*! @name USBCTRL - USB Control register */
+#define USB_USBCTRL_PDE                          (0x40U)
+#define USB_USBCTRL_SUSP                         (0x80U)
+
+/*! @name OBSERVE - USB OTG Observe register */
+#define USB_OBSERVE_DMPD                         (0x10U)
+#define USB_OBSERVE_DPPD                         (0x40U)
+#define USB_OBSERVE_DPPU                         (0x80U)
+
+/*! @name CONTROL - USB OTG Control register */
+#define USB_CONTROL_DPPULLUPNONOTG               (0x10U)
+
+/*! @name USBTRC0 - USB Transceiver Control register 0 */
+#define USB_USBTRC0_USB_RESUME_INT               (0x1U)
+#define USB_USBTRC0_SYNC_DET                     (0x2U)
+#define USB_USBTRC0_USB_CLK_RECOVERY_INT         (0x4U)
+#define USB_USBTRC0_USBRESMEN                    (0x20U)
+#define USB_USBTRC0_USBRESET                     (0x80U)
+
+/*! @name USBFRMADJUST - Frame Adjust Register */
+#define USB_USBFRMADJUST_ADJ_MASK                (0xFFU)
+#define USB_USBFRMADJUST_ADJ_SHIFT               (0U)
+#define USB_USBFRMADJUST_ADJ(x)                  (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
+
+/*! @name CLK_RECOVER_CTRL - USB Clock recovery control */
+#define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN      (0x20U)
+#define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN      (0x40U)
+#define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN      (0x80U)
+
+/*! @name CLK_RECOVER_IRC_EN - IRC48M oscillator enable register */
+#define USB_CLK_RECOVER_IRC_EN_REG_EN            (0x1U)
+#define USB_CLK_RECOVER_IRC_EN_IRC_EN            (0x2U)
+
+/*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */
+#define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR      (0x10U)
+
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE                                (0x40072000u)
+/** Peripheral USB0 base pointer */
+#define USB0                                     ((USB_TypeDef *)USB0_BASE)
+/** Array initializer of USB peripheral base addresses */
+#define USB_BASE_ADDRS                           { USB0_BASE }
+/** Array initializer of USB peripheral base pointers */
+#define USB_BASE_PTRS                            { USB0 }
+/** Interrupt vectors for the USB peripheral type */
+#define USB_IRQS                                 { USB0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USBDCD Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
+ * @{
+ */
+
+/** USBDCD - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CONTROL;                           /**< Control register, offset: 0x0 */
+  __IO uint32_t CLOCK;                             /**< Clock register, offset: 0x4 */
+  __I  uint32_t STATUS;                            /**< Status register, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t TIMER0;                            /**< TIMER0 register, offset: 0x10 */
+  __IO uint32_t TIMER1;                            /**< TIMER1 register, offset: 0x14 */
+  union {                                          /* offset: 0x18 */
+    __IO uint32_t TIMER2_BC11;                       /**< TIMER2_BC11 register, offset: 0x18 */
+    __IO uint32_t TIMER2_BC12;                       /**< TIMER2_BC12 register, offset: 0x18 */
+  };
+} USBDCD_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- USBDCD Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
+ * @{
+ */
+
+/*! @name CONTROL - Control register */
+#define USBDCD_CONTROL_IACK                      (0x1U)
+#define USBDCD_CONTROL_IF                        (0x100U)
+#define USBDCD_CONTROL_IE                        (0x10000U)
+#define USBDCD_CONTROL_BC12                      (0x20000U)
+#define USBDCD_CONTROL_START                     (0x1000000U)
+#define USBDCD_CONTROL_SR                        (0x2000000U)
+
+/*! @name CLOCK - Clock register */
+#define USBDCD_CLOCK_CLOCK_UNIT                  (0x1U)
+#define USBDCD_CLOCK_CLOCK_SPEED_MASK            (0xFFCU)
+#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT           (2U)
+#define USBDCD_CLOCK_CLOCK_SPEED(x)              (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBDCD_CLOCK_CLOCK_SPEED_MASK)
+
+/*! @name STATUS - Status register */
+#define USBDCD_STATUS_SEQ_RES_MASK               (0x30000U)
+#define USBDCD_STATUS_SEQ_RES_SHIFT              (16U)
+#define USBDCD_STATUS_SEQ_RES(x)                 (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_RES_SHIFT)) & USBDCD_STATUS_SEQ_RES_MASK)
+#define USBDCD_STATUS_SEQ_STAT_MASK              (0xC0000U)
+#define USBDCD_STATUS_SEQ_STAT_SHIFT             (18U)
+#define USBDCD_STATUS_SEQ_STAT(x)                (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_STAT_SHIFT)) & USBDCD_STATUS_SEQ_STAT_MASK)
+#define USBDCD_STATUS_ERR                        (0x100000U)
+#define USBDCD_STATUS_TO                         (0x200000U)
+#define USBDCD_STATUS_ACTIVE                     (0x400000U)
+
+/*! @name TIMER0 - TIMER0 register */
+#define USBDCD_TIMER0_TUNITCON_MASK              (0xFFFU)
+#define USBDCD_TIMER0_TUNITCON_SHIFT             (0U)
+#define USBDCD_TIMER0_TUNITCON(x)                (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TUNITCON_SHIFT)) & USBDCD_TIMER0_TUNITCON_MASK)
+#define USBDCD_TIMER0_TSEQ_INIT_MASK             (0x3FF0000U)
+#define USBDCD_TIMER0_TSEQ_INIT_SHIFT            (16U)
+#define USBDCD_TIMER0_TSEQ_INIT(x)               (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBDCD_TIMER0_TSEQ_INIT_MASK)
+
+/*! @name TIMER1 - TIMER1 register */
+#define USBDCD_TIMER1_TVDPSRC_ON_MASK            (0x3FFU)
+#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT           (0U)
+#define USBDCD_TIMER1_TVDPSRC_ON(x)              (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBDCD_TIMER1_TVDPSRC_ON_MASK)
+#define USBDCD_TIMER1_TDCD_DBNC_MASK             (0x3FF0000U)
+#define USBDCD_TIMER1_TDCD_DBNC_SHIFT            (16U)
+#define USBDCD_TIMER1_TDCD_DBNC(x)               (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBDCD_TIMER1_TDCD_DBNC_MASK)
+
+/*! @name TIMER2_BC11 - TIMER2_BC11 register */
+#define USBDCD_TIMER2_BC11_CHECK_DM_MASK         (0xFU)
+#define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT        (0U)
+#define USBDCD_TIMER2_BC11_CHECK_DM(x)           (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBDCD_TIMER2_BC11_CHECK_DM_MASK)
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK      (0x3FF0000U)
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT     (16U)
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON(x)        (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
+
+/*! @name TIMER2_BC12 - TIMER2_BC12 register */
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK       (0x3FFU)
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT      (0U)
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON(x)         (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK  (0x3FF0000U)
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x)    (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Register_Masks */
+
+
+/* USBDCD - Peripheral instance base addresses */
+/** Peripheral USBDCD base address */
+#define USBDCD_BASE                              (0x40035000u)
+/** Peripheral USBDCD base pointer */
+#define USBDCD                                   ((USBDCD_TypeDef *)USBDCD_BASE)
+/** Array initializer of USBDCD peripheral base addresses */
+#define USBDCD_BASE_ADDRS                        { USBDCD_BASE }
+/** Array initializer of USBDCD peripheral base pointers */
+#define USBDCD_BASE_PTRS                         { USBDCD }
+/** Interrupt vectors for the USBDCD peripheral type */
+#define USBDCD_IRQS                              { USBDCD_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- VREF Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
+ * @{
+ */
+
+/** VREF - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t TRM;                                /**< VREF Trim Register, offset: 0x0 */
+  __IO uint8_t SC;                                 /**< VREF Status and Control Register, offset: 0x1 */
+} VREF_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- VREF Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Masks VREF Register Masks
+ * @{
+ */
+
+/*! @name TRM - VREF Trim Register */
+#define VREF_TRM_TRIM_MASK                       (0x3FU)
+#define VREF_TRM_TRIM_SHIFT                      (0U)
+#define VREF_TRM_TRIM(x)                         (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK)
+#define VREF_TRM_CHOPEN                          (0x40U)
+
+/*! @name SC - VREF Status and Control Register */
+#define VREF_SC_MODE_LV_MASK                     (0x3U)
+#define VREF_SC_MODE_LV_SHIFT                    (0U)
+#define VREF_SC_MODE_LV(x)                       (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK)
+#define VREF_SC_VREFST                           (0x4U)
+#define VREF_SC_ICOMPEN                          (0x20U)
+#define VREF_SC_REGEN                            (0x40U)
+#define VREF_SC_VREFEN                           (0x80U)
+
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Masks */
+
+
+/* VREF - Peripheral instance base addresses */
+/** Peripheral VREF base address */
+#define VREF_BASE                                (0x40074000u)
+/** Peripheral VREF base pointer */
+#define VREF                                     ((VREF_TypeDef *)VREF_BASE)
+/** Array initializer of VREF peripheral base addresses */
+#define VREF_BASE_ADDRS                          { VREF_BASE }
+/** Array initializer of VREF peripheral base pointers */
+#define VREF_BASE_PTRS                           { VREF }
+
+/*!
+ * @}
+ */ /* end of group VREF_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- WDOG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
+ * @{
+ */
+
+/** WDOG - Register Layout Typedef */
+typedef struct {
+  __IO uint16_t STCTRLH;                           /**< Watchdog Status and Control Register High, offset: 0x0 */
+  __IO uint16_t STCTRLL;                           /**< Watchdog Status and Control Register Low, offset: 0x2 */
+  __IO uint16_t TOVALH;                            /**< Watchdog Time-out Value Register High, offset: 0x4 */
+  __IO uint16_t TOVALL;                            /**< Watchdog Time-out Value Register Low, offset: 0x6 */
+  __IO uint16_t WINH;                              /**< Watchdog Window Register High, offset: 0x8 */
+  __IO uint16_t WINL;                              /**< Watchdog Window Register Low, offset: 0xA */
+  __IO uint16_t REFRESH;                           /**< Watchdog Refresh register, offset: 0xC */
+  __IO uint16_t UNLOCK;                            /**< Watchdog Unlock register, offset: 0xE */
+  __IO uint16_t TMROUTH;                           /**< Watchdog Timer Output Register High, offset: 0x10 */
+  __IO uint16_t TMROUTL;                           /**< Watchdog Timer Output Register Low, offset: 0x12 */
+  __IO uint16_t RSTCNT;                            /**< Watchdog Reset Count register, offset: 0x14 */
+  __IO uint16_t PRESC;                             /**< Watchdog Prescaler register, offset: 0x16 */
+} WDOG_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- WDOG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Masks WDOG Register Masks
+ * @{
+ */
+
+/*! @name STCTRLH - Watchdog Status and Control Register High */
+#define WDOG_STCTRLH_WDOGEN                      (0x1U)
+#define WDOG_STCTRLH_CLKSRC                      (0x2U)
+#define WDOG_STCTRLH_IRQRSTEN                    (0x4U)
+#define WDOG_STCTRLH_WINEN                       (0x8U)
+#define WDOG_STCTRLH_ALLOWUPDATE                 (0x10U)
+#define WDOG_STCTRLH_DBGEN                       (0x20U)
+#define WDOG_STCTRLH_STOPEN                      (0x40U)
+#define WDOG_STCTRLH_WAITEN                      (0x80U)
+#define WDOG_STCTRLH_TESTWDOG                    (0x400U)
+#define WDOG_STCTRLH_TESTSEL                     (0x800U)
+#define WDOG_STCTRLH_BYTESEL_MASK                (0x3000U)
+#define WDOG_STCTRLH_BYTESEL_SHIFT               (12U)
+#define WDOG_STCTRLH_BYTESEL(x)                  (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK)
+#define WDOG_STCTRLH_DISTESTWDOG                 (0x4000U)
+
+/*! @name STCTRLL - Watchdog Status and Control Register Low */
+#define WDOG_STCTRLL_INTFLG                      (0x8000U)
+
+/*! @name PRESC - Watchdog Prescaler register */
+#define WDOG_PRESC_PRESCVAL_MASK                 (0x700U)
+#define WDOG_PRESC_PRESCVAL_SHIFT                (8U)
+#define WDOG_PRESC_PRESCVAL(x)                   (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Masks */
+
+
+/* WDOG - Peripheral instance base addresses */
+/** Peripheral WDOG base address */
+#define WDOG_BASE                                (0x40052000u)
+/** Peripheral WDOG base pointer */
+#define WDOG                                     ((WDOG_TypeDef *)WDOG_BASE)
+/** Array initializer of WDOG peripheral base addresses */
+#define WDOG_BASE_ADDRS                          { WDOG_BASE }
+/** Array initializer of WDOG peripheral base pointers */
+#define WDOG_BASE_PTRS                           { WDOG }
+/** Interrupt vectors for the WDOG peripheral type */
+#define WDOG_IRQS                                { WDOG_EWM_IRQn }
+
+/*!
+ * @}
+ */ /* end of group WDOG_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #pragma pop
+#elif defined(__CWCC__)
+  #pragma pop
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDK Compatibility
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
+ * @{
+ */
+
+#define ENET_RMON_R_DROP_REG(base)               ENET_IEEE_R_DROP_REG(base)
+#define ENET_RMON_R_FRAME_OK_REG(base)           ENET_IEEE_R_FRAME_OK_REG(base)
+#define MCG_C2_EREFS0_MASK                       MCG_C2_EREFS_MASK
+#define MCG_C2_EREFS0_SHIFT                      MCG_C2_EREFS_SHIFT
+#define MCG_C2_HGO0_MASK                         MCG_C2_HGO_MASK
+#define MCG_C2_HGO0_SHIFT                        MCG_C2_HGO_SHIFT
+#define MCG_C2_RANGE0_MASK                       MCG_C2_RANGE_MASK
+#define MCG_C2_RANGE0_SHIFT                      MCG_C2_RANGE_SHIFT
+#define MCG_C2_RANGE0(x)                         MCG_C2_RANGE(x)
+#define MCM_ISR_REG(base)                        MCM_ISCR_REG(base)
+#define MCM_ISR_FIOC_MASK                        MCM_ISCR_FIOC_MASK
+#define MCM_ISR_FIOC_SHIFT                       MCM_ISCR_FIOC_SHIFT
+#define MCM_ISR_FDZC_MASK                        MCM_ISCR_FDZC_MASK
+#define MCM_ISR_FDZC_SHIFT                       MCM_ISCR_FDZC_SHIFT
+#define MCM_ISR_FOFC_MASK                        MCM_ISCR_FOFC_MASK
+#define MCM_ISR_FOFC_SHIFT                       MCM_ISCR_FOFC_SHIFT
+#define MCM_ISR_FUFC_MASK                        MCM_ISCR_FUFC_MASK
+#define MCM_ISR_FUFC_SHIFT                       MCM_ISCR_FUFC_SHIFT
+#define MCM_ISR_FIXC_MASK                        MCM_ISCR_FIXC_MASK
+#define MCM_ISR_FIXC_SHIFT                       MCM_ISCR_FIXC_SHIFT
+#define MCM_ISR_FIDC_MASK                        MCM_ISCR_FIDC_MASK
+#define MCM_ISR_FIDC_SHIFT                       MCM_ISCR_FIDC_SHIFT
+#define MCM_ISR_FIOCE_MASK                       MCM_ISCR_FIOCE_MASK
+#define MCM_ISR_FIOCE_SHIFT                      MCM_ISCR_FIOCE_SHIFT
+#define MCM_ISR_FDZCE_MASK                       MCM_ISCR_FDZCE_MASK
+#define MCM_ISR_FDZCE_SHIFT                      MCM_ISCR_FDZCE_SHIFT
+#define MCM_ISR_FOFCE_MASK                       MCM_ISCR_FOFCE_MASK
+#define MCM_ISR_FOFCE_SHIFT                      MCM_ISCR_FOFCE_SHIFT
+#define MCM_ISR_FUFCE_MASK                       MCM_ISCR_FUFCE_MASK
+#define MCM_ISR_FUFCE_SHIFT                      MCM_ISCR_FUFCE_SHIFT
+#define MCM_ISR_FIXCE_MASK                       MCM_ISCR_FIXCE_MASK
+#define MCM_ISR_FIXCE_SHIFT                      MCM_ISCR_FIXCE_SHIFT
+#define MCM_ISR_FIDCE_MASK                       MCM_ISCR_FIDCE_MASK
+#define MCM_ISR_FIDCE_SHIFT                      MCM_ISCR_FIDCE_SHIFT
+#define DSPI0                                    SPI0
+#define DSPI1                                    SPI1
+#define DSPI2                                    SPI2
+#define FLEXCAN0                                 CAN0
+#define PTA_BASE                                 GPIOA_BASE
+#define PTA                                      GPIOA
+#define PTB_BASE                                 GPIOB_BASE
+#define PTB                                      GPIOB
+#define PTC_BASE                                 GPIOC_BASE
+#define PTC                                      GPIOC
+#define PTD_BASE                                 GPIOD_BASE
+#define PTD                                      GPIOD
+#define PTE_BASE                                 GPIOE_BASE
+#define PTE                                      GPIOE
+#define UART_WP7816_T_TYPE0_REG(base)            UART_WP7816T0_REG(base)
+#define UART_WP7816_T_TYPE1_REG(base)            UART_WP7816T1_REG(base)
+#define UART_WP7816_T_TYPE0_WI_MASK              UART_WP7816T0_WI_MASK
+#define UART_WP7816_T_TYPE0_WI_SHIFT             UART_WP7816T0_WI_SHIFT
+#define UART_WP7816_T_TYPE0_WI(x)                UART_WP7816T0_WI(x)
+#define UART_WP7816_T_TYPE1_BWI_MASK             UART_WP7816T1_BWI_MASK
+#define UART_WP7816_T_TYPE1_BWI_SHIFT            UART_WP7816T1_BWI_SHIFT
+#define UART_WP7816_T_TYPE1_BWI(x)               UART_WP7816T1_BWI(x)
+#define UART_WP7816_T_TYPE1_CWI_MASK             UART_WP7816T1_CWI_MASK
+#define UART_WP7816_T_TYPE1_CWI_SHIFT            UART_WP7816T1_CWI_SHIFT
+#define UART_WP7816_T_TYPE1_CWI(x)               UART_WP7816T1_CWI(x)
+#define Watchdog_IRQn                            WDOG_EWM_IRQn
+#define Watchdog_IRQHandler                      WDOG_EWM_IRQHandler
+#define LPTimer_IRQn                             LPTMR0_IRQn
+#define LPTimer_IRQHandler                       LPTMR0_IRQHandler
+#define LLW_IRQn                                 LLWU_IRQn
+#define LLW_IRQHandler                           LLWU_IRQHandler
+#define DMAMUX0                                  DMAMUX
+#define WDOG0                                    WDOG
+#define MCM0                                     MCM
+#define RTC0                                     RTC
+
+/*!
+ * @}
+ */ /* end of group SDK_Compatibility_Symbols */
+
+
+#endif  /* _MK64F12_H_ */
+
diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/MK64FX512.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/MK64FX512.ld
new file mode 100644
index 0000000..77b0fe3
--- /dev/null
+++ b/os/common/startup/ARMCMx/compilers/GCC/ld/MK64FX512.ld
@@ -0,0 +1,97 @@
+/*
+ * Copyright (C) 2013-2016 Fabio Utzig, http://fabioutzig.com
+ *           (C) 2017 Wim Lewis
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/*
+ * MK64FX512 memory setup.
+ */
+MEMORY
+{
+  flash0   : org = 0x00000000, len = 0x400
+  flash1   : org = 0x00000400, len = 0x10
+  flash2   : org = 0x00000410, len = 512k - 0x410
+  flash3   : org = 0x10000000, len = 128k   /* FlexNVM */
+  ram0     : org = 0x1FFF0000, len = 64k    /* SRAM_L (code RAM) */
+  ram1     : org = 0x20000000, len = 192k   /* SRAM_U (data RAM) */
+  ram2     : org = 0x14000000, len = 4k     /* FlexRAM */
+  ram3     : org = 0x00000000, len = 0
+  ram4     : org = 0x00000000, len = 0
+  ram5     : org = 0x00000000, len = 0
+  ram6     : org = 0x00000000, len = 0
+  ram7     : org = 0x00000000, len = 0
+}
+
+/* Flash region for the configuration bytes.*/
+SECTIONS
+{
+  .cfmprotect : ALIGN(4) SUBALIGN(4)
+  {
+    KEEP(*(.cfmconfig))
+  } > flash1
+}
+
+/* For each data/text section two region are defined, a virtual region
+   and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash2);
+REGION_ALIAS("XTORS_FLASH_LMA", flash2);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash2);
+REGION_ALIAS("TEXT_FLASH_LMA", flash2);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash2);
+REGION_ALIAS("RODATA_FLASH_LMA", flash2);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash2);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash2);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash2);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+   of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram1);
+
+/* RAM region to be used for the process stack. This is the stack used by
+   the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram1);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram1);
+REGION_ALIAS("DATA_RAM_LMA", flash2);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram1);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram1);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k60x.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k60x.mk
new file mode 100644
index 0000000..777df43
--- /dev/null
+++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k60x.mk
@@ -0,0 +1,12 @@
+# List of the ChibiOS generic K60x startup and CMSIS files.
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
+             $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.c
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S
+
+STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
+             $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/K60x \
+             $(CHIBIOS)/os/common/ext/CMSIS/include \
+             $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/KINETIS
+
+STARTUPLD  = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
diff --git a/os/common/startup/ARMCMx/devices/K60x/cmparams.h b/os/common/startup/ARMCMx/devices/K60x/cmparams.h
new file mode 100644
index 0000000..95c306c
--- /dev/null
+++ b/os/common/startup/ARMCMx/devices/K60x/cmparams.h
@@ -0,0 +1,81 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio.
+                           (C) 2015 RedoX https://github.com/RedoXyde
+                           (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
+                           (C) 2017 Wim Lewis
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    GCC/ARMCMx/K60x/cmparams.h
+ * @brief   ARM Cortex-M4 parameters for the Kinetis K60 family.
+ *
+ * @defgroup ARMCMx_K60 Kinetis K60 Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M4 specific parameters for the
+ *          Kinetis K60 family.
+ * @{
+ */
+
+#ifndef _CMPARAMS_H_
+#define _CMPARAMS_H_
+
+/**
+ * @brief   Cortex core model.
+ */
+#define CORTEX_MODEL            4
+
+/**
+ * @brief   Systick unit presence.
+ */
+#define CORTEX_HAS_ST           TRUE
+
+/**
+ * @brief   Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU          TRUE
+
+/**
+ * @brief   Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS    4
+
+/**
+ * @brief   Number of interrupt vectors.
+ * @note    This number does not include the 16 system vectors and must be
+ *          rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS      88
+
+/* The following code is not processed when the file is included from an
+   asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+   from this header because we need this file to be usable also from
+   assembler source files. We verify that the info matches instead.*/
+#include "k64f.h"
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* _CMPARAMS_H_ */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/K60x/hal_lld.c b/os/hal/ports/KINETIS/K60x/hal_lld.c
new file mode 100644
index 0000000..cfe633b
--- /dev/null
+++ b/os/hal/ports/KINETIS/K60x/hal_lld.c
@@ -0,0 +1,237 @@
+/*
+    ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+              Copyright (C) 2017 Fabio Utzig
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    templates/hal_lld.c
+ * @brief   HAL Driver subsystem low level driver source template.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+#ifdef __CC_ARM
+__attribute__ ((section(".ARM.__at_0x400")))
+#else
+__attribute__ ((used,section(".cfmconfig")))
+#endif
+const uint8_t _cfm[0x10] = {
+  0xFF,  /* NV_BACKKEY3: KEY=0xFF */
+  0xFF,  /* NV_BACKKEY2: KEY=0xFF */
+  0xFF,  /* NV_BACKKEY1: KEY=0xFF */
+  0xFF,  /* NV_BACKKEY0: KEY=0xFF */
+  0xFF,  /* NV_BACKKEY7: KEY=0xFF */
+  0xFF,  /* NV_BACKKEY6: KEY=0xFF */
+  0xFF,  /* NV_BACKKEY5: KEY=0xFF */
+  0xFF,  /* NV_BACKKEY4: KEY=0xFF */
+  0xFF,  /* NV_FPROT3: PROT=0xFF */
+  0xFF,  /* NV_FPROT2: PROT=0xFF */
+  0xFF,  /* NV_FPROT1: PROT=0xFF */
+  0xFF,  /* NV_FPROT0: PROT=0xFF */
+  0x7E,  /* NV_FSEC: KEYEN=1,MEEN=3,FSLACC=3,SEC=2 */
+  0xFF,  /* NV_FOPT: ??=1,??=1,FAST_INIT=1,LPBOOT1=1,RESET_PIN_CFG=1,
+                      NMI_DIS=1,EZPORT_DIS=1,LPBOOT0=1 */
+  0xFF,
+  0xFF
+};
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level HAL driver initialization.
+ * @todo    Use a macro to define the system clock frequency.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+
+}
+
+/**
+ * @brief   K60x clock initialization.
+ * @note    All the involved constants come from the file @p board.h.
+ * @note    This function is meant to be invoked early during the system
+ *          initialization, it is usually invoked from the file
+ *          @p board.c.
+ * @todo    This function needs to be more generic.
+ * @todo    This function should be combined with the nearly-identical
+ *          functions in other Kinetis ports.
+ *
+ * @special
+ */
+void k60x_clock_init(void) {
+#if !KINETIS_NO_INIT
+
+  /* Disable the watchdog */
+  WDOG->UNLOCK = 0xC520;
+  WDOG->UNLOCK = 0xD928;
+  __asm__("nop");
+  WDOG->STCTRLH &= ~WDOG_STCTRLH_WDOGEN;
+
+  SIM->SCGC5 |= SIM_SCGC5_PORTA |
+                SIM_SCGC5_PORTB |
+                SIM_SCGC5_PORTC |
+                SIM_SCGC5_PORTD |
+                SIM_SCGC5_PORTE;
+
+#if KINETIS_MCG_MODE == KINETIS_MCG_MODE_FEI
+  /* This is the default mode at reset. */
+
+  /* Configure FEI mode */
+  MCG->C4 = MCG_C4_DRST_DRS(KINETIS_MCG_FLL_DRS) |
+            (KINETIS_MCG_FLL_DMX32 ? MCG_C4_DMX32 : 0);
+
+  /* Set clock dividers */
+  SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1-1) |
+                 SIM_CLKDIV1_OUTDIV2(KINETIS_CLKDIV1_OUTDIV2-1) |
+                 SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4-1);
+  SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0); /* not strictly necessary since usb_lld will set this */
+
+#elif KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE
+
+  uint32_t ratio, frdiv;
+  uint32_t ratios[] = { 32, 64, 128, 256, 512, 1024, 1280, 1536 };
+  uint8_t ratio_quantity = sizeof(ratios) / sizeof(ratios[0]);
+  uint8_t i;
+
+  /* EXTAL0 and XTAL0 */
+  PORTA->PCR[18] = 0;
+  PORTA->PCR[19] = 0;
+
+  /*
+   * Start in FEI mode
+   */
+
+  /* Internal capacitors for crystal */
+#if defined(KINETIS_BOARD_OSCILLATOR_SETTING)
+  OSC0->CR = KINETIS_BOARD_OSCILLATOR_SETTING;
+#else /* KINETIS_BOARD_OSCILLATOR_SETTING */
+  /* Disable the internal capacitors */
+  OSC0->CR = 0;
+#endif /* KINETIS_BOARD_OSCILLATOR_SETTING */
+
+  /* TODO: need to add more flexible calculation, specially regarding
+   *       divisors which may not be available depending on the XTAL
+   *       frequency, which would required other registers to be modified.
+   */
+  /* Enable OSC, low power mode */
+  if (KINETIS_XTAL_FREQUENCY > 8000000UL)
+    MCG->C2 = MCG_C2_LOCRE0 | MCG_C2_EREFS0 | MCG_C2_RANGE0(2);
+  else
+    MCG->C2 = MCG_C2_LOCRE0 | MCG_C2_EREFS0 | MCG_C2_RANGE0(1);
+
+  frdiv = 7;
+  ratio = KINETIS_XTAL_FREQUENCY / 31250UL;
+  for (i = 0; i < ratio_quantity; ++i) {
+    if (ratio == ratios[i]) {
+      frdiv = i;
+      break;
+    }
+  }
+
+  /* Switch to crystal as clock source, FLL input of 31.25 KHz */
+  MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(frdiv);
+
+  /* Wait for crystal oscillator to begin */
+  while (!(MCG->S & MCG_S_OSCINIT0));
+
+  /* Wait for the FLL to use the oscillator */
+  while (MCG->S & MCG_S_IREFST);
+
+  /* Wait for the MCGOUTCLK to use the oscillator */
+  while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST(2));
+
+  /*
+   * Now in FBE mode
+   */
+  #define KINETIS_PLLIN_FREQUENCY 2000000UL
+  /*
+   * Config PLL input for 2 MHz
+   * TODO: Make sure KINETIS_XTAL_FREQUENCY >= 2Mhz && <= 50Mhz
+   */
+  MCG->C5 = MCG_C5_PRDIV0((KINETIS_XTAL_FREQUENCY/KINETIS_PLLIN_FREQUENCY) - 1);
+
+  /*
+   * Config PLL output to match KINETIS_SYSCLK_FREQUENCY
+   * TODO: make sure KINETIS_SYSCLK_FREQUENCY is a match
+   */
+  for(i = 24; i < 56; i++)
+  {
+    if(i == (KINETIS_PLLCLK_FREQUENCY/KINETIS_PLLIN_FREQUENCY))
+    {
+      /* Config PLL to match KINETIS_PLLCLK_FREQUENCY */
+      MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(i-24);
+      break;
+    }
+  }
+
+  if(i>=56)  /* Config PLL for 96 MHz output as default setting */
+    MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0);
+
+  /* Wait for PLL to start using crystal as its input, and to lock */
+  while ((MCG->S & (MCG_S_PLLST|MCG_S_LOCK0))!=(MCG_S_PLLST|MCG_S_LOCK0));
+
+  /*
+   * Now in PBE mode
+   */
+  /* Set the PLL dividers for the different clocks */
+  SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1-1) |
+                 SIM_CLKDIV1_OUTDIV2(KINETIS_CLKDIV1_OUTDIV2-1) |
+                 SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4-1);
+  SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0);
+  SIM->SOPT2 = SIM_SOPT2_PLLFLLSEL_IRC48M; /* FIXME ? Why this? */
+
+  /* Switch to PLL as clock source */
+  MCG->C1 = MCG_C1_CLKS(0);
+
+  /* Wait for PLL clock to be used */
+  while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL);
+
+  /*
+   * Now in PEE mode
+   */
+#else /* KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE */
+#error Unimplemented KINETIS_MCG_MODE
+#endif /* KINETIS_MCG_MODE == ... */
+
+#endif /* !KINETIS_NO_INIT */
+}
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/K60x/hal_lld.h b/os/hal/ports/KINETIS/K60x/hal_lld.h
new file mode 100644
index 0000000..8da89b3
--- /dev/null
+++ b/os/hal/ports/KINETIS/K60x/hal_lld.h
@@ -0,0 +1,302 @@
+/*
+    ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    K60x/hal_lld.h
+ * @brief   Kinetis K60x HAL subsystem low level driver header.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef HAL_LLD_H_
+#define HAL_LLD_H_
+
+#include "kinetis_registry.h"
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Defines the support for realtime counters in the HAL.
+ */
+#define HAL_IMPLEMENTS_COUNTERS FALSE /* FIXME check */
+
+/**
+ * @name    Platform identification
+ * @{
+ */
+#define PLATFORM_NAME           "Kinetis"
+/** @} */
+
+/**
+ * @name    Internal clock sources
+ * @{
+ */
+#define KINETIS_IRCLK_F         4000000     /**< Fast internal reference clock, factory trimmed. */
+#define KINETIS_IRCLK_S         32768       /**< Slow internal reference clock, factory trimmed. */
+/** @} */
+
+#define KINETIS_MCG_MODE_FEI    1    /**< FLL Engaged Internal. */
+#define KINETIS_MCG_MODE_FEE    2    /**< FLL Engaged External. */
+#define KINETIS_MCG_MODE_FBI    3    /**< FLL Bypassed Internal. */
+#define KINETIS_MCG_MODE_FBE    4    /**< FLL Bypassed External. */
+#define KINETIS_MCG_MODE_PEE    5    /**< PLL Engaged External. */
+#define KINETIS_MCG_MODE_PBE    6    /**< PLL Bypassed External. */
+#define KINETIS_MCG_MODE_BLPI   7    /**< Bypassed Low Power Internal. */
+#define KINETIS_MCG_MODE_BLPE   8    /**< Bypassed Low Power External. */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   Disables the MCG/system clock initialization in the HAL.
+ */
+#if !defined(KINETIS_NO_INIT) || defined(__DOXYGEN__)
+#define KINETIS_NO_INIT             FALSE
+#endif
+
+/**
+ * @brief   MCG mode selection.
+ */
+#if !defined(KINETIS_MCG_MODE) || defined(__DOXYGEN__)
+#define KINETIS_MCG_MODE            KINETIS_MCG_MODE_PEE
+#endif
+
+/**
+ * @brief   MCU PLL clock frequency.
+ */
+#if !defined(KINETIS_PLLCLK_FREQUENCY) || defined(__DOXYGEN__)
+#define KINETIS_PLLCLK_FREQUENCY    96000000UL
+#endif
+
+/**
+ * @brief   Clock divider for core/system clocks (OUTDIV1).
+ * @note    The allowed range is 1..16
+ * @note    The default value is calculated for a 48 MHz system clock
+ *          from a 96 MHz PLL output.
+ */
+#if !defined(KINETIS_CLKDIV1_OUTDIV1) || defined(__DOXYGEN__)
+  #if defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
+    #define KINETIS_CLKDIV1_OUTDIV1     (KINETIS_PLLCLK_FREQUENCY/KINETIS_SYSCLK_FREQUENCY)
+  #else
+    #define KINETIS_CLKDIV1_OUTDIV1     2
+  #endif
+#endif
+
+/**
+ * @brief   Clock divider for bus clock (OUTDIV2).
+ * @note    The allowed range is 1..16
+ * @note    The default value is calculated for a 48 MHz bus clock
+ *          from a 96 MHz PLL output.
+ */
+#if !defined(KINETIS_CLKDIV1_OUTDIV2) || defined(__DOXYGEN__)
+  #if defined(KINETIS_BUSCLK_FREQUENCY) && KINETIS_BUSCLK_FREQUENCY > 0
+    #define KINETIS_CLKDIV1_OUTDIV2     (KINETIS_PLLCLK_FREQUENCY/KINETIS_BUSCLK_FREQUENCY)
+  #elif defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
+    #define KINETIS_CLKDIV1_OUTDIV2	KINETIS_CLKDIV1_OUTDIV1
+  #else
+    #define KINETIS_CLKDIV1_OUTDIV2     2
+  #endif
+#endif
+
+/**
+ * @brief   Clock divider for flash clock (OUTDIV4).
+ * @note    The allowed range is 1..16
+ * @note    The default value is calculated for a 24 MHz flash clock
+ *          from a 96 MHz PLL output
+ */
+#if !defined(KINETIS_CLKDIV1_OUTDIV4) || defined(__DOXYGEN__)
+  #if defined(KINETIS_FLASHCLK_FREQUENCY) && KINETIS_FLASHCLK_FREQUENCY > 0
+    #define KINETIS_CLKDIV1_OUTDIV4     (KINETIS_PLLCLK_FREQUENCY/KINETIS_FLASHCLK_FREQUENCY)
+  #elif defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
+    #define KINETIS_CLKDIV1_OUTDIV4	(KINETIS_CLKDIV1_OUTDIV1*2)
+  #else
+    #define KINETIS_CLKDIV1_OUTDIV4     4
+  #endif
+#endif
+
+/**
+ * @brief   FLL DCO tuning enable for 32.768 kHz reference.
+ * @note    Set to 1 for fine-tuning DCO for maximum frequency with
+ *          a 32.768 kHz reference.
+ * @note    The default value is for a 32.768 kHz external crystal.
+ */
+#if !defined(KINETIS_MCG_FLL_DMX32) || defined(__DOXYGEN__)
+#define KINETIS_MCG_FLL_DMX32       1
+#endif
+
+/**
+ * @brief   FLL DCO range selection.
+ * @note    The allowed range is 0...3.
+ * @note    The default value is calculated for 48 MHz FLL output
+ *          from a 32.768 kHz external crystal.
+ *          (DMX32 && DRST_DRS=1 => F=1464; 32.768 kHz * F ~= 48 MHz.)
+ *
+ */
+#if !defined(KINETIS_MCG_FLL_DRS) || defined(__DOXYGEN__)
+#define KINETIS_MCG_FLL_DRS         2
+#endif
+
+/**
+ * @brief   MCU system/core clock frequency.
+ */
+#if !defined(KINETIS_SYSCLK_FREQUENCY) || defined(__DOXYGEN__)
+#define KINETIS_SYSCLK_FREQUENCY    (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV1)
+#endif
+
+/**
+ * @brief   MCU bus clock frequency.
+ */
+#if !defined(KINETIS_BUSCLK_FREQUENCY) || defined(__DOXYGEN__)
+#define KINETIS_BUSCLK_FREQUENCY    (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV2)
+#endif
+
+/**
+ * @brief   MCU flash clock frequency.
+ */
+#if !defined(KINETIS_FLASHCLK_FREQUENCY) || defined(__DOXYGEN__)
+#define KINETIS_FLASHCLK_FREQUENCY    (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV4)
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if !defined(KINETIS_SYSCLK_FREQUENCY)
+  #error KINETIS_SYSCLK_FREQUENCY must be defined
+#endif
+
+#if KINETIS_SYSCLK_FREQUENCY <= 0 || KINETIS_SYSCLK_FREQUENCY > KINETIS_SYSCLK_MAX
+  #error KINETIS_SYSCLK_FREQUENCY out of range
+#endif
+
+#if !defined(KINETIS_BUSCLK_FREQUENCY)
+  #error KINETIS_BUSCLK_FREQUENCY must be defined
+#endif
+
+#if KINETIS_BUSCLK_FREQUENCY <= 0 || KINETIS_BUSCLK_FREQUENCY > KINETIS_BUSCLK_MAX
+  #error KINETIS_BUSCLK_FREQUENCY out of range
+#endif
+
+#if KINETIS_BUSCLK_FREQUENCY > KINETIS_SYSCLK_FREQUENCY
+  #error KINETIS_BUSCLK_FREQUENCY must be an integer divide of\
+	 KINETIS_SYSCLK_FREQUENCY
+#endif
+
+#if !defined(KINETIS_FLASHCLK_FREQUENCY)
+  #error KINETIS_FLASHCLK_FREQUENCY must be defined
+#endif
+
+#if KINETIS_FLASHCLK_FREQUENCY <= 0 || KINETIS_FLASHCLK_FREQUENCY > KINETIS_FLASHCLK_MAX
+  #error KINETIS_FLASHCLK_FREQUENCY out of range
+#endif
+
+#if KINETIS_FLASHCLK_FREQUENCY > KINETIS_SYSCLK_FREQUENCY
+  #error KINETIS_FLASHCLK_FREQUENCY must be an integer divide of\
+	 KINETIS_SYSCLK_FREQUENCY
+#endif
+
+#if !(defined(KINETIS_CLKDIV1_OUTDIV1) && \
+      KINETIS_CLKDIV1_OUTDIV1 >= 1 && KINETIS_CLKDIV1_OUTDIV1 <= 16)
+  #error KINETIS_CLKDIV1_OUTDIV1 must be 1 through 16
+#endif
+
+#if !(defined(KINETIS_CLKDIV1_OUTDIV2) && \
+      KINETIS_CLKDIV1_OUTDIV2 >= 1 && KINETIS_CLKDIV1_OUTDIV2 <= 16)
+#error KINETIS_CLKDIV1_OUTDIV2 must be 1 through 16
+#endif
+
+#if !(defined(KINETIS_CLKDIV1_OUTDIV4) && \
+      KINETIS_CLKDIV1_OUTDIV4 >= 1 && KINETIS_CLKDIV1_OUTDIV4 <= 16)
+#error KINETIS_CLKDIV1_OUTDIV4 must be 1 through 16
+#endif
+
+#if !(KINETIS_MCG_FLL_DMX32 == 0 || KINETIS_MCG_FLL_DMX32 == 1)
+#error Invalid KINETIS_MCG_FLL_DMX32 value, must be 0 or 1
+#endif
+
+#if !(0 <= KINETIS_MCG_FLL_DRS && KINETIS_MCG_FLL_DRS <= 3)
+#error Invalid KINETIS_MCG_FLL_DRS value, must be 0...3
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type representing a system clock frequency.
+ */
+typedef uint32_t halclock_t;
+
+/**
+ * @brief   Type of the realtime free counter value.
+ */
+typedef uint32_t halrtcnt_t;
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Returns the current value of the system free running counter.
+ * @note    This service is implemented by returning the content of the
+ *          DWT_CYCCNT register.
+ *
+ * @return              The value of the system free running counter of
+ *                      type halrtcnt_t.
+ *
+ * @notapi
+ */
+#define hal_lld_get_counter_value()         0
+
+/**
+ * @brief   Realtime counter frequency.
+ * @note    The DWT_CYCCNT register is incremented directly by the system
+ *          clock so this function returns STM32_HCLK.
+ *
+ * @return              The realtime counter frequency of type halclock_t.
+ *
+ * @notapi
+ */
+#define hal_lld_get_counter_frequency()     0
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#include "nvic.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void hal_lld_init(void);
+  void k60x_clock_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/K60x/kinetis_registry.h b/os/hal/ports/KINETIS/K60x/kinetis_registry.h
new file mode 100644
index 0000000..e595c35
--- /dev/null
+++ b/os/hal/ports/KINETIS/K60x/kinetis_registry.h
@@ -0,0 +1,198 @@
+/*
+    ChibiOS - Copyright (C) 2014 Derek Mulcahy
+                        (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
+                        (C) 2017 Wim Lewis
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    K60x/kinetis_registry.h
+ * @brief   K60x capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef KINETIS_REGISTRY_H_
+#define KINETIS_REGISTRY_H_
+
+#if !defined(K60x) || defined(__DOXYGEN__)
+#define K60x  /* Processor family */
+#endif
+
+#if defined(K64FX512) || defined(K64FN1M0) || defined(__DOXYGEN__)
+#define K64F  /* Sub-family */
+#else
+#error "Unknown processor sub-family"
+#endif
+
+/*===========================================================================*/
+/* Platform capabilities.                                                    */
+/*===========================================================================*/
+
+/**
+ * @name    K60x capabilities
+ * @{
+ */
+/*===========================================================================*/
+/* K64F                                                                      */
+/*===========================================================================*/
+#if defined(K64F) || defined(__DOXYGEN__)
+
+/**
+ * @brief   Maximum system and core clock (f_SYS) frequency.
+ */
+#define KINETIS_SYSCLK_MAX     120000000L
+
+/**
+ * @brief   Maximum bus clock (f_BUS) frequency.
+ */
+#define KINETIS_BUSCLK_MAX      60000000L
+
+/**
+ * @brief   Maximum flash clock (f_FLASH) frequency.
+ */
+#define KINETIS_FLASHCLK_MAX    25000000L
+
+/* ADC attributes.*/
+#define KINETIS_HAS_ADC0            TRUE
+#define KINETIS_ADC0_IRQ_VECTOR     VectorDC
+#define KINETIS_HAS_ADC1            TRUE
+#define KINETIS_ADC1_IRQ_VECTOR     Vector164
+
+/* DAC attributes.*/
+#define KINETIS_HAS_DAC0            TRUE
+#define KINETIS_DAC0_IRQ_VECTOR     Vector120
+#define KINETIS_HAS_DAC1            TRUE
+#define KINETIS_DAC1_IRQ_VECTOR     Vector160
+
+/* DMA attributes.*/
+#define KINETIS_DMA0_IRQ_VECTOR     Vector40
+#define KINETIS_DMA1_IRQ_VECTOR     Vector44
+#define KINETIS_DMA2_IRQ_VECTOR     Vector48
+#define KINETIS_DMA3_IRQ_VECTOR     Vector4C
+#define KINETIS_DMA4_IRQ_VECTOR     Vector50
+#define KINETIS_DMA5_IRQ_VECTOR     Vector54
+#define KINETIS_DMA6_IRQ_VECTOR     Vector58
+#define KINETIS_DMA7_IRQ_VECTOR     Vector5C
+#define KINETIS_DMA8_IRQ_VECTOR     Vector60
+#define KINETIS_DMA9_IRQ_VECTOR     Vector64
+#define KINETIS_DMA10_IRQ_VECTOR    Vector68
+#define KINETIS_DMA11_IRQ_VECTOR    Vector6C
+#define KINETIS_DMA12_IRQ_VECTOR    Vector70
+#define KINETIS_DMA13_IRQ_VECTOR    Vector74
+#define KINETIS_DMA14_IRQ_VECTOR    Vector78
+#define KINETIS_DMA15_IRQ_VECTOR    Vector7C
+#define KINETIS_HAS_DMA_ERROR_IRQ   TRUE
+#define KINETIS_DMA_ERROR_IRQ_VECTOR Vector80
+
+/* EXT attributes.*/
+#define KINETIS_PORTA_IRQ_VECTOR    Vector12C
+#define KINETIS_PORTB_IRQ_VECTOR    Vector130
+#define KINETIS_PORTC_IRQ_VECTOR    Vector134
+#define KINETIS_PORTD_IRQ_VECTOR    Vector138
+#define KINETIS_PORTE_IRQ_VECTOR    Vector13C
+#define KINETIS_EXT_HAS_COMMON_CD_IRQ   FALSE
+#define KINETIS_EXT_HAS_COMMON_BCDE_IRQ FALSE
+#define KINETIS_GPIO_HAS_OPENDRAIN  TRUE
+
+/* I2C attributes.*/
+#define KINETIS_HAS_I2C0            TRUE
+#define KINETIS_I2C0_IRQ_VECTOR     VectorA0
+#define KINETIS_HAS_I2C1            TRUE
+#define KINETIS_I2C1_IRQ_VECTOR     VectorA4
+#define KINETIS_HAS_I2C2            TRUE
+#define KINETIS_I2C2_IRQ_VECTOR     Vector168
+
+/* Serial attributes.*/
+#define KINETIS_HAS_SERIAL0         TRUE
+#define KINETIS_SERIAL0_IRQ_VECTOR  VectorBC
+#define KINETIS_SERIAL0_ERROR_IRQ_VECTOR VectorC0
+#define KINETIS_SERIAL0_IS_LPUART   FALSE
+#define KINETIS_SERIAL0_IS_UARTLP   FALSE
+
+#define KINETIS_HAS_SERIAL1         TRUE
+#define KINETIS_SERIAL1_IRQ_VECTOR  VectorC4
+#define KINETIS_SERIAL1_ERROR_IRQ_VECTOR VectorC8
+#define KINETIS_SERIAL1_IS_LPUART   FALSE
+
+#define KINETIS_HAS_SERIAL2         TRUE
+#define KINETIS_SERIAL2_IRQ_VECTOR  VectorCC
+#define KINETIS_SERIAL2_ERROR_IRQ_VECTOR VectorD0
+
+#define KINETIS_HAS_SERIAL3         TRUE
+#define KINETIS_SERIAL3_IRQ_VECTOR  VectorD4
+#define KINETIS_SERIAL3_ERROR_IRQ_VECTOR VectorD8
+
+#define KINETIS_HAS_SERIAL4         TRUE
+#define KINETIS_SERIAL4_IRQ_VECTOR  Vector148
+#define KINETIS_SERIAL4_ERROR_IRQ_VECTOR Vector14C
+
+#define KINETIS_HAS_SERIAL5         TRUE
+#define KINETIS_SERIAL5_IRQ_VECTOR  Vector150
+#define KINETIS_SERIAL5_ERROR_IRQ_VECTOR Vector154
+
+#define KINETIS_HAS_SERIAL_ERROR_IRQ TRUE
+
+/* SPI attributes.*/
+#define KINETIS_HAS_SPI0            TRUE
+#define KINETIS_SPI0_IRQ_VECTOR     VectorA8
+#define KINETIS_HAS_SPI1            TRUE
+#define KINETIS_SPI1_IRQ_VECTOR     VectorAC
+#define KINETIS_HAS_SPI2            TRUE
+#define KINETIS_SPI2_IRQ_VECTOR     Vector144
+
+/* FlexTimer attributes.*/
+#define KINETIS_FTM0_CHANNELS 8
+#define KINETIS_FTM1_CHANNELS 2
+#define KINETIS_FTM2_CHANNELS 2
+#define KINETIS_FTM3_CHANNELS 8
+
+#define KINETIS_FTM0_IRQ_VECTOR     VectorE8
+#define KINETIS_FTM1_IRQ_VECTOR     VectorEC
+#define KINETIS_FTM2_IRQ_VECTOR     VectorF0
+#define KINETIS_HAS_FTM2            TRUE
+#define KINETIS_FTM3_IRQ_VECTOR     Vector15C
+#define KINETIS_HAS_FTM3            TRUE
+
+/* GPT attributes.*/
+#define KINETIS_HAS_PIT0            TRUE
+#define KINETIS_PIT0_IRQ_VECTOR     Vector100
+#define KINETIS_HAS_PIT1            TRUE
+#define KINETIS_PIT1_IRQ_VECTOR     Vector104
+#define KINETIS_HAS_PIT2            TRUE
+#define KINETIS_PIT2_IRQ_VECTOR     Vector108
+#define KINETIS_HAS_PIT3            TRUE
+#define KINETIS_PIT3_IRQ_VECTOR     Vector10C
+#define KINETIS_HAS_PIT_COMMON_IRQ  FALSE
+
+/* USB attributes.*/
+#define KINETIS_HAS_USB             TRUE
+#define KINETIS_USB_IRQ_VECTOR      Vector114
+#define KINETIS_USB0_IS_USBOTG      TRUE
+#define KINETIS_HAS_USB_CLOCK_RECOVERY TRUE
+
+/* SDHC (SDC, MMC, SDIO) attributes */
+#define KINETIS_HAS_SDHC            TRUE
+#define KINETIS_SDHC_IRQ_VECTOR     Vector184
+
+/* LPTMR attributes.*/
+#define KINETIS_LPTMR0_IRQ_VECTOR   Vector128
+
+#endif
+/** @} */
+
+#endif /* KINETIS_REGISTRY_H_ */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/K60x/platform.mk b/os/hal/ports/KINETIS/K60x/platform.mk
new file mode 100644
index 0000000..33ac2cc
--- /dev/null
+++ b/os/hal/ports/KINETIS/K60x/platform.mk
@@ -0,0 +1,19 @@
+# List of all platform files.
+PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
+              ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K60x/hal_lld.c \
+              ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_pal_lld.c \
+              ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_serial_lld.c \
+              ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_ext_lld.c \
+              ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_gpt_lld.c \
+              ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_st_lld.c \
+              ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_sdc_lld.c \
+              ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c \
+              ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_adc_lld.c \
+#             ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K60x/hal_spi_lld.c \
+#             ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K60x/hal_pwm_lld.c \
+#             ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_usb_lld.c
+
+# Required include directories
+PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
+              ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/K60x \
+              ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD
-- 
cgit v1.2.3


From 527ddd6e45c8682693deff351c544fb72e151979 Mon Sep 17 00:00:00 2001
From: Wim Lewis <wiml@hhhh.org>
Date: Sat, 6 Jan 2018 03:13:21 -0800
Subject: Board definitions for the PJRC Teensy 3.5, based on the Kinetis K64.

---
 os/hal/boards/PJRC_TEENSY_3_5/board.c  | 218 +++++++++++++++++++++++++++++
 os/hal/boards/PJRC_TEENSY_3_5/board.h  | 242 +++++++++++++++++++++++++++++++++
 os/hal/boards/PJRC_TEENSY_3_5/board.mk |   5 +
 3 files changed, 465 insertions(+)
 create mode 100644 os/hal/boards/PJRC_TEENSY_3_5/board.c
 create mode 100644 os/hal/boards/PJRC_TEENSY_3_5/board.h
 create mode 100644 os/hal/boards/PJRC_TEENSY_3_5/board.mk

(limited to 'os')

diff --git a/os/hal/boards/PJRC_TEENSY_3_5/board.c b/os/hal/boards/PJRC_TEENSY_3_5/board.c
new file mode 100644
index 0000000..e93e11d
--- /dev/null
+++ b/os/hal/boards/PJRC_TEENSY_3_5/board.c
@@ -0,0 +1,218 @@
+/*
+    ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde
+              Copyright (C) 2017 Wim Lewis
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+
+#define SOME_GPIO PAL_MODE_INPUT_PULLUP
+
+const PALConfig pal_default_config =
+{
+    .ports = {
+        {
+            /*
+             * PORTA setup.
+             *
+             * PTA0 -PTA3  -- bootloading coprocessor
+             * PTA5        -- PIN25
+             * PTA12-PTA13 -- PIN3-PIN4
+             * PTA14-PTA16 -- PIN26-PIN28
+             * PTA17       -- PIN39 / A20
+             * PTA26       -- PIN42
+             * PTA28       -- PIN40
+             * PTA29       -- PIN41
+             *
+             * PTA18/19 crystal
+             */
+            .port = IOPORT1,
+            .pads = {
+                /* PTA0-PTA3 -- bootloading coprocessor */
+                PAL_MODE_ALTERNATIVE_7,     PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_ALTERNATIVE_7,
+
+                PAL_MODE_UNCONNECTED,
+                PAL_MODE_OUTPUT_PUSHPULL,       /* PIN25 */
+                PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,           /* PIN3 */
+                PAL_MODE_OUTPUT_PUSHPULL,       /* PIN4 */
+                PAL_MODE_OUTPUT_PUSHPULL,       /* PIN26 */
+                PAL_MODE_UNCONNECTED,           /* PIN27 */
+                PAL_MODE_UNCONNECTED,           /* PIN28 */
+                PAL_MODE_UNCONNECTED,           /* PIN39 */
+                PAL_MODE_INPUT_ANALOG,          /* XTAL0 */
+                PAL_MODE_INPUT_ANALOG,          /* XTAL0 */
+                PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,           /* PIN42 */
+                PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,           /* PIN40 */
+                PAL_MODE_UNCONNECTED,           /* PIN41 */
+                PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,
+            },
+        },
+        {
+            /*
+             * PORTB setup.
+             *
+             * PTB0  - PIN16
+             * PTB1  - PIN17
+             * PTB2  - PIN19
+             * PTB3  - PIN18
+	     * PTB10 - PIN31
+	     * PTB11 - PIN32
+             * PTB16 - PIN0 - UART0_TX
+             * PTB17 - PIN1 - UART0_RX
+             * PTB18 - PIN32
+             * PTB19 - PIN25
+             */
+            .port = IOPORT2,
+            .pads = {
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   SOME_GPIO,       SOME_GPIO,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       SOME_GPIO,       SOME_GPIO,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_ALTERNATIVE_3,     PAL_MODE_ALTERNATIVE_3,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   SOME_GPIO,
+                SOME_GPIO,       SOME_GPIO,       SOME_GPIO,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+        {
+            /*
+             * PORTC setup.
+             *
+             * PTC0  - PIN15
+             * PTC1  - PIN22
+             * PTC2  - PIN23
+             * PTC3  - PIN9
+             * PTC4  - PIN10
+             * PTC5  - PIN13
+             * PTC6  - PIN11
+             * PTC7  - PIN12
+             * PTC8  - PIN35
+             * PTC9  - PIN36
+             * PTC10 - PIN37
+             * PTC11 - PIN38
+             */
+            .port = IOPORT3,
+            .pads = {
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+        {
+            /*
+             * PORTD setup.
+             *
+             * PTD0  - PIN2
+             * PTD1  - PIN14
+             * PTD2  - PIN7
+             * PTD3  - PIN8
+             * PTD4  - PIN6
+             * PTD5  - PIN20
+             * PTD6  - PIN21
+             * PTD7  - PIN5
+             */
+            .port = IOPORT4,
+            .pads = {
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   SOME_GPIO,
+                PAL_MODE_UNCONNECTED,       SOME_GPIO,       SOME_GPIO,
+                SOME_GPIO,       SOME_GPIO,       SOME_GPIO,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+        {
+            /*
+             * PORTE setup.
+             *
+	     * PTE0  - PTE5   -- SDHC slot
+	     * PTE6           -- USB OTG power switch (Teensy3.6 only)
+             * PTE10 - PIN56
+             * PTE11 - PIN57
+             * PTE24 - PIN33
+             * PTE25 - PIN34
+             * PTE26 - PIN24
+             */
+            .port = IOPORT5,
+            .pads = {
+                PAL_MODE_ALTERNATIVE_4,     PAL_MODE_ALTERNATIVE_4,     PAL_MODE_ALTERNATIVE_4,
+                PAL_MODE_ALTERNATIVE_4,     PAL_MODE_ALTERNATIVE_4,     PAL_MODE_ALTERNATIVE_4,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+    },
+};
+#endif
+
+/**
+ * @brief   Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ *          and before any other initialization.
+ */
+void __early_init(void) {
+
+  k60x_clock_init();
+}
+
+/**
+ * @brief   Board-specific initialization code.
+ * @todo    Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/PJRC_TEENSY_3_5/board.h b/os/hal/boards/PJRC_TEENSY_3_5/board.h
new file mode 100644
index 0000000..cd33874
--- /dev/null
+++ b/os/hal/boards/PJRC_TEENSY_3_5/board.h
@@ -0,0 +1,242 @@
+/*
+    ChibiOS - Copyright (C) 2017 Wim Lewis
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the PJRC Teensy 3.5 board.
+ */
+
+/*
+ * Board identifier
+ */
+#define BOARD_PJRC_TEENSY_3_5
+#define BOARD_NAME                  "PJRC Teensy 3.5"
+
+/* External 16 MHz crystal */
+#define KINETIS_XTAL_FREQUENCY      16000000UL
+
+/* Use internal capacitors for the crystal */
+#define KINETIS_BOARD_OSCILLATOR_SETTING OSC_CR_SC8P|OSC_CR_SC2P
+
+/*
+ * MCU type
+ */
+#define K64FX512
+
+/*
+ * IO pin assignments
+ */
+#define TEENSY_PIN25		5
+#define TEENSY_PIN3		12
+#define TEENSY_PIN4		13
+#define TEENSY_PIN26		14
+#define TEENSY_PIN27		15
+#define TEENSY_PIN28		16
+#define TEENSY_PIN39		17
+#define TEENSY_PIN42		26
+#define TEENSY_PIN40		28
+#define TEENSY_PIN41		29
+
+#define TEENSY_PIN25_IOPORT	IOPORT1
+#define TEENSY_PIN3_IOPORT	IOPORT1
+#define TEENSY_PIN4_IOPORT	IOPORT1
+#define TEENSY_PIN26_IOPORT	IOPORT1
+#define TEENSY_PIN27_IOPORT	IOPORT1
+#define TEENSY_PIN28_IOPORT	IOPORT1
+#define TEENSY_PIN39_IOPORT	IOPORT1
+#define TEENSY_PIN42_IOPORT	IOPORT1
+#define TEENSY_PIN40_IOPORT	IOPORT1
+#define TEENSY_PIN41_IOPORT	IOPORT1
+
+#define TEENSY_PIN16		0
+#define TEENSY_PIN17		1
+#define TEENSY_PIN19		2
+#define TEENSY_PIN18		3
+#define TEENSY_PIN49		4
+#define TEENSY_PIN50		5
+#define TEENSY_PIN31		10
+#define TEENSY_PIN32		11
+#define TEENSY_PIN0		16
+#define TEENSY_PIN1		17
+#define TEENSY_PIN29		18
+#define TEENSY_PIN30		19
+#define TEENSY_PIN43		20
+#define TEENSY_PIN46		21
+#define TEENSY_PIN44		22
+#define TEENSY_PIN45		23
+
+#define TEENSY_PIN16_IOPORT	IOPORT2
+#define TEENSY_PIN17_IOPORT	IOPORT2
+#define TEENSY_PIN19_IOPORT	IOPORT2
+#define TEENSY_PIN18_IOPORT	IOPORT2
+#define TEENSY_PIN49_IOPORT	IOPORT2
+#define TEENSY_PIN50_IOPORT	IOPORT2
+#define TEENSY_PIN31_IOPORT	IOPORT2
+#define TEENSY_PIN32_IOPORT	IOPORT2
+#define TEENSY_PIN0_IOPORT	IOPORT2
+#define TEENSY_PIN1_IOPORT	IOPORT2
+#define TEENSY_PIN29_IOPORT	IOPORT2
+#define TEENSY_PIN30_IOPORT	IOPORT2
+#define TEENSY_PIN43_IOPORT	IOPORT2
+#define TEENSY_PIN46_IOPORT	IOPORT2
+#define TEENSY_PIN44_IOPORT	IOPORT2
+#define TEENSY_PIN45_IOPORT	IOPORT2
+
+#define TEENSY_PIN15		0
+#define TEENSY_PIN22		1
+#define TEENSY_PIN23		2
+#define TEENSY_PIN9		3
+#define TEENSY_PIN10		4
+#define TEENSY_PIN13		5
+#define TEENSY_PIN11		6
+#define TEENSY_PIN12		7
+#define TEENSY_PIN35		8
+#define TEENSY_PIN36		9
+#define TEENSY_PIN37		10
+#define TEENSY_PIN38		11
+
+#define TEENSY_PIN15_IOPORT	IOPORT3
+#define TEENSY_PIN22_IOPORT	IOPORT3
+#define TEENSY_PIN23_IOPORT	IOPORT3
+#define TEENSY_PIN9_IOPORT	IOPORT3
+#define TEENSY_PIN10_IOPORT	IOPORT3
+#define TEENSY_PIN13_IOPORT	IOPORT3
+#define TEENSY_PIN11_IOPORT	IOPORT3
+#define TEENSY_PIN12_IOPORT	IOPORT3
+#define TEENSY_PIN35_IOPORT	IOPORT3
+#define TEENSY_PIN36_IOPORT	IOPORT3
+#define TEENSY_PIN37_IOPORT	IOPORT3
+#define TEENSY_PIN38_IOPORT	IOPORT3
+
+#define TEENSY_PIN2		0
+#define TEENSY_PIN14		1
+#define TEENSY_PIN7		2
+#define TEENSY_PIN8		3
+#define TEENSY_PIN6		4
+#define TEENSY_PIN20		5
+#define TEENSY_PIN21		6
+#define TEENSY_PIN5		7
+#define TEENSY_PIN47		8
+#define TEENSY_PIN48		9
+#define TEENSY_PIN55		11
+#define TEENSY_PIN53		12
+#define TEENSY_PIN52		13
+#define TEENSY_PIN51		14
+#define TEENSY_PIN54		15
+
+#define TEENSY_PIN2_IOPORT	IOPORT4
+#define TEENSY_PIN14_IOPORT	IOPORT4
+#define TEENSY_PIN7_IOPORT	IOPORT4
+#define TEENSY_PIN8_IOPORT	IOPORT4
+#define TEENSY_PIN6_IOPORT	IOPORT4
+#define TEENSY_PIN20_IOPORT	IOPORT4
+#define TEENSY_PIN21_IOPORT	IOPORT4
+#define TEENSY_PIN5_IOPORT	IOPORT4
+#define TEENSY_PIN47_IOPORT	IOPORT4
+#define TEENSY_PIN48_IOPORT	IOPORT4
+#define TEENSY_PIN55_IOPORT	IOPORT4
+#define TEENSY_PIN53_IOPORT	IOPORT4
+#define TEENSY_PIN52_IOPORT	IOPORT4
+#define TEENSY_PIN51_IOPORT	IOPORT4
+#define TEENSY_PIN54_IOPORT	IOPORT4
+
+#define TEENSY_PIN56		10
+#define TEENSY_PIN57		11
+#define TEENSY_PIN33		24
+#define TEENSY_PIN34		25
+#define TEENSY_PIN24		26
+
+#define TEENSY_PIN56_IOPORT	IOPORT5
+#define TEENSY_PIN57_IOPORT	IOPORT5
+#define TEENSY_PIN33_IOPORT	IOPORT5
+#define TEENSY_PIN34_IOPORT	IOPORT5
+#define TEENSY_PIN24_IOPORT	IOPORT5
+
+#define LINE_PIN1           PAL_LINE(TEENSY_PIN1_IOPORT, TEENSY_PIN1)
+#define LINE_PIN2           PAL_LINE(TEENSY_PIN2_IOPORT, TEENSY_PIN2)
+#define LINE_PIN3           PAL_LINE(TEENSY_PIN3_IOPORT, TEENSY_PIN3)
+#define LINE_PIN4           PAL_LINE(TEENSY_PIN4_IOPORT, TEENSY_PIN4)
+#define LINE_PIN5           PAL_LINE(TEENSY_PIN5_IOPORT, TEENSY_PIN5)
+#define LINE_PIN6           PAL_LINE(TEENSY_PIN6_IOPORT, TEENSY_PIN6)
+#define LINE_PIN7           PAL_LINE(TEENSY_PIN7_IOPORT, TEENSY_PIN7)
+#define LINE_PIN8           PAL_LINE(TEENSY_PIN8_IOPORT, TEENSY_PIN8)
+#define LINE_PIN9           PAL_LINE(TEENSY_PIN9_IOPORT, TEENSY_PIN9)
+#define LINE_PIN10          PAL_LINE(TEENSY_PIN10_IOPORT, TEENSY_PIN10)
+#define LINE_PIN11          PAL_LINE(TEENSY_PIN11_IOPORT, TEENSY_PIN11)
+#define LINE_PIN12          PAL_LINE(TEENSY_PIN12_IOPORT, TEENSY_PIN12)
+#define LINE_PIN13          PAL_LINE(TEENSY_PIN13_IOPORT, TEENSY_PIN13)
+#define LINE_PIN14          PAL_LINE(TEENSY_PIN14_IOPORT, TEENSY_PIN14)
+#define LINE_PIN15          PAL_LINE(TEENSY_PIN15_IOPORT, TEENSY_PIN15)
+#define LINE_PIN16          PAL_LINE(TEENSY_PIN16_IOPORT, TEENSY_PIN16)
+#define LINE_PIN17          PAL_LINE(TEENSY_PIN17_IOPORT, TEENSY_PIN17)
+#define LINE_PIN18          PAL_LINE(TEENSY_PIN18_IOPORT, TEENSY_PIN18)
+#define LINE_PIN19          PAL_LINE(TEENSY_PIN19_IOPORT, TEENSY_PIN19)
+#define LINE_PIN20          PAL_LINE(TEENSY_PIN20_IOPORT, TEENSY_PIN20)
+#define LINE_PIN21          PAL_LINE(TEENSY_PIN21_IOPORT, TEENSY_PIN21)
+#define LINE_PIN22          PAL_LINE(TEENSY_PIN22_IOPORT, TEENSY_PIN22)
+#define LINE_PIN23          PAL_LINE(TEENSY_PIN23_IOPORT, TEENSY_PIN23)
+#define LINE_PIN24          PAL_LINE(TEENSY_PIN24_IOPORT, TEENSY_PIN24)
+#define LINE_PIN25          PAL_LINE(TEENSY_PIN25_IOPORT, TEENSY_PIN25)
+#define LINE_PIN25          PAL_LINE(TEENSY_PIN25_IOPORT, TEENSY_PIN25)
+#define LINE_PIN26          PAL_LINE(TEENSY_PIN26_IOPORT, TEENSY_PIN26)
+#define LINE_PIN27          PAL_LINE(TEENSY_PIN27_IOPORT, TEENSY_PIN27)
+#define LINE_PIN28          PAL_LINE(TEENSY_PIN28_IOPORT, TEENSY_PIN28)
+#define LINE_PIN29          PAL_LINE(TEENSY_PIN29_IOPORT, TEENSY_PIN29)
+#define LINE_PIN30          PAL_LINE(TEENSY_PIN30_IOPORT, TEENSY_PIN30)
+#define LINE_PIN31          PAL_LINE(TEENSY_PIN31_IOPORT, TEENSY_PIN31)
+#define LINE_PIN32          PAL_LINE(TEENSY_PIN32_IOPORT, TEENSY_PIN32)
+#define LINE_PIN33          PAL_LINE(TEENSY_PIN33_IOPORT, TEENSY_PIN33)
+#define LINE_PIN34          PAL_LINE(TEENSY_PIN34_IOPORT, TEENSY_PIN34)
+#define LINE_PIN35          PAL_LINE(TEENSY_PIN35_IOPORT, TEENSY_PIN35)
+#define LINE_PIN36          PAL_LINE(TEENSY_PIN36_IOPORT, TEENSY_PIN36)
+#define LINE_PIN37          PAL_LINE(TEENSY_PIN37_IOPORT, TEENSY_PIN37)
+#define LINE_PIN38          PAL_LINE(TEENSY_PIN38_IOPORT, TEENSY_PIN38)
+#define LINE_PIN39          PAL_LINE(TEENSY_PIN39_IOPORT, TEENSY_PIN39)
+#define LINE_PIN40          PAL_LINE(TEENSY_PIN40_IOPORT, TEENSY_PIN40)
+#define LINE_PIN41          PAL_LINE(TEENSY_PIN41_IOPORT, TEENSY_PIN41)
+#define LINE_PIN42          PAL_LINE(TEENSY_PIN42_IOPORT, TEENSY_PIN42)
+#define LINE_PIN43          PAL_LINE(TEENSY_PIN43_IOPORT, TEENSY_PIN43)
+#define LINE_PIN44          PAL_LINE(TEENSY_PIN44_IOPORT, TEENSY_PIN44)
+#define LINE_PIN45          PAL_LINE(TEENSY_PIN45_IOPORT, TEENSY_PIN45)
+#define LINE_PIN46          PAL_LINE(TEENSY_PIN46_IOPORT, TEENSY_PIN46)
+#define LINE_PIN47          PAL_LINE(TEENSY_PIN47_IOPORT, TEENSY_PIN47)
+#define LINE_PIN48          PAL_LINE(TEENSY_PIN48_IOPORT, TEENSY_PIN48)
+#define LINE_PIN49          PAL_LINE(TEENSY_PIN49_IOPORT, TEENSY_PIN49)
+#define LINE_PIN50          PAL_LINE(TEENSY_PIN50_IOPORT, TEENSY_PIN50)
+#define LINE_PIN51          PAL_LINE(TEENSY_PIN51_IOPORT, TEENSY_PIN51)
+#define LINE_PIN52          PAL_LINE(TEENSY_PIN52_IOPORT, TEENSY_PIN52)
+#define LINE_PIN53          PAL_LINE(TEENSY_PIN53_IOPORT, TEENSY_PIN53)
+#define LINE_PIN54          PAL_LINE(TEENSY_PIN54_IOPORT, TEENSY_PIN54)
+#define LINE_PIN55          PAL_LINE(TEENSY_PIN55_IOPORT, TEENSY_PIN55)
+#define LINE_PIN56          PAL_LINE(TEENSY_PIN56_IOPORT, TEENSY_PIN56)
+#define LINE_PIN57          PAL_LINE(TEENSY_PIN57_IOPORT, TEENSY_PIN57)
+
+#define LINE_LED            LINE_PIN13
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
+
diff --git a/os/hal/boards/PJRC_TEENSY_3_5/board.mk b/os/hal/boards/PJRC_TEENSY_3_5/board.mk
new file mode 100644
index 0000000..4e18eb0
--- /dev/null
+++ b/os/hal/boards/PJRC_TEENSY_3_5/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_3_5/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_3_5
-- 
cgit v1.2.3


From ee3f7f1b8557f21918822009435501c618aa3535 Mon Sep 17 00:00:00 2001
From: Wim Lewis <wiml@hhhh.org>
Date: Sat, 6 Jan 2018 03:17:53 -0800
Subject: Low-level driver for the Kinetis SDHC peripheral as found on the
 MK64FX512 and other members of the Kinetis family.

---
 os/hal/ports/KINETIS/LLD/hal_sdc_lld.c | 905 +++++++++++++++++++++++++++++++++
 os/hal/ports/KINETIS/LLD/hal_sdc_lld.h | 202 ++++++++
 2 files changed, 1107 insertions(+)
 create mode 100644 os/hal/ports/KINETIS/LLD/hal_sdc_lld.c
 create mode 100644 os/hal/ports/KINETIS/LLD/hal_sdc_lld.h

(limited to 'os')

diff --git a/os/hal/ports/KINETIS/LLD/hal_sdc_lld.c b/os/hal/ports/KINETIS/LLD/hal_sdc_lld.c
new file mode 100644
index 0000000..30d8f99
--- /dev/null
+++ b/os/hal/ports/KINETIS/LLD/hal_sdc_lld.c
@@ -0,0 +1,905 @@
+/*
+    ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+              Copyright (C) 2017 Wim Lewis
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    hal_sdc_lld.c
+ * @brief   Kinetis SDC subsystem low level driver.
+ *
+ * @addtogroup SDC
+ * @{
+ */
+
+#include "hal.h"
+
+#if (HAL_USE_SDC == TRUE) || defined(__DOXYGEN__)
+
+#include "hal_mmcsd.h"
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/* We configure the SDHC block to use the system clock */
+#define KINETIS_SDHC_PERIPHERAL_FREQUENCY KINETIS_SYSCLK_FREQUENCY
+
+#ifndef KINETIS_SDHC_PRIORITY
+#define KINETIS_SDHC_PRIORITY 12 /* TODO? Default IRQ priority for SDHC */
+#endif
+
+/* The DTOC value (data timeout counter) controls how long the SDHC
+   will wait for a data transfer before indicating a timeout to
+   us. The card can tell us how long that should be, but various SDHC
+   documentation suggests that we should always allow around 500 msec
+   even if the card says it will finish sooner. This only comes into
+   play if there's a malfunction or something, so it's not critical to
+   get it exactly right.
+
+   It controls the ratio between the SDCLK frequency and the
+   timeout, so we have a different DTOCV for each bus clock
+   frequency.
+*/
+#define DTOCV_300ms_400kHz    4  /* 4  -> 2^17 -> 328 msec */
+#define DTOCV_700ms_25MHz    11  /* 11 -> 2^24 -> 671 msec */
+#define DTOCV_700ms_50MHz    12  /* 12 -> 2^25 -> 671 msec */
+
+#define TRACE(t, val)   chDbgWriteTrace ((void *)t, (void *)(uintptr_t)(val))
+#define TRACEI(t, val)  chDbgWriteTraceI((void *)t, (void *)(uintptr_t)(val))
+
+#define DIV_RND_UP(a, b) ( ((a)+(b)-1) / (b) )
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   SDCD1 driver identifier.
+ */
+#if (PLATFORM_SDC_USE_SDC1 == TRUE) || defined(__DOXYGEN__)
+SDCDriver SDCD1;
+#else
+#error HAL_USE_SDC is true but PLATFORM_SDC_USE_SDC1 is false
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+static void recover_after_botched_transfer(SDCDriver *);
+static msg_t wait_interrupt(SDCDriver *, uint32_t);
+static bool sdc_lld_transfer(SDCDriver *, uint32_t, uintptr_t, uint32_t, uint32_t);
+
+/**
+ * Compute the SDCLKFS and DVS values for a given SDCLK divisor.
+ *
+ * Note that in the current code, this function is always called with
+ * a constant argument (there are only a handful of valid SDCLK
+ * frequencies), and so GCC computes the results at compile time and
+ * does not actually emit this function into the output at all unless
+ * you're compiling with optimizations turned off.
+ *
+ * However if someone compiles with a KINETIS_SDHC_PERIPHERAL_FREQUENCY
+ * that is not a compile-tie constant, this function would get emitted.
+ */
+static uint32_t divisor_settings(unsigned divisor)
+{
+  /* First, handle all the special cases */
+  if (divisor <= 1) {
+    /* Pass through */
+    return SDHC_SYSCTL_SDCLKFS(0) | SDHC_SYSCTL_DVS(0);
+  }
+  if (divisor <= 16 && (divisor & 0x01)) {
+    /* Disable the prescaler, just use the divider. */
+    return SDHC_SYSCTL_SDCLKFS(0) | SDHC_SYSCTL_DVS(divisor - 1);
+  }
+  if (divisor <= 32 && !(divisor & 0x01)) {
+    /* Prescale by 2, but do the rest with the divider */
+    return SDHC_SYSCTL_SDCLKFS(0x01) | SDHC_SYSCTL_DVS((divisor >> 1) - 1);
+  }
+  if (divisor >= 0x1000) {
+    /* It's not possible to divide by more than 2^12. If we're asked to,
+       just do the best we can. */
+    return SDHC_SYSCTL_SDCLKFS(0x80) | SDHC_SYSCTL_DVS(0xF);
+  }
+
+  /* The bit position in SDCLKFS provides a power-of-two prescale
+     factor, and the four bits in DVS allow division by up to 16
+     (division by DVS+1). We want to approximate `divisor` using these
+     terms, but we want to round up --- it's OK to run the card a
+     little bit too slow, but not OK to run it a little bit too
+     fast. */
+
+  unsigned shift = (8 * sizeof(unsigned int) - 4) - __builtin_clz(divisor);
+
+  /* Shift the divisor value right so that it only occupies the four
+     lowest bits. Subtract one because that's how the DVS circuit
+     works. Add one if we shifted any 1-bits off the bottom, so that
+     we always round up. */
+  unsigned dvs = (divisor >> shift) - ((divisor & ((1 << shift)-1))? 0 : 1);
+
+  return SDHC_SYSCTL_SDCLKFS(1 << (shift-1)) | SDHC_SYSCTL_DVS(dvs);
+}
+
+/**
+ * @brief Enable the SDHC clock when stable.
+ *
+ * Waits for the clock divider in the SDHC block to stabilize, then
+ * enables the SD clock.
+ */
+static void enable_clock_when_stable(uint32_t new_sysctl)
+{
+  SDHC->SYSCTL = new_sysctl;
+  
+  /* Wait for clock divider to stabilize */
+  while(!(SDHC->PRSSTAT & SDHC_PRSSTAT_SDSTB)) {
+    osalThreadSleepMilliseconds(1);
+  }
+
+  /* Restart the clock */
+  SDHC->SYSCTL = new_sysctl | SDHC_SYSCTL_SDCLKEN;
+}
+
+/**
+ * Translate error bits from a CMD transaction to the HAL's error flag set.
+ */
+static sdcflags_t translate_cmd_error(uint32_t status) {
+  /* Translate the failure into the flags understood by the top half */
+
+  sdcflags_t errors = 0;
+
+  if (status & SDHC_IRQSTAT_CTOE || !(status & SDHC_IRQSTAT_CC)) {
+    errors |= SDC_COMMAND_TIMEOUT;
+  }
+  if (status & SDHC_IRQSTAT_CCE) {
+    errors |= SDC_CMD_CRC_ERROR;
+  }
+
+  /* If CTOE and CCE are both set, this indicates that the Kinetis
+     SDHC peripheral has detected a CMD line conflict in a
+     multi-master scenario. There's no specific code for that, so just
+     pass it through as a combined timeout+CRC failure. */
+
+  /* Translate any other framing and protocol errors into CRC errors. */
+  if (status & ~(SDHC_IRQSTAT_CCE|SDHC_IRQSTAT_CTOE|SDHC_IRQSTAT_CC)) {
+    errors |= SDC_CMD_CRC_ERROR;
+  }
+
+  return errors;
+}
+
+/**
+ * @brief Perform one CMD transaction on the SD bus.
+ */
+static bool send_and_wait_cmd(SDCDriver *sdcp, uint32_t cmd) {
+  /* SDCLKEN (CMD clock enabled) should be true;
+   * SDSTB (clock stable) should be true;
+   * CIHB (command inhibit / busy) should be false */
+  osalDbgAssert((SDHC->PRSSTAT & (SDHC_PRSSTAT_SDSTB|SDHC_PRSSTAT_CIHB)) == SDHC_PRSSTAT_SDSTB, "Not in expected state");
+  osalDbgAssert(SDHC->SYSCTL & SDHC_SYSCTL_SDCLKEN, "Clock disabled");
+  osalDbgCheck((cmd & SDHC_XFERTYP_DPSEL) == 0);
+
+  /* This initiates the CMD transaction */
+  TRACE(1, cmd);
+  SDHC->XFERTYP = cmd;
+
+  /* TODO: Wait on the completion interrupt instead of spin-polling. Are we in a sys-locked state at this point or not? */
+
+  int spincount = 0;
+  uint32_t status;
+  uint32_t events =
+    SDHC_IRQSTAT_CIE | SDHC_IRQSTAT_CEBE | SDHC_IRQSTAT_CCE |
+    SDHC_IRQSTAT_CTOE | /* SDHC_IRQSTAT_CRM | */ SDHC_IRQSTAT_CC;
+  for(;;) {
+    status = SDHC->IRQSTAT & events;
+    if (status & (SDHC_IRQSTAT_CTOE | SDHC_IRQSTAT_CC))
+      break;
+    osalThreadSleepMilliseconds(1);
+    spincount ++;
+    if (spincount > 1000) {
+      /* Shouldn't happen: the SDHC controller has its own timeout
+	 mechanism and should eventually set CTOE, unless we've done
+	 something like accidentally gate off the clock to the SDHC
+	 module */
+      break;
+    }
+  }
+
+  TRACE(2, status);
+
+  /* These bits are write-1-to-clear (w1c) */
+  SDHC->IRQSTAT = status;
+
+  /* In the normal case, the CC (command complete) bit is set but none
+     of the others are */
+  if (status == SDHC_IRQSTAT_CC)
+    return HAL_SUCCESS;
+
+  /* Translate the failure into the flags understood by the top half */
+  sdcp->errors |= translate_cmd_error(status);
+
+  /* Issue a reset to the CMD portion of the SDHC peripheral to clear the
+     error bits and enable subsequent commands */
+  SDHC->SYSCTL |= SDHC_SYSCTL_RSTC;
+
+  return HAL_FAILED;
+}
+
+/**
+ * @brief Perform one data transaction on the SD bus.
+ */
+static bool send_and_wait_transfer(SDCDriver *sdcp, uint32_t cmd) {
+
+  osalDbgCheck(cmd & SDHC_XFERTYP_DPSEL);
+  osalDbgCheck(cmd & SDHC_XFERTYP_DMAEN);
+
+  const uint32_t cmd_end_bits =
+    SDHC_IRQSTAT_CIE | SDHC_IRQSTAT_CEBE | SDHC_IRQSTAT_CCE |
+    SDHC_IRQSTAT_CTOE | /* SDHC_IRQSTAT_CRM | */ SDHC_IRQSTAT_CC;
+
+  const uint32_t transfer_end_bits =
+    SDHC_IRQSTAT_DMAE | SDHC_IRQSTAT_AC12E | SDHC_IRQSTAT_DEBE |
+    SDHC_IRQSTAT_DCE | SDHC_IRQSTAT_DTOE | SDHC_IRQSTAT_TC;
+
+  TRACE(3, cmd);
+
+  osalSysLock();
+  osalDbgCheck(sdcp->thread == NULL);
+
+  /* Clear anything pending from an earlier transfer */
+  SDHC->IRQSTAT = cmd_end_bits | transfer_end_bits | SDHC_IRQSTAT_DINT;
+
+  /* Enable interrupts on completions or failures */
+  uint32_t old_staten = SDHC->IRQSTATEN;
+  SDHC->IRQSTATEN = (old_staten & ~(SDHC_IRQSTAT_BRR|SDHC_IRQSTAT_BWR)) | (cmd_end_bits | transfer_end_bits | SDHC_IRQSTAT_DINT);
+  SDHC->IRQSIGEN = SDHC_IRQSTAT_CTOE | SDHC_IRQSTAT_CC;
+
+  /* Start the transfer */
+  SDHC->XFERTYP = cmd;
+
+  /* Await an interrupt */
+  osalThreadSuspendS(&sdcp->thread);
+  osalSysUnlock();
+
+  /* Retrieve the flags and clear them */
+  uint32_t cmdstat = SDHC->IRQSTAT & cmd_end_bits;
+  SDHC->IRQSTAT = cmdstat;
+  TRACE(2, cmdstat);
+
+  /* If the command failed, the transfer won't happen */
+  if (cmdstat != SDHC_IRQSTAT_CC) {
+    /* The command couldn't be sent, or wasn't acknowledged */
+    sdcp->errors |= translate_cmd_error(cmdstat);
+
+    /* Clear the error status */
+    SDHC->SYSCTL |= SDHC_SYSCTL_RSTC;
+
+    if (cmdstat == (SDHC_IRQSTAT_CCE|SDHC_IRQSTAT_CTOE)) {
+      /* A CMD-line conflict is unlikely, but doesn't require further recovery */
+    } else {
+      /* For most error situations, we don't know whether the command
+	 failed to send or we got line noise while receiving. Make sure
+	 we're in a sane state by resetting the connection. */
+      recover_after_botched_transfer(sdcp);
+    }
+
+    return HAL_FAILED;
+  }
+
+  uint32_t cmdresp = SDHC->CMDRSP[0];
+  if (cmdresp & MMCSD_R1_ERROR_MASK) {
+    /* The command was sent, and the card responded with an error indication */
+    /* TODO: See which errors can be translated into HAL errors? */
+    sdcp->errors |= SDC_UNHANDLED_ERROR;
+    return HAL_FAILED;
+  }
+
+  /* Check for end of data transfer phase */
+  uint32_t datastat;
+  for (;;) {
+    datastat = SDHC->IRQSTAT & (transfer_end_bits | SDHC_IRQSTAT_DINT);
+    if (datastat & transfer_end_bits)
+      break;
+    wait_interrupt(sdcp, transfer_end_bits);
+  }
+  TRACE(6, datastat);
+  SDHC->IRQSTAT = datastat;
+
+  /* Handle data transfer errors */
+  if ((datastat & ~(SDHC_IRQSTAT_DINT)) != SDHC_IRQSTAT_TC) {
+    bool should_cancel = false;
+
+    /* Data phase errors */
+    if (datastat & (SDHC_IRQSTAT_DCE|SDHC_IRQSTAT_DEBE)) {
+      sdcp->errors |= SDC_DATA_CRC_ERROR;
+      should_cancel = true;
+    }
+    if (datastat & SDHC_IRQSTAT_DTOE) {
+      sdcp->errors |= SDC_DATA_TIMEOUT;
+      should_cancel = true;
+    }
+
+    /* Internal DMA error */
+    if (datastat & SDHC_IRQSTAT_DMAE) {
+      sdcp->errors |= SDC_UNHANDLED_ERROR;
+      if (!(datastat & SDHC_IRQSTAT_TC))
+	should_cancel = true;
+    }
+
+    if (datastat & SDHC_IRQSTAT_AC12E) {
+      uint32_t cmd12error = SDHC->AC12ERR;
+
+      /* We don't know if CMD12 was successfully executed */
+      should_cancel = true;
+
+      if (cmd12error & SDHC_AC12ERR_AC12NE) {
+	sdcp->errors |= SDC_UNHANDLED_ERROR;
+      } else {
+	if (cmd12error & SDHC_AC12ERR_AC12TOE)
+	  sdcp->errors |= SDC_COMMAND_TIMEOUT;
+	if (cmd12error & (SDHC_AC12ERR_AC12CE|SDHC_AC12ERR_AC12EBE))
+	  sdcp->errors |= SDC_CMD_CRC_ERROR;
+      }
+    }
+
+    if (should_cancel)
+      recover_after_botched_transfer(sdcp);
+
+    return HAL_FAILED;
+  }
+
+  /* For a read transfer, make sure the DMA has finished transferring
+   * to host memory. (For a write transfer, the DMA necessarily finishes
+   * before the transfer does, so we don't need to wait for it
+   * specially.) */
+  if (!(datastat & SDHC_IRQSTAT_DINT)) {
+    for(;;) {
+      datastat = SDHC->IRQSTAT & (SDHC_IRQSTAT_DINT|SDHC_IRQSTAT_DMAE);
+      if (datastat) {
+	SDHC->IRQSTAT = datastat;
+	TRACE(7, datastat);
+	break;
+      }
+      /* ...?? */
+    }
+  }
+
+  SDHC->IRQSTATEN = old_staten;
+
+  return HAL_SUCCESS;
+}
+
+/**
+ * @brief Wait for an interrupt from the SDHC peripheral.
+ *
+ * @param[in] mask    Bits to enable in IRQSIGEN.
+ *
+ * @return            MSG_OK
+ */
+static msg_t wait_interrupt(SDCDriver *sdcp, uint32_t mask) {
+  osalSysLock();
+  SDHC->IRQSIGEN = mask;
+  msg_t wakeup = osalThreadSuspendS(&sdcp->thread);
+  osalSysUnlock();
+  return wakeup;
+}
+
+static void recover_after_botched_transfer(SDCDriver *sdcp) {
+
+  /* Send a CMD12 to make sure the card isn't still transferring anything */
+  send_and_wait_cmd(sdcp, MMCSD_CMD_STOP_TRANSMISSION);
+
+  /* And reset the data block of the SDHC peripheral */
+  SDHC->SYSCTL |= SDHC_SYSCTL_RSTD;
+}
+
+/**
+ * @brief Perform one data transfer command
+ *
+ * Sends a command to the card and waits for the corresponding data transfer
+ * (either a read or write) to complete.
+ */
+static bool sdc_lld_transfer(SDCDriver *sdcp, uint32_t startblk,
+			     uintptr_t buf, uint32_t n,
+			     uint32_t cmdx) {
+
+  osalDbgCheck(n > 0);
+  osalDbgCheck((buf & 0x03) == 0);  /* Must be 32-bit aligned */
+
+  osalDbgAssert((SDHC->PRSSTAT & (SDHC_PRSSTAT_DLA|SDHC_PRSSTAT_CDIHB|SDHC_PRSSTAT_CIHB)) == 0,
+		"SDHC interface not ready");
+
+  /* We always operate in terms of 512-byte blocks; the upper-layer
+     driver doesn't change the block size. The SDHC spec suggests that
+     only low-capacity cards support block sizes other than 512 bytes
+     anyway (SDHC "Physical Layer Simplified Specification" ver 6.0) */
+
+  if (sdcp->cardmode & SDC_MODE_HIGH_CAPACITY) {
+    SDHC->CMDARG = startblk;
+  } else {
+    SDHC->CMDARG = startblk * MMCSD_BLOCK_SIZE;
+  }
+
+  /* Store the DMA start address */
+  SDHC->DSADDR = buf;
+
+  uint32_t xfer;
+  /* For data transfers, we need to set some extra bits in XFERTYP according to the
+     transfer we're starting:
+     DPSEL -> enable data transfer
+     DTDSEL -> 1 for a read (card-to-host) transfer
+     MSBSEL, BCEN -> multiple block transfer using BLKATTR_BLKCNT
+     AC12EN -> Automatically issue MMCSD_CMD_STOP_TRANSMISSION at end of transfer
+  */
+  if (n == 1) {
+    SDHC->BLKATTR = SDHC_BLKATTR_BLKSIZE(MMCSD_BLOCK_SIZE);
+    xfer =
+      cmdx |
+      SDHC_XFERTYP_CMDTYP_NORMAL |
+      SDHC_XFERTYP_CICEN | SDHC_XFERTYP_CCCEN |
+      SDHC_XFERTYP_RSPTYP_48b |
+      SDHC_XFERTYP_DPSEL | SDHC_XFERTYP_DMAEN;
+  } else {
+    SDHC->BLKATTR =
+      SDHC_BLKATTR_BLKCNT(n) |
+      SDHC_BLKATTR_BLKSIZE(MMCSD_BLOCK_SIZE);
+    xfer =
+      cmdx |
+      SDHC_XFERTYP_CMDTYP_NORMAL |
+      SDHC_XFERTYP_CICEN | SDHC_XFERTYP_CCCEN |
+      SDHC_XFERTYP_RSPTYP_48b |
+      SDHC_XFERTYP_MSBSEL | SDHC_XFERTYP_BCEN | SDHC_XFERTYP_AC12EN |
+      SDHC_XFERTYP_DPSEL | SDHC_XFERTYP_DMAEN;
+  }
+
+  return send_and_wait_transfer(sdcp, xfer);
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if (PLATFORM_SDC_USE_SDC1 == TRUE) || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SDHC_IRQ_VECTOR) {
+  OSAL_IRQ_PROLOGUE();
+  osalSysLockFromISR();
+
+  TRACEI(4, SDHC->IRQSTAT);
+
+  /* We disable the interrupts, and wake up the usermode task to read
+   * the flags from IRQSTAT.
+   */
+  SDHC->IRQSIGEN = 0;
+
+  osalThreadResumeI(&SDCD1.thread, MSG_OK);
+
+  osalSysUnlockFromISR();
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level SDC driver initialization.
+ *
+ * @notapi
+ */
+void sdc_lld_init(void) {
+#if PLATFORM_SDC_USE_SDC1 == TRUE
+  sdcObjectInit(&SDCD1);
+#endif
+}
+
+
+/**
+ * @brief   Configures and activates the SDC peripheral.
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ *
+ * @notapi
+ */
+void sdc_lld_start(SDCDriver *sdcp) {
+
+  if (sdcp->state == BLK_STOP) {
+    SIM->SOPT2 =
+      (SIM->SOPT2 & ~SIM_SOPT2_SDHCSRC_MASK) |
+      SIM_SOPT2_SDHCSRC(0);  /* SDHC clock source 0: Core/system clock. */
+    SIM->SCGC3 |= SIM_SCGC3_SDHC; /* Enable clock to SDHC peripheral */
+
+    /* Reset the SDHC block */
+    SDHC->SYSCTL |= SDHC_SYSCTL_RSTA;
+    while(SDHC->SYSCTL & SDHC_SYSCTL_RSTA) {
+      osalThreadSleepMilliseconds(1);
+    }
+
+    SDHC->IRQSIGEN = 0;
+    nvicEnableVector(SDHC_IRQn, KINETIS_SDHC_PRIORITY);
+  }
+}
+
+/**
+ * @brief   Deactivates the SDC peripheral.
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ *
+ * @notapi
+ */
+void sdc_lld_stop(SDCDriver *sdcp) {
+
+  if (sdcp->state != BLK_STOP) {
+    /* TODO: Should we perform a reset (RSTA) before putting the
+       peripheral to sleep? */
+
+    /* Disable the card clock */
+    SDHC->SYSCTL &= ~( SDHC_SYSCTL_SDCLKEN );
+
+    /* Turn off interrupts */
+    nvicDisableVector(SDHC_IRQn);
+    SDHC->IRQSIGEN = 0;
+    SDHC->IRQSTATEN &= ~( SDHC_IRQSTATEN_CINTSEN |
+			  SDHC_IRQSTATEN_CINSEN |
+			  SDHC_IRQSTATEN_CRMSEN );
+
+    /* Disable the clock to the SDHC peripheral block */
+    SIM->SCGC3 &= ~( SIM_SCGC3_SDHC );
+  }
+}
+
+/**
+ * @brief   Starts the SDIO clock and sets it to init mode (400kHz or less).
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ *
+ * @notapi
+ */
+void sdc_lld_start_clk(SDCDriver *sdcp) {
+
+  (void)sdcp;
+
+  /* Stop the card clock (it should already be stopped) */
+  SDHC->SYSCTL &= ~( SDHC_SYSCTL_SDCLKEN );
+
+  /* Change the divisor and DTOCV for a 400kHz card closk */
+  uint32_t sysctl =
+    SDHC_SYSCTL_DTOCV(DTOCV_300ms_400kHz) |
+    divisor_settings(DIV_RND_UP(KINETIS_SDHC_PERIPHERAL_FREQUENCY, 400000));
+
+  /* Restart the clock */
+  enable_clock_when_stable(sysctl);
+
+  /* Reset any protocol machinery; this also runs the clock for 80
+     cycles without any data bits to help initalize the card's state
+     (the Kinetis peripheral docs say that this is required after card
+     insertion or power-on, but the abridged SDHC specifications I
+     have don't seem to mention it) */
+  SDHC->SYSCTL |= SDHC_SYSCTL_INITA;
+}
+
+/**
+ * @brief   Sets the SDIO clock to data mode (25MHz or less).
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ * @param[in] clk       the clock mode
+ *
+ * @notapi
+ */
+void sdc_lld_set_data_clk(SDCDriver *sdcp, sdcbusclk_t clk) {
+
+  (void)sdcp;
+
+  /* Stop the card clock */
+  SDHC->SYSCTL &= ~( SDHC_SYSCTL_SDCLKEN );
+
+  /* Change the divisor */
+  uint32_t ctl;
+  switch (clk) {
+  default:
+  case SDC_CLK_25MHz:
+    ctl =
+      SDHC_SYSCTL_DTOCV(DTOCV_700ms_25MHz) |
+      divisor_settings(DIV_RND_UP(KINETIS_SDHC_PERIPHERAL_FREQUENCY, 25000000));
+    break;
+  case SDC_CLK_50MHz:
+    ctl =
+      SDHC_SYSCTL_DTOCV(DTOCV_700ms_50MHz) |
+      divisor_settings(DIV_RND_UP(KINETIS_SDHC_PERIPHERAL_FREQUENCY, 50000000));
+    break;
+  }
+
+  /* Restart the clock */
+  enable_clock_when_stable(ctl);
+}
+
+/**
+ * @brief   Stops the SDIO clock.
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ *
+ * @notapi
+ */
+void sdc_lld_stop_clk(SDCDriver *sdcp) {
+  (void)sdcp;
+  SDHC->SYSCTL &= ~( SDHC_SYSCTL_SDCLKEN );
+}
+
+/**
+ * @brief   Switches the bus to 4 bit or 8 bit mode.
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ * @param[in] mode      bus mode
+ *
+ * @notapi
+ */
+void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode) {
+  (void)sdcp;
+  uint32_t proctl = SDHC->PROCTL & ~( SDHC_PROCTL_DTW_MASK );
+
+  switch (mode) {
+  case SDC_MODE_1BIT:
+    proctl |= SDHC_PROCTL_DTW_1BIT;
+    break;
+  case SDC_MODE_4BIT:
+    proctl |= SDHC_PROCTL_DTW_4BIT;
+    break;
+  case SDC_MODE_8BIT:
+    proctl |= SDHC_PROCTL_DTW_8BIT;
+    break;
+  default:
+    osalDbgAssert(false, "invalid bus mode");
+    break;
+  }
+
+  SDHC->PROCTL = proctl;
+}
+
+/**
+ * @brief   Sends an SDIO command with no response expected.
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ * @param[in] cmd       card command
+ * @param[in] arg       command argument
+ *
+ * @notapi
+ */
+void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg) {
+  SDHC->CMDARG = arg;
+  uint32_t xfer =
+    SDHC_XFERTYP_CMDINX(cmd) |
+    SDHC_XFERTYP_CMDTYP_NORMAL |
+    /* DPSEL=0, CICEN=0, CCCEN=0 */
+    SDHC_XFERTYP_RSPTYP_NONE;
+
+  send_and_wait_cmd(sdcp, xfer);
+}
+
+/**
+ * @brief   Sends an SDIO command with a short response expected.
+ * @note    The CRC is not verified.
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ * @param[in] cmd       card command
+ * @param[in] arg       command argument
+ * @param[out] resp     pointer to the response buffer (one word)
+ *
+ * @return              The operation status.
+ * @retval HAL_SUCCESS  operation succeeded.
+ * @retval HAL_FAILED   operation failed.
+ *
+ * @notapi
+ */
+bool sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+                            uint32_t *resp) {
+  SDHC->CMDARG = arg;
+  uint32_t xfer =
+    SDHC_XFERTYP_CMDINX(cmd) |
+    SDHC_XFERTYP_CMDTYP_NORMAL |
+    /* DPSEL=0, CICEN=0, CCCEN=0 */
+    SDHC_XFERTYP_RSPTYP_48;
+
+  bool waited = send_and_wait_cmd(sdcp, xfer);
+
+  *resp = SDHC->CMDRSP[0];
+
+  return waited;
+}
+
+/**
+ * @brief   Sends an SDIO command with a short response expected and CRC.
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ * @param[in] cmd       card command
+ * @param[in] arg       command argument
+ * @param[out] resp     pointer to the response buffer (one word)
+ *
+ * @return              The operation status.
+ * @retval HAL_SUCCESS  operation succeeded.
+ * @retval HAL_FAILED   operation failed.
+ *
+ * @notapi
+ */
+bool sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+                                uint32_t *resp) {
+  SDHC->CMDARG = arg;
+  uint32_t xfer =
+    SDHC_XFERTYP_CMDINX(cmd) |
+    SDHC_XFERTYP_CMDTYP_NORMAL |
+    /* DPSEL=0, CICEN=1, CCCEN=1 */
+    SDHC_XFERTYP_CICEN | SDHC_XFERTYP_CCCEN |
+    SDHC_XFERTYP_RSPTYP_48;
+
+  bool waited = send_and_wait_cmd(sdcp, xfer);
+
+  *resp = SDHC->CMDRSP[0];
+
+  return waited;
+}
+
+/**
+ * @brief   Sends an SDIO command with a long response expected and CRC.
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ * @param[in] cmd       card command
+ * @param[in] arg       command argument
+ * @param[out] resp     pointer to the response buffer (four words)
+ *
+ * @return              The operation status.
+ * @retval HAL_SUCCESS  operation succeeded.
+ * @retval HAL_FAILED   operation failed.
+ *
+ * @notapi
+ */
+bool sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+                               uint32_t *resp) {
+
+  /* In response format R2 (the 136-bit or "long" response) the CRC7
+     field is valid, but the command index field is set to all 1s, so
+     we need to disable the command index check function (CICEN=0). */
+  
+  SDHC->CMDARG = arg;
+  uint32_t xfer =
+    SDHC_XFERTYP_CMDINX(cmd) |
+    SDHC_XFERTYP_CMDTYP_NORMAL |
+    /* DPSEL=0, CICEN=0, CCCEN=1 */
+    SDHC_XFERTYP_CCCEN |
+    SDHC_XFERTYP_RSPTYP_136;
+
+  bool waited = send_and_wait_cmd(sdcp, xfer);
+
+  resp[0] = SDHC->CMDRSP[0];
+  resp[1] = SDHC->CMDRSP[1];
+  resp[2] = SDHC->CMDRSP[2];
+  resp[3] = SDHC->CMDRSP[3];
+
+  return waited;
+}
+
+/**
+ * @brief   Reads one or more blocks.
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ * @param[in] startblk  first block to read
+ * @param[out] buf      pointer to the read buffer
+ * @param[in] n         number of blocks to read
+ *
+ * @return              The operation status.
+ * @retval HAL_SUCCESS  operation succeeded.
+ * @retval HAL_FAILED   operation failed.
+ *
+ * @notapi
+ */
+
+bool sdc_lld_read(SDCDriver *sdcp, uint32_t startblk,
+		  uint8_t *buf, uint32_t n) {
+  uint32_t cmdx = (n == 1)?
+    SDHC_XFERTYP_CMDINX(MMCSD_CMD_READ_SINGLE_BLOCK) :
+    SDHC_XFERTYP_CMDINX(MMCSD_CMD_READ_MULTIPLE_BLOCK);
+  cmdx |= SDHC_XFERTYP_DTDSEL;
+
+  return sdc_lld_transfer(sdcp, startblk, (uintptr_t)buf, n, cmdx);
+}
+
+/**
+ * @brief   Writes one or more blocks.
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ * @param[in] startblk  first block to write
+ * @param[out] buf      pointer to the write buffer
+ * @param[in] n         number of blocks to write
+ *
+ * @return              The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED   operation failed.
+ *
+ * @notapi
+ */
+bool sdc_lld_write(SDCDriver *sdcp, uint32_t startblk,
+                   const uint8_t *buf, uint32_t n) {
+  uint32_t cmdx = (n == 1)?
+    SDHC_XFERTYP_CMDINX(MMCSD_CMD_WRITE_BLOCK) :
+    SDHC_XFERTYP_CMDINX(MMCSD_CMD_WRITE_MULTIPLE_BLOCK);
+
+  return sdc_lld_transfer(sdcp, startblk, (uintptr_t)buf, n, cmdx);
+}
+
+/**
+ * @brief   Waits for card idle condition.
+ *
+ * @param[in] sdcp      pointer to the @p SDCDriver object
+ *
+ * @return              The operation status.
+ * @retval HAL_SUCCESS  the operation succeeded.
+ * @retval HAL_FAILED   the operation failed.
+ *
+ * @api
+ */
+bool sdc_lld_sync(SDCDriver *sdcp) {
+
+  (void)sdcp;
+
+  return HAL_SUCCESS;
+}
+
+bool sdc_lld_read_special(SDCDriver *sdcp, uint8_t *buf, size_t bytes,
+			  uint8_t cmd, uint32_t argument) {
+  uintptr_t bufaddr = (uintptr_t)buf;
+
+  osalDbgCheck((bufaddr & 0x03) == 0);  /* Must be 32-bit aligned */
+  osalDbgCheck(bytes > 0);
+  osalDbgCheck(bytes < 4096);
+
+  osalDbgAssert((SDHC->PRSSTAT & (SDHC_PRSSTAT_DLA|SDHC_PRSSTAT_CDIHB|SDHC_PRSSTAT_CIHB)) == 0,
+		"SDHC interface not ready");
+
+  TRACE(5, argument);
+
+  /* Store the cmd argument and DMA start address */
+  SDHC->CMDARG = argument;
+  SDHC->DSADDR = bufaddr;
+
+  /* We're reading one block, of a (possibly) nonstandard size */
+  SDHC->BLKATTR = SDHC_BLKATTR_BLKSIZE(bytes);
+
+  uint32_t xfer =
+    SDHC_XFERTYP_CMDINX(cmd) |    /* the command */
+    SDHC_XFERTYP_DTDSEL |         /* read transfer (card -> host) */
+    SDHC_XFERTYP_CMDTYP_NORMAL |
+    SDHC_XFERTYP_CICEN | SDHC_XFERTYP_CCCEN |
+    SDHC_XFERTYP_RSPTYP_48 |
+    SDHC_XFERTYP_DPSEL | SDHC_XFERTYP_DMAEN;  /* DMA-assisted data transfer */
+
+  return send_and_wait_transfer(sdcp, xfer);
+}
+
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+  (void)sdcp;
+
+  return ( SDHC->PRSSTAT & SDHC_PRSSTAT_CLSL )? true : false;
+}
+
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+  (void)sdcp;
+  return false;
+}
+
+#endif /* HAL_USE_SDC == TRUE */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/LLD/hal_sdc_lld.h b/os/hal/ports/KINETIS/LLD/hal_sdc_lld.h
new file mode 100644
index 0000000..9f77bf6
--- /dev/null
+++ b/os/hal/ports/KINETIS/LLD/hal_sdc_lld.h
@@ -0,0 +1,202 @@
+/*
+    ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+              Copyright (C) 2017 Wim Lewis
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    hal_sdc_lld.h
+ * @brief   PLATFORM SDC subsystem low level driver header.
+ *
+ * @addtogroup SDC
+ * @{
+ */
+
+#ifndef HAL_SDC_LLD_H
+#define HAL_SDC_LLD_H
+
+#if (HAL_USE_SDC == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+#define SDHC_XFERTYP_CMDTYP_NORMAL	SDHC_XFERTYP_CMDTYP(0)
+#define SDHC_XFERTYP_CMDTYP_SUSPEND	SDHC_XFERTYP_CMDTYP(1)
+#define SDHC_XFERTYP_CMDTYP_RESUME	SDHC_XFERTYP_CMDTYP(2)
+#define SDHC_XFERTYP_CMDTYP_ABORT	SDHC_XFERTYP_CMDTYP(3)
+
+#define SDHC_XFERTYP_RSPTYP_NONE	SDHC_XFERTYP_RSPTYP(0)  /* no response */
+#define SDHC_XFERTYP_RSPTYP_136		SDHC_XFERTYP_RSPTYP(1)	/* 136-bit response */
+#define SDHC_XFERTYP_RSPTYP_48		SDHC_XFERTYP_RSPTYP(2)	/* 48-bit response */
+#define SDHC_XFERTYP_RSPTYP_48b		SDHC_XFERTYP_RSPTYP(3)	/* 48-bit plus busy */
+
+#define SDHC_PROCTL_DTW_1BIT            SDHC_PROCTL_DTW(0)
+#define SDHC_PROCTL_DTW_4BIT            SDHC_PROCTL_DTW(1)
+#define SDHC_PROCTL_DTW_8BIT            SDHC_PROCTL_DTW(2)
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    PLATFORM configuration options
+ * @{
+ */
+/**
+ * @brief   SDC1 driver enable switch.
+ * @details If set to @p TRUE the support for SDC1 is included.
+ * @note    The default is @p TRUE if HAL_USE_SDC is set.
+ */
+#if !defined(PLATFORM_SDC_USE_SDC1) || defined(__DOXYGEN__)
+#define PLATFORM_SDC_USE_SDC1                  TRUE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type of card flags.
+ */
+typedef uint32_t sdcmode_t;
+
+/**
+ * @brief   SDC Driver condition flags type.
+ */
+typedef uint32_t sdcflags_t;
+
+/**
+ * @brief   Type of a structure representing an SDC driver.
+ */
+typedef struct SDCDriver SDCDriver;
+
+/**
+ * @brief   Driver configuration structure.
+ * @note    It could be empty on some architectures.
+ */
+typedef struct {
+  /**
+   * @brief   Working area for memory consuming operations.
+   * @note    It is mandatory for detecting MMC cards bigger than 2GB else it
+   *          can be @p NULL.
+   * @note    Memory pointed by this buffer is only used by @p sdcConnect(),
+   *          afterward it can be reused for other purposes.
+   */
+  uint8_t       *scratchpad;
+  /**
+   * @brief   Bus width.
+   */
+  sdcbusmode_t  bus_width;
+  /* End of the mandatory fields.*/
+} SDCConfig;
+
+/**
+ * @brief   @p SDCDriver specific methods.
+ */
+#define _sdc_driver_methods                                                 \
+  _mmcsd_block_device_methods
+
+/**
+ * @extends MMCSDBlockDeviceVMT
+ *
+ * @brief   @p SDCDriver virtual methods table.
+ */
+struct SDCDriverVMT {
+  _sdc_driver_methods
+};
+
+/**
+ * @brief   Structure representing an SDC driver.
+ */
+struct SDCDriver {
+  /**
+   * @brief Virtual Methods Table.
+   */
+  const struct SDCDriverVMT *vmt;
+  _mmcsd_block_device_data
+  /**
+   * @brief Current configuration data.
+   */
+  const SDCConfig           *config;
+  /**
+   * @brief Various flags regarding the mounted card.
+   */
+  sdcmode_t                 cardmode;
+  /**
+   * @brief Errors flags.
+   */
+  sdcflags_t                errors;
+  /**
+   * @brief Card RCA.
+   */
+  uint32_t                  rca;
+  /* End of the mandatory fields.*/
+
+  /* Platform specific fields */
+  thread_reference_t        thread;
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if (PLATFORM_SDC_USE_SDC1 == TRUE) && !defined(__DOXYGEN__)
+extern SDCDriver SDCD1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void sdc_lld_init(void);
+  void sdc_lld_start(SDCDriver *sdcp);
+  void sdc_lld_stop(SDCDriver *sdcp);
+  void sdc_lld_start_clk(SDCDriver *sdcp);
+  void sdc_lld_set_data_clk(SDCDriver *sdcp, sdcbusclk_t clk);
+  void sdc_lld_stop_clk(SDCDriver *sdcp);
+  void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode);
+  void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg);
+  bool sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+                              uint32_t *resp);
+  bool sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+                                  uint32_t *resp);
+  bool sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+                                 uint32_t *resp);
+  bool sdc_lld_read_special(SDCDriver *sdcp, uint8_t *buf, size_t bytes,
+                            uint8_t cmd, uint32_t argument);
+  bool sdc_lld_read(SDCDriver *sdcp, uint32_t startblk,
+                    uint8_t *buf, uint32_t n);
+  bool sdc_lld_write(SDCDriver *sdcp, uint32_t startblk,
+                     const uint8_t *buf, uint32_t n);
+  bool sdc_lld_sync(SDCDriver *sdcp);
+  bool sdc_lld_is_card_inserted(SDCDriver *sdcp);
+  bool sdc_lld_is_write_protected(SDCDriver *sdcp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_SDC == TRUE */
+
+#endif /* HAL_SDC_LLD_H */
+
+/** @} */
-- 
cgit v1.2.3


From 48d924c24becc69f0c88011ab76fb12b22384d21 Mon Sep 17 00:00:00 2001
From: Wim Lewis <wiml@hhhh.org>
Date: Thu, 18 Jan 2018 01:27:22 -0800
Subject: Improved error handling: check the card's state before trying to
 abort a failed data transfer; translate card status bits into HLD error bits.
 Set BLKATTR_BLKCNT even when it's not being used, which seems to avoid errors
 when alternating between multi-block and single-block transfers. Some
 comments.

---
 os/hal/ports/KINETIS/LLD/hal_sdc_lld.c | 98 ++++++++++++++++++++++++++++++----
 1 file changed, 88 insertions(+), 10 deletions(-)

(limited to 'os')

diff --git a/os/hal/ports/KINETIS/LLD/hal_sdc_lld.c b/os/hal/ports/KINETIS/LLD/hal_sdc_lld.c
index 30d8f99..7ddeb6c 100644
--- a/os/hal/ports/KINETIS/LLD/hal_sdc_lld.c
+++ b/os/hal/ports/KINETIS/LLD/hal_sdc_lld.c
@@ -19,6 +19,18 @@
  * @file    hal_sdc_lld.c
  * @brief   Kinetis SDC subsystem low level driver.
  *
+ * This driver provides a single SDC driver based on the Kinetis
+ * "Secured Digital Host Controller (SDHC)" peripheral.
+ *
+ * In order to use this driver, other peripherals must also be configured:
+ *
+ * The MPU must either be disabled (CESR=0), or it must be configured
+ * to allow the SDHC peripheral DMA access to any data buffers (read
+ * or write).
+ *
+ * The SDHC signals must be routed to the desired pins, and pullups/pulldowns
+ * configured.
+ *
  * @addtogroup SDC
  * @{
  */
@@ -56,11 +68,34 @@
 #define DTOCV_700ms_25MHz    11  /* 11 -> 2^24 -> 671 msec */
 #define DTOCV_700ms_50MHz    12  /* 12 -> 2^25 -> 671 msec */
 
+#if 0
 #define TRACE(t, val)   chDbgWriteTrace ((void *)t, (void *)(uintptr_t)(val))
 #define TRACEI(t, val)  chDbgWriteTraceI((void *)t, (void *)(uintptr_t)(val))
+#else
+#define TRACE(t, val)
+#define TRACEI(t, val)
+#endif
 
 #define DIV_RND_UP(a, b) ( ((a)+(b)-1) / (b) )
 
+/* Error bits from the SD / MMC Card Status response word. */
+/* TODO: These really belong in a HLD, not here. */
+#define MMC_ERR_OUT_OF_RANGE            (1U << 31)
+#define MMC_ERR_ADDRESS                 (1U << 30)
+#define MMC_ERR_BLOCK_LEN               (1U << 29)
+#define MMC_ERR_ERASE_SEQ               (1U << 28)
+#define MMC_ERR_ERASE_PARAM             (1U << 27)
+#define MMC_ERR_WP                      (1U << 26)
+#define MMC_ERR_CARD_IS_LOCKED          (1U << 25)
+#define MMC_ERR_LOCK_UNLOCK_FAILED      (1U << 24)
+#define MMC_ERR_COM_CRC_ERROR           (1U << 23)
+#define MMC_ERR_ILLEGAL_COMMAND         (1U << 22)
+#define MMC_ERR_CARD_ECC_FAILED         (1U << 21)
+#define MMC_ERR_CARD_CONTROLLER         (1U << 20)
+#define MMC_ERR_ERROR                   (1U << 19)
+#define MMC_ERR_CSD_OVERWRITE           (1U << 16)
+#define MMC_ERR_AKE_SEQ                 (1U << 3)
+
 /*===========================================================================*/
 /* Driver exported variables.                                                */
 /*===========================================================================*/
@@ -96,7 +131,7 @@ static bool sdc_lld_transfer(SDCDriver *, uint32_t, uintptr_t, uint32_t, uint32_
  * you're compiling with optimizations turned off.
  *
  * However if someone compiles with a KINETIS_SDHC_PERIPHERAL_FREQUENCY
- * that is not a compile-tie constant, this function would get emitted.
+ * that is not a compile-time constant, this function would get emitted.
  */
 static uint32_t divisor_settings(unsigned divisor)
 {
@@ -184,6 +219,26 @@ static sdcflags_t translate_cmd_error(uint32_t status) {
   return errors;
 }
 
+static sdcflags_t translate_mmcsd_error(uint32_t cardstatus) {
+  sdcflags_t errors = 0;
+
+  cardstatus &= MMCSD_R1_ERROR_MASK;
+
+  if (cardstatus & MMC_ERR_COM_CRC_ERROR)
+    errors |= SDC_CMD_CRC_ERROR;
+
+  if (cardstatus & MMC_ERR_CARD_ECC_FAILED)
+    errors |= SDC_DATA_CRC_ERROR;
+
+  /* TODO: Extend the HLD error codes at least enough to distinguish
+     between invalid command/parameter errors (card is OK, but
+     retrying w/o change won't help) and other errors */
+  if (cardstatus & ~(MMC_ERR_COM_CRC_ERROR|MMC_ERR_CARD_ECC_FAILED))
+    errors |= SDC_UNHANDLED_ERROR;
+
+  return errors;
+}
+
 /**
  * @brief Perform one CMD transaction on the SD bus.
  */
@@ -194,6 +249,8 @@ static bool send_and_wait_cmd(SDCDriver *sdcp, uint32_t cmd) {
   osalDbgAssert((SDHC->PRSSTAT & (SDHC_PRSSTAT_SDSTB|SDHC_PRSSTAT_CIHB)) == SDHC_PRSSTAT_SDSTB, "Not in expected state");
   osalDbgAssert(SDHC->SYSCTL & SDHC_SYSCTL_SDCLKEN, "Clock disabled");
   osalDbgCheck((cmd & SDHC_XFERTYP_DPSEL) == 0);
+  osalDbgCheck((SDHC->IRQSTAT & (SDHC_IRQSTAT_CIE | SDHC_IRQSTAT_CEBE | SDHC_IRQSTAT_CCE |
+                                 SDHC_IRQSTAT_CTOE | SDHC_IRQSTAT_CC)) == 0);
 
   /* This initiates the CMD transaction */
   TRACE(1, cmd);
@@ -305,8 +362,7 @@ static bool send_and_wait_transfer(SDCDriver *sdcp, uint32_t cmd) {
   uint32_t cmdresp = SDHC->CMDRSP[0];
   if (cmdresp & MMCSD_R1_ERROR_MASK) {
     /* The command was sent, and the card responded with an error indication */
-    /* TODO: See which errors can be translated into HAL errors? */
-    sdcp->errors |= SDC_UNHANDLED_ERROR;
+    sdcp->errors |= translate_mmcsd_error(cmdresp);
     return HAL_FAILED;
   }
 
@@ -358,8 +414,9 @@ static bool send_and_wait_transfer(SDCDriver *sdcp, uint32_t cmd) {
       }
     }
 
-    if (should_cancel)
+    if (should_cancel) {
       recover_after_botched_transfer(sdcp);
+    }
 
     return HAL_FAILED;
   }
@@ -402,8 +459,25 @@ static msg_t wait_interrupt(SDCDriver *sdcp, uint32_t mask) {
 
 static void recover_after_botched_transfer(SDCDriver *sdcp) {
 
-  /* Send a CMD12 to make sure the card isn't still transferring anything */
-  send_and_wait_cmd(sdcp, MMCSD_CMD_STOP_TRANSMISSION);
+  /* Query the card state */
+  uint32_t cardstatus;
+  if (sdc_lld_send_cmd_short_crc(sdcp,
+                                 MMCSD_CMD_SEND_STATUS,
+                                 sdcp->rca, &cardstatus) == HAL_SUCCESS) {
+    sdcp->errors |= translate_mmcsd_error(cardstatus);
+    uint32_t state = MMCSD_R1_STS(cardstatus);
+    if (state == MMCSD_STS_DATA) {
+
+      /* Send a CMD12 to make sure the card isn't still transferring anything */
+      SDHC->CMDARG = 0;
+      send_and_wait_cmd(sdcp,
+                        SDHC_XFERTYP_CMDINX(MMCSD_CMD_STOP_TRANSMISSION) |
+                        SDHC_XFERTYP_CMDTYP_ABORT |
+                        /* TODO: Should we set CICEN and CCCEN here? */
+                        SDHC_XFERTYP_CICEN | SDHC_XFERTYP_CCCEN |
+                        SDHC_XFERTYP_RSPTYP_48b);
+    }
+  }
 
   /* And reset the data block of the SDHC peripheral */
   SDHC->SYSCTL |= SDHC_SYSCTL_RSTD;
@@ -446,9 +520,16 @@ static bool sdc_lld_transfer(SDCDriver *sdcp, uint32_t startblk,
      DTDSEL -> 1 for a read (card-to-host) transfer
      MSBSEL, BCEN -> multiple block transfer using BLKATTR_BLKCNT
      AC12EN -> Automatically issue MMCSD_CMD_STOP_TRANSMISSION at end of transfer
+
+     Setting BLKCOUNT to 1 seems to be necessary even if MSBSEL+BCEN
+     is not set, despite the datasheet suggesting otherwise. I'm not
+     sure if this is a silicon bug or if I'm misunderstanding the
+     datasheet.
   */
+  SDHC->BLKATTR =
+    SDHC_BLKATTR_BLKCNT(n) |
+    SDHC_BLKATTR_BLKSIZE(MMCSD_BLOCK_SIZE);
   if (n == 1) {
-    SDHC->BLKATTR = SDHC_BLKATTR_BLKSIZE(MMCSD_BLOCK_SIZE);
     xfer =
       cmdx |
       SDHC_XFERTYP_CMDTYP_NORMAL |
@@ -456,9 +537,6 @@ static bool sdc_lld_transfer(SDCDriver *sdcp, uint32_t startblk,
       SDHC_XFERTYP_RSPTYP_48b |
       SDHC_XFERTYP_DPSEL | SDHC_XFERTYP_DMAEN;
   } else {
-    SDHC->BLKATTR =
-      SDHC_BLKATTR_BLKCNT(n) |
-      SDHC_BLKATTR_BLKSIZE(MMCSD_BLOCK_SIZE);
     xfer =
       cmdx |
       SDHC_XFERTYP_CMDTYP_NORMAL |
-- 
cgit v1.2.3


From 7e51a3bcfac5bf8b0642e3fae7633e353fbf386d Mon Sep 17 00:00:00 2001
From: Wim Lewis <wiml@hhhh.org>
Date: Thu, 18 Jan 2018 18:23:07 -0800
Subject: Use an interrupt instead of polling for simple commands. Updated some
 comments and some trace statements.

---
 os/hal/ports/KINETIS/LLD/hal_sdc_lld.c | 36 ++++++++++++++--------------------
 1 file changed, 15 insertions(+), 21 deletions(-)

(limited to 'os')

diff --git a/os/hal/ports/KINETIS/LLD/hal_sdc_lld.c b/os/hal/ports/KINETIS/LLD/hal_sdc_lld.c
index 7ddeb6c..1b19a90 100644
--- a/os/hal/ports/KINETIS/LLD/hal_sdc_lld.c
+++ b/os/hal/ports/KINETIS/LLD/hal_sdc_lld.c
@@ -1,6 +1,6 @@
 /*
     ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
-              Copyright (C) 2017 Wim Lewis
+              Copyright (C) 2017..2018 Wim Lewis
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -219,6 +219,12 @@ static sdcflags_t translate_cmd_error(uint32_t status) {
   return errors;
 }
 
+/**
+ * Translate error bits from a card's R1 response word into the HAL's
+ * error flag set.
+ *
+ * This function should probably be in the HLD, not here.
+ */
 static sdcflags_t translate_mmcsd_error(uint32_t cardstatus) {
   sdcflags_t errors = 0;
 
@@ -256,29 +262,11 @@ static bool send_and_wait_cmd(SDCDriver *sdcp, uint32_t cmd) {
   TRACE(1, cmd);
   SDHC->XFERTYP = cmd;
 
-  /* TODO: Wait on the completion interrupt instead of spin-polling. Are we in a sys-locked state at this point or not? */
-
-  int spincount = 0;
-  uint32_t status;
   uint32_t events =
     SDHC_IRQSTAT_CIE | SDHC_IRQSTAT_CEBE | SDHC_IRQSTAT_CCE |
     SDHC_IRQSTAT_CTOE | /* SDHC_IRQSTAT_CRM | */ SDHC_IRQSTAT_CC;
-  for(;;) {
-    status = SDHC->IRQSTAT & events;
-    if (status & (SDHC_IRQSTAT_CTOE | SDHC_IRQSTAT_CC))
-      break;
-    osalThreadSleepMilliseconds(1);
-    spincount ++;
-    if (spincount > 1000) {
-      /* Shouldn't happen: the SDHC controller has its own timeout
-	 mechanism and should eventually set CTOE, unless we've done
-	 something like accidentally gate off the clock to the SDHC
-	 module */
-      break;
-    }
-  }
-
-  TRACE(2, status);
+  wait_interrupt(sdcp, SDHC_IRQSTAT_CTOE | SDHC_IRQSTAT_CC);
+  uint32_t status = SDHC->IRQSTAT & events;
 
   /* These bits are write-1-to-clear (w1c) */
   SDHC->IRQSTAT = status;
@@ -291,6 +279,8 @@ static bool send_and_wait_cmd(SDCDriver *sdcp, uint32_t cmd) {
   /* Translate the failure into the flags understood by the top half */
   sdcp->errors |= translate_cmd_error(status);
 
+  TRACE(9, SDHC->PRSSTAT);
+
   /* Issue a reset to the CMD portion of the SDHC peripheral to clear the
      error bits and enable subsequent commands */
   SDHC->SYSCTL |= SDHC_SYSCTL_RSTC;
@@ -360,6 +350,7 @@ static bool send_and_wait_transfer(SDCDriver *sdcp, uint32_t cmd) {
   }
 
   uint32_t cmdresp = SDHC->CMDRSP[0];
+  TRACE(11, cmdresp);
   if (cmdresp & MMCSD_R1_ERROR_MASK) {
     /* The command was sent, and the card responded with an error indication */
     sdcp->errors |= translate_mmcsd_error(cmdresp);
@@ -670,6 +661,8 @@ void sdc_lld_start_clk(SDCDriver *sdcp) {
      insertion or power-on, but the abridged SDHC specifications I
      have don't seem to mention it) */
   SDHC->SYSCTL |= SDHC_SYSCTL_INITA;
+
+  TRACE(9, SDHC->PRSSTAT);
 }
 
 /**
@@ -827,6 +820,7 @@ bool sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
   bool waited = send_and_wait_cmd(sdcp, xfer);
 
   *resp = SDHC->CMDRSP[0];
+  TRACE(11, *resp);
 
   return waited;
 }
-- 
cgit v1.2.3


From 90b7d6bbd03deead3d6bd6c8e334d6dfdd195feb Mon Sep 17 00:00:00 2001
From: Adrian <af@coda.pw>
Date: Wed, 31 Jan 2018 09:55:38 +0100
Subject: Added support for STM32F7

Tested only for STM32F746, other chipsets have to be checked.
---
 os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c       | 5 ++++-
 os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h       | 5 ++++-
 os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c | 5 ++++-
 os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h | 5 ++++-
 os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c  | 5 ++++-
 5 files changed, 20 insertions(+), 5 deletions(-)

(limited to 'os')

diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c
index b4c2938..500b2e7 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c
+++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c
@@ -97,7 +97,10 @@ void fsmc_init(void) {
 
 #if (defined(STM32F427xx) || defined(STM32F437xx) || \
      defined(STM32F429xx) || defined(STM32F439xx) || \
-     defined(STM32F7))
+     defined(STM32F745xx) || defined(STM32F746xx) || \
+     defined(STM32F756xx) || defined(STM32F767xx) || \
+     defined(STM32F769xx) || defined(STM32F777xx) || \
+     defined(STM32F779xx))
   #if STM32_USE_FSMC_SDRAM
     FSMCD1.sdram = (FSMC_SDRAM_TypeDef *)FSMC_Bank5_6_R_BASE;
   #endif
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h
index 2bc267f..80c5d26 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h
+++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h
@@ -36,7 +36,10 @@
  */
 #if (defined(STM32F427xx) || defined(STM32F437xx) || \
      defined(STM32F429xx) || defined(STM32F439xx) || \
-     defined(STM32F769xx))
+     defined(STM32F745xx) || defined(STM32F746xx) || \
+     defined(STM32F756xx) || defined(STM32F767xx) || \
+     defined(STM32F769xx) || defined(STM32F777xx) || \
+     defined(STM32F779xx))
   #if !defined(FSMC_Bank1_R_BASE)
   #define FSMC_Bank1_R_BASE               (FMC_R_BASE + 0x0000)
   #endif
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c
index ea1be4c..6d727c8 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c
+++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c
@@ -29,7 +29,10 @@
 
 #if (defined(STM32F427xx) || defined(STM32F437xx) || \
      defined(STM32F429xx) || defined(STM32F439xx) || \
-     defined(STM32F769xx))
+     defined(STM32F745xx) || defined(STM32F746xx) || \
+     defined(STM32F756xx) || defined(STM32F767xx) || \
+     defined(STM32F769xx) || defined(STM32F777xx) || \
+     defined(STM32F779xx))
 
 #if (STM32_USE_FSMC_SDRAM == TRUE) || defined(__DOXYGEN__)
 
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h
index fdf3268..c9f9de0 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h
+++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h
@@ -30,7 +30,10 @@
 
 #if (defined(STM32F427xx) || defined(STM32F437xx) || \
      defined(STM32F429xx) || defined(STM32F439xx) || \
-     defined(STM32F769xx))
+     defined(STM32F745xx) || defined(STM32F746xx) || \
+     defined(STM32F756xx) || defined(STM32F767xx) || \
+     defined(STM32F769xx) || defined(STM32F777xx) || \
+     defined(STM32F779xx))
 
 #include "hal_fsmc.h"
 
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c
index fbd6f56..da13ca5 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c
+++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c
@@ -148,7 +148,10 @@ void fsmcSramStop(SRAMDriver *sramp) {
     uint32_t mask = FSMC_BCR_MBKEN;
 #if (defined(STM32F427xx) || defined(STM32F437xx) || \
      defined(STM32F429xx) || defined(STM32F439xx) || \
-     defined(STM32F7))
+     defined(STM32F745xx) || defined(STM32F746xx) || \
+     defined(STM32F756xx) || defined(STM32F767xx) || \
+     defined(STM32F769xx) || defined(STM32F777xx) || \
+     defined(STM32F779xx))
     mask |= FSMC_BCR_CCLKEN;
 #endif
     sramp->sram->BCR &= ~mask;
-- 
cgit v1.2.3


From 432bc1762f17eb7b506e8fbca8ec30a3d61629b8 Mon Sep 17 00:00:00 2001
From: Fred Sundvik <fsundvik@gmail.com>
Date: Sat, 3 Feb 2018 12:41:23 +0200
Subject: Add usb_lld_wakeup_host for Kinetis

---
 os/hal/ports/KINETIS/LLD/hal_usb_lld.h | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

(limited to 'os')

diff --git a/os/hal/ports/KINETIS/LLD/hal_usb_lld.h b/os/hal/ports/KINETIS/LLD/hal_usb_lld.h
index 961490e..bd4eb39 100644
--- a/os/hal/ports/KINETIS/LLD/hal_usb_lld.h
+++ b/os/hal/ports/KINETIS/LLD/hal_usb_lld.h
@@ -76,6 +76,13 @@
   #define KINETIS_USB_ENDPOINTS USB_MAX_ENDPOINTS+1
 #endif
 
+/**
+ * @brief   Host wake-up procedure duration.
+ */
+#if !defined(USB_HOST_WAKEUP_DURATION) || defined(__DOXYGEN__)
+#define USB_HOST_WAKEUP_DURATION            2
+#endif
+
 /*===========================================================================*/
 /* Derived constants and error checks.                                       */
 /*===========================================================================*/
@@ -97,6 +104,10 @@
 #error "KINETIS_USB_IRQ_VECTOR not defined"
 #endif
 
+#if (USB_HOST_WAKEUP_DURATION < 2) || (USB_HOST_WAKEUP_DURATION > 15)
+#error "invalid USB_HOST_WAKEUP_DURATION setting, it must be between 2 and 15"
+#endif
+
 /*===========================================================================*/
 /* Driver data structures and types.                                         */
 /*===========================================================================*/
@@ -394,6 +405,18 @@ struct USBDriver {
 #endif /* KINETIS_USB0_IS_USBOTG */
 #endif
 
+/**
+ * @brief   Start of host wake-up procedure.
+ *
+ * @notapi
+ */
+#define usb_lld_wakeup_host(usbp)                                     \
+  do{                                                                 \
+    USB0->CTL |= USBx_CTL_RESUME;                                     \
+    osalThreadSleepMilliseconds(USB_HOST_WAKEUP_DURATION);            \
+    USB0->CTL &= ~USBx_CTL_RESUME;                                    \
+  } while (false)
+
 /*===========================================================================*/
 /* External declarations.                                                    */
 /*===========================================================================*/
-- 
cgit v1.2.3


From 1178cf761cf3fd4b5dcbc30bb5a9b37190f1c7b1 Mon Sep 17 00:00:00 2001
From: Fred Sundvik <fsundvik@gmail.com>
Date: Thu, 8 Feb 2018 08:34:14 +0200
Subject: Fix typo in k20xx.h

---
 os/common/ext/CMSIS/KINETIS/k20xx.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'os')

diff --git a/os/common/ext/CMSIS/KINETIS/k20xx.h b/os/common/ext/CMSIS/KINETIS/k20xx.h
index 38855aa..8218b3c 100644
--- a/os/common/ext/CMSIS/KINETIS/k20xx.h
+++ b/os/common/ext/CMSIS/KINETIS/k20xx.h
@@ -2242,7 +2242,7 @@ typedef struct
 /******** Bits definition for USBx_CTL register *****************/
 #define USBx_CTL_JSTATE              ((uint8_t)0x80) /*!< Live USB differential receiver JSTATE signal */
 #define USBx_CTL_SE0                 ((uint8_t)0x40) /*!< Live USB single ended zero signal */
-#define USBx_CTL_TXSUSPENDTOKENBUS   ((uint8_t)0x20) /*!<  */
+#define USBx_CTL_TXSUSPENDTOKENBUSY  ((uint8_t)0x20) /*!<  */
 #define USBx_CTL_RESET               ((uint8_t)0x10) /*!< Generates an USB reset signal (host mode) */
 #define USBx_CTL_HOSTMODEEN          ((uint8_t)0x08) /*!< Operate in Host mode */
 #define USBx_CTL_RESUME              ((uint8_t)0x04) /*!< Executes resume signaling */
-- 
cgit v1.2.3


From b7f761313c11d94b89b605f81a89ced34a57c603 Mon Sep 17 00:00:00 2001
From: Fred Sundvik <fsundvik@gmail.com>
Date: Thu, 8 Feb 2018 08:34:51 +0200
Subject: Fix data usb data toggle sync problem

USB control transfers are structured as the following.
For incoming transfers
Setup (Data0 out)
Data (Data1/Data0 in) - starting with data 1
Status (Data1 out)

For outgoing transfers
Setup (Data0 out)
Data (Data1/Data0 out) - starting with data 1
Status (Data1 in)

The in buffers (device to host) are always correctly synchronized, since
they can always be reset to Data1 each setup packet without any
synchronization problems.

The problem occured for outgoing transfers (host to device). For
incoming transfers the data banks always alternates, and will
automatically stay in sync. Outgoing transfers also stays in sync when
there's an odd number of data packets. However when the number is even,
including zero, then the last packet received by the device will be
data0 and the next setup packet also has to be data0, so there's a
synchronization problem.

This itself is not a problem since data toggle synchronization(DTS) is
ignored for setup packets, however if the follwoing packet after that
is also an out packet, then the data bank will be wrong and the packet
dropped. In this case the USB spec don't allow sending a nack, so it
will only recover after a timeout, when the host tries to send a new
setup packet.

The old code tried to take care of this situation by reinitializing
both data banks when a setup packet is received. The problem is that the
next packet might already have been received or is in progress of being
received at this point, so the fixup comes to late. The new code does
the fixup when a status packet is about to be sent from the device to
avoid this problem.
---
 os/hal/ports/KINETIS/LLD/hal_usb_lld.c | 57 ++++++++++++++++++++++++----------
 1 file changed, 41 insertions(+), 16 deletions(-)

(limited to 'os')

diff --git a/os/hal/ports/KINETIS/LLD/hal_usb_lld.c b/os/hal/ports/KINETIS/LLD/hal_usb_lld.c
index e8d9778..ba91d24 100644
--- a/os/hal/ports/KINETIS/LLD/hal_usb_lld.c
+++ b/os/hal/ports/KINETIS/LLD/hal_usb_lld.c
@@ -158,7 +158,7 @@ void usb_packet_transmit(USBDriver *usbp, usbep_t ep, size_t n)
   USBInEndpointState *isp = epc->in_state;
 
   bd_t *bd = (bd_t *)&_bdt[BDT_INDEX(ep, TX, isp->odd_even)];
-  
+
   if (n > (size_t)epc->in_maxsize)
     n = (size_t)epc->in_maxsize;
 
@@ -244,19 +244,16 @@ OSAL_IRQ_HANDLER(KINETIS_USB_IRQ_VECTOR) {
     {
       case BDT_PID_SETUP:                                              // SETUP
       {
-        /* Clear any pending IN stuff */
-        _bdt[BDT_INDEX(ep, TX, EVEN)].desc = 0;
-        _bdt[BDT_INDEX(ep, TX,  ODD)].desc = 0;
-        /* Also in the chibios state machine */
+        /* Clear receiving in the chibios state machine */
         (usbp)->receiving &= ~1;
-        /* After a SETUP, IN is always DATA1 */
-        usbp->epc[ep]->in_state->data_bank = DATA1;
-
-        /* Call SETUP function (ChibiOS core), which sends back stuff */
+        /* Call SETUP function (ChibiOS core), which prepares
+         * for send or receive and releases the buffer
+         */
         _usb_isr_invoke_setup_cb(usbp, ep);
-        /* Buffer is released by the above callback. */
-        /* from Paul: "unfreeze the USB, now that we're ready" */
-        USB0->CTL = USBx_CTL_USBENSOFEN;
+        /* When a setup packet is received, tx is suspended,
+         * so it needs to be resumed here.
+         */
+        USB0->CTL &= ~USBx_CTL_TXSUSPENDTOKENBUSY;
       } break;
       case BDT_PID_IN:                                                 // IN
       {
@@ -728,9 +725,23 @@ void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) {
   }
   /* Release the buffer
    * Setup packet is always DATA0
-   * Initialize buffers so current expects DATA0 & opposite DATA1 */
+   * Release the current DATA0 buffer
+   */
   bd->desc = BDT_DESC(usbp->epc[ep]->out_maxsize,DATA0);
-  _bdt[BDT_INDEX(ep, RX, os->odd_even^ODD)].desc = BDT_DESC(usbp->epc[ep]->out_maxsize,DATA1);
+  /* If DATA1 was expected, then the states are out of sync.
+   * So reset the other buffer too, and set it as DATA1.
+   * This should not happen in normal cases, but is possible in
+   * error situations. NOTE: it's possible that this is too late
+   * and the next packet has already been received and dropped, but
+   * there's nothing that we can do about that anymore at this point.
+   */
+  if (os->data_bank == DATA1)
+  {
+    bd_t *bd_next = (bd_t*)&_bdt[BDT_INDEX(ep, RX, os->odd_even^ODD)];
+    bd_next->desc = BDT_DESC(usbp->epc[ep]->out_maxsize,DATA1);
+  }
+  /* After a SETUP, both in and out are always DATA1 */
+  usbp->epc[ep]->in_state->data_bank = DATA1;
   os->data_bank = DATA1;
 }
 
@@ -762,8 +773,22 @@ void usb_lld_start_out(USBDriver *usbp, usbep_t ep) {
  * @notapi
  */
 void usb_lld_start_in(USBDriver *usbp, usbep_t ep) {
-  (void)usbp;
-  (void)ep;
+  if (ep == 0 && usbp->ep0state == USB_EP0_IN_SENDING_STS) {
+    /* When a status packet is about to be sent on endpoint 0 the
+     * next packet will be a setup packet, which means that the
+     * buffer we expect after this should be DATA0, and the following
+     * DATA1. Since no out packets should be in flight at this time
+     * it's safe to initialize the buffers according to the expectations
+     * here.
+     */
+    const USBEndpointConfig* epc = usbp->epc[ep];
+    bd_t * bd = (bd_t*)&_bdt[BDT_INDEX(ep, RX, epc->out_state->odd_even)];
+    bd_t *bd_next = (bd_t*)&_bdt[BDT_INDEX(ep, RX, epc->out_state->odd_even^ODD)];
+
+    bd->desc = BDT_DESC(usbp->epc[ep]->out_maxsize,DATA1);
+    bd_next->desc = BDT_DESC(usbp->epc[ep]->out_maxsize,DATA0);
+    epc->out_state->data_bank = DATA0;
+  }
   usb_packet_transmit(usbp,ep,usbp->epc[ep]->in_state->txsize);
 }
 
-- 
cgit v1.2.3


From 6b277eb3db9dbdc9a610dd04697b22a0f27120cc Mon Sep 17 00:00:00 2001
From: marcoveeneman <marco-veeneman@hotmail.com>
Date: Tue, 27 Feb 2018 20:59:58 +0100
Subject: Fixed startup makefiles

vectors.c was replaced by vectors.S
---
 os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk | 9 +++++----
 os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk | 9 +++++----
 2 files changed, 10 insertions(+), 8 deletions(-)

(limited to 'os')

diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk
index 6464c5e..e87e60d 100644
--- a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk
+++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk
@@ -1,10 +1,11 @@
 # List of the ChibiOS generic TM4C123x startup and CMSIS files.
-STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
-             $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.c
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c
 
-STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S \
+             $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
 
-STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
+STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
+             $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
              $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/TM4C123x \
              $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
              $(CHIBIOS_CONTRIB)/os/common/ext/TivaWare
diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk
index 5cc9a1f..c8c5f82 100644
--- a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk
+++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk
@@ -1,10 +1,11 @@
 # List of the ChibiOS generic TM4C129x startup and CMSIS files.
-STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
-             $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.c
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c
 
-STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S \
+             $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S
 
-STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
+STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
+             $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
              $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/TM4C129x \
              $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
              $(CHIBIOS_CONTRIB)/os/common/ext/TivaWare
-- 
cgit v1.2.3


From cae865f0b9cab08d3613c81e2db1f760de0ee5f8 Mon Sep 17 00:00:00 2001
From: marcoveeneman <marco-veeneman@hotmail.com>
Date: Wed, 28 Feb 2018 18:28:02 +0100
Subject: Changed PAL driver so that TM4C123x devices GPIO blocks always use
 AHB.

---
 os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c |  86 ++------------------
 os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h | 130 -------------------------------
 2 files changed, 6 insertions(+), 210 deletions(-)

(limited to 'os')

diff --git a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c
index 41fb3cd..0be8d6d 100644
--- a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c
+++ b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c
@@ -32,196 +32,122 @@
 
 #if TIVA_HAS_GPIOA || defined(__DOXYGEN__)
 #define GPIOA_BIT       (1 << 0)
-#if TIVA_GPIO_GPIOA_USE_AHB && defined(TM4C123x)
-#define GPIOA_AHB_BIT   (1 << 0)
-#else
-#define GPIOA_AHB_BIT   0
-#endif
 #else
 #define GPIOA_BIT       0
-#define GPIOA_AHB_BIT   0
 #endif
 
 #if TIVA_HAS_GPIOB || defined(__DOXYGEN__)
 #define GPIOB_BIT       (1 << 1)
-#if TIVA_GPIO_GPIOB_USE_AHB && defined(TM4C123x)
-#define GPIOB_AHB_BIT   (1 << 1)
-#else
-#define GPIOB_AHB_BIT   0
-#endif
 #else
 #define GPIOB_BIT       0
-#define GPIOB_AHB_BIT   0
 #endif
 
 #if TIVA_HAS_GPIOC || defined(__DOXYGEN__)
 #define GPIOC_BIT       (1 << 2)
-#if TIVA_GPIO_GPIOC_USE_AHB && defined(TM4C123x)
-#define GPIOC_AHB_BIT   (1 << 2)
-#else
-#define GPIOC_AHB_BIT   0
-#endif
 #else
 #define GPIOC_BIT       0
-#define GPIOC_AHB_BIT   0
 #endif
 
 #if TIVA_HAS_GPIOD || defined(__DOXYGEN__)
 #define GPIOD_BIT       (1 << 3)
-#if TIVA_GPIO_GPIOD_USE_AHB && defined(TM4C123x)
-#define GPIOD_AHB_BIT   (1 << 3)
-#else
-#define GPIOD_AHB_BIT   0
-#endif
 #else
 #define GPIOD_BIT       0
-#define GPIOD_AHB_BIT   0
 #endif
 
 #if TIVA_HAS_GPIOE || defined(__DOXYGEN__)
 #define GPIOE_BIT       (1 << 4)
-#if TIVA_GPIO_GPIOE_USE_AHB && defined(TM4C123x)
-#define GPIOE_AHB_BIT   (1 << 4)
-#else
-#define GPIOE_AHB_BIT   0
-#endif
 #else
 #define GPIOE_BIT       0
-#define GPIOE_AHB_BIT   0
 #endif
 
 #if TIVA_HAS_GPIOF || defined(__DOXYGEN__)
 #define GPIOF_BIT       (1 << 5)
-#if TIVA_GPIO_GPIOF_USE_AHB && defined(TM4C123x)
-#define GPIOF_AHB_BIT   (1 << 5)
-#else
-#define GPIOF_AHB_BIT   0
-#endif
 #else
 #define GPIOF_BIT       0
-#define GPIOF_AHB_BIT   0
 #endif
 
 #if TIVA_HAS_GPIOG || defined(__DOXYGEN__)
 #define GPIOG_BIT       (1 << 6)
-#if TIVA_GPIO_GPIOG_USE_AHB && defined(TM4C123x)
-#define GPIOG_AHB_BIT   (1 << 6)
-#else
-#define GPIOG_AHB_BIT   0
-#endif
 #else
 #define GPIOG_BIT       0
-#define GPIOG_AHB_BIT   0
 #endif
 
 #if TIVA_HAS_GPIOH || defined(__DOXYGEN__)
 #define GPIOH_BIT       (1 << 7)
-#if TIVA_GPIO_GPIOH_USE_AHB && defined(TM4C123x)
-#define GPIOH_AHB_BIT   (1 << 7)
-#else
-#define GPIOH_AHB_BIT   0
-#endif
 #else
 #define GPIOH_BIT       0
-#define GPIOH_AHB_BIT   0
 #endif
 
 #if TIVA_HAS_GPIOJ || defined(__DOXYGEN__)
 #define GPIOJ_BIT       (1 << 8)
-#if TIVA_GPIO_GPIOJ_USE_AHB && defined(TM4C123x)
-#define GPIOJ_AHB_BIT   (1 << 8)
-#else
-#define GPIOJ_AHB_BIT   0
-#endif
 #else
 #define GPIOJ_BIT       0
-#define GPIOJ_AHB_BIT   0
 #endif
 
 #if TIVA_HAS_GPIOK || defined(__DOXYGEN__)
 #define GPIOK_BIT       (1 << 9)
-#define GPIOK_AHB_BIT   (1 << 9)
 #else
 #define GPIOK_BIT       0
-#define GPIOK_AHB_BIT   0
 #endif
 
 #if TIVA_HAS_GPIOL || defined(__DOXYGEN__)
 #define GPIOL_BIT       (1 << 10)
-#define GPIOL_AHB_BIT   (1 << 10)
 #else
 #define GPIOL_BIT       0
-#define GPIOL_AHB_BIT   0
 #endif
 
 #if TIVA_HAS_GPIOM || defined(__DOXYGEN__)
 #define GPIOM_BIT       (1 << 11)
-#define GPIOM_AHB_BIT   (1 << 11)
 #else
 #define GPIOM_BIT       0
-#define GPIOM_AHB_BIT   0
 #endif
 
 #if TIVA_HAS_GPION || defined(__DOXYGEN__)
 #define GPION_BIT       (1 << 12)
-#define GPION_AHB_BIT   (1 << 12)
 #else
 #define GPION_BIT       0
-#define GPION_AHB_BIT   0
 #endif
 
 #if TIVA_HAS_GPIOP || defined(__DOXYGEN__)
 #define GPIOP_BIT       (1 << 13)
-#define GPIOP_AHB_BIT   (1 << 13)
 #else
 #define GPIOP_BIT       0
-#define GPIOP_AHB_BIT   0
 #endif
 
 #if TIVA_HAS_GPIOQ || defined(__DOXYGEN__)
 #define GPIOQ_BIT       (1 << 14)
-#define GPIOQ_AHB_BIT   (1 << 14)
 #else
 #define GPIOQ_BIT       0
-#define GPIOQ_AHB_BIT   0
 #endif
 
 #if TIVA_HAS_GPIOR || defined(__DOXYGEN__)
 #define GPIOR_BIT       (1 << 15)
-#define GPIOR_AHB_BIT   (1 << 15)
 #else
 #define GPIOR_BIT       0
-#define GPIOR_AHB_BIT   0
 #endif
 
 #if TIVA_HAS_GPIOS || defined(__DOXYGEN__)
 #define GPIOS_BIT       (1 << 16)
-#define GPIOS_AHB_BIT   (1 << 16)
 #else
 #define GPIOS_BIT       0
-#define GPIOS_AHB_BIT   0
 #endif
 
 #if TIVA_HAS_GPIOT || defined(__DOXYGEN__)
 #define GPIOT_BIT       (1 << 17)
-#define GPIOT_AHB_BIT   (1 << 17)
 #else
 #define GPIOT_BIT       0
-#define GPIOT_AHB_BIT   0
 #endif
 
 #define RCGCGPIO_MASK   (GPIOA_BIT | GPIOB_BIT | GPIOC_BIT | GPIOD_BIT |      \
                          GPIOE_BIT | GPIOF_BIT | GPIOG_BIT | GPIOH_BIT |      \
                          GPIOJ_BIT | GPIOK_BIT | GPIOL_BIT | GPIOM_BIT |      \
                          GPION_BIT | GPIOP_BIT | GPIOQ_BIT | GPIOR_BIT |      \
-                         GPIOS_BIT | GPIOR_BIT)
-
-#define GPIOHBCTL_MASK  (GPIOA_AHB_BIT | GPIOB_AHB_BIT | GPIOC_AHB_BIT |      \
-                         GPIOD_AHB_BIT | GPIOE_AHB_BIT | GPIOF_AHB_BIT |      \
-                         GPIOG_AHB_BIT | GPIOH_AHB_BIT | GPIOJ_AHB_BIT |      \
-                         GPIOK_AHB_BIT | GPIOL_AHB_BIT | GPIOM_AHB_BIT |      \
-                         GPION_AHB_BIT | GPIOP_AHB_BIT | GPIOQ_AHB_BIT |      \
-                         GPIOR_AHB_BIT | GPIOS_AHB_BIT | GPIOT_AHB_BIT)
+                         GPIOS_BIT | GPIOT_BIT)
+
+#define GPIOHBCTL_MASK  (GPIO_MASK &                                          \
+                        (GPIOA_BIT | GPIOB_BIT | GPIOC_BIT | GPIOD_BIT |      \
+                         GPIOE_BIT | GPIOF_BIT | GPIOG_BIT | GPIOH_BIT |      \
+                         GPIOJ_BIT))
 
 #define GPIOC_JTAG_MASK     (0x0F)
 #define GPIOD_NMI_MASK      (0x80)
diff --git a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h
index cf14bfb..d4b634d 100644
--- a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h
+++ b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h
@@ -337,149 +337,19 @@ typedef uint32_t ioportid_t;
 /* Driver pre-compile time settings.                                         */
 /*===========================================================================*/
 
-#if defined(TM4C123x)
-
-/**
- * @brief   GPIOA AHB enable switch.
- * @details When set to @p TRUE the AHB bus is used to access GPIOA. When set
- *          to @p FALSE the APB bus is used to access GPIOA.
- */
-#if !defined(TIVA_GPIO_GPIOA_USE_AHB) || defined(__DOXYGEN__)
-#define TIVA_GPIO_GPIOA_USE_AHB             TRUE
-#endif
-
-/**
- * @brief   GPIOB AHB enable switch.
- * @details When set to @p TRUE the AHB bus is used to access GPIOB. When set
- *          to @p FALSE the APB bus is used to access GPIOB.
- */
-#if !defined(TIVA_GPIO_GPIOB_USE_AHB) || defined(__DOXYGEN__)
-#define TIVA_GPIO_GPIOB_USE_AHB             TRUE
-#endif
-
-/**
- * @brief   GPIOC AHB enable switch.
- * @details When set to @p TRUE the AHB bus is used to access GPIOC. When set
- *          to @p FALSE the APB bus is used to access GPIOC.
- */
-#if !defined(TIVA_GPIO_GPIOC_USE_AHB) || defined(__DOXYGEN__)
-#define TIVA_GPIO_GPIOC_USE_AHB             TRUE
-#endif
-
-/**
- * @brief   GPIOD AHB enable switch.
- * @details When set to @p TRUE the AHB bus is used to access GPIOD. When set
- *          to @p FALSE the APB bus is used to access GPIOD.
- */
-#if !defined(TIVA_GPIO_GPIOD_USE_AHB) || defined(__DOXYGEN__)
-#define TIVA_GPIO_GPIOD_USE_AHB             TRUE
-#endif
-
-/**
- * @brief   GPIOE AHB enable switch.
- * @details When set to @p TRUE the AHB bus is used to access GPIOE. When set
- *          to @p FALSE the APB bus is used to access GPIOE.
- */
-#if !defined(TIVA_GPIO_GPIOE_USE_AHB) || defined(__DOXYGEN__)
-#define TIVA_GPIO_GPIOE_USE_AHB             TRUE
-#endif
-
-/**
- * @brief   GPIOF AHB enable switch.
- * @details When set to @p TRUE the AHB bus is used to access GPIOF. When set
- *          to @p FALSE the APB bus is used to access GPIOF.
- */
-#if !defined(TIVA_GPIO_GPIOF_USE_AHB) || defined(__DOXYGEN__)
-#define TIVA_GPIO_GPIOF_USE_AHB             TRUE
-#endif
-
-/**
- * @brief   GPIOG AHB enable switch.
- * @details When set to @p TRUE the AHB bus is used to access GPIOG. When set
- *          to @p FALSE the APB bus is used to access GPIOG.
- */
-#if !defined(TIVA_GPIO_GPIOG_USE_AHB) || defined(__DOXYGEN__)
-#define TIVA_GPIO_GPIOG_USE_AHB             TRUE
-#endif
-
-/**
- * @brief   GPIOH AHB enable switch.
- * @details When set to @p TRUE the AHB bus is used to access GPIOH. When set
- *          to @p FALSE the APB bus is used to access GPIOH.
- */
-#if !defined(TIVA_GPIO_GPIOH_USE_AHB) || defined(__DOXYGEN__)
-#define TIVA_GPIO_GPIOH_USE_AHB             TRUE
-#endif
-
-/**
- * @brief   GPIOJ AHB enable switch.
- * @details When set to @p TRUE the AHB bus is used to access GPIOJ. When set
- *          to @p FALSE the APB bus is used to access GPIOJ.
- */
-#if !defined(TIVA_GPIO_GPIOJ_USE_AHB) || defined(__DOXYGEN__)
-#define TIVA_GPIO_GPIOJ_USE_AHB             TRUE
-#endif
-
-#endif
-
 /*===========================================================================*/
 /* Derived constants and error checks.                                       */
 /*===========================================================================*/
 
-#if TIVA_GPIO_GPIOA_USE_AHB && defined(TM4C123x)
 #define GPIOA                               GPIO_PORTA_AHB_BASE
-#else
-#define GPIOA                               GPIO_PORTA_BASE
-#endif
-
-#if TIVA_GPIO_GPIOB_USE_AHB && defined(TM4C123x)
 #define GPIOB                               GPIO_PORTB_AHB_BASE
-#else
-#define GPIOB                               GPIO_PORTB_BASE
-#endif
-
-#if TIVA_GPIO_GPIOC_USE_AHB && defined(TM4C123x)
 #define GPIOC                               GPIO_PORTC_AHB_BASE
-#else
-#define GPIOC                               GPIO_PORTC_BASE
-#endif
-
-#if TIVA_GPIO_GPIOD_USE_AHB && defined(TM4C123x)
 #define GPIOD                               GPIO_PORTD_AHB_BASE
-#else
-#define GPIOD                               GPIO_PORTD_BASE
-#endif
-
-#if TIVA_GPIO_GPIOE_USE_AHB && defined(TM4C123x)
 #define GPIOE                               GPIO_PORTE_AHB_BASE
-#else
-#define GPIOE                               GPIO_PORTE_BASE
-#endif
-
-#if TIVA_GPIO_GPIOF_USE_AHB && defined(TM4C123x)
 #define GPIOF                               GPIO_PORTF_AHB_BASE
-#else
-#define GPIOF                               GPIO_PORTF_BASE
-#endif
-
-#if TIVA_GPIO_GPIOG_USE_AHB && defined(TM4C123x)
 #define GPIOG                               GPIO_PORTG_AHB_BASE
-#else
-#define GPIOG                               GPIO_PORTG_BASE
-#endif
-
-#if TIVA_GPIO_GPIOH_USE_AHB && defined(TM4C123x)
 #define GPIOH                               GPIO_PORTH_AHB_BASE
-#else
-#define GPIOH                               GPIO_PORTH_BASE
-#endif
-
-#if TIVA_GPIO_GPIOJ_USE_AHB && defined(TM4C123x)
 #define GPIOJ                               GPIO_PORTJ_AHB_BASE
-#else
-#define GPIOJ                               GPIO_PORTJ_BASE
-#endif
-
 #define GPIOK                               GPIO_PORTK_BASE
 #define GPIOL                               GPIO_PORTL_BASE
 #define GPIOM                               GPIO_PORTM_BASE
-- 
cgit v1.2.3


From 927b3cf1b4e00ef1c0fc31fb46f2db1c909ecde8 Mon Sep 17 00:00:00 2001
From: marcoveeneman <marco-veeneman@hotmail.com>
Date: Thu, 1 Mar 2018 23:13:01 +0100
Subject: Fixed bug in pal_lld_writepad implementation

---
 os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'os')

diff --git a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h
index d4b634d..50f37d5 100644
--- a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h
+++ b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h
@@ -631,7 +631,7 @@ typedef uint32_t ioportid_t;
  * @notapi
  */
 #define pal_lld_writepad(port, pad, bit)    \
-  (HWREG((port) + (GPIO_O_DATA + ((1 << (pad)) << 2))) = (bit))
+  (HWREG((port) + (GPIO_O_DATA + ((1 << (pad)) << 2))) = 1 << (bit))
 
 /**
  * @brief   Sets a pad logical state to @p PAL_HIGH.
-- 
cgit v1.2.3


From ff7d474ecd9fbf9d0aba0a9eeb9ac6e26c8d033b Mon Sep 17 00:00:00 2001
From: marcoveeneman <marco-veeneman@hotmail.com>
Date: Fri, 2 Mar 2018 00:02:48 +0100
Subject: Updated platform.mk files to handle halconf.h files located in
 CONFDIR

---
 os/hal/ports/TIVA/TM4C123x/platform.mk | 9 ++++++++-
 os/hal/ports/TIVA/TM4C129x/platform.mk | 9 ++++++++-
 2 files changed, 16 insertions(+), 2 deletions(-)

(limited to 'os')

diff --git a/os/hal/ports/TIVA/TM4C123x/platform.mk b/os/hal/ports/TIVA/TM4C123x/platform.mk
index de482d0..8372c25 100644
--- a/os/hal/ports/TIVA/TM4C123x/platform.mk
+++ b/os/hal/ports/TIVA/TM4C123x/platform.mk
@@ -7,7 +7,14 @@ PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
                ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C123x
 
 ifeq ($(USE_SMART_BUILD),yes)
-HALCONF := $(strip $(shell cat halconf.h | egrep -e "\#define"))
+
+# Configuration files directory
+ifeq ($(CONFDIR),)
+  CONFDIR = .
+endif
+
+HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h | egrep -e "\#define"))
+else
 endif
 
 # Drivers compatible with the platform.
diff --git a/os/hal/ports/TIVA/TM4C129x/platform.mk b/os/hal/ports/TIVA/TM4C129x/platform.mk
index 8e4c9fa..934a6c2 100644
--- a/os/hal/ports/TIVA/TM4C129x/platform.mk
+++ b/os/hal/ports/TIVA/TM4C129x/platform.mk
@@ -7,7 +7,14 @@ PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \
                ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C129x
 
 ifeq ($(USE_SMART_BUILD),yes)
-HALCONF := $(strip $(shell cat halconf.h | egrep -e "\#define"))
+
+# Configuration files directory
+ifeq ($(CONFDIR),)
+  CONFDIR = .
+endif
+
+HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h | egrep -e "\#define"))
+else
 endif
 
 # Drivers compatible with the platform.
-- 
cgit v1.2.3


From 7057148a4344deed3835d8ae8bfb49f4967911b8 Mon Sep 17 00:00:00 2001
From: marcoveeneman <marco-veeneman@hotmail.com>
Date: Fri, 2 Mar 2018 00:05:39 +0100
Subject: Fixed hal_st_lld still using old register access.

Registers are now accessed using the HWREG() macro.
---
 os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c | 44 ++++++++++++++++-----------------
 1 file changed, 22 insertions(+), 22 deletions(-)

(limited to 'os')

diff --git a/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c
index baa7112..7da95b8 100644
--- a/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c
+++ b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c
@@ -37,32 +37,32 @@
 #if TIVA_ST_TIMER_NUMBER == 0
 #define ST_HANDLER                          TIVA_WGPT0A_HANDLER
 #define ST_NUMBER                           TIVA_WGPT0A_NUMBER
-#define ST_ENABLE_CLOCK()                   (SYSCTL->RCGCWTIMER |= (1 << 0))
-#define ST_WAIT_CLOCK()                     while (!(SYSCTL->PRWTIMER & (1 << 0)))
+#define ST_ENABLE_CLOCK()                   (HWREG(SYSCTL_RCGCWTIMER) |= (1 << 0))
+#define ST_WAIT_CLOCK()                     while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 0)))
 
 #elif TIVA_ST_TIMER_NUMBER == 1
 #define ST_HANDLER                          TIVA_WGPT1A_HANDLER
 #define ST_NUMBER                           TIVA_WGPT1A_NUMBER
-#define ST_ENABLE_CLOCK()                   (SYSCTL->RCGCWTIMER |= (1 << 1))
-#define ST_WAIT_CLOCK()                     while (!(SYSCTL->PRWTIMER & (1 << 1)))
+#define ST_ENABLE_CLOCK()                   (HWREG(SYSCTL_RCGCWTIMER) |= (1 << 1))
+#define ST_WAIT_CLOCK()                     while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 1)))
 
 #elif TIVA_ST_TIMER_NUMBER == 2
 #define ST_HANDLER                          TIVA_WGPT2A_HANDLER
 #define ST_NUMBER                           TIVA_WGPT2A_NUMBER
-#define ST_ENABLE_CLOCK()                   (SYSCTL->RCGCWTIMER |= (1 << 2))
-#define ST_WAIT_CLOCK()                     while (!(SYSCTL->PRWTIMER & (1 << 2)))
+#define ST_ENABLE_CLOCK()                   (HWREG(SYSCTL_RCGCWTIMER) |= (1 << 2))
+#define ST_WAIT_CLOCK()                     while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 2)))
 
 #elif TIVA_ST_TIMER_NUMBER == 3
 #define ST_HANDLER                          TIVA_WGPT3A_HANDLER
 #define ST_NUMBER                           TIVA_WGPT3A_NUMBER
-#define ST_ENABLE_CLOCK()                   (SYSCTL->RCGCWTIMER |= (1 << 3))
-#define ST_WAIT_CLOCK()                     while (!(SYSCTL->PRWTIMER & (1 << 3)))
+#define ST_ENABLE_CLOCK()                   (HWREG(SYSCTL_RCGCWTIMER) |= (1 << 3))
+#define ST_WAIT_CLOCK()                     while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 3)))
 
 #elif TIVA_ST_TIMER_NUMBER == 4
 #define ST_HANDLER                          TIVA_WGPT4A_HANDLER
 #define ST_NUMBER                           TIVA_WGPT4A_NUMBER
-#define ST_ENABLE_CLOCK()                   (SYSCTL->RCGCWTIMER |= (1 << 4))
-#define ST_WAIT_CLOCK()                     while (!(SYSCTL->PRWTIMER & (1 << 4)))
+#define ST_ENABLE_CLOCK()                   (HWREG(SYSCTL_RCGCWTIMER) |= (1 << 4))
+#define ST_WAIT_CLOCK()                     while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 4)))
 
 #elif TIVA_ST_TIMER_NUMBER == 5
 #define ST_HANDLER                          TIVA_WGPT5A_HANDLER
@@ -83,38 +83,38 @@
 #if TIVA_ST_TIMER_NUMBER == 0
 #define ST_HANDLER                          TIVA_GPT0A_HANDLER
 #define ST_NUMBER                           TIVA_GPT0A_NUMBER
-#define ST_ENABLE_CLOCK()                   (SYSCTL->RCGCTIMER |= (1 << 0))
-#define ST_WAIT_CLOCK()                     while (!(SYSCTL->PRTIMER & (1 << 0)))
+#define ST_ENABLE_CLOCK()                   (HWREG(SYSCTL_RCGCTIMER) |= (1 << 0))
+#define ST_WAIT_CLOCK()                     while (!(HWREG(SYSCTL_PRTIMER) & (1 << 0)))
 
 #elif TIVA_ST_TIMER_NUMBER == 1
 #define ST_HANDLER                          TIVA_GPT1A_HANDLER
 #define ST_NUMBER                           TIVA_GPT1A_NUMBER
-#define ST_ENABLE_CLOCK()                   (SYSCTL->RCGCTIMER |= (1 << 1))
-#define ST_WAIT_CLOCK()                     while (!(SYSCTL->PRTIMER & (1 << 1)))
+#define ST_ENABLE_CLOCK()                   (HWREG(SYSCTL_RCGCTIMER) |= (1 << 1))
+#define ST_WAIT_CLOCK()                     while (!(HWREG(SYSCTL_PRTIMER) & (1 << 1)))
 
 #elif TIVA_ST_TIMER_NUMBER == 2
 #define ST_HANDLER                          TIVA_GPT2A_HANDLER
 #define ST_NUMBER                           TIVA_GPT2A_NUMBER
-#define ST_ENABLE_CLOCK()                   (SYSCTL->RCGCTIMER |= (1 << 2))
-#define ST_WAIT_CLOCK()                     while (!(SYSCTL->PRTIMER & (1 << 2)))
+#define ST_ENABLE_CLOCK()                   (HWREG(SYSCTL_RCGCTIMER) |= (1 << 2))
+#define ST_WAIT_CLOCK()                     while (!(HWREG(SYSCTL_PRTIMER) & (1 << 2)))
 
 #elif TIVA_ST_TIMER_NUMBER == 3
 #define ST_HANDLER                          TIVA_GPT3A_HANDLER
 #define ST_NUMBER                           TIVA_GPT3A_NUMBER
-#define ST_ENABLE_CLOCK()                   (SYSCTL->RCGCTIMER |= (1 << 3))
-#define ST_WAIT_CLOCK()                     while (!(SYSCTL->PRTIMER & (1 << 3)))
+#define ST_ENABLE_CLOCK()                   (HWREG(SYSCTL_RCGCTIMER) |= (1 << 3))
+#define ST_WAIT_CLOCK()                     while (!(HWREG(SYSCTL_PRTIMER) & (1 << 3)))
 
 #elif TIVA_ST_TIMER_NUMBER == 4
 #define ST_HANDLER                          TIVA_GPT4A_HANDLER
 #define ST_NUMBER                           TIVA_GPT4A_NUMBER
-#define ST_ENABLE_CLOCK()                   (SYSCTL->RCGCTIMER |= (1 << 4))
-#define ST_WAIT_CLOCK()                     while (!(SYSCTL->PRTIMER & (1 << 4)))
+#define ST_ENABLE_CLOCK()                   (HWREG(SYSCTL_RCGCTIMER) |= (1 << 4))
+#define ST_WAIT_CLOCK()                     while (!(HWREG(SYSCTL_PRTIMER) & (1 << 4)))
 
 #elif TIVA_ST_TIMER_NUMBER == 5
 #define ST_HANDLER                          TIVA_GPT5A_HANDLER
 #define ST_NUMBER                           TIVA_GPT5A_NUMBER
-#define ST_ENABLE_CLOCK()                   (SYSCTL->RCGCTIMER |= (1 << 5))
-#define ST_WAIT_CLOCK()                     while (!(SYSCTL->PRTIMER & (1 << 5)))
+#define ST_ENABLE_CLOCK()                   (HWREG(SYSCTL_RCGCTIMER) |= (1 << 5))
+#define ST_WAIT_CLOCK()                     while (!(HWREG(SYSCTL_PRTIMER) & (1 << 5)))
 
 #else
 #error "TIVA_ST_USE_TIMER specifies an unsupported timer"
-- 
cgit v1.2.3


From f8b91dc68237c98e6a82024251df59decdcd1de4 Mon Sep 17 00:00:00 2001
From: marcoveeneman <marco-veeneman@hotmail.com>
Date: Fri, 2 Mar 2018 00:07:02 +0100
Subject: Added number of GPIO pins to TM4C129x registry.

---
 os/hal/ports/TIVA/TM4C129x/tiva_registry.h | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'os')

diff --git a/os/hal/ports/TIVA/TM4C129x/tiva_registry.h b/os/hal/ports/TIVA/TM4C129x/tiva_registry.h
index 163d59c..cd8344d 100644
--- a/os/hal/ports/TIVA/TM4C129x/tiva_registry.h
+++ b/os/hal/ports/TIVA/TM4C129x/tiva_registry.h
@@ -77,6 +77,7 @@
 #define TIVA_HAS_GPIOR                      FALSE
 #define TIVA_HAS_GPIOS                      FALSE
 #define TIVA_HAS_GPIOT                      FALSE
+#define TIVA_GPIO_PINS                      120
 #endif
 #if defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294NCZAD)\
   || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD) || defined(PART_TM4C1299NCZAD)\
@@ -100,6 +101,7 @@
 #define TIVA_HAS_GPIOR                      TRUE
 #define TIVA_HAS_GPIOS                      TRUE
 #define TIVA_HAS_GPIOT                      TRUE
+#define TIVA_GPIO_PINS                      144
 #endif
 
 /* EPI attributes.*/
-- 
cgit v1.2.3


From 2977a2bc8792f800b4b41f1649d596aec6894461 Mon Sep 17 00:00:00 2001
From: marcoveeneman <marco-veeneman@hotmail.com>
Date: Fri, 2 Mar 2018 00:09:45 +0100
Subject: Implemented events to PAL driver for Tiva devices.

Most code from the EXT driver could be reused.
---
 os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c | 772 ++++++++++++++++++++++++++++++-
 os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h | 454 ++++++++++++++++++
 2 files changed, 1223 insertions(+), 3 deletions(-)

(limited to 'os')

diff --git a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c
index 0be8d6d..a2b297b 100644
--- a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c
+++ b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c
@@ -144,10 +144,9 @@
                          GPION_BIT | GPIOP_BIT | GPIOQ_BIT | GPIOR_BIT |      \
                          GPIOS_BIT | GPIOT_BIT)
 
-#define GPIOHBCTL_MASK  (GPIO_MASK &                                          \
-                        (GPIOA_BIT | GPIOB_BIT | GPIOC_BIT | GPIOD_BIT |      \
+#define GPIOHBCTL_MASK  (GPIOA_BIT | GPIOB_BIT | GPIOC_BIT | GPIOD_BIT |      \
                          GPIOE_BIT | GPIOF_BIT | GPIOG_BIT | GPIOH_BIT |      \
-                         GPIOJ_BIT))
+                         GPIOJ_BIT)
 
 #define GPIOC_JTAG_MASK     (0x0F)
 #define GPIOD_NMI_MASK      (0x80)
@@ -157,6 +156,11 @@
 /* Driver exported variables.                                                */
 /*===========================================================================*/
 
+/**
+ * @brief   Event records for all GPIO channels.
+ */
+palevent_t _pal_events[TIVA_GPIO_PINS];
+
 /*===========================================================================*/
 /* Driver local variables and types.                                         */
 /*===========================================================================*/
@@ -202,10 +206,608 @@ static void gpio_unlock(ioportid_t port, ioportmask_t mask)
   HWREG(port + GPIO_O_CR) = mask;
 }
 
+#if PAL_USE_CALLBACKS || PAL_USE_WAIT
+/**
+ * @brief   Enables GPIO IRQ sources.
+ */
+static void gpio_irq_enable(void)
+{
+#if TIVA_HAS_GPIOA
+  nvicEnableVector(TIVA_GPIOA_NUMBER, TIVA_EXT_GPIOA_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOB
+  nvicEnableVector(TIVA_GPIOB_NUMBER, TIVA_EXT_GPIOB_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOC
+  nvicEnableVector(TIVA_GPIOC_NUMBER, TIVA_EXT_GPIOC_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOD
+  nvicEnableVector(TIVA_GPIOD_NUMBER, TIVA_EXT_GPIOD_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOE
+  nvicEnableVector(TIVA_GPIOE_NUMBER, TIVA_EXT_GPIOE_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOF
+  nvicEnableVector(TIVA_GPIOF_NUMBER, TIVA_EXT_GPIOF_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOG
+  nvicEnableVector(TIVA_GPIOG_NUMBER, TIVA_EXT_GPIOG_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOH
+  nvicEnableVector(TIVA_GPIOH_NUMBER, TIVA_EXT_GPIOH_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOJ
+  nvicEnableVector(TIVA_GPIOJ_NUMBER, TIVA_EXT_GPIOJ_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOK
+  nvicEnableVector(TIVA_GPIOK_NUMBER, TIVA_EXT_GPIOK_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOL
+  nvicEnableVector(TIVA_GPIOL_NUMBER, TIVA_EXT_GPIOL_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOM
+  nvicEnableVector(TIVA_GPIOM_NUMBER, TIVA_EXT_GPIOM_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPION
+  nvicEnableVector(TIVA_GPION_NUMBER, TIVA_EXT_GPION_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOP
+  nvicEnableVector(TIVA_GPIOP0_NUMBER, TIVA_EXT_GPIOP0_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOP1_NUMBER, TIVA_EXT_GPIOP1_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOP2_NUMBER, TIVA_EXT_GPIOP2_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOP3_NUMBER, TIVA_EXT_GPIOP3_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOP4_NUMBER, TIVA_EXT_GPIOP4_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOP5_NUMBER, TIVA_EXT_GPIOP5_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOP6_NUMBER, TIVA_EXT_GPIOP6_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOP7_NUMBER, TIVA_EXT_GPIOP7_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOQ
+  nvicEnableVector(TIVA_GPIOQ0_NUMBER, TIVA_EXT_GPIOQ0_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOQ1_NUMBER, TIVA_EXT_GPIOQ1_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOQ2_NUMBER, TIVA_EXT_GPIOQ2_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOQ3_NUMBER, TIVA_EXT_GPIOQ3_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOQ4_NUMBER, TIVA_EXT_GPIOQ4_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOQ5_NUMBER, TIVA_EXT_GPIOQ5_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOQ6_NUMBER, TIVA_EXT_GPIOQ6_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOQ7_NUMBER, TIVA_EXT_GPIOQ7_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOR
+  nvicEnableVector(TIVA_GPIOR_NUMBER, TIVA_EXT_GPIOR_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOS
+  nvicEnableVector(TIVA_GPIOS_NUMBER, TIVA_EXT_GPIOS_IRQ_PRIORITY);
+#endif
+#if TIVA_HAS_GPIOT
+  nvicEnableVector(TIVA_GPIOT_NUMBER, TIVA_EXT_GPIOT_IRQ_PRIORITY);
+#endif
+}
+#endif
+
+#define gpio_serve_irq(mask, pin, channel) {                                \
+                                                                            \
+  if ((mask) & (1U << (pin))) {                                         \
+    _pal_isr_code(channel);                                                 \
+  }                                                                         \
+}
+
+/**
+ * @brief   Generic interrupt serving code for multiple pins per interrupt
+ *          handler.
+ */
+#define ext_lld_serve_port_interrupt(gpio, start)                             \
+  do {                                                                        \
+    uint32_t mis = HWREG(gpio + GPIO_O_MIS);                                  \
+                                                                              \
+    HWREG(gpio + GPIO_O_ICR) = mis;                                           \
+                                                                              \
+    gpio_serve_irq(mis, 0, start + 0);                                        \
+    gpio_serve_irq(mis, 1, start + 1);                                        \
+    gpio_serve_irq(mis, 2, start + 2);                                        \
+    gpio_serve_irq(mis, 3, start + 3);                                        \
+    gpio_serve_irq(mis, 4, start + 4);                                        \
+    gpio_serve_irq(mis, 5, start + 5);                                        \
+    gpio_serve_irq(mis, 6, start + 6);                                        \
+    gpio_serve_irq(mis, 7, start + 7);                                        \
+  } while (0);
+
+/**
+ * @brief   Generic interrupt serving code for single pin per interrupt
+ *          handler.
+ */
+#define ext_lld_serve_pin_interrupt(gpio, start, pin)                         \
+  do {                                                                        \
+    HWREG(gpio + GPIO_O_ICR) = (1 << pin);                                    \
+    gpio_serve_irq((1 << pin), pin, start)                                    \
+  } while (0);
+
 /*===========================================================================*/
 /* Driver interrupt handlers.                                                */
 /*===========================================================================*/
 
+#if TIVA_HAS_GPIOA || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOA interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOA_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPIOA, 0);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOB || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOB interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOB_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPIOB, 8);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOC || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOC interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOC_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPIOC, 16);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOD || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOD interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOD_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPIOD, 24);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOE || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOE interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOE_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPIOE, 32);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOF || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOF interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOF_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPIOF, 40);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOG || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOG interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOG_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPIOG, 48);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOH || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOH interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOH_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPIOH, 56);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOJ interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOJ_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPIOJ, 64);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOK || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOK interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOK_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPIOK, 72);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOL || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOL interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOL_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPIOL, 80);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOM || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOM interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOM_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPIOM, 88);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPION || defined(__DOXYGEN__)
+/**
+ * @brief   GPION interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPION_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPION, 96);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOP || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOP0 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOP0_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(GPIOP, 104, 0);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOP1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOP1_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(GPIOP, 105, 1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOP2 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOP2_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(GPIOP, 106, 2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOP3 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOP3_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(GPIOP, 107, 3);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOP4 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOP4_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(GPIOP, 108, 4);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOP5 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOP5_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(GPIOP, 109, 5);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOP6 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOP6_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(GPIOP, 110, 6);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOP7 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOP7_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(GPIOP, 111, 7);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOQ0 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOQ0_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(GPIOQ, 112, 0);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOQ1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOQ1_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(GPIOQ, 113, 1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOQ2 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOQ2_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(GPIOQ, 114, 2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOQ3 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOQ3_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(GPIOQ, 115, 3);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOQ4 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOQ4_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(GPIOQ, 116, 4);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOQ5 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOQ5_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(GPIOQ, 117, 5);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOQ6 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOQ6_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(GPIOQ, 118, 6);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+/**
+ * @brief   GPIOQ7 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOQ7_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_pin_interrupt(GPIOQ, 119, 7);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOR || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOR interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOR_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPIOR, 120);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOS || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOS interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOS_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPIOS, 128);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if TIVA_HAS_GPIOT || defined(__DOXYGEN__)
+/**
+ * @brief   GPIOT interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(TIVA_GPIOT_HANDLER)
+{
+  OSAL_IRQ_PROLOGUE();
+
+  ext_lld_serve_port_interrupt(GPIOT, 132);
+
+  OSAL_IRQ_EPILOGUE();
+}
+#endif
+
 /*===========================================================================*/
 /* Driver exported functions.                                                */
 /*===========================================================================*/
@@ -220,6 +822,14 @@ static void gpio_unlock(ioportid_t port, ioportmask_t mask)
  */
 void _pal_lld_init(const PALConfig *config)
 {
+#if PAL_USE_CALLBACKS || PAL_USE_WAIT || defined(__DOXYGEN__)
+  unsigned i;
+
+  for (i = 0; i < TIVA_GPIO_PINS; i++) {
+    _pal_init_event(i);
+  }
+#endif
+
   /*
    * Enables all GPIO clocks.
    */
@@ -292,6 +902,9 @@ void _pal_lld_init(const PALConfig *config)
 #if TIVA_HAS_GPIOT || defined(__DOXYGEN__)
   gpio_init(GPIOT, &config->PTData);
 #endif
+#if PAL_USE_CALLBACKS || PAL_USE_WAIT
+  gpio_irq_enable();
+#endif
 }
 
 /**
@@ -362,6 +975,159 @@ void _pal_lld_setgroupmode(ioportid_t port, ioportmask_t mask, iomode_t mode)
   }
 }
 
+#if PAL_USE_CALLBACKS || PAL_USE_WAIT || defined(__DOXYGEN__)
+/**
+ * @brief   Pad event enable.
+ * @note    Programming an unknown or unsupported mode is silently ignored.
+ *
+ * @param[in] port      port identifier
+ * @param[in] pad       pad number within the port
+ * @param[in] mode      pad event mode
+ *
+ * @notapi
+ */
+void _pal_lld_enablepadevent(ioportid_t port,
+                             iopadid_t pad,
+                             ioeventmode_t mode)
+{
+  //uint8_t portidx;
+  uint32_t padmask;
+
+  //portidx = (((uint32_t)port - (uint32_t)GPIOA) >> 12) & 0x1FU;
+  padmask = (1 << pad);
+
+  /* Disable interrupt before changing edge configuration.*/
+  HWREG(port + GPIO_O_IM) &= ~padmask;
+
+  /* Configure pin to be edge-sensitive.*/
+  HWREG(port + GPIO_O_IS) &= ~(1 << pad);
+
+  /* Configure edges */
+  switch(mode & PAL_EVENT_MODE_EDGES_MASK) {
+  case PAL_EVENT_MODE_BOTH_EDGES:
+    HWREG(port + GPIO_O_IBE) |= padmask;
+    break;
+  case PAL_EVENT_MODE_RISING_EDGE:
+    HWREG(port + GPIO_O_IBE) &= ~padmask;
+    HWREG(port + GPIO_O_IEV) &= ~padmask;
+    break;
+  case PAL_EVENT_MODE_FALLING_EDGE:
+    HWREG(port + GPIO_O_IBE) &= ~padmask;
+    HWREG(port + GPIO_O_IEV) |= padmask;
+    break;
+  default:
+    /* Interrupt is already disabled */
+    break;
+  }
+
+  if (mode & PAL_EVENT_MODE_EDGES_MASK) {
+    /* Enable interrupt for this pad */
+    HWREG(port + GPIO_O_IM) |= padmask;
+  }
+}
+
+/**
+ * @brief   Pad event disable.
+ * @details This function disables previously programmed event callbacks.
+ *
+ * @param[in] port      port identifier
+ * @param[in] pad       pad number within the port
+ *
+ * @notapi
+ */
+void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad)
+{
+  uint8_t portidx;
+  uint8_t eventidx;
+
+  portidx = (((uint32_t)port - (uint32_t)GPIOA) >> 12) & 0x1FU;
+
+  eventidx = portidx * 8 + pad;
+
+  HWREG(port + GPIO_O_IM) &= ~(1 << pad);
+
+#if PAL_USE_CALLBACKS || PAL_USE_WAIT
+  /* Callback cleared and/or thread reset.*/
+  _pal_clear_event(eventidx);
+#endif
+}
+
+/**
+ * @brief   Disables GPIO IRQ sources.
+ */
+void pal_lld_disable_irqs(void)
+{
+#if TIVA_HAS_GPIOA
+  nvicDisableVector(TIVA_GPIOA_NUMBER);
+#endif
+#if TIVA_HAS_GPIOB
+  nvicDisableVector(TIVA_GPIOB_NUMBER);
+#endif
+#if TIVA_HAS_GPIOC
+  nvicDisableVector(TIVA_GPIOC_NUMBER);
+#endif
+#if TIVA_HAS_GPIOD
+  nvicDisableVector(TIVA_GPIOD_NUMBER);
+#endif
+#if TIVA_HAS_GPIOE
+  nvicDisableVector(TIVA_GPIOE_NUMBER);
+#endif
+#if TIVA_HAS_GPIOF
+  nvicDisableVector(TIVA_GPIOF_NUMBER);
+#endif
+#if TIVA_HAS_GPIOG
+  nvicDisableVector(TIVA_GPIOG_NUMBER);
+#endif
+#if TIVA_HAS_GPIOH
+  nvicDisableVector(TIVA_GPIOH_NUMBER);
+#endif
+#if TIVA_HAS_GPIOJ
+  nvicDisableVector(TIVA_GPIOJ_NUMBER);
+#endif
+#if TIVA_HAS_GPIOK
+  nvicDisableVector(TIVA_GPIOK_NUMBER);
+#endif
+#if TIVA_HAS_GPIOL
+  nvicDisableVector(TIVA_GPIOL_NUMBER);
+#endif
+#if TIVA_HAS_GPIOM
+  nvicDisableVector(TIVA_GPIOM_NUMBER);
+#endif
+#if TIVA_HAS_GPION
+  nvicDisableVector(TIVA_GPION_NUMBER);
+#endif
+#if TIVA_HAS_GPIOP
+  nvicDisableVector(TIVA_GPIOP0_NUMBER);
+  nvicDisableVector(TIVA_GPIOP1_NUMBER);
+  nvicDisableVector(TIVA_GPIOP2_NUMBER);
+  nvicDisableVector(TIVA_GPIOP3_NUMBER);
+  nvicDisableVector(TIVA_GPIOP4_NUMBER);
+  nvicDisableVector(TIVA_GPIOP5_NUMBER);
+  nvicDisableVector(TIVA_GPIOP6_NUMBER);
+  nvicDisableVector(TIVA_GPIOP7_NUMBER);
+#endif
+#if TIVA_HAS_GPIOQ
+  nvicDisableVector(TIVA_GPIOQ0_NUMBER);
+  nvicDisableVector(TIVA_GPIOQ1_NUMBER);
+  nvicDisableVector(TIVA_GPIOQ2_NUMBER);
+  nvicDisableVector(TIVA_GPIOQ3_NUMBER);
+  nvicDisableVector(TIVA_GPIOQ4_NUMBER);
+  nvicDisableVector(TIVA_GPIOQ5_NUMBER);
+  nvicDisableVector(TIVA_GPIOQ6_NUMBER);
+  nvicDisableVector(TIVA_GPIOQ7_NUMBER);
+#endif
+#if TIVA_HAS_GPIOR
+  nvicDisableVector(TIVA_GPIOR_NUMBER);
+#endif
+#if TIVA_HAS_GPIOS
+  nvicDisableVector(TIVA_GPIOS_NUMBER);
+#endif
+#if TIVA_HAS_GPIOT
+  nvicDisableVector(TIVA_GPIOT_NUMBER);
+#endif
+}
+#endif /* PAL_USE_CALLBACKS || PAL_USE_WAIT */
+
 #endif /* HAL_USE_PAL */
 
 /**
diff --git a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h
index 50f37d5..34577ee 100644
--- a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h
+++ b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h
@@ -328,15 +328,255 @@ typedef uint32_t iomode_t;
  */
 typedef uint32_t ioline_t;
 
+/**
+ * @brief   Type of an event mode.
+ */
+typedef uint32_t ioeventmode_t;
+
 /**
  * @brief   Port Identifier.
  */
 typedef uint32_t ioportid_t;
 
+/**
+ * @brief   Type of an pad identifier.
+ */
+typedef uint32_t iopadid_t;
+
 /*===========================================================================*/
 /* Driver pre-compile time settings.                                         */
 /*===========================================================================*/
 
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   GPIOA interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOA_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOA_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOB interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOB_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOB_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOC interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOC_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOC_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOD interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOD_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOD_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOE interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOE_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOE_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOF interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOF_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOF_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOG interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOG_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOG_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOH interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOH_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOH_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOJ interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOJ_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOJ_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOK interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOK_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOK_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOL interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOL_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOL_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOM interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOM_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOM_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPION interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPION_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPION_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOP0 interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOP0_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOP0_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOP1 interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOP1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOP1_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOP2 interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOP2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOP2_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOP3 interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOP3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOP3_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOP4 interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOP4_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOP4_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOP5 interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOP5_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOP5_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOP6 interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOP6_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOP6_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOP7 interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOP7_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOP7_IRQ_PRIORITY        3
+#endif
+/** @} */
+
+/**
+ * @brief   GPIOQ0 interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOQ0_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOQ0_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOQ1 interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOQ1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOQ1_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOQ2 interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOQ2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOQ2_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOQ3 interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOQ3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOQ3_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOQ4 interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOQ4_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOQ4_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOQ5 interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOQ5_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOQ5_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOQ6 interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOQ6_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOQ6_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOQ7 interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOQ7_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOQ7_IRQ_PRIORITY        3
+#endif
+
+/**
+ * @brief   GPIOR interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOR_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOR_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOS interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOS_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOS_IRQ_PRIORITY         3
+#endif
+
+/**
+ * @brief   GPIOT interrupt priority level setting.
+ */
+#if !defined(TIVA_EXT_GPIOT_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_EXT_GPIOT_IRQ_PRIORITY         3
+#endif
+/** @} */
+
 /*===========================================================================*/
 /* Derived constants and error checks.                                       */
 /*===========================================================================*/
@@ -360,6 +600,166 @@ typedef uint32_t ioportid_t;
 #define GPIOS                               GPIO_PORTS_BASE
 #define GPIOT                               GPIO_PORTT_BASE
 
+#if TIVA_HAS_GPIOA &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOA_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOA"
+#endif
+
+#if TIVA_HAS_GPIOB &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOB_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOB"
+#endif
+
+#if TIVA_HAS_GPIOC &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOC_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOC"
+#endif
+
+#if TIVA_HAS_GPIOD &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOD_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOD"
+#endif
+
+#if TIVA_HAS_GPIOE &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOE_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOE"
+#endif
+
+#if TIVA_HAS_GPIOF &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOF_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOF"
+#endif
+
+#if TIVA_HAS_GPIOG &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOG_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOG"
+#endif
+
+#if TIVA_HAS_GPIOH &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOH_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOH"
+#endif
+
+#if TIVA_HAS_GPIOJ &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOJ_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOJ"
+#endif
+
+#if TIVA_HAS_GPIOK &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOK_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOK"
+#endif
+
+#if TIVA_HAS_GPIOL &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOL_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOL"
+#endif
+
+#if TIVA_HAS_GPIOM &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOM_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOM"
+#endif
+
+#if TIVA_HAS_GPION &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPION_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPION"
+#endif
+
+#if TIVA_HAS_GPIOP0 &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP0_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOP0"
+#endif
+
+#if TIVA_HAS_GPIOP1 &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOP1"
+#endif
+
+#if TIVA_HAS_GPIOP2 &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOP2"
+#endif
+
+#if TIVA_HAS_GPIOP3 &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP3_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOP3"
+#endif
+
+#if TIVA_HAS_GPIOP4 &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP4_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOP4"
+#endif
+
+#if TIVA_HAS_GPIOP5 &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP5_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOP5"
+#endif
+
+#if TIVA_HAS_GPIOP6 &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP6_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOP6"
+#endif
+
+#if TIVA_HAS_GPIOP7 &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP7_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOP7"
+#endif
+
+#if TIVA_HAS_GPIOQ0 &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ0_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOQ0"
+#endif
+
+#if TIVA_HAS_GPIOQ1 &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOQ1"
+#endif
+
+#if TIVA_HAS_GPIOQ2 &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ2_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOQ2"
+#endif
+
+#if TIVA_HAS_GPIOQ3 &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ3_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOQ3"
+#endif
+
+#if TIVA_HAS_GPIOQ4 &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ4_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOQ4"
+#endif
+
+#if TIVA_HAS_GPIOQ5 &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ5_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOQ5"
+#endif
+
+#if TIVA_HAS_GPIOQ6 &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ6_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOQ6"
+#endif
+
+#if TIVA_HAS_GPIOQ7 &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ7_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOQ7"
+#endif
+
+#if TIVA_HAS_GPIOR &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOR_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOR"
+#endif
+
+#if TIVA_HAS_GPIOS &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOS_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOS"
+#endif
+
+#if TIVA_HAS_GPIOT &&                                                         \
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOT_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to GPIOT"
+#endif
+
 /*===========================================================================*/
 /* I/O Ports Identifiers.                                                    */
 /*===========================================================================*/
@@ -661,12 +1061,59 @@ typedef uint32_t ioportid_t;
 #define pal_lld_clearpad(port, pad) \
   (HWREG((port) + (GPIO_O_DATA + ((1 << (pad)) << 2))) = 0)
 
+/**
+ * @brief   Pad event enable.
+ * @note    Programming an unknown or unsupported mode is silently ignored.
+ *
+ * @param[in] port      port identifier
+ * @param[in] pad       pad number within the port
+ * @param[in] mode      pad event mode
+ *
+ * @notapi
+ */
+#define pal_lld_enablepadevent(port, pad, mode)                             \
+  _pal_lld_enablepadevent(port, pad, mode)
+
+/**
+ * @brief   Pad event disable.
+ * @details This function disables previously programmed event callbacks.
+ *
+ * @param[in] port      port identifier
+ * @param[in] pad       pad number within the port
+ *
+ * @notapi
+ */
+#define pal_lld_disablepadevent(port, pad)                                  \
+  _pal_lld_disablepadevent(port, pad)
+
+/**
+ * @brief   Returns a PAL event structure associated to a pad.
+ *
+ * @param[in] port      port identifier
+ * @param[in] pad       pad number within the port
+ *
+ * @notapi
+ */
+#define pal_lld_get_pad_event(port, pad)                                    \
+  &_pal_events[((((((uint32_t)port - (uint32_t)GPIOA) >> 12) & 0x1FU) * 8) + pad)];
+
+/**
+ * @brief   Returns a PAL event structure associated to a line.
+ *
+ * @param[in] line      line identifier
+ *
+ * @notapi
+ */
+#define pal_lld_get_line_event(line)                                        \
+  &_pal_events[((((((uint32_t)PAL_PORT(line) - (uint32_t)GPIOA) >> 12) & 0x1FU) * 8) + PAL_PAD(line))]
+
 /*===========================================================================*/
 /* External declarations.                                                    */
 /*===========================================================================*/
 
 #if !defined(__DOXYGEN__)
 extern const PALConfig pal_default_config;
+extern palevent_t _pal_events[TIVA_GPIO_PINS];
 #endif
 
 #ifdef __cplusplus
@@ -676,6 +1123,13 @@ extern "C" {
   void _pal_lld_setgroupmode(ioportid_t port,
                              ioportmask_t mask,
                              iomode_t mode);
+#if PAL_USE_CALLBACKS || PAL_USE_WAIT
+  void _pal_lld_enablepadevent(ioportid_t port,
+                               iopadid_t pad,
+                               ioeventmode_t mode);
+  void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad);
+  void pal_lld_disable_irqs(void);
+#endif
 #ifdef __cplusplus
 }
 #endif
-- 
cgit v1.2.3


From 9a21d8e14386755d5e7644a6415b57976db56d5b Mon Sep 17 00:00:00 2001
From: marcoveeneman <marco-veeneman@hotmail.com>
Date: Fri, 2 Mar 2018 18:55:22 +0100
Subject: Removed EXT driver files

---
 os/hal/ports/TIVA/LLD/GPIO/driver.mk     |   4 -
 os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c | 981 -------------------------------
 os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.h | 523 ----------------
 3 files changed, 1508 deletions(-)
 delete mode 100644 os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c
 delete mode 100644 os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.h

(limited to 'os')

diff --git a/os/hal/ports/TIVA/LLD/GPIO/driver.mk b/os/hal/ports/TIVA/LLD/GPIO/driver.mk
index 121ef57..486fe73 100644
--- a/os/hal/ports/TIVA/LLD/GPIO/driver.mk
+++ b/os/hal/ports/TIVA/LLD/GPIO/driver.mk
@@ -2,12 +2,8 @@ ifeq ($(USE_SMART_BUILD),yes)
 ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),)
 PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c
 endif
-ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),)
-PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c
-endif
 else
 PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c
-PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c
 endif
 
 PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPIO
diff --git a/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c b/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c
deleted file mode 100644
index 40f06f9..0000000
--- a/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c
+++ /dev/null
@@ -1,981 +0,0 @@
-/*
-    Copyright (C) 2014..2017 Marco Veeneman
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    GPIO/hal_ext_lld.c
- * @brief   Tiva EXT subsystem low level driver source.
- *
- * @addtogroup EXT
- * @{
- */
-
-#include "hal.h"
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver local definitions.                                                 */
-/*===========================================================================*/
-
-/**
- * @brief   Generic interrupt serving code for multiple pins per interrupt
- *          handler.
- */
-#define ext_lld_serve_port_interrupt(gpio, start)                            \
-  do {                                                                        \
-    uint32_t mis = HWREG(gpio + GPIO_O_MIS);                                                \
-                                                                              \
-    HWREG(gpio + GPIO_O_ICR) = mis;                                                         \
-                                                                              \
-    if (mis & (1 << 0)) {                                                     \
-      EXTD1.config->channels[start + 0].cb(&EXTD1, start + 0);                \
-    }                                                                         \
-    if (mis & (1 << 1)) {                                                     \
-      EXTD1.config->channels[start + 1].cb(&EXTD1, start + 1);                \
-    }                                                                         \
-    if (mis & (1 << 2)) {                                                     \
-      EXTD1.config->channels[start + 2].cb(&EXTD1, start + 2);                \
-    }                                                                         \
-    if (mis & (1 << 3)) {                                                     \
-      EXTD1.config->channels[start + 3].cb(&EXTD1, start + 3);                \
-    }                                                                         \
-    if (mis & (1 << 4)) {                                                     \
-      EXTD1.config->channels[start + 4].cb(&EXTD1, start + 4);                \
-    }                                                                         \
-    if (mis & (1 << 5)) {                                                     \
-      EXTD1.config->channels[start + 5].cb(&EXTD1, start + 5);                \
-    }                                                                         \
-    if (mis & (1 << 6)) {                                                     \
-      EXTD1.config->channels[start + 6].cb(&EXTD1, start + 6);                \
-    }                                                                         \
-    if (mis & (1 << 7)) {                                                     \
-      EXTD1.config->channels[start + 7].cb(&EXTD1, start + 7);                \
-    }                                                                         \
-  } while (0);
-
-/**
- * @brief   Generic interrupt serving code for single pin per interrupt
- *          handler.
- */
-#define ext_lld_serve_pin_interrupt(gpiop, start, pin)                        \
-  do {                                                                        \
-    gpiop->ICR = (1 << pin);                                                  \
-    EXTD1.config->channels[start].cb(&EXTD1, start);                          \
-  } while (0);
-
-/*===========================================================================*/
-/* Driver exported variables.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   EXTD1 driver identifier.
- */
-EXTDriver EXTD1;
-
-/*===========================================================================*/
-/* Driver local variables and types.                                         */
-/*===========================================================================*/
-
-const ioportid_t gpio_table[] =
-{
-#if TIVA_HAS_GPIOA
-  GPIOA,
-#endif
-#if TIVA_HAS_GPIOB
-  GPIOB,
-#endif
-#if TIVA_HAS_GPIOC
-  GPIOC,
-#endif
-#if TIVA_HAS_GPIOD
-  GPIOD,
-#endif
-#if TIVA_HAS_GPIOE
-  GPIOE,
-#endif
-#if TIVA_HAS_GPIOF
-  GPIOF,
-#endif
-#if TIVA_HAS_GPIOG
-  GPIOG,
-#endif
-#if TIVA_HAS_GPIOH
-  GPIOH,
-#endif
-#if TIVA_HAS_GPIOJ
-  GPIOJ,
-#endif
-#if TIVA_HAS_GPIOK
-  GPIOK,
-#endif
-#if TIVA_HAS_GPIOL
-  GPIOL,
-#endif
-#if TIVA_HAS_GPIOM
-  GPIOM,
-#endif
-#if TIVA_HAS_GPION
-  GPION,
-#endif
-#if TIVA_HAS_GPIOP
-  GPIOP,
-#endif
-#if TIVA_HAS_GPIOQ
-  GPIOQ,
-#endif
-#if TIVA_HAS_GPIOR
-  GPIOR,
-#endif
-#if TIVA_HAS_GPIOS
-  GPIOS,
-#endif
-#if TIVA_HAS_GPIOT
-  GPIOT,
-#endif
-};
-
-/*===========================================================================*/
-/* Driver local functions.                                                   */
-/*===========================================================================*/
-
-/**
- * @brief   Enables GPIO IRQ sources.
- *
- * @notapi
- */
-static void ext_lld_irq_enable(void)
-{
-#if TIVA_HAS_GPIOA
-  nvicEnableVector(TIVA_GPIOA_NUMBER, TIVA_EXT_GPIOA_IRQ_PRIORITY);
-#endif
-#if TIVA_HAS_GPIOB
-  nvicEnableVector(TIVA_GPIOB_NUMBER, TIVA_EXT_GPIOB_IRQ_PRIORITY);
-#endif
-#if TIVA_HAS_GPIOC
-  nvicEnableVector(TIVA_GPIOC_NUMBER, TIVA_EXT_GPIOC_IRQ_PRIORITY);
-#endif
-#if TIVA_HAS_GPIOD
-  nvicEnableVector(TIVA_GPIOD_NUMBER, TIVA_EXT_GPIOD_IRQ_PRIORITY);
-#endif
-#if TIVA_HAS_GPIOE
-  nvicEnableVector(TIVA_GPIOE_NUMBER, TIVA_EXT_GPIOE_IRQ_PRIORITY);
-#endif
-#if TIVA_HAS_GPIOF
-  nvicEnableVector(TIVA_GPIOF_NUMBER, TIVA_EXT_GPIOF_IRQ_PRIORITY);
-#endif
-#if TIVA_HAS_GPIOG
-  nvicEnableVector(TIVA_GPIOG_NUMBER, TIVA_EXT_GPIOG_IRQ_PRIORITY);
-#endif
-#if TIVA_HAS_GPIOH
-  nvicEnableVector(TIVA_GPIOH_NUMBER, TIVA_EXT_GPIOH_IRQ_PRIORITY);
-#endif
-#if TIVA_HAS_GPIOJ
-  nvicEnableVector(TIVA_GPIOJ_NUMBER, TIVA_EXT_GPIOJ_IRQ_PRIORITY);
-#endif
-#if TIVA_HAS_GPIOK
-  nvicEnableVector(TIVA_GPIOK_NUMBER, TIVA_EXT_GPIOK_IRQ_PRIORITY);
-#endif
-#if TIVA_HAS_GPIOL
-  nvicEnableVector(TIVA_GPIOL_NUMBER, TIVA_EXT_GPIOL_IRQ_PRIORITY);
-#endif
-#if TIVA_HAS_GPIOM
-  nvicEnableVector(TIVA_GPIOM_NUMBER, TIVA_EXT_GPIOM_IRQ_PRIORITY);
-#endif
-#if TIVA_HAS_GPION
-  nvicEnableVector(TIVA_GPION_NUMBER, TIVA_EXT_GPION_IRQ_PRIORITY);
-#endif
-#if TIVA_HAS_GPIOP
-  nvicEnableVector(TIVA_GPIOP0_NUMBER, TIVA_EXT_GPIOP0_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOP1_NUMBER, TIVA_EXT_GPIOP1_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOP2_NUMBER, TIVA_EXT_GPIOP2_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOP3_NUMBER, TIVA_EXT_GPIOP3_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOP4_NUMBER, TIVA_EXT_GPIOP4_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOP5_NUMBER, TIVA_EXT_GPIOP5_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOP6_NUMBER, TIVA_EXT_GPIOP6_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOP7_NUMBER, TIVA_EXT_GPIOP7_IRQ_PRIORITY);
-#endif
-#if TIVA_HAS_GPIOQ
-  nvicEnableVector(TIVA_GPIOQ0_NUMBER, TIVA_EXT_GPIOQ0_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOQ1_NUMBER, TIVA_EXT_GPIOQ1_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOQ2_NUMBER, TIVA_EXT_GPIOQ2_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOQ3_NUMBER, TIVA_EXT_GPIOQ3_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOQ4_NUMBER, TIVA_EXT_GPIOQ4_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOQ5_NUMBER, TIVA_EXT_GPIOQ5_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOQ6_NUMBER, TIVA_EXT_GPIOQ6_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOQ7_NUMBER, TIVA_EXT_GPIOQ7_IRQ_PRIORITY);
-#endif
-#if TIVA_HAS_GPIOR
-  nvicEnableVector(TIVA_GPIOR_NUMBER, TIVA_EXT_GPIOR_IRQ_PRIORITY);
-#endif
-#if TIVA_HAS_GPIOS
-  nvicEnableVector(TIVA_GPIOS_NUMBER, TIVA_EXT_GPIOS_IRQ_PRIORITY);
-#endif
-#if TIVA_HAS_GPIOT
-  nvicEnableVector(TIVA_GPIOT_NUMBER, TIVA_EXT_GPIOT_IRQ_PRIORITY);
-#endif
-}
-
-/**
- * @brief   Disables GPIO IRQ sources.
- *
- * @notapi
- */
-static void ext_lld_irq_disable(void)
-{
-#if TIVA_HAS_GPIOA
-  nvicDisableVector(TIVA_GPIOA_NUMBER);
-#endif
-#if TIVA_HAS_GPIOB
-  nvicDisableVector(TIVA_GPIOB_NUMBER);
-#endif
-#if TIVA_HAS_GPIOC
-  nvicDisableVector(TIVA_GPIOC_NUMBER);
-#endif
-#if TIVA_HAS_GPIOD
-  nvicDisableVector(TIVA_GPIOD_NUMBER);
-#endif
-#if TIVA_HAS_GPIOE
-  nvicDisableVector(TIVA_GPIOE_NUMBER);
-#endif
-#if TIVA_HAS_GPIOF
-  nvicDisableVector(TIVA_GPIOF_NUMBER);
-#endif
-#if TIVA_HAS_GPIOG
-  nvicDisableVector(TIVA_GPIOG_NUMBER);
-#endif
-#if TIVA_HAS_GPIOH
-  nvicDisableVector(TIVA_GPIOH_NUMBER);
-#endif
-#if TIVA_HAS_GPIOJ
-  nvicDisableVector(TIVA_GPIOJ_NUMBER);
-#endif
-#if TIVA_HAS_GPIOK
-  nvicDisableVector(TIVA_GPIOK_NUMBER);
-#endif
-#if TIVA_HAS_GPIOL
-  nvicDisableVector(TIVA_GPIOL_NUMBER);
-#endif
-#if TIVA_HAS_GPIOM
-  nvicDisableVector(TIVA_GPIOM_NUMBER);
-#endif
-#if TIVA_HAS_GPION
-  nvicDisableVector(TIVA_GPION_NUMBER);
-#endif
-#if TIVA_HAS_GPIOP
-  nvicDisableVector(TIVA_GPIOP0_NUMBER);
-  nvicDisableVector(TIVA_GPIOP1_NUMBER);
-  nvicDisableVector(TIVA_GPIOP2_NUMBER);
-  nvicDisableVector(TIVA_GPIOP3_NUMBER);
-  nvicDisableVector(TIVA_GPIOP4_NUMBER);
-  nvicDisableVector(TIVA_GPIOP5_NUMBER);
-  nvicDisableVector(TIVA_GPIOP6_NUMBER);
-  nvicDisableVector(TIVA_GPIOP7_NUMBER);
-#endif
-#if TIVA_HAS_GPIOQ
-  nvicDisableVector(TIVA_GPIOQ0_NUMBER);
-  nvicDisableVector(TIVA_GPIOQ1_NUMBER);
-  nvicDisableVector(TIVA_GPIOQ2_NUMBER);
-  nvicDisableVector(TIVA_GPIOQ3_NUMBER);
-  nvicDisableVector(TIVA_GPIOQ4_NUMBER);
-  nvicDisableVector(TIVA_GPIOQ5_NUMBER);
-  nvicDisableVector(TIVA_GPIOQ6_NUMBER);
-  nvicDisableVector(TIVA_GPIOQ7_NUMBER);
-#endif
-#if TIVA_HAS_GPIOR
-  nvicDisableVector(TIVA_GPIOR_NUMBER);
-#endif
-#if TIVA_HAS_GPIOS
-  nvicDisableVector(TIVA_GPIOS_NUMBER);
-#endif
-#if TIVA_HAS_GPIOT
-  nvicDisableVector(TIVA_GPIOT_NUMBER);
-#endif
-}
-
-/*===========================================================================*/
-/* Driver interrupt handlers.                                                */
-/*===========================================================================*/
-
-#if TIVA_HAS_GPIOA || defined(__DOXYGEN__)
-/**
- * @brief   GPIOA interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOA_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_port_interrupt(GPIOA, 0);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if TIVA_HAS_GPIOB || defined(__DOXYGEN__)
-/**
- * @brief   GPIOB interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOB_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_port_interrupt(GPIOB, 8);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if TIVA_HAS_GPIOC || defined(__DOXYGEN__)
-/**
- * @brief   GPIOC interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOC_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_port_interrupt(GPIOC, 16);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if TIVA_HAS_GPIOD || defined(__DOXYGEN__)
-/**
- * @brief   GPIOD interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOD_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_port_interrupt(GPIOD, 24);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if TIVA_HAS_GPIOE || defined(__DOXYGEN__)
-/**
- * @brief   GPIOE interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOE_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_port_interrupt(GPIOE, 32);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if TIVA_HAS_GPIOF || defined(__DOXYGEN__)
-/**
- * @brief   GPIOF interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOF_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_port_interrupt(GPIOF, 40);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if TIVA_HAS_GPIOG || defined(__DOXYGEN__)
-/**
- * @brief   GPIOG interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOG_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_port_interrupt(&GPIOG, 48);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if TIVA_HAS_GPIOH || defined(__DOXYGEN__)
-/**
- * @brief   GPIOH interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOH_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_port_interrupt(&GPIOH, 56);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__)
-/**
- * @brief   GPIOJ interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOJ_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_port_interrupt(&GPIOJ, 64);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if TIVA_HAS_GPIOK || defined(__DOXYGEN__)
-/**
- * @brief   GPIOK interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOK_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_port_interrupt(&GPIOK, 72);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if TIVA_HAS_GPIOL || defined(__DOXYGEN__)
-/**
- * @brief   GPIOL interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOL_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_port_interrupt(&GPIOL, 80);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if TIVA_HAS_GPIOM || defined(__DOXYGEN__)
-/**
- * @brief   GPIOM interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOM_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_port_interrupt(&GPIOM, 88);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if TIVA_HAS_GPION || defined(__DOXYGEN__)
-/**
- * @brief   GPION interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPION_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_port_interrupt(&GPION, 96);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if TIVA_HAS_GPIOP || defined(__DOXYGEN__)
-/**
- * @brief   GPIOP0 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOP0_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_pin_interrupt(&GPIOP, 104, 0);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   GPIOP1 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOP1_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_pin_interrupt(&GPIOP, 105, 1);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   GPIOP2 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOP2_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_pin_interrupt(&GPIOP, 106, 2);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   GPIOP3 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOP3_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_pin_interrupt(&GPIOP, 107, 3);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   GPIOP4 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOP4_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_pin_interrupt(&GPIOP, 108, 4);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   GPIOP5 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOP5_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_pin_interrupt(&GPIOP, 109, 5);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   GPIOP6 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOP6_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_pin_interrupt(&GPIOP, 110, 6);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   GPIOP7 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOP7_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_pin_interrupt(&GPIOP, 111, 7);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__)
-/**
- * @brief   GPIOQ0 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOQ0_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_pin_interrupt(&GPIOQ, 112, 0);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   GPIOQ1 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOQ1_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_pin_interrupt(&GPIOQ, 113, 1);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   GPIOQ2 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOQ2_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_pin_interrupt(&GPIOQ, 114, 2);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   GPIOQ3 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOQ3_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_pin_interrupt(&GPIOQ, 115, 3);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   GPIOQ4 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOQ4_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_pin_interrupt(&GPIOQ, 116, 4);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   GPIOQ5 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOQ5_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_pin_interrupt(&GPIOQ, 117, 5);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   GPIOQ6 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOQ6_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_pin_interrupt(&GPIOQ, 118, 6);
-
-  OSAL_IRQ_EPILOGUE();
-}
-
-/**
- * @brief   GPIOQ7 interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOQ7_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_pin_interrupt(&GPIOQ, 119, 7);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if TIVA_HAS_GPIOR || defined(__DOXYGEN__)
-/**
- * @brief   GPIOR interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOR_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_port_interrupt(&GPIOR, 120);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if TIVA_HAS_GPIOS || defined(__DOXYGEN__)
-/**
- * @brief   GPIOS interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOS_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_port_interrupt(&GPIOS, 128);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-#if TIVA_HAS_GPIOT || defined(__DOXYGEN__)
-/**
- * @brief   GPIOT interrupt handler.
- *
- * @isr
- */
-OSAL_IRQ_HANDLER(TIVA_GPIOT_HANDLER)
-{
-  OSAL_IRQ_PROLOGUE();
-
-  ext_lld_serve_port_interrupt(&GPIOT, 132);
-
-  OSAL_IRQ_EPILOGUE();
-}
-#endif
-
-/*===========================================================================*/
-/* Driver exported functions.                                                */
-/*===========================================================================*/
-
-/**
- * @brief   Low level EXT driver initialization.
- *
- * @notapi
- */
-void ext_lld_init(void)
-{
-  extObjectInit(&EXTD1);
-}
-
-/**
- * @brief   Configures and activates the EXT peripheral.
- *
- * @param[in] extp      pointer to the @p EXTDriver object
- *
- * @notapi
- */
-void ext_lld_start(EXTDriver *extp)
-{
-  uint8_t i;
-
-  if (extp->state == EXT_STOP) {
-    ext_lld_irq_enable();
-  }
-
-  /* Configuration of automatic channels.*/
-  for (i = 0; i < EXT_MAX_CHANNELS; i++) {
-    if (extp->config->channels[i].mode & EXT_CH_MODE_AUTOSTART) {
-      ext_lld_channel_enable(extp, i);
-    }
-    else {
-      ext_lld_channel_disable(extp, i);
-    }
-  }
-}
-
-/**
- * @brief   Deactivates the EXT peripheral.
- *
- * @param[in] extp      pointer to the @p EXTDriver object
- *
- * @notapi
- */
-void ext_lld_stop(EXTDriver *extp)
-{
-  if (extp->state == EXT_ACTIVE) {
-    ext_lld_irq_disable();
-  }
-
-#if TIVA_HAS_GPIOA
-  HWREG(GPIOA + GPIO_O_IM) = 0;
-#endif
-#if TIVA_HAS_GPIOB
-  HWREG(GPIOB + GPIO_O_IM) = 0;
-#endif
-#if TIVA_HAS_GPIOC
-  HWREG(GPIOC + GPIO_O_IM) = 0;
-#endif
-#if TIVA_HAS_GPIOD
-  HWREG(GPIOD + GPIO_O_IM) = 0;
-#endif
-#if TIVA_HAS_GPIOE
-  HWREG(GPIOE + GPIO_O_IM) = 0;
-#endif
-#if TIVA_HAS_GPIOF
-  HWREG(GPIOF + GPIO_O_IM) = 0;
-#endif
-#if TIVA_HAS_GPIOG
-  HWREG(GPIOG + GPIO_O_IM) = 0;
-#endif
-#if TIVA_HAS_GPIOH
-  HWREG(GPIOH + GPIO_O_IM) = 0;
-#endif
-#if TIVA_HAS_GPIOJ
-  HWREG(GPIOJ + GPIO_O_IM) = 0;
-#endif
-#if TIVA_HAS_GPIOK
-  HWREG(GPIOK + GPIO_O_IM) = 0;
-#endif
-#if TIVA_HAS_GPIOL
-  HWREG(GPIOL + GPIO_O_IM) = 0;
-#endif
-#if TIVA_HAS_GPIOM
-  HWREG(GPIOM + GPIO_O_IM) = 0;
-#endif
-#if TIVA_HAS_GPION
-  HWREG(GPION + GPIO_O_IM) = 0;
-#endif
-#if TIVA_HAS_GPIOP
-  HWREG(GPIOP + GPIO_O_IM) = 0;
-#endif
-#if TIVA_HAS_GPIOQ
-  HWREG(GPIOQ + GPIO_O_IM) = 0;
-#endif
-#if TIVA_HAS_GPIOR
-  HWREG(GPIOR + GPIO_O_IM) = 0;
-#endif
-#if TIVA_HAS_GPIOS
-  HWREG(GPIOS + GPIO_O_IM) = 0;
-#endif
-#if TIVA_HAS_GPIOT
-  HWREG(GPIOT + GPIO_O_IM) = 0;
-#endif
-}
-
-/**
- * @brief   Enables an EXT channel.
- *
- * @param[in] extp      pointer to the @p EXTDriver object
- * @param[in] channel   channel to be enabled
- *
- * @notapi
- */
-void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel)
-{
-  uint32_t gpio;
-  uint8_t pin;
-  uint32_t im;
-
-  pin = channel & 0x07;
-  gpio = gpio_table[channel >> 3];
-
-  /* Disable interrupts */
-  im = HWREG(gpio + GPIO_O_IM);
-  HWREG(gpio + GPIO_O_IM) = 0;
-
-  /* Configure pin to be edge-sensitive.*/
-  HWREG(gpio + GPIO_O_IS) &= ~(1 << pin);
-
-  /* Programming edge registers.*/
-  if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) ==
-      EXT_CH_MODE_BOTH_EDGES) {
-    HWREG(gpio + GPIO_O_IBE) |= (1 << pin);
-  }
-  else if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) ==
-      EXT_CH_MODE_FALLING_EDGE) {
-    HWREG(gpio + GPIO_O_IBE) &= ~(1 << pin);
-    HWREG(gpio + GPIO_O_IEV) &= ~(1 << pin);
-  }
-  else if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) ==
-      EXT_CH_MODE_RISING_EDGE) {
-    HWREG(gpio + GPIO_O_IBE) &= ~(1 << pin);
-    HWREG(gpio + GPIO_O_IEV) |= (1 << pin);
-  }
-
-  /* Programming interrupt and event registers.*/
-  if ((extp->config->channels[channel].cb != NULL) &&
-      ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) !=
-          EXT_CH_MODE_DISABLED)) {
-    im |= (1 << pin);
-  }
-  else {
-    im &= ~(1 << pin);
-  }
-
-  /* Restore interrupts */
-  HWREG(gpio + GPIO_O_IM) = im;
-}
-
-/**
- * @brief   Disables an EXT channel.
- *
- * @param[in] extp      pointer to the @p EXTDriver object
- * @param[in] channel   channel to be disabled
- *
- * @notapi
- */
-void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel)
-{
-  (void)extp;
-  uint32_t gpio;
-  uint8_t pin;
-
-  pin = channel & 0x07;
-  gpio = gpio_table[channel >> 3];
-
-  HWREG(gpio + GPIO_O_IM) &= ~(1 << pin);
-}
-
-#endif /* HAL_USE_EXT */
-
-/** @} */
diff --git a/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.h b/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.h
deleted file mode 100644
index 731f455..0000000
--- a/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.h
+++ /dev/null
@@ -1,523 +0,0 @@
-/*
-    Copyright (C) 2014..2017 Marco Veeneman
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-/**
- * @file    GPIO/hal_ext_lld.h
- * @brief   Tiva EXT subsystem low level driver header.
- *
- * @addtogroup EXT
- * @{
- */
-
-#ifndef HAL_EXT_LLD_H
-#define HAL_EXT_LLD_H
-
-#if HAL_USE_EXT || defined(__DOXYGEN__)
-
-/*===========================================================================*/
-/* Driver constants.                                                         */
-/*===========================================================================*/
-
-/**
- * @brief   Number of EXT per port.
- */
-#define EXT_MAX_CHANNELS    TIVA_GPIO_PINS
-
-/*===========================================================================*/
-/* Driver pre-compile time settings.                                         */
-/*===========================================================================*/
-
-/**
- * @name    Configuration options
- * @{
- */
-/**
- * @brief   GPIOA interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOA_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOA_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   GPIOB interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOB_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOB_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   GPIOC interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOC_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOC_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   GPIOD interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOD_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOD_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   GPIOE interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOE_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOE_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   GPIOF interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOF_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOF_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   GPIOG interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOG_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOG_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   GPIOH interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOH_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOH_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   GPIOJ interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOJ_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOJ_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   GPIOK interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOK_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOK_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   GPIOL interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOL_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOL_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   GPIOM interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOM_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOM_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   GPION interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPION_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPION_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   GPIOP0 interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOP0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOP0_IRQ_PRIORITY        3
-#endif
-
-/**
- * @brief   GPIOP1 interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOP1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOP1_IRQ_PRIORITY        3
-#endif
-
-/**
- * @brief   GPIOP2 interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOP2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOP2_IRQ_PRIORITY        3
-#endif
-
-/**
- * @brief   GPIOP3 interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOP3_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOP3_IRQ_PRIORITY        3
-#endif
-
-/**
- * @brief   GPIOP4 interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOP4_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOP4_IRQ_PRIORITY        3
-#endif
-
-/**
- * @brief   GPIOP5 interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOP5_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOP5_IRQ_PRIORITY        3
-#endif
-
-/**
- * @brief   GPIOP6 interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOP6_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOP6_IRQ_PRIORITY        3
-#endif
-
-/**
- * @brief   GPIOP7 interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOP7_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOP7_IRQ_PRIORITY        3
-#endif
-/** @} */
-
-/**
- * @brief   GPIOQ0 interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOQ0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOQ0_IRQ_PRIORITY        3
-#endif
-
-/**
- * @brief   GPIOQ1 interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOQ1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOQ1_IRQ_PRIORITY        3
-#endif
-
-/**
- * @brief   GPIOQ2 interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOQ2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOQ2_IRQ_PRIORITY        3
-#endif
-
-/**
- * @brief   GPIOQ3 interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOQ3_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOQ3_IRQ_PRIORITY        3
-#endif
-
-/**
- * @brief   GPIOQ4 interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOQ4_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOQ4_IRQ_PRIORITY        3
-#endif
-
-/**
- * @brief   GPIOQ5 interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOQ5_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOQ5_IRQ_PRIORITY        3
-#endif
-
-/**
- * @brief   GPIOQ6 interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOQ6_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOQ6_IRQ_PRIORITY        3
-#endif
-
-/**
- * @brief   GPIOQ7 interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOQ7_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOQ7_IRQ_PRIORITY        3
-#endif
-
-/**
- * @brief   GPIOR interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOR_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOR_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   GPIOS interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOS_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOS_IRQ_PRIORITY         3
-#endif
-
-/**
- * @brief   GPIOT interrupt priority level setting.
- */
-#if !defined(TIVA_EXT_GPIOT_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOT_IRQ_PRIORITY         3
-#endif
-/** @} */
-
-/*===========================================================================*/
-/* Derived constants and error checks.                                       */
-/*===========================================================================*/
-
-#if TIVA_HAS_GPIOA &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOA_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOA"
-#endif
-
-#if TIVA_HAS_GPIOB &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOB_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOB"
-#endif
-
-#if TIVA_HAS_GPIOC &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOC_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOC"
-#endif
-
-#if TIVA_HAS_GPIOD &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOD_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOD"
-#endif
-
-#if TIVA_HAS_GPIOE &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOE_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOE"
-#endif
-
-#if TIVA_HAS_GPIOF &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOF_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOF"
-#endif
-
-#if TIVA_HAS_GPIOG &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOG_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOG"
-#endif
-
-#if TIVA_HAS_GPIOH &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOH_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOH"
-#endif
-
-#if TIVA_HAS_GPIOJ &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOJ_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOJ"
-#endif
-
-#if TIVA_HAS_GPIOK &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOK_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOK"
-#endif
-
-#if TIVA_HAS_GPIOL &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOL_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOL"
-#endif
-
-#if TIVA_HAS_GPIOM &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOM_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOM"
-#endif
-
-#if TIVA_HAS_GPION &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPION_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPION"
-#endif
-
-#if TIVA_HAS_GPIOP0 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP0_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOP0"
-#endif
-
-#if TIVA_HAS_GPIOP1 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP1_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOP1"
-#endif
-
-#if TIVA_HAS_GPIOP2 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP2_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOP2"
-#endif
-
-#if TIVA_HAS_GPIOP3 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP3_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOP3"
-#endif
-
-#if TIVA_HAS_GPIOP4 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP4_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOP4"
-#endif
-
-#if TIVA_HAS_GPIOP5 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP5_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOP5"
-#endif
-
-#if TIVA_HAS_GPIOP6 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP6_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOP6"
-#endif
-
-#if TIVA_HAS_GPIOP7 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP7_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOP7"
-#endif
-
-#if TIVA_HAS_GPIOQ0 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ0_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOQ0"
-#endif
-
-#if TIVA_HAS_GPIOQ1 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ1_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOQ1"
-#endif
-
-#if TIVA_HAS_GPIOQ2 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ2_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOQ2"
-#endif
-
-#if TIVA_HAS_GPIOQ3 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ3_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOQ3"
-#endif
-
-#if TIVA_HAS_GPIOQ4 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ4_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOQ4"
-#endif
-
-#if TIVA_HAS_GPIOQ5 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ5_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOQ5"
-#endif
-
-#if TIVA_HAS_GPIOQ6 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ6_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOQ6"
-#endif
-
-#if TIVA_HAS_GPIOQ7 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ7_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOQ7"
-#endif
-
-#if TIVA_HAS_GPIOR &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOR_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOR"
-#endif
-
-#if TIVA_HAS_GPIOS &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOS_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOS"
-#endif
-
-#if TIVA_HAS_GPIOT &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOT_IRQ_PRIORITY)
-#error "Invalid IRQ priority assigned to GPIOT"
-#endif
-
-/*===========================================================================*/
-/* Driver data structures and types.                                         */
-/*===========================================================================*/
-
-/**
- * @brief   EXT channel identifier.
- */
-typedef uint32_t expchannel_t;
-
-/**
- * @brief   Type of an EXT generic notification callback.
- *
- * @param[in] extp      pointer to the @p EXPDriver object triggering the
- *                      callback
- */
-typedef void (*extcallback_t)(EXTDriver *extp, expchannel_t channel);
-
-/**
- * @brief   Channel configuration structure.
- */
-typedef struct {
-  /**
-   * @brief Channel mode.
-   */
-  uint32_t              mode;
-  /**
-   * @brief Channel callback.
-   */
-  extcallback_t         cb;
-} EXTChannelConfig;
-
-/**
- * @brief   Driver configuration structure.
- * @note    It could be empty on some architectures.
- */
-typedef struct {
-  /**
-   * @brief Channel configurations.
-   */
-  EXTChannelConfig      channels[EXT_MAX_CHANNELS];
-  /* End of the mandatory fields.*/
-} EXTConfig;
-
-/**
- * @brief   Structure representing an EXT driver.
- */
-struct EXTDriver {
-  /**
-   * @brief Driver state.
-   */
-  extstate_t                state;
-  /**
-   * @brief Current configuration data.
-   */
-  const EXTConfig           *config;
-  /* End of the mandatory fields.*/
-};
-
-/*===========================================================================*/
-/* Driver macros.                                                            */
-/*===========================================================================*/
-
-/*===========================================================================*/
-/* External declarations.                                                    */
-/*===========================================================================*/
-
-#if !defined(__DOXYGEN__)
-extern EXTDriver EXTD1;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void ext_lld_init(void);
-  void ext_lld_start(EXTDriver *extp);
-  void ext_lld_stop(EXTDriver *extp);
-  void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel);
-  void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel);
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* HAL_USE_EXT */
-
-#endif /* HAL_EXT_LLD_H */
-
-/** @} */
-- 
cgit v1.2.3


From 9ef6a860604e9844b25f6199aff1d8c949fa4c1f Mon Sep 17 00:00:00 2001
From: marcoveeneman <marco-veeneman@hotmail.com>
Date: Wed, 7 Mar 2018 20:38:10 +0100
Subject: Renamed GPIO IRQ priority definitions for the PAL driver

---
 os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c |  64 +++++------
 os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h | 192 +++++++++++++++----------------
 2 files changed, 128 insertions(+), 128 deletions(-)

(limited to 'os')

diff --git a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c
index a2b297b..7a222e4 100644
--- a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c
+++ b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c
@@ -213,72 +213,72 @@ static void gpio_unlock(ioportid_t port, ioportmask_t mask)
 static void gpio_irq_enable(void)
 {
 #if TIVA_HAS_GPIOA
-  nvicEnableVector(TIVA_GPIOA_NUMBER, TIVA_EXT_GPIOA_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOA_NUMBER, TIVA_PAL_GPIOA_IRQ_PRIORITY);
 #endif
 #if TIVA_HAS_GPIOB
-  nvicEnableVector(TIVA_GPIOB_NUMBER, TIVA_EXT_GPIOB_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOB_NUMBER, TIVA_PAL_GPIOB_IRQ_PRIORITY);
 #endif
 #if TIVA_HAS_GPIOC
-  nvicEnableVector(TIVA_GPIOC_NUMBER, TIVA_EXT_GPIOC_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOC_NUMBER, TIVA_PAL_GPIOC_IRQ_PRIORITY);
 #endif
 #if TIVA_HAS_GPIOD
-  nvicEnableVector(TIVA_GPIOD_NUMBER, TIVA_EXT_GPIOD_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOD_NUMBER, TIVA_PAL_GPIOD_IRQ_PRIORITY);
 #endif
 #if TIVA_HAS_GPIOE
-  nvicEnableVector(TIVA_GPIOE_NUMBER, TIVA_EXT_GPIOE_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOE_NUMBER, TIVA_PAL_GPIOE_IRQ_PRIORITY);
 #endif
 #if TIVA_HAS_GPIOF
-  nvicEnableVector(TIVA_GPIOF_NUMBER, TIVA_EXT_GPIOF_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOF_NUMBER, TIVA_PAL_GPIOF_IRQ_PRIORITY);
 #endif
 #if TIVA_HAS_GPIOG
-  nvicEnableVector(TIVA_GPIOG_NUMBER, TIVA_EXT_GPIOG_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOG_NUMBER, TIVA_PAL_GPIOG_IRQ_PRIORITY);
 #endif
 #if TIVA_HAS_GPIOH
-  nvicEnableVector(TIVA_GPIOH_NUMBER, TIVA_EXT_GPIOH_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOH_NUMBER, TIVA_PAL_GPIOH_IRQ_PRIORITY);
 #endif
 #if TIVA_HAS_GPIOJ
-  nvicEnableVector(TIVA_GPIOJ_NUMBER, TIVA_EXT_GPIOJ_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOJ_NUMBER, TIVA_PAL_GPIOJ_IRQ_PRIORITY);
 #endif
 #if TIVA_HAS_GPIOK
-  nvicEnableVector(TIVA_GPIOK_NUMBER, TIVA_EXT_GPIOK_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOK_NUMBER, TIVA_PAL_GPIOK_IRQ_PRIORITY);
 #endif
 #if TIVA_HAS_GPIOL
-  nvicEnableVector(TIVA_GPIOL_NUMBER, TIVA_EXT_GPIOL_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOL_NUMBER, TIVA_PAL_GPIOL_IRQ_PRIORITY);
 #endif
 #if TIVA_HAS_GPIOM
-  nvicEnableVector(TIVA_GPIOM_NUMBER, TIVA_EXT_GPIOM_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOM_NUMBER, TIVA_PAL_GPIOM_IRQ_PRIORITY);
 #endif
 #if TIVA_HAS_GPION
-  nvicEnableVector(TIVA_GPION_NUMBER, TIVA_EXT_GPION_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPION_NUMBER, TIVA_PAL_GPION_IRQ_PRIORITY);
 #endif
 #if TIVA_HAS_GPIOP
-  nvicEnableVector(TIVA_GPIOP0_NUMBER, TIVA_EXT_GPIOP0_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOP1_NUMBER, TIVA_EXT_GPIOP1_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOP2_NUMBER, TIVA_EXT_GPIOP2_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOP3_NUMBER, TIVA_EXT_GPIOP3_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOP4_NUMBER, TIVA_EXT_GPIOP4_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOP5_NUMBER, TIVA_EXT_GPIOP5_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOP6_NUMBER, TIVA_EXT_GPIOP6_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOP7_NUMBER, TIVA_EXT_GPIOP7_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOP0_NUMBER, TIVA_PAL_GPIOP0_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOP1_NUMBER, TIVA_PAL_GPIOP1_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOP2_NUMBER, TIVA_PAL_GPIOP2_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOP3_NUMBER, TIVA_PAL_GPIOP3_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOP4_NUMBER, TIVA_PAL_GPIOP4_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOP5_NUMBER, TIVA_PAL_GPIOP5_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOP6_NUMBER, TIVA_PAL_GPIOP6_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOP7_NUMBER, TIVA_PAL_GPIOP7_IRQ_PRIORITY);
 #endif
 #if TIVA_HAS_GPIOQ
-  nvicEnableVector(TIVA_GPIOQ0_NUMBER, TIVA_EXT_GPIOQ0_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOQ1_NUMBER, TIVA_EXT_GPIOQ1_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOQ2_NUMBER, TIVA_EXT_GPIOQ2_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOQ3_NUMBER, TIVA_EXT_GPIOQ3_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOQ4_NUMBER, TIVA_EXT_GPIOQ4_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOQ5_NUMBER, TIVA_EXT_GPIOQ5_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOQ6_NUMBER, TIVA_EXT_GPIOQ6_IRQ_PRIORITY);
-  nvicEnableVector(TIVA_GPIOQ7_NUMBER, TIVA_EXT_GPIOQ7_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOQ0_NUMBER, TIVA_PAL_GPIOQ0_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOQ1_NUMBER, TIVA_PAL_GPIOQ1_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOQ2_NUMBER, TIVA_PAL_GPIOQ2_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOQ3_NUMBER, TIVA_PAL_GPIOQ3_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOQ4_NUMBER, TIVA_PAL_GPIOQ4_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOQ5_NUMBER, TIVA_PAL_GPIOQ5_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOQ6_NUMBER, TIVA_PAL_GPIOQ6_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOQ7_NUMBER, TIVA_PAL_GPIOQ7_IRQ_PRIORITY);
 #endif
 #if TIVA_HAS_GPIOR
-  nvicEnableVector(TIVA_GPIOR_NUMBER, TIVA_EXT_GPIOR_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOR_NUMBER, TIVA_PAL_GPIOR_IRQ_PRIORITY);
 #endif
 #if TIVA_HAS_GPIOS
-  nvicEnableVector(TIVA_GPIOS_NUMBER, TIVA_EXT_GPIOS_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOS_NUMBER, TIVA_PAL_GPIOS_IRQ_PRIORITY);
 #endif
 #if TIVA_HAS_GPIOT
-  nvicEnableVector(TIVA_GPIOT_NUMBER, TIVA_EXT_GPIOT_IRQ_PRIORITY);
+  nvicEnableVector(TIVA_GPIOT_NUMBER, TIVA_PAL_GPIOT_IRQ_PRIORITY);
 #endif
 }
 #endif
diff --git a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h
index 34577ee..993d5c3 100644
--- a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h
+++ b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h
@@ -354,226 +354,226 @@ typedef uint32_t iopadid_t;
 /**
  * @brief   GPIOA interrupt priority level setting.
  */
-#if !defined(TIVA_EXT_GPIOA_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOA_IRQ_PRIORITY         3
+#if !defined(TIVA_PAL_GPIOA_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOA_IRQ_PRIORITY         3
 #endif
 
 /**
  * @brief   GPIOB interrupt priority level setting.
  */
-#if !defined(TIVA_EXT_GPIOB_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOB_IRQ_PRIORITY         3
+#if !defined(TIVA_PAL_GPIOB_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOB_IRQ_PRIORITY         3
 #endif
 
 /**
  * @brief   GPIOC interrupt priority level setting.
  */
-#if !defined(TIVA_EXT_GPIOC_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOC_IRQ_PRIORITY         3
+#if !defined(TIVA_PAL_GPIOC_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOC_IRQ_PRIORITY         3
 #endif
 
 /**
  * @brief   GPIOD interrupt priority level setting.
  */
-#if !defined(TIVA_EXT_GPIOD_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOD_IRQ_PRIORITY         3
+#if !defined(TIVA_PAL_GPIOD_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOD_IRQ_PRIORITY         3
 #endif
 
 /**
  * @brief   GPIOE interrupt priority level setting.
  */
-#if !defined(TIVA_EXT_GPIOE_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOE_IRQ_PRIORITY         3
+#if !defined(TIVA_PAL_GPIOE_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOE_IRQ_PRIORITY         3
 #endif
 
 /**
  * @brief   GPIOF interrupt priority level setting.
  */
-#if !defined(TIVA_EXT_GPIOF_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOF_IRQ_PRIORITY         3
+#if !defined(TIVA_PAL_GPIOF_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOF_IRQ_PRIORITY         3
 #endif
 
 /**
  * @brief   GPIOG interrupt priority level setting.
  */
-#if !defined(TIVA_EXT_GPIOG_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOG_IRQ_PRIORITY         3
+#if !defined(TIVA_PAL_GPIOG_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOG_IRQ_PRIORITY         3
 #endif
 
 /**
  * @brief   GPIOH interrupt priority level setting.
  */
-#if !defined(TIVA_EXT_GPIOH_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOH_IRQ_PRIORITY         3
+#if !defined(TIVA_PAL_GPIOH_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOH_IRQ_PRIORITY         3
 #endif
 
 /**
  * @brief   GPIOJ interrupt priority level setting.
  */
-#if !defined(TIVA_EXT_GPIOJ_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOJ_IRQ_PRIORITY         3
+#if !defined(TIVA_PAL_GPIOJ_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOJ_IRQ_PRIORITY         3
 #endif
 
 /**
  * @brief   GPIOK interrupt priority level setting.
  */
-#if !defined(TIVA_EXT_GPIOK_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOK_IRQ_PRIORITY         3
+#if !defined(TIVA_PAL_GPIOK_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOK_IRQ_PRIORITY         3
 #endif
 
 /**
  * @brief   GPIOL interrupt priority level setting.
  */
-#if !defined(TIVA_EXT_GPIOL_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOL_IRQ_PRIORITY         3
+#if !defined(TIVA_PAL_GPIOL_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOL_IRQ_PRIORITY         3
 #endif
 
 /**
  * @brief   GPIOM interrupt priority level setting.
  */
-#if !defined(TIVA_EXT_GPIOM_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOM_IRQ_PRIORITY         3
+#if !defined(TIVA_PAL_GPIOM_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOM_IRQ_PRIORITY         3
 #endif
 
 /**
  * @brief   GPION interrupt priority level setting.
  */
-#if !defined(TIVA_EXT_GPION_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPION_IRQ_PRIORITY         3
+#if !defined(TIVA_PAL_GPION_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPION_IRQ_PRIORITY         3
 #endif
 
 /**
  * @brief   GPIOP0 interrupt priority level setting.
  */
-#if !defined(TIVA_EXT_GPIOP0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOP0_IRQ_PRIORITY        3
+#if !defined(TIVA_PAL_GPIOP0_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOP0_IRQ_PRIORITY        3
 #endif
 
 /**
  * @brief   GPIOP1 interrupt priority level setting.
  */
-#if !defined(TIVA_EXT_GPIOP1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOP1_IRQ_PRIORITY        3
+#if !defined(TIVA_PAL_GPIOP1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOP1_IRQ_PRIORITY        3
 #endif
 
 /**
  * @brief   GPIOP2 interrupt priority level setting.
  */
-#if !defined(TIVA_EXT_GPIOP2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOP2_IRQ_PRIORITY        3
+#if !defined(TIVA_PAL_GPIOP2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOP2_IRQ_PRIORITY        3
 #endif
 
 /**
  * @brief   GPIOP3 interrupt priority level setting.
  */
-#if !defined(TIVA_EXT_GPIOP3_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOP3_IRQ_PRIORITY        3
+#if !defined(TIVA_PAL_GPIOP3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOP3_IRQ_PRIORITY        3
 #endif
 
 /**
  * @brief   GPIOP4 interrupt priority level setting.
  */
-#if !defined(TIVA_EXT_GPIOP4_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOP4_IRQ_PRIORITY        3
+#if !defined(TIVA_PAL_GPIOP4_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOP4_IRQ_PRIORITY        3
 #endif
 
 /**
  * @brief   GPIOP5 interrupt priority level setting.
  */
-#if !defined(TIVA_EXT_GPIOP5_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOP5_IRQ_PRIORITY        3
+#if !defined(TIVA_PAL_GPIOP5_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOP5_IRQ_PRIORITY        3
 #endif
 
 /**
  * @brief   GPIOP6 interrupt priority level setting.
  */
-#if !defined(TIVA_EXT_GPIOP6_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOP6_IRQ_PRIORITY        3
+#if !defined(TIVA_PAL_GPIOP6_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOP6_IRQ_PRIORITY        3
 #endif
 
 /**
  * @brief   GPIOP7 interrupt priority level setting.
  */
-#if !defined(TIVA_EXT_GPIOP7_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOP7_IRQ_PRIORITY        3
+#if !defined(TIVA_PAL_GPIOP7_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOP7_IRQ_PRIORITY        3
 #endif
 /** @} */
 
 /**
  * @brief   GPIOQ0 interrupt priority level setting.
  */
-#if !defined(TIVA_EXT_GPIOQ0_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOQ0_IRQ_PRIORITY        3
+#if !defined(TIVA_PAL_GPIOQ0_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOQ0_IRQ_PRIORITY        3
 #endif
 
 /**
  * @brief   GPIOQ1 interrupt priority level setting.
  */
-#if !defined(TIVA_EXT_GPIOQ1_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOQ1_IRQ_PRIORITY        3
+#if !defined(TIVA_PAL_GPIOQ1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOQ1_IRQ_PRIORITY        3
 #endif
 
 /**
  * @brief   GPIOQ2 interrupt priority level setting.
  */
-#if !defined(TIVA_EXT_GPIOQ2_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOQ2_IRQ_PRIORITY        3
+#if !defined(TIVA_PAL_GPIOQ2_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOQ2_IRQ_PRIORITY        3
 #endif
 
 /**
  * @brief   GPIOQ3 interrupt priority level setting.
  */
-#if !defined(TIVA_EXT_GPIOQ3_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOQ3_IRQ_PRIORITY        3
+#if !defined(TIVA_PAL_GPIOQ3_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOQ3_IRQ_PRIORITY        3
 #endif
 
 /**
  * @brief   GPIOQ4 interrupt priority level setting.
  */
-#if !defined(TIVA_EXT_GPIOQ4_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOQ4_IRQ_PRIORITY        3
+#if !defined(TIVA_PAL_GPIOQ4_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOQ4_IRQ_PRIORITY        3
 #endif
 
 /**
  * @brief   GPIOQ5 interrupt priority level setting.
  */
-#if !defined(TIVA_EXT_GPIOQ5_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOQ5_IRQ_PRIORITY        3
+#if !defined(TIVA_PAL_GPIOQ5_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOQ5_IRQ_PRIORITY        3
 #endif
 
 /**
  * @brief   GPIOQ6 interrupt priority level setting.
  */
-#if !defined(TIVA_EXT_GPIOQ6_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOQ6_IRQ_PRIORITY        3
+#if !defined(TIVA_PAL_GPIOQ6_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOQ6_IRQ_PRIORITY        3
 #endif
 
 /**
  * @brief   GPIOQ7 interrupt priority level setting.
  */
-#if !defined(TIVA_EXT_GPIOQ7_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOQ7_IRQ_PRIORITY        3
+#if !defined(TIVA_PAL_GPIOQ7_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOQ7_IRQ_PRIORITY        3
 #endif
 
 /**
  * @brief   GPIOR interrupt priority level setting.
  */
-#if !defined(TIVA_EXT_GPIOR_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOR_IRQ_PRIORITY         3
+#if !defined(TIVA_PAL_GPIOR_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOR_IRQ_PRIORITY         3
 #endif
 
 /**
  * @brief   GPIOS interrupt priority level setting.
  */
-#if !defined(TIVA_EXT_GPIOS_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOS_IRQ_PRIORITY         3
+#if !defined(TIVA_PAL_GPIOS_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOS_IRQ_PRIORITY         3
 #endif
 
 /**
  * @brief   GPIOT interrupt priority level setting.
  */
-#if !defined(TIVA_EXT_GPIOT_IRQ_PRIORITY) || defined(__DOXYGEN__)
-#define TIVA_EXT_GPIOT_IRQ_PRIORITY         3
+#if !defined(TIVA_PAL_GPIOT_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define TIVA_PAL_GPIOT_IRQ_PRIORITY         3
 #endif
 /** @} */
 
@@ -601,162 +601,162 @@ typedef uint32_t iopadid_t;
 #define GPIOT                               GPIO_PORTT_BASE
 
 #if TIVA_HAS_GPIOA &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOA_IRQ_PRIORITY)
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOA_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOA"
 #endif
 
 #if TIVA_HAS_GPIOB &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOB_IRQ_PRIORITY)
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOB_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOB"
 #endif
 
 #if TIVA_HAS_GPIOC &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOC_IRQ_PRIORITY)
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOC_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOC"
 #endif
 
 #if TIVA_HAS_GPIOD &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOD_IRQ_PRIORITY)
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOD_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOD"
 #endif
 
 #if TIVA_HAS_GPIOE &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOE_IRQ_PRIORITY)
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOE_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOE"
 #endif
 
 #if TIVA_HAS_GPIOF &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOF_IRQ_PRIORITY)
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOF_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOF"
 #endif
 
 #if TIVA_HAS_GPIOG &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOG_IRQ_PRIORITY)
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOG_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOG"
 #endif
 
 #if TIVA_HAS_GPIOH &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOH_IRQ_PRIORITY)
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOH_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOH"
 #endif
 
 #if TIVA_HAS_GPIOJ &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOJ_IRQ_PRIORITY)
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOJ_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOJ"
 #endif
 
 #if TIVA_HAS_GPIOK &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOK_IRQ_PRIORITY)
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOK_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOK"
 #endif
 
 #if TIVA_HAS_GPIOL &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOL_IRQ_PRIORITY)
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOL_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOL"
 #endif
 
 #if TIVA_HAS_GPIOM &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOM_IRQ_PRIORITY)
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOM_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOM"
 #endif
 
 #if TIVA_HAS_GPION &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPION_IRQ_PRIORITY)
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPION_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPION"
 #endif
 
 #if TIVA_HAS_GPIOP0 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP0_IRQ_PRIORITY)
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP0_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOP0"
 #endif
 
 #if TIVA_HAS_GPIOP1 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP1_IRQ_PRIORITY)
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP1_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOP1"
 #endif
 
 #if TIVA_HAS_GPIOP2 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP2_IRQ_PRIORITY)
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP2_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOP2"
 #endif
 
 #if TIVA_HAS_GPIOP3 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP3_IRQ_PRIORITY)
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP3_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOP3"
 #endif
 
 #if TIVA_HAS_GPIOP4 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP4_IRQ_PRIORITY)
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP4_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOP4"
 #endif
 
 #if TIVA_HAS_GPIOP5 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP5_IRQ_PRIORITY)
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP5_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOP5"
 #endif
 
 #if TIVA_HAS_GPIOP6 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP6_IRQ_PRIORITY)
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP6_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOP6"
 #endif
 
 #if TIVA_HAS_GPIOP7 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP7_IRQ_PRIORITY)
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP7_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOP7"
 #endif
 
 #if TIVA_HAS_GPIOQ0 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ0_IRQ_PRIORITY)
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ0_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOQ0"
 #endif
 
 #if TIVA_HAS_GPIOQ1 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ1_IRQ_PRIORITY)
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ1_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOQ1"
 #endif
 
 #if TIVA_HAS_GPIOQ2 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ2_IRQ_PRIORITY)
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ2_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOQ2"
 #endif
 
 #if TIVA_HAS_GPIOQ3 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ3_IRQ_PRIORITY)
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ3_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOQ3"
 #endif
 
 #if TIVA_HAS_GPIOQ4 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ4_IRQ_PRIORITY)
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ4_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOQ4"
 #endif
 
 #if TIVA_HAS_GPIOQ5 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ5_IRQ_PRIORITY)
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ5_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOQ5"
 #endif
 
 #if TIVA_HAS_GPIOQ6 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ6_IRQ_PRIORITY)
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ6_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOQ6"
 #endif
 
 #if TIVA_HAS_GPIOQ7 &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ7_IRQ_PRIORITY)
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ7_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOQ7"
 #endif
 
 #if TIVA_HAS_GPIOR &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOR_IRQ_PRIORITY)
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOR_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOR"
 #endif
 
 #if TIVA_HAS_GPIOS &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOS_IRQ_PRIORITY)
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOS_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOS"
 #endif
 
 #if TIVA_HAS_GPIOT &&                                                         \
-    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOT_IRQ_PRIORITY)
+    !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOT_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOT"
 #endif
 
-- 
cgit v1.2.3


From ae7a4d40b84d8afc999691577210696f16e682f6 Mon Sep 17 00:00:00 2001
From: Fabien Poussin <fabien.poussin@gmail.com>
Date: Thu, 8 Mar 2018 20:14:13 +0100
Subject: Fixes for STM32F0 testhal

---
 os/hal/boards/ST_STM32F0308_DISCOVERY/board.c | 162 ++++++++++++++++++++++++--
 os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c    |   4 +-
 os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c    |  24 ++--
 3 files changed, 167 insertions(+), 23 deletions(-)

(limited to 'os')

diff --git a/os/hal/boards/ST_STM32F0308_DISCOVERY/board.c b/os/hal/boards/ST_STM32F0308_DISCOVERY/board.c
index dc058f6..3412452 100644
--- a/os/hal/boards/ST_STM32F0308_DISCOVERY/board.c
+++ b/os/hal/boards/ST_STM32F0308_DISCOVERY/board.c
@@ -1,5 +1,5 @@
 /*
-    ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
+    ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
 
     Licensed under the Apache License, Version 2.0 (the "License");
     you may not use this file except in compliance with the License.
@@ -14,15 +14,76 @@
     limitations under the License.
 */
 
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+
 #include "hal.h"
+#include "stm32_gpio.h"
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type of STM32 GPIO port setup.
+ */
+typedef struct {
+  uint32_t              moder;
+  uint32_t              otyper;
+  uint32_t              ospeedr;
+  uint32_t              pupdr;
+  uint32_t              odr;
+  uint32_t              afrl;
+  uint32_t              afrh;
+} gpio_setup_t;
+
+/**
+ * @brief   Type of STM32 GPIO initialization data.
+ */
+typedef struct {
+#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
+  gpio_setup_t          PAData;
+#endif
+#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
+  gpio_setup_t          PBData;
+#endif
+#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
+  gpio_setup_t          PCData;
+#endif
+#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
+  gpio_setup_t          PDData;
+#endif
+#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
+  gpio_setup_t          PEData;
+#endif
+#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
+  gpio_setup_t          PFData;
+#endif
+#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
+  gpio_setup_t          PGData;
+#endif
+#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
+  gpio_setup_t          PHData;
+#endif
+#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
+  gpio_setup_t          PIData;
+#endif
+} gpio_config_t;
 
-#if HAL_USE_PAL || defined(__DOXYGEN__)
 /**
- * @brief   PAL setup.
- * @details Digital I/O ports static configuration as defined in @p board.h.
- *          This variable is used by the HAL when initializing the PAL driver.
+ * @brief   STM32 GPIO static initialization data.
  */
-const PALConfig pal_default_config = {
+static const gpio_config_t gpio_default_config = {
 #if STM32_HAS_GPIOA
   {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
    VAL_GPIOA_ODR,   VAL_GPIOA_AFRL,   VAL_GPIOA_AFRH},
@@ -57,21 +118,103 @@ const PALConfig pal_default_config = {
 #endif
 #if STM32_HAS_GPIOI
   {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
-   VAL_GPIOI_ODR,   VAL_GPIOI_AFRL,   VAL_GPIOI_AFRH}
+   VAL_GPIOI_ODR,   VAL_GPIOI_AFRL,   VAL_GPIOI_AFRH},
 #endif
 };
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
+
+  gpiop->OTYPER  = config->otyper;
+  gpiop->OSPEEDR = config->ospeedr;
+  gpiop->PUPDR   = config->pupdr;
+  gpiop->ODR     = config->odr;
+  gpiop->AFRL    = config->afrl;
+  gpiop->AFRH    = config->afrh;
+  gpiop->MODER   = config->moder;
+}
+
+static void stm32_gpio_init(void) {
+
+  /* Enabling GPIO-related clocks, the mask comes from the
+     registry header file.*/
+  rccResetAHB(STM32_GPIO_EN_MASK);
+  rccEnableAHB(STM32_GPIO_EN_MASK, true);
+
+  /* Initializing all the defined GPIO ports.*/
+#if STM32_HAS_GPIOA
+  gpio_init(GPIOA, &gpio_default_config.PAData);
+#endif
+#if STM32_HAS_GPIOB
+  gpio_init(GPIOB, &gpio_default_config.PBData);
 #endif
+#if STM32_HAS_GPIOC
+  gpio_init(GPIOC, &gpio_default_config.PCData);
+#endif
+#if STM32_HAS_GPIOD
+  gpio_init(GPIOD, &gpio_default_config.PDData);
+#endif
+#if STM32_HAS_GPIOE
+  gpio_init(GPIOE, &gpio_default_config.PEData);
+#endif
+#if STM32_HAS_GPIOF
+  gpio_init(GPIOF, &gpio_default_config.PFData);
+#endif
+#if STM32_HAS_GPIOG
+  gpio_init(GPIOG, &gpio_default_config.PGData);
+#endif
+#if STM32_HAS_GPIOH
+  gpio_init(GPIOH, &gpio_default_config.PHData);
+#endif
+#if STM32_HAS_GPIOI
+  gpio_init(GPIOI, &gpio_default_config.PIData);
+#endif
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
 
 /**
  * @brief   Early initialization code.
- * @details This initialization must be performed just after stack setup
- *          and before any other initialization.
+ * @details GPIO ports and system clocks are initialized before everything
+ *          else.
  */
 void __early_init(void) {
 
+  stm32_gpio_init();
   stm32_clock_init();
 }
 
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief   SDC card detection.
+ */
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+
+  (void)sdcp;
+  /* TODO: Fill the implementation.*/
+  return true;
+}
+
+/**
+ * @brief   SDC card write protection detection.
+ */
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+  (void)sdcp;
+  /* TODO: Fill the implementation.*/
+  return false;
+}
+#endif /* HAL_USE_SDC */
+
 #if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
 /**
  * @brief   MMC_SPI card detection.
@@ -99,4 +242,5 @@ bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
  * @todo    Add your board-specific code, if any.
  */
 void boardInit(void) {
+
 }
diff --git a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c
index a2cf026..701b87d 100755
--- a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c
+++ b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c
@@ -155,7 +155,7 @@ void crc_lld_start(CRCDriver *crcp) {
   if (crcp->config == NULL)
     crcp->config = &default_config;
 
-  rccEnableCRC(FALSE);
+  rccEnableCRC();
 
 #if STM32_CRC_PROGRAMMABLE == TRUE
   crcp->crc->INIT = crcp->config->initial_val;
@@ -234,7 +234,7 @@ void crc_lld_stop(CRCDriver *crcp) {
 #else
   (void)crcp;
 #endif
-  rccDisableCRC(FALSE);
+  rccDisableCRC();
 }
 
 /**
diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c
index 6138481..cef015e 100644
--- a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c
+++ b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c
@@ -157,38 +157,38 @@ void qei_lld_start(QEIDriver *qeip) {
     /* Clock activation and timer reset.*/
 #if STM32_QEI_USE_TIM1
     if (&QEID1 == qeip) {
-      rccEnableTIM1(FALSE);
+      rccEnableTIM1();
       rccResetTIM1();
     }
 #endif
 #if STM32_QEI_USE_TIM2
     if (&QEID2 == qeip) {
-      rccEnableTIM2(FALSE);
+      rccEnableTIM2();
       rccResetTIM2();
     }
 #endif
 #if STM32_QEI_USE_TIM3
     if (&QEID3 == qeip) {
-      rccEnableTIM3(FALSE);
+      rccEnableTIM3();
       rccResetTIM3();
     }
 #endif
 #if STM32_QEI_USE_TIM4
     if (&QEID4 == qeip) {
-      rccEnableTIM4(FALSE);
+      rccEnableTIM4();
       rccResetTIM4();
     }
 #endif
 
 #if STM32_QEI_USE_TIM5
     if (&QEID5 == qeip) {
-      rccEnableTIM5(FALSE);
+      rccEnableTIM5();
       rccResetTIM5();
     }
 #endif
 #if STM32_QEI_USE_TIM8
     if (&QEID8 == qeip) {
-      rccEnableTIM8(FALSE);
+      rccEnableTIM8();
       rccResetTIM8();
     }
 #endif
@@ -235,33 +235,33 @@ void qei_lld_stop(QEIDriver *qeip) {
     /* Clock deactivation.*/
 #if STM32_QEI_USE_TIM1
     if (&QEID1 == qeip) {
-      rccDisableTIM1(FALSE);
+      rccDisableTIM1();
     }
 #endif
 #if STM32_QEI_USE_TIM2
     if (&QEID2 == qeip) {
-      rccDisableTIM2(FALSE);
+      rccDisableTIM2();
     }
 #endif
 #if STM32_QEI_USE_TIM3
     if (&QEID3 == qeip) {
-      rccDisableTIM3(FALSE);
+      rccDisableTIM3();
     }
 #endif
 #if STM32_QEI_USE_TIM4
     if (&QEID4 == qeip) {
-      rccDisableTIM4(FALSE);
+      rccDisableTIM4();
     }
 #endif
 #if STM32_QEI_USE_TIM5
     if (&QEID5 == qeip) {
-      rccDisableTIM5(FALSE);
+      rccDisableTIM5();
     }
 #endif
   }
 #if STM32_QEI_USE_TIM8
     if (&QEID8 == qeip) {
-      rccDisableTIM8(FALSE);
+      rccDisableTIM8();
     }
 #endif
 }
-- 
cgit v1.2.3


From 4aa00494c2716285e85246295fb2ed86aa99a4e4 Mon Sep 17 00:00:00 2001
From: marcoveeneman <marco-veeneman@hotmail.com>
Date: Sat, 10 Mar 2018 14:58:45 +0100
Subject: Added shared variables to startup, board and platform makefiles

---
 os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk | 5 +++++
 os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk | 5 +++++
 os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk                  | 4 ++++
 os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk                  | 4 ++++
 os/hal/ports/TIVA/TM4C123x/platform.mk                        | 4 ++++
 os/hal/ports/TIVA/TM4C129x/platform.mk                        | 4 ++++
 6 files changed, 26 insertions(+)

(limited to 'os')

diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk
index e87e60d..c1db8e2 100644
--- a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk
+++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk
@@ -11,3 +11,8 @@ STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
              $(CHIBIOS_CONTRIB)/os/common/ext/TivaWare
 
 STARTUPLD  = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
+
+# Shared variables
+ALLASM  += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC  += $(STARTUPINC)
diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk
index c8c5f82..cbe2dab 100644
--- a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk
+++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk
@@ -11,3 +11,8 @@ STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
              $(CHIBIOS_CONTRIB)/os/common/ext/TivaWare
 
 STARTUPLD  = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
+
+# Shared variables
+ALLASM  += $(STARTUPASM)
+ALLCSRC += $(STARTUPSRC)
+ALLINC  += $(STARTUPINC)
diff --git a/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk b/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk
index 8232a30..22b5467 100644
--- a/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk
+++ b/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk
@@ -3,3 +3,7 @@ BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.c
 
 # Required include directories
 BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/TI_TM4C123G_LAUNCHPAD
+
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk b/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk
index 56298eb..e95de0b 100644
--- a/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk
+++ b/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk
@@ -3,3 +3,7 @@ BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.c
 
 # Required include directories
 BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/TI_TM4C1294_LAUNCHPAD
+
+# Shared variables
+ALLCSRC += $(BOARDSRC)
+ALLINC  += $(BOARDINC)
diff --git a/os/hal/ports/TIVA/TM4C123x/platform.mk b/os/hal/ports/TIVA/TM4C123x/platform.mk
index 8372c25..8e447ec 100644
--- a/os/hal/ports/TIVA/TM4C123x/platform.mk
+++ b/os/hal/ports/TIVA/TM4C123x/platform.mk
@@ -27,3 +27,7 @@ include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/SSI/driver.mk
 include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART/driver.mk
 include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/uDMA/driver.mk
 include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/WDT/driver.mk
+
+# Shared variables
+ALLCSRC += $(PLATFORMSRC)
+ALLINC  += $(PLATFORMINC)
diff --git a/os/hal/ports/TIVA/TM4C129x/platform.mk b/os/hal/ports/TIVA/TM4C129x/platform.mk
index 934a6c2..9702796 100644
--- a/os/hal/ports/TIVA/TM4C129x/platform.mk
+++ b/os/hal/ports/TIVA/TM4C129x/platform.mk
@@ -28,3 +28,7 @@ include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/SSI/driver.mk
 include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART/driver.mk
 include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/uDMA/driver.mk
 include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/WDT/driver.mk
+
+# Shared variables
+ALLCSRC += $(PLATFORMSRC)
+ALLINC  += $(PLATFORMINC)
-- 
cgit v1.2.3


From 5e65e52f28287314eaad902d0eff6afe203c690b Mon Sep 17 00:00:00 2001
From: marcoveeneman <marco-veeneman@hotmail.com>
Date: Sat, 10 Mar 2018 15:32:24 +0100
Subject: Fixed wrong variable name for ASM files

---
 os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk | 6 +++---
 os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

(limited to 'os')

diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk
index c1db8e2..835faca 100644
--- a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk
+++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk
@@ -13,6 +13,6 @@ STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
 STARTUPLD  = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
 
 # Shared variables
-ALLASM  += $(STARTUPASM)
-ALLCSRC += $(STARTUPSRC)
-ALLINC  += $(STARTUPINC)
+ALLXASMSRC += $(STARTUPASM)
+ALLCSRC    += $(STARTUPSRC)
+ALLINC     += $(STARTUPINC)
diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk
index cbe2dab..ac4f76e 100644
--- a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk
+++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk
@@ -13,6 +13,6 @@ STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \
 STARTUPLD  = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
 
 # Shared variables
-ALLASM  += $(STARTUPASM)
-ALLCSRC += $(STARTUPSRC)
-ALLINC  += $(STARTUPINC)
+ALLXASMSRC += $(STARTUPASM)
+ALLCSRC    += $(STARTUPSRC)
+ALLINC     += $(STARTUPINC)
-- 
cgit v1.2.3


From b143e38a6684624fce07cc991853e8d2b19c420d Mon Sep 17 00:00:00 2001
From: Romain Reignier <rom.reignier@gmail.com>
Date: Sun, 11 Mar 2018 22:13:06 +0100
Subject: Keep track of STM32 RCC API

RCC API changed in 01/2018 so apply the changes.

Note that ae7a4d40b84d8afc999691577210696f16e682f6 partially fixed the changes in QEI module but some were missing.
So update the other modules too.
---
 os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c   | 24 ++++++++++++------------
 os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c    | 12 ++++++------
 os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c | 14 +++++++-------
 3 files changed, 25 insertions(+), 25 deletions(-)

(limited to 'os')

diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c
index c04278e..ed4c5b8 100644
--- a/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c
+++ b/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c
@@ -1057,75 +1057,75 @@ void eicu_lld_stop(EICUDriver *eicup) {
     if (&EICUD1 == eicup) {
       nvicDisableVector(STM32_TIM1_UP_NUMBER);
       nvicDisableVector(STM32_TIM1_CC_NUMBER);
-      rccDisableTIM1(FALSE);
+      rccDisableTIM1();
     }
 #endif
 #if STM32_EICU_USE_TIM2
     if (&EICUD2 == eicup) {
       nvicDisableVector(STM32_TIM2_NUMBER);
-      rccDisableTIM2(FALSE);
+      rccDisableTIM2();
     }
 #endif
 #if STM32_EICU_USE_TIM3
     if (&EICUD3 == eicup) {
       nvicDisableVector(STM32_TIM3_NUMBER);
-      rccDisableTIM3(FALSE);
+      rccDisableTIM3();
     }
 #endif
 #if STM32_EICU_USE_TIM4
     if (&EICUD4 == eicup) {
       nvicDisableVector(STM32_TIM4_NUMBER);
-      rccDisableTIM4(FALSE);
+      rccDisableTIM4();
     }
 #endif
 #if STM32_EICU_USE_TIM5
     if (&EICUD5 == eicup) {
       nvicDisableVector(STM32_TIM5_NUMBER);
-      rccDisableTIM5(FALSE);
+      rccDisableTIM5();
     }
 #endif
 #if STM32_EICU_USE_TIM8
     if (&EICUD8 == eicup) {
       nvicDisableVector(STM32_TIM8_UP_NUMBER);
       nvicDisableVector(STM32_TIM8_CC_NUMBER);
-      rccDisableTIM8(FALSE);
+      rccDisableTIM8();
     }
 #endif
 #if STM32_EICU_USE_TIM9
     if (&EICUD9 == eicup) {
       nvicDisableVector(STM32_TIM9_NUMBER);
-      rccDisableTIM9(FALSE);
+      rccDisableTIM9();
     }
 #endif
 #if STM32_EICU_USE_TIM12
     if (&EICUD12 == eicup) {
       nvicDisableVector(STM32_TIM12_NUMBER);
-      rccDisableTIM12(FALSE);
+      rccDisableTIM12();
     }
 #endif
   }
 #if STM32_EICU_USE_TIM10
     if (&EICUD10 == eicup) {
       nvicDisableVector(STM32_TIM10_NUMBER);
-      rccDisableTIM10(FALSE);
+      rccDisableTIM10();
     }
 #endif
 #if STM32_EICU_USE_TIM11
     if (&EICUD11 == eicup) {
       nvicDisableVector(STM32_TIM11_NUMBER);
-      rccDisableTIM11(FALSE);
+      rccDisableTIM11();
     }
 #endif
 #if STM32_EICU_USE_TIM13
     if (&EICUD13 == eicup) {
       nvicDisableVector(STM32_TIM13_NUMBER);
-      rccDisableTIM13(FALSE);
+      rccDisableTIM13();
     }
 #endif
 #if STM32_EICU_USE_TIM14
     if (&EICUD14 == eicup) {
       nvicDisableVector(STM32_TIM14_NUMBER);
-      rccDisableTIM14(FALSE);
+      rccDisableTIM14();
     }
 #endif
 }
diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c
index cef015e..e07b946 100644
--- a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c
+++ b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c
@@ -157,38 +157,38 @@ void qei_lld_start(QEIDriver *qeip) {
     /* Clock activation and timer reset.*/
 #if STM32_QEI_USE_TIM1
     if (&QEID1 == qeip) {
-      rccEnableTIM1();
+      rccEnableTIM1(FALSE);
       rccResetTIM1();
     }
 #endif
 #if STM32_QEI_USE_TIM2
     if (&QEID2 == qeip) {
-      rccEnableTIM2();
+      rccEnableTIM2(FALSE);
       rccResetTIM2();
     }
 #endif
 #if STM32_QEI_USE_TIM3
     if (&QEID3 == qeip) {
-      rccEnableTIM3();
+      rccEnableTIM3(FALSE);
       rccResetTIM3();
     }
 #endif
 #if STM32_QEI_USE_TIM4
     if (&QEID4 == qeip) {
-      rccEnableTIM4();
+      rccEnableTIM4(FALSE);
       rccResetTIM4();
     }
 #endif
 
 #if STM32_QEI_USE_TIM5
     if (&QEID5 == qeip) {
-      rccEnableTIM5();
+      rccEnableTIM5(FALSE);
       rccResetTIM5();
     }
 #endif
 #if STM32_QEI_USE_TIM8
     if (&QEID8 == qeip) {
-      rccEnableTIM8();
+      rccEnableTIM8(FALSE);
       rccResetTIM8();
     }
 #endif
diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c
index 37a48fd..d95c6a3 100644
--- a/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c
+++ b/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c
@@ -713,44 +713,44 @@ void timcap_lld_stop(TIMCAPDriver *timcapp) {
     if (&TIMCAPD1 == timcapp) {
       nvicDisableVector(STM32_TIM1_UP_NUMBER);
       nvicDisableVector(STM32_TIM1_CC_NUMBER);
-      rccDisableTIM1(FALSE);
+      rccDisableTIM1();
     }
 #endif
 #if STM32_TIMCAP_USE_TIM2
     if (&TIMCAPD2 == timcapp) {
       nvicDisableVector(STM32_TIM2_NUMBER);
-      rccDisableTIM2(FALSE);
+      rccDisableTIM2();
     }
 #endif
 #if STM32_TIMCAP_USE_TIM3
     if (&TIMCAPD3 == timcapp) {
       nvicDisableVector(STM32_TIM3_NUMBER);
-      rccDisableTIM3(FALSE);
+      rccDisableTIM3();
     }
 #endif
 #if STM32_TIMCAP_USE_TIM4
     if (&TIMCAPD4 == timcapp) {
       nvicDisableVector(STM32_TIM4_NUMBER);
-      rccDisableTIM4(FALSE);
+      rccDisableTIM4();
     }
 #endif
 #if STM32_TIMCAP_USE_TIM5
     if (&TIMCAPD5 == timcapp) {
       nvicDisableVector(STM32_TIM5_NUMBER);
-      rccDisableTIM5(FALSE);
+      rccDisableTIM5();
     }
 #endif
 #if STM32_TIMCAP_USE_TIM8
     if (&TIMCAPD8 == timcapp) {
       nvicDisableVector(STM32_TIM8_UP_NUMBER);
       nvicDisableVector(STM32_TIM8_CC_NUMBER);
-      rccDisableTIM8(FALSE);
+      rccDisableTIM8();
     }
 #endif
 #if STM32_TIMCAP_USE_TIM9
     if (&TIMCAPD9 == timcapp) {
       nvicDisableVector(STM32_TIM9_NUMBER);
-      rccDisableTIM9(FALSE);
+      rccDisableTIM9();
     }
 #endif
   }
-- 
cgit v1.2.3


From 32cdf41174686c78d7978d0a4232b1ac8bc0f2f6 Mon Sep 17 00:00:00 2001
From: marcoveeneman <marco-veeneman@hotmail.com>
Date: Mon, 12 Mar 2018 19:04:54 +0100
Subject: Fixed warnings triggered by -Wundef compile option

---
 os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h | 32 ++++++++++++++++----------------
 os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c  |  2 +-
 os/hal/ports/TIVA/TM4C123x/hal_lld.h     |  2 +-
 3 files changed, 18 insertions(+), 18 deletions(-)

(limited to 'os')

diff --git a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h
index 993d5c3..e884a92 100644
--- a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h
+++ b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h
@@ -665,82 +665,82 @@ typedef uint32_t iopadid_t;
 #error "Invalid IRQ priority assigned to GPION"
 #endif
 
-#if TIVA_HAS_GPIOP0 &&                                                         \
+#if TIVA_HAS_GPIOP &&                                                         \
     !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP0_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOP0"
 #endif
 
-#if TIVA_HAS_GPIOP1 &&                                                         \
+#if TIVA_HAS_GPIOP &&                                                         \
     !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP1_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOP1"
 #endif
 
-#if TIVA_HAS_GPIOP2 &&                                                         \
+#if TIVA_HAS_GPIOP &&                                                         \
     !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP2_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOP2"
 #endif
 
-#if TIVA_HAS_GPIOP3 &&                                                         \
+#if TIVA_HAS_GPIOP &&                                                         \
     !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP3_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOP3"
 #endif
 
-#if TIVA_HAS_GPIOP4 &&                                                         \
+#if TIVA_HAS_GPIOP &&                                                         \
     !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP4_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOP4"
 #endif
 
-#if TIVA_HAS_GPIOP5 &&                                                         \
+#if TIVA_HAS_GPIOP &&                                                         \
     !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP5_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOP5"
 #endif
 
-#if TIVA_HAS_GPIOP6 &&                                                         \
+#if TIVA_HAS_GPIOP &&                                                         \
     !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP6_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOP6"
 #endif
 
-#if TIVA_HAS_GPIOP7 &&                                                         \
+#if TIVA_HAS_GPIOP &&                                                         \
     !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP7_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOP7"
 #endif
 
-#if TIVA_HAS_GPIOQ0 &&                                                         \
+#if TIVA_HAS_GPIOQ &&                                                         \
     !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ0_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOQ0"
 #endif
 
-#if TIVA_HAS_GPIOQ1 &&                                                         \
+#if TIVA_HAS_GPIOQ &&                                                         \
     !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ1_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOQ1"
 #endif
 
-#if TIVA_HAS_GPIOQ2 &&                                                         \
+#if TIVA_HAS_GPIOQ &&                                                         \
     !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ2_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOQ2"
 #endif
 
-#if TIVA_HAS_GPIOQ3 &&                                                         \
+#if TIVA_HAS_GPIOQ &&                                                         \
     !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ3_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOQ3"
 #endif
 
-#if TIVA_HAS_GPIOQ4 &&                                                         \
+#if TIVA_HAS_GPIOQ &&                                                         \
     !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ4_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOQ4"
 #endif
 
-#if TIVA_HAS_GPIOQ5 &&                                                         \
+#if TIVA_HAS_GPIOQ &&                                                         \
     !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ5_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOQ5"
 #endif
 
-#if TIVA_HAS_GPIOQ6 &&                                                         \
+#if TIVA_HAS_GPIOQ &&                                                         \
     !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ6_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOQ6"
 #endif
 
-#if TIVA_HAS_GPIOQ7 &&                                                         \
+#if TIVA_HAS_GPIOQ &&                                                         \
     !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ7_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to GPIOQ7"
 #endif
diff --git a/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c
index 7da95b8..0f9576a 100644
--- a/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c
+++ b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c
@@ -74,7 +74,7 @@
 #error "TIVA_ST_USE_TIMER specifies an unsupported timer"
 #endif
 
-#if (ST_CLOCK_SRC / OSAL_ST_FREQUENCY) - 1 > 0xFFFF
+#if (TIVA_SYSCLK / OSAL_ST_FREQUENCY) - 1 > 0xFFFF
 #error "the selected ST frequency is not obtainable because TIM timer prescaler limits"
 #endif
 
diff --git a/os/hal/ports/TIVA/TM4C123x/hal_lld.h b/os/hal/ports/TIVA/TM4C123x/hal_lld.h
index 5937b88..5d38a67 100644
--- a/os/hal/ports/TIVA/TM4C123x/hal_lld.h
+++ b/os/hal/ports/TIVA/TM4C123x/hal_lld.h
@@ -203,7 +203,7 @@
 #error "Invalid value for TIVA_BYPASS_VALUE defined"
 #endif
 
-#if (TIVA_OSCSRC == TIVA_RCC_OSCSRC_MOSC) && (TIVA_MOSC_ENABLE == FALSE)
+#if (TIVA_OSCSRC == SYSCTL_RCC2_OSCSRC2_MO) && (TIVA_MOSC_ENABLE == FALSE)
 #error "Main Oscillator selected but not enabled"
 #endif
 
-- 
cgit v1.2.3


From 918149d48d908cf8441cbd41571b768918a4d7b1 Mon Sep 17 00:00:00 2001
From: Romain Reignier <rom.reignier@gmail.com>
Date: Sun, 11 Mar 2018 22:13:06 +0100
Subject: hal: stm32: Keep track of latest STM32 RCC API

RCC API changed in 01/2018 so apply the changes.

Note that ae7a4d40b84d8afc999691577210696f16e682f6 partially fixed the changes in QEI module but some were missing.
So update the other modules too.
---
 os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c   | 24 ++++++++++++------------
 os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c    | 12 ++++++------
 os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c | 14 +++++++-------
 3 files changed, 25 insertions(+), 25 deletions(-)

(limited to 'os')

diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c
index c04278e..ed4c5b8 100644
--- a/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c
+++ b/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c
@@ -1057,75 +1057,75 @@ void eicu_lld_stop(EICUDriver *eicup) {
     if (&EICUD1 == eicup) {
       nvicDisableVector(STM32_TIM1_UP_NUMBER);
       nvicDisableVector(STM32_TIM1_CC_NUMBER);
-      rccDisableTIM1(FALSE);
+      rccDisableTIM1();
     }
 #endif
 #if STM32_EICU_USE_TIM2
     if (&EICUD2 == eicup) {
       nvicDisableVector(STM32_TIM2_NUMBER);
-      rccDisableTIM2(FALSE);
+      rccDisableTIM2();
     }
 #endif
 #if STM32_EICU_USE_TIM3
     if (&EICUD3 == eicup) {
       nvicDisableVector(STM32_TIM3_NUMBER);
-      rccDisableTIM3(FALSE);
+      rccDisableTIM3();
     }
 #endif
 #if STM32_EICU_USE_TIM4
     if (&EICUD4 == eicup) {
       nvicDisableVector(STM32_TIM4_NUMBER);
-      rccDisableTIM4(FALSE);
+      rccDisableTIM4();
     }
 #endif
 #if STM32_EICU_USE_TIM5
     if (&EICUD5 == eicup) {
       nvicDisableVector(STM32_TIM5_NUMBER);
-      rccDisableTIM5(FALSE);
+      rccDisableTIM5();
     }
 #endif
 #if STM32_EICU_USE_TIM8
     if (&EICUD8 == eicup) {
       nvicDisableVector(STM32_TIM8_UP_NUMBER);
       nvicDisableVector(STM32_TIM8_CC_NUMBER);
-      rccDisableTIM8(FALSE);
+      rccDisableTIM8();
     }
 #endif
 #if STM32_EICU_USE_TIM9
     if (&EICUD9 == eicup) {
       nvicDisableVector(STM32_TIM9_NUMBER);
-      rccDisableTIM9(FALSE);
+      rccDisableTIM9();
     }
 #endif
 #if STM32_EICU_USE_TIM12
     if (&EICUD12 == eicup) {
       nvicDisableVector(STM32_TIM12_NUMBER);
-      rccDisableTIM12(FALSE);
+      rccDisableTIM12();
     }
 #endif
   }
 #if STM32_EICU_USE_TIM10
     if (&EICUD10 == eicup) {
       nvicDisableVector(STM32_TIM10_NUMBER);
-      rccDisableTIM10(FALSE);
+      rccDisableTIM10();
     }
 #endif
 #if STM32_EICU_USE_TIM11
     if (&EICUD11 == eicup) {
       nvicDisableVector(STM32_TIM11_NUMBER);
-      rccDisableTIM11(FALSE);
+      rccDisableTIM11();
     }
 #endif
 #if STM32_EICU_USE_TIM13
     if (&EICUD13 == eicup) {
       nvicDisableVector(STM32_TIM13_NUMBER);
-      rccDisableTIM13(FALSE);
+      rccDisableTIM13();
     }
 #endif
 #if STM32_EICU_USE_TIM14
     if (&EICUD14 == eicup) {
       nvicDisableVector(STM32_TIM14_NUMBER);
-      rccDisableTIM14(FALSE);
+      rccDisableTIM14();
     }
 #endif
 }
diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c
index cef015e..e07b946 100644
--- a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c
+++ b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c
@@ -157,38 +157,38 @@ void qei_lld_start(QEIDriver *qeip) {
     /* Clock activation and timer reset.*/
 #if STM32_QEI_USE_TIM1
     if (&QEID1 == qeip) {
-      rccEnableTIM1();
+      rccEnableTIM1(FALSE);
       rccResetTIM1();
     }
 #endif
 #if STM32_QEI_USE_TIM2
     if (&QEID2 == qeip) {
-      rccEnableTIM2();
+      rccEnableTIM2(FALSE);
       rccResetTIM2();
     }
 #endif
 #if STM32_QEI_USE_TIM3
     if (&QEID3 == qeip) {
-      rccEnableTIM3();
+      rccEnableTIM3(FALSE);
       rccResetTIM3();
     }
 #endif
 #if STM32_QEI_USE_TIM4
     if (&QEID4 == qeip) {
-      rccEnableTIM4();
+      rccEnableTIM4(FALSE);
       rccResetTIM4();
     }
 #endif
 
 #if STM32_QEI_USE_TIM5
     if (&QEID5 == qeip) {
-      rccEnableTIM5();
+      rccEnableTIM5(FALSE);
       rccResetTIM5();
     }
 #endif
 #if STM32_QEI_USE_TIM8
     if (&QEID8 == qeip) {
-      rccEnableTIM8();
+      rccEnableTIM8(FALSE);
       rccResetTIM8();
     }
 #endif
diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c
index 37a48fd..d95c6a3 100644
--- a/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c
+++ b/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c
@@ -713,44 +713,44 @@ void timcap_lld_stop(TIMCAPDriver *timcapp) {
     if (&TIMCAPD1 == timcapp) {
       nvicDisableVector(STM32_TIM1_UP_NUMBER);
       nvicDisableVector(STM32_TIM1_CC_NUMBER);
-      rccDisableTIM1(FALSE);
+      rccDisableTIM1();
     }
 #endif
 #if STM32_TIMCAP_USE_TIM2
     if (&TIMCAPD2 == timcapp) {
       nvicDisableVector(STM32_TIM2_NUMBER);
-      rccDisableTIM2(FALSE);
+      rccDisableTIM2();
     }
 #endif
 #if STM32_TIMCAP_USE_TIM3
     if (&TIMCAPD3 == timcapp) {
       nvicDisableVector(STM32_TIM3_NUMBER);
-      rccDisableTIM3(FALSE);
+      rccDisableTIM3();
     }
 #endif
 #if STM32_TIMCAP_USE_TIM4
     if (&TIMCAPD4 == timcapp) {
       nvicDisableVector(STM32_TIM4_NUMBER);
-      rccDisableTIM4(FALSE);
+      rccDisableTIM4();
     }
 #endif
 #if STM32_TIMCAP_USE_TIM5
     if (&TIMCAPD5 == timcapp) {
       nvicDisableVector(STM32_TIM5_NUMBER);
-      rccDisableTIM5(FALSE);
+      rccDisableTIM5();
     }
 #endif
 #if STM32_TIMCAP_USE_TIM8
     if (&TIMCAPD8 == timcapp) {
       nvicDisableVector(STM32_TIM8_UP_NUMBER);
       nvicDisableVector(STM32_TIM8_CC_NUMBER);
-      rccDisableTIM8(FALSE);
+      rccDisableTIM8();
     }
 #endif
 #if STM32_TIMCAP_USE_TIM9
     if (&TIMCAPD9 == timcapp) {
       nvicDisableVector(STM32_TIM9_NUMBER);
-      rccDisableTIM9(FALSE);
+      rccDisableTIM9();
     }
 #endif
   }
-- 
cgit v1.2.3


From 26a11251bfb8d951a5ba50da190f43d1d3555725 Mon Sep 17 00:00:00 2001
From: Romain Reignier <rom.reignier@gmail.com>
Date: Mon, 12 Mar 2018 21:12:24 +0100
Subject: hal_fsmc: update to new RCC API

---
 os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'os')

diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c
index 500b2e7..71c6ada 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c
+++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c
@@ -159,7 +159,7 @@ void fsmc_stop(FSMCDriver *fsmcp) {
 #if HAL_USE_NAND
       nvicDisableVector(STM32_FSMC_NUMBER);
 #endif
-      rccDisableFSMC(FALSE);
+      rccDisableFSMC();
     }
 #endif /* STM32_FSMC_USE_FSMC1 */
 
-- 
cgit v1.2.3


From e1e6f874816be7f5d47629df7fbc407f0da6625d Mon Sep 17 00:00:00 2001
From: Romain Reignier <rom.reignier@gmail.com>
Date: Mon, 12 Mar 2018 21:13:23 +0100
Subject: hal_usbh: update to new Time macros

---
 os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c | 8 ++++----
 os/hal/src/usbh/hal_usbh_aoa.c               | 4 ++--
 os/hal/src/usbh/hal_usbh_ftdi.c              | 8 ++++----
 os/hal/src/usbh/hal_usbh_msd.c               | 8 ++++----
 4 files changed, 14 insertions(+), 14 deletions(-)

(limited to 'os')

diff --git a/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c b/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c
index 4723508..2894907 100644
--- a/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c
+++ b/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c
@@ -1665,9 +1665,9 @@ usbh_urbstatus_t usbh_lld_root_hub_request(USBHDriver *usbh, uint8_t bmRequestTy
 				 * despite reporting a successful por enable. */
 				uerr("Detected enabled port; resetting OTG core");
 				otg->GAHBCFG = 0;
-				osalThreadSleepS(MS2ST(20));
+				osalThreadSleepS(OSAL_MS2I(20));
 				_usbh_start(usbh);				/* this effectively resets the core */
-				osalThreadSleepS(MS2ST(100));	/* during this delay, the core generates connect ISR */
+				osalThreadSleepS(OSAL_MS2I(100));	/* during this delay, the core generates connect ISR */
 				uinfo("OTG reset ended");
 				if (otg->HPRT & HPRT_PCSTS) {
 					/* if the device is still connected, don't report a C_CONNECTION flag, which would cause
@@ -1680,9 +1680,9 @@ usbh_urbstatus_t usbh_lld_root_hub_request(USBHDriver *usbh, uint8_t bmRequestTy
 			hprt &= ~(HPRT_PSUSP | HPRT_PENA | HPRT_PCDET | HPRT_PENCHNG | HPRT_POCCHNG);
 			while ((otg->GRSTCTL & GRSTCTL_AHBIDL) == 0);
 			otg->HPRT = hprt | HPRT_PRST;
-			osalThreadSleepS(MS2ST(15));
+			osalThreadSleepS(OSAL_MS2I(15));
 			otg->HPRT = hprt;
-			osalThreadSleepS(MS2ST(10));
+			osalThreadSleepS(OSAL_MS2I(10));
 			usbh->rootport.lld_c_status |= USBH_PORTSTATUS_C_RESET;
 			osalSysUnlock();
 		} 	break;
diff --git a/os/hal/src/usbh/hal_usbh_aoa.c b/os/hal/src/usbh/hal_usbh_aoa.c
index 85c3130..d565595 100644
--- a/os/hal/src/usbh/hal_usbh_aoa.c
+++ b/os/hal/src/usbh/hal_usbh_aoa.c
@@ -533,7 +533,7 @@ static void _vt(void *p) {
 	if ((aoacp->iq_counter == 0) && !usbhURBIsBusy(&aoacp->iq_urb)) {
 		_submitInI(aoacp);
 	}
-	chVTSetI(&aoacp->vt, MS2ST(16), _vt, aoacp);
+	chVTSetI(&aoacp->vt, OSAL_MS2I(16), _vt, aoacp);
 	osalSysUnlockFromISR();
 }
 
@@ -565,7 +565,7 @@ void usbhaoaChannelStart(USBHAOADriver *aoap) {
 	usbhURBSubmit(&aoacp->iq_urb);
 
 	chVTObjectInit(&aoacp->vt);
-	chVTSet(&aoacp->vt, MS2ST(16), _vt, aoacp);
+	chVTSet(&aoacp->vt, OSAL_MS2I(16), _vt, aoacp);
 
 	aoacp->state = USBHAOA_CHANNEL_STATE_READY;
 
diff --git a/os/hal/src/usbh/hal_usbh_ftdi.c b/os/hal/src/usbh/hal_usbh_ftdi.c
index 6fb556d..6966028 100644
--- a/os/hal/src/usbh/hal_usbh_ftdi.c
+++ b/os/hal/src/usbh/hal_usbh_ftdi.c
@@ -332,7 +332,7 @@ static usbh_urbstatus_t _ftdi_port_control(USBHFTDIPortDriver *ftdipp,
 			wLength
 	};
 
-	return usbhControlRequestExtended(ftdipp->ftdip->dev, &req, buff, NULL, MS2ST(1000));
+	return usbhControlRequestExtended(ftdipp->ftdip->dev, &req, buff, NULL, OSAL_MS2I(1000));
 }
 
 static uint32_t _get_divisor(uint32_t baud, usbhftdi_type_t type) {
@@ -394,7 +394,7 @@ static usbh_urbstatus_t _set_baudrate(USBHFTDIPortDriver *ftdipp, uint32_t baudr
 		wIndex,
 		0
 	};
-	return usbhControlRequestExtended(ftdipp->ftdip->dev, &req, NULL, NULL, MS2ST(1000));
+	return usbhControlRequestExtended(ftdipp->ftdip->dev, &req, NULL, NULL, OSAL_MS2I(1000));
 }
 
 
@@ -610,7 +610,7 @@ static void _vt(void *p) {
 	if ((ftdipp->iq_counter == 0) && !usbhURBIsBusy(&ftdipp->iq_urb)) {
 		_submitInI(ftdipp);
 	}
-	chVTSetI(&ftdipp->vt, MS2ST(16), _vt, ftdipp);
+	chVTSetI(&ftdipp->vt, OSAL_MS2I(16), _vt, ftdipp);
 	osalSysUnlockFromISR();
 }
 
@@ -690,7 +690,7 @@ void usbhftdipStart(USBHFTDIPortDriver *ftdipp, const USBHFTDIPortConfig *config
 	usbhURBSubmit(&ftdipp->iq_urb);
 
 	chVTObjectInit(&ftdipp->vt);
-	chVTSet(&ftdipp->vt, MS2ST(16), _vt, ftdipp);
+	chVTSet(&ftdipp->vt, OSAL_MS2I(16), _vt, ftdipp);
 
 	ftdipp->state = USBHFTDIP_STATE_READY;
 	osalMutexUnlock(&ftdipp->ftdip->mtx);
diff --git a/os/hal/src/usbh/hal_usbh_msd.c b/os/hal/src/usbh/hal_usbh_msd.c
index 069c47b..7233a0b 100644
--- a/os/hal/src/usbh/hal_usbh_msd.c
+++ b/os/hal/src/usbh/hal_usbh_msd.c
@@ -304,7 +304,7 @@ static msd_bot_result_t _msd_bot_transaction(msd_transaction_t *tran, USBHMassSt
 
 	/* control phase */
 	status = usbhBulkTransfer(&lunp->msdp->epout, tran->cbw,
-					sizeof(*tran->cbw), &actual_len, MS2ST(1000));
+					sizeof(*tran->cbw), &actual_len, OSAL_MS2I(1000));
 
 	if (status == USBH_URBSTATUS_CANCELLED) {
 		uerr("\tMSD: Control phase: USBH_URBSTATUS_CANCELLED");
@@ -327,7 +327,7 @@ static msd_bot_result_t _msd_bot_transaction(msd_transaction_t *tran, USBHMassSt
 				ep,
 				data,
 				tran->cbw->dCBWDataTransferLength,
-				&data_actual_len, MS2ST(20000));
+				&data_actual_len, OSAL_MS2I(20000));
 
 		if (status == USBH_URBSTATUS_CANCELLED) {
 			uerr("\tMSD: Data phase: USBH_URBSTATUS_CANCELLED");
@@ -349,7 +349,7 @@ static msd_bot_result_t _msd_bot_transaction(msd_transaction_t *tran, USBHMassSt
 
 	/* status phase */
 	status = usbhBulkTransfer(&lunp->msdp->epin, &csw,
-				sizeof(csw), &actual_len, MS2ST(1000));
+				sizeof(csw), &actual_len, OSAL_MS2I(1000));
 
 	if (status == USBH_URBSTATUS_STALL) {
 		uwarn("\tMSD: Status phase: USBH_URBSTATUS_STALL, clear halt and retry");
@@ -358,7 +358,7 @@ static msd_bot_result_t _msd_bot_transaction(msd_transaction_t *tran, USBHMassSt
 
 		if (status == USBH_URBSTATUS_OK) {
 			status = usbhBulkTransfer(&lunp->msdp->epin, &csw,
-						sizeof(csw), &actual_len, MS2ST(1000));
+						sizeof(csw), &actual_len, OSAL_MS2I(1000));
 		}
 	}
 
-- 
cgit v1.2.3


From 3a9593e6d8c7fadf46b446946f4312f4a98a6914 Mon Sep 17 00:00:00 2001
From: Romain Reignier <rom.reignier@gmail.com>
Date: Mon, 12 Mar 2018 21:13:46 +0100
Subject: fatfs: update to latest ChibiOS changes

---
 os/various/fatfs_bindings/fatfs.mk       |  2 +-
 os/various/fatfs_bindings/fatfs_diskio.c | 20 ++++++++++----------
 2 files changed, 11 insertions(+), 11 deletions(-)

(limited to 'os')

diff --git a/os/various/fatfs_bindings/fatfs.mk b/os/various/fatfs_bindings/fatfs.mk
index 238037e..f2feeb5 100644
--- a/os/various/fatfs_bindings/fatfs.mk
+++ b/os/various/fatfs_bindings/fatfs.mk
@@ -2,6 +2,6 @@
 FATFSSRC = ${CHIBIOS_CONTRIB}/os/various/fatfs_bindings/fatfs_diskio.c \
            ${CHIBIOS}/os/various/fatfs_bindings/fatfs_syscall.c \
            ${CHIBIOS}/ext/fatfs/src/ff.c \
-           ${CHIBIOS}/ext/fatfs/src/option/unicode.c
+           $(CHIBIOS)/ext/fatfs/src/ffunicode.c
 
 FATFSINC = ${CHIBIOS}/ext/fatfs/src
diff --git a/os/various/fatfs_bindings/fatfs_diskio.c b/os/various/fatfs_bindings/fatfs_diskio.c
index 9fa41e2..80d1502 100644
--- a/os/various/fatfs_bindings/fatfs_diskio.c
+++ b/os/various/fatfs_bindings/fatfs_diskio.c
@@ -89,7 +89,7 @@ DSTATUS disk_initialize (
 /* Return Disk Status                                                    */
 
 DSTATUS disk_status (
-    BYTE pdrv        /* Physical drive nmuber (0..) */
+    BYTE pdrv         /* Physical drive number (0..) */
 )
 {
   DSTATUS stat;
@@ -132,9 +132,9 @@ DSTATUS disk_status (
 /* Read Sector(s)                                                        */
 
 DRESULT disk_read (
-    BYTE pdrv,        /* Physical drive nmuber (0..) */
-    BYTE *buff,        /* Data buffer to store read data */
-    DWORD sector,    /* Sector address (LBA) */
+    BYTE pdrv,        /* Physical drive number (0..) */
+    BYTE *buff,       /* Data buffer to store read data */
+    DWORD sector,     /* Sector address (LBA) */
     UINT count        /* Number of sectors to read (1..255) */
 )
 {
@@ -181,10 +181,10 @@ DRESULT disk_read (
 /* Write Sector(s)                                                       */
 
 DRESULT disk_write (
-    BYTE pdrv,            /* Physical drive nmuber (0..) */
-    const BYTE *buff,    /* Data to be written */
-    DWORD sector,        /* Sector address (LBA) */
-    UINT count            /* Number of sectors to write (1..255) */
+    BYTE pdrv,        /* Physical drive number (0..) */
+    const BYTE *buff, /* Data to be written */
+    DWORD sector,     /* Sector address (LBA) */
+    UINT count        /* Number of sectors to write (1..255) */
 )
 {
   switch (pdrv) {
@@ -232,8 +232,8 @@ DRESULT disk_write (
 /* Miscellaneous Functions                                               */
 
 DRESULT disk_ioctl (
-    BYTE pdrv,        /* Physical drive nmuber (0..) */
-    BYTE cmd,        /* Control code */
+    BYTE pdrv,        /* Physical drive number (0..) */
+    BYTE cmd,         /* Control code */
     void *buff        /* Buffer to send/receive control data */
 )
 {
-- 
cgit v1.2.3


From 6ca20973e2889ce228b41c47231a5339d8e95970 Mon Sep 17 00:00:00 2001
From: Romain Reignier <rom.reignier@gmail.com>
Date: Mon, 12 Mar 2018 21:15:22 +0100
Subject: boards: Update board BARTHESS to newer API

---
 .../boards/NONSTANDARD_STM32F4_BARTHESS2/board.c   | 189 +++++++++++++++++++--
 1 file changed, 171 insertions(+), 18 deletions(-)

(limited to 'os')

diff --git a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c
index e6c6080..09b44f7 100644
--- a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c
+++ b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c
@@ -14,45 +14,197 @@
     limitations under the License.
 */
 
-#include "ch.h"
 #include "hal.h"
+#include "stm32_gpio.h"
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type of STM32 GPIO port setup.
+ */
+typedef struct {
+  uint32_t              moder;
+  uint32_t              otyper;
+  uint32_t              ospeedr;
+  uint32_t              pupdr;
+  uint32_t              odr;
+  uint32_t              afrl;
+  uint32_t              afrh;
+} gpio_setup_t;
+
+/**
+ * @brief   Type of STM32 GPIO initialization data.
+ */
+typedef struct {
+#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
+  gpio_setup_t          PAData;
+#endif
+#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
+  gpio_setup_t          PBData;
+#endif
+#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
+  gpio_setup_t          PCData;
+#endif
+#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
+  gpio_setup_t          PDData;
+#endif
+#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
+  gpio_setup_t          PEData;
+#endif
+#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
+  gpio_setup_t          PFData;
+#endif
+#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
+  gpio_setup_t          PGData;
+#endif
+#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
+  gpio_setup_t          PHData;
+#endif
+#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
+  gpio_setup_t          PIData;
+#endif
+#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
+  gpio_setup_t          PJData;
+#endif
+#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
+  gpio_setup_t          PKData;
+#endif
+} gpio_config_t;
 
-#if HAL_USE_PAL || defined(__DOXYGEN__)
 /**
- * @brief   PAL setup.
- * @details Digital I/O ports static configuration as defined in @p board.h.
- *          This variable is used by the HAL when initializing the PAL driver.
+ * @brief   STM32 GPIO static initialization data.
  */
-const PALConfig pal_default_config =
-{
+static const gpio_config_t gpio_default_config = {
+#if STM32_HAS_GPIOA
   {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
    VAL_GPIOA_ODR,   VAL_GPIOA_AFRL,   VAL_GPIOA_AFRH},
+#endif
+#if STM32_HAS_GPIOB
   {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
    VAL_GPIOB_ODR,   VAL_GPIOB_AFRL,   VAL_GPIOB_AFRH},
+#endif
+#if STM32_HAS_GPIOC
   {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
    VAL_GPIOC_ODR,   VAL_GPIOC_AFRL,   VAL_GPIOC_AFRH},
+#endif
+#if STM32_HAS_GPIOD
   {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
    VAL_GPIOD_ODR,   VAL_GPIOD_AFRL,   VAL_GPIOD_AFRH},
+#endif
+#if STM32_HAS_GPIOE
   {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
    VAL_GPIOE_ODR,   VAL_GPIOE_AFRL,   VAL_GPIOE_AFRH},
+#endif
+#if STM32_HAS_GPIOF
   {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
    VAL_GPIOF_ODR,   VAL_GPIOF_AFRL,   VAL_GPIOF_AFRH},
+#endif
+#if STM32_HAS_GPIOG
   {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
    VAL_GPIOG_ODR,   VAL_GPIOG_AFRL,   VAL_GPIOG_AFRH},
+#endif
+#if STM32_HAS_GPIOH
   {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
    VAL_GPIOH_ODR,   VAL_GPIOH_AFRL,   VAL_GPIOH_AFRH},
+#endif
+#if STM32_HAS_GPIOI
   {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
-   VAL_GPIOI_ODR,   VAL_GPIOI_AFRL,   VAL_GPIOI_AFRH}
+   VAL_GPIOI_ODR,   VAL_GPIOI_AFRL,   VAL_GPIOI_AFRH},
+#endif
+#if STM32_HAS_GPIOJ
+  {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
+   VAL_GPIOJ_ODR,   VAL_GPIOJ_AFRL,   VAL_GPIOJ_AFRH},
+#endif
+#if STM32_HAS_GPIOK
+  {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
+   VAL_GPIOK_ODR,   VAL_GPIOK_AFRL,   VAL_GPIOK_AFRH}
+#endif
 };
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
+
+  gpiop->OTYPER  = config->otyper;
+  gpiop->OSPEEDR = config->ospeedr;
+  gpiop->PUPDR   = config->pupdr;
+  gpiop->ODR     = config->odr;
+  gpiop->AFRL    = config->afrl;
+  gpiop->AFRH    = config->afrh;
+  gpiop->MODER   = config->moder;
+}
+
+static void stm32_gpio_init(void) {
+
+  /* Enabling GPIO-related clocks, the mask comes from the
+     registry header file.*/
+  rccResetAHB1(STM32_GPIO_EN_MASK);
+  rccEnableAHB1(STM32_GPIO_EN_MASK, true);
+
+  /* Initializing all the defined GPIO ports.*/
+#if STM32_HAS_GPIOA
+  gpio_init(GPIOA, &gpio_default_config.PAData);
+#endif
+#if STM32_HAS_GPIOB
+  gpio_init(GPIOB, &gpio_default_config.PBData);
 #endif
+#if STM32_HAS_GPIOC
+  gpio_init(GPIOC, &gpio_default_config.PCData);
+#endif
+#if STM32_HAS_GPIOD
+  gpio_init(GPIOD, &gpio_default_config.PDData);
+#endif
+#if STM32_HAS_GPIOE
+  gpio_init(GPIOE, &gpio_default_config.PEData);
+#endif
+#if STM32_HAS_GPIOF
+  gpio_init(GPIOF, &gpio_default_config.PFData);
+#endif
+#if STM32_HAS_GPIOG
+  gpio_init(GPIOG, &gpio_default_config.PGData);
+#endif
+#if STM32_HAS_GPIOH
+  gpio_init(GPIOH, &gpio_default_config.PHData);
+#endif
+#if STM32_HAS_GPIOI
+  gpio_init(GPIOI, &gpio_default_config.PIData);
+#endif
+#if STM32_HAS_GPIOJ
+  gpio_init(GPIOJ, &gpio_default_config.PJData);
+#endif
+#if STM32_HAS_GPIOK
+  gpio_init(GPIOK, &gpio_default_config.PKData);
+#endif
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
 
 /**
  * @brief   Early initialization code.
- * @details This initialization must be performed just after stack setup
- *          and before any other initialization.
+ * @details GPIO ports and system clocks are initialized before everything
+ *          else.
  */
 void __early_init(void) {
 
+  stm32_gpio_init();
   stm32_clock_init();
 }
 
@@ -60,21 +212,21 @@ void __early_init(void) {
 /**
  * @brief   SDC card detection.
  */
-bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
 
   (void)sdcp;
   /* TODO: Fill the implementation.*/
-  return TRUE;
+  return true;
 }
 
 /**
  * @brief   SDC card write protection detection.
  */
-bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) {
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
 
   (void)sdcp;
   /* TODO: Fill the implementation.*/
-  return FALSE;
+  return false;
 }
 #endif /* HAL_USE_SDC */
 
@@ -82,21 +234,21 @@ bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) {
 /**
  * @brief   MMC_SPI card detection.
  */
-bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) {
+bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
 
   (void)mmcp;
   /* TODO: Fill the implementation.*/
-  return TRUE;
+  return true;
 }
 
 /**
  * @brief   MMC_SPI card write protection detection.
  */
-bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) {
+bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
 
   (void)mmcp;
   /* TODO: Fill the implementation.*/
-  return FALSE;
+  return false;
 }
 #endif
 
@@ -105,4 +257,5 @@ bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) {
  * @todo    Add your board-specific code, if any.
  */
 void boardInit(void) {
+
 }
-- 
cgit v1.2.3


From 345e218afd4f8009729dddc6eb541d8ec6a91565 Mon Sep 17 00:00:00 2001
From: Romain Reignier <rom.reignier@gmail.com>
Date: Mon, 12 Mar 2018 21:27:50 +0100
Subject: lib_sci: FIX 'for' loop initial declarations are only allowed in C99
 or C11 mode

---
 os/various/lib_scsi.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'os')

diff --git a/os/various/lib_scsi.c b/os/various/lib_scsi.c
index ea2adda..720a90f 100644
--- a/os/various/lib_scsi.c
+++ b/os/various/lib_scsi.c
@@ -364,7 +364,8 @@ static bool data_read_write10(SCSITarget *scsip, const uint8_t *cmd) {
     size_t bs = bdi.blk_size;
     uint8_t *buf = scsip->config->blkbuf;
 
-    for (size_t i=0; i<req.blk_cnt; i++) {
+    size_t i = 0;
+    for (i=0; i<req.blk_cnt; i++) {
       if (cmd[0] == SCSI_CMD_READ_10) {
         // TODO: block error handling
         blkRead(blkdev, req.first_lba + i, buf, 1);
-- 
cgit v1.2.3


From 6513490986e564fd944ec3e460eb5f91b5cd9c35 Mon Sep 17 00:00:00 2001
From: Romain Reignier <rom.reignier@gmail.com>
Date: Mon, 12 Mar 2018 21:33:11 +0100
Subject: platform: add support for STM32L4 family

---
 os/hal/ports/STM32/STM32L4xx/platform.mk | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
 create mode 100644 os/hal/ports/STM32/STM32L4xx/platform.mk

(limited to 'os')

diff --git a/os/hal/ports/STM32/STM32L4xx/platform.mk b/os/hal/ports/STM32/STM32L4xx/platform.mk
new file mode 100644
index 0000000..b9bbfea
--- /dev/null
+++ b/os/hal/ports/STM32/STM32L4xx/platform.mk
@@ -0,0 +1,21 @@
+include ${CHIBIOS}/os/hal/ports/STM32/STM32L4xx/platform.mk
+
+PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c \
+               ${CHIBIOS_CONTRIB}/os/hal/src/hal_fsmc_sdram.c
+
+PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1 \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/DMA2Dv1 \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1 \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/LTDCv1 \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1 \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/USBHv1 \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD
-- 
cgit v1.2.3


From 424c7a2717fb6b2a847cec5c0060e3236f25e97f Mon Sep 17 00:00:00 2001
From: Fabien Poussin <fabien.poussin@gmail.com>
Date: Wed, 14 Mar 2018 20:15:13 +0100
Subject: Fixed most testhal examples for STM32, updated configs using script.
 Fixed deprecated MS2ST calls.

---
 os/hal/include/hal_community.h               | 2 +-
 os/hal/include/usbh/dev/uvc.h                | 2 +-
 os/hal/ports/KINETIS/LLD/hal_i2c_lld.c       | 2 +-
 os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c     | 2 +-
 os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c | 8 ++++----
 os/hal/ports/STM32/STM32F0xx/platform.mk     | 2 +-
 os/hal/src/hal_ee24xx.c                      | 2 +-
 os/hal/src/usbh/hal_usbh_aoa.c               | 4 ++--
 os/hal/src/usbh/hal_usbh_ftdi.c              | 8 ++++----
 os/hal/src/usbh/hal_usbh_msd.c               | 8 ++++----
 os/various/fatfs_bindings/fatfs.mk           | 2 +-
 11 files changed, 21 insertions(+), 21 deletions(-)

(limited to 'os')

diff --git a/os/hal/include/hal_community.h b/os/hal/include/hal_community.h
index cdedad6..83b1f02 100644
--- a/os/hal/include/hal_community.h
+++ b/os/hal/include/hal_community.h
@@ -48,7 +48,7 @@
 #endif
 
 #if !defined(HAL_USE_QEI)
-#define HAL_USE_QEI                        FALSE
+#define HAL_USE_QEI                         FALSE
 #endif
 
 #if !defined(HAL_USE_RNG)
diff --git a/os/hal/include/usbh/dev/uvc.h b/os/hal/include/usbh/dev/uvc.h
index 817d465..0477312 100644
--- a/os/hal/include/usbh/dev/uvc.h
+++ b/os/hal/include/usbh/dev/uvc.h
@@ -430,7 +430,7 @@ extern "C" {
 
 	static inline msg_t usbhuvcLockAndFetchS(USBHUVCDriver *uvcdp, msg_t *msg, systime_t timeout) {
 		chMtxLockS(&uvcdp->mtx);
-		msg_t ret = chMBFetchS(&uvcdp->mb, msg, timeout);
+		msg_t ret = chMBFetchTimeoutS(&uvcdp->mb, msg, timeout);
 		if (ret != MSG_OK)
 			chMtxUnlockS(&uvcdp->mtx);
 		return ret;
diff --git a/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c b/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c
index c6b3d11..a005c32 100644
--- a/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c
+++ b/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c
@@ -442,7 +442,7 @@ static inline msg_t _i2c_txrx_timeout(I2CDriver *i2cp, i2caddr_t addr,
     /* wait until the bus is released */
     /* Calculating the time window for the timeout on the busy bus condition.*/
     start = osalOsGetSystemTimeX();
-    end = start + OSAL_MS2ST(KINETIS_I2C_BUSY_TIMEOUT);
+    end = start + OSAL_TIME_MS2I(KINETIS_I2C_BUSY_TIMEOUT);
 
     while(true) {
       osalSysLock();
diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c
index 500b2e7..71c6ada 100644
--- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c
+++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c
@@ -159,7 +159,7 @@ void fsmc_stop(FSMCDriver *fsmcp) {
 #if HAL_USE_NAND
       nvicDisableVector(STM32_FSMC_NUMBER);
 #endif
-      rccDisableFSMC(FALSE);
+      rccDisableFSMC();
     }
 #endif /* STM32_FSMC_USE_FSMC1 */
 
diff --git a/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c b/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c
index 4723508..15d8853 100644
--- a/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c
+++ b/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c
@@ -1665,9 +1665,9 @@ usbh_urbstatus_t usbh_lld_root_hub_request(USBHDriver *usbh, uint8_t bmRequestTy
 				 * despite reporting a successful por enable. */
 				uerr("Detected enabled port; resetting OTG core");
 				otg->GAHBCFG = 0;
-				osalThreadSleepS(MS2ST(20));
+				osalThreadSleepS(TIME_MS2I(20));
 				_usbh_start(usbh);				/* this effectively resets the core */
-				osalThreadSleepS(MS2ST(100));	/* during this delay, the core generates connect ISR */
+				osalThreadSleepS(TIME_MS2I(100));	/* during this delay, the core generates connect ISR */
 				uinfo("OTG reset ended");
 				if (otg->HPRT & HPRT_PCSTS) {
 					/* if the device is still connected, don't report a C_CONNECTION flag, which would cause
@@ -1680,9 +1680,9 @@ usbh_urbstatus_t usbh_lld_root_hub_request(USBHDriver *usbh, uint8_t bmRequestTy
 			hprt &= ~(HPRT_PSUSP | HPRT_PENA | HPRT_PCDET | HPRT_PENCHNG | HPRT_POCCHNG);
 			while ((otg->GRSTCTL & GRSTCTL_AHBIDL) == 0);
 			otg->HPRT = hprt | HPRT_PRST;
-			osalThreadSleepS(MS2ST(15));
+			osalThreadSleepS(TIME_MS2I(15));
 			otg->HPRT = hprt;
-			osalThreadSleepS(MS2ST(10));
+			osalThreadSleepS(TIME_MS2I(10));
 			usbh->rootport.lld_c_status |= USBH_PORTSTATUS_C_RESET;
 			osalSysUnlock();
 		} 	break;
diff --git a/os/hal/ports/STM32/STM32F0xx/platform.mk b/os/hal/ports/STM32/STM32F0xx/platform.mk
index 377acdf..0102162 100644
--- a/os/hal/ports/STM32/STM32F0xx/platform.mk
+++ b/os/hal/ports/STM32/STM32F0xx/platform.mk
@@ -2,7 +2,7 @@ include ${CHIBIOS}/os/hal/ports/STM32/STM32F0xx/platform.mk
 
 PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c \
                ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c \
-               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c \
+               ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c
 
 PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1 \
                ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1 \
diff --git a/os/hal/src/hal_ee24xx.c b/os/hal/src/hal_ee24xx.c
index 632ffbb..164530e 100644
--- a/os/hal/src/hal_ee24xx.c
+++ b/os/hal/src/hal_ee24xx.c
@@ -105,7 +105,7 @@ static systime_t calc_timeout(I2CDriver *i2cp, size_t txbytes, size_t rxbytes) {
   tmo = ((txbytes + rxbytes + 1) * bitsinbyte * 1000);
   tmo /= EEPROM_I2C_CLOCK;
   tmo += 10; /* some additional milliseconds to be safer */
-  return MS2ST(tmo);
+  return TIME_MS2I(tmo);
 }
 
 /**
diff --git a/os/hal/src/usbh/hal_usbh_aoa.c b/os/hal/src/usbh/hal_usbh_aoa.c
index 85c3130..5e0fc48 100644
--- a/os/hal/src/usbh/hal_usbh_aoa.c
+++ b/os/hal/src/usbh/hal_usbh_aoa.c
@@ -533,7 +533,7 @@ static void _vt(void *p) {
 	if ((aoacp->iq_counter == 0) && !usbhURBIsBusy(&aoacp->iq_urb)) {
 		_submitInI(aoacp);
 	}
-	chVTSetI(&aoacp->vt, MS2ST(16), _vt, aoacp);
+	chVTSetI(&aoacp->vt, TIME_MS2I(16), _vt, aoacp);
 	osalSysUnlockFromISR();
 }
 
@@ -565,7 +565,7 @@ void usbhaoaChannelStart(USBHAOADriver *aoap) {
 	usbhURBSubmit(&aoacp->iq_urb);
 
 	chVTObjectInit(&aoacp->vt);
-	chVTSet(&aoacp->vt, MS2ST(16), _vt, aoacp);
+	chVTSet(&aoacp->vt, TIME_MS2I(16), _vt, aoacp);
 
 	aoacp->state = USBHAOA_CHANNEL_STATE_READY;
 
diff --git a/os/hal/src/usbh/hal_usbh_ftdi.c b/os/hal/src/usbh/hal_usbh_ftdi.c
index 6fb556d..4def19a 100644
--- a/os/hal/src/usbh/hal_usbh_ftdi.c
+++ b/os/hal/src/usbh/hal_usbh_ftdi.c
@@ -332,7 +332,7 @@ static usbh_urbstatus_t _ftdi_port_control(USBHFTDIPortDriver *ftdipp,
 			wLength
 	};
 
-	return usbhControlRequestExtended(ftdipp->ftdip->dev, &req, buff, NULL, MS2ST(1000));
+	return usbhControlRequestExtended(ftdipp->ftdip->dev, &req, buff, NULL, TIME_MS2I(1000));
 }
 
 static uint32_t _get_divisor(uint32_t baud, usbhftdi_type_t type) {
@@ -394,7 +394,7 @@ static usbh_urbstatus_t _set_baudrate(USBHFTDIPortDriver *ftdipp, uint32_t baudr
 		wIndex,
 		0
 	};
-	return usbhControlRequestExtended(ftdipp->ftdip->dev, &req, NULL, NULL, MS2ST(1000));
+	return usbhControlRequestExtended(ftdipp->ftdip->dev, &req, NULL, NULL, TIME_MS2I(1000));
 }
 
 
@@ -610,7 +610,7 @@ static void _vt(void *p) {
 	if ((ftdipp->iq_counter == 0) && !usbhURBIsBusy(&ftdipp->iq_urb)) {
 		_submitInI(ftdipp);
 	}
-	chVTSetI(&ftdipp->vt, MS2ST(16), _vt, ftdipp);
+	chVTSetI(&ftdipp->vt, TIME_MS2I(16), _vt, ftdipp);
 	osalSysUnlockFromISR();
 }
 
@@ -690,7 +690,7 @@ void usbhftdipStart(USBHFTDIPortDriver *ftdipp, const USBHFTDIPortConfig *config
 	usbhURBSubmit(&ftdipp->iq_urb);
 
 	chVTObjectInit(&ftdipp->vt);
-	chVTSet(&ftdipp->vt, MS2ST(16), _vt, ftdipp);
+	chVTSet(&ftdipp->vt, TIME_MS2I(16), _vt, ftdipp);
 
 	ftdipp->state = USBHFTDIP_STATE_READY;
 	osalMutexUnlock(&ftdipp->ftdip->mtx);
diff --git a/os/hal/src/usbh/hal_usbh_msd.c b/os/hal/src/usbh/hal_usbh_msd.c
index 069c47b..d5bbdeb 100644
--- a/os/hal/src/usbh/hal_usbh_msd.c
+++ b/os/hal/src/usbh/hal_usbh_msd.c
@@ -304,7 +304,7 @@ static msd_bot_result_t _msd_bot_transaction(msd_transaction_t *tran, USBHMassSt
 
 	/* control phase */
 	status = usbhBulkTransfer(&lunp->msdp->epout, tran->cbw,
-					sizeof(*tran->cbw), &actual_len, MS2ST(1000));
+					sizeof(*tran->cbw), &actual_len, TIME_MS2I(1000));
 
 	if (status == USBH_URBSTATUS_CANCELLED) {
 		uerr("\tMSD: Control phase: USBH_URBSTATUS_CANCELLED");
@@ -327,7 +327,7 @@ static msd_bot_result_t _msd_bot_transaction(msd_transaction_t *tran, USBHMassSt
 				ep,
 				data,
 				tran->cbw->dCBWDataTransferLength,
-				&data_actual_len, MS2ST(20000));
+				&data_actual_len, TIME_MS2I(20000));
 
 		if (status == USBH_URBSTATUS_CANCELLED) {
 			uerr("\tMSD: Data phase: USBH_URBSTATUS_CANCELLED");
@@ -349,7 +349,7 @@ static msd_bot_result_t _msd_bot_transaction(msd_transaction_t *tran, USBHMassSt
 
 	/* status phase */
 	status = usbhBulkTransfer(&lunp->msdp->epin, &csw,
-				sizeof(csw), &actual_len, MS2ST(1000));
+				sizeof(csw), &actual_len, TIME_MS2I(1000));
 
 	if (status == USBH_URBSTATUS_STALL) {
 		uwarn("\tMSD: Status phase: USBH_URBSTATUS_STALL, clear halt and retry");
@@ -358,7 +358,7 @@ static msd_bot_result_t _msd_bot_transaction(msd_transaction_t *tran, USBHMassSt
 
 		if (status == USBH_URBSTATUS_OK) {
 			status = usbhBulkTransfer(&lunp->msdp->epin, &csw,
-						sizeof(csw), &actual_len, MS2ST(1000));
+						sizeof(csw), &actual_len, TIME_MS2I(1000));
 		}
 	}
 
diff --git a/os/various/fatfs_bindings/fatfs.mk b/os/various/fatfs_bindings/fatfs.mk
index 238037e..35954b8 100644
--- a/os/various/fatfs_bindings/fatfs.mk
+++ b/os/various/fatfs_bindings/fatfs.mk
@@ -2,6 +2,6 @@
 FATFSSRC = ${CHIBIOS_CONTRIB}/os/various/fatfs_bindings/fatfs_diskio.c \
            ${CHIBIOS}/os/various/fatfs_bindings/fatfs_syscall.c \
            ${CHIBIOS}/ext/fatfs/src/ff.c \
-           ${CHIBIOS}/ext/fatfs/src/option/unicode.c
+           ${CHIBIOS}/ext/fatfs/src/option/ffunicode.c
 
 FATFSINC = ${CHIBIOS}/ext/fatfs/src
-- 
cgit v1.2.3


From 708bb829ea4bfe945ada43047b9089768e065707 Mon Sep 17 00:00:00 2001
From: marcoveeneman <marco-veeneman@hotmail.com>
Date: Fri, 16 Mar 2018 22:16:57 +0100
Subject: Fixed some more warnings

---
 os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c | 2 +-
 os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

(limited to 'os')

diff --git a/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c
index 126959f..2255110 100644
--- a/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c
+++ b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c
@@ -258,7 +258,7 @@ void spi_lld_start(SPIDriver *spip)
       nvicEnableVector(TIVA_SSI1_NUMBER, TIVA_SPI_SSI1_IRQ_PRIORITY);
     }
 #endif
-#if TIVASPI_USE_SSI2
+#if TIVA_SPI_USE_SSI2
     if (&SPID2 == spip) {
       bool b;
       b = udmaChannelAllocate(spip->dmarxnr);
diff --git a/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h
index 4dcf6db..c93c189 100644
--- a/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h
+++ b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h
@@ -156,7 +156,7 @@
 #error "Invalid IRQ priority assigned to SSI2"
 #endif
 
-#if TM4C123x_SPI_USE_SSI3 && \
+#if TIVA_SPI_USE_SSI3 && \
     !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SPI_SSI3_IRQ_PRIORITY)
 #error "Invalid IRQ priority assigned to SSI3"
 #endif
-- 
cgit v1.2.3


From d4d384557df0e8e7a8071553448b0c42849f98c0 Mon Sep 17 00:00:00 2001
From: Fabien Poussin <fabien.poussin@gmail.com>
Date: Tue, 20 Mar 2018 16:04:08 +0100
Subject: Fixes for #138

---
 os/hal/src/hal_ee24xx.c | 24 ++++++++++++------------
 os/hal/src/hal_ee25xx.c | 26 ++++++++++++--------------
 2 files changed, 24 insertions(+), 26 deletions(-)

(limited to 'os')

diff --git a/os/hal/src/hal_ee24xx.c b/os/hal/src/hal_ee24xx.c
index 164530e..725258c 100644
--- a/os/hal/src/hal_ee24xx.c
+++ b/os/hal/src/hal_ee24xx.c
@@ -202,7 +202,7 @@ static void __fitted_write(void *ip, const uint8_t *data, size_t len, uint32_t *
 
   msg_t status = MSG_RESET;
 
-  osalDbgAssert(len != 0, "something broken in hi level part");
+  osalDbgAssert(len > 0, "len must be greater than 0");
 
   status = eeprom_write(((I2CEepromFileStream *)ip)->cfg,
                         eepfs_getposition(ip), data, len);
@@ -214,15 +214,15 @@ static void __fitted_write(void *ip, const uint8_t *data, size_t len, uint32_t *
 
 /**
  * @brief     Write data to EEPROM.
- * @details   Only one EEPROM page can be written at once. So fucntion
+ * @details   Only one EEPROM page can be written at once. So function
  *            splits large data chunks in small EEPROM transactions if needed.
- * @note      To achieve the maximum effectivity use write operations
+ * @note      To achieve the maximum efficiency use write operations
  *            aligned to EEPROM page boundaries.
  */
 static size_t write(void *ip, const uint8_t *bp, size_t n) {
 
-  size_t   len = 0;     /* bytes to be written at one trasaction */
-  uint32_t written; /* total bytes successfully written */
+  size_t   len = 0;      /* bytes to be written per transaction */
+  uint32_t written = 0;  /* total bytes successfully written */
   uint16_t pagesize;
   uint32_t firstpage;
   uint32_t lastpage;
@@ -242,12 +242,10 @@ static size_t write(void *ip, const uint8_t *bp, size_t n) {
   lastpage  = (((EepromFileStream *)ip)->cfg->barrier_low +
                eepfs_getposition(ip) + n - 1) / pagesize;
 
-  written = 0;
-  /* data fitted in single page */
+  /* data fits in single page */
   if (firstpage == lastpage) {
     len = n;
     __fitted_write(ip, bp, len, &written);
-    bp += len;
     return written;
   }
 
@@ -255,17 +253,19 @@ static size_t write(void *ip, const uint8_t *bp, size_t n) {
     /* write first piece of data to first page boundary */
     len =  ((firstpage + 1) * pagesize) - eepfs_getposition(ip);
     len -= ((EepromFileStream *)ip)->cfg->barrier_low;
-    __fitted_write(ip, bp, len, &written);
+    if (__fitted_write(ip, bp, len, &written) != MSG_OK)
+      return written;
     bp += len;
 
-    /* now writes blocks at a size of pages (may be no one) */
+    /* now write page sized blocks (zero or more) */
     while ((n - written) > pagesize) {
       len = pagesize;
-      __fitted_write(ip, bp, len, &written);
+      if (__fitted_write(ip, bp, len, &written) != MSG_OK)
+        return written;
       bp += len;
     }
 
-    /* wrtie tail */
+    /* write tail */
     len = n - written;
     if (len == 0)
       return written;
diff --git a/os/hal/src/hal_ee25xx.c b/os/hal/src/hal_ee25xx.c
index 102aef8..8c35976 100644
--- a/os/hal/src/hal_ee25xx.c
+++ b/os/hal/src/hal_ee25xx.c
@@ -277,7 +277,7 @@ static msg_t __fitted_write(void *ip, const uint8_t *data, size_t len, uint32_t
 
   msg_t status = MSG_RESET;
 
-  osalDbgAssert(len != 0, "something broken in hi level part");
+  osalDbgAssert(len > 0, "len must be greater than 0");
 
   status = ll_eeprom_write(((SPIEepromFileStream *)ip)->cfg,
                            eepfs_getposition(ip), data, len);
@@ -290,15 +290,15 @@ static msg_t __fitted_write(void *ip, const uint8_t *data, size_t len, uint32_t
 
 /**
  * @brief     Write data to EEPROM.
- * @details   Only one EEPROM page can be written at once. So fucntion
+ * @details   Only one EEPROM page can be written at once. So function
  *            splits large data chunks in small EEPROM transactions if needed.
- * @note      To achieve the maximum effectivity use write operations
+ * @note      To achieve the maximum efficiency use write operations
  *            aligned to EEPROM page boundaries.
  */
 static size_t write(void *ip, const uint8_t *bp, size_t n) {
 
-  size_t   len = 0;     /* bytes to be written at one trasaction */
-  uint32_t written; /* total bytes successfully written */
+  size_t   len = 0;      /* bytes to be written per transaction */
+  uint32_t written = 0;  /* total bytes successfully written */
   uint16_t pagesize;
   uint32_t firstpage;
   uint32_t lastpage;
@@ -318,32 +318,30 @@ static size_t write(void *ip, const uint8_t *bp, size_t n) {
   firstpage = (cfg->barrier_low + eepfs_getposition(ip)) / pagesize;
   lastpage  = ((cfg->barrier_low + eepfs_getposition(ip) + n) - 1) / pagesize;
 
-  written = 0;
-  /* data fitted in single page */
+  /* data fits in single page */
   if (firstpage == lastpage) {
     len = n;
     __fitted_write(ip, bp, len, &written);
-    bp += len;
     return written;
   }
+  
   else {
     /* write first piece of data to first page boundary */
     len =  ((firstpage + 1) * pagesize) - eepfs_getposition(ip);
     len -= cfg->barrier_low;
-    __fitted_write(ip, bp, len, &written);
+    if (__fitted_write(ip, bp, len, &written) != MSG_OK)
+      return written;
     bp += len;
 
-    /* now writes blocks at a size of pages (may be no one) */
+    /* now write page sized blocks (zero or more) */
     while ((n - written) > pagesize) {
       len = pagesize;
-      if (__fitted_write(ip, bp, len, &written) != MSG_OK) // Fixed: Would increase bp forever and crash in case of timeouts...
+      if (__fitted_write(ip, bp, len, &written) != MSG_OK)
         return written;
-
       bp += len;
     }
 
-
-    /* wrtie tail */
+    /* write tail */
     len = n - written;
     if (len == 0)
       return written;
-- 
cgit v1.2.3


From d66ce4b75b1904419f62f666fb231201312a4a11 Mon Sep 17 00:00:00 2001
From: Fabien Poussin <fabien.poussin@gmail.com>
Date: Thu, 22 Mar 2018 16:30:35 +0100
Subject: Adding PID library

---
 os/various/pid.c | 191 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 os/various/pid.h |  78 +++++++++++++++++++++++
 2 files changed, 269 insertions(+)
 create mode 100644 os/various/pid.c
 create mode 100644 os/various/pid.h

(limited to 'os')

diff --git a/os/various/pid.c b/os/various/pid.c
new file mode 100644
index 0000000..fa9b92f
--- /dev/null
+++ b/os/various/pid.c
@@ -0,0 +1,191 @@
+/**********************************************************************************************
+* Arduino PID Library - Version 1.2.1
+* by Brett Beauregard <br3ttb@gmail.com> brettbeauregard.com
+* Modified by Fabien Poussin <fabien.poussin@gmail.com> for ChibiOS.
+*
+* This Library is licensed under the MIT License
+**********************************************************************************************/
+
+#include "pid.h"
+#include "osal.h"
+
+#define TIME_MS (osalOsGetSystemTimeX() / (OSAL_ST_FREQUENCY / 1000))
+
+/*Constructor (...)*********************************************************
+*    The parameters specified here are those for for which we can't set up
+*    reliable defaults, so we need to have the user set them.
+***************************************************************************/
+void pid_create(pid_t* p, float* Input, float* Output, float* Setpoint,
+        float Kp, float Ki, float Kd, int POn, int ControllerDirection)
+{
+    p->myOutput = Output;
+    p->myInput = Input;
+    p->mySetpoint = Setpoint;
+    p->inAuto = false;
+
+    pid_setOutputLimits(p, 0, 255); // default output limit corresponds to
+                                    // the arduino pwm limits
+
+    p->SampleTime = 100; // default Controller Sample Time is 100ms
+
+    pid_setControllerDirection(p, ControllerDirection);
+    pid_setTunings(p, Kp, Ki, Kd, POn);
+
+    p->lastTime = TIME_MS - p->SampleTime;
+}
+
+
+/* Compute() **********************************************************************
+*   This, as they say, is where the magic happens.  this function should be called
+*   every time "void loop()" executes.  the function will decide for itself whether a new
+*   pid Output needs to be computed.  returns true when the output is computed,
+*   false when nothing has been done.
+**********************************************************************************/
+bool pid_compute(pid_t* p)
+{
+    if(!p->inAuto) return false;
+    unsigned long now = TIME_MS;
+    unsigned long timeChange = (now - p->lastTime);
+    if(timeChange >= p->SampleTime)
+    {
+        /* Compute all the working error variables */
+        float input = *p->myInput;
+        float error = *p->mySetpoint - input;
+        float dInput = (input - p->lastInput);
+        p->outputSum += (p->ki * error);
+
+        /* Add Proportional on Measurement, if P_ON_M is specified */
+        if(!p->pOnE) p->outputSum -= p->kp * dInput;
+
+        if(p->outputSum > p->outMax) p->outputSum = p->outMax;
+        else if(p->outputSum < p->outMin) p->outputSum = p->outMin;
+
+        /* Add Proportional on Error, if P_ON_E is specified */
+        float output;
+        if(p->pOnE) output = p->kp * error;
+        else output = 0;
+
+        /* Compute Rest of PID Output */
+        output += p->outputSum - p->kd * dInput;
+
+        if(output > p->outMax) output = p->outMax;
+        else if(output < p->outMin) output = p->outMin;
+            *p->myOutput = output;
+
+        /* Remember some variables for next time */
+        p->lastInput = input;
+        p->lastTime = now;
+        return true;
+    }
+    else return false;
+}
+
+/* SetTunings(...)*************************************************************
+* This function allows the controller's dynamic performance to be adjusted.
+* it's called automatically from the constructor, but tunings can also
+* be adjusted on the fly during normal operation
+******************************************************************************/
+void pid_setTunings(pid_t* p, float Kp, float Ki, float Kd, int POn)
+{
+    if (Kp<0 || Ki<0 || Kd<0) return;
+
+    p->pOn = POn;
+    p->pOnE = POn == PID_P_ON_E;
+
+    p->dispKp = Kp; p->dispKi = Ki; p->dispKd = Kd;
+
+    float SampleTimeInSec = ((float)p->SampleTime)/1000;
+    p->kp = Kp;
+    p->ki = Ki * SampleTimeInSec;
+    p->kd = Kd / SampleTimeInSec;
+
+    if(p->controllerDirection == PID_REVERSE)
+    {
+        p->kp = (0 - p->kp);
+        p->ki = (0 - p->ki);
+        p->kd = (0 - p->kd);
+    }
+}
+
+/* SetSampleTime(...) *********************************************************
+* sets the period, in Milliseconds, at which the calculation is performed
+******************************************************************************/
+void pid_setSampleTime(pid_t* p, int NewSampleTime)
+{
+    if (NewSampleTime > 0)
+    {
+        float ratio  = (float)NewSampleTime / (float)p->SampleTime;
+        p->ki *= ratio;
+        p->kd /= ratio;
+        p->SampleTime = (unsigned long)NewSampleTime;
+    }
+}
+
+/* SetOutputLimits(...)****************************************************
+*     This function will be used far more often than SetInputLimits.  while
+*  the input to the controller will generally be in the 0-1023 range (which is
+*  the default already,)  the output will be a little different.  maybe they'll
+*  be doing a time window and will need 0-8000 or something.  or maybe they'll
+*  want to clamp it from 0-125.  who knows.  at any rate, that can all be done
+*  here.
+**************************************************************************/
+void pid_setOutputLimits(pid_t* p, float Min, float Max)
+{
+    if(Min >= Max) return;
+    p->outMin = Min;
+    p->outMax = Max;
+
+    if(p->inAuto)
+    {
+        if(*p->myOutput > p->outMax) *p->myOutput = p->outMax;
+        else if(*p->myOutput < p->outMin) *p->myOutput = p->outMin;
+
+        if(p->outputSum > p->outMax) p->outputSum = p->outMax;
+        else if(p->outputSum < p->outMin) p->outputSum = p->outMin;
+    }
+}
+
+/* SetMode(...)****************************************************************
+* Allows the controller Mode to be set to manual (0) or Automatic (non-zero)
+* when the transition from manual to auto occurs, the controller is
+* automatically initialized
+******************************************************************************/
+void pid_setMode(pid_t* p, int Mode)
+{
+    bool newAuto = (Mode == PID_AUTOMATIC);
+    if(newAuto && !p->inAuto)
+    {  /* we just went from manual to auto */
+        pid_initialize(p);
+    }
+    p->inAuto = newAuto;
+}
+
+/* Initialize()****************************************************************
+*	does all the things that need to happen to ensure a bumpless transfer
+*  from manual to automatic mode.
+******************************************************************************/
+void pid_initialize(pid_t* p)
+{
+    p->outputSum = *p->myOutput;
+    p->lastInput = *p->myInput;
+    if(p->outputSum > p->outMax) p->outputSum = p->outMax;
+    else if(p->outputSum < p->outMin) p->outputSum = p->outMin;
+}
+
+/* SetControllerDirection(...)*************************************************
+* The PID will either be connected to a DIRECT acting process (+Output leads
+* to +Input) or a REVERSE acting process(+Output leads to -Input.)  we need to
+* know which one, because otherwise we may increase the output when we should
+* be decreasing.  This is called from the constructor.
+******************************************************************************/
+void pid_setControllerDirection(pid_t* p, int Direction)
+{
+    if(p->inAuto && Direction != p->controllerDirection)
+    {
+        p->kp = (0 - p->kp);
+        p->ki = (0 - p->ki);
+        p->kd = (0 - p->kd);
+    }
+    p->controllerDirection = Direction;
+}
+
diff --git a/os/various/pid.h b/os/various/pid.h
new file mode 100644
index 0000000..d98df3e
--- /dev/null
+++ b/os/various/pid.h
@@ -0,0 +1,78 @@
+#ifndef PID_h
+#define PID_h
+
+#include "chtypes.h"
+
+//Constants used in some of the functions below
+#define PID_AUTOMATIC 1
+#define PID_MANUAL 0
+#define PID_DIRECT 0
+#define PID_REVERSE 1
+#define PID_P_ON_M 0
+#define PID_P_ON_E 1
+
+
+typedef struct {
+    
+    float dispKp; // * we'll hold on to the tuning parameters in user-entered 
+    float dispKi; //   format for display purposes
+    float dispKd; //
+    
+    float kp;                  // * (P)roportional Tuning Parameter
+    float ki;                  // * (I)ntegral Tuning Parameter
+    float kd;                  // * (D)erivative Tuning Parameter
+
+    int controllerDirection;
+    int pOn;
+
+    float *myInput;              // * Pointers to the Input, Output, and Setpoint variables
+    float *myOutput;             //   This creates a hard link between the variables and the 
+    float *mySetpoint;           //   PID, freeing the user from having to constantly tell us
+                                  //   what these values are.  with pointers we'll just know.
+    unsigned long lastTime;
+    float outputSum;
+    float lastInput;
+
+    unsigned long SampleTime;
+    float outMin;
+    float outMax;
+    
+    bool inAuto;
+    bool pOnE;
+
+} pid_t;
+
+
+//commonly used functions **************************************************************************
+void pid_create(pid_t* p, float* Input, float* Output, float* Setpoint,  // * constructor.  links the PID to the Input, Output, and 
+        float Kp, float Ki, float Kd, int POn, int ControllerDirection);  //   Setpoint.  Initial tuning parameters are also set here.
+                                                                        //   (overload for specifying proportional mode)
+
+void pid_setmode(pid_t* p, int mode);                 // * sets PID to either Manual (0) or Auto (non-0)
+
+bool pid_compute(pid_t* p);               // * performs the PID calculation.  it should be
+                                          //   called every time loop() cycles. ON/OFF and
+                                          //   calculation frequency can be set using SetMode
+                                          //   SetSampleTime respectively
+
+void pid_setOutputLimits(pid_t* p, float Min, float Max); // * clamps the output to a specific range. 0-255 by default, but
+                                                          //   it's likely the user will want to change this depending on
+                                                          //   the application
+
+
+
+//available but not commonly used functions ********************************************************
+void pid_setTunings(pid_t* p, float Kp, float Ki, float Kd, int POn);  // * While most users will set the tunings once in the 
+                                                                      //   constructor, this function gives the user the option
+                                                                      //   of changing tunings during runtime for Adaptive control
+
+void pid_setControllerDirection(pid_t* p, int Direction);  // * Sets the Direction, or "Action" of the controller. DIRECT
+                                                           //   means the output will increase when error is positive. REVERSE
+                                                          //   means the opposite.  it's very unlikely that this will be needed
+                                                          //   once it is set in the constructor.
+void pid_setSampleTime(pid_t* p, int NewSampleTime);  // * sets the frequency, in Milliseconds, with which 
+                                                      //   the PID calculation is performed.  default is 100
+
+void pid_initialize(pid_t* p);
+
+#endif
-- 
cgit v1.2.3


From 12552897f32efc7448810c8ccd70d3c22dadccf7 Mon Sep 17 00:00:00 2001
From: Fabien Poussin <fabien.poussin@gmail.com>
Date: Thu, 22 Mar 2018 16:58:48 +0100
Subject: Cleaning PID lib.

---
 os/various/pid.c | 51 +++++++++++++++++++++++++++------------------------
 os/various/pid.h | 34 +++++++++++++++++-----------------
 2 files changed, 44 insertions(+), 41 deletions(-)

(limited to 'os')

diff --git a/os/various/pid.c b/os/various/pid.c
index fa9b92f..07209ec 100644
--- a/os/various/pid.c
+++ b/os/various/pid.c
@@ -16,22 +16,23 @@
 *    reliable defaults, so we need to have the user set them.
 ***************************************************************************/
 void pid_create(pid_t* p, float* Input, float* Output, float* Setpoint,
-        float Kp, float Ki, float Kd, int POn, int ControllerDirection)
+        float Kp, float Ki, float Kd, int POn, int Direction)
 {
-    p->myOutput = Output;
-    p->myInput = Input;
-    p->mySetpoint = Setpoint;
+    p->output = Output;
+    p->input = Input;
+    p->setPoint = Setpoint;
     p->inAuto = false;
 
     pid_setOutputLimits(p, 0, 255); // default output limit corresponds to
                                     // the arduino pwm limits
 
-    p->SampleTime = 100; // default Controller Sample Time is 100ms
+    p->sampleTime = 100; // default Controller Sample Time is 100ms
 
-    pid_setControllerDirection(p, ControllerDirection);
+    pid_setDirection(p, Direction);
     pid_setTunings(p, Kp, Ki, Kd, POn);
+    pid_initialize(p);
 
-    p->lastTime = TIME_MS - p->SampleTime;
+    p->lastTime = TIME_MS - p->sampleTime;
 }
 
 
@@ -46,11 +47,11 @@ bool pid_compute(pid_t* p)
     if(!p->inAuto) return false;
     unsigned long now = TIME_MS;
     unsigned long timeChange = (now - p->lastTime);
-    if(timeChange >= p->SampleTime)
+    if(timeChange >= p->sampleTime)
     {
         /* Compute all the working error variables */
-        float input = *p->myInput;
-        float error = *p->mySetpoint - input;
+        float input = *p->input;
+        float error = *p->setPoint - input;
         float dInput = (input - p->lastInput);
         p->outputSum += (p->ki * error);
 
@@ -70,7 +71,7 @@ bool pid_compute(pid_t* p)
 
         if(output > p->outMax) output = p->outMax;
         else if(output < p->outMin) output = p->outMin;
-            *p->myOutput = output;
+            *p->output = output;
 
         /* Remember some variables for next time */
         p->lastInput = input;
@@ -87,19 +88,21 @@ bool pid_compute(pid_t* p)
 ******************************************************************************/
 void pid_setTunings(pid_t* p, float Kp, float Ki, float Kd, int POn)
 {
-    if (Kp<0 || Ki<0 || Kd<0) return;
+    if (Kp < 0 || Ki < 0 || Kd < 0) return;
 
     p->pOn = POn;
     p->pOnE = POn == PID_P_ON_E;
 
-    p->dispKp = Kp; p->dispKi = Ki; p->dispKd = Kd;
+    p->dispKp = Kp;
+    p->dispKi = Ki;
+    p->dispKd = Kd;
 
-    float SampleTimeInSec = ((float)p->SampleTime)/1000;
+    float SampleTimeInSec = ((float)p->sampleTime) / 1000.0;
     p->kp = Kp;
     p->ki = Ki * SampleTimeInSec;
     p->kd = Kd / SampleTimeInSec;
 
-    if(p->controllerDirection == PID_REVERSE)
+    if(p->direction == PID_REVERSE)
     {
         p->kp = (0 - p->kp);
         p->ki = (0 - p->ki);
@@ -114,10 +117,10 @@ void pid_setSampleTime(pid_t* p, int NewSampleTime)
 {
     if (NewSampleTime > 0)
     {
-        float ratio  = (float)NewSampleTime / (float)p->SampleTime;
+        float ratio  = (float)NewSampleTime / (float)p->sampleTime;
         p->ki *= ratio;
         p->kd /= ratio;
-        p->SampleTime = (unsigned long)NewSampleTime;
+        p->sampleTime = (unsigned long)NewSampleTime;
     }
 }
 
@@ -137,8 +140,8 @@ void pid_setOutputLimits(pid_t* p, float Min, float Max)
 
     if(p->inAuto)
     {
-        if(*p->myOutput > p->outMax) *p->myOutput = p->outMax;
-        else if(*p->myOutput < p->outMin) *p->myOutput = p->outMin;
+        if(*p->output > p->outMax) *p->output = p->outMax;
+        else if(*p->output < p->outMin) *p->output = p->outMin;
 
         if(p->outputSum > p->outMax) p->outputSum = p->outMax;
         else if(p->outputSum < p->outMin) p->outputSum = p->outMin;
@@ -166,8 +169,8 @@ void pid_setMode(pid_t* p, int Mode)
 ******************************************************************************/
 void pid_initialize(pid_t* p)
 {
-    p->outputSum = *p->myOutput;
-    p->lastInput = *p->myInput;
+    p->outputSum = *p->output;
+    p->lastInput = *p->input;
     if(p->outputSum > p->outMax) p->outputSum = p->outMax;
     else if(p->outputSum < p->outMin) p->outputSum = p->outMin;
 }
@@ -178,14 +181,14 @@ void pid_initialize(pid_t* p)
 * know which one, because otherwise we may increase the output when we should
 * be decreasing.  This is called from the constructor.
 ******************************************************************************/
-void pid_setControllerDirection(pid_t* p, int Direction)
+void pid_setDirection(pid_t* p, int Direction)
 {
-    if(p->inAuto && Direction != p->controllerDirection)
+    if(p->inAuto && Direction != p->direction)
     {
         p->kp = (0 - p->kp);
         p->ki = (0 - p->ki);
         p->kd = (0 - p->kd);
     }
-    p->controllerDirection = Direction;
+    p->direction = Direction;
 }
 
diff --git a/os/various/pid.h b/os/various/pid.h
index d98df3e..d20b35d 100644
--- a/os/various/pid.h
+++ b/os/various/pid.h
@@ -14,26 +14,26 @@
 
 typedef struct {
     
+    float kp;     // * (P)roportional Tuning Parameter
+    float ki;     // * (I)ntegral Tuning Parameter
+    float kd;     // * (D)erivative Tuning Parameter
+    
     float dispKp; // * we'll hold on to the tuning parameters in user-entered 
     float dispKi; //   format for display purposes
     float dispKd; //
-    
-    float kp;                  // * (P)roportional Tuning Parameter
-    float ki;                  // * (I)ntegral Tuning Parameter
-    float kd;                  // * (D)erivative Tuning Parameter
 
-    int controllerDirection;
+    int direction;
     int pOn;
 
-    float *myInput;              // * Pointers to the Input, Output, and Setpoint variables
-    float *myOutput;             //   This creates a hard link between the variables and the 
-    float *mySetpoint;           //   PID, freeing the user from having to constantly tell us
-                                  //   what these values are.  with pointers we'll just know.
+    float *input;              // * Pointers to the Input, Output, and Setpoint variables
+    float *output;             //   This creates a hard link between the variables and the 
+    float *setPoint;           //   PID, freeing the user from having to constantly tell us
+                               //   what these values are.  with pointers we'll just know.
     unsigned long lastTime;
     float outputSum;
     float lastInput;
 
-    unsigned long SampleTime;
+    unsigned long sampleTime;
     float outMin;
     float outMax;
     
@@ -45,15 +45,15 @@ typedef struct {
 
 //commonly used functions **************************************************************************
 void pid_create(pid_t* p, float* Input, float* Output, float* Setpoint,  // * constructor.  links the PID to the Input, Output, and 
-        float Kp, float Ki, float Kd, int POn, int ControllerDirection);  //   Setpoint.  Initial tuning parameters are also set here.
-                                                                        //   (overload for specifying proportional mode)
+                float Kp, float Ki, float Kd, int POn, int Direction);   //   Setpoint.  Initial tuning parameters are also set here.
+                                                                         //   (overload for specifying proportional mode)
 
 void pid_setmode(pid_t* p, int mode);                 // * sets PID to either Manual (0) or Auto (non-0)
 
 bool pid_compute(pid_t* p);               // * performs the PID calculation.  it should be
                                           //   called every time loop() cycles. ON/OFF and
                                           //   calculation frequency can be set using SetMode
-                                          //   SetSampleTime respectively
+                                          //   SetsampleTime respectively
 
 void pid_setOutputLimits(pid_t* p, float Min, float Max); // * clamps the output to a specific range. 0-255 by default, but
                                                           //   it's likely the user will want to change this depending on
@@ -66,10 +66,10 @@ void pid_setTunings(pid_t* p, float Kp, float Ki, float Kd, int POn);  // * Whil
                                                                       //   constructor, this function gives the user the option
                                                                       //   of changing tunings during runtime for Adaptive control
 
-void pid_setControllerDirection(pid_t* p, int Direction);  // * Sets the Direction, or "Action" of the controller. DIRECT
-                                                           //   means the output will increase when error is positive. REVERSE
-                                                          //   means the opposite.  it's very unlikely that this will be needed
-                                                          //   once it is set in the constructor.
+void pid_setDirection(pid_t* p, int Direction);  // * Sets the Direction, or "Action" of the controller. DIRECT
+                                                 //   means the output will increase when error is positive. REVERSE
+                                                 //   means the opposite.  it's very unlikely that this will be needed
+                                                 //   once it is set in the constructor.
 void pid_setSampleTime(pid_t* p, int NewSampleTime);  // * sets the frequency, in Milliseconds, with which 
                                                       //   the PID calculation is performed.  default is 100
 
-- 
cgit v1.2.3


From 9e5aba8bd9da9fbba617f6abc95a4e1a2a841882 Mon Sep 17 00:00:00 2001
From: Fabien Poussin <fabien.poussin@gmail.com>
Date: Thu, 22 Mar 2018 18:16:20 +0100
Subject: Adding basic PID demo.

---
 os/various/pid.c | 4 ++--
 os/various/pid.h | 6 +++---
 2 files changed, 5 insertions(+), 5 deletions(-)

(limited to 'os')

diff --git a/os/various/pid.c b/os/various/pid.c
index 07209ec..f704b29 100644
--- a/os/various/pid.c
+++ b/os/various/pid.c
@@ -55,7 +55,7 @@ bool pid_compute(pid_t* p)
         float dInput = (input - p->lastInput);
         p->outputSum += (p->ki * error);
 
-        /* Add Proportional on Measurement, if P_ON_M is specified */
+        /* Add Proportional on Measurement, if PID_ON_M is specified */
         if(!p->pOnE) p->outputSum -= p->kp * dInput;
 
         if(p->outputSum > p->outMax) p->outputSum = p->outMax;
@@ -91,7 +91,7 @@ void pid_setTunings(pid_t* p, float Kp, float Ki, float Kd, int POn)
     if (Kp < 0 || Ki < 0 || Kd < 0) return;
 
     p->pOn = POn;
-    p->pOnE = POn == PID_P_ON_E;
+    p->pOnE = POn == PID_ON_E;
 
     p->dispKp = Kp;
     p->dispKi = Ki;
diff --git a/os/various/pid.h b/os/various/pid.h
index d20b35d..74d116d 100644
--- a/os/various/pid.h
+++ b/os/various/pid.h
@@ -8,8 +8,8 @@
 #define PID_MANUAL 0
 #define PID_DIRECT 0
 #define PID_REVERSE 1
-#define PID_P_ON_M 0
-#define PID_P_ON_E 1
+#define PID_ON_M 0
+#define PID_ON_E 1
 
 
 typedef struct {
@@ -48,7 +48,7 @@ void pid_create(pid_t* p, float* Input, float* Output, float* Setpoint,  // * co
                 float Kp, float Ki, float Kd, int POn, int Direction);   //   Setpoint.  Initial tuning parameters are also set here.
                                                                          //   (overload for specifying proportional mode)
 
-void pid_setmode(pid_t* p, int mode);                 // * sets PID to either Manual (0) or Auto (non-0)
+void pid_setMode(pid_t* p, int mode);                 // * sets PID to either Manual (0) or Auto (non-0)
 
 bool pid_compute(pid_t* p);               // * performs the PID calculation.  it should be
                                           //   called every time loop() cycles. ON/OFF and
-- 
cgit v1.2.3


From 71fe8e7ced20bbcea503e0ef22e155c09f63a1f7 Mon Sep 17 00:00:00 2001
From: Fabien Poussin <fabien.poussin@gmail.com>
Date: Sun, 25 Mar 2018 04:21:11 +0200
Subject: Renaming PID struct typedef to avoid conflicts

---
 os/various/pid.c | 22 +++++++++++-----------
 os/various/pid.h | 54 +++++++++++++++++++++++++++---------------------------
 2 files changed, 38 insertions(+), 38 deletions(-)

(limited to 'os')

diff --git a/os/various/pid.c b/os/various/pid.c
index f704b29..fee9608 100644
--- a/os/various/pid.c
+++ b/os/various/pid.c
@@ -9,13 +9,13 @@
 #include "pid.h"
 #include "osal.h"
 
-#define TIME_MS (osalOsGetSystemTimeX() / (OSAL_ST_FREQUENCY / 1000))
+#define TIME_MS ((osalOsGetSystemTimeX() * 1000) / OSAL_ST_FREQUENCY )
 
 /*Constructor (...)*********************************************************
 *    The parameters specified here are those for for which we can't set up
 *    reliable defaults, so we need to have the user set them.
 ***************************************************************************/
-void pid_create(pid_t* p, float* Input, float* Output, float* Setpoint,
+void pid_create(pidc_t* p, float* Input, float* Output, float* Setpoint,
         float Kp, float Ki, float Kd, int POn, int Direction)
 {
     p->output = Output;
@@ -23,8 +23,8 @@ void pid_create(pid_t* p, float* Input, float* Output, float* Setpoint,
     p->setPoint = Setpoint;
     p->inAuto = false;
 
-    pid_setOutputLimits(p, 0, 255); // default output limit corresponds to
-                                    // the arduino pwm limits
+    pid_setOutputLimits(p, 0, 4095); // default output limit corresponds to
+                                     // the 12 bit dac limit
 
     p->sampleTime = 100; // default Controller Sample Time is 100ms
 
@@ -42,7 +42,7 @@ void pid_create(pid_t* p, float* Input, float* Output, float* Setpoint,
 *   pid Output needs to be computed.  returns true when the output is computed,
 *   false when nothing has been done.
 **********************************************************************************/
-bool pid_compute(pid_t* p)
+bool pid_compute(pidc_t* p)
 {
     if(!p->inAuto) return false;
     unsigned long now = TIME_MS;
@@ -86,7 +86,7 @@ bool pid_compute(pid_t* p)
 * it's called automatically from the constructor, but tunings can also
 * be adjusted on the fly during normal operation
 ******************************************************************************/
-void pid_setTunings(pid_t* p, float Kp, float Ki, float Kd, int POn)
+void pid_setTunings(pidc_t* p, float Kp, float Ki, float Kd, int POn)
 {
     if (Kp < 0 || Ki < 0 || Kd < 0) return;
 
@@ -113,7 +113,7 @@ void pid_setTunings(pid_t* p, float Kp, float Ki, float Kd, int POn)
 /* SetSampleTime(...) *********************************************************
 * sets the period, in Milliseconds, at which the calculation is performed
 ******************************************************************************/
-void pid_setSampleTime(pid_t* p, int NewSampleTime)
+void pid_setSampleTime(pidc_t* p, int NewSampleTime)
 {
     if (NewSampleTime > 0)
     {
@@ -132,7 +132,7 @@ void pid_setSampleTime(pid_t* p, int NewSampleTime)
 *  want to clamp it from 0-125.  who knows.  at any rate, that can all be done
 *  here.
 **************************************************************************/
-void pid_setOutputLimits(pid_t* p, float Min, float Max)
+void pid_setOutputLimits(pidc_t* p, float Min, float Max)
 {
     if(Min >= Max) return;
     p->outMin = Min;
@@ -153,7 +153,7 @@ void pid_setOutputLimits(pid_t* p, float Min, float Max)
 * when the transition from manual to auto occurs, the controller is
 * automatically initialized
 ******************************************************************************/
-void pid_setMode(pid_t* p, int Mode)
+void pid_setMode(pidc_t* p, int Mode)
 {
     bool newAuto = (Mode == PID_AUTOMATIC);
     if(newAuto && !p->inAuto)
@@ -167,7 +167,7 @@ void pid_setMode(pid_t* p, int Mode)
 *	does all the things that need to happen to ensure a bumpless transfer
 *  from manual to automatic mode.
 ******************************************************************************/
-void pid_initialize(pid_t* p)
+void pid_initialize(pidc_t* p)
 {
     p->outputSum = *p->output;
     p->lastInput = *p->input;
@@ -181,7 +181,7 @@ void pid_initialize(pid_t* p)
 * know which one, because otherwise we may increase the output when we should
 * be decreasing.  This is called from the constructor.
 ******************************************************************************/
-void pid_setDirection(pid_t* p, int Direction)
+void pid_setDirection(pidc_t* p, int Direction)
 {
     if(p->inAuto && Direction != p->direction)
     {
diff --git a/os/various/pid.h b/os/various/pid.h
index 74d116d..49ccd6f 100644
--- a/os/various/pid.h
+++ b/os/various/pid.h
@@ -13,11 +13,11 @@
 
 
 typedef struct {
-    
+
     float kp;     // * (P)roportional Tuning Parameter
     float ki;     // * (I)ntegral Tuning Parameter
     float kd;     // * (D)erivative Tuning Parameter
-    
+
     float dispKp; // * we'll hold on to the tuning parameters in user-entered 
     float dispKi; //   format for display purposes
     float dispKd; //
@@ -36,43 +36,43 @@ typedef struct {
     unsigned long sampleTime;
     float outMin;
     float outMax;
-    
+
     bool inAuto;
     bool pOnE;
 
-} pid_t;
+} pidc_t;
 
 
 //commonly used functions **************************************************************************
-void pid_create(pid_t* p, float* Input, float* Output, float* Setpoint,  // * constructor.  links the PID to the Input, Output, and 
-                float Kp, float Ki, float Kd, int POn, int Direction);   //   Setpoint.  Initial tuning parameters are also set here.
-                                                                         //   (overload for specifying proportional mode)
+void pid_create(pidc_t* p, float* Input, float* Output, float* Setpoint,  // * constructor.  links the PID to the Input, Output, and 
+                float Kp, float Ki, float Kd, int POn, int Direction);    //   Setpoint.  Initial tuning parameters are also set here.
+                                                                          //   (overload for specifying proportional mode)
 
-void pid_setMode(pid_t* p, int mode);                 // * sets PID to either Manual (0) or Auto (non-0)
+void pid_setMode(pidc_t* p, int mode);                 // * sets PID to either Manual (0) or Auto (non-0)
 
-bool pid_compute(pid_t* p);               // * performs the PID calculation.  it should be
-                                          //   called every time loop() cycles. ON/OFF and
-                                          //   calculation frequency can be set using SetMode
-                                          //   SetsampleTime respectively
+bool pid_compute(pidc_t* p);               // * performs the PID calculation.  it should be
+                                           //   called every time loop() cycles. ON/OFF and
+                                           //   calculation frequency can be set using SetMode
+                                           //   SetsampleTime respectively
 
-void pid_setOutputLimits(pid_t* p, float Min, float Max); // * clamps the output to a specific range. 0-255 by default, but
-                                                          //   it's likely the user will want to change this depending on
-                                                          //   the application
+void pid_setOutputLimits(pidc_t* p, float Min, float Max); // * clamps the output to a specific range. 0-255 by default, but
+                                                           //   it's likely the user will want to change this depending on
+                                                           //   the application
 
 
 
 //available but not commonly used functions ********************************************************
-void pid_setTunings(pid_t* p, float Kp, float Ki, float Kd, int POn);  // * While most users will set the tunings once in the 
-                                                                      //   constructor, this function gives the user the option
-                                                                      //   of changing tunings during runtime for Adaptive control
-
-void pid_setDirection(pid_t* p, int Direction);  // * Sets the Direction, or "Action" of the controller. DIRECT
-                                                 //   means the output will increase when error is positive. REVERSE
-                                                 //   means the opposite.  it's very unlikely that this will be needed
-                                                 //   once it is set in the constructor.
-void pid_setSampleTime(pid_t* p, int NewSampleTime);  // * sets the frequency, in Milliseconds, with which 
-                                                      //   the PID calculation is performed.  default is 100
-
-void pid_initialize(pid_t* p);
+void pid_setTunings(pidc_t* p, float Kp, float Ki, float Kd, int POn);  // * While most users will set the tunings once in the 
+                                                                        //   constructor, this function gives the user the option
+                                                                        //   of changing tunings during runtime for Adaptive control
+
+void pid_setDirection(pidc_t* p, int Direction);  // * Sets the Direction, or "Action" of the controller. DIRECT
+                                                  //   means the output will increase when error is positive. REVERSE
+                                                  //   means the opposite.  it's very unlikely that this will be needed
+                                                  //   once it is set in the constructor.
+void pid_setSampleTime(pidc_t* p, int NewSampleTime);  // * sets the frequency, in Milliseconds, with which 
+                                                       //   the PID calculation is performed.  default is 100
+
+void pid_initialize(pidc_t* p);
 
 #endif
-- 
cgit v1.2.3


From b0a75810674d430ca104edda24800ff11073fdcb Mon Sep 17 00:00:00 2001
From: Michael Walker <walkerstop@gmail.com>
Date: Mon, 30 Apr 2018 16:34:26 -0700
Subject: Attempt at Teensy 3.6 support

---
 os/common/ext/CMSIS/KINETIS/MK66F18.h              | 17635 +++++++++++++++++++
 os/common/ext/CMSIS/KINETIS/system_MK66F18.h       |   173 +
 .../startup/ARMCMx/compilers/GCC/ld/MK66FX1M0.ld   |   101 +
 .../ARMCMx/compilers/GCC/mk/startup_MK66F18.mk     |    12 +
 .../startup/ARMCMx/devices/MK66F18/cmparams.h      |    80 +
 os/hal/boards/PJRC_TEENSY_3_6/board.c              |   209 +
 os/hal/boards/PJRC_TEENSY_3_6/board.h              |   345 +
 os/hal/boards/PJRC_TEENSY_3_6/board.mk             |     5 +
 os/hal/ports/KINETIS/LLD/hal_serial_lld.c          |    12 +
 os/hal/ports/KINETIS/LLD/hal_serial_lld.h          |    69 +-
 os/hal/ports/KINETIS/MK66F18/hal_lld.c             |   238 +
 os/hal/ports/KINETIS/MK66F18/hal_lld.h             |   319 +
 os/hal/ports/KINETIS/MK66F18/hal_pwm_lld.c         |   390 +
 os/hal/ports/KINETIS/MK66F18/hal_pwm_lld.h         |   270 +
 os/hal/ports/KINETIS/MK66F18/hal_spi_lld.c         |   539 +
 os/hal/ports/KINETIS/MK66F18/hal_spi_lld.h         |   261 +
 os/hal/ports/KINETIS/MK66F18/kinetis_registry.h    |   165 +
 os/hal/ports/KINETIS/MK66F18/platform.dox          |   365 +
 os/hal/ports/KINETIS/MK66F18/platform.mk           |    18 +
 19 files changed, 21205 insertions(+), 1 deletion(-)
 create mode 100644 os/common/ext/CMSIS/KINETIS/MK66F18.h
 create mode 100644 os/common/ext/CMSIS/KINETIS/system_MK66F18.h
 create mode 100644 os/common/startup/ARMCMx/compilers/GCC/ld/MK66FX1M0.ld
 create mode 100644 os/common/startup/ARMCMx/compilers/GCC/mk/startup_MK66F18.mk
 create mode 100644 os/common/startup/ARMCMx/devices/MK66F18/cmparams.h
 create mode 100644 os/hal/boards/PJRC_TEENSY_3_6/board.c
 create mode 100644 os/hal/boards/PJRC_TEENSY_3_6/board.h
 create mode 100644 os/hal/boards/PJRC_TEENSY_3_6/board.mk
 create mode 100644 os/hal/ports/KINETIS/MK66F18/hal_lld.c
 create mode 100644 os/hal/ports/KINETIS/MK66F18/hal_lld.h
 create mode 100644 os/hal/ports/KINETIS/MK66F18/hal_pwm_lld.c
 create mode 100644 os/hal/ports/KINETIS/MK66F18/hal_pwm_lld.h
 create mode 100644 os/hal/ports/KINETIS/MK66F18/hal_spi_lld.c
 create mode 100644 os/hal/ports/KINETIS/MK66F18/hal_spi_lld.h
 create mode 100644 os/hal/ports/KINETIS/MK66F18/kinetis_registry.h
 create mode 100644 os/hal/ports/KINETIS/MK66F18/platform.dox
 create mode 100644 os/hal/ports/KINETIS/MK66F18/platform.mk

(limited to 'os')

diff --git a/os/common/ext/CMSIS/KINETIS/MK66F18.h b/os/common/ext/CMSIS/KINETIS/MK66F18.h
new file mode 100644
index 0000000..b795a23
--- /dev/null
+++ b/os/common/ext/CMSIS/KINETIS/MK66F18.h
@@ -0,0 +1,17635 @@
+/*
+** ###################################################################
+**     Processors:          MK66FN2M0VLQ18
+**                          MK66FN2M0VMD18
+**                          MK66FX1M0VLQ18
+**                          MK66FX1M0VMD18
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    K66P144M180SF5RMV2, Rev. 1, Mar 2015
+**     Version:             rev. 3.0, 2015-03-25
+**     Build:               b171205
+**
+**     Abstract:
+**         CMSIS Peripheral Access Layer for MK66F18
+**
+**     The Clear BSD License
+**     Copyright 1997-2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2017 NXP
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without
+**     modification, are permitted (subject to the limitations in the
+**     disclaimer below) provided that the following conditions are met:
+**
+**     * Redistributions of source code must retain the above copyright
+**       notice, this list of conditions and the following disclaimer.
+**
+**     * Redistributions in binary form must reproduce the above copyright
+**       notice, this list of conditions and the following disclaimer in the
+**       documentation and/or other materials provided with the distribution.
+**
+**     * Neither the name of the copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from
+**       this software without specific prior written permission.
+**
+**     NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
+**     GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+**     HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+**     WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+**     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+**     LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+**     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+**     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+**     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+**     WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+**     OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+**     IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-09-02)
+**         Initial version.
+**     - rev. 2.0 (2014-02-17)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**         Update according to reference manual rev. 2
+**     - rev. 2.1 (2014-04-16)
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.2 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.3 (2014-11-20)
+**         Update according to reverence manual K65P169M180SF5RMV2_NDA, Rev. 0 Draft A, October 2014.
+**         Update of SystemInit() to use 16MHz external crystal.
+**     - rev. 2.4 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**     - rev. 3.0 (2015-03-25)
+**         Registers updated according to the reference manual revision 1, March 2015
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK66F18.h
+ * @version 3.0
+ * @date 2015-03-25
+ * @brief CMSIS Peripheral Access Layer for MK66F18
+ *
+ * CMSIS Peripheral Access Layer for MK66F18
+ */
+
+#ifndef _MK66F18_H_
+#define _MK66F18_H_                              /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0300U
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
+
+/**
+ * @brief Macro to calculate address of an aliased word in the peripheral
+ *        bitband area for a peripheral register and bit (bit band region 0x40000000 to
+ *        0x400FFFFF).
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return  Address of the aliased word in the peripheral bitband area.
+ */
+#define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ *        be used for peripherals with 32bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
+#define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit)))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ *        be used for peripherals with 16bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
+/**
+ * @brief Macro to access a single bit of a peripheral register (bit band region
+ *        0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
+ *        be used for peripherals with 8bit access allowed.
+ * @param Reg Register to access.
+ * @param Bit Bit number to access.
+ * @return Value of the targeted bit in the bit band region.
+ */
+#define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
+
+/* ----------------------------------------------------------------------------
+   -- Interrupt vector numbers
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 116                /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+  /* Auxiliary constants */
+  NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
+
+  /* Core interrupts */
+  NonMaskableInt_IRQn          = -14,              /**< Non Maskable Interrupt */
+  HardFault_IRQn               = -13,              /**< Cortex-M4 SV Hard Fault Interrupt */
+  MemoryManagement_IRQn        = -12,              /**< Cortex-M4 Memory Management Interrupt */
+  BusFault_IRQn                = -11,              /**< Cortex-M4 Bus Fault Interrupt */
+  UsageFault_IRQn              = -10,              /**< Cortex-M4 Usage Fault Interrupt */
+  SVCall_IRQn                  = -5,               /**< Cortex-M4 SV Call Interrupt */
+  DebugMonitor_IRQn            = -4,               /**< Cortex-M4 Debug Monitor Interrupt */
+  PendSV_IRQn                  = -2,               /**< Cortex-M4 Pend SV Interrupt */
+  SysTick_IRQn                 = -1,               /**< Cortex-M4 System Tick Interrupt */
+
+  /* Device specific interrupts */
+  DMA0_DMA16_IRQn              = 0,                /**< DMA Channel 0, 16 Transfer Complete */
+  DMA1_DMA17_IRQn              = 1,                /**< DMA Channel 1, 17 Transfer Complete */
+  DMA2_DMA18_IRQn              = 2,                /**< DMA Channel 2, 18 Transfer Complete */
+  DMA3_DMA19_IRQn              = 3,                /**< DMA Channel 3, 19 Transfer Complete */
+  DMA4_DMA20_IRQn              = 4,                /**< DMA Channel 4, 20 Transfer Complete */
+  DMA5_DMA21_IRQn              = 5,                /**< DMA Channel 5, 21 Transfer Complete */
+  DMA6_DMA22_IRQn              = 6,                /**< DMA Channel 6, 22 Transfer Complete */
+  DMA7_DMA23_IRQn              = 7,                /**< DMA Channel 7, 23 Transfer Complete */
+  DMA8_DMA24_IRQn              = 8,                /**< DMA Channel 8, 24 Transfer Complete */
+  DMA9_DMA25_IRQn              = 9,                /**< DMA Channel 9, 25 Transfer Complete */
+  DMA10_DMA26_IRQn             = 10,               /**< DMA Channel 10, 26 Transfer Complete */
+  DMA11_DMA27_IRQn             = 11,               /**< DMA Channel 11, 27 Transfer Complete */
+  DMA12_DMA28_IRQn             = 12,               /**< DMA Channel 12, 28 Transfer Complete */
+  DMA13_DMA29_IRQn             = 13,               /**< DMA Channel 13, 29 Transfer Complete */
+  DMA14_DMA30_IRQn             = 14,               /**< DMA Channel 14, 30 Transfer Complete */
+  DMA15_DMA31_IRQn             = 15,               /**< DMA Channel 15, 31 Transfer Complete */
+  DMA_Error_IRQn               = 16,               /**< DMA Error Interrupt */
+  MCM_IRQn                     = 17,               /**< Normal Interrupt */
+  FTFE_IRQn                    = 18,               /**< FTFE Command complete interrupt */
+  Read_Collision_IRQn          = 19,               /**< Read Collision Interrupt */
+  LVD_LVW_IRQn                 = 20,               /**< Low Voltage Detect, Low Voltage Warning */
+  LLWU_IRQn                    = 21,               /**< Low Leakage Wakeup Unit */
+  WDOG_EWM_IRQn                = 22,               /**< WDOG Interrupt */
+  RNG_IRQn                     = 23,               /**< RNG Interrupt */
+  I2C0_IRQn                    = 24,               /**< I2C0 interrupt */
+  I2C1_IRQn                    = 25,               /**< I2C1 interrupt */
+  SPI0_IRQn                    = 26,               /**< SPI0 Interrupt */
+  SPI1_IRQn                    = 27,               /**< SPI1 Interrupt */
+  I2S0_Tx_IRQn                 = 28,               /**< I2S0 transmit interrupt */
+  I2S0_Rx_IRQn                 = 29,               /**< I2S0 receive interrupt */
+  Reserved46_IRQn              = 30,               /**< Reserved interrupt 46 */
+  UART0_RX_TX_IRQn             = 31,               /**< UART0 Receive/Transmit interrupt */
+  UART0_ERR_IRQn               = 32,               /**< UART0 Error interrupt */
+  UART1_RX_TX_IRQn             = 33,               /**< UART1 Receive/Transmit interrupt */
+  UART1_ERR_IRQn               = 34,               /**< UART1 Error interrupt */
+  UART2_RX_TX_IRQn             = 35,               /**< UART2 Receive/Transmit interrupt */
+  UART2_ERR_IRQn               = 36,               /**< UART2 Error interrupt */
+  UART3_RX_TX_IRQn             = 37,               /**< UART3 Receive/Transmit interrupt */
+  UART3_ERR_IRQn               = 38,               /**< UART3 Error interrupt */
+  ADC0_IRQn                    = 39,               /**< ADC0 interrupt */
+  CMP0_IRQn                    = 40,               /**< CMP0 interrupt */
+  CMP1_IRQn                    = 41,               /**< CMP1 interrupt */
+  FTM0_IRQn                    = 42,               /**< FTM0 fault, overflow and channels interrupt */
+  FTM1_IRQn                    = 43,               /**< FTM1 fault, overflow and channels interrupt */
+  FTM2_IRQn                    = 44,               /**< FTM2 fault, overflow and channels interrupt */
+  CMT_IRQn                     = 45,               /**< CMT interrupt */
+  RTC_IRQn                     = 46,               /**< RTC interrupt */
+  RTC_Seconds_IRQn             = 47,               /**< RTC seconds interrupt */
+  PIT0_IRQn                    = 48,               /**< PIT timer channel 0 interrupt */
+  PIT1_IRQn                    = 49,               /**< PIT timer channel 1 interrupt */
+  PIT2_IRQn                    = 50,               /**< PIT timer channel 2 interrupt */
+  PIT3_IRQn                    = 51,               /**< PIT timer channel 3 interrupt */
+  PDB0_IRQn                    = 52,               /**< PDB0 Interrupt */
+  USB_OTG_IRQn                 = 53,               /**< USB0 interrupt */
+  USBDCD_IRQn                  = 54,               /**< USBDCD Interrupt */
+  Reserved71_IRQn              = 55,               /**< Reserved interrupt 71 */
+  DAC0_IRQn                    = 56,               /**< DAC0 interrupt */
+  MCG_IRQn                     = 57,               /**< MCG Interrupt */
+  LPTMR0_IRQn                  = 58,               /**< LPTimer interrupt */
+  PORTA_IRQn                   = 59,               /**< Port A interrupt */
+  PORTB_IRQn                   = 60,               /**< Port B interrupt */
+  PORTC_IRQn                   = 61,               /**< Port C interrupt */
+  PORTD_IRQn                   = 62,               /**< Port D interrupt */
+  PORTE_IRQn                   = 63,               /**< Port E interrupt */
+  SWI_IRQn                     = 64,               /**< Software interrupt */
+  SPI2_IRQn                    = 65,               /**< SPI2 Interrupt */
+  UART4_RX_TX_IRQn             = 66,               /**< UART4 Receive/Transmit interrupt */
+  UART4_ERR_IRQn               = 67,               /**< UART4 Error interrupt */
+  Reserved84_IRQn              = 68,               /**< Reserved interrupt 84 */
+  Reserved85_IRQn              = 69,               /**< Reserved interrupt 85 */
+  CMP2_IRQn                    = 70,               /**< CMP2 interrupt */
+  FTM3_IRQn                    = 71,               /**< FTM3 fault, overflow and channels interrupt */
+  DAC1_IRQn                    = 72,               /**< DAC1 interrupt */
+  ADC1_IRQn                    = 73,               /**< ADC1 interrupt */
+  I2C2_IRQn                    = 74,               /**< I2C2 interrupt */
+  CAN0_ORed_Message_buffer_IRQn = 75,              /**< CAN0 OR'd message buffers interrupt */
+  CAN0_Bus_Off_IRQn            = 76,               /**< CAN0 bus off interrupt */
+  CAN0_Error_IRQn              = 77,               /**< CAN0 error interrupt */
+  CAN0_Tx_Warning_IRQn         = 78,               /**< CAN0 Tx warning interrupt */
+  CAN0_Rx_Warning_IRQn         = 79,               /**< CAN0 Rx warning interrupt */
+  CAN0_Wake_Up_IRQn            = 80,               /**< CAN0 wake up interrupt */
+  SDHC_IRQn                    = 81,               /**< SDHC interrupt */
+  ENET_1588_Timer_IRQn         = 82,               /**< Ethernet MAC IEEE 1588 Timer Interrupt */
+  ENET_Transmit_IRQn           = 83,               /**< Ethernet MAC Transmit Interrupt */
+  ENET_Receive_IRQn            = 84,               /**< Ethernet MAC Receive Interrupt */
+  ENET_Error_IRQn              = 85,               /**< Ethernet MAC Error and miscelaneous Interrupt */
+  LPUART0_IRQn                 = 86,               /**< LPUART0 status/error interrupt */
+  TSI0_IRQn                    = 87,               /**< TSI0 interrupt */
+  TPM1_IRQn                    = 88,               /**< TPM1 fault, overflow and channels interrupt */
+  TPM2_IRQn                    = 89,               /**< TPM2 fault, overflow and channels interrupt */
+  USBHSDCD_IRQn                = 90,               /**< USBHSDCD, USBHS Phy Interrupt */
+  I2C3_IRQn                    = 91,               /**< I2C3 interrupt */
+  CMP3_IRQn                    = 92,               /**< CMP3 interrupt */
+  USBHS_IRQn                   = 93,               /**< USB high speed OTG interrupt */
+  CAN1_ORed_Message_buffer_IRQn = 94,              /**< CAN1 OR'd message buffers interrupt */
+  CAN1_Bus_Off_IRQn            = 95,               /**< CAN1 bus off interrupt */
+  CAN1_Error_IRQn              = 96,               /**< CAN1 error interrupt */
+  CAN1_Tx_Warning_IRQn         = 97,               /**< CAN1 Tx warning interrupt */
+  CAN1_Rx_Warning_IRQn         = 98,               /**< CAN1 Rx warning interrupt */
+  CAN1_Wake_Up_IRQn            = 99                /**< CAN1 wake up interrupt */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+   -- Cortex M4 Core Configuration
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT                  0         /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS               4         /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
+
+#include "core_cm4.h"                  /* Core Peripheral Access Layer */
+#include "system_MK66F18.h"            /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+   -- Mapping Information
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Mapping_Information Mapping Information
+ * @{
+ */
+
+/** Mapping Information */
+/*!
+ * @addtogroup edma_request
+ * @{
+ */
+
+/*******************************************************************************
+ * Definitions
+ ******************************************************************************/
+
+/*!
+ * @brief Structure for the DMA hardware request
+ *
+ * Defines the structure for the DMA hardware request collections. The user can configure the
+ * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
+ * of the hardware request varies according  to the to SoC.
+ */
+typedef enum _dma_request_source
+{
+    kDmaRequestMux0Disable          = 0|0x100U,    /**< DMAMUX TriggerDisabled. */
+    kDmaRequestMux0TSI0             = 1|0x100U,    /**< TSI0. */
+    kDmaRequestMux0UART0Rx          = 2|0x100U,    /**< UART0 Receive. */
+    kDmaRequestMux0UART0Tx          = 3|0x100U,    /**< UART0 Transmit. */
+    kDmaRequestMux0UART1Rx          = 4|0x100U,    /**< UART1 Receive. */
+    kDmaRequestMux0UART1Tx          = 5|0x100U,    /**< UART1 Transmit. */
+    kDmaRequestMux0UART2Rx          = 6|0x100U,    /**< UART2 Receive. */
+    kDmaRequestMux0UART2Tx          = 7|0x100U,    /**< UART2 Transmit. */
+    kDmaRequestMux0UART3Rx          = 8|0x100U,    /**< UART3 Receive. */
+    kDmaRequestMux0UART3Tx          = 9|0x100U,    /**< UART3 Transmit. */
+    kDmaRequestMux0UART4            = 10|0x100U,   /**< UART4 Transmit or Receive. */
+    kDmaRequestMux0Reserved11       = 11|0x100U,   /**< Reserved11 */
+    kDmaRequestMux0I2S0Rx           = 12|0x100U,   /**< I2S0 Receive. */
+    kDmaRequestMux0I2S0Tx           = 13|0x100U,   /**< I2S0 Transmit. */
+    kDmaRequestMux0SPI0Rx           = 14|0x100U,   /**< SPI0 Receive. */
+    kDmaRequestMux0SPI0Tx           = 15|0x100U,   /**< SPI0 Transmit. */
+    kDmaRequestMux0SPI1Rx           = 16|0x100U,   /**< SPI1 Receive. */
+    kDmaRequestMux0SPI1Tx           = 17|0x100U,   /**< SPI1 Transmit. */
+    kDmaRequestMux0I2C0I2C3         = 18|0x100U,   /**< I2C0 and I2C3. */
+    kDmaRequestMux0I2C0             = 18|0x100U,   /**< I2C0 and I2C3. */
+    kDmaRequestMux0I2C3             = 18|0x100U,   /**< I2C0 and I2C3. */
+    kDmaRequestMux0I2C1I2C2         = 19|0x100U,   /**< I2C1 and I2C2. */
+    kDmaRequestMux0I2C1             = 19|0x100U,   /**< I2C1 and I2C2. */
+    kDmaRequestMux0I2C2             = 19|0x100U,   /**< I2C1 and I2C2. */
+    kDmaRequestMux0FTM0Channel0     = 20|0x100U,   /**< FTM0 C0V. */
+    kDmaRequestMux0FTM0Channel1     = 21|0x100U,   /**< FTM0 C1V. */
+    kDmaRequestMux0FTM0Channel2     = 22|0x100U,   /**< FTM0 C2V. */
+    kDmaRequestMux0FTM0Channel3     = 23|0x100U,   /**< FTM0 C3V. */
+    kDmaRequestMux0FTM0Channel4     = 24|0x100U,   /**< FTM0 C4V. */
+    kDmaRequestMux0FTM0Channel5     = 25|0x100U,   /**< FTM0 C5V. */
+    kDmaRequestMux0FTM0Channel6     = 26|0x100U,   /**< FTM0 C6V. */
+    kDmaRequestMux0FTM0Channel7     = 27|0x100U,   /**< FTM0 C7V. */
+    kDmaRequestMux0FTM1TPM1Channel0 = 28|0x100U,   /**< FTM1 C0V and TPM1 C0V. */
+    kDmaRequestMux0FTM1Channel0     = 28|0x100U,   /**< FTM1 C0V and TPM1 C0V. */
+    kDmaRequestMux0TPM1Channel0     = 28|0x100U,   /**< FTM1 C0V and TPM1 C0V. */
+    kDmaRequestMux0FTM1TPM1Channel1 = 29|0x100U,   /**< FTM1 C1V and TPM1 C1V. */
+    kDmaRequestMux0FTM1Channel1     = 29|0x100U,   /**< FTM1 C1V and TPM1 C1V. */
+    kDmaRequestMux0TPM1Channel1     = 29|0x100U,   /**< FTM1 C1V and TPM1 C1V. */
+    kDmaRequestMux0FTM2TPM2Channel0 = 30|0x100U,   /**< FTM2 C0V and TPM2 C0V. */
+    kDmaRequestMux0FTM2Channel0     = 30|0x100U,   /**< FTM2 C0V and TPM2 C0V. */
+    kDmaRequestMux0TPM2Channel0     = 30|0x100U,   /**< FTM2 C0V and TPM2 C0V. */
+    kDmaRequestMux0FTM2TPM2Channel1 = 31|0x100U,   /**< FTM2 C1V and TPM2 C1V. */
+    kDmaRequestMux0FTM2Channel1     = 31|0x100U,   /**< FTM2 C1V and TPM2 C1V. */
+    kDmaRequestMux0TPM2Channel1     = 31|0x100U,   /**< FTM2 C1V and TPM2 C1V. */
+    kDmaRequestMux0FTM3Channel0     = 32|0x100U,   /**< FTM3 C0V. */
+    kDmaRequestMux0FTM3Channel1     = 33|0x100U,   /**< FTM3 C1V. */
+    kDmaRequestMux0FTM3Channel2     = 34|0x100U,   /**< FTM3 C2V. */
+    kDmaRequestMux0FTM3Channel3     = 35|0x100U,   /**< FTM3 C3V. */
+    kDmaRequestMux0FTM3Channel4     = 36|0x100U,   /**< FTM3 C4V. */
+    kDmaRequestMux0FTM3Channel5     = 37|0x100U,   /**< FTM3 C5V. */
+    kDmaRequestMux0FTM3Channel6SPI2Rx = 38|0x100U, /**< FTM3 C6V and SPI2 Receive. */
+    kDmaRequestMux0FTM3Channel6     = 38|0x100U,   /**< FTM3 C6V and SPI2 Receive. */
+    kDmaRequestMux0SPI2Rx           = 38|0x100U,   /**< FTM3 C6V and SPI2 Receive. */
+    kDmaRequestMux0FTM3Channel7SPI2Tx = 39|0x100U, /**< FTM3 C7V and SPI2 Transmit. */
+    kDmaRequestMux0FTM3Channel7     = 39|0x100U,   /**< FTM3 C7V and SPI2 Transmit. */
+    kDmaRequestMux0SPI2Tx           = 39|0x100U,   /**< FTM3 C7V and SPI2 Transmit. */
+    kDmaRequestMux0ADC0             = 40|0x100U,   /**< ADC0. */
+    kDmaRequestMux0ADC1             = 41|0x100U,   /**< ADC1. */
+    kDmaRequestMux0CMP0             = 42|0x100U,   /**< CMP0. */
+    kDmaRequestMux0CMP1             = 43|0x100U,   /**< CMP1. */
+    kDmaRequestMux0CMP2CMP3         = 44|0x100U,   /**< CMP2 and CMP3. */
+    kDmaRequestMux0CMP2             = 44|0x100U,   /**< CMP2 and CMP3. */
+    kDmaRequestMux0CMP3             = 44|0x100U,   /**< CMP2 and CMP3. */
+    kDmaRequestMux0DAC0             = 45|0x100U,   /**< DAC0. */
+    kDmaRequestMux0DAC1             = 46|0x100U,   /**< DAC1. */
+    kDmaRequestMux0CMT              = 47|0x100U,   /**< CMT. */
+    kDmaRequestMux0PDB              = 48|0x100U,   /**< PDB0. */
+    kDmaRequestMux0PortA            = 49|0x100U,   /**< PTA. */
+    kDmaRequestMux0PortB            = 50|0x100U,   /**< PTB. */
+    kDmaRequestMux0PortC            = 51|0x100U,   /**< PTC. */
+    kDmaRequestMux0PortD            = 52|0x100U,   /**< PTD. */
+    kDmaRequestMux0PortE            = 53|0x100U,   /**< PTE. */
+    kDmaRequestMux0IEEE1588Timer0   = 54|0x100U,   /**< ENET IEEE 1588 timer 0. */
+    kDmaRequestMux0IEEE1588Timer1TPM1Overflow = 55|0x100U, /**< ENET IEEE 1588 timer 1 and TPM1. */
+    kDmaRequestMux0IEEE1588Timer1   = 55|0x100U,   /**< ENET IEEE 1588 timer 1 and TPM1. */
+    kDmaRequestMux0TPM1Overflow     = 55|0x100U,   /**< ENET IEEE 1588 timer 1 and TPM1. */
+    kDmaRequestMux0IEEE1588Timer2TPM2Overflow = 56|0x100U, /**< ENET IEEE 1588 timer 2 and TPM2. */
+    kDmaRequestMux0IEEE1588Timer2   = 56|0x100U,   /**< ENET IEEE 1588 timer 2 and TPM2. */
+    kDmaRequestMux0TPM2Overflow     = 56|0x100U,   /**< ENET IEEE 1588 timer 2 and TPM2. */
+    kDmaRequestMux0IEEE1588Timer3   = 57|0x100U,   /**< ENET IEEE 1588 timer 3. */
+    kDmaRequestMux0LPUART0Rx        = 58|0x100U,   /**< LPUART0 Receive. */
+    kDmaRequestMux0LPUART0Tx        = 59|0x100U,   /**< LPUART0 Transmit. */
+    kDmaRequestMux0AlwaysOn60       = 60|0x100U,   /**< DMAMUX Always Enabled slot. */
+    kDmaRequestMux0AlwaysOn61       = 61|0x100U,   /**< DMAMUX Always Enabled slot. */
+    kDmaRequestMux0AlwaysOn62       = 62|0x100U,   /**< DMAMUX Always Enabled slot. */
+    kDmaRequestMux0AlwaysOn63       = 63|0x100U,   /**< DMAMUX Always Enabled slot. */
+} dma_request_source_t;
+
+/* @} */
+
+
+/*!
+ * @}
+ */ /* end of group Mapping_Information */
+
+
+/* ----------------------------------------------------------------------------
+   -- Device Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic push
+  #else
+    #pragma push
+    #pragma anon_unions
+  #endif
+#elif defined(__CWCC__)
+  #pragma push
+  #pragma cpp_extensions on
+#elif defined(__GNUC__)
+  /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=extended
+#else
+  #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+   -- ADC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC1[2];                            /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
+  __IO uint32_t CFG1;                              /**< ADC Configuration Register 1, offset: 0x8 */
+  __IO uint32_t CFG2;                              /**< ADC Configuration Register 2, offset: 0xC */
+  __I  uint32_t R[2];                              /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
+  __IO uint32_t CV1;                               /**< Compare Value Registers, offset: 0x18 */
+  __IO uint32_t CV2;                               /**< Compare Value Registers, offset: 0x1C */
+  __IO uint32_t SC2;                               /**< Status and Control Register 2, offset: 0x20 */
+  __IO uint32_t SC3;                               /**< Status and Control Register 3, offset: 0x24 */
+  __IO uint32_t OFS;                               /**< ADC Offset Correction Register, offset: 0x28 */
+  __IO uint32_t PG;                                /**< ADC Plus-Side Gain Register, offset: 0x2C */
+  __IO uint32_t MG;                                /**< ADC Minus-Side Gain Register, offset: 0x30 */
+  __IO uint32_t CLPD;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
+  __IO uint32_t CLPS;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
+  __IO uint32_t CLP4;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
+  __IO uint32_t CLP3;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
+  __IO uint32_t CLP2;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
+  __IO uint32_t CLP1;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
+  __IO uint32_t CLP0;                              /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t CLMD;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
+  __IO uint32_t CLMS;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
+  __IO uint32_t CLM4;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
+  __IO uint32_t CLM3;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
+  __IO uint32_t CLM2;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
+  __IO uint32_t CLM1;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
+  __IO uint32_t CLM0;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ADC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/*! @name SC1 - ADC Status and Control Registers 1 */
+#define ADC_SC1_ADCH_MASK                        (0x1FU)
+#define ADC_SC1_ADCH_SHIFT                       (0U)
+#define ADC_SC1_ADCH(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
+#define ADC_SC1_DIFF_MASK                        (0x20U)
+#define ADC_SC1_DIFF_SHIFT                       (5U)
+#define ADC_SC1_DIFF(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
+#define ADC_SC1_AIEN_MASK                        (0x40U)
+#define ADC_SC1_AIEN_SHIFT                       (6U)
+#define ADC_SC1_AIEN(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
+#define ADC_SC1_COCO_MASK                        (0x80U)
+#define ADC_SC1_COCO_SHIFT                       (7U)
+#define ADC_SC1_COCO(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
+
+/* The count of ADC_SC1 */
+#define ADC_SC1_COUNT                            (2U)
+
+/*! @name CFG1 - ADC Configuration Register 1 */
+#define ADC_CFG1_ADICLK_MASK                     (0x3U)
+#define ADC_CFG1_ADICLK_SHIFT                    (0U)
+#define ADC_CFG1_ADICLK(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
+#define ADC_CFG1_MODE_MASK                       (0xCU)
+#define ADC_CFG1_MODE_SHIFT                      (2U)
+#define ADC_CFG1_MODE(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
+#define ADC_CFG1_ADLSMP_MASK                     (0x10U)
+#define ADC_CFG1_ADLSMP_SHIFT                    (4U)
+#define ADC_CFG1_ADLSMP(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
+#define ADC_CFG1_ADIV_MASK                       (0x60U)
+#define ADC_CFG1_ADIV_SHIFT                      (5U)
+#define ADC_CFG1_ADIV(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
+#define ADC_CFG1_ADLPC_MASK                      (0x80U)
+#define ADC_CFG1_ADLPC_SHIFT                     (7U)
+#define ADC_CFG1_ADLPC(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
+
+/*! @name CFG2 - ADC Configuration Register 2 */
+#define ADC_CFG2_ADLSTS_MASK                     (0x3U)
+#define ADC_CFG2_ADLSTS_SHIFT                    (0U)
+#define ADC_CFG2_ADLSTS(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
+#define ADC_CFG2_ADHSC_MASK                      (0x4U)
+#define ADC_CFG2_ADHSC_SHIFT                     (2U)
+#define ADC_CFG2_ADHSC(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
+#define ADC_CFG2_ADACKEN_MASK                    (0x8U)
+#define ADC_CFG2_ADACKEN_SHIFT                   (3U)
+#define ADC_CFG2_ADACKEN(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
+#define ADC_CFG2_MUXSEL_MASK                     (0x10U)
+#define ADC_CFG2_MUXSEL_SHIFT                    (4U)
+#define ADC_CFG2_MUXSEL(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
+
+/*! @name R - ADC Data Result Register */
+#define ADC_R_D_MASK                             (0xFFFFU)
+#define ADC_R_D_SHIFT                            (0U)
+#define ADC_R_D(x)                               (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
+
+/* The count of ADC_R */
+#define ADC_R_COUNT                              (2U)
+
+/*! @name CV1 - Compare Value Registers */
+#define ADC_CV1_CV_MASK                          (0xFFFFU)
+#define ADC_CV1_CV_SHIFT                         (0U)
+#define ADC_CV1_CV(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
+
+/*! @name CV2 - Compare Value Registers */
+#define ADC_CV2_CV_MASK                          (0xFFFFU)
+#define ADC_CV2_CV_SHIFT                         (0U)
+#define ADC_CV2_CV(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
+
+/*! @name SC2 - Status and Control Register 2 */
+#define ADC_SC2_REFSEL_MASK                      (0x3U)
+#define ADC_SC2_REFSEL_SHIFT                     (0U)
+#define ADC_SC2_REFSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
+#define ADC_SC2_DMAEN_MASK                       (0x4U)
+#define ADC_SC2_DMAEN_SHIFT                      (2U)
+#define ADC_SC2_DMAEN(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
+#define ADC_SC2_ACREN_MASK                       (0x8U)
+#define ADC_SC2_ACREN_SHIFT                      (3U)
+#define ADC_SC2_ACREN(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
+#define ADC_SC2_ACFGT_MASK                       (0x10U)
+#define ADC_SC2_ACFGT_SHIFT                      (4U)
+#define ADC_SC2_ACFGT(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
+#define ADC_SC2_ACFE_MASK                        (0x20U)
+#define ADC_SC2_ACFE_SHIFT                       (5U)
+#define ADC_SC2_ACFE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
+#define ADC_SC2_ADTRG_MASK                       (0x40U)
+#define ADC_SC2_ADTRG_SHIFT                      (6U)
+#define ADC_SC2_ADTRG(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
+#define ADC_SC2_ADACT_MASK                       (0x80U)
+#define ADC_SC2_ADACT_SHIFT                      (7U)
+#define ADC_SC2_ADACT(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
+
+/*! @name SC3 - Status and Control Register 3 */
+#define ADC_SC3_AVGS_MASK                        (0x3U)
+#define ADC_SC3_AVGS_SHIFT                       (0U)
+#define ADC_SC3_AVGS(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
+#define ADC_SC3_AVGE_MASK                        (0x4U)
+#define ADC_SC3_AVGE_SHIFT                       (2U)
+#define ADC_SC3_AVGE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
+#define ADC_SC3_ADCO_MASK                        (0x8U)
+#define ADC_SC3_ADCO_SHIFT                       (3U)
+#define ADC_SC3_ADCO(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
+#define ADC_SC3_CALF_MASK                        (0x40U)
+#define ADC_SC3_CALF_SHIFT                       (6U)
+#define ADC_SC3_CALF(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
+#define ADC_SC3_CAL_MASK                         (0x80U)
+#define ADC_SC3_CAL_SHIFT                        (7U)
+#define ADC_SC3_CAL(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
+
+/*! @name OFS - ADC Offset Correction Register */
+#define ADC_OFS_OFS_MASK                         (0xFFFFU)
+#define ADC_OFS_OFS_SHIFT                        (0U)
+#define ADC_OFS_OFS(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
+
+/*! @name PG - ADC Plus-Side Gain Register */
+#define ADC_PG_PG_MASK                           (0xFFFFU)
+#define ADC_PG_PG_SHIFT                          (0U)
+#define ADC_PG_PG(x)                             (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
+
+/*! @name MG - ADC Minus-Side Gain Register */
+#define ADC_MG_MG_MASK                           (0xFFFFU)
+#define ADC_MG_MG_SHIFT                          (0U)
+#define ADC_MG_MG(x)                             (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
+
+/*! @name CLPD - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLPD_CLPD_MASK                       (0x3FU)
+#define ADC_CLPD_CLPD_SHIFT                      (0U)
+#define ADC_CLPD_CLPD(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
+
+/*! @name CLPS - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLPS_CLPS_MASK                       (0x3FU)
+#define ADC_CLPS_CLPS_SHIFT                      (0U)
+#define ADC_CLPS_CLPS(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
+
+/*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP4_CLP4_MASK                       (0x3FFU)
+#define ADC_CLP4_CLP4_SHIFT                      (0U)
+#define ADC_CLP4_CLP4(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
+
+/*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP3_CLP3_MASK                       (0x1FFU)
+#define ADC_CLP3_CLP3_SHIFT                      (0U)
+#define ADC_CLP3_CLP3(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
+
+/*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP2_CLP2_MASK                       (0xFFU)
+#define ADC_CLP2_CLP2_SHIFT                      (0U)
+#define ADC_CLP2_CLP2(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
+
+/*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP1_CLP1_MASK                       (0x7FU)
+#define ADC_CLP1_CLP1_SHIFT                      (0U)
+#define ADC_CLP1_CLP1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
+
+/*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
+#define ADC_CLP0_CLP0_MASK                       (0x3FU)
+#define ADC_CLP0_CLP0_SHIFT                      (0U)
+#define ADC_CLP0_CLP0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
+
+/*! @name CLMD - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLMD_CLMD_MASK                       (0x3FU)
+#define ADC_CLMD_CLMD_SHIFT                      (0U)
+#define ADC_CLMD_CLMD(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
+
+/*! @name CLMS - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLMS_CLMS_MASK                       (0x3FU)
+#define ADC_CLMS_CLMS_SHIFT                      (0U)
+#define ADC_CLMS_CLMS(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
+
+/*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM4_CLM4_MASK                       (0x3FFU)
+#define ADC_CLM4_CLM4_SHIFT                      (0U)
+#define ADC_CLM4_CLM4(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
+
+/*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM3_CLM3_MASK                       (0x1FFU)
+#define ADC_CLM3_CLM3_SHIFT                      (0U)
+#define ADC_CLM3_CLM3(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
+
+/*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM2_CLM2_MASK                       (0xFFU)
+#define ADC_CLM2_CLM2_SHIFT                      (0U)
+#define ADC_CLM2_CLM2(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
+
+/*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM1_CLM1_MASK                       (0x7FU)
+#define ADC_CLM1_CLM1_SHIFT                      (0U)
+#define ADC_CLM1_CLM1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
+
+/*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
+#define ADC_CLM0_CLM0_MASK                       (0x3FU)
+#define ADC_CLM0_CLM0_SHIFT                      (0U)
+#define ADC_CLM0_CLM0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE                                (0x4003B000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0                                     ((ADC_Type *)ADC0_BASE)
+/** Peripheral ADC1 base address */
+#define ADC1_BASE                                (0x400BB000u)
+/** Peripheral ADC1 base pointer */
+#define ADC1                                     ((ADC_Type *)ADC1_BASE)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS                           { ADC0_BASE, ADC1_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS                            { ADC0, ADC1 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_IRQS                                 { ADC0_IRQn, ADC1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- AIPS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
+ * @{
+ */
+
+/** AIPS - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MPRA;                              /**< Master Privilege Register A, offset: 0x0 */
+       uint8_t RESERVED_0[28];
+  __IO uint32_t PACRA;                             /**< Peripheral Access Control Register, offset: 0x20 */
+  __IO uint32_t PACRB;                             /**< Peripheral Access Control Register, offset: 0x24 */
+  __IO uint32_t PACRC;                             /**< Peripheral Access Control Register, offset: 0x28 */
+  __IO uint32_t PACRD;                             /**< Peripheral Access Control Register, offset: 0x2C */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t PACRE;                             /**< Peripheral Access Control Register, offset: 0x40 */
+  __IO uint32_t PACRF;                             /**< Peripheral Access Control Register, offset: 0x44 */
+  __IO uint32_t PACRG;                             /**< Peripheral Access Control Register, offset: 0x48 */
+  __IO uint32_t PACRH;                             /**< Peripheral Access Control Register, offset: 0x4C */
+  __IO uint32_t PACRI;                             /**< Peripheral Access Control Register, offset: 0x50 */
+  __IO uint32_t PACRJ;                             /**< Peripheral Access Control Register, offset: 0x54 */
+  __IO uint32_t PACRK;                             /**< Peripheral Access Control Register, offset: 0x58 */
+  __IO uint32_t PACRL;                             /**< Peripheral Access Control Register, offset: 0x5C */
+  __IO uint32_t PACRM;                             /**< Peripheral Access Control Register, offset: 0x60 */
+  __IO uint32_t PACRN;                             /**< Peripheral Access Control Register, offset: 0x64 */
+  __IO uint32_t PACRO;                             /**< Peripheral Access Control Register, offset: 0x68 */
+  __IO uint32_t PACRP;                             /**< Peripheral Access Control Register, offset: 0x6C */
+} AIPS_Type;
+
+/* ----------------------------------------------------------------------------
+   -- AIPS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AIPS_Register_Masks AIPS Register Masks
+ * @{
+ */
+
+/*! @name MPRA - Master Privilege Register A */
+#define AIPS_MPRA_MPL6_MASK                      (0x10U)
+#define AIPS_MPRA_MPL6_SHIFT                     (4U)
+#define AIPS_MPRA_MPL6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL6_SHIFT)) & AIPS_MPRA_MPL6_MASK)
+#define AIPS_MPRA_MTW6_MASK                      (0x20U)
+#define AIPS_MPRA_MTW6_SHIFT                     (5U)
+#define AIPS_MPRA_MTW6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW6_SHIFT)) & AIPS_MPRA_MTW6_MASK)
+#define AIPS_MPRA_MTR6_MASK                      (0x40U)
+#define AIPS_MPRA_MTR6_SHIFT                     (6U)
+#define AIPS_MPRA_MTR6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR6_SHIFT)) & AIPS_MPRA_MTR6_MASK)
+#define AIPS_MPRA_MPL5_MASK                      (0x100U)
+#define AIPS_MPRA_MPL5_SHIFT                     (8U)
+#define AIPS_MPRA_MPL5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL5_SHIFT)) & AIPS_MPRA_MPL5_MASK)
+#define AIPS_MPRA_MTW5_MASK                      (0x200U)
+#define AIPS_MPRA_MTW5_SHIFT                     (9U)
+#define AIPS_MPRA_MTW5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW5_SHIFT)) & AIPS_MPRA_MTW5_MASK)
+#define AIPS_MPRA_MTR5_MASK                      (0x400U)
+#define AIPS_MPRA_MTR5_SHIFT                     (10U)
+#define AIPS_MPRA_MTR5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR5_SHIFT)) & AIPS_MPRA_MTR5_MASK)
+#define AIPS_MPRA_MPL4_MASK                      (0x1000U)
+#define AIPS_MPRA_MPL4_SHIFT                     (12U)
+#define AIPS_MPRA_MPL4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK)
+#define AIPS_MPRA_MTW4_MASK                      (0x2000U)
+#define AIPS_MPRA_MTW4_SHIFT                     (13U)
+#define AIPS_MPRA_MTW4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK)
+#define AIPS_MPRA_MTR4_MASK                      (0x4000U)
+#define AIPS_MPRA_MTR4_SHIFT                     (14U)
+#define AIPS_MPRA_MTR4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK)
+#define AIPS_MPRA_MPL3_MASK                      (0x10000U)
+#define AIPS_MPRA_MPL3_SHIFT                     (16U)
+#define AIPS_MPRA_MPL3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK)
+#define AIPS_MPRA_MTW3_MASK                      (0x20000U)
+#define AIPS_MPRA_MTW3_SHIFT                     (17U)
+#define AIPS_MPRA_MTW3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK)
+#define AIPS_MPRA_MTR3_MASK                      (0x40000U)
+#define AIPS_MPRA_MTR3_SHIFT                     (18U)
+#define AIPS_MPRA_MTR3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK)
+#define AIPS_MPRA_MPL2_MASK                      (0x100000U)
+#define AIPS_MPRA_MPL2_SHIFT                     (20U)
+#define AIPS_MPRA_MPL2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK)
+#define AIPS_MPRA_MTW2_MASK                      (0x200000U)
+#define AIPS_MPRA_MTW2_SHIFT                     (21U)
+#define AIPS_MPRA_MTW2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK)
+#define AIPS_MPRA_MTR2_MASK                      (0x400000U)
+#define AIPS_MPRA_MTR2_SHIFT                     (22U)
+#define AIPS_MPRA_MTR2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK)
+#define AIPS_MPRA_MPL1_MASK                      (0x1000000U)
+#define AIPS_MPRA_MPL1_SHIFT                     (24U)
+#define AIPS_MPRA_MPL1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK)
+#define AIPS_MPRA_MTW1_MASK                      (0x2000000U)
+#define AIPS_MPRA_MTW1_SHIFT                     (25U)
+#define AIPS_MPRA_MTW1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK)
+#define AIPS_MPRA_MTR1_MASK                      (0x4000000U)
+#define AIPS_MPRA_MTR1_SHIFT                     (26U)
+#define AIPS_MPRA_MTR1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK)
+#define AIPS_MPRA_MPL0_MASK                      (0x10000000U)
+#define AIPS_MPRA_MPL0_SHIFT                     (28U)
+#define AIPS_MPRA_MPL0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK)
+#define AIPS_MPRA_MTW0_MASK                      (0x20000000U)
+#define AIPS_MPRA_MTW0_SHIFT                     (29U)
+#define AIPS_MPRA_MTW0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK)
+#define AIPS_MPRA_MTR0_MASK                      (0x40000000U)
+#define AIPS_MPRA_MTR0_SHIFT                     (30U)
+#define AIPS_MPRA_MTR0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK)
+
+/*! @name PACRA - Peripheral Access Control Register */
+#define AIPS_PACRA_TP7_MASK                      (0x1U)
+#define AIPS_PACRA_TP7_SHIFT                     (0U)
+#define AIPS_PACRA_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK)
+#define AIPS_PACRA_WP7_MASK                      (0x2U)
+#define AIPS_PACRA_WP7_SHIFT                     (1U)
+#define AIPS_PACRA_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK)
+#define AIPS_PACRA_SP7_MASK                      (0x4U)
+#define AIPS_PACRA_SP7_SHIFT                     (2U)
+#define AIPS_PACRA_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK)
+#define AIPS_PACRA_TP6_MASK                      (0x10U)
+#define AIPS_PACRA_TP6_SHIFT                     (4U)
+#define AIPS_PACRA_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK)
+#define AIPS_PACRA_WP6_MASK                      (0x20U)
+#define AIPS_PACRA_WP6_SHIFT                     (5U)
+#define AIPS_PACRA_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK)
+#define AIPS_PACRA_SP6_MASK                      (0x40U)
+#define AIPS_PACRA_SP6_SHIFT                     (6U)
+#define AIPS_PACRA_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK)
+#define AIPS_PACRA_TP5_MASK                      (0x100U)
+#define AIPS_PACRA_TP5_SHIFT                     (8U)
+#define AIPS_PACRA_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK)
+#define AIPS_PACRA_WP5_MASK                      (0x200U)
+#define AIPS_PACRA_WP5_SHIFT                     (9U)
+#define AIPS_PACRA_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK)
+#define AIPS_PACRA_SP5_MASK                      (0x400U)
+#define AIPS_PACRA_SP5_SHIFT                     (10U)
+#define AIPS_PACRA_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK)
+#define AIPS_PACRA_TP4_MASK                      (0x1000U)
+#define AIPS_PACRA_TP4_SHIFT                     (12U)
+#define AIPS_PACRA_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK)
+#define AIPS_PACRA_WP4_MASK                      (0x2000U)
+#define AIPS_PACRA_WP4_SHIFT                     (13U)
+#define AIPS_PACRA_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK)
+#define AIPS_PACRA_SP4_MASK                      (0x4000U)
+#define AIPS_PACRA_SP4_SHIFT                     (14U)
+#define AIPS_PACRA_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK)
+#define AIPS_PACRA_TP3_MASK                      (0x10000U)
+#define AIPS_PACRA_TP3_SHIFT                     (16U)
+#define AIPS_PACRA_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK)
+#define AIPS_PACRA_WP3_MASK                      (0x20000U)
+#define AIPS_PACRA_WP3_SHIFT                     (17U)
+#define AIPS_PACRA_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK)
+#define AIPS_PACRA_SP3_MASK                      (0x40000U)
+#define AIPS_PACRA_SP3_SHIFT                     (18U)
+#define AIPS_PACRA_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK)
+#define AIPS_PACRA_TP2_MASK                      (0x100000U)
+#define AIPS_PACRA_TP2_SHIFT                     (20U)
+#define AIPS_PACRA_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK)
+#define AIPS_PACRA_WP2_MASK                      (0x200000U)
+#define AIPS_PACRA_WP2_SHIFT                     (21U)
+#define AIPS_PACRA_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK)
+#define AIPS_PACRA_SP2_MASK                      (0x400000U)
+#define AIPS_PACRA_SP2_SHIFT                     (22U)
+#define AIPS_PACRA_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK)
+#define AIPS_PACRA_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRA_TP1_SHIFT                     (24U)
+#define AIPS_PACRA_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK)
+#define AIPS_PACRA_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRA_WP1_SHIFT                     (25U)
+#define AIPS_PACRA_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK)
+#define AIPS_PACRA_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRA_SP1_SHIFT                     (26U)
+#define AIPS_PACRA_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK)
+#define AIPS_PACRA_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRA_TP0_SHIFT                     (28U)
+#define AIPS_PACRA_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK)
+#define AIPS_PACRA_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRA_WP0_SHIFT                     (29U)
+#define AIPS_PACRA_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK)
+#define AIPS_PACRA_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRA_SP0_SHIFT                     (30U)
+#define AIPS_PACRA_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK)
+
+/*! @name PACRB - Peripheral Access Control Register */
+#define AIPS_PACRB_TP7_MASK                      (0x1U)
+#define AIPS_PACRB_TP7_SHIFT                     (0U)
+#define AIPS_PACRB_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK)
+#define AIPS_PACRB_WP7_MASK                      (0x2U)
+#define AIPS_PACRB_WP7_SHIFT                     (1U)
+#define AIPS_PACRB_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK)
+#define AIPS_PACRB_SP7_MASK                      (0x4U)
+#define AIPS_PACRB_SP7_SHIFT                     (2U)
+#define AIPS_PACRB_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK)
+#define AIPS_PACRB_TP6_MASK                      (0x10U)
+#define AIPS_PACRB_TP6_SHIFT                     (4U)
+#define AIPS_PACRB_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK)
+#define AIPS_PACRB_WP6_MASK                      (0x20U)
+#define AIPS_PACRB_WP6_SHIFT                     (5U)
+#define AIPS_PACRB_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK)
+#define AIPS_PACRB_SP6_MASK                      (0x40U)
+#define AIPS_PACRB_SP6_SHIFT                     (6U)
+#define AIPS_PACRB_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK)
+#define AIPS_PACRB_TP5_MASK                      (0x100U)
+#define AIPS_PACRB_TP5_SHIFT                     (8U)
+#define AIPS_PACRB_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK)
+#define AIPS_PACRB_WP5_MASK                      (0x200U)
+#define AIPS_PACRB_WP5_SHIFT                     (9U)
+#define AIPS_PACRB_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK)
+#define AIPS_PACRB_SP5_MASK                      (0x400U)
+#define AIPS_PACRB_SP5_SHIFT                     (10U)
+#define AIPS_PACRB_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK)
+#define AIPS_PACRB_TP4_MASK                      (0x1000U)
+#define AIPS_PACRB_TP4_SHIFT                     (12U)
+#define AIPS_PACRB_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK)
+#define AIPS_PACRB_WP4_MASK                      (0x2000U)
+#define AIPS_PACRB_WP4_SHIFT                     (13U)
+#define AIPS_PACRB_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK)
+#define AIPS_PACRB_SP4_MASK                      (0x4000U)
+#define AIPS_PACRB_SP4_SHIFT                     (14U)
+#define AIPS_PACRB_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK)
+#define AIPS_PACRB_TP3_MASK                      (0x10000U)
+#define AIPS_PACRB_TP3_SHIFT                     (16U)
+#define AIPS_PACRB_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK)
+#define AIPS_PACRB_WP3_MASK                      (0x20000U)
+#define AIPS_PACRB_WP3_SHIFT                     (17U)
+#define AIPS_PACRB_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK)
+#define AIPS_PACRB_SP3_MASK                      (0x40000U)
+#define AIPS_PACRB_SP3_SHIFT                     (18U)
+#define AIPS_PACRB_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK)
+#define AIPS_PACRB_TP2_MASK                      (0x100000U)
+#define AIPS_PACRB_TP2_SHIFT                     (20U)
+#define AIPS_PACRB_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK)
+#define AIPS_PACRB_WP2_MASK                      (0x200000U)
+#define AIPS_PACRB_WP2_SHIFT                     (21U)
+#define AIPS_PACRB_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK)
+#define AIPS_PACRB_SP2_MASK                      (0x400000U)
+#define AIPS_PACRB_SP2_SHIFT                     (22U)
+#define AIPS_PACRB_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK)
+#define AIPS_PACRB_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRB_TP1_SHIFT                     (24U)
+#define AIPS_PACRB_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK)
+#define AIPS_PACRB_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRB_WP1_SHIFT                     (25U)
+#define AIPS_PACRB_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK)
+#define AIPS_PACRB_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRB_SP1_SHIFT                     (26U)
+#define AIPS_PACRB_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK)
+#define AIPS_PACRB_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRB_TP0_SHIFT                     (28U)
+#define AIPS_PACRB_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK)
+#define AIPS_PACRB_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRB_WP0_SHIFT                     (29U)
+#define AIPS_PACRB_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK)
+#define AIPS_PACRB_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRB_SP0_SHIFT                     (30U)
+#define AIPS_PACRB_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK)
+
+/*! @name PACRC - Peripheral Access Control Register */
+#define AIPS_PACRC_TP7_MASK                      (0x1U)
+#define AIPS_PACRC_TP7_SHIFT                     (0U)
+#define AIPS_PACRC_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK)
+#define AIPS_PACRC_WP7_MASK                      (0x2U)
+#define AIPS_PACRC_WP7_SHIFT                     (1U)
+#define AIPS_PACRC_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK)
+#define AIPS_PACRC_SP7_MASK                      (0x4U)
+#define AIPS_PACRC_SP7_SHIFT                     (2U)
+#define AIPS_PACRC_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK)
+#define AIPS_PACRC_TP6_MASK                      (0x10U)
+#define AIPS_PACRC_TP6_SHIFT                     (4U)
+#define AIPS_PACRC_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK)
+#define AIPS_PACRC_WP6_MASK                      (0x20U)
+#define AIPS_PACRC_WP6_SHIFT                     (5U)
+#define AIPS_PACRC_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK)
+#define AIPS_PACRC_SP6_MASK                      (0x40U)
+#define AIPS_PACRC_SP6_SHIFT                     (6U)
+#define AIPS_PACRC_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK)
+#define AIPS_PACRC_TP5_MASK                      (0x100U)
+#define AIPS_PACRC_TP5_SHIFT                     (8U)
+#define AIPS_PACRC_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK)
+#define AIPS_PACRC_WP5_MASK                      (0x200U)
+#define AIPS_PACRC_WP5_SHIFT                     (9U)
+#define AIPS_PACRC_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK)
+#define AIPS_PACRC_SP5_MASK                      (0x400U)
+#define AIPS_PACRC_SP5_SHIFT                     (10U)
+#define AIPS_PACRC_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK)
+#define AIPS_PACRC_TP4_MASK                      (0x1000U)
+#define AIPS_PACRC_TP4_SHIFT                     (12U)
+#define AIPS_PACRC_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK)
+#define AIPS_PACRC_WP4_MASK                      (0x2000U)
+#define AIPS_PACRC_WP4_SHIFT                     (13U)
+#define AIPS_PACRC_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK)
+#define AIPS_PACRC_SP4_MASK                      (0x4000U)
+#define AIPS_PACRC_SP4_SHIFT                     (14U)
+#define AIPS_PACRC_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK)
+#define AIPS_PACRC_TP3_MASK                      (0x10000U)
+#define AIPS_PACRC_TP3_SHIFT                     (16U)
+#define AIPS_PACRC_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK)
+#define AIPS_PACRC_WP3_MASK                      (0x20000U)
+#define AIPS_PACRC_WP3_SHIFT                     (17U)
+#define AIPS_PACRC_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK)
+#define AIPS_PACRC_SP3_MASK                      (0x40000U)
+#define AIPS_PACRC_SP3_SHIFT                     (18U)
+#define AIPS_PACRC_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK)
+#define AIPS_PACRC_TP2_MASK                      (0x100000U)
+#define AIPS_PACRC_TP2_SHIFT                     (20U)
+#define AIPS_PACRC_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK)
+#define AIPS_PACRC_WP2_MASK                      (0x200000U)
+#define AIPS_PACRC_WP2_SHIFT                     (21U)
+#define AIPS_PACRC_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK)
+#define AIPS_PACRC_SP2_MASK                      (0x400000U)
+#define AIPS_PACRC_SP2_SHIFT                     (22U)
+#define AIPS_PACRC_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK)
+#define AIPS_PACRC_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRC_TP1_SHIFT                     (24U)
+#define AIPS_PACRC_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK)
+#define AIPS_PACRC_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRC_WP1_SHIFT                     (25U)
+#define AIPS_PACRC_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK)
+#define AIPS_PACRC_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRC_SP1_SHIFT                     (26U)
+#define AIPS_PACRC_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK)
+#define AIPS_PACRC_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRC_TP0_SHIFT                     (28U)
+#define AIPS_PACRC_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK)
+#define AIPS_PACRC_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRC_WP0_SHIFT                     (29U)
+#define AIPS_PACRC_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK)
+#define AIPS_PACRC_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRC_SP0_SHIFT                     (30U)
+#define AIPS_PACRC_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK)
+
+/*! @name PACRD - Peripheral Access Control Register */
+#define AIPS_PACRD_TP7_MASK                      (0x1U)
+#define AIPS_PACRD_TP7_SHIFT                     (0U)
+#define AIPS_PACRD_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK)
+#define AIPS_PACRD_WP7_MASK                      (0x2U)
+#define AIPS_PACRD_WP7_SHIFT                     (1U)
+#define AIPS_PACRD_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK)
+#define AIPS_PACRD_SP7_MASK                      (0x4U)
+#define AIPS_PACRD_SP7_SHIFT                     (2U)
+#define AIPS_PACRD_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK)
+#define AIPS_PACRD_TP6_MASK                      (0x10U)
+#define AIPS_PACRD_TP6_SHIFT                     (4U)
+#define AIPS_PACRD_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK)
+#define AIPS_PACRD_WP6_MASK                      (0x20U)
+#define AIPS_PACRD_WP6_SHIFT                     (5U)
+#define AIPS_PACRD_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK)
+#define AIPS_PACRD_SP6_MASK                      (0x40U)
+#define AIPS_PACRD_SP6_SHIFT                     (6U)
+#define AIPS_PACRD_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK)
+#define AIPS_PACRD_TP5_MASK                      (0x100U)
+#define AIPS_PACRD_TP5_SHIFT                     (8U)
+#define AIPS_PACRD_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK)
+#define AIPS_PACRD_WP5_MASK                      (0x200U)
+#define AIPS_PACRD_WP5_SHIFT                     (9U)
+#define AIPS_PACRD_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK)
+#define AIPS_PACRD_SP5_MASK                      (0x400U)
+#define AIPS_PACRD_SP5_SHIFT                     (10U)
+#define AIPS_PACRD_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK)
+#define AIPS_PACRD_TP4_MASK                      (0x1000U)
+#define AIPS_PACRD_TP4_SHIFT                     (12U)
+#define AIPS_PACRD_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK)
+#define AIPS_PACRD_WP4_MASK                      (0x2000U)
+#define AIPS_PACRD_WP4_SHIFT                     (13U)
+#define AIPS_PACRD_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK)
+#define AIPS_PACRD_SP4_MASK                      (0x4000U)
+#define AIPS_PACRD_SP4_SHIFT                     (14U)
+#define AIPS_PACRD_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK)
+#define AIPS_PACRD_TP3_MASK                      (0x10000U)
+#define AIPS_PACRD_TP3_SHIFT                     (16U)
+#define AIPS_PACRD_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK)
+#define AIPS_PACRD_WP3_MASK                      (0x20000U)
+#define AIPS_PACRD_WP3_SHIFT                     (17U)
+#define AIPS_PACRD_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK)
+#define AIPS_PACRD_SP3_MASK                      (0x40000U)
+#define AIPS_PACRD_SP3_SHIFT                     (18U)
+#define AIPS_PACRD_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK)
+#define AIPS_PACRD_TP2_MASK                      (0x100000U)
+#define AIPS_PACRD_TP2_SHIFT                     (20U)
+#define AIPS_PACRD_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK)
+#define AIPS_PACRD_WP2_MASK                      (0x200000U)
+#define AIPS_PACRD_WP2_SHIFT                     (21U)
+#define AIPS_PACRD_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK)
+#define AIPS_PACRD_SP2_MASK                      (0x400000U)
+#define AIPS_PACRD_SP2_SHIFT                     (22U)
+#define AIPS_PACRD_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK)
+#define AIPS_PACRD_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRD_TP1_SHIFT                     (24U)
+#define AIPS_PACRD_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK)
+#define AIPS_PACRD_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRD_WP1_SHIFT                     (25U)
+#define AIPS_PACRD_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK)
+#define AIPS_PACRD_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRD_SP1_SHIFT                     (26U)
+#define AIPS_PACRD_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK)
+#define AIPS_PACRD_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRD_TP0_SHIFT                     (28U)
+#define AIPS_PACRD_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK)
+#define AIPS_PACRD_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRD_WP0_SHIFT                     (29U)
+#define AIPS_PACRD_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK)
+#define AIPS_PACRD_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRD_SP0_SHIFT                     (30U)
+#define AIPS_PACRD_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK)
+
+/*! @name PACRE - Peripheral Access Control Register */
+#define AIPS_PACRE_TP7_MASK                      (0x1U)
+#define AIPS_PACRE_TP7_SHIFT                     (0U)
+#define AIPS_PACRE_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK)
+#define AIPS_PACRE_WP7_MASK                      (0x2U)
+#define AIPS_PACRE_WP7_SHIFT                     (1U)
+#define AIPS_PACRE_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK)
+#define AIPS_PACRE_SP7_MASK                      (0x4U)
+#define AIPS_PACRE_SP7_SHIFT                     (2U)
+#define AIPS_PACRE_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK)
+#define AIPS_PACRE_TP6_MASK                      (0x10U)
+#define AIPS_PACRE_TP6_SHIFT                     (4U)
+#define AIPS_PACRE_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK)
+#define AIPS_PACRE_WP6_MASK                      (0x20U)
+#define AIPS_PACRE_WP6_SHIFT                     (5U)
+#define AIPS_PACRE_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK)
+#define AIPS_PACRE_SP6_MASK                      (0x40U)
+#define AIPS_PACRE_SP6_SHIFT                     (6U)
+#define AIPS_PACRE_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK)
+#define AIPS_PACRE_TP5_MASK                      (0x100U)
+#define AIPS_PACRE_TP5_SHIFT                     (8U)
+#define AIPS_PACRE_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK)
+#define AIPS_PACRE_WP5_MASK                      (0x200U)
+#define AIPS_PACRE_WP5_SHIFT                     (9U)
+#define AIPS_PACRE_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK)
+#define AIPS_PACRE_SP5_MASK                      (0x400U)
+#define AIPS_PACRE_SP5_SHIFT                     (10U)
+#define AIPS_PACRE_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK)
+#define AIPS_PACRE_TP4_MASK                      (0x1000U)
+#define AIPS_PACRE_TP4_SHIFT                     (12U)
+#define AIPS_PACRE_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK)
+#define AIPS_PACRE_WP4_MASK                      (0x2000U)
+#define AIPS_PACRE_WP4_SHIFT                     (13U)
+#define AIPS_PACRE_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK)
+#define AIPS_PACRE_SP4_MASK                      (0x4000U)
+#define AIPS_PACRE_SP4_SHIFT                     (14U)
+#define AIPS_PACRE_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK)
+#define AIPS_PACRE_TP3_MASK                      (0x10000U)
+#define AIPS_PACRE_TP3_SHIFT                     (16U)
+#define AIPS_PACRE_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK)
+#define AIPS_PACRE_WP3_MASK                      (0x20000U)
+#define AIPS_PACRE_WP3_SHIFT                     (17U)
+#define AIPS_PACRE_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK)
+#define AIPS_PACRE_SP3_MASK                      (0x40000U)
+#define AIPS_PACRE_SP3_SHIFT                     (18U)
+#define AIPS_PACRE_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK)
+#define AIPS_PACRE_TP2_MASK                      (0x100000U)
+#define AIPS_PACRE_TP2_SHIFT                     (20U)
+#define AIPS_PACRE_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK)
+#define AIPS_PACRE_WP2_MASK                      (0x200000U)
+#define AIPS_PACRE_WP2_SHIFT                     (21U)
+#define AIPS_PACRE_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK)
+#define AIPS_PACRE_SP2_MASK                      (0x400000U)
+#define AIPS_PACRE_SP2_SHIFT                     (22U)
+#define AIPS_PACRE_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK)
+#define AIPS_PACRE_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRE_TP1_SHIFT                     (24U)
+#define AIPS_PACRE_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK)
+#define AIPS_PACRE_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRE_WP1_SHIFT                     (25U)
+#define AIPS_PACRE_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK)
+#define AIPS_PACRE_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRE_SP1_SHIFT                     (26U)
+#define AIPS_PACRE_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK)
+#define AIPS_PACRE_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRE_TP0_SHIFT                     (28U)
+#define AIPS_PACRE_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK)
+#define AIPS_PACRE_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRE_WP0_SHIFT                     (29U)
+#define AIPS_PACRE_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK)
+#define AIPS_PACRE_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRE_SP0_SHIFT                     (30U)
+#define AIPS_PACRE_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK)
+
+/*! @name PACRF - Peripheral Access Control Register */
+#define AIPS_PACRF_TP7_MASK                      (0x1U)
+#define AIPS_PACRF_TP7_SHIFT                     (0U)
+#define AIPS_PACRF_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK)
+#define AIPS_PACRF_WP7_MASK                      (0x2U)
+#define AIPS_PACRF_WP7_SHIFT                     (1U)
+#define AIPS_PACRF_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK)
+#define AIPS_PACRF_SP7_MASK                      (0x4U)
+#define AIPS_PACRF_SP7_SHIFT                     (2U)
+#define AIPS_PACRF_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK)
+#define AIPS_PACRF_TP6_MASK                      (0x10U)
+#define AIPS_PACRF_TP6_SHIFT                     (4U)
+#define AIPS_PACRF_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK)
+#define AIPS_PACRF_WP6_MASK                      (0x20U)
+#define AIPS_PACRF_WP6_SHIFT                     (5U)
+#define AIPS_PACRF_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK)
+#define AIPS_PACRF_SP6_MASK                      (0x40U)
+#define AIPS_PACRF_SP6_SHIFT                     (6U)
+#define AIPS_PACRF_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK)
+#define AIPS_PACRF_TP5_MASK                      (0x100U)
+#define AIPS_PACRF_TP5_SHIFT                     (8U)
+#define AIPS_PACRF_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK)
+#define AIPS_PACRF_WP5_MASK                      (0x200U)
+#define AIPS_PACRF_WP5_SHIFT                     (9U)
+#define AIPS_PACRF_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK)
+#define AIPS_PACRF_SP5_MASK                      (0x400U)
+#define AIPS_PACRF_SP5_SHIFT                     (10U)
+#define AIPS_PACRF_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK)
+#define AIPS_PACRF_TP4_MASK                      (0x1000U)
+#define AIPS_PACRF_TP4_SHIFT                     (12U)
+#define AIPS_PACRF_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK)
+#define AIPS_PACRF_WP4_MASK                      (0x2000U)
+#define AIPS_PACRF_WP4_SHIFT                     (13U)
+#define AIPS_PACRF_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK)
+#define AIPS_PACRF_SP4_MASK                      (0x4000U)
+#define AIPS_PACRF_SP4_SHIFT                     (14U)
+#define AIPS_PACRF_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK)
+#define AIPS_PACRF_TP3_MASK                      (0x10000U)
+#define AIPS_PACRF_TP3_SHIFT                     (16U)
+#define AIPS_PACRF_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK)
+#define AIPS_PACRF_WP3_MASK                      (0x20000U)
+#define AIPS_PACRF_WP3_SHIFT                     (17U)
+#define AIPS_PACRF_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK)
+#define AIPS_PACRF_SP3_MASK                      (0x40000U)
+#define AIPS_PACRF_SP3_SHIFT                     (18U)
+#define AIPS_PACRF_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK)
+#define AIPS_PACRF_TP2_MASK                      (0x100000U)
+#define AIPS_PACRF_TP2_SHIFT                     (20U)
+#define AIPS_PACRF_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK)
+#define AIPS_PACRF_WP2_MASK                      (0x200000U)
+#define AIPS_PACRF_WP2_SHIFT                     (21U)
+#define AIPS_PACRF_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK)
+#define AIPS_PACRF_SP2_MASK                      (0x400000U)
+#define AIPS_PACRF_SP2_SHIFT                     (22U)
+#define AIPS_PACRF_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK)
+#define AIPS_PACRF_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRF_TP1_SHIFT                     (24U)
+#define AIPS_PACRF_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK)
+#define AIPS_PACRF_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRF_WP1_SHIFT                     (25U)
+#define AIPS_PACRF_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK)
+#define AIPS_PACRF_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRF_SP1_SHIFT                     (26U)
+#define AIPS_PACRF_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK)
+#define AIPS_PACRF_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRF_TP0_SHIFT                     (28U)
+#define AIPS_PACRF_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK)
+#define AIPS_PACRF_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRF_WP0_SHIFT                     (29U)
+#define AIPS_PACRF_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK)
+#define AIPS_PACRF_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRF_SP0_SHIFT                     (30U)
+#define AIPS_PACRF_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK)
+
+/*! @name PACRG - Peripheral Access Control Register */
+#define AIPS_PACRG_TP7_MASK                      (0x1U)
+#define AIPS_PACRG_TP7_SHIFT                     (0U)
+#define AIPS_PACRG_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK)
+#define AIPS_PACRG_WP7_MASK                      (0x2U)
+#define AIPS_PACRG_WP7_SHIFT                     (1U)
+#define AIPS_PACRG_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK)
+#define AIPS_PACRG_SP7_MASK                      (0x4U)
+#define AIPS_PACRG_SP7_SHIFT                     (2U)
+#define AIPS_PACRG_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK)
+#define AIPS_PACRG_TP6_MASK                      (0x10U)
+#define AIPS_PACRG_TP6_SHIFT                     (4U)
+#define AIPS_PACRG_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK)
+#define AIPS_PACRG_WP6_MASK                      (0x20U)
+#define AIPS_PACRG_WP6_SHIFT                     (5U)
+#define AIPS_PACRG_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK)
+#define AIPS_PACRG_SP6_MASK                      (0x40U)
+#define AIPS_PACRG_SP6_SHIFT                     (6U)
+#define AIPS_PACRG_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK)
+#define AIPS_PACRG_TP5_MASK                      (0x100U)
+#define AIPS_PACRG_TP5_SHIFT                     (8U)
+#define AIPS_PACRG_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK)
+#define AIPS_PACRG_WP5_MASK                      (0x200U)
+#define AIPS_PACRG_WP5_SHIFT                     (9U)
+#define AIPS_PACRG_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK)
+#define AIPS_PACRG_SP5_MASK                      (0x400U)
+#define AIPS_PACRG_SP5_SHIFT                     (10U)
+#define AIPS_PACRG_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK)
+#define AIPS_PACRG_TP4_MASK                      (0x1000U)
+#define AIPS_PACRG_TP4_SHIFT                     (12U)
+#define AIPS_PACRG_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK)
+#define AIPS_PACRG_WP4_MASK                      (0x2000U)
+#define AIPS_PACRG_WP4_SHIFT                     (13U)
+#define AIPS_PACRG_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK)
+#define AIPS_PACRG_SP4_MASK                      (0x4000U)
+#define AIPS_PACRG_SP4_SHIFT                     (14U)
+#define AIPS_PACRG_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK)
+#define AIPS_PACRG_TP3_MASK                      (0x10000U)
+#define AIPS_PACRG_TP3_SHIFT                     (16U)
+#define AIPS_PACRG_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK)
+#define AIPS_PACRG_WP3_MASK                      (0x20000U)
+#define AIPS_PACRG_WP3_SHIFT                     (17U)
+#define AIPS_PACRG_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK)
+#define AIPS_PACRG_SP3_MASK                      (0x40000U)
+#define AIPS_PACRG_SP3_SHIFT                     (18U)
+#define AIPS_PACRG_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK)
+#define AIPS_PACRG_TP2_MASK                      (0x100000U)
+#define AIPS_PACRG_TP2_SHIFT                     (20U)
+#define AIPS_PACRG_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK)
+#define AIPS_PACRG_WP2_MASK                      (0x200000U)
+#define AIPS_PACRG_WP2_SHIFT                     (21U)
+#define AIPS_PACRG_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK)
+#define AIPS_PACRG_SP2_MASK                      (0x400000U)
+#define AIPS_PACRG_SP2_SHIFT                     (22U)
+#define AIPS_PACRG_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK)
+#define AIPS_PACRG_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRG_TP1_SHIFT                     (24U)
+#define AIPS_PACRG_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK)
+#define AIPS_PACRG_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRG_WP1_SHIFT                     (25U)
+#define AIPS_PACRG_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK)
+#define AIPS_PACRG_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRG_SP1_SHIFT                     (26U)
+#define AIPS_PACRG_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK)
+#define AIPS_PACRG_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRG_TP0_SHIFT                     (28U)
+#define AIPS_PACRG_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK)
+#define AIPS_PACRG_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRG_WP0_SHIFT                     (29U)
+#define AIPS_PACRG_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK)
+#define AIPS_PACRG_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRG_SP0_SHIFT                     (30U)
+#define AIPS_PACRG_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK)
+
+/*! @name PACRH - Peripheral Access Control Register */
+#define AIPS_PACRH_TP7_MASK                      (0x1U)
+#define AIPS_PACRH_TP7_SHIFT                     (0U)
+#define AIPS_PACRH_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK)
+#define AIPS_PACRH_WP7_MASK                      (0x2U)
+#define AIPS_PACRH_WP7_SHIFT                     (1U)
+#define AIPS_PACRH_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK)
+#define AIPS_PACRH_SP7_MASK                      (0x4U)
+#define AIPS_PACRH_SP7_SHIFT                     (2U)
+#define AIPS_PACRH_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK)
+#define AIPS_PACRH_TP6_MASK                      (0x10U)
+#define AIPS_PACRH_TP6_SHIFT                     (4U)
+#define AIPS_PACRH_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK)
+#define AIPS_PACRH_WP6_MASK                      (0x20U)
+#define AIPS_PACRH_WP6_SHIFT                     (5U)
+#define AIPS_PACRH_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK)
+#define AIPS_PACRH_SP6_MASK                      (0x40U)
+#define AIPS_PACRH_SP6_SHIFT                     (6U)
+#define AIPS_PACRH_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK)
+#define AIPS_PACRH_TP5_MASK                      (0x100U)
+#define AIPS_PACRH_TP5_SHIFT                     (8U)
+#define AIPS_PACRH_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK)
+#define AIPS_PACRH_WP5_MASK                      (0x200U)
+#define AIPS_PACRH_WP5_SHIFT                     (9U)
+#define AIPS_PACRH_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK)
+#define AIPS_PACRH_SP5_MASK                      (0x400U)
+#define AIPS_PACRH_SP5_SHIFT                     (10U)
+#define AIPS_PACRH_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK)
+#define AIPS_PACRH_TP4_MASK                      (0x1000U)
+#define AIPS_PACRH_TP4_SHIFT                     (12U)
+#define AIPS_PACRH_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK)
+#define AIPS_PACRH_WP4_MASK                      (0x2000U)
+#define AIPS_PACRH_WP4_SHIFT                     (13U)
+#define AIPS_PACRH_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK)
+#define AIPS_PACRH_SP4_MASK                      (0x4000U)
+#define AIPS_PACRH_SP4_SHIFT                     (14U)
+#define AIPS_PACRH_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK)
+#define AIPS_PACRH_TP3_MASK                      (0x10000U)
+#define AIPS_PACRH_TP3_SHIFT                     (16U)
+#define AIPS_PACRH_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK)
+#define AIPS_PACRH_WP3_MASK                      (0x20000U)
+#define AIPS_PACRH_WP3_SHIFT                     (17U)
+#define AIPS_PACRH_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK)
+#define AIPS_PACRH_SP3_MASK                      (0x40000U)
+#define AIPS_PACRH_SP3_SHIFT                     (18U)
+#define AIPS_PACRH_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK)
+#define AIPS_PACRH_TP2_MASK                      (0x100000U)
+#define AIPS_PACRH_TP2_SHIFT                     (20U)
+#define AIPS_PACRH_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK)
+#define AIPS_PACRH_WP2_MASK                      (0x200000U)
+#define AIPS_PACRH_WP2_SHIFT                     (21U)
+#define AIPS_PACRH_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK)
+#define AIPS_PACRH_SP2_MASK                      (0x400000U)
+#define AIPS_PACRH_SP2_SHIFT                     (22U)
+#define AIPS_PACRH_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK)
+#define AIPS_PACRH_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRH_TP1_SHIFT                     (24U)
+#define AIPS_PACRH_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK)
+#define AIPS_PACRH_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRH_WP1_SHIFT                     (25U)
+#define AIPS_PACRH_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK)
+#define AIPS_PACRH_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRH_SP1_SHIFT                     (26U)
+#define AIPS_PACRH_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK)
+#define AIPS_PACRH_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRH_TP0_SHIFT                     (28U)
+#define AIPS_PACRH_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK)
+#define AIPS_PACRH_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRH_WP0_SHIFT                     (29U)
+#define AIPS_PACRH_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK)
+#define AIPS_PACRH_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRH_SP0_SHIFT                     (30U)
+#define AIPS_PACRH_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK)
+
+/*! @name PACRI - Peripheral Access Control Register */
+#define AIPS_PACRI_TP7_MASK                      (0x1U)
+#define AIPS_PACRI_TP7_SHIFT                     (0U)
+#define AIPS_PACRI_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK)
+#define AIPS_PACRI_WP7_MASK                      (0x2U)
+#define AIPS_PACRI_WP7_SHIFT                     (1U)
+#define AIPS_PACRI_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK)
+#define AIPS_PACRI_SP7_MASK                      (0x4U)
+#define AIPS_PACRI_SP7_SHIFT                     (2U)
+#define AIPS_PACRI_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK)
+#define AIPS_PACRI_TP6_MASK                      (0x10U)
+#define AIPS_PACRI_TP6_SHIFT                     (4U)
+#define AIPS_PACRI_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK)
+#define AIPS_PACRI_WP6_MASK                      (0x20U)
+#define AIPS_PACRI_WP6_SHIFT                     (5U)
+#define AIPS_PACRI_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK)
+#define AIPS_PACRI_SP6_MASK                      (0x40U)
+#define AIPS_PACRI_SP6_SHIFT                     (6U)
+#define AIPS_PACRI_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK)
+#define AIPS_PACRI_TP5_MASK                      (0x100U)
+#define AIPS_PACRI_TP5_SHIFT                     (8U)
+#define AIPS_PACRI_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK)
+#define AIPS_PACRI_WP5_MASK                      (0x200U)
+#define AIPS_PACRI_WP5_SHIFT                     (9U)
+#define AIPS_PACRI_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK)
+#define AIPS_PACRI_SP5_MASK                      (0x400U)
+#define AIPS_PACRI_SP5_SHIFT                     (10U)
+#define AIPS_PACRI_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK)
+#define AIPS_PACRI_TP4_MASK                      (0x1000U)
+#define AIPS_PACRI_TP4_SHIFT                     (12U)
+#define AIPS_PACRI_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK)
+#define AIPS_PACRI_WP4_MASK                      (0x2000U)
+#define AIPS_PACRI_WP4_SHIFT                     (13U)
+#define AIPS_PACRI_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK)
+#define AIPS_PACRI_SP4_MASK                      (0x4000U)
+#define AIPS_PACRI_SP4_SHIFT                     (14U)
+#define AIPS_PACRI_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK)
+#define AIPS_PACRI_TP3_MASK                      (0x10000U)
+#define AIPS_PACRI_TP3_SHIFT                     (16U)
+#define AIPS_PACRI_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK)
+#define AIPS_PACRI_WP3_MASK                      (0x20000U)
+#define AIPS_PACRI_WP3_SHIFT                     (17U)
+#define AIPS_PACRI_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK)
+#define AIPS_PACRI_SP3_MASK                      (0x40000U)
+#define AIPS_PACRI_SP3_SHIFT                     (18U)
+#define AIPS_PACRI_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK)
+#define AIPS_PACRI_TP2_MASK                      (0x100000U)
+#define AIPS_PACRI_TP2_SHIFT                     (20U)
+#define AIPS_PACRI_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK)
+#define AIPS_PACRI_WP2_MASK                      (0x200000U)
+#define AIPS_PACRI_WP2_SHIFT                     (21U)
+#define AIPS_PACRI_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK)
+#define AIPS_PACRI_SP2_MASK                      (0x400000U)
+#define AIPS_PACRI_SP2_SHIFT                     (22U)
+#define AIPS_PACRI_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK)
+#define AIPS_PACRI_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRI_TP1_SHIFT                     (24U)
+#define AIPS_PACRI_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK)
+#define AIPS_PACRI_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRI_WP1_SHIFT                     (25U)
+#define AIPS_PACRI_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK)
+#define AIPS_PACRI_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRI_SP1_SHIFT                     (26U)
+#define AIPS_PACRI_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK)
+#define AIPS_PACRI_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRI_TP0_SHIFT                     (28U)
+#define AIPS_PACRI_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK)
+#define AIPS_PACRI_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRI_WP0_SHIFT                     (29U)
+#define AIPS_PACRI_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK)
+#define AIPS_PACRI_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRI_SP0_SHIFT                     (30U)
+#define AIPS_PACRI_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK)
+
+/*! @name PACRJ - Peripheral Access Control Register */
+#define AIPS_PACRJ_TP7_MASK                      (0x1U)
+#define AIPS_PACRJ_TP7_SHIFT                     (0U)
+#define AIPS_PACRJ_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK)
+#define AIPS_PACRJ_WP7_MASK                      (0x2U)
+#define AIPS_PACRJ_WP7_SHIFT                     (1U)
+#define AIPS_PACRJ_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK)
+#define AIPS_PACRJ_SP7_MASK                      (0x4U)
+#define AIPS_PACRJ_SP7_SHIFT                     (2U)
+#define AIPS_PACRJ_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK)
+#define AIPS_PACRJ_TP6_MASK                      (0x10U)
+#define AIPS_PACRJ_TP6_SHIFT                     (4U)
+#define AIPS_PACRJ_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK)
+#define AIPS_PACRJ_WP6_MASK                      (0x20U)
+#define AIPS_PACRJ_WP6_SHIFT                     (5U)
+#define AIPS_PACRJ_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK)
+#define AIPS_PACRJ_SP6_MASK                      (0x40U)
+#define AIPS_PACRJ_SP6_SHIFT                     (6U)
+#define AIPS_PACRJ_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK)
+#define AIPS_PACRJ_TP5_MASK                      (0x100U)
+#define AIPS_PACRJ_TP5_SHIFT                     (8U)
+#define AIPS_PACRJ_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK)
+#define AIPS_PACRJ_WP5_MASK                      (0x200U)
+#define AIPS_PACRJ_WP5_SHIFT                     (9U)
+#define AIPS_PACRJ_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK)
+#define AIPS_PACRJ_SP5_MASK                      (0x400U)
+#define AIPS_PACRJ_SP5_SHIFT                     (10U)
+#define AIPS_PACRJ_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK)
+#define AIPS_PACRJ_TP4_MASK                      (0x1000U)
+#define AIPS_PACRJ_TP4_SHIFT                     (12U)
+#define AIPS_PACRJ_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK)
+#define AIPS_PACRJ_WP4_MASK                      (0x2000U)
+#define AIPS_PACRJ_WP4_SHIFT                     (13U)
+#define AIPS_PACRJ_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK)
+#define AIPS_PACRJ_SP4_MASK                      (0x4000U)
+#define AIPS_PACRJ_SP4_SHIFT                     (14U)
+#define AIPS_PACRJ_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK)
+#define AIPS_PACRJ_TP3_MASK                      (0x10000U)
+#define AIPS_PACRJ_TP3_SHIFT                     (16U)
+#define AIPS_PACRJ_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK)
+#define AIPS_PACRJ_WP3_MASK                      (0x20000U)
+#define AIPS_PACRJ_WP3_SHIFT                     (17U)
+#define AIPS_PACRJ_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK)
+#define AIPS_PACRJ_SP3_MASK                      (0x40000U)
+#define AIPS_PACRJ_SP3_SHIFT                     (18U)
+#define AIPS_PACRJ_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK)
+#define AIPS_PACRJ_TP2_MASK                      (0x100000U)
+#define AIPS_PACRJ_TP2_SHIFT                     (20U)
+#define AIPS_PACRJ_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK)
+#define AIPS_PACRJ_WP2_MASK                      (0x200000U)
+#define AIPS_PACRJ_WP2_SHIFT                     (21U)
+#define AIPS_PACRJ_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK)
+#define AIPS_PACRJ_SP2_MASK                      (0x400000U)
+#define AIPS_PACRJ_SP2_SHIFT                     (22U)
+#define AIPS_PACRJ_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK)
+#define AIPS_PACRJ_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRJ_TP1_SHIFT                     (24U)
+#define AIPS_PACRJ_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK)
+#define AIPS_PACRJ_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRJ_WP1_SHIFT                     (25U)
+#define AIPS_PACRJ_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK)
+#define AIPS_PACRJ_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRJ_SP1_SHIFT                     (26U)
+#define AIPS_PACRJ_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK)
+#define AIPS_PACRJ_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRJ_TP0_SHIFT                     (28U)
+#define AIPS_PACRJ_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK)
+#define AIPS_PACRJ_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRJ_WP0_SHIFT                     (29U)
+#define AIPS_PACRJ_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK)
+#define AIPS_PACRJ_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRJ_SP0_SHIFT                     (30U)
+#define AIPS_PACRJ_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK)
+
+/*! @name PACRK - Peripheral Access Control Register */
+#define AIPS_PACRK_TP7_MASK                      (0x1U)
+#define AIPS_PACRK_TP7_SHIFT                     (0U)
+#define AIPS_PACRK_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK)
+#define AIPS_PACRK_WP7_MASK                      (0x2U)
+#define AIPS_PACRK_WP7_SHIFT                     (1U)
+#define AIPS_PACRK_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK)
+#define AIPS_PACRK_SP7_MASK                      (0x4U)
+#define AIPS_PACRK_SP7_SHIFT                     (2U)
+#define AIPS_PACRK_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK)
+#define AIPS_PACRK_TP6_MASK                      (0x10U)
+#define AIPS_PACRK_TP6_SHIFT                     (4U)
+#define AIPS_PACRK_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK)
+#define AIPS_PACRK_WP6_MASK                      (0x20U)
+#define AIPS_PACRK_WP6_SHIFT                     (5U)
+#define AIPS_PACRK_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK)
+#define AIPS_PACRK_SP6_MASK                      (0x40U)
+#define AIPS_PACRK_SP6_SHIFT                     (6U)
+#define AIPS_PACRK_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK)
+#define AIPS_PACRK_TP5_MASK                      (0x100U)
+#define AIPS_PACRK_TP5_SHIFT                     (8U)
+#define AIPS_PACRK_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK)
+#define AIPS_PACRK_WP5_MASK                      (0x200U)
+#define AIPS_PACRK_WP5_SHIFT                     (9U)
+#define AIPS_PACRK_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK)
+#define AIPS_PACRK_SP5_MASK                      (0x400U)
+#define AIPS_PACRK_SP5_SHIFT                     (10U)
+#define AIPS_PACRK_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK)
+#define AIPS_PACRK_TP4_MASK                      (0x1000U)
+#define AIPS_PACRK_TP4_SHIFT                     (12U)
+#define AIPS_PACRK_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK)
+#define AIPS_PACRK_WP4_MASK                      (0x2000U)
+#define AIPS_PACRK_WP4_SHIFT                     (13U)
+#define AIPS_PACRK_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK)
+#define AIPS_PACRK_SP4_MASK                      (0x4000U)
+#define AIPS_PACRK_SP4_SHIFT                     (14U)
+#define AIPS_PACRK_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK)
+#define AIPS_PACRK_TP3_MASK                      (0x10000U)
+#define AIPS_PACRK_TP3_SHIFT                     (16U)
+#define AIPS_PACRK_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK)
+#define AIPS_PACRK_WP3_MASK                      (0x20000U)
+#define AIPS_PACRK_WP3_SHIFT                     (17U)
+#define AIPS_PACRK_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK)
+#define AIPS_PACRK_SP3_MASK                      (0x40000U)
+#define AIPS_PACRK_SP3_SHIFT                     (18U)
+#define AIPS_PACRK_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK)
+#define AIPS_PACRK_TP2_MASK                      (0x100000U)
+#define AIPS_PACRK_TP2_SHIFT                     (20U)
+#define AIPS_PACRK_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK)
+#define AIPS_PACRK_WP2_MASK                      (0x200000U)
+#define AIPS_PACRK_WP2_SHIFT                     (21U)
+#define AIPS_PACRK_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK)
+#define AIPS_PACRK_SP2_MASK                      (0x400000U)
+#define AIPS_PACRK_SP2_SHIFT                     (22U)
+#define AIPS_PACRK_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK)
+#define AIPS_PACRK_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRK_TP1_SHIFT                     (24U)
+#define AIPS_PACRK_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK)
+#define AIPS_PACRK_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRK_WP1_SHIFT                     (25U)
+#define AIPS_PACRK_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK)
+#define AIPS_PACRK_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRK_SP1_SHIFT                     (26U)
+#define AIPS_PACRK_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK)
+#define AIPS_PACRK_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRK_TP0_SHIFT                     (28U)
+#define AIPS_PACRK_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK)
+#define AIPS_PACRK_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRK_WP0_SHIFT                     (29U)
+#define AIPS_PACRK_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK)
+#define AIPS_PACRK_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRK_SP0_SHIFT                     (30U)
+#define AIPS_PACRK_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK)
+
+/*! @name PACRL - Peripheral Access Control Register */
+#define AIPS_PACRL_TP7_MASK                      (0x1U)
+#define AIPS_PACRL_TP7_SHIFT                     (0U)
+#define AIPS_PACRL_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK)
+#define AIPS_PACRL_WP7_MASK                      (0x2U)
+#define AIPS_PACRL_WP7_SHIFT                     (1U)
+#define AIPS_PACRL_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK)
+#define AIPS_PACRL_SP7_MASK                      (0x4U)
+#define AIPS_PACRL_SP7_SHIFT                     (2U)
+#define AIPS_PACRL_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK)
+#define AIPS_PACRL_TP6_MASK                      (0x10U)
+#define AIPS_PACRL_TP6_SHIFT                     (4U)
+#define AIPS_PACRL_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK)
+#define AIPS_PACRL_WP6_MASK                      (0x20U)
+#define AIPS_PACRL_WP6_SHIFT                     (5U)
+#define AIPS_PACRL_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK)
+#define AIPS_PACRL_SP6_MASK                      (0x40U)
+#define AIPS_PACRL_SP6_SHIFT                     (6U)
+#define AIPS_PACRL_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK)
+#define AIPS_PACRL_TP5_MASK                      (0x100U)
+#define AIPS_PACRL_TP5_SHIFT                     (8U)
+#define AIPS_PACRL_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK)
+#define AIPS_PACRL_WP5_MASK                      (0x200U)
+#define AIPS_PACRL_WP5_SHIFT                     (9U)
+#define AIPS_PACRL_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK)
+#define AIPS_PACRL_SP5_MASK                      (0x400U)
+#define AIPS_PACRL_SP5_SHIFT                     (10U)
+#define AIPS_PACRL_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK)
+#define AIPS_PACRL_TP4_MASK                      (0x1000U)
+#define AIPS_PACRL_TP4_SHIFT                     (12U)
+#define AIPS_PACRL_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK)
+#define AIPS_PACRL_WP4_MASK                      (0x2000U)
+#define AIPS_PACRL_WP4_SHIFT                     (13U)
+#define AIPS_PACRL_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK)
+#define AIPS_PACRL_SP4_MASK                      (0x4000U)
+#define AIPS_PACRL_SP4_SHIFT                     (14U)
+#define AIPS_PACRL_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK)
+#define AIPS_PACRL_TP3_MASK                      (0x10000U)
+#define AIPS_PACRL_TP3_SHIFT                     (16U)
+#define AIPS_PACRL_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK)
+#define AIPS_PACRL_WP3_MASK                      (0x20000U)
+#define AIPS_PACRL_WP3_SHIFT                     (17U)
+#define AIPS_PACRL_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK)
+#define AIPS_PACRL_SP3_MASK                      (0x40000U)
+#define AIPS_PACRL_SP3_SHIFT                     (18U)
+#define AIPS_PACRL_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK)
+#define AIPS_PACRL_TP2_MASK                      (0x100000U)
+#define AIPS_PACRL_TP2_SHIFT                     (20U)
+#define AIPS_PACRL_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK)
+#define AIPS_PACRL_WP2_MASK                      (0x200000U)
+#define AIPS_PACRL_WP2_SHIFT                     (21U)
+#define AIPS_PACRL_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK)
+#define AIPS_PACRL_SP2_MASK                      (0x400000U)
+#define AIPS_PACRL_SP2_SHIFT                     (22U)
+#define AIPS_PACRL_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK)
+#define AIPS_PACRL_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRL_TP1_SHIFT                     (24U)
+#define AIPS_PACRL_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK)
+#define AIPS_PACRL_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRL_WP1_SHIFT                     (25U)
+#define AIPS_PACRL_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK)
+#define AIPS_PACRL_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRL_SP1_SHIFT                     (26U)
+#define AIPS_PACRL_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK)
+#define AIPS_PACRL_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRL_TP0_SHIFT                     (28U)
+#define AIPS_PACRL_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK)
+#define AIPS_PACRL_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRL_WP0_SHIFT                     (29U)
+#define AIPS_PACRL_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK)
+#define AIPS_PACRL_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRL_SP0_SHIFT                     (30U)
+#define AIPS_PACRL_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK)
+
+/*! @name PACRM - Peripheral Access Control Register */
+#define AIPS_PACRM_TP7_MASK                      (0x1U)
+#define AIPS_PACRM_TP7_SHIFT                     (0U)
+#define AIPS_PACRM_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK)
+#define AIPS_PACRM_WP7_MASK                      (0x2U)
+#define AIPS_PACRM_WP7_SHIFT                     (1U)
+#define AIPS_PACRM_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK)
+#define AIPS_PACRM_SP7_MASK                      (0x4U)
+#define AIPS_PACRM_SP7_SHIFT                     (2U)
+#define AIPS_PACRM_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK)
+#define AIPS_PACRM_TP6_MASK                      (0x10U)
+#define AIPS_PACRM_TP6_SHIFT                     (4U)
+#define AIPS_PACRM_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK)
+#define AIPS_PACRM_WP6_MASK                      (0x20U)
+#define AIPS_PACRM_WP6_SHIFT                     (5U)
+#define AIPS_PACRM_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK)
+#define AIPS_PACRM_SP6_MASK                      (0x40U)
+#define AIPS_PACRM_SP6_SHIFT                     (6U)
+#define AIPS_PACRM_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK)
+#define AIPS_PACRM_TP5_MASK                      (0x100U)
+#define AIPS_PACRM_TP5_SHIFT                     (8U)
+#define AIPS_PACRM_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK)
+#define AIPS_PACRM_WP5_MASK                      (0x200U)
+#define AIPS_PACRM_WP5_SHIFT                     (9U)
+#define AIPS_PACRM_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK)
+#define AIPS_PACRM_SP5_MASK                      (0x400U)
+#define AIPS_PACRM_SP5_SHIFT                     (10U)
+#define AIPS_PACRM_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK)
+#define AIPS_PACRM_TP4_MASK                      (0x1000U)
+#define AIPS_PACRM_TP4_SHIFT                     (12U)
+#define AIPS_PACRM_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK)
+#define AIPS_PACRM_WP4_MASK                      (0x2000U)
+#define AIPS_PACRM_WP4_SHIFT                     (13U)
+#define AIPS_PACRM_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK)
+#define AIPS_PACRM_SP4_MASK                      (0x4000U)
+#define AIPS_PACRM_SP4_SHIFT                     (14U)
+#define AIPS_PACRM_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK)
+#define AIPS_PACRM_TP3_MASK                      (0x10000U)
+#define AIPS_PACRM_TP3_SHIFT                     (16U)
+#define AIPS_PACRM_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK)
+#define AIPS_PACRM_WP3_MASK                      (0x20000U)
+#define AIPS_PACRM_WP3_SHIFT                     (17U)
+#define AIPS_PACRM_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK)
+#define AIPS_PACRM_SP3_MASK                      (0x40000U)
+#define AIPS_PACRM_SP3_SHIFT                     (18U)
+#define AIPS_PACRM_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK)
+#define AIPS_PACRM_TP2_MASK                      (0x100000U)
+#define AIPS_PACRM_TP2_SHIFT                     (20U)
+#define AIPS_PACRM_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK)
+#define AIPS_PACRM_WP2_MASK                      (0x200000U)
+#define AIPS_PACRM_WP2_SHIFT                     (21U)
+#define AIPS_PACRM_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK)
+#define AIPS_PACRM_SP2_MASK                      (0x400000U)
+#define AIPS_PACRM_SP2_SHIFT                     (22U)
+#define AIPS_PACRM_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK)
+#define AIPS_PACRM_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRM_TP1_SHIFT                     (24U)
+#define AIPS_PACRM_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK)
+#define AIPS_PACRM_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRM_WP1_SHIFT                     (25U)
+#define AIPS_PACRM_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK)
+#define AIPS_PACRM_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRM_SP1_SHIFT                     (26U)
+#define AIPS_PACRM_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK)
+#define AIPS_PACRM_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRM_TP0_SHIFT                     (28U)
+#define AIPS_PACRM_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK)
+#define AIPS_PACRM_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRM_WP0_SHIFT                     (29U)
+#define AIPS_PACRM_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK)
+#define AIPS_PACRM_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRM_SP0_SHIFT                     (30U)
+#define AIPS_PACRM_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK)
+
+/*! @name PACRN - Peripheral Access Control Register */
+#define AIPS_PACRN_TP7_MASK                      (0x1U)
+#define AIPS_PACRN_TP7_SHIFT                     (0U)
+#define AIPS_PACRN_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK)
+#define AIPS_PACRN_WP7_MASK                      (0x2U)
+#define AIPS_PACRN_WP7_SHIFT                     (1U)
+#define AIPS_PACRN_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK)
+#define AIPS_PACRN_SP7_MASK                      (0x4U)
+#define AIPS_PACRN_SP7_SHIFT                     (2U)
+#define AIPS_PACRN_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK)
+#define AIPS_PACRN_TP6_MASK                      (0x10U)
+#define AIPS_PACRN_TP6_SHIFT                     (4U)
+#define AIPS_PACRN_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK)
+#define AIPS_PACRN_WP6_MASK                      (0x20U)
+#define AIPS_PACRN_WP6_SHIFT                     (5U)
+#define AIPS_PACRN_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK)
+#define AIPS_PACRN_SP6_MASK                      (0x40U)
+#define AIPS_PACRN_SP6_SHIFT                     (6U)
+#define AIPS_PACRN_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK)
+#define AIPS_PACRN_TP5_MASK                      (0x100U)
+#define AIPS_PACRN_TP5_SHIFT                     (8U)
+#define AIPS_PACRN_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK)
+#define AIPS_PACRN_WP5_MASK                      (0x200U)
+#define AIPS_PACRN_WP5_SHIFT                     (9U)
+#define AIPS_PACRN_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK)
+#define AIPS_PACRN_SP5_MASK                      (0x400U)
+#define AIPS_PACRN_SP5_SHIFT                     (10U)
+#define AIPS_PACRN_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK)
+#define AIPS_PACRN_TP4_MASK                      (0x1000U)
+#define AIPS_PACRN_TP4_SHIFT                     (12U)
+#define AIPS_PACRN_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK)
+#define AIPS_PACRN_WP4_MASK                      (0x2000U)
+#define AIPS_PACRN_WP4_SHIFT                     (13U)
+#define AIPS_PACRN_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK)
+#define AIPS_PACRN_SP4_MASK                      (0x4000U)
+#define AIPS_PACRN_SP4_SHIFT                     (14U)
+#define AIPS_PACRN_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK)
+#define AIPS_PACRN_TP3_MASK                      (0x10000U)
+#define AIPS_PACRN_TP3_SHIFT                     (16U)
+#define AIPS_PACRN_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK)
+#define AIPS_PACRN_WP3_MASK                      (0x20000U)
+#define AIPS_PACRN_WP3_SHIFT                     (17U)
+#define AIPS_PACRN_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK)
+#define AIPS_PACRN_SP3_MASK                      (0x40000U)
+#define AIPS_PACRN_SP3_SHIFT                     (18U)
+#define AIPS_PACRN_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK)
+#define AIPS_PACRN_TP2_MASK                      (0x100000U)
+#define AIPS_PACRN_TP2_SHIFT                     (20U)
+#define AIPS_PACRN_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK)
+#define AIPS_PACRN_WP2_MASK                      (0x200000U)
+#define AIPS_PACRN_WP2_SHIFT                     (21U)
+#define AIPS_PACRN_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK)
+#define AIPS_PACRN_SP2_MASK                      (0x400000U)
+#define AIPS_PACRN_SP2_SHIFT                     (22U)
+#define AIPS_PACRN_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK)
+#define AIPS_PACRN_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRN_TP1_SHIFT                     (24U)
+#define AIPS_PACRN_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK)
+#define AIPS_PACRN_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRN_WP1_SHIFT                     (25U)
+#define AIPS_PACRN_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK)
+#define AIPS_PACRN_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRN_SP1_SHIFT                     (26U)
+#define AIPS_PACRN_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK)
+#define AIPS_PACRN_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRN_TP0_SHIFT                     (28U)
+#define AIPS_PACRN_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK)
+#define AIPS_PACRN_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRN_WP0_SHIFT                     (29U)
+#define AIPS_PACRN_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK)
+#define AIPS_PACRN_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRN_SP0_SHIFT                     (30U)
+#define AIPS_PACRN_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK)
+
+/*! @name PACRO - Peripheral Access Control Register */
+#define AIPS_PACRO_TP7_MASK                      (0x1U)
+#define AIPS_PACRO_TP7_SHIFT                     (0U)
+#define AIPS_PACRO_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK)
+#define AIPS_PACRO_WP7_MASK                      (0x2U)
+#define AIPS_PACRO_WP7_SHIFT                     (1U)
+#define AIPS_PACRO_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK)
+#define AIPS_PACRO_SP7_MASK                      (0x4U)
+#define AIPS_PACRO_SP7_SHIFT                     (2U)
+#define AIPS_PACRO_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK)
+#define AIPS_PACRO_TP6_MASK                      (0x10U)
+#define AIPS_PACRO_TP6_SHIFT                     (4U)
+#define AIPS_PACRO_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK)
+#define AIPS_PACRO_WP6_MASK                      (0x20U)
+#define AIPS_PACRO_WP6_SHIFT                     (5U)
+#define AIPS_PACRO_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK)
+#define AIPS_PACRO_SP6_MASK                      (0x40U)
+#define AIPS_PACRO_SP6_SHIFT                     (6U)
+#define AIPS_PACRO_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK)
+#define AIPS_PACRO_TP5_MASK                      (0x100U)
+#define AIPS_PACRO_TP5_SHIFT                     (8U)
+#define AIPS_PACRO_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK)
+#define AIPS_PACRO_WP5_MASK                      (0x200U)
+#define AIPS_PACRO_WP5_SHIFT                     (9U)
+#define AIPS_PACRO_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK)
+#define AIPS_PACRO_SP5_MASK                      (0x400U)
+#define AIPS_PACRO_SP5_SHIFT                     (10U)
+#define AIPS_PACRO_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK)
+#define AIPS_PACRO_TP4_MASK                      (0x1000U)
+#define AIPS_PACRO_TP4_SHIFT                     (12U)
+#define AIPS_PACRO_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK)
+#define AIPS_PACRO_WP4_MASK                      (0x2000U)
+#define AIPS_PACRO_WP4_SHIFT                     (13U)
+#define AIPS_PACRO_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK)
+#define AIPS_PACRO_SP4_MASK                      (0x4000U)
+#define AIPS_PACRO_SP4_SHIFT                     (14U)
+#define AIPS_PACRO_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK)
+#define AIPS_PACRO_TP3_MASK                      (0x10000U)
+#define AIPS_PACRO_TP3_SHIFT                     (16U)
+#define AIPS_PACRO_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK)
+#define AIPS_PACRO_WP3_MASK                      (0x20000U)
+#define AIPS_PACRO_WP3_SHIFT                     (17U)
+#define AIPS_PACRO_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK)
+#define AIPS_PACRO_SP3_MASK                      (0x40000U)
+#define AIPS_PACRO_SP3_SHIFT                     (18U)
+#define AIPS_PACRO_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK)
+#define AIPS_PACRO_TP2_MASK                      (0x100000U)
+#define AIPS_PACRO_TP2_SHIFT                     (20U)
+#define AIPS_PACRO_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK)
+#define AIPS_PACRO_WP2_MASK                      (0x200000U)
+#define AIPS_PACRO_WP2_SHIFT                     (21U)
+#define AIPS_PACRO_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK)
+#define AIPS_PACRO_SP2_MASK                      (0x400000U)
+#define AIPS_PACRO_SP2_SHIFT                     (22U)
+#define AIPS_PACRO_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK)
+#define AIPS_PACRO_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRO_TP1_SHIFT                     (24U)
+#define AIPS_PACRO_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK)
+#define AIPS_PACRO_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRO_WP1_SHIFT                     (25U)
+#define AIPS_PACRO_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK)
+#define AIPS_PACRO_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRO_SP1_SHIFT                     (26U)
+#define AIPS_PACRO_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK)
+#define AIPS_PACRO_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRO_TP0_SHIFT                     (28U)
+#define AIPS_PACRO_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK)
+#define AIPS_PACRO_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRO_WP0_SHIFT                     (29U)
+#define AIPS_PACRO_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK)
+#define AIPS_PACRO_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRO_SP0_SHIFT                     (30U)
+#define AIPS_PACRO_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK)
+
+/*! @name PACRP - Peripheral Access Control Register */
+#define AIPS_PACRP_TP7_MASK                      (0x1U)
+#define AIPS_PACRP_TP7_SHIFT                     (0U)
+#define AIPS_PACRP_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK)
+#define AIPS_PACRP_WP7_MASK                      (0x2U)
+#define AIPS_PACRP_WP7_SHIFT                     (1U)
+#define AIPS_PACRP_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK)
+#define AIPS_PACRP_SP7_MASK                      (0x4U)
+#define AIPS_PACRP_SP7_SHIFT                     (2U)
+#define AIPS_PACRP_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK)
+#define AIPS_PACRP_TP6_MASK                      (0x10U)
+#define AIPS_PACRP_TP6_SHIFT                     (4U)
+#define AIPS_PACRP_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK)
+#define AIPS_PACRP_WP6_MASK                      (0x20U)
+#define AIPS_PACRP_WP6_SHIFT                     (5U)
+#define AIPS_PACRP_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK)
+#define AIPS_PACRP_SP6_MASK                      (0x40U)
+#define AIPS_PACRP_SP6_SHIFT                     (6U)
+#define AIPS_PACRP_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK)
+#define AIPS_PACRP_TP5_MASK                      (0x100U)
+#define AIPS_PACRP_TP5_SHIFT                     (8U)
+#define AIPS_PACRP_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK)
+#define AIPS_PACRP_WP5_MASK                      (0x200U)
+#define AIPS_PACRP_WP5_SHIFT                     (9U)
+#define AIPS_PACRP_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK)
+#define AIPS_PACRP_SP5_MASK                      (0x400U)
+#define AIPS_PACRP_SP5_SHIFT                     (10U)
+#define AIPS_PACRP_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK)
+#define AIPS_PACRP_TP4_MASK                      (0x1000U)
+#define AIPS_PACRP_TP4_SHIFT                     (12U)
+#define AIPS_PACRP_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK)
+#define AIPS_PACRP_WP4_MASK                      (0x2000U)
+#define AIPS_PACRP_WP4_SHIFT                     (13U)
+#define AIPS_PACRP_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK)
+#define AIPS_PACRP_SP4_MASK                      (0x4000U)
+#define AIPS_PACRP_SP4_SHIFT                     (14U)
+#define AIPS_PACRP_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK)
+#define AIPS_PACRP_TP3_MASK                      (0x10000U)
+#define AIPS_PACRP_TP3_SHIFT                     (16U)
+#define AIPS_PACRP_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK)
+#define AIPS_PACRP_WP3_MASK                      (0x20000U)
+#define AIPS_PACRP_WP3_SHIFT                     (17U)
+#define AIPS_PACRP_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK)
+#define AIPS_PACRP_SP3_MASK                      (0x40000U)
+#define AIPS_PACRP_SP3_SHIFT                     (18U)
+#define AIPS_PACRP_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK)
+#define AIPS_PACRP_TP2_MASK                      (0x100000U)
+#define AIPS_PACRP_TP2_SHIFT                     (20U)
+#define AIPS_PACRP_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK)
+#define AIPS_PACRP_WP2_MASK                      (0x200000U)
+#define AIPS_PACRP_WP2_SHIFT                     (21U)
+#define AIPS_PACRP_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK)
+#define AIPS_PACRP_SP2_MASK                      (0x400000U)
+#define AIPS_PACRP_SP2_SHIFT                     (22U)
+#define AIPS_PACRP_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK)
+#define AIPS_PACRP_TP1_MASK                      (0x1000000U)
+#define AIPS_PACRP_TP1_SHIFT                     (24U)
+#define AIPS_PACRP_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK)
+#define AIPS_PACRP_WP1_MASK                      (0x2000000U)
+#define AIPS_PACRP_WP1_SHIFT                     (25U)
+#define AIPS_PACRP_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK)
+#define AIPS_PACRP_SP1_MASK                      (0x4000000U)
+#define AIPS_PACRP_SP1_SHIFT                     (26U)
+#define AIPS_PACRP_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK)
+#define AIPS_PACRP_TP0_MASK                      (0x10000000U)
+#define AIPS_PACRP_TP0_SHIFT                     (28U)
+#define AIPS_PACRP_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK)
+#define AIPS_PACRP_WP0_MASK                      (0x20000000U)
+#define AIPS_PACRP_WP0_SHIFT                     (29U)
+#define AIPS_PACRP_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK)
+#define AIPS_PACRP_SP0_MASK                      (0x40000000U)
+#define AIPS_PACRP_SP0_SHIFT                     (30U)
+#define AIPS_PACRP_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group AIPS_Register_Masks */
+
+
+/* AIPS - Peripheral instance base addresses */
+/** Peripheral AIPS0 base address */
+#define AIPS0_BASE                               (0x40000000u)
+/** Peripheral AIPS0 base pointer */
+#define AIPS0                                    ((AIPS_Type *)AIPS0_BASE)
+/** Peripheral AIPS1 base address */
+#define AIPS1_BASE                               (0x40080000u)
+/** Peripheral AIPS1 base pointer */
+#define AIPS1                                    ((AIPS_Type *)AIPS1_BASE)
+/** Array initializer of AIPS peripheral base addresses */
+#define AIPS_BASE_ADDRS                          { AIPS0_BASE, AIPS1_BASE }
+/** Array initializer of AIPS peripheral base pointers */
+#define AIPS_BASE_PTRS                           { AIPS0, AIPS1 }
+
+/*!
+ * @}
+ */ /* end of group AIPS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- AXBS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
+ * @{
+ */
+
+/** AXBS - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x100 */
+    __IO uint32_t PRS;                               /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
+         uint8_t RESERVED_0[12];
+    __IO uint32_t CRS;                               /**< Control Register, array offset: 0x10, array step: 0x100 */
+         uint8_t RESERVED_1[236];
+  } SLAVE[5];
+       uint8_t RESERVED_0[768];
+  __IO uint32_t MGPCR0;                            /**< Master General Purpose Control Register, offset: 0x800 */
+       uint8_t RESERVED_1[252];
+  __IO uint32_t MGPCR1;                            /**< Master General Purpose Control Register, offset: 0x900 */
+       uint8_t RESERVED_2[252];
+  __IO uint32_t MGPCR2;                            /**< Master General Purpose Control Register, offset: 0xA00 */
+       uint8_t RESERVED_3[252];
+  __IO uint32_t MGPCR3;                            /**< Master General Purpose Control Register, offset: 0xB00 */
+       uint8_t RESERVED_4[252];
+  __IO uint32_t MGPCR4;                            /**< Master General Purpose Control Register, offset: 0xC00 */
+       uint8_t RESERVED_5[252];
+  __IO uint32_t MGPCR5;                            /**< Master General Purpose Control Register, offset: 0xD00 */
+       uint8_t RESERVED_6[252];
+  __IO uint32_t MGPCR6;                            /**< Master General Purpose Control Register, offset: 0xE00 */
+} AXBS_Type;
+
+/* ----------------------------------------------------------------------------
+   -- AXBS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup AXBS_Register_Masks AXBS Register Masks
+ * @{
+ */
+
+/*! @name PRS - Priority Registers Slave */
+#define AXBS_PRS_M0_MASK                         (0x7U)
+#define AXBS_PRS_M0_SHIFT                        (0U)
+#define AXBS_PRS_M0(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)
+#define AXBS_PRS_M1_MASK                         (0x70U)
+#define AXBS_PRS_M1_SHIFT                        (4U)
+#define AXBS_PRS_M1(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)
+#define AXBS_PRS_M2_MASK                         (0x700U)
+#define AXBS_PRS_M2_SHIFT                        (8U)
+#define AXBS_PRS_M2(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)
+#define AXBS_PRS_M3_MASK                         (0x7000U)
+#define AXBS_PRS_M3_SHIFT                        (12U)
+#define AXBS_PRS_M3(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK)
+#define AXBS_PRS_M4_MASK                         (0x70000U)
+#define AXBS_PRS_M4_SHIFT                        (16U)
+#define AXBS_PRS_M4(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK)
+#define AXBS_PRS_M5_MASK                         (0x700000U)
+#define AXBS_PRS_M5_SHIFT                        (20U)
+#define AXBS_PRS_M5(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK)
+#define AXBS_PRS_M6_MASK                         (0x7000000U)
+#define AXBS_PRS_M6_SHIFT                        (24U)
+#define AXBS_PRS_M6(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M6_SHIFT)) & AXBS_PRS_M6_MASK)
+
+/* The count of AXBS_PRS */
+#define AXBS_PRS_COUNT                           (5U)
+
+/*! @name CRS - Control Register */
+#define AXBS_CRS_PARK_MASK                       (0x7U)
+#define AXBS_CRS_PARK_SHIFT                      (0U)
+#define AXBS_CRS_PARK(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)
+#define AXBS_CRS_PCTL_MASK                       (0x30U)
+#define AXBS_CRS_PCTL_SHIFT                      (4U)
+#define AXBS_CRS_PCTL(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)
+#define AXBS_CRS_ARB_MASK                        (0x300U)
+#define AXBS_CRS_ARB_SHIFT                       (8U)
+#define AXBS_CRS_ARB(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)
+#define AXBS_CRS_HLP_MASK                        (0x40000000U)
+#define AXBS_CRS_HLP_SHIFT                       (30U)
+#define AXBS_CRS_HLP(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK)
+#define AXBS_CRS_RO_MASK                         (0x80000000U)
+#define AXBS_CRS_RO_SHIFT                        (31U)
+#define AXBS_CRS_RO(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK)
+
+/* The count of AXBS_CRS */
+#define AXBS_CRS_COUNT                           (5U)
+
+/*! @name MGPCR0 - Master General Purpose Control Register */
+#define AXBS_MGPCR0_AULB_MASK                    (0x7U)
+#define AXBS_MGPCR0_AULB_SHIFT                   (0U)
+#define AXBS_MGPCR0_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK)
+
+/*! @name MGPCR1 - Master General Purpose Control Register */
+#define AXBS_MGPCR1_AULB_MASK                    (0x7U)
+#define AXBS_MGPCR1_AULB_SHIFT                   (0U)
+#define AXBS_MGPCR1_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK)
+
+/*! @name MGPCR2 - Master General Purpose Control Register */
+#define AXBS_MGPCR2_AULB_MASK                    (0x7U)
+#define AXBS_MGPCR2_AULB_SHIFT                   (0U)
+#define AXBS_MGPCR2_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK)
+
+/*! @name MGPCR3 - Master General Purpose Control Register */
+#define AXBS_MGPCR3_AULB_MASK                    (0x7U)
+#define AXBS_MGPCR3_AULB_SHIFT                   (0U)
+#define AXBS_MGPCR3_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK)
+
+/*! @name MGPCR4 - Master General Purpose Control Register */
+#define AXBS_MGPCR4_AULB_MASK                    (0x7U)
+#define AXBS_MGPCR4_AULB_SHIFT                   (0U)
+#define AXBS_MGPCR4_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK)
+
+/*! @name MGPCR5 - Master General Purpose Control Register */
+#define AXBS_MGPCR5_AULB_MASK                    (0x7U)
+#define AXBS_MGPCR5_AULB_SHIFT                   (0U)
+#define AXBS_MGPCR5_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK)
+
+/*! @name MGPCR6 - Master General Purpose Control Register */
+#define AXBS_MGPCR6_AULB_MASK                    (0x7U)
+#define AXBS_MGPCR6_AULB_SHIFT                   (0U)
+#define AXBS_MGPCR6_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR6_AULB_SHIFT)) & AXBS_MGPCR6_AULB_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group AXBS_Register_Masks */
+
+
+/* AXBS - Peripheral instance base addresses */
+/** Peripheral AXBS base address */
+#define AXBS_BASE                                (0x40004000u)
+/** Peripheral AXBS base pointer */
+#define AXBS                                     ((AXBS_Type *)AXBS_BASE)
+/** Array initializer of AXBS peripheral base addresses */
+#define AXBS_BASE_ADDRS                          { AXBS_BASE }
+/** Array initializer of AXBS peripheral base pointers */
+#define AXBS_BASE_PTRS                           { AXBS }
+
+/*!
+ * @}
+ */ /* end of group AXBS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAN Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
+ * @{
+ */
+
+/** CAN - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< Module Configuration Register, offset: 0x0 */
+  __IO uint32_t CTRL1;                             /**< Control 1 register, offset: 0x4 */
+  __IO uint32_t TIMER;                             /**< Free Running Timer, offset: 0x8 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t RXMGMASK;                          /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
+  __IO uint32_t RX14MASK;                          /**< Rx 14 Mask register, offset: 0x14 */
+  __IO uint32_t RX15MASK;                          /**< Rx 15 Mask register, offset: 0x18 */
+  __IO uint32_t ECR;                               /**< Error Counter, offset: 0x1C */
+  __IO uint32_t ESR1;                              /**< Error and Status 1 register, offset: 0x20 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t IMASK1;                            /**< Interrupt Masks 1 register, offset: 0x28 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t IFLAG1;                            /**< Interrupt Flags 1 register, offset: 0x30 */
+  __IO uint32_t CTRL2;                             /**< Control 2 register, offset: 0x34 */
+  __I  uint32_t ESR2;                              /**< Error and Status 2 register, offset: 0x38 */
+       uint8_t RESERVED_3[8];
+  __I  uint32_t CRCR;                              /**< CRC Register, offset: 0x44 */
+  __IO uint32_t RXFGMASK;                          /**< Rx FIFO Global Mask register, offset: 0x48 */
+  __I  uint32_t RXFIR;                             /**< Rx FIFO Information Register, offset: 0x4C */
+       uint8_t RESERVED_4[48];
+  struct {                                         /* offset: 0x80, array step: 0x10 */
+    __IO uint32_t CS;                                /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
+    __IO uint32_t ID;                                /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
+    __IO uint32_t WORD0;                             /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
+    __IO uint32_t WORD1;                             /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
+  } MB[16];
+       uint8_t RESERVED_5[1792];
+  __IO uint32_t RXIMR[16];                         /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
+} CAN_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CAN Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Masks CAN Register Masks
+ * @{
+ */
+
+/*! @name MCR - Module Configuration Register */
+#define CAN_MCR_MAXMB_MASK                       (0x7FU)
+#define CAN_MCR_MAXMB_SHIFT                      (0U)
+#define CAN_MCR_MAXMB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
+#define CAN_MCR_IDAM_MASK                        (0x300U)
+#define CAN_MCR_IDAM_SHIFT                       (8U)
+#define CAN_MCR_IDAM(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
+#define CAN_MCR_AEN_MASK                         (0x1000U)
+#define CAN_MCR_AEN_SHIFT                        (12U)
+#define CAN_MCR_AEN(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
+#define CAN_MCR_LPRIOEN_MASK                     (0x2000U)
+#define CAN_MCR_LPRIOEN_SHIFT                    (13U)
+#define CAN_MCR_LPRIOEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
+#define CAN_MCR_IRMQ_MASK                        (0x10000U)
+#define CAN_MCR_IRMQ_SHIFT                       (16U)
+#define CAN_MCR_IRMQ(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
+#define CAN_MCR_SRXDIS_MASK                      (0x20000U)
+#define CAN_MCR_SRXDIS_SHIFT                     (17U)
+#define CAN_MCR_SRXDIS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
+#define CAN_MCR_WAKSRC_MASK                      (0x80000U)
+#define CAN_MCR_WAKSRC_SHIFT                     (19U)
+#define CAN_MCR_WAKSRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
+#define CAN_MCR_LPMACK_MASK                      (0x100000U)
+#define CAN_MCR_LPMACK_SHIFT                     (20U)
+#define CAN_MCR_LPMACK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
+#define CAN_MCR_WRNEN_MASK                       (0x200000U)
+#define CAN_MCR_WRNEN_SHIFT                      (21U)
+#define CAN_MCR_WRNEN(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
+#define CAN_MCR_SLFWAK_MASK                      (0x400000U)
+#define CAN_MCR_SLFWAK_SHIFT                     (22U)
+#define CAN_MCR_SLFWAK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
+#define CAN_MCR_SUPV_MASK                        (0x800000U)
+#define CAN_MCR_SUPV_SHIFT                       (23U)
+#define CAN_MCR_SUPV(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
+#define CAN_MCR_FRZACK_MASK                      (0x1000000U)
+#define CAN_MCR_FRZACK_SHIFT                     (24U)
+#define CAN_MCR_FRZACK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
+#define CAN_MCR_SOFTRST_MASK                     (0x2000000U)
+#define CAN_MCR_SOFTRST_SHIFT                    (25U)
+#define CAN_MCR_SOFTRST(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
+#define CAN_MCR_WAKMSK_MASK                      (0x4000000U)
+#define CAN_MCR_WAKMSK_SHIFT                     (26U)
+#define CAN_MCR_WAKMSK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
+#define CAN_MCR_NOTRDY_MASK                      (0x8000000U)
+#define CAN_MCR_NOTRDY_SHIFT                     (27U)
+#define CAN_MCR_NOTRDY(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
+#define CAN_MCR_HALT_MASK                        (0x10000000U)
+#define CAN_MCR_HALT_SHIFT                       (28U)
+#define CAN_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
+#define CAN_MCR_RFEN_MASK                        (0x20000000U)
+#define CAN_MCR_RFEN_SHIFT                       (29U)
+#define CAN_MCR_RFEN(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
+#define CAN_MCR_FRZ_MASK                         (0x40000000U)
+#define CAN_MCR_FRZ_SHIFT                        (30U)
+#define CAN_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
+#define CAN_MCR_MDIS_MASK                        (0x80000000U)
+#define CAN_MCR_MDIS_SHIFT                       (31U)
+#define CAN_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
+
+/*! @name CTRL1 - Control 1 register */
+#define CAN_CTRL1_PROPSEG_MASK                   (0x7U)
+#define CAN_CTRL1_PROPSEG_SHIFT                  (0U)
+#define CAN_CTRL1_PROPSEG(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
+#define CAN_CTRL1_LOM_MASK                       (0x8U)
+#define CAN_CTRL1_LOM_SHIFT                      (3U)
+#define CAN_CTRL1_LOM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
+#define CAN_CTRL1_LBUF_MASK                      (0x10U)
+#define CAN_CTRL1_LBUF_SHIFT                     (4U)
+#define CAN_CTRL1_LBUF(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
+#define CAN_CTRL1_TSYN_MASK                      (0x20U)
+#define CAN_CTRL1_TSYN_SHIFT                     (5U)
+#define CAN_CTRL1_TSYN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
+#define CAN_CTRL1_BOFFREC_MASK                   (0x40U)
+#define CAN_CTRL1_BOFFREC_SHIFT                  (6U)
+#define CAN_CTRL1_BOFFREC(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
+#define CAN_CTRL1_SMP_MASK                       (0x80U)
+#define CAN_CTRL1_SMP_SHIFT                      (7U)
+#define CAN_CTRL1_SMP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
+#define CAN_CTRL1_RWRNMSK_MASK                   (0x400U)
+#define CAN_CTRL1_RWRNMSK_SHIFT                  (10U)
+#define CAN_CTRL1_RWRNMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
+#define CAN_CTRL1_TWRNMSK_MASK                   (0x800U)
+#define CAN_CTRL1_TWRNMSK_SHIFT                  (11U)
+#define CAN_CTRL1_TWRNMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
+#define CAN_CTRL1_LPB_MASK                       (0x1000U)
+#define CAN_CTRL1_LPB_SHIFT                      (12U)
+#define CAN_CTRL1_LPB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
+#define CAN_CTRL1_CLKSRC_MASK                    (0x2000U)
+#define CAN_CTRL1_CLKSRC_SHIFT                   (13U)
+#define CAN_CTRL1_CLKSRC(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
+#define CAN_CTRL1_ERRMSK_MASK                    (0x4000U)
+#define CAN_CTRL1_ERRMSK_SHIFT                   (14U)
+#define CAN_CTRL1_ERRMSK(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
+#define CAN_CTRL1_BOFFMSK_MASK                   (0x8000U)
+#define CAN_CTRL1_BOFFMSK_SHIFT                  (15U)
+#define CAN_CTRL1_BOFFMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
+#define CAN_CTRL1_PSEG2_MASK                     (0x70000U)
+#define CAN_CTRL1_PSEG2_SHIFT                    (16U)
+#define CAN_CTRL1_PSEG2(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
+#define CAN_CTRL1_PSEG1_MASK                     (0x380000U)
+#define CAN_CTRL1_PSEG1_SHIFT                    (19U)
+#define CAN_CTRL1_PSEG1(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
+#define CAN_CTRL1_RJW_MASK                       (0xC00000U)
+#define CAN_CTRL1_RJW_SHIFT                      (22U)
+#define CAN_CTRL1_RJW(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
+#define CAN_CTRL1_PRESDIV_MASK                   (0xFF000000U)
+#define CAN_CTRL1_PRESDIV_SHIFT                  (24U)
+#define CAN_CTRL1_PRESDIV(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
+
+/*! @name TIMER - Free Running Timer */
+#define CAN_TIMER_TIMER_MASK                     (0xFFFFU)
+#define CAN_TIMER_TIMER_SHIFT                    (0U)
+#define CAN_TIMER_TIMER(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
+
+/*! @name RXMGMASK - Rx Mailboxes Global Mask Register */
+#define CAN_RXMGMASK_MG_MASK                     (0xFFFFFFFFU)
+#define CAN_RXMGMASK_MG_SHIFT                    (0U)
+#define CAN_RXMGMASK_MG(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
+
+/*! @name RX14MASK - Rx 14 Mask register */
+#define CAN_RX14MASK_RX14M_MASK                  (0xFFFFFFFFU)
+#define CAN_RX14MASK_RX14M_SHIFT                 (0U)
+#define CAN_RX14MASK_RX14M(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
+
+/*! @name RX15MASK - Rx 15 Mask register */
+#define CAN_RX15MASK_RX15M_MASK                  (0xFFFFFFFFU)
+#define CAN_RX15MASK_RX15M_SHIFT                 (0U)
+#define CAN_RX15MASK_RX15M(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
+
+/*! @name ECR - Error Counter */
+#define CAN_ECR_TXERRCNT_MASK                    (0xFFU)
+#define CAN_ECR_TXERRCNT_SHIFT                   (0U)
+#define CAN_ECR_TXERRCNT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
+#define CAN_ECR_RXERRCNT_MASK                    (0xFF00U)
+#define CAN_ECR_RXERRCNT_SHIFT                   (8U)
+#define CAN_ECR_RXERRCNT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
+
+/*! @name ESR1 - Error and Status 1 register */
+#define CAN_ESR1_WAKINT_MASK                     (0x1U)
+#define CAN_ESR1_WAKINT_SHIFT                    (0U)
+#define CAN_ESR1_WAKINT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
+#define CAN_ESR1_ERRINT_MASK                     (0x2U)
+#define CAN_ESR1_ERRINT_SHIFT                    (1U)
+#define CAN_ESR1_ERRINT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
+#define CAN_ESR1_BOFFINT_MASK                    (0x4U)
+#define CAN_ESR1_BOFFINT_SHIFT                   (2U)
+#define CAN_ESR1_BOFFINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
+#define CAN_ESR1_RX_MASK                         (0x8U)
+#define CAN_ESR1_RX_SHIFT                        (3U)
+#define CAN_ESR1_RX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
+#define CAN_ESR1_FLTCONF_MASK                    (0x30U)
+#define CAN_ESR1_FLTCONF_SHIFT                   (4U)
+#define CAN_ESR1_FLTCONF(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
+#define CAN_ESR1_TX_MASK                         (0x40U)
+#define CAN_ESR1_TX_SHIFT                        (6U)
+#define CAN_ESR1_TX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
+#define CAN_ESR1_IDLE_MASK                       (0x80U)
+#define CAN_ESR1_IDLE_SHIFT                      (7U)
+#define CAN_ESR1_IDLE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
+#define CAN_ESR1_RXWRN_MASK                      (0x100U)
+#define CAN_ESR1_RXWRN_SHIFT                     (8U)
+#define CAN_ESR1_RXWRN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
+#define CAN_ESR1_TXWRN_MASK                      (0x200U)
+#define CAN_ESR1_TXWRN_SHIFT                     (9U)
+#define CAN_ESR1_TXWRN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
+#define CAN_ESR1_STFERR_MASK                     (0x400U)
+#define CAN_ESR1_STFERR_SHIFT                    (10U)
+#define CAN_ESR1_STFERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
+#define CAN_ESR1_FRMERR_MASK                     (0x800U)
+#define CAN_ESR1_FRMERR_SHIFT                    (11U)
+#define CAN_ESR1_FRMERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
+#define CAN_ESR1_CRCERR_MASK                     (0x1000U)
+#define CAN_ESR1_CRCERR_SHIFT                    (12U)
+#define CAN_ESR1_CRCERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
+#define CAN_ESR1_ACKERR_MASK                     (0x2000U)
+#define CAN_ESR1_ACKERR_SHIFT                    (13U)
+#define CAN_ESR1_ACKERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
+#define CAN_ESR1_BIT0ERR_MASK                    (0x4000U)
+#define CAN_ESR1_BIT0ERR_SHIFT                   (14U)
+#define CAN_ESR1_BIT0ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
+#define CAN_ESR1_BIT1ERR_MASK                    (0x8000U)
+#define CAN_ESR1_BIT1ERR_SHIFT                   (15U)
+#define CAN_ESR1_BIT1ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
+#define CAN_ESR1_RWRNINT_MASK                    (0x10000U)
+#define CAN_ESR1_RWRNINT_SHIFT                   (16U)
+#define CAN_ESR1_RWRNINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
+#define CAN_ESR1_TWRNINT_MASK                    (0x20000U)
+#define CAN_ESR1_TWRNINT_SHIFT                   (17U)
+#define CAN_ESR1_TWRNINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
+#define CAN_ESR1_SYNCH_MASK                      (0x40000U)
+#define CAN_ESR1_SYNCH_SHIFT                     (18U)
+#define CAN_ESR1_SYNCH(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
+
+/*! @name IMASK1 - Interrupt Masks 1 register */
+#define CAN_IMASK1_BUFLM_MASK                    (0xFFFFFFFFU)
+#define CAN_IMASK1_BUFLM_SHIFT                   (0U)
+#define CAN_IMASK1_BUFLM(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)
+
+/*! @name IFLAG1 - Interrupt Flags 1 register */
+#define CAN_IFLAG1_BUF0I_MASK                    (0x1U)
+#define CAN_IFLAG1_BUF0I_SHIFT                   (0U)
+#define CAN_IFLAG1_BUF0I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
+#define CAN_IFLAG1_BUF4TO1I_MASK                 (0x1EU)
+#define CAN_IFLAG1_BUF4TO1I_SHIFT                (1U)
+#define CAN_IFLAG1_BUF4TO1I(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
+#define CAN_IFLAG1_BUF5I_MASK                    (0x20U)
+#define CAN_IFLAG1_BUF5I_SHIFT                   (5U)
+#define CAN_IFLAG1_BUF5I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
+#define CAN_IFLAG1_BUF6I_MASK                    (0x40U)
+#define CAN_IFLAG1_BUF6I_SHIFT                   (6U)
+#define CAN_IFLAG1_BUF6I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
+#define CAN_IFLAG1_BUF7I_MASK                    (0x80U)
+#define CAN_IFLAG1_BUF7I_SHIFT                   (7U)
+#define CAN_IFLAG1_BUF7I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
+#define CAN_IFLAG1_BUF31TO8I_MASK                (0xFFFFFF00U)
+#define CAN_IFLAG1_BUF31TO8I_SHIFT               (8U)
+#define CAN_IFLAG1_BUF31TO8I(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
+
+/*! @name CTRL2 - Control 2 register */
+#define CAN_CTRL2_EACEN_MASK                     (0x10000U)
+#define CAN_CTRL2_EACEN_SHIFT                    (16U)
+#define CAN_CTRL2_EACEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
+#define CAN_CTRL2_RRS_MASK                       (0x20000U)
+#define CAN_CTRL2_RRS_SHIFT                      (17U)
+#define CAN_CTRL2_RRS(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
+#define CAN_CTRL2_MRP_MASK                       (0x40000U)
+#define CAN_CTRL2_MRP_SHIFT                      (18U)
+#define CAN_CTRL2_MRP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
+#define CAN_CTRL2_TASD_MASK                      (0xF80000U)
+#define CAN_CTRL2_TASD_SHIFT                     (19U)
+#define CAN_CTRL2_TASD(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
+#define CAN_CTRL2_RFFN_MASK                      (0xF000000U)
+#define CAN_CTRL2_RFFN_SHIFT                     (24U)
+#define CAN_CTRL2_RFFN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
+#define CAN_CTRL2_WRMFRZ_MASK                    (0x10000000U)
+#define CAN_CTRL2_WRMFRZ_SHIFT                   (28U)
+#define CAN_CTRL2_WRMFRZ(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
+
+/*! @name ESR2 - Error and Status 2 register */
+#define CAN_ESR2_IMB_MASK                        (0x2000U)
+#define CAN_ESR2_IMB_SHIFT                       (13U)
+#define CAN_ESR2_IMB(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
+#define CAN_ESR2_VPS_MASK                        (0x4000U)
+#define CAN_ESR2_VPS_SHIFT                       (14U)
+#define CAN_ESR2_VPS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
+#define CAN_ESR2_LPTM_MASK                       (0x7F0000U)
+#define CAN_ESR2_LPTM_SHIFT                      (16U)
+#define CAN_ESR2_LPTM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
+
+/*! @name CRCR - CRC Register */
+#define CAN_CRCR_TXCRC_MASK                      (0x7FFFU)
+#define CAN_CRCR_TXCRC_SHIFT                     (0U)
+#define CAN_CRCR_TXCRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
+#define CAN_CRCR_MBCRC_MASK                      (0x7F0000U)
+#define CAN_CRCR_MBCRC_SHIFT                     (16U)
+#define CAN_CRCR_MBCRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
+
+/*! @name RXFGMASK - Rx FIFO Global Mask register */
+#define CAN_RXFGMASK_FGM_MASK                    (0xFFFFFFFFU)
+#define CAN_RXFGMASK_FGM_SHIFT                   (0U)
+#define CAN_RXFGMASK_FGM(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
+
+/*! @name RXFIR - Rx FIFO Information Register */
+#define CAN_RXFIR_IDHIT_MASK                     (0x1FFU)
+#define CAN_RXFIR_IDHIT_SHIFT                    (0U)
+#define CAN_RXFIR_IDHIT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
+
+/*! @name CS - Message Buffer 0 CS Register..Message Buffer 15 CS Register */
+#define CAN_CS_TIME_STAMP_MASK                   (0xFFFFU)
+#define CAN_CS_TIME_STAMP_SHIFT                  (0U)
+#define CAN_CS_TIME_STAMP(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
+#define CAN_CS_DLC_MASK                          (0xF0000U)
+#define CAN_CS_DLC_SHIFT                         (16U)
+#define CAN_CS_DLC(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
+#define CAN_CS_RTR_MASK                          (0x100000U)
+#define CAN_CS_RTR_SHIFT                         (20U)
+#define CAN_CS_RTR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
+#define CAN_CS_IDE_MASK                          (0x200000U)
+#define CAN_CS_IDE_SHIFT                         (21U)
+#define CAN_CS_IDE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
+#define CAN_CS_SRR_MASK                          (0x400000U)
+#define CAN_CS_SRR_SHIFT                         (22U)
+#define CAN_CS_SRR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
+#define CAN_CS_CODE_MASK                         (0xF000000U)
+#define CAN_CS_CODE_SHIFT                        (24U)
+#define CAN_CS_CODE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
+
+/* The count of CAN_CS */
+#define CAN_CS_COUNT                             (16U)
+
+/*! @name ID - Message Buffer 0 ID Register..Message Buffer 15 ID Register */
+#define CAN_ID_EXT_MASK                          (0x3FFFFU)
+#define CAN_ID_EXT_SHIFT                         (0U)
+#define CAN_ID_EXT(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
+#define CAN_ID_STD_MASK                          (0x1FFC0000U)
+#define CAN_ID_STD_SHIFT                         (18U)
+#define CAN_ID_STD(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
+#define CAN_ID_PRIO_MASK                         (0xE0000000U)
+#define CAN_ID_PRIO_SHIFT                        (29U)
+#define CAN_ID_PRIO(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
+
+/* The count of CAN_ID */
+#define CAN_ID_COUNT                             (16U)
+
+/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register */
+#define CAN_WORD0_DATA_BYTE_3_MASK               (0xFFU)
+#define CAN_WORD0_DATA_BYTE_3_SHIFT              (0U)
+#define CAN_WORD0_DATA_BYTE_3(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
+#define CAN_WORD0_DATA_BYTE_2_MASK               (0xFF00U)
+#define CAN_WORD0_DATA_BYTE_2_SHIFT              (8U)
+#define CAN_WORD0_DATA_BYTE_2(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
+#define CAN_WORD0_DATA_BYTE_1_MASK               (0xFF0000U)
+#define CAN_WORD0_DATA_BYTE_1_SHIFT              (16U)
+#define CAN_WORD0_DATA_BYTE_1(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
+#define CAN_WORD0_DATA_BYTE_0_MASK               (0xFF000000U)
+#define CAN_WORD0_DATA_BYTE_0_SHIFT              (24U)
+#define CAN_WORD0_DATA_BYTE_0(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
+
+/* The count of CAN_WORD0 */
+#define CAN_WORD0_COUNT                          (16U)
+
+/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register */
+#define CAN_WORD1_DATA_BYTE_7_MASK               (0xFFU)
+#define CAN_WORD1_DATA_BYTE_7_SHIFT              (0U)
+#define CAN_WORD1_DATA_BYTE_7(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
+#define CAN_WORD1_DATA_BYTE_6_MASK               (0xFF00U)
+#define CAN_WORD1_DATA_BYTE_6_SHIFT              (8U)
+#define CAN_WORD1_DATA_BYTE_6(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
+#define CAN_WORD1_DATA_BYTE_5_MASK               (0xFF0000U)
+#define CAN_WORD1_DATA_BYTE_5_SHIFT              (16U)
+#define CAN_WORD1_DATA_BYTE_5(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
+#define CAN_WORD1_DATA_BYTE_4_MASK               (0xFF000000U)
+#define CAN_WORD1_DATA_BYTE_4_SHIFT              (24U)
+#define CAN_WORD1_DATA_BYTE_4(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
+
+/* The count of CAN_WORD1 */
+#define CAN_WORD1_COUNT                          (16U)
+
+/*! @name RXIMR - Rx Individual Mask Registers */
+#define CAN_RXIMR_MI_MASK                        (0xFFFFFFFFU)
+#define CAN_RXIMR_MI_SHIFT                       (0U)
+#define CAN_RXIMR_MI(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
+
+/* The count of CAN_RXIMR */
+#define CAN_RXIMR_COUNT                          (16U)
+
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Masks */
+
+
+/* CAN - Peripheral instance base addresses */
+/** Peripheral CAN0 base address */
+#define CAN0_BASE                                (0x40024000u)
+/** Peripheral CAN0 base pointer */
+#define CAN0                                     ((CAN_Type *)CAN0_BASE)
+/** Peripheral CAN1 base address */
+#define CAN1_BASE                                (0x400A4000u)
+/** Peripheral CAN1 base pointer */
+#define CAN1                                     ((CAN_Type *)CAN1_BASE)
+/** Array initializer of CAN peripheral base addresses */
+#define CAN_BASE_ADDRS                           { CAN0_BASE, CAN1_BASE }
+/** Array initializer of CAN peripheral base pointers */
+#define CAN_BASE_PTRS                            { CAN0, CAN1 }
+/** Interrupt vectors for the CAN peripheral type */
+#define CAN_Rx_Warning_IRQS                      { CAN0_Rx_Warning_IRQn, CAN1_Rx_Warning_IRQn }
+#define CAN_Tx_Warning_IRQS                      { CAN0_Tx_Warning_IRQn, CAN1_Tx_Warning_IRQn }
+#define CAN_Wake_Up_IRQS                         { CAN0_Wake_Up_IRQn, CAN1_Wake_Up_IRQn }
+#define CAN_Error_IRQS                           { CAN0_Error_IRQn, CAN1_Error_IRQn }
+#define CAN_Bus_Off_IRQS                         { CAN0_Bus_Off_IRQn, CAN1_Bus_Off_IRQn }
+#define CAN_ORed_Message_buffer_IRQS             { CAN0_ORed_Message_buffer_IRQn, CAN1_ORed_Message_buffer_IRQn }
+
+/*!
+ * @}
+ */ /* end of group CAN_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CAU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
+ * @{
+ */
+
+/** CAU - Register Layout Typedef */
+typedef struct {
+  __O  uint32_t DIRECT[16];                        /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
+       uint8_t RESERVED_0[2048];
+  __O  uint32_t LDR_CASR;                          /**< Status register - Load Register command, offset: 0x840 */
+  __O  uint32_t LDR_CAA;                           /**< Accumulator register - Load Register command, offset: 0x844 */
+  __O  uint32_t LDR_CA[9];                         /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
+       uint8_t RESERVED_1[20];
+  __I  uint32_t STR_CASR;                          /**< Status register - Store Register command, offset: 0x880 */
+  __I  uint32_t STR_CAA;                           /**< Accumulator register - Store Register command, offset: 0x884 */
+  __I  uint32_t STR_CA[9];                         /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
+       uint8_t RESERVED_2[20];
+  __O  uint32_t ADR_CASR;                          /**< Status register - Add Register command, offset: 0x8C0 */
+  __O  uint32_t ADR_CAA;                           /**< Accumulator register - Add to register command, offset: 0x8C4 */
+  __O  uint32_t ADR_CA[9];                         /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
+       uint8_t RESERVED_3[20];
+  __O  uint32_t RADR_CASR;                         /**< Status register - Reverse and Add to Register command, offset: 0x900 */
+  __O  uint32_t RADR_CAA;                          /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
+  __O  uint32_t RADR_CA[9];                        /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
+       uint8_t RESERVED_4[84];
+  __O  uint32_t XOR_CASR;                          /**< Status register - Exclusive Or command, offset: 0x980 */
+  __O  uint32_t XOR_CAA;                           /**< Accumulator register - Exclusive Or command, offset: 0x984 */
+  __O  uint32_t XOR_CA[9];                         /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
+       uint8_t RESERVED_5[20];
+  __O  uint32_t ROTL_CASR;                         /**< Status register - Rotate Left command, offset: 0x9C0 */
+  __O  uint32_t ROTL_CAA;                          /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
+  __O  uint32_t ROTL_CA[9];                        /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
+       uint8_t RESERVED_6[276];
+  __O  uint32_t AESC_CASR;                         /**< Status register - AES Column Operation command, offset: 0xB00 */
+  __O  uint32_t AESC_CAA;                          /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
+  __O  uint32_t AESC_CA[9];                        /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
+       uint8_t RESERVED_7[20];
+  __O  uint32_t AESIC_CASR;                        /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
+  __O  uint32_t AESIC_CAA;                         /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
+  __O  uint32_t AESIC_CA[9];                       /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
+} CAU_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CAU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAU_Register_Masks CAU Register Masks
+ * @{
+ */
+
+/*! @name DIRECT - Direct access register 0..Direct access register 15 */
+#define CAU_DIRECT_CAU_DIRECT0_MASK              (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT0_SHIFT             (0U)
+#define CAU_DIRECT_CAU_DIRECT0(x)                (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK)
+#define CAU_DIRECT_CAU_DIRECT1_MASK              (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT1_SHIFT             (0U)
+#define CAU_DIRECT_CAU_DIRECT1(x)                (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT1_SHIFT)) & CAU_DIRECT_CAU_DIRECT1_MASK)
+#define CAU_DIRECT_CAU_DIRECT2_MASK              (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT2_SHIFT             (0U)
+#define CAU_DIRECT_CAU_DIRECT2(x)                (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT2_SHIFT)) & CAU_DIRECT_CAU_DIRECT2_MASK)
+#define CAU_DIRECT_CAU_DIRECT3_MASK              (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT3_SHIFT             (0U)
+#define CAU_DIRECT_CAU_DIRECT3(x)                (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT3_SHIFT)) & CAU_DIRECT_CAU_DIRECT3_MASK)
+#define CAU_DIRECT_CAU_DIRECT4_MASK              (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT4_SHIFT             (0U)
+#define CAU_DIRECT_CAU_DIRECT4(x)                (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT4_SHIFT)) & CAU_DIRECT_CAU_DIRECT4_MASK)
+#define CAU_DIRECT_CAU_DIRECT5_MASK              (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT5_SHIFT             (0U)
+#define CAU_DIRECT_CAU_DIRECT5(x)                (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT5_SHIFT)) & CAU_DIRECT_CAU_DIRECT5_MASK)
+#define CAU_DIRECT_CAU_DIRECT6_MASK              (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT6_SHIFT             (0U)
+#define CAU_DIRECT_CAU_DIRECT6(x)                (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT6_SHIFT)) & CAU_DIRECT_CAU_DIRECT6_MASK)
+#define CAU_DIRECT_CAU_DIRECT7_MASK              (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT7_SHIFT             (0U)
+#define CAU_DIRECT_CAU_DIRECT7(x)                (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT7_SHIFT)) & CAU_DIRECT_CAU_DIRECT7_MASK)
+#define CAU_DIRECT_CAU_DIRECT8_MASK              (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT8_SHIFT             (0U)
+#define CAU_DIRECT_CAU_DIRECT8(x)                (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT8_SHIFT)) & CAU_DIRECT_CAU_DIRECT8_MASK)
+#define CAU_DIRECT_CAU_DIRECT9_MASK              (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT9_SHIFT             (0U)
+#define CAU_DIRECT_CAU_DIRECT9(x)                (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT9_SHIFT)) & CAU_DIRECT_CAU_DIRECT9_MASK)
+#define CAU_DIRECT_CAU_DIRECT10_MASK             (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT10_SHIFT            (0U)
+#define CAU_DIRECT_CAU_DIRECT10(x)               (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT10_SHIFT)) & CAU_DIRECT_CAU_DIRECT10_MASK)
+#define CAU_DIRECT_CAU_DIRECT11_MASK             (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT11_SHIFT            (0U)
+#define CAU_DIRECT_CAU_DIRECT11(x)               (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT11_SHIFT)) & CAU_DIRECT_CAU_DIRECT11_MASK)
+#define CAU_DIRECT_CAU_DIRECT12_MASK             (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT12_SHIFT            (0U)
+#define CAU_DIRECT_CAU_DIRECT12(x)               (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT12_SHIFT)) & CAU_DIRECT_CAU_DIRECT12_MASK)
+#define CAU_DIRECT_CAU_DIRECT13_MASK             (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT13_SHIFT            (0U)
+#define CAU_DIRECT_CAU_DIRECT13(x)               (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT13_SHIFT)) & CAU_DIRECT_CAU_DIRECT13_MASK)
+#define CAU_DIRECT_CAU_DIRECT14_MASK             (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT14_SHIFT            (0U)
+#define CAU_DIRECT_CAU_DIRECT14(x)               (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT14_SHIFT)) & CAU_DIRECT_CAU_DIRECT14_MASK)
+#define CAU_DIRECT_CAU_DIRECT15_MASK             (0xFFFFFFFFU)
+#define CAU_DIRECT_CAU_DIRECT15_SHIFT            (0U)
+#define CAU_DIRECT_CAU_DIRECT15(x)               (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK)
+
+/* The count of CAU_DIRECT */
+#define CAU_DIRECT_COUNT                         (16U)
+
+/*! @name LDR_CASR - Status register - Load Register command */
+#define CAU_LDR_CASR_IC_MASK                     (0x1U)
+#define CAU_LDR_CASR_IC_SHIFT                    (0U)
+#define CAU_LDR_CASR_IC(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK)
+#define CAU_LDR_CASR_DPE_MASK                    (0x2U)
+#define CAU_LDR_CASR_DPE_SHIFT                   (1U)
+#define CAU_LDR_CASR_DPE(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK)
+#define CAU_LDR_CASR_VER_MASK                    (0xF0000000U)
+#define CAU_LDR_CASR_VER_SHIFT                   (28U)
+#define CAU_LDR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK)
+
+/*! @name LDR_CAA - Accumulator register - Load Register command */
+#define CAU_LDR_CAA_ACC_MASK                     (0xFFFFFFFFU)
+#define CAU_LDR_CAA_ACC_SHIFT                    (0U)
+#define CAU_LDR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK)
+
+/*! @name LDR_CA - General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command */
+#define CAU_LDR_CA_CA0_MASK                      (0xFFFFFFFFU)
+#define CAU_LDR_CA_CA0_SHIFT                     (0U)
+#define CAU_LDR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK)
+#define CAU_LDR_CA_CA1_MASK                      (0xFFFFFFFFU)
+#define CAU_LDR_CA_CA1_SHIFT                     (0U)
+#define CAU_LDR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA1_SHIFT)) & CAU_LDR_CA_CA1_MASK)
+#define CAU_LDR_CA_CA2_MASK                      (0xFFFFFFFFU)
+#define CAU_LDR_CA_CA2_SHIFT                     (0U)
+#define CAU_LDR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA2_SHIFT)) & CAU_LDR_CA_CA2_MASK)
+#define CAU_LDR_CA_CA3_MASK                      (0xFFFFFFFFU)
+#define CAU_LDR_CA_CA3_SHIFT                     (0U)
+#define CAU_LDR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA3_SHIFT)) & CAU_LDR_CA_CA3_MASK)
+#define CAU_LDR_CA_CA4_MASK                      (0xFFFFFFFFU)
+#define CAU_LDR_CA_CA4_SHIFT                     (0U)
+#define CAU_LDR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA4_SHIFT)) & CAU_LDR_CA_CA4_MASK)
+#define CAU_LDR_CA_CA5_MASK                      (0xFFFFFFFFU)
+#define CAU_LDR_CA_CA5_SHIFT                     (0U)
+#define CAU_LDR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA5_SHIFT)) & CAU_LDR_CA_CA5_MASK)
+#define CAU_LDR_CA_CA6_MASK                      (0xFFFFFFFFU)
+#define CAU_LDR_CA_CA6_SHIFT                     (0U)
+#define CAU_LDR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA6_SHIFT)) & CAU_LDR_CA_CA6_MASK)
+#define CAU_LDR_CA_CA7_MASK                      (0xFFFFFFFFU)
+#define CAU_LDR_CA_CA7_SHIFT                     (0U)
+#define CAU_LDR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA7_SHIFT)) & CAU_LDR_CA_CA7_MASK)
+#define CAU_LDR_CA_CA8_MASK                      (0xFFFFFFFFU)
+#define CAU_LDR_CA_CA8_SHIFT                     (0U)
+#define CAU_LDR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK)
+
+/* The count of CAU_LDR_CA */
+#define CAU_LDR_CA_COUNT                         (9U)
+
+/*! @name STR_CASR - Status register - Store Register command */
+#define CAU_STR_CASR_IC_MASK                     (0x1U)
+#define CAU_STR_CASR_IC_SHIFT                    (0U)
+#define CAU_STR_CASR_IC(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK)
+#define CAU_STR_CASR_DPE_MASK                    (0x2U)
+#define CAU_STR_CASR_DPE_SHIFT                   (1U)
+#define CAU_STR_CASR_DPE(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK)
+#define CAU_STR_CASR_VER_MASK                    (0xF0000000U)
+#define CAU_STR_CASR_VER_SHIFT                   (28U)
+#define CAU_STR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK)
+
+/*! @name STR_CAA - Accumulator register - Store Register command */
+#define CAU_STR_CAA_ACC_MASK                     (0xFFFFFFFFU)
+#define CAU_STR_CAA_ACC_SHIFT                    (0U)
+#define CAU_STR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK)
+
+/*! @name STR_CA - General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command */
+#define CAU_STR_CA_CA0_MASK                      (0xFFFFFFFFU)
+#define CAU_STR_CA_CA0_SHIFT                     (0U)
+#define CAU_STR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK)
+#define CAU_STR_CA_CA1_MASK                      (0xFFFFFFFFU)
+#define CAU_STR_CA_CA1_SHIFT                     (0U)
+#define CAU_STR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA1_SHIFT)) & CAU_STR_CA_CA1_MASK)
+#define CAU_STR_CA_CA2_MASK                      (0xFFFFFFFFU)
+#define CAU_STR_CA_CA2_SHIFT                     (0U)
+#define CAU_STR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA2_SHIFT)) & CAU_STR_CA_CA2_MASK)
+#define CAU_STR_CA_CA3_MASK                      (0xFFFFFFFFU)
+#define CAU_STR_CA_CA3_SHIFT                     (0U)
+#define CAU_STR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA3_SHIFT)) & CAU_STR_CA_CA3_MASK)
+#define CAU_STR_CA_CA4_MASK                      (0xFFFFFFFFU)
+#define CAU_STR_CA_CA4_SHIFT                     (0U)
+#define CAU_STR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA4_SHIFT)) & CAU_STR_CA_CA4_MASK)
+#define CAU_STR_CA_CA5_MASK                      (0xFFFFFFFFU)
+#define CAU_STR_CA_CA5_SHIFT                     (0U)
+#define CAU_STR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA5_SHIFT)) & CAU_STR_CA_CA5_MASK)
+#define CAU_STR_CA_CA6_MASK                      (0xFFFFFFFFU)
+#define CAU_STR_CA_CA6_SHIFT                     (0U)
+#define CAU_STR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA6_SHIFT)) & CAU_STR_CA_CA6_MASK)
+#define CAU_STR_CA_CA7_MASK                      (0xFFFFFFFFU)
+#define CAU_STR_CA_CA7_SHIFT                     (0U)
+#define CAU_STR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA7_SHIFT)) & CAU_STR_CA_CA7_MASK)
+#define CAU_STR_CA_CA8_MASK                      (0xFFFFFFFFU)
+#define CAU_STR_CA_CA8_SHIFT                     (0U)
+#define CAU_STR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK)
+
+/* The count of CAU_STR_CA */
+#define CAU_STR_CA_COUNT                         (9U)
+
+/*! @name ADR_CASR - Status register - Add Register command */
+#define CAU_ADR_CASR_IC_MASK                     (0x1U)
+#define CAU_ADR_CASR_IC_SHIFT                    (0U)
+#define CAU_ADR_CASR_IC(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK)
+#define CAU_ADR_CASR_DPE_MASK                    (0x2U)
+#define CAU_ADR_CASR_DPE_SHIFT                   (1U)
+#define CAU_ADR_CASR_DPE(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK)
+#define CAU_ADR_CASR_VER_MASK                    (0xF0000000U)
+#define CAU_ADR_CASR_VER_SHIFT                   (28U)
+#define CAU_ADR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK)
+
+/*! @name ADR_CAA - Accumulator register - Add to register command */
+#define CAU_ADR_CAA_ACC_MASK                     (0xFFFFFFFFU)
+#define CAU_ADR_CAA_ACC_SHIFT                    (0U)
+#define CAU_ADR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK)
+
+/*! @name ADR_CA - General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command */
+#define CAU_ADR_CA_CA0_MASK                      (0xFFFFFFFFU)
+#define CAU_ADR_CA_CA0_SHIFT                     (0U)
+#define CAU_ADR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK)
+#define CAU_ADR_CA_CA1_MASK                      (0xFFFFFFFFU)
+#define CAU_ADR_CA_CA1_SHIFT                     (0U)
+#define CAU_ADR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA1_SHIFT)) & CAU_ADR_CA_CA1_MASK)
+#define CAU_ADR_CA_CA2_MASK                      (0xFFFFFFFFU)
+#define CAU_ADR_CA_CA2_SHIFT                     (0U)
+#define CAU_ADR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA2_SHIFT)) & CAU_ADR_CA_CA2_MASK)
+#define CAU_ADR_CA_CA3_MASK                      (0xFFFFFFFFU)
+#define CAU_ADR_CA_CA3_SHIFT                     (0U)
+#define CAU_ADR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA3_SHIFT)) & CAU_ADR_CA_CA3_MASK)
+#define CAU_ADR_CA_CA4_MASK                      (0xFFFFFFFFU)
+#define CAU_ADR_CA_CA4_SHIFT                     (0U)
+#define CAU_ADR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA4_SHIFT)) & CAU_ADR_CA_CA4_MASK)
+#define CAU_ADR_CA_CA5_MASK                      (0xFFFFFFFFU)
+#define CAU_ADR_CA_CA5_SHIFT                     (0U)
+#define CAU_ADR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA5_SHIFT)) & CAU_ADR_CA_CA5_MASK)
+#define CAU_ADR_CA_CA6_MASK                      (0xFFFFFFFFU)
+#define CAU_ADR_CA_CA6_SHIFT                     (0U)
+#define CAU_ADR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA6_SHIFT)) & CAU_ADR_CA_CA6_MASK)
+#define CAU_ADR_CA_CA7_MASK                      (0xFFFFFFFFU)
+#define CAU_ADR_CA_CA7_SHIFT                     (0U)
+#define CAU_ADR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA7_SHIFT)) & CAU_ADR_CA_CA7_MASK)
+#define CAU_ADR_CA_CA8_MASK                      (0xFFFFFFFFU)
+#define CAU_ADR_CA_CA8_SHIFT                     (0U)
+#define CAU_ADR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK)
+
+/* The count of CAU_ADR_CA */
+#define CAU_ADR_CA_COUNT                         (9U)
+
+/*! @name RADR_CASR - Status register - Reverse and Add to Register command */
+#define CAU_RADR_CASR_IC_MASK                    (0x1U)
+#define CAU_RADR_CASR_IC_SHIFT                   (0U)
+#define CAU_RADR_CASR_IC(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK)
+#define CAU_RADR_CASR_DPE_MASK                   (0x2U)
+#define CAU_RADR_CASR_DPE_SHIFT                  (1U)
+#define CAU_RADR_CASR_DPE(x)                     (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK)
+#define CAU_RADR_CASR_VER_MASK                   (0xF0000000U)
+#define CAU_RADR_CASR_VER_SHIFT                  (28U)
+#define CAU_RADR_CASR_VER(x)                     (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK)
+
+/*! @name RADR_CAA - Accumulator register - Reverse and Add to Register command */
+#define CAU_RADR_CAA_ACC_MASK                    (0xFFFFFFFFU)
+#define CAU_RADR_CAA_ACC_SHIFT                   (0U)
+#define CAU_RADR_CAA_ACC(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK)
+
+/*! @name RADR_CA - General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command */
+#define CAU_RADR_CA_CA0_MASK                     (0xFFFFFFFFU)
+#define CAU_RADR_CA_CA0_SHIFT                    (0U)
+#define CAU_RADR_CA_CA0(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK)
+#define CAU_RADR_CA_CA1_MASK                     (0xFFFFFFFFU)
+#define CAU_RADR_CA_CA1_SHIFT                    (0U)
+#define CAU_RADR_CA_CA1(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA1_SHIFT)) & CAU_RADR_CA_CA1_MASK)
+#define CAU_RADR_CA_CA2_MASK                     (0xFFFFFFFFU)
+#define CAU_RADR_CA_CA2_SHIFT                    (0U)
+#define CAU_RADR_CA_CA2(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA2_SHIFT)) & CAU_RADR_CA_CA2_MASK)
+#define CAU_RADR_CA_CA3_MASK                     (0xFFFFFFFFU)
+#define CAU_RADR_CA_CA3_SHIFT                    (0U)
+#define CAU_RADR_CA_CA3(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA3_SHIFT)) & CAU_RADR_CA_CA3_MASK)
+#define CAU_RADR_CA_CA4_MASK                     (0xFFFFFFFFU)
+#define CAU_RADR_CA_CA4_SHIFT                    (0U)
+#define CAU_RADR_CA_CA4(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA4_SHIFT)) & CAU_RADR_CA_CA4_MASK)
+#define CAU_RADR_CA_CA5_MASK                     (0xFFFFFFFFU)
+#define CAU_RADR_CA_CA5_SHIFT                    (0U)
+#define CAU_RADR_CA_CA5(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA5_SHIFT)) & CAU_RADR_CA_CA5_MASK)
+#define CAU_RADR_CA_CA6_MASK                     (0xFFFFFFFFU)
+#define CAU_RADR_CA_CA6_SHIFT                    (0U)
+#define CAU_RADR_CA_CA6(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA6_SHIFT)) & CAU_RADR_CA_CA6_MASK)
+#define CAU_RADR_CA_CA7_MASK                     (0xFFFFFFFFU)
+#define CAU_RADR_CA_CA7_SHIFT                    (0U)
+#define CAU_RADR_CA_CA7(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA7_SHIFT)) & CAU_RADR_CA_CA7_MASK)
+#define CAU_RADR_CA_CA8_MASK                     (0xFFFFFFFFU)
+#define CAU_RADR_CA_CA8_SHIFT                    (0U)
+#define CAU_RADR_CA_CA8(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK)
+
+/* The count of CAU_RADR_CA */
+#define CAU_RADR_CA_COUNT                        (9U)
+
+/*! @name XOR_CASR - Status register - Exclusive Or command */
+#define CAU_XOR_CASR_IC_MASK                     (0x1U)
+#define CAU_XOR_CASR_IC_SHIFT                    (0U)
+#define CAU_XOR_CASR_IC(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK)
+#define CAU_XOR_CASR_DPE_MASK                    (0x2U)
+#define CAU_XOR_CASR_DPE_SHIFT                   (1U)
+#define CAU_XOR_CASR_DPE(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK)
+#define CAU_XOR_CASR_VER_MASK                    (0xF0000000U)
+#define CAU_XOR_CASR_VER_SHIFT                   (28U)
+#define CAU_XOR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK)
+
+/*! @name XOR_CAA - Accumulator register - Exclusive Or command */
+#define CAU_XOR_CAA_ACC_MASK                     (0xFFFFFFFFU)
+#define CAU_XOR_CAA_ACC_SHIFT                    (0U)
+#define CAU_XOR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK)
+
+/*! @name XOR_CA - General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command */
+#define CAU_XOR_CA_CA0_MASK                      (0xFFFFFFFFU)
+#define CAU_XOR_CA_CA0_SHIFT                     (0U)
+#define CAU_XOR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK)
+#define CAU_XOR_CA_CA1_MASK                      (0xFFFFFFFFU)
+#define CAU_XOR_CA_CA1_SHIFT                     (0U)
+#define CAU_XOR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA1_SHIFT)) & CAU_XOR_CA_CA1_MASK)
+#define CAU_XOR_CA_CA2_MASK                      (0xFFFFFFFFU)
+#define CAU_XOR_CA_CA2_SHIFT                     (0U)
+#define CAU_XOR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA2_SHIFT)) & CAU_XOR_CA_CA2_MASK)
+#define CAU_XOR_CA_CA3_MASK                      (0xFFFFFFFFU)
+#define CAU_XOR_CA_CA3_SHIFT                     (0U)
+#define CAU_XOR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA3_SHIFT)) & CAU_XOR_CA_CA3_MASK)
+#define CAU_XOR_CA_CA4_MASK                      (0xFFFFFFFFU)
+#define CAU_XOR_CA_CA4_SHIFT                     (0U)
+#define CAU_XOR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA4_SHIFT)) & CAU_XOR_CA_CA4_MASK)
+#define CAU_XOR_CA_CA5_MASK                      (0xFFFFFFFFU)
+#define CAU_XOR_CA_CA5_SHIFT                     (0U)
+#define CAU_XOR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA5_SHIFT)) & CAU_XOR_CA_CA5_MASK)
+#define CAU_XOR_CA_CA6_MASK                      (0xFFFFFFFFU)
+#define CAU_XOR_CA_CA6_SHIFT                     (0U)
+#define CAU_XOR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA6_SHIFT)) & CAU_XOR_CA_CA6_MASK)
+#define CAU_XOR_CA_CA7_MASK                      (0xFFFFFFFFU)
+#define CAU_XOR_CA_CA7_SHIFT                     (0U)
+#define CAU_XOR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA7_SHIFT)) & CAU_XOR_CA_CA7_MASK)
+#define CAU_XOR_CA_CA8_MASK                      (0xFFFFFFFFU)
+#define CAU_XOR_CA_CA8_SHIFT                     (0U)
+#define CAU_XOR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK)
+
+/* The count of CAU_XOR_CA */
+#define CAU_XOR_CA_COUNT                         (9U)
+
+/*! @name ROTL_CASR - Status register - Rotate Left command */
+#define CAU_ROTL_CASR_IC_MASK                    (0x1U)
+#define CAU_ROTL_CASR_IC_SHIFT                   (0U)
+#define CAU_ROTL_CASR_IC(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK)
+#define CAU_ROTL_CASR_DPE_MASK                   (0x2U)
+#define CAU_ROTL_CASR_DPE_SHIFT                  (1U)
+#define CAU_ROTL_CASR_DPE(x)                     (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK)
+#define CAU_ROTL_CASR_VER_MASK                   (0xF0000000U)
+#define CAU_ROTL_CASR_VER_SHIFT                  (28U)
+#define CAU_ROTL_CASR_VER(x)                     (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK)
+
+/*! @name ROTL_CAA - Accumulator register - Rotate Left command */
+#define CAU_ROTL_CAA_ACC_MASK                    (0xFFFFFFFFU)
+#define CAU_ROTL_CAA_ACC_SHIFT                   (0U)
+#define CAU_ROTL_CAA_ACC(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK)
+
+/*! @name ROTL_CA - General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command */
+#define CAU_ROTL_CA_CA0_MASK                     (0xFFFFFFFFU)
+#define CAU_ROTL_CA_CA0_SHIFT                    (0U)
+#define CAU_ROTL_CA_CA0(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK)
+#define CAU_ROTL_CA_CA1_MASK                     (0xFFFFFFFFU)
+#define CAU_ROTL_CA_CA1_SHIFT                    (0U)
+#define CAU_ROTL_CA_CA1(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA1_SHIFT)) & CAU_ROTL_CA_CA1_MASK)
+#define CAU_ROTL_CA_CA2_MASK                     (0xFFFFFFFFU)
+#define CAU_ROTL_CA_CA2_SHIFT                    (0U)
+#define CAU_ROTL_CA_CA2(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA2_SHIFT)) & CAU_ROTL_CA_CA2_MASK)
+#define CAU_ROTL_CA_CA3_MASK                     (0xFFFFFFFFU)
+#define CAU_ROTL_CA_CA3_SHIFT                    (0U)
+#define CAU_ROTL_CA_CA3(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA3_SHIFT)) & CAU_ROTL_CA_CA3_MASK)
+#define CAU_ROTL_CA_CA4_MASK                     (0xFFFFFFFFU)
+#define CAU_ROTL_CA_CA4_SHIFT                    (0U)
+#define CAU_ROTL_CA_CA4(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA4_SHIFT)) & CAU_ROTL_CA_CA4_MASK)
+#define CAU_ROTL_CA_CA5_MASK                     (0xFFFFFFFFU)
+#define CAU_ROTL_CA_CA5_SHIFT                    (0U)
+#define CAU_ROTL_CA_CA5(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA5_SHIFT)) & CAU_ROTL_CA_CA5_MASK)
+#define CAU_ROTL_CA_CA6_MASK                     (0xFFFFFFFFU)
+#define CAU_ROTL_CA_CA6_SHIFT                    (0U)
+#define CAU_ROTL_CA_CA6(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA6_SHIFT)) & CAU_ROTL_CA_CA6_MASK)
+#define CAU_ROTL_CA_CA7_MASK                     (0xFFFFFFFFU)
+#define CAU_ROTL_CA_CA7_SHIFT                    (0U)
+#define CAU_ROTL_CA_CA7(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA7_SHIFT)) & CAU_ROTL_CA_CA7_MASK)
+#define CAU_ROTL_CA_CA8_MASK                     (0xFFFFFFFFU)
+#define CAU_ROTL_CA_CA8_SHIFT                    (0U)
+#define CAU_ROTL_CA_CA8(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA8_SHIFT)) & CAU_ROTL_CA_CA8_MASK)
+
+/* The count of CAU_ROTL_CA */
+#define CAU_ROTL_CA_COUNT                        (9U)
+
+/*! @name AESC_CASR - Status register - AES Column Operation command */
+#define CAU_AESC_CASR_IC_MASK                    (0x1U)
+#define CAU_AESC_CASR_IC_SHIFT                   (0U)
+#define CAU_AESC_CASR_IC(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK)
+#define CAU_AESC_CASR_DPE_MASK                   (0x2U)
+#define CAU_AESC_CASR_DPE_SHIFT                  (1U)
+#define CAU_AESC_CASR_DPE(x)                     (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK)
+#define CAU_AESC_CASR_VER_MASK                   (0xF0000000U)
+#define CAU_AESC_CASR_VER_SHIFT                  (28U)
+#define CAU_AESC_CASR_VER(x)                     (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK)
+
+/*! @name AESC_CAA - Accumulator register - AES Column Operation command */
+#define CAU_AESC_CAA_ACC_MASK                    (0xFFFFFFFFU)
+#define CAU_AESC_CAA_ACC_SHIFT                   (0U)
+#define CAU_AESC_CAA_ACC(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CAA_ACC_SHIFT)) & CAU_AESC_CAA_ACC_MASK)
+
+/*! @name AESC_CA - General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command */
+#define CAU_AESC_CA_CA0_MASK                     (0xFFFFFFFFU)
+#define CAU_AESC_CA_CA0_SHIFT                    (0U)
+#define CAU_AESC_CA_CA0(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA0_SHIFT)) & CAU_AESC_CA_CA0_MASK)
+#define CAU_AESC_CA_CA1_MASK                     (0xFFFFFFFFU)
+#define CAU_AESC_CA_CA1_SHIFT                    (0U)
+#define CAU_AESC_CA_CA1(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA1_SHIFT)) & CAU_AESC_CA_CA1_MASK)
+#define CAU_AESC_CA_CA2_MASK                     (0xFFFFFFFFU)
+#define CAU_AESC_CA_CA2_SHIFT                    (0U)
+#define CAU_AESC_CA_CA2(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA2_SHIFT)) & CAU_AESC_CA_CA2_MASK)
+#define CAU_AESC_CA_CA3_MASK                     (0xFFFFFFFFU)
+#define CAU_AESC_CA_CA3_SHIFT                    (0U)
+#define CAU_AESC_CA_CA3(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA3_SHIFT)) & CAU_AESC_CA_CA3_MASK)
+#define CAU_AESC_CA_CA4_MASK                     (0xFFFFFFFFU)
+#define CAU_AESC_CA_CA4_SHIFT                    (0U)
+#define CAU_AESC_CA_CA4(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA4_SHIFT)) & CAU_AESC_CA_CA4_MASK)
+#define CAU_AESC_CA_CA5_MASK                     (0xFFFFFFFFU)
+#define CAU_AESC_CA_CA5_SHIFT                    (0U)
+#define CAU_AESC_CA_CA5(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA5_SHIFT)) & CAU_AESC_CA_CA5_MASK)
+#define CAU_AESC_CA_CA6_MASK                     (0xFFFFFFFFU)
+#define CAU_AESC_CA_CA6_SHIFT                    (0U)
+#define CAU_AESC_CA_CA6(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA6_SHIFT)) & CAU_AESC_CA_CA6_MASK)
+#define CAU_AESC_CA_CA7_MASK                     (0xFFFFFFFFU)
+#define CAU_AESC_CA_CA7_SHIFT                    (0U)
+#define CAU_AESC_CA_CA7(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA7_SHIFT)) & CAU_AESC_CA_CA7_MASK)
+#define CAU_AESC_CA_CA8_MASK                     (0xFFFFFFFFU)
+#define CAU_AESC_CA_CA8_SHIFT                    (0U)
+#define CAU_AESC_CA_CA8(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA8_SHIFT)) & CAU_AESC_CA_CA8_MASK)
+
+/* The count of CAU_AESC_CA */
+#define CAU_AESC_CA_COUNT                        (9U)
+
+/*! @name AESIC_CASR - Status register - AES Inverse Column Operation command */
+#define CAU_AESIC_CASR_IC_MASK                   (0x1U)
+#define CAU_AESIC_CASR_IC_SHIFT                  (0U)
+#define CAU_AESIC_CASR_IC(x)                     (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK)
+#define CAU_AESIC_CASR_DPE_MASK                  (0x2U)
+#define CAU_AESIC_CASR_DPE_SHIFT                 (1U)
+#define CAU_AESIC_CASR_DPE(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK)
+#define CAU_AESIC_CASR_VER_MASK                  (0xF0000000U)
+#define CAU_AESIC_CASR_VER_SHIFT                 (28U)
+#define CAU_AESIC_CASR_VER(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK)
+
+/*! @name AESIC_CAA - Accumulator register - AES Inverse Column Operation command */
+#define CAU_AESIC_CAA_ACC_MASK                   (0xFFFFFFFFU)
+#define CAU_AESIC_CAA_ACC_SHIFT                  (0U)
+#define CAU_AESIC_CAA_ACC(x)                     (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CAA_ACC_SHIFT)) & CAU_AESIC_CAA_ACC_MASK)
+
+/*! @name AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command */
+#define CAU_AESIC_CA_CA0_MASK                    (0xFFFFFFFFU)
+#define CAU_AESIC_CA_CA0_SHIFT                   (0U)
+#define CAU_AESIC_CA_CA0(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA0_SHIFT)) & CAU_AESIC_CA_CA0_MASK)
+#define CAU_AESIC_CA_CA1_MASK                    (0xFFFFFFFFU)
+#define CAU_AESIC_CA_CA1_SHIFT                   (0U)
+#define CAU_AESIC_CA_CA1(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA1_SHIFT)) & CAU_AESIC_CA_CA1_MASK)
+#define CAU_AESIC_CA_CA2_MASK                    (0xFFFFFFFFU)
+#define CAU_AESIC_CA_CA2_SHIFT                   (0U)
+#define CAU_AESIC_CA_CA2(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA2_SHIFT)) & CAU_AESIC_CA_CA2_MASK)
+#define CAU_AESIC_CA_CA3_MASK                    (0xFFFFFFFFU)
+#define CAU_AESIC_CA_CA3_SHIFT                   (0U)
+#define CAU_AESIC_CA_CA3(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA3_SHIFT)) & CAU_AESIC_CA_CA3_MASK)
+#define CAU_AESIC_CA_CA4_MASK                    (0xFFFFFFFFU)
+#define CAU_AESIC_CA_CA4_SHIFT                   (0U)
+#define CAU_AESIC_CA_CA4(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA4_SHIFT)) & CAU_AESIC_CA_CA4_MASK)
+#define CAU_AESIC_CA_CA5_MASK                    (0xFFFFFFFFU)
+#define CAU_AESIC_CA_CA5_SHIFT                   (0U)
+#define CAU_AESIC_CA_CA5(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA5_SHIFT)) & CAU_AESIC_CA_CA5_MASK)
+#define CAU_AESIC_CA_CA6_MASK                    (0xFFFFFFFFU)
+#define CAU_AESIC_CA_CA6_SHIFT                   (0U)
+#define CAU_AESIC_CA_CA6(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA6_SHIFT)) & CAU_AESIC_CA_CA6_MASK)
+#define CAU_AESIC_CA_CA7_MASK                    (0xFFFFFFFFU)
+#define CAU_AESIC_CA_CA7_SHIFT                   (0U)
+#define CAU_AESIC_CA_CA7(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA7_SHIFT)) & CAU_AESIC_CA_CA7_MASK)
+#define CAU_AESIC_CA_CA8_MASK                    (0xFFFFFFFFU)
+#define CAU_AESIC_CA_CA8_SHIFT                   (0U)
+#define CAU_AESIC_CA_CA8(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA8_SHIFT)) & CAU_AESIC_CA_CA8_MASK)
+
+/* The count of CAU_AESIC_CA */
+#define CAU_AESIC_CA_COUNT                       (9U)
+
+
+/*!
+ * @}
+ */ /* end of group CAU_Register_Masks */
+
+
+/* CAU - Peripheral instance base addresses */
+/** Peripheral CAU base address */
+#define CAU_BASE                                 (0xE0081000u)
+/** Peripheral CAU base pointer */
+#define CAU                                      ((CAU_Type *)CAU_BASE)
+/** Array initializer of CAU peripheral base addresses */
+#define CAU_BASE_ADDRS                           { CAU_BASE }
+/** Array initializer of CAU peripheral base pointers */
+#define CAU_BASE_PTRS                            { CAU }
+
+/*!
+ * @}
+ */ /* end of group CAU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMP Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
+ * @{
+ */
+
+/** CMP - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CR0;                                /**< CMP Control Register 0, offset: 0x0 */
+  __IO uint8_t CR1;                                /**< CMP Control Register 1, offset: 0x1 */
+  __IO uint8_t FPR;                                /**< CMP Filter Period Register, offset: 0x2 */
+  __IO uint8_t SCR;                                /**< CMP Status and Control Register, offset: 0x3 */
+  __IO uint8_t DACCR;                              /**< DAC Control Register, offset: 0x4 */
+  __IO uint8_t MUXCR;                              /**< MUX Control Register, offset: 0x5 */
+} CMP_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CMP Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMP_Register_Masks CMP Register Masks
+ * @{
+ */
+
+/*! @name CR0 - CMP Control Register 0 */
+#define CMP_CR0_HYSTCTR_MASK                     (0x3U)
+#define CMP_CR0_HYSTCTR_SHIFT                    (0U)
+#define CMP_CR0_HYSTCTR(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_FILTER_CNT_MASK                  (0x70U)
+#define CMP_CR0_FILTER_CNT_SHIFT                 (4U)
+#define CMP_CR0_FILTER_CNT(x)                    (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
+
+/*! @name CR1 - CMP Control Register 1 */
+#define CMP_CR1_EN_MASK                          (0x1U)
+#define CMP_CR1_EN_SHIFT                         (0U)
+#define CMP_CR1_EN(x)                            (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
+#define CMP_CR1_OPE_MASK                         (0x2U)
+#define CMP_CR1_OPE_SHIFT                        (1U)
+#define CMP_CR1_OPE(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
+#define CMP_CR1_COS_MASK                         (0x4U)
+#define CMP_CR1_COS_SHIFT                        (2U)
+#define CMP_CR1_COS(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
+#define CMP_CR1_INV_MASK                         (0x8U)
+#define CMP_CR1_INV_SHIFT                        (3U)
+#define CMP_CR1_INV(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
+#define CMP_CR1_PMODE_MASK                       (0x10U)
+#define CMP_CR1_PMODE_SHIFT                      (4U)
+#define CMP_CR1_PMODE(x)                         (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
+#define CMP_CR1_TRIGM_MASK                       (0x20U)
+#define CMP_CR1_TRIGM_SHIFT                      (5U)
+#define CMP_CR1_TRIGM(x)                         (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
+#define CMP_CR1_WE_MASK                          (0x40U)
+#define CMP_CR1_WE_SHIFT                         (6U)
+#define CMP_CR1_WE(x)                            (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
+#define CMP_CR1_SE_MASK                          (0x80U)
+#define CMP_CR1_SE_SHIFT                         (7U)
+#define CMP_CR1_SE(x)                            (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
+
+/*! @name FPR - CMP Filter Period Register */
+#define CMP_FPR_FILT_PER_MASK                    (0xFFU)
+#define CMP_FPR_FILT_PER_SHIFT                   (0U)
+#define CMP_FPR_FILT_PER(x)                      (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
+
+/*! @name SCR - CMP Status and Control Register */
+#define CMP_SCR_COUT_MASK                        (0x1U)
+#define CMP_SCR_COUT_SHIFT                       (0U)
+#define CMP_SCR_COUT(x)                          (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
+#define CMP_SCR_CFF_MASK                         (0x2U)
+#define CMP_SCR_CFF_SHIFT                        (1U)
+#define CMP_SCR_CFF(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
+#define CMP_SCR_CFR_MASK                         (0x4U)
+#define CMP_SCR_CFR_SHIFT                        (2U)
+#define CMP_SCR_CFR(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
+#define CMP_SCR_IEF_MASK                         (0x8U)
+#define CMP_SCR_IEF_SHIFT                        (3U)
+#define CMP_SCR_IEF(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
+#define CMP_SCR_IER_MASK                         (0x10U)
+#define CMP_SCR_IER_SHIFT                        (4U)
+#define CMP_SCR_IER(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
+#define CMP_SCR_DMAEN_MASK                       (0x40U)
+#define CMP_SCR_DMAEN_SHIFT                      (6U)
+#define CMP_SCR_DMAEN(x)                         (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
+
+/*! @name DACCR - DAC Control Register */
+#define CMP_DACCR_VOSEL_MASK                     (0x3FU)
+#define CMP_DACCR_VOSEL_SHIFT                    (0U)
+#define CMP_DACCR_VOSEL(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VRSEL_MASK                     (0x40U)
+#define CMP_DACCR_VRSEL_SHIFT                    (6U)
+#define CMP_DACCR_VRSEL(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
+#define CMP_DACCR_DACEN_MASK                     (0x80U)
+#define CMP_DACCR_DACEN_SHIFT                    (7U)
+#define CMP_DACCR_DACEN(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
+
+/*! @name MUXCR - MUX Control Register */
+#define CMP_MUXCR_MSEL_MASK                      (0x7U)
+#define CMP_MUXCR_MSEL_SHIFT                     (0U)
+#define CMP_MUXCR_MSEL(x)                        (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_PSEL_MASK                      (0x38U)
+#define CMP_MUXCR_PSEL_SHIFT                     (3U)
+#define CMP_MUXCR_PSEL(x)                        (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
+#define CMP_MUXCR_PSTM_MASK                      (0x80U)
+#define CMP_MUXCR_PSTM_SHIFT                     (7U)
+#define CMP_MUXCR_PSTM(x)                        (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group CMP_Register_Masks */
+
+
+/* CMP - Peripheral instance base addresses */
+/** Peripheral CMP0 base address */
+#define CMP0_BASE                                (0x40073000u)
+/** Peripheral CMP0 base pointer */
+#define CMP0                                     ((CMP_Type *)CMP0_BASE)
+/** Peripheral CMP1 base address */
+#define CMP1_BASE                                (0x40073008u)
+/** Peripheral CMP1 base pointer */
+#define CMP1                                     ((CMP_Type *)CMP1_BASE)
+/** Peripheral CMP2 base address */
+#define CMP2_BASE                                (0x40073010u)
+/** Peripheral CMP2 base pointer */
+#define CMP2                                     ((CMP_Type *)CMP2_BASE)
+/** Peripheral CMP3 base address */
+#define CMP3_BASE                                (0x40073018u)
+/** Peripheral CMP3 base pointer */
+#define CMP3                                     ((CMP_Type *)CMP3_BASE)
+/** Array initializer of CMP peripheral base addresses */
+#define CMP_BASE_ADDRS                           { CMP0_BASE, CMP1_BASE, CMP2_BASE, CMP3_BASE }
+/** Array initializer of CMP peripheral base pointers */
+#define CMP_BASE_PTRS                            { CMP0, CMP1, CMP2, CMP3 }
+/** Interrupt vectors for the CMP peripheral type */
+#define CMP_IRQS                                 { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn, CMP3_IRQn }
+
+/*!
+ * @}
+ */ /* end of group CMP_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CMT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
+ * @{
+ */
+
+/** CMT - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CGH1;                               /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
+  __IO uint8_t CGL1;                               /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
+  __IO uint8_t CGH2;                               /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
+  __IO uint8_t CGL2;                               /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
+  __IO uint8_t OC;                                 /**< CMT Output Control Register, offset: 0x4 */
+  __IO uint8_t MSC;                                /**< CMT Modulator Status and Control Register, offset: 0x5 */
+  __IO uint8_t CMD1;                               /**< CMT Modulator Data Register Mark High, offset: 0x6 */
+  __IO uint8_t CMD2;                               /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
+  __IO uint8_t CMD3;                               /**< CMT Modulator Data Register Space High, offset: 0x8 */
+  __IO uint8_t CMD4;                               /**< CMT Modulator Data Register Space Low, offset: 0x9 */
+  __IO uint8_t PPS;                                /**< CMT Primary Prescaler Register, offset: 0xA */
+  __IO uint8_t DMA;                                /**< CMT Direct Memory Access Register, offset: 0xB */
+} CMT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CMT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CMT_Register_Masks CMT Register Masks
+ * @{
+ */
+
+/*! @name CGH1 - CMT Carrier Generator High Data Register 1 */
+#define CMT_CGH1_PH_MASK                         (0xFFU)
+#define CMT_CGH1_PH_SHIFT                        (0U)
+#define CMT_CGH1_PH(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK)
+
+/*! @name CGL1 - CMT Carrier Generator Low Data Register 1 */
+#define CMT_CGL1_PL_MASK                         (0xFFU)
+#define CMT_CGL1_PL_SHIFT                        (0U)
+#define CMT_CGL1_PL(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK)
+
+/*! @name CGH2 - CMT Carrier Generator High Data Register 2 */
+#define CMT_CGH2_SH_MASK                         (0xFFU)
+#define CMT_CGH2_SH_SHIFT                        (0U)
+#define CMT_CGH2_SH(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK)
+
+/*! @name CGL2 - CMT Carrier Generator Low Data Register 2 */
+#define CMT_CGL2_SL_MASK                         (0xFFU)
+#define CMT_CGL2_SL_SHIFT                        (0U)
+#define CMT_CGL2_SL(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK)
+
+/*! @name OC - CMT Output Control Register */
+#define CMT_OC_IROPEN_MASK                       (0x20U)
+#define CMT_OC_IROPEN_SHIFT                      (5U)
+#define CMT_OC_IROPEN(x)                         (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK)
+#define CMT_OC_CMTPOL_MASK                       (0x40U)
+#define CMT_OC_CMTPOL_SHIFT                      (6U)
+#define CMT_OC_CMTPOL(x)                         (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK)
+#define CMT_OC_IROL_MASK                         (0x80U)
+#define CMT_OC_IROL_SHIFT                        (7U)
+#define CMT_OC_IROL(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK)
+
+/*! @name MSC - CMT Modulator Status and Control Register */
+#define CMT_MSC_MCGEN_MASK                       (0x1U)
+#define CMT_MSC_MCGEN_SHIFT                      (0U)
+#define CMT_MSC_MCGEN(x)                         (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK)
+#define CMT_MSC_EOCIE_MASK                       (0x2U)
+#define CMT_MSC_EOCIE_SHIFT                      (1U)
+#define CMT_MSC_EOCIE(x)                         (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK)
+#define CMT_MSC_FSK_MASK                         (0x4U)
+#define CMT_MSC_FSK_SHIFT                        (2U)
+#define CMT_MSC_FSK(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK)
+#define CMT_MSC_BASE_MASK                        (0x8U)
+#define CMT_MSC_BASE_SHIFT                       (3U)
+#define CMT_MSC_BASE(x)                          (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK)
+#define CMT_MSC_EXSPC_MASK                       (0x10U)
+#define CMT_MSC_EXSPC_SHIFT                      (4U)
+#define CMT_MSC_EXSPC(x)                         (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK)
+#define CMT_MSC_CMTDIV_MASK                      (0x60U)
+#define CMT_MSC_CMTDIV_SHIFT                     (5U)
+#define CMT_MSC_CMTDIV(x)                        (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK)
+#define CMT_MSC_EOCF_MASK                        (0x80U)
+#define CMT_MSC_EOCF_SHIFT                       (7U)
+#define CMT_MSC_EOCF(x)                          (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK)
+
+/*! @name CMD1 - CMT Modulator Data Register Mark High */
+#define CMT_CMD1_MB_MASK                         (0xFFU)
+#define CMT_CMD1_MB_SHIFT                        (0U)
+#define CMT_CMD1_MB(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK)
+
+/*! @name CMD2 - CMT Modulator Data Register Mark Low */
+#define CMT_CMD2_MB_MASK                         (0xFFU)
+#define CMT_CMD2_MB_SHIFT                        (0U)
+#define CMT_CMD2_MB(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK)
+
+/*! @name CMD3 - CMT Modulator Data Register Space High */
+#define CMT_CMD3_SB_MASK                         (0xFFU)
+#define CMT_CMD3_SB_SHIFT                        (0U)
+#define CMT_CMD3_SB(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK)
+
+/*! @name CMD4 - CMT Modulator Data Register Space Low */
+#define CMT_CMD4_SB_MASK                         (0xFFU)
+#define CMT_CMD4_SB_SHIFT                        (0U)
+#define CMT_CMD4_SB(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK)
+
+/*! @name PPS - CMT Primary Prescaler Register */
+#define CMT_PPS_PPSDIV_MASK                      (0xFU)
+#define CMT_PPS_PPSDIV_SHIFT                     (0U)
+#define CMT_PPS_PPSDIV(x)                        (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK)
+
+/*! @name DMA - CMT Direct Memory Access Register */
+#define CMT_DMA_DMA_MASK                         (0x1U)
+#define CMT_DMA_DMA_SHIFT                        (0U)
+#define CMT_DMA_DMA(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group CMT_Register_Masks */
+
+
+/* CMT - Peripheral instance base addresses */
+/** Peripheral CMT base address */
+#define CMT_BASE                                 (0x40062000u)
+/** Peripheral CMT base pointer */
+#define CMT                                      ((CMT_Type *)CMT_BASE)
+/** Array initializer of CMT peripheral base addresses */
+#define CMT_BASE_ADDRS                           { CMT_BASE }
+/** Array initializer of CMT peripheral base pointers */
+#define CMT_BASE_PTRS                            { CMT }
+/** Interrupt vectors for the CMT peripheral type */
+#define CMT_IRQS                                 { CMT_IRQn }
+
+/*!
+ * @}
+ */ /* end of group CMT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- CRC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+  union {                                          /* offset: 0x0 */
+    struct {                                         /* offset: 0x0 */
+      __IO uint16_t DATAL;                             /**< CRC_DATAL register., offset: 0x0 */
+      __IO uint16_t DATAH;                             /**< CRC_DATAH register., offset: 0x2 */
+    } ACCESS16BIT;
+    __IO uint32_t DATA;                              /**< CRC Data register, offset: 0x0 */
+    struct {                                         /* offset: 0x0 */
+      __IO uint8_t DATALL;                             /**< CRC_DATALL register., offset: 0x0 */
+      __IO uint8_t DATALU;                             /**< CRC_DATALU register., offset: 0x1 */
+      __IO uint8_t DATAHL;                             /**< CRC_DATAHL register., offset: 0x2 */
+      __IO uint8_t DATAHU;                             /**< CRC_DATAHU register., offset: 0x3 */
+    } ACCESS8BIT;
+  };
+  union {                                          /* offset: 0x4 */
+    struct {                                         /* offset: 0x4 */
+      __IO uint16_t GPOLYL;                            /**< CRC_GPOLYL register., offset: 0x4 */
+      __IO uint16_t GPOLYH;                            /**< CRC_GPOLYH register., offset: 0x6 */
+    } GPOLY_ACCESS16BIT;
+    __IO uint32_t GPOLY;                             /**< CRC Polynomial register, offset: 0x4 */
+    struct {                                         /* offset: 0x4 */
+      __IO uint8_t GPOLYLL;                            /**< CRC_GPOLYLL register., offset: 0x4 */
+      __IO uint8_t GPOLYLU;                            /**< CRC_GPOLYLU register., offset: 0x5 */
+      __IO uint8_t GPOLYHL;                            /**< CRC_GPOLYHL register., offset: 0x6 */
+      __IO uint8_t GPOLYHU;                            /**< CRC_GPOLYHU register., offset: 0x7 */
+    } GPOLY_ACCESS8BIT;
+  };
+  union {                                          /* offset: 0x8 */
+    __IO uint32_t CTRL;                              /**< CRC Control register, offset: 0x8 */
+    struct {                                         /* offset: 0x8 */
+           uint8_t RESERVED_0[3];
+      __IO uint8_t CTRLHU;                             /**< CRC_CTRLHU register., offset: 0xB */
+    } CTRL_ACCESS8BIT;
+  };
+} CRC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- CRC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/*! @name DATAL - CRC_DATAL register. */
+#define CRC_DATAL_DATAL_MASK                     (0xFFFFU)
+#define CRC_DATAL_DATAL_SHIFT                    (0U)
+#define CRC_DATAL_DATAL(x)                       (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
+
+/*! @name DATAH - CRC_DATAH register. */
+#define CRC_DATAH_DATAH_MASK                     (0xFFFFU)
+#define CRC_DATAH_DATAH_SHIFT                    (0U)
+#define CRC_DATAH_DATAH(x)                       (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
+
+/*! @name DATA - CRC Data register */
+#define CRC_DATA_LL_MASK                         (0xFFU)
+#define CRC_DATA_LL_SHIFT                        (0U)
+#define CRC_DATA_LL(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
+#define CRC_DATA_LU_MASK                         (0xFF00U)
+#define CRC_DATA_LU_SHIFT                        (8U)
+#define CRC_DATA_LU(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
+#define CRC_DATA_HL_MASK                         (0xFF0000U)
+#define CRC_DATA_HL_SHIFT                        (16U)
+#define CRC_DATA_HL(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
+#define CRC_DATA_HU_MASK                         (0xFF000000U)
+#define CRC_DATA_HU_SHIFT                        (24U)
+#define CRC_DATA_HU(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
+
+/*! @name DATALL - CRC_DATALL register. */
+#define CRC_DATALL_DATALL_MASK                   (0xFFU)
+#define CRC_DATALL_DATALL_SHIFT                  (0U)
+#define CRC_DATALL_DATALL(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
+
+/*! @name DATALU - CRC_DATALU register. */
+#define CRC_DATALU_DATALU_MASK                   (0xFFU)
+#define CRC_DATALU_DATALU_SHIFT                  (0U)
+#define CRC_DATALU_DATALU(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
+
+/*! @name DATAHL - CRC_DATAHL register. */
+#define CRC_DATAHL_DATAHL_MASK                   (0xFFU)
+#define CRC_DATAHL_DATAHL_SHIFT                  (0U)
+#define CRC_DATAHL_DATAHL(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
+
+/*! @name DATAHU - CRC_DATAHU register. */
+#define CRC_DATAHU_DATAHU_MASK                   (0xFFU)
+#define CRC_DATAHU_DATAHU_SHIFT                  (0U)
+#define CRC_DATAHU_DATAHU(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
+
+/*! @name GPOLYL - CRC_GPOLYL register. */
+#define CRC_GPOLYL_GPOLYL_MASK                   (0xFFFFU)
+#define CRC_GPOLYL_GPOLYL_SHIFT                  (0U)
+#define CRC_GPOLYL_GPOLYL(x)                     (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
+
+/*! @name GPOLYH - CRC_GPOLYH register. */
+#define CRC_GPOLYH_GPOLYH_MASK                   (0xFFFFU)
+#define CRC_GPOLYH_GPOLYH_SHIFT                  (0U)
+#define CRC_GPOLYH_GPOLYH(x)                     (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
+
+/*! @name GPOLY - CRC Polynomial register */
+#define CRC_GPOLY_LOW_MASK                       (0xFFFFU)
+#define CRC_GPOLY_LOW_SHIFT                      (0U)
+#define CRC_GPOLY_LOW(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
+#define CRC_GPOLY_HIGH_MASK                      (0xFFFF0000U)
+#define CRC_GPOLY_HIGH_SHIFT                     (16U)
+#define CRC_GPOLY_HIGH(x)                        (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
+
+/*! @name GPOLYLL - CRC_GPOLYLL register. */
+#define CRC_GPOLYLL_GPOLYLL_MASK                 (0xFFU)
+#define CRC_GPOLYLL_GPOLYLL_SHIFT                (0U)
+#define CRC_GPOLYLL_GPOLYLL(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
+
+/*! @name GPOLYLU - CRC_GPOLYLU register. */
+#define CRC_GPOLYLU_GPOLYLU_MASK                 (0xFFU)
+#define CRC_GPOLYLU_GPOLYLU_SHIFT                (0U)
+#define CRC_GPOLYLU_GPOLYLU(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
+
+/*! @name GPOLYHL - CRC_GPOLYHL register. */
+#define CRC_GPOLYHL_GPOLYHL_MASK                 (0xFFU)
+#define CRC_GPOLYHL_GPOLYHL_SHIFT                (0U)
+#define CRC_GPOLYHL_GPOLYHL(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
+
+/*! @name GPOLYHU - CRC_GPOLYHU register. */
+#define CRC_GPOLYHU_GPOLYHU_MASK                 (0xFFU)
+#define CRC_GPOLYHU_GPOLYHU_SHIFT                (0U)
+#define CRC_GPOLYHU_GPOLYHU(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
+
+/*! @name CTRL - CRC Control register */
+#define CRC_CTRL_TCRC_MASK                       (0x1000000U)
+#define CRC_CTRL_TCRC_SHIFT                      (24U)
+#define CRC_CTRL_TCRC(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
+#define CRC_CTRL_WAS_MASK                        (0x2000000U)
+#define CRC_CTRL_WAS_SHIFT                       (25U)
+#define CRC_CTRL_WAS(x)                          (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
+#define CRC_CTRL_FXOR_MASK                       (0x4000000U)
+#define CRC_CTRL_FXOR_SHIFT                      (26U)
+#define CRC_CTRL_FXOR(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
+#define CRC_CTRL_TOTR_MASK                       (0x30000000U)
+#define CRC_CTRL_TOTR_SHIFT                      (28U)
+#define CRC_CTRL_TOTR(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
+#define CRC_CTRL_TOT_MASK                        (0xC0000000U)
+#define CRC_CTRL_TOT_SHIFT                       (30U)
+#define CRC_CTRL_TOT(x)                          (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
+
+/*! @name CTRLHU - CRC_CTRLHU register. */
+#define CRC_CTRLHU_TCRC_MASK                     (0x1U)
+#define CRC_CTRLHU_TCRC_SHIFT                    (0U)
+#define CRC_CTRLHU_TCRC(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
+#define CRC_CTRLHU_WAS_MASK                      (0x2U)
+#define CRC_CTRLHU_WAS_SHIFT                     (1U)
+#define CRC_CTRLHU_WAS(x)                        (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
+#define CRC_CTRLHU_FXOR_MASK                     (0x4U)
+#define CRC_CTRLHU_FXOR_SHIFT                    (2U)
+#define CRC_CTRLHU_FXOR(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
+#define CRC_CTRLHU_TOTR_MASK                     (0x30U)
+#define CRC_CTRLHU_TOTR_SHIFT                    (4U)
+#define CRC_CTRLHU_TOTR(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
+#define CRC_CTRLHU_TOT_MASK                      (0xC0U)
+#define CRC_CTRLHU_TOT_SHIFT                     (6U)
+#define CRC_CTRLHU_TOT(x)                        (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC base address */
+#define CRC_BASE                                 (0x40032000u)
+/** Peripheral CRC base pointer */
+#define CRC0                                     ((CRC_Type *)CRC_BASE)
+/** Array initializer of CRC peripheral base addresses */
+#define CRC_BASE_ADDRS                           { CRC_BASE }
+/** Array initializer of CRC peripheral base pointers */
+#define CRC_BASE_PTRS                            { CRC0 }
+
+/*!
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DAC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
+ * @{
+ */
+
+/** DAC - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0x2 */
+    __IO uint8_t DATL;                               /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
+    __IO uint8_t DATH;                               /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
+  } DAT[16];
+  __IO uint8_t SR;                                 /**< DAC Status Register, offset: 0x20 */
+  __IO uint8_t C0;                                 /**< DAC Control Register, offset: 0x21 */
+  __IO uint8_t C1;                                 /**< DAC Control Register 1, offset: 0x22 */
+  __IO uint8_t C2;                                 /**< DAC Control Register 2, offset: 0x23 */
+} DAC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DAC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DAC_Register_Masks DAC Register Masks
+ * @{
+ */
+
+/*! @name DATL - DAC Data Low Register */
+#define DAC_DATL_DATA0_MASK                      (0xFFU)
+#define DAC_DATL_DATA0_SHIFT                     (0U)
+#define DAC_DATL_DATA0(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
+
+/* The count of DAC_DATL */
+#define DAC_DATL_COUNT                           (16U)
+
+/*! @name DATH - DAC Data High Register */
+#define DAC_DATH_DATA1_MASK                      (0xFU)
+#define DAC_DATH_DATA1_SHIFT                     (0U)
+#define DAC_DATH_DATA1(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
+
+/* The count of DAC_DATH */
+#define DAC_DATH_COUNT                           (16U)
+
+/*! @name SR - DAC Status Register */
+#define DAC_SR_DACBFRPBF_MASK                    (0x1U)
+#define DAC_SR_DACBFRPBF_SHIFT                   (0U)
+#define DAC_SR_DACBFRPBF(x)                      (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
+#define DAC_SR_DACBFRPTF_MASK                    (0x2U)
+#define DAC_SR_DACBFRPTF_SHIFT                   (1U)
+#define DAC_SR_DACBFRPTF(x)                      (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
+#define DAC_SR_DACBFWMF_MASK                     (0x4U)
+#define DAC_SR_DACBFWMF_SHIFT                    (2U)
+#define DAC_SR_DACBFWMF(x)                       (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK)
+
+/*! @name C0 - DAC Control Register */
+#define DAC_C0_DACBBIEN_MASK                     (0x1U)
+#define DAC_C0_DACBBIEN_SHIFT                    (0U)
+#define DAC_C0_DACBBIEN(x)                       (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
+#define DAC_C0_DACBTIEN_MASK                     (0x2U)
+#define DAC_C0_DACBTIEN_SHIFT                    (1U)
+#define DAC_C0_DACBTIEN(x)                       (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
+#define DAC_C0_DACBWIEN_MASK                     (0x4U)
+#define DAC_C0_DACBWIEN_SHIFT                    (2U)
+#define DAC_C0_DACBWIEN(x)                       (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK)
+#define DAC_C0_LPEN_MASK                         (0x8U)
+#define DAC_C0_LPEN_SHIFT                        (3U)
+#define DAC_C0_LPEN(x)                           (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
+#define DAC_C0_DACSWTRG_MASK                     (0x10U)
+#define DAC_C0_DACSWTRG_SHIFT                    (4U)
+#define DAC_C0_DACSWTRG(x)                       (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
+#define DAC_C0_DACTRGSEL_MASK                    (0x20U)
+#define DAC_C0_DACTRGSEL_SHIFT                   (5U)
+#define DAC_C0_DACTRGSEL(x)                      (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
+#define DAC_C0_DACRFS_MASK                       (0x40U)
+#define DAC_C0_DACRFS_SHIFT                      (6U)
+#define DAC_C0_DACRFS(x)                         (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
+#define DAC_C0_DACEN_MASK                        (0x80U)
+#define DAC_C0_DACEN_SHIFT                       (7U)
+#define DAC_C0_DACEN(x)                          (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
+
+/*! @name C1 - DAC Control Register 1 */
+#define DAC_C1_DACBFEN_MASK                      (0x1U)
+#define DAC_C1_DACBFEN_SHIFT                     (0U)
+#define DAC_C1_DACBFEN(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
+#define DAC_C1_DACBFMD_MASK                      (0x6U)
+#define DAC_C1_DACBFMD_SHIFT                     (1U)
+#define DAC_C1_DACBFMD(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
+#define DAC_C1_DACBFWM_MASK                      (0x18U)
+#define DAC_C1_DACBFWM_SHIFT                     (3U)
+#define DAC_C1_DACBFWM(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK)
+#define DAC_C1_DMAEN_MASK                        (0x80U)
+#define DAC_C1_DMAEN_SHIFT                       (7U)
+#define DAC_C1_DMAEN(x)                          (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
+
+/*! @name C2 - DAC Control Register 2 */
+#define DAC_C2_DACBFUP_MASK                      (0xFU)
+#define DAC_C2_DACBFUP_SHIFT                     (0U)
+#define DAC_C2_DACBFUP(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
+#define DAC_C2_DACBFRP_MASK                      (0xF0U)
+#define DAC_C2_DACBFRP_SHIFT                     (4U)
+#define DAC_C2_DACBFRP(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group DAC_Register_Masks */
+
+
+/* DAC - Peripheral instance base addresses */
+/** Peripheral DAC0 base address */
+#define DAC0_BASE                                (0x400CC000u)
+/** Peripheral DAC0 base pointer */
+#define DAC0                                     ((DAC_Type *)DAC0_BASE)
+/** Peripheral DAC1 base address */
+#define DAC1_BASE                                (0x400CD000u)
+/** Peripheral DAC1 base pointer */
+#define DAC1                                     ((DAC_Type *)DAC1_BASE)
+/** Array initializer of DAC peripheral base addresses */
+#define DAC_BASE_ADDRS                           { DAC0_BASE, DAC1_BASE }
+/** Array initializer of DAC peripheral base pointers */
+#define DAC_BASE_PTRS                            { DAC0, DAC1 }
+/** Interrupt vectors for the DAC peripheral type */
+#define DAC_IRQS                                 { DAC0_IRQn, DAC1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DAC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMA Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CR;                                /**< Control Register, offset: 0x0 */
+  __I  uint32_t ES;                                /**< Error Status Register, offset: 0x4 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t ERQ;                               /**< Enable Request Register, offset: 0xC */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t EEI;                               /**< Enable Error Interrupt Register, offset: 0x14 */
+  __O  uint8_t CEEI;                               /**< Clear Enable Error Interrupt Register, offset: 0x18 */
+  __O  uint8_t SEEI;                               /**< Set Enable Error Interrupt Register, offset: 0x19 */
+  __O  uint8_t CERQ;                               /**< Clear Enable Request Register, offset: 0x1A */
+  __O  uint8_t SERQ;                               /**< Set Enable Request Register, offset: 0x1B */
+  __O  uint8_t CDNE;                               /**< Clear DONE Status Bit Register, offset: 0x1C */
+  __O  uint8_t SSRT;                               /**< Set START Bit Register, offset: 0x1D */
+  __O  uint8_t CERR;                               /**< Clear Error Register, offset: 0x1E */
+  __O  uint8_t CINT;                               /**< Clear Interrupt Request Register, offset: 0x1F */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t INT;                               /**< Interrupt Request Register, offset: 0x24 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t ERR;                               /**< Error Register, offset: 0x2C */
+       uint8_t RESERVED_4[4];
+  __I  uint32_t HRS;                               /**< Hardware Request Status Register, offset: 0x34 */
+       uint8_t RESERVED_5[12];
+  __IO uint32_t EARS;                              /**< Enable Asynchronous Request in Stop Register, offset: 0x44 */
+       uint8_t RESERVED_6[184];
+  __IO uint8_t DCHPRI3;                            /**< Channel n Priority Register, offset: 0x100 */
+  __IO uint8_t DCHPRI2;                            /**< Channel n Priority Register, offset: 0x101 */
+  __IO uint8_t DCHPRI1;                            /**< Channel n Priority Register, offset: 0x102 */
+  __IO uint8_t DCHPRI0;                            /**< Channel n Priority Register, offset: 0x103 */
+  __IO uint8_t DCHPRI7;                            /**< Channel n Priority Register, offset: 0x104 */
+  __IO uint8_t DCHPRI6;                            /**< Channel n Priority Register, offset: 0x105 */
+  __IO uint8_t DCHPRI5;                            /**< Channel n Priority Register, offset: 0x106 */
+  __IO uint8_t DCHPRI4;                            /**< Channel n Priority Register, offset: 0x107 */
+  __IO uint8_t DCHPRI11;                           /**< Channel n Priority Register, offset: 0x108 */
+  __IO uint8_t DCHPRI10;                           /**< Channel n Priority Register, offset: 0x109 */
+  __IO uint8_t DCHPRI9;                            /**< Channel n Priority Register, offset: 0x10A */
+  __IO uint8_t DCHPRI8;                            /**< Channel n Priority Register, offset: 0x10B */
+  __IO uint8_t DCHPRI15;                           /**< Channel n Priority Register, offset: 0x10C */
+  __IO uint8_t DCHPRI14;                           /**< Channel n Priority Register, offset: 0x10D */
+  __IO uint8_t DCHPRI13;                           /**< Channel n Priority Register, offset: 0x10E */
+  __IO uint8_t DCHPRI12;                           /**< Channel n Priority Register, offset: 0x10F */
+  __IO uint8_t DCHPRI19;                           /**< Channel n Priority Register, offset: 0x110 */
+  __IO uint8_t DCHPRI18;                           /**< Channel n Priority Register, offset: 0x111 */
+  __IO uint8_t DCHPRI17;                           /**< Channel n Priority Register, offset: 0x112 */
+  __IO uint8_t DCHPRI16;                           /**< Channel n Priority Register, offset: 0x113 */
+  __IO uint8_t DCHPRI23;                           /**< Channel n Priority Register, offset: 0x114 */
+  __IO uint8_t DCHPRI22;                           /**< Channel n Priority Register, offset: 0x115 */
+  __IO uint8_t DCHPRI21;                           /**< Channel n Priority Register, offset: 0x116 */
+  __IO uint8_t DCHPRI20;                           /**< Channel n Priority Register, offset: 0x117 */
+  __IO uint8_t DCHPRI27;                           /**< Channel n Priority Register, offset: 0x118 */
+  __IO uint8_t DCHPRI26;                           /**< Channel n Priority Register, offset: 0x119 */
+  __IO uint8_t DCHPRI25;                           /**< Channel n Priority Register, offset: 0x11A */
+  __IO uint8_t DCHPRI24;                           /**< Channel n Priority Register, offset: 0x11B */
+  __IO uint8_t DCHPRI31;                           /**< Channel n Priority Register, offset: 0x11C */
+  __IO uint8_t DCHPRI30;                           /**< Channel n Priority Register, offset: 0x11D */
+  __IO uint8_t DCHPRI29;                           /**< Channel n Priority Register, offset: 0x11E */
+  __IO uint8_t DCHPRI28;                           /**< Channel n Priority Register, offset: 0x11F */
+       uint8_t RESERVED_7[3808];
+  struct {                                         /* offset: 0x1000, array step: 0x20 */
+    __IO uint32_t SADDR;                             /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
+    __IO uint16_t SOFF;                              /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
+    __IO uint16_t ATTR;                              /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
+    union {                                          /* offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLNO;                       /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLOFFNO;                    /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
+      __IO uint32_t NBYTES_MLOFFYES;                   /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */
+    };
+    __IO uint32_t SLAST;                             /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
+    __IO uint32_t DADDR;                             /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
+    __IO uint16_t DOFF;                              /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
+    union {                                          /* offset: 0x1016, array step: 0x20 */
+      __IO uint16_t CITER_ELINKNO;                     /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
+      __IO uint16_t CITER_ELINKYES;                    /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
+    };
+    __IO uint32_t DLAST_SGA;                         /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
+    __IO uint16_t CSR;                               /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
+    union {                                          /* offset: 0x101E, array step: 0x20 */
+      __IO uint16_t BITER_ELINKNO;                     /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
+      __IO uint16_t BITER_ELINKYES;                    /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
+    };
+  } TCD[32];
+} DMA_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DMA Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/*! @name CR - Control Register */
+#define DMA_CR_EDBG_MASK                         (0x2U)
+#define DMA_CR_EDBG_SHIFT                        (1U)
+#define DMA_CR_EDBG(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
+#define DMA_CR_ERCA_MASK                         (0x4U)
+#define DMA_CR_ERCA_SHIFT                        (2U)
+#define DMA_CR_ERCA(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
+#define DMA_CR_ERGA_MASK                         (0x8U)
+#define DMA_CR_ERGA_SHIFT                        (3U)
+#define DMA_CR_ERGA(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)
+#define DMA_CR_HOE_MASK                          (0x10U)
+#define DMA_CR_HOE_SHIFT                         (4U)
+#define DMA_CR_HOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
+#define DMA_CR_HALT_MASK                         (0x20U)
+#define DMA_CR_HALT_SHIFT                        (5U)
+#define DMA_CR_HALT(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
+#define DMA_CR_CLM_MASK                          (0x40U)
+#define DMA_CR_CLM_SHIFT                         (6U)
+#define DMA_CR_CLM(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
+#define DMA_CR_EMLM_MASK                         (0x80U)
+#define DMA_CR_EMLM_SHIFT                        (7U)
+#define DMA_CR_EMLM(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
+#define DMA_CR_GRP0PRI_MASK                      (0x100U)
+#define DMA_CR_GRP0PRI_SHIFT                     (8U)
+#define DMA_CR_GRP0PRI(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)
+#define DMA_CR_GRP1PRI_MASK                      (0x400U)
+#define DMA_CR_GRP1PRI_SHIFT                     (10U)
+#define DMA_CR_GRP1PRI(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)
+#define DMA_CR_ECX_MASK                          (0x10000U)
+#define DMA_CR_ECX_SHIFT                         (16U)
+#define DMA_CR_ECX(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
+#define DMA_CR_CX_MASK                           (0x20000U)
+#define DMA_CR_CX_SHIFT                          (17U)
+#define DMA_CR_CX(x)                             (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
+
+/*! @name ES - Error Status Register */
+#define DMA_ES_DBE_MASK                          (0x1U)
+#define DMA_ES_DBE_SHIFT                         (0U)
+#define DMA_ES_DBE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
+#define DMA_ES_SBE_MASK                          (0x2U)
+#define DMA_ES_SBE_SHIFT                         (1U)
+#define DMA_ES_SBE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
+#define DMA_ES_SGE_MASK                          (0x4U)
+#define DMA_ES_SGE_SHIFT                         (2U)
+#define DMA_ES_SGE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
+#define DMA_ES_NCE_MASK                          (0x8U)
+#define DMA_ES_NCE_SHIFT                         (3U)
+#define DMA_ES_NCE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
+#define DMA_ES_DOE_MASK                          (0x10U)
+#define DMA_ES_DOE_SHIFT                         (4U)
+#define DMA_ES_DOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
+#define DMA_ES_DAE_MASK                          (0x20U)
+#define DMA_ES_DAE_SHIFT                         (5U)
+#define DMA_ES_DAE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
+#define DMA_ES_SOE_MASK                          (0x40U)
+#define DMA_ES_SOE_SHIFT                         (6U)
+#define DMA_ES_SOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
+#define DMA_ES_SAE_MASK                          (0x80U)
+#define DMA_ES_SAE_SHIFT                         (7U)
+#define DMA_ES_SAE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
+#define DMA_ES_ERRCHN_MASK                       (0x1F00U)
+#define DMA_ES_ERRCHN_SHIFT                      (8U)
+#define DMA_ES_ERRCHN(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
+#define DMA_ES_CPE_MASK                          (0x4000U)
+#define DMA_ES_CPE_SHIFT                         (14U)
+#define DMA_ES_CPE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
+#define DMA_ES_GPE_MASK                          (0x8000U)
+#define DMA_ES_GPE_SHIFT                         (15U)
+#define DMA_ES_GPE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)
+#define DMA_ES_ECX_MASK                          (0x10000U)
+#define DMA_ES_ECX_SHIFT                         (16U)
+#define DMA_ES_ECX(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
+#define DMA_ES_VLD_MASK                          (0x80000000U)
+#define DMA_ES_VLD_SHIFT                         (31U)
+#define DMA_ES_VLD(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
+
+/*! @name ERQ - Enable Request Register */
+#define DMA_ERQ_ERQ0_MASK                        (0x1U)
+#define DMA_ERQ_ERQ0_SHIFT                       (0U)
+#define DMA_ERQ_ERQ0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
+#define DMA_ERQ_ERQ1_MASK                        (0x2U)
+#define DMA_ERQ_ERQ1_SHIFT                       (1U)
+#define DMA_ERQ_ERQ1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
+#define DMA_ERQ_ERQ2_MASK                        (0x4U)
+#define DMA_ERQ_ERQ2_SHIFT                       (2U)
+#define DMA_ERQ_ERQ2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
+#define DMA_ERQ_ERQ3_MASK                        (0x8U)
+#define DMA_ERQ_ERQ3_SHIFT                       (3U)
+#define DMA_ERQ_ERQ3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
+#define DMA_ERQ_ERQ4_MASK                        (0x10U)
+#define DMA_ERQ_ERQ4_SHIFT                       (4U)
+#define DMA_ERQ_ERQ4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
+#define DMA_ERQ_ERQ5_MASK                        (0x20U)
+#define DMA_ERQ_ERQ5_SHIFT                       (5U)
+#define DMA_ERQ_ERQ5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
+#define DMA_ERQ_ERQ6_MASK                        (0x40U)
+#define DMA_ERQ_ERQ6_SHIFT                       (6U)
+#define DMA_ERQ_ERQ6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
+#define DMA_ERQ_ERQ7_MASK                        (0x80U)
+#define DMA_ERQ_ERQ7_SHIFT                       (7U)
+#define DMA_ERQ_ERQ7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
+#define DMA_ERQ_ERQ8_MASK                        (0x100U)
+#define DMA_ERQ_ERQ8_SHIFT                       (8U)
+#define DMA_ERQ_ERQ8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
+#define DMA_ERQ_ERQ9_MASK                        (0x200U)
+#define DMA_ERQ_ERQ9_SHIFT                       (9U)
+#define DMA_ERQ_ERQ9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
+#define DMA_ERQ_ERQ10_MASK                       (0x400U)
+#define DMA_ERQ_ERQ10_SHIFT                      (10U)
+#define DMA_ERQ_ERQ10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
+#define DMA_ERQ_ERQ11_MASK                       (0x800U)
+#define DMA_ERQ_ERQ11_SHIFT                      (11U)
+#define DMA_ERQ_ERQ11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
+#define DMA_ERQ_ERQ12_MASK                       (0x1000U)
+#define DMA_ERQ_ERQ12_SHIFT                      (12U)
+#define DMA_ERQ_ERQ12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
+#define DMA_ERQ_ERQ13_MASK                       (0x2000U)
+#define DMA_ERQ_ERQ13_SHIFT                      (13U)
+#define DMA_ERQ_ERQ13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
+#define DMA_ERQ_ERQ14_MASK                       (0x4000U)
+#define DMA_ERQ_ERQ14_SHIFT                      (14U)
+#define DMA_ERQ_ERQ14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
+#define DMA_ERQ_ERQ15_MASK                       (0x8000U)
+#define DMA_ERQ_ERQ15_SHIFT                      (15U)
+#define DMA_ERQ_ERQ15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
+#define DMA_ERQ_ERQ16_MASK                       (0x10000U)
+#define DMA_ERQ_ERQ16_SHIFT                      (16U)
+#define DMA_ERQ_ERQ16(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)
+#define DMA_ERQ_ERQ17_MASK                       (0x20000U)
+#define DMA_ERQ_ERQ17_SHIFT                      (17U)
+#define DMA_ERQ_ERQ17(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)
+#define DMA_ERQ_ERQ18_MASK                       (0x40000U)
+#define DMA_ERQ_ERQ18_SHIFT                      (18U)
+#define DMA_ERQ_ERQ18(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)
+#define DMA_ERQ_ERQ19_MASK                       (0x80000U)
+#define DMA_ERQ_ERQ19_SHIFT                      (19U)
+#define DMA_ERQ_ERQ19(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)
+#define DMA_ERQ_ERQ20_MASK                       (0x100000U)
+#define DMA_ERQ_ERQ20_SHIFT                      (20U)
+#define DMA_ERQ_ERQ20(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)
+#define DMA_ERQ_ERQ21_MASK                       (0x200000U)
+#define DMA_ERQ_ERQ21_SHIFT                      (21U)
+#define DMA_ERQ_ERQ21(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)
+#define DMA_ERQ_ERQ22_MASK                       (0x400000U)
+#define DMA_ERQ_ERQ22_SHIFT                      (22U)
+#define DMA_ERQ_ERQ22(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)
+#define DMA_ERQ_ERQ23_MASK                       (0x800000U)
+#define DMA_ERQ_ERQ23_SHIFT                      (23U)
+#define DMA_ERQ_ERQ23(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)
+#define DMA_ERQ_ERQ24_MASK                       (0x1000000U)
+#define DMA_ERQ_ERQ24_SHIFT                      (24U)
+#define DMA_ERQ_ERQ24(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)
+#define DMA_ERQ_ERQ25_MASK                       (0x2000000U)
+#define DMA_ERQ_ERQ25_SHIFT                      (25U)
+#define DMA_ERQ_ERQ25(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)
+#define DMA_ERQ_ERQ26_MASK                       (0x4000000U)
+#define DMA_ERQ_ERQ26_SHIFT                      (26U)
+#define DMA_ERQ_ERQ26(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)
+#define DMA_ERQ_ERQ27_MASK                       (0x8000000U)
+#define DMA_ERQ_ERQ27_SHIFT                      (27U)
+#define DMA_ERQ_ERQ27(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)
+#define DMA_ERQ_ERQ28_MASK                       (0x10000000U)
+#define DMA_ERQ_ERQ28_SHIFT                      (28U)
+#define DMA_ERQ_ERQ28(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)
+#define DMA_ERQ_ERQ29_MASK                       (0x20000000U)
+#define DMA_ERQ_ERQ29_SHIFT                      (29U)
+#define DMA_ERQ_ERQ29(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)
+#define DMA_ERQ_ERQ30_MASK                       (0x40000000U)
+#define DMA_ERQ_ERQ30_SHIFT                      (30U)
+#define DMA_ERQ_ERQ30(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)
+#define DMA_ERQ_ERQ31_MASK                       (0x80000000U)
+#define DMA_ERQ_ERQ31_SHIFT                      (31U)
+#define DMA_ERQ_ERQ31(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)
+
+/*! @name EEI - Enable Error Interrupt Register */
+#define DMA_EEI_EEI0_MASK                        (0x1U)
+#define DMA_EEI_EEI0_SHIFT                       (0U)
+#define DMA_EEI_EEI0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
+#define DMA_EEI_EEI1_MASK                        (0x2U)
+#define DMA_EEI_EEI1_SHIFT                       (1U)
+#define DMA_EEI_EEI1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
+#define DMA_EEI_EEI2_MASK                        (0x4U)
+#define DMA_EEI_EEI2_SHIFT                       (2U)
+#define DMA_EEI_EEI2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
+#define DMA_EEI_EEI3_MASK                        (0x8U)
+#define DMA_EEI_EEI3_SHIFT                       (3U)
+#define DMA_EEI_EEI3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
+#define DMA_EEI_EEI4_MASK                        (0x10U)
+#define DMA_EEI_EEI4_SHIFT                       (4U)
+#define DMA_EEI_EEI4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
+#define DMA_EEI_EEI5_MASK                        (0x20U)
+#define DMA_EEI_EEI5_SHIFT                       (5U)
+#define DMA_EEI_EEI5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
+#define DMA_EEI_EEI6_MASK                        (0x40U)
+#define DMA_EEI_EEI6_SHIFT                       (6U)
+#define DMA_EEI_EEI6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
+#define DMA_EEI_EEI7_MASK                        (0x80U)
+#define DMA_EEI_EEI7_SHIFT                       (7U)
+#define DMA_EEI_EEI7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
+#define DMA_EEI_EEI8_MASK                        (0x100U)
+#define DMA_EEI_EEI8_SHIFT                       (8U)
+#define DMA_EEI_EEI8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
+#define DMA_EEI_EEI9_MASK                        (0x200U)
+#define DMA_EEI_EEI9_SHIFT                       (9U)
+#define DMA_EEI_EEI9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
+#define DMA_EEI_EEI10_MASK                       (0x400U)
+#define DMA_EEI_EEI10_SHIFT                      (10U)
+#define DMA_EEI_EEI10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
+#define DMA_EEI_EEI11_MASK                       (0x800U)
+#define DMA_EEI_EEI11_SHIFT                      (11U)
+#define DMA_EEI_EEI11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
+#define DMA_EEI_EEI12_MASK                       (0x1000U)
+#define DMA_EEI_EEI12_SHIFT                      (12U)
+#define DMA_EEI_EEI12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
+#define DMA_EEI_EEI13_MASK                       (0x2000U)
+#define DMA_EEI_EEI13_SHIFT                      (13U)
+#define DMA_EEI_EEI13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
+#define DMA_EEI_EEI14_MASK                       (0x4000U)
+#define DMA_EEI_EEI14_SHIFT                      (14U)
+#define DMA_EEI_EEI14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
+#define DMA_EEI_EEI15_MASK                       (0x8000U)
+#define DMA_EEI_EEI15_SHIFT                      (15U)
+#define DMA_EEI_EEI15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
+#define DMA_EEI_EEI16_MASK                       (0x10000U)
+#define DMA_EEI_EEI16_SHIFT                      (16U)
+#define DMA_EEI_EEI16(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)
+#define DMA_EEI_EEI17_MASK                       (0x20000U)
+#define DMA_EEI_EEI17_SHIFT                      (17U)
+#define DMA_EEI_EEI17(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)
+#define DMA_EEI_EEI18_MASK                       (0x40000U)
+#define DMA_EEI_EEI18_SHIFT                      (18U)
+#define DMA_EEI_EEI18(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)
+#define DMA_EEI_EEI19_MASK                       (0x80000U)
+#define DMA_EEI_EEI19_SHIFT                      (19U)
+#define DMA_EEI_EEI19(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)
+#define DMA_EEI_EEI20_MASK                       (0x100000U)
+#define DMA_EEI_EEI20_SHIFT                      (20U)
+#define DMA_EEI_EEI20(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)
+#define DMA_EEI_EEI21_MASK                       (0x200000U)
+#define DMA_EEI_EEI21_SHIFT                      (21U)
+#define DMA_EEI_EEI21(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)
+#define DMA_EEI_EEI22_MASK                       (0x400000U)
+#define DMA_EEI_EEI22_SHIFT                      (22U)
+#define DMA_EEI_EEI22(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)
+#define DMA_EEI_EEI23_MASK                       (0x800000U)
+#define DMA_EEI_EEI23_SHIFT                      (23U)
+#define DMA_EEI_EEI23(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)
+#define DMA_EEI_EEI24_MASK                       (0x1000000U)
+#define DMA_EEI_EEI24_SHIFT                      (24U)
+#define DMA_EEI_EEI24(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)
+#define DMA_EEI_EEI25_MASK                       (0x2000000U)
+#define DMA_EEI_EEI25_SHIFT                      (25U)
+#define DMA_EEI_EEI25(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)
+#define DMA_EEI_EEI26_MASK                       (0x4000000U)
+#define DMA_EEI_EEI26_SHIFT                      (26U)
+#define DMA_EEI_EEI26(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)
+#define DMA_EEI_EEI27_MASK                       (0x8000000U)
+#define DMA_EEI_EEI27_SHIFT                      (27U)
+#define DMA_EEI_EEI27(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)
+#define DMA_EEI_EEI28_MASK                       (0x10000000U)
+#define DMA_EEI_EEI28_SHIFT                      (28U)
+#define DMA_EEI_EEI28(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)
+#define DMA_EEI_EEI29_MASK                       (0x20000000U)
+#define DMA_EEI_EEI29_SHIFT                      (29U)
+#define DMA_EEI_EEI29(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)
+#define DMA_EEI_EEI30_MASK                       (0x40000000U)
+#define DMA_EEI_EEI30_SHIFT                      (30U)
+#define DMA_EEI_EEI30(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)
+#define DMA_EEI_EEI31_MASK                       (0x80000000U)
+#define DMA_EEI_EEI31_SHIFT                      (31U)
+#define DMA_EEI_EEI31(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)
+
+/*! @name CEEI - Clear Enable Error Interrupt Register */
+#define DMA_CEEI_CEEI_MASK                       (0x1FU)
+#define DMA_CEEI_CEEI_SHIFT                      (0U)
+#define DMA_CEEI_CEEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
+#define DMA_CEEI_CAEE_MASK                       (0x40U)
+#define DMA_CEEI_CAEE_SHIFT                      (6U)
+#define DMA_CEEI_CAEE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
+#define DMA_CEEI_NOP_MASK                        (0x80U)
+#define DMA_CEEI_NOP_SHIFT                       (7U)
+#define DMA_CEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
+
+/*! @name SEEI - Set Enable Error Interrupt Register */
+#define DMA_SEEI_SEEI_MASK                       (0x1FU)
+#define DMA_SEEI_SEEI_SHIFT                      (0U)
+#define DMA_SEEI_SEEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
+#define DMA_SEEI_SAEE_MASK                       (0x40U)
+#define DMA_SEEI_SAEE_SHIFT                      (6U)
+#define DMA_SEEI_SAEE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
+#define DMA_SEEI_NOP_MASK                        (0x80U)
+#define DMA_SEEI_NOP_SHIFT                       (7U)
+#define DMA_SEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
+
+/*! @name CERQ - Clear Enable Request Register */
+#define DMA_CERQ_CERQ_MASK                       (0x1FU)
+#define DMA_CERQ_CERQ_SHIFT                      (0U)
+#define DMA_CERQ_CERQ(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
+#define DMA_CERQ_CAER_MASK                       (0x40U)
+#define DMA_CERQ_CAER_SHIFT                      (6U)
+#define DMA_CERQ_CAER(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
+#define DMA_CERQ_NOP_MASK                        (0x80U)
+#define DMA_CERQ_NOP_SHIFT                       (7U)
+#define DMA_CERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
+
+/*! @name SERQ - Set Enable Request Register */
+#define DMA_SERQ_SERQ_MASK                       (0x1FU)
+#define DMA_SERQ_SERQ_SHIFT                      (0U)
+#define DMA_SERQ_SERQ(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
+#define DMA_SERQ_SAER_MASK                       (0x40U)
+#define DMA_SERQ_SAER_SHIFT                      (6U)
+#define DMA_SERQ_SAER(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
+#define DMA_SERQ_NOP_MASK                        (0x80U)
+#define DMA_SERQ_NOP_SHIFT                       (7U)
+#define DMA_SERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
+
+/*! @name CDNE - Clear DONE Status Bit Register */
+#define DMA_CDNE_CDNE_MASK                       (0x1FU)
+#define DMA_CDNE_CDNE_SHIFT                      (0U)
+#define DMA_CDNE_CDNE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
+#define DMA_CDNE_CADN_MASK                       (0x40U)
+#define DMA_CDNE_CADN_SHIFT                      (6U)
+#define DMA_CDNE_CADN(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
+#define DMA_CDNE_NOP_MASK                        (0x80U)
+#define DMA_CDNE_NOP_SHIFT                       (7U)
+#define DMA_CDNE_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
+
+/*! @name SSRT - Set START Bit Register */
+#define DMA_SSRT_SSRT_MASK                       (0x1FU)
+#define DMA_SSRT_SSRT_SHIFT                      (0U)
+#define DMA_SSRT_SSRT(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
+#define DMA_SSRT_SAST_MASK                       (0x40U)
+#define DMA_SSRT_SAST_SHIFT                      (6U)
+#define DMA_SSRT_SAST(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
+#define DMA_SSRT_NOP_MASK                        (0x80U)
+#define DMA_SSRT_NOP_SHIFT                       (7U)
+#define DMA_SSRT_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
+
+/*! @name CERR - Clear Error Register */
+#define DMA_CERR_CERR_MASK                       (0x1FU)
+#define DMA_CERR_CERR_SHIFT                      (0U)
+#define DMA_CERR_CERR(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
+#define DMA_CERR_CAEI_MASK                       (0x40U)
+#define DMA_CERR_CAEI_SHIFT                      (6U)
+#define DMA_CERR_CAEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
+#define DMA_CERR_NOP_MASK                        (0x80U)
+#define DMA_CERR_NOP_SHIFT                       (7U)
+#define DMA_CERR_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
+
+/*! @name CINT - Clear Interrupt Request Register */
+#define DMA_CINT_CINT_MASK                       (0x1FU)
+#define DMA_CINT_CINT_SHIFT                      (0U)
+#define DMA_CINT_CINT(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
+#define DMA_CINT_CAIR_MASK                       (0x40U)
+#define DMA_CINT_CAIR_SHIFT                      (6U)
+#define DMA_CINT_CAIR(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
+#define DMA_CINT_NOP_MASK                        (0x80U)
+#define DMA_CINT_NOP_SHIFT                       (7U)
+#define DMA_CINT_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
+
+/*! @name INT - Interrupt Request Register */
+#define DMA_INT_INT0_MASK                        (0x1U)
+#define DMA_INT_INT0_SHIFT                       (0U)
+#define DMA_INT_INT0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
+#define DMA_INT_INT1_MASK                        (0x2U)
+#define DMA_INT_INT1_SHIFT                       (1U)
+#define DMA_INT_INT1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
+#define DMA_INT_INT2_MASK                        (0x4U)
+#define DMA_INT_INT2_SHIFT                       (2U)
+#define DMA_INT_INT2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
+#define DMA_INT_INT3_MASK                        (0x8U)
+#define DMA_INT_INT3_SHIFT                       (3U)
+#define DMA_INT_INT3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
+#define DMA_INT_INT4_MASK                        (0x10U)
+#define DMA_INT_INT4_SHIFT                       (4U)
+#define DMA_INT_INT4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
+#define DMA_INT_INT5_MASK                        (0x20U)
+#define DMA_INT_INT5_SHIFT                       (5U)
+#define DMA_INT_INT5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
+#define DMA_INT_INT6_MASK                        (0x40U)
+#define DMA_INT_INT6_SHIFT                       (6U)
+#define DMA_INT_INT6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
+#define DMA_INT_INT7_MASK                        (0x80U)
+#define DMA_INT_INT7_SHIFT                       (7U)
+#define DMA_INT_INT7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
+#define DMA_INT_INT8_MASK                        (0x100U)
+#define DMA_INT_INT8_SHIFT                       (8U)
+#define DMA_INT_INT8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
+#define DMA_INT_INT9_MASK                        (0x200U)
+#define DMA_INT_INT9_SHIFT                       (9U)
+#define DMA_INT_INT9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
+#define DMA_INT_INT10_MASK                       (0x400U)
+#define DMA_INT_INT10_SHIFT                      (10U)
+#define DMA_INT_INT10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
+#define DMA_INT_INT11_MASK                       (0x800U)
+#define DMA_INT_INT11_SHIFT                      (11U)
+#define DMA_INT_INT11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
+#define DMA_INT_INT12_MASK                       (0x1000U)
+#define DMA_INT_INT12_SHIFT                      (12U)
+#define DMA_INT_INT12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
+#define DMA_INT_INT13_MASK                       (0x2000U)
+#define DMA_INT_INT13_SHIFT                      (13U)
+#define DMA_INT_INT13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
+#define DMA_INT_INT14_MASK                       (0x4000U)
+#define DMA_INT_INT14_SHIFT                      (14U)
+#define DMA_INT_INT14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
+#define DMA_INT_INT15_MASK                       (0x8000U)
+#define DMA_INT_INT15_SHIFT                      (15U)
+#define DMA_INT_INT15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
+#define DMA_INT_INT16_MASK                       (0x10000U)
+#define DMA_INT_INT16_SHIFT                      (16U)
+#define DMA_INT_INT16(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)
+#define DMA_INT_INT17_MASK                       (0x20000U)
+#define DMA_INT_INT17_SHIFT                      (17U)
+#define DMA_INT_INT17(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)
+#define DMA_INT_INT18_MASK                       (0x40000U)
+#define DMA_INT_INT18_SHIFT                      (18U)
+#define DMA_INT_INT18(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)
+#define DMA_INT_INT19_MASK                       (0x80000U)
+#define DMA_INT_INT19_SHIFT                      (19U)
+#define DMA_INT_INT19(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)
+#define DMA_INT_INT20_MASK                       (0x100000U)
+#define DMA_INT_INT20_SHIFT                      (20U)
+#define DMA_INT_INT20(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)
+#define DMA_INT_INT21_MASK                       (0x200000U)
+#define DMA_INT_INT21_SHIFT                      (21U)
+#define DMA_INT_INT21(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)
+#define DMA_INT_INT22_MASK                       (0x400000U)
+#define DMA_INT_INT22_SHIFT                      (22U)
+#define DMA_INT_INT22(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)
+#define DMA_INT_INT23_MASK                       (0x800000U)
+#define DMA_INT_INT23_SHIFT                      (23U)
+#define DMA_INT_INT23(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)
+#define DMA_INT_INT24_MASK                       (0x1000000U)
+#define DMA_INT_INT24_SHIFT                      (24U)
+#define DMA_INT_INT24(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)
+#define DMA_INT_INT25_MASK                       (0x2000000U)
+#define DMA_INT_INT25_SHIFT                      (25U)
+#define DMA_INT_INT25(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)
+#define DMA_INT_INT26_MASK                       (0x4000000U)
+#define DMA_INT_INT26_SHIFT                      (26U)
+#define DMA_INT_INT26(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)
+#define DMA_INT_INT27_MASK                       (0x8000000U)
+#define DMA_INT_INT27_SHIFT                      (27U)
+#define DMA_INT_INT27(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)
+#define DMA_INT_INT28_MASK                       (0x10000000U)
+#define DMA_INT_INT28_SHIFT                      (28U)
+#define DMA_INT_INT28(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)
+#define DMA_INT_INT29_MASK                       (0x20000000U)
+#define DMA_INT_INT29_SHIFT                      (29U)
+#define DMA_INT_INT29(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)
+#define DMA_INT_INT30_MASK                       (0x40000000U)
+#define DMA_INT_INT30_SHIFT                      (30U)
+#define DMA_INT_INT30(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)
+#define DMA_INT_INT31_MASK                       (0x80000000U)
+#define DMA_INT_INT31_SHIFT                      (31U)
+#define DMA_INT_INT31(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)
+
+/*! @name ERR - Error Register */
+#define DMA_ERR_ERR0_MASK                        (0x1U)
+#define DMA_ERR_ERR0_SHIFT                       (0U)
+#define DMA_ERR_ERR0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
+#define DMA_ERR_ERR1_MASK                        (0x2U)
+#define DMA_ERR_ERR1_SHIFT                       (1U)
+#define DMA_ERR_ERR1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
+#define DMA_ERR_ERR2_MASK                        (0x4U)
+#define DMA_ERR_ERR2_SHIFT                       (2U)
+#define DMA_ERR_ERR2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
+#define DMA_ERR_ERR3_MASK                        (0x8U)
+#define DMA_ERR_ERR3_SHIFT                       (3U)
+#define DMA_ERR_ERR3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
+#define DMA_ERR_ERR4_MASK                        (0x10U)
+#define DMA_ERR_ERR4_SHIFT                       (4U)
+#define DMA_ERR_ERR4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
+#define DMA_ERR_ERR5_MASK                        (0x20U)
+#define DMA_ERR_ERR5_SHIFT                       (5U)
+#define DMA_ERR_ERR5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
+#define DMA_ERR_ERR6_MASK                        (0x40U)
+#define DMA_ERR_ERR6_SHIFT                       (6U)
+#define DMA_ERR_ERR6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
+#define DMA_ERR_ERR7_MASK                        (0x80U)
+#define DMA_ERR_ERR7_SHIFT                       (7U)
+#define DMA_ERR_ERR7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
+#define DMA_ERR_ERR8_MASK                        (0x100U)
+#define DMA_ERR_ERR8_SHIFT                       (8U)
+#define DMA_ERR_ERR8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
+#define DMA_ERR_ERR9_MASK                        (0x200U)
+#define DMA_ERR_ERR9_SHIFT                       (9U)
+#define DMA_ERR_ERR9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
+#define DMA_ERR_ERR10_MASK                       (0x400U)
+#define DMA_ERR_ERR10_SHIFT                      (10U)
+#define DMA_ERR_ERR10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
+#define DMA_ERR_ERR11_MASK                       (0x800U)
+#define DMA_ERR_ERR11_SHIFT                      (11U)
+#define DMA_ERR_ERR11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
+#define DMA_ERR_ERR12_MASK                       (0x1000U)
+#define DMA_ERR_ERR12_SHIFT                      (12U)
+#define DMA_ERR_ERR12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
+#define DMA_ERR_ERR13_MASK                       (0x2000U)
+#define DMA_ERR_ERR13_SHIFT                      (13U)
+#define DMA_ERR_ERR13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
+#define DMA_ERR_ERR14_MASK                       (0x4000U)
+#define DMA_ERR_ERR14_SHIFT                      (14U)
+#define DMA_ERR_ERR14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
+#define DMA_ERR_ERR15_MASK                       (0x8000U)
+#define DMA_ERR_ERR15_SHIFT                      (15U)
+#define DMA_ERR_ERR15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
+#define DMA_ERR_ERR16_MASK                       (0x10000U)
+#define DMA_ERR_ERR16_SHIFT                      (16U)
+#define DMA_ERR_ERR16(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)
+#define DMA_ERR_ERR17_MASK                       (0x20000U)
+#define DMA_ERR_ERR17_SHIFT                      (17U)
+#define DMA_ERR_ERR17(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)
+#define DMA_ERR_ERR18_MASK                       (0x40000U)
+#define DMA_ERR_ERR18_SHIFT                      (18U)
+#define DMA_ERR_ERR18(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)
+#define DMA_ERR_ERR19_MASK                       (0x80000U)
+#define DMA_ERR_ERR19_SHIFT                      (19U)
+#define DMA_ERR_ERR19(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)
+#define DMA_ERR_ERR20_MASK                       (0x100000U)
+#define DMA_ERR_ERR20_SHIFT                      (20U)
+#define DMA_ERR_ERR20(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)
+#define DMA_ERR_ERR21_MASK                       (0x200000U)
+#define DMA_ERR_ERR21_SHIFT                      (21U)
+#define DMA_ERR_ERR21(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)
+#define DMA_ERR_ERR22_MASK                       (0x400000U)
+#define DMA_ERR_ERR22_SHIFT                      (22U)
+#define DMA_ERR_ERR22(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)
+#define DMA_ERR_ERR23_MASK                       (0x800000U)
+#define DMA_ERR_ERR23_SHIFT                      (23U)
+#define DMA_ERR_ERR23(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)
+#define DMA_ERR_ERR24_MASK                       (0x1000000U)
+#define DMA_ERR_ERR24_SHIFT                      (24U)
+#define DMA_ERR_ERR24(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)
+#define DMA_ERR_ERR25_MASK                       (0x2000000U)
+#define DMA_ERR_ERR25_SHIFT                      (25U)
+#define DMA_ERR_ERR25(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)
+#define DMA_ERR_ERR26_MASK                       (0x4000000U)
+#define DMA_ERR_ERR26_SHIFT                      (26U)
+#define DMA_ERR_ERR26(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)
+#define DMA_ERR_ERR27_MASK                       (0x8000000U)
+#define DMA_ERR_ERR27_SHIFT                      (27U)
+#define DMA_ERR_ERR27(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)
+#define DMA_ERR_ERR28_MASK                       (0x10000000U)
+#define DMA_ERR_ERR28_SHIFT                      (28U)
+#define DMA_ERR_ERR28(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)
+#define DMA_ERR_ERR29_MASK                       (0x20000000U)
+#define DMA_ERR_ERR29_SHIFT                      (29U)
+#define DMA_ERR_ERR29(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)
+#define DMA_ERR_ERR30_MASK                       (0x40000000U)
+#define DMA_ERR_ERR30_SHIFT                      (30U)
+#define DMA_ERR_ERR30(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)
+#define DMA_ERR_ERR31_MASK                       (0x80000000U)
+#define DMA_ERR_ERR31_SHIFT                      (31U)
+#define DMA_ERR_ERR31(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)
+
+/*! @name HRS - Hardware Request Status Register */
+#define DMA_HRS_HRS0_MASK                        (0x1U)
+#define DMA_HRS_HRS0_SHIFT                       (0U)
+#define DMA_HRS_HRS0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
+#define DMA_HRS_HRS1_MASK                        (0x2U)
+#define DMA_HRS_HRS1_SHIFT                       (1U)
+#define DMA_HRS_HRS1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
+#define DMA_HRS_HRS2_MASK                        (0x4U)
+#define DMA_HRS_HRS2_SHIFT                       (2U)
+#define DMA_HRS_HRS2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
+#define DMA_HRS_HRS3_MASK                        (0x8U)
+#define DMA_HRS_HRS3_SHIFT                       (3U)
+#define DMA_HRS_HRS3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
+#define DMA_HRS_HRS4_MASK                        (0x10U)
+#define DMA_HRS_HRS4_SHIFT                       (4U)
+#define DMA_HRS_HRS4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
+#define DMA_HRS_HRS5_MASK                        (0x20U)
+#define DMA_HRS_HRS5_SHIFT                       (5U)
+#define DMA_HRS_HRS5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
+#define DMA_HRS_HRS6_MASK                        (0x40U)
+#define DMA_HRS_HRS6_SHIFT                       (6U)
+#define DMA_HRS_HRS6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
+#define DMA_HRS_HRS7_MASK                        (0x80U)
+#define DMA_HRS_HRS7_SHIFT                       (7U)
+#define DMA_HRS_HRS7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
+#define DMA_HRS_HRS8_MASK                        (0x100U)
+#define DMA_HRS_HRS8_SHIFT                       (8U)
+#define DMA_HRS_HRS8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
+#define DMA_HRS_HRS9_MASK                        (0x200U)
+#define DMA_HRS_HRS9_SHIFT                       (9U)
+#define DMA_HRS_HRS9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
+#define DMA_HRS_HRS10_MASK                       (0x400U)
+#define DMA_HRS_HRS10_SHIFT                      (10U)
+#define DMA_HRS_HRS10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
+#define DMA_HRS_HRS11_MASK                       (0x800U)
+#define DMA_HRS_HRS11_SHIFT                      (11U)
+#define DMA_HRS_HRS11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
+#define DMA_HRS_HRS12_MASK                       (0x1000U)
+#define DMA_HRS_HRS12_SHIFT                      (12U)
+#define DMA_HRS_HRS12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
+#define DMA_HRS_HRS13_MASK                       (0x2000U)
+#define DMA_HRS_HRS13_SHIFT                      (13U)
+#define DMA_HRS_HRS13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
+#define DMA_HRS_HRS14_MASK                       (0x4000U)
+#define DMA_HRS_HRS14_SHIFT                      (14U)
+#define DMA_HRS_HRS14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
+#define DMA_HRS_HRS15_MASK                       (0x8000U)
+#define DMA_HRS_HRS15_SHIFT                      (15U)
+#define DMA_HRS_HRS15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
+#define DMA_HRS_HRS16_MASK                       (0x10000U)
+#define DMA_HRS_HRS16_SHIFT                      (16U)
+#define DMA_HRS_HRS16(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)
+#define DMA_HRS_HRS17_MASK                       (0x20000U)
+#define DMA_HRS_HRS17_SHIFT                      (17U)
+#define DMA_HRS_HRS17(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)
+#define DMA_HRS_HRS18_MASK                       (0x40000U)
+#define DMA_HRS_HRS18_SHIFT                      (18U)
+#define DMA_HRS_HRS18(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)
+#define DMA_HRS_HRS19_MASK                       (0x80000U)
+#define DMA_HRS_HRS19_SHIFT                      (19U)
+#define DMA_HRS_HRS19(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)
+#define DMA_HRS_HRS20_MASK                       (0x100000U)
+#define DMA_HRS_HRS20_SHIFT                      (20U)
+#define DMA_HRS_HRS20(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)
+#define DMA_HRS_HRS21_MASK                       (0x200000U)
+#define DMA_HRS_HRS21_SHIFT                      (21U)
+#define DMA_HRS_HRS21(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)
+#define DMA_HRS_HRS22_MASK                       (0x400000U)
+#define DMA_HRS_HRS22_SHIFT                      (22U)
+#define DMA_HRS_HRS22(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)
+#define DMA_HRS_HRS23_MASK                       (0x800000U)
+#define DMA_HRS_HRS23_SHIFT                      (23U)
+#define DMA_HRS_HRS23(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)
+#define DMA_HRS_HRS24_MASK                       (0x1000000U)
+#define DMA_HRS_HRS24_SHIFT                      (24U)
+#define DMA_HRS_HRS24(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)
+#define DMA_HRS_HRS25_MASK                       (0x2000000U)
+#define DMA_HRS_HRS25_SHIFT                      (25U)
+#define DMA_HRS_HRS25(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)
+#define DMA_HRS_HRS26_MASK                       (0x4000000U)
+#define DMA_HRS_HRS26_SHIFT                      (26U)
+#define DMA_HRS_HRS26(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)
+#define DMA_HRS_HRS27_MASK                       (0x8000000U)
+#define DMA_HRS_HRS27_SHIFT                      (27U)
+#define DMA_HRS_HRS27(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)
+#define DMA_HRS_HRS28_MASK                       (0x10000000U)
+#define DMA_HRS_HRS28_SHIFT                      (28U)
+#define DMA_HRS_HRS28(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)
+#define DMA_HRS_HRS29_MASK                       (0x20000000U)
+#define DMA_HRS_HRS29_SHIFT                      (29U)
+#define DMA_HRS_HRS29(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)
+#define DMA_HRS_HRS30_MASK                       (0x40000000U)
+#define DMA_HRS_HRS30_SHIFT                      (30U)
+#define DMA_HRS_HRS30(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)
+#define DMA_HRS_HRS31_MASK                       (0x80000000U)
+#define DMA_HRS_HRS31_SHIFT                      (31U)
+#define DMA_HRS_HRS31(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)
+
+/*! @name EARS - Enable Asynchronous Request in Stop Register */
+#define DMA_EARS_EDREQ_0_MASK                    (0x1U)
+#define DMA_EARS_EDREQ_0_SHIFT                   (0U)
+#define DMA_EARS_EDREQ_0(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
+#define DMA_EARS_EDREQ_1_MASK                    (0x2U)
+#define DMA_EARS_EDREQ_1_SHIFT                   (1U)
+#define DMA_EARS_EDREQ_1(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
+#define DMA_EARS_EDREQ_2_MASK                    (0x4U)
+#define DMA_EARS_EDREQ_2_SHIFT                   (2U)
+#define DMA_EARS_EDREQ_2(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
+#define DMA_EARS_EDREQ_3_MASK                    (0x8U)
+#define DMA_EARS_EDREQ_3_SHIFT                   (3U)
+#define DMA_EARS_EDREQ_3(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
+#define DMA_EARS_EDREQ_4_MASK                    (0x10U)
+#define DMA_EARS_EDREQ_4_SHIFT                   (4U)
+#define DMA_EARS_EDREQ_4(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
+#define DMA_EARS_EDREQ_5_MASK                    (0x20U)
+#define DMA_EARS_EDREQ_5_SHIFT                   (5U)
+#define DMA_EARS_EDREQ_5(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
+#define DMA_EARS_EDREQ_6_MASK                    (0x40U)
+#define DMA_EARS_EDREQ_6_SHIFT                   (6U)
+#define DMA_EARS_EDREQ_6(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
+#define DMA_EARS_EDREQ_7_MASK                    (0x80U)
+#define DMA_EARS_EDREQ_7_SHIFT                   (7U)
+#define DMA_EARS_EDREQ_7(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
+#define DMA_EARS_EDREQ_8_MASK                    (0x100U)
+#define DMA_EARS_EDREQ_8_SHIFT                   (8U)
+#define DMA_EARS_EDREQ_8(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)
+#define DMA_EARS_EDREQ_9_MASK                    (0x200U)
+#define DMA_EARS_EDREQ_9_SHIFT                   (9U)
+#define DMA_EARS_EDREQ_9(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)
+#define DMA_EARS_EDREQ_10_MASK                   (0x400U)
+#define DMA_EARS_EDREQ_10_SHIFT                  (10U)
+#define DMA_EARS_EDREQ_10(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)
+#define DMA_EARS_EDREQ_11_MASK                   (0x800U)
+#define DMA_EARS_EDREQ_11_SHIFT                  (11U)
+#define DMA_EARS_EDREQ_11(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)
+#define DMA_EARS_EDREQ_12_MASK                   (0x1000U)
+#define DMA_EARS_EDREQ_12_SHIFT                  (12U)
+#define DMA_EARS_EDREQ_12(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)
+#define DMA_EARS_EDREQ_13_MASK                   (0x2000U)
+#define DMA_EARS_EDREQ_13_SHIFT                  (13U)
+#define DMA_EARS_EDREQ_13(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)
+#define DMA_EARS_EDREQ_14_MASK                   (0x4000U)
+#define DMA_EARS_EDREQ_14_SHIFT                  (14U)
+#define DMA_EARS_EDREQ_14(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)
+#define DMA_EARS_EDREQ_15_MASK                   (0x8000U)
+#define DMA_EARS_EDREQ_15_SHIFT                  (15U)
+#define DMA_EARS_EDREQ_15(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)
+#define DMA_EARS_EDREQ_16_MASK                   (0x10000U)
+#define DMA_EARS_EDREQ_16_SHIFT                  (16U)
+#define DMA_EARS_EDREQ_16(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)
+#define DMA_EARS_EDREQ_17_MASK                   (0x20000U)
+#define DMA_EARS_EDREQ_17_SHIFT                  (17U)
+#define DMA_EARS_EDREQ_17(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)
+#define DMA_EARS_EDREQ_18_MASK                   (0x40000U)
+#define DMA_EARS_EDREQ_18_SHIFT                  (18U)
+#define DMA_EARS_EDREQ_18(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)
+#define DMA_EARS_EDREQ_19_MASK                   (0x80000U)
+#define DMA_EARS_EDREQ_19_SHIFT                  (19U)
+#define DMA_EARS_EDREQ_19(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)
+#define DMA_EARS_EDREQ_20_MASK                   (0x100000U)
+#define DMA_EARS_EDREQ_20_SHIFT                  (20U)
+#define DMA_EARS_EDREQ_20(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)
+#define DMA_EARS_EDREQ_21_MASK                   (0x200000U)
+#define DMA_EARS_EDREQ_21_SHIFT                  (21U)
+#define DMA_EARS_EDREQ_21(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)
+#define DMA_EARS_EDREQ_22_MASK                   (0x400000U)
+#define DMA_EARS_EDREQ_22_SHIFT                  (22U)
+#define DMA_EARS_EDREQ_22(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)
+#define DMA_EARS_EDREQ_23_MASK                   (0x800000U)
+#define DMA_EARS_EDREQ_23_SHIFT                  (23U)
+#define DMA_EARS_EDREQ_23(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)
+#define DMA_EARS_EDREQ_24_MASK                   (0x1000000U)
+#define DMA_EARS_EDREQ_24_SHIFT                  (24U)
+#define DMA_EARS_EDREQ_24(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)
+#define DMA_EARS_EDREQ_25_MASK                   (0x2000000U)
+#define DMA_EARS_EDREQ_25_SHIFT                  (25U)
+#define DMA_EARS_EDREQ_25(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)
+#define DMA_EARS_EDREQ_26_MASK                   (0x4000000U)
+#define DMA_EARS_EDREQ_26_SHIFT                  (26U)
+#define DMA_EARS_EDREQ_26(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)
+#define DMA_EARS_EDREQ_27_MASK                   (0x8000000U)
+#define DMA_EARS_EDREQ_27_SHIFT                  (27U)
+#define DMA_EARS_EDREQ_27(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)
+#define DMA_EARS_EDREQ_28_MASK                   (0x10000000U)
+#define DMA_EARS_EDREQ_28_SHIFT                  (28U)
+#define DMA_EARS_EDREQ_28(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)
+#define DMA_EARS_EDREQ_29_MASK                   (0x20000000U)
+#define DMA_EARS_EDREQ_29_SHIFT                  (29U)
+#define DMA_EARS_EDREQ_29(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)
+#define DMA_EARS_EDREQ_30_MASK                   (0x40000000U)
+#define DMA_EARS_EDREQ_30_SHIFT                  (30U)
+#define DMA_EARS_EDREQ_30(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)
+#define DMA_EARS_EDREQ_31_MASK                   (0x80000000U)
+#define DMA_EARS_EDREQ_31_SHIFT                  (31U)
+#define DMA_EARS_EDREQ_31(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)
+
+/*! @name DCHPRI3 - Channel n Priority Register */
+#define DMA_DCHPRI3_CHPRI_MASK                   (0xFU)
+#define DMA_DCHPRI3_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI3_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
+#define DMA_DCHPRI3_GRPPRI_MASK                  (0x30U)
+#define DMA_DCHPRI3_GRPPRI_SHIFT                 (4U)
+#define DMA_DCHPRI3_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)
+#define DMA_DCHPRI3_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI3_DPA_SHIFT                    (6U)
+#define DMA_DCHPRI3_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
+#define DMA_DCHPRI3_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI3_ECP_SHIFT                    (7U)
+#define DMA_DCHPRI3_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
+
+/*! @name DCHPRI2 - Channel n Priority Register */
+#define DMA_DCHPRI2_CHPRI_MASK                   (0xFU)
+#define DMA_DCHPRI2_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI2_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
+#define DMA_DCHPRI2_GRPPRI_MASK                  (0x30U)
+#define DMA_DCHPRI2_GRPPRI_SHIFT                 (4U)
+#define DMA_DCHPRI2_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)
+#define DMA_DCHPRI2_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI2_DPA_SHIFT                    (6U)
+#define DMA_DCHPRI2_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
+#define DMA_DCHPRI2_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI2_ECP_SHIFT                    (7U)
+#define DMA_DCHPRI2_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
+
+/*! @name DCHPRI1 - Channel n Priority Register */
+#define DMA_DCHPRI1_CHPRI_MASK                   (0xFU)
+#define DMA_DCHPRI1_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI1_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
+#define DMA_DCHPRI1_GRPPRI_MASK                  (0x30U)
+#define DMA_DCHPRI1_GRPPRI_SHIFT                 (4U)
+#define DMA_DCHPRI1_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)
+#define DMA_DCHPRI1_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI1_DPA_SHIFT                    (6U)
+#define DMA_DCHPRI1_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
+#define DMA_DCHPRI1_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI1_ECP_SHIFT                    (7U)
+#define DMA_DCHPRI1_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
+
+/*! @name DCHPRI0 - Channel n Priority Register */
+#define DMA_DCHPRI0_CHPRI_MASK                   (0xFU)
+#define DMA_DCHPRI0_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI0_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
+#define DMA_DCHPRI0_GRPPRI_MASK                  (0x30U)
+#define DMA_DCHPRI0_GRPPRI_SHIFT                 (4U)
+#define DMA_DCHPRI0_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)
+#define DMA_DCHPRI0_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI0_DPA_SHIFT                    (6U)
+#define DMA_DCHPRI0_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
+#define DMA_DCHPRI0_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI0_ECP_SHIFT                    (7U)
+#define DMA_DCHPRI0_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
+
+/*! @name DCHPRI7 - Channel n Priority Register */
+#define DMA_DCHPRI7_CHPRI_MASK                   (0xFU)
+#define DMA_DCHPRI7_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI7_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
+#define DMA_DCHPRI7_GRPPRI_MASK                  (0x30U)
+#define DMA_DCHPRI7_GRPPRI_SHIFT                 (4U)
+#define DMA_DCHPRI7_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)
+#define DMA_DCHPRI7_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI7_DPA_SHIFT                    (6U)
+#define DMA_DCHPRI7_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
+#define DMA_DCHPRI7_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI7_ECP_SHIFT                    (7U)
+#define DMA_DCHPRI7_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
+
+/*! @name DCHPRI6 - Channel n Priority Register */
+#define DMA_DCHPRI6_CHPRI_MASK                   (0xFU)
+#define DMA_DCHPRI6_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI6_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
+#define DMA_DCHPRI6_GRPPRI_MASK                  (0x30U)
+#define DMA_DCHPRI6_GRPPRI_SHIFT                 (4U)
+#define DMA_DCHPRI6_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)
+#define DMA_DCHPRI6_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI6_DPA_SHIFT                    (6U)
+#define DMA_DCHPRI6_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
+#define DMA_DCHPRI6_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI6_ECP_SHIFT                    (7U)
+#define DMA_DCHPRI6_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
+
+/*! @name DCHPRI5 - Channel n Priority Register */
+#define DMA_DCHPRI5_CHPRI_MASK                   (0xFU)
+#define DMA_DCHPRI5_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI5_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
+#define DMA_DCHPRI5_GRPPRI_MASK                  (0x30U)
+#define DMA_DCHPRI5_GRPPRI_SHIFT                 (4U)
+#define DMA_DCHPRI5_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)
+#define DMA_DCHPRI5_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI5_DPA_SHIFT                    (6U)
+#define DMA_DCHPRI5_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
+#define DMA_DCHPRI5_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI5_ECP_SHIFT                    (7U)
+#define DMA_DCHPRI5_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
+
+/*! @name DCHPRI4 - Channel n Priority Register */
+#define DMA_DCHPRI4_CHPRI_MASK                   (0xFU)
+#define DMA_DCHPRI4_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI4_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
+#define DMA_DCHPRI4_GRPPRI_MASK                  (0x30U)
+#define DMA_DCHPRI4_GRPPRI_SHIFT                 (4U)
+#define DMA_DCHPRI4_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)
+#define DMA_DCHPRI4_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI4_DPA_SHIFT                    (6U)
+#define DMA_DCHPRI4_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
+#define DMA_DCHPRI4_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI4_ECP_SHIFT                    (7U)
+#define DMA_DCHPRI4_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
+
+/*! @name DCHPRI11 - Channel n Priority Register */
+#define DMA_DCHPRI11_CHPRI_MASK                  (0xFU)
+#define DMA_DCHPRI11_CHPRI_SHIFT                 (0U)
+#define DMA_DCHPRI11_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
+#define DMA_DCHPRI11_GRPPRI_MASK                 (0x30U)
+#define DMA_DCHPRI11_GRPPRI_SHIFT                (4U)
+#define DMA_DCHPRI11_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)
+#define DMA_DCHPRI11_DPA_MASK                    (0x40U)
+#define DMA_DCHPRI11_DPA_SHIFT                   (6U)
+#define DMA_DCHPRI11_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
+#define DMA_DCHPRI11_ECP_MASK                    (0x80U)
+#define DMA_DCHPRI11_ECP_SHIFT                   (7U)
+#define DMA_DCHPRI11_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
+
+/*! @name DCHPRI10 - Channel n Priority Register */
+#define DMA_DCHPRI10_CHPRI_MASK                  (0xFU)
+#define DMA_DCHPRI10_CHPRI_SHIFT                 (0U)
+#define DMA_DCHPRI10_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
+#define DMA_DCHPRI10_GRPPRI_MASK                 (0x30U)
+#define DMA_DCHPRI10_GRPPRI_SHIFT                (4U)
+#define DMA_DCHPRI10_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)
+#define DMA_DCHPRI10_DPA_MASK                    (0x40U)
+#define DMA_DCHPRI10_DPA_SHIFT                   (6U)
+#define DMA_DCHPRI10_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
+#define DMA_DCHPRI10_ECP_MASK                    (0x80U)
+#define DMA_DCHPRI10_ECP_SHIFT                   (7U)
+#define DMA_DCHPRI10_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
+
+/*! @name DCHPRI9 - Channel n Priority Register */
+#define DMA_DCHPRI9_CHPRI_MASK                   (0xFU)
+#define DMA_DCHPRI9_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI9_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
+#define DMA_DCHPRI9_GRPPRI_MASK                  (0x30U)
+#define DMA_DCHPRI9_GRPPRI_SHIFT                 (4U)
+#define DMA_DCHPRI9_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)
+#define DMA_DCHPRI9_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI9_DPA_SHIFT                    (6U)
+#define DMA_DCHPRI9_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
+#define DMA_DCHPRI9_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI9_ECP_SHIFT                    (7U)
+#define DMA_DCHPRI9_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
+
+/*! @name DCHPRI8 - Channel n Priority Register */
+#define DMA_DCHPRI8_CHPRI_MASK                   (0xFU)
+#define DMA_DCHPRI8_CHPRI_SHIFT                  (0U)
+#define DMA_DCHPRI8_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
+#define DMA_DCHPRI8_GRPPRI_MASK                  (0x30U)
+#define DMA_DCHPRI8_GRPPRI_SHIFT                 (4U)
+#define DMA_DCHPRI8_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)
+#define DMA_DCHPRI8_DPA_MASK                     (0x40U)
+#define DMA_DCHPRI8_DPA_SHIFT                    (6U)
+#define DMA_DCHPRI8_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
+#define DMA_DCHPRI8_ECP_MASK                     (0x80U)
+#define DMA_DCHPRI8_ECP_SHIFT                    (7U)
+#define DMA_DCHPRI8_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
+
+/*! @name DCHPRI15 - Channel n Priority Register */
+#define DMA_DCHPRI15_CHPRI_MASK                  (0xFU)
+#define DMA_DCHPRI15_CHPRI_SHIFT                 (0U)
+#define DMA_DCHPRI15_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
+#define DMA_DCHPRI15_GRPPRI_MASK                 (0x30U)
+#define DMA_DCHPRI15_GRPPRI_SHIFT                (4U)
+#define DMA_DCHPRI15_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)
+#define DMA_DCHPRI15_DPA_MASK                    (0x40U)
+#define DMA_DCHPRI15_DPA_SHIFT                   (6U)
+#define DMA_DCHPRI15_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
+#define DMA_DCHPRI15_ECP_MASK                    (0x80U)
+#define DMA_DCHPRI15_ECP_SHIFT                   (7U)
+#define DMA_DCHPRI15_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
+
+/*! @name DCHPRI14 - Channel n Priority Register */
+#define DMA_DCHPRI14_CHPRI_MASK                  (0xFU)
+#define DMA_DCHPRI14_CHPRI_SHIFT                 (0U)
+#define DMA_DCHPRI14_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
+#define DMA_DCHPRI14_GRPPRI_MASK                 (0x30U)
+#define DMA_DCHPRI14_GRPPRI_SHIFT                (4U)
+#define DMA_DCHPRI14_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)
+#define DMA_DCHPRI14_DPA_MASK                    (0x40U)
+#define DMA_DCHPRI14_DPA_SHIFT                   (6U)
+#define DMA_DCHPRI14_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
+#define DMA_DCHPRI14_ECP_MASK                    (0x80U)
+#define DMA_DCHPRI14_ECP_SHIFT                   (7U)
+#define DMA_DCHPRI14_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
+
+/*! @name DCHPRI13 - Channel n Priority Register */
+#define DMA_DCHPRI13_CHPRI_MASK                  (0xFU)
+#define DMA_DCHPRI13_CHPRI_SHIFT                 (0U)
+#define DMA_DCHPRI13_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
+#define DMA_DCHPRI13_GRPPRI_MASK                 (0x30U)
+#define DMA_DCHPRI13_GRPPRI_SHIFT                (4U)
+#define DMA_DCHPRI13_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)
+#define DMA_DCHPRI13_DPA_MASK                    (0x40U)
+#define DMA_DCHPRI13_DPA_SHIFT                   (6U)
+#define DMA_DCHPRI13_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
+#define DMA_DCHPRI13_ECP_MASK                    (0x80U)
+#define DMA_DCHPRI13_ECP_SHIFT                   (7U)
+#define DMA_DCHPRI13_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
+
+/*! @name DCHPRI12 - Channel n Priority Register */
+#define DMA_DCHPRI12_CHPRI_MASK                  (0xFU)
+#define DMA_DCHPRI12_CHPRI_SHIFT                 (0U)
+#define DMA_DCHPRI12_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
+#define DMA_DCHPRI12_GRPPRI_MASK                 (0x30U)
+#define DMA_DCHPRI12_GRPPRI_SHIFT                (4U)
+#define DMA_DCHPRI12_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)
+#define DMA_DCHPRI12_DPA_MASK                    (0x40U)
+#define DMA_DCHPRI12_DPA_SHIFT                   (6U)
+#define DMA_DCHPRI12_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
+#define DMA_DCHPRI12_ECP_MASK                    (0x80U)
+#define DMA_DCHPRI12_ECP_SHIFT                   (7U)
+#define DMA_DCHPRI12_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
+
+/*! @name DCHPRI19 - Channel n Priority Register */
+#define DMA_DCHPRI19_CHPRI_MASK                  (0xFU)
+#define DMA_DCHPRI19_CHPRI_SHIFT                 (0U)
+#define DMA_DCHPRI19_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)
+#define DMA_DCHPRI19_GRPPRI_MASK                 (0x30U)
+#define DMA_DCHPRI19_GRPPRI_SHIFT                (4U)
+#define DMA_DCHPRI19_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)
+#define DMA_DCHPRI19_DPA_MASK                    (0x40U)
+#define DMA_DCHPRI19_DPA_SHIFT                   (6U)
+#define DMA_DCHPRI19_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)
+#define DMA_DCHPRI19_ECP_MASK                    (0x80U)
+#define DMA_DCHPRI19_ECP_SHIFT                   (7U)
+#define DMA_DCHPRI19_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)
+
+/*! @name DCHPRI18 - Channel n Priority Register */
+#define DMA_DCHPRI18_CHPRI_MASK                  (0xFU)
+#define DMA_DCHPRI18_CHPRI_SHIFT                 (0U)
+#define DMA_DCHPRI18_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)
+#define DMA_DCHPRI18_GRPPRI_MASK                 (0x30U)
+#define DMA_DCHPRI18_GRPPRI_SHIFT                (4U)
+#define DMA_DCHPRI18_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)
+#define DMA_DCHPRI18_DPA_MASK                    (0x40U)
+#define DMA_DCHPRI18_DPA_SHIFT                   (6U)
+#define DMA_DCHPRI18_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)
+#define DMA_DCHPRI18_ECP_MASK                    (0x80U)
+#define DMA_DCHPRI18_ECP_SHIFT                   (7U)
+#define DMA_DCHPRI18_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)
+
+/*! @name DCHPRI17 - Channel n Priority Register */
+#define DMA_DCHPRI17_CHPRI_MASK                  (0xFU)
+#define DMA_DCHPRI17_CHPRI_SHIFT                 (0U)
+#define DMA_DCHPRI17_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)
+#define DMA_DCHPRI17_GRPPRI_MASK                 (0x30U)
+#define DMA_DCHPRI17_GRPPRI_SHIFT                (4U)
+#define DMA_DCHPRI17_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)
+#define DMA_DCHPRI17_DPA_MASK                    (0x40U)
+#define DMA_DCHPRI17_DPA_SHIFT                   (6U)
+#define DMA_DCHPRI17_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)
+#define DMA_DCHPRI17_ECP_MASK                    (0x80U)
+#define DMA_DCHPRI17_ECP_SHIFT                   (7U)
+#define DMA_DCHPRI17_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)
+
+/*! @name DCHPRI16 - Channel n Priority Register */
+#define DMA_DCHPRI16_CHPRI_MASK                  (0xFU)
+#define DMA_DCHPRI16_CHPRI_SHIFT                 (0U)
+#define DMA_DCHPRI16_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)
+#define DMA_DCHPRI16_GRPPRI_MASK                 (0x30U)
+#define DMA_DCHPRI16_GRPPRI_SHIFT                (4U)
+#define DMA_DCHPRI16_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)
+#define DMA_DCHPRI16_DPA_MASK                    (0x40U)
+#define DMA_DCHPRI16_DPA_SHIFT                   (6U)
+#define DMA_DCHPRI16_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)
+#define DMA_DCHPRI16_ECP_MASK                    (0x80U)
+#define DMA_DCHPRI16_ECP_SHIFT                   (7U)
+#define DMA_DCHPRI16_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)
+
+/*! @name DCHPRI23 - Channel n Priority Register */
+#define DMA_DCHPRI23_CHPRI_MASK                  (0xFU)
+#define DMA_DCHPRI23_CHPRI_SHIFT                 (0U)
+#define DMA_DCHPRI23_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)
+#define DMA_DCHPRI23_GRPPRI_MASK                 (0x30U)
+#define DMA_DCHPRI23_GRPPRI_SHIFT                (4U)
+#define DMA_DCHPRI23_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)
+#define DMA_DCHPRI23_DPA_MASK                    (0x40U)
+#define DMA_DCHPRI23_DPA_SHIFT                   (6U)
+#define DMA_DCHPRI23_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)
+#define DMA_DCHPRI23_ECP_MASK                    (0x80U)
+#define DMA_DCHPRI23_ECP_SHIFT                   (7U)
+#define DMA_DCHPRI23_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)
+
+/*! @name DCHPRI22 - Channel n Priority Register */
+#define DMA_DCHPRI22_CHPRI_MASK                  (0xFU)
+#define DMA_DCHPRI22_CHPRI_SHIFT                 (0U)
+#define DMA_DCHPRI22_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)
+#define DMA_DCHPRI22_GRPPRI_MASK                 (0x30U)
+#define DMA_DCHPRI22_GRPPRI_SHIFT                (4U)
+#define DMA_DCHPRI22_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)
+#define DMA_DCHPRI22_DPA_MASK                    (0x40U)
+#define DMA_DCHPRI22_DPA_SHIFT                   (6U)
+#define DMA_DCHPRI22_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)
+#define DMA_DCHPRI22_ECP_MASK                    (0x80U)
+#define DMA_DCHPRI22_ECP_SHIFT                   (7U)
+#define DMA_DCHPRI22_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)
+
+/*! @name DCHPRI21 - Channel n Priority Register */
+#define DMA_DCHPRI21_CHPRI_MASK                  (0xFU)
+#define DMA_DCHPRI21_CHPRI_SHIFT                 (0U)
+#define DMA_DCHPRI21_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)
+#define DMA_DCHPRI21_GRPPRI_MASK                 (0x30U)
+#define DMA_DCHPRI21_GRPPRI_SHIFT                (4U)
+#define DMA_DCHPRI21_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)
+#define DMA_DCHPRI21_DPA_MASK                    (0x40U)
+#define DMA_DCHPRI21_DPA_SHIFT                   (6U)
+#define DMA_DCHPRI21_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)
+#define DMA_DCHPRI21_ECP_MASK                    (0x80U)
+#define DMA_DCHPRI21_ECP_SHIFT                   (7U)
+#define DMA_DCHPRI21_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)
+
+/*! @name DCHPRI20 - Channel n Priority Register */
+#define DMA_DCHPRI20_CHPRI_MASK                  (0xFU)
+#define DMA_DCHPRI20_CHPRI_SHIFT                 (0U)
+#define DMA_DCHPRI20_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)
+#define DMA_DCHPRI20_GRPPRI_MASK                 (0x30U)
+#define DMA_DCHPRI20_GRPPRI_SHIFT                (4U)
+#define DMA_DCHPRI20_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)
+#define DMA_DCHPRI20_DPA_MASK                    (0x40U)
+#define DMA_DCHPRI20_DPA_SHIFT                   (6U)
+#define DMA_DCHPRI20_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)
+#define DMA_DCHPRI20_ECP_MASK                    (0x80U)
+#define DMA_DCHPRI20_ECP_SHIFT                   (7U)
+#define DMA_DCHPRI20_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)
+
+/*! @name DCHPRI27 - Channel n Priority Register */
+#define DMA_DCHPRI27_CHPRI_MASK                  (0xFU)
+#define DMA_DCHPRI27_CHPRI_SHIFT                 (0U)
+#define DMA_DCHPRI27_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)
+#define DMA_DCHPRI27_GRPPRI_MASK                 (0x30U)
+#define DMA_DCHPRI27_GRPPRI_SHIFT                (4U)
+#define DMA_DCHPRI27_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)
+#define DMA_DCHPRI27_DPA_MASK                    (0x40U)
+#define DMA_DCHPRI27_DPA_SHIFT                   (6U)
+#define DMA_DCHPRI27_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)
+#define DMA_DCHPRI27_ECP_MASK                    (0x80U)
+#define DMA_DCHPRI27_ECP_SHIFT                   (7U)
+#define DMA_DCHPRI27_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)
+
+/*! @name DCHPRI26 - Channel n Priority Register */
+#define DMA_DCHPRI26_CHPRI_MASK                  (0xFU)
+#define DMA_DCHPRI26_CHPRI_SHIFT                 (0U)
+#define DMA_DCHPRI26_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)
+#define DMA_DCHPRI26_GRPPRI_MASK                 (0x30U)
+#define DMA_DCHPRI26_GRPPRI_SHIFT                (4U)
+#define DMA_DCHPRI26_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)
+#define DMA_DCHPRI26_DPA_MASK                    (0x40U)
+#define DMA_DCHPRI26_DPA_SHIFT                   (6U)
+#define DMA_DCHPRI26_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)
+#define DMA_DCHPRI26_ECP_MASK                    (0x80U)
+#define DMA_DCHPRI26_ECP_SHIFT                   (7U)
+#define DMA_DCHPRI26_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)
+
+/*! @name DCHPRI25 - Channel n Priority Register */
+#define DMA_DCHPRI25_CHPRI_MASK                  (0xFU)
+#define DMA_DCHPRI25_CHPRI_SHIFT                 (0U)
+#define DMA_DCHPRI25_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)
+#define DMA_DCHPRI25_GRPPRI_MASK                 (0x30U)
+#define DMA_DCHPRI25_GRPPRI_SHIFT                (4U)
+#define DMA_DCHPRI25_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)
+#define DMA_DCHPRI25_DPA_MASK                    (0x40U)
+#define DMA_DCHPRI25_DPA_SHIFT                   (6U)
+#define DMA_DCHPRI25_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)
+#define DMA_DCHPRI25_ECP_MASK                    (0x80U)
+#define DMA_DCHPRI25_ECP_SHIFT                   (7U)
+#define DMA_DCHPRI25_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)
+
+/*! @name DCHPRI24 - Channel n Priority Register */
+#define DMA_DCHPRI24_CHPRI_MASK                  (0xFU)
+#define DMA_DCHPRI24_CHPRI_SHIFT                 (0U)
+#define DMA_DCHPRI24_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)
+#define DMA_DCHPRI24_GRPPRI_MASK                 (0x30U)
+#define DMA_DCHPRI24_GRPPRI_SHIFT                (4U)
+#define DMA_DCHPRI24_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)
+#define DMA_DCHPRI24_DPA_MASK                    (0x40U)
+#define DMA_DCHPRI24_DPA_SHIFT                   (6U)
+#define DMA_DCHPRI24_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)
+#define DMA_DCHPRI24_ECP_MASK                    (0x80U)
+#define DMA_DCHPRI24_ECP_SHIFT                   (7U)
+#define DMA_DCHPRI24_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)
+
+/*! @name DCHPRI31 - Channel n Priority Register */
+#define DMA_DCHPRI31_CHPRI_MASK                  (0xFU)
+#define DMA_DCHPRI31_CHPRI_SHIFT                 (0U)
+#define DMA_DCHPRI31_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
+#define DMA_DCHPRI31_GRPPRI_MASK                 (0x30U)
+#define DMA_DCHPRI31_GRPPRI_SHIFT                (4U)
+#define DMA_DCHPRI31_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)
+#define DMA_DCHPRI31_DPA_MASK                    (0x40U)
+#define DMA_DCHPRI31_DPA_SHIFT                   (6U)
+#define DMA_DCHPRI31_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)
+#define DMA_DCHPRI31_ECP_MASK                    (0x80U)
+#define DMA_DCHPRI31_ECP_SHIFT                   (7U)
+#define DMA_DCHPRI31_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)
+
+/*! @name DCHPRI30 - Channel n Priority Register */
+#define DMA_DCHPRI30_CHPRI_MASK                  (0xFU)
+#define DMA_DCHPRI30_CHPRI_SHIFT                 (0U)
+#define DMA_DCHPRI30_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)
+#define DMA_DCHPRI30_GRPPRI_MASK                 (0x30U)
+#define DMA_DCHPRI30_GRPPRI_SHIFT                (4U)
+#define DMA_DCHPRI30_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)
+#define DMA_DCHPRI30_DPA_MASK                    (0x40U)
+#define DMA_DCHPRI30_DPA_SHIFT                   (6U)
+#define DMA_DCHPRI30_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)
+#define DMA_DCHPRI30_ECP_MASK                    (0x80U)
+#define DMA_DCHPRI30_ECP_SHIFT                   (7U)
+#define DMA_DCHPRI30_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)
+
+/*! @name DCHPRI29 - Channel n Priority Register */
+#define DMA_DCHPRI29_CHPRI_MASK                  (0xFU)
+#define DMA_DCHPRI29_CHPRI_SHIFT                 (0U)
+#define DMA_DCHPRI29_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)
+#define DMA_DCHPRI29_GRPPRI_MASK                 (0x30U)
+#define DMA_DCHPRI29_GRPPRI_SHIFT                (4U)
+#define DMA_DCHPRI29_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)
+#define DMA_DCHPRI29_DPA_MASK                    (0x40U)
+#define DMA_DCHPRI29_DPA_SHIFT                   (6U)
+#define DMA_DCHPRI29_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)
+#define DMA_DCHPRI29_ECP_MASK                    (0x80U)
+#define DMA_DCHPRI29_ECP_SHIFT                   (7U)
+#define DMA_DCHPRI29_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)
+
+/*! @name DCHPRI28 - Channel n Priority Register */
+#define DMA_DCHPRI28_CHPRI_MASK                  (0xFU)
+#define DMA_DCHPRI28_CHPRI_SHIFT                 (0U)
+#define DMA_DCHPRI28_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)
+#define DMA_DCHPRI28_GRPPRI_MASK                 (0x30U)
+#define DMA_DCHPRI28_GRPPRI_SHIFT                (4U)
+#define DMA_DCHPRI28_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)
+#define DMA_DCHPRI28_DPA_MASK                    (0x40U)
+#define DMA_DCHPRI28_DPA_SHIFT                   (6U)
+#define DMA_DCHPRI28_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)
+#define DMA_DCHPRI28_ECP_MASK                    (0x80U)
+#define DMA_DCHPRI28_ECP_SHIFT                   (7U)
+#define DMA_DCHPRI28_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)
+
+/*! @name SADDR - TCD Source Address */
+#define DMA_SADDR_SADDR_MASK                     (0xFFFFFFFFU)
+#define DMA_SADDR_SADDR_SHIFT                    (0U)
+#define DMA_SADDR_SADDR(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
+
+/* The count of DMA_SADDR */
+#define DMA_SADDR_COUNT                          (32U)
+
+/*! @name SOFF - TCD Signed Source Address Offset */
+#define DMA_SOFF_SOFF_MASK                       (0xFFFFU)
+#define DMA_SOFF_SOFF_SHIFT                      (0U)
+#define DMA_SOFF_SOFF(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
+
+/* The count of DMA_SOFF */
+#define DMA_SOFF_COUNT                           (32U)
+
+/*! @name ATTR - TCD Transfer Attributes */
+#define DMA_ATTR_DSIZE_MASK                      (0x7U)
+#define DMA_ATTR_DSIZE_SHIFT                     (0U)
+#define DMA_ATTR_DSIZE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
+#define DMA_ATTR_DMOD_MASK                       (0xF8U)
+#define DMA_ATTR_DMOD_SHIFT                      (3U)
+#define DMA_ATTR_DMOD(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
+#define DMA_ATTR_SSIZE_MASK                      (0x700U)
+#define DMA_ATTR_SSIZE_SHIFT                     (8U)
+#define DMA_ATTR_SSIZE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
+#define DMA_ATTR_SMOD_MASK                       (0xF800U)
+#define DMA_ATTR_SMOD_SHIFT                      (11U)
+#define DMA_ATTR_SMOD(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
+
+/* The count of DMA_ATTR */
+#define DMA_ATTR_COUNT                           (32U)
+
+/*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */
+#define DMA_NBYTES_MLNO_NBYTES_MASK              (0xFFFFFFFFU)
+#define DMA_NBYTES_MLNO_NBYTES_SHIFT             (0U)
+#define DMA_NBYTES_MLNO_NBYTES(x)                (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
+
+/* The count of DMA_NBYTES_MLNO */
+#define DMA_NBYTES_MLNO_COUNT                    (32U)
+
+/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */
+#define DMA_NBYTES_MLOFFNO_NBYTES_MASK           (0x3FFFFFFFU)
+#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT          (0U)
+#define DMA_NBYTES_MLOFFNO_NBYTES(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFNO_DMLOE_MASK            (0x40000000U)
+#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT           (30U)
+#define DMA_NBYTES_MLOFFNO_DMLOE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
+#define DMA_NBYTES_MLOFFNO_SMLOE_MASK            (0x80000000U)
+#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT           (31U)
+#define DMA_NBYTES_MLOFFNO_SMLOE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
+
+/* The count of DMA_NBYTES_MLOFFNO */
+#define DMA_NBYTES_MLOFFNO_COUNT                 (32U)
+
+/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */
+#define DMA_NBYTES_MLOFFYES_NBYTES_MASK          (0x3FFU)
+#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT         (0U)
+#define DMA_NBYTES_MLOFFYES_NBYTES(x)            (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFYES_MLOFF_MASK           (0x3FFFFC00U)
+#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT          (10U)
+#define DMA_NBYTES_MLOFFYES_MLOFF(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
+#define DMA_NBYTES_MLOFFYES_DMLOE_MASK           (0x40000000U)
+#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT          (30U)
+#define DMA_NBYTES_MLOFFYES_DMLOE(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
+#define DMA_NBYTES_MLOFFYES_SMLOE_MASK           (0x80000000U)
+#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT          (31U)
+#define DMA_NBYTES_MLOFFYES_SMLOE(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
+
+/* The count of DMA_NBYTES_MLOFFYES */
+#define DMA_NBYTES_MLOFFYES_COUNT                (32U)
+
+/*! @name SLAST - TCD Last Source Address Adjustment */
+#define DMA_SLAST_SLAST_MASK                     (0xFFFFFFFFU)
+#define DMA_SLAST_SLAST_SHIFT                    (0U)
+#define DMA_SLAST_SLAST(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
+
+/* The count of DMA_SLAST */
+#define DMA_SLAST_COUNT                          (32U)
+
+/*! @name DADDR - TCD Destination Address */
+#define DMA_DADDR_DADDR_MASK                     (0xFFFFFFFFU)
+#define DMA_DADDR_DADDR_SHIFT                    (0U)
+#define DMA_DADDR_DADDR(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
+
+/* The count of DMA_DADDR */
+#define DMA_DADDR_COUNT                          (32U)
+
+/*! @name DOFF - TCD Signed Destination Address Offset */
+#define DMA_DOFF_DOFF_MASK                       (0xFFFFU)
+#define DMA_DOFF_DOFF_SHIFT                      (0U)
+#define DMA_DOFF_DOFF(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
+
+/* The count of DMA_DOFF */
+#define DMA_DOFF_COUNT                           (32U)
+
+/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
+#define DMA_CITER_ELINKNO_CITER_MASK             (0x7FFFU)
+#define DMA_CITER_ELINKNO_CITER_SHIFT            (0U)
+#define DMA_CITER_ELINKNO_CITER(x)               (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
+#define DMA_CITER_ELINKNO_ELINK_MASK             (0x8000U)
+#define DMA_CITER_ELINKNO_ELINK_SHIFT            (15U)
+#define DMA_CITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
+
+/* The count of DMA_CITER_ELINKNO */
+#define DMA_CITER_ELINKNO_COUNT                  (32U)
+
+/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
+#define DMA_CITER_ELINKYES_CITER_MASK            (0x1FFU)
+#define DMA_CITER_ELINKYES_CITER_SHIFT           (0U)
+#define DMA_CITER_ELINKYES_CITER(x)              (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
+#define DMA_CITER_ELINKYES_LINKCH_MASK           (0x3E00U)
+#define DMA_CITER_ELINKYES_LINKCH_SHIFT          (9U)
+#define DMA_CITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
+#define DMA_CITER_ELINKYES_ELINK_MASK            (0x8000U)
+#define DMA_CITER_ELINKYES_ELINK_SHIFT           (15U)
+#define DMA_CITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
+
+/* The count of DMA_CITER_ELINKYES */
+#define DMA_CITER_ELINKYES_COUNT                 (32U)
+
+/*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
+#define DMA_DLAST_SGA_DLASTSGA_MASK              (0xFFFFFFFFU)
+#define DMA_DLAST_SGA_DLASTSGA_SHIFT             (0U)
+#define DMA_DLAST_SGA_DLASTSGA(x)                (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
+
+/* The count of DMA_DLAST_SGA */
+#define DMA_DLAST_SGA_COUNT                      (32U)
+
+/*! @name CSR - TCD Control and Status */
+#define DMA_CSR_START_MASK                       (0x1U)
+#define DMA_CSR_START_SHIFT                      (0U)
+#define DMA_CSR_START(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
+#define DMA_CSR_INTMAJOR_MASK                    (0x2U)
+#define DMA_CSR_INTMAJOR_SHIFT                   (1U)
+#define DMA_CSR_INTMAJOR(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
+#define DMA_CSR_INTHALF_MASK                     (0x4U)
+#define DMA_CSR_INTHALF_SHIFT                    (2U)
+#define DMA_CSR_INTHALF(x)                       (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
+#define DMA_CSR_DREQ_MASK                        (0x8U)
+#define DMA_CSR_DREQ_SHIFT                       (3U)
+#define DMA_CSR_DREQ(x)                          (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
+#define DMA_CSR_ESG_MASK                         (0x10U)
+#define DMA_CSR_ESG_SHIFT                        (4U)
+#define DMA_CSR_ESG(x)                           (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
+#define DMA_CSR_MAJORELINK_MASK                  (0x20U)
+#define DMA_CSR_MAJORELINK_SHIFT                 (5U)
+#define DMA_CSR_MAJORELINK(x)                    (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
+#define DMA_CSR_ACTIVE_MASK                      (0x40U)
+#define DMA_CSR_ACTIVE_SHIFT                     (6U)
+#define DMA_CSR_ACTIVE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
+#define DMA_CSR_DONE_MASK                        (0x80U)
+#define DMA_CSR_DONE_SHIFT                       (7U)
+#define DMA_CSR_DONE(x)                          (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
+#define DMA_CSR_MAJORLINKCH_MASK                 (0x1F00U)
+#define DMA_CSR_MAJORLINKCH_SHIFT                (8U)
+#define DMA_CSR_MAJORLINKCH(x)                   (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
+#define DMA_CSR_BWC_MASK                         (0xC000U)
+#define DMA_CSR_BWC_SHIFT                        (14U)
+#define DMA_CSR_BWC(x)                           (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
+
+/* The count of DMA_CSR */
+#define DMA_CSR_COUNT                            (32U)
+
+/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
+#define DMA_BITER_ELINKNO_BITER_MASK             (0x7FFFU)
+#define DMA_BITER_ELINKNO_BITER_SHIFT            (0U)
+#define DMA_BITER_ELINKNO_BITER(x)               (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
+#define DMA_BITER_ELINKNO_ELINK_MASK             (0x8000U)
+#define DMA_BITER_ELINKNO_ELINK_SHIFT            (15U)
+#define DMA_BITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
+
+/* The count of DMA_BITER_ELINKNO */
+#define DMA_BITER_ELINKNO_COUNT                  (32U)
+
+/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
+#define DMA_BITER_ELINKYES_BITER_MASK            (0x1FFU)
+#define DMA_BITER_ELINKYES_BITER_SHIFT           (0U)
+#define DMA_BITER_ELINKYES_BITER(x)              (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
+#define DMA_BITER_ELINKYES_LINKCH_MASK           (0x3E00U)
+#define DMA_BITER_ELINKYES_LINKCH_SHIFT          (9U)
+#define DMA_BITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
+#define DMA_BITER_ELINKYES_ELINK_MASK            (0x8000U)
+#define DMA_BITER_ELINKYES_ELINK_SHIFT           (15U)
+#define DMA_BITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
+
+/* The count of DMA_BITER_ELINKYES */
+#define DMA_BITER_ELINKYES_COUNT                 (32U)
+
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA base address */
+#define DMA_BASE                                 (0x40008000u)
+/** Peripheral DMA base pointer */
+#define DMA0                                     ((DMA_Type *)DMA_BASE)
+/** Array initializer of DMA peripheral base addresses */
+#define DMA_BASE_ADDRS                           { DMA_BASE }
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASE_PTRS                            { DMA0 }
+/** Interrupt vectors for the DMA peripheral type */
+#define DMA_CHN_IRQS                             { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } }
+#define DMA_ERROR_IRQS                           { DMA_Error_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
+ * @{
+ */
+
+/** DMAMUX - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CHCFG[32];                          /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
+} DMAMUX_Type;
+
+/* ----------------------------------------------------------------------------
+   -- DMAMUX Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
+ * @{
+ */
+
+/*! @name CHCFG - Channel Configuration register */
+#define DMAMUX_CHCFG_SOURCE_MASK                 (0x3FU)
+#define DMAMUX_CHCFG_SOURCE_SHIFT                (0U)
+#define DMAMUX_CHCFG_SOURCE(x)                   (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
+#define DMAMUX_CHCFG_TRIG_MASK                   (0x40U)
+#define DMAMUX_CHCFG_TRIG_SHIFT                  (6U)
+#define DMAMUX_CHCFG_TRIG(x)                     (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
+#define DMAMUX_CHCFG_ENBL_MASK                   (0x80U)
+#define DMAMUX_CHCFG_ENBL_SHIFT                  (7U)
+#define DMAMUX_CHCFG_ENBL(x)                     (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
+
+/* The count of DMAMUX_CHCFG */
+#define DMAMUX_CHCFG_COUNT                       (32U)
+
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Register_Masks */
+
+
+/* DMAMUX - Peripheral instance base addresses */
+/** Peripheral DMAMUX base address */
+#define DMAMUX_BASE                              (0x40021000u)
+/** Peripheral DMAMUX base pointer */
+#define DMAMUX                                   ((DMAMUX_Type *)DMAMUX_BASE)
+/** Array initializer of DMAMUX peripheral base addresses */
+#define DMAMUX_BASE_ADDRS                        { DMAMUX_BASE }
+/** Array initializer of DMAMUX peripheral base pointers */
+#define DMAMUX_BASE_PTRS                         { DMAMUX }
+
+/*!
+ * @}
+ */ /* end of group DMAMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- ENET Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
+ * @{
+ */
+
+/** ENET - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[4];
+  __IO uint32_t EIR;                               /**< Interrupt Event Register, offset: 0x4 */
+  __IO uint32_t EIMR;                              /**< Interrupt Mask Register, offset: 0x8 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t RDAR;                              /**< Receive Descriptor Active Register, offset: 0x10 */
+  __IO uint32_t TDAR;                              /**< Transmit Descriptor Active Register, offset: 0x14 */
+       uint8_t RESERVED_2[12];
+  __IO uint32_t ECR;                               /**< Ethernet Control Register, offset: 0x24 */
+       uint8_t RESERVED_3[24];
+  __IO uint32_t MMFR;                              /**< MII Management Frame Register, offset: 0x40 */
+  __IO uint32_t MSCR;                              /**< MII Speed Control Register, offset: 0x44 */
+       uint8_t RESERVED_4[28];
+  __IO uint32_t MIBC;                              /**< MIB Control Register, offset: 0x64 */
+       uint8_t RESERVED_5[28];
+  __IO uint32_t RCR;                               /**< Receive Control Register, offset: 0x84 */
+       uint8_t RESERVED_6[60];
+  __IO uint32_t TCR;                               /**< Transmit Control Register, offset: 0xC4 */
+       uint8_t RESERVED_7[28];
+  __IO uint32_t PALR;                              /**< Physical Address Lower Register, offset: 0xE4 */
+  __IO uint32_t PAUR;                              /**< Physical Address Upper Register, offset: 0xE8 */
+  __IO uint32_t OPD;                               /**< Opcode/Pause Duration Register, offset: 0xEC */
+       uint8_t RESERVED_8[40];
+  __IO uint32_t IAUR;                              /**< Descriptor Individual Upper Address Register, offset: 0x118 */
+  __IO uint32_t IALR;                              /**< Descriptor Individual Lower Address Register, offset: 0x11C */
+  __IO uint32_t GAUR;                              /**< Descriptor Group Upper Address Register, offset: 0x120 */
+  __IO uint32_t GALR;                              /**< Descriptor Group Lower Address Register, offset: 0x124 */
+       uint8_t RESERVED_9[28];
+  __IO uint32_t TFWR;                              /**< Transmit FIFO Watermark Register, offset: 0x144 */
+       uint8_t RESERVED_10[56];
+  __IO uint32_t RDSR;                              /**< Receive Descriptor Ring Start Register, offset: 0x180 */
+  __IO uint32_t TDSR;                              /**< Transmit Buffer Descriptor Ring Start Register, offset: 0x184 */
+  __IO uint32_t MRBR;                              /**< Maximum Receive Buffer Size Register, offset: 0x188 */
+       uint8_t RESERVED_11[4];
+  __IO uint32_t RSFL;                              /**< Receive FIFO Section Full Threshold, offset: 0x190 */
+  __IO uint32_t RSEM;                              /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
+  __IO uint32_t RAEM;                              /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
+  __IO uint32_t RAFL;                              /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
+  __IO uint32_t TSEM;                              /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
+  __IO uint32_t TAEM;                              /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
+  __IO uint32_t TAFL;                              /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
+  __IO uint32_t TIPG;                              /**< Transmit Inter-Packet Gap, offset: 0x1AC */
+  __IO uint32_t FTRL;                              /**< Frame Truncation Length, offset: 0x1B0 */
+       uint8_t RESERVED_12[12];
+  __IO uint32_t TACC;                              /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
+  __IO uint32_t RACC;                              /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
+       uint8_t RESERVED_13[56];
+       uint32_t RMON_T_DROP;                       /**< Reserved Statistic Register, offset: 0x200 */
+  __I  uint32_t RMON_T_PACKETS;                    /**< Tx Packet Count Statistic Register, offset: 0x204 */
+  __I  uint32_t RMON_T_BC_PKT;                     /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
+  __I  uint32_t RMON_T_MC_PKT;                     /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
+  __I  uint32_t RMON_T_CRC_ALIGN;                  /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
+  __I  uint32_t RMON_T_UNDERSIZE;                  /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
+  __I  uint32_t RMON_T_OVERSIZE;                   /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
+  __I  uint32_t RMON_T_FRAG;                       /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
+  __I  uint32_t RMON_T_JAB;                        /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
+  __I  uint32_t RMON_T_COL;                        /**< Tx Collision Count Statistic Register, offset: 0x224 */
+  __I  uint32_t RMON_T_P64;                        /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
+  __I  uint32_t RMON_T_P65TO127;                   /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
+  __I  uint32_t RMON_T_P128TO255;                  /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
+  __I  uint32_t RMON_T_P256TO511;                  /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
+  __I  uint32_t RMON_T_P512TO1023;                 /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
+  __I  uint32_t RMON_T_P1024TO2047;                /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
+  __I  uint32_t RMON_T_P_GTE2048;                  /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
+  __I  uint32_t RMON_T_OCTETS;                     /**< Tx Octets Statistic Register, offset: 0x244 */
+       uint32_t IEEE_T_DROP;                       /**< IEEE_T_DROP Reserved Statistic Register, offset: 0x248 */
+  __I  uint32_t IEEE_T_FRAME_OK;                   /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
+  __I  uint32_t IEEE_T_1COL;                       /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
+  __I  uint32_t IEEE_T_MCOL;                       /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
+  __I  uint32_t IEEE_T_DEF;                        /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
+  __I  uint32_t IEEE_T_LCOL;                       /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
+  __I  uint32_t IEEE_T_EXCOL;                      /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
+  __I  uint32_t IEEE_T_MACERR;                     /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
+  __I  uint32_t IEEE_T_CSERR;                      /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
+  __I  uint32_t IEEE_T_SQE;                        /**< , offset: 0x26C */
+  __I  uint32_t IEEE_T_FDXFC;                      /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
+  __I  uint32_t IEEE_T_OCTETS_OK;                  /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
+       uint8_t RESERVED_14[12];
+  __I  uint32_t RMON_R_PACKETS;                    /**< Rx Packet Count Statistic Register, offset: 0x284 */
+  __I  uint32_t RMON_R_BC_PKT;                     /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
+  __I  uint32_t RMON_R_MC_PKT;                     /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
+  __I  uint32_t RMON_R_CRC_ALIGN;                  /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
+  __I  uint32_t RMON_R_UNDERSIZE;                  /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
+  __I  uint32_t RMON_R_OVERSIZE;                   /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
+  __I  uint32_t RMON_R_FRAG;                       /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
+  __I  uint32_t RMON_R_JAB;                        /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
+       uint32_t RMON_R_RESVD_0;                    /**< Reserved Statistic Register, offset: 0x2A4 */
+  __I  uint32_t RMON_R_P64;                        /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
+  __I  uint32_t RMON_R_P65TO127;                   /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
+  __I  uint32_t RMON_R_P128TO255;                  /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
+  __I  uint32_t RMON_R_P256TO511;                  /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
+  __I  uint32_t RMON_R_P512TO1023;                 /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
+  __I  uint32_t RMON_R_P1024TO2047;                /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
+  __I  uint32_t RMON_R_P_GTE2048;                  /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
+  __I  uint32_t RMON_R_OCTETS;                     /**< Rx Octets Statistic Register, offset: 0x2C4 */
+  __I  uint32_t IEEE_R_DROP;                       /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
+  __I  uint32_t IEEE_R_FRAME_OK;                   /**< Frames Received OK Statistic Register, offset: 0x2CC */
+  __I  uint32_t IEEE_R_CRC;                        /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
+  __I  uint32_t IEEE_R_ALIGN;                      /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
+  __I  uint32_t IEEE_R_MACERR;                     /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
+  __I  uint32_t IEEE_R_FDXFC;                      /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
+  __I  uint32_t IEEE_R_OCTETS_OK;                  /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
+       uint8_t RESERVED_15[284];
+  __IO uint32_t ATCR;                              /**< Adjustable Timer Control Register, offset: 0x400 */
+  __IO uint32_t ATVR;                              /**< Timer Value Register, offset: 0x404 */
+  __IO uint32_t ATOFF;                             /**< Timer Offset Register, offset: 0x408 */
+  __IO uint32_t ATPER;                             /**< Timer Period Register, offset: 0x40C */
+  __IO uint32_t ATCOR;                             /**< Timer Correction Register, offset: 0x410 */
+  __IO uint32_t ATINC;                             /**< Time-Stamping Clock Period Register, offset: 0x414 */
+  __I  uint32_t ATSTMP;                            /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
+       uint8_t RESERVED_16[488];
+  __IO uint32_t TGSR;                              /**< Timer Global Status Register, offset: 0x604 */
+  struct {                                         /* offset: 0x608, array step: 0x8 */
+    __IO uint32_t TCSR;                              /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
+    __IO uint32_t TCCR;                              /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
+  } CHANNEL[4];
+} ENET_Type;
+
+/* ----------------------------------------------------------------------------
+   -- ENET Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Masks ENET Register Masks
+ * @{
+ */
+
+/*! @name EIR - Interrupt Event Register */
+#define ENET_EIR_TS_TIMER_MASK                   (0x8000U)
+#define ENET_EIR_TS_TIMER_SHIFT                  (15U)
+#define ENET_EIR_TS_TIMER(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
+#define ENET_EIR_TS_AVAIL_MASK                   (0x10000U)
+#define ENET_EIR_TS_AVAIL_SHIFT                  (16U)
+#define ENET_EIR_TS_AVAIL(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
+#define ENET_EIR_WAKEUP_MASK                     (0x20000U)
+#define ENET_EIR_WAKEUP_SHIFT                    (17U)
+#define ENET_EIR_WAKEUP(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
+#define ENET_EIR_PLR_MASK                        (0x40000U)
+#define ENET_EIR_PLR_SHIFT                       (18U)
+#define ENET_EIR_PLR(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
+#define ENET_EIR_UN_MASK                         (0x80000U)
+#define ENET_EIR_UN_SHIFT                        (19U)
+#define ENET_EIR_UN(x)                           (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
+#define ENET_EIR_RL_MASK                         (0x100000U)
+#define ENET_EIR_RL_SHIFT                        (20U)
+#define ENET_EIR_RL(x)                           (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
+#define ENET_EIR_LC_MASK                         (0x200000U)
+#define ENET_EIR_LC_SHIFT                        (21U)
+#define ENET_EIR_LC(x)                           (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
+#define ENET_EIR_EBERR_MASK                      (0x400000U)
+#define ENET_EIR_EBERR_SHIFT                     (22U)
+#define ENET_EIR_EBERR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
+#define ENET_EIR_MII_MASK                        (0x800000U)
+#define ENET_EIR_MII_SHIFT                       (23U)
+#define ENET_EIR_MII(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
+#define ENET_EIR_RXB_MASK                        (0x1000000U)
+#define ENET_EIR_RXB_SHIFT                       (24U)
+#define ENET_EIR_RXB(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
+#define ENET_EIR_RXF_MASK                        (0x2000000U)
+#define ENET_EIR_RXF_SHIFT                       (25U)
+#define ENET_EIR_RXF(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
+#define ENET_EIR_TXB_MASK                        (0x4000000U)
+#define ENET_EIR_TXB_SHIFT                       (26U)
+#define ENET_EIR_TXB(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
+#define ENET_EIR_TXF_MASK                        (0x8000000U)
+#define ENET_EIR_TXF_SHIFT                       (27U)
+#define ENET_EIR_TXF(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
+#define ENET_EIR_GRA_MASK                        (0x10000000U)
+#define ENET_EIR_GRA_SHIFT                       (28U)
+#define ENET_EIR_GRA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
+#define ENET_EIR_BABT_MASK                       (0x20000000U)
+#define ENET_EIR_BABT_SHIFT                      (29U)
+#define ENET_EIR_BABT(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
+#define ENET_EIR_BABR_MASK                       (0x40000000U)
+#define ENET_EIR_BABR_SHIFT                      (30U)
+#define ENET_EIR_BABR(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
+
+/*! @name EIMR - Interrupt Mask Register */
+#define ENET_EIMR_TS_TIMER_MASK                  (0x8000U)
+#define ENET_EIMR_TS_TIMER_SHIFT                 (15U)
+#define ENET_EIMR_TS_TIMER(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
+#define ENET_EIMR_TS_AVAIL_MASK                  (0x10000U)
+#define ENET_EIMR_TS_AVAIL_SHIFT                 (16U)
+#define ENET_EIMR_TS_AVAIL(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
+#define ENET_EIMR_WAKEUP_MASK                    (0x20000U)
+#define ENET_EIMR_WAKEUP_SHIFT                   (17U)
+#define ENET_EIMR_WAKEUP(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
+#define ENET_EIMR_PLR_MASK                       (0x40000U)
+#define ENET_EIMR_PLR_SHIFT                      (18U)
+#define ENET_EIMR_PLR(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
+#define ENET_EIMR_UN_MASK                        (0x80000U)
+#define ENET_EIMR_UN_SHIFT                       (19U)
+#define ENET_EIMR_UN(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
+#define ENET_EIMR_RL_MASK                        (0x100000U)
+#define ENET_EIMR_RL_SHIFT                       (20U)
+#define ENET_EIMR_RL(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
+#define ENET_EIMR_LC_MASK                        (0x200000U)
+#define ENET_EIMR_LC_SHIFT                       (21U)
+#define ENET_EIMR_LC(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
+#define ENET_EIMR_EBERR_MASK                     (0x400000U)
+#define ENET_EIMR_EBERR_SHIFT                    (22U)
+#define ENET_EIMR_EBERR(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
+#define ENET_EIMR_MII_MASK                       (0x800000U)
+#define ENET_EIMR_MII_SHIFT                      (23U)
+#define ENET_EIMR_MII(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
+#define ENET_EIMR_RXB_MASK                       (0x1000000U)
+#define ENET_EIMR_RXB_SHIFT                      (24U)
+#define ENET_EIMR_RXB(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
+#define ENET_EIMR_RXF_MASK                       (0x2000000U)
+#define ENET_EIMR_RXF_SHIFT                      (25U)
+#define ENET_EIMR_RXF(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
+#define ENET_EIMR_TXB_MASK                       (0x4000000U)
+#define ENET_EIMR_TXB_SHIFT                      (26U)
+#define ENET_EIMR_TXB(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
+#define ENET_EIMR_TXF_MASK                       (0x8000000U)
+#define ENET_EIMR_TXF_SHIFT                      (27U)
+#define ENET_EIMR_TXF(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
+#define ENET_EIMR_GRA_MASK                       (0x10000000U)
+#define ENET_EIMR_GRA_SHIFT                      (28U)
+#define ENET_EIMR_GRA(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
+#define ENET_EIMR_BABT_MASK                      (0x20000000U)
+#define ENET_EIMR_BABT_SHIFT                     (29U)
+#define ENET_EIMR_BABT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
+#define ENET_EIMR_BABR_MASK                      (0x40000000U)
+#define ENET_EIMR_BABR_SHIFT                     (30U)
+#define ENET_EIMR_BABR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
+
+/*! @name RDAR - Receive Descriptor Active Register */
+#define ENET_RDAR_RDAR_MASK                      (0x1000000U)
+#define ENET_RDAR_RDAR_SHIFT                     (24U)
+#define ENET_RDAR_RDAR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
+
+/*! @name TDAR - Transmit Descriptor Active Register */
+#define ENET_TDAR_TDAR_MASK                      (0x1000000U)
+#define ENET_TDAR_TDAR_SHIFT                     (24U)
+#define ENET_TDAR_TDAR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
+
+/*! @name ECR - Ethernet Control Register */
+#define ENET_ECR_RESET_MASK                      (0x1U)
+#define ENET_ECR_RESET_SHIFT                     (0U)
+#define ENET_ECR_RESET(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
+#define ENET_ECR_ETHEREN_MASK                    (0x2U)
+#define ENET_ECR_ETHEREN_SHIFT                   (1U)
+#define ENET_ECR_ETHEREN(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
+#define ENET_ECR_MAGICEN_MASK                    (0x4U)
+#define ENET_ECR_MAGICEN_SHIFT                   (2U)
+#define ENET_ECR_MAGICEN(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
+#define ENET_ECR_SLEEP_MASK                      (0x8U)
+#define ENET_ECR_SLEEP_SHIFT                     (3U)
+#define ENET_ECR_SLEEP(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
+#define ENET_ECR_EN1588_MASK                     (0x10U)
+#define ENET_ECR_EN1588_SHIFT                    (4U)
+#define ENET_ECR_EN1588(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
+#define ENET_ECR_DBGEN_MASK                      (0x40U)
+#define ENET_ECR_DBGEN_SHIFT                     (6U)
+#define ENET_ECR_DBGEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
+#define ENET_ECR_STOPEN_MASK                     (0x80U)
+#define ENET_ECR_STOPEN_SHIFT                    (7U)
+#define ENET_ECR_STOPEN(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ECR_STOPEN_SHIFT)) & ENET_ECR_STOPEN_MASK)
+#define ENET_ECR_DBSWP_MASK                      (0x100U)
+#define ENET_ECR_DBSWP_SHIFT                     (8U)
+#define ENET_ECR_DBSWP(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
+
+/*! @name MMFR - MII Management Frame Register */
+#define ENET_MMFR_DATA_MASK                      (0xFFFFU)
+#define ENET_MMFR_DATA_SHIFT                     (0U)
+#define ENET_MMFR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
+#define ENET_MMFR_TA_MASK                        (0x30000U)
+#define ENET_MMFR_TA_SHIFT                       (16U)
+#define ENET_MMFR_TA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
+#define ENET_MMFR_RA_MASK                        (0x7C0000U)
+#define ENET_MMFR_RA_SHIFT                       (18U)
+#define ENET_MMFR_RA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
+#define ENET_MMFR_PA_MASK                        (0xF800000U)
+#define ENET_MMFR_PA_SHIFT                       (23U)
+#define ENET_MMFR_PA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
+#define ENET_MMFR_OP_MASK                        (0x30000000U)
+#define ENET_MMFR_OP_SHIFT                       (28U)
+#define ENET_MMFR_OP(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
+#define ENET_MMFR_ST_MASK                        (0xC0000000U)
+#define ENET_MMFR_ST_SHIFT                       (30U)
+#define ENET_MMFR_ST(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
+
+/*! @name MSCR - MII Speed Control Register */
+#define ENET_MSCR_MII_SPEED_MASK                 (0x7EU)
+#define ENET_MSCR_MII_SPEED_SHIFT                (1U)
+#define ENET_MSCR_MII_SPEED(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
+#define ENET_MSCR_DIS_PRE_MASK                   (0x80U)
+#define ENET_MSCR_DIS_PRE_SHIFT                  (7U)
+#define ENET_MSCR_DIS_PRE(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
+#define ENET_MSCR_HOLDTIME_MASK                  (0x700U)
+#define ENET_MSCR_HOLDTIME_SHIFT                 (8U)
+#define ENET_MSCR_HOLDTIME(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
+
+/*! @name MIBC - MIB Control Register */
+#define ENET_MIBC_MIB_CLEAR_MASK                 (0x20000000U)
+#define ENET_MIBC_MIB_CLEAR_SHIFT                (29U)
+#define ENET_MIBC_MIB_CLEAR(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
+#define ENET_MIBC_MIB_IDLE_MASK                  (0x40000000U)
+#define ENET_MIBC_MIB_IDLE_SHIFT                 (30U)
+#define ENET_MIBC_MIB_IDLE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
+#define ENET_MIBC_MIB_DIS_MASK                   (0x80000000U)
+#define ENET_MIBC_MIB_DIS_SHIFT                  (31U)
+#define ENET_MIBC_MIB_DIS(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
+
+/*! @name RCR - Receive Control Register */
+#define ENET_RCR_LOOP_MASK                       (0x1U)
+#define ENET_RCR_LOOP_SHIFT                      (0U)
+#define ENET_RCR_LOOP(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
+#define ENET_RCR_DRT_MASK                        (0x2U)
+#define ENET_RCR_DRT_SHIFT                       (1U)
+#define ENET_RCR_DRT(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
+#define ENET_RCR_MII_MODE_MASK                   (0x4U)
+#define ENET_RCR_MII_MODE_SHIFT                  (2U)
+#define ENET_RCR_MII_MODE(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
+#define ENET_RCR_PROM_MASK                       (0x8U)
+#define ENET_RCR_PROM_SHIFT                      (3U)
+#define ENET_RCR_PROM(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
+#define ENET_RCR_BC_REJ_MASK                     (0x10U)
+#define ENET_RCR_BC_REJ_SHIFT                    (4U)
+#define ENET_RCR_BC_REJ(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
+#define ENET_RCR_FCE_MASK                        (0x20U)
+#define ENET_RCR_FCE_SHIFT                       (5U)
+#define ENET_RCR_FCE(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
+#define ENET_RCR_RMII_MODE_MASK                  (0x100U)
+#define ENET_RCR_RMII_MODE_SHIFT                 (8U)
+#define ENET_RCR_RMII_MODE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
+#define ENET_RCR_RMII_10T_MASK                   (0x200U)
+#define ENET_RCR_RMII_10T_SHIFT                  (9U)
+#define ENET_RCR_RMII_10T(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
+#define ENET_RCR_PADEN_MASK                      (0x1000U)
+#define ENET_RCR_PADEN_SHIFT                     (12U)
+#define ENET_RCR_PADEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
+#define ENET_RCR_PAUFWD_MASK                     (0x2000U)
+#define ENET_RCR_PAUFWD_SHIFT                    (13U)
+#define ENET_RCR_PAUFWD(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
+#define ENET_RCR_CRCFWD_MASK                     (0x4000U)
+#define ENET_RCR_CRCFWD_SHIFT                    (14U)
+#define ENET_RCR_CRCFWD(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
+#define ENET_RCR_CFEN_MASK                       (0x8000U)
+#define ENET_RCR_CFEN_SHIFT                      (15U)
+#define ENET_RCR_CFEN(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
+#define ENET_RCR_MAX_FL_MASK                     (0x3FFF0000U)
+#define ENET_RCR_MAX_FL_SHIFT                    (16U)
+#define ENET_RCR_MAX_FL(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
+#define ENET_RCR_NLC_MASK                        (0x40000000U)
+#define ENET_RCR_NLC_SHIFT                       (30U)
+#define ENET_RCR_NLC(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
+#define ENET_RCR_GRS_MASK                        (0x80000000U)
+#define ENET_RCR_GRS_SHIFT                       (31U)
+#define ENET_RCR_GRS(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
+
+/*! @name TCR - Transmit Control Register */
+#define ENET_TCR_GTS_MASK                        (0x1U)
+#define ENET_TCR_GTS_SHIFT                       (0U)
+#define ENET_TCR_GTS(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
+#define ENET_TCR_FDEN_MASK                       (0x4U)
+#define ENET_TCR_FDEN_SHIFT                      (2U)
+#define ENET_TCR_FDEN(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
+#define ENET_TCR_TFC_PAUSE_MASK                  (0x8U)
+#define ENET_TCR_TFC_PAUSE_SHIFT                 (3U)
+#define ENET_TCR_TFC_PAUSE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
+#define ENET_TCR_RFC_PAUSE_MASK                  (0x10U)
+#define ENET_TCR_RFC_PAUSE_SHIFT                 (4U)
+#define ENET_TCR_RFC_PAUSE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
+#define ENET_TCR_ADDSEL_MASK                     (0xE0U)
+#define ENET_TCR_ADDSEL_SHIFT                    (5U)
+#define ENET_TCR_ADDSEL(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
+#define ENET_TCR_ADDINS_MASK                     (0x100U)
+#define ENET_TCR_ADDINS_SHIFT                    (8U)
+#define ENET_TCR_ADDINS(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
+#define ENET_TCR_CRCFWD_MASK                     (0x200U)
+#define ENET_TCR_CRCFWD_SHIFT                    (9U)
+#define ENET_TCR_CRCFWD(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
+
+/*! @name PALR - Physical Address Lower Register */
+#define ENET_PALR_PADDR1_MASK                    (0xFFFFFFFFU)
+#define ENET_PALR_PADDR1_SHIFT                   (0U)
+#define ENET_PALR_PADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
+
+/*! @name PAUR - Physical Address Upper Register */
+#define ENET_PAUR_TYPE_MASK                      (0xFFFFU)
+#define ENET_PAUR_TYPE_SHIFT                     (0U)
+#define ENET_PAUR_TYPE(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
+#define ENET_PAUR_PADDR2_MASK                    (0xFFFF0000U)
+#define ENET_PAUR_PADDR2_SHIFT                   (16U)
+#define ENET_PAUR_PADDR2(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
+
+/*! @name OPD - Opcode/Pause Duration Register */
+#define ENET_OPD_PAUSE_DUR_MASK                  (0xFFFFU)
+#define ENET_OPD_PAUSE_DUR_SHIFT                 (0U)
+#define ENET_OPD_PAUSE_DUR(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
+#define ENET_OPD_OPCODE_MASK                     (0xFFFF0000U)
+#define ENET_OPD_OPCODE_SHIFT                    (16U)
+#define ENET_OPD_OPCODE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
+
+/*! @name IAUR - Descriptor Individual Upper Address Register */
+#define ENET_IAUR_IADDR1_MASK                    (0xFFFFFFFFU)
+#define ENET_IAUR_IADDR1_SHIFT                   (0U)
+#define ENET_IAUR_IADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
+
+/*! @name IALR - Descriptor Individual Lower Address Register */
+#define ENET_IALR_IADDR2_MASK                    (0xFFFFFFFFU)
+#define ENET_IALR_IADDR2_SHIFT                   (0U)
+#define ENET_IALR_IADDR2(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
+
+/*! @name GAUR - Descriptor Group Upper Address Register */
+#define ENET_GAUR_GADDR1_MASK                    (0xFFFFFFFFU)
+#define ENET_GAUR_GADDR1_SHIFT                   (0U)
+#define ENET_GAUR_GADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
+
+/*! @name GALR - Descriptor Group Lower Address Register */
+#define ENET_GALR_GADDR2_MASK                    (0xFFFFFFFFU)
+#define ENET_GALR_GADDR2_SHIFT                   (0U)
+#define ENET_GALR_GADDR2(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
+
+/*! @name TFWR - Transmit FIFO Watermark Register */
+#define ENET_TFWR_TFWR_MASK                      (0x3FU)
+#define ENET_TFWR_TFWR_SHIFT                     (0U)
+#define ENET_TFWR_TFWR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
+#define ENET_TFWR_STRFWD_MASK                    (0x100U)
+#define ENET_TFWR_STRFWD_SHIFT                   (8U)
+#define ENET_TFWR_STRFWD(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
+
+/*! @name RDSR - Receive Descriptor Ring Start Register */
+#define ENET_RDSR_R_DES_START_MASK               (0xFFFFFFF8U)
+#define ENET_RDSR_R_DES_START_SHIFT              (3U)
+#define ENET_RDSR_R_DES_START(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
+
+/*! @name TDSR - Transmit Buffer Descriptor Ring Start Register */
+#define ENET_TDSR_X_DES_START_MASK               (0xFFFFFFF8U)
+#define ENET_TDSR_X_DES_START_SHIFT              (3U)
+#define ENET_TDSR_X_DES_START(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
+
+/*! @name MRBR - Maximum Receive Buffer Size Register */
+#define ENET_MRBR_R_BUF_SIZE_MASK                (0x7F0U)
+#define ENET_MRBR_R_BUF_SIZE_SHIFT               (4U)
+#define ENET_MRBR_R_BUF_SIZE(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)
+
+/*! @name RSFL - Receive FIFO Section Full Threshold */
+#define ENET_RSFL_RX_SECTION_FULL_MASK           (0xFFU)
+#define ENET_RSFL_RX_SECTION_FULL_SHIFT          (0U)
+#define ENET_RSFL_RX_SECTION_FULL(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)
+
+/*! @name RSEM - Receive FIFO Section Empty Threshold */
+#define ENET_RSEM_RX_SECTION_EMPTY_MASK          (0xFFU)
+#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT         (0U)
+#define ENET_RSEM_RX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
+#define ENET_RSEM_STAT_SECTION_EMPTY_MASK        (0x1F0000U)
+#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT       (16U)
+#define ENET_RSEM_STAT_SECTION_EMPTY(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
+
+/*! @name RAEM - Receive FIFO Almost Empty Threshold */
+#define ENET_RAEM_RX_ALMOST_EMPTY_MASK           (0xFFU)
+#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT          (0U)
+#define ENET_RAEM_RX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)
+
+/*! @name RAFL - Receive FIFO Almost Full Threshold */
+#define ENET_RAFL_RX_ALMOST_FULL_MASK            (0xFFU)
+#define ENET_RAFL_RX_ALMOST_FULL_SHIFT           (0U)
+#define ENET_RAFL_RX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)
+
+/*! @name TSEM - Transmit FIFO Section Empty Threshold */
+#define ENET_TSEM_TX_SECTION_EMPTY_MASK          (0xFFU)
+#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT         (0U)
+#define ENET_TSEM_TX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)
+
+/*! @name TAEM - Transmit FIFO Almost Empty Threshold */
+#define ENET_TAEM_TX_ALMOST_EMPTY_MASK           (0xFFU)
+#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT          (0U)
+#define ENET_TAEM_TX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)
+
+/*! @name TAFL - Transmit FIFO Almost Full Threshold */
+#define ENET_TAFL_TX_ALMOST_FULL_MASK            (0xFFU)
+#define ENET_TAFL_TX_ALMOST_FULL_SHIFT           (0U)
+#define ENET_TAFL_TX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)
+
+/*! @name TIPG - Transmit Inter-Packet Gap */
+#define ENET_TIPG_IPG_MASK                       (0x1FU)
+#define ENET_TIPG_IPG_SHIFT                      (0U)
+#define ENET_TIPG_IPG(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
+
+/*! @name FTRL - Frame Truncation Length */
+#define ENET_FTRL_TRUNC_FL_MASK                  (0x3FFFU)
+#define ENET_FTRL_TRUNC_FL_SHIFT                 (0U)
+#define ENET_FTRL_TRUNC_FL(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
+
+/*! @name TACC - Transmit Accelerator Function Configuration */
+#define ENET_TACC_SHIFT16_MASK                   (0x1U)
+#define ENET_TACC_SHIFT16_SHIFT                  (0U)
+#define ENET_TACC_SHIFT16(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
+#define ENET_TACC_IPCHK_MASK                     (0x8U)
+#define ENET_TACC_IPCHK_SHIFT                    (3U)
+#define ENET_TACC_IPCHK(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
+#define ENET_TACC_PROCHK_MASK                    (0x10U)
+#define ENET_TACC_PROCHK_SHIFT                   (4U)
+#define ENET_TACC_PROCHK(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
+
+/*! @name RACC - Receive Accelerator Function Configuration */
+#define ENET_RACC_PADREM_MASK                    (0x1U)
+#define ENET_RACC_PADREM_SHIFT                   (0U)
+#define ENET_RACC_PADREM(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
+#define ENET_RACC_IPDIS_MASK                     (0x2U)
+#define ENET_RACC_IPDIS_SHIFT                    (1U)
+#define ENET_RACC_IPDIS(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
+#define ENET_RACC_PRODIS_MASK                    (0x4U)
+#define ENET_RACC_PRODIS_SHIFT                   (2U)
+#define ENET_RACC_PRODIS(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
+#define ENET_RACC_LINEDIS_MASK                   (0x40U)
+#define ENET_RACC_LINEDIS_SHIFT                  (6U)
+#define ENET_RACC_LINEDIS(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
+#define ENET_RACC_SHIFT16_MASK                   (0x80U)
+#define ENET_RACC_SHIFT16_SHIFT                  (7U)
+#define ENET_RACC_SHIFT16(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
+
+/*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */
+#define ENET_RMON_T_PACKETS_TXPKTS_MASK          (0xFFFFU)
+#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT         (0U)
+#define ENET_RMON_T_PACKETS_TXPKTS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
+
+/*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */
+#define ENET_RMON_T_BC_PKT_TXPKTS_MASK           (0xFFFFU)
+#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT          (0U)
+#define ENET_RMON_T_BC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
+
+/*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */
+#define ENET_RMON_T_MC_PKT_TXPKTS_MASK           (0xFFFFU)
+#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT          (0U)
+#define ENET_RMON_T_MC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
+
+/*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK        (0xFFFFU)
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT       (0U)
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
+
+/*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */
+#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK        (0xFFFFU)
+#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT       (0U)
+#define ENET_RMON_T_UNDERSIZE_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
+
+/*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */
+#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK         (0xFFFFU)
+#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT        (0U)
+#define ENET_RMON_T_OVERSIZE_TXPKTS(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
+
+/*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
+#define ENET_RMON_T_FRAG_TXPKTS_MASK             (0xFFFFU)
+#define ENET_RMON_T_FRAG_TXPKTS_SHIFT            (0U)
+#define ENET_RMON_T_FRAG_TXPKTS(x)               (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
+
+/*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */
+#define ENET_RMON_T_JAB_TXPKTS_MASK              (0xFFFFU)
+#define ENET_RMON_T_JAB_TXPKTS_SHIFT             (0U)
+#define ENET_RMON_T_JAB_TXPKTS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
+
+/*! @name RMON_T_COL - Tx Collision Count Statistic Register */
+#define ENET_RMON_T_COL_TXPKTS_MASK              (0xFFFFU)
+#define ENET_RMON_T_COL_TXPKTS_SHIFT             (0U)
+#define ENET_RMON_T_COL_TXPKTS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
+
+/*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */
+#define ENET_RMON_T_P64_TXPKTS_MASK              (0xFFFFU)
+#define ENET_RMON_T_P64_TXPKTS_SHIFT             (0U)
+#define ENET_RMON_T_P64_TXPKTS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
+
+/*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */
+#define ENET_RMON_T_P65TO127_TXPKTS_MASK         (0xFFFFU)
+#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT        (0U)
+#define ENET_RMON_T_P65TO127_TXPKTS(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
+
+/*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */
+#define ENET_RMON_T_P128TO255_TXPKTS_MASK        (0xFFFFU)
+#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT       (0U)
+#define ENET_RMON_T_P128TO255_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
+
+/*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */
+#define ENET_RMON_T_P256TO511_TXPKTS_MASK        (0xFFFFU)
+#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT       (0U)
+#define ENET_RMON_T_P256TO511_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
+
+/*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */
+#define ENET_RMON_T_P512TO1023_TXPKTS_MASK       (0xFFFFU)
+#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT      (0U)
+#define ENET_RMON_T_P512TO1023_TXPKTS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
+
+/*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */
+#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK      (0xFFFFU)
+#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT     (0U)
+#define ENET_RMON_T_P1024TO2047_TXPKTS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
+
+/*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */
+#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK        (0xFFFFU)
+#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT       (0U)
+#define ENET_RMON_T_P_GTE2048_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
+
+/*! @name RMON_T_OCTETS - Tx Octets Statistic Register */
+#define ENET_RMON_T_OCTETS_TXOCTS_MASK           (0xFFFFFFFFU)
+#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT          (0U)
+#define ENET_RMON_T_OCTETS_TXOCTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
+
+/*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */
+#define ENET_IEEE_T_FRAME_OK_COUNT_MASK          (0xFFFFU)
+#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT         (0U)
+#define ENET_IEEE_T_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
+
+/*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */
+#define ENET_IEEE_T_1COL_COUNT_MASK              (0xFFFFU)
+#define ENET_IEEE_T_1COL_COUNT_SHIFT             (0U)
+#define ENET_IEEE_T_1COL_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
+
+/*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */
+#define ENET_IEEE_T_MCOL_COUNT_MASK              (0xFFFFU)
+#define ENET_IEEE_T_MCOL_COUNT_SHIFT             (0U)
+#define ENET_IEEE_T_MCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
+
+/*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */
+#define ENET_IEEE_T_DEF_COUNT_MASK               (0xFFFFU)
+#define ENET_IEEE_T_DEF_COUNT_SHIFT              (0U)
+#define ENET_IEEE_T_DEF_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
+
+/*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */
+#define ENET_IEEE_T_LCOL_COUNT_MASK              (0xFFFFU)
+#define ENET_IEEE_T_LCOL_COUNT_SHIFT             (0U)
+#define ENET_IEEE_T_LCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
+
+/*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */
+#define ENET_IEEE_T_EXCOL_COUNT_MASK             (0xFFFFU)
+#define ENET_IEEE_T_EXCOL_COUNT_SHIFT            (0U)
+#define ENET_IEEE_T_EXCOL_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
+
+/*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */
+#define ENET_IEEE_T_MACERR_COUNT_MASK            (0xFFFFU)
+#define ENET_IEEE_T_MACERR_COUNT_SHIFT           (0U)
+#define ENET_IEEE_T_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
+
+/*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */
+#define ENET_IEEE_T_CSERR_COUNT_MASK             (0xFFFFU)
+#define ENET_IEEE_T_CSERR_COUNT_SHIFT            (0U)
+#define ENET_IEEE_T_CSERR_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
+
+/*! @name IEEE_T_SQE -  */
+#define ENET_IEEE_T_SQE_COUNT_MASK               (0xFFFFU)
+#define ENET_IEEE_T_SQE_COUNT_SHIFT              (0U)
+#define ENET_IEEE_T_SQE_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)
+
+/*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */
+#define ENET_IEEE_T_FDXFC_COUNT_MASK             (0xFFFFU)
+#define ENET_IEEE_T_FDXFC_COUNT_SHIFT            (0U)
+#define ENET_IEEE_T_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
+
+/*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */
+#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK         (0xFFFFFFFFU)
+#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT        (0U)
+#define ENET_IEEE_T_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
+
+/*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */
+#define ENET_RMON_R_PACKETS_COUNT_MASK           (0xFFFFU)
+#define ENET_RMON_R_PACKETS_COUNT_SHIFT          (0U)
+#define ENET_RMON_R_PACKETS_COUNT(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
+
+/*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */
+#define ENET_RMON_R_BC_PKT_COUNT_MASK            (0xFFFFU)
+#define ENET_RMON_R_BC_PKT_COUNT_SHIFT           (0U)
+#define ENET_RMON_R_BC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
+
+/*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */
+#define ENET_RMON_R_MC_PKT_COUNT_MASK            (0xFFFFU)
+#define ENET_RMON_R_MC_PKT_COUNT_SHIFT           (0U)
+#define ENET_RMON_R_MC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
+
+/*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */
+#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK         (0xFFFFU)
+#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT        (0U)
+#define ENET_RMON_R_CRC_ALIGN_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
+
+/*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */
+#define ENET_RMON_R_UNDERSIZE_COUNT_MASK         (0xFFFFU)
+#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT        (0U)
+#define ENET_RMON_R_UNDERSIZE_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
+
+/*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */
+#define ENET_RMON_R_OVERSIZE_COUNT_MASK          (0xFFFFU)
+#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT         (0U)
+#define ENET_RMON_R_OVERSIZE_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
+
+/*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
+#define ENET_RMON_R_FRAG_COUNT_MASK              (0xFFFFU)
+#define ENET_RMON_R_FRAG_COUNT_SHIFT             (0U)
+#define ENET_RMON_R_FRAG_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
+
+/*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */
+#define ENET_RMON_R_JAB_COUNT_MASK               (0xFFFFU)
+#define ENET_RMON_R_JAB_COUNT_SHIFT              (0U)
+#define ENET_RMON_R_JAB_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
+
+/*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */
+#define ENET_RMON_R_P64_COUNT_MASK               (0xFFFFU)
+#define ENET_RMON_R_P64_COUNT_SHIFT              (0U)
+#define ENET_RMON_R_P64_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
+
+/*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */
+#define ENET_RMON_R_P65TO127_COUNT_MASK          (0xFFFFU)
+#define ENET_RMON_R_P65TO127_COUNT_SHIFT         (0U)
+#define ENET_RMON_R_P65TO127_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
+
+/*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */
+#define ENET_RMON_R_P128TO255_COUNT_MASK         (0xFFFFU)
+#define ENET_RMON_R_P128TO255_COUNT_SHIFT        (0U)
+#define ENET_RMON_R_P128TO255_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
+
+/*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */
+#define ENET_RMON_R_P256TO511_COUNT_MASK         (0xFFFFU)
+#define ENET_RMON_R_P256TO511_COUNT_SHIFT        (0U)
+#define ENET_RMON_R_P256TO511_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
+
+/*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */
+#define ENET_RMON_R_P512TO1023_COUNT_MASK        (0xFFFFU)
+#define ENET_RMON_R_P512TO1023_COUNT_SHIFT       (0U)
+#define ENET_RMON_R_P512TO1023_COUNT(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
+
+/*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */
+#define ENET_RMON_R_P1024TO2047_COUNT_MASK       (0xFFFFU)
+#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT      (0U)
+#define ENET_RMON_R_P1024TO2047_COUNT(x)         (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
+
+/*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */
+#define ENET_RMON_R_P_GTE2048_COUNT_MASK         (0xFFFFU)
+#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT        (0U)
+#define ENET_RMON_R_P_GTE2048_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
+
+/*! @name RMON_R_OCTETS - Rx Octets Statistic Register */
+#define ENET_RMON_R_OCTETS_COUNT_MASK            (0xFFFFFFFFU)
+#define ENET_RMON_R_OCTETS_COUNT_SHIFT           (0U)
+#define ENET_RMON_R_OCTETS_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
+
+/*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */
+#define ENET_IEEE_R_DROP_COUNT_MASK              (0xFFFFU)
+#define ENET_IEEE_R_DROP_COUNT_SHIFT             (0U)
+#define ENET_IEEE_R_DROP_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
+
+/*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */
+#define ENET_IEEE_R_FRAME_OK_COUNT_MASK          (0xFFFFU)
+#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT         (0U)
+#define ENET_IEEE_R_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
+
+/*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */
+#define ENET_IEEE_R_CRC_COUNT_MASK               (0xFFFFU)
+#define ENET_IEEE_R_CRC_COUNT_SHIFT              (0U)
+#define ENET_IEEE_R_CRC_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
+
+/*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */
+#define ENET_IEEE_R_ALIGN_COUNT_MASK             (0xFFFFU)
+#define ENET_IEEE_R_ALIGN_COUNT_SHIFT            (0U)
+#define ENET_IEEE_R_ALIGN_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
+
+/*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */
+#define ENET_IEEE_R_MACERR_COUNT_MASK            (0xFFFFU)
+#define ENET_IEEE_R_MACERR_COUNT_SHIFT           (0U)
+#define ENET_IEEE_R_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
+
+/*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */
+#define ENET_IEEE_R_FDXFC_COUNT_MASK             (0xFFFFU)
+#define ENET_IEEE_R_FDXFC_COUNT_SHIFT            (0U)
+#define ENET_IEEE_R_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
+
+/*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */
+#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK         (0xFFFFFFFFU)
+#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT        (0U)
+#define ENET_IEEE_R_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
+
+/*! @name ATCR - Adjustable Timer Control Register */
+#define ENET_ATCR_EN_MASK                        (0x1U)
+#define ENET_ATCR_EN_SHIFT                       (0U)
+#define ENET_ATCR_EN(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
+#define ENET_ATCR_OFFEN_MASK                     (0x4U)
+#define ENET_ATCR_OFFEN_SHIFT                    (2U)
+#define ENET_ATCR_OFFEN(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
+#define ENET_ATCR_OFFRST_MASK                    (0x8U)
+#define ENET_ATCR_OFFRST_SHIFT                   (3U)
+#define ENET_ATCR_OFFRST(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
+#define ENET_ATCR_PEREN_MASK                     (0x10U)
+#define ENET_ATCR_PEREN_SHIFT                    (4U)
+#define ENET_ATCR_PEREN(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
+#define ENET_ATCR_PINPER_MASK                    (0x80U)
+#define ENET_ATCR_PINPER_SHIFT                   (7U)
+#define ENET_ATCR_PINPER(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
+#define ENET_ATCR_RESTART_MASK                   (0x200U)
+#define ENET_ATCR_RESTART_SHIFT                  (9U)
+#define ENET_ATCR_RESTART(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
+#define ENET_ATCR_CAPTURE_MASK                   (0x800U)
+#define ENET_ATCR_CAPTURE_SHIFT                  (11U)
+#define ENET_ATCR_CAPTURE(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
+#define ENET_ATCR_SLAVE_MASK                     (0x2000U)
+#define ENET_ATCR_SLAVE_SHIFT                    (13U)
+#define ENET_ATCR_SLAVE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
+
+/*! @name ATVR - Timer Value Register */
+#define ENET_ATVR_ATIME_MASK                     (0xFFFFFFFFU)
+#define ENET_ATVR_ATIME_SHIFT                    (0U)
+#define ENET_ATVR_ATIME(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
+
+/*! @name ATOFF - Timer Offset Register */
+#define ENET_ATOFF_OFFSET_MASK                   (0xFFFFFFFFU)
+#define ENET_ATOFF_OFFSET_SHIFT                  (0U)
+#define ENET_ATOFF_OFFSET(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
+
+/*! @name ATPER - Timer Period Register */
+#define ENET_ATPER_PERIOD_MASK                   (0xFFFFFFFFU)
+#define ENET_ATPER_PERIOD_SHIFT                  (0U)
+#define ENET_ATPER_PERIOD(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
+
+/*! @name ATCOR - Timer Correction Register */
+#define ENET_ATCOR_COR_MASK                      (0x7FFFFFFFU)
+#define ENET_ATCOR_COR_SHIFT                     (0U)
+#define ENET_ATCOR_COR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
+
+/*! @name ATINC - Time-Stamping Clock Period Register */
+#define ENET_ATINC_INC_MASK                      (0x7FU)
+#define ENET_ATINC_INC_SHIFT                     (0U)
+#define ENET_ATINC_INC(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
+#define ENET_ATINC_INC_CORR_MASK                 (0x7F00U)
+#define ENET_ATINC_INC_CORR_SHIFT                (8U)
+#define ENET_ATINC_INC_CORR(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
+
+/*! @name ATSTMP - Timestamp of Last Transmitted Frame */
+#define ENET_ATSTMP_TIMESTAMP_MASK               (0xFFFFFFFFU)
+#define ENET_ATSTMP_TIMESTAMP_SHIFT              (0U)
+#define ENET_ATSTMP_TIMESTAMP(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
+
+/*! @name TGSR - Timer Global Status Register */
+#define ENET_TGSR_TF0_MASK                       (0x1U)
+#define ENET_TGSR_TF0_SHIFT                      (0U)
+#define ENET_TGSR_TF0(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
+#define ENET_TGSR_TF1_MASK                       (0x2U)
+#define ENET_TGSR_TF1_SHIFT                      (1U)
+#define ENET_TGSR_TF1(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
+#define ENET_TGSR_TF2_MASK                       (0x4U)
+#define ENET_TGSR_TF2_SHIFT                      (2U)
+#define ENET_TGSR_TF2(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
+#define ENET_TGSR_TF3_MASK                       (0x8U)
+#define ENET_TGSR_TF3_SHIFT                      (3U)
+#define ENET_TGSR_TF3(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
+
+/*! @name TCSR - Timer Control Status Register */
+#define ENET_TCSR_TDRE_MASK                      (0x1U)
+#define ENET_TCSR_TDRE_SHIFT                     (0U)
+#define ENET_TCSR_TDRE(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
+#define ENET_TCSR_TMODE_MASK                     (0x3CU)
+#define ENET_TCSR_TMODE_SHIFT                    (2U)
+#define ENET_TCSR_TMODE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
+#define ENET_TCSR_TIE_MASK                       (0x40U)
+#define ENET_TCSR_TIE_SHIFT                      (6U)
+#define ENET_TCSR_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
+#define ENET_TCSR_TF_MASK                        (0x80U)
+#define ENET_TCSR_TF_SHIFT                       (7U)
+#define ENET_TCSR_TF(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
+
+/* The count of ENET_TCSR */
+#define ENET_TCSR_COUNT                          (4U)
+
+/*! @name TCCR - Timer Compare Capture Register */
+#define ENET_TCCR_TCC_MASK                       (0xFFFFFFFFU)
+#define ENET_TCCR_TCC_SHIFT                      (0U)
+#define ENET_TCCR_TCC(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
+
+/* The count of ENET_TCCR */
+#define ENET_TCCR_COUNT                          (4U)
+
+
+/*!
+ * @}
+ */ /* end of group ENET_Register_Masks */
+
+
+/* ENET - Peripheral instance base addresses */
+/** Peripheral ENET base address */
+#define ENET_BASE                                (0x400C0000u)
+/** Peripheral ENET base pointer */
+#define ENET                                     ((ENET_Type *)ENET_BASE)
+/** Array initializer of ENET peripheral base addresses */
+#define ENET_BASE_ADDRS                          { ENET_BASE }
+/** Array initializer of ENET peripheral base pointers */
+#define ENET_BASE_PTRS                           { ENET }
+/** Interrupt vectors for the ENET peripheral type */
+#define ENET_Transmit_IRQS                       { ENET_Transmit_IRQn }
+#define ENET_Receive_IRQS                        { ENET_Receive_IRQn }
+#define ENET_Error_IRQS                          { ENET_Error_IRQn }
+#define ENET_1588_Timer_IRQS                     { ENET_1588_Timer_IRQn }
+/* ENET Buffer Descriptor and Buffer Address Alignment. */
+#define ENET_BUFF_ALIGNMENT                      (16U)
+
+
+/*!
+ * @}
+ */ /* end of group ENET_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- EWM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
+ * @{
+ */
+
+/** EWM - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CTRL;                               /**< Control Register, offset: 0x0 */
+  __O  uint8_t SERV;                               /**< Service Register, offset: 0x1 */
+  __IO uint8_t CMPL;                               /**< Compare Low Register, offset: 0x2 */
+  __IO uint8_t CMPH;                               /**< Compare High Register, offset: 0x3 */
+} EWM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- EWM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EWM_Register_Masks EWM Register Masks
+ * @{
+ */
+
+/*! @name CTRL - Control Register */
+#define EWM_CTRL_EWMEN_MASK                      (0x1U)
+#define EWM_CTRL_EWMEN_SHIFT                     (0U)
+#define EWM_CTRL_EWMEN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
+#define EWM_CTRL_ASSIN_MASK                      (0x2U)
+#define EWM_CTRL_ASSIN_SHIFT                     (1U)
+#define EWM_CTRL_ASSIN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
+#define EWM_CTRL_INEN_MASK                       (0x4U)
+#define EWM_CTRL_INEN_SHIFT                      (2U)
+#define EWM_CTRL_INEN(x)                         (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
+#define EWM_CTRL_INTEN_MASK                      (0x8U)
+#define EWM_CTRL_INTEN_SHIFT                     (3U)
+#define EWM_CTRL_INTEN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
+
+/*! @name SERV - Service Register */
+#define EWM_SERV_SERVICE_MASK                    (0xFFU)
+#define EWM_SERV_SERVICE_SHIFT                   (0U)
+#define EWM_SERV_SERVICE(x)                      (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
+
+/*! @name CMPL - Compare Low Register */
+#define EWM_CMPL_COMPAREL_MASK                   (0xFFU)
+#define EWM_CMPL_COMPAREL_SHIFT                  (0U)
+#define EWM_CMPL_COMPAREL(x)                     (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
+
+/*! @name CMPH - Compare High Register */
+#define EWM_CMPH_COMPAREH_MASK                   (0xFFU)
+#define EWM_CMPH_COMPAREH_SHIFT                  (0U)
+#define EWM_CMPH_COMPAREH(x)                     (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group EWM_Register_Masks */
+
+
+/* EWM - Peripheral instance base addresses */
+/** Peripheral EWM base address */
+#define EWM_BASE                                 (0x40061000u)
+/** Peripheral EWM base pointer */
+#define EWM                                      ((EWM_Type *)EWM_BASE)
+/** Array initializer of EWM peripheral base addresses */
+#define EWM_BASE_ADDRS                           { EWM_BASE }
+/** Array initializer of EWM peripheral base pointers */
+#define EWM_BASE_PTRS                            { EWM }
+/** Interrupt vectors for the EWM peripheral type */
+#define EWM_IRQS                                 { WDOG_EWM_IRQn }
+
+/*!
+ * @}
+ */ /* end of group EWM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
+ * @{
+ */
+
+/** FB - Register Layout Typedef */
+typedef struct {
+  struct {                                         /* offset: 0x0, array step: 0xC */
+    __IO uint32_t CSAR;                              /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
+    __IO uint32_t CSMR;                              /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
+    __IO uint32_t CSCR;                              /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
+  } CS[6];
+       uint8_t RESERVED_0[24];
+  __IO uint32_t CSPMCR;                            /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
+} FB_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FB_Register_Masks FB Register Masks
+ * @{
+ */
+
+/*! @name CSAR - Chip Select Address Register */
+#define FB_CSAR_BA_MASK                          (0xFFFF0000U)
+#define FB_CSAR_BA_SHIFT                         (16U)
+#define FB_CSAR_BA(x)                            (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK)
+
+/* The count of FB_CSAR */
+#define FB_CSAR_COUNT                            (6U)
+
+/*! @name CSMR - Chip Select Mask Register */
+#define FB_CSMR_V_MASK                           (0x1U)
+#define FB_CSMR_V_SHIFT                          (0U)
+#define FB_CSMR_V(x)                             (((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK)
+#define FB_CSMR_WP_MASK                          (0x100U)
+#define FB_CSMR_WP_SHIFT                         (8U)
+#define FB_CSMR_WP(x)                            (((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK)
+#define FB_CSMR_BAM_MASK                         (0xFFFF0000U)
+#define FB_CSMR_BAM_SHIFT                        (16U)
+#define FB_CSMR_BAM(x)                           (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK)
+
+/* The count of FB_CSMR */
+#define FB_CSMR_COUNT                            (6U)
+
+/*! @name CSCR - Chip Select Control Register */
+#define FB_CSCR_BSTW_MASK                        (0x8U)
+#define FB_CSCR_BSTW_SHIFT                       (3U)
+#define FB_CSCR_BSTW(x)                          (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK)
+#define FB_CSCR_BSTR_MASK                        (0x10U)
+#define FB_CSCR_BSTR_SHIFT                       (4U)
+#define FB_CSCR_BSTR(x)                          (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK)
+#define FB_CSCR_BEM_MASK                         (0x20U)
+#define FB_CSCR_BEM_SHIFT                        (5U)
+#define FB_CSCR_BEM(x)                           (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK)
+#define FB_CSCR_PS_MASK                          (0xC0U)
+#define FB_CSCR_PS_SHIFT                         (6U)
+#define FB_CSCR_PS(x)                            (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK)
+#define FB_CSCR_AA_MASK                          (0x100U)
+#define FB_CSCR_AA_SHIFT                         (8U)
+#define FB_CSCR_AA(x)                            (((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK)
+#define FB_CSCR_BLS_MASK                         (0x200U)
+#define FB_CSCR_BLS_SHIFT                        (9U)
+#define FB_CSCR_BLS(x)                           (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK)
+#define FB_CSCR_WS_MASK                          (0xFC00U)
+#define FB_CSCR_WS_SHIFT                         (10U)
+#define FB_CSCR_WS(x)                            (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK)
+#define FB_CSCR_WRAH_MASK                        (0x30000U)
+#define FB_CSCR_WRAH_SHIFT                       (16U)
+#define FB_CSCR_WRAH(x)                          (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK)
+#define FB_CSCR_RDAH_MASK                        (0xC0000U)
+#define FB_CSCR_RDAH_SHIFT                       (18U)
+#define FB_CSCR_RDAH(x)                          (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK)
+#define FB_CSCR_ASET_MASK                        (0x300000U)
+#define FB_CSCR_ASET_SHIFT                       (20U)
+#define FB_CSCR_ASET(x)                          (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK)
+#define FB_CSCR_EXTS_MASK                        (0x400000U)
+#define FB_CSCR_EXTS_SHIFT                       (22U)
+#define FB_CSCR_EXTS(x)                          (((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK)
+#define FB_CSCR_SWSEN_MASK                       (0x800000U)
+#define FB_CSCR_SWSEN_SHIFT                      (23U)
+#define FB_CSCR_SWSEN(x)                         (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK)
+#define FB_CSCR_SWS_MASK                         (0xFC000000U)
+#define FB_CSCR_SWS_SHIFT                        (26U)
+#define FB_CSCR_SWS(x)                           (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK)
+
+/* The count of FB_CSCR */
+#define FB_CSCR_COUNT                            (6U)
+
+/*! @name CSPMCR - Chip Select port Multiplexing Control Register */
+#define FB_CSPMCR_GROUP5_MASK                    (0xF000U)
+#define FB_CSPMCR_GROUP5_SHIFT                   (12U)
+#define FB_CSPMCR_GROUP5(x)                      (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK)
+#define FB_CSPMCR_GROUP4_MASK                    (0xF0000U)
+#define FB_CSPMCR_GROUP4_SHIFT                   (16U)
+#define FB_CSPMCR_GROUP4(x)                      (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK)
+#define FB_CSPMCR_GROUP3_MASK                    (0xF00000U)
+#define FB_CSPMCR_GROUP3_SHIFT                   (20U)
+#define FB_CSPMCR_GROUP3(x)                      (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK)
+#define FB_CSPMCR_GROUP2_MASK                    (0xF000000U)
+#define FB_CSPMCR_GROUP2_SHIFT                   (24U)
+#define FB_CSPMCR_GROUP2(x)                      (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK)
+#define FB_CSPMCR_GROUP1_MASK                    (0xF0000000U)
+#define FB_CSPMCR_GROUP1_SHIFT                   (28U)
+#define FB_CSPMCR_GROUP1(x)                      (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group FB_Register_Masks */
+
+
+/* FB - Peripheral instance base addresses */
+/** Peripheral FB base address */
+#define FB_BASE                                  (0x4000C000u)
+/** Peripheral FB base pointer */
+#define FB                                       ((FB_Type *)FB_BASE)
+/** Array initializer of FB peripheral base addresses */
+#define FB_BASE_ADDRS                            { FB_BASE }
+/** Array initializer of FB peripheral base pointers */
+#define FB_BASE_PTRS                             { FB }
+
+/*!
+ * @}
+ */ /* end of group FB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
+ * @{
+ */
+
+/** FMC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PFAPR;                             /**< Flash Access Protection Register, offset: 0x0 */
+  __IO uint32_t PFB01CR;                           /**< Flash Bank 0-1 Control Register, offset: 0x4 */
+  __IO uint32_t PFB23CR;                           /**< Flash Bank 2-3 Control Register, offset: 0x8 */
+       uint8_t RESERVED_0[244];
+  __IO uint32_t TAGVDW0S[4];                       /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
+  __IO uint32_t TAGVDW1S[4];                       /**< Cache Tag Storage, array offset: 0x110, array step: 0x4 */
+  __IO uint32_t TAGVDW2S[4];                       /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
+  __IO uint32_t TAGVDW3S[4];                       /**< Cache Tag Storage, array offset: 0x130, array step: 0x4 */
+       uint8_t RESERVED_1[192];
+  struct {                                         /* offset: 0x200, array step: index*0x40, index2*0x10 */
+    __IO uint32_t DATA_UM;                           /**< Cache Data Storage (uppermost word), array offset: 0x200, array step: index*0x40, index2*0x10 */
+    __IO uint32_t DATA_MU;                           /**< Cache Data Storage (mid-upper word), array offset: 0x204, array step: index*0x40, index2*0x10 */
+    __IO uint32_t DATA_ML;                           /**< Cache Data Storage (mid-lower word), array offset: 0x208, array step: index*0x40, index2*0x10 */
+    __IO uint32_t DATA_LM;                           /**< Cache Data Storage (lowermost word), array offset: 0x20C, array step: index*0x40, index2*0x10 */
+  } SET[4][4];
+} FMC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Masks FMC Register Masks
+ * @{
+ */
+
+/*! @name PFAPR - Flash Access Protection Register */
+#define FMC_PFAPR_M0AP_MASK                      (0x3U)
+#define FMC_PFAPR_M0AP_SHIFT                     (0U)
+#define FMC_PFAPR_M0AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)
+#define FMC_PFAPR_M1AP_MASK                      (0xCU)
+#define FMC_PFAPR_M1AP_SHIFT                     (2U)
+#define FMC_PFAPR_M1AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)
+#define FMC_PFAPR_M2AP_MASK                      (0x30U)
+#define FMC_PFAPR_M2AP_SHIFT                     (4U)
+#define FMC_PFAPR_M2AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)
+#define FMC_PFAPR_M3AP_MASK                      (0xC0U)
+#define FMC_PFAPR_M3AP_SHIFT                     (6U)
+#define FMC_PFAPR_M3AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)
+#define FMC_PFAPR_M4AP_MASK                      (0x300U)
+#define FMC_PFAPR_M4AP_SHIFT                     (8U)
+#define FMC_PFAPR_M4AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK)
+#define FMC_PFAPR_M5AP_MASK                      (0xC00U)
+#define FMC_PFAPR_M5AP_SHIFT                     (10U)
+#define FMC_PFAPR_M5AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK)
+#define FMC_PFAPR_M6AP_MASK                      (0x3000U)
+#define FMC_PFAPR_M6AP_SHIFT                     (12U)
+#define FMC_PFAPR_M6AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK)
+#define FMC_PFAPR_M7AP_MASK                      (0xC000U)
+#define FMC_PFAPR_M7AP_SHIFT                     (14U)
+#define FMC_PFAPR_M7AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK)
+#define FMC_PFAPR_M0PFD_MASK                     (0x10000U)
+#define FMC_PFAPR_M0PFD_SHIFT                    (16U)
+#define FMC_PFAPR_M0PFD(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)
+#define FMC_PFAPR_M1PFD_MASK                     (0x20000U)
+#define FMC_PFAPR_M1PFD_SHIFT                    (17U)
+#define FMC_PFAPR_M1PFD(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)
+#define FMC_PFAPR_M2PFD_MASK                     (0x40000U)
+#define FMC_PFAPR_M2PFD_SHIFT                    (18U)
+#define FMC_PFAPR_M2PFD(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)
+#define FMC_PFAPR_M3PFD_MASK                     (0x80000U)
+#define FMC_PFAPR_M3PFD_SHIFT                    (19U)
+#define FMC_PFAPR_M3PFD(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)
+#define FMC_PFAPR_M4PFD_MASK                     (0x100000U)
+#define FMC_PFAPR_M4PFD_SHIFT                    (20U)
+#define FMC_PFAPR_M4PFD(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK)
+#define FMC_PFAPR_M5PFD_MASK                     (0x200000U)
+#define FMC_PFAPR_M5PFD_SHIFT                    (21U)
+#define FMC_PFAPR_M5PFD(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5PFD_SHIFT)) & FMC_PFAPR_M5PFD_MASK)
+#define FMC_PFAPR_M6PFD_MASK                     (0x400000U)
+#define FMC_PFAPR_M6PFD_SHIFT                    (22U)
+#define FMC_PFAPR_M6PFD(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6PFD_SHIFT)) & FMC_PFAPR_M6PFD_MASK)
+#define FMC_PFAPR_M7PFD_MASK                     (0x800000U)
+#define FMC_PFAPR_M7PFD_SHIFT                    (23U)
+#define FMC_PFAPR_M7PFD(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7PFD_SHIFT)) & FMC_PFAPR_M7PFD_MASK)
+
+/*! @name PFB01CR - Flash Bank 0-1 Control Register */
+#define FMC_PFB01CR_RFU_MASK                     (0x1U)
+#define FMC_PFB01CR_RFU_SHIFT                    (0U)
+#define FMC_PFB01CR_RFU(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_RFU_SHIFT)) & FMC_PFB01CR_RFU_MASK)
+#define FMC_PFB01CR_B0IPE_MASK                   (0x2U)
+#define FMC_PFB01CR_B0IPE_SHIFT                  (1U)
+#define FMC_PFB01CR_B0IPE(x)                     (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0IPE_SHIFT)) & FMC_PFB01CR_B0IPE_MASK)
+#define FMC_PFB01CR_B0DPE_MASK                   (0x4U)
+#define FMC_PFB01CR_B0DPE_SHIFT                  (2U)
+#define FMC_PFB01CR_B0DPE(x)                     (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0DPE_SHIFT)) & FMC_PFB01CR_B0DPE_MASK)
+#define FMC_PFB01CR_B0ICE_MASK                   (0x8U)
+#define FMC_PFB01CR_B0ICE_SHIFT                  (3U)
+#define FMC_PFB01CR_B0ICE(x)                     (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0ICE_SHIFT)) & FMC_PFB01CR_B0ICE_MASK)
+#define FMC_PFB01CR_B0DCE_MASK                   (0x10U)
+#define FMC_PFB01CR_B0DCE_SHIFT                  (4U)
+#define FMC_PFB01CR_B0DCE(x)                     (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0DCE_SHIFT)) & FMC_PFB01CR_B0DCE_MASK)
+#define FMC_PFB01CR_CRC_MASK                     (0xE0U)
+#define FMC_PFB01CR_CRC_SHIFT                    (5U)
+#define FMC_PFB01CR_CRC(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_CRC_SHIFT)) & FMC_PFB01CR_CRC_MASK)
+#define FMC_PFB01CR_B0MW_MASK                    (0x60000U)
+#define FMC_PFB01CR_B0MW_SHIFT                   (17U)
+#define FMC_PFB01CR_B0MW(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0MW_SHIFT)) & FMC_PFB01CR_B0MW_MASK)
+#define FMC_PFB01CR_S_B_INV_MASK                 (0x80000U)
+#define FMC_PFB01CR_S_B_INV_SHIFT                (19U)
+#define FMC_PFB01CR_S_B_INV(x)                   (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_S_B_INV_SHIFT)) & FMC_PFB01CR_S_B_INV_MASK)
+#define FMC_PFB01CR_CINV_WAY_MASK                (0xF00000U)
+#define FMC_PFB01CR_CINV_WAY_SHIFT               (20U)
+#define FMC_PFB01CR_CINV_WAY(x)                  (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_CINV_WAY_SHIFT)) & FMC_PFB01CR_CINV_WAY_MASK)
+#define FMC_PFB01CR_CLCK_WAY_MASK                (0xF000000U)
+#define FMC_PFB01CR_CLCK_WAY_SHIFT               (24U)
+#define FMC_PFB01CR_CLCK_WAY(x)                  (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_CLCK_WAY_SHIFT)) & FMC_PFB01CR_CLCK_WAY_MASK)
+#define FMC_PFB01CR_B0RWSC_MASK                  (0xF0000000U)
+#define FMC_PFB01CR_B0RWSC_SHIFT                 (28U)
+#define FMC_PFB01CR_B0RWSC(x)                    (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0RWSC_SHIFT)) & FMC_PFB01CR_B0RWSC_MASK)
+
+/*! @name PFB23CR - Flash Bank 2-3 Control Register */
+#define FMC_PFB23CR_RFU_MASK                     (0x1U)
+#define FMC_PFB23CR_RFU_SHIFT                    (0U)
+#define FMC_PFB23CR_RFU(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_RFU_SHIFT)) & FMC_PFB23CR_RFU_MASK)
+#define FMC_PFB23CR_B1IPE_MASK                   (0x2U)
+#define FMC_PFB23CR_B1IPE_SHIFT                  (1U)
+#define FMC_PFB23CR_B1IPE(x)                     (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1IPE_SHIFT)) & FMC_PFB23CR_B1IPE_MASK)
+#define FMC_PFB23CR_B1DPE_MASK                   (0x4U)
+#define FMC_PFB23CR_B1DPE_SHIFT                  (2U)
+#define FMC_PFB23CR_B1DPE(x)                     (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1DPE_SHIFT)) & FMC_PFB23CR_B1DPE_MASK)
+#define FMC_PFB23CR_B1ICE_MASK                   (0x8U)
+#define FMC_PFB23CR_B1ICE_SHIFT                  (3U)
+#define FMC_PFB23CR_B1ICE(x)                     (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1ICE_SHIFT)) & FMC_PFB23CR_B1ICE_MASK)
+#define FMC_PFB23CR_B1DCE_MASK                   (0x10U)
+#define FMC_PFB23CR_B1DCE_SHIFT                  (4U)
+#define FMC_PFB23CR_B1DCE(x)                     (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1DCE_SHIFT)) & FMC_PFB23CR_B1DCE_MASK)
+#define FMC_PFB23CR_B1MW_MASK                    (0x60000U)
+#define FMC_PFB23CR_B1MW_SHIFT                   (17U)
+#define FMC_PFB23CR_B1MW(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1MW_SHIFT)) & FMC_PFB23CR_B1MW_MASK)
+#define FMC_PFB23CR_B1RWSC_MASK                  (0xF0000000U)
+#define FMC_PFB23CR_B1RWSC_SHIFT                 (28U)
+#define FMC_PFB23CR_B1RWSC(x)                    (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1RWSC_SHIFT)) & FMC_PFB23CR_B1RWSC_MASK)
+
+/*! @name TAGVDW0S - Cache Tag Storage */
+#define FMC_TAGVDW0S_valid_MASK                  (0x1U)
+#define FMC_TAGVDW0S_valid_SHIFT                 (0U)
+#define FMC_TAGVDW0S_valid(x)                    (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_valid_SHIFT)) & FMC_TAGVDW0S_valid_MASK)
+#define FMC_TAGVDW0S_tag_MASK                    (0x3FFFC0U)
+#define FMC_TAGVDW0S_tag_SHIFT                   (6U)
+#define FMC_TAGVDW0S_tag(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_tag_SHIFT)) & FMC_TAGVDW0S_tag_MASK)
+
+/* The count of FMC_TAGVDW0S */
+#define FMC_TAGVDW0S_COUNT                       (4U)
+
+/*! @name TAGVDW1S - Cache Tag Storage */
+#define FMC_TAGVDW1S_valid_MASK                  (0x1U)
+#define FMC_TAGVDW1S_valid_SHIFT                 (0U)
+#define FMC_TAGVDW1S_valid(x)                    (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_valid_SHIFT)) & FMC_TAGVDW1S_valid_MASK)
+#define FMC_TAGVDW1S_tag_MASK                    (0x3FFFC0U)
+#define FMC_TAGVDW1S_tag_SHIFT                   (6U)
+#define FMC_TAGVDW1S_tag(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_tag_SHIFT)) & FMC_TAGVDW1S_tag_MASK)
+
+/* The count of FMC_TAGVDW1S */
+#define FMC_TAGVDW1S_COUNT                       (4U)
+
+/*! @name TAGVDW2S - Cache Tag Storage */
+#define FMC_TAGVDW2S_valid_MASK                  (0x1U)
+#define FMC_TAGVDW2S_valid_SHIFT                 (0U)
+#define FMC_TAGVDW2S_valid(x)                    (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_valid_SHIFT)) & FMC_TAGVDW2S_valid_MASK)
+#define FMC_TAGVDW2S_tag_MASK                    (0x3FFFC0U)
+#define FMC_TAGVDW2S_tag_SHIFT                   (6U)
+#define FMC_TAGVDW2S_tag(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_tag_SHIFT)) & FMC_TAGVDW2S_tag_MASK)
+
+/* The count of FMC_TAGVDW2S */
+#define FMC_TAGVDW2S_COUNT                       (4U)
+
+/*! @name TAGVDW3S - Cache Tag Storage */
+#define FMC_TAGVDW3S_valid_MASK                  (0x1U)
+#define FMC_TAGVDW3S_valid_SHIFT                 (0U)
+#define FMC_TAGVDW3S_valid(x)                    (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_valid_SHIFT)) & FMC_TAGVDW3S_valid_MASK)
+#define FMC_TAGVDW3S_tag_MASK                    (0x3FFFC0U)
+#define FMC_TAGVDW3S_tag_SHIFT                   (6U)
+#define FMC_TAGVDW3S_tag(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_tag_SHIFT)) & FMC_TAGVDW3S_tag_MASK)
+
+/* The count of FMC_TAGVDW3S */
+#define FMC_TAGVDW3S_COUNT                       (4U)
+
+/*! @name DATA_UM - Cache Data Storage (uppermost word) */
+#define FMC_DATA_UM_data_MASK                    (0xFFFFFFFFU)
+#define FMC_DATA_UM_data_SHIFT                   (0U)
+#define FMC_DATA_UM_data(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_DATA_UM_data_SHIFT)) & FMC_DATA_UM_data_MASK)
+
+/* The count of FMC_DATA_UM */
+#define FMC_DATA_UM_COUNT                        (4U)
+
+/* The count of FMC_DATA_UM */
+#define FMC_DATA_UM_COUNT2                       (4U)
+
+/*! @name DATA_MU - Cache Data Storage (mid-upper word) */
+#define FMC_DATA_MU_data_MASK                    (0xFFFFFFFFU)
+#define FMC_DATA_MU_data_SHIFT                   (0U)
+#define FMC_DATA_MU_data(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_DATA_MU_data_SHIFT)) & FMC_DATA_MU_data_MASK)
+
+/* The count of FMC_DATA_MU */
+#define FMC_DATA_MU_COUNT                        (4U)
+
+/* The count of FMC_DATA_MU */
+#define FMC_DATA_MU_COUNT2                       (4U)
+
+/*! @name DATA_ML - Cache Data Storage (mid-lower word) */
+#define FMC_DATA_ML_data_MASK                    (0xFFFFFFFFU)
+#define FMC_DATA_ML_data_SHIFT                   (0U)
+#define FMC_DATA_ML_data(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_DATA_ML_data_SHIFT)) & FMC_DATA_ML_data_MASK)
+
+/* The count of FMC_DATA_ML */
+#define FMC_DATA_ML_COUNT                        (4U)
+
+/* The count of FMC_DATA_ML */
+#define FMC_DATA_ML_COUNT2                       (4U)
+
+/*! @name DATA_LM - Cache Data Storage (lowermost word) */
+#define FMC_DATA_LM_data_MASK                    (0xFFFFFFFFU)
+#define FMC_DATA_LM_data_SHIFT                   (0U)
+#define FMC_DATA_LM_data(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_DATA_LM_data_SHIFT)) & FMC_DATA_LM_data_MASK)
+
+/* The count of FMC_DATA_LM */
+#define FMC_DATA_LM_COUNT                        (4U)
+
+/* The count of FMC_DATA_LM */
+#define FMC_DATA_LM_COUNT2                       (4U)
+
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Masks */
+
+
+/* FMC - Peripheral instance base addresses */
+/** Peripheral FMC base address */
+#define FMC_BASE                                 (0x4001F000u)
+/** Peripheral FMC base pointer */
+#define FMC                                      ((FMC_Type *)FMC_BASE)
+/** Array initializer of FMC peripheral base addresses */
+#define FMC_BASE_ADDRS                           { FMC_BASE }
+/** Array initializer of FMC peripheral base pointers */
+#define FMC_BASE_PTRS                            { FMC }
+
+/*!
+ * @}
+ */ /* end of group FMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTFE Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer
+ * @{
+ */
+
+/** FTFE - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t FSTAT;                              /**< Flash Status Register, offset: 0x0 */
+  __IO uint8_t FCNFG;                              /**< Flash Configuration Register, offset: 0x1 */
+  __I  uint8_t FSEC;                               /**< Flash Security Register, offset: 0x2 */
+  __I  uint8_t FOPT;                               /**< Flash Option Register, offset: 0x3 */
+  __IO uint8_t FCCOB3;                             /**< Flash Common Command Object Registers, offset: 0x4 */
+  __IO uint8_t FCCOB2;                             /**< Flash Common Command Object Registers, offset: 0x5 */
+  __IO uint8_t FCCOB1;                             /**< Flash Common Command Object Registers, offset: 0x6 */
+  __IO uint8_t FCCOB0;                             /**< Flash Common Command Object Registers, offset: 0x7 */
+  __IO uint8_t FCCOB7;                             /**< Flash Common Command Object Registers, offset: 0x8 */
+  __IO uint8_t FCCOB6;                             /**< Flash Common Command Object Registers, offset: 0x9 */
+  __IO uint8_t FCCOB5;                             /**< Flash Common Command Object Registers, offset: 0xA */
+  __IO uint8_t FCCOB4;                             /**< Flash Common Command Object Registers, offset: 0xB */
+  __IO uint8_t FCCOBB;                             /**< Flash Common Command Object Registers, offset: 0xC */
+  __IO uint8_t FCCOBA;                             /**< Flash Common Command Object Registers, offset: 0xD */
+  __IO uint8_t FCCOB9;                             /**< Flash Common Command Object Registers, offset: 0xE */
+  __IO uint8_t FCCOB8;                             /**< Flash Common Command Object Registers, offset: 0xF */
+  __IO uint8_t FPROT3;                             /**< Program Flash Protection Registers, offset: 0x10 */
+  __IO uint8_t FPROT2;                             /**< Program Flash Protection Registers, offset: 0x11 */
+  __IO uint8_t FPROT1;                             /**< Program Flash Protection Registers, offset: 0x12 */
+  __IO uint8_t FPROT0;                             /**< Program Flash Protection Registers, offset: 0x13 */
+       uint8_t RESERVED_0[2];
+  __IO uint8_t FEPROT;                             /**< EEPROM Protection Register, offset: 0x16 */
+  __IO uint8_t FDPROT;                             /**< Data Flash Protection Register, offset: 0x17 */
+  __I  uint8_t XACCH3;                             /**< Execute-only Access Registers, offset: 0x18 */
+  __I  uint8_t XACCH2;                             /**< Execute-only Access Registers, offset: 0x19 */
+  __I  uint8_t XACCH1;                             /**< Execute-only Access Registers, offset: 0x1A */
+  __I  uint8_t XACCH0;                             /**< Execute-only Access Registers, offset: 0x1B */
+  __I  uint8_t XACCL3;                             /**< Execute-only Access Registers, offset: 0x1C */
+  __I  uint8_t XACCL2;                             /**< Execute-only Access Registers, offset: 0x1D */
+  __I  uint8_t XACCL1;                             /**< Execute-only Access Registers, offset: 0x1E */
+  __I  uint8_t XACCL0;                             /**< Execute-only Access Registers, offset: 0x1F */
+  __I  uint8_t SACCH3;                             /**< Supervisor-only Access Registers, offset: 0x20 */
+  __I  uint8_t SACCH2;                             /**< Supervisor-only Access Registers, offset: 0x21 */
+  __I  uint8_t SACCH1;                             /**< Supervisor-only Access Registers, offset: 0x22 */
+  __I  uint8_t SACCH0;                             /**< Supervisor-only Access Registers, offset: 0x23 */
+  __I  uint8_t SACCL3;                             /**< Supervisor-only Access Registers, offset: 0x24 */
+  __I  uint8_t SACCL2;                             /**< Supervisor-only Access Registers, offset: 0x25 */
+  __I  uint8_t SACCL1;                             /**< Supervisor-only Access Registers, offset: 0x26 */
+  __I  uint8_t SACCL0;                             /**< Supervisor-only Access Registers, offset: 0x27 */
+  __I  uint8_t FACSS;                              /**< Flash Access Segment Size Register, offset: 0x28 */
+       uint8_t RESERVED_1[2];
+  __I  uint8_t FACSN;                              /**< Flash Access Segment Number Register, offset: 0x2B */
+} FTFE_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FTFE Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTFE_Register_Masks FTFE Register Masks
+ * @{
+ */
+
+/*! @name FSTAT - Flash Status Register */
+#define FTFE_FSTAT_MGSTAT0_MASK                  (0x1U)
+#define FTFE_FSTAT_MGSTAT0_SHIFT                 (0U)
+#define FTFE_FSTAT_MGSTAT0(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_MGSTAT0_SHIFT)) & FTFE_FSTAT_MGSTAT0_MASK)
+#define FTFE_FSTAT_FPVIOL_MASK                   (0x10U)
+#define FTFE_FSTAT_FPVIOL_SHIFT                  (4U)
+#define FTFE_FSTAT_FPVIOL(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_FPVIOL_SHIFT)) & FTFE_FSTAT_FPVIOL_MASK)
+#define FTFE_FSTAT_ACCERR_MASK                   (0x20U)
+#define FTFE_FSTAT_ACCERR_SHIFT                  (5U)
+#define FTFE_FSTAT_ACCERR(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_ACCERR_SHIFT)) & FTFE_FSTAT_ACCERR_MASK)
+#define FTFE_FSTAT_RDCOLERR_MASK                 (0x40U)
+#define FTFE_FSTAT_RDCOLERR_SHIFT                (6U)
+#define FTFE_FSTAT_RDCOLERR(x)                   (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_RDCOLERR_SHIFT)) & FTFE_FSTAT_RDCOLERR_MASK)
+#define FTFE_FSTAT_CCIF_MASK                     (0x80U)
+#define FTFE_FSTAT_CCIF_SHIFT                    (7U)
+#define FTFE_FSTAT_CCIF(x)                       (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_CCIF_SHIFT)) & FTFE_FSTAT_CCIF_MASK)
+
+/*! @name FCNFG - Flash Configuration Register */
+#define FTFE_FCNFG_EEERDY_MASK                   (0x1U)
+#define FTFE_FCNFG_EEERDY_SHIFT                  (0U)
+#define FTFE_FCNFG_EEERDY(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_EEERDY_SHIFT)) & FTFE_FCNFG_EEERDY_MASK)
+#define FTFE_FCNFG_RAMRDY_MASK                   (0x2U)
+#define FTFE_FCNFG_RAMRDY_SHIFT                  (1U)
+#define FTFE_FCNFG_RAMRDY(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RAMRDY_SHIFT)) & FTFE_FCNFG_RAMRDY_MASK)
+#define FTFE_FCNFG_PFLSH_MASK                    (0x4U)
+#define FTFE_FCNFG_PFLSH_SHIFT                   (2U)
+#define FTFE_FCNFG_PFLSH(x)                      (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_PFLSH_SHIFT)) & FTFE_FCNFG_PFLSH_MASK)
+#define FTFE_FCNFG_SWAP_MASK                     (0x8U)
+#define FTFE_FCNFG_SWAP_SHIFT                    (3U)
+#define FTFE_FCNFG_SWAP(x)                       (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_SWAP_SHIFT)) & FTFE_FCNFG_SWAP_MASK)
+#define FTFE_FCNFG_ERSSUSP_MASK                  (0x10U)
+#define FTFE_FCNFG_ERSSUSP_SHIFT                 (4U)
+#define FTFE_FCNFG_ERSSUSP(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSSUSP_SHIFT)) & FTFE_FCNFG_ERSSUSP_MASK)
+#define FTFE_FCNFG_ERSAREQ_MASK                  (0x20U)
+#define FTFE_FCNFG_ERSAREQ_SHIFT                 (5U)
+#define FTFE_FCNFG_ERSAREQ(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSAREQ_SHIFT)) & FTFE_FCNFG_ERSAREQ_MASK)
+#define FTFE_FCNFG_RDCOLLIE_MASK                 (0x40U)
+#define FTFE_FCNFG_RDCOLLIE_SHIFT                (6U)
+#define FTFE_FCNFG_RDCOLLIE(x)                   (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RDCOLLIE_SHIFT)) & FTFE_FCNFG_RDCOLLIE_MASK)
+#define FTFE_FCNFG_CCIE_MASK                     (0x80U)
+#define FTFE_FCNFG_CCIE_SHIFT                    (7U)
+#define FTFE_FCNFG_CCIE(x)                       (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CCIE_SHIFT)) & FTFE_FCNFG_CCIE_MASK)
+
+/*! @name FSEC - Flash Security Register */
+#define FTFE_FSEC_SEC_MASK                       (0x3U)
+#define FTFE_FSEC_SEC_SHIFT                      (0U)
+#define FTFE_FSEC_SEC(x)                         (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_SEC_SHIFT)) & FTFE_FSEC_SEC_MASK)
+#define FTFE_FSEC_FSLACC_MASK                    (0xCU)
+#define FTFE_FSEC_FSLACC_SHIFT                   (2U)
+#define FTFE_FSEC_FSLACC(x)                      (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_FSLACC_SHIFT)) & FTFE_FSEC_FSLACC_MASK)
+#define FTFE_FSEC_MEEN_MASK                      (0x30U)
+#define FTFE_FSEC_MEEN_SHIFT                     (4U)
+#define FTFE_FSEC_MEEN(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_MEEN_SHIFT)) & FTFE_FSEC_MEEN_MASK)
+#define FTFE_FSEC_KEYEN_MASK                     (0xC0U)
+#define FTFE_FSEC_KEYEN_SHIFT                    (6U)
+#define FTFE_FSEC_KEYEN(x)                       (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_KEYEN_SHIFT)) & FTFE_FSEC_KEYEN_MASK)
+
+/*! @name FOPT - Flash Option Register */
+#define FTFE_FOPT_OPT_MASK                       (0xFFU)
+#define FTFE_FOPT_OPT_SHIFT                      (0U)
+#define FTFE_FOPT_OPT(x)                         (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT_OPT_SHIFT)) & FTFE_FOPT_OPT_MASK)
+
+/*! @name FCCOB3 - Flash Common Command Object Registers */
+#define FTFE_FCCOB3_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB3_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB3_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB3_CCOBn_SHIFT)) & FTFE_FCCOB3_CCOBn_MASK)
+
+/*! @name FCCOB2 - Flash Common Command Object Registers */
+#define FTFE_FCCOB2_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB2_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB2_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB2_CCOBn_SHIFT)) & FTFE_FCCOB2_CCOBn_MASK)
+
+/*! @name FCCOB1 - Flash Common Command Object Registers */
+#define FTFE_FCCOB1_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB1_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB1_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB1_CCOBn_SHIFT)) & FTFE_FCCOB1_CCOBn_MASK)
+
+/*! @name FCCOB0 - Flash Common Command Object Registers */
+#define FTFE_FCCOB0_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB0_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB0_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB0_CCOBn_SHIFT)) & FTFE_FCCOB0_CCOBn_MASK)
+
+/*! @name FCCOB7 - Flash Common Command Object Registers */
+#define FTFE_FCCOB7_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB7_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB7_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB7_CCOBn_SHIFT)) & FTFE_FCCOB7_CCOBn_MASK)
+
+/*! @name FCCOB6 - Flash Common Command Object Registers */
+#define FTFE_FCCOB6_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB6_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB6_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB6_CCOBn_SHIFT)) & FTFE_FCCOB6_CCOBn_MASK)
+
+/*! @name FCCOB5 - Flash Common Command Object Registers */
+#define FTFE_FCCOB5_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB5_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB5_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB5_CCOBn_SHIFT)) & FTFE_FCCOB5_CCOBn_MASK)
+
+/*! @name FCCOB4 - Flash Common Command Object Registers */
+#define FTFE_FCCOB4_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB4_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB4_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB4_CCOBn_SHIFT)) & FTFE_FCCOB4_CCOBn_MASK)
+
+/*! @name FCCOBB - Flash Common Command Object Registers */
+#define FTFE_FCCOBB_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOBB_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOBB_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBB_CCOBn_SHIFT)) & FTFE_FCCOBB_CCOBn_MASK)
+
+/*! @name FCCOBA - Flash Common Command Object Registers */
+#define FTFE_FCCOBA_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOBA_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOBA_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBA_CCOBn_SHIFT)) & FTFE_FCCOBA_CCOBn_MASK)
+
+/*! @name FCCOB9 - Flash Common Command Object Registers */
+#define FTFE_FCCOB9_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB9_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB9_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB9_CCOBn_SHIFT)) & FTFE_FCCOB9_CCOBn_MASK)
+
+/*! @name FCCOB8 - Flash Common Command Object Registers */
+#define FTFE_FCCOB8_CCOBn_MASK                   (0xFFU)
+#define FTFE_FCCOB8_CCOBn_SHIFT                  (0U)
+#define FTFE_FCCOB8_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB8_CCOBn_SHIFT)) & FTFE_FCCOB8_CCOBn_MASK)
+
+/*! @name FPROT3 - Program Flash Protection Registers */
+#define FTFE_FPROT3_PROT_MASK                    (0xFFU)
+#define FTFE_FPROT3_PROT_SHIFT                   (0U)
+#define FTFE_FPROT3_PROT(x)                      (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT3_PROT_SHIFT)) & FTFE_FPROT3_PROT_MASK)
+
+/*! @name FPROT2 - Program Flash Protection Registers */
+#define FTFE_FPROT2_PROT_MASK                    (0xFFU)
+#define FTFE_FPROT2_PROT_SHIFT                   (0U)
+#define FTFE_FPROT2_PROT(x)                      (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT2_PROT_SHIFT)) & FTFE_FPROT2_PROT_MASK)
+
+/*! @name FPROT1 - Program Flash Protection Registers */
+#define FTFE_FPROT1_PROT_MASK                    (0xFFU)
+#define FTFE_FPROT1_PROT_SHIFT                   (0U)
+#define FTFE_FPROT1_PROT(x)                      (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT1_PROT_SHIFT)) & FTFE_FPROT1_PROT_MASK)
+
+/*! @name FPROT0 - Program Flash Protection Registers */
+#define FTFE_FPROT0_PROT_MASK                    (0xFFU)
+#define FTFE_FPROT0_PROT_SHIFT                   (0U)
+#define FTFE_FPROT0_PROT(x)                      (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT0_PROT_SHIFT)) & FTFE_FPROT0_PROT_MASK)
+
+/*! @name FEPROT - EEPROM Protection Register */
+#define FTFE_FEPROT_EPROT_MASK                   (0xFFU)
+#define FTFE_FEPROT_EPROT_SHIFT                  (0U)
+#define FTFE_FEPROT_EPROT(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FEPROT_EPROT_SHIFT)) & FTFE_FEPROT_EPROT_MASK)
+
+/*! @name FDPROT - Data Flash Protection Register */
+#define FTFE_FDPROT_DPROT_MASK                   (0xFFU)
+#define FTFE_FDPROT_DPROT_SHIFT                  (0U)
+#define FTFE_FDPROT_DPROT(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FDPROT_DPROT_SHIFT)) & FTFE_FDPROT_DPROT_MASK)
+
+/*! @name XACCH3 - Execute-only Access Registers */
+#define FTFE_XACCH3_XA_MASK                      (0xFFU)
+#define FTFE_XACCH3_XA_SHIFT                     (0U)
+#define FTFE_XACCH3_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH3_XA_SHIFT)) & FTFE_XACCH3_XA_MASK)
+
+/*! @name XACCH2 - Execute-only Access Registers */
+#define FTFE_XACCH2_XA_MASK                      (0xFFU)
+#define FTFE_XACCH2_XA_SHIFT                     (0U)
+#define FTFE_XACCH2_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH2_XA_SHIFT)) & FTFE_XACCH2_XA_MASK)
+
+/*! @name XACCH1 - Execute-only Access Registers */
+#define FTFE_XACCH1_XA_MASK                      (0xFFU)
+#define FTFE_XACCH1_XA_SHIFT                     (0U)
+#define FTFE_XACCH1_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH1_XA_SHIFT)) & FTFE_XACCH1_XA_MASK)
+
+/*! @name XACCH0 - Execute-only Access Registers */
+#define FTFE_XACCH0_XA_MASK                      (0xFFU)
+#define FTFE_XACCH0_XA_SHIFT                     (0U)
+#define FTFE_XACCH0_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH0_XA_SHIFT)) & FTFE_XACCH0_XA_MASK)
+
+/*! @name XACCL3 - Execute-only Access Registers */
+#define FTFE_XACCL3_XA_MASK                      (0xFFU)
+#define FTFE_XACCL3_XA_SHIFT                     (0U)
+#define FTFE_XACCL3_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL3_XA_SHIFT)) & FTFE_XACCL3_XA_MASK)
+
+/*! @name XACCL2 - Execute-only Access Registers */
+#define FTFE_XACCL2_XA_MASK                      (0xFFU)
+#define FTFE_XACCL2_XA_SHIFT                     (0U)
+#define FTFE_XACCL2_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL2_XA_SHIFT)) & FTFE_XACCL2_XA_MASK)
+
+/*! @name XACCL1 - Execute-only Access Registers */
+#define FTFE_XACCL1_XA_MASK                      (0xFFU)
+#define FTFE_XACCL1_XA_SHIFT                     (0U)
+#define FTFE_XACCL1_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL1_XA_SHIFT)) & FTFE_XACCL1_XA_MASK)
+
+/*! @name XACCL0 - Execute-only Access Registers */
+#define FTFE_XACCL0_XA_MASK                      (0xFFU)
+#define FTFE_XACCL0_XA_SHIFT                     (0U)
+#define FTFE_XACCL0_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL0_XA_SHIFT)) & FTFE_XACCL0_XA_MASK)
+
+/*! @name SACCH3 - Supervisor-only Access Registers */
+#define FTFE_SACCH3_SA_MASK                      (0xFFU)
+#define FTFE_SACCH3_SA_SHIFT                     (0U)
+#define FTFE_SACCH3_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH3_SA_SHIFT)) & FTFE_SACCH3_SA_MASK)
+
+/*! @name SACCH2 - Supervisor-only Access Registers */
+#define FTFE_SACCH2_SA_MASK                      (0xFFU)
+#define FTFE_SACCH2_SA_SHIFT                     (0U)
+#define FTFE_SACCH2_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH2_SA_SHIFT)) & FTFE_SACCH2_SA_MASK)
+
+/*! @name SACCH1 - Supervisor-only Access Registers */
+#define FTFE_SACCH1_SA_MASK                      (0xFFU)
+#define FTFE_SACCH1_SA_SHIFT                     (0U)
+#define FTFE_SACCH1_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH1_SA_SHIFT)) & FTFE_SACCH1_SA_MASK)
+
+/*! @name SACCH0 - Supervisor-only Access Registers */
+#define FTFE_SACCH0_SA_MASK                      (0xFFU)
+#define FTFE_SACCH0_SA_SHIFT                     (0U)
+#define FTFE_SACCH0_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH0_SA_SHIFT)) & FTFE_SACCH0_SA_MASK)
+
+/*! @name SACCL3 - Supervisor-only Access Registers */
+#define FTFE_SACCL3_SA_MASK                      (0xFFU)
+#define FTFE_SACCL3_SA_SHIFT                     (0U)
+#define FTFE_SACCL3_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL3_SA_SHIFT)) & FTFE_SACCL3_SA_MASK)
+
+/*! @name SACCL2 - Supervisor-only Access Registers */
+#define FTFE_SACCL2_SA_MASK                      (0xFFU)
+#define FTFE_SACCL2_SA_SHIFT                     (0U)
+#define FTFE_SACCL2_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL2_SA_SHIFT)) & FTFE_SACCL2_SA_MASK)
+
+/*! @name SACCL1 - Supervisor-only Access Registers */
+#define FTFE_SACCL1_SA_MASK                      (0xFFU)
+#define FTFE_SACCL1_SA_SHIFT                     (0U)
+#define FTFE_SACCL1_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL1_SA_SHIFT)) & FTFE_SACCL1_SA_MASK)
+
+/*! @name SACCL0 - Supervisor-only Access Registers */
+#define FTFE_SACCL0_SA_MASK                      (0xFFU)
+#define FTFE_SACCL0_SA_SHIFT                     (0U)
+#define FTFE_SACCL0_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL0_SA_SHIFT)) & FTFE_SACCL0_SA_MASK)
+
+/*! @name FACSS - Flash Access Segment Size Register */
+#define FTFE_FACSS_SGSIZE_MASK                   (0xFFU)
+#define FTFE_FACSS_SGSIZE_SHIFT                  (0U)
+#define FTFE_FACSS_SGSIZE(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FACSS_SGSIZE_SHIFT)) & FTFE_FACSS_SGSIZE_MASK)
+
+/*! @name FACSN - Flash Access Segment Number Register */
+#define FTFE_FACSN_NUMSG_MASK                    (0xFFU)
+#define FTFE_FACSN_NUMSG_SHIFT                   (0U)
+#define FTFE_FACSN_NUMSG(x)                      (((uint8_t)(((uint8_t)(x)) << FTFE_FACSN_NUMSG_SHIFT)) & FTFE_FACSN_NUMSG_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group FTFE_Register_Masks */
+
+
+/* FTFE - Peripheral instance base addresses */
+/** Peripheral FTFE base address */
+#define FTFE_BASE                                (0x40020000u)
+/** Peripheral FTFE base pointer */
+#define FTFE                                     ((FTFE_Type *)FTFE_BASE)
+/** Array initializer of FTFE peripheral base addresses */
+#define FTFE_BASE_ADDRS                          { FTFE_BASE }
+/** Array initializer of FTFE peripheral base pointers */
+#define FTFE_BASE_PTRS                           { FTFE }
+/** Interrupt vectors for the FTFE peripheral type */
+#define FTFE_COMMAND_COMPLETE_IRQS               { FTFE_IRQn }
+#define FTFE_READ_COLLISION_IRQS                 { Read_Collision_IRQn }
+
+/*!
+ * @}
+ */ /* end of group FTFE_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- FTM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
+ * @{
+ */
+
+/** FTM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC;                                /**< Status And Control, offset: 0x0 */
+  __IO uint32_t CNT;                               /**< Counter, offset: 0x4 */
+  __IO uint32_t MOD;                               /**< Modulo, offset: 0x8 */
+  struct {                                         /* offset: 0xC, array step: 0x8 */
+    __IO uint32_t CnSC;                              /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
+    __IO uint32_t CnV;                               /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+  } CONTROLS[8];
+  __IO uint32_t CNTIN;                             /**< Counter Initial Value, offset: 0x4C */
+  __IO uint32_t STATUS;                            /**< Capture And Compare Status, offset: 0x50 */
+  __IO uint32_t MODE;                              /**< Features Mode Selection, offset: 0x54 */
+  __IO uint32_t SYNC;                              /**< Synchronization, offset: 0x58 */
+  __IO uint32_t OUTINIT;                           /**< Initial State For Channels Output, offset: 0x5C */
+  __IO uint32_t OUTMASK;                           /**< Output Mask, offset: 0x60 */
+  __IO uint32_t COMBINE;                           /**< Function For Linked Channels, offset: 0x64 */
+  __IO uint32_t DEADTIME;                          /**< Deadtime Insertion Control, offset: 0x68 */
+  __IO uint32_t EXTTRIG;                           /**< FTM External Trigger, offset: 0x6C */
+  __IO uint32_t POL;                               /**< Channels Polarity, offset: 0x70 */
+  __IO uint32_t FMS;                               /**< Fault Mode Status, offset: 0x74 */
+  __IO uint32_t FILTER;                            /**< Input Capture Filter Control, offset: 0x78 */
+  __IO uint32_t FLTCTRL;                           /**< Fault Control, offset: 0x7C */
+  __IO uint32_t QDCTRL;                            /**< Quadrature Decoder Control And Status, offset: 0x80 */
+  __IO uint32_t CONF;                              /**< Configuration, offset: 0x84 */
+  __IO uint32_t FLTPOL;                            /**< FTM Fault Input Polarity, offset: 0x88 */
+  __IO uint32_t SYNCONF;                           /**< Synchronization Configuration, offset: 0x8C */
+  __IO uint32_t INVCTRL;                           /**< FTM Inverting Control, offset: 0x90 */
+  __IO uint32_t SWOCTRL;                           /**< FTM Software Output Control, offset: 0x94 */
+  __IO uint32_t PWMLOAD;                           /**< FTM PWM Load, offset: 0x98 */
+} FTM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- FTM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FTM_Register_Masks FTM Register Masks
+ * @{
+ */
+
+/*! @name SC - Status And Control */
+#define FTM_SC_PS_MASK                           (0x7U)
+#define FTM_SC_PS_SHIFT                          (0U)
+#define FTM_SC_PS(x)                             (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)
+#define FTM_SC_CLKS_MASK                         (0x18U)
+#define FTM_SC_CLKS_SHIFT                        (3U)
+#define FTM_SC_CLKS(x)                           (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)
+#define FTM_SC_CPWMS_MASK                        (0x20U)
+#define FTM_SC_CPWMS_SHIFT                       (5U)
+#define FTM_SC_CPWMS(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)
+#define FTM_SC_TOIE_MASK                         (0x40U)
+#define FTM_SC_TOIE_SHIFT                        (6U)
+#define FTM_SC_TOIE(x)                           (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)
+#define FTM_SC_TOF_MASK                          (0x80U)
+#define FTM_SC_TOF_SHIFT                         (7U)
+#define FTM_SC_TOF(x)                            (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)
+
+/*! @name CNT - Counter */
+#define FTM_CNT_COUNT_MASK                       (0xFFFFU)
+#define FTM_CNT_COUNT_SHIFT                      (0U)
+#define FTM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
+
+/*! @name MOD - Modulo */
+#define FTM_MOD_MOD_MASK                         (0xFFFFU)
+#define FTM_MOD_MOD_SHIFT                        (0U)
+#define FTM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
+
+/*! @name CnSC - Channel (n) Status And Control */
+#define FTM_CnSC_DMA_MASK                        (0x1U)
+#define FTM_CnSC_DMA_SHIFT                       (0U)
+#define FTM_CnSC_DMA(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)
+#define FTM_CnSC_ELSA_MASK                       (0x4U)
+#define FTM_CnSC_ELSA_SHIFT                      (2U)
+#define FTM_CnSC_ELSA(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK)
+#define FTM_CnSC_ELSB_MASK                       (0x8U)
+#define FTM_CnSC_ELSB_SHIFT                      (3U)
+#define FTM_CnSC_ELSB(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK)
+#define FTM_CnSC_MSA_MASK                        (0x10U)
+#define FTM_CnSC_MSA_SHIFT                       (4U)
+#define FTM_CnSC_MSA(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK)
+#define FTM_CnSC_MSB_MASK                        (0x20U)
+#define FTM_CnSC_MSB_SHIFT                       (5U)
+#define FTM_CnSC_MSB(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK)
+#define FTM_CnSC_CHIE_MASK                       (0x40U)
+#define FTM_CnSC_CHIE_SHIFT                      (6U)
+#define FTM_CnSC_CHIE(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)
+#define FTM_CnSC_CHF_MASK                        (0x80U)
+#define FTM_CnSC_CHF_SHIFT                       (7U)
+#define FTM_CnSC_CHF(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)
+
+/* The count of FTM_CnSC */
+#define FTM_CnSC_COUNT                           (8U)
+
+/*! @name CnV - Channel (n) Value */
+#define FTM_CnV_VAL_MASK                         (0xFFFFU)
+#define FTM_CnV_VAL_SHIFT                        (0U)
+#define FTM_CnV_VAL(x)                           (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
+
+/* The count of FTM_CnV */
+#define FTM_CnV_COUNT                            (8U)
+
+/*! @name CNTIN - Counter Initial Value */
+#define FTM_CNTIN_INIT_MASK                      (0xFFFFU)
+#define FTM_CNTIN_INIT_SHIFT                     (0U)
+#define FTM_CNTIN_INIT(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
+
+/*! @name STATUS - Capture And Compare Status */
+#define FTM_STATUS_CH0F_MASK                     (0x1U)
+#define FTM_STATUS_CH0F_SHIFT                    (0U)
+#define FTM_STATUS_CH0F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)
+#define FTM_STATUS_CH1F_MASK                     (0x2U)
+#define FTM_STATUS_CH1F_SHIFT                    (1U)
+#define FTM_STATUS_CH1F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)
+#define FTM_STATUS_CH2F_MASK                     (0x4U)
+#define FTM_STATUS_CH2F_SHIFT                    (2U)
+#define FTM_STATUS_CH2F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)
+#define FTM_STATUS_CH3F_MASK                     (0x8U)
+#define FTM_STATUS_CH3F_SHIFT                    (3U)
+#define FTM_STATUS_CH3F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)
+#define FTM_STATUS_CH4F_MASK                     (0x10U)
+#define FTM_STATUS_CH4F_SHIFT                    (4U)
+#define FTM_STATUS_CH4F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)
+#define FTM_STATUS_CH5F_MASK                     (0x20U)
+#define FTM_STATUS_CH5F_SHIFT                    (5U)
+#define FTM_STATUS_CH5F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)
+#define FTM_STATUS_CH6F_MASK                     (0x40U)
+#define FTM_STATUS_CH6F_SHIFT                    (6U)
+#define FTM_STATUS_CH6F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)
+#define FTM_STATUS_CH7F_MASK                     (0x80U)
+#define FTM_STATUS_CH7F_SHIFT                    (7U)
+#define FTM_STATUS_CH7F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)
+
+/*! @name MODE - Features Mode Selection */
+#define FTM_MODE_FTMEN_MASK                      (0x1U)
+#define FTM_MODE_FTMEN_SHIFT                     (0U)
+#define FTM_MODE_FTMEN(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)
+#define FTM_MODE_INIT_MASK                       (0x2U)
+#define FTM_MODE_INIT_SHIFT                      (1U)
+#define FTM_MODE_INIT(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK)
+#define FTM_MODE_WPDIS_MASK                      (0x4U)
+#define FTM_MODE_WPDIS_SHIFT                     (2U)
+#define FTM_MODE_WPDIS(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)
+#define FTM_MODE_PWMSYNC_MASK                    (0x8U)
+#define FTM_MODE_PWMSYNC_SHIFT                   (3U)
+#define FTM_MODE_PWMSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)
+#define FTM_MODE_CAPTEST_MASK                    (0x10U)
+#define FTM_MODE_CAPTEST_SHIFT                   (4U)
+#define FTM_MODE_CAPTEST(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)
+#define FTM_MODE_FAULTM_MASK                     (0x60U)
+#define FTM_MODE_FAULTM_SHIFT                    (5U)
+#define FTM_MODE_FAULTM(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
+#define FTM_MODE_FAULTIE_MASK                    (0x80U)
+#define FTM_MODE_FAULTIE_SHIFT                   (7U)
+#define FTM_MODE_FAULTIE(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)
+
+/*! @name SYNC - Synchronization */
+#define FTM_SYNC_CNTMIN_MASK                     (0x1U)
+#define FTM_SYNC_CNTMIN_SHIFT                    (0U)
+#define FTM_SYNC_CNTMIN(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)
+#define FTM_SYNC_CNTMAX_MASK                     (0x2U)
+#define FTM_SYNC_CNTMAX_SHIFT                    (1U)
+#define FTM_SYNC_CNTMAX(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)
+#define FTM_SYNC_REINIT_MASK                     (0x4U)
+#define FTM_SYNC_REINIT_SHIFT                    (2U)
+#define FTM_SYNC_REINIT(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)
+#define FTM_SYNC_SYNCHOM_MASK                    (0x8U)
+#define FTM_SYNC_SYNCHOM_SHIFT                   (3U)
+#define FTM_SYNC_SYNCHOM(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)
+#define FTM_SYNC_TRIG0_MASK                      (0x10U)
+#define FTM_SYNC_TRIG0_SHIFT                     (4U)
+#define FTM_SYNC_TRIG0(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)
+#define FTM_SYNC_TRIG1_MASK                      (0x20U)
+#define FTM_SYNC_TRIG1_SHIFT                     (5U)
+#define FTM_SYNC_TRIG1(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)
+#define FTM_SYNC_TRIG2_MASK                      (0x40U)
+#define FTM_SYNC_TRIG2_SHIFT                     (6U)
+#define FTM_SYNC_TRIG2(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)
+#define FTM_SYNC_SWSYNC_MASK                     (0x80U)
+#define FTM_SYNC_SWSYNC_SHIFT                    (7U)
+#define FTM_SYNC_SWSYNC(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)
+
+/*! @name OUTINIT - Initial State For Channels Output */
+#define FTM_OUTINIT_CH0OI_MASK                   (0x1U)
+#define FTM_OUTINIT_CH0OI_SHIFT                  (0U)
+#define FTM_OUTINIT_CH0OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)
+#define FTM_OUTINIT_CH1OI_MASK                   (0x2U)
+#define FTM_OUTINIT_CH1OI_SHIFT                  (1U)
+#define FTM_OUTINIT_CH1OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)
+#define FTM_OUTINIT_CH2OI_MASK                   (0x4U)
+#define FTM_OUTINIT_CH2OI_SHIFT                  (2U)
+#define FTM_OUTINIT_CH2OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)
+#define FTM_OUTINIT_CH3OI_MASK                   (0x8U)
+#define FTM_OUTINIT_CH3OI_SHIFT                  (3U)
+#define FTM_OUTINIT_CH3OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)
+#define FTM_OUTINIT_CH4OI_MASK                   (0x10U)
+#define FTM_OUTINIT_CH4OI_SHIFT                  (4U)
+#define FTM_OUTINIT_CH4OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)
+#define FTM_OUTINIT_CH5OI_MASK                   (0x20U)
+#define FTM_OUTINIT_CH5OI_SHIFT                  (5U)
+#define FTM_OUTINIT_CH5OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)
+#define FTM_OUTINIT_CH6OI_MASK                   (0x40U)
+#define FTM_OUTINIT_CH6OI_SHIFT                  (6U)
+#define FTM_OUTINIT_CH6OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)
+#define FTM_OUTINIT_CH7OI_MASK                   (0x80U)
+#define FTM_OUTINIT_CH7OI_SHIFT                  (7U)
+#define FTM_OUTINIT_CH7OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)
+
+/*! @name OUTMASK - Output Mask */
+#define FTM_OUTMASK_CH0OM_MASK                   (0x1U)
+#define FTM_OUTMASK_CH0OM_SHIFT                  (0U)
+#define FTM_OUTMASK_CH0OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)
+#define FTM_OUTMASK_CH1OM_MASK                   (0x2U)
+#define FTM_OUTMASK_CH1OM_SHIFT                  (1U)
+#define FTM_OUTMASK_CH1OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)
+#define FTM_OUTMASK_CH2OM_MASK                   (0x4U)
+#define FTM_OUTMASK_CH2OM_SHIFT                  (2U)
+#define FTM_OUTMASK_CH2OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)
+#define FTM_OUTMASK_CH3OM_MASK                   (0x8U)
+#define FTM_OUTMASK_CH3OM_SHIFT                  (3U)
+#define FTM_OUTMASK_CH3OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)
+#define FTM_OUTMASK_CH4OM_MASK                   (0x10U)
+#define FTM_OUTMASK_CH4OM_SHIFT                  (4U)
+#define FTM_OUTMASK_CH4OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)
+#define FTM_OUTMASK_CH5OM_MASK                   (0x20U)
+#define FTM_OUTMASK_CH5OM_SHIFT                  (5U)
+#define FTM_OUTMASK_CH5OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)
+#define FTM_OUTMASK_CH6OM_MASK                   (0x40U)
+#define FTM_OUTMASK_CH6OM_SHIFT                  (6U)
+#define FTM_OUTMASK_CH6OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)
+#define FTM_OUTMASK_CH7OM_MASK                   (0x80U)
+#define FTM_OUTMASK_CH7OM_SHIFT                  (7U)
+#define FTM_OUTMASK_CH7OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)
+
+/*! @name COMBINE - Function For Linked Channels */
+#define FTM_COMBINE_COMBINE0_MASK                (0x1U)
+#define FTM_COMBINE_COMBINE0_SHIFT               (0U)
+#define FTM_COMBINE_COMBINE0(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)
+#define FTM_COMBINE_COMP0_MASK                   (0x2U)
+#define FTM_COMBINE_COMP0_SHIFT                  (1U)
+#define FTM_COMBINE_COMP0(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)
+#define FTM_COMBINE_DECAPEN0_MASK                (0x4U)
+#define FTM_COMBINE_DECAPEN0_SHIFT               (2U)
+#define FTM_COMBINE_DECAPEN0(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)
+#define FTM_COMBINE_DECAP0_MASK                  (0x8U)
+#define FTM_COMBINE_DECAP0_SHIFT                 (3U)
+#define FTM_COMBINE_DECAP0(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)
+#define FTM_COMBINE_DTEN0_MASK                   (0x10U)
+#define FTM_COMBINE_DTEN0_SHIFT                  (4U)
+#define FTM_COMBINE_DTEN0(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)
+#define FTM_COMBINE_SYNCEN0_MASK                 (0x20U)
+#define FTM_COMBINE_SYNCEN0_SHIFT                (5U)
+#define FTM_COMBINE_SYNCEN0(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)
+#define FTM_COMBINE_FAULTEN0_MASK                (0x40U)
+#define FTM_COMBINE_FAULTEN0_SHIFT               (6U)
+#define FTM_COMBINE_FAULTEN0(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)
+#define FTM_COMBINE_COMBINE1_MASK                (0x100U)
+#define FTM_COMBINE_COMBINE1_SHIFT               (8U)
+#define FTM_COMBINE_COMBINE1(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)
+#define FTM_COMBINE_COMP1_MASK                   (0x200U)
+#define FTM_COMBINE_COMP1_SHIFT                  (9U)
+#define FTM_COMBINE_COMP1(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)
+#define FTM_COMBINE_DECAPEN1_MASK                (0x400U)
+#define FTM_COMBINE_DECAPEN1_SHIFT               (10U)
+#define FTM_COMBINE_DECAPEN1(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)
+#define FTM_COMBINE_DECAP1_MASK                  (0x800U)
+#define FTM_COMBINE_DECAP1_SHIFT                 (11U)
+#define FTM_COMBINE_DECAP1(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)
+#define FTM_COMBINE_DTEN1_MASK                   (0x1000U)
+#define FTM_COMBINE_DTEN1_SHIFT                  (12U)
+#define FTM_COMBINE_DTEN1(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)
+#define FTM_COMBINE_SYNCEN1_MASK                 (0x2000U)
+#define FTM_COMBINE_SYNCEN1_SHIFT                (13U)
+#define FTM_COMBINE_SYNCEN1(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)
+#define FTM_COMBINE_FAULTEN1_MASK                (0x4000U)
+#define FTM_COMBINE_FAULTEN1_SHIFT               (14U)
+#define FTM_COMBINE_FAULTEN1(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)
+#define FTM_COMBINE_COMBINE2_MASK                (0x10000U)
+#define FTM_COMBINE_COMBINE2_SHIFT               (16U)
+#define FTM_COMBINE_COMBINE2(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)
+#define FTM_COMBINE_COMP2_MASK                   (0x20000U)
+#define FTM_COMBINE_COMP2_SHIFT                  (17U)
+#define FTM_COMBINE_COMP2(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)
+#define FTM_COMBINE_DECAPEN2_MASK                (0x40000U)
+#define FTM_COMBINE_DECAPEN2_SHIFT               (18U)
+#define FTM_COMBINE_DECAPEN2(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)
+#define FTM_COMBINE_DECAP2_MASK                  (0x80000U)
+#define FTM_COMBINE_DECAP2_SHIFT                 (19U)
+#define FTM_COMBINE_DECAP2(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)
+#define FTM_COMBINE_DTEN2_MASK                   (0x100000U)
+#define FTM_COMBINE_DTEN2_SHIFT                  (20U)
+#define FTM_COMBINE_DTEN2(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)
+#define FTM_COMBINE_SYNCEN2_MASK                 (0x200000U)
+#define FTM_COMBINE_SYNCEN2_SHIFT                (21U)
+#define FTM_COMBINE_SYNCEN2(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)
+#define FTM_COMBINE_FAULTEN2_MASK                (0x400000U)
+#define FTM_COMBINE_FAULTEN2_SHIFT               (22U)
+#define FTM_COMBINE_FAULTEN2(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)
+#define FTM_COMBINE_COMBINE3_MASK                (0x1000000U)
+#define FTM_COMBINE_COMBINE3_SHIFT               (24U)
+#define FTM_COMBINE_COMBINE3(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)
+#define FTM_COMBINE_COMP3_MASK                   (0x2000000U)
+#define FTM_COMBINE_COMP3_SHIFT                  (25U)
+#define FTM_COMBINE_COMP3(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)
+#define FTM_COMBINE_DECAPEN3_MASK                (0x4000000U)
+#define FTM_COMBINE_DECAPEN3_SHIFT               (26U)
+#define FTM_COMBINE_DECAPEN3(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)
+#define FTM_COMBINE_DECAP3_MASK                  (0x8000000U)
+#define FTM_COMBINE_DECAP3_SHIFT                 (27U)
+#define FTM_COMBINE_DECAP3(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)
+#define FTM_COMBINE_DTEN3_MASK                   (0x10000000U)
+#define FTM_COMBINE_DTEN3_SHIFT                  (28U)
+#define FTM_COMBINE_DTEN3(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)
+#define FTM_COMBINE_SYNCEN3_MASK                 (0x20000000U)
+#define FTM_COMBINE_SYNCEN3_SHIFT                (29U)
+#define FTM_COMBINE_SYNCEN3(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)
+#define FTM_COMBINE_FAULTEN3_MASK                (0x40000000U)
+#define FTM_COMBINE_FAULTEN3_SHIFT               (30U)
+#define FTM_COMBINE_FAULTEN3(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)
+
+/*! @name DEADTIME - Deadtime Insertion Control */
+#define FTM_DEADTIME_DTVAL_MASK                  (0x3FU)
+#define FTM_DEADTIME_DTVAL_SHIFT                 (0U)
+#define FTM_DEADTIME_DTVAL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
+#define FTM_DEADTIME_DTPS_MASK                   (0xC0U)
+#define FTM_DEADTIME_DTPS_SHIFT                  (6U)
+#define FTM_DEADTIME_DTPS(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
+
+/*! @name EXTTRIG - FTM External Trigger */
+#define FTM_EXTTRIG_CH2TRIG_MASK                 (0x1U)
+#define FTM_EXTTRIG_CH2TRIG_SHIFT                (0U)
+#define FTM_EXTTRIG_CH2TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)
+#define FTM_EXTTRIG_CH3TRIG_MASK                 (0x2U)
+#define FTM_EXTTRIG_CH3TRIG_SHIFT                (1U)
+#define FTM_EXTTRIG_CH3TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)
+#define FTM_EXTTRIG_CH4TRIG_MASK                 (0x4U)
+#define FTM_EXTTRIG_CH4TRIG_SHIFT                (2U)
+#define FTM_EXTTRIG_CH4TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)
+#define FTM_EXTTRIG_CH5TRIG_MASK                 (0x8U)
+#define FTM_EXTTRIG_CH5TRIG_SHIFT                (3U)
+#define FTM_EXTTRIG_CH5TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)
+#define FTM_EXTTRIG_CH0TRIG_MASK                 (0x10U)
+#define FTM_EXTTRIG_CH0TRIG_SHIFT                (4U)
+#define FTM_EXTTRIG_CH0TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)
+#define FTM_EXTTRIG_CH1TRIG_MASK                 (0x20U)
+#define FTM_EXTTRIG_CH1TRIG_SHIFT                (5U)
+#define FTM_EXTTRIG_CH1TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)
+#define FTM_EXTTRIG_INITTRIGEN_MASK              (0x40U)
+#define FTM_EXTTRIG_INITTRIGEN_SHIFT             (6U)
+#define FTM_EXTTRIG_INITTRIGEN(x)                (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)
+#define FTM_EXTTRIG_TRIGF_MASK                   (0x80U)
+#define FTM_EXTTRIG_TRIGF_SHIFT                  (7U)
+#define FTM_EXTTRIG_TRIGF(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)
+
+/*! @name POL - Channels Polarity */
+#define FTM_POL_POL0_MASK                        (0x1U)
+#define FTM_POL_POL0_SHIFT                       (0U)
+#define FTM_POL_POL0(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)
+#define FTM_POL_POL1_MASK                        (0x2U)
+#define FTM_POL_POL1_SHIFT                       (1U)
+#define FTM_POL_POL1(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)
+#define FTM_POL_POL2_MASK                        (0x4U)
+#define FTM_POL_POL2_SHIFT                       (2U)
+#define FTM_POL_POL2(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)
+#define FTM_POL_POL3_MASK                        (0x8U)
+#define FTM_POL_POL3_SHIFT                       (3U)
+#define FTM_POL_POL3(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)
+#define FTM_POL_POL4_MASK                        (0x10U)
+#define FTM_POL_POL4_SHIFT                       (4U)
+#define FTM_POL_POL4(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)
+#define FTM_POL_POL5_MASK                        (0x20U)
+#define FTM_POL_POL5_SHIFT                       (5U)
+#define FTM_POL_POL5(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)
+#define FTM_POL_POL6_MASK                        (0x40U)
+#define FTM_POL_POL6_SHIFT                       (6U)
+#define FTM_POL_POL6(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)
+#define FTM_POL_POL7_MASK                        (0x80U)
+#define FTM_POL_POL7_SHIFT                       (7U)
+#define FTM_POL_POL7(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)
+
+/*! @name FMS - Fault Mode Status */
+#define FTM_FMS_FAULTF0_MASK                     (0x1U)
+#define FTM_FMS_FAULTF0_SHIFT                    (0U)
+#define FTM_FMS_FAULTF0(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)
+#define FTM_FMS_FAULTF1_MASK                     (0x2U)
+#define FTM_FMS_FAULTF1_SHIFT                    (1U)
+#define FTM_FMS_FAULTF1(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)
+#define FTM_FMS_FAULTF2_MASK                     (0x4U)
+#define FTM_FMS_FAULTF2_SHIFT                    (2U)
+#define FTM_FMS_FAULTF2(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)
+#define FTM_FMS_FAULTF3_MASK                     (0x8U)
+#define FTM_FMS_FAULTF3_SHIFT                    (3U)
+#define FTM_FMS_FAULTF3(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)
+#define FTM_FMS_FAULTIN_MASK                     (0x20U)
+#define FTM_FMS_FAULTIN_SHIFT                    (5U)
+#define FTM_FMS_FAULTIN(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)
+#define FTM_FMS_WPEN_MASK                        (0x40U)
+#define FTM_FMS_WPEN_SHIFT                       (6U)
+#define FTM_FMS_WPEN(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)
+#define FTM_FMS_FAULTF_MASK                      (0x80U)
+#define FTM_FMS_FAULTF_SHIFT                     (7U)
+#define FTM_FMS_FAULTF(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)
+
+/*! @name FILTER - Input Capture Filter Control */
+#define FTM_FILTER_CH0FVAL_MASK                  (0xFU)
+#define FTM_FILTER_CH0FVAL_SHIFT                 (0U)
+#define FTM_FILTER_CH0FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
+#define FTM_FILTER_CH1FVAL_MASK                  (0xF0U)
+#define FTM_FILTER_CH1FVAL_SHIFT                 (4U)
+#define FTM_FILTER_CH1FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
+#define FTM_FILTER_CH2FVAL_MASK                  (0xF00U)
+#define FTM_FILTER_CH2FVAL_SHIFT                 (8U)
+#define FTM_FILTER_CH2FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
+#define FTM_FILTER_CH3FVAL_MASK                  (0xF000U)
+#define FTM_FILTER_CH3FVAL_SHIFT                 (12U)
+#define FTM_FILTER_CH3FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
+
+/*! @name FLTCTRL - Fault Control */
+#define FTM_FLTCTRL_FAULT0EN_MASK                (0x1U)
+#define FTM_FLTCTRL_FAULT0EN_SHIFT               (0U)
+#define FTM_FLTCTRL_FAULT0EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)
+#define FTM_FLTCTRL_FAULT1EN_MASK                (0x2U)
+#define FTM_FLTCTRL_FAULT1EN_SHIFT               (1U)
+#define FTM_FLTCTRL_FAULT1EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)
+#define FTM_FLTCTRL_FAULT2EN_MASK                (0x4U)
+#define FTM_FLTCTRL_FAULT2EN_SHIFT               (2U)
+#define FTM_FLTCTRL_FAULT2EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)
+#define FTM_FLTCTRL_FAULT3EN_MASK                (0x8U)
+#define FTM_FLTCTRL_FAULT3EN_SHIFT               (3U)
+#define FTM_FLTCTRL_FAULT3EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)
+#define FTM_FLTCTRL_FFLTR0EN_MASK                (0x10U)
+#define FTM_FLTCTRL_FFLTR0EN_SHIFT               (4U)
+#define FTM_FLTCTRL_FFLTR0EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)
+#define FTM_FLTCTRL_FFLTR1EN_MASK                (0x20U)
+#define FTM_FLTCTRL_FFLTR1EN_SHIFT               (5U)
+#define FTM_FLTCTRL_FFLTR1EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)
+#define FTM_FLTCTRL_FFLTR2EN_MASK                (0x40U)
+#define FTM_FLTCTRL_FFLTR2EN_SHIFT               (6U)
+#define FTM_FLTCTRL_FFLTR2EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)
+#define FTM_FLTCTRL_FFLTR3EN_MASK                (0x80U)
+#define FTM_FLTCTRL_FFLTR3EN_SHIFT               (7U)
+#define FTM_FLTCTRL_FFLTR3EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)
+#define FTM_FLTCTRL_FFVAL_MASK                   (0xF00U)
+#define FTM_FLTCTRL_FFVAL_SHIFT                  (8U)
+#define FTM_FLTCTRL_FFVAL(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
+
+/*! @name QDCTRL - Quadrature Decoder Control And Status */
+#define FTM_QDCTRL_QUADEN_MASK                   (0x1U)
+#define FTM_QDCTRL_QUADEN_SHIFT                  (0U)
+#define FTM_QDCTRL_QUADEN(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)
+#define FTM_QDCTRL_TOFDIR_MASK                   (0x2U)
+#define FTM_QDCTRL_TOFDIR_SHIFT                  (1U)
+#define FTM_QDCTRL_TOFDIR(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)
+#define FTM_QDCTRL_QUADIR_MASK                   (0x4U)
+#define FTM_QDCTRL_QUADIR_SHIFT                  (2U)
+#define FTM_QDCTRL_QUADIR(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)
+#define FTM_QDCTRL_QUADMODE_MASK                 (0x8U)
+#define FTM_QDCTRL_QUADMODE_SHIFT                (3U)
+#define FTM_QDCTRL_QUADMODE(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)
+#define FTM_QDCTRL_PHBPOL_MASK                   (0x10U)
+#define FTM_QDCTRL_PHBPOL_SHIFT                  (4U)
+#define FTM_QDCTRL_PHBPOL(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)
+#define FTM_QDCTRL_PHAPOL_MASK                   (0x20U)
+#define FTM_QDCTRL_PHAPOL_SHIFT                  (5U)
+#define FTM_QDCTRL_PHAPOL(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)
+#define FTM_QDCTRL_PHBFLTREN_MASK                (0x40U)
+#define FTM_QDCTRL_PHBFLTREN_SHIFT               (6U)
+#define FTM_QDCTRL_PHBFLTREN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)
+#define FTM_QDCTRL_PHAFLTREN_MASK                (0x80U)
+#define FTM_QDCTRL_PHAFLTREN_SHIFT               (7U)
+#define FTM_QDCTRL_PHAFLTREN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
+
+/*! @name CONF - Configuration */
+#define FTM_CONF_NUMTOF_MASK                     (0x1FU)
+#define FTM_CONF_NUMTOF_SHIFT                    (0U)
+#define FTM_CONF_NUMTOF(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK)
+#define FTM_CONF_BDMMODE_MASK                    (0xC0U)
+#define FTM_CONF_BDMMODE_SHIFT                   (6U)
+#define FTM_CONF_BDMMODE(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
+#define FTM_CONF_GTBEEN_MASK                     (0x200U)
+#define FTM_CONF_GTBEEN_SHIFT                    (9U)
+#define FTM_CONF_GTBEEN(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)
+#define FTM_CONF_GTBEOUT_MASK                    (0x400U)
+#define FTM_CONF_GTBEOUT_SHIFT                   (10U)
+#define FTM_CONF_GTBEOUT(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)
+
+/*! @name FLTPOL - FTM Fault Input Polarity */
+#define FTM_FLTPOL_FLT0POL_MASK                  (0x1U)
+#define FTM_FLTPOL_FLT0POL_SHIFT                 (0U)
+#define FTM_FLTPOL_FLT0POL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)
+#define FTM_FLTPOL_FLT1POL_MASK                  (0x2U)
+#define FTM_FLTPOL_FLT1POL_SHIFT                 (1U)
+#define FTM_FLTPOL_FLT1POL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)
+#define FTM_FLTPOL_FLT2POL_MASK                  (0x4U)
+#define FTM_FLTPOL_FLT2POL_SHIFT                 (2U)
+#define FTM_FLTPOL_FLT2POL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)
+#define FTM_FLTPOL_FLT3POL_MASK                  (0x8U)
+#define FTM_FLTPOL_FLT3POL_SHIFT                 (3U)
+#define FTM_FLTPOL_FLT3POL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)
+
+/*! @name SYNCONF - Synchronization Configuration */
+#define FTM_SYNCONF_HWTRIGMODE_MASK              (0x1U)
+#define FTM_SYNCONF_HWTRIGMODE_SHIFT             (0U)
+#define FTM_SYNCONF_HWTRIGMODE(x)                (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)
+#define FTM_SYNCONF_CNTINC_MASK                  (0x4U)
+#define FTM_SYNCONF_CNTINC_SHIFT                 (2U)
+#define FTM_SYNCONF_CNTINC(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)
+#define FTM_SYNCONF_INVC_MASK                    (0x10U)
+#define FTM_SYNCONF_INVC_SHIFT                   (4U)
+#define FTM_SYNCONF_INVC(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)
+#define FTM_SYNCONF_SWOC_MASK                    (0x20U)
+#define FTM_SYNCONF_SWOC_SHIFT                   (5U)
+#define FTM_SYNCONF_SWOC(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)
+#define FTM_SYNCONF_SYNCMODE_MASK                (0x80U)
+#define FTM_SYNCONF_SYNCMODE_SHIFT               (7U)
+#define FTM_SYNCONF_SYNCMODE(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)
+#define FTM_SYNCONF_SWRSTCNT_MASK                (0x100U)
+#define FTM_SYNCONF_SWRSTCNT_SHIFT               (8U)
+#define FTM_SYNCONF_SWRSTCNT(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)
+#define FTM_SYNCONF_SWWRBUF_MASK                 (0x200U)
+#define FTM_SYNCONF_SWWRBUF_SHIFT                (9U)
+#define FTM_SYNCONF_SWWRBUF(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)
+#define FTM_SYNCONF_SWOM_MASK                    (0x400U)
+#define FTM_SYNCONF_SWOM_SHIFT                   (10U)
+#define FTM_SYNCONF_SWOM(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)
+#define FTM_SYNCONF_SWINVC_MASK                  (0x800U)
+#define FTM_SYNCONF_SWINVC_SHIFT                 (11U)
+#define FTM_SYNCONF_SWINVC(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)
+#define FTM_SYNCONF_SWSOC_MASK                   (0x1000U)
+#define FTM_SYNCONF_SWSOC_SHIFT                  (12U)
+#define FTM_SYNCONF_SWSOC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)
+#define FTM_SYNCONF_HWRSTCNT_MASK                (0x10000U)
+#define FTM_SYNCONF_HWRSTCNT_SHIFT               (16U)
+#define FTM_SYNCONF_HWRSTCNT(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)
+#define FTM_SYNCONF_HWWRBUF_MASK                 (0x20000U)
+#define FTM_SYNCONF_HWWRBUF_SHIFT                (17U)
+#define FTM_SYNCONF_HWWRBUF(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)
+#define FTM_SYNCONF_HWOM_MASK                    (0x40000U)
+#define FTM_SYNCONF_HWOM_SHIFT                   (18U)
+#define FTM_SYNCONF_HWOM(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)
+#define FTM_SYNCONF_HWINVC_MASK                  (0x80000U)
+#define FTM_SYNCONF_HWINVC_SHIFT                 (19U)
+#define FTM_SYNCONF_HWINVC(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)
+#define FTM_SYNCONF_HWSOC_MASK                   (0x100000U)
+#define FTM_SYNCONF_HWSOC_SHIFT                  (20U)
+#define FTM_SYNCONF_HWSOC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)
+
+/*! @name INVCTRL - FTM Inverting Control */
+#define FTM_INVCTRL_INV0EN_MASK                  (0x1U)
+#define FTM_INVCTRL_INV0EN_SHIFT                 (0U)
+#define FTM_INVCTRL_INV0EN(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)
+#define FTM_INVCTRL_INV1EN_MASK                  (0x2U)
+#define FTM_INVCTRL_INV1EN_SHIFT                 (1U)
+#define FTM_INVCTRL_INV1EN(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)
+#define FTM_INVCTRL_INV2EN_MASK                  (0x4U)
+#define FTM_INVCTRL_INV2EN_SHIFT                 (2U)
+#define FTM_INVCTRL_INV2EN(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)
+#define FTM_INVCTRL_INV3EN_MASK                  (0x8U)
+#define FTM_INVCTRL_INV3EN_SHIFT                 (3U)
+#define FTM_INVCTRL_INV3EN(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)
+
+/*! @name SWOCTRL - FTM Software Output Control */
+#define FTM_SWOCTRL_CH0OC_MASK                   (0x1U)
+#define FTM_SWOCTRL_CH0OC_SHIFT                  (0U)
+#define FTM_SWOCTRL_CH0OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)
+#define FTM_SWOCTRL_CH1OC_MASK                   (0x2U)
+#define FTM_SWOCTRL_CH1OC_SHIFT                  (1U)
+#define FTM_SWOCTRL_CH1OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)
+#define FTM_SWOCTRL_CH2OC_MASK                   (0x4U)
+#define FTM_SWOCTRL_CH2OC_SHIFT                  (2U)
+#define FTM_SWOCTRL_CH2OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)
+#define FTM_SWOCTRL_CH3OC_MASK                   (0x8U)
+#define FTM_SWOCTRL_CH3OC_SHIFT                  (3U)
+#define FTM_SWOCTRL_CH3OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)
+#define FTM_SWOCTRL_CH4OC_MASK                   (0x10U)
+#define FTM_SWOCTRL_CH4OC_SHIFT                  (4U)
+#define FTM_SWOCTRL_CH4OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)
+#define FTM_SWOCTRL_CH5OC_MASK                   (0x20U)
+#define FTM_SWOCTRL_CH5OC_SHIFT                  (5U)
+#define FTM_SWOCTRL_CH5OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)
+#define FTM_SWOCTRL_CH6OC_MASK                   (0x40U)
+#define FTM_SWOCTRL_CH6OC_SHIFT                  (6U)
+#define FTM_SWOCTRL_CH6OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)
+#define FTM_SWOCTRL_CH7OC_MASK                   (0x80U)
+#define FTM_SWOCTRL_CH7OC_SHIFT                  (7U)
+#define FTM_SWOCTRL_CH7OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)
+#define FTM_SWOCTRL_CH0OCV_MASK                  (0x100U)
+#define FTM_SWOCTRL_CH0OCV_SHIFT                 (8U)
+#define FTM_SWOCTRL_CH0OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)
+#define FTM_SWOCTRL_CH1OCV_MASK                  (0x200U)
+#define FTM_SWOCTRL_CH1OCV_SHIFT                 (9U)
+#define FTM_SWOCTRL_CH1OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)
+#define FTM_SWOCTRL_CH2OCV_MASK                  (0x400U)
+#define FTM_SWOCTRL_CH2OCV_SHIFT                 (10U)
+#define FTM_SWOCTRL_CH2OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)
+#define FTM_SWOCTRL_CH3OCV_MASK                  (0x800U)
+#define FTM_SWOCTRL_CH3OCV_SHIFT                 (11U)
+#define FTM_SWOCTRL_CH3OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)
+#define FTM_SWOCTRL_CH4OCV_MASK                  (0x1000U)
+#define FTM_SWOCTRL_CH4OCV_SHIFT                 (12U)
+#define FTM_SWOCTRL_CH4OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)
+#define FTM_SWOCTRL_CH5OCV_MASK                  (0x2000U)
+#define FTM_SWOCTRL_CH5OCV_SHIFT                 (13U)
+#define FTM_SWOCTRL_CH5OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)
+#define FTM_SWOCTRL_CH6OCV_MASK                  (0x4000U)
+#define FTM_SWOCTRL_CH6OCV_SHIFT                 (14U)
+#define FTM_SWOCTRL_CH6OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)
+#define FTM_SWOCTRL_CH7OCV_MASK                  (0x8000U)
+#define FTM_SWOCTRL_CH7OCV_SHIFT                 (15U)
+#define FTM_SWOCTRL_CH7OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)
+
+/*! @name PWMLOAD - FTM PWM Load */
+#define FTM_PWMLOAD_CH0SEL_MASK                  (0x1U)
+#define FTM_PWMLOAD_CH0SEL_SHIFT                 (0U)
+#define FTM_PWMLOAD_CH0SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)
+#define FTM_PWMLOAD_CH1SEL_MASK                  (0x2U)
+#define FTM_PWMLOAD_CH1SEL_SHIFT                 (1U)
+#define FTM_PWMLOAD_CH1SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)
+#define FTM_PWMLOAD_CH2SEL_MASK                  (0x4U)
+#define FTM_PWMLOAD_CH2SEL_SHIFT                 (2U)
+#define FTM_PWMLOAD_CH2SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)
+#define FTM_PWMLOAD_CH3SEL_MASK                  (0x8U)
+#define FTM_PWMLOAD_CH3SEL_SHIFT                 (3U)
+#define FTM_PWMLOAD_CH3SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)
+#define FTM_PWMLOAD_CH4SEL_MASK                  (0x10U)
+#define FTM_PWMLOAD_CH4SEL_SHIFT                 (4U)
+#define FTM_PWMLOAD_CH4SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)
+#define FTM_PWMLOAD_CH5SEL_MASK                  (0x20U)
+#define FTM_PWMLOAD_CH5SEL_SHIFT                 (5U)
+#define FTM_PWMLOAD_CH5SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)
+#define FTM_PWMLOAD_CH6SEL_MASK                  (0x40U)
+#define FTM_PWMLOAD_CH6SEL_SHIFT                 (6U)
+#define FTM_PWMLOAD_CH6SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)
+#define FTM_PWMLOAD_CH7SEL_MASK                  (0x80U)
+#define FTM_PWMLOAD_CH7SEL_SHIFT                 (7U)
+#define FTM_PWMLOAD_CH7SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)
+#define FTM_PWMLOAD_LDOK_MASK                    (0x200U)
+#define FTM_PWMLOAD_LDOK_SHIFT                   (9U)
+#define FTM_PWMLOAD_LDOK(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group FTM_Register_Masks */
+
+
+/* FTM - Peripheral instance base addresses */
+/** Peripheral FTM0 base address */
+#define FTM0_BASE                                (0x40038000u)
+/** Peripheral FTM0 base pointer */
+#define FTM0                                     ((FTM_Type *)FTM0_BASE)
+/** Peripheral FTM1 base address */
+#define FTM1_BASE                                (0x40039000u)
+/** Peripheral FTM1 base pointer */
+#define FTM1                                     ((FTM_Type *)FTM1_BASE)
+/** Peripheral FTM2 base address */
+#define FTM2_BASE                                (0x4003A000u)
+/** Peripheral FTM2 base pointer */
+#define FTM2                                     ((FTM_Type *)FTM2_BASE)
+/** Peripheral FTM3 base address */
+#define FTM3_BASE                                (0x400B9000u)
+/** Peripheral FTM3 base pointer */
+#define FTM3                                     ((FTM_Type *)FTM3_BASE)
+/** Array initializer of FTM peripheral base addresses */
+#define FTM_BASE_ADDRS                           { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
+/** Array initializer of FTM peripheral base pointers */
+#define FTM_BASE_PTRS                            { FTM0, FTM1, FTM2, FTM3 }
+/** Interrupt vectors for the FTM peripheral type */
+#define FTM_IRQS                                 { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }
+
+/*!
+ * @}
+ */ /* end of group FTM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PDOR;                              /**< Port Data Output Register, offset: 0x0 */
+  __O  uint32_t PSOR;                              /**< Port Set Output Register, offset: 0x4 */
+  __O  uint32_t PCOR;                              /**< Port Clear Output Register, offset: 0x8 */
+  __O  uint32_t PTOR;                              /**< Port Toggle Output Register, offset: 0xC */
+  __I  uint32_t PDIR;                              /**< Port Data Input Register, offset: 0x10 */
+  __IO uint32_t PDDR;                              /**< Port Data Direction Register, offset: 0x14 */
+} GPIO_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- GPIO Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/*! @name PDOR - Port Data Output Register */
+#define GPIO_PDOR_PDO_MASK                       (0xFFFFFFFFU)
+#define GPIO_PDOR_PDO_SHIFT                      (0U)
+#define GPIO_PDOR_PDO(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
+
+/*! @name PSOR - Port Set Output Register */
+#define GPIO_PSOR_PTSO_MASK                      (0xFFFFFFFFU)
+#define GPIO_PSOR_PTSO_SHIFT                     (0U)
+#define GPIO_PSOR_PTSO(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
+
+/*! @name PCOR - Port Clear Output Register */
+#define GPIO_PCOR_PTCO_MASK                      (0xFFFFFFFFU)
+#define GPIO_PCOR_PTCO_SHIFT                     (0U)
+#define GPIO_PCOR_PTCO(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
+
+/*! @name PTOR - Port Toggle Output Register */
+#define GPIO_PTOR_PTTO_MASK                      (0xFFFFFFFFU)
+#define GPIO_PTOR_PTTO_SHIFT                     (0U)
+#define GPIO_PTOR_PTTO(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
+
+/*! @name PDIR - Port Data Input Register */
+#define GPIO_PDIR_PDI_MASK                       (0xFFFFFFFFU)
+#define GPIO_PDIR_PDI_SHIFT                      (0U)
+#define GPIO_PDIR_PDI(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
+
+/*! @name PDDR - Port Data Direction Register */
+#define GPIO_PDDR_PDD_MASK                       (0xFFFFFFFFU)
+#define GPIO_PDDR_PDD_SHIFT                      (0U)
+#define GPIO_PDDR_PDD(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral GPIOA base address */
+#define GPIOA_BASE                               (0x400FF000u)
+/** Peripheral GPIOA base pointer */
+#define GPIOA                                    ((GPIO_TypeDef *)GPIOA_BASE)
+/** Peripheral GPIOB base address */
+#define GPIOB_BASE                               (0x400FF040u)
+/** Peripheral GPIOB base pointer */
+#define GPIOB                                    ((GPIO_TypeDef *)GPIOB_BASE)
+/** Peripheral GPIOC base address */
+#define GPIOC_BASE                               (0x400FF080u)
+/** Peripheral GPIOC base pointer */
+#define GPIOC                                    ((GPIO_TypeDef *)GPIOC_BASE)
+/** Peripheral GPIOD base address */
+#define GPIOD_BASE                               (0x400FF0C0u)
+/** Peripheral GPIOD base pointer */
+#define GPIOD                                    ((GPIO_TypeDef *)GPIOD_BASE)
+/** Peripheral GPIOE base address */
+#define GPIOE_BASE                               (0x400FF100u)
+/** Peripheral GPIOE base pointer */
+#define GPIOE                                    ((GPIO_TypeDef *)GPIOE_BASE)
+/** Array initializer of GPIO peripheral base addresses */
+#define GPIO_BASE_ADDRS                          { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASE_PTRS                           { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2C Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t A1;                                 /**< I2C Address Register 1, offset: 0x0 */
+  __IO uint8_t F;                                  /**< I2C Frequency Divider register, offset: 0x1 */
+  __IO uint8_t C1;                                 /**< I2C Control Register 1, offset: 0x2 */
+  __IO uint8_t S;                                  /**< I2C Status register, offset: 0x3 */
+  __IO uint8_t D;                                  /**< I2C Data I/O register, offset: 0x4 */
+  __IO uint8_t C2;                                 /**< I2C Control Register 2, offset: 0x5 */
+  __IO uint8_t FLT;                                /**< I2C Programmable Input Glitch Filter Register, offset: 0x6 */
+  __IO uint8_t RA;                                 /**< I2C Range Address register, offset: 0x7 */
+  __IO uint8_t SMB;                                /**< I2C SMBus Control and Status register, offset: 0x8 */
+  __IO uint8_t A2;                                 /**< I2C Address Register 2, offset: 0x9 */
+  __IO uint8_t SLTH;                               /**< I2C SCL Low Timeout Register High, offset: 0xA */
+  __IO uint8_t SLTL;                               /**< I2C SCL Low Timeout Register Low, offset: 0xB */
+} I2C_Type;
+
+/* ----------------------------------------------------------------------------
+   -- I2C Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/*! @name A1 - I2C Address Register 1 */
+#define I2C_A1_AD_MASK                           (0xFEU)
+#define I2C_A1_AD_SHIFT                          (1U)
+#define I2C_A1_AD(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
+
+/*! @name F - I2C Frequency Divider register */
+#define I2C_F_ICR_MASK                           (0x3FU)
+#define I2C_F_ICR_SHIFT                          (0U)
+#define I2C_F_ICR(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
+#define I2C_F_MULT_MASK                          (0xC0U)
+#define I2C_F_MULT_SHIFT                         (6U)
+#define I2C_F_MULT(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
+
+/*! @name C1 - I2C Control Register 1 */
+#define I2C_C1_DMAEN_MASK                        (0x1U)
+#define I2C_C1_DMAEN_SHIFT                       (0U)
+#define I2C_C1_DMAEN(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
+#define I2C_C1_WUEN_MASK                         (0x2U)
+#define I2C_C1_WUEN_SHIFT                        (1U)
+#define I2C_C1_WUEN(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
+#define I2C_C1_RSTA_MASK                         (0x4U)
+#define I2C_C1_RSTA_SHIFT                        (2U)
+#define I2C_C1_RSTA(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
+#define I2C_C1_TXAK_MASK                         (0x8U)
+#define I2C_C1_TXAK_SHIFT                        (3U)
+#define I2C_C1_TXAK(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
+#define I2C_C1_TX_MASK                           (0x10U)
+#define I2C_C1_TX_SHIFT                          (4U)
+#define I2C_C1_TX(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
+#define I2C_C1_MST_MASK                          (0x20U)
+#define I2C_C1_MST_SHIFT                         (5U)
+#define I2C_C1_MST(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
+#define I2C_C1_IICIE_MASK                        (0x40U)
+#define I2C_C1_IICIE_SHIFT                       (6U)
+#define I2C_C1_IICIE(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
+#define I2C_C1_IICEN_MASK                        (0x80U)
+#define I2C_C1_IICEN_SHIFT                       (7U)
+#define I2C_C1_IICEN(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
+
+/*! @name S - I2C Status register */
+#define I2C_S_RXAK_MASK                          (0x1U)
+#define I2C_S_RXAK_SHIFT                         (0U)
+#define I2C_S_RXAK(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
+#define I2C_S_IICIF_MASK                         (0x2U)
+#define I2C_S_IICIF_SHIFT                        (1U)
+#define I2C_S_IICIF(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
+#define I2C_S_SRW_MASK                           (0x4U)
+#define I2C_S_SRW_SHIFT                          (2U)
+#define I2C_S_SRW(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
+#define I2C_S_RAM_MASK                           (0x8U)
+#define I2C_S_RAM_SHIFT                          (3U)
+#define I2C_S_RAM(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
+#define I2C_S_ARBL_MASK                          (0x10U)
+#define I2C_S_ARBL_SHIFT                         (4U)
+#define I2C_S_ARBL(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
+#define I2C_S_BUSY_MASK                          (0x20U)
+#define I2C_S_BUSY_SHIFT                         (5U)
+#define I2C_S_BUSY(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
+#define I2C_S_IAAS_MASK                          (0x40U)
+#define I2C_S_IAAS_SHIFT                         (6U)
+#define I2C_S_IAAS(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
+#define I2C_S_TCF_MASK                           (0x80U)
+#define I2C_S_TCF_SHIFT                          (7U)
+#define I2C_S_TCF(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
+
+/*! @name D - I2C Data I/O register */
+#define I2C_D_DATA_MASK                          (0xFFU)
+#define I2C_D_DATA_SHIFT                         (0U)
+#define I2C_D_DATA(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
+
+/*! @name C2 - I2C Control Register 2 */
+#define I2C_C2_AD_MASK                           (0x7U)
+#define I2C_C2_AD_SHIFT                          (0U)
+#define I2C_C2_AD(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
+#define I2C_C2_RMEN_MASK                         (0x8U)
+#define I2C_C2_RMEN_SHIFT                        (3U)
+#define I2C_C2_RMEN(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
+#define I2C_C2_SBRC_MASK                         (0x10U)
+#define I2C_C2_SBRC_SHIFT                        (4U)
+#define I2C_C2_SBRC(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
+#define I2C_C2_HDRS_MASK                         (0x20U)
+#define I2C_C2_HDRS_SHIFT                        (5U)
+#define I2C_C2_HDRS(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
+#define I2C_C2_ADEXT_MASK                        (0x40U)
+#define I2C_C2_ADEXT_SHIFT                       (6U)
+#define I2C_C2_ADEXT(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
+#define I2C_C2_GCAEN_MASK                        (0x80U)
+#define I2C_C2_GCAEN_SHIFT                       (7U)
+#define I2C_C2_GCAEN(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
+
+/*! @name FLT - I2C Programmable Input Glitch Filter Register */
+#define I2C_FLT_FLT_MASK                         (0xFU)
+#define I2C_FLT_FLT_SHIFT                        (0U)
+#define I2C_FLT_FLT(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
+#define I2C_FLT_STARTF_MASK                      (0x10U)
+#define I2C_FLT_STARTF_SHIFT                     (4U)
+#define I2C_FLT_STARTF(x)                        (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
+#define I2C_FLT_SSIE_MASK                        (0x20U)
+#define I2C_FLT_SSIE_SHIFT                       (5U)
+#define I2C_FLT_SSIE(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
+#define I2C_FLT_STOPF_MASK                       (0x40U)
+#define I2C_FLT_STOPF_SHIFT                      (6U)
+#define I2C_FLT_STOPF(x)                         (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
+#define I2C_FLT_SHEN_MASK                        (0x80U)
+#define I2C_FLT_SHEN_SHIFT                       (7U)
+#define I2C_FLT_SHEN(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
+
+/*! @name RA - I2C Range Address register */
+#define I2C_RA_RAD_MASK                          (0xFEU)
+#define I2C_RA_RAD_SHIFT                         (1U)
+#define I2C_RA_RAD(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
+
+/*! @name SMB - I2C SMBus Control and Status register */
+#define I2C_SMB_SHTF2IE_MASK                     (0x1U)
+#define I2C_SMB_SHTF2IE_SHIFT                    (0U)
+#define I2C_SMB_SHTF2IE(x)                       (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
+#define I2C_SMB_SHTF2_MASK                       (0x2U)
+#define I2C_SMB_SHTF2_SHIFT                      (1U)
+#define I2C_SMB_SHTF2(x)                         (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
+#define I2C_SMB_SHTF1_MASK                       (0x4U)
+#define I2C_SMB_SHTF1_SHIFT                      (2U)
+#define I2C_SMB_SHTF1(x)                         (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
+#define I2C_SMB_SLTF_MASK                        (0x8U)
+#define I2C_SMB_SLTF_SHIFT                       (3U)
+#define I2C_SMB_SLTF(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
+#define I2C_SMB_TCKSEL_MASK                      (0x10U)
+#define I2C_SMB_TCKSEL_SHIFT                     (4U)
+#define I2C_SMB_TCKSEL(x)                        (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
+#define I2C_SMB_SIICAEN_MASK                     (0x20U)
+#define I2C_SMB_SIICAEN_SHIFT                    (5U)
+#define I2C_SMB_SIICAEN(x)                       (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
+#define I2C_SMB_ALERTEN_MASK                     (0x40U)
+#define I2C_SMB_ALERTEN_SHIFT                    (6U)
+#define I2C_SMB_ALERTEN(x)                       (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
+#define I2C_SMB_FACK_MASK                        (0x80U)
+#define I2C_SMB_FACK_SHIFT                       (7U)
+#define I2C_SMB_FACK(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
+
+/*! @name A2 - I2C Address Register 2 */
+#define I2C_A2_SAD_MASK                          (0xFEU)
+#define I2C_A2_SAD_SHIFT                         (1U)
+#define I2C_A2_SAD(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
+
+/*! @name SLTH - I2C SCL Low Timeout Register High */
+#define I2C_SLTH_SSLT_MASK                       (0xFFU)
+#define I2C_SLTH_SSLT_SHIFT                      (0U)
+#define I2C_SLTH_SSLT(x)                         (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
+
+/*! @name SLTL - I2C SCL Low Timeout Register Low */
+#define I2C_SLTL_SSLT_MASK                       (0xFFU)
+#define I2C_SLTL_SSLT_SHIFT                      (0U)
+#define I2C_SLTL_SSLT(x)                         (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE                                (0x40066000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0                                     ((I2C_Type *)I2C0_BASE)
+/** Peripheral I2C1 base address */
+#define I2C1_BASE                                (0x40067000u)
+/** Peripheral I2C1 base pointer */
+#define I2C1                                     ((I2C_Type *)I2C1_BASE)
+/** Peripheral I2C2 base address */
+#define I2C2_BASE                                (0x400E6000u)
+/** Peripheral I2C2 base pointer */
+#define I2C2                                     ((I2C_Type *)I2C2_BASE)
+/** Peripheral I2C3 base address */
+#define I2C3_BASE                                (0x400E7000u)
+/** Peripheral I2C3 base pointer */
+#define I2C3                                     ((I2C_Type *)I2C3_BASE)
+/** Array initializer of I2C peripheral base addresses */
+#define I2C_BASE_ADDRS                           { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE }
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASE_PTRS                            { I2C0, I2C1, I2C2, I2C3 }
+/** Interrupt vectors for the I2C peripheral type */
+#define I2C_IRQS                                 { I2C0_IRQn, I2C1_IRQn, I2C2_IRQn, I2C3_IRQn }
+
+/*!
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- I2S Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t TCSR;                              /**< SAI Transmit Control Register, offset: 0x0 */
+  __IO uint32_t TCR1;                              /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
+  __IO uint32_t TCR2;                              /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
+  __IO uint32_t TCR3;                              /**< SAI Transmit Configuration 3 Register, offset: 0xC */
+  __IO uint32_t TCR4;                              /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
+  __IO uint32_t TCR5;                              /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
+       uint8_t RESERVED_0[8];
+  __O  uint32_t TDR[2];                            /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
+       uint8_t RESERVED_1[24];
+  __I  uint32_t TFR[2];                            /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
+       uint8_t RESERVED_2[24];
+  __IO uint32_t TMR;                               /**< SAI Transmit Mask Register, offset: 0x60 */
+       uint8_t RESERVED_3[28];
+  __IO uint32_t RCSR;                              /**< SAI Receive Control Register, offset: 0x80 */
+  __IO uint32_t RCR1;                              /**< SAI Receive Configuration 1 Register, offset: 0x84 */
+  __IO uint32_t RCR2;                              /**< SAI Receive Configuration 2 Register, offset: 0x88 */
+  __IO uint32_t RCR3;                              /**< SAI Receive Configuration 3 Register, offset: 0x8C */
+  __IO uint32_t RCR4;                              /**< SAI Receive Configuration 4 Register, offset: 0x90 */
+  __IO uint32_t RCR5;                              /**< SAI Receive Configuration 5 Register, offset: 0x94 */
+       uint8_t RESERVED_4[8];
+  __I  uint32_t RDR[2];                            /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
+       uint8_t RESERVED_5[24];
+  __I  uint32_t RFR[2];                            /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
+       uint8_t RESERVED_6[24];
+  __IO uint32_t RMR;                               /**< SAI Receive Mask Register, offset: 0xE0 */
+       uint8_t RESERVED_7[28];
+  __IO uint32_t MCR;                               /**< SAI MCLK Control Register, offset: 0x100 */
+  __IO uint32_t MDR;                               /**< SAI MCLK Divide Register, offset: 0x104 */
+} I2S_Type;
+
+/* ----------------------------------------------------------------------------
+   -- I2S Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/*! @name TCSR - SAI Transmit Control Register */
+#define I2S_TCSR_FRDE_MASK                       (0x1U)
+#define I2S_TCSR_FRDE_SHIFT                      (0U)
+#define I2S_TCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
+#define I2S_TCSR_FWDE_MASK                       (0x2U)
+#define I2S_TCSR_FWDE_SHIFT                      (1U)
+#define I2S_TCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
+#define I2S_TCSR_FRIE_MASK                       (0x100U)
+#define I2S_TCSR_FRIE_SHIFT                      (8U)
+#define I2S_TCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
+#define I2S_TCSR_FWIE_MASK                       (0x200U)
+#define I2S_TCSR_FWIE_SHIFT                      (9U)
+#define I2S_TCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
+#define I2S_TCSR_FEIE_MASK                       (0x400U)
+#define I2S_TCSR_FEIE_SHIFT                      (10U)
+#define I2S_TCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
+#define I2S_TCSR_SEIE_MASK                       (0x800U)
+#define I2S_TCSR_SEIE_SHIFT                      (11U)
+#define I2S_TCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
+#define I2S_TCSR_WSIE_MASK                       (0x1000U)
+#define I2S_TCSR_WSIE_SHIFT                      (12U)
+#define I2S_TCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
+#define I2S_TCSR_FRF_MASK                        (0x10000U)
+#define I2S_TCSR_FRF_SHIFT                       (16U)
+#define I2S_TCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
+#define I2S_TCSR_FWF_MASK                        (0x20000U)
+#define I2S_TCSR_FWF_SHIFT                       (17U)
+#define I2S_TCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
+#define I2S_TCSR_FEF_MASK                        (0x40000U)
+#define I2S_TCSR_FEF_SHIFT                       (18U)
+#define I2S_TCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
+#define I2S_TCSR_SEF_MASK                        (0x80000U)
+#define I2S_TCSR_SEF_SHIFT                       (19U)
+#define I2S_TCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
+#define I2S_TCSR_WSF_MASK                        (0x100000U)
+#define I2S_TCSR_WSF_SHIFT                       (20U)
+#define I2S_TCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
+#define I2S_TCSR_SR_MASK                         (0x1000000U)
+#define I2S_TCSR_SR_SHIFT                        (24U)
+#define I2S_TCSR_SR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
+#define I2S_TCSR_FR_MASK                         (0x2000000U)
+#define I2S_TCSR_FR_SHIFT                        (25U)
+#define I2S_TCSR_FR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
+#define I2S_TCSR_BCE_MASK                        (0x10000000U)
+#define I2S_TCSR_BCE_SHIFT                       (28U)
+#define I2S_TCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
+#define I2S_TCSR_DBGE_MASK                       (0x20000000U)
+#define I2S_TCSR_DBGE_SHIFT                      (29U)
+#define I2S_TCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
+#define I2S_TCSR_STOPE_MASK                      (0x40000000U)
+#define I2S_TCSR_STOPE_SHIFT                     (30U)
+#define I2S_TCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
+#define I2S_TCSR_TE_MASK                         (0x80000000U)
+#define I2S_TCSR_TE_SHIFT                        (31U)
+#define I2S_TCSR_TE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
+
+/*! @name TCR1 - SAI Transmit Configuration 1 Register */
+#define I2S_TCR1_TFW_MASK                        (0x7U)
+#define I2S_TCR1_TFW_SHIFT                       (0U)
+#define I2S_TCR1_TFW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
+
+/*! @name TCR2 - SAI Transmit Configuration 2 Register */
+#define I2S_TCR2_DIV_MASK                        (0xFFU)
+#define I2S_TCR2_DIV_SHIFT                       (0U)
+#define I2S_TCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
+#define I2S_TCR2_BCD_MASK                        (0x1000000U)
+#define I2S_TCR2_BCD_SHIFT                       (24U)
+#define I2S_TCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
+#define I2S_TCR2_BCP_MASK                        (0x2000000U)
+#define I2S_TCR2_BCP_SHIFT                       (25U)
+#define I2S_TCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
+#define I2S_TCR2_MSEL_MASK                       (0xC000000U)
+#define I2S_TCR2_MSEL_SHIFT                      (26U)
+#define I2S_TCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
+#define I2S_TCR2_BCI_MASK                        (0x10000000U)
+#define I2S_TCR2_BCI_SHIFT                       (28U)
+#define I2S_TCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
+#define I2S_TCR2_BCS_MASK                        (0x20000000U)
+#define I2S_TCR2_BCS_SHIFT                       (29U)
+#define I2S_TCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
+#define I2S_TCR2_SYNC_MASK                       (0xC0000000U)
+#define I2S_TCR2_SYNC_SHIFT                      (30U)
+#define I2S_TCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
+
+/*! @name TCR3 - SAI Transmit Configuration 3 Register */
+#define I2S_TCR3_WDFL_MASK                       (0x1FU)
+#define I2S_TCR3_WDFL_SHIFT                      (0U)
+#define I2S_TCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
+#define I2S_TCR3_TCE_MASK                        (0x30000U)
+#define I2S_TCR3_TCE_SHIFT                       (16U)
+#define I2S_TCR3_TCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
+#define I2S_TCR3_CFR_MASK                        (0x3000000U)
+#define I2S_TCR3_CFR_SHIFT                       (24U)
+#define I2S_TCR3_CFR(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)
+
+/*! @name TCR4 - SAI Transmit Configuration 4 Register */
+#define I2S_TCR4_FSD_MASK                        (0x1U)
+#define I2S_TCR4_FSD_SHIFT                       (0U)
+#define I2S_TCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
+#define I2S_TCR4_FSP_MASK                        (0x2U)
+#define I2S_TCR4_FSP_SHIFT                       (1U)
+#define I2S_TCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
+#define I2S_TCR4_ONDEM_MASK                      (0x4U)
+#define I2S_TCR4_ONDEM_SHIFT                     (2U)
+#define I2S_TCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
+#define I2S_TCR4_FSE_MASK                        (0x8U)
+#define I2S_TCR4_FSE_SHIFT                       (3U)
+#define I2S_TCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
+#define I2S_TCR4_MF_MASK                         (0x10U)
+#define I2S_TCR4_MF_SHIFT                        (4U)
+#define I2S_TCR4_MF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
+#define I2S_TCR4_SYWD_MASK                       (0x1F00U)
+#define I2S_TCR4_SYWD_SHIFT                      (8U)
+#define I2S_TCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
+#define I2S_TCR4_FRSZ_MASK                       (0x1F0000U)
+#define I2S_TCR4_FRSZ_SHIFT                      (16U)
+#define I2S_TCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
+#define I2S_TCR4_FPACK_MASK                      (0x3000000U)
+#define I2S_TCR4_FPACK_SHIFT                     (24U)
+#define I2S_TCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
+#define I2S_TCR4_FCOMB_MASK                      (0xC000000U)
+#define I2S_TCR4_FCOMB_SHIFT                     (26U)
+#define I2S_TCR4_FCOMB(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
+#define I2S_TCR4_FCONT_MASK                      (0x10000000U)
+#define I2S_TCR4_FCONT_SHIFT                     (28U)
+#define I2S_TCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
+
+/*! @name TCR5 - SAI Transmit Configuration 5 Register */
+#define I2S_TCR5_FBT_MASK                        (0x1F00U)
+#define I2S_TCR5_FBT_SHIFT                       (8U)
+#define I2S_TCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
+#define I2S_TCR5_W0W_MASK                        (0x1F0000U)
+#define I2S_TCR5_W0W_SHIFT                       (16U)
+#define I2S_TCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
+#define I2S_TCR5_WNW_MASK                        (0x1F000000U)
+#define I2S_TCR5_WNW_SHIFT                       (24U)
+#define I2S_TCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
+
+/*! @name TDR - SAI Transmit Data Register */
+#define I2S_TDR_TDR_MASK                         (0xFFFFFFFFU)
+#define I2S_TDR_TDR_SHIFT                        (0U)
+#define I2S_TDR_TDR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
+
+/* The count of I2S_TDR */
+#define I2S_TDR_COUNT                            (2U)
+
+/*! @name TFR - SAI Transmit FIFO Register */
+#define I2S_TFR_RFP_MASK                         (0xFU)
+#define I2S_TFR_RFP_SHIFT                        (0U)
+#define I2S_TFR_RFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
+#define I2S_TFR_WFP_MASK                         (0xF0000U)
+#define I2S_TFR_WFP_SHIFT                        (16U)
+#define I2S_TFR_WFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
+#define I2S_TFR_WCP_MASK                         (0x80000000U)
+#define I2S_TFR_WCP_SHIFT                        (31U)
+#define I2S_TFR_WCP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
+
+/* The count of I2S_TFR */
+#define I2S_TFR_COUNT                            (2U)
+
+/*! @name TMR - SAI Transmit Mask Register */
+#define I2S_TMR_TWM_MASK                         (0xFFFFFFFFU)
+#define I2S_TMR_TWM_SHIFT                        (0U)
+#define I2S_TMR_TWM(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
+
+/*! @name RCSR - SAI Receive Control Register */
+#define I2S_RCSR_FRDE_MASK                       (0x1U)
+#define I2S_RCSR_FRDE_SHIFT                      (0U)
+#define I2S_RCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
+#define I2S_RCSR_FWDE_MASK                       (0x2U)
+#define I2S_RCSR_FWDE_SHIFT                      (1U)
+#define I2S_RCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
+#define I2S_RCSR_FRIE_MASK                       (0x100U)
+#define I2S_RCSR_FRIE_SHIFT                      (8U)
+#define I2S_RCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
+#define I2S_RCSR_FWIE_MASK                       (0x200U)
+#define I2S_RCSR_FWIE_SHIFT                      (9U)
+#define I2S_RCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
+#define I2S_RCSR_FEIE_MASK                       (0x400U)
+#define I2S_RCSR_FEIE_SHIFT                      (10U)
+#define I2S_RCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
+#define I2S_RCSR_SEIE_MASK                       (0x800U)
+#define I2S_RCSR_SEIE_SHIFT                      (11U)
+#define I2S_RCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
+#define I2S_RCSR_WSIE_MASK                       (0x1000U)
+#define I2S_RCSR_WSIE_SHIFT                      (12U)
+#define I2S_RCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
+#define I2S_RCSR_FRF_MASK                        (0x10000U)
+#define I2S_RCSR_FRF_SHIFT                       (16U)
+#define I2S_RCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
+#define I2S_RCSR_FWF_MASK                        (0x20000U)
+#define I2S_RCSR_FWF_SHIFT                       (17U)
+#define I2S_RCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
+#define I2S_RCSR_FEF_MASK                        (0x40000U)
+#define I2S_RCSR_FEF_SHIFT                       (18U)
+#define I2S_RCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
+#define I2S_RCSR_SEF_MASK                        (0x80000U)
+#define I2S_RCSR_SEF_SHIFT                       (19U)
+#define I2S_RCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
+#define I2S_RCSR_WSF_MASK                        (0x100000U)
+#define I2S_RCSR_WSF_SHIFT                       (20U)
+#define I2S_RCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
+#define I2S_RCSR_SR_MASK                         (0x1000000U)
+#define I2S_RCSR_SR_SHIFT                        (24U)
+#define I2S_RCSR_SR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
+#define I2S_RCSR_FR_MASK                         (0x2000000U)
+#define I2S_RCSR_FR_SHIFT                        (25U)
+#define I2S_RCSR_FR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
+#define I2S_RCSR_BCE_MASK                        (0x10000000U)
+#define I2S_RCSR_BCE_SHIFT                       (28U)
+#define I2S_RCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
+#define I2S_RCSR_DBGE_MASK                       (0x20000000U)
+#define I2S_RCSR_DBGE_SHIFT                      (29U)
+#define I2S_RCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
+#define I2S_RCSR_STOPE_MASK                      (0x40000000U)
+#define I2S_RCSR_STOPE_SHIFT                     (30U)
+#define I2S_RCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
+#define I2S_RCSR_RE_MASK                         (0x80000000U)
+#define I2S_RCSR_RE_SHIFT                        (31U)
+#define I2S_RCSR_RE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
+
+/*! @name RCR1 - SAI Receive Configuration 1 Register */
+#define I2S_RCR1_RFW_MASK                        (0x7U)
+#define I2S_RCR1_RFW_SHIFT                       (0U)
+#define I2S_RCR1_RFW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
+
+/*! @name RCR2 - SAI Receive Configuration 2 Register */
+#define I2S_RCR2_DIV_MASK                        (0xFFU)
+#define I2S_RCR2_DIV_SHIFT                       (0U)
+#define I2S_RCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
+#define I2S_RCR2_BCD_MASK                        (0x1000000U)
+#define I2S_RCR2_BCD_SHIFT                       (24U)
+#define I2S_RCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
+#define I2S_RCR2_BCP_MASK                        (0x2000000U)
+#define I2S_RCR2_BCP_SHIFT                       (25U)
+#define I2S_RCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
+#define I2S_RCR2_MSEL_MASK                       (0xC000000U)
+#define I2S_RCR2_MSEL_SHIFT                      (26U)
+#define I2S_RCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
+#define I2S_RCR2_BCI_MASK                        (0x10000000U)
+#define I2S_RCR2_BCI_SHIFT                       (28U)
+#define I2S_RCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
+#define I2S_RCR2_BCS_MASK                        (0x20000000U)
+#define I2S_RCR2_BCS_SHIFT                       (29U)
+#define I2S_RCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
+#define I2S_RCR2_SYNC_MASK                       (0xC0000000U)
+#define I2S_RCR2_SYNC_SHIFT                      (30U)
+#define I2S_RCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
+
+/*! @name RCR3 - SAI Receive Configuration 3 Register */
+#define I2S_RCR3_WDFL_MASK                       (0x1FU)
+#define I2S_RCR3_WDFL_SHIFT                      (0U)
+#define I2S_RCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
+#define I2S_RCR3_RCE_MASK                        (0x30000U)
+#define I2S_RCR3_RCE_SHIFT                       (16U)
+#define I2S_RCR3_RCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
+#define I2S_RCR3_CFR_MASK                        (0x3000000U)
+#define I2S_RCR3_CFR_SHIFT                       (24U)
+#define I2S_RCR3_CFR(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)
+
+/*! @name RCR4 - SAI Receive Configuration 4 Register */
+#define I2S_RCR4_FSD_MASK                        (0x1U)
+#define I2S_RCR4_FSD_SHIFT                       (0U)
+#define I2S_RCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
+#define I2S_RCR4_FSP_MASK                        (0x2U)
+#define I2S_RCR4_FSP_SHIFT                       (1U)
+#define I2S_RCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
+#define I2S_RCR4_ONDEM_MASK                      (0x4U)
+#define I2S_RCR4_ONDEM_SHIFT                     (2U)
+#define I2S_RCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
+#define I2S_RCR4_FSE_MASK                        (0x8U)
+#define I2S_RCR4_FSE_SHIFT                       (3U)
+#define I2S_RCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
+#define I2S_RCR4_MF_MASK                         (0x10U)
+#define I2S_RCR4_MF_SHIFT                        (4U)
+#define I2S_RCR4_MF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
+#define I2S_RCR4_SYWD_MASK                       (0x1F00U)
+#define I2S_RCR4_SYWD_SHIFT                      (8U)
+#define I2S_RCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
+#define I2S_RCR4_FRSZ_MASK                       (0x1F0000U)
+#define I2S_RCR4_FRSZ_SHIFT                      (16U)
+#define I2S_RCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
+#define I2S_RCR4_FPACK_MASK                      (0x3000000U)
+#define I2S_RCR4_FPACK_SHIFT                     (24U)
+#define I2S_RCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
+#define I2S_RCR4_FCOMB_MASK                      (0xC000000U)
+#define I2S_RCR4_FCOMB_SHIFT                     (26U)
+#define I2S_RCR4_FCOMB(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
+#define I2S_RCR4_FCONT_MASK                      (0x10000000U)
+#define I2S_RCR4_FCONT_SHIFT                     (28U)
+#define I2S_RCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
+
+/*! @name RCR5 - SAI Receive Configuration 5 Register */
+#define I2S_RCR5_FBT_MASK                        (0x1F00U)
+#define I2S_RCR5_FBT_SHIFT                       (8U)
+#define I2S_RCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
+#define I2S_RCR5_W0W_MASK                        (0x1F0000U)
+#define I2S_RCR5_W0W_SHIFT                       (16U)
+#define I2S_RCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
+#define I2S_RCR5_WNW_MASK                        (0x1F000000U)
+#define I2S_RCR5_WNW_SHIFT                       (24U)
+#define I2S_RCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
+
+/*! @name RDR - SAI Receive Data Register */
+#define I2S_RDR_RDR_MASK                         (0xFFFFFFFFU)
+#define I2S_RDR_RDR_SHIFT                        (0U)
+#define I2S_RDR_RDR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
+
+/* The count of I2S_RDR */
+#define I2S_RDR_COUNT                            (2U)
+
+/*! @name RFR - SAI Receive FIFO Register */
+#define I2S_RFR_RFP_MASK                         (0xFU)
+#define I2S_RFR_RFP_SHIFT                        (0U)
+#define I2S_RFR_RFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
+#define I2S_RFR_RCP_MASK                         (0x8000U)
+#define I2S_RFR_RCP_SHIFT                        (15U)
+#define I2S_RFR_RCP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
+#define I2S_RFR_WFP_MASK                         (0xF0000U)
+#define I2S_RFR_WFP_SHIFT                        (16U)
+#define I2S_RFR_WFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
+
+/* The count of I2S_RFR */
+#define I2S_RFR_COUNT                            (2U)
+
+/*! @name RMR - SAI Receive Mask Register */
+#define I2S_RMR_RWM_MASK                         (0xFFFFFFFFU)
+#define I2S_RMR_RWM_SHIFT                        (0U)
+#define I2S_RMR_RWM(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
+
+/*! @name MCR - SAI MCLK Control Register */
+#define I2S_MCR_MICS_MASK                        (0x3000000U)
+#define I2S_MCR_MICS_SHIFT                       (24U)
+#define I2S_MCR_MICS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)
+#define I2S_MCR_MOE_MASK                         (0x40000000U)
+#define I2S_MCR_MOE_SHIFT                        (30U)
+#define I2S_MCR_MOE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
+#define I2S_MCR_DUF_MASK                         (0x80000000U)
+#define I2S_MCR_DUF_SHIFT                        (31U)
+#define I2S_MCR_DUF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)
+
+/*! @name MDR - SAI MCLK Divide Register */
+#define I2S_MDR_DIVIDE_MASK                      (0xFFFU)
+#define I2S_MDR_DIVIDE_SHIFT                     (0U)
+#define I2S_MDR_DIVIDE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK)
+#define I2S_MDR_FRACT_MASK                       (0xFF000U)
+#define I2S_MDR_FRACT_SHIFT                      (12U)
+#define I2S_MDR_FRACT(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/** Peripheral I2S0 base address */
+#define I2S0_BASE                                (0x4002F000u)
+/** Peripheral I2S0 base pointer */
+#define I2S0                                     ((I2S_Type *)I2S0_BASE)
+/** Array initializer of I2S peripheral base addresses */
+#define I2S_BASE_ADDRS                           { I2S0_BASE }
+/** Array initializer of I2S peripheral base pointers */
+#define I2S_BASE_PTRS                            { I2S0 }
+/** Interrupt vectors for the I2S peripheral type */
+#define I2S_RX_IRQS                              { I2S0_Rx_IRQn }
+#define I2S_TX_IRQS                              { I2S0_Tx_IRQn }
+
+/*!
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LLWU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
+ * @{
+ */
+
+/** LLWU - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t PE1;                                /**< LLWU Pin Enable 1 register, offset: 0x0 */
+  __IO uint8_t PE2;                                /**< LLWU Pin Enable 2 register, offset: 0x1 */
+  __IO uint8_t PE3;                                /**< LLWU Pin Enable 3 register, offset: 0x2 */
+  __IO uint8_t PE4;                                /**< LLWU Pin Enable 4 register, offset: 0x3 */
+  __IO uint8_t PE5;                                /**< LLWU Pin Enable 5 register, offset: 0x4 */
+  __IO uint8_t PE6;                                /**< LLWU Pin Enable 6 register, offset: 0x5 */
+  __IO uint8_t PE7;                                /**< LLWU Pin Enable 7 register, offset: 0x6 */
+  __IO uint8_t PE8;                                /**< LLWU Pin Enable 8 register, offset: 0x7 */
+  __IO uint8_t ME;                                 /**< LLWU Module Enable register, offset: 0x8 */
+  __IO uint8_t PF1;                                /**< LLWU Pin Flag 1 register, offset: 0x9 */
+  __IO uint8_t PF2;                                /**< LLWU Pin Flag 2 register, offset: 0xA */
+  __IO uint8_t PF3;                                /**< LLWU Pin Flag 3 register, offset: 0xB */
+  __IO uint8_t PF4;                                /**< LLWU Pin Flag 4 register, offset: 0xC */
+  __I  uint8_t MF5;                                /**< LLWU Module Flag 5 register, offset: 0xD */
+  __IO uint8_t FILT1;                              /**< LLWU Pin Filter 1 register, offset: 0xE */
+  __IO uint8_t FILT2;                              /**< LLWU Pin Filter 2 register, offset: 0xF */
+  __IO uint8_t FILT3;                              /**< LLWU Pin Filter 3 register, offset: 0x10 */
+  __IO uint8_t FILT4;                              /**< LLWU Pin Filter 4 register, offset: 0x11 */
+} LLWU_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LLWU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LLWU_Register_Masks LLWU Register Masks
+ * @{
+ */
+
+/*! @name PE1 - LLWU Pin Enable 1 register */
+#define LLWU_PE1_WUPE0_MASK                      (0x3U)
+#define LLWU_PE1_WUPE0_SHIFT                     (0U)
+#define LLWU_PE1_WUPE0(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE1_MASK                      (0xCU)
+#define LLWU_PE1_WUPE1_SHIFT                     (2U)
+#define LLWU_PE1_WUPE1(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE2_MASK                      (0x30U)
+#define LLWU_PE1_WUPE2_SHIFT                     (4U)
+#define LLWU_PE1_WUPE2(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE3_MASK                      (0xC0U)
+#define LLWU_PE1_WUPE3_SHIFT                     (6U)
+#define LLWU_PE1_WUPE3(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
+
+/*! @name PE2 - LLWU Pin Enable 2 register */
+#define LLWU_PE2_WUPE4_MASK                      (0x3U)
+#define LLWU_PE2_WUPE4_SHIFT                     (0U)
+#define LLWU_PE2_WUPE4(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE5_MASK                      (0xCU)
+#define LLWU_PE2_WUPE5_SHIFT                     (2U)
+#define LLWU_PE2_WUPE5(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE6_MASK                      (0x30U)
+#define LLWU_PE2_WUPE6_SHIFT                     (4U)
+#define LLWU_PE2_WUPE6(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE7_MASK                      (0xC0U)
+#define LLWU_PE2_WUPE7_SHIFT                     (6U)
+#define LLWU_PE2_WUPE7(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
+
+/*! @name PE3 - LLWU Pin Enable 3 register */
+#define LLWU_PE3_WUPE8_MASK                      (0x3U)
+#define LLWU_PE3_WUPE8_SHIFT                     (0U)
+#define LLWU_PE3_WUPE8(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE9_MASK                      (0xCU)
+#define LLWU_PE3_WUPE9_SHIFT                     (2U)
+#define LLWU_PE3_WUPE9(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE10_MASK                     (0x30U)
+#define LLWU_PE3_WUPE10_SHIFT                    (4U)
+#define LLWU_PE3_WUPE10(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE11_MASK                     (0xC0U)
+#define LLWU_PE3_WUPE11_SHIFT                    (6U)
+#define LLWU_PE3_WUPE11(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
+
+/*! @name PE4 - LLWU Pin Enable 4 register */
+#define LLWU_PE4_WUPE12_MASK                     (0x3U)
+#define LLWU_PE4_WUPE12_SHIFT                    (0U)
+#define LLWU_PE4_WUPE12(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE13_MASK                     (0xCU)
+#define LLWU_PE4_WUPE13_SHIFT                    (2U)
+#define LLWU_PE4_WUPE13(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE14_MASK                     (0x30U)
+#define LLWU_PE4_WUPE14_SHIFT                    (4U)
+#define LLWU_PE4_WUPE14(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE15_MASK                     (0xC0U)
+#define LLWU_PE4_WUPE15_SHIFT                    (6U)
+#define LLWU_PE4_WUPE15(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
+
+/*! @name PE5 - LLWU Pin Enable 5 register */
+#define LLWU_PE5_WUPE16_MASK                     (0x3U)
+#define LLWU_PE5_WUPE16_SHIFT                    (0U)
+#define LLWU_PE5_WUPE16(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE16_SHIFT)) & LLWU_PE5_WUPE16_MASK)
+#define LLWU_PE5_WUPE17_MASK                     (0xCU)
+#define LLWU_PE5_WUPE17_SHIFT                    (2U)
+#define LLWU_PE5_WUPE17(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE17_SHIFT)) & LLWU_PE5_WUPE17_MASK)
+#define LLWU_PE5_WUPE18_MASK                     (0x30U)
+#define LLWU_PE5_WUPE18_SHIFT                    (4U)
+#define LLWU_PE5_WUPE18(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE18_SHIFT)) & LLWU_PE5_WUPE18_MASK)
+#define LLWU_PE5_WUPE19_MASK                     (0xC0U)
+#define LLWU_PE5_WUPE19_SHIFT                    (6U)
+#define LLWU_PE5_WUPE19(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE19_SHIFT)) & LLWU_PE5_WUPE19_MASK)
+
+/*! @name PE6 - LLWU Pin Enable 6 register */
+#define LLWU_PE6_WUPE20_MASK                     (0x3U)
+#define LLWU_PE6_WUPE20_SHIFT                    (0U)
+#define LLWU_PE6_WUPE20(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE20_SHIFT)) & LLWU_PE6_WUPE20_MASK)
+#define LLWU_PE6_WUPE21_MASK                     (0xCU)
+#define LLWU_PE6_WUPE21_SHIFT                    (2U)
+#define LLWU_PE6_WUPE21(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE21_SHIFT)) & LLWU_PE6_WUPE21_MASK)
+#define LLWU_PE6_WUPE22_MASK                     (0x30U)
+#define LLWU_PE6_WUPE22_SHIFT                    (4U)
+#define LLWU_PE6_WUPE22(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE22_SHIFT)) & LLWU_PE6_WUPE22_MASK)
+#define LLWU_PE6_WUPE23_MASK                     (0xC0U)
+#define LLWU_PE6_WUPE23_SHIFT                    (6U)
+#define LLWU_PE6_WUPE23(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE23_SHIFT)) & LLWU_PE6_WUPE23_MASK)
+
+/*! @name PE7 - LLWU Pin Enable 7 register */
+#define LLWU_PE7_WUPE24_MASK                     (0x3U)
+#define LLWU_PE7_WUPE24_SHIFT                    (0U)
+#define LLWU_PE7_WUPE24(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE24_SHIFT)) & LLWU_PE7_WUPE24_MASK)
+#define LLWU_PE7_WUPE25_MASK                     (0xCU)
+#define LLWU_PE7_WUPE25_SHIFT                    (2U)
+#define LLWU_PE7_WUPE25(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE25_SHIFT)) & LLWU_PE7_WUPE25_MASK)
+#define LLWU_PE7_WUPE26_MASK                     (0x30U)
+#define LLWU_PE7_WUPE26_SHIFT                    (4U)
+#define LLWU_PE7_WUPE26(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE26_SHIFT)) & LLWU_PE7_WUPE26_MASK)
+#define LLWU_PE7_WUPE27_MASK                     (0xC0U)
+#define LLWU_PE7_WUPE27_SHIFT                    (6U)
+#define LLWU_PE7_WUPE27(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE27_SHIFT)) & LLWU_PE7_WUPE27_MASK)
+
+/*! @name PE8 - LLWU Pin Enable 8 register */
+#define LLWU_PE8_WUPE28_MASK                     (0x3U)
+#define LLWU_PE8_WUPE28_SHIFT                    (0U)
+#define LLWU_PE8_WUPE28(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE28_SHIFT)) & LLWU_PE8_WUPE28_MASK)
+#define LLWU_PE8_WUPE29_MASK                     (0xCU)
+#define LLWU_PE8_WUPE29_SHIFT                    (2U)
+#define LLWU_PE8_WUPE29(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE29_SHIFT)) & LLWU_PE8_WUPE29_MASK)
+#define LLWU_PE8_WUPE30_MASK                     (0x30U)
+#define LLWU_PE8_WUPE30_SHIFT                    (4U)
+#define LLWU_PE8_WUPE30(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE30_SHIFT)) & LLWU_PE8_WUPE30_MASK)
+#define LLWU_PE8_WUPE31_MASK                     (0xC0U)
+#define LLWU_PE8_WUPE31_SHIFT                    (6U)
+#define LLWU_PE8_WUPE31(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE31_SHIFT)) & LLWU_PE8_WUPE31_MASK)
+
+/*! @name ME - LLWU Module Enable register */
+#define LLWU_ME_WUME0_MASK                       (0x1U)
+#define LLWU_ME_WUME0_SHIFT                      (0U)
+#define LLWU_ME_WUME0(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
+#define LLWU_ME_WUME1_MASK                       (0x2U)
+#define LLWU_ME_WUME1_SHIFT                      (1U)
+#define LLWU_ME_WUME1(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
+#define LLWU_ME_WUME2_MASK                       (0x4U)
+#define LLWU_ME_WUME2_SHIFT                      (2U)
+#define LLWU_ME_WUME2(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
+#define LLWU_ME_WUME3_MASK                       (0x8U)
+#define LLWU_ME_WUME3_SHIFT                      (3U)
+#define LLWU_ME_WUME3(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
+#define LLWU_ME_WUME4_MASK                       (0x10U)
+#define LLWU_ME_WUME4_SHIFT                      (4U)
+#define LLWU_ME_WUME4(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
+#define LLWU_ME_WUME5_MASK                       (0x20U)
+#define LLWU_ME_WUME5_SHIFT                      (5U)
+#define LLWU_ME_WUME5(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
+#define LLWU_ME_WUME6_MASK                       (0x40U)
+#define LLWU_ME_WUME6_SHIFT                      (6U)
+#define LLWU_ME_WUME6(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
+#define LLWU_ME_WUME7_MASK                       (0x80U)
+#define LLWU_ME_WUME7_SHIFT                      (7U)
+#define LLWU_ME_WUME7(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
+
+/*! @name PF1 - LLWU Pin Flag 1 register */
+#define LLWU_PF1_WUF0_MASK                       (0x1U)
+#define LLWU_PF1_WUF0_SHIFT                      (0U)
+#define LLWU_PF1_WUF0(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF0_SHIFT)) & LLWU_PF1_WUF0_MASK)
+#define LLWU_PF1_WUF1_MASK                       (0x2U)
+#define LLWU_PF1_WUF1_SHIFT                      (1U)
+#define LLWU_PF1_WUF1(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF1_SHIFT)) & LLWU_PF1_WUF1_MASK)
+#define LLWU_PF1_WUF2_MASK                       (0x4U)
+#define LLWU_PF1_WUF2_SHIFT                      (2U)
+#define LLWU_PF1_WUF2(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF2_SHIFT)) & LLWU_PF1_WUF2_MASK)
+#define LLWU_PF1_WUF3_MASK                       (0x8U)
+#define LLWU_PF1_WUF3_SHIFT                      (3U)
+#define LLWU_PF1_WUF3(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF3_SHIFT)) & LLWU_PF1_WUF3_MASK)
+#define LLWU_PF1_WUF4_MASK                       (0x10U)
+#define LLWU_PF1_WUF4_SHIFT                      (4U)
+#define LLWU_PF1_WUF4(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF4_SHIFT)) & LLWU_PF1_WUF4_MASK)
+#define LLWU_PF1_WUF5_MASK                       (0x20U)
+#define LLWU_PF1_WUF5_SHIFT                      (5U)
+#define LLWU_PF1_WUF5(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF5_SHIFT)) & LLWU_PF1_WUF5_MASK)
+#define LLWU_PF1_WUF6_MASK                       (0x40U)
+#define LLWU_PF1_WUF6_SHIFT                      (6U)
+#define LLWU_PF1_WUF6(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF6_SHIFT)) & LLWU_PF1_WUF6_MASK)
+#define LLWU_PF1_WUF7_MASK                       (0x80U)
+#define LLWU_PF1_WUF7_SHIFT                      (7U)
+#define LLWU_PF1_WUF7(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF7_SHIFT)) & LLWU_PF1_WUF7_MASK)
+
+/*! @name PF2 - LLWU Pin Flag 2 register */
+#define LLWU_PF2_WUF8_MASK                       (0x1U)
+#define LLWU_PF2_WUF8_SHIFT                      (0U)
+#define LLWU_PF2_WUF8(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF8_SHIFT)) & LLWU_PF2_WUF8_MASK)
+#define LLWU_PF2_WUF9_MASK                       (0x2U)
+#define LLWU_PF2_WUF9_SHIFT                      (1U)
+#define LLWU_PF2_WUF9(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF9_SHIFT)) & LLWU_PF2_WUF9_MASK)
+#define LLWU_PF2_WUF10_MASK                      (0x4U)
+#define LLWU_PF2_WUF10_SHIFT                     (2U)
+#define LLWU_PF2_WUF10(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF10_SHIFT)) & LLWU_PF2_WUF10_MASK)
+#define LLWU_PF2_WUF11_MASK                      (0x8U)
+#define LLWU_PF2_WUF11_SHIFT                     (3U)
+#define LLWU_PF2_WUF11(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF11_SHIFT)) & LLWU_PF2_WUF11_MASK)
+#define LLWU_PF2_WUF12_MASK                      (0x10U)
+#define LLWU_PF2_WUF12_SHIFT                     (4U)
+#define LLWU_PF2_WUF12(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF12_SHIFT)) & LLWU_PF2_WUF12_MASK)
+#define LLWU_PF2_WUF13_MASK                      (0x20U)
+#define LLWU_PF2_WUF13_SHIFT                     (5U)
+#define LLWU_PF2_WUF13(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF13_SHIFT)) & LLWU_PF2_WUF13_MASK)
+#define LLWU_PF2_WUF14_MASK                      (0x40U)
+#define LLWU_PF2_WUF14_SHIFT                     (6U)
+#define LLWU_PF2_WUF14(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF14_SHIFT)) & LLWU_PF2_WUF14_MASK)
+#define LLWU_PF2_WUF15_MASK                      (0x80U)
+#define LLWU_PF2_WUF15_SHIFT                     (7U)
+#define LLWU_PF2_WUF15(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF15_SHIFT)) & LLWU_PF2_WUF15_MASK)
+
+/*! @name PF3 - LLWU Pin Flag 3 register */
+#define LLWU_PF3_WUF16_MASK                      (0x1U)
+#define LLWU_PF3_WUF16_SHIFT                     (0U)
+#define LLWU_PF3_WUF16(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF16_SHIFT)) & LLWU_PF3_WUF16_MASK)
+#define LLWU_PF3_WUF17_MASK                      (0x2U)
+#define LLWU_PF3_WUF17_SHIFT                     (1U)
+#define LLWU_PF3_WUF17(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF17_SHIFT)) & LLWU_PF3_WUF17_MASK)
+#define LLWU_PF3_WUF18_MASK                      (0x4U)
+#define LLWU_PF3_WUF18_SHIFT                     (2U)
+#define LLWU_PF3_WUF18(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF18_SHIFT)) & LLWU_PF3_WUF18_MASK)
+#define LLWU_PF3_WUF19_MASK                      (0x8U)
+#define LLWU_PF3_WUF19_SHIFT                     (3U)
+#define LLWU_PF3_WUF19(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF19_SHIFT)) & LLWU_PF3_WUF19_MASK)
+#define LLWU_PF3_WUF20_MASK                      (0x10U)
+#define LLWU_PF3_WUF20_SHIFT                     (4U)
+#define LLWU_PF3_WUF20(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF20_SHIFT)) & LLWU_PF3_WUF20_MASK)
+#define LLWU_PF3_WUF21_MASK                      (0x20U)
+#define LLWU_PF3_WUF21_SHIFT                     (5U)
+#define LLWU_PF3_WUF21(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF21_SHIFT)) & LLWU_PF3_WUF21_MASK)
+#define LLWU_PF3_WUF22_MASK                      (0x40U)
+#define LLWU_PF3_WUF22_SHIFT                     (6U)
+#define LLWU_PF3_WUF22(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF22_SHIFT)) & LLWU_PF3_WUF22_MASK)
+#define LLWU_PF3_WUF23_MASK                      (0x80U)
+#define LLWU_PF3_WUF23_SHIFT                     (7U)
+#define LLWU_PF3_WUF23(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF23_SHIFT)) & LLWU_PF3_WUF23_MASK)
+
+/*! @name PF4 - LLWU Pin Flag 4 register */
+#define LLWU_PF4_WUF24_MASK                      (0x1U)
+#define LLWU_PF4_WUF24_SHIFT                     (0U)
+#define LLWU_PF4_WUF24(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF24_SHIFT)) & LLWU_PF4_WUF24_MASK)
+#define LLWU_PF4_WUF25_MASK                      (0x2U)
+#define LLWU_PF4_WUF25_SHIFT                     (1U)
+#define LLWU_PF4_WUF25(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF25_SHIFT)) & LLWU_PF4_WUF25_MASK)
+#define LLWU_PF4_WUF26_MASK                      (0x4U)
+#define LLWU_PF4_WUF26_SHIFT                     (2U)
+#define LLWU_PF4_WUF26(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF26_SHIFT)) & LLWU_PF4_WUF26_MASK)
+#define LLWU_PF4_WUF27_MASK                      (0x8U)
+#define LLWU_PF4_WUF27_SHIFT                     (3U)
+#define LLWU_PF4_WUF27(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF27_SHIFT)) & LLWU_PF4_WUF27_MASK)
+#define LLWU_PF4_WUF28_MASK                      (0x10U)
+#define LLWU_PF4_WUF28_SHIFT                     (4U)
+#define LLWU_PF4_WUF28(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF28_SHIFT)) & LLWU_PF4_WUF28_MASK)
+#define LLWU_PF4_WUF29_MASK                      (0x20U)
+#define LLWU_PF4_WUF29_SHIFT                     (5U)
+#define LLWU_PF4_WUF29(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF29_SHIFT)) & LLWU_PF4_WUF29_MASK)
+#define LLWU_PF4_WUF30_MASK                      (0x40U)
+#define LLWU_PF4_WUF30_SHIFT                     (6U)
+#define LLWU_PF4_WUF30(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF30_SHIFT)) & LLWU_PF4_WUF30_MASK)
+#define LLWU_PF4_WUF31_MASK                      (0x80U)
+#define LLWU_PF4_WUF31_SHIFT                     (7U)
+#define LLWU_PF4_WUF31(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF31_SHIFT)) & LLWU_PF4_WUF31_MASK)
+
+/*! @name MF5 - LLWU Module Flag 5 register */
+#define LLWU_MF5_MWUF0_MASK                      (0x1U)
+#define LLWU_MF5_MWUF0_SHIFT                     (0U)
+#define LLWU_MF5_MWUF0(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF0_SHIFT)) & LLWU_MF5_MWUF0_MASK)
+#define LLWU_MF5_MWUF1_MASK                      (0x2U)
+#define LLWU_MF5_MWUF1_SHIFT                     (1U)
+#define LLWU_MF5_MWUF1(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF1_SHIFT)) & LLWU_MF5_MWUF1_MASK)
+#define LLWU_MF5_MWUF2_MASK                      (0x4U)
+#define LLWU_MF5_MWUF2_SHIFT                     (2U)
+#define LLWU_MF5_MWUF2(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF2_SHIFT)) & LLWU_MF5_MWUF2_MASK)
+#define LLWU_MF5_MWUF3_MASK                      (0x8U)
+#define LLWU_MF5_MWUF3_SHIFT                     (3U)
+#define LLWU_MF5_MWUF3(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF3_SHIFT)) & LLWU_MF5_MWUF3_MASK)
+#define LLWU_MF5_MWUF4_MASK                      (0x10U)
+#define LLWU_MF5_MWUF4_SHIFT                     (4U)
+#define LLWU_MF5_MWUF4(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF4_SHIFT)) & LLWU_MF5_MWUF4_MASK)
+#define LLWU_MF5_MWUF5_MASK                      (0x20U)
+#define LLWU_MF5_MWUF5_SHIFT                     (5U)
+#define LLWU_MF5_MWUF5(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF5_SHIFT)) & LLWU_MF5_MWUF5_MASK)
+#define LLWU_MF5_MWUF6_MASK                      (0x40U)
+#define LLWU_MF5_MWUF6_SHIFT                     (6U)
+#define LLWU_MF5_MWUF6(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF6_SHIFT)) & LLWU_MF5_MWUF6_MASK)
+#define LLWU_MF5_MWUF7_MASK                      (0x80U)
+#define LLWU_MF5_MWUF7_SHIFT                     (7U)
+#define LLWU_MF5_MWUF7(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF7_SHIFT)) & LLWU_MF5_MWUF7_MASK)
+
+/*! @name FILT1 - LLWU Pin Filter 1 register */
+#define LLWU_FILT1_FILTSEL_MASK                  (0x1FU)
+#define LLWU_FILT1_FILTSEL_SHIFT                 (0U)
+#define LLWU_FILT1_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTE_MASK                    (0x60U)
+#define LLWU_FILT1_FILTE_SHIFT                   (5U)
+#define LLWU_FILT1_FILTE(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTF_MASK                    (0x80U)
+#define LLWU_FILT1_FILTF_SHIFT                   (7U)
+#define LLWU_FILT1_FILTF(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
+
+/*! @name FILT2 - LLWU Pin Filter 2 register */
+#define LLWU_FILT2_FILTSEL_MASK                  (0x1FU)
+#define LLWU_FILT2_FILTSEL_SHIFT                 (0U)
+#define LLWU_FILT2_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTE_MASK                    (0x60U)
+#define LLWU_FILT2_FILTE_SHIFT                   (5U)
+#define LLWU_FILT2_FILTE(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTF_MASK                    (0x80U)
+#define LLWU_FILT2_FILTF_SHIFT                   (7U)
+#define LLWU_FILT2_FILTF(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
+
+/*! @name FILT3 - LLWU Pin Filter 3 register */
+#define LLWU_FILT3_FILTSEL_MASK                  (0x1FU)
+#define LLWU_FILT3_FILTSEL_SHIFT                 (0U)
+#define LLWU_FILT3_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTSEL_SHIFT)) & LLWU_FILT3_FILTSEL_MASK)
+#define LLWU_FILT3_FILTE_MASK                    (0x60U)
+#define LLWU_FILT3_FILTE_SHIFT                   (5U)
+#define LLWU_FILT3_FILTE(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTE_SHIFT)) & LLWU_FILT3_FILTE_MASK)
+#define LLWU_FILT3_FILTF_MASK                    (0x80U)
+#define LLWU_FILT3_FILTF_SHIFT                   (7U)
+#define LLWU_FILT3_FILTF(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTF_SHIFT)) & LLWU_FILT3_FILTF_MASK)
+
+/*! @name FILT4 - LLWU Pin Filter 4 register */
+#define LLWU_FILT4_FILTSEL_MASK                  (0x1FU)
+#define LLWU_FILT4_FILTSEL_SHIFT                 (0U)
+#define LLWU_FILT4_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTSEL_SHIFT)) & LLWU_FILT4_FILTSEL_MASK)
+#define LLWU_FILT4_FILTE_MASK                    (0x60U)
+#define LLWU_FILT4_FILTE_SHIFT                   (5U)
+#define LLWU_FILT4_FILTE(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTE_SHIFT)) & LLWU_FILT4_FILTE_MASK)
+#define LLWU_FILT4_FILTF_MASK                    (0x80U)
+#define LLWU_FILT4_FILTF_SHIFT                   (7U)
+#define LLWU_FILT4_FILTF(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTF_SHIFT)) & LLWU_FILT4_FILTF_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group LLWU_Register_Masks */
+
+
+/* LLWU - Peripheral instance base addresses */
+/** Peripheral LLWU base address */
+#define LLWU_BASE                                (0x4007C000u)
+/** Peripheral LLWU base pointer */
+#define LLWU                                     ((LLWU_Type *)LLWU_BASE)
+/** Array initializer of LLWU peripheral base addresses */
+#define LLWU_BASE_ADDRS                          { LLWU_BASE }
+/** Array initializer of LLWU peripheral base pointers */
+#define LLWU_BASE_PTRS                           { LLWU }
+/** Interrupt vectors for the LLWU peripheral type */
+#define LLWU_IRQS                                { LLWU_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LLWU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LMEM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LMEM_Peripheral_Access_Layer LMEM Peripheral Access Layer
+ * @{
+ */
+
+/** LMEM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PCCCR;                             /**< Cache control register, offset: 0x0 */
+  __IO uint32_t PCCLCR;                            /**< Cache line control register, offset: 0x4 */
+  __IO uint32_t PCCSAR;                            /**< Cache search address register, offset: 0x8 */
+  __IO uint32_t PCCCVR;                            /**< Cache read/write value register, offset: 0xC */
+       uint8_t RESERVED_0[16];
+  __IO uint32_t PCCRMR;                            /**< Cache regions mode register, offset: 0x20 */
+} LMEM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LMEM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LMEM_Register_Masks LMEM Register Masks
+ * @{
+ */
+
+/*! @name PCCCR - Cache control register */
+#define LMEM_PCCCR_ENCACHE_MASK                  (0x1U)
+#define LMEM_PCCCR_ENCACHE_SHIFT                 (0U)
+#define LMEM_PCCCR_ENCACHE(x)                    (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENCACHE_SHIFT)) & LMEM_PCCCR_ENCACHE_MASK)
+#define LMEM_PCCCR_ENWRBUF_MASK                  (0x2U)
+#define LMEM_PCCCR_ENWRBUF_SHIFT                 (1U)
+#define LMEM_PCCCR_ENWRBUF(x)                    (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENWRBUF_SHIFT)) & LMEM_PCCCR_ENWRBUF_MASK)
+#define LMEM_PCCCR_PCCR2_MASK                    (0x4U)
+#define LMEM_PCCCR_PCCR2_SHIFT                   (2U)
+#define LMEM_PCCCR_PCCR2(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR2_SHIFT)) & LMEM_PCCCR_PCCR2_MASK)
+#define LMEM_PCCCR_PCCR3_MASK                    (0x8U)
+#define LMEM_PCCCR_PCCR3_SHIFT                   (3U)
+#define LMEM_PCCCR_PCCR3(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR3_SHIFT)) & LMEM_PCCCR_PCCR3_MASK)
+#define LMEM_PCCCR_INVW0_MASK                    (0x1000000U)
+#define LMEM_PCCCR_INVW0_SHIFT                   (24U)
+#define LMEM_PCCCR_INVW0(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW0_SHIFT)) & LMEM_PCCCR_INVW0_MASK)
+#define LMEM_PCCCR_PUSHW0_MASK                   (0x2000000U)
+#define LMEM_PCCCR_PUSHW0_SHIFT                  (25U)
+#define LMEM_PCCCR_PUSHW0(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW0_SHIFT)) & LMEM_PCCCR_PUSHW0_MASK)
+#define LMEM_PCCCR_INVW1_MASK                    (0x4000000U)
+#define LMEM_PCCCR_INVW1_SHIFT                   (26U)
+#define LMEM_PCCCR_INVW1(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW1_SHIFT)) & LMEM_PCCCR_INVW1_MASK)
+#define LMEM_PCCCR_PUSHW1_MASK                   (0x8000000U)
+#define LMEM_PCCCR_PUSHW1_SHIFT                  (27U)
+#define LMEM_PCCCR_PUSHW1(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW1_SHIFT)) & LMEM_PCCCR_PUSHW1_MASK)
+#define LMEM_PCCCR_GO_MASK                       (0x80000000U)
+#define LMEM_PCCCR_GO_SHIFT                      (31U)
+#define LMEM_PCCCR_GO(x)                         (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_GO_SHIFT)) & LMEM_PCCCR_GO_MASK)
+
+/*! @name PCCLCR - Cache line control register */
+#define LMEM_PCCLCR_LGO_MASK                     (0x1U)
+#define LMEM_PCCLCR_LGO_SHIFT                    (0U)
+#define LMEM_PCCLCR_LGO(x)                       (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LGO_SHIFT)) & LMEM_PCCLCR_LGO_MASK)
+#define LMEM_PCCLCR_CACHEADDR_MASK               (0xFFCU)
+#define LMEM_PCCLCR_CACHEADDR_SHIFT              (2U)
+#define LMEM_PCCLCR_CACHEADDR(x)                 (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_CACHEADDR_SHIFT)) & LMEM_PCCLCR_CACHEADDR_MASK)
+#define LMEM_PCCLCR_WSEL_MASK                    (0x4000U)
+#define LMEM_PCCLCR_WSEL_SHIFT                   (14U)
+#define LMEM_PCCLCR_WSEL(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_WSEL_SHIFT)) & LMEM_PCCLCR_WSEL_MASK)
+#define LMEM_PCCLCR_TDSEL_MASK                   (0x10000U)
+#define LMEM_PCCLCR_TDSEL_SHIFT                  (16U)
+#define LMEM_PCCLCR_TDSEL(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_TDSEL_SHIFT)) & LMEM_PCCLCR_TDSEL_MASK)
+#define LMEM_PCCLCR_LCIVB_MASK                   (0x100000U)
+#define LMEM_PCCLCR_LCIVB_SHIFT                  (20U)
+#define LMEM_PCCLCR_LCIVB(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIVB_SHIFT)) & LMEM_PCCLCR_LCIVB_MASK)
+#define LMEM_PCCLCR_LCIMB_MASK                   (0x200000U)
+#define LMEM_PCCLCR_LCIMB_SHIFT                  (21U)
+#define LMEM_PCCLCR_LCIMB(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIMB_SHIFT)) & LMEM_PCCLCR_LCIMB_MASK)
+#define LMEM_PCCLCR_LCWAY_MASK                   (0x400000U)
+#define LMEM_PCCLCR_LCWAY_SHIFT                  (22U)
+#define LMEM_PCCLCR_LCWAY(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCWAY_SHIFT)) & LMEM_PCCLCR_LCWAY_MASK)
+#define LMEM_PCCLCR_LCMD_MASK                    (0x3000000U)
+#define LMEM_PCCLCR_LCMD_SHIFT                   (24U)
+#define LMEM_PCCLCR_LCMD(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCMD_SHIFT)) & LMEM_PCCLCR_LCMD_MASK)
+#define LMEM_PCCLCR_LADSEL_MASK                  (0x4000000U)
+#define LMEM_PCCLCR_LADSEL_SHIFT                 (26U)
+#define LMEM_PCCLCR_LADSEL(x)                    (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LADSEL_SHIFT)) & LMEM_PCCLCR_LADSEL_MASK)
+#define LMEM_PCCLCR_LACC_MASK                    (0x8000000U)
+#define LMEM_PCCLCR_LACC_SHIFT                   (27U)
+#define LMEM_PCCLCR_LACC(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LACC_SHIFT)) & LMEM_PCCLCR_LACC_MASK)
+
+/*! @name PCCSAR - Cache search address register */
+#define LMEM_PCCSAR_LGO_MASK                     (0x1U)
+#define LMEM_PCCSAR_LGO_SHIFT                    (0U)
+#define LMEM_PCCSAR_LGO(x)                       (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_LGO_SHIFT)) & LMEM_PCCSAR_LGO_MASK)
+#define LMEM_PCCSAR_PHYADDR_MASK                 (0xFFFFFFFCU)
+#define LMEM_PCCSAR_PHYADDR_SHIFT                (2U)
+#define LMEM_PCCSAR_PHYADDR(x)                   (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK)
+
+/*! @name PCCCVR - Cache read/write value register */
+#define LMEM_PCCCVR_DATA_MASK                    (0xFFFFFFFFU)
+#define LMEM_PCCCVR_DATA_SHIFT                   (0U)
+#define LMEM_PCCCVR_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCVR_DATA_SHIFT)) & LMEM_PCCCVR_DATA_MASK)
+
+/*! @name PCCRMR - Cache regions mode register */
+#define LMEM_PCCRMR_R15_MASK                     (0x3U)
+#define LMEM_PCCRMR_R15_SHIFT                    (0U)
+#define LMEM_PCCRMR_R15(x)                       (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R15_SHIFT)) & LMEM_PCCRMR_R15_MASK)
+#define LMEM_PCCRMR_R14_MASK                     (0xCU)
+#define LMEM_PCCRMR_R14_SHIFT                    (2U)
+#define LMEM_PCCRMR_R14(x)                       (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R14_SHIFT)) & LMEM_PCCRMR_R14_MASK)
+#define LMEM_PCCRMR_R13_MASK                     (0x30U)
+#define LMEM_PCCRMR_R13_SHIFT                    (4U)
+#define LMEM_PCCRMR_R13(x)                       (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R13_SHIFT)) & LMEM_PCCRMR_R13_MASK)
+#define LMEM_PCCRMR_R12_MASK                     (0xC0U)
+#define LMEM_PCCRMR_R12_SHIFT                    (6U)
+#define LMEM_PCCRMR_R12(x)                       (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R12_SHIFT)) & LMEM_PCCRMR_R12_MASK)
+#define LMEM_PCCRMR_R11_MASK                     (0x300U)
+#define LMEM_PCCRMR_R11_SHIFT                    (8U)
+#define LMEM_PCCRMR_R11(x)                       (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R11_SHIFT)) & LMEM_PCCRMR_R11_MASK)
+#define LMEM_PCCRMR_R10_MASK                     (0xC00U)
+#define LMEM_PCCRMR_R10_SHIFT                    (10U)
+#define LMEM_PCCRMR_R10(x)                       (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R10_SHIFT)) & LMEM_PCCRMR_R10_MASK)
+#define LMEM_PCCRMR_R9_MASK                      (0x3000U)
+#define LMEM_PCCRMR_R9_SHIFT                     (12U)
+#define LMEM_PCCRMR_R9(x)                        (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R9_SHIFT)) & LMEM_PCCRMR_R9_MASK)
+#define LMEM_PCCRMR_R8_MASK                      (0xC000U)
+#define LMEM_PCCRMR_R8_SHIFT                     (14U)
+#define LMEM_PCCRMR_R8(x)                        (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R8_SHIFT)) & LMEM_PCCRMR_R8_MASK)
+#define LMEM_PCCRMR_R7_MASK                      (0x30000U)
+#define LMEM_PCCRMR_R7_SHIFT                     (16U)
+#define LMEM_PCCRMR_R7(x)                        (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R7_SHIFT)) & LMEM_PCCRMR_R7_MASK)
+#define LMEM_PCCRMR_R6_MASK                      (0xC0000U)
+#define LMEM_PCCRMR_R6_SHIFT                     (18U)
+#define LMEM_PCCRMR_R6(x)                        (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R6_SHIFT)) & LMEM_PCCRMR_R6_MASK)
+#define LMEM_PCCRMR_R5_MASK                      (0x300000U)
+#define LMEM_PCCRMR_R5_SHIFT                     (20U)
+#define LMEM_PCCRMR_R5(x)                        (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R5_SHIFT)) & LMEM_PCCRMR_R5_MASK)
+#define LMEM_PCCRMR_R4_MASK                      (0xC00000U)
+#define LMEM_PCCRMR_R4_SHIFT                     (22U)
+#define LMEM_PCCRMR_R4(x)                        (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R4_SHIFT)) & LMEM_PCCRMR_R4_MASK)
+#define LMEM_PCCRMR_R3_MASK                      (0x3000000U)
+#define LMEM_PCCRMR_R3_SHIFT                     (24U)
+#define LMEM_PCCRMR_R3(x)                        (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R3_SHIFT)) & LMEM_PCCRMR_R3_MASK)
+#define LMEM_PCCRMR_R2_MASK                      (0xC000000U)
+#define LMEM_PCCRMR_R2_SHIFT                     (26U)
+#define LMEM_PCCRMR_R2(x)                        (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R2_SHIFT)) & LMEM_PCCRMR_R2_MASK)
+#define LMEM_PCCRMR_R1_MASK                      (0x30000000U)
+#define LMEM_PCCRMR_R1_SHIFT                     (28U)
+#define LMEM_PCCRMR_R1(x)                        (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R1_SHIFT)) & LMEM_PCCRMR_R1_MASK)
+#define LMEM_PCCRMR_R0_MASK                      (0xC0000000U)
+#define LMEM_PCCRMR_R0_SHIFT                     (30U)
+#define LMEM_PCCRMR_R0(x)                        (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R0_SHIFT)) & LMEM_PCCRMR_R0_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group LMEM_Register_Masks */
+
+
+/* LMEM - Peripheral instance base addresses */
+/** Peripheral LMEM base address */
+#define LMEM_BASE                                (0xE0082000u)
+/** Peripheral LMEM base pointer */
+#define LMEM                                     ((LMEM_Type *)LMEM_BASE)
+/** Array initializer of LMEM peripheral base addresses */
+#define LMEM_BASE_ADDRS                          { LMEM_BASE }
+/** Array initializer of LMEM peripheral base pointers */
+#define LMEM_BASE_PTRS                           { LMEM }
+
+/*!
+ * @}
+ */ /* end of group LMEM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
+ * @{
+ */
+
+/** LPTMR - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CSR;                               /**< Low Power Timer Control Status Register, offset: 0x0 */
+  __IO uint32_t PSR;                               /**< Low Power Timer Prescale Register, offset: 0x4 */
+  __IO uint32_t CMR;                               /**< Low Power Timer Compare Register, offset: 0x8 */
+  __IO uint32_t CNR;                               /**< Low Power Timer Counter Register, offset: 0xC */
+} LPTMR_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LPTMR Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
+ * @{
+ */
+
+/*! @name CSR - Low Power Timer Control Status Register */
+#define LPTMR_CSR_TEN_MASK                       (0x1U)
+#define LPTMR_CSR_TEN_SHIFT                      (0U)
+#define LPTMR_CSR_TEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
+#define LPTMR_CSR_TMS_MASK                       (0x2U)
+#define LPTMR_CSR_TMS_SHIFT                      (1U)
+#define LPTMR_CSR_TMS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
+#define LPTMR_CSR_TFC_MASK                       (0x4U)
+#define LPTMR_CSR_TFC_SHIFT                      (2U)
+#define LPTMR_CSR_TFC(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
+#define LPTMR_CSR_TPP_MASK                       (0x8U)
+#define LPTMR_CSR_TPP_SHIFT                      (3U)
+#define LPTMR_CSR_TPP(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
+#define LPTMR_CSR_TPS_MASK                       (0x30U)
+#define LPTMR_CSR_TPS_SHIFT                      (4U)
+#define LPTMR_CSR_TPS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
+#define LPTMR_CSR_TIE_MASK                       (0x40U)
+#define LPTMR_CSR_TIE_SHIFT                      (6U)
+#define LPTMR_CSR_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
+#define LPTMR_CSR_TCF_MASK                       (0x80U)
+#define LPTMR_CSR_TCF_SHIFT                      (7U)
+#define LPTMR_CSR_TCF(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
+
+/*! @name PSR - Low Power Timer Prescale Register */
+#define LPTMR_PSR_PCS_MASK                       (0x3U)
+#define LPTMR_PSR_PCS_SHIFT                      (0U)
+#define LPTMR_PSR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
+#define LPTMR_PSR_PBYP_MASK                      (0x4U)
+#define LPTMR_PSR_PBYP_SHIFT                     (2U)
+#define LPTMR_PSR_PBYP(x)                        (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
+#define LPTMR_PSR_PRESCALE_MASK                  (0x78U)
+#define LPTMR_PSR_PRESCALE_SHIFT                 (3U)
+#define LPTMR_PSR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
+
+/*! @name CMR - Low Power Timer Compare Register */
+#define LPTMR_CMR_COMPARE_MASK                   (0xFFFFU)
+#define LPTMR_CMR_COMPARE_SHIFT                  (0U)
+#define LPTMR_CMR_COMPARE(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
+
+/*! @name CNR - Low Power Timer Counter Register */
+#define LPTMR_CNR_COUNTER_MASK                   (0xFFFFU)
+#define LPTMR_CNR_COUNTER_SHIFT                  (0U)
+#define LPTMR_CNR_COUNTER(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Register_Masks */
+
+
+/* LPTMR - Peripheral instance base addresses */
+/** Peripheral LPTMR0 base address */
+#define LPTMR0_BASE                              (0x40040000u)
+/** Peripheral LPTMR0 base pointer */
+#define LPTMR0                                   ((LPTMR_Type *)LPTMR0_BASE)
+/** Array initializer of LPTMR peripheral base addresses */
+#define LPTMR_BASE_ADDRS                         { LPTMR0_BASE }
+/** Array initializer of LPTMR peripheral base pointers */
+#define LPTMR_BASE_PTRS                          { LPTMR0 }
+/** Interrupt vectors for the LPTMR peripheral type */
+#define LPTMR_IRQS                               { LPTMR0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LPTMR_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- LPUART Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
+ * @{
+ */
+
+/** LPUART - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t BAUD;                              /**< LPUART Baud Rate Register, offset: 0x0 */
+  __IO uint32_t STAT;                              /**< LPUART Status Register, offset: 0x4 */
+  __IO uint32_t CTRL;                              /**< LPUART Control Register, offset: 0x8 */
+  __IO uint32_t DATA;                              /**< LPUART Data Register, offset: 0xC */
+  __IO uint32_t MATCH;                             /**< LPUART Match Address Register, offset: 0x10 */
+  __IO uint32_t MODIR;                             /**< LPUART Modem IrDA Register, offset: 0x14 */
+} LPUART_Type;
+
+/* ----------------------------------------------------------------------------
+   -- LPUART Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LPUART_Register_Masks LPUART Register Masks
+ * @{
+ */
+
+/*! @name BAUD - LPUART Baud Rate Register */
+#define LPUART_BAUD_SBR_MASK                     (0x1FFFU)
+#define LPUART_BAUD_SBR_SHIFT                    (0U)
+#define LPUART_BAUD_SBR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
+#define LPUART_BAUD_SBNS_MASK                    (0x2000U)
+#define LPUART_BAUD_SBNS_SHIFT                   (13U)
+#define LPUART_BAUD_SBNS(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
+#define LPUART_BAUD_RXEDGIE_MASK                 (0x4000U)
+#define LPUART_BAUD_RXEDGIE_SHIFT                (14U)
+#define LPUART_BAUD_RXEDGIE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
+#define LPUART_BAUD_LBKDIE_MASK                  (0x8000U)
+#define LPUART_BAUD_LBKDIE_SHIFT                 (15U)
+#define LPUART_BAUD_LBKDIE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
+#define LPUART_BAUD_RESYNCDIS_MASK               (0x10000U)
+#define LPUART_BAUD_RESYNCDIS_SHIFT              (16U)
+#define LPUART_BAUD_RESYNCDIS(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
+#define LPUART_BAUD_BOTHEDGE_MASK                (0x20000U)
+#define LPUART_BAUD_BOTHEDGE_SHIFT               (17U)
+#define LPUART_BAUD_BOTHEDGE(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
+#define LPUART_BAUD_MATCFG_MASK                  (0xC0000U)
+#define LPUART_BAUD_MATCFG_SHIFT                 (18U)
+#define LPUART_BAUD_MATCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
+#define LPUART_BAUD_RDMAE_MASK                   (0x200000U)
+#define LPUART_BAUD_RDMAE_SHIFT                  (21U)
+#define LPUART_BAUD_RDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
+#define LPUART_BAUD_TDMAE_MASK                   (0x800000U)
+#define LPUART_BAUD_TDMAE_SHIFT                  (23U)
+#define LPUART_BAUD_TDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
+#define LPUART_BAUD_OSR_MASK                     (0x1F000000U)
+#define LPUART_BAUD_OSR_SHIFT                    (24U)
+#define LPUART_BAUD_OSR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
+#define LPUART_BAUD_M10_MASK                     (0x20000000U)
+#define LPUART_BAUD_M10_SHIFT                    (29U)
+#define LPUART_BAUD_M10(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
+#define LPUART_BAUD_MAEN2_MASK                   (0x40000000U)
+#define LPUART_BAUD_MAEN2_SHIFT                  (30U)
+#define LPUART_BAUD_MAEN2(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
+#define LPUART_BAUD_MAEN1_MASK                   (0x80000000U)
+#define LPUART_BAUD_MAEN1_SHIFT                  (31U)
+#define LPUART_BAUD_MAEN1(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
+
+/*! @name STAT - LPUART Status Register */
+#define LPUART_STAT_MA2F_MASK                    (0x4000U)
+#define LPUART_STAT_MA2F_SHIFT                   (14U)
+#define LPUART_STAT_MA2F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
+#define LPUART_STAT_MA1F_MASK                    (0x8000U)
+#define LPUART_STAT_MA1F_SHIFT                   (15U)
+#define LPUART_STAT_MA1F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
+#define LPUART_STAT_PF_MASK                      (0x10000U)
+#define LPUART_STAT_PF_SHIFT                     (16U)
+#define LPUART_STAT_PF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
+#define LPUART_STAT_FE_MASK                      (0x20000U)
+#define LPUART_STAT_FE_SHIFT                     (17U)
+#define LPUART_STAT_FE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
+#define LPUART_STAT_NF_MASK                      (0x40000U)
+#define LPUART_STAT_NF_SHIFT                     (18U)
+#define LPUART_STAT_NF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
+#define LPUART_STAT_OR_MASK                      (0x80000U)
+#define LPUART_STAT_OR_SHIFT                     (19U)
+#define LPUART_STAT_OR(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
+#define LPUART_STAT_IDLE_MASK                    (0x100000U)
+#define LPUART_STAT_IDLE_SHIFT                   (20U)
+#define LPUART_STAT_IDLE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
+#define LPUART_STAT_RDRF_MASK                    (0x200000U)
+#define LPUART_STAT_RDRF_SHIFT                   (21U)
+#define LPUART_STAT_RDRF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
+#define LPUART_STAT_TC_MASK                      (0x400000U)
+#define LPUART_STAT_TC_SHIFT                     (22U)
+#define LPUART_STAT_TC(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
+#define LPUART_STAT_TDRE_MASK                    (0x800000U)
+#define LPUART_STAT_TDRE_SHIFT                   (23U)
+#define LPUART_STAT_TDRE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
+#define LPUART_STAT_RAF_MASK                     (0x1000000U)
+#define LPUART_STAT_RAF_SHIFT                    (24U)
+#define LPUART_STAT_RAF(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
+#define LPUART_STAT_LBKDE_MASK                   (0x2000000U)
+#define LPUART_STAT_LBKDE_SHIFT                  (25U)
+#define LPUART_STAT_LBKDE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
+#define LPUART_STAT_BRK13_MASK                   (0x4000000U)
+#define LPUART_STAT_BRK13_SHIFT                  (26U)
+#define LPUART_STAT_BRK13(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
+#define LPUART_STAT_RWUID_MASK                   (0x8000000U)
+#define LPUART_STAT_RWUID_SHIFT                  (27U)
+#define LPUART_STAT_RWUID(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
+#define LPUART_STAT_RXINV_MASK                   (0x10000000U)
+#define LPUART_STAT_RXINV_SHIFT                  (28U)
+#define LPUART_STAT_RXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
+#define LPUART_STAT_MSBF_MASK                    (0x20000000U)
+#define LPUART_STAT_MSBF_SHIFT                   (29U)
+#define LPUART_STAT_MSBF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
+#define LPUART_STAT_RXEDGIF_MASK                 (0x40000000U)
+#define LPUART_STAT_RXEDGIF_SHIFT                (30U)
+#define LPUART_STAT_RXEDGIF(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
+#define LPUART_STAT_LBKDIF_MASK                  (0x80000000U)
+#define LPUART_STAT_LBKDIF_SHIFT                 (31U)
+#define LPUART_STAT_LBKDIF(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
+
+/*! @name CTRL - LPUART Control Register */
+#define LPUART_CTRL_PT_MASK                      (0x1U)
+#define LPUART_CTRL_PT_SHIFT                     (0U)
+#define LPUART_CTRL_PT(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
+#define LPUART_CTRL_PE_MASK                      (0x2U)
+#define LPUART_CTRL_PE_SHIFT                     (1U)
+#define LPUART_CTRL_PE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
+#define LPUART_CTRL_ILT_MASK                     (0x4U)
+#define LPUART_CTRL_ILT_SHIFT                    (2U)
+#define LPUART_CTRL_ILT(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
+#define LPUART_CTRL_WAKE_MASK                    (0x8U)
+#define LPUART_CTRL_WAKE_SHIFT                   (3U)
+#define LPUART_CTRL_WAKE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
+#define LPUART_CTRL_M_MASK                       (0x10U)
+#define LPUART_CTRL_M_SHIFT                      (4U)
+#define LPUART_CTRL_M(x)                         (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
+#define LPUART_CTRL_RSRC_MASK                    (0x20U)
+#define LPUART_CTRL_RSRC_SHIFT                   (5U)
+#define LPUART_CTRL_RSRC(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
+#define LPUART_CTRL_DOZEEN_MASK                  (0x40U)
+#define LPUART_CTRL_DOZEEN_SHIFT                 (6U)
+#define LPUART_CTRL_DOZEEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
+#define LPUART_CTRL_LOOPS_MASK                   (0x80U)
+#define LPUART_CTRL_LOOPS_SHIFT                  (7U)
+#define LPUART_CTRL_LOOPS(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
+#define LPUART_CTRL_IDLECFG_MASK                 (0x700U)
+#define LPUART_CTRL_IDLECFG_SHIFT                (8U)
+#define LPUART_CTRL_IDLECFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
+#define LPUART_CTRL_MA2IE_MASK                   (0x4000U)
+#define LPUART_CTRL_MA2IE_SHIFT                  (14U)
+#define LPUART_CTRL_MA2IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
+#define LPUART_CTRL_MA1IE_MASK                   (0x8000U)
+#define LPUART_CTRL_MA1IE_SHIFT                  (15U)
+#define LPUART_CTRL_MA1IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
+#define LPUART_CTRL_SBK_MASK                     (0x10000U)
+#define LPUART_CTRL_SBK_SHIFT                    (16U)
+#define LPUART_CTRL_SBK(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
+#define LPUART_CTRL_RWU_MASK                     (0x20000U)
+#define LPUART_CTRL_RWU_SHIFT                    (17U)
+#define LPUART_CTRL_RWU(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
+#define LPUART_CTRL_RE_MASK                      (0x40000U)
+#define LPUART_CTRL_RE_SHIFT                     (18U)
+#define LPUART_CTRL_RE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
+#define LPUART_CTRL_TE_MASK                      (0x80000U)
+#define LPUART_CTRL_TE_SHIFT                     (19U)
+#define LPUART_CTRL_TE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
+#define LPUART_CTRL_ILIE_MASK                    (0x100000U)
+#define LPUART_CTRL_ILIE_SHIFT                   (20U)
+#define LPUART_CTRL_ILIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
+#define LPUART_CTRL_RIE_MASK                     (0x200000U)
+#define LPUART_CTRL_RIE_SHIFT                    (21U)
+#define LPUART_CTRL_RIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
+#define LPUART_CTRL_TCIE_MASK                    (0x400000U)
+#define LPUART_CTRL_TCIE_SHIFT                   (22U)
+#define LPUART_CTRL_TCIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
+#define LPUART_CTRL_TIE_MASK                     (0x800000U)
+#define LPUART_CTRL_TIE_SHIFT                    (23U)
+#define LPUART_CTRL_TIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
+#define LPUART_CTRL_PEIE_MASK                    (0x1000000U)
+#define LPUART_CTRL_PEIE_SHIFT                   (24U)
+#define LPUART_CTRL_PEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
+#define LPUART_CTRL_FEIE_MASK                    (0x2000000U)
+#define LPUART_CTRL_FEIE_SHIFT                   (25U)
+#define LPUART_CTRL_FEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
+#define LPUART_CTRL_NEIE_MASK                    (0x4000000U)
+#define LPUART_CTRL_NEIE_SHIFT                   (26U)
+#define LPUART_CTRL_NEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
+#define LPUART_CTRL_ORIE_MASK                    (0x8000000U)
+#define LPUART_CTRL_ORIE_SHIFT                   (27U)
+#define LPUART_CTRL_ORIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
+#define LPUART_CTRL_TXINV_MASK                   (0x10000000U)
+#define LPUART_CTRL_TXINV_SHIFT                  (28U)
+#define LPUART_CTRL_TXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
+#define LPUART_CTRL_TXDIR_MASK                   (0x20000000U)
+#define LPUART_CTRL_TXDIR_SHIFT                  (29U)
+#define LPUART_CTRL_TXDIR(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
+#define LPUART_CTRL_R9T8_MASK                    (0x40000000U)
+#define LPUART_CTRL_R9T8_SHIFT                   (30U)
+#define LPUART_CTRL_R9T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
+#define LPUART_CTRL_R8T9_MASK                    (0x80000000U)
+#define LPUART_CTRL_R8T9_SHIFT                   (31U)
+#define LPUART_CTRL_R8T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
+
+/*! @name DATA - LPUART Data Register */
+#define LPUART_DATA_R0T0_MASK                    (0x1U)
+#define LPUART_DATA_R0T0_SHIFT                   (0U)
+#define LPUART_DATA_R0T0(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
+#define LPUART_DATA_R1T1_MASK                    (0x2U)
+#define LPUART_DATA_R1T1_SHIFT                   (1U)
+#define LPUART_DATA_R1T1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
+#define LPUART_DATA_R2T2_MASK                    (0x4U)
+#define LPUART_DATA_R2T2_SHIFT                   (2U)
+#define LPUART_DATA_R2T2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
+#define LPUART_DATA_R3T3_MASK                    (0x8U)
+#define LPUART_DATA_R3T3_SHIFT                   (3U)
+#define LPUART_DATA_R3T3(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
+#define LPUART_DATA_R4T4_MASK                    (0x10U)
+#define LPUART_DATA_R4T4_SHIFT                   (4U)
+#define LPUART_DATA_R4T4(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
+#define LPUART_DATA_R5T5_MASK                    (0x20U)
+#define LPUART_DATA_R5T5_SHIFT                   (5U)
+#define LPUART_DATA_R5T5(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
+#define LPUART_DATA_R6T6_MASK                    (0x40U)
+#define LPUART_DATA_R6T6_SHIFT                   (6U)
+#define LPUART_DATA_R6T6(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
+#define LPUART_DATA_R7T7_MASK                    (0x80U)
+#define LPUART_DATA_R7T7_SHIFT                   (7U)
+#define LPUART_DATA_R7T7(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
+#define LPUART_DATA_R8T8_MASK                    (0x100U)
+#define LPUART_DATA_R8T8_SHIFT                   (8U)
+#define LPUART_DATA_R8T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
+#define LPUART_DATA_R9T9_MASK                    (0x200U)
+#define LPUART_DATA_R9T9_SHIFT                   (9U)
+#define LPUART_DATA_R9T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
+#define LPUART_DATA_IDLINE_MASK                  (0x800U)
+#define LPUART_DATA_IDLINE_SHIFT                 (11U)
+#define LPUART_DATA_IDLINE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
+#define LPUART_DATA_RXEMPT_MASK                  (0x1000U)
+#define LPUART_DATA_RXEMPT_SHIFT                 (12U)
+#define LPUART_DATA_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
+#define LPUART_DATA_FRETSC_MASK                  (0x2000U)
+#define LPUART_DATA_FRETSC_SHIFT                 (13U)
+#define LPUART_DATA_FRETSC(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
+#define LPUART_DATA_PARITYE_MASK                 (0x4000U)
+#define LPUART_DATA_PARITYE_SHIFT                (14U)
+#define LPUART_DATA_PARITYE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
+#define LPUART_DATA_NOISY_MASK                   (0x8000U)
+#define LPUART_DATA_NOISY_SHIFT                  (15U)
+#define LPUART_DATA_NOISY(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
+
+/*! @name MATCH - LPUART Match Address Register */
+#define LPUART_MATCH_MA1_MASK                    (0x3FFU)
+#define LPUART_MATCH_MA1_SHIFT                   (0U)
+#define LPUART_MATCH_MA1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
+#define LPUART_MATCH_MA2_MASK                    (0x3FF0000U)
+#define LPUART_MATCH_MA2_SHIFT                   (16U)
+#define LPUART_MATCH_MA2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
+
+/*! @name MODIR - LPUART Modem IrDA Register */
+#define LPUART_MODIR_TXCTSE_MASK                 (0x1U)
+#define LPUART_MODIR_TXCTSE_SHIFT                (0U)
+#define LPUART_MODIR_TXCTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
+#define LPUART_MODIR_TXRTSE_MASK                 (0x2U)
+#define LPUART_MODIR_TXRTSE_SHIFT                (1U)
+#define LPUART_MODIR_TXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
+#define LPUART_MODIR_TXRTSPOL_MASK               (0x4U)
+#define LPUART_MODIR_TXRTSPOL_SHIFT              (2U)
+#define LPUART_MODIR_TXRTSPOL(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
+#define LPUART_MODIR_RXRTSE_MASK                 (0x8U)
+#define LPUART_MODIR_RXRTSE_SHIFT                (3U)
+#define LPUART_MODIR_RXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
+#define LPUART_MODIR_TXCTSC_MASK                 (0x10U)
+#define LPUART_MODIR_TXCTSC_SHIFT                (4U)
+#define LPUART_MODIR_TXCTSC(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
+#define LPUART_MODIR_TXCTSSRC_MASK               (0x20U)
+#define LPUART_MODIR_TXCTSSRC_SHIFT              (5U)
+#define LPUART_MODIR_TXCTSSRC(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
+#define LPUART_MODIR_TNP_MASK                    (0x30000U)
+#define LPUART_MODIR_TNP_SHIFT                   (16U)
+#define LPUART_MODIR_TNP(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
+#define LPUART_MODIR_IREN_MASK                   (0x40000U)
+#define LPUART_MODIR_IREN_SHIFT                  (18U)
+#define LPUART_MODIR_IREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group LPUART_Register_Masks */
+
+
+/* LPUART - Peripheral instance base addresses */
+/** Peripheral LPUART0 base address */
+#define LPUART0_BASE                             (0x400C4000u)
+/** Peripheral LPUART0 base pointer */
+#define LPUART0                                  ((LPUART_Type *)LPUART0_BASE)
+/** Array initializer of LPUART peripheral base addresses */
+#define LPUART_BASE_ADDRS                        { LPUART0_BASE }
+/** Array initializer of LPUART peripheral base pointers */
+#define LPUART_BASE_PTRS                         { LPUART0 }
+/** Interrupt vectors for the LPUART peripheral type */
+#define LPUART_RX_TX_IRQS                        { LPUART0_IRQn }
+#define LPUART_ERR_IRQS                          { LPUART0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LPUART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
+ * @{
+ */
+
+/** MCG - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t C1;                                 /**< MCG Control 1 Register, offset: 0x0 */
+  __IO uint8_t C2;                                 /**< MCG Control 2 Register, offset: 0x1 */
+  __IO uint8_t C3;                                 /**< MCG Control 3 Register, offset: 0x2 */
+  __IO uint8_t C4;                                 /**< MCG Control 4 Register, offset: 0x3 */
+  __IO uint8_t C5;                                 /**< MCG Control 5 Register, offset: 0x4 */
+  __IO uint8_t C6;                                 /**< MCG Control 6 Register, offset: 0x5 */
+  __IO uint8_t S;                                  /**< MCG Status Register, offset: 0x6 */
+       uint8_t RESERVED_0[1];
+  __IO uint8_t SC;                                 /**< MCG Status and Control Register, offset: 0x8 */
+       uint8_t RESERVED_1[1];
+  __IO uint8_t ATCVH;                              /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
+  __IO uint8_t ATCVL;                              /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
+  __IO uint8_t C7;                                 /**< MCG Control 7 Register, offset: 0xC */
+  __IO uint8_t C8;                                 /**< MCG Control 8 Register, offset: 0xD */
+  __IO uint8_t C9;                                 /**< MCG Control 9 Register, offset: 0xE */
+       uint8_t RESERVED_2[1];
+  __IO uint8_t C11;                                /**< MCG Control 11 Register, offset: 0x10 */
+       uint8_t RESERVED_3[1];
+  __I  uint8_t S2;                                 /**< MCG Status 2 Register, offset: 0x12 */
+} MCG_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MCG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCG_Register_Masks MCG Register Masks
+ * @{
+ */
+
+/*! @name C1 - MCG Control 1 Register */
+#define MCG_C1_IREFSTEN_MASK                     (0x1U)
+#define MCG_C1_IREFSTEN_SHIFT                    (0U)
+#define MCG_C1_IREFSTEN(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
+#define MCG_C1_IRCLKEN_MASK                      (0x2U)
+#define MCG_C1_IRCLKEN_SHIFT                     (1U)
+#define MCG_C1_IRCLKEN(x)                        (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
+#define MCG_C1_IREFS_MASK                        (0x4U)
+#define MCG_C1_IREFS_SHIFT                       (2U)
+#define MCG_C1_IREFS(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
+#define MCG_C1_FRDIV_MASK                        (0x38U)
+#define MCG_C1_FRDIV_SHIFT                       (3U)
+#define MCG_C1_FRDIV(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
+#define MCG_C1_CLKS_MASK                         (0xC0U)
+#define MCG_C1_CLKS_SHIFT                        (6U)
+#define MCG_C1_CLKS(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
+
+/*! @name C2 - MCG Control 2 Register */
+#define MCG_C2_IRCS_MASK                         (0x1U)
+#define MCG_C2_IRCS_SHIFT                        (0U)
+#define MCG_C2_IRCS(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
+#define MCG_C2_LP_MASK                           (0x2U)
+#define MCG_C2_LP_SHIFT                          (1U)
+#define MCG_C2_LP(x)                             (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
+#define MCG_C2_EREFS_MASK                        (0x4U)
+#define MCG_C2_EREFS_SHIFT                       (2U)
+#define MCG_C2_EREFS_SET(x)                      (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK)
+#define MCG_C2_EREFS                             MCG_C2_EREFS_SET(1)
+#define MCG_C2_EREFS0                            MCG_C2_EREFS_SET(1)
+#define MCG_C2_HGO_MASK                          (0x8U)
+#define MCG_C2_HGO_SHIFT                         (3U)
+#define MCG_C2_HGO(x)                            (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK)
+#define MCG_C2_RANGE_MASK                        (0x30U)
+#define MCG_C2_RANGE_SHIFT                       (4U)
+#define MCG_C2_RANGE(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK)
+#define MCG_C2_FCFTRIM_MASK                      (0x40U)
+#define MCG_C2_FCFTRIM_SHIFT                     (6U)
+#define MCG_C2_FCFTRIM(x)                        (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK)
+#define MCG_C2_LOCRE0_MASK                       (0x80U)
+#define MCG_C2_LOCRE0_SHIFT                      (7U)
+#define MCG_C2_LOCRE0_SET(x)                     (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
+#define MCG_C2_LOCRE0                            MCG_C2_LOCRE0_SET(1)
+
+/*! @name C3 - MCG Control 3 Register */
+#define MCG_C3_SCTRIM_MASK                       (0xFFU)
+#define MCG_C3_SCTRIM_SHIFT                      (0U)
+#define MCG_C3_SCTRIM(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
+
+/*! @name C4 - MCG Control 4 Register */
+#define MCG_C4_SCFTRIM_MASK                      (0x1U)
+#define MCG_C4_SCFTRIM_SHIFT                     (0U)
+#define MCG_C4_SCFTRIM(x)                        (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
+#define MCG_C4_FCTRIM_MASK                       (0x1EU)
+#define MCG_C4_FCTRIM_SHIFT                      (1U)
+#define MCG_C4_FCTRIM(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
+#define MCG_C4_DRST_DRS_MASK                     (0x60U)
+#define MCG_C4_DRST_DRS_SHIFT                    (5U)
+#define MCG_C4_DRST_DRS(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
+#define MCG_C4_DMX32_MASK                        (0x80U)
+#define MCG_C4_DMX32_SHIFT                       (7U)
+#define MCG_C4_DMX32_SET(x)                      (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
+#define MCG_C4_DMX32                             MCG_C4_DMX32_SET(1)
+
+/*! @name C5 - MCG Control 5 Register */
+#define MCG_C5_PRDIV_MASK                        (0x7U)
+#define MCG_C5_PRDIV_SHIFT                       (0U)
+#define MCG_C5_PRDIV(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV_SHIFT)) & MCG_C5_PRDIV_MASK)
+#define MCG_C5_PLLSTEN_MASK                      (0x20U)
+#define MCG_C5_PLLSTEN_SHIFT                     (5U)
+#define MCG_C5_PLLSTEN(x)                        (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN_SHIFT)) & MCG_C5_PLLSTEN_MASK)
+#define MCG_C5_PLLCLKEN_MASK                     (0x40U)
+#define MCG_C5_PLLCLKEN_SHIFT                    (6U)
+#define MCG_C5_PLLCLKEN(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN_SHIFT)) & MCG_C5_PLLCLKEN_MASK)
+
+/*! @name C6 - MCG Control 6 Register */
+#define MCG_C6_VDIV_MASK                         (0x1FU)
+#define MCG_C6_VDIV_SHIFT                        (0U)
+#define MCG_C6_VDIV(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV_SHIFT)) & MCG_C6_VDIV_MASK)
+#define MCG_C6_CME0_MASK                         (0x20U)
+#define MCG_C6_CME0_SHIFT                        (5U)
+#define MCG_C6_CME0(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)
+#define MCG_C6_PLLS_MASK                         (0x40U)
+#define MCG_C6_PLLS_SHIFT                        (6U)
+#define MCG_C6_PLLS_SET(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)
+#define MCG_C6_PLLS                              MCG_C6_PLLS_SET(1)
+#define MCG_C6_LOLIE0_MASK                       (0x80U)
+#define MCG_C6_LOLIE0_SHIFT                      (7U)
+#define MCG_C6_LOLIE0(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)
+
+/*! @name S - MCG Status Register */
+#define MCG_S_IRCST_MASK                         (0x1U)
+#define MCG_S_IRCST_SHIFT                        (0U)
+#define MCG_S_IRCST(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
+#define MCG_S_OSCINIT0_MASK                      (0x2U)
+#define MCG_S_OSCINIT0_SHIFT                     (1U)
+#define MCG_S_OSCINIT0_SET(x)                    (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
+#define MCG_S_OSCINIT0                           MCG_S_OSCINIT0_SET(1)
+#define MCG_S_CLKST_MASK                         (0xCU)
+#define MCG_S_CLKST_SHIFT                        (2U)
+#define MCG_S_CLKST(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
+#define MCG_S_CLKST_PLL                          MCG_S_CLKST(3)   /*!< Output of the PLL is selected */
+#define MCG_S_IREFST_MASK                        (0x10U)
+#define MCG_S_IREFST_SHIFT                       (4U)
+#define MCG_S_IREFST_SET(x)                      (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
+#define MCG_S_IREFST                             MCG_S_IREFST_SET(1)
+#define MCG_S_PLLST_MASK                         (0x20U)
+#define MCG_S_PLLST_SHIFT                        (5U)
+#define MCG_S_PLLST_SET(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)
+#define MCG_S_PLLST                              MCG_S_PLLST_SET(1)
+#define MCG_S_LOCK0_MASK                         (0x40U)
+#define MCG_S_LOCK0_SHIFT                        (6U)
+#define MCG_S_LOCK0_SET(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)
+#define MCG_S_LOCK0                              MCG_S_LOCK0_SET(1)
+#define MCG_S_LOLS0_MASK                         (0x80U)
+#define MCG_S_LOLS0_SHIFT                        (7U)
+#define MCG_S_LOLS0(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK)
+
+/*! @name SC - MCG Status and Control Register */
+#define MCG_SC_LOCS0_MASK                        (0x1U)
+#define MCG_SC_LOCS0_SHIFT                       (0U)
+#define MCG_SC_LOCS0(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
+#define MCG_SC_FCRDIV_MASK                       (0xEU)
+#define MCG_SC_FCRDIV_SHIFT                      (1U)
+#define MCG_SC_FCRDIV(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
+#define MCG_SC_FLTPRSRV_MASK                     (0x10U)
+#define MCG_SC_FLTPRSRV_SHIFT                    (4U)
+#define MCG_SC_FLTPRSRV(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
+#define MCG_SC_ATMF_MASK                         (0x20U)
+#define MCG_SC_ATMF_SHIFT                        (5U)
+#define MCG_SC_ATMF(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
+#define MCG_SC_ATMS_MASK                         (0x40U)
+#define MCG_SC_ATMS_SHIFT                        (6U)
+#define MCG_SC_ATMS(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
+#define MCG_SC_ATME_MASK                         (0x80U)
+#define MCG_SC_ATME_SHIFT                        (7U)
+#define MCG_SC_ATME(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
+
+/*! @name ATCVH - MCG Auto Trim Compare Value High Register */
+#define MCG_ATCVH_ATCVH_MASK                     (0xFFU)
+#define MCG_ATCVH_ATCVH_SHIFT                    (0U)
+#define MCG_ATCVH_ATCVH(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
+
+/*! @name ATCVL - MCG Auto Trim Compare Value Low Register */
+#define MCG_ATCVL_ATCVL_MASK                     (0xFFU)
+#define MCG_ATCVL_ATCVL_SHIFT                    (0U)
+#define MCG_ATCVL_ATCVL(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
+
+/*! @name C7 - MCG Control 7 Register */
+#define MCG_C7_OSCSEL_MASK                       (0x3U)
+#define MCG_C7_OSCSEL_SHIFT                      (0U)
+#define MCG_C7_OSCSEL(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
+
+/*! @name C8 - MCG Control 8 Register */
+#define MCG_C8_LOCS1_MASK                        (0x1U)
+#define MCG_C8_LOCS1_SHIFT                       (0U)
+#define MCG_C8_LOCS1(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)
+#define MCG_C8_CME1_MASK                         (0x20U)
+#define MCG_C8_CME1_SHIFT                        (5U)
+#define MCG_C8_CME1(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)
+#define MCG_C8_LOLRE_MASK                        (0x40U)
+#define MCG_C8_LOLRE_SHIFT                       (6U)
+#define MCG_C8_LOLRE(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)
+#define MCG_C8_LOCRE1_MASK                       (0x80U)
+#define MCG_C8_LOCRE1_SHIFT                      (7U)
+#define MCG_C8_LOCRE1(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)
+
+/*! @name C9 - MCG Control 9 Register */
+#define MCG_C9_EXT_PLL_LOCS_MASK                 (0x1U)
+#define MCG_C9_EXT_PLL_LOCS_SHIFT                (0U)
+#define MCG_C9_EXT_PLL_LOCS(x)                   (((uint8_t)(((uint8_t)(x)) << MCG_C9_EXT_PLL_LOCS_SHIFT)) & MCG_C9_EXT_PLL_LOCS_MASK)
+#define MCG_C9_PLL_LOCRE_MASK                    (0x10U)
+#define MCG_C9_PLL_LOCRE_SHIFT                   (4U)
+#define MCG_C9_PLL_LOCRE(x)                      (((uint8_t)(((uint8_t)(x)) << MCG_C9_PLL_LOCRE_SHIFT)) & MCG_C9_PLL_LOCRE_MASK)
+#define MCG_C9_PLL_CME_MASK                      (0x20U)
+#define MCG_C9_PLL_CME_SHIFT                     (5U)
+#define MCG_C9_PLL_CME(x)                        (((uint8_t)(((uint8_t)(x)) << MCG_C9_PLL_CME_SHIFT)) & MCG_C9_PLL_CME_MASK)
+
+/*! @name C11 - MCG Control 11 Register */
+#define MCG_C11_PLLCS_MASK                       (0x10U)
+#define MCG_C11_PLLCS_SHIFT                      (4U)
+#define MCG_C11_PLLCS(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C11_PLLCS_SHIFT)) & MCG_C11_PLLCS_MASK)
+
+/*! @name S2 - MCG Status 2 Register */
+#define MCG_S2_PLLCST_MASK                       (0x10U)
+#define MCG_S2_PLLCST_SHIFT                      (4U)
+#define MCG_S2_PLLCST(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_S2_PLLCST_SHIFT)) & MCG_S2_PLLCST_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group MCG_Register_Masks */
+
+
+/* MCG - Peripheral instance base addresses */
+/** Peripheral MCG base address */
+#define MCG_BASE                                 (0x40064000u)
+/** Peripheral MCG base pointer */
+#define MCG                                      ((MCG_Type *)MCG_BASE)
+/** Array initializer of MCG peripheral base addresses */
+#define MCG_BASE_ADDRS                           { MCG_BASE }
+/** Array initializer of MCG peripheral base pointers */
+#define MCG_BASE_PTRS                            { MCG }
+/* MCG C5[PLLCLKEN0] backward compatibility */
+#define MCG_C5_PLLCLKEN0_MASK         (MCG_C5_PLLCLKEN_MASK)
+#define MCG_C5_PLLCLKEN0_SHIFT        (MCG_C5_PLLCLKEN_SHIFT)
+#define MCG_C5_PLLCLKEN0_WIDTH        (MCG_C5_PLLCLKEN_WIDTH)
+#define MCG_C5_PLLCLKEN0(x)           (MCG_C5_PLLCLKEN(x))
+
+/* MCG C5[PLLSTEN0] backward compatibility */
+#define MCG_C5_PLLSTEN0_MASK         (MCG_C5_PLLSTEN_MASK)
+#define MCG_C5_PLLSTEN0_SHIFT        (MCG_C5_PLLSTEN_SHIFT)
+#define MCG_C5_PLLSTEN0_WIDTH        (MCG_C5_PLLSTEN_WIDTH)
+#define MCG_C5_PLLSTEN0(x)           (MCG_C5_PLLSTEN(x))
+
+/* MCG C5[PRDIV0] backward compatibility */
+#define MCG_C5_PRDIV0_MASK         (MCG_C5_PRDIV_MASK)
+#define MCG_C5_PRDIV0_SHIFT        (MCG_C5_PRDIV_SHIFT)
+#define MCG_C5_PRDIV0_WIDTH        (MCG_C5_PRDIV_WIDTH)
+#define MCG_C5_PRDIV0(x)           (MCG_C5_PRDIV(x))
+
+/* MCG C6[VDIV0] backward compatibility */
+#define MCG_C6_VDIV0_MASK         (MCG_C6_VDIV_MASK)
+#define MCG_C6_VDIV0_SHIFT        (MCG_C6_VDIV_SHIFT)
+#define MCG_C6_VDIV0_WIDTH        (MCG_C6_VDIV_WIDTH)
+#define MCG_C6_VDIV0(x)           (MCG_C6_VDIV(x))
+
+
+/*!
+ * @}
+ */ /* end of group MCG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- MCM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
+ * @{
+ */
+
+/** MCM - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[8];
+  __I  uint16_t PLASC;                             /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
+  __I  uint16_t PLAMC;                             /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
+  __IO uint32_t CR;                                /**< Control Register, offset: 0xC */
+  __IO uint32_t ISCR;                              /**< Interrupt Status Register, offset: 0x10 */
+  __IO uint32_t ETBCC;                             /**< ETB Counter Control register, offset: 0x14 */
+  __IO uint32_t ETBRL;                             /**< ETB Reload register, offset: 0x18 */
+  __I  uint32_t ETBCNT;                            /**< ETB Counter Value register, offset: 0x1C */
+  __I  uint32_t FADR;                              /**< Fault address register, offset: 0x20 */
+  __I  uint32_t FATR;                              /**< Fault attributes register, offset: 0x24 */
+  __I  uint32_t FDR;                               /**< Fault data register, offset: 0x28 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t PID;                               /**< Process ID register, offset: 0x30 */
+       uint8_t RESERVED_2[12];
+  __IO uint32_t CPO;                               /**< Compute Operation Control Register, offset: 0x40 */
+} MCM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- MCM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MCM_Register_Masks MCM Register Masks
+ * @{
+ */
+
+/*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
+#define MCM_PLASC_ASC_MASK                       (0xFFU)
+#define MCM_PLASC_ASC_SHIFT                      (0U)
+#define MCM_PLASC_ASC(x)                         (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
+
+/*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
+#define MCM_PLAMC_AMC_MASK                       (0xFFU)
+#define MCM_PLAMC_AMC_SHIFT                      (0U)
+#define MCM_PLAMC_AMC(x)                         (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
+
+/*! @name CR - Control Register */
+#define MCM_CR_SRAMUAP_MASK                      (0x3000000U)
+#define MCM_CR_SRAMUAP_SHIFT                     (24U)
+#define MCM_CR_SRAMUAP(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUAP_SHIFT)) & MCM_CR_SRAMUAP_MASK)
+#define MCM_CR_SRAMUWP_MASK                      (0x4000000U)
+#define MCM_CR_SRAMUWP_SHIFT                     (26U)
+#define MCM_CR_SRAMUWP(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUWP_SHIFT)) & MCM_CR_SRAMUWP_MASK)
+#define MCM_CR_SRAMLAP_MASK                      (0x30000000U)
+#define MCM_CR_SRAMLAP_SHIFT                     (28U)
+#define MCM_CR_SRAMLAP(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLAP_SHIFT)) & MCM_CR_SRAMLAP_MASK)
+#define MCM_CR_SRAMLWP_MASK                      (0x40000000U)
+#define MCM_CR_SRAMLWP_SHIFT                     (30U)
+#define MCM_CR_SRAMLWP(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLWP_SHIFT)) & MCM_CR_SRAMLWP_MASK)
+
+/*! @name ISCR - Interrupt Status Register */
+#define MCM_ISCR_IRQ_MASK                        (0x2U)
+#define MCM_ISCR_IRQ_SHIFT                       (1U)
+#define MCM_ISCR_IRQ(x)                          (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_IRQ_SHIFT)) & MCM_ISCR_IRQ_MASK)
+#define MCM_ISCR_NMI_MASK                        (0x4U)
+#define MCM_ISCR_NMI_SHIFT                       (2U)
+#define MCM_ISCR_NMI(x)                          (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_NMI_SHIFT)) & MCM_ISCR_NMI_MASK)
+#define MCM_ISCR_DHREQ_MASK                      (0x8U)
+#define MCM_ISCR_DHREQ_SHIFT                     (3U)
+#define MCM_ISCR_DHREQ(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_DHREQ_SHIFT)) & MCM_ISCR_DHREQ_MASK)
+#define MCM_ISCR_FIOC_MASK                       (0x100U)
+#define MCM_ISCR_FIOC_SHIFT                      (8U)
+#define MCM_ISCR_FIOC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)
+#define MCM_ISCR_FDZC_MASK                       (0x200U)
+#define MCM_ISCR_FDZC_SHIFT                      (9U)
+#define MCM_ISCR_FDZC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)
+#define MCM_ISCR_FOFC_MASK                       (0x400U)
+#define MCM_ISCR_FOFC_SHIFT                      (10U)
+#define MCM_ISCR_FOFC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)
+#define MCM_ISCR_FUFC_MASK                       (0x800U)
+#define MCM_ISCR_FUFC_SHIFT                      (11U)
+#define MCM_ISCR_FUFC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)
+#define MCM_ISCR_FIXC_MASK                       (0x1000U)
+#define MCM_ISCR_FIXC_SHIFT                      (12U)
+#define MCM_ISCR_FIXC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)
+#define MCM_ISCR_FIDC_MASK                       (0x8000U)
+#define MCM_ISCR_FIDC_SHIFT                      (15U)
+#define MCM_ISCR_FIDC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)
+#define MCM_ISCR_FIOCE_MASK                      (0x1000000U)
+#define MCM_ISCR_FIOCE_SHIFT                     (24U)
+#define MCM_ISCR_FIOCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)
+#define MCM_ISCR_FDZCE_MASK                      (0x2000000U)
+#define MCM_ISCR_FDZCE_SHIFT                     (25U)
+#define MCM_ISCR_FDZCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)
+#define MCM_ISCR_FOFCE_MASK                      (0x4000000U)
+#define MCM_ISCR_FOFCE_SHIFT                     (26U)
+#define MCM_ISCR_FOFCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)
+#define MCM_ISCR_FUFCE_MASK                      (0x8000000U)
+#define MCM_ISCR_FUFCE_SHIFT                     (27U)
+#define MCM_ISCR_FUFCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)
+#define MCM_ISCR_FIXCE_MASK                      (0x10000000U)
+#define MCM_ISCR_FIXCE_SHIFT                     (28U)
+#define MCM_ISCR_FIXCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)
+#define MCM_ISCR_FIDCE_MASK                      (0x80000000U)
+#define MCM_ISCR_FIDCE_SHIFT                     (31U)
+#define MCM_ISCR_FIDCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)
+
+/*! @name ETBCC - ETB Counter Control register */
+#define MCM_ETBCC_CNTEN_MASK                     (0x1U)
+#define MCM_ETBCC_CNTEN_SHIFT                    (0U)
+#define MCM_ETBCC_CNTEN(x)                       (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_CNTEN_SHIFT)) & MCM_ETBCC_CNTEN_MASK)
+#define MCM_ETBCC_RSPT_MASK                      (0x6U)
+#define MCM_ETBCC_RSPT_SHIFT                     (1U)
+#define MCM_ETBCC_RSPT(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RSPT_SHIFT)) & MCM_ETBCC_RSPT_MASK)
+#define MCM_ETBCC_RLRQ_MASK                      (0x8U)
+#define MCM_ETBCC_RLRQ_SHIFT                     (3U)
+#define MCM_ETBCC_RLRQ(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RLRQ_SHIFT)) & MCM_ETBCC_RLRQ_MASK)
+#define MCM_ETBCC_ETDIS_MASK                     (0x10U)
+#define MCM_ETBCC_ETDIS_SHIFT                    (4U)
+#define MCM_ETBCC_ETDIS(x)                       (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ETDIS_SHIFT)) & MCM_ETBCC_ETDIS_MASK)
+#define MCM_ETBCC_ITDIS_MASK                     (0x20U)
+#define MCM_ETBCC_ITDIS_SHIFT                    (5U)
+#define MCM_ETBCC_ITDIS(x)                       (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ITDIS_SHIFT)) & MCM_ETBCC_ITDIS_MASK)
+
+/*! @name ETBRL - ETB Reload register */
+#define MCM_ETBRL_RELOAD_MASK                    (0x7FFU)
+#define MCM_ETBRL_RELOAD_SHIFT                   (0U)
+#define MCM_ETBRL_RELOAD(x)                      (((uint32_t)(((uint32_t)(x)) << MCM_ETBRL_RELOAD_SHIFT)) & MCM_ETBRL_RELOAD_MASK)
+
+/*! @name ETBCNT - ETB Counter Value register */
+#define MCM_ETBCNT_COUNTER_MASK                  (0x7FFU)
+#define MCM_ETBCNT_COUNTER_SHIFT                 (0U)
+#define MCM_ETBCNT_COUNTER(x)                    (((uint32_t)(((uint32_t)(x)) << MCM_ETBCNT_COUNTER_SHIFT)) & MCM_ETBCNT_COUNTER_MASK)
+
+/*! @name FADR - Fault address register */
+#define MCM_FADR_ADDRESS_MASK                    (0xFFFFFFFFU)
+#define MCM_FADR_ADDRESS_SHIFT                   (0U)
+#define MCM_FADR_ADDRESS(x)                      (((uint32_t)(((uint32_t)(x)) << MCM_FADR_ADDRESS_SHIFT)) & MCM_FADR_ADDRESS_MASK)
+
+/*! @name FATR - Fault attributes register */
+#define MCM_FATR_BEDA_MASK                       (0x1U)
+#define MCM_FATR_BEDA_SHIFT                      (0U)
+#define MCM_FATR_BEDA(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEDA_SHIFT)) & MCM_FATR_BEDA_MASK)
+#define MCM_FATR_BEMD_MASK                       (0x2U)
+#define MCM_FATR_BEMD_SHIFT                      (1U)
+#define MCM_FATR_BEMD(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMD_SHIFT)) & MCM_FATR_BEMD_MASK)
+#define MCM_FATR_BESZ_MASK                       (0x30U)
+#define MCM_FATR_BESZ_SHIFT                      (4U)
+#define MCM_FATR_BESZ(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BESZ_SHIFT)) & MCM_FATR_BESZ_MASK)
+#define MCM_FATR_BEWT_MASK                       (0x80U)
+#define MCM_FATR_BEWT_SHIFT                      (7U)
+#define MCM_FATR_BEWT(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEWT_SHIFT)) & MCM_FATR_BEWT_MASK)
+#define MCM_FATR_BEMN_MASK                       (0xF00U)
+#define MCM_FATR_BEMN_SHIFT                      (8U)
+#define MCM_FATR_BEMN(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMN_SHIFT)) & MCM_FATR_BEMN_MASK)
+#define MCM_FATR_BEOVR_MASK                      (0x80000000U)
+#define MCM_FATR_BEOVR_SHIFT                     (31U)
+#define MCM_FATR_BEOVR(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEOVR_SHIFT)) & MCM_FATR_BEOVR_MASK)
+
+/*! @name FDR - Fault data register */
+#define MCM_FDR_DATA_MASK                        (0xFFFFFFFFU)
+#define MCM_FDR_DATA_SHIFT                       (0U)
+#define MCM_FDR_DATA(x)                          (((uint32_t)(((uint32_t)(x)) << MCM_FDR_DATA_SHIFT)) & MCM_FDR_DATA_MASK)
+
+/*! @name PID - Process ID register */
+#define MCM_PID_PID_MASK                         (0xFFU)
+#define MCM_PID_PID_SHIFT                        (0U)
+#define MCM_PID_PID(x)                           (((uint32_t)(((uint32_t)(x)) << MCM_PID_PID_SHIFT)) & MCM_PID_PID_MASK)
+
+/*! @name CPO - Compute Operation Control Register */
+#define MCM_CPO_CPOREQ_MASK                      (0x1U)
+#define MCM_CPO_CPOREQ_SHIFT                     (0U)
+#define MCM_CPO_CPOREQ(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)
+#define MCM_CPO_CPOACK_MASK                      (0x2U)
+#define MCM_CPO_CPOACK_SHIFT                     (1U)
+#define MCM_CPO_CPOACK(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)
+#define MCM_CPO_CPOWOI_MASK                      (0x4U)
+#define MCM_CPO_CPOWOI_SHIFT                     (2U)
+#define MCM_CPO_CPOWOI(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group MCM_Register_Masks */
+
+
+/* MCM - Peripheral instance base addresses */
+/** Peripheral MCM base address */
+#define MCM_BASE                                 (0xE0080000u)
+/** Peripheral MCM base pointer */
+#define MCM                                      ((MCM_Type *)MCM_BASE)
+/** Array initializer of MCM peripheral base addresses */
+#define MCM_BASE_ADDRS                           { MCM_BASE }
+/** Array initializer of MCM peripheral base pointers */
+#define MCM_BASE_PTRS                            { MCM }
+/** Interrupt vectors for the MCM peripheral type */
+#define MCM_IRQS                                 { MCM_IRQn }
+
+/*!
+ * @}
+ */ /* end of group MCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- NV Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
+ * @{
+ */
+
+/** NV - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t BACKKEY3;                           /**< Backdoor Comparison Key 3., offset: 0x0 */
+  __I  uint8_t BACKKEY2;                           /**< Backdoor Comparison Key 2., offset: 0x1 */
+  __I  uint8_t BACKKEY1;                           /**< Backdoor Comparison Key 1., offset: 0x2 */
+  __I  uint8_t BACKKEY0;                           /**< Backdoor Comparison Key 0., offset: 0x3 */
+  __I  uint8_t BACKKEY7;                           /**< Backdoor Comparison Key 7., offset: 0x4 */
+  __I  uint8_t BACKKEY6;                           /**< Backdoor Comparison Key 6., offset: 0x5 */
+  __I  uint8_t BACKKEY5;                           /**< Backdoor Comparison Key 5., offset: 0x6 */
+  __I  uint8_t BACKKEY4;                           /**< Backdoor Comparison Key 4., offset: 0x7 */
+  __I  uint8_t FPROT3;                             /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
+  __I  uint8_t FPROT2;                             /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
+  __I  uint8_t FPROT1;                             /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
+  __I  uint8_t FPROT0;                             /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
+  __I  uint8_t FSEC;                               /**< Non-volatile Flash Security Register, offset: 0xC */
+  __I  uint8_t FOPT;                               /**< Non-volatile Flash Option Register, offset: 0xD */
+  __I  uint8_t FEPROT;                             /**< Non-volatile EERAM Protection Register, offset: 0xE */
+  __I  uint8_t FDPROT;                             /**< Non-volatile D-Flash Protection Register, offset: 0xF */
+} NV_Type;
+
+/* ----------------------------------------------------------------------------
+   -- NV Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup NV_Register_Masks NV Register Masks
+ * @{
+ */
+
+/*! @name BACKKEY3 - Backdoor Comparison Key 3. */
+#define NV_BACKKEY3_KEY_MASK                     (0xFFU)
+#define NV_BACKKEY3_KEY_SHIFT                    (0U)
+#define NV_BACKKEY3_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
+
+/*! @name BACKKEY2 - Backdoor Comparison Key 2. */
+#define NV_BACKKEY2_KEY_MASK                     (0xFFU)
+#define NV_BACKKEY2_KEY_SHIFT                    (0U)
+#define NV_BACKKEY2_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
+
+/*! @name BACKKEY1 - Backdoor Comparison Key 1. */
+#define NV_BACKKEY1_KEY_MASK                     (0xFFU)
+#define NV_BACKKEY1_KEY_SHIFT                    (0U)
+#define NV_BACKKEY1_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
+
+/*! @name BACKKEY0 - Backdoor Comparison Key 0. */
+#define NV_BACKKEY0_KEY_MASK                     (0xFFU)
+#define NV_BACKKEY0_KEY_SHIFT                    (0U)
+#define NV_BACKKEY0_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
+
+/*! @name BACKKEY7 - Backdoor Comparison Key 7. */
+#define NV_BACKKEY7_KEY_MASK                     (0xFFU)
+#define NV_BACKKEY7_KEY_SHIFT                    (0U)
+#define NV_BACKKEY7_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
+
+/*! @name BACKKEY6 - Backdoor Comparison Key 6. */
+#define NV_BACKKEY6_KEY_MASK                     (0xFFU)
+#define NV_BACKKEY6_KEY_SHIFT                    (0U)
+#define NV_BACKKEY6_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
+
+/*! @name BACKKEY5 - Backdoor Comparison Key 5. */
+#define NV_BACKKEY5_KEY_MASK                     (0xFFU)
+#define NV_BACKKEY5_KEY_SHIFT                    (0U)
+#define NV_BACKKEY5_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
+
+/*! @name BACKKEY4 - Backdoor Comparison Key 4. */
+#define NV_BACKKEY4_KEY_MASK                     (0xFFU)
+#define NV_BACKKEY4_KEY_SHIFT                    (0U)
+#define NV_BACKKEY4_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
+
+/*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */
+#define NV_FPROT3_PROT_MASK                      (0xFFU)
+#define NV_FPROT3_PROT_SHIFT                     (0U)
+#define NV_FPROT3_PROT(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
+
+/*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */
+#define NV_FPROT2_PROT_MASK                      (0xFFU)
+#define NV_FPROT2_PROT_SHIFT                     (0U)
+#define NV_FPROT2_PROT(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
+
+/*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */
+#define NV_FPROT1_PROT_MASK                      (0xFFU)
+#define NV_FPROT1_PROT_SHIFT                     (0U)
+#define NV_FPROT1_PROT(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
+
+/*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */
+#define NV_FPROT0_PROT_MASK                      (0xFFU)
+#define NV_FPROT0_PROT_SHIFT                     (0U)
+#define NV_FPROT0_PROT(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
+
+/*! @name FSEC - Non-volatile Flash Security Register */
+#define NV_FSEC_SEC_MASK                         (0x3U)
+#define NV_FSEC_SEC_SHIFT                        (0U)
+#define NV_FSEC_SEC(x)                           (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
+#define NV_FSEC_FSLACC_MASK                      (0xCU)
+#define NV_FSEC_FSLACC_SHIFT                     (2U)
+#define NV_FSEC_FSLACC(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_MEEN_MASK                        (0x30U)
+#define NV_FSEC_MEEN_SHIFT                       (4U)
+#define NV_FSEC_MEEN(x)                          (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
+#define NV_FSEC_KEYEN_MASK                       (0xC0U)
+#define NV_FSEC_KEYEN_SHIFT                      (6U)
+#define NV_FSEC_KEYEN(x)                         (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
+
+/*! @name FOPT - Non-volatile Flash Option Register */
+#define NV_FOPT_LPBOOT_MASK                      (0x1U)
+#define NV_FOPT_LPBOOT_SHIFT                     (0U)
+#define NV_FOPT_LPBOOT(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK)
+#define NV_FOPT_EZPORT_DIS_MASK                  (0x2U)
+#define NV_FOPT_EZPORT_DIS_SHIFT                 (1U)
+#define NV_FOPT_EZPORT_DIS(x)                    (((uint8_t)(((uint8_t)(x)) << NV_FOPT_EZPORT_DIS_SHIFT)) & NV_FOPT_EZPORT_DIS_MASK)
+#define NV_FOPT_NMI_DIS_MASK                     (0x4U)
+#define NV_FOPT_NMI_DIS_SHIFT                    (2U)
+#define NV_FOPT_NMI_DIS(x)                       (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
+
+/*! @name FEPROT - Non-volatile EERAM Protection Register */
+#define NV_FEPROT_EPROT_MASK                     (0xFFU)
+#define NV_FEPROT_EPROT_SHIFT                    (0U)
+#define NV_FEPROT_EPROT(x)                       (((uint8_t)(((uint8_t)(x)) << NV_FEPROT_EPROT_SHIFT)) & NV_FEPROT_EPROT_MASK)
+
+/*! @name FDPROT - Non-volatile D-Flash Protection Register */
+#define NV_FDPROT_DPROT_MASK                     (0xFFU)
+#define NV_FDPROT_DPROT_SHIFT                    (0U)
+#define NV_FDPROT_DPROT(x)                       (((uint8_t)(((uint8_t)(x)) << NV_FDPROT_DPROT_SHIFT)) & NV_FDPROT_DPROT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group NV_Register_Masks */
+
+
+/* NV - Peripheral instance base addresses */
+/** Peripheral FTFE_FlashConfig base address */
+#define FTFE_FlashConfig_BASE                    (0x400u)
+/** Peripheral FTFE_FlashConfig base pointer */
+#define FTFE_FlashConfig                         ((NV_Type *)FTFE_FlashConfig_BASE)
+/** Array initializer of NV peripheral base addresses */
+#define NV_BASE_ADDRS                            { FTFE_FlashConfig_BASE }
+/** Array initializer of NV peripheral base pointers */
+#define NV_BASE_PTRS                             { FTFE_FlashConfig }
+
+/*!
+ * @}
+ */ /* end of group NV_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- OSC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC0_Peripheral_Access_Layer OSC Peripheral Access Layer
+ * @{
+ */
+
+/** OSC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t CR;                                 /**< OSC Control Register, offset: 0x0 */
+       uint8_t RESERVED_0[1];
+  __IO uint8_t DIV;                                /**< OSC0_DIV, offset: 0x2 */
+} OSC0_Type;
+
+/* ----------------------------------------------------------------------------
+   -- OSC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OSC0_Register_Masks OSC Register Masks
+ * @{
+ */
+
+/*! @name CR - OSC Control Register */
+#define OSC0_CR_SC16P_MASK                        (0x1U)
+#define OSC0_CR_SC16P_SHIFT                       (0U)
+#define OSC0_CR_SC16P(x)                          (((uint8_t)(((uint8_t)(x)) << OSC0_CR_SC16P_SHIFT)) & OSC0_CR_SC16P_MASK)
+#define OSC0_CR_SC8P_MASK                         (0x2U)
+#define OSC0_CR_SC8P_SHIFT                        (1U)
+#define OSC0_CR_SC8P(x)                           (((uint8_t)(((uint8_t)(x)) << OSC0_CR_SC8P_SHIFT)) & OSC0_CR_SC8P_MASK)
+#define OSC_CR_SC8P                               OSC0_CR_SC8P(1)
+#define OSC0_CR_SC4P_MASK                         (0x4U)
+#define OSC0_CR_SC4P_SHIFT                        (2U)
+#define OSC0_CR_SC4P(x)                           (((uint8_t)(((uint8_t)(x)) << OSC0_CR_SC4P_SHIFT)) & OSC0_CR_SC4P_MASK)
+#define OSC_CR_SC4P                               OSC0_CR_SC4P(1)
+#define OSC0_CR_SC2P_MASK                         (0x8U)
+#define OSC0_CR_SC2P_SHIFT                        (3U)
+#define OSC0_CR_SC2P(x)                           (((uint8_t)(((uint8_t)(x)) << OSC0_CR_SC2P_SHIFT)) & OSC0_CR_SC2P_MASK)
+#define OSC_CR_SC2P                               OSC0_CR_SC2P(1)
+#define OSC0_CR_EREFSTEN_MASK                     (0x20U)
+#define OSC0_CR_EREFSTEN_SHIFT                    (5U)
+#define OSC0_CR_EREFSTEN(x)                       (((uint8_t)(((uint8_t)(x)) << OSC0_CR_EREFSTEN_SHIFT)) & OSC0_CR_EREFSTEN_MASK)
+#define OSC0_CR_ERCLKEN_MASK                      (0x80U)
+#define OSC0_CR_ERCLKEN_SHIFT                     (7U)
+#define OSC0_CR_ERCLKEN(x)                        (((uint8_t)(((uint8_t)(x)) << OSC0_CR_ERCLKEN_SHIFT)) & OSC0_CR_ERCLKEN_MASK)
+
+/*! @name DIV - OSC0_DIV */
+#define OSC0_DIV_ERPS_MASK                        (0xC0U)
+#define OSC0_DIV_ERPS_SHIFT                       (6U)
+#define OSC0_DIV_ERPS(x)                          (((uint8_t)(((uint8_t)(x)) << OSC0_DIV_ERPS_SHIFT)) & OSC0_DIV_ERPS_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group OSC0_Register_Masks */
+
+
+/* OSC - Peripheral instance base addresses */
+/** Peripheral OSC base address */
+#define OSC0_BASE                                 (0x40065000u)
+/** Peripheral OSC base pointer */
+#define OSC0                                      ((OSC0_Type *)OSC0_BASE)
+/** Array initializer of OSC peripheral base addresses */
+#define OSC0_BASE_ADDRS                           { OSC0_BASE }
+/** Array initializer of OSC peripheral base pointers */
+#define OSC0_BASE_PTRS                            { OSC }
+
+/*!
+ * @}
+ */ /* end of group OSC0_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PDB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
+ * @{
+ */
+
+/** PDB - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC;                                /**< Status and Control register, offset: 0x0 */
+  __IO uint32_t MOD;                               /**< Modulus register, offset: 0x4 */
+  __I  uint32_t CNT;                               /**< Counter register, offset: 0x8 */
+  __IO uint32_t IDLY;                              /**< Interrupt Delay register, offset: 0xC */
+  struct {                                         /* offset: 0x10, array step: 0x28 */
+    __IO uint32_t C1;                                /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
+    __IO uint32_t S;                                 /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
+    __IO uint32_t DLY[2];                            /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
+         uint8_t RESERVED_0[24];
+  } CH[2];
+       uint8_t RESERVED_0[240];
+  struct {                                         /* offset: 0x150, array step: 0x8 */
+    __IO uint32_t INTC;                              /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
+    __IO uint32_t INT;                               /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
+  } DAC[2];
+       uint8_t RESERVED_1[48];
+  __IO uint32_t POEN;                              /**< Pulse-Out n Enable register, offset: 0x190 */
+  __IO uint32_t PODLY[4];                          /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
+} PDB_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PDB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PDB_Register_Masks PDB Register Masks
+ * @{
+ */
+
+/*! @name SC - Status and Control register */
+#define PDB_SC_LDOK_MASK                         (0x1U)
+#define PDB_SC_LDOK_SHIFT                        (0U)
+#define PDB_SC_LDOK(x)                           (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK)
+#define PDB_SC_CONT_MASK                         (0x2U)
+#define PDB_SC_CONT_SHIFT                        (1U)
+#define PDB_SC_CONT(x)                           (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK)
+#define PDB_SC_MULT_MASK                         (0xCU)
+#define PDB_SC_MULT_SHIFT                        (2U)
+#define PDB_SC_MULT(x)                           (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK)
+#define PDB_SC_PDBIE_MASK                        (0x20U)
+#define PDB_SC_PDBIE_SHIFT                       (5U)
+#define PDB_SC_PDBIE(x)                          (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK)
+#define PDB_SC_PDBIF_MASK                        (0x40U)
+#define PDB_SC_PDBIF_SHIFT                       (6U)
+#define PDB_SC_PDBIF(x)                          (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK)
+#define PDB_SC_PDBEN_MASK                        (0x80U)
+#define PDB_SC_PDBEN_SHIFT                       (7U)
+#define PDB_SC_PDBEN(x)                          (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK)
+#define PDB_SC_TRGSEL_MASK                       (0xF00U)
+#define PDB_SC_TRGSEL_SHIFT                      (8U)
+#define PDB_SC_TRGSEL(x)                         (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK)
+#define PDB_SC_PRESCALER_MASK                    (0x7000U)
+#define PDB_SC_PRESCALER_SHIFT                   (12U)
+#define PDB_SC_PRESCALER(x)                      (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK)
+#define PDB_SC_DMAEN_MASK                        (0x8000U)
+#define PDB_SC_DMAEN_SHIFT                       (15U)
+#define PDB_SC_DMAEN(x)                          (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK)
+#define PDB_SC_SWTRIG_MASK                       (0x10000U)
+#define PDB_SC_SWTRIG_SHIFT                      (16U)
+#define PDB_SC_SWTRIG(x)                         (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK)
+#define PDB_SC_PDBEIE_MASK                       (0x20000U)
+#define PDB_SC_PDBEIE_SHIFT                      (17U)
+#define PDB_SC_PDBEIE(x)                         (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK)
+#define PDB_SC_LDMOD_MASK                        (0xC0000U)
+#define PDB_SC_LDMOD_SHIFT                       (18U)
+#define PDB_SC_LDMOD(x)                          (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK)
+
+/*! @name MOD - Modulus register */
+#define PDB_MOD_MOD_MASK                         (0xFFFFU)
+#define PDB_MOD_MOD_SHIFT                        (0U)
+#define PDB_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK)
+
+/*! @name CNT - Counter register */
+#define PDB_CNT_CNT_MASK                         (0xFFFFU)
+#define PDB_CNT_CNT_SHIFT                        (0U)
+#define PDB_CNT_CNT(x)                           (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK)
+
+/*! @name IDLY - Interrupt Delay register */
+#define PDB_IDLY_IDLY_MASK                       (0xFFFFU)
+#define PDB_IDLY_IDLY_SHIFT                      (0U)
+#define PDB_IDLY_IDLY(x)                         (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK)
+
+/*! @name C1 - Channel n Control register 1 */
+#define PDB_C1_EN_MASK                           (0xFFU)
+#define PDB_C1_EN_SHIFT                          (0U)
+#define PDB_C1_EN(x)                             (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK)
+#define PDB_C1_TOS_MASK                          (0xFF00U)
+#define PDB_C1_TOS_SHIFT                         (8U)
+#define PDB_C1_TOS(x)                            (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK)
+#define PDB_C1_BB_MASK                           (0xFF0000U)
+#define PDB_C1_BB_SHIFT                          (16U)
+#define PDB_C1_BB(x)                             (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK)
+
+/* The count of PDB_C1 */
+#define PDB_C1_COUNT                             (2U)
+
+/*! @name S - Channel n Status register */
+#define PDB_S_ERR_MASK                           (0xFFU)
+#define PDB_S_ERR_SHIFT                          (0U)
+#define PDB_S_ERR(x)                             (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK)
+#define PDB_S_CF_MASK                            (0xFF0000U)
+#define PDB_S_CF_SHIFT                           (16U)
+#define PDB_S_CF(x)                              (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK)
+
+/* The count of PDB_S */
+#define PDB_S_COUNT                              (2U)
+
+/*! @name DLY - Channel n Delay 0 register..Channel n Delay 1 register */
+#define PDB_DLY_DLY_MASK                         (0xFFFFU)
+#define PDB_DLY_DLY_SHIFT                        (0U)
+#define PDB_DLY_DLY(x)                           (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK)
+
+/* The count of PDB_DLY */
+#define PDB_DLY_COUNT                            (2U)
+
+/* The count of PDB_DLY */
+#define PDB_DLY_COUNT2                           (2U)
+
+/*! @name INTC - DAC Interval Trigger n Control register */
+#define PDB_INTC_TOE_MASK                        (0x1U)
+#define PDB_INTC_TOE_SHIFT                       (0U)
+#define PDB_INTC_TOE(x)                          (((uint32_t)(((uint32_t)(x)) << PDB_INTC_TOE_SHIFT)) & PDB_INTC_TOE_MASK)
+#define PDB_INTC_EXT_MASK                        (0x2U)
+#define PDB_INTC_EXT_SHIFT                       (1U)
+#define PDB_INTC_EXT(x)                          (((uint32_t)(((uint32_t)(x)) << PDB_INTC_EXT_SHIFT)) & PDB_INTC_EXT_MASK)
+
+/* The count of PDB_INTC */
+#define PDB_INTC_COUNT                           (2U)
+
+/*! @name INT - DAC Interval n register */
+#define PDB_INT_INT_MASK                         (0xFFFFU)
+#define PDB_INT_INT_SHIFT                        (0U)
+#define PDB_INT_INT(x)                           (((uint32_t)(((uint32_t)(x)) << PDB_INT_INT_SHIFT)) & PDB_INT_INT_MASK)
+
+/* The count of PDB_INT */
+#define PDB_INT_COUNT                            (2U)
+
+/*! @name POEN - Pulse-Out n Enable register */
+#define PDB_POEN_POEN_MASK                       (0xFFU)
+#define PDB_POEN_POEN_SHIFT                      (0U)
+#define PDB_POEN_POEN(x)                         (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK)
+
+/*! @name PODLY - Pulse-Out n Delay register */
+#define PDB_PODLY_DLY2_MASK                      (0xFFFFU)
+#define PDB_PODLY_DLY2_SHIFT                     (0U)
+#define PDB_PODLY_DLY2(x)                        (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK)
+#define PDB_PODLY_DLY1_MASK                      (0xFFFF0000U)
+#define PDB_PODLY_DLY1_SHIFT                     (16U)
+#define PDB_PODLY_DLY1(x)                        (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK)
+
+/* The count of PDB_PODLY */
+#define PDB_PODLY_COUNT                          (4U)
+
+
+/*!
+ * @}
+ */ /* end of group PDB_Register_Masks */
+
+
+/* PDB - Peripheral instance base addresses */
+/** Peripheral PDB0 base address */
+#define PDB0_BASE                                (0x40036000u)
+/** Peripheral PDB0 base pointer */
+#define PDB0                                     ((PDB_Type *)PDB0_BASE)
+/** Array initializer of PDB peripheral base addresses */
+#define PDB_BASE_ADDRS                           { PDB0_BASE }
+/** Array initializer of PDB peripheral base pointers */
+#define PDB_BASE_PTRS                            { PDB0 }
+/** Interrupt vectors for the PDB peripheral type */
+#define PDB_IRQS                                 { PDB0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group PDB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PIT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
+ * @{
+ */
+
+/** PIT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< PIT Module Control Register, offset: 0x0 */
+       uint8_t RESERVED_0[220];
+  __I  uint32_t LTMR64H;                           /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
+  __I  uint32_t LTMR64L;                           /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
+       uint8_t RESERVED_1[24];
+  struct {                                         /* offset: 0x100, array step: 0x10 */
+    __IO uint32_t LDVAL;                             /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
+    __I  uint32_t CVAL;                              /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
+    __IO uint32_t TCTRL;                             /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
+    __IO uint32_t TFLG;                              /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
+  } CHANNEL[4];
+} PIT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PIT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PIT_Register_Masks PIT Register Masks
+ * @{
+ */
+
+/*! @name MCR - PIT Module Control Register */
+#define PIT_MCR_FRZ_MASK                         (0x1U)
+#define PIT_MCR_FRZ_SHIFT                        (0U)
+#define PIT_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
+#define PIT_MCR_MDIS_MASK                        (0x2U)
+#define PIT_MCR_MDIS_SHIFT                       (1U)
+#define PIT_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
+
+/*! @name LTMR64H - PIT Upper Lifetime Timer Register */
+#define PIT_LTMR64H_LTH_MASK                     (0xFFFFFFFFU)
+#define PIT_LTMR64H_LTH_SHIFT                    (0U)
+#define PIT_LTMR64H_LTH(x)                       (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
+
+/*! @name LTMR64L - PIT Lower Lifetime Timer Register */
+#define PIT_LTMR64L_LTL_MASK                     (0xFFFFFFFFU)
+#define PIT_LTMR64L_LTL_SHIFT                    (0U)
+#define PIT_LTMR64L_LTL(x)                       (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
+
+/*! @name LDVAL - Timer Load Value Register */
+#define PIT_LDVAL_TSV_MASK                       (0xFFFFFFFFU)
+#define PIT_LDVAL_TSV_SHIFT                      (0U)
+#define PIT_LDVAL_TSV(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
+
+/* The count of PIT_LDVAL */
+#define PIT_LDVAL_COUNT                          (4U)
+
+/*! @name CVAL - Current Timer Value Register */
+#define PIT_CVAL_TVL_MASK                        (0xFFFFFFFFU)
+#define PIT_CVAL_TVL_SHIFT                       (0U)
+#define PIT_CVAL_TVL(x)                          (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
+
+/* The count of PIT_CVAL */
+#define PIT_CVAL_COUNT                           (4U)
+
+/*! @name TCTRL - Timer Control Register */
+#define PIT_TCTRL_TEN_MASK                       (0x1U)
+#define PIT_TCTRL_TEN_SHIFT                      (0U)
+#define PIT_TCTRL_TEN(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
+#define PIT_TCTRL_TIE_MASK                       (0x2U)
+#define PIT_TCTRL_TIE_SHIFT                      (1U)
+#define PIT_TCTRL_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
+#define PIT_TCTRL_CHN_MASK                       (0x4U)
+#define PIT_TCTRL_CHN_SHIFT                      (2U)
+#define PIT_TCTRL_CHN(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
+
+/* The count of PIT_TCTRL */
+#define PIT_TCTRL_COUNT                          (4U)
+
+/*! @name TFLG - Timer Flag Register */
+#define PIT_TFLG_TIF_MASK                        (0x1U)
+#define PIT_TFLG_TIF_SHIFT                       (0U)
+#define PIT_TFLG_TIF(x)                          (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
+
+/* The count of PIT_TFLG */
+#define PIT_TFLG_COUNT                           (4U)
+
+
+/*!
+ * @}
+ */ /* end of group PIT_Register_Masks */
+
+
+/* PIT - Peripheral instance base addresses */
+/** Peripheral PIT base address */
+#define PIT_BASE                                 (0x40037000u)
+/** Peripheral PIT base pointer */
+#define PIT                                      ((PIT_Type *)PIT_BASE)
+/** Array initializer of PIT peripheral base addresses */
+#define PIT_BASE_ADDRS                           { PIT_BASE }
+/** Array initializer of PIT peripheral base pointers */
+#define PIT_BASE_PTRS                            { PIT }
+/** Interrupt vectors for the PIT peripheral type */
+#define PIT_IRQS                                 { { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn } }
+
+/*!
+ * @}
+ */ /* end of group PIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
+ * @{
+ */
+
+/** PMC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t LVDSC1;                             /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
+  __IO uint8_t LVDSC2;                             /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
+  __IO uint8_t REGSC;                              /**< Regulator Status And Control register, offset: 0x2 */
+} PMC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- PMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PMC_Register_Masks PMC Register Masks
+ * @{
+ */
+
+/*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */
+#define PMC_LVDSC1_LVDV_MASK                     (0x3U)
+#define PMC_LVDSC1_LVDV_SHIFT                    (0U)
+#define PMC_LVDSC1_LVDV(x)                       (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDRE_MASK                    (0x10U)
+#define PMC_LVDSC1_LVDRE_SHIFT                   (4U)
+#define PMC_LVDSC1_LVDRE(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
+#define PMC_LVDSC1_LVDIE_MASK                    (0x20U)
+#define PMC_LVDSC1_LVDIE_SHIFT                   (5U)
+#define PMC_LVDSC1_LVDIE(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
+#define PMC_LVDSC1_LVDACK_MASK                   (0x40U)
+#define PMC_LVDSC1_LVDACK_SHIFT                  (6U)
+#define PMC_LVDSC1_LVDACK(x)                     (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
+#define PMC_LVDSC1_LVDF_MASK                     (0x80U)
+#define PMC_LVDSC1_LVDF_SHIFT                    (7U)
+#define PMC_LVDSC1_LVDF(x)                       (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
+
+/*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */
+#define PMC_LVDSC2_LVWV_MASK                     (0x3U)
+#define PMC_LVDSC2_LVWV_SHIFT                    (0U)
+#define PMC_LVDSC2_LVWV(x)                       (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWIE_MASK                    (0x20U)
+#define PMC_LVDSC2_LVWIE_SHIFT                   (5U)
+#define PMC_LVDSC2_LVWIE(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
+#define PMC_LVDSC2_LVWACK_MASK                   (0x40U)
+#define PMC_LVDSC2_LVWACK_SHIFT                  (6U)
+#define PMC_LVDSC2_LVWACK(x)                     (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
+#define PMC_LVDSC2_LVWF_MASK                     (0x80U)
+#define PMC_LVDSC2_LVWF_SHIFT                    (7U)
+#define PMC_LVDSC2_LVWF(x)                       (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
+
+/*! @name REGSC - Regulator Status And Control register */
+#define PMC_REGSC_BGBE_MASK                      (0x1U)
+#define PMC_REGSC_BGBE_SHIFT                     (0U)
+#define PMC_REGSC_BGBE(x)                        (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
+#define PMC_REGSC_REGONS_MASK                    (0x4U)
+#define PMC_REGSC_REGONS_SHIFT                   (2U)
+#define PMC_REGSC_REGONS(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
+#define PMC_REGSC_ACKISO_MASK                    (0x8U)
+#define PMC_REGSC_ACKISO_SHIFT                   (3U)
+#define PMC_REGSC_ACKISO(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
+#define PMC_REGSC_BGEN_MASK                      (0x10U)
+#define PMC_REGSC_BGEN_SHIFT                     (4U)
+#define PMC_REGSC_BGEN(x)                        (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group PMC_Register_Masks */
+
+
+/* PMC - Peripheral instance base addresses */
+/** Peripheral PMC base address */
+#define PMC_BASE                                 (0x4007D000u)
+/** Peripheral PMC base pointer */
+#define PMC                                      ((PMC_Type *)PMC_BASE)
+/** Array initializer of PMC peripheral base addresses */
+#define PMC_BASE_ADDRS                           { PMC_BASE }
+/** Array initializer of PMC peripheral base pointers */
+#define PMC_BASE_PTRS                            { PMC }
+/** Interrupt vectors for the PMC peripheral type */
+#define PMC_IRQS                                 { LVD_LVW_IRQn }
+
+/*!
+ * @}
+ */ /* end of group PMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- PORT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
+ * @{
+ */
+
+/** PORT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PCR[32];                           /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
+  __O  uint32_t GPCLR;                             /**< Global Pin Control Low Register, offset: 0x80 */
+  __O  uint32_t GPCHR;                             /**< Global Pin Control High Register, offset: 0x84 */
+       uint8_t RESERVED_0[24];
+  __IO uint32_t ISFR;                              /**< Interrupt Status Flag Register, offset: 0xA0 */
+       uint8_t RESERVED_1[28];
+  __IO uint32_t DFER;                              /**< Digital Filter Enable Register, offset: 0xC0 */
+  __IO uint32_t DFCR;                              /**< Digital Filter Clock Register, offset: 0xC4 */
+  __IO uint32_t DFWR;                              /**< Digital Filter Width Register, offset: 0xC8 */
+} PORT_TypeDef;
+
+/* ----------------------------------------------------------------------------
+   -- PORT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PORT_Register_Masks PORT Register Masks
+ * @{
+ */
+
+/*! @name PCR - Pin Control Register n */
+#define PORTx_PCRn_PS_MASK                         (0x1U)
+#define PORTx_PCRn_PS_SHIFT                        (0U)
+#define PORTx_PCRn_PS_SET(x)                       (((uint32_t)(((uint32_t)(x)) << PORTx_PCRn_PS_SHIFT)) & PORTx_PCRn_PS_MASK)
+#define PORTx_PCRn_PS                              PORTx_PCRn_PS_SET(1)
+#define PORTx_PCRn_PE_MASK                         (0x2U)
+#define PORTx_PCRn_PE_SHIFT                        (1U)
+#define PORTx_PCRn_PE_SET(x)                       (((uint32_t)(((uint32_t)(x)) << PORTx_PCRn_PE_SHIFT)) & PORTx_PCRn_PE_MASK)
+#define PORTx_PCRn_PE                              PORTx_PCRn_PE_SET(1)
+#define PORTx_PCRn_SRE_MASK                        (0x4U)
+#define PORTx_PCRn_SRE_SHIFT                       (2U)
+#define PORTx_PCRn_SRE(x)                          (((uint32_t)(((uint32_t)(x)) << PORTx_PCRn_SRE_SHIFT)) & PORTx_PCRn_SRE_MASK)
+#define PORTx_PCRn_PFE_MASK                        (0x10U)
+#define PORTx_PCRn_PFE_SHIFT                       (4U)
+#define PORTx_PCRn_PFE(x)                          (((uint32_t)(((uint32_t)(x)) << PORTx_PCRn_PFE_SHIFT)) & PORTx_PCRn_PFE_MASK)
+#define PORTx_PCRn_ODE_MASK                        (0x20U)
+#define PORTx_PCRn_ODE_SHIFT                       (5U)
+#define PORTx_PCRn_ODE_SET(x)                      (((uint32_t)(((uint32_t)(x)) << PORTx_PCRn_ODE_SHIFT)) & PORTx_PCRn_ODE_MASK)
+#define PORTx_PCRn_ODE                             PORTx_PCRn_ODE_SET(1)
+#define PORTx_PCRn_DSE_MASK                        (0x40U)
+#define PORTx_PCRn_DSE_SHIFT                       (6U)
+#define PORTx_PCRn_DSE(x)                          (((uint32_t)(((uint32_t)(x)) << PORTx_PCRn_DSE_SHIFT)) & PORTx_PCRn_DSE_MASK)
+#define PORTx_PCRn_MUX_MASK                        (0x700U)
+#define PORTx_PCRn_MUX_SHIFT                       (8U)
+#define PORTx_PCRn_MUX(x)                          (((uint32_t)(((uint32_t)(x)) << PORTx_PCRn_MUX_SHIFT)) & PORTx_PCRn_MUX_MASK)
+#define PORTx_PCRn_LK_MASK                         (0x8000U)
+#define PORTx_PCRn_LK_SHIFT                        (15U)
+#define PORTx_PCRn_LK(x)                           (((uint32_t)(((uint32_t)(x)) << PORTx_PCRn_LK_SHIFT)) & PORTx_PCRn_LK_MASK)
+#define PORTx_PCRn_IRQC_MASK                       (0xF0000U)
+#define PORTx_PCRn_IRQC_SHIFT                      (16U)
+#define PORTx_PCRn_IRQC(x)                         (((uint32_t)(((uint32_t)(x)) << PORTx_PCRn_IRQC_SHIFT)) & PORTx_PCRn_IRQC_MASK)
+#define PORTx_PCRn_ISF_MASK                        (0x1000000U)
+#define PORTx_PCRn_ISF_SHIFT                       (24U)
+#define PORTx_PCRn_ISF(x)                          (((uint32_t)(((uint32_t)(x)) << PORTx_PCRn_ISF_SHIFT)) & PORTx_PCRn_ISF_MASK)
+
+/* The count of PORT_PCR */
+#define PORTx_PCRn_COUNT                           (32U)
+
+/*! @name GPCLR - Global Pin Control Low Register */
+#define PORT_GPCLR_GPWD_MASK                     (0xFFFFU)
+#define PORT_GPCLR_GPWD_SHIFT                    (0U)
+#define PORT_GPCLR_GPWD(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWE_MASK                     (0xFFFF0000U)
+#define PORT_GPCLR_GPWE_SHIFT                    (16U)
+#define PORT_GPCLR_GPWE(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
+
+/*! @name GPCHR - Global Pin Control High Register */
+#define PORT_GPCHR_GPWD_MASK                     (0xFFFFU)
+#define PORT_GPCHR_GPWD_SHIFT                    (0U)
+#define PORT_GPCHR_GPWD(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWE_MASK                     (0xFFFF0000U)
+#define PORT_GPCHR_GPWE_SHIFT                    (16U)
+#define PORT_GPCHR_GPWE(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
+
+/*! @name ISFR - Interrupt Status Flag Register */
+#define PORT_ISFR_ISF_MASK                       (0xFFFFFFFFU)
+#define PORT_ISFR_ISF_SHIFT                      (0U)
+#define PORT_ISFR_ISF(x)                         (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
+
+/*! @name DFER - Digital Filter Enable Register */
+#define PORT_DFER_DFE_MASK                       (0xFFFFFFFFU)
+#define PORT_DFER_DFE_SHIFT                      (0U)
+#define PORT_DFER_DFE(x)                         (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)
+
+/*! @name DFCR - Digital Filter Clock Register */
+#define PORT_DFCR_CS_MASK                        (0x1U)
+#define PORT_DFCR_CS_SHIFT                       (0U)
+#define PORT_DFCR_CS(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)
+
+/*! @name DFWR - Digital Filter Width Register */
+#define PORT_DFWR_FILT_MASK                      (0x1FU)
+#define PORT_DFWR_FILT_SHIFT                     (0U)
+#define PORT_DFWR_FILT(x)                        (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group PORT_Register_Masks */
+
+
+/* PORT - Peripheral instance base addresses */
+/** Peripheral PORTA base address */
+#define PORTA_BASE                               (0x40049000u)
+/** Peripheral PORTA base pointer */
+#define PORTA                                    ((PORT_TypeDef *)PORTA_BASE)
+/** Peripheral PORTB base address */
+#define PORTB_BASE                               (0x4004A000u)
+/** Peripheral PORTB base pointer */
+#define PORTB                                    ((PORT_TypeDef *)PORTB_BASE)
+/** Peripheral PORTC base address */
+#define PORTC_BASE                               (0x4004B000u)
+/** Peripheral PORTC base pointer */
+#define PORTC                                    ((PORT_TypeDef *)PORTC_BASE)
+/** Peripheral PORTD base address */
+#define PORTD_BASE                               (0x4004C000u)
+/** Peripheral PORTD base pointer */
+#define PORTD                                    ((PORT_TypeDef *)PORTD_BASE)
+/** Peripheral PORTE base address */
+#define PORTE_BASE                               (0x4004D000u)
+/** Peripheral PORTE base pointer */
+#define PORTE                                    ((PORT_TypeDef *)PORTE_BASE)
+/** Array initializer of PORT peripheral base addresses */
+#define PORT_BASE_ADDRS                          { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
+/** Array initializer of PORT peripheral base pointers */
+#define PORT_BASE_PTRS                           { PORTA, PORTB, PORTC, PORTD, PORTE }
+/** Interrupt vectors for the PORT peripheral type */
+#define PORT_IRQS                                { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
+
+/*!
+ * @}
+ */ /* end of group PORT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RCM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
+ * @{
+ */
+
+/** RCM - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t SRS0;                               /**< System Reset Status Register 0, offset: 0x0 */
+  __I  uint8_t SRS1;                               /**< System Reset Status Register 1, offset: 0x1 */
+       uint8_t RESERVED_0[2];
+  __IO uint8_t RPFC;                               /**< Reset Pin Filter Control register, offset: 0x4 */
+  __IO uint8_t RPFW;                               /**< Reset Pin Filter Width register, offset: 0x5 */
+       uint8_t RESERVED_1[1];
+  __I  uint8_t MR;                                 /**< Mode Register, offset: 0x7 */
+  __IO uint8_t SSRS0;                              /**< Sticky System Reset Status Register 0, offset: 0x8 */
+  __IO uint8_t SSRS1;                              /**< Sticky System Reset Status Register 1, offset: 0x9 */
+} RCM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- RCM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RCM_Register_Masks RCM Register Masks
+ * @{
+ */
+
+/*! @name SRS0 - System Reset Status Register 0 */
+#define RCM_SRS0_WAKEUP_MASK                     (0x1U)
+#define RCM_SRS0_WAKEUP_SHIFT                    (0U)
+#define RCM_SRS0_WAKEUP(x)                       (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
+#define RCM_SRS0_LVD_MASK                        (0x2U)
+#define RCM_SRS0_LVD_SHIFT                       (1U)
+#define RCM_SRS0_LVD(x)                          (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
+#define RCM_SRS0_LOC_MASK                        (0x4U)
+#define RCM_SRS0_LOC_SHIFT                       (2U)
+#define RCM_SRS0_LOC(x)                          (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK)
+#define RCM_SRS0_LOL_MASK                        (0x8U)
+#define RCM_SRS0_LOL_SHIFT                       (3U)
+#define RCM_SRS0_LOL(x)                          (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK)
+#define RCM_SRS0_WDOG_MASK                       (0x20U)
+#define RCM_SRS0_WDOG_SHIFT                      (5U)
+#define RCM_SRS0_WDOG(x)                         (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
+#define RCM_SRS0_PIN_MASK                        (0x40U)
+#define RCM_SRS0_PIN_SHIFT                       (6U)
+#define RCM_SRS0_PIN(x)                          (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
+#define RCM_SRS0_POR_MASK                        (0x80U)
+#define RCM_SRS0_POR_SHIFT                       (7U)
+#define RCM_SRS0_POR(x)                          (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
+
+/*! @name SRS1 - System Reset Status Register 1 */
+#define RCM_SRS1_JTAG_MASK                       (0x1U)
+#define RCM_SRS1_JTAG_SHIFT                      (0U)
+#define RCM_SRS1_JTAG(x)                         (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_JTAG_SHIFT)) & RCM_SRS1_JTAG_MASK)
+#define RCM_SRS1_LOCKUP_MASK                     (0x2U)
+#define RCM_SRS1_LOCKUP_SHIFT                    (1U)
+#define RCM_SRS1_LOCKUP(x)                       (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
+#define RCM_SRS1_SW_MASK                         (0x4U)
+#define RCM_SRS1_SW_SHIFT                        (2U)
+#define RCM_SRS1_SW(x)                           (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
+#define RCM_SRS1_MDM_AP_MASK                     (0x8U)
+#define RCM_SRS1_MDM_AP_SHIFT                    (3U)
+#define RCM_SRS1_MDM_AP(x)                       (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
+#define RCM_SRS1_EZPT_MASK                       (0x10U)
+#define RCM_SRS1_EZPT_SHIFT                      (4U)
+#define RCM_SRS1_EZPT(x)                         (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_EZPT_SHIFT)) & RCM_SRS1_EZPT_MASK)
+#define RCM_SRS1_SACKERR_MASK                    (0x20U)
+#define RCM_SRS1_SACKERR_SHIFT                   (5U)
+#define RCM_SRS1_SACKERR(x)                      (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
+
+/*! @name RPFC - Reset Pin Filter Control register */
+#define RCM_RPFC_RSTFLTSRW_MASK                  (0x3U)
+#define RCM_RPFC_RSTFLTSRW_SHIFT                 (0U)
+#define RCM_RPFC_RSTFLTSRW(x)                    (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSS_MASK                   (0x4U)
+#define RCM_RPFC_RSTFLTSS_SHIFT                  (2U)
+#define RCM_RPFC_RSTFLTSS(x)                     (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
+
+/*! @name RPFW - Reset Pin Filter Width register */
+#define RCM_RPFW_RSTFLTSEL_MASK                  (0x1FU)
+#define RCM_RPFW_RSTFLTSEL_SHIFT                 (0U)
+#define RCM_RPFW_RSTFLTSEL(x)                    (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
+
+/*! @name MR - Mode Register */
+#define RCM_MR_EZP_MS_MASK                       (0x2U)
+#define RCM_MR_EZP_MS_SHIFT                      (1U)
+#define RCM_MR_EZP_MS(x)                         (((uint8_t)(((uint8_t)(x)) << RCM_MR_EZP_MS_SHIFT)) & RCM_MR_EZP_MS_MASK)
+
+/*! @name SSRS0 - Sticky System Reset Status Register 0 */
+#define RCM_SSRS0_SWAKEUP_MASK                   (0x1U)
+#define RCM_SSRS0_SWAKEUP_SHIFT                  (0U)
+#define RCM_SSRS0_SWAKEUP(x)                     (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWAKEUP_SHIFT)) & RCM_SSRS0_SWAKEUP_MASK)
+#define RCM_SSRS0_SLVD_MASK                      (0x2U)
+#define RCM_SSRS0_SLVD_SHIFT                     (1U)
+#define RCM_SSRS0_SLVD(x)                        (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLVD_SHIFT)) & RCM_SSRS0_SLVD_MASK)
+#define RCM_SSRS0_SLOC_MASK                      (0x4U)
+#define RCM_SSRS0_SLOC_SHIFT                     (2U)
+#define RCM_SSRS0_SLOC(x)                        (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOC_SHIFT)) & RCM_SSRS0_SLOC_MASK)
+#define RCM_SSRS0_SLOL_MASK                      (0x8U)
+#define RCM_SSRS0_SLOL_SHIFT                     (3U)
+#define RCM_SSRS0_SLOL(x)                        (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOL_SHIFT)) & RCM_SSRS0_SLOL_MASK)
+#define RCM_SSRS0_SWDOG_MASK                     (0x20U)
+#define RCM_SSRS0_SWDOG_SHIFT                    (5U)
+#define RCM_SSRS0_SWDOG(x)                       (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWDOG_SHIFT)) & RCM_SSRS0_SWDOG_MASK)
+#define RCM_SSRS0_SPIN_MASK                      (0x40U)
+#define RCM_SSRS0_SPIN_SHIFT                     (6U)
+#define RCM_SSRS0_SPIN(x)                        (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPIN_SHIFT)) & RCM_SSRS0_SPIN_MASK)
+#define RCM_SSRS0_SPOR_MASK                      (0x80U)
+#define RCM_SSRS0_SPOR_SHIFT                     (7U)
+#define RCM_SSRS0_SPOR(x)                        (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPOR_SHIFT)) & RCM_SSRS0_SPOR_MASK)
+
+/*! @name SSRS1 - Sticky System Reset Status Register 1 */
+#define RCM_SSRS1_SJTAG_MASK                     (0x1U)
+#define RCM_SSRS1_SJTAG_SHIFT                    (0U)
+#define RCM_SSRS1_SJTAG(x)                       (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SJTAG_SHIFT)) & RCM_SSRS1_SJTAG_MASK)
+#define RCM_SSRS1_SLOCKUP_MASK                   (0x2U)
+#define RCM_SSRS1_SLOCKUP_SHIFT                  (1U)
+#define RCM_SSRS1_SLOCKUP(x)                     (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SLOCKUP_SHIFT)) & RCM_SSRS1_SLOCKUP_MASK)
+#define RCM_SSRS1_SSW_MASK                       (0x4U)
+#define RCM_SSRS1_SSW_SHIFT                      (2U)
+#define RCM_SSRS1_SSW(x)                         (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSW_SHIFT)) & RCM_SSRS1_SSW_MASK)
+#define RCM_SSRS1_SMDM_AP_MASK                   (0x8U)
+#define RCM_SSRS1_SMDM_AP_SHIFT                  (3U)
+#define RCM_SSRS1_SMDM_AP(x)                     (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SMDM_AP_SHIFT)) & RCM_SSRS1_SMDM_AP_MASK)
+#define RCM_SSRS1_SEZPT_MASK                     (0x10U)
+#define RCM_SSRS1_SEZPT_SHIFT                    (4U)
+#define RCM_SSRS1_SEZPT(x)                       (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SEZPT_SHIFT)) & RCM_SSRS1_SEZPT_MASK)
+#define RCM_SSRS1_SSACKERR_MASK                  (0x20U)
+#define RCM_SSRS1_SSACKERR_SHIFT                 (5U)
+#define RCM_SSRS1_SSACKERR(x)                    (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSACKERR_SHIFT)) & RCM_SSRS1_SSACKERR_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group RCM_Register_Masks */
+
+
+/* RCM - Peripheral instance base addresses */
+/** Peripheral RCM base address */
+#define RCM_BASE                                 (0x4007F000u)
+/** Peripheral RCM base pointer */
+#define RCM                                      ((RCM_Type *)RCM_BASE)
+/** Array initializer of RCM peripheral base addresses */
+#define RCM_BASE_ADDRS                           { RCM_BASE }
+/** Array initializer of RCM peripheral base pointers */
+#define RCM_BASE_PTRS                            { RCM }
+
+/*!
+ * @}
+ */ /* end of group RCM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
+ * @{
+ */
+
+/** RFSYS - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t REG[8];                            /**< Register file register, array offset: 0x0, array step: 0x4 */
+} RFSYS_Type;
+
+/* ----------------------------------------------------------------------------
+   -- RFSYS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
+ * @{
+ */
+
+/*! @name REG - Register file register */
+#define RFSYS_REG_LL_MASK                        (0xFFU)
+#define RFSYS_REG_LL_SHIFT                       (0U)
+#define RFSYS_REG_LL(x)                          (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
+#define RFSYS_REG_LH_MASK                        (0xFF00U)
+#define RFSYS_REG_LH_SHIFT                       (8U)
+#define RFSYS_REG_LH(x)                          (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
+#define RFSYS_REG_HL_MASK                        (0xFF0000U)
+#define RFSYS_REG_HL_SHIFT                       (16U)
+#define RFSYS_REG_HL(x)                          (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
+#define RFSYS_REG_HH_MASK                        (0xFF000000U)
+#define RFSYS_REG_HH_SHIFT                       (24U)
+#define RFSYS_REG_HH(x)                          (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
+
+/* The count of RFSYS_REG */
+#define RFSYS_REG_COUNT                          (8U)
+
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Register_Masks */
+
+
+/* RFSYS - Peripheral instance base addresses */
+/** Peripheral RFSYS base address */
+#define RFSYS_BASE                               (0x40041000u)
+/** Peripheral RFSYS base pointer */
+#define RFSYS                                    ((RFSYS_Type *)RFSYS_BASE)
+/** Array initializer of RFSYS peripheral base addresses */
+#define RFSYS_BASE_ADDRS                         { RFSYS_BASE }
+/** Array initializer of RFSYS peripheral base pointers */
+#define RFSYS_BASE_PTRS                          { RFSYS }
+
+/*!
+ * @}
+ */ /* end of group RFSYS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RFVBAT Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
+ * @{
+ */
+
+/** RFVBAT - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t REG[8];                            /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
+} RFVBAT_Type;
+
+/* ----------------------------------------------------------------------------
+   -- RFVBAT Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
+ * @{
+ */
+
+/*! @name REG - VBAT register file register */
+#define RFVBAT_REG_LL_MASK                       (0xFFU)
+#define RFVBAT_REG_LL_SHIFT                      (0U)
+#define RFVBAT_REG_LL(x)                         (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LL_SHIFT)) & RFVBAT_REG_LL_MASK)
+#define RFVBAT_REG_LH_MASK                       (0xFF00U)
+#define RFVBAT_REG_LH_SHIFT                      (8U)
+#define RFVBAT_REG_LH(x)                         (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LH_SHIFT)) & RFVBAT_REG_LH_MASK)
+#define RFVBAT_REG_HL_MASK                       (0xFF0000U)
+#define RFVBAT_REG_HL_SHIFT                      (16U)
+#define RFVBAT_REG_HL(x)                         (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HL_SHIFT)) & RFVBAT_REG_HL_MASK)
+#define RFVBAT_REG_HH_MASK                       (0xFF000000U)
+#define RFVBAT_REG_HH_SHIFT                      (24U)
+#define RFVBAT_REG_HH(x)                         (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HH_SHIFT)) & RFVBAT_REG_HH_MASK)
+
+/* The count of RFVBAT_REG */
+#define RFVBAT_REG_COUNT                         (8U)
+
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Register_Masks */
+
+
+/* RFVBAT - Peripheral instance base addresses */
+/** Peripheral RFVBAT base address */
+#define RFVBAT_BASE                              (0x4003E000u)
+/** Peripheral RFVBAT base pointer */
+#define RFVBAT                                   ((RFVBAT_Type *)RFVBAT_BASE)
+/** Array initializer of RFVBAT peripheral base addresses */
+#define RFVBAT_BASE_ADDRS                        { RFVBAT_BASE }
+/** Array initializer of RFVBAT peripheral base pointers */
+#define RFVBAT_BASE_PTRS                         { RFVBAT }
+
+/*!
+ * @}
+ */ /* end of group RFVBAT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RNG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
+ * @{
+ */
+
+/** RNG - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CR;                                /**< RNGA Control Register, offset: 0x0 */
+  __I  uint32_t SR;                                /**< RNGA Status Register, offset: 0x4 */
+  __O  uint32_t ER;                                /**< RNGA Entropy Register, offset: 0x8 */
+  __I  uint32_t OR;                                /**< RNGA Output Register, offset: 0xC */
+} RNG_Type;
+
+/* ----------------------------------------------------------------------------
+   -- RNG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RNG_Register_Masks RNG Register Masks
+ * @{
+ */
+
+/*! @name CR - RNGA Control Register */
+#define RNG_CR_GO_MASK                           (0x1U)
+#define RNG_CR_GO_SHIFT                          (0U)
+#define RNG_CR_GO(x)                             (((uint32_t)(((uint32_t)(x)) << RNG_CR_GO_SHIFT)) & RNG_CR_GO_MASK)
+#define RNG_CR_HA_MASK                           (0x2U)
+#define RNG_CR_HA_SHIFT                          (1U)
+#define RNG_CR_HA(x)                             (((uint32_t)(((uint32_t)(x)) << RNG_CR_HA_SHIFT)) & RNG_CR_HA_MASK)
+#define RNG_CR_INTM_MASK                         (0x4U)
+#define RNG_CR_INTM_SHIFT                        (2U)
+#define RNG_CR_INTM(x)                           (((uint32_t)(((uint32_t)(x)) << RNG_CR_INTM_SHIFT)) & RNG_CR_INTM_MASK)
+#define RNG_CR_CLRI_MASK                         (0x8U)
+#define RNG_CR_CLRI_SHIFT                        (3U)
+#define RNG_CR_CLRI(x)                           (((uint32_t)(((uint32_t)(x)) << RNG_CR_CLRI_SHIFT)) & RNG_CR_CLRI_MASK)
+#define RNG_CR_SLP_MASK                          (0x10U)
+#define RNG_CR_SLP_SHIFT                         (4U)
+#define RNG_CR_SLP(x)                            (((uint32_t)(((uint32_t)(x)) << RNG_CR_SLP_SHIFT)) & RNG_CR_SLP_MASK)
+
+/*! @name SR - RNGA Status Register */
+#define RNG_SR_SECV_MASK                         (0x1U)
+#define RNG_SR_SECV_SHIFT                        (0U)
+#define RNG_SR_SECV(x)                           (((uint32_t)(((uint32_t)(x)) << RNG_SR_SECV_SHIFT)) & RNG_SR_SECV_MASK)
+#define RNG_SR_LRS_MASK                          (0x2U)
+#define RNG_SR_LRS_SHIFT                         (1U)
+#define RNG_SR_LRS(x)                            (((uint32_t)(((uint32_t)(x)) << RNG_SR_LRS_SHIFT)) & RNG_SR_LRS_MASK)
+#define RNG_SR_ORU_MASK                          (0x4U)
+#define RNG_SR_ORU_SHIFT                         (2U)
+#define RNG_SR_ORU(x)                            (((uint32_t)(((uint32_t)(x)) << RNG_SR_ORU_SHIFT)) & RNG_SR_ORU_MASK)
+#define RNG_SR_ERRI_MASK                         (0x8U)
+#define RNG_SR_ERRI_SHIFT                        (3U)
+#define RNG_SR_ERRI(x)                           (((uint32_t)(((uint32_t)(x)) << RNG_SR_ERRI_SHIFT)) & RNG_SR_ERRI_MASK)
+#define RNG_SR_SLP_MASK                          (0x10U)
+#define RNG_SR_SLP_SHIFT                         (4U)
+#define RNG_SR_SLP(x)                            (((uint32_t)(((uint32_t)(x)) << RNG_SR_SLP_SHIFT)) & RNG_SR_SLP_MASK)
+#define RNG_SR_OREG_LVL_MASK                     (0xFF00U)
+#define RNG_SR_OREG_LVL_SHIFT                    (8U)
+#define RNG_SR_OREG_LVL(x)                       (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_LVL_SHIFT)) & RNG_SR_OREG_LVL_MASK)
+#define RNG_SR_OREG_SIZE_MASK                    (0xFF0000U)
+#define RNG_SR_OREG_SIZE_SHIFT                   (16U)
+#define RNG_SR_OREG_SIZE(x)                      (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_SIZE_SHIFT)) & RNG_SR_OREG_SIZE_MASK)
+
+/*! @name ER - RNGA Entropy Register */
+#define RNG_ER_EXT_ENT_MASK                      (0xFFFFFFFFU)
+#define RNG_ER_EXT_ENT_SHIFT                     (0U)
+#define RNG_ER_EXT_ENT(x)                        (((uint32_t)(((uint32_t)(x)) << RNG_ER_EXT_ENT_SHIFT)) & RNG_ER_EXT_ENT_MASK)
+
+/*! @name OR - RNGA Output Register */
+#define RNG_OR_RANDOUT_MASK                      (0xFFFFFFFFU)
+#define RNG_OR_RANDOUT_SHIFT                     (0U)
+#define RNG_OR_RANDOUT(x)                        (((uint32_t)(((uint32_t)(x)) << RNG_OR_RANDOUT_SHIFT)) & RNG_OR_RANDOUT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group RNG_Register_Masks */
+
+
+/* RNG - Peripheral instance base addresses */
+/** Peripheral RNG base address */
+#define RNG_BASE                                 (0x400A0000u)
+/** Peripheral RNG base pointer */
+#define RNG                                      ((RNG_Type *)RNG_BASE)
+/** Array initializer of RNG peripheral base addresses */
+#define RNG_BASE_ADDRS                           { RNG_BASE }
+/** Array initializer of RNG peripheral base pointers */
+#define RNG_BASE_PTRS                            { RNG }
+/** Interrupt vectors for the RNG peripheral type */
+#define RNG_IRQS                                 { RNG_IRQn }
+
+/*!
+ * @}
+ */ /* end of group RNG_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- RTC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t TSR;                               /**< RTC Time Seconds Register, offset: 0x0 */
+  __IO uint32_t TPR;                               /**< RTC Time Prescaler Register, offset: 0x4 */
+  __IO uint32_t TAR;                               /**< RTC Time Alarm Register, offset: 0x8 */
+  __IO uint32_t TCR;                               /**< RTC Time Compensation Register, offset: 0xC */
+  __IO uint32_t CR;                                /**< RTC Control Register, offset: 0x10 */
+  __IO uint32_t SR;                                /**< RTC Status Register, offset: 0x14 */
+  __IO uint32_t LR;                                /**< RTC Lock Register, offset: 0x18 */
+  __IO uint32_t IER;                               /**< RTC Interrupt Enable Register, offset: 0x1C */
+  __I  uint32_t TTSR;                              /**< RTC Tamper Time Seconds Register, offset: 0x20 */
+  __IO uint32_t MER;                               /**< RTC Monotonic Enable Register, offset: 0x24 */
+  __IO uint32_t MCLR;                              /**< RTC Monotonic Counter Low Register, offset: 0x28 */
+  __IO uint32_t MCHR;                              /**< RTC Monotonic Counter High Register, offset: 0x2C */
+       uint8_t RESERVED_0[2000];
+  __IO uint32_t WAR;                               /**< RTC Write Access Register, offset: 0x800 */
+  __IO uint32_t RAR;                               /**< RTC Read Access Register, offset: 0x804 */
+} RTC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- RTC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/*! @name TSR - RTC Time Seconds Register */
+#define RTC_TSR_TSR_MASK                         (0xFFFFFFFFU)
+#define RTC_TSR_TSR_SHIFT                        (0U)
+#define RTC_TSR_TSR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
+
+/*! @name TPR - RTC Time Prescaler Register */
+#define RTC_TPR_TPR_MASK                         (0xFFFFU)
+#define RTC_TPR_TPR_SHIFT                        (0U)
+#define RTC_TPR_TPR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
+
+/*! @name TAR - RTC Time Alarm Register */
+#define RTC_TAR_TAR_MASK                         (0xFFFFFFFFU)
+#define RTC_TAR_TAR_SHIFT                        (0U)
+#define RTC_TAR_TAR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
+
+/*! @name TCR - RTC Time Compensation Register */
+#define RTC_TCR_TCR_MASK                         (0xFFU)
+#define RTC_TCR_TCR_SHIFT                        (0U)
+#define RTC_TCR_TCR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
+#define RTC_TCR_CIR_MASK                         (0xFF00U)
+#define RTC_TCR_CIR_SHIFT                        (8U)
+#define RTC_TCR_CIR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
+#define RTC_TCR_TCV_MASK                         (0xFF0000U)
+#define RTC_TCR_TCV_SHIFT                        (16U)
+#define RTC_TCR_TCV(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
+#define RTC_TCR_CIC_MASK                         (0xFF000000U)
+#define RTC_TCR_CIC_SHIFT                        (24U)
+#define RTC_TCR_CIC(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
+
+/*! @name CR - RTC Control Register */
+#define RTC_CR_SWR_MASK                          (0x1U)
+#define RTC_CR_SWR_SHIFT                         (0U)
+#define RTC_CR_SWR(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
+#define RTC_CR_WPE_MASK                          (0x2U)
+#define RTC_CR_WPE_SHIFT                         (1U)
+#define RTC_CR_WPE(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
+#define RTC_CR_SUP_MASK                          (0x4U)
+#define RTC_CR_SUP_SHIFT                         (2U)
+#define RTC_CR_SUP(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
+#define RTC_CR_UM_MASK                           (0x8U)
+#define RTC_CR_UM_SHIFT                          (3U)
+#define RTC_CR_UM(x)                             (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
+#define RTC_CR_WPS_MASK                          (0x10U)
+#define RTC_CR_WPS_SHIFT                         (4U)
+#define RTC_CR_WPS(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
+#define RTC_CR_OSCE_MASK                         (0x100U)
+#define RTC_CR_OSCE_SHIFT                        (8U)
+#define RTC_CR_OSCE(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
+#define RTC_CR_CLKO_MASK                         (0x200U)
+#define RTC_CR_CLKO_SHIFT                        (9U)
+#define RTC_CR_CLKO(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
+#define RTC_CR_SC16P_MASK                        (0x400U)
+#define RTC_CR_SC16P_SHIFT                       (10U)
+#define RTC_CR_SC16P(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
+#define RTC_CR_SC8P_MASK                         (0x800U)
+#define RTC_CR_SC8P_SHIFT                        (11U)
+#define RTC_CR_SC8P(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
+#define RTC_CR_SC4P_MASK                         (0x1000U)
+#define RTC_CR_SC4P_SHIFT                        (12U)
+#define RTC_CR_SC4P(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
+#define RTC_CR_SC2P_MASK                         (0x2000U)
+#define RTC_CR_SC2P_SHIFT                        (13U)
+#define RTC_CR_SC2P(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
+
+/*! @name SR - RTC Status Register */
+#define RTC_SR_TIF_MASK                          (0x1U)
+#define RTC_SR_TIF_SHIFT                         (0U)
+#define RTC_SR_TIF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
+#define RTC_SR_TOF_MASK                          (0x2U)
+#define RTC_SR_TOF_SHIFT                         (1U)
+#define RTC_SR_TOF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
+#define RTC_SR_TAF_MASK                          (0x4U)
+#define RTC_SR_TAF_SHIFT                         (2U)
+#define RTC_SR_TAF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
+#define RTC_SR_MOF_MASK                          (0x8U)
+#define RTC_SR_MOF_SHIFT                         (3U)
+#define RTC_SR_MOF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_MOF_SHIFT)) & RTC_SR_MOF_MASK)
+#define RTC_SR_TCE_MASK                          (0x10U)
+#define RTC_SR_TCE_SHIFT                         (4U)
+#define RTC_SR_TCE(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
+
+/*! @name LR - RTC Lock Register */
+#define RTC_LR_TCL_MASK                          (0x8U)
+#define RTC_LR_TCL_SHIFT                         (3U)
+#define RTC_LR_TCL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
+#define RTC_LR_CRL_MASK                          (0x10U)
+#define RTC_LR_CRL_SHIFT                         (4U)
+#define RTC_LR_CRL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
+#define RTC_LR_SRL_MASK                          (0x20U)
+#define RTC_LR_SRL_SHIFT                         (5U)
+#define RTC_LR_SRL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
+#define RTC_LR_LRL_MASK                          (0x40U)
+#define RTC_LR_LRL_SHIFT                         (6U)
+#define RTC_LR_LRL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
+#define RTC_LR_TTSL_MASK                         (0x100U)
+#define RTC_LR_TTSL_SHIFT                        (8U)
+#define RTC_LR_TTSL(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_LR_TTSL_SHIFT)) & RTC_LR_TTSL_MASK)
+#define RTC_LR_MEL_MASK                          (0x200U)
+#define RTC_LR_MEL_SHIFT                         (9U)
+#define RTC_LR_MEL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_MEL_SHIFT)) & RTC_LR_MEL_MASK)
+#define RTC_LR_MCLL_MASK                         (0x400U)
+#define RTC_LR_MCLL_SHIFT                        (10U)
+#define RTC_LR_MCLL(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCLL_SHIFT)) & RTC_LR_MCLL_MASK)
+#define RTC_LR_MCHL_MASK                         (0x800U)
+#define RTC_LR_MCHL_SHIFT                        (11U)
+#define RTC_LR_MCHL(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCHL_SHIFT)) & RTC_LR_MCHL_MASK)
+
+/*! @name IER - RTC Interrupt Enable Register */
+#define RTC_IER_TIIE_MASK                        (0x1U)
+#define RTC_IER_TIIE_SHIFT                       (0U)
+#define RTC_IER_TIIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
+#define RTC_IER_TOIE_MASK                        (0x2U)
+#define RTC_IER_TOIE_SHIFT                       (1U)
+#define RTC_IER_TOIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
+#define RTC_IER_TAIE_MASK                        (0x4U)
+#define RTC_IER_TAIE_SHIFT                       (2U)
+#define RTC_IER_TAIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
+#define RTC_IER_MOIE_MASK                        (0x8U)
+#define RTC_IER_MOIE_SHIFT                       (3U)
+#define RTC_IER_MOIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_MOIE_SHIFT)) & RTC_IER_MOIE_MASK)
+#define RTC_IER_TSIE_MASK                        (0x10U)
+#define RTC_IER_TSIE_SHIFT                       (4U)
+#define RTC_IER_TSIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
+#define RTC_IER_WPON_MASK                        (0x80U)
+#define RTC_IER_WPON_SHIFT                       (7U)
+#define RTC_IER_WPON(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
+
+/*! @name TTSR - RTC Tamper Time Seconds Register */
+#define RTC_TTSR_TTS_MASK                        (0xFFFFFFFFU)
+#define RTC_TTSR_TTS_SHIFT                       (0U)
+#define RTC_TTSR_TTS(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_TTSR_TTS_SHIFT)) & RTC_TTSR_TTS_MASK)
+
+/*! @name MER - RTC Monotonic Enable Register */
+#define RTC_MER_MCE_MASK                         (0x10U)
+#define RTC_MER_MCE_SHIFT                        (4U)
+#define RTC_MER_MCE(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_MER_MCE_SHIFT)) & RTC_MER_MCE_MASK)
+
+/*! @name MCLR - RTC Monotonic Counter Low Register */
+#define RTC_MCLR_MCL_MASK                        (0xFFFFFFFFU)
+#define RTC_MCLR_MCL_SHIFT                       (0U)
+#define RTC_MCLR_MCL(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_MCLR_MCL_SHIFT)) & RTC_MCLR_MCL_MASK)
+
+/*! @name MCHR - RTC Monotonic Counter High Register */
+#define RTC_MCHR_MCH_MASK                        (0xFFFFFFFFU)
+#define RTC_MCHR_MCH_SHIFT                       (0U)
+#define RTC_MCHR_MCH(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_MCHR_MCH_SHIFT)) & RTC_MCHR_MCH_MASK)
+
+/*! @name WAR - RTC Write Access Register */
+#define RTC_WAR_TSRW_MASK                        (0x1U)
+#define RTC_WAR_TSRW_SHIFT                       (0U)
+#define RTC_WAR_TSRW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK)
+#define RTC_WAR_TPRW_MASK                        (0x2U)
+#define RTC_WAR_TPRW_SHIFT                       (1U)
+#define RTC_WAR_TPRW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK)
+#define RTC_WAR_TARW_MASK                        (0x4U)
+#define RTC_WAR_TARW_SHIFT                       (2U)
+#define RTC_WAR_TARW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK)
+#define RTC_WAR_TCRW_MASK                        (0x8U)
+#define RTC_WAR_TCRW_SHIFT                       (3U)
+#define RTC_WAR_TCRW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK)
+#define RTC_WAR_CRW_MASK                         (0x10U)
+#define RTC_WAR_CRW_SHIFT                        (4U)
+#define RTC_WAR_CRW(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK)
+#define RTC_WAR_SRW_MASK                         (0x20U)
+#define RTC_WAR_SRW_SHIFT                        (5U)
+#define RTC_WAR_SRW(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK)
+#define RTC_WAR_LRW_MASK                         (0x40U)
+#define RTC_WAR_LRW_SHIFT                        (6U)
+#define RTC_WAR_LRW(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK)
+#define RTC_WAR_IERW_MASK                        (0x80U)
+#define RTC_WAR_IERW_SHIFT                       (7U)
+#define RTC_WAR_IERW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK)
+#define RTC_WAR_TTSW_MASK                        (0x100U)
+#define RTC_WAR_TTSW_SHIFT                       (8U)
+#define RTC_WAR_TTSW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TTSW_SHIFT)) & RTC_WAR_TTSW_MASK)
+#define RTC_WAR_MERW_MASK                        (0x200U)
+#define RTC_WAR_MERW_SHIFT                       (9U)
+#define RTC_WAR_MERW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MERW_SHIFT)) & RTC_WAR_MERW_MASK)
+#define RTC_WAR_MCLW_MASK                        (0x400U)
+#define RTC_WAR_MCLW_SHIFT                       (10U)
+#define RTC_WAR_MCLW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCLW_SHIFT)) & RTC_WAR_MCLW_MASK)
+#define RTC_WAR_MCHW_MASK                        (0x800U)
+#define RTC_WAR_MCHW_SHIFT                       (11U)
+#define RTC_WAR_MCHW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCHW_SHIFT)) & RTC_WAR_MCHW_MASK)
+
+/*! @name RAR - RTC Read Access Register */
+#define RTC_RAR_TSRR_MASK                        (0x1U)
+#define RTC_RAR_TSRR_SHIFT                       (0U)
+#define RTC_RAR_TSRR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK)
+#define RTC_RAR_TPRR_MASK                        (0x2U)
+#define RTC_RAR_TPRR_SHIFT                       (1U)
+#define RTC_RAR_TPRR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK)
+#define RTC_RAR_TARR_MASK                        (0x4U)
+#define RTC_RAR_TARR_SHIFT                       (2U)
+#define RTC_RAR_TARR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK)
+#define RTC_RAR_TCRR_MASK                        (0x8U)
+#define RTC_RAR_TCRR_SHIFT                       (3U)
+#define RTC_RAR_TCRR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK)
+#define RTC_RAR_CRR_MASK                         (0x10U)
+#define RTC_RAR_CRR_SHIFT                        (4U)
+#define RTC_RAR_CRR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK)
+#define RTC_RAR_SRR_MASK                         (0x20U)
+#define RTC_RAR_SRR_SHIFT                        (5U)
+#define RTC_RAR_SRR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK)
+#define RTC_RAR_LRR_MASK                         (0x40U)
+#define RTC_RAR_LRR_SHIFT                        (6U)
+#define RTC_RAR_LRR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK)
+#define RTC_RAR_IERR_MASK                        (0x80U)
+#define RTC_RAR_IERR_SHIFT                       (7U)
+#define RTC_RAR_IERR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK)
+#define RTC_RAR_TTSR_MASK                        (0x100U)
+#define RTC_RAR_TTSR_SHIFT                       (8U)
+#define RTC_RAR_TTSR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TTSR_SHIFT)) & RTC_RAR_TTSR_MASK)
+#define RTC_RAR_MERR_MASK                        (0x200U)
+#define RTC_RAR_MERR_SHIFT                       (9U)
+#define RTC_RAR_MERR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MERR_SHIFT)) & RTC_RAR_MERR_MASK)
+#define RTC_RAR_MCLR_MASK                        (0x400U)
+#define RTC_RAR_MCLR_SHIFT                       (10U)
+#define RTC_RAR_MCLR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCLR_SHIFT)) & RTC_RAR_MCLR_MASK)
+#define RTC_RAR_MCHR_MASK                        (0x800U)
+#define RTC_RAR_MCHR_SHIFT                       (11U)
+#define RTC_RAR_MCHR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCHR_SHIFT)) & RTC_RAR_MCHR_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE                                 (0x4003D000u)
+/** Peripheral RTC base pointer */
+#define RTC                                      ((RTC_Type *)RTC_BASE)
+/** Array initializer of RTC peripheral base addresses */
+#define RTC_BASE_ADDRS                           { RTC_BASE }
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASE_PTRS                            { RTC }
+/** Interrupt vectors for the RTC peripheral type */
+#define RTC_IRQS                                 { RTC_IRQn }
+#define RTC_SECONDS_IRQS                         { RTC_Seconds_IRQn }
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDHC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer
+ * @{
+ */
+
+/** SDHC - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t DSADDR;                            /**< DMA System Address register, offset: 0x0 */
+  __IO uint32_t BLKATTR;                           /**< Block Attributes register, offset: 0x4 */
+  __IO uint32_t CMDARG;                            /**< Command Argument register, offset: 0x8 */
+  __IO uint32_t XFERTYP;                           /**< Transfer Type register, offset: 0xC */
+  __I  uint32_t CMDRSP[4];                         /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */
+  __IO uint32_t DATPORT;                           /**< Buffer Data Port register, offset: 0x20 */
+  __I  uint32_t PRSSTAT;                           /**< Present State register, offset: 0x24 */
+  __IO uint32_t PROCTL;                            /**< Protocol Control register, offset: 0x28 */
+  __IO uint32_t SYSCTL;                            /**< System Control register, offset: 0x2C */
+  __IO uint32_t IRQSTAT;                           /**< Interrupt Status register, offset: 0x30 */
+  __IO uint32_t IRQSTATEN;                         /**< Interrupt Status Enable register, offset: 0x34 */
+  __IO uint32_t IRQSIGEN;                          /**< Interrupt Signal Enable register, offset: 0x38 */
+  __I  uint32_t AC12ERR;                           /**< Auto CMD12 Error Status Register, offset: 0x3C */
+  __I  uint32_t HTCAPBLT;                          /**< Host Controller Capabilities, offset: 0x40 */
+  __IO uint32_t WML;                               /**< Watermark Level Register, offset: 0x44 */
+       uint8_t RESERVED_0[8];
+  __O  uint32_t FEVT;                              /**< Force Event register, offset: 0x50 */
+  __I  uint32_t ADMAES;                            /**< ADMA Error Status register, offset: 0x54 */
+  __IO uint32_t ADSADDR;                           /**< ADMA System Addressregister, offset: 0x58 */
+       uint8_t RESERVED_1[100];
+  __IO uint32_t VENDOR;                            /**< Vendor Specific register, offset: 0xC0 */
+  __IO uint32_t MMCBOOT;                           /**< MMC Boot register, offset: 0xC4 */
+       uint8_t RESERVED_2[52];
+  __I  uint32_t HOSTVER;                           /**< Host Controller Version, offset: 0xFC */
+} SDHC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SDHC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDHC_Register_Masks SDHC Register Masks
+ * @{
+ */
+
+/*! @name DSADDR - DMA System Address register */
+#define SDHC_DSADDR_DSADDR_MASK                  (0xFFFFFFFCU)
+#define SDHC_DSADDR_DSADDR_SHIFT                 (2U)
+#define SDHC_DSADDR_DSADDR(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_DSADDR_DSADDR_SHIFT)) & SDHC_DSADDR_DSADDR_MASK)
+
+/*! @name BLKATTR - Block Attributes register */
+#define SDHC_BLKATTR_BLKSIZE_MASK                (0x1FFFU)
+#define SDHC_BLKATTR_BLKSIZE_SHIFT               (0U)
+#define SDHC_BLKATTR_BLKSIZE(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKSIZE_SHIFT)) & SDHC_BLKATTR_BLKSIZE_MASK)
+#define SDHC_BLKATTR_BLKCNT_MASK                 (0xFFFF0000U)
+#define SDHC_BLKATTR_BLKCNT_SHIFT                (16U)
+#define SDHC_BLKATTR_BLKCNT(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKCNT_SHIFT)) & SDHC_BLKATTR_BLKCNT_MASK)
+
+/*! @name CMDARG - Command Argument register */
+#define SDHC_CMDARG_CMDARG_MASK                  (0xFFFFFFFFU)
+#define SDHC_CMDARG_CMDARG_SHIFT                 (0U)
+#define SDHC_CMDARG_CMDARG(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_CMDARG_CMDARG_SHIFT)) & SDHC_CMDARG_CMDARG_MASK)
+
+/*! @name XFERTYP - Transfer Type register */
+#define SDHC_XFERTYP_DMAEN_MASK                  (0x1U)
+#define SDHC_XFERTYP_DMAEN_SHIFT                 (0U)
+#define SDHC_XFERTYP_DMAEN(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DMAEN_SHIFT)) & SDHC_XFERTYP_DMAEN_MASK)
+#define SDHC_XFERTYP_BCEN_MASK                   (0x2U)
+#define SDHC_XFERTYP_BCEN_SHIFT                  (1U)
+#define SDHC_XFERTYP_BCEN(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_BCEN_SHIFT)) & SDHC_XFERTYP_BCEN_MASK)
+#define SDHC_XFERTYP_AC12EN_MASK                 (0x4U)
+#define SDHC_XFERTYP_AC12EN_SHIFT                (2U)
+#define SDHC_XFERTYP_AC12EN(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_AC12EN_SHIFT)) & SDHC_XFERTYP_AC12EN_MASK)
+#define SDHC_XFERTYP_DTDSEL_MASK                 (0x10U)
+#define SDHC_XFERTYP_DTDSEL_SHIFT                (4U)
+#define SDHC_XFERTYP_DTDSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DTDSEL_SHIFT)) & SDHC_XFERTYP_DTDSEL_MASK)
+#define SDHC_XFERTYP_MSBSEL_MASK                 (0x20U)
+#define SDHC_XFERTYP_MSBSEL_SHIFT                (5U)
+#define SDHC_XFERTYP_MSBSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_MSBSEL_SHIFT)) & SDHC_XFERTYP_MSBSEL_MASK)
+#define SDHC_XFERTYP_RSPTYP_MASK                 (0x30000U)
+#define SDHC_XFERTYP_RSPTYP_SHIFT                (16U)
+#define SDHC_XFERTYP_RSPTYP(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_RSPTYP_SHIFT)) & SDHC_XFERTYP_RSPTYP_MASK)
+#define SDHC_XFERTYP_CCCEN_MASK                  (0x80000U)
+#define SDHC_XFERTYP_CCCEN_SHIFT                 (19U)
+#define SDHC_XFERTYP_CCCEN(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CCCEN_SHIFT)) & SDHC_XFERTYP_CCCEN_MASK)
+#define SDHC_XFERTYP_CICEN_MASK                  (0x100000U)
+#define SDHC_XFERTYP_CICEN_SHIFT                 (20U)
+#define SDHC_XFERTYP_CICEN(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CICEN_SHIFT)) & SDHC_XFERTYP_CICEN_MASK)
+#define SDHC_XFERTYP_DPSEL_MASK                  (0x200000U)
+#define SDHC_XFERTYP_DPSEL_SHIFT                 (21U)
+#define SDHC_XFERTYP_DPSEL(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DPSEL_SHIFT)) & SDHC_XFERTYP_DPSEL_MASK)
+#define SDHC_XFERTYP_CMDTYP_MASK                 (0xC00000U)
+#define SDHC_XFERTYP_CMDTYP_SHIFT                (22U)
+#define SDHC_XFERTYP_CMDTYP(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDTYP_SHIFT)) & SDHC_XFERTYP_CMDTYP_MASK)
+#define SDHC_XFERTYP_CMDINX_MASK                 (0x3F000000U)
+#define SDHC_XFERTYP_CMDINX_SHIFT                (24U)
+#define SDHC_XFERTYP_CMDINX(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDINX_SHIFT)) & SDHC_XFERTYP_CMDINX_MASK)
+
+/*! @name CMDRSP - Command Response 0..Command Response 3 */
+#define SDHC_CMDRSP_CMDRSP0_MASK                 (0xFFFFFFFFU)
+#define SDHC_CMDRSP_CMDRSP0_SHIFT                (0U)
+#define SDHC_CMDRSP_CMDRSP0(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP0_SHIFT)) & SDHC_CMDRSP_CMDRSP0_MASK)
+#define SDHC_CMDRSP_CMDRSP1_MASK                 (0xFFFFFFFFU)
+#define SDHC_CMDRSP_CMDRSP1_SHIFT                (0U)
+#define SDHC_CMDRSP_CMDRSP1(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP1_SHIFT)) & SDHC_CMDRSP_CMDRSP1_MASK)
+#define SDHC_CMDRSP_CMDRSP2_MASK                 (0xFFFFFFFFU)
+#define SDHC_CMDRSP_CMDRSP2_SHIFT                (0U)
+#define SDHC_CMDRSP_CMDRSP2(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP2_SHIFT)) & SDHC_CMDRSP_CMDRSP2_MASK)
+#define SDHC_CMDRSP_CMDRSP3_MASK                 (0xFFFFFFFFU)
+#define SDHC_CMDRSP_CMDRSP3_SHIFT                (0U)
+#define SDHC_CMDRSP_CMDRSP3(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP3_SHIFT)) & SDHC_CMDRSP_CMDRSP3_MASK)
+
+/* The count of SDHC_CMDRSP */
+#define SDHC_CMDRSP_COUNT                        (4U)
+
+/*! @name DATPORT - Buffer Data Port register */
+#define SDHC_DATPORT_DATCONT_MASK                (0xFFFFFFFFU)
+#define SDHC_DATPORT_DATCONT_SHIFT               (0U)
+#define SDHC_DATPORT_DATCONT(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_DATPORT_DATCONT_SHIFT)) & SDHC_DATPORT_DATCONT_MASK)
+
+/*! @name PRSSTAT - Present State register */
+#define SDHC_PRSSTAT_CIHB_MASK                   (0x1U)
+#define SDHC_PRSSTAT_CIHB_SHIFT                  (0U)
+#define SDHC_PRSSTAT_CIHB(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CIHB_SHIFT)) & SDHC_PRSSTAT_CIHB_MASK)
+#define SDHC_PRSSTAT_CDIHB_MASK                  (0x2U)
+#define SDHC_PRSSTAT_CDIHB_SHIFT                 (1U)
+#define SDHC_PRSSTAT_CDIHB(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CDIHB_SHIFT)) & SDHC_PRSSTAT_CDIHB_MASK)
+#define SDHC_PRSSTAT_DLA_MASK                    (0x4U)
+#define SDHC_PRSSTAT_DLA_SHIFT                   (2U)
+#define SDHC_PRSSTAT_DLA(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLA_SHIFT)) & SDHC_PRSSTAT_DLA_MASK)
+#define SDHC_PRSSTAT_SDSTB_MASK                  (0x8U)
+#define SDHC_PRSSTAT_SDSTB_SHIFT                 (3U)
+#define SDHC_PRSSTAT_SDSTB(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDSTB_SHIFT)) & SDHC_PRSSTAT_SDSTB_MASK)
+#define SDHC_PRSSTAT_IPGOFF_MASK                 (0x10U)
+#define SDHC_PRSSTAT_IPGOFF_SHIFT                (4U)
+#define SDHC_PRSSTAT_IPGOFF(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_IPGOFF_SHIFT)) & SDHC_PRSSTAT_IPGOFF_MASK)
+#define SDHC_PRSSTAT_HCKOFF_MASK                 (0x20U)
+#define SDHC_PRSSTAT_HCKOFF_SHIFT                (5U)
+#define SDHC_PRSSTAT_HCKOFF(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_HCKOFF_SHIFT)) & SDHC_PRSSTAT_HCKOFF_MASK)
+#define SDHC_PRSSTAT_PEROFF_MASK                 (0x40U)
+#define SDHC_PRSSTAT_PEROFF_SHIFT                (6U)
+#define SDHC_PRSSTAT_PEROFF(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_PEROFF_SHIFT)) & SDHC_PRSSTAT_PEROFF_MASK)
+#define SDHC_PRSSTAT_SDOFF_MASK                  (0x80U)
+#define SDHC_PRSSTAT_SDOFF_SHIFT                 (7U)
+#define SDHC_PRSSTAT_SDOFF(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDOFF_SHIFT)) & SDHC_PRSSTAT_SDOFF_MASK)
+#define SDHC_PRSSTAT_WTA_MASK                    (0x100U)
+#define SDHC_PRSSTAT_WTA_SHIFT                   (8U)
+#define SDHC_PRSSTAT_WTA(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_WTA_SHIFT)) & SDHC_PRSSTAT_WTA_MASK)
+#define SDHC_PRSSTAT_RTA_MASK                    (0x200U)
+#define SDHC_PRSSTAT_RTA_SHIFT                   (9U)
+#define SDHC_PRSSTAT_RTA(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_RTA_SHIFT)) & SDHC_PRSSTAT_RTA_MASK)
+#define SDHC_PRSSTAT_BWEN_MASK                   (0x400U)
+#define SDHC_PRSSTAT_BWEN_SHIFT                  (10U)
+#define SDHC_PRSSTAT_BWEN(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BWEN_SHIFT)) & SDHC_PRSSTAT_BWEN_MASK)
+#define SDHC_PRSSTAT_BREN_MASK                   (0x800U)
+#define SDHC_PRSSTAT_BREN_SHIFT                  (11U)
+#define SDHC_PRSSTAT_BREN(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BREN_SHIFT)) & SDHC_PRSSTAT_BREN_MASK)
+#define SDHC_PRSSTAT_CINS_MASK                   (0x10000U)
+#define SDHC_PRSSTAT_CINS_SHIFT                  (16U)
+#define SDHC_PRSSTAT_CINS(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CINS_SHIFT)) & SDHC_PRSSTAT_CINS_MASK)
+#define SDHC_PRSSTAT_CLSL_MASK                   (0x800000U)
+#define SDHC_PRSSTAT_CLSL_SHIFT                  (23U)
+#define SDHC_PRSSTAT_CLSL(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CLSL_SHIFT)) & SDHC_PRSSTAT_CLSL_MASK)
+#define SDHC_PRSSTAT_DLSL_MASK                   (0xFF000000U)
+#define SDHC_PRSSTAT_DLSL_SHIFT                  (24U)
+#define SDHC_PRSSTAT_DLSL(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLSL_SHIFT)) & SDHC_PRSSTAT_DLSL_MASK)
+
+/*! @name PROCTL - Protocol Control register */
+#define SDHC_PROCTL_LCTL_MASK                    (0x1U)
+#define SDHC_PROCTL_LCTL_SHIFT                   (0U)
+#define SDHC_PROCTL_LCTL(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_LCTL_SHIFT)) & SDHC_PROCTL_LCTL_MASK)
+#define SDHC_PROCTL_DTW_MASK                     (0x6U)
+#define SDHC_PROCTL_DTW_SHIFT                    (1U)
+#define SDHC_PROCTL_DTW(x)                       (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DTW_SHIFT)) & SDHC_PROCTL_DTW_MASK)
+#define SDHC_PROCTL_D3CD_MASK                    (0x8U)
+#define SDHC_PROCTL_D3CD_SHIFT                   (3U)
+#define SDHC_PROCTL_D3CD(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_D3CD_SHIFT)) & SDHC_PROCTL_D3CD_MASK)
+#define SDHC_PROCTL_EMODE_MASK                   (0x30U)
+#define SDHC_PROCTL_EMODE_SHIFT                  (4U)
+#define SDHC_PROCTL_EMODE(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_EMODE_SHIFT)) & SDHC_PROCTL_EMODE_MASK)
+#define SDHC_PROCTL_CDTL_MASK                    (0x40U)
+#define SDHC_PROCTL_CDTL_SHIFT                   (6U)
+#define SDHC_PROCTL_CDTL(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDTL_SHIFT)) & SDHC_PROCTL_CDTL_MASK)
+#define SDHC_PROCTL_CDSS_MASK                    (0x80U)
+#define SDHC_PROCTL_CDSS_SHIFT                   (7U)
+#define SDHC_PROCTL_CDSS(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDSS_SHIFT)) & SDHC_PROCTL_CDSS_MASK)
+#define SDHC_PROCTL_DMAS_MASK                    (0x300U)
+#define SDHC_PROCTL_DMAS_SHIFT                   (8U)
+#define SDHC_PROCTL_DMAS(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DMAS_SHIFT)) & SDHC_PROCTL_DMAS_MASK)
+#define SDHC_PROCTL_SABGREQ_MASK                 (0x10000U)
+#define SDHC_PROCTL_SABGREQ_SHIFT                (16U)
+#define SDHC_PROCTL_SABGREQ(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_SABGREQ_SHIFT)) & SDHC_PROCTL_SABGREQ_MASK)
+#define SDHC_PROCTL_CREQ_MASK                    (0x20000U)
+#define SDHC_PROCTL_CREQ_SHIFT                   (17U)
+#define SDHC_PROCTL_CREQ(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CREQ_SHIFT)) & SDHC_PROCTL_CREQ_MASK)
+#define SDHC_PROCTL_RWCTL_MASK                   (0x40000U)
+#define SDHC_PROCTL_RWCTL_SHIFT                  (18U)
+#define SDHC_PROCTL_RWCTL(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_RWCTL_SHIFT)) & SDHC_PROCTL_RWCTL_MASK)
+#define SDHC_PROCTL_IABG_MASK                    (0x80000U)
+#define SDHC_PROCTL_IABG_SHIFT                   (19U)
+#define SDHC_PROCTL_IABG(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_IABG_SHIFT)) & SDHC_PROCTL_IABG_MASK)
+#define SDHC_PROCTL_WECINT_MASK                  (0x1000000U)
+#define SDHC_PROCTL_WECINT_SHIFT                 (24U)
+#define SDHC_PROCTL_WECINT(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINT_SHIFT)) & SDHC_PROCTL_WECINT_MASK)
+#define SDHC_PROCTL_WECINS_MASK                  (0x2000000U)
+#define SDHC_PROCTL_WECINS_SHIFT                 (25U)
+#define SDHC_PROCTL_WECINS(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINS_SHIFT)) & SDHC_PROCTL_WECINS_MASK)
+#define SDHC_PROCTL_WECRM_MASK                   (0x4000000U)
+#define SDHC_PROCTL_WECRM_SHIFT                  (26U)
+#define SDHC_PROCTL_WECRM(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECRM_SHIFT)) & SDHC_PROCTL_WECRM_MASK)
+
+/*! @name SYSCTL - System Control register */
+#define SDHC_SYSCTL_IPGEN_MASK                   (0x1U)
+#define SDHC_SYSCTL_IPGEN_SHIFT                  (0U)
+#define SDHC_SYSCTL_IPGEN(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_IPGEN_SHIFT)) & SDHC_SYSCTL_IPGEN_MASK)
+#define SDHC_SYSCTL_HCKEN_MASK                   (0x2U)
+#define SDHC_SYSCTL_HCKEN_SHIFT                  (1U)
+#define SDHC_SYSCTL_HCKEN(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_HCKEN_SHIFT)) & SDHC_SYSCTL_HCKEN_MASK)
+#define SDHC_SYSCTL_PEREN_MASK                   (0x4U)
+#define SDHC_SYSCTL_PEREN_SHIFT                  (2U)
+#define SDHC_SYSCTL_PEREN(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_PEREN_SHIFT)) & SDHC_SYSCTL_PEREN_MASK)
+#define SDHC_SYSCTL_SDCLKEN_MASK                 (0x8U)
+#define SDHC_SYSCTL_SDCLKEN_SHIFT                (3U)
+#define SDHC_SYSCTL_SDCLKEN(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKEN_SHIFT)) & SDHC_SYSCTL_SDCLKEN_MASK)
+#define SDHC_SYSCTL_DVS_MASK                     (0xF0U)
+#define SDHC_SYSCTL_DVS_SHIFT                    (4U)
+#define SDHC_SYSCTL_DVS(x)                       (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DVS_SHIFT)) & SDHC_SYSCTL_DVS_MASK)
+#define SDHC_SYSCTL_SDCLKFS_MASK                 (0xFF00U)
+#define SDHC_SYSCTL_SDCLKFS_SHIFT                (8U)
+#define SDHC_SYSCTL_SDCLKFS(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKFS_SHIFT)) & SDHC_SYSCTL_SDCLKFS_MASK)
+#define SDHC_SYSCTL_DTOCV_MASK                   (0xF0000U)
+#define SDHC_SYSCTL_DTOCV_SHIFT                  (16U)
+#define SDHC_SYSCTL_DTOCV(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DTOCV_SHIFT)) & SDHC_SYSCTL_DTOCV_MASK)
+#define SDHC_SYSCTL_RSTA_MASK                    (0x1000000U)
+#define SDHC_SYSCTL_RSTA_SHIFT                   (24U)
+#define SDHC_SYSCTL_RSTA(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTA_SHIFT)) & SDHC_SYSCTL_RSTA_MASK)
+#define SDHC_SYSCTL_RSTC_MASK                    (0x2000000U)
+#define SDHC_SYSCTL_RSTC_SHIFT                   (25U)
+#define SDHC_SYSCTL_RSTC(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTC_SHIFT)) & SDHC_SYSCTL_RSTC_MASK)
+#define SDHC_SYSCTL_RSTD_MASK                    (0x4000000U)
+#define SDHC_SYSCTL_RSTD_SHIFT                   (26U)
+#define SDHC_SYSCTL_RSTD(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTD_SHIFT)) & SDHC_SYSCTL_RSTD_MASK)
+#define SDHC_SYSCTL_INITA_MASK                   (0x8000000U)
+#define SDHC_SYSCTL_INITA_SHIFT                  (27U)
+#define SDHC_SYSCTL_INITA(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_INITA_SHIFT)) & SDHC_SYSCTL_INITA_MASK)
+
+/*! @name IRQSTAT - Interrupt Status register */
+#define SDHC_IRQSTAT_CC_MASK                     (0x1U)
+#define SDHC_IRQSTAT_CC_SHIFT                    (0U)
+#define SDHC_IRQSTAT_CC(x)                       (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CC_SHIFT)) & SDHC_IRQSTAT_CC_MASK)
+#define SDHC_IRQSTAT_TC_MASK                     (0x2U)
+#define SDHC_IRQSTAT_TC_SHIFT                    (1U)
+#define SDHC_IRQSTAT_TC(x)                       (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_TC_SHIFT)) & SDHC_IRQSTAT_TC_MASK)
+#define SDHC_IRQSTAT_BGE_MASK                    (0x4U)
+#define SDHC_IRQSTAT_BGE_SHIFT                   (2U)
+#define SDHC_IRQSTAT_BGE(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BGE_SHIFT)) & SDHC_IRQSTAT_BGE_MASK)
+#define SDHC_IRQSTAT_DINT_MASK                   (0x8U)
+#define SDHC_IRQSTAT_DINT_SHIFT                  (3U)
+#define SDHC_IRQSTAT_DINT(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DINT_SHIFT)) & SDHC_IRQSTAT_DINT_MASK)
+#define SDHC_IRQSTAT_BWR_MASK                    (0x10U)
+#define SDHC_IRQSTAT_BWR_SHIFT                   (4U)
+#define SDHC_IRQSTAT_BWR(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BWR_SHIFT)) & SDHC_IRQSTAT_BWR_MASK)
+#define SDHC_IRQSTAT_BRR_MASK                    (0x20U)
+#define SDHC_IRQSTAT_BRR_SHIFT                   (5U)
+#define SDHC_IRQSTAT_BRR(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BRR_SHIFT)) & SDHC_IRQSTAT_BRR_MASK)
+#define SDHC_IRQSTAT_CINS_MASK                   (0x40U)
+#define SDHC_IRQSTAT_CINS_SHIFT                  (6U)
+#define SDHC_IRQSTAT_CINS(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINS_SHIFT)) & SDHC_IRQSTAT_CINS_MASK)
+#define SDHC_IRQSTAT_CRM_MASK                    (0x80U)
+#define SDHC_IRQSTAT_CRM_SHIFT                   (7U)
+#define SDHC_IRQSTAT_CRM(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CRM_SHIFT)) & SDHC_IRQSTAT_CRM_MASK)
+#define SDHC_IRQSTAT_CINT_MASK                   (0x100U)
+#define SDHC_IRQSTAT_CINT_SHIFT                  (8U)
+#define SDHC_IRQSTAT_CINT(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINT_SHIFT)) & SDHC_IRQSTAT_CINT_MASK)
+#define SDHC_IRQSTAT_CTOE_MASK                   (0x10000U)
+#define SDHC_IRQSTAT_CTOE_SHIFT                  (16U)
+#define SDHC_IRQSTAT_CTOE(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CTOE_SHIFT)) & SDHC_IRQSTAT_CTOE_MASK)
+#define SDHC_IRQSTAT_CCE_MASK                    (0x20000U)
+#define SDHC_IRQSTAT_CCE_SHIFT                   (17U)
+#define SDHC_IRQSTAT_CCE(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CCE_SHIFT)) & SDHC_IRQSTAT_CCE_MASK)
+#define SDHC_IRQSTAT_CEBE_MASK                   (0x40000U)
+#define SDHC_IRQSTAT_CEBE_SHIFT                  (18U)
+#define SDHC_IRQSTAT_CEBE(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CEBE_SHIFT)) & SDHC_IRQSTAT_CEBE_MASK)
+#define SDHC_IRQSTAT_CIE_MASK                    (0x80000U)
+#define SDHC_IRQSTAT_CIE_SHIFT                   (19U)
+#define SDHC_IRQSTAT_CIE(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CIE_SHIFT)) & SDHC_IRQSTAT_CIE_MASK)
+#define SDHC_IRQSTAT_DTOE_MASK                   (0x100000U)
+#define SDHC_IRQSTAT_DTOE_SHIFT                  (20U)
+#define SDHC_IRQSTAT_DTOE(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DTOE_SHIFT)) & SDHC_IRQSTAT_DTOE_MASK)
+#define SDHC_IRQSTAT_DCE_MASK                    (0x200000U)
+#define SDHC_IRQSTAT_DCE_SHIFT                   (21U)
+#define SDHC_IRQSTAT_DCE(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DCE_SHIFT)) & SDHC_IRQSTAT_DCE_MASK)
+#define SDHC_IRQSTAT_DEBE_MASK                   (0x400000U)
+#define SDHC_IRQSTAT_DEBE_SHIFT                  (22U)
+#define SDHC_IRQSTAT_DEBE(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DEBE_SHIFT)) & SDHC_IRQSTAT_DEBE_MASK)
+#define SDHC_IRQSTAT_AC12E_MASK                  (0x1000000U)
+#define SDHC_IRQSTAT_AC12E_SHIFT                 (24U)
+#define SDHC_IRQSTAT_AC12E(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_AC12E_SHIFT)) & SDHC_IRQSTAT_AC12E_MASK)
+#define SDHC_IRQSTAT_DMAE_MASK                   (0x10000000U)
+#define SDHC_IRQSTAT_DMAE_SHIFT                  (28U)
+#define SDHC_IRQSTAT_DMAE(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DMAE_SHIFT)) & SDHC_IRQSTAT_DMAE_MASK)
+
+/*! @name IRQSTATEN - Interrupt Status Enable register */
+#define SDHC_IRQSTATEN_CCSEN_MASK                (0x1U)
+#define SDHC_IRQSTATEN_CCSEN_SHIFT               (0U)
+#define SDHC_IRQSTATEN_CCSEN(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCSEN_SHIFT)) & SDHC_IRQSTATEN_CCSEN_MASK)
+#define SDHC_IRQSTATEN_TCSEN_MASK                (0x2U)
+#define SDHC_IRQSTATEN_TCSEN_SHIFT               (1U)
+#define SDHC_IRQSTATEN_TCSEN(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_TCSEN_SHIFT)) & SDHC_IRQSTATEN_TCSEN_MASK)
+#define SDHC_IRQSTATEN_BGESEN_MASK               (0x4U)
+#define SDHC_IRQSTATEN_BGESEN_SHIFT              (2U)
+#define SDHC_IRQSTATEN_BGESEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BGESEN_SHIFT)) & SDHC_IRQSTATEN_BGESEN_MASK)
+#define SDHC_IRQSTATEN_DINTSEN_MASK              (0x8U)
+#define SDHC_IRQSTATEN_DINTSEN_SHIFT             (3U)
+#define SDHC_IRQSTATEN_DINTSEN(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DINTSEN_SHIFT)) & SDHC_IRQSTATEN_DINTSEN_MASK)
+#define SDHC_IRQSTATEN_BWRSEN_MASK               (0x10U)
+#define SDHC_IRQSTATEN_BWRSEN_SHIFT              (4U)
+#define SDHC_IRQSTATEN_BWRSEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BWRSEN_SHIFT)) & SDHC_IRQSTATEN_BWRSEN_MASK)
+#define SDHC_IRQSTATEN_BRRSEN_MASK               (0x20U)
+#define SDHC_IRQSTATEN_BRRSEN_SHIFT              (5U)
+#define SDHC_IRQSTATEN_BRRSEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BRRSEN_SHIFT)) & SDHC_IRQSTATEN_BRRSEN_MASK)
+#define SDHC_IRQSTATEN_CINSEN_MASK               (0x40U)
+#define SDHC_IRQSTATEN_CINSEN_SHIFT              (6U)
+#define SDHC_IRQSTATEN_CINSEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINSEN_SHIFT)) & SDHC_IRQSTATEN_CINSEN_MASK)
+#define SDHC_IRQSTATEN_CRMSEN_MASK               (0x80U)
+#define SDHC_IRQSTATEN_CRMSEN_SHIFT              (7U)
+#define SDHC_IRQSTATEN_CRMSEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CRMSEN_SHIFT)) & SDHC_IRQSTATEN_CRMSEN_MASK)
+#define SDHC_IRQSTATEN_CINTSEN_MASK              (0x100U)
+#define SDHC_IRQSTATEN_CINTSEN_SHIFT             (8U)
+#define SDHC_IRQSTATEN_CINTSEN(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINTSEN_SHIFT)) & SDHC_IRQSTATEN_CINTSEN_MASK)
+#define SDHC_IRQSTATEN_CTOESEN_MASK              (0x10000U)
+#define SDHC_IRQSTATEN_CTOESEN_SHIFT             (16U)
+#define SDHC_IRQSTATEN_CTOESEN(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CTOESEN_SHIFT)) & SDHC_IRQSTATEN_CTOESEN_MASK)
+#define SDHC_IRQSTATEN_CCESEN_MASK               (0x20000U)
+#define SDHC_IRQSTATEN_CCESEN_SHIFT              (17U)
+#define SDHC_IRQSTATEN_CCESEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCESEN_SHIFT)) & SDHC_IRQSTATEN_CCESEN_MASK)
+#define SDHC_IRQSTATEN_CEBESEN_MASK              (0x40000U)
+#define SDHC_IRQSTATEN_CEBESEN_SHIFT             (18U)
+#define SDHC_IRQSTATEN_CEBESEN(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CEBESEN_SHIFT)) & SDHC_IRQSTATEN_CEBESEN_MASK)
+#define SDHC_IRQSTATEN_CIESEN_MASK               (0x80000U)
+#define SDHC_IRQSTATEN_CIESEN_SHIFT              (19U)
+#define SDHC_IRQSTATEN_CIESEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CIESEN_SHIFT)) & SDHC_IRQSTATEN_CIESEN_MASK)
+#define SDHC_IRQSTATEN_DTOESEN_MASK              (0x100000U)
+#define SDHC_IRQSTATEN_DTOESEN_SHIFT             (20U)
+#define SDHC_IRQSTATEN_DTOESEN(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DTOESEN_SHIFT)) & SDHC_IRQSTATEN_DTOESEN_MASK)
+#define SDHC_IRQSTATEN_DCESEN_MASK               (0x200000U)
+#define SDHC_IRQSTATEN_DCESEN_SHIFT              (21U)
+#define SDHC_IRQSTATEN_DCESEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DCESEN_SHIFT)) & SDHC_IRQSTATEN_DCESEN_MASK)
+#define SDHC_IRQSTATEN_DEBESEN_MASK              (0x400000U)
+#define SDHC_IRQSTATEN_DEBESEN_SHIFT             (22U)
+#define SDHC_IRQSTATEN_DEBESEN(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DEBESEN_SHIFT)) & SDHC_IRQSTATEN_DEBESEN_MASK)
+#define SDHC_IRQSTATEN_AC12ESEN_MASK             (0x1000000U)
+#define SDHC_IRQSTATEN_AC12ESEN_SHIFT            (24U)
+#define SDHC_IRQSTATEN_AC12ESEN(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_AC12ESEN_SHIFT)) & SDHC_IRQSTATEN_AC12ESEN_MASK)
+#define SDHC_IRQSTATEN_DMAESEN_MASK              (0x10000000U)
+#define SDHC_IRQSTATEN_DMAESEN_SHIFT             (28U)
+#define SDHC_IRQSTATEN_DMAESEN(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DMAESEN_SHIFT)) & SDHC_IRQSTATEN_DMAESEN_MASK)
+
+/*! @name IRQSIGEN - Interrupt Signal Enable register */
+#define SDHC_IRQSIGEN_CCIEN_MASK                 (0x1U)
+#define SDHC_IRQSIGEN_CCIEN_SHIFT                (0U)
+#define SDHC_IRQSIGEN_CCIEN(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCIEN_SHIFT)) & SDHC_IRQSIGEN_CCIEN_MASK)
+#define SDHC_IRQSIGEN_TCIEN_MASK                 (0x2U)
+#define SDHC_IRQSIGEN_TCIEN_SHIFT                (1U)
+#define SDHC_IRQSIGEN_TCIEN(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_TCIEN_SHIFT)) & SDHC_IRQSIGEN_TCIEN_MASK)
+#define SDHC_IRQSIGEN_BGEIEN_MASK                (0x4U)
+#define SDHC_IRQSIGEN_BGEIEN_SHIFT               (2U)
+#define SDHC_IRQSIGEN_BGEIEN(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BGEIEN_SHIFT)) & SDHC_IRQSIGEN_BGEIEN_MASK)
+#define SDHC_IRQSIGEN_DINTIEN_MASK               (0x8U)
+#define SDHC_IRQSIGEN_DINTIEN_SHIFT              (3U)
+#define SDHC_IRQSIGEN_DINTIEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DINTIEN_SHIFT)) & SDHC_IRQSIGEN_DINTIEN_MASK)
+#define SDHC_IRQSIGEN_BWRIEN_MASK                (0x10U)
+#define SDHC_IRQSIGEN_BWRIEN_SHIFT               (4U)
+#define SDHC_IRQSIGEN_BWRIEN(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BWRIEN_SHIFT)) & SDHC_IRQSIGEN_BWRIEN_MASK)
+#define SDHC_IRQSIGEN_BRRIEN_MASK                (0x20U)
+#define SDHC_IRQSIGEN_BRRIEN_SHIFT               (5U)
+#define SDHC_IRQSIGEN_BRRIEN(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BRRIEN_SHIFT)) & SDHC_IRQSIGEN_BRRIEN_MASK)
+#define SDHC_IRQSIGEN_CINSIEN_MASK               (0x40U)
+#define SDHC_IRQSIGEN_CINSIEN_SHIFT              (6U)
+#define SDHC_IRQSIGEN_CINSIEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINSIEN_SHIFT)) & SDHC_IRQSIGEN_CINSIEN_MASK)
+#define SDHC_IRQSIGEN_CRMIEN_MASK                (0x80U)
+#define SDHC_IRQSIGEN_CRMIEN_SHIFT               (7U)
+#define SDHC_IRQSIGEN_CRMIEN(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CRMIEN_SHIFT)) & SDHC_IRQSIGEN_CRMIEN_MASK)
+#define SDHC_IRQSIGEN_CINTIEN_MASK               (0x100U)
+#define SDHC_IRQSIGEN_CINTIEN_SHIFT              (8U)
+#define SDHC_IRQSIGEN_CINTIEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINTIEN_SHIFT)) & SDHC_IRQSIGEN_CINTIEN_MASK)
+#define SDHC_IRQSIGEN_CTOEIEN_MASK               (0x10000U)
+#define SDHC_IRQSIGEN_CTOEIEN_SHIFT              (16U)
+#define SDHC_IRQSIGEN_CTOEIEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CTOEIEN_SHIFT)) & SDHC_IRQSIGEN_CTOEIEN_MASK)
+#define SDHC_IRQSIGEN_CCEIEN_MASK                (0x20000U)
+#define SDHC_IRQSIGEN_CCEIEN_SHIFT               (17U)
+#define SDHC_IRQSIGEN_CCEIEN(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCEIEN_SHIFT)) & SDHC_IRQSIGEN_CCEIEN_MASK)
+#define SDHC_IRQSIGEN_CEBEIEN_MASK               (0x40000U)
+#define SDHC_IRQSIGEN_CEBEIEN_SHIFT              (18U)
+#define SDHC_IRQSIGEN_CEBEIEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CEBEIEN_SHIFT)) & SDHC_IRQSIGEN_CEBEIEN_MASK)
+#define SDHC_IRQSIGEN_CIEIEN_MASK                (0x80000U)
+#define SDHC_IRQSIGEN_CIEIEN_SHIFT               (19U)
+#define SDHC_IRQSIGEN_CIEIEN(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CIEIEN_SHIFT)) & SDHC_IRQSIGEN_CIEIEN_MASK)
+#define SDHC_IRQSIGEN_DTOEIEN_MASK               (0x100000U)
+#define SDHC_IRQSIGEN_DTOEIEN_SHIFT              (20U)
+#define SDHC_IRQSIGEN_DTOEIEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DTOEIEN_SHIFT)) & SDHC_IRQSIGEN_DTOEIEN_MASK)
+#define SDHC_IRQSIGEN_DCEIEN_MASK                (0x200000U)
+#define SDHC_IRQSIGEN_DCEIEN_SHIFT               (21U)
+#define SDHC_IRQSIGEN_DCEIEN(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DCEIEN_SHIFT)) & SDHC_IRQSIGEN_DCEIEN_MASK)
+#define SDHC_IRQSIGEN_DEBEIEN_MASK               (0x400000U)
+#define SDHC_IRQSIGEN_DEBEIEN_SHIFT              (22U)
+#define SDHC_IRQSIGEN_DEBEIEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DEBEIEN_SHIFT)) & SDHC_IRQSIGEN_DEBEIEN_MASK)
+#define SDHC_IRQSIGEN_AC12EIEN_MASK              (0x1000000U)
+#define SDHC_IRQSIGEN_AC12EIEN_SHIFT             (24U)
+#define SDHC_IRQSIGEN_AC12EIEN(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_AC12EIEN_SHIFT)) & SDHC_IRQSIGEN_AC12EIEN_MASK)
+#define SDHC_IRQSIGEN_DMAEIEN_MASK               (0x10000000U)
+#define SDHC_IRQSIGEN_DMAEIEN_SHIFT              (28U)
+#define SDHC_IRQSIGEN_DMAEIEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DMAEIEN_SHIFT)) & SDHC_IRQSIGEN_DMAEIEN_MASK)
+
+/*! @name AC12ERR - Auto CMD12 Error Status Register */
+#define SDHC_AC12ERR_AC12NE_MASK                 (0x1U)
+#define SDHC_AC12ERR_AC12NE_SHIFT                (0U)
+#define SDHC_AC12ERR_AC12NE(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12NE_SHIFT)) & SDHC_AC12ERR_AC12NE_MASK)
+#define SDHC_AC12ERR_AC12TOE_MASK                (0x2U)
+#define SDHC_AC12ERR_AC12TOE_SHIFT               (1U)
+#define SDHC_AC12ERR_AC12TOE(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12TOE_SHIFT)) & SDHC_AC12ERR_AC12TOE_MASK)
+#define SDHC_AC12ERR_AC12EBE_MASK                (0x4U)
+#define SDHC_AC12ERR_AC12EBE_SHIFT               (2U)
+#define SDHC_AC12ERR_AC12EBE(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12EBE_SHIFT)) & SDHC_AC12ERR_AC12EBE_MASK)
+#define SDHC_AC12ERR_AC12CE_MASK                 (0x8U)
+#define SDHC_AC12ERR_AC12CE_SHIFT                (3U)
+#define SDHC_AC12ERR_AC12CE(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12CE_SHIFT)) & SDHC_AC12ERR_AC12CE_MASK)
+#define SDHC_AC12ERR_AC12IE_MASK                 (0x10U)
+#define SDHC_AC12ERR_AC12IE_SHIFT                (4U)
+#define SDHC_AC12ERR_AC12IE(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12IE_SHIFT)) & SDHC_AC12ERR_AC12IE_MASK)
+#define SDHC_AC12ERR_CNIBAC12E_MASK              (0x80U)
+#define SDHC_AC12ERR_CNIBAC12E_SHIFT             (7U)
+#define SDHC_AC12ERR_CNIBAC12E(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_CNIBAC12E_SHIFT)) & SDHC_AC12ERR_CNIBAC12E_MASK)
+
+/*! @name HTCAPBLT - Host Controller Capabilities */
+#define SDHC_HTCAPBLT_MBL_MASK                   (0x70000U)
+#define SDHC_HTCAPBLT_MBL_SHIFT                  (16U)
+#define SDHC_HTCAPBLT_MBL(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_MBL_SHIFT)) & SDHC_HTCAPBLT_MBL_MASK)
+#define SDHC_HTCAPBLT_ADMAS_MASK                 (0x100000U)
+#define SDHC_HTCAPBLT_ADMAS_SHIFT                (20U)
+#define SDHC_HTCAPBLT_ADMAS(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_ADMAS_SHIFT)) & SDHC_HTCAPBLT_ADMAS_MASK)
+#define SDHC_HTCAPBLT_HSS_MASK                   (0x200000U)
+#define SDHC_HTCAPBLT_HSS_SHIFT                  (21U)
+#define SDHC_HTCAPBLT_HSS(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_HSS_SHIFT)) & SDHC_HTCAPBLT_HSS_MASK)
+#define SDHC_HTCAPBLT_DMAS_MASK                  (0x400000U)
+#define SDHC_HTCAPBLT_DMAS_SHIFT                 (22U)
+#define SDHC_HTCAPBLT_DMAS(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_DMAS_SHIFT)) & SDHC_HTCAPBLT_DMAS_MASK)
+#define SDHC_HTCAPBLT_SRS_MASK                   (0x800000U)
+#define SDHC_HTCAPBLT_SRS_SHIFT                  (23U)
+#define SDHC_HTCAPBLT_SRS(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_SRS_SHIFT)) & SDHC_HTCAPBLT_SRS_MASK)
+#define SDHC_HTCAPBLT_VS33_MASK                  (0x1000000U)
+#define SDHC_HTCAPBLT_VS33_SHIFT                 (24U)
+#define SDHC_HTCAPBLT_VS33(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_VS33_SHIFT)) & SDHC_HTCAPBLT_VS33_MASK)
+
+/*! @name WML - Watermark Level Register */
+#define SDHC_WML_RDWML_MASK                      (0xFFU)
+#define SDHC_WML_RDWML_SHIFT                     (0U)
+#define SDHC_WML_RDWML(x)                        (((uint32_t)(((uint32_t)(x)) << SDHC_WML_RDWML_SHIFT)) & SDHC_WML_RDWML_MASK)
+#define SDHC_WML_WRWML_MASK                      (0xFF0000U)
+#define SDHC_WML_WRWML_SHIFT                     (16U)
+#define SDHC_WML_WRWML(x)                        (((uint32_t)(((uint32_t)(x)) << SDHC_WML_WRWML_SHIFT)) & SDHC_WML_WRWML_MASK)
+
+/*! @name FEVT - Force Event register */
+#define SDHC_FEVT_AC12NE_MASK                    (0x1U)
+#define SDHC_FEVT_AC12NE_SHIFT                   (0U)
+#define SDHC_FEVT_AC12NE(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12NE_SHIFT)) & SDHC_FEVT_AC12NE_MASK)
+#define SDHC_FEVT_AC12TOE_MASK                   (0x2U)
+#define SDHC_FEVT_AC12TOE_SHIFT                  (1U)
+#define SDHC_FEVT_AC12TOE(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12TOE_SHIFT)) & SDHC_FEVT_AC12TOE_MASK)
+#define SDHC_FEVT_AC12CE_MASK                    (0x4U)
+#define SDHC_FEVT_AC12CE_SHIFT                   (2U)
+#define SDHC_FEVT_AC12CE(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12CE_SHIFT)) & SDHC_FEVT_AC12CE_MASK)
+#define SDHC_FEVT_AC12EBE_MASK                   (0x8U)
+#define SDHC_FEVT_AC12EBE_SHIFT                  (3U)
+#define SDHC_FEVT_AC12EBE(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12EBE_SHIFT)) & SDHC_FEVT_AC12EBE_MASK)
+#define SDHC_FEVT_AC12IE_MASK                    (0x10U)
+#define SDHC_FEVT_AC12IE_SHIFT                   (4U)
+#define SDHC_FEVT_AC12IE(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12IE_SHIFT)) & SDHC_FEVT_AC12IE_MASK)
+#define SDHC_FEVT_CNIBAC12E_MASK                 (0x80U)
+#define SDHC_FEVT_CNIBAC12E_SHIFT                (7U)
+#define SDHC_FEVT_CNIBAC12E(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CNIBAC12E_SHIFT)) & SDHC_FEVT_CNIBAC12E_MASK)
+#define SDHC_FEVT_CTOE_MASK                      (0x10000U)
+#define SDHC_FEVT_CTOE_SHIFT                     (16U)
+#define SDHC_FEVT_CTOE(x)                        (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CTOE_SHIFT)) & SDHC_FEVT_CTOE_MASK)
+#define SDHC_FEVT_CCE_MASK                       (0x20000U)
+#define SDHC_FEVT_CCE_SHIFT                      (17U)
+#define SDHC_FEVT_CCE(x)                         (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CCE_SHIFT)) & SDHC_FEVT_CCE_MASK)
+#define SDHC_FEVT_CEBE_MASK                      (0x40000U)
+#define SDHC_FEVT_CEBE_SHIFT                     (18U)
+#define SDHC_FEVT_CEBE(x)                        (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CEBE_SHIFT)) & SDHC_FEVT_CEBE_MASK)
+#define SDHC_FEVT_CIE_MASK                       (0x80000U)
+#define SDHC_FEVT_CIE_SHIFT                      (19U)
+#define SDHC_FEVT_CIE(x)                         (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CIE_SHIFT)) & SDHC_FEVT_CIE_MASK)
+#define SDHC_FEVT_DTOE_MASK                      (0x100000U)
+#define SDHC_FEVT_DTOE_SHIFT                     (20U)
+#define SDHC_FEVT_DTOE(x)                        (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DTOE_SHIFT)) & SDHC_FEVT_DTOE_MASK)
+#define SDHC_FEVT_DCE_MASK                       (0x200000U)
+#define SDHC_FEVT_DCE_SHIFT                      (21U)
+#define SDHC_FEVT_DCE(x)                         (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DCE_SHIFT)) & SDHC_FEVT_DCE_MASK)
+#define SDHC_FEVT_DEBE_MASK                      (0x400000U)
+#define SDHC_FEVT_DEBE_SHIFT                     (22U)
+#define SDHC_FEVT_DEBE(x)                        (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DEBE_SHIFT)) & SDHC_FEVT_DEBE_MASK)
+#define SDHC_FEVT_AC12E_MASK                     (0x1000000U)
+#define SDHC_FEVT_AC12E_SHIFT                    (24U)
+#define SDHC_FEVT_AC12E(x)                       (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12E_SHIFT)) & SDHC_FEVT_AC12E_MASK)
+#define SDHC_FEVT_DMAE_MASK                      (0x10000000U)
+#define SDHC_FEVT_DMAE_SHIFT                     (28U)
+#define SDHC_FEVT_DMAE(x)                        (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DMAE_SHIFT)) & SDHC_FEVT_DMAE_MASK)
+#define SDHC_FEVT_CINT_MASK                      (0x80000000U)
+#define SDHC_FEVT_CINT_SHIFT                     (31U)
+#define SDHC_FEVT_CINT(x)                        (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CINT_SHIFT)) & SDHC_FEVT_CINT_MASK)
+
+/*! @name ADMAES - ADMA Error Status register */
+#define SDHC_ADMAES_ADMAES_MASK                  (0x3U)
+#define SDHC_ADMAES_ADMAES_SHIFT                 (0U)
+#define SDHC_ADMAES_ADMAES(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMAES_SHIFT)) & SDHC_ADMAES_ADMAES_MASK)
+#define SDHC_ADMAES_ADMALME_MASK                 (0x4U)
+#define SDHC_ADMAES_ADMALME_SHIFT                (2U)
+#define SDHC_ADMAES_ADMALME(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMALME_SHIFT)) & SDHC_ADMAES_ADMALME_MASK)
+#define SDHC_ADMAES_ADMADCE_MASK                 (0x8U)
+#define SDHC_ADMAES_ADMADCE_SHIFT                (3U)
+#define SDHC_ADMAES_ADMADCE(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMADCE_SHIFT)) & SDHC_ADMAES_ADMADCE_MASK)
+
+/*! @name ADSADDR - ADMA System Addressregister */
+#define SDHC_ADSADDR_ADSADDR_MASK                (0xFFFFFFFCU)
+#define SDHC_ADSADDR_ADSADDR_SHIFT               (2U)
+#define SDHC_ADSADDR_ADSADDR(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_ADSADDR_ADSADDR_SHIFT)) & SDHC_ADSADDR_ADSADDR_MASK)
+
+/*! @name VENDOR - Vendor Specific register */
+#define SDHC_VENDOR_EXBLKNU_MASK                 (0x2U)
+#define SDHC_VENDOR_EXBLKNU_SHIFT                (1U)
+#define SDHC_VENDOR_EXBLKNU(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXBLKNU_SHIFT)) & SDHC_VENDOR_EXBLKNU_MASK)
+#define SDHC_VENDOR_INTSTVAL_MASK                (0xFF0000U)
+#define SDHC_VENDOR_INTSTVAL_SHIFT               (16U)
+#define SDHC_VENDOR_INTSTVAL(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_INTSTVAL_SHIFT)) & SDHC_VENDOR_INTSTVAL_MASK)
+
+/*! @name MMCBOOT - MMC Boot register */
+#define SDHC_MMCBOOT_DTOCVACK_MASK               (0xFU)
+#define SDHC_MMCBOOT_DTOCVACK_SHIFT              (0U)
+#define SDHC_MMCBOOT_DTOCVACK(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_DTOCVACK_SHIFT)) & SDHC_MMCBOOT_DTOCVACK_MASK)
+#define SDHC_MMCBOOT_BOOTACK_MASK                (0x10U)
+#define SDHC_MMCBOOT_BOOTACK_SHIFT               (4U)
+#define SDHC_MMCBOOT_BOOTACK(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTACK_SHIFT)) & SDHC_MMCBOOT_BOOTACK_MASK)
+#define SDHC_MMCBOOT_BOOTMODE_MASK               (0x20U)
+#define SDHC_MMCBOOT_BOOTMODE_SHIFT              (5U)
+#define SDHC_MMCBOOT_BOOTMODE(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTMODE_SHIFT)) & SDHC_MMCBOOT_BOOTMODE_MASK)
+#define SDHC_MMCBOOT_BOOTEN_MASK                 (0x40U)
+#define SDHC_MMCBOOT_BOOTEN_SHIFT                (6U)
+#define SDHC_MMCBOOT_BOOTEN(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTEN_SHIFT)) & SDHC_MMCBOOT_BOOTEN_MASK)
+#define SDHC_MMCBOOT_AUTOSABGEN_MASK             (0x80U)
+#define SDHC_MMCBOOT_AUTOSABGEN_SHIFT            (7U)
+#define SDHC_MMCBOOT_AUTOSABGEN(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_AUTOSABGEN_SHIFT)) & SDHC_MMCBOOT_AUTOSABGEN_MASK)
+#define SDHC_MMCBOOT_BOOTBLKCNT_MASK             (0xFFFF0000U)
+#define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT            (16U)
+#define SDHC_MMCBOOT_BOOTBLKCNT(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTBLKCNT_SHIFT)) & SDHC_MMCBOOT_BOOTBLKCNT_MASK)
+
+/*! @name HOSTVER - Host Controller Version */
+#define SDHC_HOSTVER_SVN_MASK                    (0xFFU)
+#define SDHC_HOSTVER_SVN_SHIFT                   (0U)
+#define SDHC_HOSTVER_SVN(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_SVN_SHIFT)) & SDHC_HOSTVER_SVN_MASK)
+#define SDHC_HOSTVER_VVN_MASK                    (0xFF00U)
+#define SDHC_HOSTVER_VVN_SHIFT                   (8U)
+#define SDHC_HOSTVER_VVN(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_VVN_SHIFT)) & SDHC_HOSTVER_VVN_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group SDHC_Register_Masks */
+
+
+/* SDHC - Peripheral instance base addresses */
+/** Peripheral SDHC base address */
+#define SDHC_BASE                                (0x400B1000u)
+/** Peripheral SDHC base pointer */
+#define SDHC                                     ((SDHC_Type *)SDHC_BASE)
+/** Array initializer of SDHC peripheral base addresses */
+#define SDHC_BASE_ADDRS                          { SDHC_BASE }
+/** Array initializer of SDHC peripheral base pointers */
+#define SDHC_BASE_PTRS                           { SDHC }
+/** Interrupt vectors for the SDHC peripheral type */
+#define SDHC_IRQS                                { SDHC_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SDHC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDRAM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDRAM_Peripheral_Access_Layer SDRAM Peripheral Access Layer
+ * @{
+ */
+
+/** SDRAM - Register Layout Typedef */
+typedef struct {
+       uint8_t RESERVED_0[66];
+  __IO uint16_t CTRL;                              /**< Control Register, offset: 0x42 */
+       uint8_t RESERVED_1[4];
+  struct {                                         /* offset: 0x48, array step: 0x8 */
+    __IO uint32_t AC;                                /**< Address and Control Register, array offset: 0x48, array step: 0x8 */
+    __IO uint32_t CM;                                /**< Control Mask, array offset: 0x4C, array step: 0x8 */
+  } BLOCK[2];
+} SDRAM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SDRAM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDRAM_Register_Masks SDRAM Register Masks
+ * @{
+ */
+
+/*! @name CTRL - Control Register */
+#define SDRAM_CTRL_RC_MASK                       (0x1FFU)
+#define SDRAM_CTRL_RC_SHIFT                      (0U)
+#define SDRAM_CTRL_RC(x)                         (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_RC_SHIFT)) & SDRAM_CTRL_RC_MASK)
+#define SDRAM_CTRL_RTIM_MASK                     (0x600U)
+#define SDRAM_CTRL_RTIM_SHIFT                    (9U)
+#define SDRAM_CTRL_RTIM(x)                       (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_RTIM_SHIFT)) & SDRAM_CTRL_RTIM_MASK)
+#define SDRAM_CTRL_IS_MASK                       (0x800U)
+#define SDRAM_CTRL_IS_SHIFT                      (11U)
+#define SDRAM_CTRL_IS(x)                         (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_IS_SHIFT)) & SDRAM_CTRL_IS_MASK)
+
+/*! @name AC - Address and Control Register */
+#define SDRAM_AC_IP_MASK                         (0x8U)
+#define SDRAM_AC_IP_SHIFT                        (3U)
+#define SDRAM_AC_IP(x)                           (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_IP_SHIFT)) & SDRAM_AC_IP_MASK)
+#define SDRAM_AC_PS_MASK                         (0x30U)
+#define SDRAM_AC_PS_SHIFT                        (4U)
+#define SDRAM_AC_PS(x)                           (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_PS_SHIFT)) & SDRAM_AC_PS_MASK)
+#define SDRAM_AC_IMRS_MASK                       (0x40U)
+#define SDRAM_AC_IMRS_SHIFT                      (6U)
+#define SDRAM_AC_IMRS(x)                         (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_IMRS_SHIFT)) & SDRAM_AC_IMRS_MASK)
+#define SDRAM_AC_CBM_MASK                        (0x700U)
+#define SDRAM_AC_CBM_SHIFT                       (8U)
+#define SDRAM_AC_CBM(x)                          (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_CBM_SHIFT)) & SDRAM_AC_CBM_MASK)
+#define SDRAM_AC_CASL_MASK                       (0x3000U)
+#define SDRAM_AC_CASL_SHIFT                      (12U)
+#define SDRAM_AC_CASL(x)                         (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_CASL_SHIFT)) & SDRAM_AC_CASL_MASK)
+#define SDRAM_AC_RE_MASK                         (0x8000U)
+#define SDRAM_AC_RE_SHIFT                        (15U)
+#define SDRAM_AC_RE(x)                           (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_RE_SHIFT)) & SDRAM_AC_RE_MASK)
+#define SDRAM_AC_BA_MASK                         (0xFFFC0000U)
+#define SDRAM_AC_BA_SHIFT                        (18U)
+#define SDRAM_AC_BA(x)                           (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_BA_SHIFT)) & SDRAM_AC_BA_MASK)
+
+/* The count of SDRAM_AC */
+#define SDRAM_AC_COUNT                           (2U)
+
+/*! @name CM - Control Mask */
+#define SDRAM_CM_V_MASK                          (0x1U)
+#define SDRAM_CM_V_SHIFT                         (0U)
+#define SDRAM_CM_V(x)                            (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_V_SHIFT)) & SDRAM_CM_V_MASK)
+#define SDRAM_CM_WP_MASK                         (0x100U)
+#define SDRAM_CM_WP_SHIFT                        (8U)
+#define SDRAM_CM_WP(x)                           (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_WP_SHIFT)) & SDRAM_CM_WP_MASK)
+#define SDRAM_CM_BAM_MASK                        (0xFFFC0000U)
+#define SDRAM_CM_BAM_SHIFT                       (18U)
+#define SDRAM_CM_BAM(x)                          (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_BAM_SHIFT)) & SDRAM_CM_BAM_MASK)
+
+/* The count of SDRAM_CM */
+#define SDRAM_CM_COUNT                           (2U)
+
+
+/*!
+ * @}
+ */ /* end of group SDRAM_Register_Masks */
+
+
+/* SDRAM - Peripheral instance base addresses */
+/** Peripheral SDRAM base address */
+#define SDRAM_BASE                               (0x4000F000u)
+/** Peripheral SDRAM base pointer */
+#define SDRAM                                    ((SDRAM_Type *)SDRAM_BASE)
+/** Array initializer of SDRAM peripheral base addresses */
+#define SDRAM_BASE_ADDRS                         { SDRAM_BASE }
+/** Array initializer of SDRAM peripheral base pointers */
+#define SDRAM_BASE_PTRS                          { SDRAM }
+
+/*!
+ * @}
+ */ /* end of group SDRAM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SIM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
+ * @{
+ */
+
+/** SIM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SOPT1;                             /**< System Options Register 1, offset: 0x0 */
+  __IO uint32_t SOPT1CFG;                          /**< SOPT1 Configuration Register, offset: 0x4 */
+  __IO uint32_t USBPHYCTL;                         /**< USB PHY Control Register, offset: 0x8 */
+       uint8_t RESERVED_0[4088];
+  __IO uint32_t SOPT2;                             /**< System Options Register 2, offset: 0x1004 */
+       uint8_t RESERVED_1[4];
+  __IO uint32_t SOPT4;                             /**< System Options Register 4, offset: 0x100C */
+  __IO uint32_t SOPT5;                             /**< System Options Register 5, offset: 0x1010 */
+       uint8_t RESERVED_2[4];
+  __IO uint32_t SOPT7;                             /**< System Options Register 7, offset: 0x1018 */
+  __IO uint32_t SOPT8;                             /**< System Options Register 8, offset: 0x101C */
+  __IO uint32_t SOPT9;                             /**< System Options Register 9, offset: 0x1020 */
+  __I  uint32_t SDID;                              /**< System Device Identification Register, offset: 0x1024 */
+  __IO uint32_t SCGC1;                             /**< System Clock Gating Control Register 1, offset: 0x1028 */
+  __IO uint32_t SCGC2;                             /**< System Clock Gating Control Register 2, offset: 0x102C */
+  __IO uint32_t SCGC3;                             /**< System Clock Gating Control Register 3, offset: 0x1030 */
+  __IO uint32_t SCGC4;                             /**< System Clock Gating Control Register 4, offset: 0x1034 */
+  __IO uint32_t SCGC5;                             /**< System Clock Gating Control Register 5, offset: 0x1038 */
+  __IO uint32_t SCGC6;                             /**< System Clock Gating Control Register 6, offset: 0x103C */
+  __IO uint32_t SCGC7;                             /**< System Clock Gating Control Register 7, offset: 0x1040 */
+  __IO uint32_t CLKDIV1;                           /**< System Clock Divider Register 1, offset: 0x1044 */
+  __IO uint32_t CLKDIV2;                           /**< System Clock Divider Register 2, offset: 0x1048 */
+  __IO uint32_t FCFG1;                             /**< Flash Configuration Register 1, offset: 0x104C */
+  __I  uint32_t FCFG2;                             /**< Flash Configuration Register 2, offset: 0x1050 */
+  __I  uint32_t UIDH;                              /**< Unique Identification Register High, offset: 0x1054 */
+  __I  uint32_t UIDMH;                             /**< Unique Identification Register Mid-High, offset: 0x1058 */
+  __I  uint32_t UIDML;                             /**< Unique Identification Register Mid Low, offset: 0x105C */
+  __I  uint32_t UIDL;                              /**< Unique Identification Register Low, offset: 0x1060 */
+  __IO uint32_t CLKDIV3;                           /**< System Clock Divider Register 3, offset: 0x1064 */
+  __IO uint32_t CLKDIV4;                           /**< System Clock Divider Register 4, offset: 0x1068 */
+} SIM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SIM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SIM_Register_Masks SIM Register Masks
+ * @{
+ */
+
+/*! @name SOPT1 - System Options Register 1 */
+#define SIM_SOPT1_RAMSIZE_MASK                   (0xF000U)
+#define SIM_SOPT1_RAMSIZE_SHIFT                  (12U)
+#define SIM_SOPT1_RAMSIZE(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)
+#define SIM_SOPT1_OSC32KSEL_MASK                 (0xC0000U)
+#define SIM_SOPT1_OSC32KSEL_SHIFT                (18U)
+#define SIM_SOPT1_OSC32KSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
+#define SIM_SOPT1_USBVSTBY_MASK                  (0x20000000U)
+#define SIM_SOPT1_USBVSTBY_SHIFT                 (29U)
+#define SIM_SOPT1_USBVSTBY(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)
+#define SIM_SOPT1_USBSSTBY_MASK                  (0x40000000U)
+#define SIM_SOPT1_USBSSTBY_SHIFT                 (30U)
+#define SIM_SOPT1_USBSSTBY(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)
+#define SIM_SOPT1_USBREGEN_MASK                  (0x80000000U)
+#define SIM_SOPT1_USBREGEN_SHIFT                 (31U)
+#define SIM_SOPT1_USBREGEN(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)
+
+/*! @name SOPT1CFG - SOPT1 Configuration Register */
+#define SIM_SOPT1CFG_URWE_MASK                   (0x1000000U)
+#define SIM_SOPT1CFG_URWE_SHIFT                  (24U)
+#define SIM_SOPT1CFG_URWE(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
+#define SIM_SOPT1CFG_UVSWE_MASK                  (0x2000000U)
+#define SIM_SOPT1CFG_UVSWE_SHIFT                 (25U)
+#define SIM_SOPT1CFG_UVSWE(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)
+#define SIM_SOPT1CFG_USSWE_MASK                  (0x4000000U)
+#define SIM_SOPT1CFG_USSWE_SHIFT                 (26U)
+#define SIM_SOPT1CFG_USSWE(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)
+
+/*! @name USBPHYCTL - USB PHY Control Register */
+#define SIM_USBPHYCTL_USBVREGSEL_MASK            (0x100U)
+#define SIM_USBPHYCTL_USBVREGSEL_SHIFT           (8U)
+#define SIM_USBPHYCTL_USBVREGSEL(x)              (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBVREGSEL_SHIFT)) & SIM_USBPHYCTL_USBVREGSEL_MASK)
+#define SIM_USBPHYCTL_USBVREGPD_MASK             (0x200U)
+#define SIM_USBPHYCTL_USBVREGPD_SHIFT            (9U)
+#define SIM_USBPHYCTL_USBVREGPD(x)               (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBVREGPD_SHIFT)) & SIM_USBPHYCTL_USBVREGPD_MASK)
+#define SIM_USBPHYCTL_USB3VOUTTRG_MASK           (0x700000U)
+#define SIM_USBPHYCTL_USB3VOUTTRG_SHIFT          (20U)
+#define SIM_USBPHYCTL_USB3VOUTTRG(x)             (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USB3VOUTTRG_SHIFT)) & SIM_USBPHYCTL_USB3VOUTTRG_MASK)
+#define SIM_USBPHYCTL_USBDISILIM_MASK            (0x800000U)
+#define SIM_USBPHYCTL_USBDISILIM_SHIFT           (23U)
+#define SIM_USBPHYCTL_USBDISILIM(x)              (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBDISILIM_SHIFT)) & SIM_USBPHYCTL_USBDISILIM_MASK)
+
+/*! @name SOPT2 - System Options Register 2 */
+#define SIM_SOPT2_USBSLSRC_MASK                  (0x1U)
+#define SIM_SOPT2_USBSLSRC_SHIFT                 (0U)
+#define SIM_SOPT2_USBSLSRC(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSLSRC_SHIFT)) & SIM_SOPT2_USBSLSRC_MASK)
+#define SIM_SOPT2_USBREGEN_MASK                  (0x2U)
+#define SIM_SOPT2_USBREGEN_SHIFT                 (1U)
+#define SIM_SOPT2_USBREGEN(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBREGEN_SHIFT)) & SIM_SOPT2_USBREGEN_MASK)
+#define SIM_SOPT2_RTCCLKOUTSEL_MASK              (0x10U)
+#define SIM_SOPT2_RTCCLKOUTSEL_SHIFT             (4U)
+#define SIM_SOPT2_RTCCLKOUTSEL(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
+#define SIM_SOPT2_CLKOUTSEL_MASK                 (0xE0U)
+#define SIM_SOPT2_CLKOUTSEL_SHIFT                (5U)
+#define SIM_SOPT2_CLKOUTSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_FBSL_MASK                      (0x300U)
+#define SIM_SOPT2_FBSL_SHIFT                     (8U)
+#define SIM_SOPT2_FBSL(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FBSL_SHIFT)) & SIM_SOPT2_FBSL_MASK)
+#define SIM_SOPT2_TRACECLKSEL_MASK               (0x1000U)
+#define SIM_SOPT2_TRACECLKSEL_SHIFT              (12U)
+#define SIM_SOPT2_TRACECLKSEL(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)
+#define SIM_SOPT2_PLLFLLSEL_MASK                 (0x30000U)
+#define SIM_SOPT2_PLLFLLSEL_SHIFT                (16U)
+#define SIM_SOPT2_PLLFLLSEL_SET(x)               (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
+#define SIM_SOPT2_PLLFLLSEL                      SIM_SOPT2_PLLFLLSEL_SET(1)
+#define SIM_SOPT2_USBSRC_MASK                    (0x40000U)
+#define SIM_SOPT2_USBSRC_SHIFT                   (18U)
+#define SIM_SOPT2_USBSRC_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)
+#define SIM_SOPT2_USBSRC                         SIM_SOPT2_USBSRC_SET(1)
+#define SIM_SOPT2_RMIISRC_MASK                   (0x80000U)
+#define SIM_SOPT2_RMIISRC_SHIFT                  (19U)
+#define SIM_SOPT2_RMIISRC(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RMIISRC_SHIFT)) & SIM_SOPT2_RMIISRC_MASK)
+#define SIM_SOPT2_TIMESRC_MASK                   (0x300000U)
+#define SIM_SOPT2_TIMESRC_SHIFT                  (20U)
+#define SIM_SOPT2_TIMESRC(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TIMESRC_SHIFT)) & SIM_SOPT2_TIMESRC_MASK)
+#define SIM_SOPT2_TPMSRC_MASK                    (0x3000000U)
+#define SIM_SOPT2_TPMSRC_SHIFT                   (24U)
+#define SIM_SOPT2_TPMSRC(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TPMSRC_SHIFT)) & SIM_SOPT2_TPMSRC_MASK)
+#define SIM_SOPT2_LPUARTSRC_MASK                 (0xC000000U)
+#define SIM_SOPT2_LPUARTSRC_SHIFT                (26U)
+#define SIM_SOPT2_LPUARTSRC(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUARTSRC_SHIFT)) & SIM_SOPT2_LPUARTSRC_MASK)
+#define SIM_SOPT2_SDHCSRC_MASK                   (0x30000000U)
+#define SIM_SOPT2_SDHCSRC_SHIFT                  (28U)
+#define SIM_SOPT2_SDHCSRC(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_SDHCSRC_SHIFT)) & SIM_SOPT2_SDHCSRC_MASK)
+
+/*! @name SOPT4 - System Options Register 4 */
+#define SIM_SOPT4_FTM0FLT0_MASK                  (0x1U)
+#define SIM_SOPT4_FTM0FLT0_SHIFT                 (0U)
+#define SIM_SOPT4_FTM0FLT0(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)
+#define SIM_SOPT4_FTM0FLT1_MASK                  (0x2U)
+#define SIM_SOPT4_FTM0FLT1_SHIFT                 (1U)
+#define SIM_SOPT4_FTM0FLT1(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)
+#define SIM_SOPT4_FTM0FLT2_MASK                  (0x4U)
+#define SIM_SOPT4_FTM0FLT2_SHIFT                 (2U)
+#define SIM_SOPT4_FTM0FLT2(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT2_SHIFT)) & SIM_SOPT4_FTM0FLT2_MASK)
+#define SIM_SOPT4_FTM0FLT3_MASK                  (0x8U)
+#define SIM_SOPT4_FTM0FLT3_SHIFT                 (3U)
+#define SIM_SOPT4_FTM0FLT3(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT3_SHIFT)) & SIM_SOPT4_FTM0FLT3_MASK)
+#define SIM_SOPT4_FTM1FLT0_MASK                  (0x10U)
+#define SIM_SOPT4_FTM1FLT0_SHIFT                 (4U)
+#define SIM_SOPT4_FTM1FLT0(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)
+#define SIM_SOPT4_FTM2FLT0_MASK                  (0x100U)
+#define SIM_SOPT4_FTM2FLT0_SHIFT                 (8U)
+#define SIM_SOPT4_FTM2FLT0(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK)
+#define SIM_SOPT4_FTM3FLT0_MASK                  (0x1000U)
+#define SIM_SOPT4_FTM3FLT0_SHIFT                 (12U)
+#define SIM_SOPT4_FTM3FLT0(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3FLT0_SHIFT)) & SIM_SOPT4_FTM3FLT0_MASK)
+#define SIM_SOPT4_FTM1CH0SRC_MASK                (0xC0000U)
+#define SIM_SOPT4_FTM1CH0SRC_SHIFT               (18U)
+#define SIM_SOPT4_FTM1CH0SRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK)
+#define SIM_SOPT4_FTM2CH0SRC_MASK                (0x300000U)
+#define SIM_SOPT4_FTM2CH0SRC_SHIFT               (20U)
+#define SIM_SOPT4_FTM2CH0SRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK)
+#define SIM_SOPT4_FTM2CH1SRC_MASK                (0x400000U)
+#define SIM_SOPT4_FTM2CH1SRC_SHIFT               (22U)
+#define SIM_SOPT4_FTM2CH1SRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH1SRC_SHIFT)) & SIM_SOPT4_FTM2CH1SRC_MASK)
+#define SIM_SOPT4_FTM0CLKSEL_MASK                (0x1000000U)
+#define SIM_SOPT4_FTM0CLKSEL_SHIFT               (24U)
+#define SIM_SOPT4_FTM0CLKSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK)
+#define SIM_SOPT4_FTM1CLKSEL_MASK                (0x2000000U)
+#define SIM_SOPT4_FTM1CLKSEL_SHIFT               (25U)
+#define SIM_SOPT4_FTM1CLKSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK)
+#define SIM_SOPT4_FTM2CLKSEL_MASK                (0x4000000U)
+#define SIM_SOPT4_FTM2CLKSEL_SHIFT               (26U)
+#define SIM_SOPT4_FTM2CLKSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK)
+#define SIM_SOPT4_FTM3CLKSEL_MASK                (0x8000000U)
+#define SIM_SOPT4_FTM3CLKSEL_SHIFT               (27U)
+#define SIM_SOPT4_FTM3CLKSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3CLKSEL_SHIFT)) & SIM_SOPT4_FTM3CLKSEL_MASK)
+#define SIM_SOPT4_FTM0TRG0SRC_MASK               (0x10000000U)
+#define SIM_SOPT4_FTM0TRG0SRC_SHIFT              (28U)
+#define SIM_SOPT4_FTM0TRG0SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)
+#define SIM_SOPT4_FTM0TRG1SRC_MASK               (0x20000000U)
+#define SIM_SOPT4_FTM0TRG1SRC_SHIFT              (29U)
+#define SIM_SOPT4_FTM0TRG1SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK)
+#define SIM_SOPT4_FTM3TRG0SRC_MASK               (0x40000000U)
+#define SIM_SOPT4_FTM3TRG0SRC_SHIFT              (30U)
+#define SIM_SOPT4_FTM3TRG0SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG0SRC_SHIFT)) & SIM_SOPT4_FTM3TRG0SRC_MASK)
+#define SIM_SOPT4_FTM3TRG1SRC_MASK               (0x80000000U)
+#define SIM_SOPT4_FTM3TRG1SRC_SHIFT              (31U)
+#define SIM_SOPT4_FTM3TRG1SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG1SRC_SHIFT)) & SIM_SOPT4_FTM3TRG1SRC_MASK)
+
+/*! @name SOPT5 - System Options Register 5 */
+#define SIM_SOPT5_UART0TXSRC_MASK                (0x3U)
+#define SIM_SOPT5_UART0TXSRC_SHIFT               (0U)
+#define SIM_SOPT5_UART0TXSRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
+#define SIM_SOPT5_UART0RXSRC_MASK                (0xCU)
+#define SIM_SOPT5_UART0RXSRC_SHIFT               (2U)
+#define SIM_SOPT5_UART0RXSRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
+#define SIM_SOPT5_UART1TXSRC_MASK                (0x30U)
+#define SIM_SOPT5_UART1TXSRC_SHIFT               (4U)
+#define SIM_SOPT5_UART1TXSRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
+#define SIM_SOPT5_UART1RXSRC_MASK                (0xC0U)
+#define SIM_SOPT5_UART1RXSRC_SHIFT               (6U)
+#define SIM_SOPT5_UART1RXSRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
+#define SIM_SOPT5_LPUART0TXSRC_MASK              (0x30000U)
+#define SIM_SOPT5_LPUART0TXSRC_SHIFT             (16U)
+#define SIM_SOPT5_LPUART0TXSRC(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0TXSRC_SHIFT)) & SIM_SOPT5_LPUART0TXSRC_MASK)
+#define SIM_SOPT5_LPUART0RXSRC_MASK              (0xC0000U)
+#define SIM_SOPT5_LPUART0RXSRC_SHIFT             (18U)
+#define SIM_SOPT5_LPUART0RXSRC(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0RXSRC_SHIFT)) & SIM_SOPT5_LPUART0RXSRC_MASK)
+
+/*! @name SOPT7 - System Options Register 7 */
+#define SIM_SOPT7_ADC0TRGSEL_MASK                (0xFU)
+#define SIM_SOPT7_ADC0TRGSEL_SHIFT               (0U)
+#define SIM_SOPT7_ADC0TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_MASK             (0x10U)
+#define SIM_SOPT7_ADC0PRETRGSEL_SHIFT            (4U)
+#define SIM_SOPT7_ADC0PRETRGSEL(x)               (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
+#define SIM_SOPT7_ADC0ALTTRGEN_MASK              (0x80U)
+#define SIM_SOPT7_ADC0ALTTRGEN_SHIFT             (7U)
+#define SIM_SOPT7_ADC0ALTTRGEN(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
+#define SIM_SOPT7_ADC1TRGSEL_MASK                (0xF00U)
+#define SIM_SOPT7_ADC1TRGSEL_SHIFT               (8U)
+#define SIM_SOPT7_ADC1TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1TRGSEL_SHIFT)) & SIM_SOPT7_ADC1TRGSEL_MASK)
+#define SIM_SOPT7_ADC1PRETRGSEL_MASK             (0x1000U)
+#define SIM_SOPT7_ADC1PRETRGSEL_SHIFT            (12U)
+#define SIM_SOPT7_ADC1PRETRGSEL(x)               (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC1PRETRGSEL_MASK)
+#define SIM_SOPT7_ADC1ALTTRGEN_MASK              (0x8000U)
+#define SIM_SOPT7_ADC1ALTTRGEN_SHIFT             (15U)
+#define SIM_SOPT7_ADC1ALTTRGEN(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC1ALTTRGEN_MASK)
+
+/*! @name SOPT8 - System Options Register 8 */
+#define SIM_SOPT8_FTM0SYNCBIT_MASK               (0x1U)
+#define SIM_SOPT8_FTM0SYNCBIT_SHIFT              (0U)
+#define SIM_SOPT8_FTM0SYNCBIT(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0SYNCBIT_SHIFT)) & SIM_SOPT8_FTM0SYNCBIT_MASK)
+#define SIM_SOPT8_FTM1SYNCBIT_MASK               (0x2U)
+#define SIM_SOPT8_FTM1SYNCBIT_SHIFT              (1U)
+#define SIM_SOPT8_FTM1SYNCBIT(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM1SYNCBIT_SHIFT)) & SIM_SOPT8_FTM1SYNCBIT_MASK)
+#define SIM_SOPT8_FTM2SYNCBIT_MASK               (0x4U)
+#define SIM_SOPT8_FTM2SYNCBIT_SHIFT              (2U)
+#define SIM_SOPT8_FTM2SYNCBIT(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM2SYNCBIT_SHIFT)) & SIM_SOPT8_FTM2SYNCBIT_MASK)
+#define SIM_SOPT8_FTM3SYNCBIT_MASK               (0x8U)
+#define SIM_SOPT8_FTM3SYNCBIT_SHIFT              (3U)
+#define SIM_SOPT8_FTM3SYNCBIT(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3SYNCBIT_SHIFT)) & SIM_SOPT8_FTM3SYNCBIT_MASK)
+#define SIM_SOPT8_FTM0OCH0SRC_MASK               (0x10000U)
+#define SIM_SOPT8_FTM0OCH0SRC_SHIFT              (16U)
+#define SIM_SOPT8_FTM0OCH0SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH0SRC_SHIFT)) & SIM_SOPT8_FTM0OCH0SRC_MASK)
+#define SIM_SOPT8_FTM0OCH1SRC_MASK               (0x20000U)
+#define SIM_SOPT8_FTM0OCH1SRC_SHIFT              (17U)
+#define SIM_SOPT8_FTM0OCH1SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH1SRC_SHIFT)) & SIM_SOPT8_FTM0OCH1SRC_MASK)
+#define SIM_SOPT8_FTM0OCH2SRC_MASK               (0x40000U)
+#define SIM_SOPT8_FTM0OCH2SRC_SHIFT              (18U)
+#define SIM_SOPT8_FTM0OCH2SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH2SRC_SHIFT)) & SIM_SOPT8_FTM0OCH2SRC_MASK)
+#define SIM_SOPT8_FTM0OCH3SRC_MASK               (0x80000U)
+#define SIM_SOPT8_FTM0OCH3SRC_SHIFT              (19U)
+#define SIM_SOPT8_FTM0OCH3SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH3SRC_SHIFT)) & SIM_SOPT8_FTM0OCH3SRC_MASK)
+#define SIM_SOPT8_FTM0OCH4SRC_MASK               (0x100000U)
+#define SIM_SOPT8_FTM0OCH4SRC_SHIFT              (20U)
+#define SIM_SOPT8_FTM0OCH4SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH4SRC_SHIFT)) & SIM_SOPT8_FTM0OCH4SRC_MASK)
+#define SIM_SOPT8_FTM0OCH5SRC_MASK               (0x200000U)
+#define SIM_SOPT8_FTM0OCH5SRC_SHIFT              (21U)
+#define SIM_SOPT8_FTM0OCH5SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH5SRC_SHIFT)) & SIM_SOPT8_FTM0OCH5SRC_MASK)
+#define SIM_SOPT8_FTM0OCH6SRC_MASK               (0x400000U)
+#define SIM_SOPT8_FTM0OCH6SRC_SHIFT              (22U)
+#define SIM_SOPT8_FTM0OCH6SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH6SRC_SHIFT)) & SIM_SOPT8_FTM0OCH6SRC_MASK)
+#define SIM_SOPT8_FTM0OCH7SRC_MASK               (0x800000U)
+#define SIM_SOPT8_FTM0OCH7SRC_SHIFT              (23U)
+#define SIM_SOPT8_FTM0OCH7SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH7SRC_SHIFT)) & SIM_SOPT8_FTM0OCH7SRC_MASK)
+#define SIM_SOPT8_FTM3OCH0SRC_MASK               (0x1000000U)
+#define SIM_SOPT8_FTM3OCH0SRC_SHIFT              (24U)
+#define SIM_SOPT8_FTM3OCH0SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH0SRC_SHIFT)) & SIM_SOPT8_FTM3OCH0SRC_MASK)
+#define SIM_SOPT8_FTM3OCH1SRC_MASK               (0x2000000U)
+#define SIM_SOPT8_FTM3OCH1SRC_SHIFT              (25U)
+#define SIM_SOPT8_FTM3OCH1SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH1SRC_SHIFT)) & SIM_SOPT8_FTM3OCH1SRC_MASK)
+#define SIM_SOPT8_FTM3OCH2SRC_MASK               (0x4000000U)
+#define SIM_SOPT8_FTM3OCH2SRC_SHIFT              (26U)
+#define SIM_SOPT8_FTM3OCH2SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH2SRC_SHIFT)) & SIM_SOPT8_FTM3OCH2SRC_MASK)
+#define SIM_SOPT8_FTM3OCH3SRC_MASK               (0x8000000U)
+#define SIM_SOPT8_FTM3OCH3SRC_SHIFT              (27U)
+#define SIM_SOPT8_FTM3OCH3SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH3SRC_SHIFT)) & SIM_SOPT8_FTM3OCH3SRC_MASK)
+#define SIM_SOPT8_FTM3OCH4SRC_MASK               (0x10000000U)
+#define SIM_SOPT8_FTM3OCH4SRC_SHIFT              (28U)
+#define SIM_SOPT8_FTM3OCH4SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH4SRC_SHIFT)) & SIM_SOPT8_FTM3OCH4SRC_MASK)
+#define SIM_SOPT8_FTM3OCH5SRC_MASK               (0x20000000U)
+#define SIM_SOPT8_FTM3OCH5SRC_SHIFT              (29U)
+#define SIM_SOPT8_FTM3OCH5SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH5SRC_SHIFT)) & SIM_SOPT8_FTM3OCH5SRC_MASK)
+#define SIM_SOPT8_FTM3OCH6SRC_MASK               (0x40000000U)
+#define SIM_SOPT8_FTM3OCH6SRC_SHIFT              (30U)
+#define SIM_SOPT8_FTM3OCH6SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH6SRC_SHIFT)) & SIM_SOPT8_FTM3OCH6SRC_MASK)
+#define SIM_SOPT8_FTM3OCH7SRC_MASK               (0x80000000U)
+#define SIM_SOPT8_FTM3OCH7SRC_SHIFT              (31U)
+#define SIM_SOPT8_FTM3OCH7SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH7SRC_SHIFT)) & SIM_SOPT8_FTM3OCH7SRC_MASK)
+
+/*! @name SOPT9 - System Options Register 9 */
+#define SIM_SOPT9_TPM1CH0SRC_MASK                (0xC0000U)
+#define SIM_SOPT9_TPM1CH0SRC_SHIFT               (18U)
+#define SIM_SOPT9_TPM1CH0SRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM1CH0SRC_SHIFT)) & SIM_SOPT9_TPM1CH0SRC_MASK)
+#define SIM_SOPT9_TPM2CH0SRC_MASK                (0x300000U)
+#define SIM_SOPT9_TPM2CH0SRC_SHIFT               (20U)
+#define SIM_SOPT9_TPM2CH0SRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM2CH0SRC_SHIFT)) & SIM_SOPT9_TPM2CH0SRC_MASK)
+#define SIM_SOPT9_TPM1CLKSEL_MASK                (0x2000000U)
+#define SIM_SOPT9_TPM1CLKSEL_SHIFT               (25U)
+#define SIM_SOPT9_TPM1CLKSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM1CLKSEL_SHIFT)) & SIM_SOPT9_TPM1CLKSEL_MASK)
+#define SIM_SOPT9_TPM2CLKSEL_MASK                (0x4000000U)
+#define SIM_SOPT9_TPM2CLKSEL_SHIFT               (26U)
+#define SIM_SOPT9_TPM2CLKSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM2CLKSEL_SHIFT)) & SIM_SOPT9_TPM2CLKSEL_MASK)
+
+/*! @name SDID - System Device Identification Register */
+#define SIM_SDID_PINID_MASK                      (0xFU)
+#define SIM_SDID_PINID_SHIFT                     (0U)
+#define SIM_SDID_PINID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
+#define SIM_SDID_FAMID_MASK                      (0x70U)
+#define SIM_SDID_FAMID_SHIFT                     (4U)
+#define SIM_SDID_FAMID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
+#define SIM_SDID_DIEID_MASK                      (0xF80U)
+#define SIM_SDID_DIEID_SHIFT                     (7U)
+#define SIM_SDID_DIEID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
+#define SIM_SDID_REVID_MASK                      (0xF000U)
+#define SIM_SDID_REVID_SHIFT                     (12U)
+#define SIM_SDID_REVID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
+#define SIM_SDID_SERIESID_MASK                   (0xF00000U)
+#define SIM_SDID_SERIESID_SHIFT                  (20U)
+#define SIM_SDID_SERIESID(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
+#define SIM_SDID_SUBFAMID_MASK                   (0xF000000U)
+#define SIM_SDID_SUBFAMID_SHIFT                  (24U)
+#define SIM_SDID_SUBFAMID(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
+#define SIM_SDID_FAMILYID_MASK                   (0xF0000000U)
+#define SIM_SDID_FAMILYID_SHIFT                  (28U)
+#define SIM_SDID_FAMILYID(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK)
+
+/*! @name SCGC1 - System Clock Gating Control Register 1 */
+#define SIM_SCGC1_I2C2_MASK                      (0x40U)
+#define SIM_SCGC1_I2C2_SHIFT                     (6U)
+#define SIM_SCGC1_I2C2(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C2_SHIFT)) & SIM_SCGC1_I2C2_MASK)
+#define SIM_SCGC1_I2C3_MASK                      (0x80U)
+#define SIM_SCGC1_I2C3_SHIFT                     (7U)
+#define SIM_SCGC1_I2C3(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C3_SHIFT)) & SIM_SCGC1_I2C3_MASK)
+#define SIM_SCGC1_UART4_MASK                     (0x400U)
+#define SIM_SCGC1_UART4_SHIFT                    (10U)
+#define SIM_SCGC1_UART4(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART4_SHIFT)) & SIM_SCGC1_UART4_MASK)
+
+/*! @name SCGC2 - System Clock Gating Control Register 2 */
+#define SIM_SCGC2_ENET_MASK                      (0x1U)
+#define SIM_SCGC2_ENET_SHIFT                     (0U)
+#define SIM_SCGC2_ENET(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_ENET_SHIFT)) & SIM_SCGC2_ENET_MASK)
+#define SIM_SCGC2_LPUART0_MASK                   (0x10U)
+#define SIM_SCGC2_LPUART0_SHIFT                  (4U)
+#define SIM_SCGC2_LPUART0(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_LPUART0_SHIFT)) & SIM_SCGC2_LPUART0_MASK)
+#define SIM_SCGC2_TPM1_MASK                      (0x200U)
+#define SIM_SCGC2_TPM1_SHIFT                     (9U)
+#define SIM_SCGC2_TPM1(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_TPM1_SHIFT)) & SIM_SCGC2_TPM1_MASK)
+#define SIM_SCGC2_TPM2_MASK                      (0x400U)
+#define SIM_SCGC2_TPM2_SHIFT                     (10U)
+#define SIM_SCGC2_TPM2(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_TPM2_SHIFT)) & SIM_SCGC2_TPM2_MASK)
+#define SIM_SCGC2_DAC0_MASK                      (0x1000U)
+#define SIM_SCGC2_DAC0_SHIFT                     (12U)
+#define SIM_SCGC2_DAC0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC0_SHIFT)) & SIM_SCGC2_DAC0_MASK)
+#define SIM_SCGC2_DAC1_MASK                      (0x2000U)
+#define SIM_SCGC2_DAC1_SHIFT                     (13U)
+#define SIM_SCGC2_DAC1(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC1_SHIFT)) & SIM_SCGC2_DAC1_MASK)
+
+/*! @name SCGC3 - System Clock Gating Control Register 3 */
+#define SIM_SCGC3_RNGA_MASK                      (0x1U)
+#define SIM_SCGC3_RNGA_SHIFT                     (0U)
+#define SIM_SCGC3_RNGA(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_RNGA_SHIFT)) & SIM_SCGC3_RNGA_MASK)
+#define SIM_SCGC3_USBHS_MASK                     (0x2U)
+#define SIM_SCGC3_USBHS_SHIFT                    (1U)
+#define SIM_SCGC3_USBHS(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHS_SHIFT)) & SIM_SCGC3_USBHS_MASK)
+#define SIM_SCGC3_USBHSPHY_MASK                  (0x4U)
+#define SIM_SCGC3_USBHSPHY_SHIFT                 (2U)
+#define SIM_SCGC3_USBHSPHY(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHSPHY_SHIFT)) & SIM_SCGC3_USBHSPHY_MASK)
+#define SIM_SCGC3_USBHSDCD_MASK                  (0x8U)
+#define SIM_SCGC3_USBHSDCD_SHIFT                 (3U)
+#define SIM_SCGC3_USBHSDCD(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHSDCD_SHIFT)) & SIM_SCGC3_USBHSDCD_MASK)
+#define SIM_SCGC3_FLEXCAN1_MASK                  (0x10U)
+#define SIM_SCGC3_FLEXCAN1_SHIFT                 (4U)
+#define SIM_SCGC3_FLEXCAN1(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FLEXCAN1_SHIFT)) & SIM_SCGC3_FLEXCAN1_MASK)
+#define SIM_SCGC3_SPI2_MASK                      (0x1000U)
+#define SIM_SCGC3_SPI2_SHIFT                     (12U)
+#define SIM_SCGC3_SPI2(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SPI2_SHIFT)) & SIM_SCGC3_SPI2_MASK)
+#define SIM_SCGC3_SDHC_MASK                      (0x20000U)
+#define SIM_SCGC3_SDHC_SHIFT                     (17U)
+#define SIM_SCGC3_SDHC(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SDHC_SHIFT)) & SIM_SCGC3_SDHC_MASK)
+#define SIM_SCGC3_FTM2_MASK                      (0x1000000U)
+#define SIM_SCGC3_FTM2_SHIFT                     (24U)
+#define SIM_SCGC3_FTM2(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM2_SHIFT)) & SIM_SCGC3_FTM2_MASK)
+#define SIM_SCGC3_FTM3_MASK                      (0x2000000U)
+#define SIM_SCGC3_FTM3_SHIFT                     (25U)
+#define SIM_SCGC3_FTM3(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM3_SHIFT)) & SIM_SCGC3_FTM3_MASK)
+#define SIM_SCGC3_ADC1_MASK                      (0x8000000U)
+#define SIM_SCGC3_ADC1_SHIFT                     (27U)
+#define SIM_SCGC3_ADC1(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_ADC1_SHIFT)) & SIM_SCGC3_ADC1_MASK)
+
+/*! @name SCGC4 - System Clock Gating Control Register 4 */
+#define SIM_SCGC4_EWM_MASK                       (0x2U)
+#define SIM_SCGC4_EWM_SHIFT                      (1U)
+#define SIM_SCGC4_EWM(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)
+#define SIM_SCGC4_CMT_MASK                       (0x4U)
+#define SIM_SCGC4_CMT_SHIFT                      (2U)
+#define SIM_SCGC4_CMT(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK)
+#define SIM_SCGC4_I2C0_MASK                      (0x40U)
+#define SIM_SCGC4_I2C0_SHIFT                     (6U)
+#define SIM_SCGC4_I2C0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
+#define SIM_SCGC4_I2C1_MASK                      (0x80U)
+#define SIM_SCGC4_I2C1_SHIFT                     (7U)
+#define SIM_SCGC4_I2C1(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
+#define SIM_SCGC4_UART0_MASK                     (0x400U)
+#define SIM_SCGC4_UART0_SHIFT                    (10U)
+#define SIM_SCGC4_UART0(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)
+#define SIM_SCGC4_UART1_MASK                     (0x800U)
+#define SIM_SCGC4_UART1_SHIFT                    (11U)
+#define SIM_SCGC4_UART1(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)
+#define SIM_SCGC4_UART2_MASK                     (0x1000U)
+#define SIM_SCGC4_UART2_SHIFT                    (12U)
+#define SIM_SCGC4_UART2(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
+#define SIM_SCGC4_UART3_MASK                     (0x2000U)
+#define SIM_SCGC4_UART3_SHIFT                    (13U)
+#define SIM_SCGC4_UART3(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART3_SHIFT)) & SIM_SCGC4_UART3_MASK)
+#define SIM_SCGC4_USBOTG_MASK                    (0x40000U)
+#define SIM_SCGC4_USBOTG_SHIFT                   (18U)
+#define SIM_SCGC4_USBOTG_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK)
+#define SIM_SCGC4_USBOTG                         SIM_SCGC4_USBOTG_SET(1)
+#define SIM_SCGC4_CMP_MASK                       (0x80000U)
+#define SIM_SCGC4_CMP_SHIFT                      (19U)
+#define SIM_SCGC4_CMP(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
+#define SIM_SCGC4_VREF_MASK                      (0x100000U)
+#define SIM_SCGC4_VREF_SHIFT                     (20U)
+#define SIM_SCGC4_VREF(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
+
+/*! @name SCGC5 - System Clock Gating Control Register 5 */
+#define SIM_SCGC5_LPTMR_MASK                     (0x1U)
+#define SIM_SCGC5_LPTMR_SHIFT                    (0U)
+#define SIM_SCGC5_LPTMR(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
+#define SIM_SCGC5_TSI_MASK                       (0x20U)
+#define SIM_SCGC5_TSI_SHIFT                      (5U)
+#define SIM_SCGC5_TSI(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK)
+#define SIM_SCGC5_PORTA_MASK                     (0x200U)
+#define SIM_SCGC5_PORTA_SHIFT                    (9U)
+#define SIM_SCGC5_PORTA_SET(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
+#define SIM_SCGC5_PORTA                          SIM_SCGC5_PORTA_SET(1)
+#define SIM_SCGC5_PORTB_MASK                     (0x400U)
+#define SIM_SCGC5_PORTB_SHIFT                    (10U)
+#define SIM_SCGC5_PORTB_SET(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
+#define SIM_SCGC5_PORTB                          SIM_SCGC5_PORTB_SET(1)
+#define SIM_SCGC5_PORTC_MASK                     (0x800U)
+#define SIM_SCGC5_PORTC_SHIFT                    (11U)
+#define SIM_SCGC5_PORTC_SET(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
+#define SIM_SCGC5_PORTC                          SIM_SCGC5_PORTC_SET(1)
+#define SIM_SCGC5_PORTD_MASK                     (0x1000U)
+#define SIM_SCGC5_PORTD_SHIFT                    (12U)
+#define SIM_SCGC5_PORTD_SET(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
+#define SIM_SCGC5_PORTD                          SIM_SCGC5_PORTD_SET(1)
+#define SIM_SCGC5_PORTE_MASK                     (0x2000U)
+#define SIM_SCGC5_PORTE_SHIFT                    (13U)
+#define SIM_SCGC5_PORTE_SET(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
+#define SIM_SCGC5_PORTE                          SIM_SCGC5_PORTE_SET(1)
+
+/*! @name SCGC6 - System Clock Gating Control Register 6 */
+#define SIM_SCGC6_FTF_MASK                       (0x1U)
+#define SIM_SCGC6_FTF_SHIFT                      (0U)
+#define SIM_SCGC6_FTF(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
+#define SIM_SCGC6_DMAMUX_MASK                    (0x2U)
+#define SIM_SCGC6_DMAMUX_SHIFT                   (1U)
+#define SIM_SCGC6_DMAMUX(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
+#define SIM_SCGC6_FLEXCAN0_MASK                  (0x10U)
+#define SIM_SCGC6_FLEXCAN0_SHIFT                 (4U)
+#define SIM_SCGC6_FLEXCAN0(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FLEXCAN0_SHIFT)) & SIM_SCGC6_FLEXCAN0_MASK)
+#define SIM_SCGC6_RNGA_MASK                      (0x200U)
+#define SIM_SCGC6_RNGA_SHIFT                     (9U)
+#define SIM_SCGC6_RNGA(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RNGA_SHIFT)) & SIM_SCGC6_RNGA_MASK)
+#define SIM_SCGC6_SPI0_MASK                      (0x1000U)
+#define SIM_SCGC6_SPI0_SHIFT                     (12U)
+#define SIM_SCGC6_SPI0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)
+#define SIM_SCGC6_SPI1_MASK                      (0x2000U)
+#define SIM_SCGC6_SPI1_SHIFT                     (13U)
+#define SIM_SCGC6_SPI1(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)
+#define SIM_SCGC6_I2S_MASK                       (0x8000U)
+#define SIM_SCGC6_I2S_SHIFT                      (15U)
+#define SIM_SCGC6_I2S(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)
+#define SIM_SCGC6_CRC_MASK                       (0x40000U)
+#define SIM_SCGC6_CRC_SHIFT                      (18U)
+#define SIM_SCGC6_CRC(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)
+#define SIM_SCGC6_USBDCD_MASK                    (0x200000U)
+#define SIM_SCGC6_USBDCD_SHIFT                   (21U)
+#define SIM_SCGC6_USBDCD(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_USBDCD_SHIFT)) & SIM_SCGC6_USBDCD_MASK)
+#define SIM_SCGC6_PDB_MASK                       (0x400000U)
+#define SIM_SCGC6_PDB_SHIFT                      (22U)
+#define SIM_SCGC6_PDB(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK)
+#define SIM_SCGC6_PIT_MASK                       (0x800000U)
+#define SIM_SCGC6_PIT_SHIFT                      (23U)
+#define SIM_SCGC6_PIT(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
+#define SIM_SCGC6_FTM0_MASK                      (0x1000000U)
+#define SIM_SCGC6_FTM0_SHIFT                     (24U)
+#define SIM_SCGC6_FTM0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)
+#define SIM_SCGC6_FTM1_MASK                      (0x2000000U)
+#define SIM_SCGC6_FTM1_SHIFT                     (25U)
+#define SIM_SCGC6_FTM1(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK)
+#define SIM_SCGC6_FTM2_MASK                      (0x4000000U)
+#define SIM_SCGC6_FTM2_SHIFT                     (26U)
+#define SIM_SCGC6_FTM2(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK)
+#define SIM_SCGC6_ADC0_MASK                      (0x8000000U)
+#define SIM_SCGC6_ADC0_SHIFT                     (27U)
+#define SIM_SCGC6_ADC0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
+#define SIM_SCGC6_RTC_MASK                       (0x20000000U)
+#define SIM_SCGC6_RTC_SHIFT                      (29U)
+#define SIM_SCGC6_RTC(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
+#define SIM_SCGC6_DAC0_MASK                      (0x80000000U)
+#define SIM_SCGC6_DAC0_SHIFT                     (31U)
+#define SIM_SCGC6_DAC0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)
+
+/*! @name SCGC7 - System Clock Gating Control Register 7 */
+#define SIM_SCGC7_FLEXBUS_MASK                   (0x1U)
+#define SIM_SCGC7_FLEXBUS_SHIFT                  (0U)
+#define SIM_SCGC7_FLEXBUS(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_FLEXBUS_SHIFT)) & SIM_SCGC7_FLEXBUS_MASK)
+#define SIM_SCGC7_DMA_MASK                       (0x2U)
+#define SIM_SCGC7_DMA_SHIFT                      (1U)
+#define SIM_SCGC7_DMA(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
+#define SIM_SCGC7_MPU_MASK                       (0x4U)
+#define SIM_SCGC7_MPU_SHIFT                      (2U)
+#define SIM_SCGC7_MPU(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_MPU_SHIFT)) & SIM_SCGC7_MPU_MASK)
+#define SIM_SCGC7_SDRAMC_MASK                    (0x8U)
+#define SIM_SCGC7_SDRAMC_SHIFT                   (3U)
+#define SIM_SCGC7_SDRAMC(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_SDRAMC_SHIFT)) & SIM_SCGC7_SDRAMC_MASK)
+
+/*! @name CLKDIV1 - System Clock Divider Register 1 */
+#define SIM_CLKDIV1_OUTDIV4_MASK                 (0xF0000U)
+#define SIM_CLKDIV1_OUTDIV4_SHIFT                (16U)
+#define SIM_CLKDIV1_OUTDIV4(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
+#define SIM_CLKDIV1_OUTDIV3_MASK                 (0xF00000U)
+#define SIM_CLKDIV1_OUTDIV3_SHIFT                (20U)
+#define SIM_CLKDIV1_OUTDIV3(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV3_SHIFT)) & SIM_CLKDIV1_OUTDIV3_MASK)
+#define SIM_CLKDIV1_OUTDIV2_MASK                 (0xF000000U)
+#define SIM_CLKDIV1_OUTDIV2_SHIFT                (24U)
+#define SIM_CLKDIV1_OUTDIV2(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)
+#define SIM_CLKDIV1_OUTDIV1_MASK                 (0xF0000000U)
+#define SIM_CLKDIV1_OUTDIV1_SHIFT                (28U)
+#define SIM_CLKDIV1_OUTDIV1(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
+
+/*! @name CLKDIV2 - System Clock Divider Register 2 */
+#define SIM_CLKDIV2_USBFRAC_MASK                 (0x1U)
+#define SIM_CLKDIV2_USBFRAC_SHIFT                (0U)
+#define SIM_CLKDIV2_USBFRAC_SET(x)               (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBFRAC_SHIFT)) & SIM_CLKDIV2_USBFRAC_MASK)
+#define SIM_CLKDIV2_USBFRAC                      SIM_CLKDIV2_USBFRAC_SET(1)
+#define SIM_CLKDIV2_USBDIV_MASK                  (0xEU)
+#define SIM_CLKDIV2_USBDIV_SHIFT                 (1U)
+#define SIM_CLKDIV2_USBDIV(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK)
+
+/*! @name FCFG1 - Flash Configuration Register 1 */
+#define SIM_FCFG1_FLASHDIS_MASK                  (0x1U)
+#define SIM_FCFG1_FLASHDIS_SHIFT                 (0U)
+#define SIM_FCFG1_FLASHDIS(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
+#define SIM_FCFG1_FLASHDOZE_MASK                 (0x2U)
+#define SIM_FCFG1_FLASHDOZE_SHIFT                (1U)
+#define SIM_FCFG1_FLASHDOZE(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
+#define SIM_FCFG1_DEPART_MASK                    (0xF00U)
+#define SIM_FCFG1_DEPART_SHIFT                   (8U)
+#define SIM_FCFG1_DEPART(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_DEPART_SHIFT)) & SIM_FCFG1_DEPART_MASK)
+#define SIM_FCFG1_EESIZE_MASK                    (0xF0000U)
+#define SIM_FCFG1_EESIZE_SHIFT                   (16U)
+#define SIM_FCFG1_EESIZE(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EESIZE_SHIFT)) & SIM_FCFG1_EESIZE_MASK)
+#define SIM_FCFG1_PFSIZE_MASK                    (0xF000000U)
+#define SIM_FCFG1_PFSIZE_SHIFT                   (24U)
+#define SIM_FCFG1_PFSIZE(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
+#define SIM_FCFG1_NVMSIZE_MASK                   (0xF0000000U)
+#define SIM_FCFG1_NVMSIZE_SHIFT                  (28U)
+#define SIM_FCFG1_NVMSIZE(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_NVMSIZE_SHIFT)) & SIM_FCFG1_NVMSIZE_MASK)
+
+/*! @name FCFG2 - Flash Configuration Register 2 */
+#define SIM_FCFG2_MAXADDR1_MASK                  (0x7F0000U)
+#define SIM_FCFG2_MAXADDR1_SHIFT                 (16U)
+#define SIM_FCFG2_MAXADDR1(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
+#define SIM_FCFG2_PFLSH_MASK                     (0x800000U)
+#define SIM_FCFG2_PFLSH_SHIFT                    (23U)
+#define SIM_FCFG2_PFLSH(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_PFLSH_SHIFT)) & SIM_FCFG2_PFLSH_MASK)
+#define SIM_FCFG2_MAXADDR0_MASK                  (0x7F000000U)
+#define SIM_FCFG2_MAXADDR0_SHIFT                 (24U)
+#define SIM_FCFG2_MAXADDR0(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
+#define SIM_FCFG2_SWAPPFLSH_MASK                 (0x80000000U)
+#define SIM_FCFG2_SWAPPFLSH_SHIFT                (31U)
+#define SIM_FCFG2_SWAPPFLSH(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_SWAPPFLSH_SHIFT)) & SIM_FCFG2_SWAPPFLSH_MASK)
+
+/*! @name UIDH - Unique Identification Register High */
+#define SIM_UIDH_UID_MASK                        (0xFFFFFFFFU)
+#define SIM_UIDH_UID_SHIFT                       (0U)
+#define SIM_UIDH_UID(x)                          (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK)
+
+/*! @name UIDMH - Unique Identification Register Mid-High */
+#define SIM_UIDMH_UID_MASK                       (0xFFFFFFFFU)
+#define SIM_UIDMH_UID_SHIFT                      (0U)
+#define SIM_UIDMH_UID(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
+
+/*! @name UIDML - Unique Identification Register Mid Low */
+#define SIM_UIDML_UID_MASK                       (0xFFFFFFFFU)
+#define SIM_UIDML_UID_SHIFT                      (0U)
+#define SIM_UIDML_UID(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
+
+/*! @name UIDL - Unique Identification Register Low */
+#define SIM_UIDL_UID_MASK                        (0xFFFFFFFFU)
+#define SIM_UIDL_UID_SHIFT                       (0U)
+#define SIM_UIDL_UID(x)                          (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
+
+/*! @name CLKDIV3 - System Clock Divider Register 3 */
+#define SIM_CLKDIV3_PLLFLLFRAC_MASK              (0x1U)
+#define SIM_CLKDIV3_PLLFLLFRAC_SHIFT             (0U)
+#define SIM_CLKDIV3_PLLFLLFRAC(x)                (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV3_PLLFLLFRAC_SHIFT)) & SIM_CLKDIV3_PLLFLLFRAC_MASK)
+#define SIM_CLKDIV3_PLLFLLDIV_MASK               (0xEU)
+#define SIM_CLKDIV3_PLLFLLDIV_SHIFT              (1U)
+#define SIM_CLKDIV3_PLLFLLDIV(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV3_PLLFLLDIV_SHIFT)) & SIM_CLKDIV3_PLLFLLDIV_MASK)
+
+/*! @name CLKDIV4 - System Clock Divider Register 4 */
+#define SIM_CLKDIV4_TRACEFRAC_MASK               (0x1U)
+#define SIM_CLKDIV4_TRACEFRAC_SHIFT              (0U)
+#define SIM_CLKDIV4_TRACEFRAC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV4_TRACEFRAC_SHIFT)) & SIM_CLKDIV4_TRACEFRAC_MASK)
+#define SIM_CLKDIV4_TRACEDIV_MASK                (0xEU)
+#define SIM_CLKDIV4_TRACEDIV_SHIFT               (1U)
+#define SIM_CLKDIV4_TRACEDIV(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV4_TRACEDIV_SHIFT)) & SIM_CLKDIV4_TRACEDIV_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group SIM_Register_Masks */
+
+
+/* SIM - Peripheral instance base addresses */
+/** Peripheral SIM base address */
+#define SIM_BASE                                 (0x40047000u)
+/** Peripheral SIM base pointer */
+#define SIM                                      ((SIM_Type *)SIM_BASE)
+/** Array initializer of SIM peripheral base addresses */
+#define SIM_BASE_ADDRS                           { SIM_BASE }
+/** Array initializer of SIM peripheral base pointers */
+#define SIM_BASE_PTRS                            { SIM }
+
+/*!
+ * @}
+ */ /* end of group SIM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SMC Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
+ * @{
+ */
+
+/** SMC - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t PMPROT;                             /**< Power Mode Protection register, offset: 0x0 */
+  __IO uint8_t PMCTRL;                             /**< Power Mode Control register, offset: 0x1 */
+  __IO uint8_t STOPCTRL;                           /**< Stop Control Register, offset: 0x2 */
+  __I  uint8_t PMSTAT;                             /**< Power Mode Status register, offset: 0x3 */
+} SMC_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SMC Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMC_Register_Masks SMC Register Masks
+ * @{
+ */
+
+/*! @name PMPROT - Power Mode Protection register */
+#define SMC_PMPROT_AVLLS_MASK                    (0x2U)
+#define SMC_PMPROT_AVLLS_SHIFT                   (1U)
+#define SMC_PMPROT_AVLLS(x)                      (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
+#define SMC_PMPROT_ALLS_MASK                     (0x8U)
+#define SMC_PMPROT_ALLS_SHIFT                    (3U)
+#define SMC_PMPROT_ALLS(x)                       (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
+#define SMC_PMPROT_AVLP_MASK                     (0x20U)
+#define SMC_PMPROT_AVLP_SHIFT                    (5U)
+#define SMC_PMPROT_AVLP(x)                       (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
+#define SMC_PMPROT_AHSRUN_MASK                   (0x80U)
+#define SMC_PMPROT_AHSRUN_SHIFT                  (7U)
+#define SMC_PMPROT_AHSRUN(x)                     (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AHSRUN_SHIFT)) & SMC_PMPROT_AHSRUN_MASK)
+
+/*! @name PMCTRL - Power Mode Control register */
+#define SMC_PMCTRL_STOPM_MASK                    (0x7U)
+#define SMC_PMCTRL_STOPM_SHIFT                   (0U)
+#define SMC_PMCTRL_STOPM(x)                      (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPA_MASK                    (0x8U)
+#define SMC_PMCTRL_STOPA_SHIFT                   (3U)
+#define SMC_PMCTRL_STOPA(x)                      (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
+#define SMC_PMCTRL_RUNM_MASK                     (0x60U)
+#define SMC_PMCTRL_RUNM_SHIFT                    (5U)
+#define SMC_PMCTRL_RUNM(x)                       (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
+
+/*! @name STOPCTRL - Stop Control Register */
+#define SMC_STOPCTRL_LLSM_MASK                   (0x7U)
+#define SMC_STOPCTRL_LLSM_SHIFT                  (0U)
+#define SMC_STOPCTRL_LLSM(x)                     (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_LLSM_SHIFT)) & SMC_STOPCTRL_LLSM_MASK)
+#define SMC_STOPCTRL_RAM2PO_MASK                 (0x10U)
+#define SMC_STOPCTRL_RAM2PO_SHIFT                (4U)
+#define SMC_STOPCTRL_RAM2PO(x)                   (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_RAM2PO_SHIFT)) & SMC_STOPCTRL_RAM2PO_MASK)
+#define SMC_STOPCTRL_PORPO_MASK                  (0x20U)
+#define SMC_STOPCTRL_PORPO_SHIFT                 (5U)
+#define SMC_STOPCTRL_PORPO(x)                    (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK)
+#define SMC_STOPCTRL_PSTOPO_MASK                 (0xC0U)
+#define SMC_STOPCTRL_PSTOPO_SHIFT                (6U)
+#define SMC_STOPCTRL_PSTOPO(x)                   (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK)
+
+/*! @name PMSTAT - Power Mode Status register */
+#define SMC_PMSTAT_PMSTAT_MASK                   (0xFFU)
+#define SMC_PMSTAT_PMSTAT_SHIFT                  (0U)
+#define SMC_PMSTAT_PMSTAT(x)                     (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group SMC_Register_Masks */
+
+
+/* SMC - Peripheral instance base addresses */
+/** Peripheral SMC base address */
+#define SMC_BASE                                 (0x4007E000u)
+/** Peripheral SMC base pointer */
+#define SMC                                      ((SMC_Type *)SMC_BASE)
+/** Array initializer of SMC peripheral base addresses */
+#define SMC_BASE_ADDRS                           { SMC_BASE }
+/** Array initializer of SMC peripheral base pointers */
+#define SMC_BASE_PTRS                            { SMC }
+
+/*!
+ * @}
+ */ /* end of group SMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SPI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t MCR;                               /**< Module Configuration Register, offset: 0x0 */
+       uint8_t RESERVED_0[4];
+  __IO uint32_t TCR;                               /**< Transfer Count Register, offset: 0x8 */
+  union {                                          /* offset: 0xC */
+    __IO uint32_t CTAR[2];                           /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
+    __IO uint32_t CTAR_SLAVE[1];                     /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
+  };
+       uint8_t RESERVED_1[24];
+  __IO uint32_t SR;                                /**< Status Register, offset: 0x2C */
+  __IO uint32_t RSER;                              /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
+  union {                                          /* offset: 0x34 */
+    __IO uint32_t PUSHR;                             /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
+    __IO uint32_t PUSHR_SLAVE;                       /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
+  };
+  __I  uint32_t POPR;                              /**< POP RX FIFO Register, offset: 0x38 */
+  __I  uint32_t TXFR0;                             /**< Transmit FIFO Registers, offset: 0x3C */
+  __I  uint32_t TXFR1;                             /**< Transmit FIFO Registers, offset: 0x40 */
+  __I  uint32_t TXFR2;                             /**< Transmit FIFO Registers, offset: 0x44 */
+  __I  uint32_t TXFR3;                             /**< Transmit FIFO Registers, offset: 0x48 */
+       uint8_t RESERVED_2[48];
+  __I  uint32_t RXFR0;                             /**< Receive FIFO Registers, offset: 0x7C */
+  __I  uint32_t RXFR1;                             /**< Receive FIFO Registers, offset: 0x80 */
+  __I  uint32_t RXFR2;                             /**< Receive FIFO Registers, offset: 0x84 */
+  __I  uint32_t RXFR3;                             /**< Receive FIFO Registers, offset: 0x88 */
+} SPI_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SPI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/*! @name MCR - Module Configuration Register */
+#define SPI_MCR_HALT_MASK                        (0x1U)
+#define SPI_MCR_HALT_SHIFT                       (0U)
+#define SPI_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
+#define SPI_MCR_SMPL_PT_MASK                     (0x300U)
+#define SPI_MCR_SMPL_PT_SHIFT                    (8U)
+#define SPI_MCR_SMPL_PT(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
+#define SPI_MCR_CLR_RXF_MASK                     (0x400U)
+#define SPI_MCR_CLR_RXF_SHIFT                    (10U)
+#define SPI_MCR_CLR_RXF(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
+#define SPI_MCR_CLR_TXF_MASK                     (0x800U)
+#define SPI_MCR_CLR_TXF_SHIFT                    (11U)
+#define SPI_MCR_CLR_TXF(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
+#define SPI_MCR_DIS_RXF_MASK                     (0x1000U)
+#define SPI_MCR_DIS_RXF_SHIFT                    (12U)
+#define SPI_MCR_DIS_RXF(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
+#define SPI_MCR_DIS_TXF_MASK                     (0x2000U)
+#define SPI_MCR_DIS_TXF_SHIFT                    (13U)
+#define SPI_MCR_DIS_TXF(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
+#define SPI_MCR_MDIS_MASK                        (0x4000U)
+#define SPI_MCR_MDIS_SHIFT                       (14U)
+#define SPI_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
+#define SPI_MCR_DOZE_MASK                        (0x8000U)
+#define SPI_MCR_DOZE_SHIFT                       (15U)
+#define SPI_MCR_DOZE(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
+#define SPI_MCR_PCSIS_MASK                       (0x3F0000U)
+#define SPI_MCR_PCSIS_SHIFT                      (16U)
+#define SPI_MCR_PCSIS(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
+#define SPI_MCR_ROOE_MASK                        (0x1000000U)
+#define SPI_MCR_ROOE_SHIFT                       (24U)
+#define SPI_MCR_ROOE(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
+#define SPI_MCR_PCSSE_MASK                       (0x2000000U)
+#define SPI_MCR_PCSSE_SHIFT                      (25U)
+#define SPI_MCR_PCSSE(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)
+#define SPI_MCR_MTFE_MASK                        (0x4000000U)
+#define SPI_MCR_MTFE_SHIFT                       (26U)
+#define SPI_MCR_MTFE(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
+#define SPI_MCR_FRZ_MASK                         (0x8000000U)
+#define SPI_MCR_FRZ_SHIFT                        (27U)
+#define SPI_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
+#define SPI_MCR_DCONF_MASK                       (0x30000000U)
+#define SPI_MCR_DCONF_SHIFT                      (28U)
+#define SPI_MCR_DCONF(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
+#define SPI_MCR_CONT_SCKE_MASK                   (0x40000000U)
+#define SPI_MCR_CONT_SCKE_SHIFT                  (30U)
+#define SPI_MCR_CONT_SCKE(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
+#define SPI_MCR_MSTR_MASK                        (0x80000000U)
+#define SPI_MCR_MSTR_SHIFT                       (31U)
+#define SPI_MCR_MSTR(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)
+
+/*! @name TCR - Transfer Count Register */
+#define SPI_TCR_SPI_TCNT_MASK                    (0xFFFF0000U)
+#define SPI_TCR_SPI_TCNT_SHIFT                   (16U)
+#define SPI_TCR_SPI_TCNT(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK)
+
+/*! @name CTAR - Clock and Transfer Attributes Register (In Master Mode) */
+#define SPI_CTAR_BR_MASK                         (0xFU)
+#define SPI_CTAR_BR_SHIFT                        (0U)
+#define SPI_CTAR_BR(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK)
+#define SPI_CTAR_DT_MASK                         (0xF0U)
+#define SPI_CTAR_DT_SHIFT                        (4U)
+#define SPI_CTAR_DT(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK)
+#define SPI_CTAR_ASC_MASK                        (0xF00U)
+#define SPI_CTAR_ASC_SHIFT                       (8U)
+#define SPI_CTAR_ASC(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK)
+#define SPI_CTAR_CSSCK_MASK                      (0xF000U)
+#define SPI_CTAR_CSSCK_SHIFT                     (12U)
+#define SPI_CTAR_CSSCK(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK)
+#define SPI_CTAR_PBR_MASK                        (0x30000U)
+#define SPI_CTAR_PBR_SHIFT                       (16U)
+#define SPI_CTAR_PBR(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)
+#define SPI_CTAR_PDT_MASK                        (0xC0000U)
+#define SPI_CTAR_PDT_SHIFT                       (18U)
+#define SPI_CTAR_PDT(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)
+#define SPI_CTAR_PASC_MASK                       (0x300000U)
+#define SPI_CTAR_PASC_SHIFT                      (20U)
+#define SPI_CTAR_PASC(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)
+#define SPI_CTAR_PCSSCK_MASK                     (0xC00000U)
+#define SPI_CTAR_PCSSCK_SHIFT                    (22U)
+#define SPI_CTAR_PCSSCK(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
+#define SPI_CTAR_LSBFE_MASK                      (0x1000000U)
+#define SPI_CTAR_LSBFE_SHIFT                     (24U)
+#define SPI_CTAR_LSBFE(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)
+#define SPI_CTAR_CPHA_MASK                       (0x2000000U)
+#define SPI_CTAR_CPHA_SHIFT                      (25U)
+#define SPI_CTAR_CPHA(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)
+#define SPI_CTAR_CPOL_MASK                       (0x4000000U)
+#define SPI_CTAR_CPOL_SHIFT                      (26U)
+#define SPI_CTAR_CPOL(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)
+#define SPI_CTAR_FMSZ_MASK                       (0x78000000U)
+#define SPI_CTAR_FMSZ_SHIFT                      (27U)
+#define SPI_CTAR_FMSZ(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK)
+#define SPI_CTAR_DBR_MASK                        (0x80000000U)
+#define SPI_CTAR_DBR_SHIFT                       (31U)
+#define SPI_CTAR_DBR(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)
+
+/* The count of SPI_CTAR */
+#define SPI_CTAR_COUNT                           (2U)
+
+/*! @name CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) */
+#define SPI_CTAR_SLAVE_CPHA_MASK                 (0x2000000U)
+#define SPI_CTAR_SLAVE_CPHA_SHIFT                (25U)
+#define SPI_CTAR_SLAVE_CPHA(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)
+#define SPI_CTAR_SLAVE_CPOL_MASK                 (0x4000000U)
+#define SPI_CTAR_SLAVE_CPOL_SHIFT                (26U)
+#define SPI_CTAR_SLAVE_CPOL(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)
+#define SPI_CTAR_SLAVE_FMSZ_MASK                 (0x78000000U)
+#define SPI_CTAR_SLAVE_FMSZ_SHIFT                (27U)
+#define SPI_CTAR_SLAVE_FMSZ(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK)
+
+/* The count of SPI_CTAR_SLAVE */
+#define SPI_CTAR_SLAVE_COUNT                     (1U)
+
+/*! @name SR - Status Register */
+#define SPI_SR_POPNXTPTR_MASK                    (0xFU)
+#define SPI_SR_POPNXTPTR_SHIFT                   (0U)
+#define SPI_SR_POPNXTPTR(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK)
+#define SPI_SR_RXCTR_MASK                        (0xF0U)
+#define SPI_SR_RXCTR_SHIFT                       (4U)
+#define SPI_SR_RXCTR(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK)
+#define SPI_SR_TXNXTPTR_MASK                     (0xF00U)
+#define SPI_SR_TXNXTPTR_SHIFT                    (8U)
+#define SPI_SR_TXNXTPTR(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK)
+#define SPI_SR_TXCTR_MASK                        (0xF000U)
+#define SPI_SR_TXCTR_SHIFT                       (12U)
+#define SPI_SR_TXCTR(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK)
+#define SPI_SR_RFDF_MASK                         (0x20000U)
+#define SPI_SR_RFDF_SHIFT                        (17U)
+#define SPI_SR_RFDF(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)
+#define SPI_SR_RFOF_MASK                         (0x80000U)
+#define SPI_SR_RFOF_SHIFT                        (19U)
+#define SPI_SR_RFOF(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)
+#define SPI_SR_TFFF_MASK                         (0x2000000U)
+#define SPI_SR_TFFF_SHIFT                        (25U)
+#define SPI_SR_TFFF(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
+#define SPI_SR_TFUF_MASK                         (0x8000000U)
+#define SPI_SR_TFUF_SHIFT                        (27U)
+#define SPI_SR_TFUF(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)
+#define SPI_SR_EOQF_MASK                         (0x10000000U)
+#define SPI_SR_EOQF_SHIFT                        (28U)
+#define SPI_SR_EOQF(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)
+#define SPI_SR_TXRXS_MASK                        (0x40000000U)
+#define SPI_SR_TXRXS_SHIFT                       (30U)
+#define SPI_SR_TXRXS(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)
+#define SPI_SR_TCF_MASK                          (0x80000000U)
+#define SPI_SR_TCF_SHIFT                         (31U)
+#define SPI_SR_TCF(x)                            (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)
+
+/*! @name RSER - DMA/Interrupt Request Select and Enable Register */
+#define SPI_RSER_RFDF_DIRS_MASK                  (0x10000U)
+#define SPI_RSER_RFDF_DIRS_SHIFT                 (16U)
+#define SPI_RSER_RFDF_DIRS(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)
+#define SPI_RSER_RFDF_RE_MASK                    (0x20000U)
+#define SPI_RSER_RFDF_RE_SHIFT                   (17U)
+#define SPI_RSER_RFDF_RE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)
+#define SPI_RSER_RFOF_RE_MASK                    (0x80000U)
+#define SPI_RSER_RFOF_RE_SHIFT                   (19U)
+#define SPI_RSER_RFOF_RE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)
+#define SPI_RSER_TFFF_DIRS_MASK                  (0x1000000U)
+#define SPI_RSER_TFFF_DIRS_SHIFT                 (24U)
+#define SPI_RSER_TFFF_DIRS(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)
+#define SPI_RSER_TFFF_RE_MASK                    (0x2000000U)
+#define SPI_RSER_TFFF_RE_SHIFT                   (25U)
+#define SPI_RSER_TFFF_RE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
+#define SPI_RSER_TFUF_RE_MASK                    (0x8000000U)
+#define SPI_RSER_TFUF_RE_SHIFT                   (27U)
+#define SPI_RSER_TFUF_RE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)
+#define SPI_RSER_EOQF_RE_MASK                    (0x10000000U)
+#define SPI_RSER_EOQF_RE_SHIFT                   (28U)
+#define SPI_RSER_EOQF_RE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)
+#define SPI_RSER_TCF_RE_MASK                     (0x80000000U)
+#define SPI_RSER_TCF_RE_SHIFT                    (31U)
+#define SPI_RSER_TCF_RE(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)
+
+/*! @name PUSHR - PUSH TX FIFO Register In Master Mode */
+#define SPI_PUSHR_TXDATA_MASK                    (0xFFFFU)
+#define SPI_PUSHR_TXDATA_SHIFT                   (0U)
+#define SPI_PUSHR_TXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK)
+#define SPI_PUSHR_PCS_MASK                       (0x3F0000U)
+#define SPI_PUSHR_PCS_SHIFT                      (16U)
+#define SPI_PUSHR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)
+#define SPI_PUSHR_CTCNT_MASK                     (0x4000000U)
+#define SPI_PUSHR_CTCNT_SHIFT                    (26U)
+#define SPI_PUSHR_CTCNT(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)
+#define SPI_PUSHR_EOQ_MASK                       (0x8000000U)
+#define SPI_PUSHR_EOQ_SHIFT                      (27U)
+#define SPI_PUSHR_EOQ(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)
+#define SPI_PUSHR_CTAS_MASK                      (0x70000000U)
+#define SPI_PUSHR_CTAS_SHIFT                     (28U)
+#define SPI_PUSHR_CTAS(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)
+#define SPI_PUSHR_CONT_MASK                      (0x80000000U)
+#define SPI_PUSHR_CONT_SHIFT                     (31U)
+#define SPI_PUSHR_CONT(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)
+
+/*! @name PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode */
+#define SPI_PUSHR_SLAVE_TXDATA_MASK              (0xFFFFFFFFU)
+#define SPI_PUSHR_SLAVE_TXDATA_SHIFT             (0U)
+#define SPI_PUSHR_SLAVE_TXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK)
+
+/*! @name POPR - POP RX FIFO Register */
+#define SPI_POPR_RXDATA_MASK                     (0xFFFFFFFFU)
+#define SPI_POPR_RXDATA_SHIFT                    (0U)
+#define SPI_POPR_RXDATA(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK)
+
+/*! @name TXFR0 - Transmit FIFO Registers */
+#define SPI_TXFR0_TXDATA_MASK                    (0xFFFFU)
+#define SPI_TXFR0_TXDATA_SHIFT                   (0U)
+#define SPI_TXFR0_TXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK)
+#define SPI_TXFR0_TXCMD_TXDATA_MASK              (0xFFFF0000U)
+#define SPI_TXFR0_TXCMD_TXDATA_SHIFT             (16U)
+#define SPI_TXFR0_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK)
+
+/*! @name TXFR1 - Transmit FIFO Registers */
+#define SPI_TXFR1_TXDATA_MASK                    (0xFFFFU)
+#define SPI_TXFR1_TXDATA_SHIFT                   (0U)
+#define SPI_TXFR1_TXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK)
+#define SPI_TXFR1_TXCMD_TXDATA_MASK              (0xFFFF0000U)
+#define SPI_TXFR1_TXCMD_TXDATA_SHIFT             (16U)
+#define SPI_TXFR1_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK)
+
+/*! @name TXFR2 - Transmit FIFO Registers */
+#define SPI_TXFR2_TXDATA_MASK                    (0xFFFFU)
+#define SPI_TXFR2_TXDATA_SHIFT                   (0U)
+#define SPI_TXFR2_TXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK)
+#define SPI_TXFR2_TXCMD_TXDATA_MASK              (0xFFFF0000U)
+#define SPI_TXFR2_TXCMD_TXDATA_SHIFT             (16U)
+#define SPI_TXFR2_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK)
+
+/*! @name TXFR3 - Transmit FIFO Registers */
+#define SPI_TXFR3_TXDATA_MASK                    (0xFFFFU)
+#define SPI_TXFR3_TXDATA_SHIFT                   (0U)
+#define SPI_TXFR3_TXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK)
+#define SPI_TXFR3_TXCMD_TXDATA_MASK              (0xFFFF0000U)
+#define SPI_TXFR3_TXCMD_TXDATA_SHIFT             (16U)
+#define SPI_TXFR3_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK)
+
+/*! @name RXFR0 - Receive FIFO Registers */
+#define SPI_RXFR0_RXDATA_MASK                    (0xFFFFFFFFU)
+#define SPI_RXFR0_RXDATA_SHIFT                   (0U)
+#define SPI_RXFR0_RXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK)
+
+/*! @name RXFR1 - Receive FIFO Registers */
+#define SPI_RXFR1_RXDATA_MASK                    (0xFFFFFFFFU)
+#define SPI_RXFR1_RXDATA_SHIFT                   (0U)
+#define SPI_RXFR1_RXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK)
+
+/*! @name RXFR2 - Receive FIFO Registers */
+#define SPI_RXFR2_RXDATA_MASK                    (0xFFFFFFFFU)
+#define SPI_RXFR2_RXDATA_SHIFT                   (0U)
+#define SPI_RXFR2_RXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK)
+
+/*! @name RXFR3 - Receive FIFO Registers */
+#define SPI_RXFR3_RXDATA_MASK                    (0xFFFFFFFFU)
+#define SPI_RXFR3_RXDATA_SHIFT                   (0U)
+#define SPI_RXFR3_RXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE                                (0x4002C000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0                                     ((SPI_Type *)SPI0_BASE)
+/** Peripheral SPI1 base address */
+#define SPI1_BASE                                (0x4002D000u)
+/** Peripheral SPI1 base pointer */
+#define SPI1                                     ((SPI_Type *)SPI1_BASE)
+/** Peripheral SPI2 base address */
+#define SPI2_BASE                                (0x400AC000u)
+/** Peripheral SPI2 base pointer */
+#define SPI2                                     ((SPI_Type *)SPI2_BASE)
+/** Array initializer of SPI peripheral base addresses */
+#define SPI_BASE_ADDRS                           { SPI0_BASE, SPI1_BASE, SPI2_BASE }
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASE_PTRS                            { SPI0, SPI1, SPI2 }
+/** Interrupt vectors for the SPI peripheral type */
+#define SPI_IRQS                                 { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- SYSMPU Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSMPU_Peripheral_Access_Layer SYSMPU Peripheral Access Layer
+ * @{
+ */
+
+/** SYSMPU - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CESR;                              /**< Control/Error Status Register, offset: 0x0 */
+       uint8_t RESERVED_0[12];
+  struct {                                         /* offset: 0x10, array step: 0x8 */
+    __I  uint32_t EAR;                               /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
+    __I  uint32_t EDR;                               /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
+  } SP[5];
+       uint8_t RESERVED_1[968];
+  __IO uint32_t WORD[12][4];                       /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
+       uint8_t RESERVED_2[832];
+  __IO uint32_t RGDAAC[12];                        /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
+} SYSMPU_Type;
+
+/* ----------------------------------------------------------------------------
+   -- SYSMPU Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSMPU_Register_Masks SYSMPU Register Masks
+ * @{
+ */
+
+/*! @name CESR - Control/Error Status Register */
+#define SYSMPU_CESR_VLD_MASK                     (0x1U)
+#define SYSMPU_CESR_VLD_SHIFT                    (0U)
+#define SYSMPU_CESR_VLD(x)                       (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_VLD_SHIFT)) & SYSMPU_CESR_VLD_MASK)
+#define SYSMPU_CESR_NRGD_MASK                    (0xF00U)
+#define SYSMPU_CESR_NRGD_SHIFT                   (8U)
+#define SYSMPU_CESR_NRGD(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NRGD_SHIFT)) & SYSMPU_CESR_NRGD_MASK)
+#define SYSMPU_CESR_NSP_MASK                     (0xF000U)
+#define SYSMPU_CESR_NSP_SHIFT                    (12U)
+#define SYSMPU_CESR_NSP(x)                       (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NSP_SHIFT)) & SYSMPU_CESR_NSP_MASK)
+#define SYSMPU_CESR_HRL_MASK                     (0xF0000U)
+#define SYSMPU_CESR_HRL_SHIFT                    (16U)
+#define SYSMPU_CESR_HRL(x)                       (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_HRL_SHIFT)) & SYSMPU_CESR_HRL_MASK)
+#define SYSMPU_CESR_SPERR_MASK                   (0xF8000000U)
+#define SYSMPU_CESR_SPERR_SHIFT                  (27U)
+#define SYSMPU_CESR_SPERR(x)                     (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_SPERR_SHIFT)) & SYSMPU_CESR_SPERR_MASK)
+
+/*! @name EAR - Error Address Register, slave port n */
+#define SYSMPU_EAR_EADDR_MASK                    (0xFFFFFFFFU)
+#define SYSMPU_EAR_EADDR_SHIFT                   (0U)
+#define SYSMPU_EAR_EADDR(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_EAR_EADDR_SHIFT)) & SYSMPU_EAR_EADDR_MASK)
+
+/* The count of SYSMPU_EAR */
+#define SYSMPU_EAR_COUNT                         (5U)
+
+/*! @name EDR - Error Detail Register, slave port n */
+#define SYSMPU_EDR_ERW_MASK                      (0x1U)
+#define SYSMPU_EDR_ERW_SHIFT                     (0U)
+#define SYSMPU_EDR_ERW(x)                        (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_ERW_SHIFT)) & SYSMPU_EDR_ERW_MASK)
+#define SYSMPU_EDR_EATTR_MASK                    (0xEU)
+#define SYSMPU_EDR_EATTR_SHIFT                   (1U)
+#define SYSMPU_EDR_EATTR(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EATTR_SHIFT)) & SYSMPU_EDR_EATTR_MASK)
+#define SYSMPU_EDR_EMN_MASK                      (0xF0U)
+#define SYSMPU_EDR_EMN_SHIFT                     (4U)
+#define SYSMPU_EDR_EMN(x)                        (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EMN_SHIFT)) & SYSMPU_EDR_EMN_MASK)
+#define SYSMPU_EDR_EPID_MASK                     (0xFF00U)
+#define SYSMPU_EDR_EPID_SHIFT                    (8U)
+#define SYSMPU_EDR_EPID(x)                       (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EPID_SHIFT)) & SYSMPU_EDR_EPID_MASK)
+#define SYSMPU_EDR_EACD_MASK                     (0xFFFF0000U)
+#define SYSMPU_EDR_EACD_SHIFT                    (16U)
+#define SYSMPU_EDR_EACD(x)                       (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EACD_SHIFT)) & SYSMPU_EDR_EACD_MASK)
+
+/* The count of SYSMPU_EDR */
+#define SYSMPU_EDR_COUNT                         (5U)
+
+/*! @name WORD - Region Descriptor n, Word 0..Region Descriptor n, Word 3 */
+#define SYSMPU_WORD_VLD_MASK                     (0x1U)
+#define SYSMPU_WORD_VLD_SHIFT                    (0U)
+#define SYSMPU_WORD_VLD(x)                       (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_VLD_SHIFT)) & SYSMPU_WORD_VLD_MASK)
+#define SYSMPU_WORD_M0UM_MASK                    (0x7U)
+#define SYSMPU_WORD_M0UM_SHIFT                   (0U)
+#define SYSMPU_WORD_M0UM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0UM_SHIFT)) & SYSMPU_WORD_M0UM_MASK)
+#define SYSMPU_WORD_M0SM_MASK                    (0x18U)
+#define SYSMPU_WORD_M0SM_SHIFT                   (3U)
+#define SYSMPU_WORD_M0SM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0SM_SHIFT)) & SYSMPU_WORD_M0SM_MASK)
+#define SYSMPU_WORD_M0PE_MASK                    (0x20U)
+#define SYSMPU_WORD_M0PE_SHIFT                   (5U)
+#define SYSMPU_WORD_M0PE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0PE_SHIFT)) & SYSMPU_WORD_M0PE_MASK)
+#define SYSMPU_WORD_ENDADDR_MASK                 (0xFFFFFFE0U)
+#define SYSMPU_WORD_ENDADDR_SHIFT                (5U)
+#define SYSMPU_WORD_ENDADDR(x)                   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_ENDADDR_SHIFT)) & SYSMPU_WORD_ENDADDR_MASK)
+#define SYSMPU_WORD_SRTADDR_MASK                 (0xFFFFFFE0U)
+#define SYSMPU_WORD_SRTADDR_SHIFT                (5U)
+#define SYSMPU_WORD_SRTADDR(x)                   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_SRTADDR_SHIFT)) & SYSMPU_WORD_SRTADDR_MASK)
+#define SYSMPU_WORD_M1UM_MASK                    (0x1C0U)
+#define SYSMPU_WORD_M1UM_SHIFT                   (6U)
+#define SYSMPU_WORD_M1UM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1UM_SHIFT)) & SYSMPU_WORD_M1UM_MASK)
+#define SYSMPU_WORD_M1SM_MASK                    (0x600U)
+#define SYSMPU_WORD_M1SM_SHIFT                   (9U)
+#define SYSMPU_WORD_M1SM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1SM_SHIFT)) & SYSMPU_WORD_M1SM_MASK)
+#define SYSMPU_WORD_M1PE_MASK                    (0x800U)
+#define SYSMPU_WORD_M1PE_SHIFT                   (11U)
+#define SYSMPU_WORD_M1PE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1PE_SHIFT)) & SYSMPU_WORD_M1PE_MASK)
+#define SYSMPU_WORD_M2UM_MASK                    (0x7000U)
+#define SYSMPU_WORD_M2UM_SHIFT                   (12U)
+#define SYSMPU_WORD_M2UM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2UM_SHIFT)) & SYSMPU_WORD_M2UM_MASK)
+#define SYSMPU_WORD_M2SM_MASK                    (0x18000U)
+#define SYSMPU_WORD_M2SM_SHIFT                   (15U)
+#define SYSMPU_WORD_M2SM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2SM_SHIFT)) & SYSMPU_WORD_M2SM_MASK)
+#define SYSMPU_WORD_PIDMASK_MASK                 (0xFF0000U)
+#define SYSMPU_WORD_PIDMASK_SHIFT                (16U)
+#define SYSMPU_WORD_PIDMASK(x)                   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PIDMASK_SHIFT)) & SYSMPU_WORD_PIDMASK_MASK)
+#define SYSMPU_WORD_M2PE_MASK                    (0x20000U)
+#define SYSMPU_WORD_M2PE_SHIFT                   (17U)
+#define SYSMPU_WORD_M2PE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2PE_SHIFT)) & SYSMPU_WORD_M2PE_MASK)
+#define SYSMPU_WORD_M3UM_MASK                    (0x1C0000U)
+#define SYSMPU_WORD_M3UM_SHIFT                   (18U)
+#define SYSMPU_WORD_M3UM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3UM_SHIFT)) & SYSMPU_WORD_M3UM_MASK)
+#define SYSMPU_WORD_M3SM_MASK                    (0x600000U)
+#define SYSMPU_WORD_M3SM_SHIFT                   (21U)
+#define SYSMPU_WORD_M3SM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3SM_SHIFT)) & SYSMPU_WORD_M3SM_MASK)
+#define SYSMPU_WORD_M3PE_MASK                    (0x800000U)
+#define SYSMPU_WORD_M3PE_SHIFT                   (23U)
+#define SYSMPU_WORD_M3PE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3PE_SHIFT)) & SYSMPU_WORD_M3PE_MASK)
+#define SYSMPU_WORD_PID_MASK                     (0xFF000000U)
+#define SYSMPU_WORD_PID_SHIFT                    (24U)
+#define SYSMPU_WORD_PID(x)                       (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PID_SHIFT)) & SYSMPU_WORD_PID_MASK)
+#define SYSMPU_WORD_M4WE_MASK                    (0x1000000U)
+#define SYSMPU_WORD_M4WE_SHIFT                   (24U)
+#define SYSMPU_WORD_M4WE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4WE_SHIFT)) & SYSMPU_WORD_M4WE_MASK)
+#define SYSMPU_WORD_M4RE_MASK                    (0x2000000U)
+#define SYSMPU_WORD_M4RE_SHIFT                   (25U)
+#define SYSMPU_WORD_M4RE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4RE_SHIFT)) & SYSMPU_WORD_M4RE_MASK)
+#define SYSMPU_WORD_M5WE_MASK                    (0x4000000U)
+#define SYSMPU_WORD_M5WE_SHIFT                   (26U)
+#define SYSMPU_WORD_M5WE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5WE_SHIFT)) & SYSMPU_WORD_M5WE_MASK)
+#define SYSMPU_WORD_M5RE_MASK                    (0x8000000U)
+#define SYSMPU_WORD_M5RE_SHIFT                   (27U)
+#define SYSMPU_WORD_M5RE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5RE_SHIFT)) & SYSMPU_WORD_M5RE_MASK)
+#define SYSMPU_WORD_M6WE_MASK                    (0x10000000U)
+#define SYSMPU_WORD_M6WE_SHIFT                   (28U)
+#define SYSMPU_WORD_M6WE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6WE_SHIFT)) & SYSMPU_WORD_M6WE_MASK)
+#define SYSMPU_WORD_M6RE_MASK                    (0x20000000U)
+#define SYSMPU_WORD_M6RE_SHIFT                   (29U)
+#define SYSMPU_WORD_M6RE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6RE_SHIFT)) & SYSMPU_WORD_M6RE_MASK)
+#define SYSMPU_WORD_M7WE_MASK                    (0x40000000U)
+#define SYSMPU_WORD_M7WE_SHIFT                   (30U)
+#define SYSMPU_WORD_M7WE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7WE_SHIFT)) & SYSMPU_WORD_M7WE_MASK)
+#define SYSMPU_WORD_M7RE_MASK                    (0x80000000U)
+#define SYSMPU_WORD_M7RE_SHIFT                   (31U)
+#define SYSMPU_WORD_M7RE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7RE_SHIFT)) & SYSMPU_WORD_M7RE_MASK)
+
+/* The count of SYSMPU_WORD */
+#define SYSMPU_WORD_COUNT                        (12U)
+
+/* The count of SYSMPU_WORD */
+#define SYSMPU_WORD_COUNT2                       (4U)
+
+/*! @name RGDAAC - Region Descriptor Alternate Access Control n */
+#define SYSMPU_RGDAAC_M0UM_MASK                  (0x7U)
+#define SYSMPU_RGDAAC_M0UM_SHIFT                 (0U)
+#define SYSMPU_RGDAAC_M0UM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0UM_SHIFT)) & SYSMPU_RGDAAC_M0UM_MASK)
+#define SYSMPU_RGDAAC_M0SM_MASK                  (0x18U)
+#define SYSMPU_RGDAAC_M0SM_SHIFT                 (3U)
+#define SYSMPU_RGDAAC_M0SM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0SM_SHIFT)) & SYSMPU_RGDAAC_M0SM_MASK)
+#define SYSMPU_RGDAAC_M0PE_MASK                  (0x20U)
+#define SYSMPU_RGDAAC_M0PE_SHIFT                 (5U)
+#define SYSMPU_RGDAAC_M0PE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0PE_SHIFT)) & SYSMPU_RGDAAC_M0PE_MASK)
+#define SYSMPU_RGDAAC_M1UM_MASK                  (0x1C0U)
+#define SYSMPU_RGDAAC_M1UM_SHIFT                 (6U)
+#define SYSMPU_RGDAAC_M1UM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1UM_SHIFT)) & SYSMPU_RGDAAC_M1UM_MASK)
+#define SYSMPU_RGDAAC_M1SM_MASK                  (0x600U)
+#define SYSMPU_RGDAAC_M1SM_SHIFT                 (9U)
+#define SYSMPU_RGDAAC_M1SM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1SM_SHIFT)) & SYSMPU_RGDAAC_M1SM_MASK)
+#define SYSMPU_RGDAAC_M1PE_MASK                  (0x800U)
+#define SYSMPU_RGDAAC_M1PE_SHIFT                 (11U)
+#define SYSMPU_RGDAAC_M1PE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1PE_SHIFT)) & SYSMPU_RGDAAC_M1PE_MASK)
+#define SYSMPU_RGDAAC_M2UM_MASK                  (0x7000U)
+#define SYSMPU_RGDAAC_M2UM_SHIFT                 (12U)
+#define SYSMPU_RGDAAC_M2UM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2UM_SHIFT)) & SYSMPU_RGDAAC_M2UM_MASK)
+#define SYSMPU_RGDAAC_M2SM_MASK                  (0x18000U)
+#define SYSMPU_RGDAAC_M2SM_SHIFT                 (15U)
+#define SYSMPU_RGDAAC_M2SM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2SM_SHIFT)) & SYSMPU_RGDAAC_M2SM_MASK)
+#define SYSMPU_RGDAAC_M2PE_MASK                  (0x20000U)
+#define SYSMPU_RGDAAC_M2PE_SHIFT                 (17U)
+#define SYSMPU_RGDAAC_M2PE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2PE_SHIFT)) & SYSMPU_RGDAAC_M2PE_MASK)
+#define SYSMPU_RGDAAC_M3UM_MASK                  (0x1C0000U)
+#define SYSMPU_RGDAAC_M3UM_SHIFT                 (18U)
+#define SYSMPU_RGDAAC_M3UM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3UM_SHIFT)) & SYSMPU_RGDAAC_M3UM_MASK)
+#define SYSMPU_RGDAAC_M3SM_MASK                  (0x600000U)
+#define SYSMPU_RGDAAC_M3SM_SHIFT                 (21U)
+#define SYSMPU_RGDAAC_M3SM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3SM_SHIFT)) & SYSMPU_RGDAAC_M3SM_MASK)
+#define SYSMPU_RGDAAC_M3PE_MASK                  (0x800000U)
+#define SYSMPU_RGDAAC_M3PE_SHIFT                 (23U)
+#define SYSMPU_RGDAAC_M3PE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3PE_SHIFT)) & SYSMPU_RGDAAC_M3PE_MASK)
+#define SYSMPU_RGDAAC_M4WE_MASK                  (0x1000000U)
+#define SYSMPU_RGDAAC_M4WE_SHIFT                 (24U)
+#define SYSMPU_RGDAAC_M4WE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4WE_SHIFT)) & SYSMPU_RGDAAC_M4WE_MASK)
+#define SYSMPU_RGDAAC_M4RE_MASK                  (0x2000000U)
+#define SYSMPU_RGDAAC_M4RE_SHIFT                 (25U)
+#define SYSMPU_RGDAAC_M4RE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4RE_SHIFT)) & SYSMPU_RGDAAC_M4RE_MASK)
+#define SYSMPU_RGDAAC_M5WE_MASK                  (0x4000000U)
+#define SYSMPU_RGDAAC_M5WE_SHIFT                 (26U)
+#define SYSMPU_RGDAAC_M5WE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5WE_SHIFT)) & SYSMPU_RGDAAC_M5WE_MASK)
+#define SYSMPU_RGDAAC_M5RE_MASK                  (0x8000000U)
+#define SYSMPU_RGDAAC_M5RE_SHIFT                 (27U)
+#define SYSMPU_RGDAAC_M5RE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5RE_SHIFT)) & SYSMPU_RGDAAC_M5RE_MASK)
+#define SYSMPU_RGDAAC_M6WE_MASK                  (0x10000000U)
+#define SYSMPU_RGDAAC_M6WE_SHIFT                 (28U)
+#define SYSMPU_RGDAAC_M6WE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6WE_SHIFT)) & SYSMPU_RGDAAC_M6WE_MASK)
+#define SYSMPU_RGDAAC_M6RE_MASK                  (0x20000000U)
+#define SYSMPU_RGDAAC_M6RE_SHIFT                 (29U)
+#define SYSMPU_RGDAAC_M6RE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6RE_SHIFT)) & SYSMPU_RGDAAC_M6RE_MASK)
+#define SYSMPU_RGDAAC_M7WE_MASK                  (0x40000000U)
+#define SYSMPU_RGDAAC_M7WE_SHIFT                 (30U)
+#define SYSMPU_RGDAAC_M7WE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7WE_SHIFT)) & SYSMPU_RGDAAC_M7WE_MASK)
+#define SYSMPU_RGDAAC_M7RE_MASK                  (0x80000000U)
+#define SYSMPU_RGDAAC_M7RE_SHIFT                 (31U)
+#define SYSMPU_RGDAAC_M7RE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7RE_SHIFT)) & SYSMPU_RGDAAC_M7RE_MASK)
+
+/* The count of SYSMPU_RGDAAC */
+#define SYSMPU_RGDAAC_COUNT                      (12U)
+
+
+/*!
+ * @}
+ */ /* end of group SYSMPU_Register_Masks */
+
+
+/* SYSMPU - Peripheral instance base addresses */
+/** Peripheral SYSMPU base address */
+#define SYSMPU_BASE                              (0x4000D000u)
+/** Peripheral SYSMPU base pointer */
+#define SYSMPU                                   ((SYSMPU_Type *)SYSMPU_BASE)
+/** Array initializer of SYSMPU peripheral base addresses */
+#define SYSMPU_BASE_ADDRS                        { SYSMPU_BASE }
+/** Array initializer of SYSMPU peripheral base pointers */
+#define SYSMPU_BASE_PTRS                         { SYSMPU }
+
+/*!
+ * @}
+ */ /* end of group SYSMPU_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- TPM Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TPM_Peripheral_Access_Layer TPM Peripheral Access Layer
+ * @{
+ */
+
+/** TPM - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t SC;                                /**< Status and Control, offset: 0x0 */
+  __IO uint32_t CNT;                               /**< Counter, offset: 0x4 */
+  __IO uint32_t MOD;                               /**< Modulo, offset: 0x8 */
+  struct {                                         /* offset: 0xC, array step: 0x8 */
+    __IO uint32_t CnSC;                              /**< Channel (n) Status and Control, array offset: 0xC, array step: 0x8 */
+    __IO uint32_t CnV;                               /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
+  } CONTROLS[2];
+       uint8_t RESERVED_0[52];
+  __IO uint32_t STATUS;                            /**< Capture and Compare Status, offset: 0x50 */
+       uint8_t RESERVED_1[16];
+  __IO uint32_t COMBINE;                           /**< Combine Channel Register, offset: 0x64 */
+       uint8_t RESERVED_2[8];
+  __IO uint32_t POL;                               /**< Channel Polarity, offset: 0x70 */
+       uint8_t RESERVED_3[4];
+  __IO uint32_t FILTER;                            /**< Filter Control, offset: 0x78 */
+       uint8_t RESERVED_4[4];
+  __IO uint32_t QDCTRL;                            /**< Quadrature Decoder Control and Status, offset: 0x80 */
+  __IO uint32_t CONF;                              /**< Configuration, offset: 0x84 */
+} TPM_Type;
+
+/* ----------------------------------------------------------------------------
+   -- TPM Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TPM_Register_Masks TPM Register Masks
+ * @{
+ */
+
+/*! @name SC - Status and Control */
+#define TPM_SC_PS_MASK                           (0x7U)
+#define TPM_SC_PS_SHIFT                          (0U)
+#define TPM_SC_PS(x)                             (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK)
+#define TPM_SC_CMOD_MASK                         (0x18U)
+#define TPM_SC_CMOD_SHIFT                        (3U)
+#define TPM_SC_CMOD(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK)
+#define TPM_SC_CPWMS_MASK                        (0x20U)
+#define TPM_SC_CPWMS_SHIFT                       (5U)
+#define TPM_SC_CPWMS(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK)
+#define TPM_SC_TOIE_MASK                         (0x40U)
+#define TPM_SC_TOIE_SHIFT                        (6U)
+#define TPM_SC_TOIE(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK)
+#define TPM_SC_TOF_MASK                          (0x80U)
+#define TPM_SC_TOF_SHIFT                         (7U)
+#define TPM_SC_TOF(x)                            (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK)
+#define TPM_SC_DMA_MASK                          (0x100U)
+#define TPM_SC_DMA_SHIFT                         (8U)
+#define TPM_SC_DMA(x)                            (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK)
+
+/*! @name CNT - Counter */
+#define TPM_CNT_COUNT_MASK                       (0xFFFFU)
+#define TPM_CNT_COUNT_SHIFT                      (0U)
+#define TPM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK)
+
+/*! @name MOD - Modulo */
+#define TPM_MOD_MOD_MASK                         (0xFFFFU)
+#define TPM_MOD_MOD_SHIFT                        (0U)
+#define TPM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK)
+
+/*! @name CnSC - Channel (n) Status and Control */
+#define TPM_CnSC_DMA_MASK                        (0x1U)
+#define TPM_CnSC_DMA_SHIFT                       (0U)
+#define TPM_CnSC_DMA(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK)
+#define TPM_CnSC_ELSA_MASK                       (0x4U)
+#define TPM_CnSC_ELSA_SHIFT                      (2U)
+#define TPM_CnSC_ELSA(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK)
+#define TPM_CnSC_ELSB_MASK                       (0x8U)
+#define TPM_CnSC_ELSB_SHIFT                      (3U)
+#define TPM_CnSC_ELSB(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK)
+#define TPM_CnSC_MSA_MASK                        (0x10U)
+#define TPM_CnSC_MSA_SHIFT                       (4U)
+#define TPM_CnSC_MSA(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK)
+#define TPM_CnSC_MSB_MASK                        (0x20U)
+#define TPM_CnSC_MSB_SHIFT                       (5U)
+#define TPM_CnSC_MSB(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK)
+#define TPM_CnSC_CHIE_MASK                       (0x40U)
+#define TPM_CnSC_CHIE_SHIFT                      (6U)
+#define TPM_CnSC_CHIE(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK)
+#define TPM_CnSC_CHF_MASK                        (0x80U)
+#define TPM_CnSC_CHF_SHIFT                       (7U)
+#define TPM_CnSC_CHF(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK)
+
+/* The count of TPM_CnSC */
+#define TPM_CnSC_COUNT                           (2U)
+
+/*! @name CnV - Channel (n) Value */
+#define TPM_CnV_VAL_MASK                         (0xFFFFU)
+#define TPM_CnV_VAL_SHIFT                        (0U)
+#define TPM_CnV_VAL(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK)
+
+/* The count of TPM_CnV */
+#define TPM_CnV_COUNT                            (2U)
+
+/*! @name STATUS - Capture and Compare Status */
+#define TPM_STATUS_CH0F_MASK                     (0x1U)
+#define TPM_STATUS_CH0F_SHIFT                    (0U)
+#define TPM_STATUS_CH0F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK)
+#define TPM_STATUS_CH1F_MASK                     (0x2U)
+#define TPM_STATUS_CH1F_SHIFT                    (1U)
+#define TPM_STATUS_CH1F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK)
+#define TPM_STATUS_TOF_MASK                      (0x100U)
+#define TPM_STATUS_TOF_SHIFT                     (8U)
+#define TPM_STATUS_TOF(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK)
+
+/*! @name COMBINE - Combine Channel Register */
+#define TPM_COMBINE_COMBINE0_MASK                (0x1U)
+#define TPM_COMBINE_COMBINE0_SHIFT               (0U)
+#define TPM_COMBINE_COMBINE0(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE0_SHIFT)) & TPM_COMBINE_COMBINE0_MASK)
+#define TPM_COMBINE_COMSWAP0_MASK                (0x2U)
+#define TPM_COMBINE_COMSWAP0_SHIFT               (1U)
+#define TPM_COMBINE_COMSWAP0(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP0_SHIFT)) & TPM_COMBINE_COMSWAP0_MASK)
+
+/*! @name POL - Channel Polarity */
+#define TPM_POL_POL0_MASK                        (0x1U)
+#define TPM_POL_POL0_SHIFT                       (0U)
+#define TPM_POL_POL0(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK)
+#define TPM_POL_POL1_MASK                        (0x2U)
+#define TPM_POL_POL1_SHIFT                       (1U)
+#define TPM_POL_POL1(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK)
+
+/*! @name FILTER - Filter Control */
+#define TPM_FILTER_CH0FVAL_MASK                  (0xFU)
+#define TPM_FILTER_CH0FVAL_SHIFT                 (0U)
+#define TPM_FILTER_CH0FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH0FVAL_SHIFT)) & TPM_FILTER_CH0FVAL_MASK)
+#define TPM_FILTER_CH1FVAL_MASK                  (0xF0U)
+#define TPM_FILTER_CH1FVAL_SHIFT                 (4U)
+#define TPM_FILTER_CH1FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH1FVAL_SHIFT)) & TPM_FILTER_CH1FVAL_MASK)
+
+/*! @name QDCTRL - Quadrature Decoder Control and Status */
+#define TPM_QDCTRL_QUADEN_MASK                   (0x1U)
+#define TPM_QDCTRL_QUADEN_SHIFT                  (0U)
+#define TPM_QDCTRL_QUADEN(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADEN_SHIFT)) & TPM_QDCTRL_QUADEN_MASK)
+#define TPM_QDCTRL_TOFDIR_MASK                   (0x2U)
+#define TPM_QDCTRL_TOFDIR_SHIFT                  (1U)
+#define TPM_QDCTRL_TOFDIR(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_TOFDIR_SHIFT)) & TPM_QDCTRL_TOFDIR_MASK)
+#define TPM_QDCTRL_QUADIR_MASK                   (0x4U)
+#define TPM_QDCTRL_QUADIR_SHIFT                  (2U)
+#define TPM_QDCTRL_QUADIR(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADIR_SHIFT)) & TPM_QDCTRL_QUADIR_MASK)
+#define TPM_QDCTRL_QUADMODE_MASK                 (0x8U)
+#define TPM_QDCTRL_QUADMODE_SHIFT                (3U)
+#define TPM_QDCTRL_QUADMODE(x)                   (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADMODE_SHIFT)) & TPM_QDCTRL_QUADMODE_MASK)
+
+/*! @name CONF - Configuration */
+#define TPM_CONF_DOZEEN_MASK                     (0x20U)
+#define TPM_CONF_DOZEEN_SHIFT                    (5U)
+#define TPM_CONF_DOZEEN(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK)
+#define TPM_CONF_DBGMODE_MASK                    (0xC0U)
+#define TPM_CONF_DBGMODE_SHIFT                   (6U)
+#define TPM_CONF_DBGMODE(x)                      (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK)
+#define TPM_CONF_GTBSYNC_MASK                    (0x100U)
+#define TPM_CONF_GTBSYNC_SHIFT                   (8U)
+#define TPM_CONF_GTBSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK)
+#define TPM_CONF_GTBEEN_MASK                     (0x200U)
+#define TPM_CONF_GTBEEN_SHIFT                    (9U)
+#define TPM_CONF_GTBEEN(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK)
+#define TPM_CONF_CSOT_MASK                       (0x10000U)
+#define TPM_CONF_CSOT_SHIFT                      (16U)
+#define TPM_CONF_CSOT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK)
+#define TPM_CONF_CSOO_MASK                       (0x20000U)
+#define TPM_CONF_CSOO_SHIFT                      (17U)
+#define TPM_CONF_CSOO(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK)
+#define TPM_CONF_CROT_MASK                       (0x40000U)
+#define TPM_CONF_CROT_SHIFT                      (18U)
+#define TPM_CONF_CROT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK)
+#define TPM_CONF_CPOT_MASK                       (0x80000U)
+#define TPM_CONF_CPOT_SHIFT                      (19U)
+#define TPM_CONF_CPOT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK)
+#define TPM_CONF_TRGPOL_MASK                     (0x400000U)
+#define TPM_CONF_TRGPOL_SHIFT                    (22U)
+#define TPM_CONF_TRGPOL(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK)
+#define TPM_CONF_TRGSRC_MASK                     (0x800000U)
+#define TPM_CONF_TRGSRC_SHIFT                    (23U)
+#define TPM_CONF_TRGSRC(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK)
+#define TPM_CONF_TRGSEL_MASK                     (0xF000000U)
+#define TPM_CONF_TRGSEL_SHIFT                    (24U)
+#define TPM_CONF_TRGSEL(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group TPM_Register_Masks */
+
+
+/* TPM - Peripheral instance base addresses */
+/** Peripheral TPM1 base address */
+#define TPM1_BASE                                (0x400C9000u)
+/** Peripheral TPM1 base pointer */
+#define TPM1                                     ((TPM_Type *)TPM1_BASE)
+/** Peripheral TPM2 base address */
+#define TPM2_BASE                                (0x400CA000u)
+/** Peripheral TPM2 base pointer */
+#define TPM2                                     ((TPM_Type *)TPM2_BASE)
+/** Array initializer of TPM peripheral base addresses */
+#define TPM_BASE_ADDRS                           { 0u, TPM1_BASE, TPM2_BASE }
+/** Array initializer of TPM peripheral base pointers */
+#define TPM_BASE_PTRS                            { (TPM_Type *)0u, TPM1, TPM2 }
+/** Interrupt vectors for the TPM peripheral type */
+#define TPM_IRQS                                 { NotAvail_IRQn, TPM1_IRQn, TPM2_IRQn }
+
+/*!
+ * @}
+ */ /* end of group TPM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- TSI Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TSI_Peripheral_Access_Layer TSI Peripheral Access Layer
+ * @{
+ */
+
+/** TSI - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t GENCS;                             /**< TSI General Control and Status Register, offset: 0x0 */
+  __IO uint32_t DATA;                              /**< TSI DATA Register, offset: 0x4 */
+  __IO uint32_t TSHD;                              /**< TSI Threshold Register, offset: 0x8 */
+} TSI_Type;
+
+/* ----------------------------------------------------------------------------
+   -- TSI Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup TSI_Register_Masks TSI Register Masks
+ * @{
+ */
+
+/*! @name GENCS - TSI General Control and Status Register */
+#define TSI_GENCS_EOSDMEO_MASK                   (0x1U)
+#define TSI_GENCS_EOSDMEO_SHIFT                  (0U)
+#define TSI_GENCS_EOSDMEO(x)                     (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSDMEO_SHIFT)) & TSI_GENCS_EOSDMEO_MASK)
+#define TSI_GENCS_CURSW_MASK                     (0x2U)
+#define TSI_GENCS_CURSW_SHIFT                    (1U)
+#define TSI_GENCS_CURSW(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_CURSW_SHIFT)) & TSI_GENCS_CURSW_MASK)
+#define TSI_GENCS_EOSF_MASK                      (0x4U)
+#define TSI_GENCS_EOSF_SHIFT                     (2U)
+#define TSI_GENCS_EOSF(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK)
+#define TSI_GENCS_SCNIP_MASK                     (0x8U)
+#define TSI_GENCS_SCNIP_SHIFT                    (3U)
+#define TSI_GENCS_SCNIP(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK)
+#define TSI_GENCS_STM_MASK                       (0x10U)
+#define TSI_GENCS_STM_SHIFT                      (4U)
+#define TSI_GENCS_STM(x)                         (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK)
+#define TSI_GENCS_STPE_MASK                      (0x20U)
+#define TSI_GENCS_STPE_SHIFT                     (5U)
+#define TSI_GENCS_STPE(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK)
+#define TSI_GENCS_TSIIEN_MASK                    (0x40U)
+#define TSI_GENCS_TSIIEN_SHIFT                   (6U)
+#define TSI_GENCS_TSIIEN(x)                      (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIEN_SHIFT)) & TSI_GENCS_TSIIEN_MASK)
+#define TSI_GENCS_TSIEN_MASK                     (0x80U)
+#define TSI_GENCS_TSIEN_SHIFT                    (7U)
+#define TSI_GENCS_TSIEN(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK)
+#define TSI_GENCS_NSCN_MASK                      (0x1F00U)
+#define TSI_GENCS_NSCN_SHIFT                     (8U)
+#define TSI_GENCS_NSCN(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_NSCN_SHIFT)) & TSI_GENCS_NSCN_MASK)
+#define TSI_GENCS_PS_MASK                        (0xE000U)
+#define TSI_GENCS_PS_SHIFT                       (13U)
+#define TSI_GENCS_PS(x)                          (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_PS_SHIFT)) & TSI_GENCS_PS_MASK)
+#define TSI_GENCS_EXTCHRG_MASK                   (0x70000U)
+#define TSI_GENCS_EXTCHRG_SHIFT                  (16U)
+#define TSI_GENCS_EXTCHRG(x)                     (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EXTCHRG_SHIFT)) & TSI_GENCS_EXTCHRG_MASK)
+#define TSI_GENCS_DVOLT_MASK                     (0x180000U)
+#define TSI_GENCS_DVOLT_SHIFT                    (19U)
+#define TSI_GENCS_DVOLT(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DVOLT_SHIFT)) & TSI_GENCS_DVOLT_MASK)
+#define TSI_GENCS_REFCHRG_MASK                   (0xE00000U)
+#define TSI_GENCS_REFCHRG_SHIFT                  (21U)
+#define TSI_GENCS_REFCHRG(x)                     (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_REFCHRG_SHIFT)) & TSI_GENCS_REFCHRG_MASK)
+#define TSI_GENCS_MODE_MASK                      (0xF000000U)
+#define TSI_GENCS_MODE_SHIFT                     (24U)
+#define TSI_GENCS_MODE(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_MODE_SHIFT)) & TSI_GENCS_MODE_MASK)
+#define TSI_GENCS_ESOR_MASK                      (0x10000000U)
+#define TSI_GENCS_ESOR_SHIFT                     (28U)
+#define TSI_GENCS_ESOR(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK)
+#define TSI_GENCS_OUTRGF_MASK                    (0x80000000U)
+#define TSI_GENCS_OUTRGF_SHIFT                   (31U)
+#define TSI_GENCS_OUTRGF(x)                      (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRGF_SHIFT)) & TSI_GENCS_OUTRGF_MASK)
+
+/*! @name DATA - TSI DATA Register */
+#define TSI_DATA_TSICNT_MASK                     (0xFFFFU)
+#define TSI_DATA_TSICNT_SHIFT                    (0U)
+#define TSI_DATA_TSICNT(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICNT_SHIFT)) & TSI_DATA_TSICNT_MASK)
+#define TSI_DATA_SWTS_MASK                       (0x400000U)
+#define TSI_DATA_SWTS_SHIFT                      (22U)
+#define TSI_DATA_SWTS(x)                         (((uint32_t)(((uint32_t)(x)) << TSI_DATA_SWTS_SHIFT)) & TSI_DATA_SWTS_MASK)
+#define TSI_DATA_DMAEN_MASK                      (0x800000U)
+#define TSI_DATA_DMAEN_SHIFT                     (23U)
+#define TSI_DATA_DMAEN(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_DATA_DMAEN_SHIFT)) & TSI_DATA_DMAEN_MASK)
+#define TSI_DATA_TSICH_MASK                      (0xF0000000U)
+#define TSI_DATA_TSICH_SHIFT                     (28U)
+#define TSI_DATA_TSICH(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICH_SHIFT)) & TSI_DATA_TSICH_MASK)
+
+/*! @name TSHD - TSI Threshold Register */
+#define TSI_TSHD_THRESL_MASK                     (0xFFFFU)
+#define TSI_TSHD_THRESL_SHIFT                    (0U)
+#define TSI_TSHD_THRESL(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESL_SHIFT)) & TSI_TSHD_THRESL_MASK)
+#define TSI_TSHD_THRESH_MASK                     (0xFFFF0000U)
+#define TSI_TSHD_THRESH_SHIFT                    (16U)
+#define TSI_TSHD_THRESH(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESH_SHIFT)) & TSI_TSHD_THRESH_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group TSI_Register_Masks */
+
+
+/* TSI - Peripheral instance base addresses */
+/** Peripheral TSI0 base address */
+#define TSI0_BASE                                (0x40045000u)
+/** Peripheral TSI0 base pointer */
+#define TSI0                                     ((TSI_Type *)TSI0_BASE)
+/** Array initializer of TSI peripheral base addresses */
+#define TSI_BASE_ADDRS                           { TSI0_BASE }
+/** Array initializer of TSI peripheral base pointers */
+#define TSI_BASE_PTRS                            { TSI0 }
+/** Interrupt vectors for the TSI peripheral type */
+#define TSI_IRQS                                 { TSI0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group TSI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- UART Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
+ * @{
+ */
+
+/** UART - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t BDH;                                /**< UART Baud Rate Registers: High, offset: 0x0 */
+  __IO uint8_t BDL;                                /**< UART Baud Rate Registers: Low, offset: 0x1 */
+  __IO uint8_t C1;                                 /**< UART Control Register 1, offset: 0x2 */
+  __IO uint8_t C2;                                 /**< UART Control Register 2, offset: 0x3 */
+  __I  uint8_t S1;                                 /**< UART Status Register 1, offset: 0x4 */
+  __IO uint8_t S2;                                 /**< UART Status Register 2, offset: 0x5 */
+  __IO uint8_t C3;                                 /**< UART Control Register 3, offset: 0x6 */
+  __IO uint8_t D;                                  /**< UART Data Register, offset: 0x7 */
+  __IO uint8_t MA1;                                /**< UART Match Address Registers 1, offset: 0x8 */
+  __IO uint8_t MA2;                                /**< UART Match Address Registers 2, offset: 0x9 */
+  __IO uint8_t C4;                                 /**< UART Control Register 4, offset: 0xA */
+  __IO uint8_t C5;                                 /**< UART Control Register 5, offset: 0xB */
+  __I  uint8_t ED;                                 /**< UART Extended Data Register, offset: 0xC */
+  __IO uint8_t MODEM;                              /**< UART Modem Register, offset: 0xD */
+  __IO uint8_t IR;                                 /**< UART Infrared Register, offset: 0xE */
+       uint8_t RESERVED_0[1];
+  __IO uint8_t PFIFO;                              /**< UART FIFO Parameters, offset: 0x10 */
+  __IO uint8_t CFIFO;                              /**< UART FIFO Control Register, offset: 0x11 */
+  __IO uint8_t SFIFO;                              /**< UART FIFO Status Register, offset: 0x12 */
+  __IO uint8_t TWFIFO;                             /**< UART FIFO Transmit Watermark, offset: 0x13 */
+  __I  uint8_t TCFIFO;                             /**< UART FIFO Transmit Count, offset: 0x14 */
+  __IO uint8_t RWFIFO;                             /**< UART FIFO Receive Watermark, offset: 0x15 */
+  __I  uint8_t RCFIFO;                             /**< UART FIFO Receive Count, offset: 0x16 */
+       uint8_t RESERVED_1[1];
+  __IO uint8_t C7816;                              /**< UART 7816 Control Register, offset: 0x18 */
+  __IO uint8_t IE7816;                             /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
+  __IO uint8_t IS7816;                             /**< UART 7816 Interrupt Status Register, offset: 0x1A */
+  __IO uint8_t WP7816;                             /**< UART 7816 Wait Parameter Register, offset: 0x1B */
+  __IO uint8_t WN7816;                             /**< UART 7816 Wait N Register, offset: 0x1C */
+  __IO uint8_t WF7816;                             /**< UART 7816 Wait FD Register, offset: 0x1D */
+  __IO uint8_t ET7816;                             /**< UART 7816 Error Threshold Register, offset: 0x1E */
+  __IO uint8_t TL7816;                             /**< UART 7816 Transmit Length Register, offset: 0x1F */
+       uint8_t RESERVED_2[26];
+  __IO uint8_t AP7816A_T0;                         /**< UART 7816 ATR Duration Timer Register A, offset: 0x3A */
+  __IO uint8_t AP7816B_T0;                         /**< UART 7816 ATR Duration Timer Register B, offset: 0x3B */
+  union {                                          /* offset: 0x3C */
+    struct {                                         /* offset: 0x3C */
+      __IO uint8_t WP7816A_T0;                         /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
+      __IO uint8_t WP7816B_T0;                         /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
+    } TYPE0;
+    struct {                                         /* offset: 0x3C */
+      __IO uint8_t WP7816A_T1;                         /**< UART 7816 Wait Parameter Register A, offset: 0x3C */
+      __IO uint8_t WP7816B_T1;                         /**< UART 7816 Wait Parameter Register B, offset: 0x3D */
+    } TYPE1;
+  };
+  __IO uint8_t WGP7816_T1;                         /**< UART 7816 Wait and Guard Parameter Register, offset: 0x3E */
+  __IO uint8_t WP7816C_T1;                         /**< UART 7816 Wait Parameter Register C, offset: 0x3F */
+} UART_Type;
+
+/* ----------------------------------------------------------------------------
+   -- UART Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UART_Register_Masks UART Register Masks
+ * @{
+ */
+
+/*! @name BDH - UART Baud Rate Registers: High */
+#define UART_BDH_SBR_MASK                        (0x1FU)
+#define UART_BDH_SBR_SHIFT                       (0U)
+#define UART_BDH_SBR(x)                          (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK)
+#define UART_BDH_SBNS_MASK                       (0x20U)
+#define UART_BDH_SBNS_SHIFT                      (5U)
+#define UART_BDH_SBNS(x)                         (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBNS_SHIFT)) & UART_BDH_SBNS_MASK)
+#define UART_BDH_RXEDGIE_MASK                    (0x40U)
+#define UART_BDH_RXEDGIE_SHIFT                   (6U)
+#define UART_BDH_RXEDGIE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK)
+#define UART_BDH_LBKDIE_MASK                     (0x80U)
+#define UART_BDH_LBKDIE_SHIFT                    (7U)
+#define UART_BDH_LBKDIE(x)                       (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK)
+
+/*! @name BDL - UART Baud Rate Registers: Low */
+#define UART_BDL_SBR_MASK                        (0xFFU)
+#define UART_BDL_SBR_SHIFT                       (0U)
+#define UART_BDL_SBR(x)                          (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK)
+
+/*! @name C1 - UART Control Register 1 */
+#define UART_C1_PT_MASK                          (0x1U)
+#define UART_C1_PT_SHIFT                         (0U)
+#define UART_C1_PT(x)                            (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK)
+#define UART_C1_PE_MASK                          (0x2U)
+#define UART_C1_PE_SHIFT                         (1U)
+#define UART_C1_PE(x)                            (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK)
+#define UART_C1_ILT_MASK                         (0x4U)
+#define UART_C1_ILT_SHIFT                        (2U)
+#define UART_C1_ILT(x)                           (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK)
+#define UART_C1_WAKE_MASK                        (0x8U)
+#define UART_C1_WAKE_SHIFT                       (3U)
+#define UART_C1_WAKE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK)
+#define UART_C1_M_MASK                           (0x10U)
+#define UART_C1_M_SHIFT                          (4U)
+#define UART_C1_M(x)                             (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK)
+#define UART_C1_RSRC_MASK                        (0x20U)
+#define UART_C1_RSRC_SHIFT                       (5U)
+#define UART_C1_RSRC(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK)
+#define UART_C1_UARTSWAI_MASK                    (0x40U)
+#define UART_C1_UARTSWAI_SHIFT                   (6U)
+#define UART_C1_UARTSWAI(x)                      (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK)
+#define UART_C1_LOOPS_MASK                       (0x80U)
+#define UART_C1_LOOPS_SHIFT                      (7U)
+#define UART_C1_LOOPS(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK)
+
+/*! @name C2 - UART Control Register 2 */
+#define UART_C2_SBK_MASK                         (0x1U)
+#define UART_C2_SBK_SHIFT                        (0U)
+#define UART_C2_SBK(x)                           (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK)
+#define UART_C2_RWU_MASK                         (0x2U)
+#define UART_C2_RWU_SHIFT                        (1U)
+#define UART_C2_RWU(x)                           (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK)
+#define UART_C2_RE_MASK                          (0x4U)
+#define UART_C2_RE_SHIFT                         (2U)
+#define UART_C2_RE(x)                            (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK)
+#define UART_C2_TE_MASK                          (0x8U)
+#define UART_C2_TE_SHIFT                         (3U)
+#define UART_C2_TE(x)                            (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK)
+#define UART_C2_ILIE_MASK                        (0x10U)
+#define UART_C2_ILIE_SHIFT                       (4U)
+#define UART_C2_ILIE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK)
+#define UART_C2_RIE_MASK                         (0x20U)
+#define UART_C2_RIE_SHIFT                        (5U)
+#define UART_C2_RIE(x)                           (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK)
+#define UART_C2_TCIE_MASK                        (0x40U)
+#define UART_C2_TCIE_SHIFT                       (6U)
+#define UART_C2_TCIE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK)
+#define UART_C2_TIE_MASK                         (0x80U)
+#define UART_C2_TIE_SHIFT                        (7U)
+#define UART_C2_TIE(x)                           (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK)
+
+/*! @name S1 - UART Status Register 1 */
+#define UART_S1_PF_MASK                          (0x1U)
+#define UART_S1_PF_SHIFT                         (0U)
+#define UART_S1_PF(x)                            (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK)
+#define UART_S1_FE_MASK                          (0x2U)
+#define UART_S1_FE_SHIFT                         (1U)
+#define UART_S1_FE(x)                            (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK)
+#define UART_S1_NF_MASK                          (0x4U)
+#define UART_S1_NF_SHIFT                         (2U)
+#define UART_S1_NF(x)                            (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK)
+#define UART_S1_OR_MASK                          (0x8U)
+#define UART_S1_OR_SHIFT                         (3U)
+#define UART_S1_OR(x)                            (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK)
+#define UART_S1_IDLE_MASK                        (0x10U)
+#define UART_S1_IDLE_SHIFT                       (4U)
+#define UART_S1_IDLE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK)
+#define UART_S1_RDRF_MASK                        (0x20U)
+#define UART_S1_RDRF_SHIFT                       (5U)
+#define UART_S1_RDRF(x)                          (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK)
+#define UART_S1_TC_MASK                          (0x40U)
+#define UART_S1_TC_SHIFT                         (6U)
+#define UART_S1_TC(x)                            (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK)
+#define UART_S1_TDRE_MASK                        (0x80U)
+#define UART_S1_TDRE_SHIFT                       (7U)
+#define UART_S1_TDRE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK)
+
+/*! @name S2 - UART Status Register 2 */
+#define UART_S2_RAF_MASK                         (0x1U)
+#define UART_S2_RAF_SHIFT                        (0U)
+#define UART_S2_RAF(x)                           (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK)
+#define UART_S2_LBKDE_MASK                       (0x2U)
+#define UART_S2_LBKDE_SHIFT                      (1U)
+#define UART_S2_LBKDE(x)                         (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK)
+#define UART_S2_BRK13_MASK                       (0x4U)
+#define UART_S2_BRK13_SHIFT                      (2U)
+#define UART_S2_BRK13(x)                         (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK)
+#define UART_S2_RWUID_MASK                       (0x8U)
+#define UART_S2_RWUID_SHIFT                      (3U)
+#define UART_S2_RWUID(x)                         (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK)
+#define UART_S2_RXINV_MASK                       (0x10U)
+#define UART_S2_RXINV_SHIFT                      (4U)
+#define UART_S2_RXINV(x)                         (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK)
+#define UART_S2_MSBF_MASK                        (0x20U)
+#define UART_S2_MSBF_SHIFT                       (5U)
+#define UART_S2_MSBF(x)                          (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK)
+#define UART_S2_RXEDGIF_MASK                     (0x40U)
+#define UART_S2_RXEDGIF_SHIFT                    (6U)
+#define UART_S2_RXEDGIF(x)                       (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK)
+#define UART_S2_LBKDIF_MASK                      (0x80U)
+#define UART_S2_LBKDIF_SHIFT                     (7U)
+#define UART_S2_LBKDIF(x)                        (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK)
+
+/*! @name C3 - UART Control Register 3 */
+#define UART_C3_PEIE_MASK                        (0x1U)
+#define UART_C3_PEIE_SHIFT                       (0U)
+#define UART_C3_PEIE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK)
+#define UART_C3_FEIE_MASK                        (0x2U)
+#define UART_C3_FEIE_SHIFT                       (1U)
+#define UART_C3_FEIE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK)
+#define UART_C3_NEIE_MASK                        (0x4U)
+#define UART_C3_NEIE_SHIFT                       (2U)
+#define UART_C3_NEIE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK)
+#define UART_C3_ORIE_MASK                        (0x8U)
+#define UART_C3_ORIE_SHIFT                       (3U)
+#define UART_C3_ORIE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK)
+#define UART_C3_TXINV_MASK                       (0x10U)
+#define UART_C3_TXINV_SHIFT                      (4U)
+#define UART_C3_TXINV(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK)
+#define UART_C3_TXDIR_MASK                       (0x20U)
+#define UART_C3_TXDIR_SHIFT                      (5U)
+#define UART_C3_TXDIR(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK)
+#define UART_C3_T8_MASK                          (0x40U)
+#define UART_C3_T8_SHIFT                         (6U)
+#define UART_C3_T8(x)                            (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK)
+#define UART_C3_R8_MASK                          (0x80U)
+#define UART_C3_R8_SHIFT                         (7U)
+#define UART_C3_R8(x)                            (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK)
+
+/*! @name D - UART Data Register */
+#define UART_D_RT_MASK                           (0xFFU)
+#define UART_D_RT_SHIFT                          (0U)
+#define UART_D_RT(x)                             (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK)
+
+/*! @name MA1 - UART Match Address Registers 1 */
+#define UART_MA1_MA_MASK                         (0xFFU)
+#define UART_MA1_MA_SHIFT                        (0U)
+#define UART_MA1_MA(x)                           (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK)
+
+/*! @name MA2 - UART Match Address Registers 2 */
+#define UART_MA2_MA_MASK                         (0xFFU)
+#define UART_MA2_MA_SHIFT                        (0U)
+#define UART_MA2_MA(x)                           (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK)
+
+/*! @name C4 - UART Control Register 4 */
+#define UART_C4_BRFA_MASK                        (0x1FU)
+#define UART_C4_BRFA_SHIFT                       (0U)
+#define UART_C4_BRFA(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK)
+#define UART_C4_M10_MASK                         (0x20U)
+#define UART_C4_M10_SHIFT                        (5U)
+#define UART_C4_M10(x)                           (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK)
+#define UART_C4_MAEN2_MASK                       (0x40U)
+#define UART_C4_MAEN2_SHIFT                      (6U)
+#define UART_C4_MAEN2(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK)
+#define UART_C4_MAEN1_MASK                       (0x80U)
+#define UART_C4_MAEN1_SHIFT                      (7U)
+#define UART_C4_MAEN1(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK)
+
+/*! @name C5 - UART Control Register 5 */
+#define UART_C5_RDMAS_MASK                       (0x20U)
+#define UART_C5_RDMAS_SHIFT                      (5U)
+#define UART_C5_RDMAS(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK)
+#define UART_C5_TDMAS_MASK                       (0x80U)
+#define UART_C5_TDMAS_SHIFT                      (7U)
+#define UART_C5_TDMAS(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK)
+
+/*! @name ED - UART Extended Data Register */
+#define UART_ED_PARITYE_MASK                     (0x40U)
+#define UART_ED_PARITYE_SHIFT                    (6U)
+#define UART_ED_PARITYE(x)                       (((uint8_t)(((uint8_t)(x)) << UART_ED_PARITYE_SHIFT)) & UART_ED_PARITYE_MASK)
+#define UART_ED_NOISY_MASK                       (0x80U)
+#define UART_ED_NOISY_SHIFT                      (7U)
+#define UART_ED_NOISY(x)                         (((uint8_t)(((uint8_t)(x)) << UART_ED_NOISY_SHIFT)) & UART_ED_NOISY_MASK)
+
+/*! @name MODEM - UART Modem Register */
+#define UART_MODEM_TXCTSE_MASK                   (0x1U)
+#define UART_MODEM_TXCTSE_SHIFT                  (0U)
+#define UART_MODEM_TXCTSE(x)                     (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXCTSE_SHIFT)) & UART_MODEM_TXCTSE_MASK)
+#define UART_MODEM_TXRTSE_MASK                   (0x2U)
+#define UART_MODEM_TXRTSE_SHIFT                  (1U)
+#define UART_MODEM_TXRTSE(x)                     (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSE_SHIFT)) & UART_MODEM_TXRTSE_MASK)
+#define UART_MODEM_TXRTSPOL_MASK                 (0x4U)
+#define UART_MODEM_TXRTSPOL_SHIFT                (2U)
+#define UART_MODEM_TXRTSPOL(x)                   (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSPOL_SHIFT)) & UART_MODEM_TXRTSPOL_MASK)
+#define UART_MODEM_RXRTSE_MASK                   (0x8U)
+#define UART_MODEM_RXRTSE_SHIFT                  (3U)
+#define UART_MODEM_RXRTSE(x)                     (((uint8_t)(((uint8_t)(x)) << UART_MODEM_RXRTSE_SHIFT)) & UART_MODEM_RXRTSE_MASK)
+
+/*! @name IR - UART Infrared Register */
+#define UART_IR_TNP_MASK                         (0x3U)
+#define UART_IR_TNP_SHIFT                        (0U)
+#define UART_IR_TNP(x)                           (((uint8_t)(((uint8_t)(x)) << UART_IR_TNP_SHIFT)) & UART_IR_TNP_MASK)
+#define UART_IR_IREN_MASK                        (0x4U)
+#define UART_IR_IREN_SHIFT                       (2U)
+#define UART_IR_IREN(x)                          (((uint8_t)(((uint8_t)(x)) << UART_IR_IREN_SHIFT)) & UART_IR_IREN_MASK)
+
+/*! @name PFIFO - UART FIFO Parameters */
+#define UART_PFIFO_RXFIFOSIZE_MASK               (0x7U)
+#define UART_PFIFO_RXFIFOSIZE_SHIFT              (0U)
+#define UART_PFIFO_RXFIFOSIZE(x)                 (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFIFOSIZE_SHIFT)) & UART_PFIFO_RXFIFOSIZE_MASK)
+#define UART_PFIFO_RXFE_MASK                     (0x8U)
+#define UART_PFIFO_RXFE_SHIFT                    (3U)
+#define UART_PFIFO_RXFE(x)                       (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFE_SHIFT)) & UART_PFIFO_RXFE_MASK)
+#define UART_PFIFO_TXFIFOSIZE_MASK               (0x70U)
+#define UART_PFIFO_TXFIFOSIZE_SHIFT              (4U)
+#define UART_PFIFO_TXFIFOSIZE(x)                 (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFIFOSIZE_SHIFT)) & UART_PFIFO_TXFIFOSIZE_MASK)
+#define UART_PFIFO_TXFE_MASK                     (0x80U)
+#define UART_PFIFO_TXFE_SHIFT                    (7U)
+#define UART_PFIFO_TXFE(x)                       (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFE_SHIFT)) & UART_PFIFO_TXFE_MASK)
+
+/*! @name CFIFO - UART FIFO Control Register */
+#define UART_CFIFO_RXUFE_MASK                    (0x1U)
+#define UART_CFIFO_RXUFE_SHIFT                   (0U)
+#define UART_CFIFO_RXUFE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXUFE_SHIFT)) & UART_CFIFO_RXUFE_MASK)
+#define UART_CFIFO_TXOFE_MASK                    (0x2U)
+#define UART_CFIFO_TXOFE_SHIFT                   (1U)
+#define UART_CFIFO_TXOFE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXOFE_SHIFT)) & UART_CFIFO_TXOFE_MASK)
+#define UART_CFIFO_RXOFE_MASK                    (0x4U)
+#define UART_CFIFO_RXOFE_SHIFT                   (2U)
+#define UART_CFIFO_RXOFE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXOFE_SHIFT)) & UART_CFIFO_RXOFE_MASK)
+#define UART_CFIFO_RXFLUSH_MASK                  (0x40U)
+#define UART_CFIFO_RXFLUSH_SHIFT                 (6U)
+#define UART_CFIFO_RXFLUSH(x)                    (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXFLUSH_SHIFT)) & UART_CFIFO_RXFLUSH_MASK)
+#define UART_CFIFO_TXFLUSH_MASK                  (0x80U)
+#define UART_CFIFO_TXFLUSH_SHIFT                 (7U)
+#define UART_CFIFO_TXFLUSH(x)                    (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXFLUSH_SHIFT)) & UART_CFIFO_TXFLUSH_MASK)
+
+/*! @name SFIFO - UART FIFO Status Register */
+#define UART_SFIFO_RXUF_MASK                     (0x1U)
+#define UART_SFIFO_RXUF_SHIFT                    (0U)
+#define UART_SFIFO_RXUF(x)                       (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXUF_SHIFT)) & UART_SFIFO_RXUF_MASK)
+#define UART_SFIFO_TXOF_MASK                     (0x2U)
+#define UART_SFIFO_TXOF_SHIFT                    (1U)
+#define UART_SFIFO_TXOF(x)                       (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXOF_SHIFT)) & UART_SFIFO_TXOF_MASK)
+#define UART_SFIFO_RXOF_MASK                     (0x4U)
+#define UART_SFIFO_RXOF_SHIFT                    (2U)
+#define UART_SFIFO_RXOF(x)                       (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXOF_SHIFT)) & UART_SFIFO_RXOF_MASK)
+#define UART_SFIFO_RXEMPT_MASK                   (0x40U)
+#define UART_SFIFO_RXEMPT_SHIFT                  (6U)
+#define UART_SFIFO_RXEMPT(x)                     (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXEMPT_SHIFT)) & UART_SFIFO_RXEMPT_MASK)
+#define UART_SFIFO_TXEMPT_MASK                   (0x80U)
+#define UART_SFIFO_TXEMPT_SHIFT                  (7U)
+#define UART_SFIFO_TXEMPT(x)                     (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXEMPT_SHIFT)) & UART_SFIFO_TXEMPT_MASK)
+
+/*! @name TWFIFO - UART FIFO Transmit Watermark */
+#define UART_TWFIFO_TXWATER_MASK                 (0xFFU)
+#define UART_TWFIFO_TXWATER_SHIFT                (0U)
+#define UART_TWFIFO_TXWATER(x)                   (((uint8_t)(((uint8_t)(x)) << UART_TWFIFO_TXWATER_SHIFT)) & UART_TWFIFO_TXWATER_MASK)
+
+/*! @name TCFIFO - UART FIFO Transmit Count */
+#define UART_TCFIFO_TXCOUNT_MASK                 (0xFFU)
+#define UART_TCFIFO_TXCOUNT_SHIFT                (0U)
+#define UART_TCFIFO_TXCOUNT(x)                   (((uint8_t)(((uint8_t)(x)) << UART_TCFIFO_TXCOUNT_SHIFT)) & UART_TCFIFO_TXCOUNT_MASK)
+
+/*! @name RWFIFO - UART FIFO Receive Watermark */
+#define UART_RWFIFO_RXWATER_MASK                 (0xFFU)
+#define UART_RWFIFO_RXWATER_SHIFT                (0U)
+#define UART_RWFIFO_RXWATER(x)                   (((uint8_t)(((uint8_t)(x)) << UART_RWFIFO_RXWATER_SHIFT)) & UART_RWFIFO_RXWATER_MASK)
+
+/*! @name RCFIFO - UART FIFO Receive Count */
+#define UART_RCFIFO_RXCOUNT_MASK                 (0xFFU)
+#define UART_RCFIFO_RXCOUNT_SHIFT                (0U)
+#define UART_RCFIFO_RXCOUNT(x)                   (((uint8_t)(((uint8_t)(x)) << UART_RCFIFO_RXCOUNT_SHIFT)) & UART_RCFIFO_RXCOUNT_MASK)
+
+/*! @name C7816 - UART 7816 Control Register */
+#define UART_C7816_ISO_7816E_MASK                (0x1U)
+#define UART_C7816_ISO_7816E_SHIFT               (0U)
+#define UART_C7816_ISO_7816E(x)                  (((uint8_t)(((uint8_t)(x)) << UART_C7816_ISO_7816E_SHIFT)) & UART_C7816_ISO_7816E_MASK)
+#define UART_C7816_TTYPE_MASK                    (0x2U)
+#define UART_C7816_TTYPE_SHIFT                   (1U)
+#define UART_C7816_TTYPE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_C7816_TTYPE_SHIFT)) & UART_C7816_TTYPE_MASK)
+#define UART_C7816_INIT_MASK                     (0x4U)
+#define UART_C7816_INIT_SHIFT                    (2U)
+#define UART_C7816_INIT(x)                       (((uint8_t)(((uint8_t)(x)) << UART_C7816_INIT_SHIFT)) & UART_C7816_INIT_MASK)
+#define UART_C7816_ANACK_MASK                    (0x8U)
+#define UART_C7816_ANACK_SHIFT                   (3U)
+#define UART_C7816_ANACK(x)                      (((uint8_t)(((uint8_t)(x)) << UART_C7816_ANACK_SHIFT)) & UART_C7816_ANACK_MASK)
+#define UART_C7816_ONACK_MASK                    (0x10U)
+#define UART_C7816_ONACK_SHIFT                   (4U)
+#define UART_C7816_ONACK(x)                      (((uint8_t)(((uint8_t)(x)) << UART_C7816_ONACK_SHIFT)) & UART_C7816_ONACK_MASK)
+
+/*! @name IE7816 - UART 7816 Interrupt Enable Register */
+#define UART_IE7816_RXTE_MASK                    (0x1U)
+#define UART_IE7816_RXTE_SHIFT                   (0U)
+#define UART_IE7816_RXTE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_IE7816_RXTE_SHIFT)) & UART_IE7816_RXTE_MASK)
+#define UART_IE7816_TXTE_MASK                    (0x2U)
+#define UART_IE7816_TXTE_SHIFT                   (1U)
+#define UART_IE7816_TXTE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_IE7816_TXTE_SHIFT)) & UART_IE7816_TXTE_MASK)
+#define UART_IE7816_GTVE_MASK                    (0x4U)
+#define UART_IE7816_GTVE_SHIFT                   (2U)
+#define UART_IE7816_GTVE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_IE7816_GTVE_SHIFT)) & UART_IE7816_GTVE_MASK)
+#define UART_IE7816_ADTE_MASK                    (0x8U)
+#define UART_IE7816_ADTE_SHIFT                   (3U)
+#define UART_IE7816_ADTE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_IE7816_ADTE_SHIFT)) & UART_IE7816_ADTE_MASK)
+#define UART_IE7816_INITDE_MASK                  (0x10U)
+#define UART_IE7816_INITDE_SHIFT                 (4U)
+#define UART_IE7816_INITDE(x)                    (((uint8_t)(((uint8_t)(x)) << UART_IE7816_INITDE_SHIFT)) & UART_IE7816_INITDE_MASK)
+#define UART_IE7816_BWTE_MASK                    (0x20U)
+#define UART_IE7816_BWTE_SHIFT                   (5U)
+#define UART_IE7816_BWTE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_IE7816_BWTE_SHIFT)) & UART_IE7816_BWTE_MASK)
+#define UART_IE7816_CWTE_MASK                    (0x40U)
+#define UART_IE7816_CWTE_SHIFT                   (6U)
+#define UART_IE7816_CWTE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_IE7816_CWTE_SHIFT)) & UART_IE7816_CWTE_MASK)
+#define UART_IE7816_WTE_MASK                     (0x80U)
+#define UART_IE7816_WTE_SHIFT                    (7U)
+#define UART_IE7816_WTE(x)                       (((uint8_t)(((uint8_t)(x)) << UART_IE7816_WTE_SHIFT)) & UART_IE7816_WTE_MASK)
+
+/*! @name IS7816 - UART 7816 Interrupt Status Register */
+#define UART_IS7816_RXT_MASK                     (0x1U)
+#define UART_IS7816_RXT_SHIFT                    (0U)
+#define UART_IS7816_RXT(x)                       (((uint8_t)(((uint8_t)(x)) << UART_IS7816_RXT_SHIFT)) & UART_IS7816_RXT_MASK)
+#define UART_IS7816_TXT_MASK                     (0x2U)
+#define UART_IS7816_TXT_SHIFT                    (1U)
+#define UART_IS7816_TXT(x)                       (((uint8_t)(((uint8_t)(x)) << UART_IS7816_TXT_SHIFT)) & UART_IS7816_TXT_MASK)
+#define UART_IS7816_GTV_MASK                     (0x4U)
+#define UART_IS7816_GTV_SHIFT                    (2U)
+#define UART_IS7816_GTV(x)                       (((uint8_t)(((uint8_t)(x)) << UART_IS7816_GTV_SHIFT)) & UART_IS7816_GTV_MASK)
+#define UART_IS7816_ADT_MASK                     (0x8U)
+#define UART_IS7816_ADT_SHIFT                    (3U)
+#define UART_IS7816_ADT(x)                       (((uint8_t)(((uint8_t)(x)) << UART_IS7816_ADT_SHIFT)) & UART_IS7816_ADT_MASK)
+#define UART_IS7816_INITD_MASK                   (0x10U)
+#define UART_IS7816_INITD_SHIFT                  (4U)
+#define UART_IS7816_INITD(x)                     (((uint8_t)(((uint8_t)(x)) << UART_IS7816_INITD_SHIFT)) & UART_IS7816_INITD_MASK)
+#define UART_IS7816_BWT_MASK                     (0x20U)
+#define UART_IS7816_BWT_SHIFT                    (5U)
+#define UART_IS7816_BWT(x)                       (((uint8_t)(((uint8_t)(x)) << UART_IS7816_BWT_SHIFT)) & UART_IS7816_BWT_MASK)
+#define UART_IS7816_CWT_MASK                     (0x40U)
+#define UART_IS7816_CWT_SHIFT                    (6U)
+#define UART_IS7816_CWT(x)                       (((uint8_t)(((uint8_t)(x)) << UART_IS7816_CWT_SHIFT)) & UART_IS7816_CWT_MASK)
+#define UART_IS7816_WT_MASK                      (0x80U)
+#define UART_IS7816_WT_SHIFT                     (7U)
+#define UART_IS7816_WT(x)                        (((uint8_t)(((uint8_t)(x)) << UART_IS7816_WT_SHIFT)) & UART_IS7816_WT_MASK)
+
+/*! @name WP7816 - UART 7816 Wait Parameter Register */
+#define UART_WP7816_WTX_MASK                     (0xFFU)
+#define UART_WP7816_WTX_SHIFT                    (0U)
+#define UART_WP7816_WTX(x)                       (((uint8_t)(((uint8_t)(x)) << UART_WP7816_WTX_SHIFT)) & UART_WP7816_WTX_MASK)
+
+/*! @name WN7816 - UART 7816 Wait N Register */
+#define UART_WN7816_GTN_MASK                     (0xFFU)
+#define UART_WN7816_GTN_SHIFT                    (0U)
+#define UART_WN7816_GTN(x)                       (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK)
+
+/*! @name WF7816 - UART 7816 Wait FD Register */
+#define UART_WF7816_GTFD_MASK                    (0xFFU)
+#define UART_WF7816_GTFD_SHIFT                   (0U)
+#define UART_WF7816_GTFD(x)                      (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK)
+
+/*! @name ET7816 - UART 7816 Error Threshold Register */
+#define UART_ET7816_RXTHRESHOLD_MASK             (0xFU)
+#define UART_ET7816_RXTHRESHOLD_SHIFT            (0U)
+#define UART_ET7816_RXTHRESHOLD(x)               (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK)
+#define UART_ET7816_TXTHRESHOLD_MASK             (0xF0U)
+#define UART_ET7816_TXTHRESHOLD_SHIFT            (4U)
+#define UART_ET7816_TXTHRESHOLD(x)               (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK)
+
+/*! @name TL7816 - UART 7816 Transmit Length Register */
+#define UART_TL7816_TLEN_MASK                    (0xFFU)
+#define UART_TL7816_TLEN_SHIFT                   (0U)
+#define UART_TL7816_TLEN(x)                      (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK)
+
+/*! @name AP7816A_T0 - UART 7816 ATR Duration Timer Register A */
+#define UART_AP7816A_T0_ADTI_H_MASK              (0xFFU)
+#define UART_AP7816A_T0_ADTI_H_SHIFT             (0U)
+#define UART_AP7816A_T0_ADTI_H(x)                (((uint8_t)(((uint8_t)(x)) << UART_AP7816A_T0_ADTI_H_SHIFT)) & UART_AP7816A_T0_ADTI_H_MASK)
+
+/*! @name AP7816B_T0 - UART 7816 ATR Duration Timer Register B */
+#define UART_AP7816B_T0_ADTI_L_MASK              (0xFFU)
+#define UART_AP7816B_T0_ADTI_L_SHIFT             (0U)
+#define UART_AP7816B_T0_ADTI_L(x)                (((uint8_t)(((uint8_t)(x)) << UART_AP7816B_T0_ADTI_L_SHIFT)) & UART_AP7816B_T0_ADTI_L_MASK)
+
+/*! @name WP7816A_T0 - UART 7816 Wait Parameter Register A */
+#define UART_WP7816A_T0_WI_H_MASK                (0xFFU)
+#define UART_WP7816A_T0_WI_H_SHIFT               (0U)
+#define UART_WP7816A_T0_WI_H(x)                  (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T0_WI_H_SHIFT)) & UART_WP7816A_T0_WI_H_MASK)
+
+/*! @name WP7816B_T0 - UART 7816 Wait Parameter Register B */
+#define UART_WP7816B_T0_WI_L_MASK                (0xFFU)
+#define UART_WP7816B_T0_WI_L_SHIFT               (0U)
+#define UART_WP7816B_T0_WI_L(x)                  (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T0_WI_L_SHIFT)) & UART_WP7816B_T0_WI_L_MASK)
+
+/*! @name WP7816A_T1 - UART 7816 Wait Parameter Register A */
+#define UART_WP7816A_T1_BWI_H_MASK               (0xFFU)
+#define UART_WP7816A_T1_BWI_H_SHIFT              (0U)
+#define UART_WP7816A_T1_BWI_H(x)                 (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T1_BWI_H_SHIFT)) & UART_WP7816A_T1_BWI_H_MASK)
+
+/*! @name WP7816B_T1 - UART 7816 Wait Parameter Register B */
+#define UART_WP7816B_T1_BWI_L_MASK               (0xFFU)
+#define UART_WP7816B_T1_BWI_L_SHIFT              (0U)
+#define UART_WP7816B_T1_BWI_L(x)                 (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T1_BWI_L_SHIFT)) & UART_WP7816B_T1_BWI_L_MASK)
+
+/*! @name WGP7816_T1 - UART 7816 Wait and Guard Parameter Register */
+#define UART_WGP7816_T1_BGI_MASK                 (0xFU)
+#define UART_WGP7816_T1_BGI_SHIFT                (0U)
+#define UART_WGP7816_T1_BGI(x)                   (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_BGI_SHIFT)) & UART_WGP7816_T1_BGI_MASK)
+#define UART_WGP7816_T1_CWI1_MASK                (0xF0U)
+#define UART_WGP7816_T1_CWI1_SHIFT               (4U)
+#define UART_WGP7816_T1_CWI1(x)                  (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_CWI1_SHIFT)) & UART_WGP7816_T1_CWI1_MASK)
+
+/*! @name WP7816C_T1 - UART 7816 Wait Parameter Register C */
+#define UART_WP7816C_T1_CWI2_MASK                (0x1FU)
+#define UART_WP7816C_T1_CWI2_SHIFT               (0U)
+#define UART_WP7816C_T1_CWI2(x)                  (((uint8_t)(((uint8_t)(x)) << UART_WP7816C_T1_CWI2_SHIFT)) & UART_WP7816C_T1_CWI2_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group UART_Register_Masks */
+
+
+/* UART - Peripheral instance base addresses */
+/** Peripheral UART0 base address */
+#define UART0_BASE                               (0x4006A000u)
+/** Peripheral UART0 base pointer */
+#define UART0                                    ((UART_Type *)UART0_BASE)
+/** Peripheral UART1 base address */
+#define UART1_BASE                               (0x4006B000u)
+/** Peripheral UART1 base pointer */
+#define UART1                                    ((UART_Type *)UART1_BASE)
+/** Peripheral UART2 base address */
+#define UART2_BASE                               (0x4006C000u)
+/** Peripheral UART2 base pointer */
+#define UART2                                    ((UART_Type *)UART2_BASE)
+/** Peripheral UART3 base address */
+#define UART3_BASE                               (0x4006D000u)
+/** Peripheral UART3 base pointer */
+#define UART3                                    ((UART_Type *)UART3_BASE)
+/** Peripheral UART4 base address */
+#define UART4_BASE                               (0x400EA000u)
+/** Peripheral UART4 base pointer */
+#define UART4                                    ((UART_Type *)UART4_BASE)
+/** Array initializer of UART peripheral base addresses */
+#define UART_BASE_ADDRS                          { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE }
+/** Array initializer of UART peripheral base pointers */
+#define UART_BASE_PTRS                           { UART0, UART1, UART2, UART3, UART4 }
+/** Interrupt vectors for the UART peripheral type */
+#define UART_RX_TX_IRQS                          { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn, UART3_RX_TX_IRQn, UART4_RX_TX_IRQn }
+#define UART_ERR_IRQS                            { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn, UART3_ERR_IRQn, UART4_ERR_IRQn }
+
+/*!
+ * @}
+ */ /* end of group UART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USB Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBx_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+  __I  uint8_t PERID;                              /**< Peripheral ID register, offset: 0x0 */
+       uint8_t RESERVED_0[3];
+  __I  uint8_t IDCOMP;                             /**< Peripheral ID Complement register, offset: 0x4 */
+       uint8_t RESERVED_1[3];
+  __I  uint8_t REV;                                /**< Peripheral Revision register, offset: 0x8 */
+       uint8_t RESERVED_2[3];
+  __I  uint8_t ADDINFO;                            /**< Peripheral Additional Info register, offset: 0xC */
+       uint8_t RESERVED_3[3];
+  __IO uint8_t OTGISTAT;                           /**< OTG Interrupt Status register, offset: 0x10 */
+       uint8_t RESERVED_4[3];
+  __IO uint8_t OTGICR;                             /**< OTG Interrupt Control register, offset: 0x14 */
+       uint8_t RESERVED_5[3];
+  __IO uint8_t OTGSTAT;                            /**< OTG Status register, offset: 0x18 */
+       uint8_t RESERVED_6[3];
+  __IO uint8_t OTGCTL;                             /**< OTG Control register, offset: 0x1C */
+       uint8_t RESERVED_7[99];
+  __IO uint8_t ISTAT;                              /**< Interrupt Status register, offset: 0x80 */
+       uint8_t RESERVED_8[3];
+  __IO uint8_t INTEN;                              /**< Interrupt Enable register, offset: 0x84 */
+       uint8_t RESERVED_9[3];
+  __IO uint8_t ERRSTAT;                            /**< Error Interrupt Status register, offset: 0x88 */
+       uint8_t RESERVED_10[3];
+  __IO uint8_t ERREN;                              /**< Error Interrupt Enable register, offset: 0x8C */
+       uint8_t RESERVED_11[3];
+  __I  uint8_t STAT;                               /**< Status register, offset: 0x90 */
+       uint8_t RESERVED_12[3];
+  __IO uint8_t CTL;                                /**< Control register, offset: 0x94 */
+       uint8_t RESERVED_13[3];
+  __IO uint8_t ADDR;                               /**< Address register, offset: 0x98 */
+       uint8_t RESERVED_14[3];
+  __IO uint8_t BDTPAGE1;                           /**< BDT Page register 1, offset: 0x9C */
+       uint8_t RESERVED_15[3];
+  __IO uint8_t FRMNUML;                            /**< Frame Number register Low, offset: 0xA0 */
+       uint8_t RESERVED_16[3];
+  __IO uint8_t FRMNUMH;                            /**< Frame Number register High, offset: 0xA4 */
+       uint8_t RESERVED_17[3];
+  __IO uint8_t TOKEN;                              /**< Token register, offset: 0xA8 */
+       uint8_t RESERVED_18[3];
+  __IO uint8_t SOFTHLD;                            /**< SOF Threshold register, offset: 0xAC */
+       uint8_t RESERVED_19[3];
+  __IO uint8_t BDTPAGE2;                           /**< BDT Page Register 2, offset: 0xB0 */
+       uint8_t RESERVED_20[3];
+  __IO uint8_t BDTPAGE3;                           /**< BDT Page Register 3, offset: 0xB4 */
+       uint8_t RESERVED_21[11];
+  struct {                                         /* offset: 0xC0, array step: 0x4 */
+    __IO uint8_t V;                                /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
+         uint8_t RESERVED_0[3];
+  } ENDPT[16];
+  __IO uint8_t USBCTRL;                            /**< USB Control register, offset: 0x100 */
+       uint8_t RESERVED_22[3];
+  __I  uint8_t OBSERVE;                            /**< USB OTG Observe register, offset: 0x104 */
+       uint8_t RESERVED_23[3];
+  __IO uint8_t CONTROL;                            /**< USB OTG Control register, offset: 0x108 */
+       uint8_t RESERVED_24[3];
+  __IO uint8_t USBTRC0;                            /**< USB Transceiver Control register 0, offset: 0x10C */
+       uint8_t RESERVED_25[7];
+  __IO uint8_t USBFRMADJUST;                       /**< Frame Adjust Register, offset: 0x114 */
+       uint8_t RESERVED_26[43];
+  __IO uint8_t CLK_RECOVER_CTRL;                   /**< USB Clock recovery control, offset: 0x140 */
+       uint8_t RESERVED_27[3];
+  __IO uint8_t CLK_RECOVER_IRC_EN;                 /**< IRC48M oscillator enable register, offset: 0x144 */
+       uint8_t RESERVED_28[15];
+  __IO uint8_t CLK_RECOVER_INT_EN;                 /**< Clock recovery combined interrupt enable, offset: 0x154 */
+       uint8_t RESERVED_29[7];
+  __IO uint8_t CLK_RECOVER_INT_STATUS;             /**< Clock recovery separated interrupt status, offset: 0x15C */
+} USBx_Type;
+
+/* ----------------------------------------------------------------------------
+   -- USB Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBx_Register_Masks USB Register Masks
+ * @{
+ */
+
+/*! @name PERID - Peripheral ID register */
+#define USBx_PERID_ID_MASK                        (0x3FU)
+#define USBx_PERID_ID_SHIFT                       (0U)
+#define USBx_PERID_ID(x)                          (((uint8_t)(((uint8_t)(x)) << USBx_PERID_ID_SHIFT)) & USBx_PERID_ID_MASK)
+
+/*! @name IDCOMP - Peripheral ID Complement register */
+#define USBx_IDCOMP_NID_MASK                      (0x3FU)
+#define USBx_IDCOMP_NID_SHIFT                     (0U)
+#define USBx_IDCOMP_NID(x)                        (((uint8_t)(((uint8_t)(x)) << USBx_IDCOMP_NID_SHIFT)) & USBx_IDCOMP_NID_MASK)
+
+/*! @name REV - Peripheral Revision register */
+#define USBx_REV_REV_MASK                         (0xFFU)
+#define USBx_REV_REV_SHIFT                        (0U)
+#define USBx_REV_REV(x)                           (((uint8_t)(((uint8_t)(x)) << USBx_REV_REV_SHIFT)) & USBx_REV_REV_MASK)
+
+/*! @name ADDINFO - Peripheral Additional Info register */
+#define USBx_ADDINFO_IEHOST_MASK                  (0x1U)
+#define USBx_ADDINFO_IEHOST_SHIFT                 (0U)
+#define USBx_ADDINFO_IEHOST(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_ADDINFO_IEHOST_SHIFT)) & USBx_ADDINFO_IEHOST_MASK)
+
+/*! @name OTGISTAT - OTG Interrupt Status register */
+#define USBx_OTGISTAT_AVBUSCHG_MASK               (0x1U)
+#define USBx_OTGISTAT_AVBUSCHG_SHIFT              (0U)
+#define USBx_OTGISTAT_AVBUSCHG(x)                 (((uint8_t)(((uint8_t)(x)) << USBx_OTGISTAT_AVBUSCHG_SHIFT)) & USBx_OTGISTAT_AVBUSCHG_MASK)
+#define USBx_OTGISTAT_B_SESS_CHG_MASK             (0x4U)
+#define USBx_OTGISTAT_B_SESS_CHG_SHIFT            (2U)
+#define USBx_OTGISTAT_B_SESS_CHG(x)               (((uint8_t)(((uint8_t)(x)) << USBx_OTGISTAT_B_SESS_CHG_SHIFT)) & USBx_OTGISTAT_B_SESS_CHG_MASK)
+#define USBx_OTGISTAT_SESSVLDCHG_MASK             (0x8U)
+#define USBx_OTGISTAT_SESSVLDCHG_SHIFT            (3U)
+#define USBx_OTGISTAT_SESSVLDCHG(x)               (((uint8_t)(((uint8_t)(x)) << USBx_OTGISTAT_SESSVLDCHG_SHIFT)) & USBx_OTGISTAT_SESSVLDCHG_MASK)
+#define USBx_OTGISTAT_LINE_STATE_CHG_MASK         (0x20U)
+#define USBx_OTGISTAT_LINE_STATE_CHG_SHIFT        (5U)
+#define USBx_OTGISTAT_LINE_STATE_CHG(x)           (((uint8_t)(((uint8_t)(x)) << USBx_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USBx_OTGISTAT_LINE_STATE_CHG_MASK)
+#define USBx_OTGISTAT_ONEMSEC_MASK                (0x40U)
+#define USBx_OTGISTAT_ONEMSEC_SHIFT               (6U)
+#define USBx_OTGISTAT_ONEMSEC(x)                  (((uint8_t)(((uint8_t)(x)) << USBx_OTGISTAT_ONEMSEC_SHIFT)) & USBx_OTGISTAT_ONEMSEC_MASK)
+#define USBx_OTGISTAT_IDCHG_MASK                  (0x80U)
+#define USBx_OTGISTAT_IDCHG_SHIFT                 (7U)
+#define USBx_OTGISTAT_IDCHG(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_OTGISTAT_IDCHG_SHIFT)) & USBx_OTGISTAT_IDCHG_MASK)
+
+/*! @name OTGICR - OTG Interrupt Control register */
+#define USBx_OTGICR_AVBUSEN_MASK                  (0x1U)
+#define USBx_OTGICR_AVBUSEN_SHIFT                 (0U)
+#define USBx_OTGICR_AVBUSEN(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_OTGICR_AVBUSEN_SHIFT)) & USBx_OTGICR_AVBUSEN_MASK)
+#define USBx_OTGICR_BSESSEN_MASK                  (0x4U)
+#define USBx_OTGICR_BSESSEN_SHIFT                 (2U)
+#define USBx_OTGICR_BSESSEN(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_OTGICR_BSESSEN_SHIFT)) & USBx_OTGICR_BSESSEN_MASK)
+#define USBx_OTGICR_SESSVLDEN_MASK                (0x8U)
+#define USBx_OTGICR_SESSVLDEN_SHIFT               (3U)
+#define USBx_OTGICR_SESSVLDEN(x)                  (((uint8_t)(((uint8_t)(x)) << USBx_OTGICR_SESSVLDEN_SHIFT)) & USBx_OTGICR_SESSVLDEN_MASK)
+#define USBx_OTGICR_LINESTATEEN_MASK              (0x20U)
+#define USBx_OTGICR_LINESTATEEN_SHIFT             (5U)
+#define USBx_OTGICR_LINESTATEEN(x)                (((uint8_t)(((uint8_t)(x)) << USBx_OTGICR_LINESTATEEN_SHIFT)) & USBx_OTGICR_LINESTATEEN_MASK)
+#define USBx_OTGICR_ONEMSECEN_MASK                (0x40U)
+#define USBx_OTGICR_ONEMSECEN_SHIFT               (6U)
+#define USBx_OTGICR_ONEMSECEN(x)                  (((uint8_t)(((uint8_t)(x)) << USBx_OTGICR_ONEMSECEN_SHIFT)) & USBx_OTGICR_ONEMSECEN_MASK)
+#define USBx_OTGICR_IDEN_MASK                     (0x80U)
+#define USBx_OTGICR_IDEN_SHIFT                    (7U)
+#define USBx_OTGICR_IDEN(x)                       (((uint8_t)(((uint8_t)(x)) << USBx_OTGICR_IDEN_SHIFT)) & USBx_OTGICR_IDEN_MASK)
+
+/*! @name OTGSTAT - OTG Status register */
+#define USBx_OTGSTAT_AVBUSVLD_MASK                (0x1U)
+#define USBx_OTGSTAT_AVBUSVLD_SHIFT               (0U)
+#define USBx_OTGSTAT_AVBUSVLD(x)                  (((uint8_t)(((uint8_t)(x)) << USBx_OTGSTAT_AVBUSVLD_SHIFT)) & USBx_OTGSTAT_AVBUSVLD_MASK)
+#define USBx_OTGSTAT_BSESSEND_MASK                (0x4U)
+#define USBx_OTGSTAT_BSESSEND_SHIFT               (2U)
+#define USBx_OTGSTAT_BSESSEND(x)                  (((uint8_t)(((uint8_t)(x)) << USBx_OTGSTAT_BSESSEND_SHIFT)) & USBx_OTGSTAT_BSESSEND_MASK)
+#define USBx_OTGSTAT_SESS_VLD_MASK                (0x8U)
+#define USBx_OTGSTAT_SESS_VLD_SHIFT               (3U)
+#define USBx_OTGSTAT_SESS_VLD(x)                  (((uint8_t)(((uint8_t)(x)) << USBx_OTGSTAT_SESS_VLD_SHIFT)) & USBx_OTGSTAT_SESS_VLD_MASK)
+#define USBx_OTGSTAT_LINESTATESTABLE_MASK         (0x20U)
+#define USBx_OTGSTAT_LINESTATESTABLE_SHIFT        (5U)
+#define USBx_OTGSTAT_LINESTATESTABLE(x)           (((uint8_t)(((uint8_t)(x)) << USBx_OTGSTAT_LINESTATESTABLE_SHIFT)) & USBx_OTGSTAT_LINESTATESTABLE_MASK)
+#define USBx_OTGSTAT_ONEMSECEN_MASK               (0x40U)
+#define USBx_OTGSTAT_ONEMSECEN_SHIFT              (6U)
+#define USBx_OTGSTAT_ONEMSECEN(x)                 (((uint8_t)(((uint8_t)(x)) << USBx_OTGSTAT_ONEMSECEN_SHIFT)) & USBx_OTGSTAT_ONEMSECEN_MASK)
+#define USBx_OTGSTAT_ID_MASK                      (0x80U)
+#define USBx_OTGSTAT_ID_SHIFT                     (7U)
+#define USBx_OTGSTAT_ID(x)                        (((uint8_t)(((uint8_t)(x)) << USBx_OTGSTAT_ID_SHIFT)) & USBx_OTGSTAT_ID_MASK)
+
+/*! @name OTGCTL - OTG Control register */
+#define USBx_OTGCTL_OTGEN_MASK                    (0x4U)
+#define USBx_OTGCTL_OTGEN_SHIFT                   (2U)
+#define USBx_OTGCTL_OTGEN(x)                      (((uint8_t)(((uint8_t)(x)) << USBx_OTGCTL_OTGEN_SHIFT)) & USBx_OTGCTL_OTGEN_MASK)
+#define USBx_OTGCTL_DMLOW_MASK                    (0x10U)
+#define USBx_OTGCTL_DMLOW_SHIFT                   (4U)
+#define USBx_OTGCTL_DMLOW(x)                      (((uint8_t)(((uint8_t)(x)) << USBx_OTGCTL_DMLOW_SHIFT)) & USBx_OTGCTL_DMLOW_MASK)
+#define USBx_OTGCTL_DPLOW_MASK                    (0x20U)
+#define USBx_OTGCTL_DPLOW_SHIFT                   (5U)
+#define USBx_OTGCTL_DPLOW(x)                      (((uint8_t)(((uint8_t)(x)) << USBx_OTGCTL_DPLOW_SHIFT)) & USBx_OTGCTL_DPLOW_MASK)
+#define USBx_OTGCTL_DPHIGH_MASK                   (0x80U)
+#define USBx_OTGCTL_DPHIGH_SHIFT                  (7U)
+#define USBx_OTGCTL_DPHIGH(x)                     (((uint8_t)(((uint8_t)(x)) << USBx_OTGCTL_DPHIGH_SHIFT)) & USBx_OTGCTL_DPHIGH_MASK)
+
+/*! @name ISTAT - Interrupt Status register */
+#define USBx_ISTAT_USBRST_MASK                    (0x1U)
+#define USBx_ISTAT_USBRST_SHIFT                   (0U)
+#define USBx_ISTAT_USBRST_SET(x)                  (((uint8_t)(((uint8_t)(x)) << USBx_ISTAT_USBRST_SHIFT)) & USBx_ISTAT_USBRST_MASK)
+#define USBx_ISTAT_USBRST                         USBx_ISTAT_USBRST_SET(1)
+#define USBx_ISTAT_ERROR_MASK                     (0x2U)
+#define USBx_ISTAT_ERROR_SHIFT                    (1U)
+#define USBx_ISTAT_ERROR_SET(x)                   (((uint8_t)(((uint8_t)(x)) << USBx_ISTAT_ERROR_SHIFT)) & USBx_ISTAT_ERROR_MASK)
+#define USBx_ISTAT_ERROR                          USBx_ISTAT_ERROR_SET(1)
+#define USBx_ISTAT_SOFTOK_MASK                    (0x4U)
+#define USBx_ISTAT_SOFTOK_SHIFT                   (2U)
+#define USBx_ISTAT_SOFTOK_SET(x)                  (((uint8_t)(((uint8_t)(x)) << USBx_ISTAT_SOFTOK_SHIFT)) & USBx_ISTAT_SOFTOK_MASK)
+#define USBx_ISTAT_SOFTOK                         USBx_ISTAT_SOFTOK_SET(1)
+#define USBx_ISTAT_TOKDNE_MASK                    (0x8U)
+#define USBx_ISTAT_TOKDNE_SHIFT                   (3U)
+#define USBx_ISTAT_TOKDNE_SET(x)                  (((uint8_t)(((uint8_t)(x)) << USBx_ISTAT_TOKDNE_SHIFT)) & USBx_ISTAT_TOKDNE_MASK)
+#define USBx_ISTAT_TOKDNE                         USBx_ISTAT_TOKDNE_SET(1)
+#define USBx_ISTAT_SLEEP_MASK                     (0x10U)
+#define USBx_ISTAT_SLEEP_SHIFT                    (4U)
+#define USBx_ISTAT_SLEEP_SET(x)                   (((uint8_t)(((uint8_t)(x)) << USBx_ISTAT_SLEEP_SHIFT)) & USBx_ISTAT_SLEEP_MASK)
+#define USBx_ISTAT_SLEEP                          USBx_ISTAT_SLEEP_SET(1)
+#define USBx_ISTAT_RESUME_MASK                    (0x20U)
+#define USBx_ISTAT_RESUME_SHIFT                   (5U)
+#define USBx_ISTAT_RESUME_SET(x)                  (((uint8_t)(((uint8_t)(x)) << USBx_ISTAT_RESUME_SHIFT)) & USBx_ISTAT_RESUME_MASK)
+#define USBx_ISTAT_RESUME                         USBx_ISTAT_RESUME_SET(1)
+#define USBx_ISTAT_ATTACH_MASK                    (0x40U)
+#define USBx_ISTAT_ATTACH_SHIFT                   (6U)
+#define USBx_ISTAT_ATTACH(x)                      (((uint8_t)(((uint8_t)(x)) << USBx_ISTAT_ATTACH_SHIFT)) & USBx_ISTAT_ATTACH_MASK)
+#define USBx_ISTAT_STALL_MASK                     (0x80U)
+#define USBx_ISTAT_STALL_SHIFT                    (7U)
+#define USBx_ISTAT_STALL_SET(x)                   (((uint8_t)(((uint8_t)(x)) << USBx_ISTAT_STALL_SHIFT)) & USBx_ISTAT_STALL_MASK)
+#define USBx_ISTAT_STALL                          USBx_ISTAT_STALL_SET(1) 
+
+/*! @name INTEN - Interrupt Enable register */
+#define USBx_INTEN_USBRSTEN_MASK                  (0x1U)
+#define USBx_INTEN_USBRSTEN_SHIFT                 (0U)
+#define USBx_INTEN_USBRSTEN_SET(x)                (((uint8_t)(((uint8_t)(x)) << USBx_INTEN_USBRSTEN_SHIFT)) & USBx_INTEN_USBRSTEN_MASK)
+#define USBx_INTEN_USBRSTEN                       USBx_INTEN_USBRSTEN_SET(1)
+#define USBx_INTEN_ERROREN_MASK                   (0x2U)
+#define USBx_INTEN_ERROREN_SHIFT                  (1U)
+#define USBx_INTEN_ERROREN_SET(x)                 (((uint8_t)(((uint8_t)(x)) << USBx_INTEN_ERROREN_SHIFT)) & USBx_INTEN_ERROREN_MASK)
+#define USBx_INTEN_ERROREN                        USBx_INTEN_ERROREN_SET(1)
+#define USBx_INTEN_SOFTOKEN_MASK                  (0x4U)
+#define USBx_INTEN_SOFTOKEN_SHIFT                 (2U)
+#define USBx_INTEN_SOFTOKEN_SET(x)                (((uint8_t)(((uint8_t)(x)) << USBx_INTEN_SOFTOKEN_SHIFT)) & USBx_INTEN_SOFTOKEN_MASK)
+#define USBx_INTEN_SOFTOKEN                       USBx_INTEN_SOFTOKEN_SET(1)
+#define USBx_INTEN_TOKDNEEN_MASK                  (0x8U)
+#define USBx_INTEN_TOKDNEEN_SHIFT                 (3U)
+#define USBx_INTEN_TOKDNEEN_SET(x)                (((uint8_t)(((uint8_t)(x)) << USBx_INTEN_TOKDNEEN_SHIFT)) & USBx_INTEN_TOKDNEEN_MASK)
+#define USBx_INTEN_TOKDNEEN                       USBx_INTEN_TOKDNEEN_SET(1)
+#define USBx_INTEN_SLEEPEN_MASK                   (0x10U)
+#define USBx_INTEN_SLEEPEN_SHIFT                  (4U)
+#define USBx_INTEN_SLEEPEN_SET(x)                 (((uint8_t)(((uint8_t)(x)) << USBx_INTEN_SLEEPEN_SHIFT)) & USBx_INTEN_SLEEPEN_MASK)
+#define USBx_INTEN_SLEEPEN                        USBx_INTEN_SLEEPEN_SET(1)
+#define USBx_INTEN_RESUMEEN_MASK                  (0x20U)
+#define USBx_INTEN_RESUMEEN_SHIFT                 (5U)
+#define USBx_INTEN_RESUMEEN_SET(x)                (((uint8_t)(((uint8_t)(x)) << USBx_INTEN_RESUMEEN_SHIFT)) & USBx_INTEN_RESUMEEN_MASK)
+#define USBx_INTEN_RESUMEEN                       USBx_INTEN_RESUMEEN_SET(1)
+#define USBx_INTEN_ATTACHEN_MASK                  (0x40U)
+#define USBx_INTEN_ATTACHEN_SHIFT                 (6U)
+#define USBx_INTEN_ATTACHEN(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_INTEN_ATTACHEN_SHIFT)) & USBx_INTEN_ATTACHEN_MASK)
+#define USBx_INTEN_STALLEN_MASK                   (0x80U)
+#define USBx_INTEN_STALLEN_SHIFT                  (7U)
+#define USBx_INTEN_STALLEN_SET(x)                 (((uint8_t)(((uint8_t)(x)) << USBx_INTEN_STALLEN_SHIFT)) & USBx_INTEN_STALLEN_MASK)
+#define USBx_INTEN_STALLEN                        USBx_INTEN_STALLEN_SET(1)
+
+/*! @name ERRSTAT - Error Interrupt Status register */
+#define USBx_ERRSTAT_PIDERR_MASK                  (0x1U)
+#define USBx_ERRSTAT_PIDERR_SHIFT                 (0U)
+#define USBx_ERRSTAT_PIDERR(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_ERRSTAT_PIDERR_SHIFT)) & USBx_ERRSTAT_PIDERR_MASK)
+#define USBx_ERRSTAT_CRC5EOF_MASK                 (0x2U)
+#define USBx_ERRSTAT_CRC5EOF_SHIFT                (1U)
+#define USBx_ERRSTAT_CRC5EOF(x)                   (((uint8_t)(((uint8_t)(x)) << USBx_ERRSTAT_CRC5EOF_SHIFT)) & USBx_ERRSTAT_CRC5EOF_MASK)
+#define USBx_ERRSTAT_CRC16_MASK                   (0x4U)
+#define USBx_ERRSTAT_CRC16_SHIFT                  (2U)
+#define USBx_ERRSTAT_CRC16(x)                     (((uint8_t)(((uint8_t)(x)) << USBx_ERRSTAT_CRC16_SHIFT)) & USBx_ERRSTAT_CRC16_MASK)
+#define USBx_ERRSTAT_DFN8_MASK                    (0x8U)
+#define USBx_ERRSTAT_DFN8_SHIFT                   (3U)
+#define USBx_ERRSTAT_DFN8(x)                      (((uint8_t)(((uint8_t)(x)) << USBx_ERRSTAT_DFN8_SHIFT)) & USBx_ERRSTAT_DFN8_MASK)
+#define USBx_ERRSTAT_BTOERR_MASK                  (0x10U)
+#define USBx_ERRSTAT_BTOERR_SHIFT                 (4U)
+#define USBx_ERRSTAT_BTOERR(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_ERRSTAT_BTOERR_SHIFT)) & USBx_ERRSTAT_BTOERR_MASK)
+#define USBx_ERRSTAT_DMAERR_MASK                  (0x20U)
+#define USBx_ERRSTAT_DMAERR_SHIFT                 (5U)
+#define USBx_ERRSTAT_DMAERR(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_ERRSTAT_DMAERR_SHIFT)) & USBx_ERRSTAT_DMAERR_MASK)
+#define USBx_ERRSTAT_BTSERR_MASK                  (0x80U)
+#define USBx_ERRSTAT_BTSERR_SHIFT                 (7U)
+#define USBx_ERRSTAT_BTSERR(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_ERRSTAT_BTSERR_SHIFT)) & USBx_ERRSTAT_BTSERR_MASK)
+
+/*! @name ERREN - Error Interrupt Enable register */
+#define USBx_ERREN_PIDERREN_MASK                  (0x1U)
+#define USBx_ERREN_PIDERREN_SHIFT                 (0U)
+#define USBx_ERREN_PIDERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_ERREN_PIDERREN_SHIFT)) & USBx_ERREN_PIDERREN_MASK)
+#define USBx_ERREN_CRC5EOFEN_MASK                 (0x2U)
+#define USBx_ERREN_CRC5EOFEN_SHIFT                (1U)
+#define USBx_ERREN_CRC5EOFEN(x)                   (((uint8_t)(((uint8_t)(x)) << USBx_ERREN_CRC5EOFEN_SHIFT)) & USBx_ERREN_CRC5EOFEN_MASK)
+#define USBx_ERREN_CRC16EN_MASK                   (0x4U)
+#define USBx_ERREN_CRC16EN_SHIFT                  (2U)
+#define USBx_ERREN_CRC16EN(x)                     (((uint8_t)(((uint8_t)(x)) << USBx_ERREN_CRC16EN_SHIFT)) & USBx_ERREN_CRC16EN_MASK)
+#define USBx_ERREN_DFN8EN_MASK                    (0x8U)
+#define USBx_ERREN_DFN8EN_SHIFT                   (3U)
+#define USBx_ERREN_DFN8EN(x)                      (((uint8_t)(((uint8_t)(x)) << USBx_ERREN_DFN8EN_SHIFT)) & USBx_ERREN_DFN8EN_MASK)
+#define USBx_ERREN_BTOERREN_MASK                  (0x10U)
+#define USBx_ERREN_BTOERREN_SHIFT                 (4U)
+#define USBx_ERREN_BTOERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_ERREN_BTOERREN_SHIFT)) & USBx_ERREN_BTOERREN_MASK)
+#define USBx_ERREN_DMAERREN_MASK                  (0x20U)
+#define USBx_ERREN_DMAERREN_SHIFT                 (5U)
+#define USBx_ERREN_DMAERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_ERREN_DMAERREN_SHIFT)) & USBx_ERREN_DMAERREN_MASK)
+#define USBx_ERREN_BTSERREN_MASK                  (0x80U)
+#define USBx_ERREN_BTSERREN_SHIFT                 (7U)
+#define USBx_ERREN_BTSERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_ERREN_BTSERREN_SHIFT)) & USBx_ERREN_BTSERREN_MASK)
+
+/*! @name STAT - Status register */
+#define USBx_STAT_ODD_MASK                        (0x4U)
+#define USBx_STAT_ODD_SHIFT                       (2U)
+#define USBx_STAT_ODD(x)                          (((uint8_t)(((uint8_t)(x)) << USBx_STAT_ODD_SHIFT)) & USBx_STAT_ODD_MASK)
+#define USBx_STAT_TX_MASK                         (0x8U)
+#define USBx_STAT_TX_SHIFT                        (3U)
+#define USBx_STAT_TX(x)                           (((uint8_t)(((uint8_t)(x)) << USBx_STAT_TX_SHIFT)) & USBx_STAT_TX_MASK)
+#define USBx_STAT_ENDP_MASK                       (0xF0U)
+#define USBx_STAT_ENDP_SHIFT                      (4U)
+#define USBx_STAT_ENDP(x)                         (((uint8_t)(((uint8_t)(x)) << USBx_STAT_ENDP_SHIFT)) & USBx_STAT_ENDP_MASK)
+
+/*! @name CTL - Control register */
+#define USBx_CTL_USBENSOFEN_MASK                  (0x1U)
+#define USBx_CTL_USBENSOFEN_SHIFT                 (0U)
+#define USBx_CTL_USBENSOFEN_SET(x)                (((uint8_t)(((uint8_t)(x)) << USBx_CTL_USBENSOFEN_SHIFT)) & USBx_CTL_USBENSOFEN_MASK)
+#define USBx_CTL_USBENSOFEN                       USBx_CTL_USBENSOFEN_SET(1)
+#define USBx_CTL_ODDRST_MASK                      (0x2U)
+#define USBx_CTL_ODDRST_SHIFT                     (1U)
+#define USBx_CTL_ODDRST_SET(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_CTL_ODDRST_SHIFT)) & USBx_CTL_ODDRST_MASK)
+#define USBx_CTL_ODDRST                           USBx_CTL_ODDRST_SET(1)
+#define USBx_CTL_RESUME_MASK                      (0x4U)
+#define USBx_CTL_RESUME_SHIFT                     (2U)
+#define USBx_CTL_RESUME_SET(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_CTL_RESUME_SHIFT)) & USBx_CTL_RESUME_MASK)
+#define USBx_CTL_RESUME                           USBx_CTL_RESUME_SET(1)
+#define USBx_CTL_HOSTMODEEN_MASK                  (0x8U)
+#define USBx_CTL_HOSTMODEEN_SHIFT                 (3U)
+#define USBx_CTL_HOSTMODEEN(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_CTL_HOSTMODEEN_SHIFT)) & USBx_CTL_HOSTMODEEN_MASK)
+#define USBx_CTL_RESET_MASK                       (0x10U)
+#define USBx_CTL_RESET_SHIFT                      (4U)
+#define USBx_CTL_RESET(x)                         (((uint8_t)(((uint8_t)(x)) << USBx_CTL_RESET_SHIFT)) & USBx_CTL_RESET_MASK)
+#define USBx_CTL_TXSUSPENDTOKENBUSY_MASK          (0x20U)
+#define USBx_CTL_TXSUSPENDTOKENBUSY_SHIFT         (5U)
+#define USBx_CTL_TXSUSPENDTOKENBUSY_SET(x)        (((uint8_t)(((uint8_t)(x)) << USBx_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USBx_CTL_TXSUSPENDTOKENBUSY_MASK)
+#define USBx_CTL_TXSUSPENDTOKENBUSY               USBx_CTL_TXSUSPENDTOKENBUSY_SET(1)
+#define USBx_CTL_SE0_MASK                         (0x40U)
+#define USBx_CTL_SE0_SHIFT                        (6U)
+#define USBx_CTL_SE0(x)                           (((uint8_t)(((uint8_t)(x)) << USBx_CTL_SE0_SHIFT)) & USBx_CTL_SE0_MASK)
+#define USBx_CTL_JSTATE_MASK                      (0x80U)
+#define USBx_CTL_JSTATE_SHIFT                     (7U)
+#define USBx_CTL_JSTATE(x)                        (((uint8_t)(((uint8_t)(x)) << USBx_CTL_JSTATE_SHIFT)) & USBx_CTL_JSTATE_MASK)
+
+/*! @name ADDR - Address register */
+#define USBx_ADDR_ADDR_MASK                       (0x7FU)
+#define USBx_ADDR_ADDR_SHIFT                      (0U)
+#define USBx_ADDR_ADDR(x)                         (((uint8_t)(((uint8_t)(x)) << USBx_ADDR_ADDR_SHIFT)) & USBx_ADDR_ADDR_MASK)
+#define USBx_ADDR_LSEN_MASK                       (0x80U)
+#define USBx_ADDR_LSEN_SHIFT                      (7U)
+#define USBx_ADDR_LSEN(x)                         (((uint8_t)(((uint8_t)(x)) << USBx_ADDR_LSEN_SHIFT)) & USBx_ADDR_LSEN_MASK)
+
+/*! @name BDTPAGE1 - BDT Page register 1 */
+#define USBx_BDTPAGE1_BDTBA_MASK                  (0xFEU)
+#define USBx_BDTPAGE1_BDTBA_SHIFT                 (1U)
+#define USBx_BDTPAGE1_BDTBA(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_BDTPAGE1_BDTBA_SHIFT)) & USBx_BDTPAGE1_BDTBA_MASK)
+
+/*! @name FRMNUML - Frame Number register Low */
+#define USBx_FRMNUML_FRM_MASK                     (0xFFU)
+#define USBx_FRMNUML_FRM_SHIFT                    (0U)
+#define USBx_FRMNUML_FRM(x)                       (((uint8_t)(((uint8_t)(x)) << USBx_FRMNUML_FRM_SHIFT)) & USBx_FRMNUML_FRM_MASK)
+
+/*! @name FRMNUMH - Frame Number register High */
+#define USBx_FRMNUMH_FRM_MASK                     (0x7U)
+#define USBx_FRMNUMH_FRM_SHIFT                    (0U)
+#define USBx_FRMNUMH_FRM(x)                       (((uint8_t)(((uint8_t)(x)) << USBx_FRMNUMH_FRM_SHIFT)) & USBx_FRMNUMH_FRM_MASK)
+
+/*! @name TOKEN - Token register */
+#define USBx_TOKEN_TOKENENDPT_MASK                (0xFU)
+#define USBx_TOKEN_TOKENENDPT_SHIFT               (0U)
+#define USBx_TOKEN_TOKENENDPT(x)                  (((uint8_t)(((uint8_t)(x)) << USBx_TOKEN_TOKENENDPT_SHIFT)) & USBx_TOKEN_TOKENENDPT_MASK)
+#define USBx_TOKEN_TOKENPID_MASK                  (0xF0U)
+#define USBx_TOKEN_TOKENPID_SHIFT                 (4U)
+#define USBx_TOKEN_TOKENPID(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_TOKEN_TOKENPID_SHIFT)) & USBx_TOKEN_TOKENPID_MASK)
+
+/*! @name SOFTHLD - SOF Threshold register */
+#define USBx_SOFTHLD_CNT_MASK                     (0xFFU)
+#define USBx_SOFTHLD_CNT_SHIFT                    (0U)
+#define USBx_SOFTHLD_CNT(x)                       (((uint8_t)(((uint8_t)(x)) << USBx_SOFTHLD_CNT_SHIFT)) & USBx_SOFTHLD_CNT_MASK)
+
+/*! @name BDTPAGE2 - BDT Page Register 2 */
+#define USBx_BDTPAGE2_BDTBA_MASK                  (0xFFU)
+#define USBx_BDTPAGE2_BDTBA_SHIFT                 (0U)
+#define USBx_BDTPAGE2_BDTBA(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_BDTPAGE2_BDTBA_SHIFT)) & USBx_BDTPAGE2_BDTBA_MASK)
+
+/*! @name BDTPAGE3 - BDT Page Register 3 */
+#define USBx_BDTPAGE3_BDTBA_MASK                  (0xFFU)
+#define USBx_BDTPAGE3_BDTBA_SHIFT                 (0U)
+#define USBx_BDTPAGE3_BDTBA(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_BDTPAGE3_BDTBA_SHIFT)) & USBx_BDTPAGE3_BDTBA_MASK)
+
+/*! @name ENDPT - Endpoint Control register */
+#define USBx_ENDPTn_EPHSHK_MASK                    (0x1U)
+#define USBx_ENDPTn_EPHSHK_SHIFT                   (0U)
+#define USBx_ENDPTn_EPHSHK_SET(x)                      (((uint8_t)(((uint8_t)(x)) << USBx_ENDPTn_EPHSHK_SHIFT)) & USBx_ENDPTn_EPHSHK_MASK)
+#define USBx_ENDPTn_EPHSHK                         USBx_ENDPTn_EPHSHK_SET(1)
+#define USBx_ENDPTn_EPSTALL_MASK                   (0x2U)
+#define USBx_ENDPTn_EPSTALL_SHIFT                  (1U)
+#define USBx_ENDPTn_EPSTALL_SET(x)                 (((uint8_t)(((uint8_t)(x)) << USBx_ENDPTn_EPSTALL_SHIFT)) & USBx_ENDPTn_EPSTALL_MASK)
+#define USBx_ENDPTn_EPSTALL                        USBx_ENDPTn_EPSTALL_SET(1)
+#define USBx_ENDPTn_EPTXEN_MASK                    (0x4U)
+#define USBx_ENDPTn_EPTXEN_SHIFT                   (2U)
+#define USBx_ENDPTn_EPTXEN_SET(x)                  (((uint8_t)(((uint8_t)(x)) << USBx_ENDPTn_EPTXEN_SHIFT)) & USBx_ENDPTn_EPTXEN_MASK)
+#define USBx_ENDPTn_EPTXEN                         USBx_ENDPTn_EPTXEN_SET(1)
+#define USBx_ENDPTn_EPRXEN_MASK                    (0x8U)
+#define USBx_ENDPTn_EPRXEN_SHIFT                   (3U)
+#define USBx_ENDPTn_EPRXEN_SET(x)                  (((uint8_t)(((uint8_t)(x)) << USBx_ENDPTn_EPRXEN_SHIFT)) & USBx_ENDPTn_EPRXEN_MASK)
+#define USBx_ENDPTn_EPRXEN                         USBx_ENDPTn_EPRXEN_SET(1)
+#define USBx_ENDPTn_EPCTLDIS_MASK                  (0x10U)
+#define USBx_ENDPTn_EPCTLDIS_SHIFT                 (4U)
+#define USBx_ENDPTn_EPCTLDIS_SET(x)                (((uint8_t)(((uint8_t)(x)) << USBx_ENDPTn_EPCTLDIS_SHIFT)) & USBx_ENDPTn_EPCTLDIS_MASK)
+#define USBx_ENDPTn_EPCTLDIS                       USBx_ENDPTn_EPCTLDIS_SET(1)
+#define USBx_ENDPTn_RETRYDIS_MASK                  (0x40U)
+#define USBx_ENDPTn_RETRYDIS_SHIFT                 (6U)
+#define USBx_ENDPTn_RETRYDIS(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_ENDPTn_RETRYDIS_SHIFT)) & USBx_ENDPTn_RETRYDIS_MASK)
+#define USBx_ENDPTn_HOSTWOHUB_MASK                 (0x80U)
+#define USBx_ENDPTn_HOSTWOHUB_SHIFT                (7U)
+#define USBx_ENDPTn_HOSTWOHUB(x)                   (((uint8_t)(((uint8_t)(x)) << USBx_ENDPTn_HOSTWOHUB_SHIFT)) & USBx_ENDPTn_HOSTWOHUB_MASK)
+
+/* The count of USBx_ENDPT */
+#define USBx_ENDPTn_COUNT                          (16U)
+
+/*! @name USBCTRL - USB Control register */
+#define USBx_USBCTRL_PDE_MASK                     (0x40U)
+#define USBx_USBCTRL_PDE_SHIFT                    (6U)
+#define USBx_USBCTRL_PDE(x)                       (((uint8_t)(((uint8_t)(x)) << USBx_USBCTRL_PDE_SHIFT)) & USBx_USBCTRL_PDE_MASK)
+#define USBx_USBCTRL_SUSP_MASK                    (0x80U)
+#define USBx_USBCTRL_SUSP_SHIFT                   (7U)
+#define USBx_USBCTRL_SUSP(x)                      (((uint8_t)(((uint8_t)(x)) << USBx_USBCTRL_SUSP_SHIFT)) & USBx_USBCTRL_SUSP_MASK)
+
+/*! @name OBSERVE - USB OTG Observe register */
+#define USBx_OBSERVE_DMPD_MASK                    (0x10U)
+#define USBx_OBSERVE_DMPD_SHIFT                   (4U)
+#define USBx_OBSERVE_DMPD(x)                      (((uint8_t)(((uint8_t)(x)) << USBx_OBSERVE_DMPD_SHIFT)) & USBx_OBSERVE_DMPD_MASK)
+#define USBx_OBSERVE_DPPD_MASK                    (0x40U)
+#define USBx_OBSERVE_DPPD_SHIFT                   (6U)
+#define USBx_OBSERVE_DPPD(x)                      (((uint8_t)(((uint8_t)(x)) << USBx_OBSERVE_DPPD_SHIFT)) & USBx_OBSERVE_DPPD_MASK)
+#define USBx_OBSERVE_DPPU_MASK                    (0x80U)
+#define USBx_OBSERVE_DPPU_SHIFT                   (7U)
+#define USBx_OBSERVE_DPPU(x)                      (((uint8_t)(((uint8_t)(x)) << USBx_OBSERVE_DPPU_SHIFT)) & USBx_OBSERVE_DPPU_MASK)
+
+/*! @name CONTROL - USB OTG Control register */
+#define USBx_CONTROL_DPPULLUPNONOTG_MASK          (0x10U)
+#define USBx_CONTROL_DPPULLUPNONOTG_SHIFT         (4U)
+#define USBx_CONTROL_DPPULLUPNONOTG_SET(x)        (((uint8_t)(((uint8_t)(x)) << USBx_CONTROL_DPPULLUPNONOTG_SHIFT)) & USBx_CONTROL_DPPULLUPNONOTG_MASK)
+#define USBx_CONTROL_DPPULLUPNONOTG               USBx_CONTROL_DPPULLUPNONOTG_SET(1)
+
+/*! @name USBTRC0 - USB Transceiver Control register 0 */
+#define USBx_USBTRC0_USBx_RESUME_INT_MASK          (0x1U)
+#define USBx_USBTRC0_USBx_RESUME_INT_SHIFT         (0U)
+#define USBx_USBTRC0_USBx_RESUME_INT(x)            (((uint8_t)(((uint8_t)(x)) << USBx_USBTRC0_USBx_RESUME_INT_SHIFT)) & USBx_USBTRC0_USBx_RESUME_INT_MASK)
+#define USBx_USBTRC0_SYNC_DET_MASK                (0x2U)
+#define USBx_USBTRC0_SYNC_DET_SHIFT               (1U)
+#define USBx_USBTRC0_SYNC_DET(x)                  (((uint8_t)(((uint8_t)(x)) << USBx_USBTRC0_SYNC_DET_SHIFT)) & USBx_USBTRC0_SYNC_DET_MASK)
+#define USBx_USBTRC0_USBx_CLK_RECOVERY_INT_MASK    (0x4U)
+#define USBx_USBTRC0_USBx_CLK_RECOVERY_INT_SHIFT   (2U)
+#define USBx_USBTRC0_USBx_CLK_RECOVERY_INT(x)      (((uint8_t)(((uint8_t)(x)) << USBx_USBTRC0_USBx_CLK_RECOVERY_INT_SHIFT)) & USBx_USBTRC0_USBx_CLK_RECOVERY_INT_MASK)
+#define USBx_USBTRC0_USBRESMEN_MASK               (0x20U)
+#define USBx_USBTRC0_USBRESMEN_SHIFT              (5U)
+#define USBx_USBTRC0_USBRESMEN(x)                 (((uint8_t)(((uint8_t)(x)) << USBx_USBTRC0_USBRESMEN_SHIFT)) & USBx_USBTRC0_USBRESMEN_MASK)
+#define USBx_USBTRC0_USBRESET_MASK                (0x80U)
+#define USBx_USBTRC0_USBRESET_SHIFT               (7U)
+#define USBx_USBTRC0_USBRESET_SET(x)              (((uint8_t)(((uint8_t)(x)) << USBx_USBTRC0_USBRESET_SHIFT)) & USBx_USBTRC0_USBRESET_MASK)
+#define USBx_USBTRC0_USBRESET                     USBx_USBTRC0_USBRESET_SET(1)
+
+/*! @name USBFRMADJUST - Frame Adjust Register */
+#define USBx_USBFRMADJUST_ADJ_MASK                (0xFFU)
+#define USBx_USBFRMADJUST_ADJ_SHIFT               (0U)
+#define USBx_USBFRMADJUST_ADJ(x)                  (((uint8_t)(((uint8_t)(x)) << USBx_USBFRMADJUST_ADJ_SHIFT)) & USBx_USBFRMADJUST_ADJ_MASK)
+
+/*! @name CLK_RECOVER_CTRL - USB Clock recovery control */
+#define USBx_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U)
+#define USBx_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U)
+#define USBx_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USBx_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USBx_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
+#define USBx_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U)
+#define USBx_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U)
+#define USBx_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USBx_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USBx_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
+#define USBx_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U)
+#define USBx_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U)
+#define USBx_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SET(x) (((uint8_t)(((uint8_t)(x)) << USBx_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USBx_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
+#define USBx_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN        USBx_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SET(1)
+
+/*! @name CLK_RECOVER_IRC_EN - IRC48M oscillator enable register */
+#define USBx_CLK_RECOVER_IRC_EN_REG_EN_MASK       (0x1U)
+#define USBx_CLK_RECOVER_IRC_EN_REG_EN_SHIFT      (0U)
+#define USBx_CLK_RECOVER_IRC_EN_REG_EN_SET(x)     (((uint8_t)(((uint8_t)(x)) << USBx_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)) & USBx_CLK_RECOVER_IRC_EN_REG_EN_MASK)
+#define USBx_CLK_RECOVER_IRC_EN_REG_EN            USBx_CLK_RECOVER_IRC_EN_REG_EN_SET(1)
+#define USBx_CLK_RECOVER_IRC_EN_IRC_EN_MASK       (0x2U)
+#define USBx_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT      (1U)
+#define USBx_CLK_RECOVER_IRC_EN_IRC_EN_SET(x)     (((uint8_t)(((uint8_t)(x)) << USBx_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USBx_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
+#define USBx_CLK_RECOVER_IRC_EN_IRC_EN            USBx_CLK_RECOVER_IRC_EN_IRC_EN_SET(1)
+
+/*! @name CLK_RECOVER_INT_EN - Clock recovery combined interrupt enable */
+#define USBx_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK (0x10U)
+#define USBx_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT (4U)
+#define USBx_CLK_RECOVER_INT_EN_OVF_ERROR_EN(x)   (((uint8_t)(((uint8_t)(x)) << USBx_CLK_RECOVER_INT_EN_OVF_ERROR_EN_SHIFT)) & USBx_CLK_RECOVER_INT_EN_OVF_ERROR_EN_MASK)
+
+/*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */
+#define USBx_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U)
+#define USBx_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U)
+#define USBx_CLK_RECOVER_INT_STATUS_OVF_ERROR(x)  (((uint8_t)(((uint8_t)(x)) << USBx_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USBx_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group USBx_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE                                (0x40072000u)
+/** Peripheral USB0 base pointer */
+#define USB0                                     ((USBx_Type *)USB0_BASE)
+/** Array initializer of USB peripheral base addresses */
+#define USBx_BASE_ADDRS                           { USB0_BASE }
+/** Array initializer of USB peripheral base pointers */
+#define USBx_BASE_PTRS                            { USB0 }
+/** Interrupt vectors for the USB peripheral type */
+#define USBx_IRQS                                 { USB_OTG_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USBx_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USBDCD Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
+ * @{
+ */
+
+/** USBDCD - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CONTROL;                           /**< Control register, offset: 0x0 */
+  __IO uint32_t CLOCK;                             /**< Clock register, offset: 0x4 */
+  __I  uint32_t STATUS;                            /**< Status register, offset: 0x8 */
+  __IO uint32_t SIGNAL_OVERRIDE;                   /**< Signal Override Register, offset: 0xC */
+  __IO uint32_t TIMER0;                            /**< TIMER0 register, offset: 0x10 */
+  __IO uint32_t TIMER1;                            /**< TIMER1 register, offset: 0x14 */
+  union {                                          /* offset: 0x18 */
+    __IO uint32_t TIMER2_BC11;                       /**< TIMER2_BC11 register, offset: 0x18 */
+    __IO uint32_t TIMER2_BC12;                       /**< TIMER2_BC12 register, offset: 0x18 */
+  };
+} USBDCD_Type;
+
+/* ----------------------------------------------------------------------------
+   -- USBDCD Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
+ * @{
+ */
+
+/*! @name CONTROL - Control register */
+#define USBDCD_CONTROL_IACK_MASK                 (0x1U)
+#define USBDCD_CONTROL_IACK_SHIFT                (0U)
+#define USBDCD_CONTROL_IACK(x)                   (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IACK_SHIFT)) & USBDCD_CONTROL_IACK_MASK)
+#define USBDCD_CONTROL_IF_MASK                   (0x100U)
+#define USBDCD_CONTROL_IF_SHIFT                  (8U)
+#define USBDCD_CONTROL_IF(x)                     (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IF_SHIFT)) & USBDCD_CONTROL_IF_MASK)
+#define USBDCD_CONTROL_IE_MASK                   (0x10000U)
+#define USBDCD_CONTROL_IE_SHIFT                  (16U)
+#define USBDCD_CONTROL_IE(x)                     (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IE_SHIFT)) & USBDCD_CONTROL_IE_MASK)
+#define USBDCD_CONTROL_BC12_MASK                 (0x20000U)
+#define USBDCD_CONTROL_BC12_SHIFT                (17U)
+#define USBDCD_CONTROL_BC12(x)                   (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_BC12_SHIFT)) & USBDCD_CONTROL_BC12_MASK)
+#define USBDCD_CONTROL_START_MASK                (0x1000000U)
+#define USBDCD_CONTROL_START_SHIFT               (24U)
+#define USBDCD_CONTROL_START(x)                  (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_START_SHIFT)) & USBDCD_CONTROL_START_MASK)
+#define USBDCD_CONTROL_SR_MASK                   (0x2000000U)
+#define USBDCD_CONTROL_SR_SHIFT                  (25U)
+#define USBDCD_CONTROL_SR(x)                     (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_SR_SHIFT)) & USBDCD_CONTROL_SR_MASK)
+
+/*! @name CLOCK - Clock register */
+#define USBDCD_CLOCK_CLOCK_UNIT_MASK             (0x1U)
+#define USBDCD_CLOCK_CLOCK_UNIT_SHIFT            (0U)
+#define USBDCD_CLOCK_CLOCK_UNIT(x)               (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBDCD_CLOCK_CLOCK_UNIT_MASK)
+#define USBDCD_CLOCK_CLOCK_SPEED_MASK            (0xFFCU)
+#define USBDCD_CLOCK_CLOCK_SPEED_SHIFT           (2U)
+#define USBDCD_CLOCK_CLOCK_SPEED(x)              (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBDCD_CLOCK_CLOCK_SPEED_MASK)
+
+/*! @name STATUS - Status register */
+#define USBDCD_STATUS_SEQ_RES_MASK               (0x30000U)
+#define USBDCD_STATUS_SEQ_RES_SHIFT              (16U)
+#define USBDCD_STATUS_SEQ_RES(x)                 (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_RES_SHIFT)) & USBDCD_STATUS_SEQ_RES_MASK)
+#define USBDCD_STATUS_SEQ_STAT_MASK              (0xC0000U)
+#define USBDCD_STATUS_SEQ_STAT_SHIFT             (18U)
+#define USBDCD_STATUS_SEQ_STAT(x)                (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_STAT_SHIFT)) & USBDCD_STATUS_SEQ_STAT_MASK)
+#define USBDCD_STATUS_ERR_MASK                   (0x100000U)
+#define USBDCD_STATUS_ERR_SHIFT                  (20U)
+#define USBDCD_STATUS_ERR(x)                     (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ERR_SHIFT)) & USBDCD_STATUS_ERR_MASK)
+#define USBDCD_STATUS_TO_MASK                    (0x200000U)
+#define USBDCD_STATUS_TO_SHIFT                   (21U)
+#define USBDCD_STATUS_TO(x)                      (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_TO_SHIFT)) & USBDCD_STATUS_TO_MASK)
+#define USBDCD_STATUS_ACTIVE_MASK                (0x400000U)
+#define USBDCD_STATUS_ACTIVE_SHIFT               (22U)
+#define USBDCD_STATUS_ACTIVE(x)                  (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ACTIVE_SHIFT)) & USBDCD_STATUS_ACTIVE_MASK)
+
+/*! @name SIGNAL_OVERRIDE - Signal Override Register */
+#define USBDCD_SIGNAL_OVERRIDE_PS_MASK           (0x3U)
+#define USBDCD_SIGNAL_OVERRIDE_PS_SHIFT          (0U)
+#define USBDCD_SIGNAL_OVERRIDE_PS(x)             (((uint32_t)(((uint32_t)(x)) << USBDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBDCD_SIGNAL_OVERRIDE_PS_MASK)
+
+/*! @name TIMER0 - TIMER0 register */
+#define USBDCD_TIMER0_TUNITCON_MASK              (0xFFFU)
+#define USBDCD_TIMER0_TUNITCON_SHIFT             (0U)
+#define USBDCD_TIMER0_TUNITCON(x)                (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TUNITCON_SHIFT)) & USBDCD_TIMER0_TUNITCON_MASK)
+#define USBDCD_TIMER0_TSEQ_INIT_MASK             (0x3FF0000U)
+#define USBDCD_TIMER0_TSEQ_INIT_SHIFT            (16U)
+#define USBDCD_TIMER0_TSEQ_INIT(x)               (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBDCD_TIMER0_TSEQ_INIT_MASK)
+
+/*! @name TIMER1 - TIMER1 register */
+#define USBDCD_TIMER1_TVDPSRC_ON_MASK            (0x3FFU)
+#define USBDCD_TIMER1_TVDPSRC_ON_SHIFT           (0U)
+#define USBDCD_TIMER1_TVDPSRC_ON(x)              (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBDCD_TIMER1_TVDPSRC_ON_MASK)
+#define USBDCD_TIMER1_TDCD_DBNC_MASK             (0x3FF0000U)
+#define USBDCD_TIMER1_TDCD_DBNC_SHIFT            (16U)
+#define USBDCD_TIMER1_TDCD_DBNC(x)               (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBDCD_TIMER1_TDCD_DBNC_MASK)
+
+/*! @name TIMER2_BC11 - TIMER2_BC11 register */
+#define USBDCD_TIMER2_BC11_CHECK_DM_MASK         (0xFU)
+#define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT        (0U)
+#define USBDCD_TIMER2_BC11_CHECK_DM(x)           (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBDCD_TIMER2_BC11_CHECK_DM_MASK)
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK      (0x3FF0000U)
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT     (16U)
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON(x)        (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
+
+/*! @name TIMER2_BC12 - TIMER2_BC12 register */
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK       (0x3FFU)
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT      (0U)
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON(x)         (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK  (0x3FF0000U)
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x)    (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Register_Masks */
+
+
+/* USBDCD - Peripheral instance base addresses */
+/** Peripheral USBDCD base address */
+#define USBDCD_BASE                              (0x40035000u)
+/** Peripheral USBDCD base pointer */
+#define USBDCD                                   ((USBDCD_Type *)USBDCD_BASE)
+/** Array initializer of USBDCD peripheral base addresses */
+#define USBDCD_BASE_ADDRS                        { USBDCD_BASE }
+/** Array initializer of USBDCD peripheral base pointers */
+#define USBDCD_BASE_PTRS                         { USBDCD }
+/** Interrupt vectors for the USBDCD peripheral type */
+#define USBDCD_IRQS                              { USBDCD_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USBDCD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USBHS Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBHS_Peripheral_Access_Layer USBHS Peripheral Access Layer
+ * @{
+ */
+
+/** USBHS - Register Layout Typedef */
+typedef struct {
+  __I  uint32_t ID;                                /**< Identification Register, offset: 0x0 */
+  __I  uint32_t HWGENERAL;                         /**< General Hardware Parameters Register, offset: 0x4 */
+  __I  uint32_t HWHOST;                            /**< Host Hardware Parameters Register, offset: 0x8 */
+  __I  uint32_t HWDEVICE;                          /**< Device Hardware Parameters Register, offset: 0xC */
+  __I  uint32_t HWTXBUF;                           /**< Transmit Buffer Hardware Parameters Register, offset: 0x10 */
+  __I  uint32_t HWRXBUF;                           /**< Receive Buffer Hardware Parameters Register, offset: 0x14 */
+       uint8_t RESERVED_0[104];
+  __IO uint32_t GPTIMER0LD;                        /**< General Purpose Timer n Load Register, offset: 0x80 */
+  __IO uint32_t GPTIMER0CTL;                       /**< General Purpose Timer n Control Register, offset: 0x84 */
+  __IO uint32_t GPTIMER1LD;                        /**< General Purpose Timer n Load Register, offset: 0x88 */
+  __IO uint32_t GPTIMER1CTL;                       /**< General Purpose Timer n Control Register, offset: 0x8C */
+  __IO uint32_t USBx_SBUSCFG;                       /**< System Bus Interface Configuration Register, offset: 0x90 */
+       uint8_t RESERVED_1[108];
+  __I  uint32_t HCIVERSION;                        /**< Host Controller Interface Version and Capability Registers Length Register, offset: 0x100 */
+  __I  uint32_t HCSPARAMS;                         /**< Host Controller Structural Parameters Register, offset: 0x104 */
+  __I  uint32_t HCCPARAMS;                         /**< Host Controller Capability Parameters Register, offset: 0x108 */
+       uint8_t RESERVED_2[22];
+  __I  uint16_t DCIVERSION;                        /**< Device Controller Interface Version, offset: 0x122 */
+  __I  uint32_t DCCPARAMS;                         /**< Device Controller Capability Parameters, offset: 0x124 */
+       uint8_t RESERVED_3[24];
+  __IO uint32_t USBCMD;                            /**< USB Command Register, offset: 0x140 */
+  __IO uint32_t USBSTS;                            /**< USB Status Register, offset: 0x144 */
+  __IO uint32_t USBINTR;                           /**< USB Interrupt Enable Register, offset: 0x148 */
+  __IO uint32_t FRINDEX;                           /**< Frame Index Register, offset: 0x14C */
+       uint8_t RESERVED_4[4];
+  union {                                          /* offset: 0x154 */
+    __IO uint32_t DEVICEADDR;                        /**< Device Address Register, offset: 0x154 */
+    __IO uint32_t PERIODICLISTBASE;                  /**< Periodic Frame List Base Address Register, offset: 0x154 */
+  };
+  union {                                          /* offset: 0x158 */
+    __IO uint32_t ASYNCLISTADDR;                     /**< Current Asynchronous List Address Register, offset: 0x158 */
+    __IO uint32_t EPLISTADDR;                        /**< Endpoint List Address Register, offset: 0x158 */
+  };
+  __I  uint32_t TTCTRL;                            /**< Host TT Asynchronous Buffer Control, offset: 0x15C */
+  __IO uint32_t BURSTSIZE;                         /**< Master Interface Data Burst Size Register, offset: 0x160 */
+  __IO uint32_t TXFILLTUNING;                      /**< Transmit FIFO Tuning Control Register, offset: 0x164 */
+       uint8_t RESERVED_5[16];
+  __IO uint32_t ENDPTNAK;                          /**< Endpoint NAK Register, offset: 0x178 */
+  __IO uint32_t ENDPTNAKEN;                        /**< Endpoint NAK Enable Register, offset: 0x17C */
+       uint32_t CONFIGFLAG;                        /**< Configure Flag Register, offset: 0x180 */
+  __IO uint32_t PORTSC1;                           /**< Port Status and Control Registers, offset: 0x184 */
+       uint8_t RESERVED_6[28];
+  __IO uint32_t OTGSC;                             /**< On-the-Go Status and Control Register, offset: 0x1A4 */
+  __IO uint32_t USBMODE;                           /**< USB Mode Register, offset: 0x1A8 */
+  __IO uint32_t EPSETUPSR;                         /**< Endpoint Setup Status Register, offset: 0x1AC */
+  __IO uint32_t EPPRIME;                           /**< Endpoint Initialization Register, offset: 0x1B0 */
+  __IO uint32_t EPFLUSH;                           /**< Endpoint Flush Register, offset: 0x1B4 */
+  __I  uint32_t EPSR;                              /**< Endpoint Status Register, offset: 0x1B8 */
+  __IO uint32_t EPCOMPLETE;                        /**< Endpoint Complete Register, offset: 0x1BC */
+  __IO uint32_t EPCR0;                             /**< Endpoint Control Register 0, offset: 0x1C0 */
+  __IO uint32_t EPCR[7];                           /**< Endpoint Control Register n, array offset: 0x1C4, array step: 0x4 */
+       uint8_t RESERVED_7[32];
+  __IO uint32_t USBGENCTRL;                        /**< USB General Control Register, offset: 0x200 */
+} USBHS_Type;
+
+/* ----------------------------------------------------------------------------
+   -- USBHS Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBHS_Register_Masks USBHS Register Masks
+ * @{
+ */
+
+/*! @name ID - Identification Register */
+#define USBHS_ID_ID_MASK                         (0x3FU)
+#define USBHS_ID_ID_SHIFT                        (0U)
+#define USBHS_ID_ID(x)                           (((uint32_t)(((uint32_t)(x)) << USBHS_ID_ID_SHIFT)) & USBHS_ID_ID_MASK)
+#define USBHS_ID_NID_MASK                        (0x3F00U)
+#define USBHS_ID_NID_SHIFT                       (8U)
+#define USBHS_ID_NID(x)                          (((uint32_t)(((uint32_t)(x)) << USBHS_ID_NID_SHIFT)) & USBHS_ID_NID_MASK)
+#define USBHS_ID_TAG_MASK                        (0x1F0000U)
+#define USBHS_ID_TAG_SHIFT                       (16U)
+#define USBHS_ID_TAG(x)                          (((uint32_t)(((uint32_t)(x)) << USBHS_ID_TAG_SHIFT)) & USBHS_ID_TAG_MASK)
+#define USBHS_ID_REVISION_MASK                   (0x1E00000U)
+#define USBHS_ID_REVISION_SHIFT                  (21U)
+#define USBHS_ID_REVISION(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_ID_REVISION_SHIFT)) & USBHS_ID_REVISION_MASK)
+#define USBHS_ID_VERSION_MASK                    (0x1E000000U)
+#define USBHS_ID_VERSION_SHIFT                   (25U)
+#define USBHS_ID_VERSION(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_ID_VERSION_SHIFT)) & USBHS_ID_VERSION_MASK)
+#define USBHS_ID_VERSIONID_MASK                  (0xE0000000U)
+#define USBHS_ID_VERSIONID_SHIFT                 (29U)
+#define USBHS_ID_VERSIONID(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_ID_VERSIONID_SHIFT)) & USBHS_ID_VERSIONID_MASK)
+
+/*! @name HWGENERAL - General Hardware Parameters Register */
+#define USBHS_HWGENERAL_PHYW_MASK                (0x30U)
+#define USBHS_HWGENERAL_PHYW_SHIFT               (4U)
+#define USBHS_HWGENERAL_PHYW(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_PHYW_SHIFT)) & USBHS_HWGENERAL_PHYW_MASK)
+#define USBHS_HWGENERAL_PHYM_MASK                (0x1C0U)
+#define USBHS_HWGENERAL_PHYM_SHIFT               (6U)
+#define USBHS_HWGENERAL_PHYM(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_PHYM_SHIFT)) & USBHS_HWGENERAL_PHYM_MASK)
+#define USBHS_HWGENERAL_SM_MASK                  (0x600U)
+#define USBHS_HWGENERAL_SM_SHIFT                 (9U)
+#define USBHS_HWGENERAL_SM(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_SM_SHIFT)) & USBHS_HWGENERAL_SM_MASK)
+
+/*! @name HWHOST - Host Hardware Parameters Register */
+#define USBHS_HWHOST_HC_MASK                     (0x1U)
+#define USBHS_HWHOST_HC_SHIFT                    (0U)
+#define USBHS_HWHOST_HC(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_HC_SHIFT)) & USBHS_HWHOST_HC_MASK)
+#define USBHS_HWHOST_NPORT_MASK                  (0xEU)
+#define USBHS_HWHOST_NPORT_SHIFT                 (1U)
+#define USBHS_HWHOST_NPORT(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_NPORT_SHIFT)) & USBHS_HWHOST_NPORT_MASK)
+#define USBHS_HWHOST_TTASY_MASK                  (0xFF0000U)
+#define USBHS_HWHOST_TTASY_SHIFT                 (16U)
+#define USBHS_HWHOST_TTASY(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_TTASY_SHIFT)) & USBHS_HWHOST_TTASY_MASK)
+#define USBHS_HWHOST_TTPER_MASK                  (0xFF000000U)
+#define USBHS_HWHOST_TTPER_SHIFT                 (24U)
+#define USBHS_HWHOST_TTPER(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_TTPER_SHIFT)) & USBHS_HWHOST_TTPER_MASK)
+
+/*! @name HWDEVICE - Device Hardware Parameters Register */
+#define USBHS_HWDEVICE_DC_MASK                   (0x1U)
+#define USBHS_HWDEVICE_DC_SHIFT                  (0U)
+#define USBHS_HWDEVICE_DC(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_HWDEVICE_DC_SHIFT)) & USBHS_HWDEVICE_DC_MASK)
+#define USBHS_HWDEVICE_DEVEP_MASK                (0x3EU)
+#define USBHS_HWDEVICE_DEVEP_SHIFT               (1U)
+#define USBHS_HWDEVICE_DEVEP(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_HWDEVICE_DEVEP_SHIFT)) & USBHS_HWDEVICE_DEVEP_MASK)
+
+/*! @name HWTXBUF - Transmit Buffer Hardware Parameters Register */
+#define USBHS_HWTXBUF_TXBURST_MASK               (0xFFU)
+#define USBHS_HWTXBUF_TXBURST_SHIFT              (0U)
+#define USBHS_HWTXBUF_TXBURST(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXBURST_SHIFT)) & USBHS_HWTXBUF_TXBURST_MASK)
+#define USBHS_HWTXBUF_TXADD_MASK                 (0xFF00U)
+#define USBHS_HWTXBUF_TXADD_SHIFT                (8U)
+#define USBHS_HWTXBUF_TXADD(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXADD_SHIFT)) & USBHS_HWTXBUF_TXADD_MASK)
+#define USBHS_HWTXBUF_TXCHANADD_MASK             (0xFF0000U)
+#define USBHS_HWTXBUF_TXCHANADD_SHIFT            (16U)
+#define USBHS_HWTXBUF_TXCHANADD(x)               (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXCHANADD_SHIFT)) & USBHS_HWTXBUF_TXCHANADD_MASK)
+#define USBHS_HWTXBUF_TXLC_MASK                  (0x80000000U)
+#define USBHS_HWTXBUF_TXLC_SHIFT                 (31U)
+#define USBHS_HWTXBUF_TXLC(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXLC_SHIFT)) & USBHS_HWTXBUF_TXLC_MASK)
+
+/*! @name HWRXBUF - Receive Buffer Hardware Parameters Register */
+#define USBHS_HWRXBUF_RXBURST_MASK               (0xFFU)
+#define USBHS_HWRXBUF_RXBURST_SHIFT              (0U)
+#define USBHS_HWRXBUF_RXBURST(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_HWRXBUF_RXBURST_SHIFT)) & USBHS_HWRXBUF_RXBURST_MASK)
+#define USBHS_HWRXBUF_RXADD_MASK                 (0xFF00U)
+#define USBHS_HWRXBUF_RXADD_SHIFT                (8U)
+#define USBHS_HWRXBUF_RXADD(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_HWRXBUF_RXADD_SHIFT)) & USBHS_HWRXBUF_RXADD_MASK)
+
+/*! @name GPTIMER0LD - General Purpose Timer n Load Register */
+#define USBHS_GPTIMER0LD_GPTLD_MASK              (0xFFFFFFU)
+#define USBHS_GPTIMER0LD_GPTLD_SHIFT             (0U)
+#define USBHS_GPTIMER0LD_GPTLD(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0LD_GPTLD_SHIFT)) & USBHS_GPTIMER0LD_GPTLD_MASK)
+
+/*! @name GPTIMER0CTL - General Purpose Timer n Control Register */
+#define USBHS_GPTIMER0CTL_GPTCNT_MASK            (0xFFFFFFU)
+#define USBHS_GPTIMER0CTL_GPTCNT_SHIFT           (0U)
+#define USBHS_GPTIMER0CTL_GPTCNT(x)              (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_GPTCNT_SHIFT)) & USBHS_GPTIMER0CTL_GPTCNT_MASK)
+#define USBHS_GPTIMER0CTL_MODE_MASK              (0x1000000U)
+#define USBHS_GPTIMER0CTL_MODE_SHIFT             (24U)
+#define USBHS_GPTIMER0CTL_MODE(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_MODE_SHIFT)) & USBHS_GPTIMER0CTL_MODE_MASK)
+#define USBHS_GPTIMER0CTL_RST_MASK               (0x40000000U)
+#define USBHS_GPTIMER0CTL_RST_SHIFT              (30U)
+#define USBHS_GPTIMER0CTL_RST(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_RST_SHIFT)) & USBHS_GPTIMER0CTL_RST_MASK)
+#define USBHS_GPTIMER0CTL_RUN_MASK               (0x80000000U)
+#define USBHS_GPTIMER0CTL_RUN_SHIFT              (31U)
+#define USBHS_GPTIMER0CTL_RUN(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_RUN_SHIFT)) & USBHS_GPTIMER0CTL_RUN_MASK)
+
+/*! @name GPTIMER1LD - General Purpose Timer n Load Register */
+#define USBHS_GPTIMER1LD_GPTLD_MASK              (0xFFFFFFU)
+#define USBHS_GPTIMER1LD_GPTLD_SHIFT             (0U)
+#define USBHS_GPTIMER1LD_GPTLD(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1LD_GPTLD_SHIFT)) & USBHS_GPTIMER1LD_GPTLD_MASK)
+
+/*! @name GPTIMER1CTL - General Purpose Timer n Control Register */
+#define USBHS_GPTIMER1CTL_GPTCNT_MASK            (0xFFFFFFU)
+#define USBHS_GPTIMER1CTL_GPTCNT_SHIFT           (0U)
+#define USBHS_GPTIMER1CTL_GPTCNT(x)              (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_GPTCNT_SHIFT)) & USBHS_GPTIMER1CTL_GPTCNT_MASK)
+#define USBHS_GPTIMER1CTL_MODE_MASK              (0x1000000U)
+#define USBHS_GPTIMER1CTL_MODE_SHIFT             (24U)
+#define USBHS_GPTIMER1CTL_MODE(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_MODE_SHIFT)) & USBHS_GPTIMER1CTL_MODE_MASK)
+#define USBHS_GPTIMER1CTL_RST_MASK               (0x40000000U)
+#define USBHS_GPTIMER1CTL_RST_SHIFT              (30U)
+#define USBHS_GPTIMER1CTL_RST(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_RST_SHIFT)) & USBHS_GPTIMER1CTL_RST_MASK)
+#define USBHS_GPTIMER1CTL_RUN_MASK               (0x80000000U)
+#define USBHS_GPTIMER1CTL_RUN_SHIFT              (31U)
+#define USBHS_GPTIMER1CTL_RUN(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_RUN_SHIFT)) & USBHS_GPTIMER1CTL_RUN_MASK)
+
+/*! @name USBx_SBUSCFG - System Bus Interface Configuration Register */
+#define USBHS_USBx_SBUSCFG_BURSTMODE_MASK         (0x7U)
+#define USBHS_USBx_SBUSCFG_BURSTMODE_SHIFT        (0U)
+#define USBHS_USBx_SBUSCFG_BURSTMODE(x)           (((uint32_t)(((uint32_t)(x)) << USBHS_USBx_SBUSCFG_BURSTMODE_SHIFT)) & USBHS_USBx_SBUSCFG_BURSTMODE_MASK)
+
+/*! @name HCIVERSION - Host Controller Interface Version and Capability Registers Length Register */
+#define USBHS_HCIVERSION_CAPLENGTH_MASK          (0xFFU)
+#define USBHS_HCIVERSION_CAPLENGTH_SHIFT         (0U)
+#define USBHS_HCIVERSION_CAPLENGTH(x)            (((uint32_t)(((uint32_t)(x)) << USBHS_HCIVERSION_CAPLENGTH_SHIFT)) & USBHS_HCIVERSION_CAPLENGTH_MASK)
+#define USBHS_HCIVERSION_HCIVERSION_MASK         (0xFFFF0000U)
+#define USBHS_HCIVERSION_HCIVERSION_SHIFT        (16U)
+#define USBHS_HCIVERSION_HCIVERSION(x)           (((uint32_t)(((uint32_t)(x)) << USBHS_HCIVERSION_HCIVERSION_SHIFT)) & USBHS_HCIVERSION_HCIVERSION_MASK)
+
+/*! @name HCSPARAMS - Host Controller Structural Parameters Register */
+#define USBHS_HCSPARAMS_N_PORTS_MASK             (0xFU)
+#define USBHS_HCSPARAMS_N_PORTS_SHIFT            (0U)
+#define USBHS_HCSPARAMS_N_PORTS(x)               (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PORTS_SHIFT)) & USBHS_HCSPARAMS_N_PORTS_MASK)
+#define USBHS_HCSPARAMS_PPC_MASK                 (0x10U)
+#define USBHS_HCSPARAMS_PPC_SHIFT                (4U)
+#define USBHS_HCSPARAMS_PPC(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PPC_SHIFT)) & USBHS_HCSPARAMS_PPC_MASK)
+#define USBHS_HCSPARAMS_N_PCC_MASK               (0xF00U)
+#define USBHS_HCSPARAMS_N_PCC_SHIFT              (8U)
+#define USBHS_HCSPARAMS_N_PCC(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PCC_SHIFT)) & USBHS_HCSPARAMS_N_PCC_MASK)
+#define USBHS_HCSPARAMS_N_CC_MASK                (0xF000U)
+#define USBHS_HCSPARAMS_N_CC_SHIFT               (12U)
+#define USBHS_HCSPARAMS_N_CC(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_CC_SHIFT)) & USBHS_HCSPARAMS_N_CC_MASK)
+#define USBHS_HCSPARAMS_PI_MASK                  (0x10000U)
+#define USBHS_HCSPARAMS_PI_SHIFT                 (16U)
+#define USBHS_HCSPARAMS_PI(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PI_SHIFT)) & USBHS_HCSPARAMS_PI_MASK)
+#define USBHS_HCSPARAMS_N_PTT_MASK               (0xF00000U)
+#define USBHS_HCSPARAMS_N_PTT_SHIFT              (20U)
+#define USBHS_HCSPARAMS_N_PTT(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PTT_SHIFT)) & USBHS_HCSPARAMS_N_PTT_MASK)
+#define USBHS_HCSPARAMS_N_TT_MASK                (0xF000000U)
+#define USBHS_HCSPARAMS_N_TT_SHIFT               (24U)
+#define USBHS_HCSPARAMS_N_TT(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_TT_SHIFT)) & USBHS_HCSPARAMS_N_TT_MASK)
+
+/*! @name HCCPARAMS - Host Controller Capability Parameters Register */
+#define USBHS_HCCPARAMS_ADC_MASK                 (0x1U)
+#define USBHS_HCCPARAMS_ADC_SHIFT                (0U)
+#define USBHS_HCCPARAMS_ADC(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_ADC_SHIFT)) & USBHS_HCCPARAMS_ADC_MASK)
+#define USBHS_HCCPARAMS_PFL_MASK                 (0x2U)
+#define USBHS_HCCPARAMS_PFL_SHIFT                (1U)
+#define USBHS_HCCPARAMS_PFL(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_PFL_SHIFT)) & USBHS_HCCPARAMS_PFL_MASK)
+#define USBHS_HCCPARAMS_ASP_MASK                 (0x4U)
+#define USBHS_HCCPARAMS_ASP_SHIFT                (2U)
+#define USBHS_HCCPARAMS_ASP(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_ASP_SHIFT)) & USBHS_HCCPARAMS_ASP_MASK)
+#define USBHS_HCCPARAMS_IST_MASK                 (0xF0U)
+#define USBHS_HCCPARAMS_IST_SHIFT                (4U)
+#define USBHS_HCCPARAMS_IST(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_IST_SHIFT)) & USBHS_HCCPARAMS_IST_MASK)
+#define USBHS_HCCPARAMS_EECP_MASK                (0xFF00U)
+#define USBHS_HCCPARAMS_EECP_SHIFT               (8U)
+#define USBHS_HCCPARAMS_EECP(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_EECP_SHIFT)) & USBHS_HCCPARAMS_EECP_MASK)
+
+/*! @name DCIVERSION - Device Controller Interface Version */
+#define USBHS_DCIVERSION_DCIVERSION_MASK         (0xFFFFU)
+#define USBHS_DCIVERSION_DCIVERSION_SHIFT        (0U)
+#define USBHS_DCIVERSION_DCIVERSION(x)           (((uint16_t)(((uint16_t)(x)) << USBHS_DCIVERSION_DCIVERSION_SHIFT)) & USBHS_DCIVERSION_DCIVERSION_MASK)
+
+/*! @name DCCPARAMS - Device Controller Capability Parameters */
+#define USBHS_DCCPARAMS_DEN_MASK                 (0x1FU)
+#define USBHS_DCCPARAMS_DEN_SHIFT                (0U)
+#define USBHS_DCCPARAMS_DEN(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_DEN_SHIFT)) & USBHS_DCCPARAMS_DEN_MASK)
+#define USBHS_DCCPARAMS_DC_MASK                  (0x80U)
+#define USBHS_DCCPARAMS_DC_SHIFT                 (7U)
+#define USBHS_DCCPARAMS_DC(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_DC_SHIFT)) & USBHS_DCCPARAMS_DC_MASK)
+#define USBHS_DCCPARAMS_HC_MASK                  (0x100U)
+#define USBHS_DCCPARAMS_HC_SHIFT                 (8U)
+#define USBHS_DCCPARAMS_HC(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_HC_SHIFT)) & USBHS_DCCPARAMS_HC_MASK)
+
+/*! @name USBCMD - USB Command Register */
+#define USBHS_USBCMD_RS_MASK                     (0x1U)
+#define USBHS_USBCMD_RS_SHIFT                    (0U)
+#define USBHS_USBCMD_RS(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_RS_SHIFT)) & USBHS_USBCMD_RS_MASK)
+#define USBHS_USBCMD_RST_MASK                    (0x2U)
+#define USBHS_USBCMD_RST_SHIFT                   (1U)
+#define USBHS_USBCMD_RST(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_RST_SHIFT)) & USBHS_USBCMD_RST_MASK)
+#define USBHS_USBCMD_FS_MASK                     (0xCU)
+#define USBHS_USBCMD_FS_SHIFT                    (2U)
+#define USBHS_USBCMD_FS(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_FS_SHIFT)) & USBHS_USBCMD_FS_MASK)
+#define USBHS_USBCMD_PSE_MASK                    (0x10U)
+#define USBHS_USBCMD_PSE_SHIFT                   (4U)
+#define USBHS_USBCMD_PSE(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_PSE_SHIFT)) & USBHS_USBCMD_PSE_MASK)
+#define USBHS_USBCMD_ASE_MASK                    (0x20U)
+#define USBHS_USBCMD_ASE_SHIFT                   (5U)
+#define USBHS_USBCMD_ASE(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASE_SHIFT)) & USBHS_USBCMD_ASE_MASK)
+#define USBHS_USBCMD_IAA_MASK                    (0x40U)
+#define USBHS_USBCMD_IAA_SHIFT                   (6U)
+#define USBHS_USBCMD_IAA(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_IAA_SHIFT)) & USBHS_USBCMD_IAA_MASK)
+#define USBHS_USBCMD_ASP_MASK                    (0x300U)
+#define USBHS_USBCMD_ASP_SHIFT                   (8U)
+#define USBHS_USBCMD_ASP(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASP_SHIFT)) & USBHS_USBCMD_ASP_MASK)
+#define USBHS_USBCMD_ASPE_MASK                   (0x800U)
+#define USBHS_USBCMD_ASPE_SHIFT                  (11U)
+#define USBHS_USBCMD_ASPE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASPE_SHIFT)) & USBHS_USBCMD_ASPE_MASK)
+#define USBHS_USBCMD_SUTW_MASK                   (0x2000U)
+#define USBHS_USBCMD_SUTW_SHIFT                  (13U)
+#define USBHS_USBCMD_SUTW(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_SUTW_SHIFT)) & USBHS_USBCMD_SUTW_MASK)
+#define USBHS_USBCMD_ATDTW_MASK                  (0x4000U)
+#define USBHS_USBCMD_ATDTW_SHIFT                 (14U)
+#define USBHS_USBCMD_ATDTW(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ATDTW_SHIFT)) & USBHS_USBCMD_ATDTW_MASK)
+#define USBHS_USBCMD_FS2_MASK                    (0x8000U)
+#define USBHS_USBCMD_FS2_SHIFT                   (15U)
+#define USBHS_USBCMD_FS2(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_FS2_SHIFT)) & USBHS_USBCMD_FS2_MASK)
+#define USBHS_USBCMD_ITC_MASK                    (0xFF0000U)
+#define USBHS_USBCMD_ITC_SHIFT                   (16U)
+#define USBHS_USBCMD_ITC(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ITC_SHIFT)) & USBHS_USBCMD_ITC_MASK)
+
+/*! @name USBSTS - USB Status Register */
+#define USBHS_USBSTS_UI_MASK                     (0x1U)
+#define USBHS_USBSTS_UI_SHIFT                    (0U)
+#define USBHS_USBSTS_UI(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UI_SHIFT)) & USBHS_USBSTS_UI_MASK)
+#define USBHS_USBSTS_UEI_MASK                    (0x2U)
+#define USBHS_USBSTS_UEI_SHIFT                   (1U)
+#define USBHS_USBSTS_UEI(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UEI_SHIFT)) & USBHS_USBSTS_UEI_MASK)
+#define USBHS_USBSTS_PCI_MASK                    (0x4U)
+#define USBHS_USBSTS_PCI_SHIFT                   (2U)
+#define USBHS_USBSTS_PCI(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_PCI_SHIFT)) & USBHS_USBSTS_PCI_MASK)
+#define USBHS_USBSTS_FRI_MASK                    (0x8U)
+#define USBHS_USBSTS_FRI_SHIFT                   (3U)
+#define USBHS_USBSTS_FRI(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_FRI_SHIFT)) & USBHS_USBSTS_FRI_MASK)
+#define USBHS_USBSTS_SEI_MASK                    (0x10U)
+#define USBHS_USBSTS_SEI_SHIFT                   (4U)
+#define USBHS_USBSTS_SEI(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SEI_SHIFT)) & USBHS_USBSTS_SEI_MASK)
+#define USBHS_USBSTS_AAI_MASK                    (0x20U)
+#define USBHS_USBSTS_AAI_SHIFT                   (5U)
+#define USBHS_USBSTS_AAI(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AAI_SHIFT)) & USBHS_USBSTS_AAI_MASK)
+#define USBHS_USBSTS_URI_MASK                    (0x40U)
+#define USBHS_USBSTS_URI_SHIFT                   (6U)
+#define USBHS_USBSTS_URI(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_URI_SHIFT)) & USBHS_USBSTS_URI_MASK)
+#define USBHS_USBSTS_SRI_MASK                    (0x80U)
+#define USBHS_USBSTS_SRI_SHIFT                   (7U)
+#define USBHS_USBSTS_SRI(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SRI_SHIFT)) & USBHS_USBSTS_SRI_MASK)
+#define USBHS_USBSTS_SLI_MASK                    (0x100U)
+#define USBHS_USBSTS_SLI_SHIFT                   (8U)
+#define USBHS_USBSTS_SLI(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SLI_SHIFT)) & USBHS_USBSTS_SLI_MASK)
+#define USBHS_USBSTS_HCH_MASK                    (0x1000U)
+#define USBHS_USBSTS_HCH_SHIFT                   (12U)
+#define USBHS_USBSTS_HCH(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_HCH_SHIFT)) & USBHS_USBSTS_HCH_MASK)
+#define USBHS_USBSTS_RCL_MASK                    (0x2000U)
+#define USBHS_USBSTS_RCL_SHIFT                   (13U)
+#define USBHS_USBSTS_RCL(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_RCL_SHIFT)) & USBHS_USBSTS_RCL_MASK)
+#define USBHS_USBSTS_PS_MASK                     (0x4000U)
+#define USBHS_USBSTS_PS_SHIFT                    (14U)
+#define USBHS_USBSTS_PS(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_PS_SHIFT)) & USBHS_USBSTS_PS_MASK)
+#define USBHS_USBSTS_AS_MASK                     (0x8000U)
+#define USBHS_USBSTS_AS_SHIFT                    (15U)
+#define USBHS_USBSTS_AS(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AS_SHIFT)) & USBHS_USBSTS_AS_MASK)
+#define USBHS_USBSTS_NAKI_MASK                   (0x10000U)
+#define USBHS_USBSTS_NAKI_SHIFT                  (16U)
+#define USBHS_USBSTS_NAKI(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_NAKI_SHIFT)) & USBHS_USBSTS_NAKI_MASK)
+#define USBHS_USBSTS_UAI_MASK                    (0x40000U)
+#define USBHS_USBSTS_UAI_SHIFT                   (18U)
+#define USBHS_USBSTS_UAI(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UAI_SHIFT)) & USBHS_USBSTS_UAI_MASK)
+#define USBHS_USBSTS_UPI_MASK                    (0x80000U)
+#define USBHS_USBSTS_UPI_SHIFT                   (19U)
+#define USBHS_USBSTS_UPI(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UPI_SHIFT)) & USBHS_USBSTS_UPI_MASK)
+#define USBHS_USBSTS_TI0_MASK                    (0x1000000U)
+#define USBHS_USBSTS_TI0_SHIFT                   (24U)
+#define USBHS_USBSTS_TI0(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI0_SHIFT)) & USBHS_USBSTS_TI0_MASK)
+#define USBHS_USBSTS_TI1_MASK                    (0x2000000U)
+#define USBHS_USBSTS_TI1_SHIFT                   (25U)
+#define USBHS_USBSTS_TI1(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI1_SHIFT)) & USBHS_USBSTS_TI1_MASK)
+
+/*! @name USBINTR - USB Interrupt Enable Register */
+#define USBHS_USBINTR_UE_MASK                    (0x1U)
+#define USBHS_USBINTR_UE_SHIFT                   (0U)
+#define USBHS_USBINTR_UE(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UE_SHIFT)) & USBHS_USBINTR_UE_MASK)
+#define USBHS_USBINTR_UEE_MASK                   (0x2U)
+#define USBHS_USBINTR_UEE_SHIFT                  (1U)
+#define USBHS_USBINTR_UEE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UEE_SHIFT)) & USBHS_USBINTR_UEE_MASK)
+#define USBHS_USBINTR_PCE_MASK                   (0x4U)
+#define USBHS_USBINTR_PCE_SHIFT                  (2U)
+#define USBHS_USBINTR_PCE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_PCE_SHIFT)) & USBHS_USBINTR_PCE_MASK)
+#define USBHS_USBINTR_FRE_MASK                   (0x8U)
+#define USBHS_USBINTR_FRE_SHIFT                  (3U)
+#define USBHS_USBINTR_FRE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_FRE_SHIFT)) & USBHS_USBINTR_FRE_MASK)
+#define USBHS_USBINTR_SEE_MASK                   (0x10U)
+#define USBHS_USBINTR_SEE_SHIFT                  (4U)
+#define USBHS_USBINTR_SEE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SEE_SHIFT)) & USBHS_USBINTR_SEE_MASK)
+#define USBHS_USBINTR_AAE_MASK                   (0x20U)
+#define USBHS_USBINTR_AAE_SHIFT                  (5U)
+#define USBHS_USBINTR_AAE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_AAE_SHIFT)) & USBHS_USBINTR_AAE_MASK)
+#define USBHS_USBINTR_URE_MASK                   (0x40U)
+#define USBHS_USBINTR_URE_SHIFT                  (6U)
+#define USBHS_USBINTR_URE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_URE_SHIFT)) & USBHS_USBINTR_URE_MASK)
+#define USBHS_USBINTR_SRE_MASK                   (0x80U)
+#define USBHS_USBINTR_SRE_SHIFT                  (7U)
+#define USBHS_USBINTR_SRE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SRE_SHIFT)) & USBHS_USBINTR_SRE_MASK)
+#define USBHS_USBINTR_SLE_MASK                   (0x100U)
+#define USBHS_USBINTR_SLE_SHIFT                  (8U)
+#define USBHS_USBINTR_SLE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SLE_SHIFT)) & USBHS_USBINTR_SLE_MASK)
+#define USBHS_USBINTR_NAKE_MASK                  (0x10000U)
+#define USBHS_USBINTR_NAKE_SHIFT                 (16U)
+#define USBHS_USBINTR_NAKE(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_NAKE_SHIFT)) & USBHS_USBINTR_NAKE_MASK)
+#define USBHS_USBINTR_UAIE_MASK                  (0x40000U)
+#define USBHS_USBINTR_UAIE_SHIFT                 (18U)
+#define USBHS_USBINTR_UAIE(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UAIE_SHIFT)) & USBHS_USBINTR_UAIE_MASK)
+#define USBHS_USBINTR_UPIE_MASK                  (0x80000U)
+#define USBHS_USBINTR_UPIE_SHIFT                 (19U)
+#define USBHS_USBINTR_UPIE(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UPIE_SHIFT)) & USBHS_USBINTR_UPIE_MASK)
+#define USBHS_USBINTR_TIE0_MASK                  (0x1000000U)
+#define USBHS_USBINTR_TIE0_SHIFT                 (24U)
+#define USBHS_USBINTR_TIE0(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE0_SHIFT)) & USBHS_USBINTR_TIE0_MASK)
+#define USBHS_USBINTR_TIE1_MASK                  (0x2000000U)
+#define USBHS_USBINTR_TIE1_SHIFT                 (25U)
+#define USBHS_USBINTR_TIE1(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE1_SHIFT)) & USBHS_USBINTR_TIE1_MASK)
+
+/*! @name FRINDEX - Frame Index Register */
+#define USBHS_FRINDEX_FRINDEX_MASK               (0x3FFFU)
+#define USBHS_FRINDEX_FRINDEX_SHIFT              (0U)
+#define USBHS_FRINDEX_FRINDEX(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_FRINDEX_FRINDEX_SHIFT)) & USBHS_FRINDEX_FRINDEX_MASK)
+#define USBHS_FRINDEX_Reerved_MASK               (0xFFFFC000U)
+#define USBHS_FRINDEX_Reerved_SHIFT              (14U)
+#define USBHS_FRINDEX_Reerved(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_FRINDEX_Reerved_SHIFT)) & USBHS_FRINDEX_Reerved_MASK)
+
+/*! @name DEVICEADDR - Device Address Register */
+#define USBHS_DEVICEADDR_USBADRA_MASK            (0x1000000U)
+#define USBHS_DEVICEADDR_USBADRA_SHIFT           (24U)
+#define USBHS_DEVICEADDR_USBADRA(x)              (((uint32_t)(((uint32_t)(x)) << USBHS_DEVICEADDR_USBADRA_SHIFT)) & USBHS_DEVICEADDR_USBADRA_MASK)
+#define USBHS_DEVICEADDR_USBADR_MASK             (0xFE000000U)
+#define USBHS_DEVICEADDR_USBADR_SHIFT            (25U)
+#define USBHS_DEVICEADDR_USBADR(x)               (((uint32_t)(((uint32_t)(x)) << USBHS_DEVICEADDR_USBADR_SHIFT)) & USBHS_DEVICEADDR_USBADR_MASK)
+
+/*! @name PERIODICLISTBASE - Periodic Frame List Base Address Register */
+#define USBHS_PERIODICLISTBASE_PERBASE_MASK      (0xFFFFF000U)
+#define USBHS_PERIODICLISTBASE_PERBASE_SHIFT     (12U)
+#define USBHS_PERIODICLISTBASE_PERBASE(x)        (((uint32_t)(((uint32_t)(x)) << USBHS_PERIODICLISTBASE_PERBASE_SHIFT)) & USBHS_PERIODICLISTBASE_PERBASE_MASK)
+
+/*! @name ASYNCLISTADDR - Current Asynchronous List Address Register */
+#define USBHS_ASYNCLISTADDR_ASYBASE_MASK         (0xFFFFFFE0U)
+#define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT        (5U)
+#define USBHS_ASYNCLISTADDR_ASYBASE(x)           (((uint32_t)(((uint32_t)(x)) << USBHS_ASYNCLISTADDR_ASYBASE_SHIFT)) & USBHS_ASYNCLISTADDR_ASYBASE_MASK)
+
+/*! @name EPLISTADDR - Endpoint List Address Register */
+#define USBHS_EPLISTADDR_EPBASE_MASK             (0xFFFFF800U)
+#define USBHS_EPLISTADDR_EPBASE_SHIFT            (11U)
+#define USBHS_EPLISTADDR_EPBASE(x)               (((uint32_t)(((uint32_t)(x)) << USBHS_EPLISTADDR_EPBASE_SHIFT)) & USBHS_EPLISTADDR_EPBASE_MASK)
+
+/*! @name TTCTRL - Host TT Asynchronous Buffer Control */
+#define USBHS_TTCTRL_TTHA_MASK                   (0x7F000000U)
+#define USBHS_TTCTRL_TTHA_SHIFT                  (24U)
+#define USBHS_TTCTRL_TTHA(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_TTCTRL_TTHA_SHIFT)) & USBHS_TTCTRL_TTHA_MASK)
+#define USBHS_TTCTRL_Reerved_MASK                (0x80000000U)
+#define USBHS_TTCTRL_Reerved_SHIFT               (31U)
+#define USBHS_TTCTRL_Reerved(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_TTCTRL_Reerved_SHIFT)) & USBHS_TTCTRL_Reerved_MASK)
+
+/*! @name BURSTSIZE - Master Interface Data Burst Size Register */
+#define USBHS_BURSTSIZE_RXPBURST_MASK            (0xFFU)
+#define USBHS_BURSTSIZE_RXPBURST_SHIFT           (0U)
+#define USBHS_BURSTSIZE_RXPBURST(x)              (((uint32_t)(((uint32_t)(x)) << USBHS_BURSTSIZE_RXPBURST_SHIFT)) & USBHS_BURSTSIZE_RXPBURST_MASK)
+#define USBHS_BURSTSIZE_TXPBURST_MASK            (0xFF00U)
+#define USBHS_BURSTSIZE_TXPBURST_SHIFT           (8U)
+#define USBHS_BURSTSIZE_TXPBURST(x)              (((uint32_t)(((uint32_t)(x)) << USBHS_BURSTSIZE_TXPBURST_SHIFT)) & USBHS_BURSTSIZE_TXPBURST_MASK)
+
+/*! @name TXFILLTUNING - Transmit FIFO Tuning Control Register */
+#define USBHS_TXFILLTUNING_TXSCHOH_MASK          (0x7FU)
+#define USBHS_TXFILLTUNING_TXSCHOH_SHIFT         (0U)
+#define USBHS_TXFILLTUNING_TXSCHOH(x)            (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXSCHOH_SHIFT)) & USBHS_TXFILLTUNING_TXSCHOH_MASK)
+#define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK      (0x1F00U)
+#define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT     (8U)
+#define USBHS_TXFILLTUNING_TXSCHHEALTH(x)        (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USBHS_TXFILLTUNING_TXSCHHEALTH_MASK)
+#define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK      (0x3F0000U)
+#define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT     (16U)
+#define USBHS_TXFILLTUNING_TXFIFOTHRES(x)        (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USBHS_TXFILLTUNING_TXFIFOTHRES_MASK)
+
+/*! @name ENDPTNAK - Endpoint NAK Register */
+#define USBHS_ENDPTNAK_EPRN_MASK                 (0xFU)
+#define USBHS_ENDPTNAK_EPRN_SHIFT                (0U)
+#define USBHS_ENDPTNAK_EPRN(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAK_EPRN_SHIFT)) & USBHS_ENDPTNAK_EPRN_MASK)
+#define USBHS_ENDPTNAK_EPTN_MASK                 (0xF0000U)
+#define USBHS_ENDPTNAK_EPTN_SHIFT                (16U)
+#define USBHS_ENDPTNAK_EPTN(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAK_EPTN_SHIFT)) & USBHS_ENDPTNAK_EPTN_MASK)
+
+/*! @name ENDPTNAKEN - Endpoint NAK Enable Register */
+#define USBHS_ENDPTNAKEN_EPRNE_MASK              (0xFU)
+#define USBHS_ENDPTNAKEN_EPRNE_SHIFT             (0U)
+#define USBHS_ENDPTNAKEN_EPRNE(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAKEN_EPRNE_SHIFT)) & USBHS_ENDPTNAKEN_EPRNE_MASK)
+#define USBHS_ENDPTNAKEN_EPTNE_MASK              (0xF0000U)
+#define USBHS_ENDPTNAKEN_EPTNE_SHIFT             (16U)
+#define USBHS_ENDPTNAKEN_EPTNE(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAKEN_EPTNE_SHIFT)) & USBHS_ENDPTNAKEN_EPTNE_MASK)
+
+/*! @name PORTSC1 - Port Status and Control Registers */
+#define USBHS_PORTSC1_CCS_MASK                   (0x1U)
+#define USBHS_PORTSC1_CCS_SHIFT                  (0U)
+#define USBHS_PORTSC1_CCS(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CCS_SHIFT)) & USBHS_PORTSC1_CCS_MASK)
+#define USBHS_PORTSC1_CSC_MASK                   (0x2U)
+#define USBHS_PORTSC1_CSC_SHIFT                  (1U)
+#define USBHS_PORTSC1_CSC(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CSC_SHIFT)) & USBHS_PORTSC1_CSC_MASK)
+#define USBHS_PORTSC1_PE_MASK                    (0x4U)
+#define USBHS_PORTSC1_PE_SHIFT                   (2U)
+#define USBHS_PORTSC1_PE(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PE_SHIFT)) & USBHS_PORTSC1_PE_MASK)
+#define USBHS_PORTSC1_PEC_MASK                   (0x8U)
+#define USBHS_PORTSC1_PEC_SHIFT                  (3U)
+#define USBHS_PORTSC1_PEC(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PEC_SHIFT)) & USBHS_PORTSC1_PEC_MASK)
+#define USBHS_PORTSC1_OCA_MASK                   (0x10U)
+#define USBHS_PORTSC1_OCA_SHIFT                  (4U)
+#define USBHS_PORTSC1_OCA(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCA_SHIFT)) & USBHS_PORTSC1_OCA_MASK)
+#define USBHS_PORTSC1_OCC_MASK                   (0x20U)
+#define USBHS_PORTSC1_OCC_SHIFT                  (5U)
+#define USBHS_PORTSC1_OCC(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCC_SHIFT)) & USBHS_PORTSC1_OCC_MASK)
+#define USBHS_PORTSC1_FPR_MASK                   (0x40U)
+#define USBHS_PORTSC1_FPR_SHIFT                  (6U)
+#define USBHS_PORTSC1_FPR(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_FPR_SHIFT)) & USBHS_PORTSC1_FPR_MASK)
+#define USBHS_PORTSC1_SUSP_MASK                  (0x80U)
+#define USBHS_PORTSC1_SUSP_SHIFT                 (7U)
+#define USBHS_PORTSC1_SUSP(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_SUSP_SHIFT)) & USBHS_PORTSC1_SUSP_MASK)
+#define USBHS_PORTSC1_PR_MASK                    (0x100U)
+#define USBHS_PORTSC1_PR_SHIFT                   (8U)
+#define USBHS_PORTSC1_PR(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PR_SHIFT)) & USBHS_PORTSC1_PR_MASK)
+#define USBHS_PORTSC1_HSP_MASK                   (0x200U)
+#define USBHS_PORTSC1_HSP_SHIFT                  (9U)
+#define USBHS_PORTSC1_HSP(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_HSP_SHIFT)) & USBHS_PORTSC1_HSP_MASK)
+#define USBHS_PORTSC1_LS_MASK                    (0xC00U)
+#define USBHS_PORTSC1_LS_SHIFT                   (10U)
+#define USBHS_PORTSC1_LS(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_LS_SHIFT)) & USBHS_PORTSC1_LS_MASK)
+#define USBHS_PORTSC1_PP_MASK                    (0x1000U)
+#define USBHS_PORTSC1_PP_SHIFT                   (12U)
+#define USBHS_PORTSC1_PP(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PP_SHIFT)) & USBHS_PORTSC1_PP_MASK)
+#define USBHS_PORTSC1_PO_MASK                    (0x2000U)
+#define USBHS_PORTSC1_PO_SHIFT                   (13U)
+#define USBHS_PORTSC1_PO(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PO_SHIFT)) & USBHS_PORTSC1_PO_MASK)
+#define USBHS_PORTSC1_PIC_MASK                   (0xC000U)
+#define USBHS_PORTSC1_PIC_SHIFT                  (14U)
+#define USBHS_PORTSC1_PIC(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PIC_SHIFT)) & USBHS_PORTSC1_PIC_MASK)
+#define USBHS_PORTSC1_PTC_MASK                   (0xF0000U)
+#define USBHS_PORTSC1_PTC_SHIFT                  (16U)
+#define USBHS_PORTSC1_PTC(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTC_SHIFT)) & USBHS_PORTSC1_PTC_MASK)
+#define USBHS_PORTSC1_WKCN_MASK                  (0x100000U)
+#define USBHS_PORTSC1_WKCN_SHIFT                 (20U)
+#define USBHS_PORTSC1_WKCN(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKCN_SHIFT)) & USBHS_PORTSC1_WKCN_MASK)
+#define USBHS_PORTSC1_WKDS_MASK                  (0x200000U)
+#define USBHS_PORTSC1_WKDS_SHIFT                 (21U)
+#define USBHS_PORTSC1_WKDS(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKDS_SHIFT)) & USBHS_PORTSC1_WKDS_MASK)
+#define USBHS_PORTSC1_WKOC_MASK                  (0x400000U)
+#define USBHS_PORTSC1_WKOC_SHIFT                 (22U)
+#define USBHS_PORTSC1_WKOC(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKOC_SHIFT)) & USBHS_PORTSC1_WKOC_MASK)
+#define USBHS_PORTSC1_PHCD_MASK                  (0x800000U)
+#define USBHS_PORTSC1_PHCD_SHIFT                 (23U)
+#define USBHS_PORTSC1_PHCD(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PHCD_SHIFT)) & USBHS_PORTSC1_PHCD_MASK)
+#define USBHS_PORTSC1_PFSC_MASK                  (0x1000000U)
+#define USBHS_PORTSC1_PFSC_SHIFT                 (24U)
+#define USBHS_PORTSC1_PFSC(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PFSC_SHIFT)) & USBHS_PORTSC1_PFSC_MASK)
+#define USBHS_PORTSC1_PTS2_MASK                  (0x2000000U)
+#define USBHS_PORTSC1_PTS2_SHIFT                 (25U)
+#define USBHS_PORTSC1_PTS2(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTS2_SHIFT)) & USBHS_PORTSC1_PTS2_MASK)
+#define USBHS_PORTSC1_PSPD_MASK                  (0xC000000U)
+#define USBHS_PORTSC1_PSPD_SHIFT                 (26U)
+#define USBHS_PORTSC1_PSPD(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PSPD_SHIFT)) & USBHS_PORTSC1_PSPD_MASK)
+#define USBHS_PORTSC1_PTS_MASK                   (0xC0000000U)
+#define USBHS_PORTSC1_PTS_SHIFT                  (30U)
+#define USBHS_PORTSC1_PTS(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTS_SHIFT)) & USBHS_PORTSC1_PTS_MASK)
+
+/*! @name OTGSC - On-the-Go Status and Control Register */
+#define USBHS_OTGSC_VD_MASK                      (0x1U)
+#define USBHS_OTGSC_VD_SHIFT                     (0U)
+#define USBHS_OTGSC_VD(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_VD_SHIFT)) & USBHS_OTGSC_VD_MASK)
+#define USBHS_OTGSC_VC_MASK                      (0x2U)
+#define USBHS_OTGSC_VC_SHIFT                     (1U)
+#define USBHS_OTGSC_VC(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_VC_SHIFT)) & USBHS_OTGSC_VC_MASK)
+#define USBHS_OTGSC_HAAR_MASK                    (0x4U)
+#define USBHS_OTGSC_HAAR_SHIFT                   (2U)
+#define USBHS_OTGSC_HAAR(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_HAAR_SHIFT)) & USBHS_OTGSC_HAAR_MASK)
+#define USBHS_OTGSC_OT_MASK                      (0x8U)
+#define USBHS_OTGSC_OT_SHIFT                     (3U)
+#define USBHS_OTGSC_OT(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_OT_SHIFT)) & USBHS_OTGSC_OT_MASK)
+#define USBHS_OTGSC_DP_MASK                      (0x10U)
+#define USBHS_OTGSC_DP_SHIFT                     (4U)
+#define USBHS_OTGSC_DP(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DP_SHIFT)) & USBHS_OTGSC_DP_MASK)
+#define USBHS_OTGSC_IDPU_MASK                    (0x20U)
+#define USBHS_OTGSC_IDPU_SHIFT                   (5U)
+#define USBHS_OTGSC_IDPU(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDPU_SHIFT)) & USBHS_OTGSC_IDPU_MASK)
+#define USBHS_OTGSC_HABA_MASK                    (0x80U)
+#define USBHS_OTGSC_HABA_SHIFT                   (7U)
+#define USBHS_OTGSC_HABA(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_HABA_SHIFT)) & USBHS_OTGSC_HABA_MASK)
+#define USBHS_OTGSC_ID_MASK                      (0x100U)
+#define USBHS_OTGSC_ID_SHIFT                     (8U)
+#define USBHS_OTGSC_ID(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ID_SHIFT)) & USBHS_OTGSC_ID_MASK)
+#define USBHS_OTGSC_AVV_MASK                     (0x200U)
+#define USBHS_OTGSC_AVV_SHIFT                    (9U)
+#define USBHS_OTGSC_AVV(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVV_SHIFT)) & USBHS_OTGSC_AVV_MASK)
+#define USBHS_OTGSC_ASV_MASK                     (0x400U)
+#define USBHS_OTGSC_ASV_SHIFT                    (10U)
+#define USBHS_OTGSC_ASV(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASV_SHIFT)) & USBHS_OTGSC_ASV_MASK)
+#define USBHS_OTGSC_BSV_MASK                     (0x800U)
+#define USBHS_OTGSC_BSV_SHIFT                    (11U)
+#define USBHS_OTGSC_BSV(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSV_SHIFT)) & USBHS_OTGSC_BSV_MASK)
+#define USBHS_OTGSC_BSE_MASK                     (0x1000U)
+#define USBHS_OTGSC_BSE_SHIFT                    (12U)
+#define USBHS_OTGSC_BSE(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSE_SHIFT)) & USBHS_OTGSC_BSE_MASK)
+#define USBHS_OTGSC_MST_MASK                     (0x2000U)
+#define USBHS_OTGSC_MST_SHIFT                    (13U)
+#define USBHS_OTGSC_MST(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_MST_SHIFT)) & USBHS_OTGSC_MST_MASK)
+#define USBHS_OTGSC_DPS_MASK                     (0x4000U)
+#define USBHS_OTGSC_DPS_SHIFT                    (14U)
+#define USBHS_OTGSC_DPS(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPS_SHIFT)) & USBHS_OTGSC_DPS_MASK)
+#define USBHS_OTGSC_IDIS_MASK                    (0x10000U)
+#define USBHS_OTGSC_IDIS_SHIFT                   (16U)
+#define USBHS_OTGSC_IDIS(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDIS_SHIFT)) & USBHS_OTGSC_IDIS_MASK)
+#define USBHS_OTGSC_AVVIS_MASK                   (0x20000U)
+#define USBHS_OTGSC_AVVIS_SHIFT                  (17U)
+#define USBHS_OTGSC_AVVIS(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVVIS_SHIFT)) & USBHS_OTGSC_AVVIS_MASK)
+#define USBHS_OTGSC_ASVIS_MASK                   (0x40000U)
+#define USBHS_OTGSC_ASVIS_SHIFT                  (18U)
+#define USBHS_OTGSC_ASVIS(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASVIS_SHIFT)) & USBHS_OTGSC_ASVIS_MASK)
+#define USBHS_OTGSC_BSVIS_MASK                   (0x80000U)
+#define USBHS_OTGSC_BSVIS_SHIFT                  (19U)
+#define USBHS_OTGSC_BSVIS(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSVIS_SHIFT)) & USBHS_OTGSC_BSVIS_MASK)
+#define USBHS_OTGSC_BSEIS_MASK                   (0x100000U)
+#define USBHS_OTGSC_BSEIS_SHIFT                  (20U)
+#define USBHS_OTGSC_BSEIS(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSEIS_SHIFT)) & USBHS_OTGSC_BSEIS_MASK)
+#define USBHS_OTGSC_MSS_MASK                     (0x200000U)
+#define USBHS_OTGSC_MSS_SHIFT                    (21U)
+#define USBHS_OTGSC_MSS(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_MSS_SHIFT)) & USBHS_OTGSC_MSS_MASK)
+#define USBHS_OTGSC_DPIS_MASK                    (0x400000U)
+#define USBHS_OTGSC_DPIS_SHIFT                   (22U)
+#define USBHS_OTGSC_DPIS(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPIS_SHIFT)) & USBHS_OTGSC_DPIS_MASK)
+#define USBHS_OTGSC_IDIE_MASK                    (0x1000000U)
+#define USBHS_OTGSC_IDIE_SHIFT                   (24U)
+#define USBHS_OTGSC_IDIE(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDIE_SHIFT)) & USBHS_OTGSC_IDIE_MASK)
+#define USBHS_OTGSC_AVVIE_MASK                   (0x2000000U)
+#define USBHS_OTGSC_AVVIE_SHIFT                  (25U)
+#define USBHS_OTGSC_AVVIE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVVIE_SHIFT)) & USBHS_OTGSC_AVVIE_MASK)
+#define USBHS_OTGSC_ASVIE_MASK                   (0x4000000U)
+#define USBHS_OTGSC_ASVIE_SHIFT                  (26U)
+#define USBHS_OTGSC_ASVIE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASVIE_SHIFT)) & USBHS_OTGSC_ASVIE_MASK)
+#define USBHS_OTGSC_BSVIE_MASK                   (0x8000000U)
+#define USBHS_OTGSC_BSVIE_SHIFT                  (27U)
+#define USBHS_OTGSC_BSVIE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSVIE_SHIFT)) & USBHS_OTGSC_BSVIE_MASK)
+#define USBHS_OTGSC_BSEIE_MASK                   (0x10000000U)
+#define USBHS_OTGSC_BSEIE_SHIFT                  (28U)
+#define USBHS_OTGSC_BSEIE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSEIE_SHIFT)) & USBHS_OTGSC_BSEIE_MASK)
+#define USBHS_OTGSC_MSE_MASK                     (0x20000000U)
+#define USBHS_OTGSC_MSE_SHIFT                    (29U)
+#define USBHS_OTGSC_MSE(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_MSE_SHIFT)) & USBHS_OTGSC_MSE_MASK)
+#define USBHS_OTGSC_DPIE_MASK                    (0x40000000U)
+#define USBHS_OTGSC_DPIE_SHIFT                   (30U)
+#define USBHS_OTGSC_DPIE(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPIE_SHIFT)) & USBHS_OTGSC_DPIE_MASK)
+
+/*! @name USBMODE - USB Mode Register */
+#define USBHS_USBMODE_CM_MASK                    (0x3U)
+#define USBHS_USBMODE_CM_SHIFT                   (0U)
+#define USBHS_USBMODE_CM(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_CM_SHIFT)) & USBHS_USBMODE_CM_MASK)
+#define USBHS_USBMODE_ES_MASK                    (0x4U)
+#define USBHS_USBMODE_ES_SHIFT                   (2U)
+#define USBHS_USBMODE_ES(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_ES_SHIFT)) & USBHS_USBMODE_ES_MASK)
+#define USBHS_USBMODE_SLOM_MASK                  (0x8U)
+#define USBHS_USBMODE_SLOM_SHIFT                 (3U)
+#define USBHS_USBMODE_SLOM(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_SLOM_SHIFT)) & USBHS_USBMODE_SLOM_MASK)
+#define USBHS_USBMODE_SDIS_MASK                  (0x10U)
+#define USBHS_USBMODE_SDIS_SHIFT                 (4U)
+#define USBHS_USBMODE_SDIS(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_SDIS_SHIFT)) & USBHS_USBMODE_SDIS_MASK)
+#define USBHS_USBMODE_TXHSD_MASK                 (0x7000U)
+#define USBHS_USBMODE_TXHSD_SHIFT                (12U)
+#define USBHS_USBMODE_TXHSD(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_TXHSD_SHIFT)) & USBHS_USBMODE_TXHSD_MASK)
+
+/*! @name EPSETUPSR - Endpoint Setup Status Register */
+#define USBHS_EPSETUPSR_EPSETUPSTAT_MASK         (0xFU)
+#define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT        (0U)
+#define USBHS_EPSETUPSR_EPSETUPSTAT(x)           (((uint32_t)(((uint32_t)(x)) << USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT)) & USBHS_EPSETUPSR_EPSETUPSTAT_MASK)
+
+/*! @name EPPRIME - Endpoint Initialization Register */
+#define USBHS_EPPRIME_PERB_MASK                  (0xFU)
+#define USBHS_EPPRIME_PERB_SHIFT                 (0U)
+#define USBHS_EPPRIME_PERB(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_EPPRIME_PERB_SHIFT)) & USBHS_EPPRIME_PERB_MASK)
+#define USBHS_EPPRIME_PETB_MASK                  (0xF0000U)
+#define USBHS_EPPRIME_PETB_SHIFT                 (16U)
+#define USBHS_EPPRIME_PETB(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_EPPRIME_PETB_SHIFT)) & USBHS_EPPRIME_PETB_MASK)
+
+/*! @name EPFLUSH - Endpoint Flush Register */
+#define USBHS_EPFLUSH_FERB_MASK                  (0xFU)
+#define USBHS_EPFLUSH_FERB_SHIFT                 (0U)
+#define USBHS_EPFLUSH_FERB(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_EPFLUSH_FERB_SHIFT)) & USBHS_EPFLUSH_FERB_MASK)
+#define USBHS_EPFLUSH_FETB_MASK                  (0xF0000U)
+#define USBHS_EPFLUSH_FETB_SHIFT                 (16U)
+#define USBHS_EPFLUSH_FETB(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_EPFLUSH_FETB_SHIFT)) & USBHS_EPFLUSH_FETB_MASK)
+
+/*! @name EPSR - Endpoint Status Register */
+#define USBHS_EPSR_ERBR_MASK                     (0xFU)
+#define USBHS_EPSR_ERBR_SHIFT                    (0U)
+#define USBHS_EPSR_ERBR(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_EPSR_ERBR_SHIFT)) & USBHS_EPSR_ERBR_MASK)
+#define USBHS_EPSR_ETBR_MASK                     (0xF0000U)
+#define USBHS_EPSR_ETBR_SHIFT                    (16U)
+#define USBHS_EPSR_ETBR(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_EPSR_ETBR_SHIFT)) & USBHS_EPSR_ETBR_MASK)
+
+/*! @name EPCOMPLETE - Endpoint Complete Register */
+#define USBHS_EPCOMPLETE_ERCE_MASK               (0xFU)
+#define USBHS_EPCOMPLETE_ERCE_SHIFT              (0U)
+#define USBHS_EPCOMPLETE_ERCE(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_EPCOMPLETE_ERCE_SHIFT)) & USBHS_EPCOMPLETE_ERCE_MASK)
+#define USBHS_EPCOMPLETE_ETCE_MASK               (0xF0000U)
+#define USBHS_EPCOMPLETE_ETCE_SHIFT              (16U)
+#define USBHS_EPCOMPLETE_ETCE(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_EPCOMPLETE_ETCE_SHIFT)) & USBHS_EPCOMPLETE_ETCE_MASK)
+
+/*! @name EPCR0 - Endpoint Control Register 0 */
+#define USBHS_EPCR0_RXS_MASK                     (0x1U)
+#define USBHS_EPCR0_RXS_SHIFT                    (0U)
+#define USBHS_EPCR0_RXS(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_RXS_SHIFT)) & USBHS_EPCR0_RXS_MASK)
+#define USBHS_EPCR0_RXT_MASK                     (0xCU)
+#define USBHS_EPCR0_RXT_SHIFT                    (2U)
+#define USBHS_EPCR0_RXT(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_RXT_SHIFT)) & USBHS_EPCR0_RXT_MASK)
+#define USBHS_EPCR0_RXE_MASK                     (0x80U)
+#define USBHS_EPCR0_RXE_SHIFT                    (7U)
+#define USBHS_EPCR0_RXE(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_RXE_SHIFT)) & USBHS_EPCR0_RXE_MASK)
+#define USBHS_EPCR0_TXS_MASK                     (0x10000U)
+#define USBHS_EPCR0_TXS_SHIFT                    (16U)
+#define USBHS_EPCR0_TXS(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_TXS_SHIFT)) & USBHS_EPCR0_TXS_MASK)
+#define USBHS_EPCR0_TXT_MASK                     (0xC0000U)
+#define USBHS_EPCR0_TXT_SHIFT                    (18U)
+#define USBHS_EPCR0_TXT(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_TXT_SHIFT)) & USBHS_EPCR0_TXT_MASK)
+#define USBHS_EPCR0_TXE_MASK                     (0x800000U)
+#define USBHS_EPCR0_TXE_SHIFT                    (23U)
+#define USBHS_EPCR0_TXE(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_TXE_SHIFT)) & USBHS_EPCR0_TXE_MASK)
+
+/*! @name EPCR - Endpoint Control Register n */
+#define USBHS_EPCR_RXS_MASK                      (0x1U)
+#define USBHS_EPCR_RXS_SHIFT                     (0U)
+#define USBHS_EPCR_RXS(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXS_SHIFT)) & USBHS_EPCR_RXS_MASK)
+#define USBHS_EPCR_RXD_MASK                      (0x2U)
+#define USBHS_EPCR_RXD_SHIFT                     (1U)
+#define USBHS_EPCR_RXD(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXD_SHIFT)) & USBHS_EPCR_RXD_MASK)
+#define USBHS_EPCR_RXT_MASK                      (0xCU)
+#define USBHS_EPCR_RXT_SHIFT                     (2U)
+#define USBHS_EPCR_RXT(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXT_SHIFT)) & USBHS_EPCR_RXT_MASK)
+#define USBHS_EPCR_RXI_MASK                      (0x20U)
+#define USBHS_EPCR_RXI_SHIFT                     (5U)
+#define USBHS_EPCR_RXI(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXI_SHIFT)) & USBHS_EPCR_RXI_MASK)
+#define USBHS_EPCR_RXR_MASK                      (0x40U)
+#define USBHS_EPCR_RXR_SHIFT                     (6U)
+#define USBHS_EPCR_RXR(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXR_SHIFT)) & USBHS_EPCR_RXR_MASK)
+#define USBHS_EPCR_RXE_MASK                      (0x80U)
+#define USBHS_EPCR_RXE_SHIFT                     (7U)
+#define USBHS_EPCR_RXE(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXE_SHIFT)) & USBHS_EPCR_RXE_MASK)
+#define USBHS_EPCR_TXS_MASK                      (0x10000U)
+#define USBHS_EPCR_TXS_SHIFT                     (16U)
+#define USBHS_EPCR_TXS(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXS_SHIFT)) & USBHS_EPCR_TXS_MASK)
+#define USBHS_EPCR_TXD_MASK                      (0x20000U)
+#define USBHS_EPCR_TXD_SHIFT                     (17U)
+#define USBHS_EPCR_TXD(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXD_SHIFT)) & USBHS_EPCR_TXD_MASK)
+#define USBHS_EPCR_TXT_MASK                      (0xC0000U)
+#define USBHS_EPCR_TXT_SHIFT                     (18U)
+#define USBHS_EPCR_TXT(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXT_SHIFT)) & USBHS_EPCR_TXT_MASK)
+#define USBHS_EPCR_TXI_MASK                      (0x200000U)
+#define USBHS_EPCR_TXI_SHIFT                     (21U)
+#define USBHS_EPCR_TXI(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXI_SHIFT)) & USBHS_EPCR_TXI_MASK)
+#define USBHS_EPCR_TXR_MASK                      (0x400000U)
+#define USBHS_EPCR_TXR_SHIFT                     (22U)
+#define USBHS_EPCR_TXR(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXR_SHIFT)) & USBHS_EPCR_TXR_MASK)
+#define USBHS_EPCR_TXE_MASK                      (0x800000U)
+#define USBHS_EPCR_TXE_SHIFT                     (23U)
+#define USBHS_EPCR_TXE(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXE_SHIFT)) & USBHS_EPCR_TXE_MASK)
+
+/* The count of USBHS_EPCR */
+#define USBHS_EPCR_COUNT                         (7U)
+
+/*! @name USBGENCTRL - USB General Control Register */
+#define USBHS_USBGENCTRL_WU_IE_MASK              (0x1U)
+#define USBHS_USBGENCTRL_WU_IE_SHIFT             (0U)
+#define USBHS_USBGENCTRL_WU_IE(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_USBGENCTRL_WU_IE_SHIFT)) & USBHS_USBGENCTRL_WU_IE_MASK)
+#define USBHS_USBGENCTRL_WU_INT_CLR_MASK         (0x20U)
+#define USBHS_USBGENCTRL_WU_INT_CLR_SHIFT        (5U)
+#define USBHS_USBGENCTRL_WU_INT_CLR(x)           (((uint32_t)(((uint32_t)(x)) << USBHS_USBGENCTRL_WU_INT_CLR_SHIFT)) & USBHS_USBGENCTRL_WU_INT_CLR_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group USBHS_Register_Masks */
+
+
+/* USBHS - Peripheral instance base addresses */
+/** Peripheral USBHS base address */
+#define USBHS_BASE                               (0x400A1000u)
+/** Peripheral USBHS base pointer */
+#define USBHS                                    ((USBHS_Type *)USBHS_BASE)
+/** Array initializer of USBHS peripheral base addresses */
+#define USBHS_BASE_ADDRS                         { USBHS_BASE }
+/** Array initializer of USBHS peripheral base pointers */
+#define USBHS_BASE_PTRS                          { USBHS }
+/** Interrupt vectors for the USBHS peripheral type */
+#define USBHS_IRQS                               { USBHS_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USBHS_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USBHSDCD Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBHSDCD_Peripheral_Access_Layer USBHSDCD Peripheral Access Layer
+ * @{
+ */
+
+/** USBHSDCD - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t CONTROL;                           /**< Control register, offset: 0x0 */
+  __IO uint32_t CLOCK;                             /**< Clock register, offset: 0x4 */
+  __I  uint32_t STATUS;                            /**< Status register, offset: 0x8 */
+  __IO uint32_t SIGNAL_OVERRIDE;                   /**< Signal Override Register, offset: 0xC */
+  __IO uint32_t TIMER0;                            /**< TIMER0 register, offset: 0x10 */
+  __IO uint32_t TIMER1;                            /**< TIMER1 register, offset: 0x14 */
+  union {                                          /* offset: 0x18 */
+    __IO uint32_t TIMER2_BC11;                       /**< TIMER2_BC11 register, offset: 0x18 */
+    __IO uint32_t TIMER2_BC12;                       /**< TIMER2_BC12 register, offset: 0x18 */
+  };
+} USBHSDCD_Type;
+
+/* ----------------------------------------------------------------------------
+   -- USBHSDCD Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBHSDCD_Register_Masks USBHSDCD Register Masks
+ * @{
+ */
+
+/*! @name CONTROL - Control register */
+#define USBHSDCD_CONTROL_IACK_MASK               (0x1U)
+#define USBHSDCD_CONTROL_IACK_SHIFT              (0U)
+#define USBHSDCD_CONTROL_IACK(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IACK_SHIFT)) & USBHSDCD_CONTROL_IACK_MASK)
+#define USBHSDCD_CONTROL_IF_MASK                 (0x100U)
+#define USBHSDCD_CONTROL_IF_SHIFT                (8U)
+#define USBHSDCD_CONTROL_IF(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IF_SHIFT)) & USBHSDCD_CONTROL_IF_MASK)
+#define USBHSDCD_CONTROL_IE_MASK                 (0x10000U)
+#define USBHSDCD_CONTROL_IE_SHIFT                (16U)
+#define USBHSDCD_CONTROL_IE(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IE_SHIFT)) & USBHSDCD_CONTROL_IE_MASK)
+#define USBHSDCD_CONTROL_BC12_MASK               (0x20000U)
+#define USBHSDCD_CONTROL_BC12_SHIFT              (17U)
+#define USBHSDCD_CONTROL_BC12(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_BC12_SHIFT)) & USBHSDCD_CONTROL_BC12_MASK)
+#define USBHSDCD_CONTROL_START_MASK              (0x1000000U)
+#define USBHSDCD_CONTROL_START_SHIFT             (24U)
+#define USBHSDCD_CONTROL_START(x)                (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_START_SHIFT)) & USBHSDCD_CONTROL_START_MASK)
+#define USBHSDCD_CONTROL_SR_MASK                 (0x2000000U)
+#define USBHSDCD_CONTROL_SR_SHIFT                (25U)
+#define USBHSDCD_CONTROL_SR(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_SR_SHIFT)) & USBHSDCD_CONTROL_SR_MASK)
+
+/*! @name CLOCK - Clock register */
+#define USBHSDCD_CLOCK_CLOCK_UNIT_MASK           (0x1U)
+#define USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT          (0U)
+#define USBHSDCD_CLOCK_CLOCK_UNIT(x)             (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBHSDCD_CLOCK_CLOCK_UNIT_MASK)
+#define USBHSDCD_CLOCK_CLOCK_SPEED_MASK          (0xFFCU)
+#define USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT         (2U)
+#define USBHSDCD_CLOCK_CLOCK_SPEED(x)            (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBHSDCD_CLOCK_CLOCK_SPEED_MASK)
+
+/*! @name STATUS - Status register */
+#define USBHSDCD_STATUS_SEQ_RES_MASK             (0x30000U)
+#define USBHSDCD_STATUS_SEQ_RES_SHIFT            (16U)
+#define USBHSDCD_STATUS_SEQ_RES(x)               (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_RES_SHIFT)) & USBHSDCD_STATUS_SEQ_RES_MASK)
+#define USBHSDCD_STATUS_SEQ_STAT_MASK            (0xC0000U)
+#define USBHSDCD_STATUS_SEQ_STAT_SHIFT           (18U)
+#define USBHSDCD_STATUS_SEQ_STAT(x)              (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_STAT_SHIFT)) & USBHSDCD_STATUS_SEQ_STAT_MASK)
+#define USBHSDCD_STATUS_ERR_MASK                 (0x100000U)
+#define USBHSDCD_STATUS_ERR_SHIFT                (20U)
+#define USBHSDCD_STATUS_ERR(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ERR_SHIFT)) & USBHSDCD_STATUS_ERR_MASK)
+#define USBHSDCD_STATUS_TO_MASK                  (0x200000U)
+#define USBHSDCD_STATUS_TO_SHIFT                 (21U)
+#define USBHSDCD_STATUS_TO(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_TO_SHIFT)) & USBHSDCD_STATUS_TO_MASK)
+#define USBHSDCD_STATUS_ACTIVE_MASK              (0x400000U)
+#define USBHSDCD_STATUS_ACTIVE_SHIFT             (22U)
+#define USBHSDCD_STATUS_ACTIVE(x)                (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ACTIVE_SHIFT)) & USBHSDCD_STATUS_ACTIVE_MASK)
+
+/*! @name SIGNAL_OVERRIDE - Signal Override Register */
+#define USBHSDCD_SIGNAL_OVERRIDE_PS_MASK         (0x3U)
+#define USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT        (0U)
+#define USBHSDCD_SIGNAL_OVERRIDE_PS(x)           (((uint32_t)(((uint32_t)(x)) << USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBHSDCD_SIGNAL_OVERRIDE_PS_MASK)
+
+/*! @name TIMER0 - TIMER0 register */
+#define USBHSDCD_TIMER0_TUNITCON_MASK            (0xFFFU)
+#define USBHSDCD_TIMER0_TUNITCON_SHIFT           (0U)
+#define USBHSDCD_TIMER0_TUNITCON(x)              (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TUNITCON_SHIFT)) & USBHSDCD_TIMER0_TUNITCON_MASK)
+#define USBHSDCD_TIMER0_TSEQ_INIT_MASK           (0x3FF0000U)
+#define USBHSDCD_TIMER0_TSEQ_INIT_SHIFT          (16U)
+#define USBHSDCD_TIMER0_TSEQ_INIT(x)             (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBHSDCD_TIMER0_TSEQ_INIT_MASK)
+
+/*! @name TIMER1 - TIMER1 register */
+#define USBHSDCD_TIMER1_TVDPSRC_ON_MASK          (0x3FFU)
+#define USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT         (0U)
+#define USBHSDCD_TIMER1_TVDPSRC_ON(x)            (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBHSDCD_TIMER1_TVDPSRC_ON_MASK)
+#define USBHSDCD_TIMER1_TDCD_DBNC_MASK           (0x3FF0000U)
+#define USBHSDCD_TIMER1_TDCD_DBNC_SHIFT          (16U)
+#define USBHSDCD_TIMER1_TDCD_DBNC(x)             (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBHSDCD_TIMER1_TDCD_DBNC_MASK)
+
+/*! @name TIMER2_BC11 - TIMER2_BC11 register */
+#define USBHSDCD_TIMER2_BC11_CHECK_DM_MASK       (0xFU)
+#define USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT      (0U)
+#define USBHSDCD_TIMER2_BC11_CHECK_DM(x)         (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBHSDCD_TIMER2_BC11_CHECK_DM_MASK)
+#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK    (0x3FF0000U)
+#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT   (16U)
+#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON(x)      (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
+
+/*! @name TIMER2_BC12 - TIMER2_BC12 register */
+#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK     (0x3FFU)
+#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT    (0U)
+#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON(x)       (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
+#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U)
+#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
+#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x)  (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group USBHSDCD_Register_Masks */
+
+
+/* USBHSDCD - Peripheral instance base addresses */
+/** Peripheral USBHSDCD base address */
+#define USBHSDCD_BASE                            (0x400A3000u)
+/** Peripheral USBHSDCD base pointer */
+#define USBHSDCD                                 ((USBHSDCD_Type *)USBHSDCD_BASE)
+/** Array initializer of USBHSDCD peripheral base addresses */
+#define USBHSDCD_BASE_ADDRS                      { USBHSDCD_BASE }
+/** Array initializer of USBHSDCD peripheral base pointers */
+#define USBHSDCD_BASE_PTRS                       { USBHSDCD }
+/** Interrupt vectors for the USBHSDCD peripheral type */
+#define USBHSDCD_IRQS                            { USBHSDCD_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USBHSDCD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- USBPHY Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer
+ * @{
+ */
+
+/** USBPHY - Register Layout Typedef */
+typedef struct {
+  __IO uint32_t PWD;                               /**< USB PHY Power-Down Register, offset: 0x0 */
+  __IO uint32_t PWD_SET;                           /**< USB PHY Power-Down Register, offset: 0x4 */
+  __IO uint32_t PWD_CLR;                           /**< USB PHY Power-Down Register, offset: 0x8 */
+  __IO uint32_t PWD_TOG;                           /**< USB PHY Power-Down Register, offset: 0xC */
+  __IO uint32_t TX;                                /**< USB PHY Transmitter Control Register, offset: 0x10 */
+  __IO uint32_t TX_SET;                            /**< USB PHY Transmitter Control Register, offset: 0x14 */
+  __IO uint32_t TX_CLR;                            /**< USB PHY Transmitter Control Register, offset: 0x18 */
+  __IO uint32_t TX_TOG;                            /**< USB PHY Transmitter Control Register, offset: 0x1C */
+  __IO uint32_t RX;                                /**< USB PHY Receiver Control Register, offset: 0x20 */
+  __IO uint32_t RX_SET;                            /**< USB PHY Receiver Control Register, offset: 0x24 */
+  __IO uint32_t RX_CLR;                            /**< USB PHY Receiver Control Register, offset: 0x28 */
+  __IO uint32_t RX_TOG;                            /**< USB PHY Receiver Control Register, offset: 0x2C */
+  __IO uint32_t CTRL;                              /**< USB PHY General Control Register, offset: 0x30 */
+  __IO uint32_t CTRL_SET;                          /**< USB PHY General Control Register, offset: 0x34 */
+  __IO uint32_t CTRL_CLR;                          /**< USB PHY General Control Register, offset: 0x38 */
+  __IO uint32_t CTRL_TOG;                          /**< USB PHY General Control Register, offset: 0x3C */
+  __IO uint32_t STATUS;                            /**< USB PHY Status Register, offset: 0x40 */
+       uint8_t RESERVED_0[12];
+  __IO uint32_t DEBUGr;                            /**< USB PHY Debug Register, offset: 0x50 */
+  __IO uint32_t DEBUG_SET;                         /**< USB PHY Debug Register, offset: 0x54 */
+  __IO uint32_t DEBUG_CLR;                         /**< USB PHY Debug Register, offset: 0x58 */
+  __IO uint32_t DEBUG_TOG;                         /**< USB PHY Debug Register, offset: 0x5C */
+  __I  uint32_t DEBUG0_STATUS;                     /**< UTMI Debug Status Register 0, offset: 0x60 */
+       uint8_t RESERVED_1[12];
+  __IO uint32_t DEBUG1;                            /**< UTMI Debug Status Register 1, offset: 0x70 */
+  __IO uint32_t DEBUG1_SET;                        /**< UTMI Debug Status Register 1, offset: 0x74 */
+  __IO uint32_t DEBUG1_CLR;                        /**< UTMI Debug Status Register 1, offset: 0x78 */
+  __IO uint32_t DEBUG1_TOG;                        /**< UTMI Debug Status Register 1, offset: 0x7C */
+  __I  uint32_t VERSION;                           /**< UTMI RTL Version, offset: 0x80 */
+       uint8_t RESERVED_2[28];
+  __IO uint32_t PLL_SIC;                           /**< USB PHY PLL Control/Status Register, offset: 0xA0 */
+  __IO uint32_t PLL_SIC_SET;                       /**< USB PHY PLL Control/Status Register, offset: 0xA4 */
+  __IO uint32_t PLL_SIC_CLR;                       /**< USB PHY PLL Control/Status Register, offset: 0xA8 */
+  __IO uint32_t PLL_SIC_TOG;                       /**< USB PHY PLL Control/Status Register, offset: 0xAC */
+       uint8_t RESERVED_3[16];
+  __IO uint32_t USB1_VBUS_DETECT;                  /**< USB PHY VBUS Detect Control Register, offset: 0xC0 */
+  __IO uint32_t USB1_VBUS_DETECT_SET;              /**< USB PHY VBUS Detect Control Register, offset: 0xC4 */
+  __IO uint32_t USB1_VBUS_DETECT_CLR;              /**< USB PHY VBUS Detect Control Register, offset: 0xC8 */
+  __IO uint32_t USB1_VBUS_DETECT_TOG;              /**< USB PHY VBUS Detect Control Register, offset: 0xCC */
+  __I  uint32_t USB1_VBUS_DET_STAT;                /**< USB PHY VBUS Detector Status Register, offset: 0xD0 */
+       uint8_t RESERVED_4[28];
+  __I  uint32_t USB1_CHRG_DET_STAT;                /**< USB PHY Charger Detect Status Register, offset: 0xF0 */
+       uint8_t RESERVED_5[12];
+  __IO uint32_t ANACTRL;                           /**< USB PHY Analog Control Register, offset: 0x100 */
+  __IO uint32_t ANACTRL_SET;                       /**< USB PHY Analog Control Register, offset: 0x104 */
+  __IO uint32_t ANACTRL_CLR;                       /**< USB PHY Analog Control Register, offset: 0x108 */
+  __IO uint32_t ANACTRL_TOG;                       /**< USB PHY Analog Control Register, offset: 0x10C */
+  __IO uint32_t USB1_LOOPBACK;                     /**< USB PHY Loopback Control/Status Register, offset: 0x110 */
+  __IO uint32_t USB1_LOOPBACK_SET;                 /**< USB PHY Loopback Control/Status Register, offset: 0x114 */
+  __IO uint32_t USB1_LOOPBACK_CLR;                 /**< USB PHY Loopback Control/Status Register, offset: 0x118 */
+  __IO uint32_t USB1_LOOPBACK_TOG;                 /**< USB PHY Loopback Control/Status Register, offset: 0x11C */
+  __IO uint32_t USB1_LOOPBACK_HSFSCNT;             /**< USB PHY Loopback Packet Number Select Register, offset: 0x120 */
+  __IO uint32_t USB1_LOOPBACK_HSFSCNT_SET;         /**< USB PHY Loopback Packet Number Select Register, offset: 0x124 */
+  __IO uint32_t USB1_LOOPBACK_HSFSCNT_CLR;         /**< USB PHY Loopback Packet Number Select Register, offset: 0x128 */
+  __IO uint32_t USB1_LOOPBACK_HSFSCNT_TOG;         /**< USB PHY Loopback Packet Number Select Register, offset: 0x12C */
+  __IO uint32_t TRIM_OVERRIDE_EN;                  /**< USB PHY Trim Override Enable Register, offset: 0x130 */
+  __IO uint32_t TRIM_OVERRIDE_EN_SET;              /**< USB PHY Trim Override Enable Register, offset: 0x134 */
+  __IO uint32_t TRIM_OVERRIDE_EN_CLR;              /**< USB PHY Trim Override Enable Register, offset: 0x138 */
+  __IO uint32_t TRIM_OVERRIDE_EN_TOG;              /**< USB PHY Trim Override Enable Register, offset: 0x13C */
+} USBPHY_Type;
+
+/* ----------------------------------------------------------------------------
+   -- USBPHY Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBPHY_Register_Masks USBPHY Register Masks
+ * @{
+ */
+
+/*! @name PWD - USB PHY Power-Down Register */
+#define USBPHY_PWD_TXPWDFS_MASK                  (0x400U)
+#define USBPHY_PWD_TXPWDFS_SHIFT                 (10U)
+#define USBPHY_PWD_TXPWDFS(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK)
+#define USBPHY_PWD_TXPWDIBIAS_MASK               (0x800U)
+#define USBPHY_PWD_TXPWDIBIAS_SHIFT              (11U)
+#define USBPHY_PWD_TXPWDIBIAS(x)                 (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK)
+#define USBPHY_PWD_TXPWDV2I_MASK                 (0x1000U)
+#define USBPHY_PWD_TXPWDV2I_SHIFT                (12U)
+#define USBPHY_PWD_TXPWDV2I(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK)
+#define USBPHY_PWD_RXPWDENV_MASK                 (0x20000U)
+#define USBPHY_PWD_RXPWDENV_SHIFT                (17U)
+#define USBPHY_PWD_RXPWDENV(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK)
+#define USBPHY_PWD_RXPWD1PT1_MASK                (0x40000U)
+#define USBPHY_PWD_RXPWD1PT1_SHIFT               (18U)
+#define USBPHY_PWD_RXPWD1PT1(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK)
+#define USBPHY_PWD_RXPWDDIFF_MASK                (0x80000U)
+#define USBPHY_PWD_RXPWDDIFF_SHIFT               (19U)
+#define USBPHY_PWD_RXPWDDIFF(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK)
+#define USBPHY_PWD_RXPWDRX_MASK                  (0x100000U)
+#define USBPHY_PWD_RXPWDRX_SHIFT                 (20U)
+#define USBPHY_PWD_RXPWDRX(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK)
+
+/*! @name PWD_SET - USB PHY Power-Down Register */
+#define USBPHY_PWD_SET_TXPWDFS_MASK              (0x400U)
+#define USBPHY_PWD_SET_TXPWDFS_SHIFT             (10U)
+#define USBPHY_PWD_SET_TXPWDFS(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK)
+#define USBPHY_PWD_SET_TXPWDIBIAS_MASK           (0x800U)
+#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT          (11U)
+#define USBPHY_PWD_SET_TXPWDIBIAS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK)
+#define USBPHY_PWD_SET_TXPWDV2I_MASK             (0x1000U)
+#define USBPHY_PWD_SET_TXPWDV2I_SHIFT            (12U)
+#define USBPHY_PWD_SET_TXPWDV2I(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK)
+#define USBPHY_PWD_SET_RXPWDENV_MASK             (0x20000U)
+#define USBPHY_PWD_SET_RXPWDENV_SHIFT            (17U)
+#define USBPHY_PWD_SET_RXPWDENV(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK)
+#define USBPHY_PWD_SET_RXPWD1PT1_MASK            (0x40000U)
+#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT           (18U)
+#define USBPHY_PWD_SET_RXPWD1PT1(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK)
+#define USBPHY_PWD_SET_RXPWDDIFF_MASK            (0x80000U)
+#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT           (19U)
+#define USBPHY_PWD_SET_RXPWDDIFF(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK)
+#define USBPHY_PWD_SET_RXPWDRX_MASK              (0x100000U)
+#define USBPHY_PWD_SET_RXPWDRX_SHIFT             (20U)
+#define USBPHY_PWD_SET_RXPWDRX(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK)
+
+/*! @name PWD_CLR - USB PHY Power-Down Register */
+#define USBPHY_PWD_CLR_TXPWDFS_MASK              (0x400U)
+#define USBPHY_PWD_CLR_TXPWDFS_SHIFT             (10U)
+#define USBPHY_PWD_CLR_TXPWDFS(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK)
+#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK           (0x800U)
+#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT          (11U)
+#define USBPHY_PWD_CLR_TXPWDIBIAS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK)
+#define USBPHY_PWD_CLR_TXPWDV2I_MASK             (0x1000U)
+#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT            (12U)
+#define USBPHY_PWD_CLR_TXPWDV2I(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK)
+#define USBPHY_PWD_CLR_RXPWDENV_MASK             (0x20000U)
+#define USBPHY_PWD_CLR_RXPWDENV_SHIFT            (17U)
+#define USBPHY_PWD_CLR_RXPWDENV(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK)
+#define USBPHY_PWD_CLR_RXPWD1PT1_MASK            (0x40000U)
+#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT           (18U)
+#define USBPHY_PWD_CLR_RXPWD1PT1(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK)
+#define USBPHY_PWD_CLR_RXPWDDIFF_MASK            (0x80000U)
+#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT           (19U)
+#define USBPHY_PWD_CLR_RXPWDDIFF(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK)
+#define USBPHY_PWD_CLR_RXPWDRX_MASK              (0x100000U)
+#define USBPHY_PWD_CLR_RXPWDRX_SHIFT             (20U)
+#define USBPHY_PWD_CLR_RXPWDRX(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK)
+
+/*! @name PWD_TOG - USB PHY Power-Down Register */
+#define USBPHY_PWD_TOG_TXPWDFS_MASK              (0x400U)
+#define USBPHY_PWD_TOG_TXPWDFS_SHIFT             (10U)
+#define USBPHY_PWD_TOG_TXPWDFS(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK)
+#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK           (0x800U)
+#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT          (11U)
+#define USBPHY_PWD_TOG_TXPWDIBIAS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK)
+#define USBPHY_PWD_TOG_TXPWDV2I_MASK             (0x1000U)
+#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT            (12U)
+#define USBPHY_PWD_TOG_TXPWDV2I(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK)
+#define USBPHY_PWD_TOG_RXPWDENV_MASK             (0x20000U)
+#define USBPHY_PWD_TOG_RXPWDENV_SHIFT            (17U)
+#define USBPHY_PWD_TOG_RXPWDENV(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK)
+#define USBPHY_PWD_TOG_RXPWD1PT1_MASK            (0x40000U)
+#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT           (18U)
+#define USBPHY_PWD_TOG_RXPWD1PT1(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK)
+#define USBPHY_PWD_TOG_RXPWDDIFF_MASK            (0x80000U)
+#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT           (19U)
+#define USBPHY_PWD_TOG_RXPWDDIFF(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK)
+#define USBPHY_PWD_TOG_RXPWDRX_MASK              (0x100000U)
+#define USBPHY_PWD_TOG_RXPWDRX_SHIFT             (20U)
+#define USBPHY_PWD_TOG_RXPWDRX(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK)
+
+/*! @name TX - USB PHY Transmitter Control Register */
+#define USBPHY_TX_D_CAL_MASK                     (0xFU)
+#define USBPHY_TX_D_CAL_SHIFT                    (0U)
+#define USBPHY_TX_D_CAL(x)                       (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK)
+#define USBPHY_TX_TXCAL45DM_MASK                 (0xF00U)
+#define USBPHY_TX_TXCAL45DM_SHIFT                (8U)
+#define USBPHY_TX_TXCAL45DM(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DM_SHIFT)) & USBPHY_TX_TXCAL45DM_MASK)
+#define USBPHY_TX_TXCAL45DP_MASK                 (0xF0000U)
+#define USBPHY_TX_TXCAL45DP_SHIFT                (16U)
+#define USBPHY_TX_TXCAL45DP(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK)
+#define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK        (0x1C000000U)
+#define USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT       (26U)
+#define USBPHY_TX_USBPHY_TX_EDGECTRL(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_USBPHY_TX_EDGECTRL_MASK)
+
+/*! @name TX_SET - USB PHY Transmitter Control Register */
+#define USBPHY_TX_SET_D_CAL_MASK                 (0xFU)
+#define USBPHY_TX_SET_D_CAL_SHIFT                (0U)
+#define USBPHY_TX_SET_D_CAL(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK)
+#define USBPHY_TX_SET_TXCAL45DM_MASK             (0xF00U)
+#define USBPHY_TX_SET_TXCAL45DM_SHIFT            (8U)
+#define USBPHY_TX_SET_TXCAL45DM(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DM_SHIFT)) & USBPHY_TX_SET_TXCAL45DM_MASK)
+#define USBPHY_TX_SET_TXCAL45DP_MASK             (0xF0000U)
+#define USBPHY_TX_SET_TXCAL45DP_SHIFT            (16U)
+#define USBPHY_TX_SET_TXCAL45DP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK)
+#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK    (0x1C000000U)
+#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT   (26U)
+#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK)
+
+/*! @name TX_CLR - USB PHY Transmitter Control Register */
+#define USBPHY_TX_CLR_D_CAL_MASK                 (0xFU)
+#define USBPHY_TX_CLR_D_CAL_SHIFT                (0U)
+#define USBPHY_TX_CLR_D_CAL(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK)
+#define USBPHY_TX_CLR_TXCAL45DM_MASK             (0xF00U)
+#define USBPHY_TX_CLR_TXCAL45DM_SHIFT            (8U)
+#define USBPHY_TX_CLR_TXCAL45DM(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DM_SHIFT)) & USBPHY_TX_CLR_TXCAL45DM_MASK)
+#define USBPHY_TX_CLR_TXCAL45DP_MASK             (0xF0000U)
+#define USBPHY_TX_CLR_TXCAL45DP_SHIFT            (16U)
+#define USBPHY_TX_CLR_TXCAL45DP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK)
+#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK    (0x1C000000U)
+#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT   (26U)
+#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK)
+
+/*! @name TX_TOG - USB PHY Transmitter Control Register */
+#define USBPHY_TX_TOG_D_CAL_MASK                 (0xFU)
+#define USBPHY_TX_TOG_D_CAL_SHIFT                (0U)
+#define USBPHY_TX_TOG_D_CAL(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK)
+#define USBPHY_TX_TOG_TXCAL45DM_MASK             (0xF00U)
+#define USBPHY_TX_TOG_TXCAL45DM_SHIFT            (8U)
+#define USBPHY_TX_TOG_TXCAL45DM(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DM_SHIFT)) & USBPHY_TX_TOG_TXCAL45DM_MASK)
+#define USBPHY_TX_TOG_TXCAL45DP_MASK             (0xF0000U)
+#define USBPHY_TX_TOG_TXCAL45DP_SHIFT            (16U)
+#define USBPHY_TX_TOG_TXCAL45DP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK)
+#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK    (0x1C000000U)
+#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT   (26U)
+#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK)
+
+/*! @name RX - USB PHY Receiver Control Register */
+#define USBPHY_RX_ENVADJ_MASK                    (0x7U)
+#define USBPHY_RX_ENVADJ_SHIFT                   (0U)
+#define USBPHY_RX_ENVADJ(x)                      (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK)
+#define USBPHY_RX_DISCONADJ_MASK                 (0x70U)
+#define USBPHY_RX_DISCONADJ_SHIFT                (4U)
+#define USBPHY_RX_DISCONADJ(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK)
+#define USBPHY_RX_RXDBYPASS_MASK                 (0x400000U)
+#define USBPHY_RX_RXDBYPASS_SHIFT                (22U)
+#define USBPHY_RX_RXDBYPASS(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK)
+
+/*! @name RX_SET - USB PHY Receiver Control Register */
+#define USBPHY_RX_SET_ENVADJ_MASK                (0x7U)
+#define USBPHY_RX_SET_ENVADJ_SHIFT               (0U)
+#define USBPHY_RX_SET_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK)
+#define USBPHY_RX_SET_DISCONADJ_MASK             (0x70U)
+#define USBPHY_RX_SET_DISCONADJ_SHIFT            (4U)
+#define USBPHY_RX_SET_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK)
+#define USBPHY_RX_SET_RXDBYPASS_MASK             (0x400000U)
+#define USBPHY_RX_SET_RXDBYPASS_SHIFT            (22U)
+#define USBPHY_RX_SET_RXDBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK)
+
+/*! @name RX_CLR - USB PHY Receiver Control Register */
+#define USBPHY_RX_CLR_ENVADJ_MASK                (0x7U)
+#define USBPHY_RX_CLR_ENVADJ_SHIFT               (0U)
+#define USBPHY_RX_CLR_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK)
+#define USBPHY_RX_CLR_DISCONADJ_MASK             (0x70U)
+#define USBPHY_RX_CLR_DISCONADJ_SHIFT            (4U)
+#define USBPHY_RX_CLR_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK)
+#define USBPHY_RX_CLR_RXDBYPASS_MASK             (0x400000U)
+#define USBPHY_RX_CLR_RXDBYPASS_SHIFT            (22U)
+#define USBPHY_RX_CLR_RXDBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK)
+
+/*! @name RX_TOG - USB PHY Receiver Control Register */
+#define USBPHY_RX_TOG_ENVADJ_MASK                (0x7U)
+#define USBPHY_RX_TOG_ENVADJ_SHIFT               (0U)
+#define USBPHY_RX_TOG_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK)
+#define USBPHY_RX_TOG_DISCONADJ_MASK             (0x70U)
+#define USBPHY_RX_TOG_DISCONADJ_SHIFT            (4U)
+#define USBPHY_RX_TOG_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK)
+#define USBPHY_RX_TOG_RXDBYPASS_MASK             (0x400000U)
+#define USBPHY_RX_TOG_RXDBYPASS_SHIFT            (22U)
+#define USBPHY_RX_TOG_RXDBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK)
+
+/*! @name CTRL - USB PHY General Control Register */
+#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK      (0x2U)
+#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT     (1U)
+#define USBPHY_CTRL_ENHOSTDISCONDETECT(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK)
+#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK    (0x8U)
+#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT   (3U)
+#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK)
+#define USBPHY_CTRL_ENDEVPLUGINDET_MASK          (0x10U)
+#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT         (4U)
+#define USBPHY_CTRL_ENDEVPLUGINDET(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDET_MASK)
+#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK           (0x1000U)
+#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT          (12U)
+#define USBPHY_CTRL_DEVPLUGIN_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK)
+#define USBPHY_CTRL_ENUTMILEVEL2_MASK            (0x4000U)
+#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT           (14U)
+#define USBPHY_CTRL_ENUTMILEVEL2(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK)
+#define USBPHY_CTRL_ENUTMILEVEL3_MASK            (0x8000U)
+#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT           (15U)
+#define USBPHY_CTRL_ENUTMILEVEL3(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK)
+#define USBPHY_CTRL_AUTORESUME_EN_MASK           (0x40000U)
+#define USBPHY_CTRL_AUTORESUME_EN_SHIFT          (18U)
+#define USBPHY_CTRL_AUTORESUME_EN(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK)
+#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK       (0x80000U)
+#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT      (19U)
+#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK)
+#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK       (0x100000U)
+#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT      (20U)
+#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK)
+#define USBPHY_CTRL_FSDLL_RST_EN_MASK            (0x1000000U)
+#define USBPHY_CTRL_FSDLL_RST_EN_SHIFT           (24U)
+#define USBPHY_CTRL_FSDLL_RST_EN(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK)
+#define USBPHY_CTRL_OTG_ID_VALUE_MASK            (0x8000000U)
+#define USBPHY_CTRL_OTG_ID_VALUE_SHIFT           (27U)
+#define USBPHY_CTRL_OTG_ID_VALUE(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK)
+#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK       (0x10000000U)
+#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT      (28U)
+#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK)
+#define USBPHY_CTRL_UTMI_SUSPENDM_MASK           (0x20000000U)
+#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT          (29U)
+#define USBPHY_CTRL_UTMI_SUSPENDM(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK)
+#define USBPHY_CTRL_CLKGATE_MASK                 (0x40000000U)
+#define USBPHY_CTRL_CLKGATE_SHIFT                (30U)
+#define USBPHY_CTRL_CLKGATE(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK)
+#define USBPHY_CTRL_SFTRST_MASK                  (0x80000000U)
+#define USBPHY_CTRL_SFTRST_SHIFT                 (31U)
+#define USBPHY_CTRL_SFTRST(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK)
+
+/*! @name CTRL_SET - USB PHY General Control Register */
+#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK  (0x2U)
+#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U)
+#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK)
+#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U)
+#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U)
+#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK)
+#define USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK      (0x10U)
+#define USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT     (4U)
+#define USBPHY_CTRL_SET_ENDEVPLUGINDET(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK)
+#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK       (0x1000U)
+#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT      (12U)
+#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK)
+#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK        (0x4000U)
+#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT       (14U)
+#define USBPHY_CTRL_SET_ENUTMILEVEL2(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK)
+#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK        (0x8000U)
+#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT       (15U)
+#define USBPHY_CTRL_SET_ENUTMILEVEL3(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK)
+#define USBPHY_CTRL_SET_AUTORESUME_EN_MASK       (0x40000U)
+#define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT      (18U)
+#define USBPHY_CTRL_SET_AUTORESUME_EN(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK)
+#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
+#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT  (19U)
+#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK)
+#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
+#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT  (20U)
+#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK)
+#define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK        (0x1000000U)
+#define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT       (24U)
+#define USBPHY_CTRL_SET_FSDLL_RST_EN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK)
+#define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK        (0x8000000U)
+#define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT       (27U)
+#define USBPHY_CTRL_SET_OTG_ID_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK)
+#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK   (0x10000000U)
+#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT  (28U)
+#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK)
+#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK       (0x20000000U)
+#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT      (29U)
+#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK)
+#define USBPHY_CTRL_SET_CLKGATE_MASK             (0x40000000U)
+#define USBPHY_CTRL_SET_CLKGATE_SHIFT            (30U)
+#define USBPHY_CTRL_SET_CLKGATE(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK)
+#define USBPHY_CTRL_SET_SFTRST_MASK              (0x80000000U)
+#define USBPHY_CTRL_SET_SFTRST_SHIFT             (31U)
+#define USBPHY_CTRL_SET_SFTRST(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK)
+
+/*! @name CTRL_CLR - USB PHY General Control Register */
+#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK  (0x2U)
+#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U)
+#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK)
+#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U)
+#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U)
+#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK)
+#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK      (0x10U)
+#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT     (4U)
+#define USBPHY_CTRL_CLR_ENDEVPLUGINDET(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK)
+#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK       (0x1000U)
+#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT      (12U)
+#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK)
+#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK        (0x4000U)
+#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT       (14U)
+#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK)
+#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK        (0x8000U)
+#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT       (15U)
+#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK)
+#define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK       (0x40000U)
+#define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT      (18U)
+#define USBPHY_CTRL_CLR_AUTORESUME_EN(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK)
+#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
+#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT  (19U)
+#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK)
+#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
+#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT  (20U)
+#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK)
+#define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK        (0x1000000U)
+#define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT       (24U)
+#define USBPHY_CTRL_CLR_FSDLL_RST_EN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK)
+#define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK        (0x8000000U)
+#define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT       (27U)
+#define USBPHY_CTRL_CLR_OTG_ID_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK)
+#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK   (0x10000000U)
+#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT  (28U)
+#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK)
+#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK       (0x20000000U)
+#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT      (29U)
+#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK)
+#define USBPHY_CTRL_CLR_CLKGATE_MASK             (0x40000000U)
+#define USBPHY_CTRL_CLR_CLKGATE_SHIFT            (30U)
+#define USBPHY_CTRL_CLR_CLKGATE(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK)
+#define USBPHY_CTRL_CLR_SFTRST_MASK              (0x80000000U)
+#define USBPHY_CTRL_CLR_SFTRST_SHIFT             (31U)
+#define USBPHY_CTRL_CLR_SFTRST(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK)
+
+/*! @name CTRL_TOG - USB PHY General Control Register */
+#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK  (0x2U)
+#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U)
+#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK)
+#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U)
+#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U)
+#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK)
+#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK      (0x10U)
+#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT     (4U)
+#define USBPHY_CTRL_TOG_ENDEVPLUGINDET(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK)
+#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK       (0x1000U)
+#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT      (12U)
+#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK)
+#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK        (0x4000U)
+#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT       (14U)
+#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK)
+#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK        (0x8000U)
+#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT       (15U)
+#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK)
+#define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK       (0x40000U)
+#define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT      (18U)
+#define USBPHY_CTRL_TOG_AUTORESUME_EN(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK)
+#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
+#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT  (19U)
+#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK)
+#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
+#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT  (20U)
+#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK)
+#define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK        (0x1000000U)
+#define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT       (24U)
+#define USBPHY_CTRL_TOG_FSDLL_RST_EN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK)
+#define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK        (0x8000000U)
+#define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT       (27U)
+#define USBPHY_CTRL_TOG_OTG_ID_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK)
+#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK   (0x10000000U)
+#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT  (28U)
+#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK)
+#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK       (0x20000000U)
+#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT      (29U)
+#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK)
+#define USBPHY_CTRL_TOG_CLKGATE_MASK             (0x40000000U)
+#define USBPHY_CTRL_TOG_CLKGATE_SHIFT            (30U)
+#define USBPHY_CTRL_TOG_CLKGATE(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK)
+#define USBPHY_CTRL_TOG_SFTRST_MASK              (0x80000000U)
+#define USBPHY_CTRL_TOG_SFTRST_SHIFT             (31U)
+#define USBPHY_CTRL_TOG_SFTRST(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK)
+
+/*! @name STATUS - USB PHY Status Register */
+#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U)
+#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U)
+#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK)
+#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK      (0x40U)
+#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT     (6U)
+#define USBPHY_STATUS_DEVPLUGIN_STATUS(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK)
+#define USBPHY_STATUS_OTGID_STATUS_MASK          (0x100U)
+#define USBPHY_STATUS_OTGID_STATUS_SHIFT         (8U)
+#define USBPHY_STATUS_OTGID_STATUS(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK)
+#define USBPHY_STATUS_RESUME_STATUS_MASK         (0x400U)
+#define USBPHY_STATUS_RESUME_STATUS_SHIFT        (10U)
+#define USBPHY_STATUS_RESUME_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK)
+
+/*! @name DEBUG - USB PHY Debug Register */
+#define USBPHY_DEBUG_OTGIDPIOLOCK_MASK           (0x1U)
+#define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT          (0U)
+#define USBPHY_DEBUG_OTGIDPIOLOCK(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK)
+#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK   (0x2U)
+#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT  (1U)
+#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK)
+#define USBPHY_DEBUG_HSTPULLDOWN_MASK            (0xCU)
+#define USBPHY_DEBUG_HSTPULLDOWN_SHIFT           (2U)
+#define USBPHY_DEBUG_HSTPULLDOWN(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK)
+#define USBPHY_DEBUG_ENHSTPULLDOWN_MASK          (0x30U)
+#define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT         (4U)
+#define USBPHY_DEBUG_ENHSTPULLDOWN(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK)
+#define USBPHY_DEBUG_TX2RXCOUNT_MASK             (0xF00U)
+#define USBPHY_DEBUG_TX2RXCOUNT_SHIFT            (8U)
+#define USBPHY_DEBUG_TX2RXCOUNT(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK)
+#define USBPHY_DEBUG_ENTX2RXCOUNT_MASK           (0x1000U)
+#define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT          (12U)
+#define USBPHY_DEBUG_ENTX2RXCOUNT(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK)
+#define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK      (0x1F0000U)
+#define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT     (16U)
+#define USBPHY_DEBUG_SQUELCHRESETCOUNT(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK)
+#define USBPHY_DEBUG_ENSQUELCHRESET_MASK         (0x1000000U)
+#define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT        (24U)
+#define USBPHY_DEBUG_ENSQUELCHRESET(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK)
+#define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK     (0x1E000000U)
+#define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT    (25U)
+#define USBPHY_DEBUG_SQUELCHRESETLENGTH(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK)
+#define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK      (0x20000000U)
+#define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT     (29U)
+#define USBPHY_DEBUG_HOST_RESUME_DEBUG(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK)
+#define USBPHY_DEBUG_CLKGATE_MASK                (0x40000000U)
+#define USBPHY_DEBUG_CLKGATE_SHIFT               (30U)
+#define USBPHY_DEBUG_CLKGATE(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK)
+
+/*! @name DEBUG_SET - USB PHY Debug Register */
+#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK       (0x1U)
+#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT      (0U)
+#define USBPHY_DEBUG_SET_OTGIDPIOLOCK(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK)
+#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U)
+#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U)
+#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK)
+#define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK        (0xCU)
+#define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT       (2U)
+#define USBPHY_DEBUG_SET_HSTPULLDOWN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK)
+#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK      (0x30U)
+#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT     (4U)
+#define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK)
+#define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK         (0xF00U)
+#define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT        (8U)
+#define USBPHY_DEBUG_SET_TX2RXCOUNT(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK)
+#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK       (0x1000U)
+#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT      (12U)
+#define USBPHY_DEBUG_SET_ENTX2RXCOUNT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK)
+#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK  (0x1F0000U)
+#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U)
+#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK)
+#define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK     (0x1000000U)
+#define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT    (24U)
+#define USBPHY_DEBUG_SET_ENSQUELCHRESET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK)
+#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U)
+#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U)
+#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK)
+#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK  (0x20000000U)
+#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U)
+#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK)
+#define USBPHY_DEBUG_SET_CLKGATE_MASK            (0x40000000U)
+#define USBPHY_DEBUG_SET_CLKGATE_SHIFT           (30U)
+#define USBPHY_DEBUG_SET_CLKGATE(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK)
+
+/*! @name DEBUG_CLR - USB PHY Debug Register */
+#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK       (0x1U)
+#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT      (0U)
+#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK)
+#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U)
+#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U)
+#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK)
+#define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK        (0xCU)
+#define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT       (2U)
+#define USBPHY_DEBUG_CLR_HSTPULLDOWN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK)
+#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK      (0x30U)
+#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT     (4U)
+#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK)
+#define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK         (0xF00U)
+#define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT        (8U)
+#define USBPHY_DEBUG_CLR_TX2RXCOUNT(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK)
+#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK       (0x1000U)
+#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT      (12U)
+#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK)
+#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK  (0x1F0000U)
+#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U)
+#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK)
+#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK     (0x1000000U)
+#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT    (24U)
+#define USBPHY_DEBUG_CLR_ENSQUELCHRESET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK)
+#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U)
+#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U)
+#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK)
+#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK  (0x20000000U)
+#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U)
+#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)
+#define USBPHY_DEBUG_CLR_CLKGATE_MASK            (0x40000000U)
+#define USBPHY_DEBUG_CLR_CLKGATE_SHIFT           (30U)
+#define USBPHY_DEBUG_CLR_CLKGATE(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK)
+
+/*! @name DEBUG_TOG - USB PHY Debug Register */
+#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK       (0x1U)
+#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT      (0U)
+#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK)
+#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
+#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
+#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK)
+#define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK        (0xCU)
+#define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT       (2U)
+#define USBPHY_DEBUG_TOG_HSTPULLDOWN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK)
+#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK      (0x30U)
+#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT     (4U)
+#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK)
+#define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK         (0xF00U)
+#define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT        (8U)
+#define USBPHY_DEBUG_TOG_TX2RXCOUNT(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK)
+#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK       (0x1000U)
+#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT      (12U)
+#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK)
+#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK  (0x1F0000U)
+#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U)
+#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK)
+#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK     (0x1000000U)
+#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT    (24U)
+#define USBPHY_DEBUG_TOG_ENSQUELCHRESET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK)
+#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
+#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U)
+#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK)
+#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK  (0x20000000U)
+#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U)
+#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK)
+#define USBPHY_DEBUG_TOG_CLKGATE_MASK            (0x40000000U)
+#define USBPHY_DEBUG_TOG_CLKGATE_SHIFT           (30U)
+#define USBPHY_DEBUG_TOG_CLKGATE(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK)
+
+/*! @name DEBUG0_STATUS - UTMI Debug Status Register 0 */
+#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU)
+#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U)
+#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK)
+#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U)
+#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U)
+#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK)
+#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK  (0xFC000000U)
+#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U)
+#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK)
+
+/*! @name DEBUG1 - UTMI Debug Status Register 1 */
+#define USBPHY_DEBUG1_ENTAILADJVD_MASK           (0x6000U)
+#define USBPHY_DEBUG1_ENTAILADJVD_SHIFT          (13U)
+#define USBPHY_DEBUG1_ENTAILADJVD(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK)
+
+/*! @name DEBUG1_SET - UTMI Debug Status Register 1 */
+#define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK       (0x6000U)
+#define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT      (13U)
+#define USBPHY_DEBUG1_SET_ENTAILADJVD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK)
+
+/*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */
+#define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK       (0x6000U)
+#define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT      (13U)
+#define USBPHY_DEBUG1_CLR_ENTAILADJVD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK)
+
+/*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */
+#define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK       (0x6000U)
+#define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT      (13U)
+#define USBPHY_DEBUG1_TOG_ENTAILADJVD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK)
+
+/*! @name VERSION - UTMI RTL Version */
+#define USBPHY_VERSION_STEP_MASK                 (0xFFFFU)
+#define USBPHY_VERSION_STEP_SHIFT                (0U)
+#define USBPHY_VERSION_STEP(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK)
+#define USBPHY_VERSION_MINOR_MASK                (0xFF0000U)
+#define USBPHY_VERSION_MINOR_SHIFT               (16U)
+#define USBPHY_VERSION_MINOR(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK)
+#define USBPHY_VERSION_MAJOR_MASK                (0xFF000000U)
+#define USBPHY_VERSION_MAJOR_SHIFT               (24U)
+#define USBPHY_VERSION_MAJOR(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK)
+
+/*! @name PLL_SIC - USB PHY PLL Control/Status Register */
+#define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK          (0x3U)
+#define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT         (0U)
+#define USBPHY_PLL_SIC_PLL_DIV_SEL(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)
+#define USBPHY_PLL_SIC_PLL_EN_USBx_CLKS_MASK      (0x40U)
+#define USBPHY_PLL_SIC_PLL_EN_USBx_CLKS_SHIFT     (6U)
+#define USBPHY_PLL_SIC_PLL_EN_USBx_CLKS(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USBx_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USBx_CLKS_MASK)
+#define USBPHY_PLL_SIC_PLL_HOLD_RING_OFF_MASK    (0x800U)
+#define USBPHY_PLL_SIC_PLL_HOLD_RING_OFF_SHIFT   (11U)
+#define USBPHY_PLL_SIC_PLL_HOLD_RING_OFF(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_HOLD_RING_OFF_SHIFT)) & USBPHY_PLL_SIC_PLL_HOLD_RING_OFF_MASK)
+#define USBPHY_PLL_SIC_PLL_POWER_MASK            (0x1000U)
+#define USBPHY_PLL_SIC_PLL_POWER_SHIFT           (12U)
+#define USBPHY_PLL_SIC_PLL_POWER(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK)
+#define USBPHY_PLL_SIC_PLL_ENABLE_MASK           (0x2000U)
+#define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT          (13U)
+#define USBPHY_PLL_SIC_PLL_ENABLE(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK)
+#define USBPHY_PLL_SIC_PLL_BYPASS_MASK           (0x10000U)
+#define USBPHY_PLL_SIC_PLL_BYPASS_SHIFT          (16U)
+#define USBPHY_PLL_SIC_PLL_BYPASS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_PLL_BYPASS_MASK)
+#define USBPHY_PLL_SIC_PLL_LOCK_MASK             (0x80000000U)
+#define USBPHY_PLL_SIC_PLL_LOCK_SHIFT            (31U)
+#define USBPHY_PLL_SIC_PLL_LOCK(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK)
+
+/*! @name PLL_SIC_SET - USB PHY PLL Control/Status Register */
+#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK      (0x3U)
+#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT     (0U)
+#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK)
+#define USBPHY_PLL_SIC_SET_PLL_EN_USBx_CLKS_MASK  (0x40U)
+#define USBPHY_PLL_SIC_SET_PLL_EN_USBx_CLKS_SHIFT (6U)
+#define USBPHY_PLL_SIC_SET_PLL_EN_USBx_CLKS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USBx_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USBx_CLKS_MASK)
+#define USBPHY_PLL_SIC_SET_PLL_HOLD_RING_OFF_MASK (0x800U)
+#define USBPHY_PLL_SIC_SET_PLL_HOLD_RING_OFF_SHIFT (11U)
+#define USBPHY_PLL_SIC_SET_PLL_HOLD_RING_OFF(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_HOLD_RING_OFF_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_HOLD_RING_OFF_MASK)
+#define USBPHY_PLL_SIC_SET_PLL_POWER_MASK        (0x1000U)
+#define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT       (12U)
+#define USBPHY_PLL_SIC_SET_PLL_POWER(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK)
+#define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK       (0x2000U)
+#define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT      (13U)
+#define USBPHY_PLL_SIC_SET_PLL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK)
+#define USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK       (0x10000U)
+#define USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT      (16U)
+#define USBPHY_PLL_SIC_SET_PLL_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK)
+#define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK         (0x80000000U)
+#define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT        (31U)
+#define USBPHY_PLL_SIC_SET_PLL_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK)
+
+/*! @name PLL_SIC_CLR - USB PHY PLL Control/Status Register */
+#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK      (0x3U)
+#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT     (0U)
+#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK)
+#define USBPHY_PLL_SIC_CLR_PLL_EN_USBx_CLKS_MASK  (0x40U)
+#define USBPHY_PLL_SIC_CLR_PLL_EN_USBx_CLKS_SHIFT (6U)
+#define USBPHY_PLL_SIC_CLR_PLL_EN_USBx_CLKS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USBx_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USBx_CLKS_MASK)
+#define USBPHY_PLL_SIC_CLR_PLL_HOLD_RING_OFF_MASK (0x800U)
+#define USBPHY_PLL_SIC_CLR_PLL_HOLD_RING_OFF_SHIFT (11U)
+#define USBPHY_PLL_SIC_CLR_PLL_HOLD_RING_OFF(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_HOLD_RING_OFF_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_HOLD_RING_OFF_MASK)
+#define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK        (0x1000U)
+#define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT       (12U)
+#define USBPHY_PLL_SIC_CLR_PLL_POWER(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK)
+#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK       (0x2000U)
+#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT      (13U)
+#define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK)
+#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK       (0x10000U)
+#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT      (16U)
+#define USBPHY_PLL_SIC_CLR_PLL_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK)
+#define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK         (0x80000000U)
+#define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT        (31U)
+#define USBPHY_PLL_SIC_CLR_PLL_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK)
+
+/*! @name PLL_SIC_TOG - USB PHY PLL Control/Status Register */
+#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK      (0x3U)
+#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT     (0U)
+#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK)
+#define USBPHY_PLL_SIC_TOG_PLL_EN_USBx_CLKS_MASK  (0x40U)
+#define USBPHY_PLL_SIC_TOG_PLL_EN_USBx_CLKS_SHIFT (6U)
+#define USBPHY_PLL_SIC_TOG_PLL_EN_USBx_CLKS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USBx_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USBx_CLKS_MASK)
+#define USBPHY_PLL_SIC_TOG_PLL_HOLD_RING_OFF_MASK (0x800U)
+#define USBPHY_PLL_SIC_TOG_PLL_HOLD_RING_OFF_SHIFT (11U)
+#define USBPHY_PLL_SIC_TOG_PLL_HOLD_RING_OFF(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_HOLD_RING_OFF_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_HOLD_RING_OFF_MASK)
+#define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK        (0x1000U)
+#define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT       (12U)
+#define USBPHY_PLL_SIC_TOG_PLL_POWER(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK)
+#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK       (0x2000U)
+#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT      (13U)
+#define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK)
+#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK       (0x10000U)
+#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT      (16U)
+#define USBPHY_PLL_SIC_TOG_PLL_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK)
+#define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK         (0x80000000U)
+#define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT        (31U)
+#define USBPHY_PLL_SIC_TOG_PLL_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK)
+
+/*! @name USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register */
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U)
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U)
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK)
+#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U)
+#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U)
+#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U)
+#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U)
+#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U)
+#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U)
+#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U)
+#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U)
+#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U)
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U)
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U)
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U)
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK)
+#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U)
+#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U)
+#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK)
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U)
+#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK)
+#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK  (0x100000U)
+#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U)
+#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK)
+#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U)
+#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U)
+#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK)
+#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK (0x80000000U)
+#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT (31U)
+#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK)
+
+/*! @name USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register */
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U)
+#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U)
+#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U)
+#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U)
+#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U)
+#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U)
+#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U)
+#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x100000U)
+#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U)
+#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U)
+#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U)
+#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK)
+#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK (0x80000000U)
+#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT (31U)
+#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK)
+
+/*! @name USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register */
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x100000U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK)
+#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK (0x80000000U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT (31U)
+#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK)
+
+/*! @name USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register */
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x100000U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK)
+#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK (0x80000000U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT (31U)
+#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK)
+
+/*! @name USB1_VBUS_DET_STAT - USB PHY VBUS Detector Status Register */
+#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK   (0x1U)
+#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT  (0U)
+#define USBPHY_USB1_VBUS_DET_STAT_SESSEND(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK)
+#define USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK    (0x2U)
+#define USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT   (1U)
+#define USBPHY_USB1_VBUS_DET_STAT_BVALID(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK)
+#define USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK    (0x4U)
+#define USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT   (2U)
+#define USBPHY_USB1_VBUS_DET_STAT_AVALID(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK)
+#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK (0x8U)
+#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT (3U)
+#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK)
+#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK (0x10U)
+#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT (4U)
+#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK)
+
+/*! @name USB1_CHRG_DET_STAT - USB PHY Charger Detect Status Register */
+#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK (0x1U)
+#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT (0U)
+#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK)
+#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK (0x2U)
+#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT (1U)
+#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK)
+#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK  (0x4U)
+#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT (2U)
+#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK)
+#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK  (0x8U)
+#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT (3U)
+#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK)
+#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK (0x10U)
+#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT (4U)
+#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK)
+
+/*! @name ANACTRL - USB PHY Analog Control Register */
+#define USBPHY_ANACTRL_TESTCLK_SEL_MASK          (0x1U)
+#define USBPHY_ANACTRL_TESTCLK_SEL_SHIFT         (0U)
+#define USBPHY_ANACTRL_TESTCLK_SEL(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TESTCLK_SEL_SHIFT)) & USBPHY_ANACTRL_TESTCLK_SEL_MASK)
+#define USBPHY_ANACTRL_PFD_CLKGATE_MASK          (0x2U)
+#define USBPHY_ANACTRL_PFD_CLKGATE_SHIFT         (1U)
+#define USBPHY_ANACTRL_PFD_CLKGATE(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLKGATE_SHIFT)) & USBPHY_ANACTRL_PFD_CLKGATE_MASK)
+#define USBPHY_ANACTRL_PFD_CLK_SEL_MASK          (0xCU)
+#define USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT         (2U)
+#define USBPHY_ANACTRL_PFD_CLK_SEL(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_PFD_CLK_SEL_MASK)
+#define USBPHY_ANACTRL_PFD_FRAC_MASK             (0x3F0U)
+#define USBPHY_ANACTRL_PFD_FRAC_SHIFT            (4U)
+#define USBPHY_ANACTRL_PFD_FRAC(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_FRAC_SHIFT)) & USBPHY_ANACTRL_PFD_FRAC_MASK)
+#define USBPHY_ANACTRL_DEV_PULLDOWN_MASK         (0x400U)
+#define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT        (10U)
+#define USBPHY_ANACTRL_DEV_PULLDOWN(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK)
+#define USBPHY_ANACTRL_EMPH_PULSE_CTRL_MASK      (0x1800U)
+#define USBPHY_ANACTRL_EMPH_PULSE_CTRL_SHIFT     (11U)
+#define USBPHY_ANACTRL_EMPH_PULSE_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_EMPH_PULSE_CTRL_SHIFT)) & USBPHY_ANACTRL_EMPH_PULSE_CTRL_MASK)
+#define USBPHY_ANACTRL_EMPH_EN_MASK              (0x2000U)
+#define USBPHY_ANACTRL_EMPH_EN_SHIFT             (13U)
+#define USBPHY_ANACTRL_EMPH_EN(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_EMPH_EN_SHIFT)) & USBPHY_ANACTRL_EMPH_EN_MASK)
+#define USBPHY_ANACTRL_EMPH_CUR_CTRL_MASK        (0xC000U)
+#define USBPHY_ANACTRL_EMPH_CUR_CTRL_SHIFT       (14U)
+#define USBPHY_ANACTRL_EMPH_CUR_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_EMPH_CUR_CTRL_SHIFT)) & USBPHY_ANACTRL_EMPH_CUR_CTRL_MASK)
+#define USBPHY_ANACTRL_PFD_STABLE_MASK           (0x80000000U)
+#define USBPHY_ANACTRL_PFD_STABLE_SHIFT          (31U)
+#define USBPHY_ANACTRL_PFD_STABLE(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_STABLE_SHIFT)) & USBPHY_ANACTRL_PFD_STABLE_MASK)
+
+/*! @name ANACTRL_SET - USB PHY Analog Control Register */
+#define USBPHY_ANACTRL_SET_TESTCLK_SEL_MASK      (0x1U)
+#define USBPHY_ANACTRL_SET_TESTCLK_SEL_SHIFT     (0U)
+#define USBPHY_ANACTRL_SET_TESTCLK_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_TESTCLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_TESTCLK_SEL_MASK)
+#define USBPHY_ANACTRL_SET_PFD_CLKGATE_MASK      (0x2U)
+#define USBPHY_ANACTRL_SET_PFD_CLKGATE_SHIFT     (1U)
+#define USBPHY_ANACTRL_SET_PFD_CLKGATE(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLKGATE_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLKGATE_MASK)
+#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK      (0xCU)
+#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT     (2U)
+#define USBPHY_ANACTRL_SET_PFD_CLK_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK)
+#define USBPHY_ANACTRL_SET_PFD_FRAC_MASK         (0x3F0U)
+#define USBPHY_ANACTRL_SET_PFD_FRAC_SHIFT        (4U)
+#define USBPHY_ANACTRL_SET_PFD_FRAC(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_FRAC_SHIFT)) & USBPHY_ANACTRL_SET_PFD_FRAC_MASK)
+#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK     (0x400U)
+#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT    (10U)
+#define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK)
+#define USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL_MASK  (0x1800U)
+#define USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL_SHIFT (11U)
+#define USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL_SHIFT)) & USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL_MASK)
+#define USBPHY_ANACTRL_SET_EMPH_EN_MASK          (0x2000U)
+#define USBPHY_ANACTRL_SET_EMPH_EN_SHIFT         (13U)
+#define USBPHY_ANACTRL_SET_EMPH_EN(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_EMPH_EN_SHIFT)) & USBPHY_ANACTRL_SET_EMPH_EN_MASK)
+#define USBPHY_ANACTRL_SET_EMPH_CUR_CTRL_MASK    (0xC000U)
+#define USBPHY_ANACTRL_SET_EMPH_CUR_CTRL_SHIFT   (14U)
+#define USBPHY_ANACTRL_SET_EMPH_CUR_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_EMPH_CUR_CTRL_SHIFT)) & USBPHY_ANACTRL_SET_EMPH_CUR_CTRL_MASK)
+#define USBPHY_ANACTRL_SET_PFD_STABLE_MASK       (0x80000000U)
+#define USBPHY_ANACTRL_SET_PFD_STABLE_SHIFT      (31U)
+#define USBPHY_ANACTRL_SET_PFD_STABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_STABLE_SHIFT)) & USBPHY_ANACTRL_SET_PFD_STABLE_MASK)
+
+/*! @name ANACTRL_CLR - USB PHY Analog Control Register */
+#define USBPHY_ANACTRL_CLR_TESTCLK_SEL_MASK      (0x1U)
+#define USBPHY_ANACTRL_CLR_TESTCLK_SEL_SHIFT     (0U)
+#define USBPHY_ANACTRL_CLR_TESTCLK_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_TESTCLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_TESTCLK_SEL_MASK)
+#define USBPHY_ANACTRL_CLR_PFD_CLKGATE_MASK      (0x2U)
+#define USBPHY_ANACTRL_CLR_PFD_CLKGATE_SHIFT     (1U)
+#define USBPHY_ANACTRL_CLR_PFD_CLKGATE(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLKGATE_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLKGATE_MASK)
+#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK      (0xCU)
+#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT     (2U)
+#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK)
+#define USBPHY_ANACTRL_CLR_PFD_FRAC_MASK         (0x3F0U)
+#define USBPHY_ANACTRL_CLR_PFD_FRAC_SHIFT        (4U)
+#define USBPHY_ANACTRL_CLR_PFD_FRAC(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_FRAC_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_FRAC_MASK)
+#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK     (0x400U)
+#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT    (10U)
+#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK)
+#define USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL_MASK  (0x1800U)
+#define USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL_SHIFT (11U)
+#define USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL_SHIFT)) & USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL_MASK)
+#define USBPHY_ANACTRL_CLR_EMPH_EN_MASK          (0x2000U)
+#define USBPHY_ANACTRL_CLR_EMPH_EN_SHIFT         (13U)
+#define USBPHY_ANACTRL_CLR_EMPH_EN(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_EMPH_EN_SHIFT)) & USBPHY_ANACTRL_CLR_EMPH_EN_MASK)
+#define USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL_MASK    (0xC000U)
+#define USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL_SHIFT   (14U)
+#define USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL_SHIFT)) & USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL_MASK)
+#define USBPHY_ANACTRL_CLR_PFD_STABLE_MASK       (0x80000000U)
+#define USBPHY_ANACTRL_CLR_PFD_STABLE_SHIFT      (31U)
+#define USBPHY_ANACTRL_CLR_PFD_STABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_STABLE_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_STABLE_MASK)
+
+/*! @name ANACTRL_TOG - USB PHY Analog Control Register */
+#define USBPHY_ANACTRL_TOG_TESTCLK_SEL_MASK      (0x1U)
+#define USBPHY_ANACTRL_TOG_TESTCLK_SEL_SHIFT     (0U)
+#define USBPHY_ANACTRL_TOG_TESTCLK_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_TESTCLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_TESTCLK_SEL_MASK)
+#define USBPHY_ANACTRL_TOG_PFD_CLKGATE_MASK      (0x2U)
+#define USBPHY_ANACTRL_TOG_PFD_CLKGATE_SHIFT     (1U)
+#define USBPHY_ANACTRL_TOG_PFD_CLKGATE(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLKGATE_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLKGATE_MASK)
+#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK      (0xCU)
+#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT     (2U)
+#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK)
+#define USBPHY_ANACTRL_TOG_PFD_FRAC_MASK         (0x3F0U)
+#define USBPHY_ANACTRL_TOG_PFD_FRAC_SHIFT        (4U)
+#define USBPHY_ANACTRL_TOG_PFD_FRAC(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_FRAC_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_FRAC_MASK)
+#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK     (0x400U)
+#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT    (10U)
+#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK)
+#define USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL_MASK  (0x1800U)
+#define USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL_SHIFT (11U)
+#define USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL_SHIFT)) & USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL_MASK)
+#define USBPHY_ANACTRL_TOG_EMPH_EN_MASK          (0x2000U)
+#define USBPHY_ANACTRL_TOG_EMPH_EN_SHIFT         (13U)
+#define USBPHY_ANACTRL_TOG_EMPH_EN(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_EMPH_EN_SHIFT)) & USBPHY_ANACTRL_TOG_EMPH_EN_MASK)
+#define USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL_MASK    (0xC000U)
+#define USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL_SHIFT   (14U)
+#define USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL_SHIFT)) & USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL_MASK)
+#define USBPHY_ANACTRL_TOG_PFD_STABLE_MASK       (0x80000000U)
+#define USBPHY_ANACTRL_TOG_PFD_STABLE_SHIFT      (31U)
+#define USBPHY_ANACTRL_TOG_PFD_STABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_STABLE_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_STABLE_MASK)
+
+/*! @name USB1_LOOPBACK - USB PHY Loopback Control/Status Register */
+#define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK (0x1U)
+#define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT (0U)
+#define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK)
+#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK  (0x2U)
+#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT (1U)
+#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK)
+#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK  (0x4U)
+#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT (2U)
+#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK)
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK (0x8U)
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT (3U)
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK)
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK (0x10U)
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT (4U)
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK)
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK     (0x20U)
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT    (5U)
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_EN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK)
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK    (0x40U)
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT   (6U)
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK)
+#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK  (0x80U)
+#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT (7U)
+#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK)
+#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK  (0x100U)
+#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT (8U)
+#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK)
+#define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK (0x8000U)
+#define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT (15U)
+#define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK)
+#define USBPHY_USB1_LOOPBACK_TSTPKT_MASK         (0xFF0000U)
+#define USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT        (16U)
+#define USBPHY_USB1_LOOPBACK_TSTPKT(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTPKT_MASK)
+
+/*! @name USB1_LOOPBACK_SET - USB PHY Loopback Control/Status Register */
+#define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK (0x1U)
+#define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT (0U)
+#define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK)
+#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK (0x2U)
+#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT (1U)
+#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK)
+#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK (0x4U)
+#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT (2U)
+#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK (0x8U)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT (3U)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK (0x10U)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT (4U)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK (0x20U)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT (5U)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK (0x40U)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT (6U)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK)
+#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK (0x80U)
+#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT (7U)
+#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK)
+#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK (0x100U)
+#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT (8U)
+#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK (0x8000U)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT (15U)
+#define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK)
+#define USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK     (0xFF0000U)
+#define USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT    (16U)
+#define USBPHY_USB1_LOOPBACK_SET_TSTPKT(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK)
+
+/*! @name USB1_LOOPBACK_CLR - USB PHY Loopback Control/Status Register */
+#define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK (0x1U)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT (0U)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK (0x2U)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT (1U)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK (0x4U)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT (2U)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK (0x8U)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT (3U)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK (0x10U)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT (4U)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK (0x20U)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT (5U)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK (0x40U)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT (6U)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK (0x80U)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT (7U)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK (0x100U)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT (8U)
+#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK (0x8000U)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT (15U)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK     (0xFF0000U)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT    (16U)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTPKT(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK)
+
+/*! @name USB1_LOOPBACK_TOG - USB PHY Loopback Control/Status Register */
+#define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK (0x1U)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT (0U)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK (0x2U)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT (1U)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK (0x4U)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT (2U)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK (0x8U)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT (3U)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK (0x10U)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT (4U)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK (0x20U)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT (5U)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK (0x40U)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT (6U)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK (0x80U)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT (7U)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK (0x100U)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT (8U)
+#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK (0x8000U)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT (15U)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK     (0xFF0000U)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT    (16U)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTPKT(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK)
+
+/*! @name USB1_LOOPBACK_HSFSCNT - USB PHY Loopback Packet Number Select Register */
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK (0xFFFFU)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT (0U)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT (16U)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK)
+
+/*! @name USB1_LOOPBACK_HSFSCNT_SET - USB PHY Loopback Packet Number Select Register */
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK (0xFFFFU)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT (0U)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT (16U)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK)
+
+/*! @name USB1_LOOPBACK_HSFSCNT_CLR - USB PHY Loopback Packet Number Select Register */
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK (0xFFFFU)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT (0U)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT (16U)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK)
+
+/*! @name USB1_LOOPBACK_HSFSCNT_TOG - USB PHY Loopback Packet Number Select Register */
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK (0xFFFFU)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT (0U)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT (16U)
+#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK)
+
+/*! @name TRIM_OVERRIDE_EN - USB PHY Trim Override Enable Register */
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DM_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x30000U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (16U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBx_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBx_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBx_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBx_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBx_REG_ENV_TAIL_ADJ_VD_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U)
+#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DM_MASK)
+
+/*! @name TRIM_OVERRIDE_EN_SET - USB PHY Trim Override Enable Register */
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DM_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x30000U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (16U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBx_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBx_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBx_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBx_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBx_REG_ENV_TAIL_ADJ_VD_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U)
+#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DM_MASK)
+
+/*! @name TRIM_OVERRIDE_EN_CLR - USB PHY Trim Override Enable Register */
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DM_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x30000U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (16U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBx_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBx_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBx_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBx_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBx_REG_ENV_TAIL_ADJ_VD_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U)
+#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DM_MASK)
+
+/*! @name TRIM_OVERRIDE_EN_TOG - USB PHY Trim Override Enable Register */
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_MASK (0x10U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_SHIFT (4U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DM_OVERRIDE_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x30000U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (16U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBx_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBx_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBx_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBx_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBx_REG_ENV_TAIL_ADJ_VD_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_MASK (0xF0000000U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_SHIFT (28U)
+#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DM_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group USBPHY_Register_Masks */
+
+
+/* USBPHY - Peripheral instance base addresses */
+/** Peripheral USBPHY base address */
+#define USBPHY_BASE                              (0x400A2000u)
+/** Peripheral USBPHY base pointer */
+#define USBPHY                                   ((USBPHY_Type *)USBPHY_BASE)
+/** Array initializer of USBPHY peripheral base addresses */
+#define USBPHY_BASE_ADDRS                        { USBPHY_BASE }
+/** Array initializer of USBPHY peripheral base pointers */
+#define USBPHY_BASE_PTRS                         { USBPHY }
+
+/*!
+ * @}
+ */ /* end of group USBPHY_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- VREF Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
+ * @{
+ */
+
+/** VREF - Register Layout Typedef */
+typedef struct {
+  __IO uint8_t TRM;                                /**< VREF Trim Register, offset: 0x0 */
+  __IO uint8_t SC;                                 /**< VREF Status and Control Register, offset: 0x1 */
+} VREF_Type;
+
+/* ----------------------------------------------------------------------------
+   -- VREF Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup VREF_Register_Masks VREF Register Masks
+ * @{
+ */
+
+/*! @name TRM - VREF Trim Register */
+#define VREF_TRM_TRIM_MASK                       (0x3FU)
+#define VREF_TRM_TRIM_SHIFT                      (0U)
+#define VREF_TRM_TRIM(x)                         (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK)
+#define VREF_TRM_CHOPEN_MASK                     (0x40U)
+#define VREF_TRM_CHOPEN_SHIFT                    (6U)
+#define VREF_TRM_CHOPEN(x)                       (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK)
+
+/*! @name SC - VREF Status and Control Register */
+#define VREF_SC_MODE_LV_MASK                     (0x3U)
+#define VREF_SC_MODE_LV_SHIFT                    (0U)
+#define VREF_SC_MODE_LV(x)                       (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK)
+#define VREF_SC_VREFST_MASK                      (0x4U)
+#define VREF_SC_VREFST_SHIFT                     (2U)
+#define VREF_SC_VREFST(x)                        (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK)
+#define VREF_SC_ICOMPEN_MASK                     (0x20U)
+#define VREF_SC_ICOMPEN_SHIFT                    (5U)
+#define VREF_SC_ICOMPEN(x)                       (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK)
+#define VREF_SC_REGEN_MASK                       (0x40U)
+#define VREF_SC_REGEN_SHIFT                      (6U)
+#define VREF_SC_REGEN(x)                         (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK)
+#define VREF_SC_VREFEN_MASK                      (0x80U)
+#define VREF_SC_VREFEN_SHIFT                     (7U)
+#define VREF_SC_VREFEN(x)                        (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group VREF_Register_Masks */
+
+
+/* VREF - Peripheral instance base addresses */
+/** Peripheral VREF base address */
+#define VREF_BASE                                (0x40074000u)
+/** Peripheral VREF base pointer */
+#define VREF                                     ((VREF_Type *)VREF_BASE)
+/** Array initializer of VREF peripheral base addresses */
+#define VREF_BASE_ADDRS                          { VREF_BASE }
+/** Array initializer of VREF peripheral base pointers */
+#define VREF_BASE_PTRS                           { VREF }
+
+/*!
+ * @}
+ */ /* end of group VREF_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- WDOG Peripheral Access Layer
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
+ * @{
+ */
+
+/** WDOG - Register Layout Typedef */
+typedef struct {
+  __IO uint16_t STCTRLH;                           /**< Watchdog Status and Control Register High, offset: 0x0 */
+  __IO uint16_t STCTRLL;                           /**< Watchdog Status and Control Register Low, offset: 0x2 */
+  __IO uint16_t TOVALH;                            /**< Watchdog Time-out Value Register High, offset: 0x4 */
+  __IO uint16_t TOVALL;                            /**< Watchdog Time-out Value Register Low, offset: 0x6 */
+  __IO uint16_t WINH;                              /**< Watchdog Window Register High, offset: 0x8 */
+  __IO uint16_t WINL;                              /**< Watchdog Window Register Low, offset: 0xA */
+  __IO uint16_t REFRESH;                           /**< Watchdog Refresh register, offset: 0xC */
+  __IO uint16_t UNLOCK;                            /**< Watchdog Unlock register, offset: 0xE */
+  __IO uint16_t TMROUTH;                           /**< Watchdog Timer Output Register High, offset: 0x10 */
+  __IO uint16_t TMROUTL;                           /**< Watchdog Timer Output Register Low, offset: 0x12 */
+  __IO uint16_t RSTCNT;                            /**< Watchdog Reset Count register, offset: 0x14 */
+  __IO uint16_t PRESC;                             /**< Watchdog Prescaler register, offset: 0x16 */
+} WDOG_Type;
+
+/* ----------------------------------------------------------------------------
+   -- WDOG Register Masks
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WDOG_Register_Masks WDOG Register Masks
+ * @{
+ */
+
+/*! @name STCTRLH - Watchdog Status and Control Register High */
+#define WDOG_STCTRLH_WDOGEN_MASK                 (0x1U)
+#define WDOG_STCTRLH_WDOGEN_SHIFT                (0U)
+#define WDOG_STCTRLH_WDOGEN_SET(x)               (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WDOGEN_SHIFT)) & WDOG_STCTRLH_WDOGEN_MASK)
+#define WDOG_STCTRLH_WDOGEN                      WDOG_STCTRLH_WDOGEN_SET(1)
+#define WDOG_STCTRLH_CLKSRC_MASK                 (0x2U)
+#define WDOG_STCTRLH_CLKSRC_SHIFT                (1U)
+#define WDOG_STCTRLH_CLKSRC(x)                   (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK)
+#define WDOG_STCTRLH_IRQRSTEN_MASK               (0x4U)
+#define WDOG_STCTRLH_IRQRSTEN_SHIFT              (2U)
+#define WDOG_STCTRLH_IRQRSTEN(x)                 (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK)
+#define WDOG_STCTRLH_WINEN_MASK                  (0x8U)
+#define WDOG_STCTRLH_WINEN_SHIFT                 (3U)
+#define WDOG_STCTRLH_WINEN(x)                    (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK)
+#define WDOG_STCTRLH_ALLOWUPDATE_MASK            (0x10U)
+#define WDOG_STCTRLH_ALLOWUPDATE_SHIFT           (4U)
+#define WDOG_STCTRLH_ALLOWUPDATE(x)              (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK)
+#define WDOG_STCTRLH_DBGEN_MASK                  (0x20U)
+#define WDOG_STCTRLH_DBGEN_SHIFT                 (5U)
+#define WDOG_STCTRLH_DBGEN(x)                    (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK)
+#define WDOG_STCTRLH_STOPEN_MASK                 (0x40U)
+#define WDOG_STCTRLH_STOPEN_SHIFT                (6U)
+#define WDOG_STCTRLH_STOPEN(x)                   (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK)
+#define WDOG_STCTRLH_WAITEN_MASK                 (0x80U)
+#define WDOG_STCTRLH_WAITEN_SHIFT                (7U)
+#define WDOG_STCTRLH_WAITEN(x)                   (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WAITEN_SHIFT)) & WDOG_STCTRLH_WAITEN_MASK)
+#define WDOG_STCTRLH_TESTWDOG_MASK               (0x400U)
+#define WDOG_STCTRLH_TESTWDOG_SHIFT              (10U)
+#define WDOG_STCTRLH_TESTWDOG(x)                 (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK)
+#define WDOG_STCTRLH_TESTSEL_MASK                (0x800U)
+#define WDOG_STCTRLH_TESTSEL_SHIFT               (11U)
+#define WDOG_STCTRLH_TESTSEL(x)                  (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK)
+#define WDOG_STCTRLH_BYTESEL_MASK                (0x3000U)
+#define WDOG_STCTRLH_BYTESEL_SHIFT               (12U)
+#define WDOG_STCTRLH_BYTESEL(x)                  (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK)
+#define WDOG_STCTRLH_DISTESTWDOG_MASK            (0x4000U)
+#define WDOG_STCTRLH_DISTESTWDOG_SHIFT           (14U)
+#define WDOG_STCTRLH_DISTESTWDOG(x)              (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK)
+
+/*! @name STCTRLL - Watchdog Status and Control Register Low */
+#define WDOG_STCTRLL_INTFLG_MASK                 (0x8000U)
+#define WDOG_STCTRLL_INTFLG_SHIFT                (15U)
+#define WDOG_STCTRLL_INTFLG(x)                   (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK)
+
+/*! @name TOVALH - Watchdog Time-out Value Register High */
+#define WDOG_TOVALH_TOVALHIGH_MASK               (0xFFFFU)
+#define WDOG_TOVALH_TOVALHIGH_SHIFT              (0U)
+#define WDOG_TOVALH_TOVALHIGH(x)                 (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK)
+
+/*! @name TOVALL - Watchdog Time-out Value Register Low */
+#define WDOG_TOVALL_TOVALLOW_MASK                (0xFFFFU)
+#define WDOG_TOVALL_TOVALLOW_SHIFT               (0U)
+#define WDOG_TOVALL_TOVALLOW(x)                  (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK)
+
+/*! @name WINH - Watchdog Window Register High */
+#define WDOG_WINH_WINHIGH_MASK                   (0xFFFFU)
+#define WDOG_WINH_WINHIGH_SHIFT                  (0U)
+#define WDOG_WINH_WINHIGH(x)                     (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK)
+
+/*! @name WINL - Watchdog Window Register Low */
+#define WDOG_WINL_WINLOW_MASK                    (0xFFFFU)
+#define WDOG_WINL_WINLOW_SHIFT                   (0U)
+#define WDOG_WINL_WINLOW(x)                      (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK)
+
+/*! @name REFRESH - Watchdog Refresh register */
+#define WDOG_REFRESH_WDOGREFRESH_MASK            (0xFFFFU)
+#define WDOG_REFRESH_WDOGREFRESH_SHIFT           (0U)
+#define WDOG_REFRESH_WDOGREFRESH(x)              (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK)
+
+/*! @name UNLOCK - Watchdog Unlock register */
+#define WDOG_UNLOCK_WDOGUNLOCK_MASK              (0xFFFFU)
+#define WDOG_UNLOCK_WDOGUNLOCK_SHIFT             (0U)
+#define WDOG_UNLOCK_WDOGUNLOCK(x)                (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK)
+
+/*! @name TMROUTH - Watchdog Timer Output Register High */
+#define WDOG_TMROUTH_TIMEROUTHIGH_MASK           (0xFFFFU)
+#define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT          (0U)
+#define WDOG_TMROUTH_TIMEROUTHIGH(x)             (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK)
+
+/*! @name TMROUTL - Watchdog Timer Output Register Low */
+#define WDOG_TMROUTL_TIMEROUTLOW_MASK            (0xFFFFU)
+#define WDOG_TMROUTL_TIMEROUTLOW_SHIFT           (0U)
+#define WDOG_TMROUTL_TIMEROUTLOW(x)              (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK)
+
+/*! @name RSTCNT - Watchdog Reset Count register */
+#define WDOG_RSTCNT_RSTCNT_MASK                  (0xFFFFU)
+#define WDOG_RSTCNT_RSTCNT_SHIFT                 (0U)
+#define WDOG_RSTCNT_RSTCNT(x)                    (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK)
+
+/*! @name PRESC - Watchdog Prescaler register */
+#define WDOG_PRESC_PRESCVAL_MASK                 (0x700U)
+#define WDOG_PRESC_PRESCVAL_SHIFT                (8U)
+#define WDOG_PRESC_PRESCVAL(x)                   (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group WDOG_Register_Masks */
+
+
+/* WDOG - Peripheral instance base addresses */
+/** Peripheral WDOG base address */
+#define WDOG_BASE                                (0x40052000u)
+/** Peripheral WDOG base pointer */
+#define WDOG                                     ((WDOG_Type *)WDOG_BASE)
+/** Array initializer of WDOG peripheral base addresses */
+#define WDOG_BASE_ADDRS                          { WDOG_BASE }
+/** Array initializer of WDOG peripheral base pointers */
+#define WDOG_BASE_PTRS                           { WDOG }
+/** Interrupt vectors for the WDOG peripheral type */
+#define WDOG_IRQS                                { WDOG_EWM_IRQn }
+
+/*!
+ * @}
+ */ /* end of group WDOG_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang diagnostic pop
+  #else
+    #pragma pop
+  #endif
+#elif defined(__CWCC__)
+  #pragma pop
+#elif defined(__GNUC__)
+  /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma language=default
+#else
+  #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+   -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+ * @{
+ */
+
+#if defined(__ARMCC_VERSION)
+  #if (__ARMCC_VERSION >= 6010050)
+    #pragma clang system_header
+  #endif
+#elif defined(__IAR_SYSTEMS_ICC__)
+  #pragma system_include
+#endif
+
+/**
+ * @brief Mask and left-shift a bit field value for use in a register bit range.
+ * @param field Name of the register bit field.
+ * @param value Value of the bit field.
+ * @return Masked and shifted value.
+ */
+#define NXP_VAL2FLD(field, value)    (((value) << (field ## _SHIFT)) & (field ## _MASK))
+/**
+ * @brief Mask and right-shift a register value to extract a bit field value.
+ * @param field Name of the register bit field.
+ * @param value Value of the register.
+ * @return Masked and shifted bit field value.
+ */
+#define NXP_FLD2VAL(field, value)    (((value) & (field ## _MASK)) >> (field ## _SHIFT))
+
+/*!
+ * @}
+ */ /* end of group Bit_Field_Generic_Macros */
+
+
+/* ----------------------------------------------------------------------------
+   -- SDK Compatibility
+   ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
+ * @{
+ */
+
+#define ENET_RMON_R_DROP_REG(base)               ENET_IEEE_R_DROP_REG(base)
+#define ENET_RMON_R_FRAME_OK_REG(base)           ENET_IEEE_R_FRAME_OK_REG(base)
+#define FMC_PFB0CR_RFU_MASK                      FMC_PFB01CR_RFU_MASK
+#define FMC_PFB0CR_RFU_SHIFT                     FMC_PFB01CR_RFU_SHIFT
+#define FMC_PFB0CR_B0IPE_MASK                    FMC_PFB01CR_B0IPE_MASK
+#define FMC_PFB0CR_B0IPE_SHIFT                   FMC_PFB01CR_B0IPE_SHIFT
+#define FMC_PFB0CR_B0DPE_MASK                    FMC_PFB01CR_B0DPE_MASK
+#define FMC_PFB0CR_B0DPE_SHIFT                   FMC_PFB01CR_B0DPE_SHIFT
+#define FMC_PFB0CR_B0ICE_MASK                    FMC_PFB01CR_B0ICE_MASK
+#define FMC_PFB0CR_B0ICE_SHIFT                   FMC_PFB01CR_B0ICE_SHIFT
+#define FMC_PFB0CR_B0DCE_MASK                    FMC_PFB01CR_B0DCE_MASK
+#define FMC_PFB0CR_B0DCE_SHIFT                   FMC_PFB01CR_B0DCE_SHIFT
+#define FMC_PFB0CR_CRC_MASK                      FMC_PFB01CR_CRC_MASK
+#define FMC_PFB0CR_CRC_SHIFT                     FMC_PFB01CR_CRC_SHIFT
+#define FMC_PFB0CR_CRC(x)                        FMC_PFB01CR_CRC(x)
+#define FMC_PFB0CR_B0MW_MASK                     FMC_PFB01CR_B0MW_MASK
+#define FMC_PFB0CR_B0MW_SHIFT                    FMC_PFB01CR_B0MW_SHIFT
+#define FMC_PFB0CR_B0MW(x)                       FMC_PFB01CR_B0MW(x)
+#define FMC_PFB0CR_S_B_INV_MASK                  FMC_PFB01CR_S_B_INV_MASK
+#define FMC_PFB0CR_S_B_INV_SHIFT                 FMC_PFB01CR_S_B_INV_SHIFT
+#define FMC_PFB0CR_CINV_WAY_MASK                 FMC_PFB01CR_CINV_WAY_MASK
+#define FMC_PFB0CR_CINV_WAY_SHIFT                FMC_PFB01CR_CINV_WAY_SHIFT
+#define FMC_PFB0CR_CINV_WAY(x)                   FMC_PFB01CR_CINV_WAY(x)
+#define FMC_PFB0CR_CLCK_WAY_MASK                 FMC_PFB01CR_CLCK_WAY_MASK
+#define FMC_PFB0CR_CLCK_WAY_SHIFT                FMC_PFB01CR_CLCK_WAY_SHIFT
+#define FMC_PFB0CR_CLCK_WAY(x)                   FMC_PFB01CR_CLCK_WAY(x)
+#define FMC_PFB0CR_B0RWSC_MASK                   FMC_PFB01CR_B0RWSC_MASK
+#define FMC_PFB0CR_B0RWSC_SHIFT                  FMC_PFB01CR_B0RWSC_SHIFT
+#define FMC_PFB0CR_B0RWSC(x)                     FMC_PFB01CR_B0RWSC(x)
+#define FMC_PFB1CR_RFU_MASK                      FMC_PFB23CR_RFU_MASK
+#define FMC_PFB1CR_RFU_SHIFT                     FMC_PFB23CR_RFU_SHIFT
+#define FMC_PFB1CR_B1IPE_MASK                    FMC_PFB23CR_B1IPE_MASK
+#define FMC_PFB1CR_B1IPE_SHIFT                   FMC_PFB23CR_B1IPE_SHIFT
+#define FMC_PFB1CR_B1DPE_MASK                    FMC_PFB23CR_B1DPE_MASK
+#define FMC_PFB1CR_B1DPE_SHIFT                   FMC_PFB23CR_B1DPE_SHIFT
+#define FMC_PFB1CR_B1ICE_MASK                    FMC_PFB23CR_B1ICE_MASK
+#define FMC_PFB1CR_B1ICE_SHIFT                   FMC_PFB23CR_B1ICE_SHIFT
+#define FMC_PFB1CR_B1DCE_MASK                    FMC_PFB23CR_B1DCE_MASK
+#define FMC_PFB1CR_B1DCE_SHIFT                   FMC_PFB23CR_B1DCE_SHIFT
+#define FMC_PFB1CR_B1MW_MASK                     FMC_PFB23CR_B1MW_MASK
+#define FMC_PFB1CR_B1MW_SHIFT                    FMC_PFB23CR_B1MW_SHIFT
+#define FMC_PFB1CR_B1MW(x)                       FMC_PFB23CR_B1MW(x)
+#define FMC_PFB1CR_B1RWSC_MASK                   FMC_PFB23CR_B1RWSC_MASK
+#define FMC_PFB1CR_B1RWSC_SHIFT                  FMC_PFB23CR_B1RWSC_SHIFT
+#define FMC_PFB1CR_B1RWSC(x)                     FMC_PFB23CR_B1RWSC(x)
+#define LLWU_PE8_WUPE130_MASK                    LLWU_PE8_WUPE30_MASK
+#define LLWU_PE8_WUPE130_SHIFT                   LLWU_PE8_WUPE30_SHIFT
+#define LLWU_PE8_WUPE130(x)                      LLWU_PE8_WUPE30(x)
+#define MCG_C2_EREFS0_MASK                       MCG_C2_EREFS_MASK
+#define MCG_C2_EREFS0_SHIFT                      MCG_C2_EREFS_SHIFT
+#define MCG_C2_HGO0_MASK                         MCG_C2_HGO_MASK
+#define MCG_C2_HGO0_SHIFT                        MCG_C2_HGO_SHIFT
+#define MCG_C2_RANGE0_MASK                       MCG_C2_RANGE_MASK
+#define MCG_C2_RANGE0_SHIFT                      MCG_C2_RANGE_SHIFT
+#define MCG_C2_RANGE0(x)                         MCG_C2_RANGE(x)
+#define PMC_REGSC_BGBDS_MASK                     This_symbol_has_been_deprecated
+#define PMC_REGSC_BGBDS_SHIFT                    This_symbol_has_been_deprecated
+#define SDHC_VENDOR_EXTDMAEN_MASK                This_symbol_has_been_deprecated
+#define SDHC_VENDOR_EXTDMAEN_SHIFT               This_symbol_has_been_deprecated
+#define SDRAM_CTRL_COC_MASK                      This_symbol_has_been_deprecated
+#define SDRAM_CTRL_COC_SHIFT                     This_symbol_has_been_deprecated
+#define SDRAM_CTRL_NAM_MASK                      This_symbol_has_been_deprecated
+#define SDRAM_CTRL_NAM_SHIFT                     This_symbol_has_been_deprecated
+#define SMC_STOPCTRL_LPOPO_MASK                  This_symbol_has_been_deprecated
+#define SMC_STOPCTRL_LPOPO_SHIFT                 This_symbol_has_been_deprecated
+#define UART_C6_CP_MASK                          This_symbol_has_been_deprecated
+#define UART_C6_CP_SHIFT                         This_symbol_has_been_deprecated
+#define UART_C6_CE_MASK                          This_symbol_has_been_deprecated
+#define UART_C6_CE_SHIFT                         This_symbol_has_been_deprecated
+#define UART_C6_TX709_MASK                       This_symbol_has_been_deprecated
+#define UART_C6_TX709_SHIFT                      This_symbol_has_been_deprecated
+#define UART_C6_EN709_MASK                       This_symbol_has_been_deprecated
+#define UART_C6_EN709_SHIFT                      This_symbol_has_been_deprecated
+#define UART_PCTH_PCTH_MASK                      This_symbol_has_been_deprecated
+#define UART_PCTH_PCTH_SHIFT                     This_symbol_has_been_deprecated
+#define UART_PCTH_PCTH(x)                        This_symbol_has_been_deprecated
+#define UART_PCTL_PCTL_MASK                      This_symbol_has_been_deprecated
+#define UART_PCTL_PCTL_SHIFT                     This_symbol_has_been_deprecated
+#define UART_PCTL_PCTL(x)                        This_symbol_has_been_deprecated
+#define UART_IE0_CPTXIE_MASK                     This_symbol_has_been_deprecated
+#define UART_IE0_CPTXIE_SHIFT                    This_symbol_has_been_deprecated
+#define UART_IE0_CTXDIE_MASK                     This_symbol_has_been_deprecated
+#define UART_IE0_CTXDIE_SHIFT                    This_symbol_has_been_deprecated
+#define UART_IE0_RPLOFIE_MASK                    This_symbol_has_been_deprecated
+#define UART_IE0_RPLOFIE_SHIFT                   This_symbol_has_been_deprecated
+#define UART_SDTH_SDTH_MASK                      This_symbol_has_been_deprecated
+#define UART_SDTH_SDTH_SHIFT                     This_symbol_has_been_deprecated
+#define UART_SDTH_SDTH(x)                        This_symbol_has_been_deprecated
+#define UART_SDTL_SDTL_MASK                      This_symbol_has_been_deprecated
+#define UART_SDTL_SDTL_SHIFT                     This_symbol_has_been_deprecated
+#define UART_SDTL_SDTL(x)                        This_symbol_has_been_deprecated
+#define UART_PRE_PREAMBLE_MASK                   This_symbol_has_been_deprecated
+#define UART_PRE_PREAMBLE_SHIFT                  This_symbol_has_been_deprecated
+#define UART_PRE_PREAMBLE(x)                     This_symbol_has_been_deprecated
+#define UART_TPL_TPL_MASK                        This_symbol_has_been_deprecated
+#define UART_TPL_TPL_SHIFT                       This_symbol_has_been_deprecated
+#define UART_TPL_TPL(x)                          This_symbol_has_been_deprecated
+#define UART_IE_TXDIE_MASK                       This_symbol_has_been_deprecated
+#define UART_IE_TXDIE_SHIFT                      This_symbol_has_been_deprecated
+#define UART_IE_PSIE_MASK                        This_symbol_has_been_deprecated
+#define UART_IE_PSIE_SHIFT                       This_symbol_has_been_deprecated
+#define UART_IE_PCTEIE_MASK                      This_symbol_has_been_deprecated
+#define UART_IE_PCTEIE_SHIFT                     This_symbol_has_been_deprecated
+#define UART_IE_PTXIE_MASK                       This_symbol_has_been_deprecated
+#define UART_IE_PTXIE_SHIFT                      This_symbol_has_been_deprecated
+#define UART_IE_PRXIE_MASK                       This_symbol_has_been_deprecated
+#define UART_IE_PRXIE_SHIFT                      This_symbol_has_been_deprecated
+#define UART_IE_ISDIE_MASK                       This_symbol_has_been_deprecated
+#define UART_IE_ISDIE_SHIFT                      This_symbol_has_been_deprecated
+#define UART_IE_WBEIE_MASK                       This_symbol_has_been_deprecated
+#define UART_IE_WBEIE_SHIFT                      This_symbol_has_been_deprecated
+#define UART_IE_PEIE_MASK                        This_symbol_has_been_deprecated
+#define UART_IE_PEIE_SHIFT                       This_symbol_has_been_deprecated
+#define UART_WB_WBASE_MASK                       This_symbol_has_been_deprecated
+#define UART_WB_WBASE_SHIFT                      This_symbol_has_been_deprecated
+#define UART_WB_WBASE(x)                         This_symbol_has_been_deprecated
+#define UART_S3_TXFF_MASK                        This_symbol_has_been_deprecated
+#define UART_S3_TXFF_SHIFT                       This_symbol_has_been_deprecated
+#define UART_S3_PSF_MASK                         This_symbol_has_been_deprecated
+#define UART_S3_PSF_SHIFT                        This_symbol_has_been_deprecated
+#define UART_S3_PCTEF_MASK                       This_symbol_has_been_deprecated
+#define UART_S3_PCTEF_SHIFT                      This_symbol_has_been_deprecated
+#define UART_S3_PTXF_MASK                        This_symbol_has_been_deprecated
+#define UART_S3_PTXF_SHIFT                       This_symbol_has_been_deprecated
+#define UART_S3_PRXF_MASK                        This_symbol_has_been_deprecated
+#define UART_S3_PRXF_SHIFT                       This_symbol_has_been_deprecated
+#define UART_S3_ISD_MASK                         This_symbol_has_been_deprecated
+#define UART_S3_ISD_SHIFT                        This_symbol_has_been_deprecated
+#define UART_S3_WBEF_MASK                        This_symbol_has_been_deprecated
+#define UART_S3_WBEF_SHIFT                       This_symbol_has_been_deprecated
+#define UART_S3_PEF_MASK                         This_symbol_has_been_deprecated
+#define UART_S3_PEF_SHIFT                        This_symbol_has_been_deprecated
+#define UART_S4_FE_MASK                          This_symbol_has_been_deprecated
+#define UART_S4_FE_SHIFT                         This_symbol_has_been_deprecated
+#define UART_S4_TXDF_MASK                        This_symbol_has_been_deprecated
+#define UART_S4_TXDF_SHIFT                       This_symbol_has_been_deprecated
+#define UART_S4_CDET_MASK                        This_symbol_has_been_deprecated
+#define UART_S4_CDET_SHIFT                       This_symbol_has_been_deprecated
+#define UART_S4_CDET(x)                          This_symbol_has_been_deprecated
+#define UART_S4_RPLOF_MASK                       This_symbol_has_been_deprecated
+#define UART_S4_RPLOF_SHIFT                      This_symbol_has_been_deprecated
+#define UART_S4_LNF_MASK                         This_symbol_has_been_deprecated
+#define UART_S4_LNF_SHIFT                        This_symbol_has_been_deprecated
+#define UART_RPL_RPL_MASK                        This_symbol_has_been_deprecated
+#define UART_RPL_RPL_SHIFT                       This_symbol_has_been_deprecated
+#define UART_RPL_RPL(x)                          This_symbol_has_been_deprecated
+#define UART_RPREL_RPREL_MASK                    This_symbol_has_been_deprecated
+#define UART_RPREL_RPREL_SHIFT                   This_symbol_has_been_deprecated
+#define UART_RPREL_RPREL(x)                      This_symbol_has_been_deprecated
+#define UART_CPW_CPW_MASK                        This_symbol_has_been_deprecated
+#define UART_CPW_CPW_SHIFT                       This_symbol_has_been_deprecated
+#define UART_CPW_CPW(x)                          This_symbol_has_been_deprecated
+#define UART_RIDTH_RIDTH_MASK                    This_symbol_has_been_deprecated
+#define UART_RIDTH_RIDTH_SHIFT                   This_symbol_has_been_deprecated
+#define UART_RIDTH_RIDTH(x)                      This_symbol_has_been_deprecated
+#define UART_RIDTL_RIDTL_MASK                    This_symbol_has_been_deprecated
+#define UART_RIDTL_RIDTL_SHIFT                   This_symbol_has_been_deprecated
+#define UART_RIDTL_RIDTL(x)                      This_symbol_has_been_deprecated
+#define UART_TIDTH_TIDTH_MASK                    This_symbol_has_been_deprecated
+#define UART_TIDTH_TIDTH_SHIFT                   This_symbol_has_been_deprecated
+#define UART_TIDTH_TIDTH(x)                      This_symbol_has_been_deprecated
+#define UART_TIDTL_TIDTL_MASK                    This_symbol_has_been_deprecated
+#define UART_TIDTL_TIDTL_SHIFT                   This_symbol_has_been_deprecated
+#define UART_TIDTL_TIDTL(x)                      This_symbol_has_been_deprecated
+#define UART_RB1TH_RB1TH_MASK                    This_symbol_has_been_deprecated
+#define UART_RB1TH_RB1TH_SHIFT                   This_symbol_has_been_deprecated
+#define UART_RB1TH_RB1TH(x)                      This_symbol_has_been_deprecated
+#define UART_RB1TL_RB1TL_MASK                    This_symbol_has_been_deprecated
+#define UART_RB1TL_RB1TL_SHIFT                   This_symbol_has_been_deprecated
+#define UART_RB1TL_RB1TL(x)                      This_symbol_has_been_deprecated
+#define UART_TB1TH_TB1TH_MASK                    This_symbol_has_been_deprecated
+#define UART_TB1TH_TB1TH_SHIFT                   This_symbol_has_been_deprecated
+#define UART_TB1TH_TB1TH(x)                      This_symbol_has_been_deprecated
+#define UART_TB1TL_TB1TL_MASK                    This_symbol_has_been_deprecated
+#define UART_TB1TL_TB1TL_SHIFT                   This_symbol_has_been_deprecated
+#define UART_TB1TL_TB1TL(x)                      This_symbol_has_been_deprecated
+#define UART_PROG_REG_MIN_DMC1_MASK              This_symbol_has_been_deprecated
+#define UART_PROG_REG_MIN_DMC1_SHIFT             This_symbol_has_been_deprecated
+#define UART_PROG_REG_MIN_DMC1(x)                This_symbol_has_been_deprecated
+#define UART_PROG_REG_LCV_LEN_MASK               This_symbol_has_been_deprecated
+#define UART_PROG_REG_LCV_LEN_SHIFT              This_symbol_has_been_deprecated
+#define UART_PROG_REG_LCV_LEN(x)                 This_symbol_has_been_deprecated
+#define UART_STATE_REG_SM_STATE_MASK             This_symbol_has_been_deprecated
+#define UART_STATE_REG_SM_STATE_SHIFT            This_symbol_has_been_deprecated
+#define UART_STATE_REG_SM_STATE(x)               This_symbol_has_been_deprecated
+#define UART_STATE_REG_TX_STATE_MASK             This_symbol_has_been_deprecated
+#define UART_STATE_REG_TX_STATE_SHIFT            This_symbol_has_been_deprecated
+#define UART_STATE_REG_TX_STATE(x)               This_symbol_has_been_deprecated
+#define USBx_ADDINFO_IRQNUM_MASK                  This_symbol_has_been_deprecated
+#define USBx_ADDINFO_IRQNUM_SHIFT                 This_symbol_has_been_deprecated
+#define USBx_ADDINFO_IRQNUM(x)                    This_symbol_has_been_deprecated
+#define USBHS_USBSTS_ULPII_MASK                  This_symbol_has_been_deprecated
+#define USBHS_USBSTS_ULPII_SHIFT                 This_symbol_has_been_deprecated
+#define USBHS_USBINTR_ULPIE_MASK                 This_symbol_has_been_deprecated
+#define USBHS_USBINTR_ULPIE_SHIFT                This_symbol_has_been_deprecated
+#define USBPHY_CTRL_CLK_SWITCH_ENJ_MASK          This_symbol_has_been_deprecated
+#define USBPHY_CTRL_CLK_SWITCH_ENJ_SHIFT         This_symbol_has_been_deprecated
+#define USBPHY_CTRL_SET_CLK_SWITCH_ENJ_MASK      This_symbol_has_been_deprecated
+#define USBPHY_CTRL_SET_CLK_SWITCH_ENJ_SHIFT     This_symbol_has_been_deprecated
+#define USBPHY_CTRL_CLR_CLK_SWITCH_ENJ_MASK      This_symbol_has_been_deprecated
+#define USBPHY_CTRL_CLR_CLK_SWITCH_ENJ_SHIFT     This_symbol_has_been_deprecated
+#define USBPHY_CTRL_TOG_CLK_SWITCH_ENJ_MASK      This_symbol_has_been_deprecated
+#define USBPHY_CTRL_TOG_CLK_SWITCH_ENJ_SHIFT     This_symbol_has_been_deprecated
+#define MCM_ISR_REG(base)                        MCM_ISCR_REG(base)
+#define MCM_ISR_IRQ_MASK                         MCM_ISCR_IRQ_MASK
+#define MCM_ISR_IRQ_SHIFT                        MCM_ISCR_IRQ_SHIFT
+#define MCM_ISR_NMI_MASK                         MCM_ISCR_NMI_MASK
+#define MCM_ISR_NMI_SHIFT                        MCM_ISCR_NMI_SHIFT
+#define MCM_ISR_DHREQ_MASK                       MCM_ISCR_DHREQ_MASK
+#define MCM_ISR_DHREQ_SHIFT                      MCM_ISCR_DHREQ_SHIFT
+#define MCM_ISR_FIOC_MASK                        MCM_ISCR_FIOC_MASK
+#define MCM_ISR_FIOC_SHIFT                       MCM_ISCR_FIOC_SHIFT
+#define MCM_ISR_FDZC_MASK                        MCM_ISCR_FDZC_MASK
+#define MCM_ISR_FDZC_SHIFT                       MCM_ISCR_FDZC_SHIFT
+#define MCM_ISR_FOFC_MASK                        MCM_ISCR_FOFC_MASK
+#define MCM_ISR_FOFC_SHIFT                       MCM_ISCR_FOFC_SHIFT
+#define MCM_ISR_FUFC_MASK                        MCM_ISCR_FUFC_MASK
+#define MCM_ISR_FUFC_SHIFT                       MCM_ISCR_FUFC_SHIFT
+#define MCM_ISR_FIXC_MASK                        MCM_ISCR_FIXC_MASK
+#define MCM_ISR_FIXC_SHIFT                       MCM_ISCR_FIXC_SHIFT
+#define MCM_ISR_FIDC_MASK                        MCM_ISCR_FIDC_MASK
+#define MCM_ISR_FIDC_SHIFT                       MCM_ISCR_FIDC_SHIFT
+#define MCM_ISR_FIOCE_MASK                       MCM_ISCR_FIOCE_MASK
+#define MCM_ISR_FIOCE_SHIFT                      MCM_ISCR_FIOCE_SHIFT
+#define MCM_ISR_FDZCE_MASK                       MCM_ISCR_FDZCE_MASK
+#define MCM_ISR_FDZCE_SHIFT                      MCM_ISCR_FDZCE_SHIFT
+#define MCM_ISR_FOFCE_MASK                       MCM_ISCR_FOFCE_MASK
+#define MCM_ISR_FOFCE_SHIFT                      MCM_ISCR_FOFCE_SHIFT
+#define MCM_ISR_FUFCE_MASK                       MCM_ISCR_FUFCE_MASK
+#define MCM_ISR_FUFCE_SHIFT                      MCM_ISCR_FUFCE_SHIFT
+#define MCM_ISR_FIXCE_MASK                       MCM_ISCR_FIXCE_MASK
+#define MCM_ISR_FIXCE_SHIFT                      MCM_ISCR_FIXCE_SHIFT
+#define MCM_ISR_FIDCE_MASK                       MCM_ISCR_FIDCE_MASK
+#define MCM_ISR_FIDCE_SHIFT                      MCM_ISCR_FIDCE_SHIFT
+#define DMAMUX0                                  DMAMUX
+#define DSPI0                                    SPI0
+#define DSPI1                                    SPI1
+#define DSPI2                                    SPI2
+#define FLEXCAN0                                 CAN0
+#define FLEXCAN1                                 CAN1
+#define PTA_BASE                                 GPIOA_BASE
+#define PTA                                      GPIOA
+#define PTB_BASE                                 GPIOB_BASE
+#define PTB                                      GPIOB
+#define PTC_BASE                                 GPIOC_BASE
+#define PTC                                      GPIOC
+#define PTD_BASE                                 GPIOD_BASE
+#define PTD                                      GPIOD
+#define PTE_BASE                                 GPIOE_BASE
+#define PTE                                      GPIOE
+#define Watchdog_IRQn                            WDOG_EWM_IRQn
+#define Watchdog_IRQHandler                      WDOG_EWM_IRQHandler
+#define LPTimer_IRQn                             LPTMR0_IRQn
+#define LPTimer_IRQHandler                       LPTMR0_IRQHandler
+#define UART0_LON_IRQn                           This_symbol_has_been_deprecated
+#define UART0_LON_IRQHandler                     This_symbol_has_been_deprecated
+#define LLW_IRQn                                 LLWU_IRQn
+#define LLW_IRQHandler                           LLWU_IRQHandler
+
+/*!
+ * @}
+ */ /* end of group SDK_Compatibility_Symbols */
+
+
+#endif  /* _MK66F18_H_ */
+
diff --git a/os/common/ext/CMSIS/KINETIS/system_MK66F18.h b/os/common/ext/CMSIS/KINETIS/system_MK66F18.h
new file mode 100644
index 0000000..57ae6a1
--- /dev/null
+++ b/os/common/ext/CMSIS/KINETIS/system_MK66F18.h
@@ -0,0 +1,173 @@
+/*
+** ###################################################################
+**     Processors:          MK66FN2M0VLQ18
+**                          MK66FN2M0VMD18
+**                          MK66FX1M0VLQ18
+**                          MK66FX1M0VMD18
+**
+**     Compilers:           Keil ARM C/C++ Compiler
+**                          Freescale C/C++ for Embedded ARM
+**                          GNU C Compiler
+**                          IAR ANSI C/C++ Compiler for ARM
+**                          MCUXpresso Compiler
+**
+**     Reference manual:    K66P144M180SF5RMV2, Rev. 1, Mar 2015
+**     Version:             rev. 3.0, 2015-03-25
+**     Build:               b171226
+**
+**     Abstract:
+**         Provides a system configuration function and a global variable that
+**         contains the system frequency. It configures the device and initializes
+**         the oscillator (PLL) that is part of the microcontroller device.
+**
+**     The Clear BSD License
+**     Copyright 2016 Freescale Semiconductor, Inc.
+**     Copyright 2016-2017 NXP
+**     All rights reserved.
+**
+**     Redistribution and use in source and binary forms, with or without
+**     modification, are permitted (subject to the limitations in the
+**     disclaimer below) provided that the following conditions are met:
+**
+**     * Redistributions of source code must retain the above copyright
+**       notice, this list of conditions and the following disclaimer.
+**
+**     * Redistributions in binary form must reproduce the above copyright
+**       notice, this list of conditions and the following disclaimer in the
+**       documentation and/or other materials provided with the distribution.
+**
+**     * Neither the name of the copyright holder nor the names of its
+**       contributors may be used to endorse or promote products derived from
+**       this software without specific prior written permission.
+**
+**     NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE
+**     GRANTED BY THIS LICENSE. THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT
+**     HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED
+**     WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+**     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+**     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+**     LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+**     CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+**     SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR
+**     BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
+**     WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE
+**     OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN
+**     IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+**     http:                 www.nxp.com
+**     mail:                 support@nxp.com
+**
+**     Revisions:
+**     - rev. 1.0 (2013-09-02)
+**         Initial version.
+**     - rev. 2.0 (2014-02-17)
+**         Register accessor macros added to the memory map.
+**         Symbols for Processor Expert memory map compatibility added to the memory map.
+**         Startup file for gcc has been updated according to CMSIS 3.2.
+**         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
+**         Update according to reference manual rev. 2
+**     - rev. 2.1 (2014-04-16)
+**         Update of SystemInit() and SystemCoreClockUpdate() functions.
+**     - rev. 2.2 (2014-10-14)
+**         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
+**     - rev. 2.3 (2014-11-20)
+**         Update according to reverence manual K65P169M180SF5RMV2_NDA, Rev. 0 Draft A, October 2014.
+**         Update of SystemInit() to use 16MHz external crystal.
+**     - rev. 2.4 (2015-02-19)
+**         Renamed interrupt vector LLW to LLWU.
+**     - rev. 3.0 (2015-03-25)
+**         Registers updated according to the reference manual revision 1, March 2015
+**
+** ###################################################################
+*/
+
+/*!
+ * @file MK66F18
+ * @version 3.0
+ * @date 2015-03-25
+ * @brief Device specific configuration file for MK66F18 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef _SYSTEM_MK66F18_H_
+#define _SYSTEM_MK66F18_H_                       /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+
+#ifndef DISABLE_WDOG
+  #define DISABLE_WDOG                 1
+#endif
+
+/* Define clock source values */
+
+#define CPU_XTAL_CLK_HZ                16000000U           /* Value of the external crystal or oscillator clock frequency of the system oscillator (OSC) in Hz */
+#define CPU_XTAL32k_CLK_HZ             32768U              /* Value of the external 32k crystal or oscillator clock frequency of the RTC in Hz */
+#define CPU_INT_SLOW_CLK_HZ            32768U              /* Value of the slow internal oscillator clock frequency in Hz */
+#define CPU_INT_FAST_CLK_HZ            4000000U            /* Value of the fast internal oscillator clock frequency in Hz */
+#define CPU_INT_IRC_CLK_HZ             48000000U           /* Value of the 48M internal oscillator clock frequency in Hz */
+
+/* RTC oscillator setting */
+/* RTC_CR: SC2P=0,SC4P=0,SC8P=0,SC16P=0,CLKO=1,OSCE=1,WPS=0,UM=0,SUP=0,WPE=0,SWR=0 */
+#define SYSTEM_RTC_CR_VALUE            0x0300U             /* RTC_CR */
+
+/* Low power mode enable */
+/* SMC_PMPROT: AHSRUN=1,AVLP=1,ALLS=1,AVLLS=1 */
+#define SYSTEM_SMC_PMPROT_VALUE        0xAAU               /* SMC_PMPROT */
+
+#define DEFAULT_SYSTEM_CLOCK           20971520u
+
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+/**
+ * @brief SystemInit function hook.
+ *
+ * This weak function allows to call specific initialization code during the
+ * SystemInit() execution.This can be used when an application specific code needs
+ * to be called as close to the reset entry as possible (for example the Multicore
+ * Manager MCMGR_EarlyInit() function call).
+ * NOTE: No global r/w variables can be used in this hook function because the
+ * initialization of these variables happens after this function.
+ */
+void SystemInitHook (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif  /* _SYSTEM_MK66F18_H_ */
diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/MK66FX1M0.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/MK66FX1M0.ld
new file mode 100644
index 0000000..c0e2cf2
--- /dev/null
+++ b/os/common/startup/ARMCMx/compilers/GCC/ld/MK66FX1M0.ld
@@ -0,0 +1,101 @@
+/*
+ * Copyright (C) 2013-2016 Fabio Utzig, http://fabioutzig.com
+ *           (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining
+ * a copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
+ * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+ * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+ * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+ * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ */
+
+/*
+ * MK66FX1M0 memory setup.
+ */
+MEMORY
+{
+  flash0   : org = 0x00000000, len = 0x400
+  flash1   : org = 0x00000400, len = 0x10
+  flash2   : org = 0x00000410, len = 1024k - 0x410
+  flash3   : org = 0x00000000, len = 0
+  flash4   : org = 0x00000000, len = 0
+  flash5   : org = 0x00000000, len = 0
+  flash6   : org = 0x00000000, len = 0
+  flash7   : org = 0x00000000, len = 0
+  ram0     : org = 0x1FFF0000, len = 256k
+  ram1     : org = 0x00000000, len = 0
+  ram2     : org = 0x00000000, len = 0
+  ram3     : org = 0x00000000, len = 0
+  ram4     : org = 0x00000000, len = 0
+  ram5     : org = 0x00000000, len = 0
+  ram6     : org = 0x00000000, len = 0
+  ram7     : org = 0x00000000, len = 0
+}
+
+/* Flash region for the configuration bytes.*/
+SECTIONS
+{
+  .cfmprotect : ALIGN(4) SUBALIGN(4)
+  {
+    KEEP(*(.cfmconfig))
+  } > flash1
+}
+
+/* For each data/text section two region are defined, a virtual region
+   and a load region (_LMA suffix).*/
+
+/* Flash region to be used for exception vectors.*/
+REGION_ALIAS("VECTORS_FLASH", flash0);
+REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
+
+/* Flash region to be used for constructors and destructors.*/
+REGION_ALIAS("XTORS_FLASH", flash2);
+REGION_ALIAS("XTORS_FLASH_LMA", flash2);
+
+/* Flash region to be used for code text.*/
+REGION_ALIAS("TEXT_FLASH", flash2);
+REGION_ALIAS("TEXT_FLASH_LMA", flash2);
+
+/* Flash region to be used for read only data.*/
+REGION_ALIAS("RODATA_FLASH", flash2);
+REGION_ALIAS("RODATA_FLASH_LMA", flash2);
+
+/* Flash region to be used for various.*/
+REGION_ALIAS("VARIOUS_FLASH", flash2);
+REGION_ALIAS("VARIOUS_FLASH_LMA", flash2);
+
+/* Flash region to be used for RAM(n) initialization data.*/
+REGION_ALIAS("RAM_INIT_FLASH_LMA", flash2);
+
+/* RAM region to be used for Main stack. This stack accommodates the processing
+   of all exceptions and interrupts.*/
+REGION_ALIAS("MAIN_STACK_RAM", ram0);
+
+/* RAM region to be used for the process stack. This is the stack used by
+   the main() function.*/
+REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+
+/* RAM region to be used for data segment.*/
+REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM_LMA", flash2);
+
+/* RAM region to be used for BSS segment.*/
+REGION_ALIAS("BSS_RAM", ram0);
+
+/* RAM region to be used for the default heap.*/
+REGION_ALIAS("HEAP_RAM", ram0);
+
+/* Generic rules inclusion.*/
+INCLUDE rules.ld
diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_MK66F18.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_MK66F18.mk
new file mode 100644
index 0000000..0cdd891
--- /dev/null
+++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_MK66F18.mk
@@ -0,0 +1,12 @@
+# List of the ChibiOS generic MK66F18 startup and CMSIS files.
+STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
+             $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.c
+
+STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S
+
+STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
+             $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/MK66F18 \
+             $(CHIBIOS)/os/common/ext/CMSIS/include \
+             $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/KINETIS
+
+STARTUPLD  = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
diff --git a/os/common/startup/ARMCMx/devices/MK66F18/cmparams.h b/os/common/startup/ARMCMx/devices/MK66F18/cmparams.h
new file mode 100644
index 0000000..e47bd09
--- /dev/null
+++ b/os/common/startup/ARMCMx/devices/MK66F18/cmparams.h
@@ -0,0 +1,80 @@
+/*
+    ChibiOS/RT - Copyright (C) 2006-2014 Giovanni Di Sirio.
+                           (C) 2015 RedoX https://github.com/RedoXyde
+                           (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+    This file is part of ChibiOS/RT.
+
+    ChibiOS/RT is free software; you can redistribute it and/or modify
+    it under the terms of the GNU General Public License as published by
+    the Free Software Foundation; either version 3 of the License, or
+    (at your option) any later version.
+
+    ChibiOS/RT is distributed in the hope that it will be useful,
+    but WITHOUT ANY WARRANTY; without even the implied warranty of
+    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+    GNU General Public License for more details.
+
+    You should have received a copy of the GNU General Public License
+    along with this program.  If not, see <http://www.gnu.org/licenses/>.
+*/
+
+/**
+ * @file    GCC/ARMCMx/MK66F18/cmparams.h
+ * @brief   ARM Cortex-M4 parameters for the Kinetis MK66F18.
+ *
+ * @defgroup ARMCMx_MK66F18 Kinetis MK66F18 Specific Parameters
+ * @ingroup ARMCMx_SPECIFIC
+ * @details This file contains the Cortex-M4 specific parameters for the
+ *          Kinetis MK66F18 platform.
+ * @{
+ */
+
+#ifndef _CMPARAMS_H_
+#define _CMPARAMS_H_
+
+/**
+ * @brief   Cortex core model.
+ */
+#define CORTEX_MODEL            4
+
+/**
+ * @brief   Systick unit presence.
+ */
+#define CORTEX_HAS_ST           TRUE
+
+/**
+ * @brief   Floating Point unit presence.
+ */
+#define CORTEX_HAS_FPU          TRUE
+
+/**
+ * @brief   Number of bits in priority masks.
+ */
+#define CORTEX_PRIORITY_BITS    4
+
+/**
+ * @brief   Number of interrupt vectors.
+ * @note    This number does not include the 16 system vectors and must be
+ *          rounded to a multiple of 8.
+ */
+#define CORTEX_NUM_VECTORS      104
+
+/* The following code is not processed when the file is included from an
+   asm module.*/
+#if !defined(_FROM_ASM_)
+
+/* Including the device CMSIS header. Note, we are not using the definitions
+   from this header because we need this file to be usable also from
+   assembler source files. We verify that the info matches instead.*/
+#include "MK66F18.h"
+
+#if CORTEX_PRIORITY_BITS != __NVIC_PRIO_BITS
+#error "CMSIS __NVIC_PRIO_BITS mismatch"
+#endif
+
+#endif /* !defined(_FROM_ASM_) */
+
+#endif /* _CMPARAMS_H_ */
+
+/** @} */
diff --git a/os/hal/boards/PJRC_TEENSY_3_6/board.c b/os/hal/boards/PJRC_TEENSY_3_6/board.c
new file mode 100644
index 0000000..3e2f022
--- /dev/null
+++ b/os/hal/boards/PJRC_TEENSY_3_6/board.c
@@ -0,0 +1,209 @@
+/*
+    ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+    .ports = {
+        {
+            /*
+             * PORTA setup.
+             *
+             * PTA0 - SWD
+             * PTA3 - SWD
+             * PTA5 - PIN25
+             * PTA12 - PIN3
+             * PTA13 - PIN4
+             * PTA14 - PIN26
+             * PTA15 - PIN27
+             * PTA16 - PIN28
+             * PTA17 - PIN39
+             * PTA18 - Crystal
+             * PTA19 - Crystal
+             * PTA26 - PIN42
+             * PTA28 - PIN40
+             * PTA29 - PIN41
+             *
+             */
+            .port = IOPORT1,
+            .pads = {
+                PAL_MODE_ALTERNATIVE_7,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_ALTERNATIVE_7,       PAL_MODE_UNCONNECTED,       PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_INPUT_ANALOG,      PAL_MODE_INPUT_ANALOG,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+        {
+            /*
+             * PORTB setup.
+             *
+             * PTB0 - PIN16
+             * PTB1 - PIN17
+             * PTB2 - PIN19
+             * PTB3 - PIN18
+             * PTB4 - PIN49
+             * PTB5 - PIN50
+             * PTB10 - PIN31
+             * PTB11 - PIN32
+             * PTB16 - PIN0 - UART0_RX 
+             * PTB17 - PIN1 - UART0_TX
+             * PTB18 - PIN29
+             * PTB19 - PIN30
+             * PTB20 - PIN43
+             * PTB21 - PIN46
+             * PTB22 - PIN44
+             * PTB23 - PIN45
+             */
+            .port = IOPORT2,
+            .pads = {
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_ALTERNATIVE_3,     PAL_MODE_ALTERNATIVE_3,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+        {
+            /*
+             * PORTC setup.
+             * PTC0 - PIN15
+             * PTC1 - PIN22
+             * PTC2 - PIN23
+             * PTC3 - PIN9
+             * PTC4 - PIN10
+             * PTC5 - PIN13
+             * PTC6 - PIN11
+             * PTC7 - PIN12
+             * PTC8 - PIN35
+             * PTC9 - PIN36
+             * PTC10 - PIN37
+             * PTC11 - PIN38
+             *
+             */
+            .port = IOPORT3,
+            .pads = {
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+        {
+            /*
+             * PORTD setup.
+             *
+             * PTD0 - PIN2
+             * PTD1 - PIN14
+             * PTD2 - PIN7
+             * PTD3 - PIN8
+             * PTD4 - PIN6
+             * PTD5 - PIN20
+             * PTD6 - PIN21
+             * PTD7 - PIN5
+             * PTD8 - PIN47
+             * PTD9 - PIN48
+             * PTD11 - PIN55
+             * PTD12 - PIN53
+             * PTD13 - PIN52
+             * PTD14 - PIN51
+             * PTD15 - PIN54
+             */
+            .port = IOPORT4,
+            .pads = {
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_UNCONNECTED,       PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+        {
+            /*
+             * PORTE setup.
+             *
+             * PTE10 - PIN56
+             * PTE11 - PIN57
+             * PTE24 - PIN33
+             * PTE25 - PIN34
+             * PTE26 - PIN24
+             */
+            .port = IOPORT5,
+            .pads = {
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+    },
+};
+#endif
+
+/**
+ * @brief   Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ *          and before any other initialization.
+ */
+void __early_init(void) {
+
+  MK66F18_clock_init();
+}
+
+/**
+ * @brief   Board-specific initialization code.
+ * @todo    Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/PJRC_TEENSY_3_6/board.h b/os/hal/boards/PJRC_TEENSY_3_6/board.h
new file mode 100644
index 0000000..9b0a8ad
--- /dev/null
+++ b/os/hal/boards/PJRC_TEENSY_3_6/board.h
@@ -0,0 +1,345 @@
+/*
+    ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the PJRC Teensy 3.6 board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_PJRC_TEENSY_3_6
+#define BOARD_NAME                  "PJRC Teensy 3.6"
+
+/* External 16 MHz crystal */
+#define KINETIS_XTAL_FREQUENCY      16000000UL
+
+/* Use internal capacitors for the crystal */
+#define KINETIS_BOARD_OSCILLATOR_SETTING OSC_CR_SC8P|OSC_CR_SC2P
+
+/*
+ * MCU type
+ */
+#define MK66F18
+
+/*
+ * IO pins assignments.
+ */
+#define PORTA_PIN0                  0
+#define PORTA_PIN1                  1
+#define PORTA_PIN2                  2
+#define PORTA_PIN3                  3
+#define PORTA_PIN4                  4
+#define TEENSY_PIN25                5
+#define PORTA_PIN6                  6
+#define PORTA_PIN7                  7
+#define PORTA_PIN8                  8
+#define PORTA_PIN9                  9
+#define PORTA_PIN10                 10
+#define PORTA_PIN11                 11
+#define TEENSY_PIN3                 12
+#define TEENSY_PIN4                 13
+#define TEENSY_PIN26                14
+#define TEENSY_PIN27                15
+#define TEENSY_PIN28                16
+#define TEENSY_PIN39                17
+#define PORTA_PIN18                 18
+#define PORTA_PIN19                 19
+#define PORTA_PIN20                 20
+#define PORTA_PIN21                 21
+#define PORTA_PIN22                 22
+#define PORTA_PIN23                 23
+#define PORTA_PIN24                 24
+#define PORTA_PIN25                 25
+#define TEENSY_PIN42                26
+#define PORTA_PIN27                 27
+#define TEENSY_PIN40                28
+#define TEENSY_PIN41                29
+#define PORTA_PIN30                 30
+#define PORTA_PIN31                 31
+
+#define TEENSY_PIN40_IOPORT  IOPORT1
+#define TEENSY_PIN41_IOPORT  IOPORT1
+#define TEENSY_PIN42_IOPORT  IOPORT1
+#define TEENSY_PIN3_IOPORT   IOPORT1
+#define TEENSY_PIN4_IOPORT   IOPORT1
+#define TEENSY_PIN25_IOPORT  IOPORT1
+#define TEENSY_PIN26_IOPORT  IOPORT1
+#define TEENSY_PIN27_IOPORT  IOPORT1
+#define TEENSY_PIN28_IOPORT  IOPORT1
+#define TEENSY_PIN39_IOPORT  IOPORT1
+
+#define TEENSY_PIN16                0
+#define TEENSY_PIN17                1
+#define TEENSY_PIN19                2
+#define TEENSY_PIN18                3
+#define TEENSY_PIN49                4
+#define TEENSY_PIN50                5
+#define PORTB_PIN6                  6
+#define PORTB_PIN7                  7
+#define PORTB_PIN8                  8
+#define PORTB_PIN9                  9
+#define TEENSY_PIN31                10
+#define TEENSY_PIN32                11
+#define PORTB_PIN12                 12
+#define PORTB_PIN13                 13
+#define PORTB_PIN14                 14
+#define PORTB_PIN15                 15
+#define TEENSY_PIN0                 16
+#define TEENSY_PIN1                 17
+#define TEENSY_PIN29                18
+#define TEENSY_PIN30                19
+#define TEENSY_PIN43                20
+#define TEENSY_PIN46                21
+#define TEENSY_PIN44                22
+#define TEENSY_PIN45                23
+#define PORTB_PIN24                 24
+#define PORTB_PIN25                 25
+#define PORTB_PIN26                 26
+#define PORTB_PIN27                 27
+#define PORTB_PIN28                 28
+#define PORTB_PIN29                 29
+#define PORTB_PIN30                 30
+#define PORTB_PIN31                 31
+
+#define TEENSY_PIN49_IOPORT  IOPORT2
+#define TEENSY_PIN50_IOPORT  IOPORT2
+#define TEENSY_PIN43_IOPORT  IOPORT2
+#define TEENSY_PIN44_IOPORT  IOPORT2
+#define TEENSY_PIN45_IOPORT  IOPORT2
+#define TEENSY_PIN46_IOPORT  IOPORT2
+#define TEENSY_PIN0_IOPORT   IOPORT2
+#define TEENSY_PIN1_IOPORT   IOPORT2
+#define TEENSY_PIN29_IOPORT  IOPORT2
+#define TEENSY_PIN30_IOPORT  IOPORT2
+#define TEENSY_PIN31_IOPORT  IOPORT2
+#define TEENSY_PIN32_IOPORT  IOPORT2
+#define TEENSY_PIN16_IOPORT  IOPORT2
+#define TEENSY_PIN17_IOPORT  IOPORT2
+#define TEENSY_PIN19_IOPORT  IOPORT2
+#define TEENSY_PIN18_IOPORT  IOPORT2
+
+#define TEENSY_PIN15                0
+#define TEENSY_PIN22                1
+#define TEENSY_PIN23                2
+#define TEENSY_PIN9                 3
+#define TEENSY_PIN10                4
+#define TEENSY_PIN13                5
+#define TEENSY_PIN11                6
+#define TEENSY_PIN12                7
+#define TEENSY_PIN35                8
+#define TEENSY_PIN36                9
+#define TEENSY_PIN37                10
+#define TEENSY_PIN38                11
+#define PORTC_PIN12                 12
+#define PORTC_PIN13                 13
+#define PORTC_PIN14                 14
+#define PORTC_PIN15                 15
+#define PORTC_PIN16                 16
+#define PORTC_PIN17                 17
+#define PORTC_PIN18                 18
+#define PORTC_PIN19                 19
+#define PORTC_PIN20                 20
+#define PORTC_PIN21                 21
+#define PORTC_PIN22                 22
+#define PORTC_PIN23                 23
+#define PORTC_PIN24                 24
+#define PORTC_PIN25                 25
+#define PORTC_PIN26                 26
+#define PORTC_PIN27                 27
+#define PORTC_PIN28                 28
+#define PORTC_PIN29                 29
+#define PORTC_PIN30                 30
+#define PORTC_PIN31                 31
+
+#define TEENSY_PIN9_IOPORT   IOPORT3
+#define TEENSY_PIN10_IOPORT  IOPORT3
+#define TEENSY_PIN11_IOPORT  IOPORT3
+#define TEENSY_PIN12_IOPORT  IOPORT3
+#define TEENSY_PIN35_IOPORT  IOPORT3
+#define TEENSY_PIN36_IOPORT  IOPORT3
+#define TEENSY_PIN37_IOPORT  IOPORT3
+#define TEENSY_PIN38_IOPORT  IOPORT3
+#define TEENSY_PIN13_IOPORT  IOPORT3
+#define TEENSY_PIN15_IOPORT  IOPORT3
+#define TEENSY_PIN22_IOPORT  IOPORT3
+#define TEENSY_PIN23_IOPORT  IOPORT3
+
+#define TEENSY_PIN2                 0
+#define TEENSY_PIN14                1
+#define TEENSY_PIN7                 2
+#define TEENSY_PIN8                 3
+#define TEENSY_PIN6                 4
+#define TEENSY_PIN20                5
+#define TEENSY_PIN21                6
+#define TEENSY_PIN5                 7
+#define TEENSY_PIN47                8
+#define TEENSY_PIN48                9
+#define PORTD_PIN10                 10
+#define TEENSY_PIN55                11
+#define TEENSY_PIN53                12
+#define TEENSY_PIN52                13
+#define TEENSY_PIN51                14
+#define TEENSY_PIN54                15
+#define PORTD_PIN16                 16
+#define PORTD_PIN17                 17
+#define PORTD_PIN18                 18
+#define PORTD_PIN19                 19
+#define PORTD_PIN20                 20
+#define PORTD_PIN21                 21
+#define PORTD_PIN22                 22
+#define PORTD_PIN23                 23
+#define PORTD_PIN24                 24
+#define PORTD_PIN25                 25
+#define PORTD_PIN26                 26
+#define PORTD_PIN27                 27
+#define PORTD_PIN28                 28
+#define PORTD_PIN29                 29
+#define PORTD_PIN30                 30
+#define PORTD_PIN31                 31
+
+#define TEENSY_PIN51_IOPORT  IOPORT4
+#define TEENSY_PIN52_IOPORT  IOPORT4
+#define TEENSY_PIN53_IOPORT  IOPORT4
+#define TEENSY_PIN54_IOPORT  IOPORT4
+#define TEENSY_PIN55_IOPORT  IOPORT4
+#define TEENSY_PIN47_IOPORT  IOPORT4
+#define TEENSY_PIN48_IOPORT  IOPORT4
+#define TEENSY_PIN2_IOPORT   IOPORT4
+#define TEENSY_PIN5_IOPORT   IOPORT4
+#define TEENSY_PIN6_IOPORT   IOPORT4
+#define TEENSY_PIN7_IOPORT   IOPORT4
+#define TEENSY_PIN8_IOPORT   IOPORT4
+#define TEENSY_PIN14_IOPORT  IOPORT4
+#define TEENSY_PIN20_IOPORT  IOPORT4
+#define TEENSY_PIN21_IOPORT  IOPORT4
+
+#define PORTE_PIN0                  0
+#define PORTE_PIN1                  1
+#define PORTE_PIN2                  2
+#define PORTE_PIN3                  3
+#define PORTE_PIN4                  4
+#define PORTE_PIN5                  5
+#define PORTE_PIN6                  6
+#define PORTE_PIN7                  7
+#define PORTE_PIN8                  8
+#define PORTE_PIN9                  9
+#define TEENSY_PIN56                10
+#define TEENSY_PIN57                11
+#define PORTE_PIN12                 12
+#define PORTE_PIN13                 13
+#define PORTE_PIN14                 14
+#define PORTE_PIN15                 15
+#define PORTE_PIN16                 16
+#define PORTE_PIN17                 17
+#define PORTE_PIN18                 18
+#define PORTE_PIN19                 19
+#define PORTE_PIN20                 20
+#define PORTE_PIN21                 21
+#define PORTE_PIN22                 22
+#define PORTE_PIN23                 23
+#define TEENSY_PIN33                24
+#define TEENSY_PIN34                25
+#define TEENSY_PIN24                26
+#define PORTE_PIN27                 27
+#define PORTE_PIN28                 28
+#define PORTE_PIN29                 29
+#define PORTE_PIN30                 30
+#define PORTE_PIN31                 31
+
+#define TEENSY_PIN56_IOPORT  IOPORT5
+#define TEENSY_PIN57_IOPORT  IOPORT5
+#define TEENSY_PIN24_IOPORT  IOPORT5
+#define TEENSY_PIN33_IOPORT  IOPORT5
+#define TEENSY_PIN34_IOPORT  IOPORT5
+
+
+#define LINE_PIN0           PAL_LINE(TEENSY_PIN0_IOPORT, TEENSY_PIN0)
+#define LINE_PIN1           PAL_LINE(TEENSY_PIN1_IOPORT, TEENSY_PIN1)
+#define LINE_PIN2           PAL_LINE(TEENSY_PIN2_IOPORT, TEENSY_PIN2)
+#define LINE_PIN3           PAL_LINE(TEENSY_PIN3_IOPORT, TEENSY_PIN3)
+#define LINE_PIN4           PAL_LINE(TEENSY_PIN4_IOPORT, TEENSY_PIN4)
+#define LINE_PIN5           PAL_LINE(TEENSY_PIN5_IOPORT, TEENSY_PIN5)
+#define LINE_PIN6           PAL_LINE(TEENSY_PIN6_IOPORT, TEENSY_PIN6)
+#define LINE_PIN7           PAL_LINE(TEENSY_PIN7_IOPORT, TEENSY_PIN7)
+#define LINE_PIN8           PAL_LINE(TEENSY_PIN8_IOPORT, TEENSY_PIN8)
+#define LINE_PIN9           PAL_LINE(TEENSY_PIN9_IOPORT, TEENSY_PIN9)
+#define LINE_PIN10          PAL_LINE(TEENSY_PIN10_IOPORT, TEENSY_PIN10)
+#define LINE_PIN11          PAL_LINE(TEENSY_PIN11_IOPORT, TEENSY_PIN11)
+#define LINE_PIN12          PAL_LINE(TEENSY_PIN12_IOPORT, TEENSY_PIN12)
+#define LINE_PIN13          PAL_LINE(TEENSY_PIN13_IOPORT, TEENSY_PIN13)
+#define LINE_PIN14          PAL_LINE(TEENSY_PIN14_IOPORT, TEENSY_PIN14)
+#define LINE_PIN15          PAL_LINE(TEENSY_PIN15_IOPORT, TEENSY_PIN15)
+#define LINE_PIN16          PAL_LINE(TEENSY_PIN16_IOPORT, TEENSY_PIN16)
+#define LINE_PIN17          PAL_LINE(TEENSY_PIN17_IOPORT, TEENSY_PIN17)
+#define LINE_PIN18          PAL_LINE(TEENSY_PIN18_IOPORT, TEENSY_PIN18)
+#define LINE_PIN19          PAL_LINE(TEENSY_PIN19_IOPORT, TEENSY_PIN19)
+#define LINE_PIN20          PAL_LINE(TEENSY_PIN20_IOPORT, TEENSY_PIN20)
+#define LINE_PIN21          PAL_LINE(TEENSY_PIN21_IOPORT, TEENSY_PIN21)
+#define LINE_PIN22          PAL_LINE(TEENSY_PIN22_IOPORT, TEENSY_PIN22)
+#define LINE_PIN23          PAL_LINE(TEENSY_PIN23_IOPORT, TEENSY_PIN23)
+#define LINE_PIN24          PAL_LINE(TEENSY_PIN24_IOPORT, TEENSY_PIN24)
+#define LINE_PIN25          PAL_LINE(TEENSY_PIN25_IOPORT, TEENSY_PIN25)
+#define LINE_PIN25          PAL_LINE(TEENSY_PIN25_IOPORT, TEENSY_PIN25)
+#define LINE_PIN26          PAL_LINE(TEENSY_PIN26_IOPORT, TEENSY_PIN26)
+#define LINE_PIN27          PAL_LINE(TEENSY_PIN27_IOPORT, TEENSY_PIN27)
+#define LINE_PIN28          PAL_LINE(TEENSY_PIN28_IOPORT, TEENSY_PIN28)
+#define LINE_PIN29          PAL_LINE(TEENSY_PIN29_IOPORT, TEENSY_PIN29)
+#define LINE_PIN30          PAL_LINE(TEENSY_PIN30_IOPORT, TEENSY_PIN30)
+#define LINE_PIN31          PAL_LINE(TEENSY_PIN31_IOPORT, TEENSY_PIN31)
+#define LINE_PIN32          PAL_LINE(TEENSY_PIN32_IOPORT, TEENSY_PIN32)
+#define LINE_PIN33          PAL_LINE(TEENSY_PIN33_IOPORT, TEENSY_PIN33)
+#define LINE_PIN34          PAL_LINE(TEENSY_PIN34_IOPORT, TEENSY_PIN34)
+#define LINE_PIN35          PAL_LINE(TEENSY_PIN35_IOPORT, TEENSY_PIN35)
+#define LINE_PIN36          PAL_LINE(TEENSY_PIN36_IOPORT, TEENSY_PIN36)
+#define LINE_PIN37          PAL_LINE(TEENSY_PIN37_IOPORT, TEENSY_PIN37)
+#define LINE_PIN38          PAL_LINE(TEENSY_PIN38_IOPORT, TEENSY_PIN38)
+#define LINE_PIN39          PAL_LINE(TEENSY_PIN39_IOPORT, TEENSY_PIN39)
+#define LINE_PIN40          PAL_LINE(TEENSY_PIN40_IOPORT, TEENSY_PIN40)
+#define LINE_PIN41          PAL_LINE(TEENSY_PIN41_IOPORT, TEENSY_PIN41)
+#define LINE_PIN42          PAL_LINE(TEENSY_PIN42_IOPORT, TEENSY_PIN42)
+#define LINE_PIN43          PAL_LINE(TEENSY_PIN43_IOPORT, TEENSY_PIN43)
+#define LINE_PIN44          PAL_LINE(TEENSY_PIN44_IOPORT, TEENSY_PIN44)
+#define LINE_PIN45          PAL_LINE(TEENSY_PIN45_IOPORT, TEENSY_PIN45)
+#define LINE_PIN46          PAL_LINE(TEENSY_PIN46_IOPORT, TEENSY_PIN46)
+#define LINE_PIN47          PAL_LINE(TEENSY_PIN47_IOPORT, TEENSY_PIN47)
+#define LINE_PIN48          PAL_LINE(TEENSY_PIN48_IOPORT, TEENSY_PIN48)
+#define LINE_PIN49          PAL_LINE(TEENSY_PIN49_IOPORT, TEENSY_PIN49)
+#define LINE_PIN50          PAL_LINE(TEENSY_PIN50_IOPORT, TEENSY_PIN50)
+#define LINE_PIN51          PAL_LINE(TEENSY_PIN51_IOPORT, TEENSY_PIN50)
+#define LINE_PIN52          PAL_LINE(TEENSY_PIN52_IOPORT, TEENSY_PIN52)
+#define LINE_PIN53          PAL_LINE(TEENSY_PIN53_IOPORT, TEENSY_PIN53)
+#define LINE_PIN54          PAL_LINE(TEENSY_PIN54_IOPORT, TEENSY_PIN54)
+#define LINE_PIN55          PAL_LINE(TEENSY_PIN55_IOPORT, TEENSY_PIN55)
+#define LINE_PIN56          PAL_LINE(TEENSY_PIN56_IOPORT, TEENSY_PIN56)
+#define LINE_PIN57          PAL_LINE(TEENSY_PIN57_IOPORT, TEENSY_PIN57)
+
+#define LINE_LED            LINE_PIN13
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
diff --git a/os/hal/boards/PJRC_TEENSY_3_6/board.mk b/os/hal/boards/PJRC_TEENSY_3_6/board.mk
new file mode 100644
index 0000000..6e2695c
--- /dev/null
+++ b/os/hal/boards/PJRC_TEENSY_3_6/board.mk
@@ -0,0 +1,5 @@
+# List of all the board related files.
+BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_3_6/board.c
+
+# Required include directories
+BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/PJRC_TEENSY_3_6
diff --git a/os/hal/ports/KINETIS/LLD/hal_serial_lld.c b/os/hal/ports/KINETIS/LLD/hal_serial_lld.c
index c80cf22..c75d41a 100644
--- a/os/hal/ports/KINETIS/LLD/hal_serial_lld.c
+++ b/os/hal/ports/KINETIS/LLD/hal_serial_lld.c
@@ -50,6 +50,18 @@ SerialDriver SD2;
 SerialDriver SD3;
 #endif
 
+#if KINETIS_SERIAL_USE_UART3 || defined(__DOXYGEN__)
+SerialDriver SD4;
+#endif
+
+#if KINETIS_SERIAL_USE_UART4 || defined(__DOXYGEN__)
+SerialDriver SD5;
+#endif
+
+#if KINETIS_SERIAL_USE_UART5 || defined(__DOXYGEN__)
+SerialDriver SD6;
+#endif
+
 /*===========================================================================*/
 /* Driver local variables and types.                                         */
 /*===========================================================================*/
diff --git a/os/hal/ports/KINETIS/LLD/hal_serial_lld.h b/os/hal/ports/KINETIS/LLD/hal_serial_lld.h
index f11c063..3cb6d2b 100644
--- a/os/hal/ports/KINETIS/LLD/hal_serial_lld.h
+++ b/os/hal/ports/KINETIS/LLD/hal_serial_lld.h
@@ -60,6 +60,27 @@
 #if !defined(KINETIS_SERIAL_USE_UART2) || defined(__DOXYGEN__)
 #define KINETIS_SERIAL_USE_UART2             FALSE
 #endif
+/**
+ * @brief   SD4 driver enable switch.
+ * @details If set to @p TRUE the support for SD4 is included.
+ */
+#if !defined(KINETIS_SERIAL_USE_UART3) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_USE_UART3             FALSE
+#endif
+/**
+ * @brief   SD5 driver enable switch.
+ * @details If set to @p TRUE the support for SD5 is included.
+ */
+#if !defined(KINETIS_SERIAL_USE_UART4) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_USE_UART4             FALSE
+#endif
+/**
+ * @brief   SD6 driver enable switch.
+ * @details If set to @p TRUE the support for SD6 is included.
+ */
+#if !defined(KINETIS_SERIAL_USE_UART5) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_USE_UART5             FALSE
+#endif
 
 /**
  * @brief   UART0 interrupt priority level setting.
@@ -82,6 +103,27 @@
 #define KINETIS_SERIAL_UART2_PRIORITY        12
 #endif
 
+/**
+ * @brief   UART3 interrupt priority level setting.
+ */
+#if !defined(KINETIS_SERIAL_UART3_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_UART3_PRIORITY        12
+#endif
+
+/**
+ * @brief   UART4 interrupt priority level setting.
+ */
+#if !defined(KINETIS_SERIAL_UART4_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_UART4_PRIORITY        12
+#endif
+
+/**
+ * @brief   UART5 interrupt priority level setting.
+ */
+#if !defined(KINETIS_SERIAL_UART5_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_UART5_PRIORITY        12
+#endif
+
 /**
  * @brief   UART0 clock source.
  */
@@ -115,8 +157,21 @@
 #error "UART2 not present in the selected device"
 #endif
 
+#if KINETIS_SERIAL_USE_UART3 && !KINETIS_HAS_SERIAL3
+#error "UART3 not present in the selected device"
+#endif
+
+#if KINETIS_SERIAL_USE_UART4 && !KINETIS_HAS_SERIAL4
+#error "UART4 not present in the selected device"
+#endif
+
+#if KINETIS_SERIAL_USE_UART5 && !KINETIS_HAS_SERIAL5
+#error "UART5 not present in the selected device"
+#endif
+
 #if !(KINETIS_SERIAL_USE_UART0 || KINETIS_SERIAL_USE_UART1 || \
-      KINETIS_SERIAL_USE_UART2)
+      KINETIS_SERIAL_USE_UART2 || KINETIS_SERIAL_USE_UART3 || \
+      KINETIS_SERIAL_USE_UART4 || KINETIS_SERIAL_USE_UART5)
 #error "Serial driver activated but no UART peripheral assigned"
 #endif
 
@@ -203,6 +258,18 @@ extern SerialDriver SD2;
 extern SerialDriver SD3;
 #endif
 
+#if KINETIS_SERIAL_USE_UART3 && !defined(__DOXYGEN__)
+extern SerialDriver SD4;
+#endif
+
+#if KINETIS_SERIAL_USE_UART4 && !defined(__DOXYGEN__)
+extern SerialDriver SD5;
+#endif
+
+#if KINETIS_SERIAL_USE_UART5 && !defined(__DOXYGEN__)
+extern SerialDriver SD6;
+#endif
+
 #ifdef __cplusplus
 extern "C" {
 #endif
diff --git a/os/hal/ports/KINETIS/MK66F18/hal_lld.c b/os/hal/ports/KINETIS/MK66F18/hal_lld.c
new file mode 100644
index 0000000..857f384
--- /dev/null
+++ b/os/hal/ports/KINETIS/MK66F18/hal_lld.c
@@ -0,0 +1,238 @@
+/*
+    ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    templates/hal_lld.c
+ * @brief   HAL Driver subsystem low level driver source template.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#include "hal.h"
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+#ifdef __CC_ARM
+__attribute__ ((section(".ARM.__at_0x400")))
+#else
+__attribute__ ((used,section(".cfmconfig")))
+#endif
+const uint8_t _cfm[0x10] = {
+  0xFF,  /* NV_BACKKEY3: KEY=0xFF */
+  0xFF,  /* NV_BACKKEY2: KEY=0xFF */
+  0xFF,  /* NV_BACKKEY1: KEY=0xFF */
+  0xFF,  /* NV_BACKKEY0: KEY=0xFF */
+  0xFF,  /* NV_BACKKEY7: KEY=0xFF */
+  0xFF,  /* NV_BACKKEY6: KEY=0xFF */
+  0xFF,  /* NV_BACKKEY5: KEY=0xFF */
+  0xFF,  /* NV_BACKKEY4: KEY=0xFF */
+  0xFF,  /* NV_FPROT3: PROT=0xFF */
+  0xFF,  /* NV_FPROT2: PROT=0xFF */
+  0xFF,  /* NV_FPROT1: PROT=0xFF */
+  0xFF,  /* NV_FPROT0: PROT=0xFF */
+  0x7E,  /* NV_FSEC: KEYEN=1,MEEN=3,FSLACC=3,SEC=2 */
+  0xFF,  /* NV_FOPT: ??=1,??=1,FAST_INIT=1,LPBOOT1=1,RESET_PIN_CFG=1,
+                      NMI_DIS=1,EZPORT_DIS=1,LPBOOT0=1 */
+  0xFF,
+  0xFF
+};
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level HAL driver initialization.
+ * @todo    Use a macro to define the system clock frequency.
+ *
+ * @notapi
+ */
+void hal_lld_init(void) {
+
+}
+
+/**
+ * @brief   MK66F18 clock initialization.
+ * @note    All the involved constants come from the file @p board.h.
+ * @note    This function is meant to be invoked early during the system
+ *          initialization, it is usually invoked from the file
+ *          @p board.c.
+ * @todo    This function needs to be more generic.
+ *
+ * @special
+ */
+void MK66F18_clock_init(void) {
+#if !KINETIS_NO_INIT
+
+  /* Disable the watchdog */
+  WDOG->UNLOCK = 0xC520;
+  WDOG->UNLOCK = 0xD928;
+  WDOG->STCTRLH &= ~WDOG_STCTRLH_WDOGEN;
+
+  SIM->SCGC5 |= SIM_SCGC5_PORTA |
+                SIM_SCGC5_PORTB |
+                SIM_SCGC5_PORTC |
+                SIM_SCGC5_PORTD |
+                SIM_SCGC5_PORTE;
+
+#if KINETIS_MCG_MODE == KINETIS_MCG_MODE_FEI
+  /* This is the default mode at reset. */
+
+  /* Configure FEI mode */
+  MCG->C4 = MCG_C4_DRST_DRS(KINETIS_MCG_FLL_DRS) |
+            (KINETIS_MCG_FLL_DMX32 ? MCG_C4_DMX32 : 0);
+
+  /* Set clock dividers */
+  SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1-1) |
+                 SIM_CLKDIV1_OUTDIV2(KINETIS_CLKDIV1_OUTDIV2-1) |
+#if defined(MK66F18)
+                 SIM_CLKDIV1_OUTDIV3(KINETIS_CLKDIV1_OUTDIV3-1) |
+#endif
+                 SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4-1);
+  SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0); /* not strictly necessary since usb_lld will set this */
+
+#elif KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE
+
+  uint32_t ratio, frdiv;
+  uint32_t ratios[] = { 32, 64, 128, 256, 512, 1024, 1280, 1536 };
+  uint8_t ratio_quantity = sizeof(ratios) / sizeof(ratios[0]);
+  uint8_t i;
+
+  /* EXTAL0 and XTAL0 */
+  PORTA->PCR[18] = 0;
+  PORTA->PCR[19] = 0;
+
+  /*
+   * Start in FEI mode
+   */
+
+  /* Internal capacitors for crystal */
+#if defined(KINETIS_BOARD_OSCILLATOR_SETTING)
+  OSC0->CR = KINETIS_BOARD_OSCILLATOR_SETTING;
+#else /* KINETIS_BOARD_OSCILLATOR_SETTING */
+  /* Disable the internal capacitors */
+  OSC0->CR = 0;
+#endif /* KINETIS_BOARD_OSCILLATOR_SETTING */
+
+  /* TODO: need to add more flexible calculation, specially regarding
+   *       divisors which may not be available depending on the XTAL
+   *       frequency, which would required other registers to be modified.
+   */
+  /* Enable OSC, low power mode */
+  if (KINETIS_XTAL_FREQUENCY > 8000000UL)
+    MCG->C2 = MCG_C2_LOCRE0 | MCG_C2_EREFS0 | MCG_C2_RANGE0(2);
+  else
+    MCG->C2 = MCG_C2_LOCRE0 | MCG_C2_EREFS0 | MCG_C2_RANGE0(1);
+
+  frdiv = 7;
+  ratio = KINETIS_XTAL_FREQUENCY / 31250UL;
+  for (i = 0; i < ratio_quantity; ++i) {
+    if (ratio == ratios[i]) {
+      frdiv = i;
+      break;
+    }
+  }
+
+  /* Switch to crystal as clock source, FLL input of 31.25 KHz */
+  MCG->C1 = MCG_C1_CLKS(2) | MCG_C1_FRDIV(frdiv);
+
+  /* Wait for crystal oscillator to begin */
+  while (!(MCG->S & MCG_S_OSCINIT0));
+
+  /* Wait for the FLL to use the oscillator */
+  while (MCG->S & MCG_S_IREFST);
+
+  /* Wait for the MCGOUTCLK to use the oscillator */
+  while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST(2));
+
+  /*
+   * Now in FBE mode
+   */
+  #define KINETIS_PLLIN_FREQUENCY 2000000UL
+  /*
+   * Config PLL input for 2 MHz
+   * TODO: Make sure KINETIS_XTAL_FREQUENCY >= 2Mhz && <= 50Mhz
+   */
+  MCG->C5 = MCG_C5_PRDIV0((KINETIS_XTAL_FREQUENCY/KINETIS_PLLIN_FREQUENCY) - 1);
+
+  /*
+   * Config PLL output to match KINETIS_SYSCLK_FREQUENCY
+   * TODO: make sure KINETIS_SYSCLK_FREQUENCY is a match
+   */
+  for(i = 24; i < 56; i++)
+  {
+    if(i == (KINETIS_PLLCLK_FREQUENCY/KINETIS_PLLIN_FREQUENCY))
+    {
+      /* Config PLL to match KINETIS_PLLCLK_FREQUENCY */
+      MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(i-24);
+      break;
+    }
+  }
+
+  if(i>=56)  /* Config PLL for 96 MHz output as default setting */
+    MCG->C6 = MCG_C6_PLLS | MCG_C6_VDIV0(0);
+
+  /* Wait for PLL to start using crystal as its input, and to lock */
+  while ((MCG->S & (MCG_S_PLLST|MCG_S_LOCK0))!=(MCG_S_PLLST|MCG_S_LOCK0));
+
+  /*
+   * Now in PBE mode
+   */
+  /* Set the PLL dividers for the different clocks */
+  SIM->CLKDIV1 = SIM_CLKDIV1_OUTDIV1(KINETIS_CLKDIV1_OUTDIV1-1) |
+                 SIM_CLKDIV1_OUTDIV2(KINETIS_CLKDIV1_OUTDIV2-1) |
+                 SIM_CLKDIV1_OUTDIV4(KINETIS_CLKDIV1_OUTDIV4-1);
+  SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0);
+
+  /* Configure peripherals to use MCGPLLCLK */
+  SIM->SOPT2 = SIM_SOPT2_PLLFLLSEL;
+
+  /* Switch to PLL as clock source */
+  MCG->C1 = MCG_C1_CLKS(0);
+
+  /* Wait for PLL clock to be used */
+  while ((MCG->S & MCG_S_CLKST_MASK) != MCG_S_CLKST_PLL);
+
+  /*
+   * Now in PEE mode
+   */
+#else /* KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE */
+#error Unimplemented KINETIS_MCG_MODE
+#endif /* KINETIS_MCG_MODE == ... */
+
+#endif /* !KINETIS_NO_INIT */
+}
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/MK66F18/hal_lld.h b/os/hal/ports/KINETIS/MK66F18/hal_lld.h
new file mode 100644
index 0000000..832955e
--- /dev/null
+++ b/os/hal/ports/KINETIS/MK66F18/hal_lld.h
@@ -0,0 +1,319 @@
+/*
+    ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    MK66F18/hal_lld.h
+ * @brief   Kinetis MK66F18 HAL subsystem low level driver header.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef HAL_LLD_H_
+#define HAL_LLD_H_
+
+#include "kinetis_registry.h"
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Defines the support for realtime counters in the HAL.
+ */
+#define HAL_IMPLEMENTS_COUNTERS FALSE
+
+/**
+ * @name    Platform identification
+ * @{
+ */
+#define PLATFORM_NAME           "Kinetis"
+/** @} */
+
+/**
+ * @name    Internal clock sources
+ * @{
+ */
+#define KINETIS_IRCLK_F         4000000     /**< Fast internal reference clock, factory trimmed. */
+#define KINETIS_IRCLK_S         32768       /**< Slow internal reference clock, factory trimmed. */
+/** @} */
+
+#define KINETIS_MCG_MODE_FEI    1    /**< FLL Engaged Internal. */
+#define KINETIS_MCG_MODE_FEE    2    /**< FLL Engaged External. */
+#define KINETIS_MCG_MODE_FBI    3    /**< FLL Bypassed Internal. */
+#define KINETIS_MCG_MODE_FBE    4    /**< FLL Bypassed External. */
+#define KINETIS_MCG_MODE_PEE    5    /**< PLL Engaged External. */
+#define KINETIS_MCG_MODE_PBE    6    /**< PLL Bypassed External. */
+#define KINETIS_MCG_MODE_BLPI   7    /**< Bypassed Low Power Internal. */
+#define KINETIS_MCG_MODE_BLPE   8    /**< Bypassed Low Power External. */
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   Disables the MCG/system clock initialization in the HAL.
+ */
+#if !defined(KINETIS_NO_INIT) || defined(__DOXYGEN__)
+#define KINETIS_NO_INIT             FALSE
+#endif
+
+/**
+ * @brief   MCG mode selection.
+ */
+#if !defined(KINETIS_MCG_MODE) || defined(__DOXYGEN__)
+#define KINETIS_MCG_MODE            KINETIS_MCG_MODE_PEE
+#endif
+
+/**
+ * @brief   MCU PLL clock frequency.
+ */
+#if !defined(KINETIS_PLLCLK_FREQUENCY) || defined(__DOXYGEN__)
+#define KINETIS_PLLCLK_FREQUENCY    96000000UL
+#endif
+
+/**
+ * @brief   Clock divider for core/system clocks (OUTDIV1).
+ * @note    The allowed range is 1..16
+ * @note    The default value is calculated for a 48 MHz system clock
+ *          from a 96 MHz PLL output.
+ */
+#if !defined(KINETIS_CLKDIV1_OUTDIV1) || defined(__DOXYGEN__)
+  #if defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
+    #define KINETIS_CLKDIV1_OUTDIV1     (KINETIS_PLLCLK_FREQUENCY/KINETIS_SYSCLK_FREQUENCY)
+  #else
+    #define KINETIS_CLKDIV1_OUTDIV1     2
+  #endif
+#endif
+
+/**
+ * @brief   Clock divider for bus clock (OUTDIV2).
+ * @note    The allowed range is 1..16
+ * @note    The default value is calculated for a 48 MHz bus clock
+ *          from a 96 MHz PLL output.
+ */
+#if !defined(KINETIS_CLKDIV1_OUTDIV2) || defined(__DOXYGEN__)
+  #if defined(KINETIS_BUSCLK_FREQUENCY) && KINETIS_BUSCLK_FREQUENCY > 0
+    #define KINETIS_CLKDIV1_OUTDIV2     (KINETIS_PLLCLK_FREQUENCY/KINETIS_BUSCLK_FREQUENCY)
+  #elif defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
+    #define KINETIS_CLKDIV1_OUTDIV2	KINETIS_CLKDIV1_OUTDIV1
+  #else
+    #define KINETIS_CLKDIV1_OUTDIV2     2
+  #endif
+#endif
+
+/**
+ * @brief   Clock divider for FlexBus clock (OUTDIV3).
+ * @note    The allowed range is 1..16
+ * @note    The default value is calculated for a 48 MHz clock
+ *          from a 96 MHz PLL output.
+ */
+#if !defined(KINETIS_CLKDIV1_OUTDIV3) || defined(__DOXYGEN__)
+  #if defined(KINETIS_FLEXBUSCLK_FREQUENCY) && KINETIS_FLEXBUSCLK_FREQUENCY > 0
+    #define KINETIS_CLKDIV1_OUTDIV3     (KINETIS_PLLCLK_FREQUENCY/KINETIS_FLEXBUSCLK_FREQUENCY)
+  #endif
+#endif
+
+/**
+ * @brief   Clock divider for flash clock (OUTDIV4).
+ * @note    The allowed range is 1..16
+ * @note    The default value is calculated for a 24 MHz flash clock
+ *          from a 96 MHz PLL output
+ */
+#if !defined(KINETIS_CLKDIV1_OUTDIV4) || defined(__DOXYGEN__)
+  #if defined(KINETIS_FLASHCLK_FREQUENCY) && KINETIS_FLASHCLK_FREQUENCY > 0
+    #define KINETIS_CLKDIV1_OUTDIV4     (KINETIS_PLLCLK_FREQUENCY/KINETIS_FLASHCLK_FREQUENCY)
+  #elif defined(KINETIS_SYSCLK_FREQUENCY) && KINETIS_SYSCLK_FREQUENCY > 0
+    #define KINETIS_CLKDIV1_OUTDIV4	(KINETIS_CLKDIV1_OUTDIV1*2)
+  #else
+    #define KINETIS_CLKDIV1_OUTDIV4     4
+  #endif
+#endif
+
+/**
+ * @brief   FLL DCO tuning enable for 32.768 kHz reference.
+ * @note    Set to 1 for fine-tuning DCO for maximum frequency with
+ *          a 32.768 kHz reference.
+ * @note    The default value is for a 32.768 kHz external crystal.
+ */
+#if !defined(KINETIS_MCG_FLL_DMX32) || defined(__DOXYGEN__)
+#define KINETIS_MCG_FLL_DMX32       1
+#endif
+
+/**
+ * @brief   FLL DCO range selection.
+ * @note    The allowed range is 0...3.
+ * @note    The default value is calculated for 48 MHz FLL output
+ *          from a 32.768 kHz external crystal.
+ *          (DMX32 && DRST_DRS=1 => F=1464; 32.768 kHz * F ~= 48 MHz.)
+ *
+ */
+#if !defined(KINETIS_MCG_FLL_DRS) || defined(__DOXYGEN__)
+#define KINETIS_MCG_FLL_DRS         2
+#endif
+
+/**
+ * @brief   MCU system/core clock frequency.
+ */
+#if !defined(KINETIS_SYSCLK_FREQUENCY) || defined(__DOXYGEN__)
+#define KINETIS_SYSCLK_FREQUENCY    (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV1)
+#endif
+
+/**
+ * @brief   MCU bus clock frequency.
+ */
+#if !defined(KINETIS_BUSCLK_FREQUENCY) || defined(__DOXYGEN__)
+#define KINETIS_BUSCLK_FREQUENCY    (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV2)
+#endif
+
+/**
+ * @brief   MCU flash clock frequency.
+ */
+#if !defined(KINETIS_FLASHCLK_FREQUENCY) || defined(__DOXYGEN__)
+#define KINETIS_FLASHCLK_FREQUENCY    (KINETIS_PLLCLK_FREQUENCY / KINETIS_CLKDIV1_OUTDIV4)
+#endif
+
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if !defined(KINETIS_SYSCLK_FREQUENCY)
+  #error KINETIS_SYSCLK_FREQUENCY must be defined
+#endif
+
+#if KINETIS_SYSCLK_FREQUENCY <= 0 || KINETIS_SYSCLK_FREQUENCY > KINETIS_SYSCLK_MAX
+  #error KINETIS_SYSCLK_FREQUENCY out of range
+#endif
+
+#if !defined(KINETIS_BUSCLK_FREQUENCY)
+  #error KINETIS_BUSCLK_FREQUENCY must be defined
+#endif
+
+#if KINETIS_BUSCLK_FREQUENCY <= 0 || KINETIS_BUSCLK_FREQUENCY > KINETIS_BUSCLK_MAX
+  #error KINETIS_BUSCLK_FREQUENCY out of range
+#endif
+
+#if KINETIS_BUSCLK_FREQUENCY > KINETIS_SYSCLK_FREQUENCY
+  #error KINETIS_BUSCLK_FREQUENCY must be an integer divide of\
+	 KINETIS_SYSCLK_FREQUENCY
+#endif
+
+#if !defined(KINETIS_FLASHCLK_FREQUENCY)
+  #error KINETIS_FLASHCLK_FREQUENCY must be defined
+#endif
+
+#if KINETIS_FLASHCLK_FREQUENCY <= 0 || KINETIS_FLASHCLK_FREQUENCY > KINETIS_FLASHCLK_MAX
+  #error KINETIS_FLASHCLK_FREQUENCY out of range
+#endif
+
+#if KINETIS_FLASHCLK_FREQUENCY > KINETIS_SYSCLK_FREQUENCY
+  #error KINETIS_FLASHCLK_FREQUENCY must be an integer divide of\
+	 KINETIS_SYSCLK_FREQUENCY
+#endif
+
+#if !(defined(KINETIS_CLKDIV1_OUTDIV1) && \
+      KINETIS_CLKDIV1_OUTDIV1 >= 1 && KINETIS_CLKDIV1_OUTDIV1 <= 16)
+  #error KINETIS_CLKDIV1_OUTDIV1 must be 1 through 16
+#endif
+
+#if !(defined(KINETIS_CLKDIV1_OUTDIV2) && \
+      KINETIS_CLKDIV1_OUTDIV2 >= 1 && KINETIS_CLKDIV1_OUTDIV2 <= 16)
+#error KINETIS_CLKDIV1_OUTDIV2 must be 1 through 16
+#endif
+
+#if !(defined(KINETIS_CLKDIV1_OUTDIV3) && \
+      KINETIS_CLKDIV1_OUTDIV3 >= 1 && KINETIS_CLKDIV1_OUTDIV3 <= 16)
+#error KINETIS_CLKDIV1_OUTDIV3 must be 1 through 16
+#endif
+
+#if !(defined(KINETIS_CLKDIV1_OUTDIV4) && \
+      KINETIS_CLKDIV1_OUTDIV4 >= 1 && KINETIS_CLKDIV1_OUTDIV4 <= 16)
+#error KINETIS_CLKDIV1_OUTDIV4 must be 1 through 16
+#endif
+
+#if !(KINETIS_MCG_FLL_DMX32 == 0 || KINETIS_MCG_FLL_DMX32 == 1)
+#error Invalid KINETIS_MCG_FLL_DMX32 value, must be 0 or 1
+#endif
+
+#if !(0 <= KINETIS_MCG_FLL_DRS && KINETIS_MCG_FLL_DRS <= 3)
+#error Invalid KINETIS_MCG_FLL_DRS value, must be 0...3
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type representing a system clock frequency.
+ */
+typedef uint32_t halclock_t;
+
+/**
+ * @brief   Type of the realtime free counter value.
+ */
+typedef uint32_t halrtcnt_t;
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Returns the current value of the system free running counter.
+ * @note    This service is implemented by returning the content of the
+ *          DWT_CYCCNT register.
+ *
+ * @return              The value of the system free running counter of
+ *                      type halrtcnt_t.
+ *
+ * @notapi
+ */
+#define hal_lld_get_counter_value()         0
+
+/**
+ * @brief   Realtime counter frequency.
+ * @note    The DWT_CYCCNT register is incremented directly by the system
+ *          clock so this function returns STM32_HCLK.
+ *
+ * @return              The realtime counter frequency of type halclock_t.
+ *
+ * @notapi
+ */
+#define hal_lld_get_counter_frequency()     0
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#include "nvic.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void hal_lld_init(void);
+  void MK66F18_clock_init(void);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/MK66F18/hal_pwm_lld.c b/os/hal/ports/KINETIS/MK66F18/hal_pwm_lld.c
new file mode 100644
index 0000000..f39823d
--- /dev/null
+++ b/os/hal/ports/KINETIS/MK66F18/hal_pwm_lld.c
@@ -0,0 +1,390 @@
+/*
+    ChibiOS/HAL - Copyright (C) 2014 Adam J. Porter
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    MK66F18/pwm_lld.c
+ * @brief   KINETIS PWM subsystem low level driver source.
+ *
+ * @addtogroup PWM
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_PWM || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   PWMD1 driver identifier.
+ * @note    The driver PWMD1 allocates the timer FTM0 when enabled.
+ */
+#if KINETIS_PWM_USE_FTM0 || defined(__DOXYGEN__)
+PWMDriver PWMD1;
+#endif
+
+/**
+ * @brief   PWMD2 driver identifier.
+ * @note    The driver PWMD2 allocates the timer FTM1 when enabled.
+ */
+#if KINETIS_PWM_USE_FTM1 || defined(__DOXYGEN__)
+PWMDriver PWMD2;
+#endif
+
+/**
+ * @brief   PWMD3 driver identifier.
+ * @note    The driver PWMD3 allocates the timer FTM2 when enabled.
+ */
+#if KINETIS_PWM_USE_FTM2 || defined(__DOXYGEN__)
+PWMDriver PWMD3;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+static void pwm_lld_serve_interrupt(PWMDriver *pwmp) {
+  uint32_t sr;
+
+  sr = pwmp->ftm->SC;
+  pwmp->ftm->SC = sr&(~FTM_SC_TOF);
+
+  if (((sr & FTM_SC_TOF) != 0) &&                          /* Timer Overflow */
+      ((sr & FTM_SC_TOIE) != 0) &&
+      (pwmp->config->callback != NULL)) {
+    pwmp->config->callback(pwmp);
+  }
+
+  uint8_t n=0;
+  for(n=0;n<pwmp->channels;n++) {
+    sr = pwmp->ftm->CHANNEL[n].CnSC;
+    pwmp->ftm->CHANNEL[n].CnSC = sr&(~FTM_CnSC_CHF);
+    if (((sr & FTM_CnSC_CHF) != 0) &&
+        ((sr & FTM_CnSC_CHIE) != 0) &&
+        (pwmp->config->channels[n].callback != NULL)) {
+      pwmp->config->channels[n].callback(pwmp);
+    }
+  }
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if KINETIS_PWM_USE_FTM0
+/**
+ * @brief   FTM0 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_FTM0_IRQ_VECTOR) {
+  OSAL_IRQ_PROLOGUE();
+  pwm_lld_serve_interrupt(&PWMD1);
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_PWM_USE_FTM0 */
+
+#if KINETIS_PWM_USE_FTM1
+/**
+ * @brief   FTM1 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_FTM1_IRQ_VECTOR) {
+
+  OSAL_IRQ_PROLOGUE();
+  pwm_lld_serve_interrupt(&PWMD2);
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_PWM_USE_FTM1 */
+
+#if KINETIS_PWM_USE_FTM2
+/**
+ * @brief   FTM2 interrupt handler.
+ *
+ * @isr
+ */
+OSAL_IRQ_HANDLER(KINETIS_FTM2_IRQ_VECTOR) {
+
+  OSAL_IRQ_PROLOGUE();
+  pwm_lld_serve_interrupt(&PWMD3);
+  OSAL_IRQ_EPILOGUE();
+}
+#endif /* KINETIS_PWM_USE_FTM2 */
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level PWM driver initialization.
+ *
+ * @notapi
+ */
+void pwm_lld_init(void) {
+
+#if KINETIS_PWM_USE_FTM0
+  pwmObjectInit(&PWMD1);
+  PWMD1.channels = KINETIS_FTM0_CHANNELS;
+  PWMD1.ftm = FTM0;
+#endif
+
+#if KINETIS_PWM_USE_FTM1
+  pwmObjectInit(&PWMD2);
+  PWMD2.channels = KINETIS_FTM1_CHANNELS;
+  PWMD2.ftm = FTM1;
+#endif
+
+#if KINETIS_PWM_USE_FTM2
+  pwmObjectInit(&PWMD3);
+  PWMD3.channels = KINETIS_FTM2_CHANNELS;
+  PWMD3.ftm = FTM2;
+#endif
+}
+
+/**
+ * @brief   Configures and activates the PWM peripheral.
+ * @note    Starting a driver that is already in the @p PWM_READY state
+ *          disables all the active channels.
+ *
+ * @param[in] pwmp      pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_start(PWMDriver *pwmp) {
+  uint16_t psc;
+  uint8_t i=0;
+
+  if (pwmp->state == PWM_STOP) {
+    /* Clock activation and timer reset.*/
+#if KINETIS_PWM_USE_FTM0
+    if (&PWMD1 == pwmp) {
+      SIM->SCGC6 |= SIM_SCGC6_FTM0;
+      nvicEnableVector(FTM0_IRQn, KINETIS_PWM_FTM0_PRIORITY);
+    }
+#endif
+
+#if KINETIS_PWM_USE_FTM1
+    if (&PWMD2 == pwmp) {
+      SIM->SCGC6 |= SIM_SCGC6_FTM1;
+      nvicEnableVector(FTM1_IRQn, KINETIS_PWM_FTM1_PRIORITY);
+    }
+#endif
+
+#if KINETIS_PWM_USE_FTM2
+    if (&PWMD3 == pwmp) {
+      SIM->SCGC3 |= SIM_SCGC3_FTM2;
+      nvicEnableVector(FTM2_IRQn, KINETIS_PWM_FTM2_PRIORITY);
+    }
+#endif
+  }
+  pwmp->ftm->MODE =  FTM_MODE_FTMEN_MASK|FTM_MODE_PWMSYNC_MASK;
+  pwmp->ftm->SYNC =  FTM_SYNC_CNTMIN_MASK|FTM_SYNC_CNTMAX_MASK
+                    |FTM_SYNC_SWSYNC_MASK;
+  pwmp->ftm->COMBINE =  FTM_COMBINE_SYNCEN3_MASK | FTM_COMBINE_SYNCEN2_MASK
+                      | FTM_COMBINE_SYNCEN1_MASK | FTM_COMBINE_SYNCEN0_MASK;
+  pwmp->ftm->SYNCONF =  FTM_SYNCONF_SYNCMODE_MASK;
+
+  pwmp->ftm->CNTIN = 0x0000;
+  //~ pwmp->ftm->SC = 0;       /* Disable FTM counter.*/
+  pwmp->ftm->CNT = 0x0000; /* Clear count register.*/
+
+  /* Prescaler value calculation.*/
+  psc = (KINETIS_SYSCLK_FREQUENCY / pwmp->config->frequency);
+  //~ /* Prescaler must be power of two between 1 and 128.*/
+  osalDbgAssert(psc <= 128 && !(psc & (psc - 1)), "invalid frequency");
+  //~ /* Prescaler register value determination.
+     //~ Prescaler register value conveniently corresponds to bit position,
+     //~ i.e., register value for prescaler CLK/64 is 6 ((1 << 6) == 64).*/
+  for (i = 0; i < 8; i++) {
+    if (psc == (unsigned)(1 << i)) {
+      break;
+    }
+  }
+
+  /* Set prescaler and clock mode.
+     This also sets the following:
+          CPWMS up-counting mode
+          Timer overflow interrupt disabled
+          DMA disabled.*/
+  pwmp->ftm->SC = FTM_SC_CLKS(1) | FTM_SC_PS(i);
+  /* Configure period */
+  pwmp->ftm->MOD = pwmp->period-1;
+  pwmp->ftm->PWMLOAD = FTM_PWMLOAD_LDOK_MASK;
+}
+
+/**
+ * @brief   Deactivates the PWM peripheral.
+ *
+ * @param[in] pwmp      pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_stop(PWMDriver *pwmp) {
+
+  /* If in ready state then disables the PWM clock.*/
+  if (pwmp->state == PWM_READY) {
+#if KINETIS_PWM_USE_FTM0
+    if (&PWMD1 == pwmp) {
+      SIM->SCGC6 &= ~SIM_SCGC6_FTM0;
+      nvicDisableVector(FTM0_IRQn);
+    }
+#endif
+
+#if KINETIS_PWM_USE_FTM1
+    if (&PWMD2 == pwmp) {
+      SIM->SCGC6 &= ~SIM_SCGC6_FTM1;
+      nvicDisableVector(FTM1_IRQn);
+    }
+#endif
+
+#if KINETIS_PWM_USE_FTM2
+    if (&PWMD3 == pwmp) {
+      SIM->SCGC3 &= ~SIM_SCGC3_FTM2;
+      nvicDisableVector(FTM2_IRQn);
+    }
+#endif
+    /* Disable FTM counter.*/
+    pwmp->ftm->SC = 0;
+    pwmp->ftm->MOD = 0;
+  }
+}
+
+/**
+ * @brief   Enables a PWM channel.
+ * @pre     The PWM unit must have been activated using @p pwmStart().
+ * @post    The channel is active using the specified configuration.
+ * @note    The function has effect at the next cycle start.
+ * @note    Channel notification is not enabled.
+ *
+ * @param[in] pwmp      pointer to a @p PWMDriver object
+ * @param[in] channel   PWM channel identifier (0...channels-1)
+ * @param[in] width     PWM pulse width as clock pulses number
+ *
+ * @notapi
+ */
+void pwm_lld_enable_channel(PWMDriver *pwmp,
+                            pwmchannel_t channel,
+                            pwmcnt_t width) {
+  uint32_t mode = FTM_CnSC_MSB; /* Edge-aligned PWM mode.*/
+
+  switch (pwmp->config->channels[channel].mode & PWM_OUTPUT_MASK) {
+  case PWM_OUTPUT_ACTIVE_HIGH:
+    mode |= FTM_CnSC_ELSB;
+    break;
+  case PWM_OUTPUT_ACTIVE_LOW:
+    mode |= FTM_CnSC_ELSA;
+    break;
+  }
+
+  if (pwmp->ftm->CHANNEL[channel].CnSC & FTM_CnSC_CHIE)
+    mode |= FTM_CnSC_CHIE;
+
+  pwmp->ftm->CHANNEL[channel].CnSC = mode;
+  pwmp->ftm->CHANNEL[channel].CnV = width;
+  pwmp->ftm->PWMLOAD = FTM_PWMLOAD_LDOK_MASK;
+}
+
+/**
+ * @brief   Disables a PWM channel and its notification.
+ * @pre     The PWM unit must have been activated using @p pwmStart().
+ * @post    The channel is disabled and its output line returned to the
+ *          idle state.
+ * @note    The function has effect at the next cycle start.
+ *
+ * @param[in] pwmp      pointer to a @p PWMDriver object
+ * @param[in] channel   PWM channel identifier (0...channels-1)
+ *
+ * @notapi
+ */
+void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) {
+
+  pwmp->ftm->CHANNEL[channel].CnSC = 0;
+  pwmp->ftm->CHANNEL[channel].CnV = 0;
+}
+
+/**
+ * @brief   Enables the periodic activation edge notification.
+ * @pre     The PWM unit must have been activated using @p pwmStart().
+ * @note    If the notification is already enabled then the call has no effect.
+ *
+ * @param[in] pwmp      pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) {
+  pwmp->ftm->SC |= FTM_SC_TOIE;
+}
+
+/**
+ * @brief   Disables the periodic activation edge notification.
+ * @pre     The PWM unit must have been activated using @p pwmStart().
+ * @note    If the notification is already disabled then the call has no effect.
+ *
+ * @param[in] pwmp      pointer to a @p PWMDriver object
+ *
+ * @notapi
+ */
+void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) {
+  pwmp->ftm->SC &= ~FTM_SC_TOIE;
+}
+
+/**
+ * @brief   Enables a channel de-activation edge notification.
+ * @pre     The PWM unit must have been activated using @p pwmStart().
+ * @pre     The channel must have been activated using @p pwmEnableChannel().
+ * @note    If the notification is already enabled then the call has no effect.
+ *
+ * @param[in] pwmp      pointer to a @p PWMDriver object
+ * @param[in] channel   PWM channel identifier (0...channels-1)
+ *
+ * @notapi
+ */
+void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
+                                         pwmchannel_t channel) {
+  pwmp->ftm->CHANNEL[channel].CnSC |= FTM_CnSC_CHIE;
+}
+
+/**
+ * @brief   Disables a channel de-activation edge notification.
+ * @pre     The PWM unit must have been activated using @p pwmStart().
+ * @pre     The channel must have been activated using @p pwmEnableChannel().
+ * @note    If the notification is already disabled then the call has no effect.
+ *
+ * @param[in] pwmp      pointer to a @p PWMDriver object
+ * @param[in] channel   PWM channel identifier (0...channels-1)
+ *
+ * @notapi
+ */
+void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
+                                          pwmchannel_t channel) {
+  pwmp->ftm->CHANNEL[channel].CnSC &= ~FTM_CnSC_CHIE;
+}
+
+#endif /* HAL_USE_PWM */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/MK66F18/hal_pwm_lld.h b/os/hal/ports/KINETIS/MK66F18/hal_pwm_lld.h
new file mode 100644
index 0000000..9332e34
--- /dev/null
+++ b/os/hal/ports/KINETIS/MK66F18/hal_pwm_lld.h
@@ -0,0 +1,270 @@
+/*
+    ChibiOS/HAL - Copyright (C) 2014 Adam J. Porter
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    MK66F18/pwm_lld.h
+ * @brief   KINETIS PWM subsystem low level driver header.
+ *
+ * @addtogroup PWM
+ * @{
+ */
+
+#ifndef HAL_PWM_LLD_H_
+#define HAL_PWM_LLD_H_
+
+#if HAL_USE_PWM || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Number of PWM channels per PWM driver.
+ */
+#define PWM_CHANNELS                            8
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+#if !defined(KINETIS_PWM_USE_FTM0)
+  #define KINETIS_PWM_USE_FTM0 FALSE
+#endif
+
+#if !defined(KINETIS_PWM_USE_FTM1)
+  #define KINETIS_PWM_USE_FTM1 FALSE
+#endif
+
+#if !defined(KINETIS_PWM_USE_FTM2)
+  #define KINETIS_PWM_USE_FTM2 FALSE
+#endif
+
+/**
+ * @brief   FTM0 interrupt priority level setting.
+ */
+#if !defined(KINETIS_PWM_FTM0_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_PWM_FTM0_PRIORITY        12
+#endif
+
+/**
+ * @brief   FTM1 interrupt priority level setting.
+ */
+#if !defined(KINETIS_PWM_FTM1_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_PWM_FTM1_PRIORITY        12
+#endif
+
+/**
+ * @brief   FTM2 interrupt priority level setting.
+ */
+#if !defined(KINETIS_PWM_FTM2_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_PWM_FTM2_PRIORITY        12
+#endif
+
+/** @} */
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   If advanced timer features switch.
+ * @details If set to @p TRUE the advanced features for TIM1 and TIM8 are
+ *          enabled.
+ * @note    The default is @p TRUE.
+ */
+#if !defined(KINETIS_PWM_USE_ADVANCED) || defined(__DOXYGEN__)
+#define KINETIS_PWM_USE_ADVANCED              FALSE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Configuration checks.                                                     */
+/*===========================================================================*/
+
+#if !KINETIS_PWM_USE_FTM0 && !KINETIS_PWM_USE_FTM1 && !KINETIS_PWM_USE_FTM2
+#error "PWM driver activated but no FTM peripheral assigned"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type of a PWM mode.
+ */
+typedef uint32_t pwmmode_t;
+
+/**
+ * @brief   Type of a PWM channel.
+ */
+typedef uint8_t pwmchannel_t;
+
+/**
+ * @brief   Type of a channels mask.
+ */
+typedef uint32_t pwmchnmsk_t;
+
+/**
+ * @brief   Type of a PWM counter.
+ */
+typedef uint16_t pwmcnt_t;
+
+/**
+ * @brief   Type of a PWM driver channel configuration structure.
+ */
+typedef struct {
+  /**
+   * @brief Channel active logic level.
+   */
+  pwmmode_t                 mode;
+
+  /**
+   * @brief Channel callback pointer.
+   * @note  This callback is invoked on the channel compare event. If set to
+   *        @p NULL then the callback is disabled.
+   */
+  pwmcallback_t             callback;
+  /* End of the mandatory fields.*/
+} PWMChannelConfig;
+
+/**
+ * @brief   Type of a PWM driver configuration structure.
+ */
+typedef struct {
+  /**
+   * @brief   Timer clock in Hz.
+   * @note    The low level can use assertions in order to catch invalid
+   *          frequency specifications.
+   */
+  uint32_t                  frequency;
+  /**
+   * @brief   PWM period in ticks.
+   * @note    The low level can use assertions in order to catch invalid
+   *          period specifications.
+   */
+  pwmcnt_t                  period;
+  /**
+   * @brief Periodic callback pointer.
+   * @note  This callback is invoked on PWM counter reset. If set to
+   *        @p NULL then the callback is disabled.
+   */
+  pwmcallback_t             callback;
+  /**
+   * @brief Channels configurations.
+   */
+  PWMChannelConfig          channels[PWM_CHANNELS];
+  /* End of the mandatory fields.*/
+} PWMConfig;
+
+/**
+ * @brief   Structure representing a PWM driver.
+ */
+struct PWMDriver {
+  /**
+   * @brief Driver state.
+   */
+  pwmstate_t                state;
+  /**
+   * @brief Current driver configuration data.
+   */
+  const PWMConfig           *config;
+  /**
+   * @brief   Current PWM period in ticks.
+   */
+  pwmcnt_t                  period;
+  /**
+   * @brief   Mask of the enabled channels.
+   */
+  pwmchnmsk_t               enabled;
+  /**
+   * @brief   Number of channels in this instance.
+   */
+  pwmchannel_t              channels;
+#if defined(PWM_DRIVER_EXT_FIELDS)
+  PWM_DRIVER_EXT_FIELDS
+#endif
+  /* End of the mandatory fields.*/
+  /**
+   * @brief Pointer to the FTM registers block.
+   */
+  FTM_TypeDef               *ftm;
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/**
+ * @brief   Changes the period the PWM peripheral.
+ * @details This function changes the period of a PWM unit that has already
+ *          been activated using @p pwmStart().
+ * @pre     The PWM unit must have been activated using @p pwmStart().
+ * @post    The PWM unit period is changed to the new value.
+ * @note    The function has effect at the next cycle start.
+ * @note    If a period is specified that is shorter than the pulse width
+ *          programmed in one of the channels then the behavior is not
+ *          guaranteed.
+ *
+ * @param[in] pwmp      pointer to a @p PWMDriver object
+ * @param[in] period    new cycle time in ticks
+ *
+ * @notapi
+ */
+#define pwm_lld_change_period(pwmp, period)                                 \
+  do { \
+    (pwmp)->ftm->MOD = ((period) - 1); \
+    pwmp->ftm->PWMLOAD = FTM_PWMLOAD_LDOK_MASK;\
+  } while(0)
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if KINETIS_PWM_USE_FTM0 || defined(__DOXYGEN__)
+extern PWMDriver PWMD1;
+#endif
+#if KINETIS_PWM_USE_FTM1 || defined(__DOXYGEN__)
+extern PWMDriver PWMD2;
+#endif
+#if KINETIS_PWM_USE_FTM2 || defined(__DOXYGEN__)
+extern PWMDriver PWMD3;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void pwm_lld_init(void);
+  void pwm_lld_start(PWMDriver *pwmp);
+  void pwm_lld_stop(PWMDriver *pwmp);
+  void pwm_lld_enable_channel(PWMDriver *pwmp,
+                              pwmchannel_t channel,
+                              pwmcnt_t width);
+  void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel);
+  void pwm_lld_enable_periodic_notification(PWMDriver *pwmp);
+  void pwm_lld_disable_periodic_notification(PWMDriver *pwmp);
+  void pwm_lld_enable_channel_notification(PWMDriver *pwmp,
+                                           pwmchannel_t channel);
+  void pwm_lld_disable_channel_notification(PWMDriver *pwmp,
+                                            pwmchannel_t channel);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_PWM */
+
+#endif /* HAL_PWM_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/MK66F18/hal_spi_lld.c b/os/hal/ports/KINETIS/MK66F18/hal_spi_lld.c
new file mode 100644
index 0000000..29ab4e8
--- /dev/null
+++ b/os/hal/ports/KINETIS/MK66F18/hal_spi_lld.c
@@ -0,0 +1,539 @@
+/*
+    ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    KINETIS/spi_lld.c
+ * @brief   KINETIS SPI subsystem low level driver source.
+ *
+ * @addtogroup SPI
+ * @{
+ */
+
+#include "hal.h"
+
+#if HAL_USE_SPI || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver local definitions.                                                 */
+/*===========================================================================*/
+
+#if !defined(KINETIS_SPI0_RX_DMA_IRQ_PRIORITY)
+#define KINETIS_SPI0_RX_DMA_IRQ_PRIORITY    8
+#endif
+
+#if !defined(KINETIS_SPI0_RX_DMAMUX_CHANNEL)
+#define KINETIS_SPI0_RX_DMAMUX_CHANNEL      0
+#endif
+
+#if !defined(KINETIS_SPI0_RX_DMA_CHANNEL)
+#define KINETIS_SPI0_RX_DMA_CHANNEL         0
+#endif
+
+#if !defined(KINETIS_SPI0_TX_DMAMUX_CHANNEL)
+#define KINETIS_SPI0_TX_DMAMUX_CHANNEL      1
+#endif
+
+#if !defined(KINETIS_SPI0_TX_DMA_CHANNEL)
+#define KINETIS_SPI0_TX_DMA_CHANNEL         1
+#endif
+
+#if !defined(KINETIS_SPI1_RX_DMA_IRQ_PRIORITY)
+#define KINETIS_SPI1_RX_DMA_IRQ_PRIORITY    8
+#endif
+
+#if !defined(KINETIS_SPI1_RX_DMAMUX_CHANNEL)
+#define KINETIS_SPI1_RX_DMAMUX_CHANNEL      0
+#endif
+
+#if !defined(KINETIS_SPI1_RX_DMA_CHANNEL)
+#define KINETIS_SPI1_RX_DMA_CHANNEL         0
+#endif
+
+#if !defined(KINETIS_SPI1_TX_DMAMUX_CHANNEL)
+#define KINETIS_SPI1_TX_DMAMUX_CHANNEL      1
+#endif
+
+#if !defined(KINETIS_SPI1_TX_DMA_CHANNEL)
+#define KINETIS_SPI1_TX_DMA_CHANNEL         1
+#endif
+
+#if KINETIS_SPI_USE_SPI0
+#define DMAMUX_SPI_RX_SOURCE    16
+#define DMAMUX_SPI_TX_SOURCE    17
+#endif
+
+#if KINETIS_SPI_USE_SPI1
+#define DMAMUX_SPI_RX_SOURCE    18
+#define DMAMUX_SPI_TX_SOURCE    19
+#endif
+
+/*===========================================================================*/
+/* Driver exported variables.                                                */
+/*===========================================================================*/
+
+/** @brief SPI0 driver identifier.*/
+#if KINETIS_SPI_USE_SPI0 || defined(__DOXYGEN__)
+SPIDriver SPID1;
+#endif
+
+/** @brief SPI1 driver identifier.*/
+#if KINETIS_SPI_USE_SPI1 || defined(__DOXYGEN__)
+SPIDriver SPID2;
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types.                                         */
+/*===========================================================================*/
+
+/* Use a dummy byte as the source/destination when a buffer is not provided */
+/* Note: The MMC driver relies on 0xFF being sent for dummy bytes. */
+static volatile uint16_t dmaRxDummy;
+static uint16_t dmaTxDummy = 0xFFFF;
+
+/*===========================================================================*/
+/* Driver local functions.                                                   */
+/*===========================================================================*/
+
+static void spi_start_xfer(SPIDriver *spip, bool polling)
+{
+  /*
+   * Enable the DSPI peripheral in master mode.
+   * Clear the TX and RX FIFOs.
+   * */
+  spip->spi->MCR = SPIx_MCR_MSTR | SPIx_MCR_CLR_TXF | SPIx_MCR_CLR_RXF;
+
+  /* If we are not polling then enable DMA */
+  if (!polling) {
+
+    /* Enable receive dma and transmit dma */
+    spip->spi->RSER = SPIx_RSER_RFDF_DIRS | SPIx_RSER_RFDF_RE |
+        SPIx_RSER_TFFF_RE | SPIx_RSER_TFFF_DIRS;
+
+    /* Configure RX DMA */
+    if (spip->rxbuf) {
+      DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DADDR = (uint32_t)spip->rxbuf;
+      DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DOFF = spip->word_size;
+    } else {
+      DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DADDR = (uint32_t)&dmaRxDummy;
+      DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DOFF = 0;
+    }
+    DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].BITER_ELINKNO = spip->count;
+    DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].CITER_ELINKNO = spip->count;
+
+    /* Enable Request Register (ERQ) for RX by writing 0 to SERQ */
+    DMA->SERQ = KINETIS_SPI0_RX_DMA_CHANNEL;
+
+    /* Configure TX DMA */
+    if (spip->txbuf) {
+      DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SADDR =  (uint32_t)spip->txbuf;
+      DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SOFF = spip->word_size;
+    } else {
+      DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SADDR =  (uint32_t)&dmaTxDummy;
+      DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SOFF = 0;
+    }
+    DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].BITER_ELINKNO = spip->count;
+    DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].CITER_ELINKNO = spip->count;
+
+    /* Enable Request Register (ERQ) for TX by writing 1 to SERQ */
+    DMA->SERQ = KINETIS_SPI0_TX_DMA_CHANNEL;
+  }
+}
+
+static void spi_stop_xfer(SPIDriver *spip)
+{
+  /* Halt the DSPI peripheral */
+  spip->spi->MCR = SPIx_MCR_MSTR | SPIx_MCR_HALT;
+
+  /* Clear all the flags which are currently set. */
+  spip->spi->SR |= spip->spi->SR;
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers.                                                */
+/*===========================================================================*/
+
+#if KINETIS_SPI_USE_SPI0 || defined(__DOXYGEN__)
+
+OSAL_IRQ_HANDLER(KINETIS_DMA0_IRQ_VECTOR) {
+  OSAL_IRQ_PROLOGUE();
+
+  /* Clear bit 0 in Interrupt Request Register (INT) by writing 0 to CINT */
+  DMA->CINT = KINETIS_SPI0_RX_DMA_CHANNEL;
+
+  spi_stop_xfer(&SPID1);
+
+  _spi_isr_code(&SPID1);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+#endif
+
+#if KINETIS_SPI_USE_SPI1 || defined(__DOXYGEN__)
+
+OSAL_IRQ_HANDLER(KINETIS_DMA0_IRQ_VECTOR) {
+  OSAL_IRQ_PROLOGUE();
+
+  /* Clear bit 0 in Interrupt Request Register (INT) by writing 0 to CINT */
+  DMA->CINT = KINETIS_SPI1_RX_DMA_CHANNEL;
+
+  spi_stop_xfer(&SPID2);
+
+  _spi_isr_code(&SPID2);
+
+  OSAL_IRQ_EPILOGUE();
+}
+
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions.                                                */
+/*===========================================================================*/
+
+/**
+ * @brief   Low level SPI driver initialization.
+ *
+ * @notapi
+ */
+void spi_lld_init(void) {
+#if KINETIS_SPI_USE_SPI0
+  spiObjectInit(&SPID1);
+#endif
+#if KINETIS_SPI_USE_SPI1
+  spiObjectInit(&SPID2);
+#endif
+}
+
+/**
+ * @brief   Configures and activates the SPI peripheral.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ *
+ * @notapi
+ */
+void spi_lld_start(SPIDriver *spip) {
+
+  /* If in stopped state then enables the SPI and DMA clocks.*/
+  if (spip->state == SPI_STOP) {
+
+#if KINETIS_SPI_USE_SPI0
+    if (&SPID1 == spip) {
+
+      /* Enable the clock for SPI0 */
+      SIM->SCGC6 |= SIM_SCGC6_SPI0;
+
+      SPID1.spi = SPI0;
+
+      if (spip->config->tar0) {
+        spip->spi->CTAR[0] = spip->config->tar0;
+      } else {
+        spip->spi->CTAR[0] = KINETIS_SPI_TAR0_DEFAULT;
+      }
+    }
+#endif
+
+#if KINETIS_SPI_USE_SPI1
+    if (&SPID2 == spip) {
+
+      /* Enable the clock for SPI0 */
+      SIM->SCGC6 |= SIM_SCGC6_SPI1;
+
+      SPID2.spi = SPI1;
+
+      if (spip->config->tar0) {
+        spip->spi->CTAR[0] = spip->config->tar0;
+      } else {
+        spip->spi->CTAR[0] = KINETIS_SPI_TAR0_DEFAULT;
+      }
+    }
+#endif
+
+    nvicEnableVector(DMA0_IRQn, KINETIS_SPI0_RX_DMA_IRQ_PRIORITY);
+
+    SIM->SCGC6 |= SIM_SCGC6_DMAMUX;
+    SIM->SCGC7 |= SIM_SCGC7_DMA;
+
+    /* Clear DMA error flags */
+    DMA->ERR = 0x0F;
+
+#if KINETIS_SPI_USE_SPI0
+    /* Rx, select SPI Rx FIFO */
+    DMAMUX->CHCFG[KINETIS_SPI0_RX_DMAMUX_CHANNEL] = DMAMUX_CHCFGn_ENBL |
+        DMAMUX_CHCFGn_SOURCE(DMAMUX_SPI_RX_SOURCE);
+
+    /* Tx, select SPI Tx FIFO */
+    DMAMUX->CHCFG[KINETIS_SPI0_TX_DMAMUX_CHANNEL] = DMAMUX_CHCFGn_ENBL |
+        DMAMUX_CHCFGn_SOURCE(DMAMUX_SPI_TX_SOURCE);
+
+    /* Extract the frame size from the TAR */
+    uint16_t frame_size = ((spip->spi->CTAR[0] >> SPIx_CTARn_FMSZ_SHIFT) &
+        SPIx_CTARn_FMSZ_MASK) + 1;
+
+    /* DMA transfer size is 16 bits for a frame size > 8 bits */
+    uint16_t dma_size = frame_size > 8 ? 1 : 0;
+
+    /* DMA word size is 2 for a 16 bit frame size */
+    spip->word_size = frame_size > 8 ? 2 : 1;
+
+    /* configure DMA RX fixed values */
+    DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].SADDR = (uint32_t)&SPI0->POPR;
+    DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].SOFF = 0;
+    DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].SLAST = 0;
+    DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].DLASTSGA = 0;
+    DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].ATTR = DMA_ATTR_SSIZE(dma_size) |
+        DMA_ATTR_DSIZE(dma_size);
+    DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].NBYTES_MLNO = spip->word_size;
+    DMA->TCD[KINETIS_SPI0_RX_DMA_CHANNEL].CSR = DMA_CSR_DREQ_MASK |
+        DMA_CSR_INTMAJOR_MASK;
+
+    /* configure DMA TX fixed values */
+    DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].SLAST = 0;
+    DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].DADDR = (uint32_t)&SPI0->PUSHR;
+    DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].DOFF = 0;
+    DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].DLASTSGA = 0;
+    DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].ATTR = DMA_ATTR_SSIZE(dma_size) |
+        DMA_ATTR_DSIZE(dma_size);
+    DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].NBYTES_MLNO = spip->word_size;
+    DMA->TCD[KINETIS_SPI0_TX_DMA_CHANNEL].CSR = DMA_CSR_DREQ_MASK;
+#endif
+
+#if KINETIS_SPI_USE_SPI1
+    /* Rx, select SPI Rx FIFO */
+    DMAMUX->CHCFG[KINETIS_SPI1_RX_DMAMUX_CHANNEL] = DMAMUX_CHCFGn_ENBL |
+        DMAMUX_CHCFGn_SOURCE(DMAMUX_SPI_RX_SOURCE);
+
+    /* Tx, select SPI Tx FIFO */
+    DMAMUX->CHCFG[KINETIS_SPI1_TX_DMAMUX_CHANNEL] = DMAMUX_CHCFGn_ENBL |
+        DMAMUX_CHCFGn_SOURCE(DMAMUX_SPI_TX_SOURCE);
+
+    /* Extract the frame size from the TAR */
+    uint16_t frame_size = ((spip->spi->CTAR[0] >> SPIx_CTARn_FMSZ_SHIFT) &
+        SPIx_CTARn_FMSZ_MASK) + 1;
+
+    /* DMA transfer size is 16 bits for a frame size > 8 bits */
+    uint16_t dma_size = frame_size > 8 ? 1 : 0;
+
+    /* DMA word size is 2 for a 16 bit frame size */
+    spip->word_size = frame_size > 8 ? 2 : 1;
+
+    /* configure DMA RX fixed values */
+    DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].SADDR = (uint32_t)&SPI1->POPR;
+    DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].SOFF = 0;
+    DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].SLAST = 0;
+    DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].DLASTSGA = 0;
+    DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].ATTR = DMA_ATTR_SSIZE(dma_size) |
+        DMA_ATTR_DSIZE(dma_size);
+    DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].NBYTES_MLNO = spip->word_size;
+    DMA->TCD[KINETIS_SPI1_RX_DMA_CHANNEL].CSR = DMA_CSR_DREQ_MASK |
+        DMA_CSR_INTMAJOR_MASK;
+
+    /* configure DMA TX fixed values */
+    DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].SLAST = 0;
+    DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].DADDR = (uint32_t)&SPI1->PUSHR;
+    DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].DOFF = 0;
+    DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].DLASTSGA = 0;
+    DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].ATTR = DMA_ATTR_SSIZE(dma_size) |
+        DMA_ATTR_DSIZE(dma_size);
+    DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].NBYTES_MLNO = spip->word_size;
+    DMA->TCD[KINETIS_SPI1_TX_DMA_CHANNEL].CSR = DMA_CSR_DREQ_MASK;
+#endif
+  }
+}
+
+/**
+ * @brief   Deactivates the SPI peripheral.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ *
+ * @notapi
+ */
+void spi_lld_stop(SPIDriver *spip) {
+
+  /* If in ready state then disables the SPI clock.*/
+  if (spip->state == SPI_READY) {
+
+    nvicDisableVector(DMA0_IRQn);
+
+    SIM->SCGC7 &= ~SIM_SCGC7_DMA;
+    SIM->SCGC6 &= ~SIM_SCGC6_DMAMUX;
+
+#if KINETIS_SPI_USE_SPI0
+    if (&SPID1 == spip) {
+      /* SPI halt.*/
+      spip->spi->MCR |= SPIx_MCR_HALT;
+    }
+
+    /* Disable the clock for SPI0 */
+    SIM->SCGC6 &= ~SIM_SCGC6_SPI0;
+#endif
+
+#if KINETIS_SPI_USE_SPI1
+    if (&SPID2 == spip) {
+      /* SPI halt.*/
+      spip->spi->MCR |= SPIx_MCR_HALT;
+    }
+
+    /* Disable the clock for SPI1 */
+    SIM->SCGC6 &= ~SIM_SCGC6_SPI1;
+#endif
+  }
+}
+
+/**
+ * @brief   Asserts the slave select signal and prepares for transfers.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ *
+ * @notapi
+ */
+void spi_lld_select(SPIDriver *spip) {
+
+  palClearPad(spip->config->ssport, spip->config->sspad);
+}
+
+/**
+ * @brief   Deasserts the slave select signal.
+ * @details The previously selected peripheral is unselected.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ *
+ * @notapi
+ */
+void spi_lld_unselect(SPIDriver *spip) {
+
+  palSetPad(spip->config->ssport, spip->config->sspad);
+}
+
+/**
+ * @brief   Ignores data on the SPI bus.
+ * @details This asynchronous function starts the transmission of a series of
+ *          idle words on the SPI bus and ignores the received data.
+ * @post    At the end of the operation the configured callback is invoked.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ * @param[in] n         number of words to be ignored
+ *
+ * @notapi
+ */
+void spi_lld_ignore(SPIDriver *spip, size_t n) {
+
+  spip->count = n;
+  spip->rxbuf = NULL;
+  spip->txbuf = NULL;
+
+  spi_start_xfer(spip, false);
+}
+
+/**
+ * @brief   Exchanges data on the SPI bus.
+ * @details This asynchronous function starts a simultaneous transmit/receive
+ *          operation.
+ * @post    At the end of the operation the configured callback is invoked.
+ * @note    The buffers are organized as uint8_t arrays for data sizes below or
+ *          equal to 8 bits else it is organized as uint16_t arrays.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ * @param[in] n         number of words to be exchanged
+ * @param[in] txbuf     the pointer to the transmit buffer
+ * @param[out] rxbuf    the pointer to the receive buffer
+ *
+ * @notapi
+ */
+void spi_lld_exchange(SPIDriver *spip, size_t n,
+                      const void *txbuf, void *rxbuf) {
+
+  spip->count = n;
+  spip->rxbuf = rxbuf;
+  spip->txbuf = txbuf;
+
+  spi_start_xfer(spip, false);
+}
+
+/**
+ * @brief   Sends data over the SPI bus.
+ * @details This asynchronous function starts a transmit operation.
+ * @post    At the end of the operation the configured callback is invoked.
+ * @note    The buffers are organized as uint8_t arrays for data sizes below or
+ *          equal to 8 bits else it is organized as uint16_t arrays.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ * @param[in] n         number of words to send
+ * @param[in] txbuf     the pointer to the transmit buffer
+ *
+ * @notapi
+ */
+void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) {
+
+  spip->count = n;
+  spip->rxbuf = NULL;
+  spip->txbuf = (void *)txbuf;
+
+  spi_start_xfer(spip, false);
+}
+
+/**
+ * @brief   Receives data from the SPI bus.
+ * @details This asynchronous function starts a receive operation.
+ * @post    At the end of the operation the configured callback is invoked.
+ * @note    The buffers are organized as uint8_t arrays for data sizes below or
+ *          equal to 8 bits else it is organized as uint16_t arrays.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ * @param[in] n         number of words to receive
+ * @param[out] rxbuf    the pointer to the receive buffer
+ *
+ * @notapi
+ */
+void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) {
+
+  spip->count = n;
+  spip->rxbuf = rxbuf;
+  spip->txbuf = NULL;
+
+  spi_start_xfer(spip, false);
+}
+
+/**
+ * @brief   Exchanges one frame using a polled wait.
+ * @details This synchronous function exchanges one frame using a polled
+ *          synchronization method. This function is useful when exchanging
+ *          small amount of data on high speed channels, usually in this
+ *          situation is much more efficient just wait for completion using
+ *          polling than suspending the thread waiting for an interrupt.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object
+ * @param[in] frame     the data frame to send over the SPI bus
+ * @return              The received data frame from the SPI bus.
+ */
+uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) {
+
+  spi_start_xfer(spip, true);
+
+  spip->spi->PUSHR = SPIx_PUSHR_TXDATA(frame);
+
+  while ((spip->spi->SR & SPIx_SR_RFDF) == 0)
+    ;
+
+  frame = spip->spi->POPR;
+
+  spi_stop_xfer(spip);
+
+  return frame;
+}
+
+#endif /* HAL_USE_SPI */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/MK66F18/hal_spi_lld.h b/os/hal/ports/KINETIS/MK66F18/hal_spi_lld.h
new file mode 100644
index 0000000..0cf108e
--- /dev/null
+++ b/os/hal/ports/KINETIS/MK66F18/hal_spi_lld.h
@@ -0,0 +1,261 @@
+/*
+    ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    KINETIS/spi_lld.h
+ * @brief   KINETIS SPI subsystem low level driver header.
+ *
+ * @addtogroup SPI
+ * @{
+ */
+
+#ifndef HAL_SPI_LLD_H_
+#define HAL_SPI_LLD_H_
+
+#if HAL_USE_SPI || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants.                                                         */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver pre-compile time settings.                                         */
+/*===========================================================================*/
+
+/**
+ * @name    Configuration options
+ * @{
+ */
+/**
+ * @brief   SPI0 driver enable switch.
+ * @details If set to @p TRUE the support for SPI0 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(KINETIS_SPI_USE_SPI0) || defined(__DOXYGEN__)
+#define KINETIS_SPI_USE_SPI0                  FALSE
+#endif
+
+/**
+ * @brief   SPI0 interrupt priority level setting.
+ */
+#if !defined(KINETIS_SPI_SPI0_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_SPI_SPI0_IRQ_PRIORITY         10
+#endif
+
+/**
+ * @brief   SPI1 driver enable switch.
+ * @details If set to @p TRUE the support for SPI0 is included.
+ * @note    The default is @p FALSE.
+ */
+#if !defined(KINETIS_SPI_USE_SPI1) || defined(__DOXYGEN__)
+#define KINETIS_SPI_USE_SPI1                  FALSE
+#endif
+
+/**
+ * @brief   SPI1 interrupt priority level setting.
+ */
+#if !defined(KINETIS_SPI_SPI1_IRQ_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_SPI_SPI1_IRQ_PRIORITY         10
+#endif
+
+/*===========================================================================*/
+/* Derived constants and error checks.                                       */
+/*===========================================================================*/
+
+#if KINETIS_SPI_USE_SPI0 && !KINETIS_HAS_SPI0
+#error "SPI0 not present in the selected device"
+#endif
+
+#if KINETIS_SPI_USE_SPI1 && !KINETIS_HAS_SPI1
+#error "SPI1 not present in the selected device"
+#endif
+
+#if KINETIS_SPI_USE_SPI0 && KINETIS_SPI_USE_SPI1
+#error "Only one SPI peripheral can be enabled"
+#endif
+
+#if !(KINETIS_SPI_USE_SPI0 || KINETIS_SPI_USE_SPI1)
+#error "SPI driver activated but no SPI peripheral assigned"
+#endif
+
+#if KINETIS_SPI_USE_SPI0 &&                                                 \
+    !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_SPI_SPI0_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SPI0"
+#endif
+
+#if KINETIS_SPI_USE_SPI1 &&                                                 \
+    !OSAL_IRQ_IS_VALID_PRIORITY(KINETIS_SPI_SPI1_IRQ_PRIORITY)
+#error "Invalid IRQ priority assigned to SPI1"
+#endif
+
+/*===========================================================================*/
+/* Driver data structures and types.                                         */
+/*===========================================================================*/
+
+/**
+ * @brief   Type of a structure representing an SPI driver.
+ */
+typedef struct SPIDriver SPIDriver;
+
+/**
+ * @brief   SPI notification callback type.
+ *
+ * @param[in] spip      pointer to the @p SPIDriver object triggering the
+ *                      callback
+ */
+typedef void (*spicallback_t)(SPIDriver *spip);
+
+/**
+ * @brief   Driver configuration structure.
+ */
+typedef struct {
+  /**
+   * @brief Operation complete callback or @p NULL.
+   */
+  spicallback_t             end_cb;
+  /* End of the mandatory fields.*/
+  /**
+   * @brief The chip select line port - when not using pcs.
+   */
+  ioportid_t                ssport;
+  /**
+   * @brief The chip select line pad number - when not using pcs.
+   */
+  uint16_t                  sspad;
+  /**
+   * @brief SPI initialization data.
+   */
+  uint32_t                  tar0;
+} SPIConfig;
+
+/**
+ * @brief   Structure representing a SPI driver.
+ */
+struct SPIDriver {
+  /**
+   * @brief Driver state.
+   */
+  spistate_t                state;
+  /**
+   * @brief Current configuration data.
+   */
+  const SPIConfig           *config;
+#if SPI_USE_WAIT || defined(__DOXYGEN__)
+  /**
+   * @brief Waiting thread.
+   */
+  thread_reference_t        thread;
+#endif /* SPI_USE_WAIT */
+#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__)
+  /**
+   * @brief Mutex protecting the bus.
+   */
+  mutex_t                   mutex;
+#endif /* SPI_USE_MUTUAL_EXCLUSION */
+#if defined(SPI_DRIVER_EXT_FIELDS)
+  SPI_DRIVER_EXT_FIELDS
+#endif
+  /* End of the mandatory fields.*/
+  /**
+   * @brief Pointer to the SPIx registers block.
+   */
+  SPI_TypeDef               *spi;
+  /**
+   * @brief   Number of bytes/words of data to transfer.
+   */
+  size_t                    count;
+  /**
+   * @brief   Word size in bytes.
+   */
+  size_t                    word_size;
+  /**
+   * @brief   Pointer to the buffer with data to send.
+   */
+  const uint8_t             *txbuf;
+  /**
+   * @brief   Pointer to the buffer to put received data.
+   */
+  uint8_t                   *rxbuf;
+};
+
+/*===========================================================================*/
+/* Driver macros.                                                            */
+/*===========================================================================*/
+
+/* TAR settings for n bits at SYSCLK / 2 */
+#define KINETIS_SPI_TAR_SYSCLK_DIV_2(n)\
+    SPIx_CTARn_FMSZ((n) - 1) | \
+    SPIx_CTARn_CPOL | \
+    SPIx_CTARn_CPHA | \
+    SPIx_CTARn_DBR | \
+    SPIx_CTARn_PBR(0) | \
+    SPIx_CTARn_BR(0) | \
+    SPIx_CTARn_CSSCK(0) | \
+    SPIx_CTARn_ASC(0) | \
+    SPIx_CTARn_DT(0)
+
+/* TAR settings for n bits at SYSCLK / 4096 for debugging */
+#define KINETIS_SPI_TAR_SYSCLK_DIV_4096(n) \
+    SPIx_CTARn_FMSZ(((n) - 1)) | \
+    SPIx_CTARn_CPOL | \
+    SPIx_CTARn_CPHA | \
+    SPIx_CTARn_PBR(0) | \
+    SPIx_CTARn_BR(0xB) | \
+    SPIx_CTARn_CSSCK(0xB) | \
+    SPIx_CTARn_ASC(0x7) | \
+    SPIx_CTARn_DT(0xB)
+
+#define KINETIS_SPI_TAR_8BIT_FAST   KINETIS_SPI_TAR_SYSCLK_DIV_2(8)
+#define KINETIS_SPI_TAR_8BIT_SLOW   KINETIS_SPI_TAR_SYSCLK_DIV_4096(8)
+
+#define KINETIS_SPI_TAR0_DEFAULT    KINETIS_SPI_TAR_SYSCLK_DIV_2(8)
+#define KINETIS_SPI_TAR1_DEFAULT    KINETIS_SPI_TAR_SYSCLK_DIV_2(8)
+
+/*===========================================================================*/
+/* External declarations.                                                    */
+/*===========================================================================*/
+
+#if KINETIS_SPI_USE_SPI0 && !defined(__DOXYGEN__)
+extern SPIDriver SPID1;
+#endif
+
+#if KINETIS_SPI_USE_SPI1 && !defined(__DOXYGEN__)
+extern SPIDriver SPID2;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void spi_lld_init(void);
+  void spi_lld_start(SPIDriver *spip);
+  void spi_lld_stop(SPIDriver *spip);
+  void spi_lld_select(SPIDriver *spip);
+  void spi_lld_unselect(SPIDriver *spip);
+  void spi_lld_ignore(SPIDriver *spip, size_t n);
+  void spi_lld_exchange(SPIDriver *spip, size_t n,
+                        const void *txbuf, void *rxbuf);
+  void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf);
+  void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf);
+  uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_SPI */
+
+#endif /* HAL_SPI_LLD_H_ */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/MK66F18/kinetis_registry.h b/os/hal/ports/KINETIS/MK66F18/kinetis_registry.h
new file mode 100644
index 0000000..f733244
--- /dev/null
+++ b/os/hal/ports/KINETIS/MK66F18/kinetis_registry.h
@@ -0,0 +1,165 @@
+/*
+    ChibiOS - Copyright (C) 2014 Derek Mulcahy
+                        (C) 2016 flabbergast <s3+flabbergast@sdfeu.org>
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/**
+ * @file    MK66F18/kinetis_registry.h
+ * @brief   MK66F18 capabilities registry.
+ *
+ * @addtogroup HAL
+ * @{
+ */
+
+#ifndef KINETIS_REGISTRY_H_
+#define KINETIS_REGISTRY_H_
+
+#if !defined(MK66F18) || defined(__DOXYGEN__)
+#define MK66F18 
+#endif
+
+/*===========================================================================*/
+/* Platform capabilities.                                                    */
+/*===========================================================================*/
+
+/**
+ * @brief   Maximum system and core clock (f_SYS) frequency.
+ */
+#define KINETIS_SYSCLK_MAX      180000000L
+
+/**
+ * @brief   Maximum bus clock (f_BUS) frequency.
+ */
+#define KINETIS_BUSCLK_MAX      60000000L
+
+/**
+ * @brief   Maximum flash clock (f_FLASH) frequency.
+ */
+#define KINETIS_FLASHCLK_MAX    28000000L
+
+/* ADC attributes.*/
+#define KINETIS_HAS_ADC0            TRUE
+#define KINETIS_ADC0_IRQ_VECTOR     VectorDC
+#define KINETIS_HAS_ADC1            TRUE
+#define KINETIS_ADC1_IRQ_VECTOR     Vector164
+
+/* DAC attributes.*/
+#define KINETIS_HAS_DAC0            TRUE
+#define KINETIS_DAC0_IRQ_VECTOR     Vector120
+#define KINETIS_HAS_DAC1            TRUE
+#define KINETIS_DAC1_IRQ_VECTOR     Vector160
+
+/* DMA attributes.*/
+#define KINETIS_DMA0_IRQ_VECTOR     Vector40
+#define KINETIS_DMA1_IRQ_VECTOR     Vector44
+#define KINETIS_DMA2_IRQ_VECTOR     Vector48
+#define KINETIS_DMA3_IRQ_VECTOR     Vector4C
+#define KINETIS_DMA4_IRQ_VECTOR     Vector50
+#define KINETIS_DMA5_IRQ_VECTOR     Vector54
+#define KINETIS_DMA6_IRQ_VECTOR     Vector58
+#define KINETIS_DMA7_IRQ_VECTOR     Vector5C
+#define KINETIS_DMA8_IRQ_VECTOR     Vector60
+#define KINETIS_DMA9_IRQ_VECTOR     Vector64
+#define KINETIS_DMA10_IRQ_VECTOR     Vector68
+#define KINETIS_DMA11_IRQ_VECTOR     Vector6C
+#define KINETIS_DMA12_IRQ_VECTOR     Vector70
+#define KINETIS_DMA13_IRQ_VECTOR     Vector74
+#define KINETIS_DMA14_IRQ_VECTOR     Vector78
+#define KINETIS_DMA15_IRQ_VECTOR     Vector7C
+#define KINETIS_HAS_DMA_ERROR_IRQ   TRUE
+#define KINETIS_DMA_ERROR_IRQ_VECTOR Vector80
+
+/* EXT attributes.*/
+#define KINETIS_PORTA_IRQ_VECTOR    Vector12C
+#define KINETIS_PORTB_IRQ_VECTOR    Vector130
+#define KINETIS_PORTC_IRQ_VECTOR    Vector134
+#define KINETIS_PORTD_IRQ_VECTOR    Vector138
+#define KINETIS_PORTE_IRQ_VECTOR    Vector13C
+#define KINETIS_EXT_HAS_COMMON_CD_IRQ   FALSE
+#define KINETIS_EXT_HAS_COMMON_BCDE_IRQ FALSE
+#define KINETIS_GPIO_HAS_OPENDRAIN  TRUE
+
+/* I2C attributes.*/
+#define KINETIS_HAS_I2C0            TRUE
+#define KINETIS_I2C0_IRQ_VECTOR     VectorA0
+#define KINETIS_HAS_I2C1            TRUE
+#define KINETIS_I2C1_IRQ_VECTOR     VectorA4
+
+/* Serial attributes.*/
+#define KINETIS_HAS_SERIAL0         TRUE
+#define KINETIS_SERIAL0_IRQ_VECTOR  VectorBC
+#define KINETIS_HAS_SERIAL1         TRUE
+#define KINETIS_SERIAL1_IRQ_VECTOR  VectorC4
+#define KINETIS_HAS_SERIAL2         TRUE
+#define KINETIS_SERIAL2_IRQ_VECTOR  VectorCC
+#define KINETIS_HAS_SERIAL3         TRUE
+#define KINETIS_SERIAL3_IRQ_VECTOR  VectorD4
+#define KINETIS_HAS_SERIAL_ERROR_IRQ TRUE
+#define KINETIS_SERIAL0_ERROR_IRQ_VECTOR VectorC0
+#define KINETIS_SERIAL1_ERROR_IRQ_VECTOR VectorC8
+#define KINETIS_SERIAL2_ERROR_IRQ_VECTOR VectorD0
+#define KINETIS_SERIAL3_ERROR_IRQ_VECTOR VectorD8
+#define KINETIS_SERIAL0_IS_LPUART   FALSE
+#define KINETIS_SERIAL0_IS_UARTLP   FALSE
+#define KINETIS_SERIAL1_IS_LPUART   FALSE
+#define KINETIS_SERIAL1_IS_UARTLP   FALSE
+#define KINETIS_SERIAL2_IS_LPUART   FALSE
+#define KINETIS_SERIAL2_IS_UARTLP   FALSE
+#define KINETIS_SERIAL3_IS_LPUART   FALSE
+#define KINETIS_SERIAL3_IS_UARTLP   FALSE
+
+/* SPI attributes.*/
+#define KINETIS_HAS_SPI0            TRUE
+#define KINETIS_SPI0_IRQ_VECTOR     VectorA8
+#define KINETIS_HAS_SPI1            TRUE
+#define KINETIS_SPI1_IRQ_VECTOR     VectorAC
+
+/* FlexTimer attributes.*/
+#define KINETIS_FTM0_CHANNELS 8
+#define KINETIS_FTM1_CHANNELS 2
+#define KINETIS_FTM2_CHANNELS 2
+#define KINETIS_FTM3_CHANNELS 8
+
+#define KINETIS_HAS_FTM0            TRUE
+#define KINETIS_FTM0_IRQ_VECTOR     VectorE8
+#define KINETIS_HAS_FTM1            TRUE
+#define KINETIS_FTM1_IRQ_VECTOR     VectorEC
+#define KINETIS_HAS_FTM2            TRUE
+#define KINETIS_FTM2_IRQ_VECTOR     VectorF0
+#define KINETIS_HAS_FTM3            TRUE
+#define KINETIS_FTM3_IRQ_VECTOR     Vector15C
+
+/* GPT attributes.*/
+#define KINETIS_HAS_PIT0            TRUE
+#define KINETIS_PIT0_IRQ_VECTOR     Vector100
+#define KINETIS_HAS_PIT1            TRUE
+#define KINETIS_PIT1_IRQ_VECTOR     Vector104
+#define KINETIS_HAS_PIT2            TRUE
+#define KINETIS_PIT2_IRQ_VECTOR     Vector108
+#define KINETIS_HAS_PIT3            TRUE
+#define KINETIS_PIT3_IRQ_VECTOR     Vector10C
+#define KINETIS_HAS_PIT_COMMON_IRQ  FALSE
+
+/* USB attributes.*/
+#define KINETIS_HAS_USB             TRUE
+#define KINETIS_USB_IRQ_VECTOR      Vector114
+#define KINETIS_USB0_IS_USBOTG      TRUE
+#define KINETIS_HAS_USB_CLOCK_RECOVERY TRUE
+
+/** @} */
+
+#endif /* KINETIS_REGISTRY_H_ */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/MK66F18/platform.dox b/os/hal/ports/KINETIS/MK66F18/platform.dox
new file mode 100644
index 0000000..beb8f61
--- /dev/null
+++ b/os/hal/ports/KINETIS/MK66F18/platform.dox
@@ -0,0 +1,365 @@
+/*
+    ChibiOS - Copyright (C) 2014-2015 Fabio Utzig
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+/* TODO Still need to edit this entire file */
+
+/**
+ * @defgroup MK66FX1M0_DRIVERS MK66FX1M0 Drivers
+ * @details This section describes all the supported drivers on the MK66FX1M0
+ *          platform and the implementation details of the single drivers.
+ *
+ * @ingroup platforms
+ */
+
+/**
+ * @defgroup MK66FX1M0_HAL MK66FX1M0 Initialization Support
+ * @details The MK66FX1M0 HAL support is responsible for system initialization.
+ *
+ * @section mk66fx1m0_hal_1 Supported HW resources
+ * - PLL1.
+ * - PLL2.
+ * - RCC.
+ * - Flash.
+ * .
+ * @section mk66fx1m0_hal_2 MK66FX1M0 HAL driver implementation features
+ * - PLL startup and stabilization.
+ * - Clock tree initialization.
+ * - Clock source selection.
+ * - Flash wait states initialization based on the selected clock options.
+ * - SYSTICK initialization based on current clock and kernel required rate.
+ * - DMA support initialization.
+ * .
+ * @ingroup MK66FX1M0_DRIVERS
+ */
+
+/**
+ * @defgroup MK66FX1M0_ADC MK66FX1M0 ADC Support
+ * @details The MK66FX1M0 ADC driver supports the ADC peripherals using DMA
+ *          channels for maximum performance.
+ *
+ * @section mk66fx1m0_adc_1 Supported HW resources
+ * - ADC1.
+ * - ADC2.
+ * - ADC3.
+ * - DMA2.
+ * .
+ * @section mk66fx1m0_adc_2 MK66FX1M0 ADC driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Streaming conversion using DMA for maximum performance.
+ * - Programmable ADC interrupt priority level.
+ * - Programmable DMA bus priority for each DMA channel.
+ * - Programmable DMA interrupt priority for each DMA channel.
+ * - DMA and ADC errors detection.
+ * .
+ * @ingroup MK66FX1M0_DRIVERS
+ */
+
+/**
+ * @defgroup MK66FX1M0_CAN MK66FX1M0 CAN Support
+ * @details The MK66FX1M0 CAN driver uses the CAN peripherals.
+ *
+ * @section mk66fx1m0_can_1 Supported HW resources
+ * - bxCAN1.
+ * .
+ * @section mk66fx1m0_can_2 MK66FX1M0 CAN driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Support for bxCAN sleep mode.
+ * - Programmable bxCAN interrupts priority level.
+ * .
+ * @ingroup MK66FX1M0_DRIVERS
+ */
+
+/**
+ * @defgroup MK66FX1M0_EXT MK66FX1M0 EXT Support
+ * @details The MK66FX1M0 EXT driver uses the EXTI peripheral.
+ *
+ * @section mk66fx1m0_ext_1 Supported HW resources
+ * - EXTI.
+ * .
+ * @section mk66fx1m0_ext_2 MK66FX1M0 EXT driver implementation features
+ * - Each EXTI channel can be independently enabled and programmed.
+ * - Programmable EXTI interrupts priority level.
+ * - Capability to work as event sources (WFE) rather than interrupt sources.
+ * .
+ * @ingroup MK66FX1M0_DRIVERS
+ */
+
+/**
+ * @defgroup MK66FX1M0_GPT MK66FX1M0 GPT Support
+ * @details The MK66FX1M0 GPT driver uses the TIMx peripherals.
+ *
+ * @section mk66fx1m0_gpt_1 Supported HW resources
+ * - TIM1.
+ * - TIM2.
+ * - TIM3.
+ * - TIM4.
+ * - TIM5.
+ * - TIM8.
+ * .
+ * @section mk66fx1m0_gpt_2 MK66FX1M0 GPT driver implementation features
+ * - Each timer can be independently enabled and programmed. Unused
+ *   peripherals are left in low power mode.
+ * - Programmable TIMx interrupts priority level.
+ * .
+ * @ingroup MK66FX1M0_DRIVERS
+ */
+
+/**
+ * @defgroup MK66FX1M0_ICU MK66FX1M0 ICU Support
+ * @details The MK66FX1M0 ICU driver uses the TIMx peripherals.
+ *
+ * @section mk66fx1m0_icu_1 Supported HW resources
+ * - TIM1.
+ * - TIM2.
+ * - TIM3.
+ * - TIM4.
+ * - TIM5.
+ * - TIM8.
+ * .
+ * @section mk66fx1m0_icu_2 MK66FX1M0 ICU driver implementation features
+ * - Each timer can be independently enabled and programmed. Unused
+ *   peripherals are left in low power mode.
+ * - Programmable TIMx interrupts priority level.
+ * .
+ * @ingroup MK66FX1M0_DRIVERS
+ */
+
+/**
+ * @defgroup MK66FX1M0_MAC MK66FX1M0 MAC Support
+ * @details The MK66FX1M0 MAC driver supports the ETH peripheral.
+ *
+ * @section mk66fx1m0_mac_1 Supported HW resources
+ * - ETH.
+ * - PHY (external).
+ * .
+ * @section mk66fx1m0_mac_2 MK66FX1M0 MAC driver implementation features
+ * - Dedicated DMA operations.
+ * - Support for checksum off-loading.
+ * .
+ * @ingroup MK66FX1M0_DRIVERS
+ */
+
+/**
+ * @defgroup MK66FX1M0_PAL MK66FX1M0 PAL Support
+ * @details The MK66FX1M0 PAL driver uses the GPIO peripherals.
+ *
+ * @section mk66fx1m0_pal_1 Supported HW resources
+ * - GPIOA.
+ * - GPIOB.
+ * - GPIOC.
+ * - GPIOD.
+ * - GPIOE.
+ * - GPIOF.
+ * - GPIOG.
+ * - GPIOH.
+ * - GPIOI.
+ * .
+ * @section mk66fx1m0_pal_2 MK66FX1M0 PAL driver implementation features
+ * The PAL driver implementation fully supports the following hardware
+ * capabilities:
+ * - 16 bits wide ports.
+ * - Atomic set/reset functions.
+ * - Atomic set+reset function (atomic bus operations).
+ * - Output latched regardless of the pad setting.
+ * - Direct read of input pads regardless of the pad setting.
+ * .
+ * @section mk66fx1m0_pal_3 Supported PAL setup modes
+ * The MK66FX1M0 PAL driver supports the following I/O modes:
+ * - @p PAL_MODE_RESET.
+ * - @p PAL_MODE_UNCONNECTED.
+ * - @p PAL_MODE_INPUT.
+ * - @p PAL_MODE_INPUT_PULLUP.
+ * - @p PAL_MODE_INPUT_PULLDOWN.
+ * - @p PAL_MODE_INPUT_ANALOG.
+ * - @p PAL_MODE_OUTPUT_PUSHPULL.
+ * - @p PAL_MODE_OUTPUT_OPENDRAIN.
+ * - @p PAL_MODE_ALTERNATE (non standard).
+ * .
+ * Any attempt to setup an invalid mode is ignored.
+ *
+ * @section mk66fx1m0_pal_4 Suboptimal behavior
+ * The MK66FX1M0 GPIO is less than optimal in several areas, the limitations
+ * should be taken in account while using the PAL driver:
+ * - Pad/port toggling operations are not atomic.
+ * - Pad/group mode setup is not atomic.
+ * .
+ * @ingroup MK66FX1M0_DRIVERS
+ */
+
+/**
+ * @defgroup MK66FX1M0_PWM MK66FX1M0 PWM Support
+ * @details The MK66FX1M0 PWM driver uses the TIMx peripherals.
+ *
+ * @section mk66fx1m0_pwm_1 Supported HW resources
+ * - TIM1.
+ * - TIM2.
+ * - TIM3.
+ * - TIM4.
+ * - TIM5.
+ * - TIM8.
+ * .
+ * @section mk66fx1m0_pwm_2 MK66FX1M0 PWM driver implementation features
+ * - Each timer can be independently enabled and programmed. Unused
+ *   peripherals are left in low power mode.
+ * - Four independent PWM channels per timer.
+ * - Programmable TIMx interrupts priority level.
+ * .
+ * @ingroup MK66FX1M0_DRIVERS
+ */
+
+/**
+ * @defgroup MK66FX1M0_SDC MK66FX1M0 SDC Support
+ * @details The MK66FX1M0 SDC driver uses the SDIO peripheral.
+ *
+ * @section mk66fx1m0_sdc_1 Supported HW resources
+ * - SDIO.
+ * - DMA2.
+ * .
+ * @section mk66fx1m0_sdc_2 MK66FX1M0 SDC driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Programmable interrupt priority.
+ * - DMA is used for receiving and transmitting.
+ * - Programmable DMA bus priority for each DMA channel.
+ * .
+ * @ingroup MK66FX1M0_DRIVERS
+ */
+
+/**
+ * @defgroup MK66FX1M0_SERIAL MK66FX1M0 Serial Support
+ * @details The MK66FX1M0 Serial driver uses the USART/UART peripherals in a
+ *          buffered, interrupt driven, implementation.
+ *
+ * @section mk66fx1m0_serial_1 Supported HW resources
+ * The serial driver can support any of the following hardware resources:
+ * - USART1.
+ * - USART2.
+ * - USART3.
+ * - UART4.
+ * - UART5.
+ * - USART6.
+ * .
+ * @section mk66fx1m0_serial_2 MK66FX1M0 Serial driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Each UART/USART can be independently enabled and programmed. Unused
+ *   peripherals are left in low power mode.
+ * - Fully interrupt driven.
+ * - Programmable priority levels for each UART/USART.
+ * .
+ * @ingroup MK66FX1M0_DRIVERS
+ */
+
+/**
+ * @defgroup MK66FX1M0_SPI MK66FX1M0 SPI Support
+ * @details The SPI driver supports the MK66FX1M0 SPI peripherals using DMA
+ *          channels for maximum performance.
+ *
+ * @section mk66fx1m0_spi_1 Supported HW resources
+ * - SPI1.
+ * - SPI2.
+ * - SPI3.
+ * - DMA1.
+ * - DMA2.
+ * .
+ * @section mk66fx1m0_spi_2 MK66FX1M0 SPI driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Each SPI can be independently enabled and programmed. Unused
+ *   peripherals are left in low power mode.
+ * - Programmable interrupt priority levels for each SPI.
+ * - DMA is used for receiving and transmitting.
+ * - Programmable DMA bus priority for each DMA channel.
+ * - Programmable DMA interrupt priority for each DMA channel.
+ * - Programmable DMA error hook.
+ * .
+ * @ingroup MK66FX1M0_DRIVERS
+ */
+
+/**
+ * @defgroup MK66FX1M0_UART MK66FX1M0 UART Support
+ * @details The UART driver supports the MK66FX1M0 USART peripherals using DMA
+ *          channels for maximum performance.
+ *
+ * @section mk66fx1m0_uart_1 Supported HW resources
+ * The UART driver can support any of the following hardware resources:
+ * - USART1.
+ * - USART2.
+ * - USART3.
+ * - DMA1.
+ * - DMA2.
+ * .
+ * @section mk66fx1m0_uart_2 MK66FX1M0 UART driver implementation features
+ * - Clock stop for reduced power usage when the driver is in stop state.
+ * - Each UART/USART can be independently enabled and programmed. Unused
+ *   peripherals are left in low power mode.
+ * - Programmable interrupt priority levels for each UART/USART.
+ * - DMA is used for receiving and transmitting.
+ * - Programmable DMA bus priority for each DMA channel.
+ * - Programmable DMA interrupt priority for each DMA channel.
+ * - Programmable DMA error hook.
+ * .
+ * @ingroup MK66FX1M0_DRIVERS
+ */
+
+/**
+ * @defgroup MK66FX1M0_PLATFORM_DRIVERS MK66FX1M0 Platform Drivers
+ * @details Platform support drivers. Platform drivers do not implement HAL
+ *          standard driver templates, their role is to support platform
+ *          specific functionalities.
+ *
+ * @ingroup MK66FX1M0_DRIVERS
+ */
+
+/**
+ * @defgroup MK66FX1M0_DMA MK66FX1M0 DMA Support
+ * @details This DMA helper driver is used by the other drivers in order to
+ *          access the shared DMA resources in a consistent way.
+ *
+ * @section mk66fx1m0_dma_1 Supported HW resources
+ * The DMA driver can support any of the following hardware resources:
+ * - DMA1.
+ * - DMA2.
+ * .
+ * @section mk66fx1m0_dma_2 MK66FX1M0 DMA driver implementation features
+ * - Exports helper functions/macros to the other drivers that share the
+ *   DMA resource.
+ * - Automatic DMA clock stop when not in use by any driver.
+ * - DMA streams and interrupt vectors sharing among multiple drivers.
+ * .
+ * @ingroup MK66FX1M0_PLATFORM_DRIVERS
+ */
+
+/**
+ * @defgroup MK66FX1M0_ISR MK66FX1M0 ISR Support
+ * @details This ISR helper driver is used by the other drivers in order to
+ *          map ISR names to physical vector names.
+ *
+ * @ingroup MK66FX1M0_PLATFORM_DRIVERS
+ */
+
+/**
+ * @defgroup MK66FX1M0_RCC MK66FX1M0 RCC Support
+ * @details This RCC helper driver is used by the other drivers in order to
+ *          access the shared RCC resources in a consistent way.
+ *
+ * @section mk66fx1m0_rcc_1 Supported HW resources
+ * - RCC.
+ * .
+ * @section mk66fx1m0_rcc_2 MK66FX1M0 RCC driver implementation features
+ * - Peripherals reset.
+ * - Peripherals clock enable.
+ * - Peripherals clock disable.
+ * .
+ * @ingroup MK66FX1M0_PLATFORM_DRIVERS
+ */
diff --git a/os/hal/ports/KINETIS/MK66F18/platform.mk b/os/hal/ports/KINETIS/MK66F18/platform.mk
new file mode 100644
index 0000000..d66a31d
--- /dev/null
+++ b/os/hal/ports/KINETIS/MK66F18/platform.mk
@@ -0,0 +1,18 @@
+# List of all platform files.
+PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
+              ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/MK66F18/hal_lld.c \
+              ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_pal_lld.c \
+              ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_serial_lld.c \
+              ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/MK66F18/hal_spi_lld.c \
+              ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c \
+              ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_ext_lld.c \
+              ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_adc_lld.c \
+              ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_gpt_lld.c \
+              ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/MK66F18/hal_pwm_lld.c \
+              ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_st_lld.c \
+              ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_usb_lld.c
+
+# Required include directories
+PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \
+              ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/MK66F18 \
+              ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD
-- 
cgit v1.2.3


From 4e9f077fb10255dced1da4d5d2ad9f8ae41442a2 Mon Sep 17 00:00:00 2001
From: Michael Walker <walkerstop@gmail.com>
Date: Tue, 1 May 2018 00:26:06 -0700
Subject: Enable Kinesis on newer ChibiOS

---
 .../ARMCMx/compilers/GCC/mk/startup_k20x.mk        |  1 +
 .../ARMCMx/compilers/GCC/mk/startup_kl2x.mk        |  1 +
 .../ARMCMx/compilers/GCC/mk/startup_nrf51.mk       |  3 ++-
 .../ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk    |  3 ++-
 .../ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk    |  3 ++-
 os/hal/ports/KINETIS/LLD/hal_pal_lld.h             |  5 +++++
 os/hal/ports/KINETIS/LLD/hal_usb_lld.h             | 23 ++++++++++++++++++++++
 7 files changed, 36 insertions(+), 3 deletions(-)

(limited to 'os')

diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x.mk
index 0c2ec7d..f474d19 100644
--- a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x.mk
+++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_k20x.mk
@@ -7,6 +7,7 @@ STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S
 STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
              $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/K20x \
              $(CHIBIOS)/os/common/ext/CMSIS/include \
+             $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
              $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/KINETIS
 
 STARTUPLD  = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_kl2x.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_kl2x.mk
index ca67f10..0c9d329 100644
--- a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_kl2x.mk
+++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_kl2x.mk
@@ -7,6 +7,7 @@ STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S
 STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
              $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/KL2x \
              $(CHIBIOS)/os/common/ext/CMSIS/include \
+             $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
              $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/KINETIS
 
 STARTUPLD  = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_nrf51.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_nrf51.mk
index f005ce0..8ec318f 100644
--- a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_nrf51.mk
+++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_nrf51.mk
@@ -5,6 +5,7 @@ STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
 STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v6m.S
 
 STARTUPINC = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/NRF51822 \
-             $(CHIBIOS)/os/common/ext/CMSIS/include
+             $(CHIBIOS)/os/common/ext/CMSIS/include \
+             $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include
 
 STARTUPLD  = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk
index e9c97e5..8457328 100644
--- a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk
+++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk
@@ -6,6 +6,7 @@ STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S
 
 STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
              $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/TM4C123x \
-             $(CHIBIOS)/os/common/ext/CMSIS/include
+             $(CHIBIOS)/os/common/ext/CMSIS/include \
+             $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include
 
 STARTUPLD  = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk
index e151434..e488537 100644
--- a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk
+++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk
@@ -6,6 +6,7 @@ STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S
 
 STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
              $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/TM4C129x \
-             $(CHIBIOS)/os/common/ext/CMSIS/include
+             $(CHIBIOS)/os/common/ext/CMSIS/include \
+             $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include
 
 STARTUPLD  = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
diff --git a/os/hal/ports/KINETIS/LLD/hal_pal_lld.h b/os/hal/ports/KINETIS/LLD/hal_pal_lld.h
index 833d95e..6129f69 100644
--- a/os/hal/ports/KINETIS/LLD/hal_pal_lld.h
+++ b/os/hal/ports/KINETIS/LLD/hal_pal_lld.h
@@ -82,6 +82,11 @@ typedef uint32_t ioline_t;
  */
 typedef GPIO_TypeDef *ioportid_t;
 
+/**
+ * @brief   Type of an pad identifier.
+ */
+typedef uint32_t iopadid_t;
+
 /**
  * @brief   Port Configuration.
  * @details This structure stores the configuration parameters of all pads
diff --git a/os/hal/ports/KINETIS/LLD/hal_usb_lld.h b/os/hal/ports/KINETIS/LLD/hal_usb_lld.h
index 593ef16..615d10d 100644
--- a/os/hal/ports/KINETIS/LLD/hal_usb_lld.h
+++ b/os/hal/ports/KINETIS/LLD/hal_usb_lld.h
@@ -326,6 +326,10 @@ struct USBDriver {
    * @brief   Current USB device configuration.
    */
   uint8_t                       configuration;
+  /**
+   * @brief   State of the driver when a suspend happened.
+   */
+  usbstate_t                    saved_state;
 #if defined(USB_DRIVER_EXT_FIELDS)
   USB_DRIVER_EXT_FIELDS
 #endif
@@ -340,6 +344,25 @@ struct USBDriver {
 /* Driver macros.                                                            */
 /*===========================================================================*/
 
+/**
+ * @brief   Host wake-up procedure duration.
+ */
+#if !defined(USB_HOST_WAKEUP_DURATION) || defined(__DOXYGEN__)
+#define USB_HOST_WAKEUP_DURATION            2
+#endif
+
+/**
+ * @brief   Start of host wake-up procedure.
+ *
+ * @notapi
+ */
+#define usb_lld_wakeup_host(usbp)                                           \
+  do{                                                                       \
+    USB0->CTL |= USBx_CTL_RESUME;                                     \
+    osalThreadSleepMilliseconds(USB_HOST_WAKEUP_DURATION);                  \
+    USB0->CTL &= ~USBx_CTL_RESUME;                                    \
+  } while (false)
+
 /**
  * @brief   Returns the current frame number.
  *
-- 
cgit v1.2.3


From 547c570af0dec888252c8ba87942f303567af5b6 Mon Sep 17 00:00:00 2001
From: Michael Walker <walkerstop@gmail.com>
Date: Tue, 1 May 2018 00:42:01 -0700
Subject: Update

---
 os/common/startup/ARMCMx/compilers/GCC/mk/startup_MK66F18.mk | 1 +
 1 file changed, 1 insertion(+)

(limited to 'os')

diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_MK66F18.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_MK66F18.mk
index 0cdd891..50dff2d 100644
--- a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_MK66F18.mk
+++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_MK66F18.mk
@@ -7,6 +7,7 @@ STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S
 STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \
              $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/MK66F18 \
              $(CHIBIOS)/os/common/ext/CMSIS/include \
+             $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \
              $(CHIBIOS_CONTRIB)/os/common/ext/CMSIS/KINETIS
 
 STARTUPLD  = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
-- 
cgit v1.2.3


From 7506c2a2c158513ab3db9d382495e089725d79f3 Mon Sep 17 00:00:00 2001
From: Michael Walker <walkerstop@gmail.com>
Date: Tue, 1 May 2018 00:46:42 -0700
Subject: support Teensy 3.6

---
 os/hal/ports/KINETIS/LLD/hal_usb_lld.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)

(limited to 'os')

diff --git a/os/hal/ports/KINETIS/LLD/hal_usb_lld.c b/os/hal/ports/KINETIS/LLD/hal_usb_lld.c
index e8d9778..77421c8 100644
--- a/os/hal/ports/KINETIS/LLD/hal_usb_lld.c
+++ b/os/hal/ports/KINETIS/LLD/hal_usb_lld.c
@@ -398,15 +398,21 @@ void usb_lld_init(void) {
 
 #if KINETIS_USB_USE_USB0
 
+  /* Set USB clock source to MCGPLLCLK, MCGFLLCLK, USB1 PFD, or IRC48M */
   SIM->SOPT2 |= SIM_SOPT2_USBSRC;
 
-#if defined(K20x5) || defined(K20x7)
+#if defined(K20x5) || defined(K20x7) || defined(MK66F18)
 
 #if KINETIS_MCG_MODE == KINETIS_MCG_MODE_FEI
 
   /* MCGOUTCLK is the SYSCLK frequency, so don't divide for USB clock */
   SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0);
 
+#if defined(MK66F18)
+  /* Switch from default MCGPLLCLK to IRC48M for USB */
+  SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_SET(3);
+#endif
+
 #elif KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE
 
   #define KINETIS_USBCLK_FREQUENCY 48000000UL
-- 
cgit v1.2.3


From 46233064c5527da13c9ea1668a41659a7f8e9a45 Mon Sep 17 00:00:00 2001
From: Michael Walker <walkerstop@gmail.com>
Date: Tue, 1 May 2018 01:07:46 -0700
Subject: iasdfa

---
 os/hal/ports/KINETIS/MK66F18/hal_lld.h | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'os')

diff --git a/os/hal/ports/KINETIS/MK66F18/hal_lld.h b/os/hal/ports/KINETIS/MK66F18/hal_lld.h
index 832955e..4faf575 100644
--- a/os/hal/ports/KINETIS/MK66F18/hal_lld.h
+++ b/os/hal/ports/KINETIS/MK66F18/hal_lld.h
@@ -128,6 +128,9 @@
 #if !defined(KINETIS_CLKDIV1_OUTDIV3) || defined(__DOXYGEN__)
   #if defined(KINETIS_FLEXBUSCLK_FREQUENCY) && KINETIS_FLEXBUSCLK_FREQUENCY > 0
     #define KINETIS_CLKDIV1_OUTDIV3     (KINETIS_PLLCLK_FREQUENCY/KINETIS_FLEXBUSCLK_FREQUENCY)
+  #else
+    /* If no FlexBus frequency provided, use bus speed divider */
+    #define KINETIS_CLKDIV1_OUTDIV3     KINETIS_CLKDIV1_OUTDIV2
   #endif
 #endif
 
-- 
cgit v1.2.3


From 0fbddccd80d3f7f27d2d9286b5e280b53a9e8bd0 Mon Sep 17 00:00:00 2001
From: Michael Walker <walkerstop@gmail.com>
Date: Tue, 1 May 2018 03:26:28 -0700
Subject: disable voltage inrush regulator

---
 os/common/ext/CMSIS/KINETIS/MK66F18.h  | 9 ++++++---
 os/hal/ports/KINETIS/LLD/hal_usb_lld.c | 6 ++++++
 2 files changed, 12 insertions(+), 3 deletions(-)

(limited to 'os')

diff --git a/os/common/ext/CMSIS/KINETIS/MK66F18.h b/os/common/ext/CMSIS/KINETIS/MK66F18.h
index b795a23..b564626 100644
--- a/os/common/ext/CMSIS/KINETIS/MK66F18.h
+++ b/os/common/ext/CMSIS/KINETIS/MK66F18.h
@@ -12032,7 +12032,8 @@ typedef struct {
 #define SIM_SOPT1_USBSSTBY(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)
 #define SIM_SOPT1_USBREGEN_MASK                  (0x80000000U)
 #define SIM_SOPT1_USBREGEN_SHIFT                 (31U)
-#define SIM_SOPT1_USBREGEN(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)
+#define SIM_SOPT1_USBREGEN_SET(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)
+#define SIM_SOPT1_USBREGEN                       SIM_SOPT1_USBREGEN_SET(1)
 
 /*! @name SOPT1CFG - SOPT1 Configuration Register */
 #define SIM_SOPT1CFG_URWE_MASK                   (0x1000000U)
@@ -12057,7 +12058,8 @@ typedef struct {
 #define SIM_USBPHYCTL_USB3VOUTTRG(x)             (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USB3VOUTTRG_SHIFT)) & SIM_USBPHYCTL_USB3VOUTTRG_MASK)
 #define SIM_USBPHYCTL_USBDISILIM_MASK            (0x800000U)
 #define SIM_USBPHYCTL_USBDISILIM_SHIFT           (23U)
-#define SIM_USBPHYCTL_USBDISILIM(x)              (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBDISILIM_SHIFT)) & SIM_USBPHYCTL_USBDISILIM_MASK)
+#define SIM_USBPHYCTL_USBDISILIM_SET(x)          (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBDISILIM_SHIFT)) & SIM_USBPHYCTL_USBDISILIM_MASK)
+#define SIM_USBPHYCTL_USBDISILIM                 SIM_USBPHYCTL_USBDISILIM_SET(1)
 
 /*! @name SOPT2 - System Options Register 2 */
 #define SIM_SOPT2_USBSLSRC_MASK                  (0x1U)
@@ -12065,7 +12067,8 @@ typedef struct {
 #define SIM_SOPT2_USBSLSRC(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSLSRC_SHIFT)) & SIM_SOPT2_USBSLSRC_MASK)
 #define SIM_SOPT2_USBREGEN_MASK                  (0x2U)
 #define SIM_SOPT2_USBREGEN_SHIFT                 (1U)
-#define SIM_SOPT2_USBREGEN(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBREGEN_SHIFT)) & SIM_SOPT2_USBREGEN_MASK)
+#define SIM_SOPT2_USBREGEN_SET(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBREGEN_SHIFT)) & SIM_SOPT2_USBREGEN_MASK)
+#define SIM_SOPT2_USBREGEN                       SIM_SOPT2_USBREGEN_SET(1)
 #define SIM_SOPT2_RTCCLKOUTSEL_MASK              (0x10U)
 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT             (4U)
 #define SIM_SOPT2_RTCCLKOUTSEL(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
diff --git a/os/hal/ports/KINETIS/LLD/hal_usb_lld.c b/os/hal/ports/KINETIS/LLD/hal_usb_lld.c
index 77421c8..7b7aa0e 100644
--- a/os/hal/ports/KINETIS/LLD/hal_usb_lld.c
+++ b/os/hal/ports/KINETIS/LLD/hal_usb_lld.c
@@ -461,9 +461,15 @@ void usb_lld_start(USBDriver *usbp) {
         _bdt[i].addr=0;
       }
 
+#if defined(MK66F18)
+      /* Disable the USB current limiter */
+      SIM->USBPHYCTL |= SIM_USBPHYCTL_USBDISILIM;
+#endif
+
       /* Enable Clock */
 #if KINETIS_USB0_IS_USBOTG
       SIM->SCGC4 |= SIM_SCGC4_USBOTG;
+
 #else /* KINETIS_USB0_IS_USBOTG */
       SIM->SCGC4 |= SIM_SCGC4_USBFS;
 #endif /* KINETIS_USB0_IS_USBOTG */
-- 
cgit v1.2.3


From 4d7ccdd1fce0c95c57129b80c81fab829daf9f99 Mon Sep 17 00:00:00 2001
From: Michael Walker <walkerstop@gmail.com>
Date: Tue, 1 May 2018 14:46:56 -0700
Subject: More corrections

---
 os/common/ext/CMSIS/KINETIS/MK66F18.h |   8 +-
 os/hal/boards/PJRC_TEENSY_3_6/board.c | 425 +++++++++++----------
 os/hal/boards/PJRC_TEENSY_3_6/board.h | 690 +++++++++++++++++-----------------
 3 files changed, 566 insertions(+), 557 deletions(-)

(limited to 'os')

diff --git a/os/common/ext/CMSIS/KINETIS/MK66F18.h b/os/common/ext/CMSIS/KINETIS/MK66F18.h
index b564626..c016c30 100644
--- a/os/common/ext/CMSIS/KINETIS/MK66F18.h
+++ b/os/common/ext/CMSIS/KINETIS/MK66F18.h
@@ -279,7 +279,7 @@ typedef enum IRQn {
  * @{
  */
 
-#define __MPU_PRESENT                  0         /**< Defines if an MPU is present or not */
+#define __MPU_PRESENT                  1         /**< Defines if an MPU is present or not */
 #define __NVIC_PRIO_BITS               4         /**< Number of priority bits implemented in the NVIC */
 #define __Vendor_SysTickConfig         0         /**< Vendor specific implementation of SysTickConfig is defined */
 #define __FPU_PRESENT                  1         /**< Defines if an FPU is present or not */
@@ -12340,7 +12340,8 @@ typedef struct {
 #define SIM_SCGC3_USBHS(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHS_SHIFT)) & SIM_SCGC3_USBHS_MASK)
 #define SIM_SCGC3_USBHSPHY_MASK                  (0x4U)
 #define SIM_SCGC3_USBHSPHY_SHIFT                 (2U)
-#define SIM_SCGC3_USBHSPHY(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHSPHY_SHIFT)) & SIM_SCGC3_USBHSPHY_MASK)
+#define SIM_SCGC3_USBHSPHY_SET(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHSPHY_SHIFT)) & SIM_SCGC3_USBHSPHY_MASK)
+#define SIM_SCGC3_USBHSPHY                       SIM_SCGC3_USBHSPHY_SET(1)
 #define SIM_SCGC3_USBHSDCD_MASK                  (0x8U)
 #define SIM_SCGC3_USBHSDCD_SHIFT                 (3U)
 #define SIM_SCGC3_USBHSDCD(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHSDCD_SHIFT)) & SIM_SCGC3_USBHSDCD_MASK)
@@ -14465,7 +14466,8 @@ typedef struct {
 #define USBx_CTL_RESUME                           USBx_CTL_RESUME_SET(1)
 #define USBx_CTL_HOSTMODEEN_MASK                  (0x8U)
 #define USBx_CTL_HOSTMODEEN_SHIFT                 (3U)
-#define USBx_CTL_HOSTMODEEN(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_CTL_HOSTMODEEN_SHIFT)) & USBx_CTL_HOSTMODEEN_MASK)
+#define USBx_CTL_HOSTMODEEN_SET(x)                (((uint8_t)(((uint8_t)(x)) << USBx_CTL_HOSTMODEEN_SHIFT)) & USBx_CTL_HOSTMODEEN_MASK)
+#define USBx_CTL_HOSTMODEEN                       USBx_CTL_HOSTMODEEN_SET(1) 
 #define USBx_CTL_RESET_MASK                       (0x10U)
 #define USBx_CTL_RESET_SHIFT                      (4U)
 #define USBx_CTL_RESET(x)                         (((uint8_t)(((uint8_t)(x)) << USBx_CTL_RESET_SHIFT)) & USBx_CTL_RESET_MASK)
diff --git a/os/hal/boards/PJRC_TEENSY_3_6/board.c b/os/hal/boards/PJRC_TEENSY_3_6/board.c
index 3e2f022..e59f4ae 100644
--- a/os/hal/boards/PJRC_TEENSY_3_6/board.c
+++ b/os/hal/boards/PJRC_TEENSY_3_6/board.c
@@ -1,209 +1,216 @@
-/*
-    ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-#include "hal.h"
-
-#if HAL_USE_PAL || defined(__DOXYGEN__)
-/**
- * @brief   PAL setup.
- * @details Digital I/O ports static configuration as defined in @p board.h.
- *          This variable is used by the HAL when initializing the PAL driver.
- */
-const PALConfig pal_default_config =
-{
-    .ports = {
-        {
-            /*
-             * PORTA setup.
-             *
-             * PTA0 - SWD
-             * PTA3 - SWD
-             * PTA5 - PIN25
-             * PTA12 - PIN3
-             * PTA13 - PIN4
-             * PTA14 - PIN26
-             * PTA15 - PIN27
-             * PTA16 - PIN28
-             * PTA17 - PIN39
-             * PTA18 - Crystal
-             * PTA19 - Crystal
-             * PTA26 - PIN42
-             * PTA28 - PIN40
-             * PTA29 - PIN41
-             *
-             */
-            .port = IOPORT1,
-            .pads = {
-                PAL_MODE_ALTERNATIVE_7,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
-                PAL_MODE_ALTERNATIVE_7,       PAL_MODE_UNCONNECTED,       PAL_MODE_OUTPUT_PUSHPULL,
-                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
-                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
-                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
-                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
-                PAL_MODE_INPUT_ANALOG,      PAL_MODE_INPUT_ANALOG,       PAL_MODE_UNCONNECTED,
-                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
-                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_OUTPUT_PUSHPULL,
-                PAL_MODE_UNCONNECTED,       PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
-                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
-            },
-        },
-        {
-            /*
-             * PORTB setup.
-             *
-             * PTB0 - PIN16
-             * PTB1 - PIN17
-             * PTB2 - PIN19
-             * PTB3 - PIN18
-             * PTB4 - PIN49
-             * PTB5 - PIN50
-             * PTB10 - PIN31
-             * PTB11 - PIN32
-             * PTB16 - PIN0 - UART0_RX 
-             * PTB17 - PIN1 - UART0_TX
-             * PTB18 - PIN29
-             * PTB19 - PIN30
-             * PTB20 - PIN43
-             * PTB21 - PIN46
-             * PTB22 - PIN44
-             * PTB23 - PIN45
-             */
-            .port = IOPORT2,
-            .pads = {
-                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
-                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
-                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
-                PAL_MODE_UNCONNECTED,       PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
-                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
-                PAL_MODE_UNCONNECTED,       PAL_MODE_ALTERNATIVE_3,     PAL_MODE_ALTERNATIVE_3,
-                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
-                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
-                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
-                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
-                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
-            },
-        },
-        {
-            /*
-             * PORTC setup.
-             * PTC0 - PIN15
-             * PTC1 - PIN22
-             * PTC2 - PIN23
-             * PTC3 - PIN9
-             * PTC4 - PIN10
-             * PTC5 - PIN13
-             * PTC6 - PIN11
-             * PTC7 - PIN12
-             * PTC8 - PIN35
-             * PTC9 - PIN36
-             * PTC10 - PIN37
-             * PTC11 - PIN38
-             *
-             */
-            .port = IOPORT3,
-            .pads = {
-                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
-                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
-                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
-                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
-                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
-                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
-                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
-                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
-                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
-                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
-                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
-            },
-        },
-        {
-            /*
-             * PORTD setup.
-             *
-             * PTD0 - PIN2
-             * PTD1 - PIN14
-             * PTD2 - PIN7
-             * PTD3 - PIN8
-             * PTD4 - PIN6
-             * PTD5 - PIN20
-             * PTD6 - PIN21
-             * PTD7 - PIN5
-             * PTD8 - PIN47
-             * PTD9 - PIN48
-             * PTD11 - PIN55
-             * PTD12 - PIN53
-             * PTD13 - PIN52
-             * PTD14 - PIN51
-             * PTD15 - PIN54
-             */
-            .port = IOPORT4,
-            .pads = {
-                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
-                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
-                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
-                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_UNCONNECTED,       PAL_MODE_OUTPUT_PUSHPULL,
-                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
-                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
-                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
-                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
-                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
-                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
-                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
-            },
-        },
-        {
-            /*
-             * PORTE setup.
-             *
-             * PTE10 - PIN56
-             * PTE11 - PIN57
-             * PTE24 - PIN33
-             * PTE25 - PIN34
-             * PTE26 - PIN24
-             */
-            .port = IOPORT5,
-            .pads = {
-                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
-                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
-                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
-                PAL_MODE_UNCONNECTED,       PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
-                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
-                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
-                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
-                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
-                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
-                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
-                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
-            },
-        },
-    },
-};
-#endif
-
-/**
- * @brief   Early initialization code.
- * @details This initialization must be performed just after stack setup
- *          and before any other initialization.
- */
-void __early_init(void) {
-
-  MK66F18_clock_init();
-}
-
-/**
- * @brief   Board-specific initialization code.
- * @todo    Add your board-specific code, if any.
- */
-void boardInit(void) {
-}
+/*
+    ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+#include "hal.h"
+
+#if HAL_USE_PAL || defined(__DOXYGEN__)
+/**
+ * @brief   PAL setup.
+ * @details Digital I/O ports static configuration as defined in @p board.h.
+ *          This variable is used by the HAL when initializing the PAL driver.
+ */
+const PALConfig pal_default_config =
+{
+    .ports = {
+        {
+            /*
+             * PORTA setup.
+             *
+             * PTA0 - SWD
+             * PTA3 - SWD
+             * PTA5 - PIN25
+             * PTA12 - PIN3
+             * PTA13 - PIN4
+             * PTA14 - PIN26
+             * PTA15 - PIN27
+             * PTA16 - PIN28
+             * PTA17 - PIN39
+             * PTA18 - Crystal
+             * PTA19 - Crystal
+             * PTA26 - PIN42
+             * PTA28 - PIN40
+             * PTA29 - PIN41
+             *
+             */
+            .port = IOPORT1,
+            .pads = {
+                PAL_MODE_ALTERNATIVE_7,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_ALTERNATIVE_7,       PAL_MODE_UNCONNECTED,       PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_INPUT_ANALOG,      PAL_MODE_INPUT_ANALOG,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+        {
+            /*
+             * PORTB setup.
+             *
+             * PTB0 - PIN16
+             * PTB1 - PIN17
+             * PTB2 - PIN19
+             * PTB3 - PIN18
+             * PTB4 - PIN49
+             * PTB5 - PIN50
+             * PTB10 - PIN31
+             * PTB11 - PIN32
+             * PTB16 - PIN0 - UART0_RX 
+             * PTB17 - PIN1 - UART0_TX
+             * PTB18 - PIN29
+             * PTB19 - PIN30
+             * PTB20 - PIN43
+             * PTB21 - PIN46
+             * PTB22 - PIN44
+             * PTB23 - PIN45
+             */
+            .port = IOPORT2,
+            .pads = {
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_ALTERNATIVE_3,     PAL_MODE_ALTERNATIVE_3,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+        {
+            /*
+             * PORTC setup.
+             * PTC0 - PIN15
+             * PTC1 - PIN22
+             * PTC2 - PIN23
+             * PTC3 - PIN9
+             * PTC4 - PIN10
+             * PTC5 - PIN13
+             * PTC6 - PIN11
+             * PTC7 - PIN12
+             * PTC8 - PIN35
+             * PTC9 - PIN36
+             * PTC10 - PIN37
+             * PTC11 - PIN38
+             *
+             */
+            .port = IOPORT3,
+            .pads = {
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+        {
+            /*
+             * PORTD setup.
+             *
+             * PTD0 - PIN2
+             * PTD1 - PIN14
+             * PTD2 - PIN7
+             * PTD3 - PIN8
+             * PTD4 - PIN6
+             * PTD5 - PIN20
+             * PTD6 - PIN21
+             * PTD7 - PIN5
+             * PTD8 - PIN47
+             * PTD9 - PIN48
+             * PTD11 - PIN55
+             * PTD12 - PIN53
+             * PTD13 - PIN52
+             * PTD14 - PIN51
+             * PTD15 - PIN54
+             */
+            .port = IOPORT4,
+            .pads = {
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_UNCONNECTED,       PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+        {
+            /*
+             * PORTE setup.
+             *
+             * PTE0 - SDHC
+             * PTE1 - SDHC
+             * PTE2 - SDHC
+             * PTE3 - SDHC
+             * PTE4 - SDHC
+             * PTE5 - SDHC
+             * PTE6 - USB OTG power switch
+             * PTE10 - PIN56
+             * PTE11 - PIN57
+             * PTE24 - PIN33
+             * PTE25 - PIN34
+             * PTE26 - PIN24
+             */
+            .port = IOPORT5,
+            .pads = {
+                PAL_MODE_ALTERNATIVE_4,     PAL_MODE_ALTERNATIVE_4,     PAL_MODE_ALTERNATIVE_4,
+                PAL_MODE_ALTERNATIVE_4,     PAL_MODE_ALTERNATIVE_4,     PAL_MODE_ALTERNATIVE_4,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,   PAL_MODE_OUTPUT_PUSHPULL,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+                PAL_MODE_UNCONNECTED,       PAL_MODE_UNCONNECTED,
+            },
+        },
+    },
+};
+#endif
+
+/**
+ * @brief   Early initialization code.
+ * @details This initialization must be performed just after stack setup
+ *          and before any other initialization.
+ */
+void __early_init(void) {
+
+  MK66F18_clock_init();
+}
+
+/**
+ * @brief   Board-specific initialization code.
+ * @todo    Add your board-specific code, if any.
+ */
+void boardInit(void) {
+}
diff --git a/os/hal/boards/PJRC_TEENSY_3_6/board.h b/os/hal/boards/PJRC_TEENSY_3_6/board.h
index 9b0a8ad..febd40c 100644
--- a/os/hal/boards/PJRC_TEENSY_3_6/board.h
+++ b/os/hal/boards/PJRC_TEENSY_3_6/board.h
@@ -1,345 +1,345 @@
-/*
-    ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde
-
-    Licensed under the Apache License, Version 2.0 (the "License");
-    you may not use this file except in compliance with the License.
-    You may obtain a copy of the License at
-
-        http://www.apache.org/licenses/LICENSE-2.0
-
-    Unless required by applicable law or agreed to in writing, software
-    distributed under the License is distributed on an "AS IS" BASIS,
-    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
-    See the License for the specific language governing permissions and
-    limitations under the License.
-*/
-
-#ifndef _BOARD_H_
-#define _BOARD_H_
-
-/*
- * Setup for the PJRC Teensy 3.6 board.
- */
-
-/*
- * Board identifier.
- */
-#define BOARD_PJRC_TEENSY_3_6
-#define BOARD_NAME                  "PJRC Teensy 3.6"
-
-/* External 16 MHz crystal */
-#define KINETIS_XTAL_FREQUENCY      16000000UL
-
-/* Use internal capacitors for the crystal */
-#define KINETIS_BOARD_OSCILLATOR_SETTING OSC_CR_SC8P|OSC_CR_SC2P
-
-/*
- * MCU type
- */
-#define MK66F18
-
-/*
- * IO pins assignments.
- */
-#define PORTA_PIN0                  0
-#define PORTA_PIN1                  1
-#define PORTA_PIN2                  2
-#define PORTA_PIN3                  3
-#define PORTA_PIN4                  4
-#define TEENSY_PIN25                5
-#define PORTA_PIN6                  6
-#define PORTA_PIN7                  7
-#define PORTA_PIN8                  8
-#define PORTA_PIN9                  9
-#define PORTA_PIN10                 10
-#define PORTA_PIN11                 11
-#define TEENSY_PIN3                 12
-#define TEENSY_PIN4                 13
-#define TEENSY_PIN26                14
-#define TEENSY_PIN27                15
-#define TEENSY_PIN28                16
-#define TEENSY_PIN39                17
-#define PORTA_PIN18                 18
-#define PORTA_PIN19                 19
-#define PORTA_PIN20                 20
-#define PORTA_PIN21                 21
-#define PORTA_PIN22                 22
-#define PORTA_PIN23                 23
-#define PORTA_PIN24                 24
-#define PORTA_PIN25                 25
-#define TEENSY_PIN42                26
-#define PORTA_PIN27                 27
-#define TEENSY_PIN40                28
-#define TEENSY_PIN41                29
-#define PORTA_PIN30                 30
-#define PORTA_PIN31                 31
-
-#define TEENSY_PIN40_IOPORT  IOPORT1
-#define TEENSY_PIN41_IOPORT  IOPORT1
-#define TEENSY_PIN42_IOPORT  IOPORT1
-#define TEENSY_PIN3_IOPORT   IOPORT1
-#define TEENSY_PIN4_IOPORT   IOPORT1
-#define TEENSY_PIN25_IOPORT  IOPORT1
-#define TEENSY_PIN26_IOPORT  IOPORT1
-#define TEENSY_PIN27_IOPORT  IOPORT1
-#define TEENSY_PIN28_IOPORT  IOPORT1
-#define TEENSY_PIN39_IOPORT  IOPORT1
-
-#define TEENSY_PIN16                0
-#define TEENSY_PIN17                1
-#define TEENSY_PIN19                2
-#define TEENSY_PIN18                3
-#define TEENSY_PIN49                4
-#define TEENSY_PIN50                5
-#define PORTB_PIN6                  6
-#define PORTB_PIN7                  7
-#define PORTB_PIN8                  8
-#define PORTB_PIN9                  9
-#define TEENSY_PIN31                10
-#define TEENSY_PIN32                11
-#define PORTB_PIN12                 12
-#define PORTB_PIN13                 13
-#define PORTB_PIN14                 14
-#define PORTB_PIN15                 15
-#define TEENSY_PIN0                 16
-#define TEENSY_PIN1                 17
-#define TEENSY_PIN29                18
-#define TEENSY_PIN30                19
-#define TEENSY_PIN43                20
-#define TEENSY_PIN46                21
-#define TEENSY_PIN44                22
-#define TEENSY_PIN45                23
-#define PORTB_PIN24                 24
-#define PORTB_PIN25                 25
-#define PORTB_PIN26                 26
-#define PORTB_PIN27                 27
-#define PORTB_PIN28                 28
-#define PORTB_PIN29                 29
-#define PORTB_PIN30                 30
-#define PORTB_PIN31                 31
-
-#define TEENSY_PIN49_IOPORT  IOPORT2
-#define TEENSY_PIN50_IOPORT  IOPORT2
-#define TEENSY_PIN43_IOPORT  IOPORT2
-#define TEENSY_PIN44_IOPORT  IOPORT2
-#define TEENSY_PIN45_IOPORT  IOPORT2
-#define TEENSY_PIN46_IOPORT  IOPORT2
-#define TEENSY_PIN0_IOPORT   IOPORT2
-#define TEENSY_PIN1_IOPORT   IOPORT2
-#define TEENSY_PIN29_IOPORT  IOPORT2
-#define TEENSY_PIN30_IOPORT  IOPORT2
-#define TEENSY_PIN31_IOPORT  IOPORT2
-#define TEENSY_PIN32_IOPORT  IOPORT2
-#define TEENSY_PIN16_IOPORT  IOPORT2
-#define TEENSY_PIN17_IOPORT  IOPORT2
-#define TEENSY_PIN19_IOPORT  IOPORT2
-#define TEENSY_PIN18_IOPORT  IOPORT2
-
-#define TEENSY_PIN15                0
-#define TEENSY_PIN22                1
-#define TEENSY_PIN23                2
-#define TEENSY_PIN9                 3
-#define TEENSY_PIN10                4
-#define TEENSY_PIN13                5
-#define TEENSY_PIN11                6
-#define TEENSY_PIN12                7
-#define TEENSY_PIN35                8
-#define TEENSY_PIN36                9
-#define TEENSY_PIN37                10
-#define TEENSY_PIN38                11
-#define PORTC_PIN12                 12
-#define PORTC_PIN13                 13
-#define PORTC_PIN14                 14
-#define PORTC_PIN15                 15
-#define PORTC_PIN16                 16
-#define PORTC_PIN17                 17
-#define PORTC_PIN18                 18
-#define PORTC_PIN19                 19
-#define PORTC_PIN20                 20
-#define PORTC_PIN21                 21
-#define PORTC_PIN22                 22
-#define PORTC_PIN23                 23
-#define PORTC_PIN24                 24
-#define PORTC_PIN25                 25
-#define PORTC_PIN26                 26
-#define PORTC_PIN27                 27
-#define PORTC_PIN28                 28
-#define PORTC_PIN29                 29
-#define PORTC_PIN30                 30
-#define PORTC_PIN31                 31
-
-#define TEENSY_PIN9_IOPORT   IOPORT3
-#define TEENSY_PIN10_IOPORT  IOPORT3
-#define TEENSY_PIN11_IOPORT  IOPORT3
-#define TEENSY_PIN12_IOPORT  IOPORT3
-#define TEENSY_PIN35_IOPORT  IOPORT3
-#define TEENSY_PIN36_IOPORT  IOPORT3
-#define TEENSY_PIN37_IOPORT  IOPORT3
-#define TEENSY_PIN38_IOPORT  IOPORT3
-#define TEENSY_PIN13_IOPORT  IOPORT3
-#define TEENSY_PIN15_IOPORT  IOPORT3
-#define TEENSY_PIN22_IOPORT  IOPORT3
-#define TEENSY_PIN23_IOPORT  IOPORT3
-
-#define TEENSY_PIN2                 0
-#define TEENSY_PIN14                1
-#define TEENSY_PIN7                 2
-#define TEENSY_PIN8                 3
-#define TEENSY_PIN6                 4
-#define TEENSY_PIN20                5
-#define TEENSY_PIN21                6
-#define TEENSY_PIN5                 7
-#define TEENSY_PIN47                8
-#define TEENSY_PIN48                9
-#define PORTD_PIN10                 10
-#define TEENSY_PIN55                11
-#define TEENSY_PIN53                12
-#define TEENSY_PIN52                13
-#define TEENSY_PIN51                14
-#define TEENSY_PIN54                15
-#define PORTD_PIN16                 16
-#define PORTD_PIN17                 17
-#define PORTD_PIN18                 18
-#define PORTD_PIN19                 19
-#define PORTD_PIN20                 20
-#define PORTD_PIN21                 21
-#define PORTD_PIN22                 22
-#define PORTD_PIN23                 23
-#define PORTD_PIN24                 24
-#define PORTD_PIN25                 25
-#define PORTD_PIN26                 26
-#define PORTD_PIN27                 27
-#define PORTD_PIN28                 28
-#define PORTD_PIN29                 29
-#define PORTD_PIN30                 30
-#define PORTD_PIN31                 31
-
-#define TEENSY_PIN51_IOPORT  IOPORT4
-#define TEENSY_PIN52_IOPORT  IOPORT4
-#define TEENSY_PIN53_IOPORT  IOPORT4
-#define TEENSY_PIN54_IOPORT  IOPORT4
-#define TEENSY_PIN55_IOPORT  IOPORT4
-#define TEENSY_PIN47_IOPORT  IOPORT4
-#define TEENSY_PIN48_IOPORT  IOPORT4
-#define TEENSY_PIN2_IOPORT   IOPORT4
-#define TEENSY_PIN5_IOPORT   IOPORT4
-#define TEENSY_PIN6_IOPORT   IOPORT4
-#define TEENSY_PIN7_IOPORT   IOPORT4
-#define TEENSY_PIN8_IOPORT   IOPORT4
-#define TEENSY_PIN14_IOPORT  IOPORT4
-#define TEENSY_PIN20_IOPORT  IOPORT4
-#define TEENSY_PIN21_IOPORT  IOPORT4
-
-#define PORTE_PIN0                  0
-#define PORTE_PIN1                  1
-#define PORTE_PIN2                  2
-#define PORTE_PIN3                  3
-#define PORTE_PIN4                  4
-#define PORTE_PIN5                  5
-#define PORTE_PIN6                  6
-#define PORTE_PIN7                  7
-#define PORTE_PIN8                  8
-#define PORTE_PIN9                  9
-#define TEENSY_PIN56                10
-#define TEENSY_PIN57                11
-#define PORTE_PIN12                 12
-#define PORTE_PIN13                 13
-#define PORTE_PIN14                 14
-#define PORTE_PIN15                 15
-#define PORTE_PIN16                 16
-#define PORTE_PIN17                 17
-#define PORTE_PIN18                 18
-#define PORTE_PIN19                 19
-#define PORTE_PIN20                 20
-#define PORTE_PIN21                 21
-#define PORTE_PIN22                 22
-#define PORTE_PIN23                 23
-#define TEENSY_PIN33                24
-#define TEENSY_PIN34                25
-#define TEENSY_PIN24                26
-#define PORTE_PIN27                 27
-#define PORTE_PIN28                 28
-#define PORTE_PIN29                 29
-#define PORTE_PIN30                 30
-#define PORTE_PIN31                 31
-
-#define TEENSY_PIN56_IOPORT  IOPORT5
-#define TEENSY_PIN57_IOPORT  IOPORT5
-#define TEENSY_PIN24_IOPORT  IOPORT5
-#define TEENSY_PIN33_IOPORT  IOPORT5
-#define TEENSY_PIN34_IOPORT  IOPORT5
-
-
-#define LINE_PIN0           PAL_LINE(TEENSY_PIN0_IOPORT, TEENSY_PIN0)
-#define LINE_PIN1           PAL_LINE(TEENSY_PIN1_IOPORT, TEENSY_PIN1)
-#define LINE_PIN2           PAL_LINE(TEENSY_PIN2_IOPORT, TEENSY_PIN2)
-#define LINE_PIN3           PAL_LINE(TEENSY_PIN3_IOPORT, TEENSY_PIN3)
-#define LINE_PIN4           PAL_LINE(TEENSY_PIN4_IOPORT, TEENSY_PIN4)
-#define LINE_PIN5           PAL_LINE(TEENSY_PIN5_IOPORT, TEENSY_PIN5)
-#define LINE_PIN6           PAL_LINE(TEENSY_PIN6_IOPORT, TEENSY_PIN6)
-#define LINE_PIN7           PAL_LINE(TEENSY_PIN7_IOPORT, TEENSY_PIN7)
-#define LINE_PIN8           PAL_LINE(TEENSY_PIN8_IOPORT, TEENSY_PIN8)
-#define LINE_PIN9           PAL_LINE(TEENSY_PIN9_IOPORT, TEENSY_PIN9)
-#define LINE_PIN10          PAL_LINE(TEENSY_PIN10_IOPORT, TEENSY_PIN10)
-#define LINE_PIN11          PAL_LINE(TEENSY_PIN11_IOPORT, TEENSY_PIN11)
-#define LINE_PIN12          PAL_LINE(TEENSY_PIN12_IOPORT, TEENSY_PIN12)
-#define LINE_PIN13          PAL_LINE(TEENSY_PIN13_IOPORT, TEENSY_PIN13)
-#define LINE_PIN14          PAL_LINE(TEENSY_PIN14_IOPORT, TEENSY_PIN14)
-#define LINE_PIN15          PAL_LINE(TEENSY_PIN15_IOPORT, TEENSY_PIN15)
-#define LINE_PIN16          PAL_LINE(TEENSY_PIN16_IOPORT, TEENSY_PIN16)
-#define LINE_PIN17          PAL_LINE(TEENSY_PIN17_IOPORT, TEENSY_PIN17)
-#define LINE_PIN18          PAL_LINE(TEENSY_PIN18_IOPORT, TEENSY_PIN18)
-#define LINE_PIN19          PAL_LINE(TEENSY_PIN19_IOPORT, TEENSY_PIN19)
-#define LINE_PIN20          PAL_LINE(TEENSY_PIN20_IOPORT, TEENSY_PIN20)
-#define LINE_PIN21          PAL_LINE(TEENSY_PIN21_IOPORT, TEENSY_PIN21)
-#define LINE_PIN22          PAL_LINE(TEENSY_PIN22_IOPORT, TEENSY_PIN22)
-#define LINE_PIN23          PAL_LINE(TEENSY_PIN23_IOPORT, TEENSY_PIN23)
-#define LINE_PIN24          PAL_LINE(TEENSY_PIN24_IOPORT, TEENSY_PIN24)
-#define LINE_PIN25          PAL_LINE(TEENSY_PIN25_IOPORT, TEENSY_PIN25)
-#define LINE_PIN25          PAL_LINE(TEENSY_PIN25_IOPORT, TEENSY_PIN25)
-#define LINE_PIN26          PAL_LINE(TEENSY_PIN26_IOPORT, TEENSY_PIN26)
-#define LINE_PIN27          PAL_LINE(TEENSY_PIN27_IOPORT, TEENSY_PIN27)
-#define LINE_PIN28          PAL_LINE(TEENSY_PIN28_IOPORT, TEENSY_PIN28)
-#define LINE_PIN29          PAL_LINE(TEENSY_PIN29_IOPORT, TEENSY_PIN29)
-#define LINE_PIN30          PAL_LINE(TEENSY_PIN30_IOPORT, TEENSY_PIN30)
-#define LINE_PIN31          PAL_LINE(TEENSY_PIN31_IOPORT, TEENSY_PIN31)
-#define LINE_PIN32          PAL_LINE(TEENSY_PIN32_IOPORT, TEENSY_PIN32)
-#define LINE_PIN33          PAL_LINE(TEENSY_PIN33_IOPORT, TEENSY_PIN33)
-#define LINE_PIN34          PAL_LINE(TEENSY_PIN34_IOPORT, TEENSY_PIN34)
-#define LINE_PIN35          PAL_LINE(TEENSY_PIN35_IOPORT, TEENSY_PIN35)
-#define LINE_PIN36          PAL_LINE(TEENSY_PIN36_IOPORT, TEENSY_PIN36)
-#define LINE_PIN37          PAL_LINE(TEENSY_PIN37_IOPORT, TEENSY_PIN37)
-#define LINE_PIN38          PAL_LINE(TEENSY_PIN38_IOPORT, TEENSY_PIN38)
-#define LINE_PIN39          PAL_LINE(TEENSY_PIN39_IOPORT, TEENSY_PIN39)
-#define LINE_PIN40          PAL_LINE(TEENSY_PIN40_IOPORT, TEENSY_PIN40)
-#define LINE_PIN41          PAL_LINE(TEENSY_PIN41_IOPORT, TEENSY_PIN41)
-#define LINE_PIN42          PAL_LINE(TEENSY_PIN42_IOPORT, TEENSY_PIN42)
-#define LINE_PIN43          PAL_LINE(TEENSY_PIN43_IOPORT, TEENSY_PIN43)
-#define LINE_PIN44          PAL_LINE(TEENSY_PIN44_IOPORT, TEENSY_PIN44)
-#define LINE_PIN45          PAL_LINE(TEENSY_PIN45_IOPORT, TEENSY_PIN45)
-#define LINE_PIN46          PAL_LINE(TEENSY_PIN46_IOPORT, TEENSY_PIN46)
-#define LINE_PIN47          PAL_LINE(TEENSY_PIN47_IOPORT, TEENSY_PIN47)
-#define LINE_PIN48          PAL_LINE(TEENSY_PIN48_IOPORT, TEENSY_PIN48)
-#define LINE_PIN49          PAL_LINE(TEENSY_PIN49_IOPORT, TEENSY_PIN49)
-#define LINE_PIN50          PAL_LINE(TEENSY_PIN50_IOPORT, TEENSY_PIN50)
-#define LINE_PIN51          PAL_LINE(TEENSY_PIN51_IOPORT, TEENSY_PIN50)
-#define LINE_PIN52          PAL_LINE(TEENSY_PIN52_IOPORT, TEENSY_PIN52)
-#define LINE_PIN53          PAL_LINE(TEENSY_PIN53_IOPORT, TEENSY_PIN53)
-#define LINE_PIN54          PAL_LINE(TEENSY_PIN54_IOPORT, TEENSY_PIN54)
-#define LINE_PIN55          PAL_LINE(TEENSY_PIN55_IOPORT, TEENSY_PIN55)
-#define LINE_PIN56          PAL_LINE(TEENSY_PIN56_IOPORT, TEENSY_PIN56)
-#define LINE_PIN57          PAL_LINE(TEENSY_PIN57_IOPORT, TEENSY_PIN57)
-
-#define LINE_LED            LINE_PIN13
-
-#if !defined(_FROM_ASM_)
-#ifdef __cplusplus
-extern "C" {
-#endif
-  void boardInit(void);
-#ifdef __cplusplus
-}
-#endif
-#endif /* _FROM_ASM_ */
-
-#endif /* _BOARD_H_ */
+/*
+    ChibiOS - Copyright (C) 2015 RedoX https://github.com/RedoXyde
+
+    Licensed under the Apache License, Version 2.0 (the "License");
+    you may not use this file except in compliance with the License.
+    You may obtain a copy of the License at
+
+        http://www.apache.org/licenses/LICENSE-2.0
+
+    Unless required by applicable law or agreed to in writing, software
+    distributed under the License is distributed on an "AS IS" BASIS,
+    WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+    See the License for the specific language governing permissions and
+    limitations under the License.
+*/
+
+#ifndef _BOARD_H_
+#define _BOARD_H_
+
+/*
+ * Setup for the PJRC Teensy 3.6 board.
+ */
+
+/*
+ * Board identifier.
+ */
+#define BOARD_PJRC_TEENSY_3_6
+#define BOARD_NAME                  "PJRC Teensy 3.6"
+
+/* External 16 MHz crystal */
+#define KINETIS_XTAL_FREQUENCY      16000000UL
+
+/* Use internal capacitors for the crystal */
+#define KINETIS_BOARD_OSCILLATOR_SETTING OSC_CR_SC8P|OSC_CR_SC2P
+
+/*
+ * MCU type
+ */
+#define MK66F18
+
+/*
+ * IO pins assignments.
+ */
+#define PORTA_PIN0                  0
+#define PORTA_PIN1                  1
+#define PORTA_PIN2                  2
+#define PORTA_PIN3                  3
+#define PORTA_PIN4                  4
+#define TEENSY_PIN25                5
+#define PORTA_PIN6                  6
+#define PORTA_PIN7                  7
+#define PORTA_PIN8                  8
+#define PORTA_PIN9                  9
+#define PORTA_PIN10                 10
+#define PORTA_PIN11                 11
+#define TEENSY_PIN3                 12
+#define TEENSY_PIN4                 13
+#define TEENSY_PIN26                14
+#define TEENSY_PIN27                15
+#define TEENSY_PIN28                16
+#define TEENSY_PIN39                17
+#define PORTA_PIN18                 18
+#define PORTA_PIN19                 19
+#define PORTA_PIN20                 20
+#define PORTA_PIN21                 21
+#define PORTA_PIN22                 22
+#define PORTA_PIN23                 23
+#define PORTA_PIN24                 24
+#define PORTA_PIN25                 25
+#define TEENSY_PIN42                26
+#define PORTA_PIN27                 27
+#define TEENSY_PIN40                28
+#define TEENSY_PIN41                29
+#define PORTA_PIN30                 30
+#define PORTA_PIN31                 31
+
+#define TEENSY_PIN40_IOPORT  IOPORT1
+#define TEENSY_PIN41_IOPORT  IOPORT1
+#define TEENSY_PIN42_IOPORT  IOPORT1
+#define TEENSY_PIN3_IOPORT   IOPORT1
+#define TEENSY_PIN4_IOPORT   IOPORT1
+#define TEENSY_PIN25_IOPORT  IOPORT1
+#define TEENSY_PIN26_IOPORT  IOPORT1
+#define TEENSY_PIN27_IOPORT  IOPORT1
+#define TEENSY_PIN28_IOPORT  IOPORT1
+#define TEENSY_PIN39_IOPORT  IOPORT1
+
+#define TEENSY_PIN16                0
+#define TEENSY_PIN17                1
+#define TEENSY_PIN19                2
+#define TEENSY_PIN18                3
+#define TEENSY_PIN49                4
+#define TEENSY_PIN50                5
+#define PORTB_PIN6                  6
+#define PORTB_PIN7                  7
+#define PORTB_PIN8                  8
+#define PORTB_PIN9                  9
+#define TEENSY_PIN31                10
+#define TEENSY_PIN32                11
+#define PORTB_PIN12                 12
+#define PORTB_PIN13                 13
+#define PORTB_PIN14                 14
+#define PORTB_PIN15                 15
+#define TEENSY_PIN0                 16
+#define TEENSY_PIN1                 17
+#define TEENSY_PIN29                18
+#define TEENSY_PIN30                19
+#define TEENSY_PIN43                20
+#define TEENSY_PIN46                21
+#define TEENSY_PIN44                22
+#define TEENSY_PIN45                23
+#define PORTB_PIN24                 24
+#define PORTB_PIN25                 25
+#define PORTB_PIN26                 26
+#define PORTB_PIN27                 27
+#define PORTB_PIN28                 28
+#define PORTB_PIN29                 29
+#define PORTB_PIN30                 30
+#define PORTB_PIN31                 31
+
+#define TEENSY_PIN49_IOPORT  IOPORT2
+#define TEENSY_PIN50_IOPORT  IOPORT2
+#define TEENSY_PIN43_IOPORT  IOPORT2
+#define TEENSY_PIN44_IOPORT  IOPORT2
+#define TEENSY_PIN45_IOPORT  IOPORT2
+#define TEENSY_PIN46_IOPORT  IOPORT2
+#define TEENSY_PIN0_IOPORT   IOPORT2
+#define TEENSY_PIN1_IOPORT   IOPORT2
+#define TEENSY_PIN29_IOPORT  IOPORT2
+#define TEENSY_PIN30_IOPORT  IOPORT2
+#define TEENSY_PIN31_IOPORT  IOPORT2
+#define TEENSY_PIN32_IOPORT  IOPORT2
+#define TEENSY_PIN16_IOPORT  IOPORT2
+#define TEENSY_PIN17_IOPORT  IOPORT2
+#define TEENSY_PIN19_IOPORT  IOPORT2
+#define TEENSY_PIN18_IOPORT  IOPORT2
+
+#define TEENSY_PIN15                0
+#define TEENSY_PIN22                1
+#define TEENSY_PIN23                2
+#define TEENSY_PIN9                 3
+#define TEENSY_PIN10                4
+#define TEENSY_PIN13                5
+#define TEENSY_PIN11                6
+#define TEENSY_PIN12                7
+#define TEENSY_PIN35                8
+#define TEENSY_PIN36                9
+#define TEENSY_PIN37                10
+#define TEENSY_PIN38                11
+#define PORTC_PIN12                 12
+#define PORTC_PIN13                 13
+#define PORTC_PIN14                 14
+#define PORTC_PIN15                 15
+#define PORTC_PIN16                 16
+#define PORTC_PIN17                 17
+#define PORTC_PIN18                 18
+#define PORTC_PIN19                 19
+#define PORTC_PIN20                 20
+#define PORTC_PIN21                 21
+#define PORTC_PIN22                 22
+#define PORTC_PIN23                 23
+#define PORTC_PIN24                 24
+#define PORTC_PIN25                 25
+#define PORTC_PIN26                 26
+#define PORTC_PIN27                 27
+#define PORTC_PIN28                 28
+#define PORTC_PIN29                 29
+#define PORTC_PIN30                 30
+#define PORTC_PIN31                 31
+
+#define TEENSY_PIN9_IOPORT   IOPORT3
+#define TEENSY_PIN10_IOPORT  IOPORT3
+#define TEENSY_PIN11_IOPORT  IOPORT3
+#define TEENSY_PIN12_IOPORT  IOPORT3
+#define TEENSY_PIN35_IOPORT  IOPORT3
+#define TEENSY_PIN36_IOPORT  IOPORT3
+#define TEENSY_PIN37_IOPORT  IOPORT3
+#define TEENSY_PIN38_IOPORT  IOPORT3
+#define TEENSY_PIN13_IOPORT  IOPORT3
+#define TEENSY_PIN15_IOPORT  IOPORT3
+#define TEENSY_PIN22_IOPORT  IOPORT3
+#define TEENSY_PIN23_IOPORT  IOPORT3
+
+#define TEENSY_PIN2                 0
+#define TEENSY_PIN14                1
+#define TEENSY_PIN7                 2
+#define TEENSY_PIN8                 3
+#define TEENSY_PIN6                 4
+#define TEENSY_PIN20                5
+#define TEENSY_PIN21                6
+#define TEENSY_PIN5                 7
+#define TEENSY_PIN47                8
+#define TEENSY_PIN48                9
+#define PORTD_PIN10                 10
+#define TEENSY_PIN55                11
+#define TEENSY_PIN53                12
+#define TEENSY_PIN52                13
+#define TEENSY_PIN51                14
+#define TEENSY_PIN54                15
+#define PORTD_PIN16                 16
+#define PORTD_PIN17                 17
+#define PORTD_PIN18                 18
+#define PORTD_PIN19                 19
+#define PORTD_PIN20                 20
+#define PORTD_PIN21                 21
+#define PORTD_PIN22                 22
+#define PORTD_PIN23                 23
+#define PORTD_PIN24                 24
+#define PORTD_PIN25                 25
+#define PORTD_PIN26                 26
+#define PORTD_PIN27                 27
+#define PORTD_PIN28                 28
+#define PORTD_PIN29                 29
+#define PORTD_PIN30                 30
+#define PORTD_PIN31                 31
+
+#define TEENSY_PIN51_IOPORT  IOPORT4
+#define TEENSY_PIN52_IOPORT  IOPORT4
+#define TEENSY_PIN53_IOPORT  IOPORT4
+#define TEENSY_PIN54_IOPORT  IOPORT4
+#define TEENSY_PIN55_IOPORT  IOPORT4
+#define TEENSY_PIN47_IOPORT  IOPORT4
+#define TEENSY_PIN48_IOPORT  IOPORT4
+#define TEENSY_PIN2_IOPORT   IOPORT4
+#define TEENSY_PIN5_IOPORT   IOPORT4
+#define TEENSY_PIN6_IOPORT   IOPORT4
+#define TEENSY_PIN7_IOPORT   IOPORT4
+#define TEENSY_PIN8_IOPORT   IOPORT4
+#define TEENSY_PIN14_IOPORT  IOPORT4
+#define TEENSY_PIN20_IOPORT  IOPORT4
+#define TEENSY_PIN21_IOPORT  IOPORT4
+
+#define PORTE_PIN0                  0
+#define PORTE_PIN1                  1
+#define PORTE_PIN2                  2
+#define PORTE_PIN3                  3
+#define PORTE_PIN4                  4
+#define PORTE_PIN5                  5
+#define PORTE_PIN6                  6
+#define PORTE_PIN7                  7
+#define PORTE_PIN8                  8
+#define PORTE_PIN9                  9
+#define TEENSY_PIN56                10
+#define TEENSY_PIN57                11
+#define PORTE_PIN12                 12
+#define PORTE_PIN13                 13
+#define PORTE_PIN14                 14
+#define PORTE_PIN15                 15
+#define PORTE_PIN16                 16
+#define PORTE_PIN17                 17
+#define PORTE_PIN18                 18
+#define PORTE_PIN19                 19
+#define PORTE_PIN20                 20
+#define PORTE_PIN21                 21
+#define PORTE_PIN22                 22
+#define PORTE_PIN23                 23
+#define TEENSY_PIN33                24
+#define TEENSY_PIN34                25
+#define TEENSY_PIN24                26
+#define PORTE_PIN27                 27
+#define PORTE_PIN28                 28
+#define PORTE_PIN29                 29
+#define PORTE_PIN30                 30
+#define PORTE_PIN31                 31
+
+#define TEENSY_PIN56_IOPORT  IOPORT5
+#define TEENSY_PIN57_IOPORT  IOPORT5
+#define TEENSY_PIN24_IOPORT  IOPORT5
+#define TEENSY_PIN33_IOPORT  IOPORT5
+#define TEENSY_PIN34_IOPORT  IOPORT5
+
+
+#define LINE_PIN0           PAL_LINE(TEENSY_PIN0_IOPORT, TEENSY_PIN0)
+#define LINE_PIN1           PAL_LINE(TEENSY_PIN1_IOPORT, TEENSY_PIN1)
+#define LINE_PIN2           PAL_LINE(TEENSY_PIN2_IOPORT, TEENSY_PIN2)
+#define LINE_PIN3           PAL_LINE(TEENSY_PIN3_IOPORT, TEENSY_PIN3)
+#define LINE_PIN4           PAL_LINE(TEENSY_PIN4_IOPORT, TEENSY_PIN4)
+#define LINE_PIN5           PAL_LINE(TEENSY_PIN5_IOPORT, TEENSY_PIN5)
+#define LINE_PIN6           PAL_LINE(TEENSY_PIN6_IOPORT, TEENSY_PIN6)
+#define LINE_PIN7           PAL_LINE(TEENSY_PIN7_IOPORT, TEENSY_PIN7)
+#define LINE_PIN8           PAL_LINE(TEENSY_PIN8_IOPORT, TEENSY_PIN8)
+#define LINE_PIN9           PAL_LINE(TEENSY_PIN9_IOPORT, TEENSY_PIN9)
+#define LINE_PIN10          PAL_LINE(TEENSY_PIN10_IOPORT, TEENSY_PIN10)
+#define LINE_PIN11          PAL_LINE(TEENSY_PIN11_IOPORT, TEENSY_PIN11)
+#define LINE_PIN12          PAL_LINE(TEENSY_PIN12_IOPORT, TEENSY_PIN12)
+#define LINE_PIN13          PAL_LINE(TEENSY_PIN13_IOPORT, TEENSY_PIN13)
+#define LINE_PIN14          PAL_LINE(TEENSY_PIN14_IOPORT, TEENSY_PIN14)
+#define LINE_PIN15          PAL_LINE(TEENSY_PIN15_IOPORT, TEENSY_PIN15)
+#define LINE_PIN16          PAL_LINE(TEENSY_PIN16_IOPORT, TEENSY_PIN16)
+#define LINE_PIN17          PAL_LINE(TEENSY_PIN17_IOPORT, TEENSY_PIN17)
+#define LINE_PIN18          PAL_LINE(TEENSY_PIN18_IOPORT, TEENSY_PIN18)
+#define LINE_PIN19          PAL_LINE(TEENSY_PIN19_IOPORT, TEENSY_PIN19)
+#define LINE_PIN20          PAL_LINE(TEENSY_PIN20_IOPORT, TEENSY_PIN20)
+#define LINE_PIN21          PAL_LINE(TEENSY_PIN21_IOPORT, TEENSY_PIN21)
+#define LINE_PIN22          PAL_LINE(TEENSY_PIN22_IOPORT, TEENSY_PIN22)
+#define LINE_PIN23          PAL_LINE(TEENSY_PIN23_IOPORT, TEENSY_PIN23)
+#define LINE_PIN24          PAL_LINE(TEENSY_PIN24_IOPORT, TEENSY_PIN24)
+#define LINE_PIN25          PAL_LINE(TEENSY_PIN25_IOPORT, TEENSY_PIN25)
+#define LINE_PIN25          PAL_LINE(TEENSY_PIN25_IOPORT, TEENSY_PIN25)
+#define LINE_PIN26          PAL_LINE(TEENSY_PIN26_IOPORT, TEENSY_PIN26)
+#define LINE_PIN27          PAL_LINE(TEENSY_PIN27_IOPORT, TEENSY_PIN27)
+#define LINE_PIN28          PAL_LINE(TEENSY_PIN28_IOPORT, TEENSY_PIN28)
+#define LINE_PIN29          PAL_LINE(TEENSY_PIN29_IOPORT, TEENSY_PIN29)
+#define LINE_PIN30          PAL_LINE(TEENSY_PIN30_IOPORT, TEENSY_PIN30)
+#define LINE_PIN31          PAL_LINE(TEENSY_PIN31_IOPORT, TEENSY_PIN31)
+#define LINE_PIN32          PAL_LINE(TEENSY_PIN32_IOPORT, TEENSY_PIN32)
+#define LINE_PIN33          PAL_LINE(TEENSY_PIN33_IOPORT, TEENSY_PIN33)
+#define LINE_PIN34          PAL_LINE(TEENSY_PIN34_IOPORT, TEENSY_PIN34)
+#define LINE_PIN35          PAL_LINE(TEENSY_PIN35_IOPORT, TEENSY_PIN35)
+#define LINE_PIN36          PAL_LINE(TEENSY_PIN36_IOPORT, TEENSY_PIN36)
+#define LINE_PIN37          PAL_LINE(TEENSY_PIN37_IOPORT, TEENSY_PIN37)
+#define LINE_PIN38          PAL_LINE(TEENSY_PIN38_IOPORT, TEENSY_PIN38)
+#define LINE_PIN39          PAL_LINE(TEENSY_PIN39_IOPORT, TEENSY_PIN39)
+#define LINE_PIN40          PAL_LINE(TEENSY_PIN40_IOPORT, TEENSY_PIN40)
+#define LINE_PIN41          PAL_LINE(TEENSY_PIN41_IOPORT, TEENSY_PIN41)
+#define LINE_PIN42          PAL_LINE(TEENSY_PIN42_IOPORT, TEENSY_PIN42)
+#define LINE_PIN43          PAL_LINE(TEENSY_PIN43_IOPORT, TEENSY_PIN43)
+#define LINE_PIN44          PAL_LINE(TEENSY_PIN44_IOPORT, TEENSY_PIN44)
+#define LINE_PIN45          PAL_LINE(TEENSY_PIN45_IOPORT, TEENSY_PIN45)
+#define LINE_PIN46          PAL_LINE(TEENSY_PIN46_IOPORT, TEENSY_PIN46)
+#define LINE_PIN47          PAL_LINE(TEENSY_PIN47_IOPORT, TEENSY_PIN47)
+#define LINE_PIN48          PAL_LINE(TEENSY_PIN48_IOPORT, TEENSY_PIN48)
+#define LINE_PIN49          PAL_LINE(TEENSY_PIN49_IOPORT, TEENSY_PIN49)
+#define LINE_PIN50          PAL_LINE(TEENSY_PIN50_IOPORT, TEENSY_PIN50)
+#define LINE_PIN51          PAL_LINE(TEENSY_PIN51_IOPORT, TEENSY_PIN50)
+#define LINE_PIN52          PAL_LINE(TEENSY_PIN52_IOPORT, TEENSY_PIN52)
+#define LINE_PIN53          PAL_LINE(TEENSY_PIN53_IOPORT, TEENSY_PIN53)
+#define LINE_PIN54          PAL_LINE(TEENSY_PIN54_IOPORT, TEENSY_PIN54)
+#define LINE_PIN55          PAL_LINE(TEENSY_PIN55_IOPORT, TEENSY_PIN55)
+#define LINE_PIN56          PAL_LINE(TEENSY_PIN56_IOPORT, TEENSY_PIN56)
+#define LINE_PIN57          PAL_LINE(TEENSY_PIN57_IOPORT, TEENSY_PIN57)
+
+#define LINE_LED            LINE_PIN13
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+  void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
+#endif /* _BOARD_H_ */
-- 
cgit v1.2.3


From 457afa6202fe9f8e6accb65411629172bb32c41b Mon Sep 17 00:00:00 2001
From: Michael Walker <walkerstop@gmail.com>
Date: Wed, 2 May 2018 03:36:12 -0700
Subject: Remove duplication

---
 os/hal/ports/KINETIS/LLD/hal_usb_lld.h | 19 -------------------
 1 file changed, 19 deletions(-)

(limited to 'os')

diff --git a/os/hal/ports/KINETIS/LLD/hal_usb_lld.h b/os/hal/ports/KINETIS/LLD/hal_usb_lld.h
index ed65b3b..bd4eb39 100644
--- a/os/hal/ports/KINETIS/LLD/hal_usb_lld.h
+++ b/os/hal/ports/KINETIS/LLD/hal_usb_lld.h
@@ -355,25 +355,6 @@ struct USBDriver {
 /* Driver macros.                                                            */
 /*===========================================================================*/
 
-/**
- * @brief   Host wake-up procedure duration.
- */
-#if !defined(USB_HOST_WAKEUP_DURATION) || defined(__DOXYGEN__)
-#define USB_HOST_WAKEUP_DURATION            2
-#endif
-
-/**
- * @brief   Start of host wake-up procedure.
- *
- * @notapi
- */
-#define usb_lld_wakeup_host(usbp)                                           \
-  do{                                                                       \
-    USB0->CTL |= USBx_CTL_RESUME;                                     \
-    osalThreadSleepMilliseconds(USB_HOST_WAKEUP_DURATION);                  \
-    USB0->CTL &= ~USBx_CTL_RESUME;                                    \
-  } while (false)
-
 /**
  * @brief   Returns the current frame number.
  *
-- 
cgit v1.2.3


From 1fefdf78fef847c27d3768cc78de0ee901889465 Mon Sep 17 00:00:00 2001
From: Michael Walker <walkerstop@gmail.com>
Date: Wed, 2 May 2018 03:47:26 -0700
Subject: Remove duplicate code already in upstream master and add include dir

---
 os/common/startup/ARMCMx/compilers/GCC/mk/startup_nrf52.mk | 3 ++-
 os/hal/ports/KINETIS/LLD/hal_pal_lld.h                     | 5 -----
 2 files changed, 2 insertions(+), 6 deletions(-)

(limited to 'os')

diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_nrf52.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_nrf52.mk
index 693ae67..450ec41 100644
--- a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_nrf52.mk
+++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_nrf52.mk
@@ -5,6 +5,7 @@ STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \
 STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S
 
 STARTUPINC = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/NRF52832 \
-             $(CHIBIOS)/os/common/ext/CMSIS/include
+             $(CHIBIOS)/os/common/ext/CMSIS/include \
+             $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include
 
 STARTUPLD  = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld
diff --git a/os/hal/ports/KINETIS/LLD/hal_pal_lld.h b/os/hal/ports/KINETIS/LLD/hal_pal_lld.h
index 6129f69..833d95e 100644
--- a/os/hal/ports/KINETIS/LLD/hal_pal_lld.h
+++ b/os/hal/ports/KINETIS/LLD/hal_pal_lld.h
@@ -82,11 +82,6 @@ typedef uint32_t ioline_t;
  */
 typedef GPIO_TypeDef *ioportid_t;
 
-/**
- * @brief   Type of an pad identifier.
- */
-typedef uint32_t iopadid_t;
-
 /**
  * @brief   Port Configuration.
  * @details This structure stores the configuration parameters of all pads
-- 
cgit v1.2.3


From 0f3af19758181dde931d3889ccc8eef0f00b4e39 Mon Sep 17 00:00:00 2001
From: Michael Walker <walkerstop@gmail.com>
Date: Wed, 2 May 2018 05:15:22 -0700
Subject: Disable MPU by default

---
 os/hal/ports/KINETIS/MK66F18/hal_lld.c | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'os')

diff --git a/os/hal/ports/KINETIS/MK66F18/hal_lld.c b/os/hal/ports/KINETIS/MK66F18/hal_lld.c
index 857f384..bb8991a 100644
--- a/os/hal/ports/KINETIS/MK66F18/hal_lld.c
+++ b/os/hal/ports/KINETIS/MK66F18/hal_lld.c
@@ -81,6 +81,11 @@ const uint8_t _cfm[0x10] = {
  */
 void hal_lld_init(void) {
 
+#if defined(MK66F18)
+  /* Disable the MPU by default */
+  SYSMPU->CESR &= ~SYSMPU_CESR_VLD_MASK;
+#endif
+
 }
 
 /**
-- 
cgit v1.2.3


From 5bec0d7abc33169ef468e194297853a4d7f6ba79 Mon Sep 17 00:00:00 2001
From: Michael Walker <walkerstop@gmail.com>
Date: Wed, 2 May 2018 06:49:29 -0700
Subject: Always use IRC48M clock for USB on MK66F18

---
 os/hal/ports/KINETIS/LLD/hal_usb_lld.c | 11 ++++++-----
 1 file changed, 6 insertions(+), 5 deletions(-)

(limited to 'os')

diff --git a/os/hal/ports/KINETIS/LLD/hal_usb_lld.c b/os/hal/ports/KINETIS/LLD/hal_usb_lld.c
index fee91c5..694f5e2 100644
--- a/os/hal/ports/KINETIS/LLD/hal_usb_lld.c
+++ b/os/hal/ports/KINETIS/LLD/hal_usb_lld.c
@@ -405,11 +405,6 @@ void usb_lld_init(void) {
   /* MCGOUTCLK is the SYSCLK frequency, so don't divide for USB clock */
   SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0);
 
-#if defined(MK66F18)
-  /* Switch from default MCGPLLCLK to IRC48M for USB */
-  SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_SET(3);
-#endif
-
 #elif KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE
 
   #define KINETIS_USBCLK_FREQUENCY 48000000UL
@@ -429,6 +424,12 @@ void usb_lld_init(void) {
 #error USB clock setting not implemented for this KINETIS_MCG_MODE
 #endif /* KINETIS_MCG_MODE == ... */
 
+#if defined(MK66F18)
+  /* Switch from default MCGPLLCLK to IRC48M for USB */
+  SIM->CLKDIV2 = SIM_CLKDIV2_USBDIV(0);
+  SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_SET(3);
+#endif
+
 #elif defined(KL25) || defined (KL26) || defined(KL27)
 
   /* No extra clock dividers for USB clock */
-- 
cgit v1.2.3


From 8f7e1d18b943d1e2ba808f9a8e1e79cc78b6044e Mon Sep 17 00:00:00 2001
From: Michael Walker <walkerstop@gmail.com>
Date: Wed, 2 May 2018 07:53:01 -0700
Subject: Always use IRC48M clock for USB on MK66F18

---
 os/hal/ports/KINETIS/LLD/hal_usb_lld.c | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'os')

diff --git a/os/hal/ports/KINETIS/LLD/hal_usb_lld.c b/os/hal/ports/KINETIS/LLD/hal_usb_lld.c
index 694f5e2..a01b92e 100644
--- a/os/hal/ports/KINETIS/LLD/hal_usb_lld.c
+++ b/os/hal/ports/KINETIS/LLD/hal_usb_lld.c
@@ -407,6 +407,8 @@ void usb_lld_init(void) {
 
 #elif KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE
 
+#if !defined(MK66F18)
+  /* Note:  We don't need this for MK66F18, we can use IRC48M clock for USB */
   #define KINETIS_USBCLK_FREQUENCY 48000000UL
   uint32_t i,j;
   for(i=0; i < 2; i++) {
@@ -419,6 +421,7 @@ void usb_lld_init(void) {
   }
   usbfrac_match_found:
   osalDbgAssert(i<2 && j <8,"USB Init error");
+#endif
 
 #else /* KINETIS_MCG_MODE == KINETIS_MCG_MODE_PEE */
 #error USB clock setting not implemented for this KINETIS_MCG_MODE
-- 
cgit v1.2.3


From f4b640014d7b042e80dfaec520d3a02fb7220dfe Mon Sep 17 00:00:00 2001
From: Michael Walker <walkerstop@gmail.com>
Date: Thu, 3 May 2018 15:17:52 -0700
Subject: Correct register definitions for MK66F18 for LPTMR and FlexRAM

---
 os/common/ext/CMSIS/KINETIS/MK66F18.h           | 96 ++++++++++++++-----------
 os/hal/ports/KINETIS/MK66F18/kinetis_registry.h |  3 +
 2 files changed, 57 insertions(+), 42 deletions(-)

(limited to 'os')

diff --git a/os/common/ext/CMSIS/KINETIS/MK66F18.h b/os/common/ext/CMSIS/KINETIS/MK66F18.h
index c016c30..bfe9f80 100644
--- a/os/common/ext/CMSIS/KINETIS/MK66F18.h
+++ b/os/common/ext/CMSIS/KINETIS/MK66F18.h
@@ -6738,12 +6738,15 @@ typedef struct {
 #define FTFE_FSTAT_FPVIOL_MASK                   (0x10U)
 #define FTFE_FSTAT_FPVIOL_SHIFT                  (4U)
 #define FTFE_FSTAT_FPVIOL(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_FPVIOL_SHIFT)) & FTFE_FSTAT_FPVIOL_MASK)
+#define FTFL_FSTAT_FPVIOL                        FTFE_FSTAT_FPVIOL(1)
 #define FTFE_FSTAT_ACCERR_MASK                   (0x20U)
 #define FTFE_FSTAT_ACCERR_SHIFT                  (5U)
 #define FTFE_FSTAT_ACCERR(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_ACCERR_SHIFT)) & FTFE_FSTAT_ACCERR_MASK)
+#define FTFL_FSTAT_ACCERR                        FTFE_FSTAT_ACCERR(1)
 #define FTFE_FSTAT_RDCOLERR_MASK                 (0x40U)
 #define FTFE_FSTAT_RDCOLERR_SHIFT                (6U)
 #define FTFE_FSTAT_RDCOLERR(x)                   (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_RDCOLERR_SHIFT)) & FTFE_FSTAT_RDCOLERR_MASK)
+#define FTFL_FSTAT_RDCOLERR                      FTFE_FSTAT_RDCOLERR(1)
 #define FTFE_FSTAT_CCIF_MASK                     (0x80U)
 #define FTFE_FSTAT_CCIF_SHIFT                    (7U)
 #define FTFE_FSTAT_CCIF(x)                       (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_CCIF_SHIFT)) & FTFE_FSTAT_CCIF_MASK)
@@ -6752,9 +6755,11 @@ typedef struct {
 #define FTFE_FCNFG_EEERDY_MASK                   (0x1U)
 #define FTFE_FCNFG_EEERDY_SHIFT                  (0U)
 #define FTFE_FCNFG_EEERDY(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_EEERDY_SHIFT)) & FTFE_FCNFG_EEERDY_MASK)
+#define FTFL_FCNFG_EEERDY                        FTFE_FCNFG_EEERDY(1)
 #define FTFE_FCNFG_RAMRDY_MASK                   (0x2U)
 #define FTFE_FCNFG_RAMRDY_SHIFT                  (1U)
 #define FTFE_FCNFG_RAMRDY(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RAMRDY_SHIFT)) & FTFE_FCNFG_RAMRDY_MASK)
+#define FTFL_FCNFG_RAMRDY                        FTFE_FCNFG_RAMRDY(1)
 #define FTFE_FCNFG_PFLSH_MASK                    (0x4U)
 #define FTFE_FCNFG_PFLSH_SHIFT                   (2U)
 #define FTFE_FCNFG_PFLSH(x)                      (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_PFLSH_SHIFT)) & FTFE_FCNFG_PFLSH_MASK)
@@ -6984,6 +6989,7 @@ typedef struct {
 #define FTFE_BASE                                (0x40020000u)
 /** Peripheral FTFE base pointer */
 #define FTFE                                     ((FTFE_Type *)FTFE_BASE)
+#define FTFL                                     ((FTFE_Type *)FTFE_BASE)
 /** Array initializer of FTFE peripheral base addresses */
 #define FTFE_BASE_ADDRS                          { FTFE_BASE }
 /** Array initializer of FTFE peripheral base pointers */
@@ -8995,48 +9001,51 @@ typedef struct {
  */
 
 /*! @name CSR - Low Power Timer Control Status Register */
-#define LPTMR_CSR_TEN_MASK                       (0x1U)
-#define LPTMR_CSR_TEN_SHIFT                      (0U)
-#define LPTMR_CSR_TEN(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
-#define LPTMR_CSR_TMS_MASK                       (0x2U)
-#define LPTMR_CSR_TMS_SHIFT                      (1U)
-#define LPTMR_CSR_TMS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
-#define LPTMR_CSR_TFC_MASK                       (0x4U)
-#define LPTMR_CSR_TFC_SHIFT                      (2U)
-#define LPTMR_CSR_TFC(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
-#define LPTMR_CSR_TPP_MASK                       (0x8U)
-#define LPTMR_CSR_TPP_SHIFT                      (3U)
-#define LPTMR_CSR_TPP(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
-#define LPTMR_CSR_TPS_MASK                       (0x30U)
-#define LPTMR_CSR_TPS_SHIFT                      (4U)
-#define LPTMR_CSR_TPS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
-#define LPTMR_CSR_TIE_MASK                       (0x40U)
-#define LPTMR_CSR_TIE_SHIFT                      (6U)
-#define LPTMR_CSR_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
-#define LPTMR_CSR_TCF_MASK                       (0x80U)
-#define LPTMR_CSR_TCF_SHIFT                      (7U)
-#define LPTMR_CSR_TCF(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
+#define LPTMRx_CSR_TEN_MASK                       (0x1U)
+#define LPTMRx_CSR_TEN_SHIFT                      (0U)
+#define LPTMRx_CSR_TEN_SET(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMRx_CSR_TEN_SHIFT)) & LPTMRx_CSR_TEN_MASK)
+#define LPTMRx_CSR_TEN                            LPTMRx_CSR_TEN_SET(1)
+#define LPTMRx_CSR_TMS_MASK                       (0x2U)
+#define LPTMRx_CSR_TMS_SHIFT                      (1U)
+#define LPTMRx_CSR_TMS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMRx_CSR_TMS_SHIFT)) & LPTMRx_CSR_TMS_MASK)
+#define LPTMRx_CSR_TFC_MASK                       (0x4U)
+#define LPTMRx_CSR_TFC_SHIFT                      (2U)
+#define LPTMRx_CSR_TFC(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMRx_CSR_TFC_SHIFT)) & LPTMRx_CSR_TFC_MASK)
+#define LPTMRx_CSR_TPP_MASK                       (0x8U)
+#define LPTMRx_CSR_TPP_SHIFT                      (3U)
+#define LPTMRx_CSR_TPP(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMRx_CSR_TPP_SHIFT)) & LPTMRx_CSR_TPP_MASK)
+#define LPTMRx_CSR_TPS_MASK                       (0x30U)
+#define LPTMRx_CSR_TPS_SHIFT                      (4U)
+#define LPTMRx_CSR_TPS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMRx_CSR_TPS_SHIFT)) & LPTMRx_CSR_TPS_MASK)
+#define LPTMRx_CSR_TIE_MASK                       (0x40U)
+#define LPTMRx_CSR_TIE_SHIFT                      (6U)
+#define LPTMRx_CSR_TIE_SET(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMRx_CSR_TIE_SHIFT)) & LPTMRx_CSR_TIE_MASK)
+#define LPTMRx_CSR_TIE                            LPTMRx_CSR_TIE_SET(1)
+#define LPTMRx_CSR_TCF_MASK                       (0x80U)
+#define LPTMRx_CSR_TCF_SHIFT                      (7U)
+#define LPTMRx_CSR_TCF_SET(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMRx_CSR_TCF_SHIFT)) & LPTMRx_CSR_TCF_MASK)
+#define LPTMRx_CSR_TCF                            LPTMRx_CSR_TCF_SET(1)
 
 /*! @name PSR - Low Power Timer Prescale Register */
-#define LPTMR_PSR_PCS_MASK                       (0x3U)
-#define LPTMR_PSR_PCS_SHIFT                      (0U)
-#define LPTMR_PSR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
-#define LPTMR_PSR_PBYP_MASK                      (0x4U)
-#define LPTMR_PSR_PBYP_SHIFT                     (2U)
-#define LPTMR_PSR_PBYP(x)                        (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
-#define LPTMR_PSR_PRESCALE_MASK                  (0x78U)
-#define LPTMR_PSR_PRESCALE_SHIFT                 (3U)
-#define LPTMR_PSR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
+#define LPTMRx_PSR_PCS_MASK                       (0x3U)
+#define LPTMRx_PSR_PCS_SHIFT                      (0U)
+#define LPTMRx_PSR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMRx_PSR_PCS_SHIFT)) & LPTMRx_PSR_PCS_MASK)
+#define LPTMRx_PSR_PBYP_MASK                      (0x4U)
+#define LPTMRx_PSR_PBYP_SHIFT                     (2U)
+#define LPTMRx_PSR_PBYP(x)                        (((uint32_t)(((uint32_t)(x)) << LPTMRx_PSR_PBYP_SHIFT)) & LPTMRx_PSR_PBYP_MASK)
+#define LPTMRx_PSR_PRESCALE_MASK                  (0x78U)
+ #define LPTMRx_PSR_PRESCALE_SHIFT                 (3U)
+#define LPTMRx_PSR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x)) << LPTMRx_PSR_PRESCALE_SHIFT)) & LPTMRx_PSR_PRESCALE_MASK)
 
 /*! @name CMR - Low Power Timer Compare Register */
-#define LPTMR_CMR_COMPARE_MASK                   (0xFFFFU)
-#define LPTMR_CMR_COMPARE_SHIFT                  (0U)
-#define LPTMR_CMR_COMPARE(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
+#define LPTMRx_CMR_COMPARE_MASK                   (0xFFFFU)
+#define LPTMRx_CMR_COMPARE_SHIFT                  (0U)
+#define LPTMRx_CMR_COMPARE(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
 
 /*! @name CNR - Low Power Timer Counter Register */
-#define LPTMR_CNR_COUNTER_MASK                   (0xFFFFU)
-#define LPTMR_CNR_COUNTER_SHIFT                  (0U)
-#define LPTMR_CNR_COUNTER(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
+#define LPTMRx_CNR_COUNTER_MASK                   (0xFFFFU)
+#define LPTMRx_CNR_COUNTER_SHIFT                  (0U)
+#define LPTMRx_CNR_COUNTER(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
 
 
 /*!
@@ -9050,11 +9059,11 @@ typedef struct {
 /** Peripheral LPTMR0 base pointer */
 #define LPTMR0                                   ((LPTMR_Type *)LPTMR0_BASE)
 /** Array initializer of LPTMR peripheral base addresses */
-#define LPTMR_BASE_ADDRS                         { LPTMR0_BASE }
+#define LPTMRx_BASE_ADDRS                         { LPTMR0_BASE }
 /** Array initializer of LPTMR peripheral base pointers */
-#define LPTMR_BASE_PTRS                          { LPTMR0 }
+#define LPTMRx_BASE_PTRS                          { LPTMR0 }
 /** Interrupt vectors for the LPTMR peripheral type */
-#define LPTMR_IRQS                               { LPTMR0_IRQn }
+#define LPTMRx_IRQS                               { LPTMR0_IRQn }
 
 /*!
  * @}
@@ -9421,7 +9430,8 @@ typedef struct {
 #define MCG_C1_IREFSTEN(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
 #define MCG_C1_IRCLKEN_MASK                      (0x2U)
 #define MCG_C1_IRCLKEN_SHIFT                     (1U)
-#define MCG_C1_IRCLKEN(x)                        (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
+#define MCG_C1_IRCLKEN_SET(x)                    (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
+#define MCG_C1_IRCLKEN                           MCG_C1_IRCLKEN_SET(1)
 #define MCG_C1_IREFS_MASK                        (0x4U)
 #define MCG_C1_IREFS_SHIFT                       (2U)
 #define MCG_C1_IREFS(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
@@ -9435,7 +9445,8 @@ typedef struct {
 /*! @name C2 - MCG Control 2 Register */
 #define MCG_C2_IRCS_MASK                         (0x1U)
 #define MCG_C2_IRCS_SHIFT                        (0U)
-#define MCG_C2_IRCS(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
+#define MCG_C2_IRCS_SET(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
+#define MCG_C2_IRCS                              MCG_C2_IRCS_SET(1)
 #define MCG_C2_LP_MASK                           (0x2U)
 #define MCG_C2_LP_SHIFT                          (1U)
 #define MCG_C2_LP(x)                             (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
@@ -12403,7 +12414,8 @@ typedef struct {
 /*! @name SCGC5 - System Clock Gating Control Register 5 */
 #define SIM_SCGC5_LPTMR_MASK                     (0x1U)
 #define SIM_SCGC5_LPTMR_SHIFT                    (0U)
-#define SIM_SCGC5_LPTMR(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
+#define SIM_SCGC5_LPTMR_SET(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
+#define SIM_SCGC5_LPTMR                          SIM_SCGC5_LPTMR_SET(1)
 #define SIM_SCGC5_TSI_MASK                       (0x20U)
 #define SIM_SCGC5_TSI_SHIFT                      (5U)
 #define SIM_SCGC5_TSI(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK)
diff --git a/os/hal/ports/KINETIS/MK66F18/kinetis_registry.h b/os/hal/ports/KINETIS/MK66F18/kinetis_registry.h
index f733244..6634b10 100644
--- a/os/hal/ports/KINETIS/MK66F18/kinetis_registry.h
+++ b/os/hal/ports/KINETIS/MK66F18/kinetis_registry.h
@@ -158,6 +158,9 @@
 #define KINETIS_USB0_IS_USBOTG      TRUE
 #define KINETIS_HAS_USB_CLOCK_RECOVERY TRUE
 
+/* LPTMR attributes.*/
+#define KINETIS_LPTMR0_IRQ_VECTOR   Vector128
+
 /** @} */
 
 #endif /* KINETIS_REGISTRY_H_ */
-- 
cgit v1.2.3


From 619d45c0ffc02ca122f5ec7c34a1d6f82060fb7d Mon Sep 17 00:00:00 2001
From: Michael Walker <walkerstop@gmail.com>
Date: Thu, 3 May 2018 18:41:14 -0700
Subject: Fix MK66F18 compilation for the following HALs: Serial, I2C, EXT,
 ADC, GPT, PWM, SPI

---
 os/common/ext/CMSIS/KINETIS/MK66F18.h              | 12802 ++++++++++++-------
 .../startup/ARMCMx/compilers/GCC/ld/MK66FX1M0.ld   |    22 +-
 os/hal/ports/KINETIS/LLD/hal_i2c_lld.c             |     6 +
 os/hal/ports/KINETIS/LLD/hal_sdc_lld.c             |    18 +-
 os/hal/ports/KINETIS/LLD/hal_serial_lld.c          |     2 +-
 os/hal/ports/KINETIS/MK66F18/hal_lld.c             |     4 +-
 os/hal/ports/KINETIS/MK66F18/platform.mk           |     1 +
 7 files changed, 8218 insertions(+), 4637 deletions(-)

(limited to 'os')

diff --git a/os/common/ext/CMSIS/KINETIS/MK66F18.h b/os/common/ext/CMSIS/KINETIS/MK66F18.h
index bfe9f80..432944f 100644
--- a/os/common/ext/CMSIS/KINETIS/MK66F18.h
+++ b/os/common/ext/CMSIS/KINETIS/MK66F18.h
@@ -75,6 +75,8 @@
 **         Renamed interrupt vector LLW to LLWU.
 **     - rev. 3.0 (2015-03-25)
 **         Registers updated according to the reference manual revision 1, March 2015
+**     - Revised 2018-05-04 by Michael Walker <walkerstop@gmail.com> to support ChibiOS LLD HAL
+**         Register names and other names updated to match other Kinetis definitions for other MCUs
 **
 ** ###################################################################
 */
@@ -147,6 +149,23 @@
 /** Interrupt Number Definitions */
 #define NUMBER_OF_INT_VECTORS 116                /**< Number of interrupts in the Vector table */
 
+#define DMA0_IRQn   DMA0_DMA16_IRQn
+#define DMA1_IRQn   DMA1_DMA17_IRQn
+#define DMA2_IRQn   DMA2_DMA18_IRQn
+#define DMA3_IRQn   DMA3_DMA19_IRQn
+#define DMA4_IRQn   DMA4_DMA20_IRQn
+#define DMA5_IRQn   DMA5_DMA21_IRQn
+#define DMA6_IRQn   DMA6_DMA22_IRQn
+#define DMA7_IRQn   DMA7_DMA23_IRQn
+#define DMA8_IRQn   DMA8_DMA24_IRQn
+#define DMA9_IRQn   DMA9_DMA25_IRQn
+#define DMA10_IRQn  DMA10_DMA26_IRQn
+#define DMA11_IRQn  DMA11_DMA27_IRQn
+#define DMA12_IRQn  DMA12_DMA28_IRQn
+#define DMA13_IRQn  DMA13_DMA29_IRQn
+#define DMA14_IRQn  DMA14_DMA30_IRQn
+#define DMA15_IRQn  DMA15_DMA21_IRQn
+
 typedef enum IRQn {
   /* Auxiliary constants */
   NotAvail_IRQn                = -128,             /**< Not available device specific interrupt */
@@ -194,14 +213,14 @@ typedef enum IRQn {
   I2S0_Tx_IRQn                 = 28,               /**< I2S0 transmit interrupt */
   I2S0_Rx_IRQn                 = 29,               /**< I2S0 receive interrupt */
   Reserved46_IRQn              = 30,               /**< Reserved interrupt 46 */
-  UART0_RX_TX_IRQn             = 31,               /**< UART0 Receive/Transmit interrupt */
-  UART0_ERR_IRQn               = 32,               /**< UART0 Error interrupt */
-  UART1_RX_TX_IRQn             = 33,               /**< UART1 Receive/Transmit interrupt */
-  UART1_ERR_IRQn               = 34,               /**< UART1 Error interrupt */
-  UART2_RX_TX_IRQn             = 35,               /**< UART2 Receive/Transmit interrupt */
-  UART2_ERR_IRQn               = 36,               /**< UART2 Error interrupt */
-  UART3_RX_TX_IRQn             = 37,               /**< UART3 Receive/Transmit interrupt */
-  UART3_ERR_IRQn               = 38,               /**< UART3 Error interrupt */
+  UART0Status_IRQn             = 31,               /**< UART0 Receive/Transmit interrupt */
+  UART0Error_IRQn              = 32,               /**< UART0 Error interrupt */
+  UART1Status_IRQn             = 33,               /**< UART1 Receive/Transmit interrupt */
+  UART1Error_IRQn              = 34,               /**< UART1 Error interrupt */
+  UART2Status_IRQn             = 35,               /**< UART2 Receive/Transmit interrupt */
+  UART2Error_IRQn              = 36,               /**< UART2 Error interrupt */
+  UART3Status_IRQn             = 37,               /**< UART3 Receive/Transmit interrupt */
+  UART3Error_IRQn              = 38,               /**< UART3 Error interrupt */
   ADC0_IRQn                    = 39,               /**< ADC0 interrupt */
   CMP0_IRQn                    = 40,               /**< CMP0 interrupt */
   CMP1_IRQn                    = 41,               /**< CMP1 interrupt */
@@ -211,10 +230,10 @@ typedef enum IRQn {
   CMT_IRQn                     = 45,               /**< CMT interrupt */
   RTC_IRQn                     = 46,               /**< RTC interrupt */
   RTC_Seconds_IRQn             = 47,               /**< RTC seconds interrupt */
-  PIT0_IRQn                    = 48,               /**< PIT timer channel 0 interrupt */
-  PIT1_IRQn                    = 49,               /**< PIT timer channel 1 interrupt */
-  PIT2_IRQn                    = 50,               /**< PIT timer channel 2 interrupt */
-  PIT3_IRQn                    = 51,               /**< PIT timer channel 3 interrupt */
+  PITChannel0_IRQn             = 48,               /**< PIT timer channel 0 interrupt */
+  PITChannel1_IRQn             = 49,               /**< PIT timer channel 1 interrupt */
+  PITChannel2_IRQn             = 50,               /**< PIT timer channel 2 interrupt */
+  PITChannel3_IRQn             = 51,               /**< PIT timer channel 3 interrupt */
   PDB0_IRQn                    = 52,               /**< PDB0 Interrupt */
   USB_OTG_IRQn                 = 53,               /**< USB0 interrupt */
   USBDCD_IRQn                  = 54,               /**< USBDCD Interrupt */
@@ -222,15 +241,15 @@ typedef enum IRQn {
   DAC0_IRQn                    = 56,               /**< DAC0 interrupt */
   MCG_IRQn                     = 57,               /**< MCG Interrupt */
   LPTMR0_IRQn                  = 58,               /**< LPTimer interrupt */
-  PORTA_IRQn                   = 59,               /**< Port A interrupt */
-  PORTB_IRQn                   = 60,               /**< Port B interrupt */
-  PORTC_IRQn                   = 61,               /**< Port C interrupt */
-  PORTD_IRQn                   = 62,               /**< Port D interrupt */
-  PORTE_IRQn                   = 63,               /**< Port E interrupt */
+  PINA_IRQn                    = 59,               /**< Port A interrupt */
+  PINB_IRQn                    = 60,               /**< Port B interrupt */
+  PINC_IRQn                    = 61,               /**< Port C interrupt */
+  PIND_IRQn                    = 62,               /**< Port D interrupt */
+  PINE_IRQn                    = 63,               /**< Port E interrupt */
   SWI_IRQn                     = 64,               /**< Software interrupt */
   SPI2_IRQn                    = 65,               /**< SPI2 Interrupt */
-  UART4_RX_TX_IRQn             = 66,               /**< UART4 Receive/Transmit interrupt */
-  UART4_ERR_IRQn               = 67,               /**< UART4 Error interrupt */
+  UART4Status_IRQn             = 66,               /**< UART4 Receive/Transmit interrupt */
+  UART4Error_IRQn              = 67,               /**< UART4 Error interrupt */
   Reserved84_IRQn              = 68,               /**< Reserved interrupt 84 */
   Reserved85_IRQn              = 69,               /**< Reserved interrupt 85 */
   CMP2_IRQn                    = 70,               /**< CMP2 interrupt */
@@ -453,16 +472,18 @@ typedef enum _dma_request_source
    ---------------------------------------------------------------------------- */
 
 /*!
- * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @addtogroup ADCx_Peripheral_Access_Layer ADC Peripheral Access Layer
  * @{
  */
 
 /** ADC - Register Layout Typedef */
 typedef struct {
-  __IO uint32_t SC1[2];                            /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
+  __IO uint32_t SC1A;                            /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
+  __IO uint32_t SC1B;                            /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
   __IO uint32_t CFG1;                              /**< ADC Configuration Register 1, offset: 0x8 */
   __IO uint32_t CFG2;                              /**< ADC Configuration Register 2, offset: 0xC */
-  __I  uint32_t R[2];                              /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
+  __I  uint32_t RA;                              /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
+  __I  uint32_t RB;                              /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
   __IO uint32_t CV1;                               /**< Compare Value Registers, offset: 0x18 */
   __IO uint32_t CV2;                               /**< Compare Value Registers, offset: 0x1C */
   __IO uint32_t SC2;                               /**< Status and Control Register 2, offset: 0x20 */
@@ -485,233 +506,274 @@ typedef struct {
   __IO uint32_t CLM2;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
   __IO uint32_t CLM1;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
   __IO uint32_t CLM0;                              /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
-} ADC_Type;
+} ADC_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- ADC Register Masks
    ---------------------------------------------------------------------------- */
 
 /*!
- * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @addtogroup ADCx_Register_Masks ADC Register Masks
  * @{
  */
 
 /*! @name SC1 - ADC Status and Control Registers 1 */
-#define ADC_SC1_ADCH_MASK                        (0x1FU)
-#define ADC_SC1_ADCH_SHIFT                       (0U)
-#define ADC_SC1_ADCH(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
-#define ADC_SC1_DIFF_MASK                        (0x20U)
-#define ADC_SC1_DIFF_SHIFT                       (5U)
-#define ADC_SC1_DIFF(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
-#define ADC_SC1_AIEN_MASK                        (0x40U)
-#define ADC_SC1_AIEN_SHIFT                       (6U)
-#define ADC_SC1_AIEN(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
-#define ADC_SC1_COCO_MASK                        (0x80U)
-#define ADC_SC1_COCO_SHIFT                       (7U)
-#define ADC_SC1_COCO(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
-
-/* The count of ADC_SC1 */
-#define ADC_SC1_COUNT                            (2U)
+#define ADCx_SC1n_ADCH_MASK                        (0x1FU)
+#define ADCx_SC1n_ADCH_SHIFT                       (0U)
+#define ADCx_SC1n_ADCH(x)                          (((uint32_t)(((uint32_t)(x)) << ADCx_SC1n_ADCH_SHIFT)) & ADCx_SC1n_ADCH_MASK)
+#define ADCx_SC1n_DIFF_MASK                        (0x20U)
+#define ADCx_SC1n_DIFF_SHIFT                       (5U)
+#define ADCx_SC1n_DIFF_SET(x)                      (((uint32_t)(((uint32_t)(x)) << ADCx_SC1n_DIFF_SHIFT)) & ADCx_SC1n_DIFF_MASK)
+#define ADCx_SC1n_DIFF ADCx_SC1n_DIFF_MASK
+#define ADCx_SC1n_AIEN_MASK                        (0x40U)
+#define ADCx_SC1n_AIEN_SHIFT                       (6U)
+#define ADCx_SC1n_AIEN_SET(x)                      (((uint32_t)(((uint32_t)(x)) << ADCx_SC1n_AIEN_SHIFT)) & ADCx_SC1n_AIEN_MASK)
+#define ADCx_SC1n_AIEN ADCx_SC1n_AIEN_MASK
+#define ADCx_SC1n_COCO_MASK                        (0x80U)
+#define ADCx_SC1n_COCO_SHIFT                       (7U)
+#define ADCx_SC1n_COCO_SET(x)                      (((uint32_t)(((uint32_t)(x)) << ADCx_SC1n_COCO_SHIFT)) & ADCx_SC1n_COCO_MASK)
+#define ADCx_SC1n_COCO ADCx_SC1n_COCO_MASK
+
+/* The count of ADCx_SC1n */
+#define ADCx_SC1n_COUNT                            (2U)
 
 /*! @name CFG1 - ADC Configuration Register 1 */
-#define ADC_CFG1_ADICLK_MASK                     (0x3U)
-#define ADC_CFG1_ADICLK_SHIFT                    (0U)
-#define ADC_CFG1_ADICLK(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
-#define ADC_CFG1_MODE_MASK                       (0xCU)
-#define ADC_CFG1_MODE_SHIFT                      (2U)
-#define ADC_CFG1_MODE(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
-#define ADC_CFG1_ADLSMP_MASK                     (0x10U)
-#define ADC_CFG1_ADLSMP_SHIFT                    (4U)
-#define ADC_CFG1_ADLSMP(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
-#define ADC_CFG1_ADIV_MASK                       (0x60U)
-#define ADC_CFG1_ADIV_SHIFT                      (5U)
-#define ADC_CFG1_ADIV(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
-#define ADC_CFG1_ADLPC_MASK                      (0x80U)
-#define ADC_CFG1_ADLPC_SHIFT                     (7U)
-#define ADC_CFG1_ADLPC(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
+#define ADCx_CFG1_ADICLK_MASK                     (0x3U)
+#define ADCx_CFG1_ADICLK_SHIFT                    (0U)
+#define ADCx_CFG1_ADICLK(x)                       (((uint32_t)(((uint32_t)(x)) << ADCx_CFG1_ADICLK_SHIFT)) & ADCx_CFG1_ADICLK_MASK)
+#define ADCx_CFG1_MODE_MASK                       (0xCU)
+#define ADCx_CFG1_MODE_SHIFT                      (2U)
+#define ADCx_CFG1_MODE_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_CFG1_MODE_SHIFT)) & ADCx_CFG1_MODE_MASK)
+#define ADCx_CFG1_MODE ADCx_CFG1_MODE_MASK
+#define ADCx_CFG1_ADLSMP_MASK                     (0x10U)
+#define ADCx_CFG1_ADLSMP_SHIFT                    (4U)
+#define ADCx_CFG1_ADLSMP_SET(x)                   (((uint32_t)(((uint32_t)(x)) << ADCx_CFG1_ADLSMP_SHIFT)) & ADCx_CFG1_ADLSMP_MASK)
+#define ADCx_CFG1_ADLSMP ADCx_CFG1_ADLSMP_MASK
+#define ADCx_CFG1_ADIV_MASK                       (0x60U)
+#define ADCx_CFG1_ADIV_SHIFT                      (5U)
+#define ADCx_CFG1_ADIV(x)                         (((uint32_t)(((uint32_t)(x)) << ADCx_CFG1_ADIV_SHIFT)) & ADCx_CFG1_ADIV_MASK)
+#define ADCx_CFG1_ADLPC_MASK                      (0x80U)
+#define ADCx_CFG1_ADLPC_SHIFT                     (7U)
+#define ADCx_CFG1_ADLPC_SET(x)                    (((uint32_t)(((uint32_t)(x)) << ADCx_CFG1_ADLPC_SHIFT)) & ADCx_CFG1_ADLPC_MASK)
+#define ADCx_CFG1_ADLPC ADCx_CFG1_ADLPC_MASK
 
 /*! @name CFG2 - ADC Configuration Register 2 */
-#define ADC_CFG2_ADLSTS_MASK                     (0x3U)
-#define ADC_CFG2_ADLSTS_SHIFT                    (0U)
-#define ADC_CFG2_ADLSTS(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
-#define ADC_CFG2_ADHSC_MASK                      (0x4U)
-#define ADC_CFG2_ADHSC_SHIFT                     (2U)
-#define ADC_CFG2_ADHSC(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
-#define ADC_CFG2_ADACKEN_MASK                    (0x8U)
-#define ADC_CFG2_ADACKEN_SHIFT                   (3U)
-#define ADC_CFG2_ADACKEN(x)                      (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
-#define ADC_CFG2_MUXSEL_MASK                     (0x10U)
-#define ADC_CFG2_MUXSEL_SHIFT                    (4U)
-#define ADC_CFG2_MUXSEL(x)                       (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
+#define ADCx_CFG2_ADLSTS_MASK                     (0x3U)
+#define ADCx_CFG2_ADLSTS_SHIFT                    (0U)
+#define ADCx_CFG2_ADLSTS_SET(x)                   (((uint32_t)(((uint32_t)(x)) << ADCx_CFG2_ADLSTS_SHIFT)) & ADCx_CFG2_ADLSTS_MASK)
+#define ADCx_CFG2_ADLSTS ADCx_CFG2_ADLSTS_MASK
+#define ADCx_CFG2_ADHSC_MASK                      (0x4U)
+#define ADCx_CFG2_ADHSC_SHIFT                     (2U)
+#define ADCx_CFG2_ADHSC_SET(x)                    (((uint32_t)(((uint32_t)(x)) << ADCx_CFG2_ADHSC_SHIFT)) & ADCx_CFG2_ADHSC_MASK)
+#define ADCx_CFG2_ADHSC ADCx_CFG2_ADHSC_MASK
+#define ADCx_CFG2_ADACKEN_MASK                    (0x8U)
+#define ADCx_CFG2_ADACKEN_SHIFT                   (3U)
+#define ADCx_CFG2_ADACKEN_SET(x)                  (((uint32_t)(((uint32_t)(x)) << ADCx_CFG2_ADACKEN_SHIFT)) & ADCx_CFG2_ADACKEN_MASK)
+#define ADCx_CFG2_ADACKEN ADCx_CFG2_ADACKEN_MASK
+#define ADCx_CFG2_MUXSEL_MASK                     (0x10U)
+#define ADCx_CFG2_MUXSEL_SHIFT                    (4U)
+#define ADCx_CFG2_MUXSEL_SET(x)                   (((uint32_t)(((uint32_t)(x)) << ADCx_CFG2_MUXSEL_SHIFT)) & ADCx_CFG2_MUXSEL_MASK)
+#define ADCx_CFG2_MUXSEL ADCx_CFG2_MUXSEL_MASK
 
 /*! @name R - ADC Data Result Register */
-#define ADC_R_D_MASK                             (0xFFFFU)
-#define ADC_R_D_SHIFT                            (0U)
-#define ADC_R_D(x)                               (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
+#define ADCx_R_D_MASK                             (0xFFFFU)
+#define ADCx_R_D_SHIFT                            (0U)
+#define ADCx_R_D_SET(x)                           (((uint32_t)(((uint32_t)(x)) << ADCx_R_D_SHIFT)) & ADCx_R_D_MASK)
+#define ADCx_R_D ADCx_R_D_MASK
 
-/* The count of ADC_R */
-#define ADC_R_COUNT                              (2U)
+/* The count of ADCx_R */
+#define ADCx_R_COUNT                              (2U)
 
 /*! @name CV1 - Compare Value Registers */
-#define ADC_CV1_CV_MASK                          (0xFFFFU)
-#define ADC_CV1_CV_SHIFT                         (0U)
-#define ADC_CV1_CV(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
+#define ADCx_CV1_CV_MASK                          (0xFFFFU)
+#define ADCx_CV1_CV_SHIFT                         (0U)
+#define ADCx_CV1_CV_SET(x)                        (((uint32_t)(((uint32_t)(x)) << ADCx_CV1_CV_SHIFT)) & ADCx_CV1_CV_MASK)
+#define ADCx_CV1_CV ADCx_CV1_CV_MASK
 
 /*! @name CV2 - Compare Value Registers */
-#define ADC_CV2_CV_MASK                          (0xFFFFU)
-#define ADC_CV2_CV_SHIFT                         (0U)
-#define ADC_CV2_CV(x)                            (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
+#define ADCx_CV2_CV_MASK                          (0xFFFFU)
+#define ADCx_CV2_CV_SHIFT                         (0U)
+#define ADCx_CV2_CV_SET(x)                        (((uint32_t)(((uint32_t)(x)) << ADCx_CV2_CV_SHIFT)) & ADCx_CV2_CV_MASK)
+#define ADCx_CV2_CV ADCx_CV2_CV_MASK
 
 /*! @name SC2 - Status and Control Register 2 */
-#define ADC_SC2_REFSEL_MASK                      (0x3U)
-#define ADC_SC2_REFSEL_SHIFT                     (0U)
-#define ADC_SC2_REFSEL(x)                        (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
-#define ADC_SC2_DMAEN_MASK                       (0x4U)
-#define ADC_SC2_DMAEN_SHIFT                      (2U)
-#define ADC_SC2_DMAEN(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
-#define ADC_SC2_ACREN_MASK                       (0x8U)
-#define ADC_SC2_ACREN_SHIFT                      (3U)
-#define ADC_SC2_ACREN(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
-#define ADC_SC2_ACFGT_MASK                       (0x10U)
-#define ADC_SC2_ACFGT_SHIFT                      (4U)
-#define ADC_SC2_ACFGT(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
-#define ADC_SC2_ACFE_MASK                        (0x20U)
-#define ADC_SC2_ACFE_SHIFT                       (5U)
-#define ADC_SC2_ACFE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
-#define ADC_SC2_ADTRG_MASK                       (0x40U)
-#define ADC_SC2_ADTRG_SHIFT                      (6U)
-#define ADC_SC2_ADTRG(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
-#define ADC_SC2_ADACT_MASK                       (0x80U)
-#define ADC_SC2_ADACT_SHIFT                      (7U)
-#define ADC_SC2_ADACT(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
+#define ADCx_SC2_REFSEL_MASK                      (0x3U)
+#define ADCx_SC2_REFSEL_SHIFT                     (0U)
+#define ADCx_SC2_REFSEL_SET(x)                    (((uint32_t)(((uint32_t)(x)) << ADCx_SC2_REFSEL_SHIFT)) & ADCx_SC2_REFSEL_MASK)
+#define ADCx_SC2_REFSEL ADCx_SC2_REFSEL_MASK
+#define ADCx_SC2_DMAEN_MASK                       (0x4U)
+#define ADCx_SC2_DMAEN_SHIFT                      (2U)
+#define ADCx_SC2_DMAEN_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_SC2_DMAEN_SHIFT)) & ADCx_SC2_DMAEN_MASK)
+#define ADCx_SC2_DMAEN ADCx_SC2_DMAEN_MASK
+#define ADCx_SC2_ACREN_MASK                       (0x8U)
+#define ADCx_SC2_ACREN_SHIFT                      (3U)
+#define ADCx_SC2_ACREN_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_SC2_ACREN_SHIFT)) & ADCx_SC2_ACREN_MASK)
+#define ADCx_SC2_ACREN ADCx_SC2_ACREN_MASK
+#define ADCx_SC2_ACFGT_MASK                       (0x10U)
+#define ADCx_SC2_ACFGT_SHIFT                      (4U)
+#define ADCx_SC2_ACFGT_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_SC2_ACFGT_SHIFT)) & ADCx_SC2_ACFGT_MASK)
+#define ADCx_SC2_ACFGT ADCx_SC2_ACFGT_MASK
+#define ADCx_SC2_ACFE_MASK                        (0x20U)
+#define ADCx_SC2_ACFE_SHIFT                       (5U)
+#define ADCx_SC2_ACFE_SET(x)                      (((uint32_t)(((uint32_t)(x)) << ADCx_SC2_ACFE_SHIFT)) & ADCx_SC2_ACFE_MASK)
+#define ADCx_SC2_ACFE ADCx_SC2_ACFE_MASK
+#define ADCx_SC2_ADTRG_MASK                       (0x40U)
+#define ADCx_SC2_ADTRG_SHIFT                      (6U)
+#define ADCx_SC2_ADTRG_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_SC2_ADTRG_SHIFT)) & ADCx_SC2_ADTRG_MASK)
+#define ADCx_SC2_ADTRG ADCx_SC2_ADTRG_MASK
+#define ADCx_SC2_ADACT_MASK                       (0x80U)
+#define ADCx_SC2_ADACT_SHIFT                      (7U)
+#define ADCx_SC2_ADACT_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_SC2_ADACT_SHIFT)) & ADCx_SC2_ADACT_MASK)
+#define ADCx_SC2_ADACT ADCx_SC2_ADACT_MASK
 
 /*! @name SC3 - Status and Control Register 3 */
-#define ADC_SC3_AVGS_MASK                        (0x3U)
-#define ADC_SC3_AVGS_SHIFT                       (0U)
-#define ADC_SC3_AVGS(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
-#define ADC_SC3_AVGE_MASK                        (0x4U)
-#define ADC_SC3_AVGE_SHIFT                       (2U)
-#define ADC_SC3_AVGE(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
-#define ADC_SC3_ADCO_MASK                        (0x8U)
-#define ADC_SC3_ADCO_SHIFT                       (3U)
-#define ADC_SC3_ADCO(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
-#define ADC_SC3_CALF_MASK                        (0x40U)
-#define ADC_SC3_CALF_SHIFT                       (6U)
-#define ADC_SC3_CALF(x)                          (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
-#define ADC_SC3_CAL_MASK                         (0x80U)
-#define ADC_SC3_CAL_SHIFT                        (7U)
-#define ADC_SC3_CAL(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
+#define ADCx_SC3_AVGS_MASK                        (0x3U)
+#define ADCx_SC3_AVGS_SHIFT                       (0U)
+#define ADCx_SC3_AVGS(x)                          (((uint32_t)(((uint32_t)(x)) << ADCx_SC3_AVGS_SHIFT)) & ADCx_SC3_AVGS_MASK)
+#define ADCx_SC3_AVGE_MASK                        (0x4U)
+#define ADCx_SC3_AVGE_SHIFT                       (2U)
+#define ADCx_SC3_AVGE_SET(x)                      (((uint32_t)(((uint32_t)(x)) << ADCx_SC3_AVGE_SHIFT)) & ADCx_SC3_AVGE_MASK)
+#define ADCx_SC3_AVGE ADCx_SC3_AVGE_MASK
+#define ADCx_SC3_ADCO_MASK                        (0x8U)
+#define ADCx_SC3_ADCO_SHIFT                       (3U)
+#define ADCx_SC3_ADCO_SET(x)                      (((uint32_t)(((uint32_t)(x)) << ADCx_SC3_ADCO_SHIFT)) & ADCx_SC3_ADCO_MASK)
+#define ADCx_SC3_ADCO ADCx_SC3_ADCO_MASK
+#define ADCx_SC3_CALF_MASK                        (0x40U)
+#define ADCx_SC3_CALF_SHIFT                       (6U)
+#define ADCx_SC3_CALF_SET(x)                      (((uint32_t)(((uint32_t)(x)) << ADCx_SC3_CALF_SHIFT)) & ADCx_SC3_CALF_MASK)
+#define ADCx_SC3_CALF ADCx_SC3_CALF_MASK
+#define ADCx_SC3_CAL_MASK                         (0x80U)
+#define ADCx_SC3_CAL_SHIFT                        (7U)
+#define ADCx_SC3_CAL_SET(x)                       (((uint32_t)(((uint32_t)(x)) << ADCx_SC3_CAL_SHIFT)) & ADCx_SC3_CAL_MASK)
+#define ADCx_SC3_CAL ADCx_SC3_CAL_MASK
 
 /*! @name OFS - ADC Offset Correction Register */
-#define ADC_OFS_OFS_MASK                         (0xFFFFU)
-#define ADC_OFS_OFS_SHIFT                        (0U)
-#define ADC_OFS_OFS(x)                           (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
+#define ADCx_OFS_OFS_MASK                         (0xFFFFU)
+#define ADCx_OFS_OFS_SHIFT                        (0U)
+#define ADCx_OFS_OFS_SET(x)                       (((uint32_t)(((uint32_t)(x)) << ADCx_OFS_OFS_SHIFT)) & ADCx_OFS_OFS_MASK)
+#define ADCx_OFS_OFS ADCx_OFS_OFS_MASK
 
 /*! @name PG - ADC Plus-Side Gain Register */
-#define ADC_PG_PG_MASK                           (0xFFFFU)
-#define ADC_PG_PG_SHIFT                          (0U)
-#define ADC_PG_PG(x)                             (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
+#define ADCx_PG_PG_MASK                           (0xFFFFU)
+#define ADCx_PG_PG_SHIFT                          (0U)
+#define ADCx_PG_PG_SET(x)                         (((uint32_t)(((uint32_t)(x)) << ADCx_PG_PG_SHIFT)) & ADCx_PG_PG_MASK)
+#define ADCx_PG_PG ADCx_PG_PG_MASK
 
 /*! @name MG - ADC Minus-Side Gain Register */
-#define ADC_MG_MG_MASK                           (0xFFFFU)
-#define ADC_MG_MG_SHIFT                          (0U)
-#define ADC_MG_MG(x)                             (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
+#define ADCx_MG_MG_MASK                           (0xFFFFU)
+#define ADCx_MG_MG_SHIFT                          (0U)
+#define ADCx_MG_MG_SET(x)                         (((uint32_t)(((uint32_t)(x)) << ADCx_MG_MG_SHIFT)) & ADCx_MG_MG_MASK)
+#define ADCx_MG_MG ADCx_MG_MG_MASK
 
 /*! @name CLPD - ADC Plus-Side General Calibration Value Register */
-#define ADC_CLPD_CLPD_MASK                       (0x3FU)
-#define ADC_CLPD_CLPD_SHIFT                      (0U)
-#define ADC_CLPD_CLPD(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
+#define ADCx_CLPD_CLPD_MASK                       (0x3FU)
+#define ADCx_CLPD_CLPD_SHIFT                      (0U)
+#define ADCx_CLPD_CLPD_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_CLPD_CLPD_SHIFT)) & ADCx_CLPD_CLPD_MASK)
+#define ADCx_CLPD_CLPD ADCx_CLPD_CLPD_MASK
 
 /*! @name CLPS - ADC Plus-Side General Calibration Value Register */
-#define ADC_CLPS_CLPS_MASK                       (0x3FU)
-#define ADC_CLPS_CLPS_SHIFT                      (0U)
-#define ADC_CLPS_CLPS(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
+#define ADCx_CLPS_CLPS_MASK                       (0x3FU)
+#define ADCx_CLPS_CLPS_SHIFT                      (0U)
+#define ADCx_CLPS_CLPS_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_CLPS_CLPS_SHIFT)) & ADCx_CLPS_CLPS_MASK)
+#define ADCx_CLPS_CLPS ADCx_CLPS_CLPS_MASK
 
 /*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
-#define ADC_CLP4_CLP4_MASK                       (0x3FFU)
-#define ADC_CLP4_CLP4_SHIFT                      (0U)
-#define ADC_CLP4_CLP4(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
+#define ADCx_CLP4_CLP4_MASK                       (0x3FFU)
+#define ADCx_CLP4_CLP4_SHIFT                      (0U)
+#define ADCx_CLP4_CLP4_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_CLP4_CLP4_SHIFT)) & ADCx_CLP4_CLP4_MASK)
+#define ADCx_CLP4_CLP4 ADCx_CLP4_CLP4_MASK
 
 /*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
-#define ADC_CLP3_CLP3_MASK                       (0x1FFU)
-#define ADC_CLP3_CLP3_SHIFT                      (0U)
-#define ADC_CLP3_CLP3(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
+#define ADCx_CLP3_CLP3_MASK                       (0x1FFU)
+#define ADCx_CLP3_CLP3_SHIFT                      (0U)
+#define ADCx_CLP3_CLP3_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_CLP3_CLP3_SHIFT)) & ADCx_CLP3_CLP3_MASK)
+#define ADCx_CLP3_CLP3 ADCx_CLP3_CLP3_MASK
 
 /*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
-#define ADC_CLP2_CLP2_MASK                       (0xFFU)
-#define ADC_CLP2_CLP2_SHIFT                      (0U)
-#define ADC_CLP2_CLP2(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
+#define ADCx_CLP2_CLP2_MASK                       (0xFFU)
+#define ADCx_CLP2_CLP2_SHIFT                      (0U)
+#define ADCx_CLP2_CLP2_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_CLP2_CLP2_SHIFT)) & ADCx_CLP2_CLP2_MASK)
+#define ADCx_CLP2_CLP2 ADCx_CLP2_CLP2_MASK
 
 /*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
-#define ADC_CLP1_CLP1_MASK                       (0x7FU)
-#define ADC_CLP1_CLP1_SHIFT                      (0U)
-#define ADC_CLP1_CLP1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
+#define ADCx_CLP1_CLP1_MASK                       (0x7FU)
+#define ADCx_CLP1_CLP1_SHIFT                      (0U)
+#define ADCx_CLP1_CLP1_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_CLP1_CLP1_SHIFT)) & ADCx_CLP1_CLP1_MASK)
+#define ADCx_CLP1_CLP1 ADCx_CLP1_CLP1_MASK
 
 /*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
-#define ADC_CLP0_CLP0_MASK                       (0x3FU)
-#define ADC_CLP0_CLP0_SHIFT                      (0U)
-#define ADC_CLP0_CLP0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
+#define ADCx_CLP0_CLP0_MASK                       (0x3FU)
+#define ADCx_CLP0_CLP0_SHIFT                      (0U)
+#define ADCx_CLP0_CLP0_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_CLP0_CLP0_SHIFT)) & ADCx_CLP0_CLP0_MASK)
+#define ADCx_CLP0_CLP0 ADCx_CLP0_CLP0_MASK
 
 /*! @name CLMD - ADC Minus-Side General Calibration Value Register */
-#define ADC_CLMD_CLMD_MASK                       (0x3FU)
-#define ADC_CLMD_CLMD_SHIFT                      (0U)
-#define ADC_CLMD_CLMD(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
+#define ADCx_CLMD_CLMD_MASK                       (0x3FU)
+#define ADCx_CLMD_CLMD_SHIFT                      (0U)
+#define ADCx_CLMD_CLMD_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_CLMD_CLMD_SHIFT)) & ADCx_CLMD_CLMD_MASK)
+#define ADCx_CLMD_CLMD ADCx_CLMD_CLMD_MASK
 
 /*! @name CLMS - ADC Minus-Side General Calibration Value Register */
-#define ADC_CLMS_CLMS_MASK                       (0x3FU)
-#define ADC_CLMS_CLMS_SHIFT                      (0U)
-#define ADC_CLMS_CLMS(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
+#define ADCx_CLMS_CLMS_MASK                       (0x3FU)
+#define ADCx_CLMS_CLMS_SHIFT                      (0U)
+#define ADCx_CLMS_CLMS_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_CLMS_CLMS_SHIFT)) & ADCx_CLMS_CLMS_MASK)
+#define ADCx_CLMS_CLMS ADCx_CLMS_CLMS_MASK
 
 /*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
-#define ADC_CLM4_CLM4_MASK                       (0x3FFU)
-#define ADC_CLM4_CLM4_SHIFT                      (0U)
-#define ADC_CLM4_CLM4(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
+#define ADCx_CLM4_CLM4_MASK                       (0x3FFU)
+#define ADCx_CLM4_CLM4_SHIFT                      (0U)
+#define ADCx_CLM4_CLM4_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_CLM4_CLM4_SHIFT)) & ADCx_CLM4_CLM4_MASK)
+#define ADCx_CLM4_CLM4 ADCx_CLM4_CLM4_MASK
 
 /*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
-#define ADC_CLM3_CLM3_MASK                       (0x1FFU)
-#define ADC_CLM3_CLM3_SHIFT                      (0U)
-#define ADC_CLM3_CLM3(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
+#define ADCx_CLM3_CLM3_MASK                       (0x1FFU)
+#define ADCx_CLM3_CLM3_SHIFT                      (0U)
+#define ADCx_CLM3_CLM3_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_CLM3_CLM3_SHIFT)) & ADCx_CLM3_CLM3_MASK)
+#define ADCx_CLM3_CLM3 ADCx_CLM3_CLM3_MASK
 
 /*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
-#define ADC_CLM2_CLM2_MASK                       (0xFFU)
-#define ADC_CLM2_CLM2_SHIFT                      (0U)
-#define ADC_CLM2_CLM2(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
+#define ADCx_CLM2_CLM2_MASK                       (0xFFU)
+#define ADCx_CLM2_CLM2_SHIFT                      (0U)
+#define ADCx_CLM2_CLM2_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_CLM2_CLM2_SHIFT)) & ADCx_CLM2_CLM2_MASK)
+#define ADCx_CLM2_CLM2 ADCx_CLM2_CLM2_MASK
 
 /*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
-#define ADC_CLM1_CLM1_MASK                       (0x7FU)
-#define ADC_CLM1_CLM1_SHIFT                      (0U)
-#define ADC_CLM1_CLM1(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
+#define ADCx_CLM1_CLM1_MASK                       (0x7FU)
+#define ADCx_CLM1_CLM1_SHIFT                      (0U)
+#define ADCx_CLM1_CLM1_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_CLM1_CLM1_SHIFT)) & ADCx_CLM1_CLM1_MASK)
+#define ADCx_CLM1_CLM1 ADCx_CLM1_CLM1_MASK
 
 /*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
-#define ADC_CLM0_CLM0_MASK                       (0x3FU)
-#define ADC_CLM0_CLM0_SHIFT                      (0U)
-#define ADC_CLM0_CLM0(x)                         (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
+#define ADCx_CLM0_CLM0_MASK                       (0x3FU)
+#define ADCx_CLM0_CLM0_SHIFT                      (0U)
+#define ADCx_CLM0_CLM0_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ADCx_CLM0_CLM0_SHIFT)) & ADCx_CLM0_CLM0_MASK)
+#define ADCx_CLM0_CLM0 ADCx_CLM0_CLM0_MASK
 
 
 /*!
  * @}
- */ /* end of group ADC_Register_Masks */
+ */ /* end of group ADCx_Register_Masks */
 
 
 /* ADC - Peripheral instance base addresses */
 /** Peripheral ADC0 base address */
 #define ADC0_BASE                                (0x4003B000u)
 /** Peripheral ADC0 base pointer */
-#define ADC0                                     ((ADC_Type *)ADC0_BASE)
+#define ADC0                                     ((ADC_TypeDef *)ADC0_BASE)
 /** Peripheral ADC1 base address */
 #define ADC1_BASE                                (0x400BB000u)
 /** Peripheral ADC1 base pointer */
-#define ADC1                                     ((ADC_Type *)ADC1_BASE)
+#define ADC1                                     ((ADC_TypeDef *)ADC1_BASE)
 /** Array initializer of ADC peripheral base addresses */
-#define ADC_BASE_ADDRS                           { ADC0_BASE, ADC1_BASE }
+#define ADCx_BASE_ADDRS                           { ADC0_BASE, ADC1_BASE }
 /** Array initializer of ADC peripheral base pointers */
-#define ADC_BASE_PTRS                            { ADC0, ADC1 }
+#define ADCx_BASE_PTRS                            { ADC0, ADC1 }
 /** Interrupt vectors for the ADC peripheral type */
-#define ADC_IRQS                                 { ADC0_IRQn, ADC1_IRQn }
+#define ADCx_IRQS                                 { ADC0_IRQn, ADC1_IRQn }
 
 /*!
  * @}
- */ /* end of group ADC_Peripheral_Access_Layer */
+ */ /* end of group ADCx_Peripheral_Access_Layer */
 
 
 /* ----------------------------------------------------------------------------
@@ -744,7 +806,7 @@ typedef struct {
   __IO uint32_t PACRN;                             /**< Peripheral Access Control Register, offset: 0x64 */
   __IO uint32_t PACRO;                             /**< Peripheral Access Control Register, offset: 0x68 */
   __IO uint32_t PACRP;                             /**< Peripheral Access Control Register, offset: 0x6C */
-} AIPS_Type;
+} AIPS_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- AIPS Register Masks
@@ -758,1251 +820,1656 @@ typedef struct {
 /*! @name MPRA - Master Privilege Register A */
 #define AIPS_MPRA_MPL6_MASK                      (0x10U)
 #define AIPS_MPRA_MPL6_SHIFT                     (4U)
-#define AIPS_MPRA_MPL6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL6_SHIFT)) & AIPS_MPRA_MPL6_MASK)
+#define AIPS_MPRA_MPL6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL6_SHIFT)) & AIPS_MPRA_MPL6_MASK)
+#define AIPS_MPRA_MPL6 AIPS_MPRA_MPL6_MASK
 #define AIPS_MPRA_MTW6_MASK                      (0x20U)
 #define AIPS_MPRA_MTW6_SHIFT                     (5U)
-#define AIPS_MPRA_MTW6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW6_SHIFT)) & AIPS_MPRA_MTW6_MASK)
+#define AIPS_MPRA_MTW6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW6_SHIFT)) & AIPS_MPRA_MTW6_MASK)
+#define AIPS_MPRA_MTW6 AIPS_MPRA_MTW6_MASK
 #define AIPS_MPRA_MTR6_MASK                      (0x40U)
 #define AIPS_MPRA_MTR6_SHIFT                     (6U)
-#define AIPS_MPRA_MTR6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR6_SHIFT)) & AIPS_MPRA_MTR6_MASK)
+#define AIPS_MPRA_MTR6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR6_SHIFT)) & AIPS_MPRA_MTR6_MASK)
+#define AIPS_MPRA_MTR6 AIPS_MPRA_MTR6_MASK
 #define AIPS_MPRA_MPL5_MASK                      (0x100U)
 #define AIPS_MPRA_MPL5_SHIFT                     (8U)
-#define AIPS_MPRA_MPL5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL5_SHIFT)) & AIPS_MPRA_MPL5_MASK)
+#define AIPS_MPRA_MPL5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL5_SHIFT)) & AIPS_MPRA_MPL5_MASK)
+#define AIPS_MPRA_MPL5 AIPS_MPRA_MPL5_MASK
 #define AIPS_MPRA_MTW5_MASK                      (0x200U)
 #define AIPS_MPRA_MTW5_SHIFT                     (9U)
-#define AIPS_MPRA_MTW5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW5_SHIFT)) & AIPS_MPRA_MTW5_MASK)
+#define AIPS_MPRA_MTW5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW5_SHIFT)) & AIPS_MPRA_MTW5_MASK)
+#define AIPS_MPRA_MTW5 AIPS_MPRA_MTW5_MASK
 #define AIPS_MPRA_MTR5_MASK                      (0x400U)
 #define AIPS_MPRA_MTR5_SHIFT                     (10U)
-#define AIPS_MPRA_MTR5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR5_SHIFT)) & AIPS_MPRA_MTR5_MASK)
+#define AIPS_MPRA_MTR5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR5_SHIFT)) & AIPS_MPRA_MTR5_MASK)
+#define AIPS_MPRA_MTR5 AIPS_MPRA_MTR5_MASK
 #define AIPS_MPRA_MPL4_MASK                      (0x1000U)
 #define AIPS_MPRA_MPL4_SHIFT                     (12U)
-#define AIPS_MPRA_MPL4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK)
+#define AIPS_MPRA_MPL4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK)
+#define AIPS_MPRA_MPL4 AIPS_MPRA_MPL4_MASK
 #define AIPS_MPRA_MTW4_MASK                      (0x2000U)
 #define AIPS_MPRA_MTW4_SHIFT                     (13U)
-#define AIPS_MPRA_MTW4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK)
+#define AIPS_MPRA_MTW4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK)
+#define AIPS_MPRA_MTW4 AIPS_MPRA_MTW4_MASK
 #define AIPS_MPRA_MTR4_MASK                      (0x4000U)
 #define AIPS_MPRA_MTR4_SHIFT                     (14U)
-#define AIPS_MPRA_MTR4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK)
+#define AIPS_MPRA_MTR4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK)
+#define AIPS_MPRA_MTR4 AIPS_MPRA_MTR4_MASK
 #define AIPS_MPRA_MPL3_MASK                      (0x10000U)
 #define AIPS_MPRA_MPL3_SHIFT                     (16U)
-#define AIPS_MPRA_MPL3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK)
+#define AIPS_MPRA_MPL3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK)
+#define AIPS_MPRA_MPL3 AIPS_MPRA_MPL3_MASK
 #define AIPS_MPRA_MTW3_MASK                      (0x20000U)
 #define AIPS_MPRA_MTW3_SHIFT                     (17U)
-#define AIPS_MPRA_MTW3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK)
+#define AIPS_MPRA_MTW3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK)
+#define AIPS_MPRA_MTW3 AIPS_MPRA_MTW3_MASK
 #define AIPS_MPRA_MTR3_MASK                      (0x40000U)
 #define AIPS_MPRA_MTR3_SHIFT                     (18U)
-#define AIPS_MPRA_MTR3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK)
+#define AIPS_MPRA_MTR3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK)
+#define AIPS_MPRA_MTR3 AIPS_MPRA_MTR3_MASK
 #define AIPS_MPRA_MPL2_MASK                      (0x100000U)
 #define AIPS_MPRA_MPL2_SHIFT                     (20U)
-#define AIPS_MPRA_MPL2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK)
+#define AIPS_MPRA_MPL2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK)
+#define AIPS_MPRA_MPL2 AIPS_MPRA_MPL2_MASK
 #define AIPS_MPRA_MTW2_MASK                      (0x200000U)
 #define AIPS_MPRA_MTW2_SHIFT                     (21U)
-#define AIPS_MPRA_MTW2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK)
+#define AIPS_MPRA_MTW2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK)
+#define AIPS_MPRA_MTW2 AIPS_MPRA_MTW2_MASK
 #define AIPS_MPRA_MTR2_MASK                      (0x400000U)
 #define AIPS_MPRA_MTR2_SHIFT                     (22U)
-#define AIPS_MPRA_MTR2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK)
+#define AIPS_MPRA_MTR2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK)
+#define AIPS_MPRA_MTR2 AIPS_MPRA_MTR2_MASK
 #define AIPS_MPRA_MPL1_MASK                      (0x1000000U)
 #define AIPS_MPRA_MPL1_SHIFT                     (24U)
-#define AIPS_MPRA_MPL1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK)
+#define AIPS_MPRA_MPL1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK)
+#define AIPS_MPRA_MPL1 AIPS_MPRA_MPL1_MASK
 #define AIPS_MPRA_MTW1_MASK                      (0x2000000U)
 #define AIPS_MPRA_MTW1_SHIFT                     (25U)
-#define AIPS_MPRA_MTW1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK)
+#define AIPS_MPRA_MTW1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK)
+#define AIPS_MPRA_MTW1 AIPS_MPRA_MTW1_MASK
 #define AIPS_MPRA_MTR1_MASK                      (0x4000000U)
 #define AIPS_MPRA_MTR1_SHIFT                     (26U)
-#define AIPS_MPRA_MTR1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK)
+#define AIPS_MPRA_MTR1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK)
+#define AIPS_MPRA_MTR1 AIPS_MPRA_MTR1_MASK
 #define AIPS_MPRA_MPL0_MASK                      (0x10000000U)
 #define AIPS_MPRA_MPL0_SHIFT                     (28U)
-#define AIPS_MPRA_MPL0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK)
+#define AIPS_MPRA_MPL0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK)
+#define AIPS_MPRA_MPL0 AIPS_MPRA_MPL0_MASK
 #define AIPS_MPRA_MTW0_MASK                      (0x20000000U)
 #define AIPS_MPRA_MTW0_SHIFT                     (29U)
-#define AIPS_MPRA_MTW0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK)
+#define AIPS_MPRA_MTW0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK)
+#define AIPS_MPRA_MTW0 AIPS_MPRA_MTW0_MASK
 #define AIPS_MPRA_MTR0_MASK                      (0x40000000U)
 #define AIPS_MPRA_MTR0_SHIFT                     (30U)
-#define AIPS_MPRA_MTR0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK)
+#define AIPS_MPRA_MTR0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK)
+#define AIPS_MPRA_MTR0 AIPS_MPRA_MTR0_MASK
 
 /*! @name PACRA - Peripheral Access Control Register */
 #define AIPS_PACRA_TP7_MASK                      (0x1U)
 #define AIPS_PACRA_TP7_SHIFT                     (0U)
-#define AIPS_PACRA_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK)
+#define AIPS_PACRA_TP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK)
+#define AIPS_PACRA_TP7 AIPS_PACRA_TP7_MASK
 #define AIPS_PACRA_WP7_MASK                      (0x2U)
 #define AIPS_PACRA_WP7_SHIFT                     (1U)
-#define AIPS_PACRA_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK)
+#define AIPS_PACRA_WP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK)
+#define AIPS_PACRA_WP7 AIPS_PACRA_WP7_MASK
 #define AIPS_PACRA_SP7_MASK                      (0x4U)
 #define AIPS_PACRA_SP7_SHIFT                     (2U)
-#define AIPS_PACRA_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK)
+#define AIPS_PACRA_SP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK)
+#define AIPS_PACRA_SP7 AIPS_PACRA_SP7_MASK
 #define AIPS_PACRA_TP6_MASK                      (0x10U)
 #define AIPS_PACRA_TP6_SHIFT                     (4U)
-#define AIPS_PACRA_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK)
+#define AIPS_PACRA_TP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK)
+#define AIPS_PACRA_TP6 AIPS_PACRA_TP6_MASK
 #define AIPS_PACRA_WP6_MASK                      (0x20U)
 #define AIPS_PACRA_WP6_SHIFT                     (5U)
-#define AIPS_PACRA_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK)
+#define AIPS_PACRA_WP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK)
+#define AIPS_PACRA_WP6 AIPS_PACRA_WP6_MASK
 #define AIPS_PACRA_SP6_MASK                      (0x40U)
 #define AIPS_PACRA_SP6_SHIFT                     (6U)
-#define AIPS_PACRA_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK)
+#define AIPS_PACRA_SP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK)
+#define AIPS_PACRA_SP6 AIPS_PACRA_SP6_MASK
 #define AIPS_PACRA_TP5_MASK                      (0x100U)
 #define AIPS_PACRA_TP5_SHIFT                     (8U)
-#define AIPS_PACRA_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK)
+#define AIPS_PACRA_TP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK)
+#define AIPS_PACRA_TP5 AIPS_PACRA_TP5_MASK
 #define AIPS_PACRA_WP5_MASK                      (0x200U)
 #define AIPS_PACRA_WP5_SHIFT                     (9U)
-#define AIPS_PACRA_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK)
+#define AIPS_PACRA_WP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK)
+#define AIPS_PACRA_WP5 AIPS_PACRA_WP5_MASK
 #define AIPS_PACRA_SP5_MASK                      (0x400U)
 #define AIPS_PACRA_SP5_SHIFT                     (10U)
-#define AIPS_PACRA_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK)
+#define AIPS_PACRA_SP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK)
+#define AIPS_PACRA_SP5 AIPS_PACRA_SP5_MASK
 #define AIPS_PACRA_TP4_MASK                      (0x1000U)
 #define AIPS_PACRA_TP4_SHIFT                     (12U)
-#define AIPS_PACRA_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK)
+#define AIPS_PACRA_TP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK)
+#define AIPS_PACRA_TP4 AIPS_PACRA_TP4_MASK
 #define AIPS_PACRA_WP4_MASK                      (0x2000U)
 #define AIPS_PACRA_WP4_SHIFT                     (13U)
-#define AIPS_PACRA_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK)
+#define AIPS_PACRA_WP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK)
+#define AIPS_PACRA_WP4 AIPS_PACRA_WP4_MASK
 #define AIPS_PACRA_SP4_MASK                      (0x4000U)
 #define AIPS_PACRA_SP4_SHIFT                     (14U)
-#define AIPS_PACRA_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK)
+#define AIPS_PACRA_SP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK)
+#define AIPS_PACRA_SP4 AIPS_PACRA_SP4_MASK
 #define AIPS_PACRA_TP3_MASK                      (0x10000U)
 #define AIPS_PACRA_TP3_SHIFT                     (16U)
-#define AIPS_PACRA_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK)
+#define AIPS_PACRA_TP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK)
+#define AIPS_PACRA_TP3 AIPS_PACRA_TP3_MASK
 #define AIPS_PACRA_WP3_MASK                      (0x20000U)
 #define AIPS_PACRA_WP3_SHIFT                     (17U)
-#define AIPS_PACRA_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK)
+#define AIPS_PACRA_WP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK)
+#define AIPS_PACRA_WP3 AIPS_PACRA_WP3_MASK
 #define AIPS_PACRA_SP3_MASK                      (0x40000U)
 #define AIPS_PACRA_SP3_SHIFT                     (18U)
-#define AIPS_PACRA_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK)
+#define AIPS_PACRA_SP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK)
+#define AIPS_PACRA_SP3 AIPS_PACRA_SP3_MASK
 #define AIPS_PACRA_TP2_MASK                      (0x100000U)
 #define AIPS_PACRA_TP2_SHIFT                     (20U)
-#define AIPS_PACRA_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK)
+#define AIPS_PACRA_TP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK)
+#define AIPS_PACRA_TP2 AIPS_PACRA_TP2_MASK
 #define AIPS_PACRA_WP2_MASK                      (0x200000U)
 #define AIPS_PACRA_WP2_SHIFT                     (21U)
-#define AIPS_PACRA_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK)
+#define AIPS_PACRA_WP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK)
+#define AIPS_PACRA_WP2 AIPS_PACRA_WP2_MASK
 #define AIPS_PACRA_SP2_MASK                      (0x400000U)
 #define AIPS_PACRA_SP2_SHIFT                     (22U)
-#define AIPS_PACRA_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK)
+#define AIPS_PACRA_SP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK)
+#define AIPS_PACRA_SP2 AIPS_PACRA_SP2_MASK
 #define AIPS_PACRA_TP1_MASK                      (0x1000000U)
 #define AIPS_PACRA_TP1_SHIFT                     (24U)
-#define AIPS_PACRA_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK)
+#define AIPS_PACRA_TP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK)
+#define AIPS_PACRA_TP1 AIPS_PACRA_TP1_MASK
 #define AIPS_PACRA_WP1_MASK                      (0x2000000U)
 #define AIPS_PACRA_WP1_SHIFT                     (25U)
-#define AIPS_PACRA_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK)
+#define AIPS_PACRA_WP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK)
+#define AIPS_PACRA_WP1 AIPS_PACRA_WP1_MASK
 #define AIPS_PACRA_SP1_MASK                      (0x4000000U)
 #define AIPS_PACRA_SP1_SHIFT                     (26U)
-#define AIPS_PACRA_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK)
+#define AIPS_PACRA_SP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK)
+#define AIPS_PACRA_SP1 AIPS_PACRA_SP1_MASK
 #define AIPS_PACRA_TP0_MASK                      (0x10000000U)
 #define AIPS_PACRA_TP0_SHIFT                     (28U)
-#define AIPS_PACRA_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK)
+#define AIPS_PACRA_TP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK)
+#define AIPS_PACRA_TP0 AIPS_PACRA_TP0_MASK
 #define AIPS_PACRA_WP0_MASK                      (0x20000000U)
 #define AIPS_PACRA_WP0_SHIFT                     (29U)
-#define AIPS_PACRA_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK)
+#define AIPS_PACRA_WP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK)
+#define AIPS_PACRA_WP0 AIPS_PACRA_WP0_MASK
 #define AIPS_PACRA_SP0_MASK                      (0x40000000U)
 #define AIPS_PACRA_SP0_SHIFT                     (30U)
-#define AIPS_PACRA_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK)
+#define AIPS_PACRA_SP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK)
+#define AIPS_PACRA_SP0 AIPS_PACRA_SP0_MASK
 
 /*! @name PACRB - Peripheral Access Control Register */
 #define AIPS_PACRB_TP7_MASK                      (0x1U)
 #define AIPS_PACRB_TP7_SHIFT                     (0U)
-#define AIPS_PACRB_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK)
+#define AIPS_PACRB_TP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK)
+#define AIPS_PACRB_TP7 AIPS_PACRB_TP7_MASK
 #define AIPS_PACRB_WP7_MASK                      (0x2U)
 #define AIPS_PACRB_WP7_SHIFT                     (1U)
-#define AIPS_PACRB_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK)
+#define AIPS_PACRB_WP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK)
+#define AIPS_PACRB_WP7 AIPS_PACRB_WP7_MASK
 #define AIPS_PACRB_SP7_MASK                      (0x4U)
 #define AIPS_PACRB_SP7_SHIFT                     (2U)
-#define AIPS_PACRB_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK)
+#define AIPS_PACRB_SP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK)
+#define AIPS_PACRB_SP7 AIPS_PACRB_SP7_MASK
 #define AIPS_PACRB_TP6_MASK                      (0x10U)
 #define AIPS_PACRB_TP6_SHIFT                     (4U)
-#define AIPS_PACRB_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK)
+#define AIPS_PACRB_TP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK)
+#define AIPS_PACRB_TP6 AIPS_PACRB_TP6_MASK
 #define AIPS_PACRB_WP6_MASK                      (0x20U)
 #define AIPS_PACRB_WP6_SHIFT                     (5U)
-#define AIPS_PACRB_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK)
+#define AIPS_PACRB_WP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK)
+#define AIPS_PACRB_WP6 AIPS_PACRB_WP6_MASK
 #define AIPS_PACRB_SP6_MASK                      (0x40U)
 #define AIPS_PACRB_SP6_SHIFT                     (6U)
-#define AIPS_PACRB_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK)
+#define AIPS_PACRB_SP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK)
+#define AIPS_PACRB_SP6 AIPS_PACRB_SP6_MASK
 #define AIPS_PACRB_TP5_MASK                      (0x100U)
 #define AIPS_PACRB_TP5_SHIFT                     (8U)
-#define AIPS_PACRB_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK)
+#define AIPS_PACRB_TP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK)
+#define AIPS_PACRB_TP5 AIPS_PACRB_TP5_MASK
 #define AIPS_PACRB_WP5_MASK                      (0x200U)
 #define AIPS_PACRB_WP5_SHIFT                     (9U)
-#define AIPS_PACRB_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK)
+#define AIPS_PACRB_WP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK)
+#define AIPS_PACRB_WP5 AIPS_PACRB_WP5_MASK
 #define AIPS_PACRB_SP5_MASK                      (0x400U)
 #define AIPS_PACRB_SP5_SHIFT                     (10U)
-#define AIPS_PACRB_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK)
+#define AIPS_PACRB_SP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK)
+#define AIPS_PACRB_SP5 AIPS_PACRB_SP5_MASK
 #define AIPS_PACRB_TP4_MASK                      (0x1000U)
 #define AIPS_PACRB_TP4_SHIFT                     (12U)
-#define AIPS_PACRB_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK)
+#define AIPS_PACRB_TP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK)
+#define AIPS_PACRB_TP4 AIPS_PACRB_TP4_MASK
 #define AIPS_PACRB_WP4_MASK                      (0x2000U)
 #define AIPS_PACRB_WP4_SHIFT                     (13U)
-#define AIPS_PACRB_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK)
+#define AIPS_PACRB_WP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK)
+#define AIPS_PACRB_WP4 AIPS_PACRB_WP4_MASK
 #define AIPS_PACRB_SP4_MASK                      (0x4000U)
 #define AIPS_PACRB_SP4_SHIFT                     (14U)
-#define AIPS_PACRB_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK)
+#define AIPS_PACRB_SP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK)
+#define AIPS_PACRB_SP4 AIPS_PACRB_SP4_MASK
 #define AIPS_PACRB_TP3_MASK                      (0x10000U)
 #define AIPS_PACRB_TP3_SHIFT                     (16U)
-#define AIPS_PACRB_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK)
+#define AIPS_PACRB_TP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK)
+#define AIPS_PACRB_TP3 AIPS_PACRB_TP3_MASK
 #define AIPS_PACRB_WP3_MASK                      (0x20000U)
 #define AIPS_PACRB_WP3_SHIFT                     (17U)
-#define AIPS_PACRB_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK)
+#define AIPS_PACRB_WP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK)
+#define AIPS_PACRB_WP3 AIPS_PACRB_WP3_MASK
 #define AIPS_PACRB_SP3_MASK                      (0x40000U)
 #define AIPS_PACRB_SP3_SHIFT                     (18U)
-#define AIPS_PACRB_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK)
+#define AIPS_PACRB_SP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK)
+#define AIPS_PACRB_SP3 AIPS_PACRB_SP3_MASK
 #define AIPS_PACRB_TP2_MASK                      (0x100000U)
 #define AIPS_PACRB_TP2_SHIFT                     (20U)
-#define AIPS_PACRB_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK)
+#define AIPS_PACRB_TP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK)
+#define AIPS_PACRB_TP2 AIPS_PACRB_TP2_MASK
 #define AIPS_PACRB_WP2_MASK                      (0x200000U)
 #define AIPS_PACRB_WP2_SHIFT                     (21U)
-#define AIPS_PACRB_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK)
+#define AIPS_PACRB_WP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK)
+#define AIPS_PACRB_WP2 AIPS_PACRB_WP2_MASK
 #define AIPS_PACRB_SP2_MASK                      (0x400000U)
 #define AIPS_PACRB_SP2_SHIFT                     (22U)
-#define AIPS_PACRB_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK)
+#define AIPS_PACRB_SP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK)
+#define AIPS_PACRB_SP2 AIPS_PACRB_SP2_MASK
 #define AIPS_PACRB_TP1_MASK                      (0x1000000U)
 #define AIPS_PACRB_TP1_SHIFT                     (24U)
-#define AIPS_PACRB_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK)
+#define AIPS_PACRB_TP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK)
+#define AIPS_PACRB_TP1 AIPS_PACRB_TP1_MASK
 #define AIPS_PACRB_WP1_MASK                      (0x2000000U)
 #define AIPS_PACRB_WP1_SHIFT                     (25U)
-#define AIPS_PACRB_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK)
+#define AIPS_PACRB_WP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK)
+#define AIPS_PACRB_WP1 AIPS_PACRB_WP1_MASK
 #define AIPS_PACRB_SP1_MASK                      (0x4000000U)
 #define AIPS_PACRB_SP1_SHIFT                     (26U)
-#define AIPS_PACRB_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK)
+#define AIPS_PACRB_SP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK)
+#define AIPS_PACRB_SP1 AIPS_PACRB_SP1_MASK
 #define AIPS_PACRB_TP0_MASK                      (0x10000000U)
 #define AIPS_PACRB_TP0_SHIFT                     (28U)
-#define AIPS_PACRB_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK)
+#define AIPS_PACRB_TP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK)
+#define AIPS_PACRB_TP0 AIPS_PACRB_TP0_MASK
 #define AIPS_PACRB_WP0_MASK                      (0x20000000U)
 #define AIPS_PACRB_WP0_SHIFT                     (29U)
-#define AIPS_PACRB_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK)
+#define AIPS_PACRB_WP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK)
+#define AIPS_PACRB_WP0 AIPS_PACRB_WP0_MASK
 #define AIPS_PACRB_SP0_MASK                      (0x40000000U)
 #define AIPS_PACRB_SP0_SHIFT                     (30U)
-#define AIPS_PACRB_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK)
+#define AIPS_PACRB_SP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK)
+#define AIPS_PACRB_SP0 AIPS_PACRB_SP0_MASK
 
 /*! @name PACRC - Peripheral Access Control Register */
 #define AIPS_PACRC_TP7_MASK                      (0x1U)
 #define AIPS_PACRC_TP7_SHIFT                     (0U)
-#define AIPS_PACRC_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK)
+#define AIPS_PACRC_TP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK)
+#define AIPS_PACRC_TP7 AIPS_PACRC_TP7_MASK
 #define AIPS_PACRC_WP7_MASK                      (0x2U)
 #define AIPS_PACRC_WP7_SHIFT                     (1U)
-#define AIPS_PACRC_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK)
+#define AIPS_PACRC_WP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK)
+#define AIPS_PACRC_WP7 AIPS_PACRC_WP7_MASK
 #define AIPS_PACRC_SP7_MASK                      (0x4U)
 #define AIPS_PACRC_SP7_SHIFT                     (2U)
-#define AIPS_PACRC_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK)
+#define AIPS_PACRC_SP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK)
+#define AIPS_PACRC_SP7 AIPS_PACRC_SP7_MASK
 #define AIPS_PACRC_TP6_MASK                      (0x10U)
 #define AIPS_PACRC_TP6_SHIFT                     (4U)
-#define AIPS_PACRC_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK)
+#define AIPS_PACRC_TP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK)
+#define AIPS_PACRC_TP6 AIPS_PACRC_TP6_MASK
 #define AIPS_PACRC_WP6_MASK                      (0x20U)
 #define AIPS_PACRC_WP6_SHIFT                     (5U)
-#define AIPS_PACRC_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK)
+#define AIPS_PACRC_WP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK)
+#define AIPS_PACRC_WP6 AIPS_PACRC_WP6_MASK
 #define AIPS_PACRC_SP6_MASK                      (0x40U)
 #define AIPS_PACRC_SP6_SHIFT                     (6U)
-#define AIPS_PACRC_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK)
+#define AIPS_PACRC_SP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK)
+#define AIPS_PACRC_SP6 AIPS_PACRC_SP6_MASK
 #define AIPS_PACRC_TP5_MASK                      (0x100U)
 #define AIPS_PACRC_TP5_SHIFT                     (8U)
-#define AIPS_PACRC_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK)
+#define AIPS_PACRC_TP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK)
+#define AIPS_PACRC_TP5 AIPS_PACRC_TP5_MASK
 #define AIPS_PACRC_WP5_MASK                      (0x200U)
 #define AIPS_PACRC_WP5_SHIFT                     (9U)
-#define AIPS_PACRC_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK)
+#define AIPS_PACRC_WP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK)
+#define AIPS_PACRC_WP5 AIPS_PACRC_WP5_MASK
 #define AIPS_PACRC_SP5_MASK                      (0x400U)
 #define AIPS_PACRC_SP5_SHIFT                     (10U)
-#define AIPS_PACRC_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK)
+#define AIPS_PACRC_SP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK)
+#define AIPS_PACRC_SP5 AIPS_PACRC_SP5_MASK
 #define AIPS_PACRC_TP4_MASK                      (0x1000U)
 #define AIPS_PACRC_TP4_SHIFT                     (12U)
-#define AIPS_PACRC_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK)
+#define AIPS_PACRC_TP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK)
+#define AIPS_PACRC_TP4 AIPS_PACRC_TP4_MASK
 #define AIPS_PACRC_WP4_MASK                      (0x2000U)
 #define AIPS_PACRC_WP4_SHIFT                     (13U)
-#define AIPS_PACRC_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK)
+#define AIPS_PACRC_WP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK)
+#define AIPS_PACRC_WP4 AIPS_PACRC_WP4_MASK
 #define AIPS_PACRC_SP4_MASK                      (0x4000U)
 #define AIPS_PACRC_SP4_SHIFT                     (14U)
-#define AIPS_PACRC_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK)
+#define AIPS_PACRC_SP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK)
+#define AIPS_PACRC_SP4 AIPS_PACRC_SP4_MASK
 #define AIPS_PACRC_TP3_MASK                      (0x10000U)
 #define AIPS_PACRC_TP3_SHIFT                     (16U)
-#define AIPS_PACRC_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK)
+#define AIPS_PACRC_TP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK)
+#define AIPS_PACRC_TP3 AIPS_PACRC_TP3_MASK
 #define AIPS_PACRC_WP3_MASK                      (0x20000U)
 #define AIPS_PACRC_WP3_SHIFT                     (17U)
-#define AIPS_PACRC_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK)
+#define AIPS_PACRC_WP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK)
+#define AIPS_PACRC_WP3 AIPS_PACRC_WP3_MASK
 #define AIPS_PACRC_SP3_MASK                      (0x40000U)
 #define AIPS_PACRC_SP3_SHIFT                     (18U)
-#define AIPS_PACRC_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK)
+#define AIPS_PACRC_SP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK)
+#define AIPS_PACRC_SP3 AIPS_PACRC_SP3_MASK
 #define AIPS_PACRC_TP2_MASK                      (0x100000U)
 #define AIPS_PACRC_TP2_SHIFT                     (20U)
-#define AIPS_PACRC_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK)
+#define AIPS_PACRC_TP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK)
+#define AIPS_PACRC_TP2 AIPS_PACRC_TP2_MASK
 #define AIPS_PACRC_WP2_MASK                      (0x200000U)
 #define AIPS_PACRC_WP2_SHIFT                     (21U)
-#define AIPS_PACRC_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK)
+#define AIPS_PACRC_WP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK)
+#define AIPS_PACRC_WP2 AIPS_PACRC_WP2_MASK
 #define AIPS_PACRC_SP2_MASK                      (0x400000U)
 #define AIPS_PACRC_SP2_SHIFT                     (22U)
-#define AIPS_PACRC_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK)
+#define AIPS_PACRC_SP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK)
+#define AIPS_PACRC_SP2 AIPS_PACRC_SP2_MASK
 #define AIPS_PACRC_TP1_MASK                      (0x1000000U)
 #define AIPS_PACRC_TP1_SHIFT                     (24U)
-#define AIPS_PACRC_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK)
+#define AIPS_PACRC_TP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK)
+#define AIPS_PACRC_TP1 AIPS_PACRC_TP1_MASK
 #define AIPS_PACRC_WP1_MASK                      (0x2000000U)
 #define AIPS_PACRC_WP1_SHIFT                     (25U)
-#define AIPS_PACRC_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK)
+#define AIPS_PACRC_WP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK)
+#define AIPS_PACRC_WP1 AIPS_PACRC_WP1_MASK
 #define AIPS_PACRC_SP1_MASK                      (0x4000000U)
 #define AIPS_PACRC_SP1_SHIFT                     (26U)
-#define AIPS_PACRC_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK)
+#define AIPS_PACRC_SP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK)
+#define AIPS_PACRC_SP1 AIPS_PACRC_SP1_MASK
 #define AIPS_PACRC_TP0_MASK                      (0x10000000U)
 #define AIPS_PACRC_TP0_SHIFT                     (28U)
-#define AIPS_PACRC_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK)
+#define AIPS_PACRC_TP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK)
+#define AIPS_PACRC_TP0 AIPS_PACRC_TP0_MASK
 #define AIPS_PACRC_WP0_MASK                      (0x20000000U)
 #define AIPS_PACRC_WP0_SHIFT                     (29U)
-#define AIPS_PACRC_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK)
+#define AIPS_PACRC_WP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK)
+#define AIPS_PACRC_WP0 AIPS_PACRC_WP0_MASK
 #define AIPS_PACRC_SP0_MASK                      (0x40000000U)
 #define AIPS_PACRC_SP0_SHIFT                     (30U)
-#define AIPS_PACRC_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK)
+#define AIPS_PACRC_SP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK)
+#define AIPS_PACRC_SP0 AIPS_PACRC_SP0_MASK
 
 /*! @name PACRD - Peripheral Access Control Register */
 #define AIPS_PACRD_TP7_MASK                      (0x1U)
 #define AIPS_PACRD_TP7_SHIFT                     (0U)
-#define AIPS_PACRD_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK)
+#define AIPS_PACRD_TP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK)
+#define AIPS_PACRD_TP7 AIPS_PACRD_TP7_MASK
 #define AIPS_PACRD_WP7_MASK                      (0x2U)
 #define AIPS_PACRD_WP7_SHIFT                     (1U)
-#define AIPS_PACRD_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK)
+#define AIPS_PACRD_WP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK)
+#define AIPS_PACRD_WP7 AIPS_PACRD_WP7_MASK
 #define AIPS_PACRD_SP7_MASK                      (0x4U)
 #define AIPS_PACRD_SP7_SHIFT                     (2U)
-#define AIPS_PACRD_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK)
+#define AIPS_PACRD_SP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK)
+#define AIPS_PACRD_SP7 AIPS_PACRD_SP7_MASK
 #define AIPS_PACRD_TP6_MASK                      (0x10U)
 #define AIPS_PACRD_TP6_SHIFT                     (4U)
-#define AIPS_PACRD_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK)
+#define AIPS_PACRD_TP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK)
+#define AIPS_PACRD_TP6 AIPS_PACRD_TP6_MASK
 #define AIPS_PACRD_WP6_MASK                      (0x20U)
 #define AIPS_PACRD_WP6_SHIFT                     (5U)
-#define AIPS_PACRD_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK)
+#define AIPS_PACRD_WP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK)
+#define AIPS_PACRD_WP6 AIPS_PACRD_WP6_MASK
 #define AIPS_PACRD_SP6_MASK                      (0x40U)
 #define AIPS_PACRD_SP6_SHIFT                     (6U)
-#define AIPS_PACRD_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK)
+#define AIPS_PACRD_SP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK)
+#define AIPS_PACRD_SP6 AIPS_PACRD_SP6_MASK
 #define AIPS_PACRD_TP5_MASK                      (0x100U)
 #define AIPS_PACRD_TP5_SHIFT                     (8U)
-#define AIPS_PACRD_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK)
+#define AIPS_PACRD_TP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK)
+#define AIPS_PACRD_TP5 AIPS_PACRD_TP5_MASK
 #define AIPS_PACRD_WP5_MASK                      (0x200U)
 #define AIPS_PACRD_WP5_SHIFT                     (9U)
-#define AIPS_PACRD_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK)
+#define AIPS_PACRD_WP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK)
+#define AIPS_PACRD_WP5 AIPS_PACRD_WP5_MASK
 #define AIPS_PACRD_SP5_MASK                      (0x400U)
 #define AIPS_PACRD_SP5_SHIFT                     (10U)
-#define AIPS_PACRD_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK)
+#define AIPS_PACRD_SP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK)
+#define AIPS_PACRD_SP5 AIPS_PACRD_SP5_MASK
 #define AIPS_PACRD_TP4_MASK                      (0x1000U)
 #define AIPS_PACRD_TP4_SHIFT                     (12U)
-#define AIPS_PACRD_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK)
+#define AIPS_PACRD_TP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK)
+#define AIPS_PACRD_TP4 AIPS_PACRD_TP4_MASK
 #define AIPS_PACRD_WP4_MASK                      (0x2000U)
 #define AIPS_PACRD_WP4_SHIFT                     (13U)
-#define AIPS_PACRD_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK)
+#define AIPS_PACRD_WP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK)
+#define AIPS_PACRD_WP4 AIPS_PACRD_WP4_MASK
 #define AIPS_PACRD_SP4_MASK                      (0x4000U)
 #define AIPS_PACRD_SP4_SHIFT                     (14U)
-#define AIPS_PACRD_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK)
+#define AIPS_PACRD_SP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK)
+#define AIPS_PACRD_SP4 AIPS_PACRD_SP4_MASK
 #define AIPS_PACRD_TP3_MASK                      (0x10000U)
 #define AIPS_PACRD_TP3_SHIFT                     (16U)
-#define AIPS_PACRD_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK)
+#define AIPS_PACRD_TP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK)
+#define AIPS_PACRD_TP3 AIPS_PACRD_TP3_MASK
 #define AIPS_PACRD_WP3_MASK                      (0x20000U)
 #define AIPS_PACRD_WP3_SHIFT                     (17U)
-#define AIPS_PACRD_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK)
+#define AIPS_PACRD_WP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK)
+#define AIPS_PACRD_WP3 AIPS_PACRD_WP3_MASK
 #define AIPS_PACRD_SP3_MASK                      (0x40000U)
 #define AIPS_PACRD_SP3_SHIFT                     (18U)
-#define AIPS_PACRD_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK)
+#define AIPS_PACRD_SP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK)
+#define AIPS_PACRD_SP3 AIPS_PACRD_SP3_MASK
 #define AIPS_PACRD_TP2_MASK                      (0x100000U)
 #define AIPS_PACRD_TP2_SHIFT                     (20U)
-#define AIPS_PACRD_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK)
+#define AIPS_PACRD_TP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK)
+#define AIPS_PACRD_TP2 AIPS_PACRD_TP2_MASK
 #define AIPS_PACRD_WP2_MASK                      (0x200000U)
 #define AIPS_PACRD_WP2_SHIFT                     (21U)
-#define AIPS_PACRD_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK)
+#define AIPS_PACRD_WP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK)
+#define AIPS_PACRD_WP2 AIPS_PACRD_WP2_MASK
 #define AIPS_PACRD_SP2_MASK                      (0x400000U)
 #define AIPS_PACRD_SP2_SHIFT                     (22U)
-#define AIPS_PACRD_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK)
+#define AIPS_PACRD_SP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK)
+#define AIPS_PACRD_SP2 AIPS_PACRD_SP2_MASK
 #define AIPS_PACRD_TP1_MASK                      (0x1000000U)
 #define AIPS_PACRD_TP1_SHIFT                     (24U)
-#define AIPS_PACRD_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK)
+#define AIPS_PACRD_TP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK)
+#define AIPS_PACRD_TP1 AIPS_PACRD_TP1_MASK
 #define AIPS_PACRD_WP1_MASK                      (0x2000000U)
 #define AIPS_PACRD_WP1_SHIFT                     (25U)
-#define AIPS_PACRD_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK)
+#define AIPS_PACRD_WP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK)
+#define AIPS_PACRD_WP1 AIPS_PACRD_WP1_MASK
 #define AIPS_PACRD_SP1_MASK                      (0x4000000U)
 #define AIPS_PACRD_SP1_SHIFT                     (26U)
-#define AIPS_PACRD_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK)
+#define AIPS_PACRD_SP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK)
+#define AIPS_PACRD_SP1 AIPS_PACRD_SP1_MASK
 #define AIPS_PACRD_TP0_MASK                      (0x10000000U)
 #define AIPS_PACRD_TP0_SHIFT                     (28U)
-#define AIPS_PACRD_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK)
+#define AIPS_PACRD_TP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK)
+#define AIPS_PACRD_TP0 AIPS_PACRD_TP0_MASK
 #define AIPS_PACRD_WP0_MASK                      (0x20000000U)
 #define AIPS_PACRD_WP0_SHIFT                     (29U)
-#define AIPS_PACRD_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK)
+#define AIPS_PACRD_WP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK)
+#define AIPS_PACRD_WP0 AIPS_PACRD_WP0_MASK
 #define AIPS_PACRD_SP0_MASK                      (0x40000000U)
 #define AIPS_PACRD_SP0_SHIFT                     (30U)
-#define AIPS_PACRD_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK)
+#define AIPS_PACRD_SP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK)
+#define AIPS_PACRD_SP0 AIPS_PACRD_SP0_MASK
 
 /*! @name PACRE - Peripheral Access Control Register */
 #define AIPS_PACRE_TP7_MASK                      (0x1U)
 #define AIPS_PACRE_TP7_SHIFT                     (0U)
-#define AIPS_PACRE_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK)
+#define AIPS_PACRE_TP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK)
+#define AIPS_PACRE_TP7 AIPS_PACRE_TP7_MASK
 #define AIPS_PACRE_WP7_MASK                      (0x2U)
 #define AIPS_PACRE_WP7_SHIFT                     (1U)
-#define AIPS_PACRE_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK)
+#define AIPS_PACRE_WP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK)
+#define AIPS_PACRE_WP7 AIPS_PACRE_WP7_MASK
 #define AIPS_PACRE_SP7_MASK                      (0x4U)
 #define AIPS_PACRE_SP7_SHIFT                     (2U)
-#define AIPS_PACRE_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK)
+#define AIPS_PACRE_SP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK)
+#define AIPS_PACRE_SP7 AIPS_PACRE_SP7_MASK
 #define AIPS_PACRE_TP6_MASK                      (0x10U)
 #define AIPS_PACRE_TP6_SHIFT                     (4U)
-#define AIPS_PACRE_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK)
+#define AIPS_PACRE_TP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK)
+#define AIPS_PACRE_TP6 AIPS_PACRE_TP6_MASK
 #define AIPS_PACRE_WP6_MASK                      (0x20U)
 #define AIPS_PACRE_WP6_SHIFT                     (5U)
-#define AIPS_PACRE_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK)
+#define AIPS_PACRE_WP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK)
+#define AIPS_PACRE_WP6 AIPS_PACRE_WP6_MASK
 #define AIPS_PACRE_SP6_MASK                      (0x40U)
 #define AIPS_PACRE_SP6_SHIFT                     (6U)
-#define AIPS_PACRE_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK)
+#define AIPS_PACRE_SP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK)
+#define AIPS_PACRE_SP6 AIPS_PACRE_SP6_MASK
 #define AIPS_PACRE_TP5_MASK                      (0x100U)
 #define AIPS_PACRE_TP5_SHIFT                     (8U)
-#define AIPS_PACRE_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK)
+#define AIPS_PACRE_TP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK)
+#define AIPS_PACRE_TP5 AIPS_PACRE_TP5_MASK
 #define AIPS_PACRE_WP5_MASK                      (0x200U)
 #define AIPS_PACRE_WP5_SHIFT                     (9U)
-#define AIPS_PACRE_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK)
+#define AIPS_PACRE_WP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK)
+#define AIPS_PACRE_WP5 AIPS_PACRE_WP5_MASK
 #define AIPS_PACRE_SP5_MASK                      (0x400U)
 #define AIPS_PACRE_SP5_SHIFT                     (10U)
-#define AIPS_PACRE_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK)
+#define AIPS_PACRE_SP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK)
+#define AIPS_PACRE_SP5 AIPS_PACRE_SP5_MASK
 #define AIPS_PACRE_TP4_MASK                      (0x1000U)
 #define AIPS_PACRE_TP4_SHIFT                     (12U)
-#define AIPS_PACRE_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK)
+#define AIPS_PACRE_TP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK)
+#define AIPS_PACRE_TP4 AIPS_PACRE_TP4_MASK
 #define AIPS_PACRE_WP4_MASK                      (0x2000U)
 #define AIPS_PACRE_WP4_SHIFT                     (13U)
-#define AIPS_PACRE_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK)
+#define AIPS_PACRE_WP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK)
+#define AIPS_PACRE_WP4 AIPS_PACRE_WP4_MASK
 #define AIPS_PACRE_SP4_MASK                      (0x4000U)
 #define AIPS_PACRE_SP4_SHIFT                     (14U)
-#define AIPS_PACRE_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK)
+#define AIPS_PACRE_SP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK)
+#define AIPS_PACRE_SP4 AIPS_PACRE_SP4_MASK
 #define AIPS_PACRE_TP3_MASK                      (0x10000U)
 #define AIPS_PACRE_TP3_SHIFT                     (16U)
-#define AIPS_PACRE_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK)
+#define AIPS_PACRE_TP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK)
+#define AIPS_PACRE_TP3 AIPS_PACRE_TP3_MASK
 #define AIPS_PACRE_WP3_MASK                      (0x20000U)
 #define AIPS_PACRE_WP3_SHIFT                     (17U)
-#define AIPS_PACRE_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK)
+#define AIPS_PACRE_WP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK)
+#define AIPS_PACRE_WP3 AIPS_PACRE_WP3_MASK
 #define AIPS_PACRE_SP3_MASK                      (0x40000U)
 #define AIPS_PACRE_SP3_SHIFT                     (18U)
-#define AIPS_PACRE_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK)
+#define AIPS_PACRE_SP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK)
+#define AIPS_PACRE_SP3 AIPS_PACRE_SP3_MASK
 #define AIPS_PACRE_TP2_MASK                      (0x100000U)
 #define AIPS_PACRE_TP2_SHIFT                     (20U)
-#define AIPS_PACRE_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK)
+#define AIPS_PACRE_TP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK)
+#define AIPS_PACRE_TP2 AIPS_PACRE_TP2_MASK
 #define AIPS_PACRE_WP2_MASK                      (0x200000U)
 #define AIPS_PACRE_WP2_SHIFT                     (21U)
-#define AIPS_PACRE_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK)
+#define AIPS_PACRE_WP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK)
+#define AIPS_PACRE_WP2 AIPS_PACRE_WP2_MASK
 #define AIPS_PACRE_SP2_MASK                      (0x400000U)
 #define AIPS_PACRE_SP2_SHIFT                     (22U)
-#define AIPS_PACRE_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK)
+#define AIPS_PACRE_SP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK)
+#define AIPS_PACRE_SP2 AIPS_PACRE_SP2_MASK
 #define AIPS_PACRE_TP1_MASK                      (0x1000000U)
 #define AIPS_PACRE_TP1_SHIFT                     (24U)
-#define AIPS_PACRE_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK)
+#define AIPS_PACRE_TP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK)
+#define AIPS_PACRE_TP1 AIPS_PACRE_TP1_MASK
 #define AIPS_PACRE_WP1_MASK                      (0x2000000U)
 #define AIPS_PACRE_WP1_SHIFT                     (25U)
-#define AIPS_PACRE_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK)
+#define AIPS_PACRE_WP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK)
+#define AIPS_PACRE_WP1 AIPS_PACRE_WP1_MASK
 #define AIPS_PACRE_SP1_MASK                      (0x4000000U)
 #define AIPS_PACRE_SP1_SHIFT                     (26U)
-#define AIPS_PACRE_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK)
+#define AIPS_PACRE_SP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK)
+#define AIPS_PACRE_SP1 AIPS_PACRE_SP1_MASK
 #define AIPS_PACRE_TP0_MASK                      (0x10000000U)
 #define AIPS_PACRE_TP0_SHIFT                     (28U)
-#define AIPS_PACRE_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK)
+#define AIPS_PACRE_TP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK)
+#define AIPS_PACRE_TP0 AIPS_PACRE_TP0_MASK
 #define AIPS_PACRE_WP0_MASK                      (0x20000000U)
 #define AIPS_PACRE_WP0_SHIFT                     (29U)
-#define AIPS_PACRE_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK)
+#define AIPS_PACRE_WP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK)
+#define AIPS_PACRE_WP0 AIPS_PACRE_WP0_MASK
 #define AIPS_PACRE_SP0_MASK                      (0x40000000U)
 #define AIPS_PACRE_SP0_SHIFT                     (30U)
-#define AIPS_PACRE_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK)
+#define AIPS_PACRE_SP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK)
+#define AIPS_PACRE_SP0 AIPS_PACRE_SP0_MASK
 
 /*! @name PACRF - Peripheral Access Control Register */
 #define AIPS_PACRF_TP7_MASK                      (0x1U)
 #define AIPS_PACRF_TP7_SHIFT                     (0U)
-#define AIPS_PACRF_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK)
+#define AIPS_PACRF_TP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK)
+#define AIPS_PACRF_TP7 AIPS_PACRF_TP7_MASK
 #define AIPS_PACRF_WP7_MASK                      (0x2U)
 #define AIPS_PACRF_WP7_SHIFT                     (1U)
-#define AIPS_PACRF_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK)
+#define AIPS_PACRF_WP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK)
+#define AIPS_PACRF_WP7 AIPS_PACRF_WP7_MASK
 #define AIPS_PACRF_SP7_MASK                      (0x4U)
 #define AIPS_PACRF_SP7_SHIFT                     (2U)
-#define AIPS_PACRF_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK)
+#define AIPS_PACRF_SP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK)
+#define AIPS_PACRF_SP7 AIPS_PACRF_SP7_MASK
 #define AIPS_PACRF_TP6_MASK                      (0x10U)
 #define AIPS_PACRF_TP6_SHIFT                     (4U)
-#define AIPS_PACRF_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK)
+#define AIPS_PACRF_TP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK)
+#define AIPS_PACRF_TP6 AIPS_PACRF_TP6_MASK
 #define AIPS_PACRF_WP6_MASK                      (0x20U)
 #define AIPS_PACRF_WP6_SHIFT                     (5U)
-#define AIPS_PACRF_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK)
+#define AIPS_PACRF_WP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK)
+#define AIPS_PACRF_WP6 AIPS_PACRF_WP6_MASK
 #define AIPS_PACRF_SP6_MASK                      (0x40U)
 #define AIPS_PACRF_SP6_SHIFT                     (6U)
-#define AIPS_PACRF_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK)
+#define AIPS_PACRF_SP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK)
+#define AIPS_PACRF_SP6 AIPS_PACRF_SP6_MASK
 #define AIPS_PACRF_TP5_MASK                      (0x100U)
 #define AIPS_PACRF_TP5_SHIFT                     (8U)
-#define AIPS_PACRF_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK)
+#define AIPS_PACRF_TP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK)
+#define AIPS_PACRF_TP5 AIPS_PACRF_TP5_MASK
 #define AIPS_PACRF_WP5_MASK                      (0x200U)
 #define AIPS_PACRF_WP5_SHIFT                     (9U)
-#define AIPS_PACRF_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK)
+#define AIPS_PACRF_WP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK)
+#define AIPS_PACRF_WP5 AIPS_PACRF_WP5_MASK
 #define AIPS_PACRF_SP5_MASK                      (0x400U)
 #define AIPS_PACRF_SP5_SHIFT                     (10U)
-#define AIPS_PACRF_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK)
+#define AIPS_PACRF_SP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK)
+#define AIPS_PACRF_SP5 AIPS_PACRF_SP5_MASK
 #define AIPS_PACRF_TP4_MASK                      (0x1000U)
 #define AIPS_PACRF_TP4_SHIFT                     (12U)
-#define AIPS_PACRF_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK)
+#define AIPS_PACRF_TP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK)
+#define AIPS_PACRF_TP4 AIPS_PACRF_TP4_MASK
 #define AIPS_PACRF_WP4_MASK                      (0x2000U)
 #define AIPS_PACRF_WP4_SHIFT                     (13U)
-#define AIPS_PACRF_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK)
+#define AIPS_PACRF_WP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK)
+#define AIPS_PACRF_WP4 AIPS_PACRF_WP4_MASK
 #define AIPS_PACRF_SP4_MASK                      (0x4000U)
 #define AIPS_PACRF_SP4_SHIFT                     (14U)
-#define AIPS_PACRF_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK)
+#define AIPS_PACRF_SP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK)
+#define AIPS_PACRF_SP4 AIPS_PACRF_SP4_MASK
 #define AIPS_PACRF_TP3_MASK                      (0x10000U)
 #define AIPS_PACRF_TP3_SHIFT                     (16U)
-#define AIPS_PACRF_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK)
+#define AIPS_PACRF_TP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK)
+#define AIPS_PACRF_TP3 AIPS_PACRF_TP3_MASK
 #define AIPS_PACRF_WP3_MASK                      (0x20000U)
 #define AIPS_PACRF_WP3_SHIFT                     (17U)
-#define AIPS_PACRF_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK)
+#define AIPS_PACRF_WP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK)
+#define AIPS_PACRF_WP3 AIPS_PACRF_WP3_MASK
 #define AIPS_PACRF_SP3_MASK                      (0x40000U)
 #define AIPS_PACRF_SP3_SHIFT                     (18U)
-#define AIPS_PACRF_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK)
+#define AIPS_PACRF_SP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK)
+#define AIPS_PACRF_SP3 AIPS_PACRF_SP3_MASK
 #define AIPS_PACRF_TP2_MASK                      (0x100000U)
 #define AIPS_PACRF_TP2_SHIFT                     (20U)
-#define AIPS_PACRF_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK)
+#define AIPS_PACRF_TP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK)
+#define AIPS_PACRF_TP2 AIPS_PACRF_TP2_MASK
 #define AIPS_PACRF_WP2_MASK                      (0x200000U)
 #define AIPS_PACRF_WP2_SHIFT                     (21U)
-#define AIPS_PACRF_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK)
+#define AIPS_PACRF_WP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK)
+#define AIPS_PACRF_WP2 AIPS_PACRF_WP2_MASK
 #define AIPS_PACRF_SP2_MASK                      (0x400000U)
 #define AIPS_PACRF_SP2_SHIFT                     (22U)
-#define AIPS_PACRF_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK)
+#define AIPS_PACRF_SP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK)
+#define AIPS_PACRF_SP2 AIPS_PACRF_SP2_MASK
 #define AIPS_PACRF_TP1_MASK                      (0x1000000U)
 #define AIPS_PACRF_TP1_SHIFT                     (24U)
-#define AIPS_PACRF_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK)
+#define AIPS_PACRF_TP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK)
+#define AIPS_PACRF_TP1 AIPS_PACRF_TP1_MASK
 #define AIPS_PACRF_WP1_MASK                      (0x2000000U)
 #define AIPS_PACRF_WP1_SHIFT                     (25U)
-#define AIPS_PACRF_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK)
+#define AIPS_PACRF_WP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK)
+#define AIPS_PACRF_WP1 AIPS_PACRF_WP1_MASK
 #define AIPS_PACRF_SP1_MASK                      (0x4000000U)
 #define AIPS_PACRF_SP1_SHIFT                     (26U)
-#define AIPS_PACRF_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK)
+#define AIPS_PACRF_SP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK)
+#define AIPS_PACRF_SP1 AIPS_PACRF_SP1_MASK
 #define AIPS_PACRF_TP0_MASK                      (0x10000000U)
 #define AIPS_PACRF_TP0_SHIFT                     (28U)
-#define AIPS_PACRF_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK)
+#define AIPS_PACRF_TP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK)
+#define AIPS_PACRF_TP0 AIPS_PACRF_TP0_MASK
 #define AIPS_PACRF_WP0_MASK                      (0x20000000U)
 #define AIPS_PACRF_WP0_SHIFT                     (29U)
-#define AIPS_PACRF_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK)
+#define AIPS_PACRF_WP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK)
+#define AIPS_PACRF_WP0 AIPS_PACRF_WP0_MASK
 #define AIPS_PACRF_SP0_MASK                      (0x40000000U)
 #define AIPS_PACRF_SP0_SHIFT                     (30U)
-#define AIPS_PACRF_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK)
+#define AIPS_PACRF_SP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK)
+#define AIPS_PACRF_SP0 AIPS_PACRF_SP0_MASK
 
 /*! @name PACRG - Peripheral Access Control Register */
 #define AIPS_PACRG_TP7_MASK                      (0x1U)
 #define AIPS_PACRG_TP7_SHIFT                     (0U)
-#define AIPS_PACRG_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK)
+#define AIPS_PACRG_TP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK)
+#define AIPS_PACRG_TP7 AIPS_PACRG_TP7_MASK
 #define AIPS_PACRG_WP7_MASK                      (0x2U)
 #define AIPS_PACRG_WP7_SHIFT                     (1U)
-#define AIPS_PACRG_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK)
+#define AIPS_PACRG_WP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK)
+#define AIPS_PACRG_WP7 AIPS_PACRG_WP7_MASK
 #define AIPS_PACRG_SP7_MASK                      (0x4U)
 #define AIPS_PACRG_SP7_SHIFT                     (2U)
-#define AIPS_PACRG_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK)
+#define AIPS_PACRG_SP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK)
+#define AIPS_PACRG_SP7 AIPS_PACRG_SP7_MASK
 #define AIPS_PACRG_TP6_MASK                      (0x10U)
 #define AIPS_PACRG_TP6_SHIFT                     (4U)
-#define AIPS_PACRG_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK)
+#define AIPS_PACRG_TP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK)
+#define AIPS_PACRG_TP6 AIPS_PACRG_TP6_MASK
 #define AIPS_PACRG_WP6_MASK                      (0x20U)
 #define AIPS_PACRG_WP6_SHIFT                     (5U)
-#define AIPS_PACRG_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK)
+#define AIPS_PACRG_WP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK)
+#define AIPS_PACRG_WP6 AIPS_PACRG_WP6_MASK
 #define AIPS_PACRG_SP6_MASK                      (0x40U)
 #define AIPS_PACRG_SP6_SHIFT                     (6U)
-#define AIPS_PACRG_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK)
+#define AIPS_PACRG_SP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK)
+#define AIPS_PACRG_SP6 AIPS_PACRG_SP6_MASK
 #define AIPS_PACRG_TP5_MASK                      (0x100U)
 #define AIPS_PACRG_TP5_SHIFT                     (8U)
-#define AIPS_PACRG_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK)
+#define AIPS_PACRG_TP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK)
+#define AIPS_PACRG_TP5 AIPS_PACRG_TP5_MASK
 #define AIPS_PACRG_WP5_MASK                      (0x200U)
 #define AIPS_PACRG_WP5_SHIFT                     (9U)
-#define AIPS_PACRG_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK)
+#define AIPS_PACRG_WP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK)
+#define AIPS_PACRG_WP5 AIPS_PACRG_WP5_MASK
 #define AIPS_PACRG_SP5_MASK                      (0x400U)
 #define AIPS_PACRG_SP5_SHIFT                     (10U)
-#define AIPS_PACRG_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK)
+#define AIPS_PACRG_SP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK)
+#define AIPS_PACRG_SP5 AIPS_PACRG_SP5_MASK
 #define AIPS_PACRG_TP4_MASK                      (0x1000U)
 #define AIPS_PACRG_TP4_SHIFT                     (12U)
-#define AIPS_PACRG_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK)
+#define AIPS_PACRG_TP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK)
+#define AIPS_PACRG_TP4 AIPS_PACRG_TP4_MASK
 #define AIPS_PACRG_WP4_MASK                      (0x2000U)
 #define AIPS_PACRG_WP4_SHIFT                     (13U)
-#define AIPS_PACRG_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK)
+#define AIPS_PACRG_WP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK)
+#define AIPS_PACRG_WP4 AIPS_PACRG_WP4_MASK
 #define AIPS_PACRG_SP4_MASK                      (0x4000U)
 #define AIPS_PACRG_SP4_SHIFT                     (14U)
-#define AIPS_PACRG_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK)
+#define AIPS_PACRG_SP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK)
+#define AIPS_PACRG_SP4 AIPS_PACRG_SP4_MASK
 #define AIPS_PACRG_TP3_MASK                      (0x10000U)
 #define AIPS_PACRG_TP3_SHIFT                     (16U)
-#define AIPS_PACRG_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK)
+#define AIPS_PACRG_TP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK)
+#define AIPS_PACRG_TP3 AIPS_PACRG_TP3_MASK
 #define AIPS_PACRG_WP3_MASK                      (0x20000U)
 #define AIPS_PACRG_WP3_SHIFT                     (17U)
-#define AIPS_PACRG_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK)
+#define AIPS_PACRG_WP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK)
+#define AIPS_PACRG_WP3 AIPS_PACRG_WP3_MASK
 #define AIPS_PACRG_SP3_MASK                      (0x40000U)
 #define AIPS_PACRG_SP3_SHIFT                     (18U)
-#define AIPS_PACRG_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK)
+#define AIPS_PACRG_SP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK)
+#define AIPS_PACRG_SP3 AIPS_PACRG_SP3_MASK
 #define AIPS_PACRG_TP2_MASK                      (0x100000U)
 #define AIPS_PACRG_TP2_SHIFT                     (20U)
-#define AIPS_PACRG_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK)
+#define AIPS_PACRG_TP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK)
+#define AIPS_PACRG_TP2 AIPS_PACRG_TP2_MASK
 #define AIPS_PACRG_WP2_MASK                      (0x200000U)
 #define AIPS_PACRG_WP2_SHIFT                     (21U)
-#define AIPS_PACRG_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK)
+#define AIPS_PACRG_WP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK)
+#define AIPS_PACRG_WP2 AIPS_PACRG_WP2_MASK
 #define AIPS_PACRG_SP2_MASK                      (0x400000U)
 #define AIPS_PACRG_SP2_SHIFT                     (22U)
-#define AIPS_PACRG_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK)
+#define AIPS_PACRG_SP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK)
+#define AIPS_PACRG_SP2 AIPS_PACRG_SP2_MASK
 #define AIPS_PACRG_TP1_MASK                      (0x1000000U)
 #define AIPS_PACRG_TP1_SHIFT                     (24U)
-#define AIPS_PACRG_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK)
+#define AIPS_PACRG_TP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK)
+#define AIPS_PACRG_TP1 AIPS_PACRG_TP1_MASK
 #define AIPS_PACRG_WP1_MASK                      (0x2000000U)
 #define AIPS_PACRG_WP1_SHIFT                     (25U)
-#define AIPS_PACRG_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK)
+#define AIPS_PACRG_WP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK)
+#define AIPS_PACRG_WP1 AIPS_PACRG_WP1_MASK
 #define AIPS_PACRG_SP1_MASK                      (0x4000000U)
 #define AIPS_PACRG_SP1_SHIFT                     (26U)
-#define AIPS_PACRG_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK)
+#define AIPS_PACRG_SP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK)
+#define AIPS_PACRG_SP1 AIPS_PACRG_SP1_MASK
 #define AIPS_PACRG_TP0_MASK                      (0x10000000U)
 #define AIPS_PACRG_TP0_SHIFT                     (28U)
-#define AIPS_PACRG_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK)
+#define AIPS_PACRG_TP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK)
+#define AIPS_PACRG_TP0 AIPS_PACRG_TP0_MASK
 #define AIPS_PACRG_WP0_MASK                      (0x20000000U)
 #define AIPS_PACRG_WP0_SHIFT                     (29U)
-#define AIPS_PACRG_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK)
+#define AIPS_PACRG_WP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK)
+#define AIPS_PACRG_WP0 AIPS_PACRG_WP0_MASK
 #define AIPS_PACRG_SP0_MASK                      (0x40000000U)
 #define AIPS_PACRG_SP0_SHIFT                     (30U)
-#define AIPS_PACRG_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK)
+#define AIPS_PACRG_SP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK)
+#define AIPS_PACRG_SP0 AIPS_PACRG_SP0_MASK
 
 /*! @name PACRH - Peripheral Access Control Register */
 #define AIPS_PACRH_TP7_MASK                      (0x1U)
 #define AIPS_PACRH_TP7_SHIFT                     (0U)
-#define AIPS_PACRH_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK)
+#define AIPS_PACRH_TP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK)
+#define AIPS_PACRH_TP7 AIPS_PACRH_TP7_MASK
 #define AIPS_PACRH_WP7_MASK                      (0x2U)
 #define AIPS_PACRH_WP7_SHIFT                     (1U)
-#define AIPS_PACRH_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK)
+#define AIPS_PACRH_WP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK)
+#define AIPS_PACRH_WP7 AIPS_PACRH_WP7_MASK
 #define AIPS_PACRH_SP7_MASK                      (0x4U)
 #define AIPS_PACRH_SP7_SHIFT                     (2U)
-#define AIPS_PACRH_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK)
+#define AIPS_PACRH_SP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK)
+#define AIPS_PACRH_SP7 AIPS_PACRH_SP7_MASK
 #define AIPS_PACRH_TP6_MASK                      (0x10U)
 #define AIPS_PACRH_TP6_SHIFT                     (4U)
-#define AIPS_PACRH_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK)
+#define AIPS_PACRH_TP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK)
+#define AIPS_PACRH_TP6 AIPS_PACRH_TP6_MASK
 #define AIPS_PACRH_WP6_MASK                      (0x20U)
 #define AIPS_PACRH_WP6_SHIFT                     (5U)
-#define AIPS_PACRH_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK)
+#define AIPS_PACRH_WP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK)
+#define AIPS_PACRH_WP6 AIPS_PACRH_WP6_MASK
 #define AIPS_PACRH_SP6_MASK                      (0x40U)
 #define AIPS_PACRH_SP6_SHIFT                     (6U)
-#define AIPS_PACRH_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK)
+#define AIPS_PACRH_SP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK)
+#define AIPS_PACRH_SP6 AIPS_PACRH_SP6_MASK
 #define AIPS_PACRH_TP5_MASK                      (0x100U)
 #define AIPS_PACRH_TP5_SHIFT                     (8U)
-#define AIPS_PACRH_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK)
+#define AIPS_PACRH_TP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK)
+#define AIPS_PACRH_TP5 AIPS_PACRH_TP5_MASK
 #define AIPS_PACRH_WP5_MASK                      (0x200U)
 #define AIPS_PACRH_WP5_SHIFT                     (9U)
-#define AIPS_PACRH_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK)
+#define AIPS_PACRH_WP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK)
+#define AIPS_PACRH_WP5 AIPS_PACRH_WP5_MASK
 #define AIPS_PACRH_SP5_MASK                      (0x400U)
 #define AIPS_PACRH_SP5_SHIFT                     (10U)
-#define AIPS_PACRH_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK)
+#define AIPS_PACRH_SP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK)
+#define AIPS_PACRH_SP5 AIPS_PACRH_SP5_MASK
 #define AIPS_PACRH_TP4_MASK                      (0x1000U)
 #define AIPS_PACRH_TP4_SHIFT                     (12U)
-#define AIPS_PACRH_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK)
+#define AIPS_PACRH_TP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK)
+#define AIPS_PACRH_TP4 AIPS_PACRH_TP4_MASK
 #define AIPS_PACRH_WP4_MASK                      (0x2000U)
 #define AIPS_PACRH_WP4_SHIFT                     (13U)
-#define AIPS_PACRH_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK)
+#define AIPS_PACRH_WP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK)
+#define AIPS_PACRH_WP4 AIPS_PACRH_WP4_MASK
 #define AIPS_PACRH_SP4_MASK                      (0x4000U)
 #define AIPS_PACRH_SP4_SHIFT                     (14U)
-#define AIPS_PACRH_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK)
+#define AIPS_PACRH_SP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK)
+#define AIPS_PACRH_SP4 AIPS_PACRH_SP4_MASK
 #define AIPS_PACRH_TP3_MASK                      (0x10000U)
 #define AIPS_PACRH_TP3_SHIFT                     (16U)
-#define AIPS_PACRH_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK)
+#define AIPS_PACRH_TP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK)
+#define AIPS_PACRH_TP3 AIPS_PACRH_TP3_MASK
 #define AIPS_PACRH_WP3_MASK                      (0x20000U)
 #define AIPS_PACRH_WP3_SHIFT                     (17U)
-#define AIPS_PACRH_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK)
+#define AIPS_PACRH_WP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK)
+#define AIPS_PACRH_WP3 AIPS_PACRH_WP3_MASK
 #define AIPS_PACRH_SP3_MASK                      (0x40000U)
 #define AIPS_PACRH_SP3_SHIFT                     (18U)
-#define AIPS_PACRH_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK)
+#define AIPS_PACRH_SP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK)
+#define AIPS_PACRH_SP3 AIPS_PACRH_SP3_MASK
 #define AIPS_PACRH_TP2_MASK                      (0x100000U)
 #define AIPS_PACRH_TP2_SHIFT                     (20U)
-#define AIPS_PACRH_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK)
+#define AIPS_PACRH_TP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK)
+#define AIPS_PACRH_TP2 AIPS_PACRH_TP2_MASK
 #define AIPS_PACRH_WP2_MASK                      (0x200000U)
 #define AIPS_PACRH_WP2_SHIFT                     (21U)
-#define AIPS_PACRH_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK)
+#define AIPS_PACRH_WP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK)
+#define AIPS_PACRH_WP2 AIPS_PACRH_WP2_MASK
 #define AIPS_PACRH_SP2_MASK                      (0x400000U)
 #define AIPS_PACRH_SP2_SHIFT                     (22U)
-#define AIPS_PACRH_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK)
+#define AIPS_PACRH_SP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK)
+#define AIPS_PACRH_SP2 AIPS_PACRH_SP2_MASK
 #define AIPS_PACRH_TP1_MASK                      (0x1000000U)
 #define AIPS_PACRH_TP1_SHIFT                     (24U)
-#define AIPS_PACRH_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK)
+#define AIPS_PACRH_TP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK)
+#define AIPS_PACRH_TP1 AIPS_PACRH_TP1_MASK
 #define AIPS_PACRH_WP1_MASK                      (0x2000000U)
 #define AIPS_PACRH_WP1_SHIFT                     (25U)
-#define AIPS_PACRH_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK)
+#define AIPS_PACRH_WP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK)
+#define AIPS_PACRH_WP1 AIPS_PACRH_WP1_MASK
 #define AIPS_PACRH_SP1_MASK                      (0x4000000U)
 #define AIPS_PACRH_SP1_SHIFT                     (26U)
-#define AIPS_PACRH_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK)
+#define AIPS_PACRH_SP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK)
+#define AIPS_PACRH_SP1 AIPS_PACRH_SP1_MASK
 #define AIPS_PACRH_TP0_MASK                      (0x10000000U)
 #define AIPS_PACRH_TP0_SHIFT                     (28U)
-#define AIPS_PACRH_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK)
+#define AIPS_PACRH_TP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK)
+#define AIPS_PACRH_TP0 AIPS_PACRH_TP0_MASK
 #define AIPS_PACRH_WP0_MASK                      (0x20000000U)
 #define AIPS_PACRH_WP0_SHIFT                     (29U)
-#define AIPS_PACRH_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK)
+#define AIPS_PACRH_WP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK)
+#define AIPS_PACRH_WP0 AIPS_PACRH_WP0_MASK
 #define AIPS_PACRH_SP0_MASK                      (0x40000000U)
 #define AIPS_PACRH_SP0_SHIFT                     (30U)
-#define AIPS_PACRH_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK)
+#define AIPS_PACRH_SP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK)
+#define AIPS_PACRH_SP0 AIPS_PACRH_SP0_MASK
 
 /*! @name PACRI - Peripheral Access Control Register */
 #define AIPS_PACRI_TP7_MASK                      (0x1U)
 #define AIPS_PACRI_TP7_SHIFT                     (0U)
-#define AIPS_PACRI_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK)
+#define AIPS_PACRI_TP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK)
+#define AIPS_PACRI_TP7 AIPS_PACRI_TP7_MASK
 #define AIPS_PACRI_WP7_MASK                      (0x2U)
 #define AIPS_PACRI_WP7_SHIFT                     (1U)
-#define AIPS_PACRI_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK)
+#define AIPS_PACRI_WP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK)
+#define AIPS_PACRI_WP7 AIPS_PACRI_WP7_MASK
 #define AIPS_PACRI_SP7_MASK                      (0x4U)
 #define AIPS_PACRI_SP7_SHIFT                     (2U)
-#define AIPS_PACRI_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK)
+#define AIPS_PACRI_SP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK)
+#define AIPS_PACRI_SP7 AIPS_PACRI_SP7_MASK
 #define AIPS_PACRI_TP6_MASK                      (0x10U)
 #define AIPS_PACRI_TP6_SHIFT                     (4U)
-#define AIPS_PACRI_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK)
+#define AIPS_PACRI_TP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK)
+#define AIPS_PACRI_TP6 AIPS_PACRI_TP6_MASK
 #define AIPS_PACRI_WP6_MASK                      (0x20U)
 #define AIPS_PACRI_WP6_SHIFT                     (5U)
-#define AIPS_PACRI_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK)
+#define AIPS_PACRI_WP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK)
+#define AIPS_PACRI_WP6 AIPS_PACRI_WP6_MASK
 #define AIPS_PACRI_SP6_MASK                      (0x40U)
 #define AIPS_PACRI_SP6_SHIFT                     (6U)
-#define AIPS_PACRI_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK)
+#define AIPS_PACRI_SP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK)
+#define AIPS_PACRI_SP6 AIPS_PACRI_SP6_MASK
 #define AIPS_PACRI_TP5_MASK                      (0x100U)
 #define AIPS_PACRI_TP5_SHIFT                     (8U)
-#define AIPS_PACRI_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK)
+#define AIPS_PACRI_TP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK)
+#define AIPS_PACRI_TP5 AIPS_PACRI_TP5_MASK
 #define AIPS_PACRI_WP5_MASK                      (0x200U)
 #define AIPS_PACRI_WP5_SHIFT                     (9U)
-#define AIPS_PACRI_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK)
+#define AIPS_PACRI_WP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK)
+#define AIPS_PACRI_WP5 AIPS_PACRI_WP5_MASK
 #define AIPS_PACRI_SP5_MASK                      (0x400U)
 #define AIPS_PACRI_SP5_SHIFT                     (10U)
-#define AIPS_PACRI_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK)
+#define AIPS_PACRI_SP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK)
+#define AIPS_PACRI_SP5 AIPS_PACRI_SP5_MASK
 #define AIPS_PACRI_TP4_MASK                      (0x1000U)
 #define AIPS_PACRI_TP4_SHIFT                     (12U)
-#define AIPS_PACRI_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK)
+#define AIPS_PACRI_TP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK)
+#define AIPS_PACRI_TP4 AIPS_PACRI_TP4_MASK
 #define AIPS_PACRI_WP4_MASK                      (0x2000U)
 #define AIPS_PACRI_WP4_SHIFT                     (13U)
-#define AIPS_PACRI_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK)
+#define AIPS_PACRI_WP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK)
+#define AIPS_PACRI_WP4 AIPS_PACRI_WP4_MASK
 #define AIPS_PACRI_SP4_MASK                      (0x4000U)
 #define AIPS_PACRI_SP4_SHIFT                     (14U)
-#define AIPS_PACRI_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK)
+#define AIPS_PACRI_SP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK)
+#define AIPS_PACRI_SP4 AIPS_PACRI_SP4_MASK
 #define AIPS_PACRI_TP3_MASK                      (0x10000U)
 #define AIPS_PACRI_TP3_SHIFT                     (16U)
-#define AIPS_PACRI_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK)
+#define AIPS_PACRI_TP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK)
+#define AIPS_PACRI_TP3 AIPS_PACRI_TP3_MASK
 #define AIPS_PACRI_WP3_MASK                      (0x20000U)
 #define AIPS_PACRI_WP3_SHIFT                     (17U)
-#define AIPS_PACRI_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK)
+#define AIPS_PACRI_WP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK)
+#define AIPS_PACRI_WP3 AIPS_PACRI_WP3_MASK
 #define AIPS_PACRI_SP3_MASK                      (0x40000U)
 #define AIPS_PACRI_SP3_SHIFT                     (18U)
-#define AIPS_PACRI_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK)
+#define AIPS_PACRI_SP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK)
+#define AIPS_PACRI_SP3 AIPS_PACRI_SP3_MASK
 #define AIPS_PACRI_TP2_MASK                      (0x100000U)
 #define AIPS_PACRI_TP2_SHIFT                     (20U)
-#define AIPS_PACRI_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK)
+#define AIPS_PACRI_TP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK)
+#define AIPS_PACRI_TP2 AIPS_PACRI_TP2_MASK
 #define AIPS_PACRI_WP2_MASK                      (0x200000U)
 #define AIPS_PACRI_WP2_SHIFT                     (21U)
-#define AIPS_PACRI_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK)
+#define AIPS_PACRI_WP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK)
+#define AIPS_PACRI_WP2 AIPS_PACRI_WP2_MASK
 #define AIPS_PACRI_SP2_MASK                      (0x400000U)
 #define AIPS_PACRI_SP2_SHIFT                     (22U)
-#define AIPS_PACRI_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK)
+#define AIPS_PACRI_SP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK)
+#define AIPS_PACRI_SP2 AIPS_PACRI_SP2_MASK
 #define AIPS_PACRI_TP1_MASK                      (0x1000000U)
 #define AIPS_PACRI_TP1_SHIFT                     (24U)
-#define AIPS_PACRI_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK)
+#define AIPS_PACRI_TP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK)
+#define AIPS_PACRI_TP1 AIPS_PACRI_TP1_MASK
 #define AIPS_PACRI_WP1_MASK                      (0x2000000U)
 #define AIPS_PACRI_WP1_SHIFT                     (25U)
-#define AIPS_PACRI_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK)
+#define AIPS_PACRI_WP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK)
+#define AIPS_PACRI_WP1 AIPS_PACRI_WP1_MASK
 #define AIPS_PACRI_SP1_MASK                      (0x4000000U)
 #define AIPS_PACRI_SP1_SHIFT                     (26U)
-#define AIPS_PACRI_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK)
+#define AIPS_PACRI_SP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK)
+#define AIPS_PACRI_SP1 AIPS_PACRI_SP1_MASK
 #define AIPS_PACRI_TP0_MASK                      (0x10000000U)
 #define AIPS_PACRI_TP0_SHIFT                     (28U)
-#define AIPS_PACRI_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK)
+#define AIPS_PACRI_TP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK)
+#define AIPS_PACRI_TP0 AIPS_PACRI_TP0_MASK
 #define AIPS_PACRI_WP0_MASK                      (0x20000000U)
 #define AIPS_PACRI_WP0_SHIFT                     (29U)
-#define AIPS_PACRI_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK)
+#define AIPS_PACRI_WP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK)
+#define AIPS_PACRI_WP0 AIPS_PACRI_WP0_MASK
 #define AIPS_PACRI_SP0_MASK                      (0x40000000U)
 #define AIPS_PACRI_SP0_SHIFT                     (30U)
-#define AIPS_PACRI_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK)
+#define AIPS_PACRI_SP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK)
+#define AIPS_PACRI_SP0 AIPS_PACRI_SP0_MASK
 
 /*! @name PACRJ - Peripheral Access Control Register */
 #define AIPS_PACRJ_TP7_MASK                      (0x1U)
 #define AIPS_PACRJ_TP7_SHIFT                     (0U)
-#define AIPS_PACRJ_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK)
+#define AIPS_PACRJ_TP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK)
+#define AIPS_PACRJ_TP7 AIPS_PACRJ_TP7_MASK
 #define AIPS_PACRJ_WP7_MASK                      (0x2U)
 #define AIPS_PACRJ_WP7_SHIFT                     (1U)
-#define AIPS_PACRJ_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK)
+#define AIPS_PACRJ_WP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK)
+#define AIPS_PACRJ_WP7 AIPS_PACRJ_WP7_MASK
 #define AIPS_PACRJ_SP7_MASK                      (0x4U)
 #define AIPS_PACRJ_SP7_SHIFT                     (2U)
-#define AIPS_PACRJ_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK)
+#define AIPS_PACRJ_SP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK)
+#define AIPS_PACRJ_SP7 AIPS_PACRJ_SP7_MASK
 #define AIPS_PACRJ_TP6_MASK                      (0x10U)
 #define AIPS_PACRJ_TP6_SHIFT                     (4U)
-#define AIPS_PACRJ_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK)
+#define AIPS_PACRJ_TP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK)
+#define AIPS_PACRJ_TP6 AIPS_PACRJ_TP6_MASK
 #define AIPS_PACRJ_WP6_MASK                      (0x20U)
 #define AIPS_PACRJ_WP6_SHIFT                     (5U)
-#define AIPS_PACRJ_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK)
+#define AIPS_PACRJ_WP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK)
+#define AIPS_PACRJ_WP6 AIPS_PACRJ_WP6_MASK
 #define AIPS_PACRJ_SP6_MASK                      (0x40U)
 #define AIPS_PACRJ_SP6_SHIFT                     (6U)
-#define AIPS_PACRJ_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK)
+#define AIPS_PACRJ_SP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK)
+#define AIPS_PACRJ_SP6 AIPS_PACRJ_SP6_MASK
 #define AIPS_PACRJ_TP5_MASK                      (0x100U)
 #define AIPS_PACRJ_TP5_SHIFT                     (8U)
-#define AIPS_PACRJ_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK)
+#define AIPS_PACRJ_TP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK)
+#define AIPS_PACRJ_TP5 AIPS_PACRJ_TP5_MASK
 #define AIPS_PACRJ_WP5_MASK                      (0x200U)
 #define AIPS_PACRJ_WP5_SHIFT                     (9U)
-#define AIPS_PACRJ_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK)
+#define AIPS_PACRJ_WP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK)
+#define AIPS_PACRJ_WP5 AIPS_PACRJ_WP5_MASK
 #define AIPS_PACRJ_SP5_MASK                      (0x400U)
 #define AIPS_PACRJ_SP5_SHIFT                     (10U)
-#define AIPS_PACRJ_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK)
+#define AIPS_PACRJ_SP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK)
+#define AIPS_PACRJ_SP5 AIPS_PACRJ_SP5_MASK
 #define AIPS_PACRJ_TP4_MASK                      (0x1000U)
 #define AIPS_PACRJ_TP4_SHIFT                     (12U)
-#define AIPS_PACRJ_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK)
+#define AIPS_PACRJ_TP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK)
+#define AIPS_PACRJ_TP4 AIPS_PACRJ_TP4_MASK
 #define AIPS_PACRJ_WP4_MASK                      (0x2000U)
 #define AIPS_PACRJ_WP4_SHIFT                     (13U)
-#define AIPS_PACRJ_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK)
+#define AIPS_PACRJ_WP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK)
+#define AIPS_PACRJ_WP4 AIPS_PACRJ_WP4_MASK
 #define AIPS_PACRJ_SP4_MASK                      (0x4000U)
 #define AIPS_PACRJ_SP4_SHIFT                     (14U)
-#define AIPS_PACRJ_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK)
+#define AIPS_PACRJ_SP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK)
+#define AIPS_PACRJ_SP4 AIPS_PACRJ_SP4_MASK
 #define AIPS_PACRJ_TP3_MASK                      (0x10000U)
 #define AIPS_PACRJ_TP3_SHIFT                     (16U)
-#define AIPS_PACRJ_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK)
+#define AIPS_PACRJ_TP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK)
+#define AIPS_PACRJ_TP3 AIPS_PACRJ_TP3_MASK
 #define AIPS_PACRJ_WP3_MASK                      (0x20000U)
 #define AIPS_PACRJ_WP3_SHIFT                     (17U)
-#define AIPS_PACRJ_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK)
+#define AIPS_PACRJ_WP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK)
+#define AIPS_PACRJ_WP3 AIPS_PACRJ_WP3_MASK
 #define AIPS_PACRJ_SP3_MASK                      (0x40000U)
 #define AIPS_PACRJ_SP3_SHIFT                     (18U)
-#define AIPS_PACRJ_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK)
+#define AIPS_PACRJ_SP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK)
+#define AIPS_PACRJ_SP3 AIPS_PACRJ_SP3_MASK
 #define AIPS_PACRJ_TP2_MASK                      (0x100000U)
 #define AIPS_PACRJ_TP2_SHIFT                     (20U)
-#define AIPS_PACRJ_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK)
+#define AIPS_PACRJ_TP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK)
+#define AIPS_PACRJ_TP2 AIPS_PACRJ_TP2_MASK
 #define AIPS_PACRJ_WP2_MASK                      (0x200000U)
 #define AIPS_PACRJ_WP2_SHIFT                     (21U)
-#define AIPS_PACRJ_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK)
+#define AIPS_PACRJ_WP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK)
+#define AIPS_PACRJ_WP2 AIPS_PACRJ_WP2_MASK
 #define AIPS_PACRJ_SP2_MASK                      (0x400000U)
 #define AIPS_PACRJ_SP2_SHIFT                     (22U)
-#define AIPS_PACRJ_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK)
+#define AIPS_PACRJ_SP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK)
+#define AIPS_PACRJ_SP2 AIPS_PACRJ_SP2_MASK
 #define AIPS_PACRJ_TP1_MASK                      (0x1000000U)
 #define AIPS_PACRJ_TP1_SHIFT                     (24U)
-#define AIPS_PACRJ_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK)
+#define AIPS_PACRJ_TP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK)
+#define AIPS_PACRJ_TP1 AIPS_PACRJ_TP1_MASK
 #define AIPS_PACRJ_WP1_MASK                      (0x2000000U)
 #define AIPS_PACRJ_WP1_SHIFT                     (25U)
-#define AIPS_PACRJ_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK)
+#define AIPS_PACRJ_WP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK)
+#define AIPS_PACRJ_WP1 AIPS_PACRJ_WP1_MASK
 #define AIPS_PACRJ_SP1_MASK                      (0x4000000U)
 #define AIPS_PACRJ_SP1_SHIFT                     (26U)
-#define AIPS_PACRJ_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK)
+#define AIPS_PACRJ_SP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK)
+#define AIPS_PACRJ_SP1 AIPS_PACRJ_SP1_MASK
 #define AIPS_PACRJ_TP0_MASK                      (0x10000000U)
 #define AIPS_PACRJ_TP0_SHIFT                     (28U)
-#define AIPS_PACRJ_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK)
+#define AIPS_PACRJ_TP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK)
+#define AIPS_PACRJ_TP0 AIPS_PACRJ_TP0_MASK
 #define AIPS_PACRJ_WP0_MASK                      (0x20000000U)
 #define AIPS_PACRJ_WP0_SHIFT                     (29U)
-#define AIPS_PACRJ_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK)
+#define AIPS_PACRJ_WP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK)
+#define AIPS_PACRJ_WP0 AIPS_PACRJ_WP0_MASK
 #define AIPS_PACRJ_SP0_MASK                      (0x40000000U)
 #define AIPS_PACRJ_SP0_SHIFT                     (30U)
-#define AIPS_PACRJ_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK)
+#define AIPS_PACRJ_SP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK)
+#define AIPS_PACRJ_SP0 AIPS_PACRJ_SP0_MASK
 
 /*! @name PACRK - Peripheral Access Control Register */
 #define AIPS_PACRK_TP7_MASK                      (0x1U)
 #define AIPS_PACRK_TP7_SHIFT                     (0U)
-#define AIPS_PACRK_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK)
+#define AIPS_PACRK_TP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK)
+#define AIPS_PACRK_TP7 AIPS_PACRK_TP7_MASK
 #define AIPS_PACRK_WP7_MASK                      (0x2U)
 #define AIPS_PACRK_WP7_SHIFT                     (1U)
-#define AIPS_PACRK_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK)
+#define AIPS_PACRK_WP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK)
+#define AIPS_PACRK_WP7 AIPS_PACRK_WP7_MASK
 #define AIPS_PACRK_SP7_MASK                      (0x4U)
 #define AIPS_PACRK_SP7_SHIFT                     (2U)
-#define AIPS_PACRK_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK)
+#define AIPS_PACRK_SP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK)
+#define AIPS_PACRK_SP7 AIPS_PACRK_SP7_MASK
 #define AIPS_PACRK_TP6_MASK                      (0x10U)
 #define AIPS_PACRK_TP6_SHIFT                     (4U)
-#define AIPS_PACRK_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK)
+#define AIPS_PACRK_TP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK)
+#define AIPS_PACRK_TP6 AIPS_PACRK_TP6_MASK
 #define AIPS_PACRK_WP6_MASK                      (0x20U)
 #define AIPS_PACRK_WP6_SHIFT                     (5U)
-#define AIPS_PACRK_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK)
+#define AIPS_PACRK_WP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK)
+#define AIPS_PACRK_WP6 AIPS_PACRK_WP6_MASK
 #define AIPS_PACRK_SP6_MASK                      (0x40U)
 #define AIPS_PACRK_SP6_SHIFT                     (6U)
-#define AIPS_PACRK_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK)
+#define AIPS_PACRK_SP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK)
+#define AIPS_PACRK_SP6 AIPS_PACRK_SP6_MASK
 #define AIPS_PACRK_TP5_MASK                      (0x100U)
 #define AIPS_PACRK_TP5_SHIFT                     (8U)
-#define AIPS_PACRK_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK)
+#define AIPS_PACRK_TP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK)
+#define AIPS_PACRK_TP5 AIPS_PACRK_TP5_MASK
 #define AIPS_PACRK_WP5_MASK                      (0x200U)
 #define AIPS_PACRK_WP5_SHIFT                     (9U)
-#define AIPS_PACRK_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK)
+#define AIPS_PACRK_WP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK)
+#define AIPS_PACRK_WP5 AIPS_PACRK_WP5_MASK
 #define AIPS_PACRK_SP5_MASK                      (0x400U)
 #define AIPS_PACRK_SP5_SHIFT                     (10U)
-#define AIPS_PACRK_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK)
+#define AIPS_PACRK_SP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK)
+#define AIPS_PACRK_SP5 AIPS_PACRK_SP5_MASK
 #define AIPS_PACRK_TP4_MASK                      (0x1000U)
 #define AIPS_PACRK_TP4_SHIFT                     (12U)
-#define AIPS_PACRK_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK)
+#define AIPS_PACRK_TP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK)
+#define AIPS_PACRK_TP4 AIPS_PACRK_TP4_MASK
 #define AIPS_PACRK_WP4_MASK                      (0x2000U)
 #define AIPS_PACRK_WP4_SHIFT                     (13U)
-#define AIPS_PACRK_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK)
+#define AIPS_PACRK_WP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK)
+#define AIPS_PACRK_WP4 AIPS_PACRK_WP4_MASK
 #define AIPS_PACRK_SP4_MASK                      (0x4000U)
 #define AIPS_PACRK_SP4_SHIFT                     (14U)
-#define AIPS_PACRK_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK)
+#define AIPS_PACRK_SP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK)
+#define AIPS_PACRK_SP4 AIPS_PACRK_SP4_MASK
 #define AIPS_PACRK_TP3_MASK                      (0x10000U)
 #define AIPS_PACRK_TP3_SHIFT                     (16U)
-#define AIPS_PACRK_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK)
+#define AIPS_PACRK_TP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK)
+#define AIPS_PACRK_TP3 AIPS_PACRK_TP3_MASK
 #define AIPS_PACRK_WP3_MASK                      (0x20000U)
 #define AIPS_PACRK_WP3_SHIFT                     (17U)
-#define AIPS_PACRK_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK)
+#define AIPS_PACRK_WP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK)
+#define AIPS_PACRK_WP3 AIPS_PACRK_WP3_MASK
 #define AIPS_PACRK_SP3_MASK                      (0x40000U)
 #define AIPS_PACRK_SP3_SHIFT                     (18U)
-#define AIPS_PACRK_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK)
+#define AIPS_PACRK_SP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK)
+#define AIPS_PACRK_SP3 AIPS_PACRK_SP3_MASK
 #define AIPS_PACRK_TP2_MASK                      (0x100000U)
 #define AIPS_PACRK_TP2_SHIFT                     (20U)
-#define AIPS_PACRK_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK)
+#define AIPS_PACRK_TP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK)
+#define AIPS_PACRK_TP2 AIPS_PACRK_TP2_MASK
 #define AIPS_PACRK_WP2_MASK                      (0x200000U)
 #define AIPS_PACRK_WP2_SHIFT                     (21U)
-#define AIPS_PACRK_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK)
+#define AIPS_PACRK_WP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK)
+#define AIPS_PACRK_WP2 AIPS_PACRK_WP2_MASK
 #define AIPS_PACRK_SP2_MASK                      (0x400000U)
 #define AIPS_PACRK_SP2_SHIFT                     (22U)
-#define AIPS_PACRK_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK)
+#define AIPS_PACRK_SP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK)
+#define AIPS_PACRK_SP2 AIPS_PACRK_SP2_MASK
 #define AIPS_PACRK_TP1_MASK                      (0x1000000U)
 #define AIPS_PACRK_TP1_SHIFT                     (24U)
-#define AIPS_PACRK_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK)
+#define AIPS_PACRK_TP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK)
+#define AIPS_PACRK_TP1 AIPS_PACRK_TP1_MASK
 #define AIPS_PACRK_WP1_MASK                      (0x2000000U)
 #define AIPS_PACRK_WP1_SHIFT                     (25U)
-#define AIPS_PACRK_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK)
+#define AIPS_PACRK_WP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK)
+#define AIPS_PACRK_WP1 AIPS_PACRK_WP1_MASK
 #define AIPS_PACRK_SP1_MASK                      (0x4000000U)
 #define AIPS_PACRK_SP1_SHIFT                     (26U)
-#define AIPS_PACRK_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK)
+#define AIPS_PACRK_SP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK)
+#define AIPS_PACRK_SP1 AIPS_PACRK_SP1_MASK
 #define AIPS_PACRK_TP0_MASK                      (0x10000000U)
 #define AIPS_PACRK_TP0_SHIFT                     (28U)
-#define AIPS_PACRK_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK)
+#define AIPS_PACRK_TP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK)
+#define AIPS_PACRK_TP0 AIPS_PACRK_TP0_MASK
 #define AIPS_PACRK_WP0_MASK                      (0x20000000U)
 #define AIPS_PACRK_WP0_SHIFT                     (29U)
-#define AIPS_PACRK_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK)
+#define AIPS_PACRK_WP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK)
+#define AIPS_PACRK_WP0 AIPS_PACRK_WP0_MASK
 #define AIPS_PACRK_SP0_MASK                      (0x40000000U)
 #define AIPS_PACRK_SP0_SHIFT                     (30U)
-#define AIPS_PACRK_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK)
+#define AIPS_PACRK_SP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK)
+#define AIPS_PACRK_SP0 AIPS_PACRK_SP0_MASK
 
 /*! @name PACRL - Peripheral Access Control Register */
 #define AIPS_PACRL_TP7_MASK                      (0x1U)
 #define AIPS_PACRL_TP7_SHIFT                     (0U)
-#define AIPS_PACRL_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK)
+#define AIPS_PACRL_TP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK)
+#define AIPS_PACRL_TP7 AIPS_PACRL_TP7_MASK
 #define AIPS_PACRL_WP7_MASK                      (0x2U)
 #define AIPS_PACRL_WP7_SHIFT                     (1U)
-#define AIPS_PACRL_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK)
+#define AIPS_PACRL_WP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK)
+#define AIPS_PACRL_WP7 AIPS_PACRL_WP7_MASK
 #define AIPS_PACRL_SP7_MASK                      (0x4U)
 #define AIPS_PACRL_SP7_SHIFT                     (2U)
-#define AIPS_PACRL_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK)
+#define AIPS_PACRL_SP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK)
+#define AIPS_PACRL_SP7 AIPS_PACRL_SP7_MASK
 #define AIPS_PACRL_TP6_MASK                      (0x10U)
 #define AIPS_PACRL_TP6_SHIFT                     (4U)
-#define AIPS_PACRL_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK)
+#define AIPS_PACRL_TP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK)
+#define AIPS_PACRL_TP6 AIPS_PACRL_TP6_MASK
 #define AIPS_PACRL_WP6_MASK                      (0x20U)
 #define AIPS_PACRL_WP6_SHIFT                     (5U)
-#define AIPS_PACRL_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK)
+#define AIPS_PACRL_WP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK)
+#define AIPS_PACRL_WP6 AIPS_PACRL_WP6_MASK
 #define AIPS_PACRL_SP6_MASK                      (0x40U)
 #define AIPS_PACRL_SP6_SHIFT                     (6U)
-#define AIPS_PACRL_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK)
+#define AIPS_PACRL_SP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK)
+#define AIPS_PACRL_SP6 AIPS_PACRL_SP6_MASK
 #define AIPS_PACRL_TP5_MASK                      (0x100U)
 #define AIPS_PACRL_TP5_SHIFT                     (8U)
-#define AIPS_PACRL_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK)
+#define AIPS_PACRL_TP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK)
+#define AIPS_PACRL_TP5 AIPS_PACRL_TP5_MASK
 #define AIPS_PACRL_WP5_MASK                      (0x200U)
 #define AIPS_PACRL_WP5_SHIFT                     (9U)
-#define AIPS_PACRL_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK)
+#define AIPS_PACRL_WP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK)
+#define AIPS_PACRL_WP5 AIPS_PACRL_WP5_MASK
 #define AIPS_PACRL_SP5_MASK                      (0x400U)
 #define AIPS_PACRL_SP5_SHIFT                     (10U)
-#define AIPS_PACRL_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK)
+#define AIPS_PACRL_SP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK)
+#define AIPS_PACRL_SP5 AIPS_PACRL_SP5_MASK
 #define AIPS_PACRL_TP4_MASK                      (0x1000U)
 #define AIPS_PACRL_TP4_SHIFT                     (12U)
-#define AIPS_PACRL_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK)
+#define AIPS_PACRL_TP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK)
+#define AIPS_PACRL_TP4 AIPS_PACRL_TP4_MASK
 #define AIPS_PACRL_WP4_MASK                      (0x2000U)
 #define AIPS_PACRL_WP4_SHIFT                     (13U)
-#define AIPS_PACRL_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK)
+#define AIPS_PACRL_WP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK)
+#define AIPS_PACRL_WP4 AIPS_PACRL_WP4_MASK
 #define AIPS_PACRL_SP4_MASK                      (0x4000U)
 #define AIPS_PACRL_SP4_SHIFT                     (14U)
-#define AIPS_PACRL_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK)
+#define AIPS_PACRL_SP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK)
+#define AIPS_PACRL_SP4 AIPS_PACRL_SP4_MASK
 #define AIPS_PACRL_TP3_MASK                      (0x10000U)
 #define AIPS_PACRL_TP3_SHIFT                     (16U)
-#define AIPS_PACRL_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK)
+#define AIPS_PACRL_TP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK)
+#define AIPS_PACRL_TP3 AIPS_PACRL_TP3_MASK
 #define AIPS_PACRL_WP3_MASK                      (0x20000U)
 #define AIPS_PACRL_WP3_SHIFT                     (17U)
-#define AIPS_PACRL_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK)
+#define AIPS_PACRL_WP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK)
+#define AIPS_PACRL_WP3 AIPS_PACRL_WP3_MASK
 #define AIPS_PACRL_SP3_MASK                      (0x40000U)
 #define AIPS_PACRL_SP3_SHIFT                     (18U)
-#define AIPS_PACRL_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK)
+#define AIPS_PACRL_SP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK)
+#define AIPS_PACRL_SP3 AIPS_PACRL_SP3_MASK
 #define AIPS_PACRL_TP2_MASK                      (0x100000U)
 #define AIPS_PACRL_TP2_SHIFT                     (20U)
-#define AIPS_PACRL_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK)
+#define AIPS_PACRL_TP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK)
+#define AIPS_PACRL_TP2 AIPS_PACRL_TP2_MASK
 #define AIPS_PACRL_WP2_MASK                      (0x200000U)
 #define AIPS_PACRL_WP2_SHIFT                     (21U)
-#define AIPS_PACRL_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK)
+#define AIPS_PACRL_WP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK)
+#define AIPS_PACRL_WP2 AIPS_PACRL_WP2_MASK
 #define AIPS_PACRL_SP2_MASK                      (0x400000U)
 #define AIPS_PACRL_SP2_SHIFT                     (22U)
-#define AIPS_PACRL_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK)
+#define AIPS_PACRL_SP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK)
+#define AIPS_PACRL_SP2 AIPS_PACRL_SP2_MASK
 #define AIPS_PACRL_TP1_MASK                      (0x1000000U)
 #define AIPS_PACRL_TP1_SHIFT                     (24U)
-#define AIPS_PACRL_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK)
+#define AIPS_PACRL_TP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK)
+#define AIPS_PACRL_TP1 AIPS_PACRL_TP1_MASK
 #define AIPS_PACRL_WP1_MASK                      (0x2000000U)
 #define AIPS_PACRL_WP1_SHIFT                     (25U)
-#define AIPS_PACRL_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK)
+#define AIPS_PACRL_WP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK)
+#define AIPS_PACRL_WP1 AIPS_PACRL_WP1_MASK
 #define AIPS_PACRL_SP1_MASK                      (0x4000000U)
 #define AIPS_PACRL_SP1_SHIFT                     (26U)
-#define AIPS_PACRL_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK)
+#define AIPS_PACRL_SP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK)
+#define AIPS_PACRL_SP1 AIPS_PACRL_SP1_MASK
 #define AIPS_PACRL_TP0_MASK                      (0x10000000U)
 #define AIPS_PACRL_TP0_SHIFT                     (28U)
-#define AIPS_PACRL_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK)
+#define AIPS_PACRL_TP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK)
+#define AIPS_PACRL_TP0 AIPS_PACRL_TP0_MASK
 #define AIPS_PACRL_WP0_MASK                      (0x20000000U)
 #define AIPS_PACRL_WP0_SHIFT                     (29U)
-#define AIPS_PACRL_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK)
+#define AIPS_PACRL_WP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK)
+#define AIPS_PACRL_WP0 AIPS_PACRL_WP0_MASK
 #define AIPS_PACRL_SP0_MASK                      (0x40000000U)
 #define AIPS_PACRL_SP0_SHIFT                     (30U)
-#define AIPS_PACRL_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK)
+#define AIPS_PACRL_SP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK)
+#define AIPS_PACRL_SP0 AIPS_PACRL_SP0_MASK
 
 /*! @name PACRM - Peripheral Access Control Register */
 #define AIPS_PACRM_TP7_MASK                      (0x1U)
 #define AIPS_PACRM_TP7_SHIFT                     (0U)
-#define AIPS_PACRM_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK)
+#define AIPS_PACRM_TP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK)
+#define AIPS_PACRM_TP7 AIPS_PACRM_TP7_MASK
 #define AIPS_PACRM_WP7_MASK                      (0x2U)
 #define AIPS_PACRM_WP7_SHIFT                     (1U)
-#define AIPS_PACRM_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK)
+#define AIPS_PACRM_WP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK)
+#define AIPS_PACRM_WP7 AIPS_PACRM_WP7_MASK
 #define AIPS_PACRM_SP7_MASK                      (0x4U)
 #define AIPS_PACRM_SP7_SHIFT                     (2U)
-#define AIPS_PACRM_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK)
+#define AIPS_PACRM_SP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK)
+#define AIPS_PACRM_SP7 AIPS_PACRM_SP7_MASK
 #define AIPS_PACRM_TP6_MASK                      (0x10U)
 #define AIPS_PACRM_TP6_SHIFT                     (4U)
-#define AIPS_PACRM_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK)
+#define AIPS_PACRM_TP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK)
+#define AIPS_PACRM_TP6 AIPS_PACRM_TP6_MASK
 #define AIPS_PACRM_WP6_MASK                      (0x20U)
 #define AIPS_PACRM_WP6_SHIFT                     (5U)
-#define AIPS_PACRM_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK)
+#define AIPS_PACRM_WP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK)
+#define AIPS_PACRM_WP6 AIPS_PACRM_WP6_MASK
 #define AIPS_PACRM_SP6_MASK                      (0x40U)
 #define AIPS_PACRM_SP6_SHIFT                     (6U)
-#define AIPS_PACRM_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK)
+#define AIPS_PACRM_SP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK)
+#define AIPS_PACRM_SP6 AIPS_PACRM_SP6_MASK
 #define AIPS_PACRM_TP5_MASK                      (0x100U)
 #define AIPS_PACRM_TP5_SHIFT                     (8U)
-#define AIPS_PACRM_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK)
+#define AIPS_PACRM_TP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK)
+#define AIPS_PACRM_TP5 AIPS_PACRM_TP5_MASK
 #define AIPS_PACRM_WP5_MASK                      (0x200U)
 #define AIPS_PACRM_WP5_SHIFT                     (9U)
-#define AIPS_PACRM_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK)
+#define AIPS_PACRM_WP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK)
+#define AIPS_PACRM_WP5 AIPS_PACRM_WP5_MASK
 #define AIPS_PACRM_SP5_MASK                      (0x400U)
 #define AIPS_PACRM_SP5_SHIFT                     (10U)
-#define AIPS_PACRM_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK)
+#define AIPS_PACRM_SP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK)
+#define AIPS_PACRM_SP5 AIPS_PACRM_SP5_MASK
 #define AIPS_PACRM_TP4_MASK                      (0x1000U)
 #define AIPS_PACRM_TP4_SHIFT                     (12U)
-#define AIPS_PACRM_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK)
+#define AIPS_PACRM_TP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK)
+#define AIPS_PACRM_TP4 AIPS_PACRM_TP4_MASK
 #define AIPS_PACRM_WP4_MASK                      (0x2000U)
 #define AIPS_PACRM_WP4_SHIFT                     (13U)
-#define AIPS_PACRM_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK)
+#define AIPS_PACRM_WP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK)
+#define AIPS_PACRM_WP4 AIPS_PACRM_WP4_MASK
 #define AIPS_PACRM_SP4_MASK                      (0x4000U)
 #define AIPS_PACRM_SP4_SHIFT                     (14U)
-#define AIPS_PACRM_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK)
+#define AIPS_PACRM_SP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK)
+#define AIPS_PACRM_SP4 AIPS_PACRM_SP4_MASK
 #define AIPS_PACRM_TP3_MASK                      (0x10000U)
 #define AIPS_PACRM_TP3_SHIFT                     (16U)
-#define AIPS_PACRM_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK)
+#define AIPS_PACRM_TP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK)
+#define AIPS_PACRM_TP3 AIPS_PACRM_TP3_MASK
 #define AIPS_PACRM_WP3_MASK                      (0x20000U)
 #define AIPS_PACRM_WP3_SHIFT                     (17U)
-#define AIPS_PACRM_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK)
+#define AIPS_PACRM_WP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK)
+#define AIPS_PACRM_WP3 AIPS_PACRM_WP3_MASK
 #define AIPS_PACRM_SP3_MASK                      (0x40000U)
 #define AIPS_PACRM_SP3_SHIFT                     (18U)
-#define AIPS_PACRM_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK)
+#define AIPS_PACRM_SP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK)
+#define AIPS_PACRM_SP3 AIPS_PACRM_SP3_MASK
 #define AIPS_PACRM_TP2_MASK                      (0x100000U)
 #define AIPS_PACRM_TP2_SHIFT                     (20U)
-#define AIPS_PACRM_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK)
+#define AIPS_PACRM_TP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK)
+#define AIPS_PACRM_TP2 AIPS_PACRM_TP2_MASK
 #define AIPS_PACRM_WP2_MASK                      (0x200000U)
 #define AIPS_PACRM_WP2_SHIFT                     (21U)
-#define AIPS_PACRM_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK)
+#define AIPS_PACRM_WP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK)
+#define AIPS_PACRM_WP2 AIPS_PACRM_WP2_MASK
 #define AIPS_PACRM_SP2_MASK                      (0x400000U)
 #define AIPS_PACRM_SP2_SHIFT                     (22U)
-#define AIPS_PACRM_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK)
+#define AIPS_PACRM_SP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK)
+#define AIPS_PACRM_SP2 AIPS_PACRM_SP2_MASK
 #define AIPS_PACRM_TP1_MASK                      (0x1000000U)
 #define AIPS_PACRM_TP1_SHIFT                     (24U)
-#define AIPS_PACRM_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK)
+#define AIPS_PACRM_TP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK)
+#define AIPS_PACRM_TP1 AIPS_PACRM_TP1_MASK
 #define AIPS_PACRM_WP1_MASK                      (0x2000000U)
 #define AIPS_PACRM_WP1_SHIFT                     (25U)
-#define AIPS_PACRM_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK)
+#define AIPS_PACRM_WP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK)
+#define AIPS_PACRM_WP1 AIPS_PACRM_WP1_MASK
 #define AIPS_PACRM_SP1_MASK                      (0x4000000U)
 #define AIPS_PACRM_SP1_SHIFT                     (26U)
-#define AIPS_PACRM_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK)
+#define AIPS_PACRM_SP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK)
+#define AIPS_PACRM_SP1 AIPS_PACRM_SP1_MASK
 #define AIPS_PACRM_TP0_MASK                      (0x10000000U)
 #define AIPS_PACRM_TP0_SHIFT                     (28U)
-#define AIPS_PACRM_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK)
+#define AIPS_PACRM_TP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK)
+#define AIPS_PACRM_TP0 AIPS_PACRM_TP0_MASK
 #define AIPS_PACRM_WP0_MASK                      (0x20000000U)
 #define AIPS_PACRM_WP0_SHIFT                     (29U)
-#define AIPS_PACRM_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK)
+#define AIPS_PACRM_WP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK)
+#define AIPS_PACRM_WP0 AIPS_PACRM_WP0_MASK
 #define AIPS_PACRM_SP0_MASK                      (0x40000000U)
 #define AIPS_PACRM_SP0_SHIFT                     (30U)
-#define AIPS_PACRM_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK)
+#define AIPS_PACRM_SP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK)
+#define AIPS_PACRM_SP0 AIPS_PACRM_SP0_MASK
 
 /*! @name PACRN - Peripheral Access Control Register */
 #define AIPS_PACRN_TP7_MASK                      (0x1U)
 #define AIPS_PACRN_TP7_SHIFT                     (0U)
-#define AIPS_PACRN_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK)
+#define AIPS_PACRN_TP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK)
+#define AIPS_PACRN_TP7 AIPS_PACRN_TP7_MASK
 #define AIPS_PACRN_WP7_MASK                      (0x2U)
 #define AIPS_PACRN_WP7_SHIFT                     (1U)
-#define AIPS_PACRN_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK)
+#define AIPS_PACRN_WP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK)
+#define AIPS_PACRN_WP7 AIPS_PACRN_WP7_MASK
 #define AIPS_PACRN_SP7_MASK                      (0x4U)
 #define AIPS_PACRN_SP7_SHIFT                     (2U)
-#define AIPS_PACRN_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK)
+#define AIPS_PACRN_SP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK)
+#define AIPS_PACRN_SP7 AIPS_PACRN_SP7_MASK
 #define AIPS_PACRN_TP6_MASK                      (0x10U)
 #define AIPS_PACRN_TP6_SHIFT                     (4U)
-#define AIPS_PACRN_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK)
+#define AIPS_PACRN_TP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK)
+#define AIPS_PACRN_TP6 AIPS_PACRN_TP6_MASK
 #define AIPS_PACRN_WP6_MASK                      (0x20U)
 #define AIPS_PACRN_WP6_SHIFT                     (5U)
-#define AIPS_PACRN_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK)
+#define AIPS_PACRN_WP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK)
+#define AIPS_PACRN_WP6 AIPS_PACRN_WP6_MASK
 #define AIPS_PACRN_SP6_MASK                      (0x40U)
 #define AIPS_PACRN_SP6_SHIFT                     (6U)
-#define AIPS_PACRN_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK)
+#define AIPS_PACRN_SP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK)
+#define AIPS_PACRN_SP6 AIPS_PACRN_SP6_MASK
 #define AIPS_PACRN_TP5_MASK                      (0x100U)
 #define AIPS_PACRN_TP5_SHIFT                     (8U)
-#define AIPS_PACRN_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK)
+#define AIPS_PACRN_TP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK)
+#define AIPS_PACRN_TP5 AIPS_PACRN_TP5_MASK
 #define AIPS_PACRN_WP5_MASK                      (0x200U)
 #define AIPS_PACRN_WP5_SHIFT                     (9U)
-#define AIPS_PACRN_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK)
+#define AIPS_PACRN_WP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK)
+#define AIPS_PACRN_WP5 AIPS_PACRN_WP5_MASK
 #define AIPS_PACRN_SP5_MASK                      (0x400U)
 #define AIPS_PACRN_SP5_SHIFT                     (10U)
-#define AIPS_PACRN_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK)
+#define AIPS_PACRN_SP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK)
+#define AIPS_PACRN_SP5 AIPS_PACRN_SP5_MASK
 #define AIPS_PACRN_TP4_MASK                      (0x1000U)
 #define AIPS_PACRN_TP4_SHIFT                     (12U)
-#define AIPS_PACRN_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK)
+#define AIPS_PACRN_TP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK)
+#define AIPS_PACRN_TP4 AIPS_PACRN_TP4_MASK
 #define AIPS_PACRN_WP4_MASK                      (0x2000U)
 #define AIPS_PACRN_WP4_SHIFT                     (13U)
-#define AIPS_PACRN_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK)
+#define AIPS_PACRN_WP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK)
+#define AIPS_PACRN_WP4 AIPS_PACRN_WP4_MASK
 #define AIPS_PACRN_SP4_MASK                      (0x4000U)
 #define AIPS_PACRN_SP4_SHIFT                     (14U)
-#define AIPS_PACRN_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK)
+#define AIPS_PACRN_SP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK)
+#define AIPS_PACRN_SP4 AIPS_PACRN_SP4_MASK
 #define AIPS_PACRN_TP3_MASK                      (0x10000U)
 #define AIPS_PACRN_TP3_SHIFT                     (16U)
-#define AIPS_PACRN_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK)
+#define AIPS_PACRN_TP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK)
+#define AIPS_PACRN_TP3 AIPS_PACRN_TP3_MASK
 #define AIPS_PACRN_WP3_MASK                      (0x20000U)
 #define AIPS_PACRN_WP3_SHIFT                     (17U)
-#define AIPS_PACRN_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK)
+#define AIPS_PACRN_WP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK)
+#define AIPS_PACRN_WP3 AIPS_PACRN_WP3_MASK
 #define AIPS_PACRN_SP3_MASK                      (0x40000U)
 #define AIPS_PACRN_SP3_SHIFT                     (18U)
-#define AIPS_PACRN_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK)
+#define AIPS_PACRN_SP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK)
+#define AIPS_PACRN_SP3 AIPS_PACRN_SP3_MASK
 #define AIPS_PACRN_TP2_MASK                      (0x100000U)
 #define AIPS_PACRN_TP2_SHIFT                     (20U)
-#define AIPS_PACRN_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK)
+#define AIPS_PACRN_TP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK)
+#define AIPS_PACRN_TP2 AIPS_PACRN_TP2_MASK
 #define AIPS_PACRN_WP2_MASK                      (0x200000U)
 #define AIPS_PACRN_WP2_SHIFT                     (21U)
-#define AIPS_PACRN_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK)
+#define AIPS_PACRN_WP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK)
+#define AIPS_PACRN_WP2 AIPS_PACRN_WP2_MASK
 #define AIPS_PACRN_SP2_MASK                      (0x400000U)
 #define AIPS_PACRN_SP2_SHIFT                     (22U)
-#define AIPS_PACRN_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK)
+#define AIPS_PACRN_SP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK)
+#define AIPS_PACRN_SP2 AIPS_PACRN_SP2_MASK
 #define AIPS_PACRN_TP1_MASK                      (0x1000000U)
 #define AIPS_PACRN_TP1_SHIFT                     (24U)
-#define AIPS_PACRN_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK)
+#define AIPS_PACRN_TP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK)
+#define AIPS_PACRN_TP1 AIPS_PACRN_TP1_MASK
 #define AIPS_PACRN_WP1_MASK                      (0x2000000U)
 #define AIPS_PACRN_WP1_SHIFT                     (25U)
-#define AIPS_PACRN_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK)
+#define AIPS_PACRN_WP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK)
+#define AIPS_PACRN_WP1 AIPS_PACRN_WP1_MASK
 #define AIPS_PACRN_SP1_MASK                      (0x4000000U)
 #define AIPS_PACRN_SP1_SHIFT                     (26U)
-#define AIPS_PACRN_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK)
+#define AIPS_PACRN_SP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK)
+#define AIPS_PACRN_SP1 AIPS_PACRN_SP1_MASK
 #define AIPS_PACRN_TP0_MASK                      (0x10000000U)
 #define AIPS_PACRN_TP0_SHIFT                     (28U)
-#define AIPS_PACRN_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK)
+#define AIPS_PACRN_TP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK)
+#define AIPS_PACRN_TP0 AIPS_PACRN_TP0_MASK
 #define AIPS_PACRN_WP0_MASK                      (0x20000000U)
 #define AIPS_PACRN_WP0_SHIFT                     (29U)
-#define AIPS_PACRN_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK)
+#define AIPS_PACRN_WP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK)
+#define AIPS_PACRN_WP0 AIPS_PACRN_WP0_MASK
 #define AIPS_PACRN_SP0_MASK                      (0x40000000U)
 #define AIPS_PACRN_SP0_SHIFT                     (30U)
-#define AIPS_PACRN_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK)
+#define AIPS_PACRN_SP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK)
+#define AIPS_PACRN_SP0 AIPS_PACRN_SP0_MASK
 
 /*! @name PACRO - Peripheral Access Control Register */
 #define AIPS_PACRO_TP7_MASK                      (0x1U)
 #define AIPS_PACRO_TP7_SHIFT                     (0U)
-#define AIPS_PACRO_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK)
+#define AIPS_PACRO_TP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK)
+#define AIPS_PACRO_TP7 AIPS_PACRO_TP7_MASK
 #define AIPS_PACRO_WP7_MASK                      (0x2U)
 #define AIPS_PACRO_WP7_SHIFT                     (1U)
-#define AIPS_PACRO_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK)
+#define AIPS_PACRO_WP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK)
+#define AIPS_PACRO_WP7 AIPS_PACRO_WP7_MASK
 #define AIPS_PACRO_SP7_MASK                      (0x4U)
 #define AIPS_PACRO_SP7_SHIFT                     (2U)
-#define AIPS_PACRO_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK)
+#define AIPS_PACRO_SP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK)
+#define AIPS_PACRO_SP7 AIPS_PACRO_SP7_MASK
 #define AIPS_PACRO_TP6_MASK                      (0x10U)
 #define AIPS_PACRO_TP6_SHIFT                     (4U)
-#define AIPS_PACRO_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK)
+#define AIPS_PACRO_TP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK)
+#define AIPS_PACRO_TP6 AIPS_PACRO_TP6_MASK
 #define AIPS_PACRO_WP6_MASK                      (0x20U)
 #define AIPS_PACRO_WP6_SHIFT                     (5U)
-#define AIPS_PACRO_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK)
+#define AIPS_PACRO_WP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK)
+#define AIPS_PACRO_WP6 AIPS_PACRO_WP6_MASK
 #define AIPS_PACRO_SP6_MASK                      (0x40U)
 #define AIPS_PACRO_SP6_SHIFT                     (6U)
-#define AIPS_PACRO_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK)
+#define AIPS_PACRO_SP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK)
+#define AIPS_PACRO_SP6 AIPS_PACRO_SP6_MASK
 #define AIPS_PACRO_TP5_MASK                      (0x100U)
 #define AIPS_PACRO_TP5_SHIFT                     (8U)
-#define AIPS_PACRO_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK)
+#define AIPS_PACRO_TP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK)
+#define AIPS_PACRO_TP5 AIPS_PACRO_TP5_MASK
 #define AIPS_PACRO_WP5_MASK                      (0x200U)
 #define AIPS_PACRO_WP5_SHIFT                     (9U)
-#define AIPS_PACRO_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK)
+#define AIPS_PACRO_WP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK)
+#define AIPS_PACRO_WP5 AIPS_PACRO_WP5_MASK
 #define AIPS_PACRO_SP5_MASK                      (0x400U)
 #define AIPS_PACRO_SP5_SHIFT                     (10U)
-#define AIPS_PACRO_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK)
+#define AIPS_PACRO_SP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK)
+#define AIPS_PACRO_SP5 AIPS_PACRO_SP5_MASK
 #define AIPS_PACRO_TP4_MASK                      (0x1000U)
 #define AIPS_PACRO_TP4_SHIFT                     (12U)
-#define AIPS_PACRO_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK)
+#define AIPS_PACRO_TP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK)
+#define AIPS_PACRO_TP4 AIPS_PACRO_TP4_MASK
 #define AIPS_PACRO_WP4_MASK                      (0x2000U)
 #define AIPS_PACRO_WP4_SHIFT                     (13U)
-#define AIPS_PACRO_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK)
+#define AIPS_PACRO_WP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK)
+#define AIPS_PACRO_WP4 AIPS_PACRO_WP4_MASK
 #define AIPS_PACRO_SP4_MASK                      (0x4000U)
 #define AIPS_PACRO_SP4_SHIFT                     (14U)
-#define AIPS_PACRO_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK)
+#define AIPS_PACRO_SP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK)
+#define AIPS_PACRO_SP4 AIPS_PACRO_SP4_MASK
 #define AIPS_PACRO_TP3_MASK                      (0x10000U)
 #define AIPS_PACRO_TP3_SHIFT                     (16U)
-#define AIPS_PACRO_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK)
+#define AIPS_PACRO_TP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK)
+#define AIPS_PACRO_TP3 AIPS_PACRO_TP3_MASK
 #define AIPS_PACRO_WP3_MASK                      (0x20000U)
 #define AIPS_PACRO_WP3_SHIFT                     (17U)
-#define AIPS_PACRO_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK)
+#define AIPS_PACRO_WP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK)
+#define AIPS_PACRO_WP3 AIPS_PACRO_WP3_MASK
 #define AIPS_PACRO_SP3_MASK                      (0x40000U)
 #define AIPS_PACRO_SP3_SHIFT                     (18U)
-#define AIPS_PACRO_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK)
+#define AIPS_PACRO_SP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK)
+#define AIPS_PACRO_SP3 AIPS_PACRO_SP3_MASK
 #define AIPS_PACRO_TP2_MASK                      (0x100000U)
 #define AIPS_PACRO_TP2_SHIFT                     (20U)
-#define AIPS_PACRO_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK)
+#define AIPS_PACRO_TP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK)
+#define AIPS_PACRO_TP2 AIPS_PACRO_TP2_MASK
 #define AIPS_PACRO_WP2_MASK                      (0x200000U)
 #define AIPS_PACRO_WP2_SHIFT                     (21U)
-#define AIPS_PACRO_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK)
+#define AIPS_PACRO_WP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK)
+#define AIPS_PACRO_WP2 AIPS_PACRO_WP2_MASK
 #define AIPS_PACRO_SP2_MASK                      (0x400000U)
 #define AIPS_PACRO_SP2_SHIFT                     (22U)
-#define AIPS_PACRO_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK)
+#define AIPS_PACRO_SP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK)
+#define AIPS_PACRO_SP2 AIPS_PACRO_SP2_MASK
 #define AIPS_PACRO_TP1_MASK                      (0x1000000U)
 #define AIPS_PACRO_TP1_SHIFT                     (24U)
-#define AIPS_PACRO_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK)
+#define AIPS_PACRO_TP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK)
+#define AIPS_PACRO_TP1 AIPS_PACRO_TP1_MASK
 #define AIPS_PACRO_WP1_MASK                      (0x2000000U)
 #define AIPS_PACRO_WP1_SHIFT                     (25U)
-#define AIPS_PACRO_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK)
+#define AIPS_PACRO_WP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK)
+#define AIPS_PACRO_WP1 AIPS_PACRO_WP1_MASK
 #define AIPS_PACRO_SP1_MASK                      (0x4000000U)
 #define AIPS_PACRO_SP1_SHIFT                     (26U)
-#define AIPS_PACRO_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK)
+#define AIPS_PACRO_SP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK)
+#define AIPS_PACRO_SP1 AIPS_PACRO_SP1_MASK
 #define AIPS_PACRO_TP0_MASK                      (0x10000000U)
 #define AIPS_PACRO_TP0_SHIFT                     (28U)
-#define AIPS_PACRO_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK)
+#define AIPS_PACRO_TP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK)
+#define AIPS_PACRO_TP0 AIPS_PACRO_TP0_MASK
 #define AIPS_PACRO_WP0_MASK                      (0x20000000U)
 #define AIPS_PACRO_WP0_SHIFT                     (29U)
-#define AIPS_PACRO_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK)
+#define AIPS_PACRO_WP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK)
+#define AIPS_PACRO_WP0 AIPS_PACRO_WP0_MASK
 #define AIPS_PACRO_SP0_MASK                      (0x40000000U)
 #define AIPS_PACRO_SP0_SHIFT                     (30U)
-#define AIPS_PACRO_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK)
+#define AIPS_PACRO_SP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK)
+#define AIPS_PACRO_SP0 AIPS_PACRO_SP0_MASK
 
 /*! @name PACRP - Peripheral Access Control Register */
 #define AIPS_PACRP_TP7_MASK                      (0x1U)
 #define AIPS_PACRP_TP7_SHIFT                     (0U)
-#define AIPS_PACRP_TP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK)
+#define AIPS_PACRP_TP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK)
+#define AIPS_PACRP_TP7 AIPS_PACRP_TP7_MASK
 #define AIPS_PACRP_WP7_MASK                      (0x2U)
 #define AIPS_PACRP_WP7_SHIFT                     (1U)
-#define AIPS_PACRP_WP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK)
+#define AIPS_PACRP_WP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK)
+#define AIPS_PACRP_WP7 AIPS_PACRP_WP7_MASK
 #define AIPS_PACRP_SP7_MASK                      (0x4U)
 #define AIPS_PACRP_SP7_SHIFT                     (2U)
-#define AIPS_PACRP_SP7(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK)
+#define AIPS_PACRP_SP7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK)
+#define AIPS_PACRP_SP7 AIPS_PACRP_SP7_MASK
 #define AIPS_PACRP_TP6_MASK                      (0x10U)
 #define AIPS_PACRP_TP6_SHIFT                     (4U)
-#define AIPS_PACRP_TP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK)
+#define AIPS_PACRP_TP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK)
+#define AIPS_PACRP_TP6 AIPS_PACRP_TP6_MASK
 #define AIPS_PACRP_WP6_MASK                      (0x20U)
 #define AIPS_PACRP_WP6_SHIFT                     (5U)
-#define AIPS_PACRP_WP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK)
+#define AIPS_PACRP_WP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK)
+#define AIPS_PACRP_WP6 AIPS_PACRP_WP6_MASK
 #define AIPS_PACRP_SP6_MASK                      (0x40U)
 #define AIPS_PACRP_SP6_SHIFT                     (6U)
-#define AIPS_PACRP_SP6(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK)
+#define AIPS_PACRP_SP6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK)
+#define AIPS_PACRP_SP6 AIPS_PACRP_SP6_MASK
 #define AIPS_PACRP_TP5_MASK                      (0x100U)
 #define AIPS_PACRP_TP5_SHIFT                     (8U)
-#define AIPS_PACRP_TP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK)
+#define AIPS_PACRP_TP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK)
+#define AIPS_PACRP_TP5 AIPS_PACRP_TP5_MASK
 #define AIPS_PACRP_WP5_MASK                      (0x200U)
 #define AIPS_PACRP_WP5_SHIFT                     (9U)
-#define AIPS_PACRP_WP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK)
+#define AIPS_PACRP_WP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK)
+#define AIPS_PACRP_WP5 AIPS_PACRP_WP5_MASK
 #define AIPS_PACRP_SP5_MASK                      (0x400U)
 #define AIPS_PACRP_SP5_SHIFT                     (10U)
-#define AIPS_PACRP_SP5(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK)
+#define AIPS_PACRP_SP5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK)
+#define AIPS_PACRP_SP5 AIPS_PACRP_SP5_MASK
 #define AIPS_PACRP_TP4_MASK                      (0x1000U)
 #define AIPS_PACRP_TP4_SHIFT                     (12U)
-#define AIPS_PACRP_TP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK)
+#define AIPS_PACRP_TP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK)
+#define AIPS_PACRP_TP4 AIPS_PACRP_TP4_MASK
 #define AIPS_PACRP_WP4_MASK                      (0x2000U)
 #define AIPS_PACRP_WP4_SHIFT                     (13U)
-#define AIPS_PACRP_WP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK)
+#define AIPS_PACRP_WP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK)
+#define AIPS_PACRP_WP4 AIPS_PACRP_WP4_MASK
 #define AIPS_PACRP_SP4_MASK                      (0x4000U)
 #define AIPS_PACRP_SP4_SHIFT                     (14U)
-#define AIPS_PACRP_SP4(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK)
+#define AIPS_PACRP_SP4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK)
+#define AIPS_PACRP_SP4 AIPS_PACRP_SP4_MASK
 #define AIPS_PACRP_TP3_MASK                      (0x10000U)
 #define AIPS_PACRP_TP3_SHIFT                     (16U)
-#define AIPS_PACRP_TP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK)
+#define AIPS_PACRP_TP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK)
+#define AIPS_PACRP_TP3 AIPS_PACRP_TP3_MASK
 #define AIPS_PACRP_WP3_MASK                      (0x20000U)
 #define AIPS_PACRP_WP3_SHIFT                     (17U)
-#define AIPS_PACRP_WP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK)
+#define AIPS_PACRP_WP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK)
+#define AIPS_PACRP_WP3 AIPS_PACRP_WP3_MASK
 #define AIPS_PACRP_SP3_MASK                      (0x40000U)
 #define AIPS_PACRP_SP3_SHIFT                     (18U)
-#define AIPS_PACRP_SP3(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK)
+#define AIPS_PACRP_SP3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK)
+#define AIPS_PACRP_SP3 AIPS_PACRP_SP3_MASK
 #define AIPS_PACRP_TP2_MASK                      (0x100000U)
 #define AIPS_PACRP_TP2_SHIFT                     (20U)
-#define AIPS_PACRP_TP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK)
+#define AIPS_PACRP_TP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK)
+#define AIPS_PACRP_TP2 AIPS_PACRP_TP2_MASK
 #define AIPS_PACRP_WP2_MASK                      (0x200000U)
 #define AIPS_PACRP_WP2_SHIFT                     (21U)
-#define AIPS_PACRP_WP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK)
+#define AIPS_PACRP_WP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK)
+#define AIPS_PACRP_WP2 AIPS_PACRP_WP2_MASK
 #define AIPS_PACRP_SP2_MASK                      (0x400000U)
 #define AIPS_PACRP_SP2_SHIFT                     (22U)
-#define AIPS_PACRP_SP2(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK)
+#define AIPS_PACRP_SP2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK)
+#define AIPS_PACRP_SP2 AIPS_PACRP_SP2_MASK
 #define AIPS_PACRP_TP1_MASK                      (0x1000000U)
 #define AIPS_PACRP_TP1_SHIFT                     (24U)
-#define AIPS_PACRP_TP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK)
+#define AIPS_PACRP_TP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK)
+#define AIPS_PACRP_TP1 AIPS_PACRP_TP1_MASK
 #define AIPS_PACRP_WP1_MASK                      (0x2000000U)
 #define AIPS_PACRP_WP1_SHIFT                     (25U)
-#define AIPS_PACRP_WP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK)
+#define AIPS_PACRP_WP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK)
+#define AIPS_PACRP_WP1 AIPS_PACRP_WP1_MASK
 #define AIPS_PACRP_SP1_MASK                      (0x4000000U)
 #define AIPS_PACRP_SP1_SHIFT                     (26U)
-#define AIPS_PACRP_SP1(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK)
+#define AIPS_PACRP_SP1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK)
+#define AIPS_PACRP_SP1 AIPS_PACRP_SP1_MASK
 #define AIPS_PACRP_TP0_MASK                      (0x10000000U)
 #define AIPS_PACRP_TP0_SHIFT                     (28U)
-#define AIPS_PACRP_TP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK)
+#define AIPS_PACRP_TP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK)
+#define AIPS_PACRP_TP0 AIPS_PACRP_TP0_MASK
 #define AIPS_PACRP_WP0_MASK                      (0x20000000U)
 #define AIPS_PACRP_WP0_SHIFT                     (29U)
-#define AIPS_PACRP_WP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK)
+#define AIPS_PACRP_WP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK)
+#define AIPS_PACRP_WP0 AIPS_PACRP_WP0_MASK
 #define AIPS_PACRP_SP0_MASK                      (0x40000000U)
 #define AIPS_PACRP_SP0_SHIFT                     (30U)
-#define AIPS_PACRP_SP0(x)                        (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK)
+#define AIPS_PACRP_SP0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK)
+#define AIPS_PACRP_SP0 AIPS_PACRP_SP0_MASK
 
 
 /*!
@@ -2014,11 +2481,11 @@ typedef struct {
 /** Peripheral AIPS0 base address */
 #define AIPS0_BASE                               (0x40000000u)
 /** Peripheral AIPS0 base pointer */
-#define AIPS0                                    ((AIPS_Type *)AIPS0_BASE)
+#define AIPS0                                    ((AIPS_TypeDef *)AIPS0_BASE)
 /** Peripheral AIPS1 base address */
 #define AIPS1_BASE                               (0x40080000u)
 /** Peripheral AIPS1 base pointer */
-#define AIPS1                                    ((AIPS_Type *)AIPS1_BASE)
+#define AIPS1                                    ((AIPS_TypeDef *)AIPS1_BASE)
 /** Array initializer of AIPS peripheral base addresses */
 #define AIPS_BASE_ADDRS                          { AIPS0_BASE, AIPS1_BASE }
 /** Array initializer of AIPS peripheral base pointers */
@@ -2060,7 +2527,7 @@ typedef struct {
   __IO uint32_t MGPCR5;                            /**< Master General Purpose Control Register, offset: 0xD00 */
        uint8_t RESERVED_6[252];
   __IO uint32_t MGPCR6;                            /**< Master General Purpose Control Register, offset: 0xE00 */
-} AXBS_Type;
+} AXBS_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- AXBS Register Masks
@@ -2074,25 +2541,32 @@ typedef struct {
 /*! @name PRS - Priority Registers Slave */
 #define AXBS_PRS_M0_MASK                         (0x7U)
 #define AXBS_PRS_M0_SHIFT                        (0U)
-#define AXBS_PRS_M0(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)
+#define AXBS_PRS_M0_SET(x)                       (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)
+#define AXBS_PRS_M0 AXBS_PRS_M0_MASK
 #define AXBS_PRS_M1_MASK                         (0x70U)
 #define AXBS_PRS_M1_SHIFT                        (4U)
-#define AXBS_PRS_M1(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)
+#define AXBS_PRS_M1_SET(x)                       (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)
+#define AXBS_PRS_M1 AXBS_PRS_M1_MASK
 #define AXBS_PRS_M2_MASK                         (0x700U)
 #define AXBS_PRS_M2_SHIFT                        (8U)
-#define AXBS_PRS_M2(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)
+#define AXBS_PRS_M2_SET(x)                       (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)
+#define AXBS_PRS_M2 AXBS_PRS_M2_MASK
 #define AXBS_PRS_M3_MASK                         (0x7000U)
 #define AXBS_PRS_M3_SHIFT                        (12U)
-#define AXBS_PRS_M3(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK)
+#define AXBS_PRS_M3_SET(x)                       (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK)
+#define AXBS_PRS_M3 AXBS_PRS_M3_MASK
 #define AXBS_PRS_M4_MASK                         (0x70000U)
 #define AXBS_PRS_M4_SHIFT                        (16U)
-#define AXBS_PRS_M4(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK)
+#define AXBS_PRS_M4_SET(x)                       (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK)
+#define AXBS_PRS_M4 AXBS_PRS_M4_MASK
 #define AXBS_PRS_M5_MASK                         (0x700000U)
 #define AXBS_PRS_M5_SHIFT                        (20U)
-#define AXBS_PRS_M5(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK)
+#define AXBS_PRS_M5_SET(x)                       (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK)
+#define AXBS_PRS_M5 AXBS_PRS_M5_MASK
 #define AXBS_PRS_M6_MASK                         (0x7000000U)
 #define AXBS_PRS_M6_SHIFT                        (24U)
-#define AXBS_PRS_M6(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M6_SHIFT)) & AXBS_PRS_M6_MASK)
+#define AXBS_PRS_M6_SET(x)                       (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M6_SHIFT)) & AXBS_PRS_M6_MASK)
+#define AXBS_PRS_M6 AXBS_PRS_M6_MASK
 
 /* The count of AXBS_PRS */
 #define AXBS_PRS_COUNT                           (5U)
@@ -2100,19 +2574,24 @@ typedef struct {
 /*! @name CRS - Control Register */
 #define AXBS_CRS_PARK_MASK                       (0x7U)
 #define AXBS_CRS_PARK_SHIFT                      (0U)
-#define AXBS_CRS_PARK(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)
+#define AXBS_CRS_PARK_SET(x)                     (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)
+#define AXBS_CRS_PARK AXBS_CRS_PARK_MASK
 #define AXBS_CRS_PCTL_MASK                       (0x30U)
 #define AXBS_CRS_PCTL_SHIFT                      (4U)
-#define AXBS_CRS_PCTL(x)                         (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)
+#define AXBS_CRS_PCTL_SET(x)                     (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)
+#define AXBS_CRS_PCTL AXBS_CRS_PCTL_MASK
 #define AXBS_CRS_ARB_MASK                        (0x300U)
 #define AXBS_CRS_ARB_SHIFT                       (8U)
-#define AXBS_CRS_ARB(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)
+#define AXBS_CRS_ARB_SET(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)
+#define AXBS_CRS_ARB AXBS_CRS_ARB_MASK
 #define AXBS_CRS_HLP_MASK                        (0x40000000U)
 #define AXBS_CRS_HLP_SHIFT                       (30U)
-#define AXBS_CRS_HLP(x)                          (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK)
+#define AXBS_CRS_HLP_SET(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK)
+#define AXBS_CRS_HLP AXBS_CRS_HLP_MASK
 #define AXBS_CRS_RO_MASK                         (0x80000000U)
 #define AXBS_CRS_RO_SHIFT                        (31U)
-#define AXBS_CRS_RO(x)                           (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK)
+#define AXBS_CRS_RO_SET(x)                       (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK)
+#define AXBS_CRS_RO AXBS_CRS_RO_MASK
 
 /* The count of AXBS_CRS */
 #define AXBS_CRS_COUNT                           (5U)
@@ -2120,37 +2599,44 @@ typedef struct {
 /*! @name MGPCR0 - Master General Purpose Control Register */
 #define AXBS_MGPCR0_AULB_MASK                    (0x7U)
 #define AXBS_MGPCR0_AULB_SHIFT                   (0U)
-#define AXBS_MGPCR0_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK)
+#define AXBS_MGPCR0_AULB_SET(x)                  (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK)
+#define AXBS_MGPCR0_AULB AXBS_MGPCR0_AULB_MASK
 
 /*! @name MGPCR1 - Master General Purpose Control Register */
 #define AXBS_MGPCR1_AULB_MASK                    (0x7U)
 #define AXBS_MGPCR1_AULB_SHIFT                   (0U)
-#define AXBS_MGPCR1_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK)
+#define AXBS_MGPCR1_AULB_SET(x)                  (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK)
+#define AXBS_MGPCR1_AULB AXBS_MGPCR1_AULB_MASK
 
 /*! @name MGPCR2 - Master General Purpose Control Register */
 #define AXBS_MGPCR2_AULB_MASK                    (0x7U)
 #define AXBS_MGPCR2_AULB_SHIFT                   (0U)
-#define AXBS_MGPCR2_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK)
+#define AXBS_MGPCR2_AULB_SET(x)                  (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK)
+#define AXBS_MGPCR2_AULB AXBS_MGPCR2_AULB_MASK
 
 /*! @name MGPCR3 - Master General Purpose Control Register */
 #define AXBS_MGPCR3_AULB_MASK                    (0x7U)
 #define AXBS_MGPCR3_AULB_SHIFT                   (0U)
-#define AXBS_MGPCR3_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK)
+#define AXBS_MGPCR3_AULB_SET(x)                  (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK)
+#define AXBS_MGPCR3_AULB AXBS_MGPCR3_AULB_MASK
 
 /*! @name MGPCR4 - Master General Purpose Control Register */
 #define AXBS_MGPCR4_AULB_MASK                    (0x7U)
 #define AXBS_MGPCR4_AULB_SHIFT                   (0U)
-#define AXBS_MGPCR4_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK)
+#define AXBS_MGPCR4_AULB_SET(x)                  (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK)
+#define AXBS_MGPCR4_AULB AXBS_MGPCR4_AULB_MASK
 
 /*! @name MGPCR5 - Master General Purpose Control Register */
 #define AXBS_MGPCR5_AULB_MASK                    (0x7U)
 #define AXBS_MGPCR5_AULB_SHIFT                   (0U)
-#define AXBS_MGPCR5_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK)
+#define AXBS_MGPCR5_AULB_SET(x)                  (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK)
+#define AXBS_MGPCR5_AULB AXBS_MGPCR5_AULB_MASK
 
 /*! @name MGPCR6 - Master General Purpose Control Register */
 #define AXBS_MGPCR6_AULB_MASK                    (0x7U)
 #define AXBS_MGPCR6_AULB_SHIFT                   (0U)
-#define AXBS_MGPCR6_AULB(x)                      (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR6_AULB_SHIFT)) & AXBS_MGPCR6_AULB_MASK)
+#define AXBS_MGPCR6_AULB_SET(x)                  (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR6_AULB_SHIFT)) & AXBS_MGPCR6_AULB_MASK)
+#define AXBS_MGPCR6_AULB AXBS_MGPCR6_AULB_MASK
 
 
 /*!
@@ -2162,7 +2648,7 @@ typedef struct {
 /** Peripheral AXBS base address */
 #define AXBS_BASE                                (0x40004000u)
 /** Peripheral AXBS base pointer */
-#define AXBS                                     ((AXBS_Type *)AXBS_BASE)
+#define AXBS                                     ((AXBS_TypeDef *)AXBS_BASE)
 /** Array initializer of AXBS peripheral base addresses */
 #define AXBS_BASE_ADDRS                          { AXBS_BASE }
 /** Array initializer of AXBS peripheral base pointers */
@@ -2212,7 +2698,7 @@ typedef struct {
   } MB[16];
        uint8_t RESERVED_5[1792];
   __IO uint32_t RXIMR[16];                         /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
-} CAN_Type;
+} CAN_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- CAN Register Masks
@@ -2226,289 +2712,374 @@ typedef struct {
 /*! @name MCR - Module Configuration Register */
 #define CAN_MCR_MAXMB_MASK                       (0x7FU)
 #define CAN_MCR_MAXMB_SHIFT                      (0U)
-#define CAN_MCR_MAXMB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
+#define CAN_MCR_MAXMB_SET(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
+#define CAN_MCR_MAXMB CAN_MCR_MAXMB_MASK
 #define CAN_MCR_IDAM_MASK                        (0x300U)
 #define CAN_MCR_IDAM_SHIFT                       (8U)
-#define CAN_MCR_IDAM(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
+#define CAN_MCR_IDAM_SET(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
+#define CAN_MCR_IDAM CAN_MCR_IDAM_MASK
 #define CAN_MCR_AEN_MASK                         (0x1000U)
 #define CAN_MCR_AEN_SHIFT                        (12U)
-#define CAN_MCR_AEN(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
+#define CAN_MCR_AEN_SET(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
+#define CAN_MCR_AEN CAN_MCR_AEN_MASK
 #define CAN_MCR_LPRIOEN_MASK                     (0x2000U)
 #define CAN_MCR_LPRIOEN_SHIFT                    (13U)
-#define CAN_MCR_LPRIOEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
+#define CAN_MCR_LPRIOEN_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
+#define CAN_MCR_LPRIOEN CAN_MCR_LPRIOEN_MASK
 #define CAN_MCR_IRMQ_MASK                        (0x10000U)
 #define CAN_MCR_IRMQ_SHIFT                       (16U)
-#define CAN_MCR_IRMQ(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
+#define CAN_MCR_IRMQ_SET(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
+#define CAN_MCR_IRMQ CAN_MCR_IRMQ_MASK
 #define CAN_MCR_SRXDIS_MASK                      (0x20000U)
 #define CAN_MCR_SRXDIS_SHIFT                     (17U)
-#define CAN_MCR_SRXDIS(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
+#define CAN_MCR_SRXDIS_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
+#define CAN_MCR_SRXDIS CAN_MCR_SRXDIS_MASK
 #define CAN_MCR_WAKSRC_MASK                      (0x80000U)
 #define CAN_MCR_WAKSRC_SHIFT                     (19U)
-#define CAN_MCR_WAKSRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
+#define CAN_MCR_WAKSRC_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
+#define CAN_MCR_WAKSRC CAN_MCR_WAKSRC_MASK
 #define CAN_MCR_LPMACK_MASK                      (0x100000U)
 #define CAN_MCR_LPMACK_SHIFT                     (20U)
-#define CAN_MCR_LPMACK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
+#define CAN_MCR_LPMACK_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
+#define CAN_MCR_LPMACK CAN_MCR_LPMACK_MASK
 #define CAN_MCR_WRNEN_MASK                       (0x200000U)
 #define CAN_MCR_WRNEN_SHIFT                      (21U)
-#define CAN_MCR_WRNEN(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
+#define CAN_MCR_WRNEN_SET(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
+#define CAN_MCR_WRNEN CAN_MCR_WRNEN_MASK
 #define CAN_MCR_SLFWAK_MASK                      (0x400000U)
 #define CAN_MCR_SLFWAK_SHIFT                     (22U)
-#define CAN_MCR_SLFWAK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
+#define CAN_MCR_SLFWAK_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
+#define CAN_MCR_SLFWAK CAN_MCR_SLFWAK_MASK
 #define CAN_MCR_SUPV_MASK                        (0x800000U)
 #define CAN_MCR_SUPV_SHIFT                       (23U)
-#define CAN_MCR_SUPV(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
+#define CAN_MCR_SUPV_SET(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
+#define CAN_MCR_SUPV CAN_MCR_SUPV_MASK
 #define CAN_MCR_FRZACK_MASK                      (0x1000000U)
 #define CAN_MCR_FRZACK_SHIFT                     (24U)
-#define CAN_MCR_FRZACK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
+#define CAN_MCR_FRZACK_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
+#define CAN_MCR_FRZACK CAN_MCR_FRZACK_MASK
 #define CAN_MCR_SOFTRST_MASK                     (0x2000000U)
 #define CAN_MCR_SOFTRST_SHIFT                    (25U)
-#define CAN_MCR_SOFTRST(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
+#define CAN_MCR_SOFTRST_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
+#define CAN_MCR_SOFTRST CAN_MCR_SOFTRST_MASK
 #define CAN_MCR_WAKMSK_MASK                      (0x4000000U)
 #define CAN_MCR_WAKMSK_SHIFT                     (26U)
-#define CAN_MCR_WAKMSK(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
+#define CAN_MCR_WAKMSK_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
+#define CAN_MCR_WAKMSK CAN_MCR_WAKMSK_MASK
 #define CAN_MCR_NOTRDY_MASK                      (0x8000000U)
 #define CAN_MCR_NOTRDY_SHIFT                     (27U)
-#define CAN_MCR_NOTRDY(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
+#define CAN_MCR_NOTRDY_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
+#define CAN_MCR_NOTRDY CAN_MCR_NOTRDY_MASK
 #define CAN_MCR_HALT_MASK                        (0x10000000U)
 #define CAN_MCR_HALT_SHIFT                       (28U)
-#define CAN_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
+#define CAN_MCR_HALT_SET(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
+#define CAN_MCR_HALT CAN_MCR_HALT_MASK
 #define CAN_MCR_RFEN_MASK                        (0x20000000U)
 #define CAN_MCR_RFEN_SHIFT                       (29U)
-#define CAN_MCR_RFEN(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
+#define CAN_MCR_RFEN_SET(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
+#define CAN_MCR_RFEN CAN_MCR_RFEN_MASK
 #define CAN_MCR_FRZ_MASK                         (0x40000000U)
 #define CAN_MCR_FRZ_SHIFT                        (30U)
-#define CAN_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
+#define CAN_MCR_FRZ_SET(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
+#define CAN_MCR_FRZ CAN_MCR_FRZ_MASK
 #define CAN_MCR_MDIS_MASK                        (0x80000000U)
 #define CAN_MCR_MDIS_SHIFT                       (31U)
-#define CAN_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
+#define CAN_MCR_MDIS_SET(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
+#define CAN_MCR_MDIS CAN_MCR_MDIS_MASK
 
 /*! @name CTRL1 - Control 1 register */
 #define CAN_CTRL1_PROPSEG_MASK                   (0x7U)
 #define CAN_CTRL1_PROPSEG_SHIFT                  (0U)
-#define CAN_CTRL1_PROPSEG(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
+#define CAN_CTRL1_PROPSEG_SET(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
+#define CAN_CTRL1_PROPSEG CAN_CTRL1_PROPSEG_MASK
 #define CAN_CTRL1_LOM_MASK                       (0x8U)
 #define CAN_CTRL1_LOM_SHIFT                      (3U)
-#define CAN_CTRL1_LOM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
+#define CAN_CTRL1_LOM_SET(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
+#define CAN_CTRL1_LOM CAN_CTRL1_LOM_MASK
 #define CAN_CTRL1_LBUF_MASK                      (0x10U)
 #define CAN_CTRL1_LBUF_SHIFT                     (4U)
-#define CAN_CTRL1_LBUF(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
+#define CAN_CTRL1_LBUF_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
+#define CAN_CTRL1_LBUF CAN_CTRL1_LBUF_MASK
 #define CAN_CTRL1_TSYN_MASK                      (0x20U)
 #define CAN_CTRL1_TSYN_SHIFT                     (5U)
-#define CAN_CTRL1_TSYN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
+#define CAN_CTRL1_TSYN_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
+#define CAN_CTRL1_TSYN CAN_CTRL1_TSYN_MASK
 #define CAN_CTRL1_BOFFREC_MASK                   (0x40U)
 #define CAN_CTRL1_BOFFREC_SHIFT                  (6U)
-#define CAN_CTRL1_BOFFREC(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
+#define CAN_CTRL1_BOFFREC_SET(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
+#define CAN_CTRL1_BOFFREC CAN_CTRL1_BOFFREC_MASK
 #define CAN_CTRL1_SMP_MASK                       (0x80U)
 #define CAN_CTRL1_SMP_SHIFT                      (7U)
-#define CAN_CTRL1_SMP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
+#define CAN_CTRL1_SMP_SET(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
+#define CAN_CTRL1_SMP CAN_CTRL1_SMP_MASK
 #define CAN_CTRL1_RWRNMSK_MASK                   (0x400U)
 #define CAN_CTRL1_RWRNMSK_SHIFT                  (10U)
-#define CAN_CTRL1_RWRNMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
+#define CAN_CTRL1_RWRNMSK_SET(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
+#define CAN_CTRL1_RWRNMSK CAN_CTRL1_RWRNMSK_MASK
 #define CAN_CTRL1_TWRNMSK_MASK                   (0x800U)
 #define CAN_CTRL1_TWRNMSK_SHIFT                  (11U)
-#define CAN_CTRL1_TWRNMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
+#define CAN_CTRL1_TWRNMSK_SET(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
+#define CAN_CTRL1_TWRNMSK CAN_CTRL1_TWRNMSK_MASK
 #define CAN_CTRL1_LPB_MASK                       (0x1000U)
 #define CAN_CTRL1_LPB_SHIFT                      (12U)
-#define CAN_CTRL1_LPB(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
+#define CAN_CTRL1_LPB_SET(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
+#define CAN_CTRL1_LPB CAN_CTRL1_LPB_MASK
 #define CAN_CTRL1_CLKSRC_MASK                    (0x2000U)
 #define CAN_CTRL1_CLKSRC_SHIFT                   (13U)
-#define CAN_CTRL1_CLKSRC(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
+#define CAN_CTRL1_CLKSRC_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
+#define CAN_CTRL1_CLKSRC CAN_CTRL1_CLKSRC_MASK
 #define CAN_CTRL1_ERRMSK_MASK                    (0x4000U)
 #define CAN_CTRL1_ERRMSK_SHIFT                   (14U)
-#define CAN_CTRL1_ERRMSK(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
+#define CAN_CTRL1_ERRMSK_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
+#define CAN_CTRL1_ERRMSK CAN_CTRL1_ERRMSK_MASK
 #define CAN_CTRL1_BOFFMSK_MASK                   (0x8000U)
 #define CAN_CTRL1_BOFFMSK_SHIFT                  (15U)
-#define CAN_CTRL1_BOFFMSK(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
+#define CAN_CTRL1_BOFFMSK_SET(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
+#define CAN_CTRL1_BOFFMSK CAN_CTRL1_BOFFMSK_MASK
 #define CAN_CTRL1_PSEG2_MASK                     (0x70000U)
 #define CAN_CTRL1_PSEG2_SHIFT                    (16U)
-#define CAN_CTRL1_PSEG2(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
+#define CAN_CTRL1_PSEG2_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
+#define CAN_CTRL1_PSEG2 CAN_CTRL1_PSEG2_MASK
 #define CAN_CTRL1_PSEG1_MASK                     (0x380000U)
 #define CAN_CTRL1_PSEG1_SHIFT                    (19U)
-#define CAN_CTRL1_PSEG1(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
+#define CAN_CTRL1_PSEG1_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
+#define CAN_CTRL1_PSEG1 CAN_CTRL1_PSEG1_MASK
 #define CAN_CTRL1_RJW_MASK                       (0xC00000U)
 #define CAN_CTRL1_RJW_SHIFT                      (22U)
-#define CAN_CTRL1_RJW(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
+#define CAN_CTRL1_RJW_SET(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
+#define CAN_CTRL1_RJW CAN_CTRL1_RJW_MASK
 #define CAN_CTRL1_PRESDIV_MASK                   (0xFF000000U)
 #define CAN_CTRL1_PRESDIV_SHIFT                  (24U)
-#define CAN_CTRL1_PRESDIV(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
+#define CAN_CTRL1_PRESDIV_SET(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
+#define CAN_CTRL1_PRESDIV CAN_CTRL1_PRESDIV_MASK
 
 /*! @name TIMER - Free Running Timer */
 #define CAN_TIMER_TIMER_MASK                     (0xFFFFU)
 #define CAN_TIMER_TIMER_SHIFT                    (0U)
-#define CAN_TIMER_TIMER(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
+#define CAN_TIMER_TIMER_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
+#define CAN_TIMER_TIMER CAN_TIMER_TIMER_MASK
 
 /*! @name RXMGMASK - Rx Mailboxes Global Mask Register */
 #define CAN_RXMGMASK_MG_MASK                     (0xFFFFFFFFU)
 #define CAN_RXMGMASK_MG_SHIFT                    (0U)
-#define CAN_RXMGMASK_MG(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
+#define CAN_RXMGMASK_MG_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
+#define CAN_RXMGMASK_MG CAN_RXMGMASK_MG_MASK
 
 /*! @name RX14MASK - Rx 14 Mask register */
 #define CAN_RX14MASK_RX14M_MASK                  (0xFFFFFFFFU)
 #define CAN_RX14MASK_RX14M_SHIFT                 (0U)
-#define CAN_RX14MASK_RX14M(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
+#define CAN_RX14MASK_RX14M_SET(x)                (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
+#define CAN_RX14MASK_RX14M CAN_RX14MASK_RX14M_MASK
 
 /*! @name RX15MASK - Rx 15 Mask register */
 #define CAN_RX15MASK_RX15M_MASK                  (0xFFFFFFFFU)
 #define CAN_RX15MASK_RX15M_SHIFT                 (0U)
-#define CAN_RX15MASK_RX15M(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
+#define CAN_RX15MASK_RX15M_SET(x)                (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
+#define CAN_RX15MASK_RX15M CAN_RX15MASK_RX15M_MASK
 
 /*! @name ECR - Error Counter */
 #define CAN_ECR_TXERRCNT_MASK                    (0xFFU)
 #define CAN_ECR_TXERRCNT_SHIFT                   (0U)
-#define CAN_ECR_TXERRCNT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
+#define CAN_ECR_TXERRCNT_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
+#define CAN_ECR_TXERRCNT CAN_ECR_TXERRCNT_MASK
 #define CAN_ECR_RXERRCNT_MASK                    (0xFF00U)
 #define CAN_ECR_RXERRCNT_SHIFT                   (8U)
-#define CAN_ECR_RXERRCNT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
+#define CAN_ECR_RXERRCNT_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
+#define CAN_ECR_RXERRCNT CAN_ECR_RXERRCNT_MASK
 
 /*! @name ESR1 - Error and Status 1 register */
 #define CAN_ESR1_WAKINT_MASK                     (0x1U)
 #define CAN_ESR1_WAKINT_SHIFT                    (0U)
-#define CAN_ESR1_WAKINT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
+#define CAN_ESR1_WAKINT_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
+#define CAN_ESR1_WAKINT CAN_ESR1_WAKINT_MASK
 #define CAN_ESR1_ERRINT_MASK                     (0x2U)
 #define CAN_ESR1_ERRINT_SHIFT                    (1U)
-#define CAN_ESR1_ERRINT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
+#define CAN_ESR1_ERRINT_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
+#define CAN_ESR1_ERRINT CAN_ESR1_ERRINT_MASK
 #define CAN_ESR1_BOFFINT_MASK                    (0x4U)
 #define CAN_ESR1_BOFFINT_SHIFT                   (2U)
-#define CAN_ESR1_BOFFINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
+#define CAN_ESR1_BOFFINT_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
+#define CAN_ESR1_BOFFINT CAN_ESR1_BOFFINT_MASK
 #define CAN_ESR1_RX_MASK                         (0x8U)
 #define CAN_ESR1_RX_SHIFT                        (3U)
-#define CAN_ESR1_RX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
+#define CAN_ESR1_RX_SET(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
+#define CAN_ESR1_RX CAN_ESR1_RX_MASK
 #define CAN_ESR1_FLTCONF_MASK                    (0x30U)
 #define CAN_ESR1_FLTCONF_SHIFT                   (4U)
-#define CAN_ESR1_FLTCONF(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
+#define CAN_ESR1_FLTCONF_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
+#define CAN_ESR1_FLTCONF CAN_ESR1_FLTCONF_MASK
 #define CAN_ESR1_TX_MASK                         (0x40U)
 #define CAN_ESR1_TX_SHIFT                        (6U)
-#define CAN_ESR1_TX(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
+#define CAN_ESR1_TX_SET(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
+#define CAN_ESR1_TX CAN_ESR1_TX_MASK
 #define CAN_ESR1_IDLE_MASK                       (0x80U)
 #define CAN_ESR1_IDLE_SHIFT                      (7U)
-#define CAN_ESR1_IDLE(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
+#define CAN_ESR1_IDLE_SET(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
+#define CAN_ESR1_IDLE CAN_ESR1_IDLE_MASK
 #define CAN_ESR1_RXWRN_MASK                      (0x100U)
 #define CAN_ESR1_RXWRN_SHIFT                     (8U)
-#define CAN_ESR1_RXWRN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
+#define CAN_ESR1_RXWRN_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
+#define CAN_ESR1_RXWRN CAN_ESR1_RXWRN_MASK
 #define CAN_ESR1_TXWRN_MASK                      (0x200U)
 #define CAN_ESR1_TXWRN_SHIFT                     (9U)
-#define CAN_ESR1_TXWRN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
+#define CAN_ESR1_TXWRN_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
+#define CAN_ESR1_TXWRN CAN_ESR1_TXWRN_MASK
 #define CAN_ESR1_STFERR_MASK                     (0x400U)
 #define CAN_ESR1_STFERR_SHIFT                    (10U)
-#define CAN_ESR1_STFERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
+#define CAN_ESR1_STFERR_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
+#define CAN_ESR1_STFERR CAN_ESR1_STFERR_MASK
 #define CAN_ESR1_FRMERR_MASK                     (0x800U)
 #define CAN_ESR1_FRMERR_SHIFT                    (11U)
-#define CAN_ESR1_FRMERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
+#define CAN_ESR1_FRMERR_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
+#define CAN_ESR1_FRMERR CAN_ESR1_FRMERR_MASK
 #define CAN_ESR1_CRCERR_MASK                     (0x1000U)
 #define CAN_ESR1_CRCERR_SHIFT                    (12U)
-#define CAN_ESR1_CRCERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
+#define CAN_ESR1_CRCERR_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
+#define CAN_ESR1_CRCERR CAN_ESR1_CRCERR_MASK
 #define CAN_ESR1_ACKERR_MASK                     (0x2000U)
 #define CAN_ESR1_ACKERR_SHIFT                    (13U)
-#define CAN_ESR1_ACKERR(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
+#define CAN_ESR1_ACKERR_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
+#define CAN_ESR1_ACKERR CAN_ESR1_ACKERR_MASK
 #define CAN_ESR1_BIT0ERR_MASK                    (0x4000U)
 #define CAN_ESR1_BIT0ERR_SHIFT                   (14U)
-#define CAN_ESR1_BIT0ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
+#define CAN_ESR1_BIT0ERR_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
+#define CAN_ESR1_BIT0ERR CAN_ESR1_BIT0ERR_MASK
 #define CAN_ESR1_BIT1ERR_MASK                    (0x8000U)
 #define CAN_ESR1_BIT1ERR_SHIFT                   (15U)
-#define CAN_ESR1_BIT1ERR(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
+#define CAN_ESR1_BIT1ERR_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
+#define CAN_ESR1_BIT1ERR CAN_ESR1_BIT1ERR_MASK
 #define CAN_ESR1_RWRNINT_MASK                    (0x10000U)
 #define CAN_ESR1_RWRNINT_SHIFT                   (16U)
-#define CAN_ESR1_RWRNINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
+#define CAN_ESR1_RWRNINT_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
+#define CAN_ESR1_RWRNINT CAN_ESR1_RWRNINT_MASK
 #define CAN_ESR1_TWRNINT_MASK                    (0x20000U)
 #define CAN_ESR1_TWRNINT_SHIFT                   (17U)
-#define CAN_ESR1_TWRNINT(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
+#define CAN_ESR1_TWRNINT_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
+#define CAN_ESR1_TWRNINT CAN_ESR1_TWRNINT_MASK
 #define CAN_ESR1_SYNCH_MASK                      (0x40000U)
 #define CAN_ESR1_SYNCH_SHIFT                     (18U)
-#define CAN_ESR1_SYNCH(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
+#define CAN_ESR1_SYNCH_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
+#define CAN_ESR1_SYNCH CAN_ESR1_SYNCH_MASK
 
 /*! @name IMASK1 - Interrupt Masks 1 register */
 #define CAN_IMASK1_BUFLM_MASK                    (0xFFFFFFFFU)
 #define CAN_IMASK1_BUFLM_SHIFT                   (0U)
-#define CAN_IMASK1_BUFLM(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)
+#define CAN_IMASK1_BUFLM_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)
+#define CAN_IMASK1_BUFLM CAN_IMASK1_BUFLM_MASK
 
 /*! @name IFLAG1 - Interrupt Flags 1 register */
 #define CAN_IFLAG1_BUF0I_MASK                    (0x1U)
 #define CAN_IFLAG1_BUF0I_SHIFT                   (0U)
-#define CAN_IFLAG1_BUF0I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
+#define CAN_IFLAG1_BUF0I_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
+#define CAN_IFLAG1_BUF0I CAN_IFLAG1_BUF0I_MASK
 #define CAN_IFLAG1_BUF4TO1I_MASK                 (0x1EU)
 #define CAN_IFLAG1_BUF4TO1I_SHIFT                (1U)
-#define CAN_IFLAG1_BUF4TO1I(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
+#define CAN_IFLAG1_BUF4TO1I_SET(x)               (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
+#define CAN_IFLAG1_BUF4TO1I CAN_IFLAG1_BUF4TO1I_MASK
 #define CAN_IFLAG1_BUF5I_MASK                    (0x20U)
 #define CAN_IFLAG1_BUF5I_SHIFT                   (5U)
-#define CAN_IFLAG1_BUF5I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
+#define CAN_IFLAG1_BUF5I_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
+#define CAN_IFLAG1_BUF5I CAN_IFLAG1_BUF5I_MASK
 #define CAN_IFLAG1_BUF6I_MASK                    (0x40U)
 #define CAN_IFLAG1_BUF6I_SHIFT                   (6U)
-#define CAN_IFLAG1_BUF6I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
+#define CAN_IFLAG1_BUF6I_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
+#define CAN_IFLAG1_BUF6I CAN_IFLAG1_BUF6I_MASK
 #define CAN_IFLAG1_BUF7I_MASK                    (0x80U)
 #define CAN_IFLAG1_BUF7I_SHIFT                   (7U)
-#define CAN_IFLAG1_BUF7I(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
+#define CAN_IFLAG1_BUF7I_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
+#define CAN_IFLAG1_BUF7I CAN_IFLAG1_BUF7I_MASK
 #define CAN_IFLAG1_BUF31TO8I_MASK                (0xFFFFFF00U)
 #define CAN_IFLAG1_BUF31TO8I_SHIFT               (8U)
-#define CAN_IFLAG1_BUF31TO8I(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
+#define CAN_IFLAG1_BUF31TO8I_SET(x)              (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
+#define CAN_IFLAG1_BUF31TO8I CAN_IFLAG1_BUF31TO8I_MASK
 
 /*! @name CTRL2 - Control 2 register */
 #define CAN_CTRL2_EACEN_MASK                     (0x10000U)
 #define CAN_CTRL2_EACEN_SHIFT                    (16U)
-#define CAN_CTRL2_EACEN(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
+#define CAN_CTRL2_EACEN_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
+#define CAN_CTRL2_EACEN CAN_CTRL2_EACEN_MASK
 #define CAN_CTRL2_RRS_MASK                       (0x20000U)
 #define CAN_CTRL2_RRS_SHIFT                      (17U)
-#define CAN_CTRL2_RRS(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
+#define CAN_CTRL2_RRS_SET(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
+#define CAN_CTRL2_RRS CAN_CTRL2_RRS_MASK
 #define CAN_CTRL2_MRP_MASK                       (0x40000U)
 #define CAN_CTRL2_MRP_SHIFT                      (18U)
-#define CAN_CTRL2_MRP(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
+#define CAN_CTRL2_MRP_SET(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
+#define CAN_CTRL2_MRP CAN_CTRL2_MRP_MASK
 #define CAN_CTRL2_TASD_MASK                      (0xF80000U)
 #define CAN_CTRL2_TASD_SHIFT                     (19U)
-#define CAN_CTRL2_TASD(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
+#define CAN_CTRL2_TASD_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
+#define CAN_CTRL2_TASD CAN_CTRL2_TASD_MASK
 #define CAN_CTRL2_RFFN_MASK                      (0xF000000U)
 #define CAN_CTRL2_RFFN_SHIFT                     (24U)
-#define CAN_CTRL2_RFFN(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
+#define CAN_CTRL2_RFFN_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
+#define CAN_CTRL2_RFFN CAN_CTRL2_RFFN_MASK
 #define CAN_CTRL2_WRMFRZ_MASK                    (0x10000000U)
 #define CAN_CTRL2_WRMFRZ_SHIFT                   (28U)
-#define CAN_CTRL2_WRMFRZ(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
+#define CAN_CTRL2_WRMFRZ_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
+#define CAN_CTRL2_WRMFRZ CAN_CTRL2_WRMFRZ_MASK
 
 /*! @name ESR2 - Error and Status 2 register */
 #define CAN_ESR2_IMB_MASK                        (0x2000U)
 #define CAN_ESR2_IMB_SHIFT                       (13U)
-#define CAN_ESR2_IMB(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
+#define CAN_ESR2_IMB_SET(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
+#define CAN_ESR2_IMB CAN_ESR2_IMB_MASK
 #define CAN_ESR2_VPS_MASK                        (0x4000U)
 #define CAN_ESR2_VPS_SHIFT                       (14U)
-#define CAN_ESR2_VPS(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
+#define CAN_ESR2_VPS_SET(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
+#define CAN_ESR2_VPS CAN_ESR2_VPS_MASK
 #define CAN_ESR2_LPTM_MASK                       (0x7F0000U)
 #define CAN_ESR2_LPTM_SHIFT                      (16U)
-#define CAN_ESR2_LPTM(x)                         (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
+#define CAN_ESR2_LPTM_SET(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
+#define CAN_ESR2_LPTM CAN_ESR2_LPTM_MASK
 
 /*! @name CRCR - CRC Register */
 #define CAN_CRCR_TXCRC_MASK                      (0x7FFFU)
 #define CAN_CRCR_TXCRC_SHIFT                     (0U)
-#define CAN_CRCR_TXCRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
+#define CAN_CRCR_TXCRC_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
+#define CAN_CRCR_TXCRC CAN_CRCR_TXCRC_MASK
 #define CAN_CRCR_MBCRC_MASK                      (0x7F0000U)
 #define CAN_CRCR_MBCRC_SHIFT                     (16U)
-#define CAN_CRCR_MBCRC(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
+#define CAN_CRCR_MBCRC_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
+#define CAN_CRCR_MBCRC CAN_CRCR_MBCRC_MASK
 
 /*! @name RXFGMASK - Rx FIFO Global Mask register */
 #define CAN_RXFGMASK_FGM_MASK                    (0xFFFFFFFFU)
 #define CAN_RXFGMASK_FGM_SHIFT                   (0U)
-#define CAN_RXFGMASK_FGM(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
+#define CAN_RXFGMASK_FGM_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
+#define CAN_RXFGMASK_FGM CAN_RXFGMASK_FGM_MASK
 
 /*! @name RXFIR - Rx FIFO Information Register */
 #define CAN_RXFIR_IDHIT_MASK                     (0x1FFU)
 #define CAN_RXFIR_IDHIT_SHIFT                    (0U)
-#define CAN_RXFIR_IDHIT(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
+#define CAN_RXFIR_IDHIT_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
+#define CAN_RXFIR_IDHIT CAN_RXFIR_IDHIT_MASK
 
 /*! @name CS - Message Buffer 0 CS Register..Message Buffer 15 CS Register */
 #define CAN_CS_TIME_STAMP_MASK                   (0xFFFFU)
 #define CAN_CS_TIME_STAMP_SHIFT                  (0U)
-#define CAN_CS_TIME_STAMP(x)                     (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
+#define CAN_CS_TIME_STAMP_SET(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
+#define CAN_CS_TIME_STAMP CAN_CS_TIME_STAMP_MASK
 #define CAN_CS_DLC_MASK                          (0xF0000U)
 #define CAN_CS_DLC_SHIFT                         (16U)
-#define CAN_CS_DLC(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
+#define CAN_CS_DLC_SET(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
+#define CAN_CS_DLC CAN_CS_DLC_MASK
 #define CAN_CS_RTR_MASK                          (0x100000U)
 #define CAN_CS_RTR_SHIFT                         (20U)
-#define CAN_CS_RTR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
+#define CAN_CS_RTR_SET(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
+#define CAN_CS_RTR CAN_CS_RTR_MASK
 #define CAN_CS_IDE_MASK                          (0x200000U)
 #define CAN_CS_IDE_SHIFT                         (21U)
-#define CAN_CS_IDE(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
+#define CAN_CS_IDE_SET(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
+#define CAN_CS_IDE CAN_CS_IDE_MASK
 #define CAN_CS_SRR_MASK                          (0x400000U)
 #define CAN_CS_SRR_SHIFT                         (22U)
-#define CAN_CS_SRR(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
+#define CAN_CS_SRR_SET(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
+#define CAN_CS_SRR CAN_CS_SRR_MASK
 #define CAN_CS_CODE_MASK                         (0xF000000U)
 #define CAN_CS_CODE_SHIFT                        (24U)
-#define CAN_CS_CODE(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
+#define CAN_CS_CODE_SET(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
+#define CAN_CS_CODE CAN_CS_CODE_MASK
 
 /* The count of CAN_CS */
 #define CAN_CS_COUNT                             (16U)
@@ -2516,13 +3087,16 @@ typedef struct {
 /*! @name ID - Message Buffer 0 ID Register..Message Buffer 15 ID Register */
 #define CAN_ID_EXT_MASK                          (0x3FFFFU)
 #define CAN_ID_EXT_SHIFT                         (0U)
-#define CAN_ID_EXT(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
+#define CAN_ID_EXT_SET(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
+#define CAN_ID_EXT CAN_ID_EXT_MASK
 #define CAN_ID_STD_MASK                          (0x1FFC0000U)
 #define CAN_ID_STD_SHIFT                         (18U)
-#define CAN_ID_STD(x)                            (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
+#define CAN_ID_STD_SET(x)                        (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
+#define CAN_ID_STD CAN_ID_STD_MASK
 #define CAN_ID_PRIO_MASK                         (0xE0000000U)
 #define CAN_ID_PRIO_SHIFT                        (29U)
-#define CAN_ID_PRIO(x)                           (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
+#define CAN_ID_PRIO_SET(x)                       (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
+#define CAN_ID_PRIO CAN_ID_PRIO_MASK
 
 /* The count of CAN_ID */
 #define CAN_ID_COUNT                             (16U)
@@ -2530,16 +3104,20 @@ typedef struct {
 /*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register */
 #define CAN_WORD0_DATA_BYTE_3_MASK               (0xFFU)
 #define CAN_WORD0_DATA_BYTE_3_SHIFT              (0U)
-#define CAN_WORD0_DATA_BYTE_3(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
+#define CAN_WORD0_DATA_BYTE_3_SET(x)             (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
+#define CAN_WORD0_DATA_BYTE_3 CAN_WORD0_DATA_BYTE_3_MASK
 #define CAN_WORD0_DATA_BYTE_2_MASK               (0xFF00U)
 #define CAN_WORD0_DATA_BYTE_2_SHIFT              (8U)
-#define CAN_WORD0_DATA_BYTE_2(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
+#define CAN_WORD0_DATA_BYTE_2_SET(x)             (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
+#define CAN_WORD0_DATA_BYTE_2 CAN_WORD0_DATA_BYTE_2_MASK
 #define CAN_WORD0_DATA_BYTE_1_MASK               (0xFF0000U)
 #define CAN_WORD0_DATA_BYTE_1_SHIFT              (16U)
-#define CAN_WORD0_DATA_BYTE_1(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
+#define CAN_WORD0_DATA_BYTE_1_SET(x)             (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
+#define CAN_WORD0_DATA_BYTE_1 CAN_WORD0_DATA_BYTE_1_MASK
 #define CAN_WORD0_DATA_BYTE_0_MASK               (0xFF000000U)
 #define CAN_WORD0_DATA_BYTE_0_SHIFT              (24U)
-#define CAN_WORD0_DATA_BYTE_0(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
+#define CAN_WORD0_DATA_BYTE_0_SET(x)             (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
+#define CAN_WORD0_DATA_BYTE_0 CAN_WORD0_DATA_BYTE_0_MASK
 
 /* The count of CAN_WORD0 */
 #define CAN_WORD0_COUNT                          (16U)
@@ -2547,16 +3125,20 @@ typedef struct {
 /*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register */
 #define CAN_WORD1_DATA_BYTE_7_MASK               (0xFFU)
 #define CAN_WORD1_DATA_BYTE_7_SHIFT              (0U)
-#define CAN_WORD1_DATA_BYTE_7(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
+#define CAN_WORD1_DATA_BYTE_7_SET(x)             (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
+#define CAN_WORD1_DATA_BYTE_7 CAN_WORD1_DATA_BYTE_7_MASK
 #define CAN_WORD1_DATA_BYTE_6_MASK               (0xFF00U)
 #define CAN_WORD1_DATA_BYTE_6_SHIFT              (8U)
-#define CAN_WORD1_DATA_BYTE_6(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
+#define CAN_WORD1_DATA_BYTE_6_SET(x)             (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
+#define CAN_WORD1_DATA_BYTE_6 CAN_WORD1_DATA_BYTE_6_MASK
 #define CAN_WORD1_DATA_BYTE_5_MASK               (0xFF0000U)
 #define CAN_WORD1_DATA_BYTE_5_SHIFT              (16U)
-#define CAN_WORD1_DATA_BYTE_5(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
+#define CAN_WORD1_DATA_BYTE_5_SET(x)             (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
+#define CAN_WORD1_DATA_BYTE_5 CAN_WORD1_DATA_BYTE_5_MASK
 #define CAN_WORD1_DATA_BYTE_4_MASK               (0xFF000000U)
 #define CAN_WORD1_DATA_BYTE_4_SHIFT              (24U)
-#define CAN_WORD1_DATA_BYTE_4(x)                 (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
+#define CAN_WORD1_DATA_BYTE_4_SET(x)             (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
+#define CAN_WORD1_DATA_BYTE_4 CAN_WORD1_DATA_BYTE_4_MASK
 
 /* The count of CAN_WORD1 */
 #define CAN_WORD1_COUNT                          (16U)
@@ -2564,7 +3146,8 @@ typedef struct {
 /*! @name RXIMR - Rx Individual Mask Registers */
 #define CAN_RXIMR_MI_MASK                        (0xFFFFFFFFU)
 #define CAN_RXIMR_MI_SHIFT                       (0U)
-#define CAN_RXIMR_MI(x)                          (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
+#define CAN_RXIMR_MI_SET(x)                      (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
+#define CAN_RXIMR_MI CAN_RXIMR_MI_MASK
 
 /* The count of CAN_RXIMR */
 #define CAN_RXIMR_COUNT                          (16U)
@@ -2579,11 +3162,11 @@ typedef struct {
 /** Peripheral CAN0 base address */
 #define CAN0_BASE                                (0x40024000u)
 /** Peripheral CAN0 base pointer */
-#define CAN0                                     ((CAN_Type *)CAN0_BASE)
+#define CAN0                                     ((CAN_TypeDef *)CAN0_BASE)
 /** Peripheral CAN1 base address */
 #define CAN1_BASE                                (0x400A4000u)
 /** Peripheral CAN1 base pointer */
-#define CAN1                                     ((CAN_Type *)CAN1_BASE)
+#define CAN1                                     ((CAN_TypeDef *)CAN1_BASE)
 /** Array initializer of CAN peripheral base addresses */
 #define CAN_BASE_ADDRS                           { CAN0_BASE, CAN1_BASE }
 /** Array initializer of CAN peripheral base pointers */
@@ -2645,7 +3228,7 @@ typedef struct {
   __O  uint32_t AESIC_CASR;                        /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
   __O  uint32_t AESIC_CAA;                         /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
   __O  uint32_t AESIC_CA[9];                       /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
-} CAU_Type;
+} CAU_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- CAU Register Masks
@@ -2659,52 +3242,68 @@ typedef struct {
 /*! @name DIRECT - Direct access register 0..Direct access register 15 */
 #define CAU_DIRECT_CAU_DIRECT0_MASK              (0xFFFFFFFFU)
 #define CAU_DIRECT_CAU_DIRECT0_SHIFT             (0U)
-#define CAU_DIRECT_CAU_DIRECT0(x)                (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK)
+#define CAU_DIRECT_CAU_DIRECT0_SET(x)            (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK)
+#define CAU_DIRECT_CAU_DIRECT0 CAU_DIRECT_CAU_DIRECT0_MASK
 #define CAU_DIRECT_CAU_DIRECT1_MASK              (0xFFFFFFFFU)
 #define CAU_DIRECT_CAU_DIRECT1_SHIFT             (0U)
-#define CAU_DIRECT_CAU_DIRECT1(x)                (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT1_SHIFT)) & CAU_DIRECT_CAU_DIRECT1_MASK)
+#define CAU_DIRECT_CAU_DIRECT1_SET(x)            (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT1_SHIFT)) & CAU_DIRECT_CAU_DIRECT1_MASK)
+#define CAU_DIRECT_CAU_DIRECT1 CAU_DIRECT_CAU_DIRECT1_MASK
 #define CAU_DIRECT_CAU_DIRECT2_MASK              (0xFFFFFFFFU)
 #define CAU_DIRECT_CAU_DIRECT2_SHIFT             (0U)
-#define CAU_DIRECT_CAU_DIRECT2(x)                (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT2_SHIFT)) & CAU_DIRECT_CAU_DIRECT2_MASK)
+#define CAU_DIRECT_CAU_DIRECT2_SET(x)            (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT2_SHIFT)) & CAU_DIRECT_CAU_DIRECT2_MASK)
+#define CAU_DIRECT_CAU_DIRECT2 CAU_DIRECT_CAU_DIRECT2_MASK
 #define CAU_DIRECT_CAU_DIRECT3_MASK              (0xFFFFFFFFU)
 #define CAU_DIRECT_CAU_DIRECT3_SHIFT             (0U)
-#define CAU_DIRECT_CAU_DIRECT3(x)                (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT3_SHIFT)) & CAU_DIRECT_CAU_DIRECT3_MASK)
+#define CAU_DIRECT_CAU_DIRECT3_SET(x)            (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT3_SHIFT)) & CAU_DIRECT_CAU_DIRECT3_MASK)
+#define CAU_DIRECT_CAU_DIRECT3 CAU_DIRECT_CAU_DIRECT3_MASK
 #define CAU_DIRECT_CAU_DIRECT4_MASK              (0xFFFFFFFFU)
 #define CAU_DIRECT_CAU_DIRECT4_SHIFT             (0U)
-#define CAU_DIRECT_CAU_DIRECT4(x)                (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT4_SHIFT)) & CAU_DIRECT_CAU_DIRECT4_MASK)
+#define CAU_DIRECT_CAU_DIRECT4_SET(x)            (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT4_SHIFT)) & CAU_DIRECT_CAU_DIRECT4_MASK)
+#define CAU_DIRECT_CAU_DIRECT4 CAU_DIRECT_CAU_DIRECT4_MASK
 #define CAU_DIRECT_CAU_DIRECT5_MASK              (0xFFFFFFFFU)
 #define CAU_DIRECT_CAU_DIRECT5_SHIFT             (0U)
-#define CAU_DIRECT_CAU_DIRECT5(x)                (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT5_SHIFT)) & CAU_DIRECT_CAU_DIRECT5_MASK)
+#define CAU_DIRECT_CAU_DIRECT5_SET(x)            (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT5_SHIFT)) & CAU_DIRECT_CAU_DIRECT5_MASK)
+#define CAU_DIRECT_CAU_DIRECT5 CAU_DIRECT_CAU_DIRECT5_MASK
 #define CAU_DIRECT_CAU_DIRECT6_MASK              (0xFFFFFFFFU)
 #define CAU_DIRECT_CAU_DIRECT6_SHIFT             (0U)
-#define CAU_DIRECT_CAU_DIRECT6(x)                (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT6_SHIFT)) & CAU_DIRECT_CAU_DIRECT6_MASK)
+#define CAU_DIRECT_CAU_DIRECT6_SET(x)            (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT6_SHIFT)) & CAU_DIRECT_CAU_DIRECT6_MASK)
+#define CAU_DIRECT_CAU_DIRECT6 CAU_DIRECT_CAU_DIRECT6_MASK
 #define CAU_DIRECT_CAU_DIRECT7_MASK              (0xFFFFFFFFU)
 #define CAU_DIRECT_CAU_DIRECT7_SHIFT             (0U)
-#define CAU_DIRECT_CAU_DIRECT7(x)                (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT7_SHIFT)) & CAU_DIRECT_CAU_DIRECT7_MASK)
+#define CAU_DIRECT_CAU_DIRECT7_SET(x)            (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT7_SHIFT)) & CAU_DIRECT_CAU_DIRECT7_MASK)
+#define CAU_DIRECT_CAU_DIRECT7 CAU_DIRECT_CAU_DIRECT7_MASK
 #define CAU_DIRECT_CAU_DIRECT8_MASK              (0xFFFFFFFFU)
 #define CAU_DIRECT_CAU_DIRECT8_SHIFT             (0U)
-#define CAU_DIRECT_CAU_DIRECT8(x)                (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT8_SHIFT)) & CAU_DIRECT_CAU_DIRECT8_MASK)
+#define CAU_DIRECT_CAU_DIRECT8_SET(x)            (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT8_SHIFT)) & CAU_DIRECT_CAU_DIRECT8_MASK)
+#define CAU_DIRECT_CAU_DIRECT8 CAU_DIRECT_CAU_DIRECT8_MASK
 #define CAU_DIRECT_CAU_DIRECT9_MASK              (0xFFFFFFFFU)
 #define CAU_DIRECT_CAU_DIRECT9_SHIFT             (0U)
-#define CAU_DIRECT_CAU_DIRECT9(x)                (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT9_SHIFT)) & CAU_DIRECT_CAU_DIRECT9_MASK)
+#define CAU_DIRECT_CAU_DIRECT9_SET(x)            (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT9_SHIFT)) & CAU_DIRECT_CAU_DIRECT9_MASK)
+#define CAU_DIRECT_CAU_DIRECT9 CAU_DIRECT_CAU_DIRECT9_MASK
 #define CAU_DIRECT_CAU_DIRECT10_MASK             (0xFFFFFFFFU)
 #define CAU_DIRECT_CAU_DIRECT10_SHIFT            (0U)
-#define CAU_DIRECT_CAU_DIRECT10(x)               (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT10_SHIFT)) & CAU_DIRECT_CAU_DIRECT10_MASK)
+#define CAU_DIRECT_CAU_DIRECT10_SET(x)           (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT10_SHIFT)) & CAU_DIRECT_CAU_DIRECT10_MASK)
+#define CAU_DIRECT_CAU_DIRECT10 CAU_DIRECT_CAU_DIRECT10_MASK
 #define CAU_DIRECT_CAU_DIRECT11_MASK             (0xFFFFFFFFU)
 #define CAU_DIRECT_CAU_DIRECT11_SHIFT            (0U)
-#define CAU_DIRECT_CAU_DIRECT11(x)               (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT11_SHIFT)) & CAU_DIRECT_CAU_DIRECT11_MASK)
+#define CAU_DIRECT_CAU_DIRECT11_SET(x)           (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT11_SHIFT)) & CAU_DIRECT_CAU_DIRECT11_MASK)
+#define CAU_DIRECT_CAU_DIRECT11 CAU_DIRECT_CAU_DIRECT11_MASK
 #define CAU_DIRECT_CAU_DIRECT12_MASK             (0xFFFFFFFFU)
 #define CAU_DIRECT_CAU_DIRECT12_SHIFT            (0U)
-#define CAU_DIRECT_CAU_DIRECT12(x)               (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT12_SHIFT)) & CAU_DIRECT_CAU_DIRECT12_MASK)
+#define CAU_DIRECT_CAU_DIRECT12_SET(x)           (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT12_SHIFT)) & CAU_DIRECT_CAU_DIRECT12_MASK)
+#define CAU_DIRECT_CAU_DIRECT12 CAU_DIRECT_CAU_DIRECT12_MASK
 #define CAU_DIRECT_CAU_DIRECT13_MASK             (0xFFFFFFFFU)
 #define CAU_DIRECT_CAU_DIRECT13_SHIFT            (0U)
-#define CAU_DIRECT_CAU_DIRECT13(x)               (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT13_SHIFT)) & CAU_DIRECT_CAU_DIRECT13_MASK)
+#define CAU_DIRECT_CAU_DIRECT13_SET(x)           (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT13_SHIFT)) & CAU_DIRECT_CAU_DIRECT13_MASK)
+#define CAU_DIRECT_CAU_DIRECT13 CAU_DIRECT_CAU_DIRECT13_MASK
 #define CAU_DIRECT_CAU_DIRECT14_MASK             (0xFFFFFFFFU)
 #define CAU_DIRECT_CAU_DIRECT14_SHIFT            (0U)
-#define CAU_DIRECT_CAU_DIRECT14(x)               (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT14_SHIFT)) & CAU_DIRECT_CAU_DIRECT14_MASK)
+#define CAU_DIRECT_CAU_DIRECT14_SET(x)           (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT14_SHIFT)) & CAU_DIRECT_CAU_DIRECT14_MASK)
+#define CAU_DIRECT_CAU_DIRECT14 CAU_DIRECT_CAU_DIRECT14_MASK
 #define CAU_DIRECT_CAU_DIRECT15_MASK             (0xFFFFFFFFU)
 #define CAU_DIRECT_CAU_DIRECT15_SHIFT            (0U)
-#define CAU_DIRECT_CAU_DIRECT15(x)               (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK)
+#define CAU_DIRECT_CAU_DIRECT15_SET(x)           (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK)
+#define CAU_DIRECT_CAU_DIRECT15 CAU_DIRECT_CAU_DIRECT15_MASK
 
 /* The count of CAU_DIRECT */
 #define CAU_DIRECT_COUNT                         (16U)
@@ -2712,47 +3311,60 @@ typedef struct {
 /*! @name LDR_CASR - Status register - Load Register command */
 #define CAU_LDR_CASR_IC_MASK                     (0x1U)
 #define CAU_LDR_CASR_IC_SHIFT                    (0U)
-#define CAU_LDR_CASR_IC(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK)
+#define CAU_LDR_CASR_IC_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK)
+#define CAU_LDR_CASR_IC CAU_LDR_CASR_IC_MASK
 #define CAU_LDR_CASR_DPE_MASK                    (0x2U)
 #define CAU_LDR_CASR_DPE_SHIFT                   (1U)
-#define CAU_LDR_CASR_DPE(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK)
+#define CAU_LDR_CASR_DPE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK)
+#define CAU_LDR_CASR_DPE CAU_LDR_CASR_DPE_MASK
 #define CAU_LDR_CASR_VER_MASK                    (0xF0000000U)
 #define CAU_LDR_CASR_VER_SHIFT                   (28U)
-#define CAU_LDR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK)
+#define CAU_LDR_CASR_VER_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK)
+#define CAU_LDR_CASR_VER CAU_LDR_CASR_VER_MASK
 
 /*! @name LDR_CAA - Accumulator register - Load Register command */
 #define CAU_LDR_CAA_ACC_MASK                     (0xFFFFFFFFU)
 #define CAU_LDR_CAA_ACC_SHIFT                    (0U)
-#define CAU_LDR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK)
+#define CAU_LDR_CAA_ACC_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK)
+#define CAU_LDR_CAA_ACC CAU_LDR_CAA_ACC_MASK
 
 /*! @name LDR_CA - General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command */
 #define CAU_LDR_CA_CA0_MASK                      (0xFFFFFFFFU)
 #define CAU_LDR_CA_CA0_SHIFT                     (0U)
-#define CAU_LDR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK)
+#define CAU_LDR_CA_CA0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK)
+#define CAU_LDR_CA_CA0 CAU_LDR_CA_CA0_MASK
 #define CAU_LDR_CA_CA1_MASK                      (0xFFFFFFFFU)
 #define CAU_LDR_CA_CA1_SHIFT                     (0U)
-#define CAU_LDR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA1_SHIFT)) & CAU_LDR_CA_CA1_MASK)
+#define CAU_LDR_CA_CA1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA1_SHIFT)) & CAU_LDR_CA_CA1_MASK)
+#define CAU_LDR_CA_CA1 CAU_LDR_CA_CA1_MASK
 #define CAU_LDR_CA_CA2_MASK                      (0xFFFFFFFFU)
 #define CAU_LDR_CA_CA2_SHIFT                     (0U)
-#define CAU_LDR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA2_SHIFT)) & CAU_LDR_CA_CA2_MASK)
+#define CAU_LDR_CA_CA2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA2_SHIFT)) & CAU_LDR_CA_CA2_MASK)
+#define CAU_LDR_CA_CA2 CAU_LDR_CA_CA2_MASK
 #define CAU_LDR_CA_CA3_MASK                      (0xFFFFFFFFU)
 #define CAU_LDR_CA_CA3_SHIFT                     (0U)
-#define CAU_LDR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA3_SHIFT)) & CAU_LDR_CA_CA3_MASK)
+#define CAU_LDR_CA_CA3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA3_SHIFT)) & CAU_LDR_CA_CA3_MASK)
+#define CAU_LDR_CA_CA3 CAU_LDR_CA_CA3_MASK
 #define CAU_LDR_CA_CA4_MASK                      (0xFFFFFFFFU)
 #define CAU_LDR_CA_CA4_SHIFT                     (0U)
-#define CAU_LDR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA4_SHIFT)) & CAU_LDR_CA_CA4_MASK)
+#define CAU_LDR_CA_CA4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA4_SHIFT)) & CAU_LDR_CA_CA4_MASK)
+#define CAU_LDR_CA_CA4 CAU_LDR_CA_CA4_MASK
 #define CAU_LDR_CA_CA5_MASK                      (0xFFFFFFFFU)
 #define CAU_LDR_CA_CA5_SHIFT                     (0U)
-#define CAU_LDR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA5_SHIFT)) & CAU_LDR_CA_CA5_MASK)
+#define CAU_LDR_CA_CA5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA5_SHIFT)) & CAU_LDR_CA_CA5_MASK)
+#define CAU_LDR_CA_CA5 CAU_LDR_CA_CA5_MASK
 #define CAU_LDR_CA_CA6_MASK                      (0xFFFFFFFFU)
 #define CAU_LDR_CA_CA6_SHIFT                     (0U)
-#define CAU_LDR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA6_SHIFT)) & CAU_LDR_CA_CA6_MASK)
+#define CAU_LDR_CA_CA6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA6_SHIFT)) & CAU_LDR_CA_CA6_MASK)
+#define CAU_LDR_CA_CA6 CAU_LDR_CA_CA6_MASK
 #define CAU_LDR_CA_CA7_MASK                      (0xFFFFFFFFU)
 #define CAU_LDR_CA_CA7_SHIFT                     (0U)
-#define CAU_LDR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA7_SHIFT)) & CAU_LDR_CA_CA7_MASK)
+#define CAU_LDR_CA_CA7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA7_SHIFT)) & CAU_LDR_CA_CA7_MASK)
+#define CAU_LDR_CA_CA7 CAU_LDR_CA_CA7_MASK
 #define CAU_LDR_CA_CA8_MASK                      (0xFFFFFFFFU)
 #define CAU_LDR_CA_CA8_SHIFT                     (0U)
-#define CAU_LDR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK)
+#define CAU_LDR_CA_CA8_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK)
+#define CAU_LDR_CA_CA8 CAU_LDR_CA_CA8_MASK
 
 /* The count of CAU_LDR_CA */
 #define CAU_LDR_CA_COUNT                         (9U)
@@ -2760,47 +3372,60 @@ typedef struct {
 /*! @name STR_CASR - Status register - Store Register command */
 #define CAU_STR_CASR_IC_MASK                     (0x1U)
 #define CAU_STR_CASR_IC_SHIFT                    (0U)
-#define CAU_STR_CASR_IC(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK)
+#define CAU_STR_CASR_IC_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK)
+#define CAU_STR_CASR_IC CAU_STR_CASR_IC_MASK
 #define CAU_STR_CASR_DPE_MASK                    (0x2U)
 #define CAU_STR_CASR_DPE_SHIFT                   (1U)
-#define CAU_STR_CASR_DPE(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK)
+#define CAU_STR_CASR_DPE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK)
+#define CAU_STR_CASR_DPE CAU_STR_CASR_DPE_MASK
 #define CAU_STR_CASR_VER_MASK                    (0xF0000000U)
 #define CAU_STR_CASR_VER_SHIFT                   (28U)
-#define CAU_STR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK)
+#define CAU_STR_CASR_VER_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK)
+#define CAU_STR_CASR_VER CAU_STR_CASR_VER_MASK
 
 /*! @name STR_CAA - Accumulator register - Store Register command */
 #define CAU_STR_CAA_ACC_MASK                     (0xFFFFFFFFU)
 #define CAU_STR_CAA_ACC_SHIFT                    (0U)
-#define CAU_STR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK)
+#define CAU_STR_CAA_ACC_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK)
+#define CAU_STR_CAA_ACC CAU_STR_CAA_ACC_MASK
 
 /*! @name STR_CA - General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command */
 #define CAU_STR_CA_CA0_MASK                      (0xFFFFFFFFU)
 #define CAU_STR_CA_CA0_SHIFT                     (0U)
-#define CAU_STR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK)
+#define CAU_STR_CA_CA0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK)
+#define CAU_STR_CA_CA0 CAU_STR_CA_CA0_MASK
 #define CAU_STR_CA_CA1_MASK                      (0xFFFFFFFFU)
 #define CAU_STR_CA_CA1_SHIFT                     (0U)
-#define CAU_STR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA1_SHIFT)) & CAU_STR_CA_CA1_MASK)
+#define CAU_STR_CA_CA1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA1_SHIFT)) & CAU_STR_CA_CA1_MASK)
+#define CAU_STR_CA_CA1 CAU_STR_CA_CA1_MASK
 #define CAU_STR_CA_CA2_MASK                      (0xFFFFFFFFU)
 #define CAU_STR_CA_CA2_SHIFT                     (0U)
-#define CAU_STR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA2_SHIFT)) & CAU_STR_CA_CA2_MASK)
+#define CAU_STR_CA_CA2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA2_SHIFT)) & CAU_STR_CA_CA2_MASK)
+#define CAU_STR_CA_CA2 CAU_STR_CA_CA2_MASK
 #define CAU_STR_CA_CA3_MASK                      (0xFFFFFFFFU)
 #define CAU_STR_CA_CA3_SHIFT                     (0U)
-#define CAU_STR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA3_SHIFT)) & CAU_STR_CA_CA3_MASK)
+#define CAU_STR_CA_CA3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA3_SHIFT)) & CAU_STR_CA_CA3_MASK)
+#define CAU_STR_CA_CA3 CAU_STR_CA_CA3_MASK
 #define CAU_STR_CA_CA4_MASK                      (0xFFFFFFFFU)
 #define CAU_STR_CA_CA4_SHIFT                     (0U)
-#define CAU_STR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA4_SHIFT)) & CAU_STR_CA_CA4_MASK)
+#define CAU_STR_CA_CA4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA4_SHIFT)) & CAU_STR_CA_CA4_MASK)
+#define CAU_STR_CA_CA4 CAU_STR_CA_CA4_MASK
 #define CAU_STR_CA_CA5_MASK                      (0xFFFFFFFFU)
 #define CAU_STR_CA_CA5_SHIFT                     (0U)
-#define CAU_STR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA5_SHIFT)) & CAU_STR_CA_CA5_MASK)
+#define CAU_STR_CA_CA5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA5_SHIFT)) & CAU_STR_CA_CA5_MASK)
+#define CAU_STR_CA_CA5 CAU_STR_CA_CA5_MASK
 #define CAU_STR_CA_CA6_MASK                      (0xFFFFFFFFU)
 #define CAU_STR_CA_CA6_SHIFT                     (0U)
-#define CAU_STR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA6_SHIFT)) & CAU_STR_CA_CA6_MASK)
+#define CAU_STR_CA_CA6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA6_SHIFT)) & CAU_STR_CA_CA6_MASK)
+#define CAU_STR_CA_CA6 CAU_STR_CA_CA6_MASK
 #define CAU_STR_CA_CA7_MASK                      (0xFFFFFFFFU)
 #define CAU_STR_CA_CA7_SHIFT                     (0U)
-#define CAU_STR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA7_SHIFT)) & CAU_STR_CA_CA7_MASK)
+#define CAU_STR_CA_CA7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA7_SHIFT)) & CAU_STR_CA_CA7_MASK)
+#define CAU_STR_CA_CA7 CAU_STR_CA_CA7_MASK
 #define CAU_STR_CA_CA8_MASK                      (0xFFFFFFFFU)
 #define CAU_STR_CA_CA8_SHIFT                     (0U)
-#define CAU_STR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK)
+#define CAU_STR_CA_CA8_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK)
+#define CAU_STR_CA_CA8 CAU_STR_CA_CA8_MASK
 
 /* The count of CAU_STR_CA */
 #define CAU_STR_CA_COUNT                         (9U)
@@ -2808,47 +3433,60 @@ typedef struct {
 /*! @name ADR_CASR - Status register - Add Register command */
 #define CAU_ADR_CASR_IC_MASK                     (0x1U)
 #define CAU_ADR_CASR_IC_SHIFT                    (0U)
-#define CAU_ADR_CASR_IC(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK)
+#define CAU_ADR_CASR_IC_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK)
+#define CAU_ADR_CASR_IC CAU_ADR_CASR_IC_MASK
 #define CAU_ADR_CASR_DPE_MASK                    (0x2U)
 #define CAU_ADR_CASR_DPE_SHIFT                   (1U)
-#define CAU_ADR_CASR_DPE(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK)
+#define CAU_ADR_CASR_DPE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK)
+#define CAU_ADR_CASR_DPE CAU_ADR_CASR_DPE_MASK
 #define CAU_ADR_CASR_VER_MASK                    (0xF0000000U)
 #define CAU_ADR_CASR_VER_SHIFT                   (28U)
-#define CAU_ADR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK)
+#define CAU_ADR_CASR_VER_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK)
+#define CAU_ADR_CASR_VER CAU_ADR_CASR_VER_MASK
 
 /*! @name ADR_CAA - Accumulator register - Add to register command */
 #define CAU_ADR_CAA_ACC_MASK                     (0xFFFFFFFFU)
 #define CAU_ADR_CAA_ACC_SHIFT                    (0U)
-#define CAU_ADR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK)
+#define CAU_ADR_CAA_ACC_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK)
+#define CAU_ADR_CAA_ACC CAU_ADR_CAA_ACC_MASK
 
 /*! @name ADR_CA - General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command */
 #define CAU_ADR_CA_CA0_MASK                      (0xFFFFFFFFU)
 #define CAU_ADR_CA_CA0_SHIFT                     (0U)
-#define CAU_ADR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK)
+#define CAU_ADR_CA_CA0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK)
+#define CAU_ADR_CA_CA0 CAU_ADR_CA_CA0_MASK
 #define CAU_ADR_CA_CA1_MASK                      (0xFFFFFFFFU)
 #define CAU_ADR_CA_CA1_SHIFT                     (0U)
-#define CAU_ADR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA1_SHIFT)) & CAU_ADR_CA_CA1_MASK)
+#define CAU_ADR_CA_CA1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA1_SHIFT)) & CAU_ADR_CA_CA1_MASK)
+#define CAU_ADR_CA_CA1 CAU_ADR_CA_CA1_MASK
 #define CAU_ADR_CA_CA2_MASK                      (0xFFFFFFFFU)
 #define CAU_ADR_CA_CA2_SHIFT                     (0U)
-#define CAU_ADR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA2_SHIFT)) & CAU_ADR_CA_CA2_MASK)
+#define CAU_ADR_CA_CA2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA2_SHIFT)) & CAU_ADR_CA_CA2_MASK)
+#define CAU_ADR_CA_CA2 CAU_ADR_CA_CA2_MASK
 #define CAU_ADR_CA_CA3_MASK                      (0xFFFFFFFFU)
 #define CAU_ADR_CA_CA3_SHIFT                     (0U)
-#define CAU_ADR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA3_SHIFT)) & CAU_ADR_CA_CA3_MASK)
+#define CAU_ADR_CA_CA3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA3_SHIFT)) & CAU_ADR_CA_CA3_MASK)
+#define CAU_ADR_CA_CA3 CAU_ADR_CA_CA3_MASK
 #define CAU_ADR_CA_CA4_MASK                      (0xFFFFFFFFU)
 #define CAU_ADR_CA_CA4_SHIFT                     (0U)
-#define CAU_ADR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA4_SHIFT)) & CAU_ADR_CA_CA4_MASK)
+#define CAU_ADR_CA_CA4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA4_SHIFT)) & CAU_ADR_CA_CA4_MASK)
+#define CAU_ADR_CA_CA4 CAU_ADR_CA_CA4_MASK
 #define CAU_ADR_CA_CA5_MASK                      (0xFFFFFFFFU)
 #define CAU_ADR_CA_CA5_SHIFT                     (0U)
-#define CAU_ADR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA5_SHIFT)) & CAU_ADR_CA_CA5_MASK)
+#define CAU_ADR_CA_CA5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA5_SHIFT)) & CAU_ADR_CA_CA5_MASK)
+#define CAU_ADR_CA_CA5 CAU_ADR_CA_CA5_MASK
 #define CAU_ADR_CA_CA6_MASK                      (0xFFFFFFFFU)
 #define CAU_ADR_CA_CA6_SHIFT                     (0U)
-#define CAU_ADR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA6_SHIFT)) & CAU_ADR_CA_CA6_MASK)
+#define CAU_ADR_CA_CA6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA6_SHIFT)) & CAU_ADR_CA_CA6_MASK)
+#define CAU_ADR_CA_CA6 CAU_ADR_CA_CA6_MASK
 #define CAU_ADR_CA_CA7_MASK                      (0xFFFFFFFFU)
 #define CAU_ADR_CA_CA7_SHIFT                     (0U)
-#define CAU_ADR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA7_SHIFT)) & CAU_ADR_CA_CA7_MASK)
+#define CAU_ADR_CA_CA7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA7_SHIFT)) & CAU_ADR_CA_CA7_MASK)
+#define CAU_ADR_CA_CA7 CAU_ADR_CA_CA7_MASK
 #define CAU_ADR_CA_CA8_MASK                      (0xFFFFFFFFU)
 #define CAU_ADR_CA_CA8_SHIFT                     (0U)
-#define CAU_ADR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK)
+#define CAU_ADR_CA_CA8_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK)
+#define CAU_ADR_CA_CA8 CAU_ADR_CA_CA8_MASK
 
 /* The count of CAU_ADR_CA */
 #define CAU_ADR_CA_COUNT                         (9U)
@@ -2856,47 +3494,60 @@ typedef struct {
 /*! @name RADR_CASR - Status register - Reverse and Add to Register command */
 #define CAU_RADR_CASR_IC_MASK                    (0x1U)
 #define CAU_RADR_CASR_IC_SHIFT                   (0U)
-#define CAU_RADR_CASR_IC(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK)
+#define CAU_RADR_CASR_IC_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK)
+#define CAU_RADR_CASR_IC CAU_RADR_CASR_IC_MASK
 #define CAU_RADR_CASR_DPE_MASK                   (0x2U)
 #define CAU_RADR_CASR_DPE_SHIFT                  (1U)
-#define CAU_RADR_CASR_DPE(x)                     (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK)
+#define CAU_RADR_CASR_DPE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK)
+#define CAU_RADR_CASR_DPE CAU_RADR_CASR_DPE_MASK
 #define CAU_RADR_CASR_VER_MASK                   (0xF0000000U)
 #define CAU_RADR_CASR_VER_SHIFT                  (28U)
-#define CAU_RADR_CASR_VER(x)                     (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK)
+#define CAU_RADR_CASR_VER_SET(x)                 (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK)
+#define CAU_RADR_CASR_VER CAU_RADR_CASR_VER_MASK
 
 /*! @name RADR_CAA - Accumulator register - Reverse and Add to Register command */
 #define CAU_RADR_CAA_ACC_MASK                    (0xFFFFFFFFU)
 #define CAU_RADR_CAA_ACC_SHIFT                   (0U)
-#define CAU_RADR_CAA_ACC(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK)
+#define CAU_RADR_CAA_ACC_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK)
+#define CAU_RADR_CAA_ACC CAU_RADR_CAA_ACC_MASK
 
 /*! @name RADR_CA - General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command */
 #define CAU_RADR_CA_CA0_MASK                     (0xFFFFFFFFU)
 #define CAU_RADR_CA_CA0_SHIFT                    (0U)
-#define CAU_RADR_CA_CA0(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK)
+#define CAU_RADR_CA_CA0_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK)
+#define CAU_RADR_CA_CA0 CAU_RADR_CA_CA0_MASK
 #define CAU_RADR_CA_CA1_MASK                     (0xFFFFFFFFU)
 #define CAU_RADR_CA_CA1_SHIFT                    (0U)
-#define CAU_RADR_CA_CA1(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA1_SHIFT)) & CAU_RADR_CA_CA1_MASK)
+#define CAU_RADR_CA_CA1_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA1_SHIFT)) & CAU_RADR_CA_CA1_MASK)
+#define CAU_RADR_CA_CA1 CAU_RADR_CA_CA1_MASK
 #define CAU_RADR_CA_CA2_MASK                     (0xFFFFFFFFU)
 #define CAU_RADR_CA_CA2_SHIFT                    (0U)
-#define CAU_RADR_CA_CA2(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA2_SHIFT)) & CAU_RADR_CA_CA2_MASK)
+#define CAU_RADR_CA_CA2_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA2_SHIFT)) & CAU_RADR_CA_CA2_MASK)
+#define CAU_RADR_CA_CA2 CAU_RADR_CA_CA2_MASK
 #define CAU_RADR_CA_CA3_MASK                     (0xFFFFFFFFU)
 #define CAU_RADR_CA_CA3_SHIFT                    (0U)
-#define CAU_RADR_CA_CA3(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA3_SHIFT)) & CAU_RADR_CA_CA3_MASK)
+#define CAU_RADR_CA_CA3_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA3_SHIFT)) & CAU_RADR_CA_CA3_MASK)
+#define CAU_RADR_CA_CA3 CAU_RADR_CA_CA3_MASK
 #define CAU_RADR_CA_CA4_MASK                     (0xFFFFFFFFU)
 #define CAU_RADR_CA_CA4_SHIFT                    (0U)
-#define CAU_RADR_CA_CA4(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA4_SHIFT)) & CAU_RADR_CA_CA4_MASK)
+#define CAU_RADR_CA_CA4_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA4_SHIFT)) & CAU_RADR_CA_CA4_MASK)
+#define CAU_RADR_CA_CA4 CAU_RADR_CA_CA4_MASK
 #define CAU_RADR_CA_CA5_MASK                     (0xFFFFFFFFU)
 #define CAU_RADR_CA_CA5_SHIFT                    (0U)
-#define CAU_RADR_CA_CA5(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA5_SHIFT)) & CAU_RADR_CA_CA5_MASK)
+#define CAU_RADR_CA_CA5_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA5_SHIFT)) & CAU_RADR_CA_CA5_MASK)
+#define CAU_RADR_CA_CA5 CAU_RADR_CA_CA5_MASK
 #define CAU_RADR_CA_CA6_MASK                     (0xFFFFFFFFU)
 #define CAU_RADR_CA_CA6_SHIFT                    (0U)
-#define CAU_RADR_CA_CA6(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA6_SHIFT)) & CAU_RADR_CA_CA6_MASK)
+#define CAU_RADR_CA_CA6_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA6_SHIFT)) & CAU_RADR_CA_CA6_MASK)
+#define CAU_RADR_CA_CA6 CAU_RADR_CA_CA6_MASK
 #define CAU_RADR_CA_CA7_MASK                     (0xFFFFFFFFU)
 #define CAU_RADR_CA_CA7_SHIFT                    (0U)
-#define CAU_RADR_CA_CA7(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA7_SHIFT)) & CAU_RADR_CA_CA7_MASK)
+#define CAU_RADR_CA_CA7_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA7_SHIFT)) & CAU_RADR_CA_CA7_MASK)
+#define CAU_RADR_CA_CA7 CAU_RADR_CA_CA7_MASK
 #define CAU_RADR_CA_CA8_MASK                     (0xFFFFFFFFU)
 #define CAU_RADR_CA_CA8_SHIFT                    (0U)
-#define CAU_RADR_CA_CA8(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK)
+#define CAU_RADR_CA_CA8_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK)
+#define CAU_RADR_CA_CA8 CAU_RADR_CA_CA8_MASK
 
 /* The count of CAU_RADR_CA */
 #define CAU_RADR_CA_COUNT                        (9U)
@@ -2904,47 +3555,60 @@ typedef struct {
 /*! @name XOR_CASR - Status register - Exclusive Or command */
 #define CAU_XOR_CASR_IC_MASK                     (0x1U)
 #define CAU_XOR_CASR_IC_SHIFT                    (0U)
-#define CAU_XOR_CASR_IC(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK)
+#define CAU_XOR_CASR_IC_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK)
+#define CAU_XOR_CASR_IC CAU_XOR_CASR_IC_MASK
 #define CAU_XOR_CASR_DPE_MASK                    (0x2U)
 #define CAU_XOR_CASR_DPE_SHIFT                   (1U)
-#define CAU_XOR_CASR_DPE(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK)
+#define CAU_XOR_CASR_DPE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK)
+#define CAU_XOR_CASR_DPE CAU_XOR_CASR_DPE_MASK
 #define CAU_XOR_CASR_VER_MASK                    (0xF0000000U)
 #define CAU_XOR_CASR_VER_SHIFT                   (28U)
-#define CAU_XOR_CASR_VER(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK)
+#define CAU_XOR_CASR_VER_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK)
+#define CAU_XOR_CASR_VER CAU_XOR_CASR_VER_MASK
 
 /*! @name XOR_CAA - Accumulator register - Exclusive Or command */
 #define CAU_XOR_CAA_ACC_MASK                     (0xFFFFFFFFU)
 #define CAU_XOR_CAA_ACC_SHIFT                    (0U)
-#define CAU_XOR_CAA_ACC(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK)
+#define CAU_XOR_CAA_ACC_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK)
+#define CAU_XOR_CAA_ACC CAU_XOR_CAA_ACC_MASK
 
 /*! @name XOR_CA - General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command */
 #define CAU_XOR_CA_CA0_MASK                      (0xFFFFFFFFU)
 #define CAU_XOR_CA_CA0_SHIFT                     (0U)
-#define CAU_XOR_CA_CA0(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK)
+#define CAU_XOR_CA_CA0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK)
+#define CAU_XOR_CA_CA0 CAU_XOR_CA_CA0_MASK
 #define CAU_XOR_CA_CA1_MASK                      (0xFFFFFFFFU)
 #define CAU_XOR_CA_CA1_SHIFT                     (0U)
-#define CAU_XOR_CA_CA1(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA1_SHIFT)) & CAU_XOR_CA_CA1_MASK)
+#define CAU_XOR_CA_CA1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA1_SHIFT)) & CAU_XOR_CA_CA1_MASK)
+#define CAU_XOR_CA_CA1 CAU_XOR_CA_CA1_MASK
 #define CAU_XOR_CA_CA2_MASK                      (0xFFFFFFFFU)
 #define CAU_XOR_CA_CA2_SHIFT                     (0U)
-#define CAU_XOR_CA_CA2(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA2_SHIFT)) & CAU_XOR_CA_CA2_MASK)
+#define CAU_XOR_CA_CA2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA2_SHIFT)) & CAU_XOR_CA_CA2_MASK)
+#define CAU_XOR_CA_CA2 CAU_XOR_CA_CA2_MASK
 #define CAU_XOR_CA_CA3_MASK                      (0xFFFFFFFFU)
 #define CAU_XOR_CA_CA3_SHIFT                     (0U)
-#define CAU_XOR_CA_CA3(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA3_SHIFT)) & CAU_XOR_CA_CA3_MASK)
+#define CAU_XOR_CA_CA3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA3_SHIFT)) & CAU_XOR_CA_CA3_MASK)
+#define CAU_XOR_CA_CA3 CAU_XOR_CA_CA3_MASK
 #define CAU_XOR_CA_CA4_MASK                      (0xFFFFFFFFU)
 #define CAU_XOR_CA_CA4_SHIFT                     (0U)
-#define CAU_XOR_CA_CA4(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA4_SHIFT)) & CAU_XOR_CA_CA4_MASK)
+#define CAU_XOR_CA_CA4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA4_SHIFT)) & CAU_XOR_CA_CA4_MASK)
+#define CAU_XOR_CA_CA4 CAU_XOR_CA_CA4_MASK
 #define CAU_XOR_CA_CA5_MASK                      (0xFFFFFFFFU)
 #define CAU_XOR_CA_CA5_SHIFT                     (0U)
-#define CAU_XOR_CA_CA5(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA5_SHIFT)) & CAU_XOR_CA_CA5_MASK)
+#define CAU_XOR_CA_CA5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA5_SHIFT)) & CAU_XOR_CA_CA5_MASK)
+#define CAU_XOR_CA_CA5 CAU_XOR_CA_CA5_MASK
 #define CAU_XOR_CA_CA6_MASK                      (0xFFFFFFFFU)
 #define CAU_XOR_CA_CA6_SHIFT                     (0U)
-#define CAU_XOR_CA_CA6(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA6_SHIFT)) & CAU_XOR_CA_CA6_MASK)
+#define CAU_XOR_CA_CA6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA6_SHIFT)) & CAU_XOR_CA_CA6_MASK)
+#define CAU_XOR_CA_CA6 CAU_XOR_CA_CA6_MASK
 #define CAU_XOR_CA_CA7_MASK                      (0xFFFFFFFFU)
 #define CAU_XOR_CA_CA7_SHIFT                     (0U)
-#define CAU_XOR_CA_CA7(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA7_SHIFT)) & CAU_XOR_CA_CA7_MASK)
+#define CAU_XOR_CA_CA7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA7_SHIFT)) & CAU_XOR_CA_CA7_MASK)
+#define CAU_XOR_CA_CA7 CAU_XOR_CA_CA7_MASK
 #define CAU_XOR_CA_CA8_MASK                      (0xFFFFFFFFU)
 #define CAU_XOR_CA_CA8_SHIFT                     (0U)
-#define CAU_XOR_CA_CA8(x)                        (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK)
+#define CAU_XOR_CA_CA8_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK)
+#define CAU_XOR_CA_CA8 CAU_XOR_CA_CA8_MASK
 
 /* The count of CAU_XOR_CA */
 #define CAU_XOR_CA_COUNT                         (9U)
@@ -2952,47 +3616,60 @@ typedef struct {
 /*! @name ROTL_CASR - Status register - Rotate Left command */
 #define CAU_ROTL_CASR_IC_MASK                    (0x1U)
 #define CAU_ROTL_CASR_IC_SHIFT                   (0U)
-#define CAU_ROTL_CASR_IC(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK)
+#define CAU_ROTL_CASR_IC_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK)
+#define CAU_ROTL_CASR_IC CAU_ROTL_CASR_IC_MASK
 #define CAU_ROTL_CASR_DPE_MASK                   (0x2U)
 #define CAU_ROTL_CASR_DPE_SHIFT                  (1U)
-#define CAU_ROTL_CASR_DPE(x)                     (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK)
+#define CAU_ROTL_CASR_DPE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK)
+#define CAU_ROTL_CASR_DPE CAU_ROTL_CASR_DPE_MASK
 #define CAU_ROTL_CASR_VER_MASK                   (0xF0000000U)
 #define CAU_ROTL_CASR_VER_SHIFT                  (28U)
-#define CAU_ROTL_CASR_VER(x)                     (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK)
+#define CAU_ROTL_CASR_VER_SET(x)                 (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK)
+#define CAU_ROTL_CASR_VER CAU_ROTL_CASR_VER_MASK
 
 /*! @name ROTL_CAA - Accumulator register - Rotate Left command */
 #define CAU_ROTL_CAA_ACC_MASK                    (0xFFFFFFFFU)
 #define CAU_ROTL_CAA_ACC_SHIFT                   (0U)
-#define CAU_ROTL_CAA_ACC(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK)
+#define CAU_ROTL_CAA_ACC_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK)
+#define CAU_ROTL_CAA_ACC CAU_ROTL_CAA_ACC_MASK
 
 /*! @name ROTL_CA - General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command */
 #define CAU_ROTL_CA_CA0_MASK                     (0xFFFFFFFFU)
 #define CAU_ROTL_CA_CA0_SHIFT                    (0U)
-#define CAU_ROTL_CA_CA0(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK)
+#define CAU_ROTL_CA_CA0_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK)
+#define CAU_ROTL_CA_CA0 CAU_ROTL_CA_CA0_MASK
 #define CAU_ROTL_CA_CA1_MASK                     (0xFFFFFFFFU)
 #define CAU_ROTL_CA_CA1_SHIFT                    (0U)
-#define CAU_ROTL_CA_CA1(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA1_SHIFT)) & CAU_ROTL_CA_CA1_MASK)
+#define CAU_ROTL_CA_CA1_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA1_SHIFT)) & CAU_ROTL_CA_CA1_MASK)
+#define CAU_ROTL_CA_CA1 CAU_ROTL_CA_CA1_MASK
 #define CAU_ROTL_CA_CA2_MASK                     (0xFFFFFFFFU)
 #define CAU_ROTL_CA_CA2_SHIFT                    (0U)
-#define CAU_ROTL_CA_CA2(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA2_SHIFT)) & CAU_ROTL_CA_CA2_MASK)
+#define CAU_ROTL_CA_CA2_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA2_SHIFT)) & CAU_ROTL_CA_CA2_MASK)
+#define CAU_ROTL_CA_CA2 CAU_ROTL_CA_CA2_MASK
 #define CAU_ROTL_CA_CA3_MASK                     (0xFFFFFFFFU)
 #define CAU_ROTL_CA_CA3_SHIFT                    (0U)
-#define CAU_ROTL_CA_CA3(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA3_SHIFT)) & CAU_ROTL_CA_CA3_MASK)
+#define CAU_ROTL_CA_CA3_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA3_SHIFT)) & CAU_ROTL_CA_CA3_MASK)
+#define CAU_ROTL_CA_CA3 CAU_ROTL_CA_CA3_MASK
 #define CAU_ROTL_CA_CA4_MASK                     (0xFFFFFFFFU)
 #define CAU_ROTL_CA_CA4_SHIFT                    (0U)
-#define CAU_ROTL_CA_CA4(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA4_SHIFT)) & CAU_ROTL_CA_CA4_MASK)
+#define CAU_ROTL_CA_CA4_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA4_SHIFT)) & CAU_ROTL_CA_CA4_MASK)
+#define CAU_ROTL_CA_CA4 CAU_ROTL_CA_CA4_MASK
 #define CAU_ROTL_CA_CA5_MASK                     (0xFFFFFFFFU)
 #define CAU_ROTL_CA_CA5_SHIFT                    (0U)
-#define CAU_ROTL_CA_CA5(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA5_SHIFT)) & CAU_ROTL_CA_CA5_MASK)
+#define CAU_ROTL_CA_CA5_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA5_SHIFT)) & CAU_ROTL_CA_CA5_MASK)
+#define CAU_ROTL_CA_CA5 CAU_ROTL_CA_CA5_MASK
 #define CAU_ROTL_CA_CA6_MASK                     (0xFFFFFFFFU)
 #define CAU_ROTL_CA_CA6_SHIFT                    (0U)
-#define CAU_ROTL_CA_CA6(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA6_SHIFT)) & CAU_ROTL_CA_CA6_MASK)
+#define CAU_ROTL_CA_CA6_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA6_SHIFT)) & CAU_ROTL_CA_CA6_MASK)
+#define CAU_ROTL_CA_CA6 CAU_ROTL_CA_CA6_MASK
 #define CAU_ROTL_CA_CA7_MASK                     (0xFFFFFFFFU)
 #define CAU_ROTL_CA_CA7_SHIFT                    (0U)
-#define CAU_ROTL_CA_CA7(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA7_SHIFT)) & CAU_ROTL_CA_CA7_MASK)
+#define CAU_ROTL_CA_CA7_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA7_SHIFT)) & CAU_ROTL_CA_CA7_MASK)
+#define CAU_ROTL_CA_CA7 CAU_ROTL_CA_CA7_MASK
 #define CAU_ROTL_CA_CA8_MASK                     (0xFFFFFFFFU)
 #define CAU_ROTL_CA_CA8_SHIFT                    (0U)
-#define CAU_ROTL_CA_CA8(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA8_SHIFT)) & CAU_ROTL_CA_CA8_MASK)
+#define CAU_ROTL_CA_CA8_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA8_SHIFT)) & CAU_ROTL_CA_CA8_MASK)
+#define CAU_ROTL_CA_CA8 CAU_ROTL_CA_CA8_MASK
 
 /* The count of CAU_ROTL_CA */
 #define CAU_ROTL_CA_COUNT                        (9U)
@@ -3000,47 +3677,60 @@ typedef struct {
 /*! @name AESC_CASR - Status register - AES Column Operation command */
 #define CAU_AESC_CASR_IC_MASK                    (0x1U)
 #define CAU_AESC_CASR_IC_SHIFT                   (0U)
-#define CAU_AESC_CASR_IC(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK)
+#define CAU_AESC_CASR_IC_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK)
+#define CAU_AESC_CASR_IC CAU_AESC_CASR_IC_MASK
 #define CAU_AESC_CASR_DPE_MASK                   (0x2U)
 #define CAU_AESC_CASR_DPE_SHIFT                  (1U)
-#define CAU_AESC_CASR_DPE(x)                     (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK)
+#define CAU_AESC_CASR_DPE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK)
+#define CAU_AESC_CASR_DPE CAU_AESC_CASR_DPE_MASK
 #define CAU_AESC_CASR_VER_MASK                   (0xF0000000U)
 #define CAU_AESC_CASR_VER_SHIFT                  (28U)
-#define CAU_AESC_CASR_VER(x)                     (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK)
+#define CAU_AESC_CASR_VER_SET(x)                 (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK)
+#define CAU_AESC_CASR_VER CAU_AESC_CASR_VER_MASK
 
 /*! @name AESC_CAA - Accumulator register - AES Column Operation command */
 #define CAU_AESC_CAA_ACC_MASK                    (0xFFFFFFFFU)
 #define CAU_AESC_CAA_ACC_SHIFT                   (0U)
-#define CAU_AESC_CAA_ACC(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CAA_ACC_SHIFT)) & CAU_AESC_CAA_ACC_MASK)
+#define CAU_AESC_CAA_ACC_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CAA_ACC_SHIFT)) & CAU_AESC_CAA_ACC_MASK)
+#define CAU_AESC_CAA_ACC CAU_AESC_CAA_ACC_MASK
 
 /*! @name AESC_CA - General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command */
 #define CAU_AESC_CA_CA0_MASK                     (0xFFFFFFFFU)
 #define CAU_AESC_CA_CA0_SHIFT                    (0U)
-#define CAU_AESC_CA_CA0(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA0_SHIFT)) & CAU_AESC_CA_CA0_MASK)
+#define CAU_AESC_CA_CA0_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA0_SHIFT)) & CAU_AESC_CA_CA0_MASK)
+#define CAU_AESC_CA_CA0 CAU_AESC_CA_CA0_MASK
 #define CAU_AESC_CA_CA1_MASK                     (0xFFFFFFFFU)
 #define CAU_AESC_CA_CA1_SHIFT                    (0U)
-#define CAU_AESC_CA_CA1(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA1_SHIFT)) & CAU_AESC_CA_CA1_MASK)
+#define CAU_AESC_CA_CA1_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA1_SHIFT)) & CAU_AESC_CA_CA1_MASK)
+#define CAU_AESC_CA_CA1 CAU_AESC_CA_CA1_MASK
 #define CAU_AESC_CA_CA2_MASK                     (0xFFFFFFFFU)
 #define CAU_AESC_CA_CA2_SHIFT                    (0U)
-#define CAU_AESC_CA_CA2(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA2_SHIFT)) & CAU_AESC_CA_CA2_MASK)
+#define CAU_AESC_CA_CA2_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA2_SHIFT)) & CAU_AESC_CA_CA2_MASK)
+#define CAU_AESC_CA_CA2 CAU_AESC_CA_CA2_MASK
 #define CAU_AESC_CA_CA3_MASK                     (0xFFFFFFFFU)
 #define CAU_AESC_CA_CA3_SHIFT                    (0U)
-#define CAU_AESC_CA_CA3(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA3_SHIFT)) & CAU_AESC_CA_CA3_MASK)
+#define CAU_AESC_CA_CA3_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA3_SHIFT)) & CAU_AESC_CA_CA3_MASK)
+#define CAU_AESC_CA_CA3 CAU_AESC_CA_CA3_MASK
 #define CAU_AESC_CA_CA4_MASK                     (0xFFFFFFFFU)
 #define CAU_AESC_CA_CA4_SHIFT                    (0U)
-#define CAU_AESC_CA_CA4(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA4_SHIFT)) & CAU_AESC_CA_CA4_MASK)
+#define CAU_AESC_CA_CA4_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA4_SHIFT)) & CAU_AESC_CA_CA4_MASK)
+#define CAU_AESC_CA_CA4 CAU_AESC_CA_CA4_MASK
 #define CAU_AESC_CA_CA5_MASK                     (0xFFFFFFFFU)
 #define CAU_AESC_CA_CA5_SHIFT                    (0U)
-#define CAU_AESC_CA_CA5(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA5_SHIFT)) & CAU_AESC_CA_CA5_MASK)
+#define CAU_AESC_CA_CA5_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA5_SHIFT)) & CAU_AESC_CA_CA5_MASK)
+#define CAU_AESC_CA_CA5 CAU_AESC_CA_CA5_MASK
 #define CAU_AESC_CA_CA6_MASK                     (0xFFFFFFFFU)
 #define CAU_AESC_CA_CA6_SHIFT                    (0U)
-#define CAU_AESC_CA_CA6(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA6_SHIFT)) & CAU_AESC_CA_CA6_MASK)
+#define CAU_AESC_CA_CA6_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA6_SHIFT)) & CAU_AESC_CA_CA6_MASK)
+#define CAU_AESC_CA_CA6 CAU_AESC_CA_CA6_MASK
 #define CAU_AESC_CA_CA7_MASK                     (0xFFFFFFFFU)
 #define CAU_AESC_CA_CA7_SHIFT                    (0U)
-#define CAU_AESC_CA_CA7(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA7_SHIFT)) & CAU_AESC_CA_CA7_MASK)
+#define CAU_AESC_CA_CA7_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA7_SHIFT)) & CAU_AESC_CA_CA7_MASK)
+#define CAU_AESC_CA_CA7 CAU_AESC_CA_CA7_MASK
 #define CAU_AESC_CA_CA8_MASK                     (0xFFFFFFFFU)
 #define CAU_AESC_CA_CA8_SHIFT                    (0U)
-#define CAU_AESC_CA_CA8(x)                       (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA8_SHIFT)) & CAU_AESC_CA_CA8_MASK)
+#define CAU_AESC_CA_CA8_SET(x)                   (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA8_SHIFT)) & CAU_AESC_CA_CA8_MASK)
+#define CAU_AESC_CA_CA8 CAU_AESC_CA_CA8_MASK
 
 /* The count of CAU_AESC_CA */
 #define CAU_AESC_CA_COUNT                        (9U)
@@ -3048,47 +3738,60 @@ typedef struct {
 /*! @name AESIC_CASR - Status register - AES Inverse Column Operation command */
 #define CAU_AESIC_CASR_IC_MASK                   (0x1U)
 #define CAU_AESIC_CASR_IC_SHIFT                  (0U)
-#define CAU_AESIC_CASR_IC(x)                     (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK)
+#define CAU_AESIC_CASR_IC_SET(x)                 (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK)
+#define CAU_AESIC_CASR_IC CAU_AESIC_CASR_IC_MASK
 #define CAU_AESIC_CASR_DPE_MASK                  (0x2U)
 #define CAU_AESIC_CASR_DPE_SHIFT                 (1U)
-#define CAU_AESIC_CASR_DPE(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK)
+#define CAU_AESIC_CASR_DPE_SET(x)                (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK)
+#define CAU_AESIC_CASR_DPE CAU_AESIC_CASR_DPE_MASK
 #define CAU_AESIC_CASR_VER_MASK                  (0xF0000000U)
 #define CAU_AESIC_CASR_VER_SHIFT                 (28U)
-#define CAU_AESIC_CASR_VER(x)                    (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK)
+#define CAU_AESIC_CASR_VER_SET(x)                (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK)
+#define CAU_AESIC_CASR_VER CAU_AESIC_CASR_VER_MASK
 
 /*! @name AESIC_CAA - Accumulator register - AES Inverse Column Operation command */
 #define CAU_AESIC_CAA_ACC_MASK                   (0xFFFFFFFFU)
 #define CAU_AESIC_CAA_ACC_SHIFT                  (0U)
-#define CAU_AESIC_CAA_ACC(x)                     (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CAA_ACC_SHIFT)) & CAU_AESIC_CAA_ACC_MASK)
+#define CAU_AESIC_CAA_ACC_SET(x)                 (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CAA_ACC_SHIFT)) & CAU_AESIC_CAA_ACC_MASK)
+#define CAU_AESIC_CAA_ACC CAU_AESIC_CAA_ACC_MASK
 
 /*! @name AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command */
 #define CAU_AESIC_CA_CA0_MASK                    (0xFFFFFFFFU)
 #define CAU_AESIC_CA_CA0_SHIFT                   (0U)
-#define CAU_AESIC_CA_CA0(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA0_SHIFT)) & CAU_AESIC_CA_CA0_MASK)
+#define CAU_AESIC_CA_CA0_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA0_SHIFT)) & CAU_AESIC_CA_CA0_MASK)
+#define CAU_AESIC_CA_CA0 CAU_AESIC_CA_CA0_MASK
 #define CAU_AESIC_CA_CA1_MASK                    (0xFFFFFFFFU)
 #define CAU_AESIC_CA_CA1_SHIFT                   (0U)
-#define CAU_AESIC_CA_CA1(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA1_SHIFT)) & CAU_AESIC_CA_CA1_MASK)
+#define CAU_AESIC_CA_CA1_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA1_SHIFT)) & CAU_AESIC_CA_CA1_MASK)
+#define CAU_AESIC_CA_CA1 CAU_AESIC_CA_CA1_MASK
 #define CAU_AESIC_CA_CA2_MASK                    (0xFFFFFFFFU)
 #define CAU_AESIC_CA_CA2_SHIFT                   (0U)
-#define CAU_AESIC_CA_CA2(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA2_SHIFT)) & CAU_AESIC_CA_CA2_MASK)
+#define CAU_AESIC_CA_CA2_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA2_SHIFT)) & CAU_AESIC_CA_CA2_MASK)
+#define CAU_AESIC_CA_CA2 CAU_AESIC_CA_CA2_MASK
 #define CAU_AESIC_CA_CA3_MASK                    (0xFFFFFFFFU)
 #define CAU_AESIC_CA_CA3_SHIFT                   (0U)
-#define CAU_AESIC_CA_CA3(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA3_SHIFT)) & CAU_AESIC_CA_CA3_MASK)
+#define CAU_AESIC_CA_CA3_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA3_SHIFT)) & CAU_AESIC_CA_CA3_MASK)
+#define CAU_AESIC_CA_CA3 CAU_AESIC_CA_CA3_MASK
 #define CAU_AESIC_CA_CA4_MASK                    (0xFFFFFFFFU)
 #define CAU_AESIC_CA_CA4_SHIFT                   (0U)
-#define CAU_AESIC_CA_CA4(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA4_SHIFT)) & CAU_AESIC_CA_CA4_MASK)
+#define CAU_AESIC_CA_CA4_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA4_SHIFT)) & CAU_AESIC_CA_CA4_MASK)
+#define CAU_AESIC_CA_CA4 CAU_AESIC_CA_CA4_MASK
 #define CAU_AESIC_CA_CA5_MASK                    (0xFFFFFFFFU)
 #define CAU_AESIC_CA_CA5_SHIFT                   (0U)
-#define CAU_AESIC_CA_CA5(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA5_SHIFT)) & CAU_AESIC_CA_CA5_MASK)
+#define CAU_AESIC_CA_CA5_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA5_SHIFT)) & CAU_AESIC_CA_CA5_MASK)
+#define CAU_AESIC_CA_CA5 CAU_AESIC_CA_CA5_MASK
 #define CAU_AESIC_CA_CA6_MASK                    (0xFFFFFFFFU)
 #define CAU_AESIC_CA_CA6_SHIFT                   (0U)
-#define CAU_AESIC_CA_CA6(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA6_SHIFT)) & CAU_AESIC_CA_CA6_MASK)
+#define CAU_AESIC_CA_CA6_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA6_SHIFT)) & CAU_AESIC_CA_CA6_MASK)
+#define CAU_AESIC_CA_CA6 CAU_AESIC_CA_CA6_MASK
 #define CAU_AESIC_CA_CA7_MASK                    (0xFFFFFFFFU)
 #define CAU_AESIC_CA_CA7_SHIFT                   (0U)
-#define CAU_AESIC_CA_CA7(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA7_SHIFT)) & CAU_AESIC_CA_CA7_MASK)
+#define CAU_AESIC_CA_CA7_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA7_SHIFT)) & CAU_AESIC_CA_CA7_MASK)
+#define CAU_AESIC_CA_CA7 CAU_AESIC_CA_CA7_MASK
 #define CAU_AESIC_CA_CA8_MASK                    (0xFFFFFFFFU)
 #define CAU_AESIC_CA_CA8_SHIFT                   (0U)
-#define CAU_AESIC_CA_CA8(x)                      (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA8_SHIFT)) & CAU_AESIC_CA_CA8_MASK)
+#define CAU_AESIC_CA_CA8_SET(x)                  (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA8_SHIFT)) & CAU_AESIC_CA_CA8_MASK)
+#define CAU_AESIC_CA_CA8 CAU_AESIC_CA_CA8_MASK
 
 /* The count of CAU_AESIC_CA */
 #define CAU_AESIC_CA_COUNT                       (9U)
@@ -3103,7 +3806,7 @@ typedef struct {
 /** Peripheral CAU base address */
 #define CAU_BASE                                 (0xE0081000u)
 /** Peripheral CAU base pointer */
-#define CAU                                      ((CAU_Type *)CAU_BASE)
+#define CAU                                      ((CAU_TypeDef *)CAU_BASE)
 /** Array initializer of CAU peripheral base addresses */
 #define CAU_BASE_ADDRS                           { CAU_BASE }
 /** Array initializer of CAU peripheral base pointers */
@@ -3131,7 +3834,7 @@ typedef struct {
   __IO uint8_t SCR;                                /**< CMP Status and Control Register, offset: 0x3 */
   __IO uint8_t DACCR;                              /**< DAC Control Register, offset: 0x4 */
   __IO uint8_t MUXCR;                              /**< MUX Control Register, offset: 0x5 */
-} CMP_Type;
+} CMP_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- CMP Register Masks
@@ -3145,83 +3848,106 @@ typedef struct {
 /*! @name CR0 - CMP Control Register 0 */
 #define CMP_CR0_HYSTCTR_MASK                     (0x3U)
 #define CMP_CR0_HYSTCTR_SHIFT                    (0U)
-#define CMP_CR0_HYSTCTR(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_HYSTCTR_SET(x)                   (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
+#define CMP_CR0_HYSTCTR CMP_CR0_HYSTCTR_MASK
 #define CMP_CR0_FILTER_CNT_MASK                  (0x70U)
 #define CMP_CR0_FILTER_CNT_SHIFT                 (4U)
-#define CMP_CR0_FILTER_CNT(x)                    (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
+#define CMP_CR0_FILTER_CNT_SET(x)                (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
+#define CMP_CR0_FILTER_CNT CMP_CR0_FILTER_CNT_MASK
 
 /*! @name CR1 - CMP Control Register 1 */
 #define CMP_CR1_EN_MASK                          (0x1U)
 #define CMP_CR1_EN_SHIFT                         (0U)
-#define CMP_CR1_EN(x)                            (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
+#define CMP_CR1_EN_SET(x)                        (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
+#define CMP_CR1_EN CMP_CR1_EN_MASK
 #define CMP_CR1_OPE_MASK                         (0x2U)
 #define CMP_CR1_OPE_SHIFT                        (1U)
-#define CMP_CR1_OPE(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
+#define CMP_CR1_OPE_SET(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
+#define CMP_CR1_OPE CMP_CR1_OPE_MASK
 #define CMP_CR1_COS_MASK                         (0x4U)
 #define CMP_CR1_COS_SHIFT                        (2U)
-#define CMP_CR1_COS(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
+#define CMP_CR1_COS_SET(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
+#define CMP_CR1_COS CMP_CR1_COS_MASK
 #define CMP_CR1_INV_MASK                         (0x8U)
 #define CMP_CR1_INV_SHIFT                        (3U)
-#define CMP_CR1_INV(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
+#define CMP_CR1_INV_SET(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
+#define CMP_CR1_INV CMP_CR1_INV_MASK
 #define CMP_CR1_PMODE_MASK                       (0x10U)
 #define CMP_CR1_PMODE_SHIFT                      (4U)
-#define CMP_CR1_PMODE(x)                         (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
+#define CMP_CR1_PMODE_SET(x)                     (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
+#define CMP_CR1_PMODE CMP_CR1_PMODE_MASK
 #define CMP_CR1_TRIGM_MASK                       (0x20U)
 #define CMP_CR1_TRIGM_SHIFT                      (5U)
-#define CMP_CR1_TRIGM(x)                         (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
+#define CMP_CR1_TRIGM_SET(x)                     (((uint8_t)(((uint8_t)(x)) << CMP_CR1_TRIGM_SHIFT)) & CMP_CR1_TRIGM_MASK)
+#define CMP_CR1_TRIGM CMP_CR1_TRIGM_MASK
 #define CMP_CR1_WE_MASK                          (0x40U)
 #define CMP_CR1_WE_SHIFT                         (6U)
-#define CMP_CR1_WE(x)                            (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
+#define CMP_CR1_WE_SET(x)                        (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
+#define CMP_CR1_WE CMP_CR1_WE_MASK
 #define CMP_CR1_SE_MASK                          (0x80U)
 #define CMP_CR1_SE_SHIFT                         (7U)
-#define CMP_CR1_SE(x)                            (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
+#define CMP_CR1_SE_SET(x)                        (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
+#define CMP_CR1_SE CMP_CR1_SE_MASK
 
 /*! @name FPR - CMP Filter Period Register */
 #define CMP_FPR_FILT_PER_MASK                    (0xFFU)
 #define CMP_FPR_FILT_PER_SHIFT                   (0U)
-#define CMP_FPR_FILT_PER(x)                      (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
+#define CMP_FPR_FILT_PER_SET(x)                  (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
+#define CMP_FPR_FILT_PER CMP_FPR_FILT_PER_MASK
 
 /*! @name SCR - CMP Status and Control Register */
 #define CMP_SCR_COUT_MASK                        (0x1U)
 #define CMP_SCR_COUT_SHIFT                       (0U)
-#define CMP_SCR_COUT(x)                          (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
+#define CMP_SCR_COUT_SET(x)                      (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
+#define CMP_SCR_COUT CMP_SCR_COUT_MASK
 #define CMP_SCR_CFF_MASK                         (0x2U)
 #define CMP_SCR_CFF_SHIFT                        (1U)
-#define CMP_SCR_CFF(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
+#define CMP_SCR_CFF_SET(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
+#define CMP_SCR_CFF CMP_SCR_CFF_MASK
 #define CMP_SCR_CFR_MASK                         (0x4U)
 #define CMP_SCR_CFR_SHIFT                        (2U)
-#define CMP_SCR_CFR(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
+#define CMP_SCR_CFR_SET(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
+#define CMP_SCR_CFR CMP_SCR_CFR_MASK
 #define CMP_SCR_IEF_MASK                         (0x8U)
 #define CMP_SCR_IEF_SHIFT                        (3U)
-#define CMP_SCR_IEF(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
+#define CMP_SCR_IEF_SET(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
+#define CMP_SCR_IEF CMP_SCR_IEF_MASK
 #define CMP_SCR_IER_MASK                         (0x10U)
 #define CMP_SCR_IER_SHIFT                        (4U)
-#define CMP_SCR_IER(x)                           (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
+#define CMP_SCR_IER_SET(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
+#define CMP_SCR_IER CMP_SCR_IER_MASK
 #define CMP_SCR_DMAEN_MASK                       (0x40U)
 #define CMP_SCR_DMAEN_SHIFT                      (6U)
-#define CMP_SCR_DMAEN(x)                         (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
+#define CMP_SCR_DMAEN_SET(x)                     (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
+#define CMP_SCR_DMAEN CMP_SCR_DMAEN_MASK
 
 /*! @name DACCR - DAC Control Register */
 #define CMP_DACCR_VOSEL_MASK                     (0x3FU)
 #define CMP_DACCR_VOSEL_SHIFT                    (0U)
-#define CMP_DACCR_VOSEL(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VOSEL_SET(x)                   (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
+#define CMP_DACCR_VOSEL CMP_DACCR_VOSEL_MASK
 #define CMP_DACCR_VRSEL_MASK                     (0x40U)
 #define CMP_DACCR_VRSEL_SHIFT                    (6U)
-#define CMP_DACCR_VRSEL(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
+#define CMP_DACCR_VRSEL_SET(x)                   (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
+#define CMP_DACCR_VRSEL CMP_DACCR_VRSEL_MASK
 #define CMP_DACCR_DACEN_MASK                     (0x80U)
 #define CMP_DACCR_DACEN_SHIFT                    (7U)
-#define CMP_DACCR_DACEN(x)                       (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
+#define CMP_DACCR_DACEN_SET(x)                   (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
+#define CMP_DACCR_DACEN CMP_DACCR_DACEN_MASK
 
 /*! @name MUXCR - MUX Control Register */
 #define CMP_MUXCR_MSEL_MASK                      (0x7U)
 #define CMP_MUXCR_MSEL_SHIFT                     (0U)
-#define CMP_MUXCR_MSEL(x)                        (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_MSEL_SET(x)                    (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
+#define CMP_MUXCR_MSEL CMP_MUXCR_MSEL_MASK
 #define CMP_MUXCR_PSEL_MASK                      (0x38U)
 #define CMP_MUXCR_PSEL_SHIFT                     (3U)
-#define CMP_MUXCR_PSEL(x)                        (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
+#define CMP_MUXCR_PSEL_SET(x)                    (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
+#define CMP_MUXCR_PSEL CMP_MUXCR_PSEL_MASK
 #define CMP_MUXCR_PSTM_MASK                      (0x80U)
 #define CMP_MUXCR_PSTM_SHIFT                     (7U)
-#define CMP_MUXCR_PSTM(x)                        (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)
+#define CMP_MUXCR_PSTM_SET(x)                    (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)
+#define CMP_MUXCR_PSTM CMP_MUXCR_PSTM_MASK
 
 
 /*!
@@ -3233,19 +3959,19 @@ typedef struct {
 /** Peripheral CMP0 base address */
 #define CMP0_BASE                                (0x40073000u)
 /** Peripheral CMP0 base pointer */
-#define CMP0                                     ((CMP_Type *)CMP0_BASE)
+#define CMP0                                     ((CMP_TypeDef *)CMP0_BASE)
 /** Peripheral CMP1 base address */
 #define CMP1_BASE                                (0x40073008u)
 /** Peripheral CMP1 base pointer */
-#define CMP1                                     ((CMP_Type *)CMP1_BASE)
+#define CMP1                                     ((CMP_TypeDef *)CMP1_BASE)
 /** Peripheral CMP2 base address */
 #define CMP2_BASE                                (0x40073010u)
 /** Peripheral CMP2 base pointer */
-#define CMP2                                     ((CMP_Type *)CMP2_BASE)
+#define CMP2                                     ((CMP_TypeDef *)CMP2_BASE)
 /** Peripheral CMP3 base address */
 #define CMP3_BASE                                (0x40073018u)
 /** Peripheral CMP3 base pointer */
-#define CMP3                                     ((CMP_Type *)CMP3_BASE)
+#define CMP3                                     ((CMP_TypeDef *)CMP3_BASE)
 /** Array initializer of CMP peripheral base addresses */
 #define CMP_BASE_ADDRS                           { CMP0_BASE, CMP1_BASE, CMP2_BASE, CMP3_BASE }
 /** Array initializer of CMP peripheral base pointers */
@@ -3281,7 +4007,7 @@ typedef struct {
   __IO uint8_t CMD4;                               /**< CMT Modulator Data Register Space Low, offset: 0x9 */
   __IO uint8_t PPS;                                /**< CMT Primary Prescaler Register, offset: 0xA */
   __IO uint8_t DMA;                                /**< CMT Direct Memory Access Register, offset: 0xB */
-} CMT_Type;
+} CMT_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- CMT Register Masks
@@ -3295,86 +4021,106 @@ typedef struct {
 /*! @name CGH1 - CMT Carrier Generator High Data Register 1 */
 #define CMT_CGH1_PH_MASK                         (0xFFU)
 #define CMT_CGH1_PH_SHIFT                        (0U)
-#define CMT_CGH1_PH(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK)
+#define CMT_CGH1_PH_SET(x)                       (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK)
+#define CMT_CGH1_PH CMT_CGH1_PH_MASK
 
 /*! @name CGL1 - CMT Carrier Generator Low Data Register 1 */
 #define CMT_CGL1_PL_MASK                         (0xFFU)
 #define CMT_CGL1_PL_SHIFT                        (0U)
-#define CMT_CGL1_PL(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK)
+#define CMT_CGL1_PL_SET(x)                       (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK)
+#define CMT_CGL1_PL CMT_CGL1_PL_MASK
 
 /*! @name CGH2 - CMT Carrier Generator High Data Register 2 */
 #define CMT_CGH2_SH_MASK                         (0xFFU)
 #define CMT_CGH2_SH_SHIFT                        (0U)
-#define CMT_CGH2_SH(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK)
+#define CMT_CGH2_SH_SET(x)                       (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK)
+#define CMT_CGH2_SH CMT_CGH2_SH_MASK
 
 /*! @name CGL2 - CMT Carrier Generator Low Data Register 2 */
 #define CMT_CGL2_SL_MASK                         (0xFFU)
 #define CMT_CGL2_SL_SHIFT                        (0U)
-#define CMT_CGL2_SL(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK)
+#define CMT_CGL2_SL_SET(x)                       (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK)
+#define CMT_CGL2_SL CMT_CGL2_SL_MASK
 
 /*! @name OC - CMT Output Control Register */
 #define CMT_OC_IROPEN_MASK                       (0x20U)
 #define CMT_OC_IROPEN_SHIFT                      (5U)
-#define CMT_OC_IROPEN(x)                         (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK)
+#define CMT_OC_IROPEN_SET(x)                     (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK)
+#define CMT_OC_IROPEN CMT_OC_IROPEN_MASK
 #define CMT_OC_CMTPOL_MASK                       (0x40U)
 #define CMT_OC_CMTPOL_SHIFT                      (6U)
-#define CMT_OC_CMTPOL(x)                         (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK)
+#define CMT_OC_CMTPOL_SET(x)                     (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK)
+#define CMT_OC_CMTPOL CMT_OC_CMTPOL_MASK
 #define CMT_OC_IROL_MASK                         (0x80U)
 #define CMT_OC_IROL_SHIFT                        (7U)
-#define CMT_OC_IROL(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK)
+#define CMT_OC_IROL_SET(x)                       (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK)
+#define CMT_OC_IROL CMT_OC_IROL_MASK
 
 /*! @name MSC - CMT Modulator Status and Control Register */
 #define CMT_MSC_MCGEN_MASK                       (0x1U)
 #define CMT_MSC_MCGEN_SHIFT                      (0U)
-#define CMT_MSC_MCGEN(x)                         (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK)
+#define CMT_MSC_MCGEN_SET(x)                     (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK)
+#define CMT_MSC_MCGEN CMT_MSC_MCGEN_MASK
 #define CMT_MSC_EOCIE_MASK                       (0x2U)
 #define CMT_MSC_EOCIE_SHIFT                      (1U)
-#define CMT_MSC_EOCIE(x)                         (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK)
+#define CMT_MSC_EOCIE_SET(x)                     (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK)
+#define CMT_MSC_EOCIE CMT_MSC_EOCIE_MASK
 #define CMT_MSC_FSK_MASK                         (0x4U)
 #define CMT_MSC_FSK_SHIFT                        (2U)
-#define CMT_MSC_FSK(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK)
+#define CMT_MSC_FSK_SET(x)                       (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK)
+#define CMT_MSC_FSK CMT_MSC_FSK_MASK
 #define CMT_MSC_BASE_MASK                        (0x8U)
 #define CMT_MSC_BASE_SHIFT                       (3U)
-#define CMT_MSC_BASE(x)                          (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK)
+#define CMT_MSC_BASE_SET(x)                      (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK)
+#define CMT_MSC_BASE CMT_MSC_BASE_MASK
 #define CMT_MSC_EXSPC_MASK                       (0x10U)
 #define CMT_MSC_EXSPC_SHIFT                      (4U)
-#define CMT_MSC_EXSPC(x)                         (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK)
+#define CMT_MSC_EXSPC_SET(x)                     (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK)
+#define CMT_MSC_EXSPC CMT_MSC_EXSPC_MASK
 #define CMT_MSC_CMTDIV_MASK                      (0x60U)
 #define CMT_MSC_CMTDIV_SHIFT                     (5U)
-#define CMT_MSC_CMTDIV(x)                        (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK)
+#define CMT_MSC_CMTDIV_SET(x)                    (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK)
+#define CMT_MSC_CMTDIV CMT_MSC_CMTDIV_MASK
 #define CMT_MSC_EOCF_MASK                        (0x80U)
 #define CMT_MSC_EOCF_SHIFT                       (7U)
-#define CMT_MSC_EOCF(x)                          (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK)
+#define CMT_MSC_EOCF_SET(x)                      (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK)
+#define CMT_MSC_EOCF CMT_MSC_EOCF_MASK
 
 /*! @name CMD1 - CMT Modulator Data Register Mark High */
 #define CMT_CMD1_MB_MASK                         (0xFFU)
 #define CMT_CMD1_MB_SHIFT                        (0U)
-#define CMT_CMD1_MB(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK)
+#define CMT_CMD1_MB_SET(x)                       (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK)
+#define CMT_CMD1_MB CMT_CMD1_MB_MASK
 
 /*! @name CMD2 - CMT Modulator Data Register Mark Low */
 #define CMT_CMD2_MB_MASK                         (0xFFU)
 #define CMT_CMD2_MB_SHIFT                        (0U)
-#define CMT_CMD2_MB(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK)
+#define CMT_CMD2_MB_SET(x)                       (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK)
+#define CMT_CMD2_MB CMT_CMD2_MB_MASK
 
 /*! @name CMD3 - CMT Modulator Data Register Space High */
 #define CMT_CMD3_SB_MASK                         (0xFFU)
 #define CMT_CMD3_SB_SHIFT                        (0U)
-#define CMT_CMD3_SB(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK)
+#define CMT_CMD3_SB_SET(x)                       (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK)
+#define CMT_CMD3_SB CMT_CMD3_SB_MASK
 
 /*! @name CMD4 - CMT Modulator Data Register Space Low */
 #define CMT_CMD4_SB_MASK                         (0xFFU)
 #define CMT_CMD4_SB_SHIFT                        (0U)
-#define CMT_CMD4_SB(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK)
+#define CMT_CMD4_SB_SET(x)                       (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK)
+#define CMT_CMD4_SB CMT_CMD4_SB_MASK
 
 /*! @name PPS - CMT Primary Prescaler Register */
 #define CMT_PPS_PPSDIV_MASK                      (0xFU)
 #define CMT_PPS_PPSDIV_SHIFT                     (0U)
-#define CMT_PPS_PPSDIV(x)                        (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK)
+#define CMT_PPS_PPSDIV_SET(x)                    (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK)
+#define CMT_PPS_PPSDIV CMT_PPS_PPSDIV_MASK
 
 /*! @name DMA - CMT Direct Memory Access Register */
 #define CMT_DMA_DMA_MASK                         (0x1U)
 #define CMT_DMA_DMA_SHIFT                        (0U)
-#define CMT_DMA_DMA(x)                           (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK)
+#define CMT_DMA_DMA_SET(x)                       (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK)
+#define CMT_DMA_DMA CMT_DMA_DMA_MASK
 
 
 /*!
@@ -3386,7 +4132,7 @@ typedef struct {
 /** Peripheral CMT base address */
 #define CMT_BASE                                 (0x40062000u)
 /** Peripheral CMT base pointer */
-#define CMT                                      ((CMT_Type *)CMT_BASE)
+#define CMT                                      ((CMT_TypeDef *)CMT_BASE)
 /** Array initializer of CMT peripheral base addresses */
 #define CMT_BASE_ADDRS                           { CMT_BASE }
 /** Array initializer of CMT peripheral base pointers */
@@ -3443,7 +4189,7 @@ typedef struct {
       __IO uint8_t CTRLHU;                             /**< CRC_CTRLHU register., offset: 0xB */
     } CTRL_ACCESS8BIT;
   };
-} CRC_Type;
+} CRC_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- CRC Register Masks
@@ -3457,118 +4203,146 @@ typedef struct {
 /*! @name DATAL - CRC_DATAL register. */
 #define CRC_DATAL_DATAL_MASK                     (0xFFFFU)
 #define CRC_DATAL_DATAL_SHIFT                    (0U)
-#define CRC_DATAL_DATAL(x)                       (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
+#define CRC_DATAL_DATAL_SET(x)                   (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
+#define CRC_DATAL_DATAL CRC_DATAL_DATAL_MASK
 
 /*! @name DATAH - CRC_DATAH register. */
 #define CRC_DATAH_DATAH_MASK                     (0xFFFFU)
 #define CRC_DATAH_DATAH_SHIFT                    (0U)
-#define CRC_DATAH_DATAH(x)                       (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
+#define CRC_DATAH_DATAH_SET(x)                   (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
+#define CRC_DATAH_DATAH CRC_DATAH_DATAH_MASK
 
 /*! @name DATA - CRC Data register */
 #define CRC_DATA_LL_MASK                         (0xFFU)
 #define CRC_DATA_LL_SHIFT                        (0U)
-#define CRC_DATA_LL(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
+#define CRC_DATA_LL_SET(x)                       (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
+#define CRC_DATA_LL CRC_DATA_LL_MASK
 #define CRC_DATA_LU_MASK                         (0xFF00U)
 #define CRC_DATA_LU_SHIFT                        (8U)
-#define CRC_DATA_LU(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
+#define CRC_DATA_LU_SET(x)                       (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
+#define CRC_DATA_LU CRC_DATA_LU_MASK
 #define CRC_DATA_HL_MASK                         (0xFF0000U)
 #define CRC_DATA_HL_SHIFT                        (16U)
-#define CRC_DATA_HL(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
+#define CRC_DATA_HL_SET(x)                       (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
+#define CRC_DATA_HL CRC_DATA_HL_MASK
 #define CRC_DATA_HU_MASK                         (0xFF000000U)
 #define CRC_DATA_HU_SHIFT                        (24U)
-#define CRC_DATA_HU(x)                           (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
+#define CRC_DATA_HU_SET(x)                       (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
+#define CRC_DATA_HU CRC_DATA_HU_MASK
 
 /*! @name DATALL - CRC_DATALL register. */
 #define CRC_DATALL_DATALL_MASK                   (0xFFU)
 #define CRC_DATALL_DATALL_SHIFT                  (0U)
-#define CRC_DATALL_DATALL(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
+#define CRC_DATALL_DATALL_SET(x)                 (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
+#define CRC_DATALL_DATALL CRC_DATALL_DATALL_MASK
 
 /*! @name DATALU - CRC_DATALU register. */
 #define CRC_DATALU_DATALU_MASK                   (0xFFU)
 #define CRC_DATALU_DATALU_SHIFT                  (0U)
-#define CRC_DATALU_DATALU(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
+#define CRC_DATALU_DATALU_SET(x)                 (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
+#define CRC_DATALU_DATALU CRC_DATALU_DATALU_MASK
 
 /*! @name DATAHL - CRC_DATAHL register. */
 #define CRC_DATAHL_DATAHL_MASK                   (0xFFU)
 #define CRC_DATAHL_DATAHL_SHIFT                  (0U)
-#define CRC_DATAHL_DATAHL(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
+#define CRC_DATAHL_DATAHL_SET(x)                 (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
+#define CRC_DATAHL_DATAHL CRC_DATAHL_DATAHL_MASK
 
 /*! @name DATAHU - CRC_DATAHU register. */
 #define CRC_DATAHU_DATAHU_MASK                   (0xFFU)
 #define CRC_DATAHU_DATAHU_SHIFT                  (0U)
-#define CRC_DATAHU_DATAHU(x)                     (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
+#define CRC_DATAHU_DATAHU_SET(x)                 (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
+#define CRC_DATAHU_DATAHU CRC_DATAHU_DATAHU_MASK
 
 /*! @name GPOLYL - CRC_GPOLYL register. */
 #define CRC_GPOLYL_GPOLYL_MASK                   (0xFFFFU)
 #define CRC_GPOLYL_GPOLYL_SHIFT                  (0U)
-#define CRC_GPOLYL_GPOLYL(x)                     (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
+#define CRC_GPOLYL_GPOLYL_SET(x)                 (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
+#define CRC_GPOLYL_GPOLYL CRC_GPOLYL_GPOLYL_MASK
 
 /*! @name GPOLYH - CRC_GPOLYH register. */
 #define CRC_GPOLYH_GPOLYH_MASK                   (0xFFFFU)
 #define CRC_GPOLYH_GPOLYH_SHIFT                  (0U)
-#define CRC_GPOLYH_GPOLYH(x)                     (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
+#define CRC_GPOLYH_GPOLYH_SET(x)                 (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
+#define CRC_GPOLYH_GPOLYH CRC_GPOLYH_GPOLYH_MASK
 
 /*! @name GPOLY - CRC Polynomial register */
 #define CRC_GPOLY_LOW_MASK                       (0xFFFFU)
 #define CRC_GPOLY_LOW_SHIFT                      (0U)
-#define CRC_GPOLY_LOW(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
+#define CRC_GPOLY_LOW_SET(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
+#define CRC_GPOLY_LOW CRC_GPOLY_LOW_MASK
 #define CRC_GPOLY_HIGH_MASK                      (0xFFFF0000U)
 #define CRC_GPOLY_HIGH_SHIFT                     (16U)
-#define CRC_GPOLY_HIGH(x)                        (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
+#define CRC_GPOLY_HIGH_SET(x)                    (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
+#define CRC_GPOLY_HIGH CRC_GPOLY_HIGH_MASK
 
 /*! @name GPOLYLL - CRC_GPOLYLL register. */
 #define CRC_GPOLYLL_GPOLYLL_MASK                 (0xFFU)
 #define CRC_GPOLYLL_GPOLYLL_SHIFT                (0U)
-#define CRC_GPOLYLL_GPOLYLL(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
+#define CRC_GPOLYLL_GPOLYLL_SET(x)               (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
+#define CRC_GPOLYLL_GPOLYLL CRC_GPOLYLL_GPOLYLL_MASK
 
 /*! @name GPOLYLU - CRC_GPOLYLU register. */
 #define CRC_GPOLYLU_GPOLYLU_MASK                 (0xFFU)
 #define CRC_GPOLYLU_GPOLYLU_SHIFT                (0U)
-#define CRC_GPOLYLU_GPOLYLU(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
+#define CRC_GPOLYLU_GPOLYLU_SET(x)               (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
+#define CRC_GPOLYLU_GPOLYLU CRC_GPOLYLU_GPOLYLU_MASK
 
 /*! @name GPOLYHL - CRC_GPOLYHL register. */
 #define CRC_GPOLYHL_GPOLYHL_MASK                 (0xFFU)
 #define CRC_GPOLYHL_GPOLYHL_SHIFT                (0U)
-#define CRC_GPOLYHL_GPOLYHL(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
+#define CRC_GPOLYHL_GPOLYHL_SET(x)               (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
+#define CRC_GPOLYHL_GPOLYHL CRC_GPOLYHL_GPOLYHL_MASK
 
 /*! @name GPOLYHU - CRC_GPOLYHU register. */
 #define CRC_GPOLYHU_GPOLYHU_MASK                 (0xFFU)
 #define CRC_GPOLYHU_GPOLYHU_SHIFT                (0U)
-#define CRC_GPOLYHU_GPOLYHU(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
+#define CRC_GPOLYHU_GPOLYHU_SET(x)               (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
+#define CRC_GPOLYHU_GPOLYHU CRC_GPOLYHU_GPOLYHU_MASK
 
 /*! @name CTRL - CRC Control register */
 #define CRC_CTRL_TCRC_MASK                       (0x1000000U)
 #define CRC_CTRL_TCRC_SHIFT                      (24U)
-#define CRC_CTRL_TCRC(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
+#define CRC_CTRL_TCRC_SET(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
+#define CRC_CTRL_TCRC CRC_CTRL_TCRC_MASK
 #define CRC_CTRL_WAS_MASK                        (0x2000000U)
 #define CRC_CTRL_WAS_SHIFT                       (25U)
-#define CRC_CTRL_WAS(x)                          (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
+#define CRC_CTRL_WAS_SET(x)                      (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
+#define CRC_CTRL_WAS CRC_CTRL_WAS_MASK
 #define CRC_CTRL_FXOR_MASK                       (0x4000000U)
 #define CRC_CTRL_FXOR_SHIFT                      (26U)
-#define CRC_CTRL_FXOR(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
+#define CRC_CTRL_FXOR_SET(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
+#define CRC_CTRL_FXOR CRC_CTRL_FXOR_MASK
 #define CRC_CTRL_TOTR_MASK                       (0x30000000U)
 #define CRC_CTRL_TOTR_SHIFT                      (28U)
-#define CRC_CTRL_TOTR(x)                         (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
+#define CRC_CTRL_TOTR_SET(x)                     (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
+#define CRC_CTRL_TOTR CRC_CTRL_TOTR_MASK
 #define CRC_CTRL_TOT_MASK                        (0xC0000000U)
 #define CRC_CTRL_TOT_SHIFT                       (30U)
-#define CRC_CTRL_TOT(x)                          (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
+#define CRC_CTRL_TOT_SET(x)                      (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
+#define CRC_CTRL_TOT CRC_CTRL_TOT_MASK
 
 /*! @name CTRLHU - CRC_CTRLHU register. */
 #define CRC_CTRLHU_TCRC_MASK                     (0x1U)
 #define CRC_CTRLHU_TCRC_SHIFT                    (0U)
-#define CRC_CTRLHU_TCRC(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
+#define CRC_CTRLHU_TCRC_SET(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
+#define CRC_CTRLHU_TCRC CRC_CTRLHU_TCRC_MASK
 #define CRC_CTRLHU_WAS_MASK                      (0x2U)
 #define CRC_CTRLHU_WAS_SHIFT                     (1U)
-#define CRC_CTRLHU_WAS(x)                        (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
+#define CRC_CTRLHU_WAS_SET(x)                    (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
+#define CRC_CTRLHU_WAS CRC_CTRLHU_WAS_MASK
 #define CRC_CTRLHU_FXOR_MASK                     (0x4U)
 #define CRC_CTRLHU_FXOR_SHIFT                    (2U)
-#define CRC_CTRLHU_FXOR(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
+#define CRC_CTRLHU_FXOR_SET(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
+#define CRC_CTRLHU_FXOR CRC_CTRLHU_FXOR_MASK
 #define CRC_CTRLHU_TOTR_MASK                     (0x30U)
 #define CRC_CTRLHU_TOTR_SHIFT                    (4U)
-#define CRC_CTRLHU_TOTR(x)                       (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
+#define CRC_CTRLHU_TOTR_SET(x)                   (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
+#define CRC_CTRLHU_TOTR CRC_CTRLHU_TOTR_MASK
 #define CRC_CTRLHU_TOT_MASK                      (0xC0U)
 #define CRC_CTRLHU_TOT_SHIFT                     (6U)
-#define CRC_CTRLHU_TOT(x)                        (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
+#define CRC_CTRLHU_TOT_SET(x)                    (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
+#define CRC_CTRLHU_TOT CRC_CTRLHU_TOT_MASK
 
 
 /*!
@@ -3580,7 +4354,7 @@ typedef struct {
 /** Peripheral CRC base address */
 #define CRC_BASE                                 (0x40032000u)
 /** Peripheral CRC base pointer */
-#define CRC0                                     ((CRC_Type *)CRC_BASE)
+#define CRC0                                     ((CRC_TypeDef *)CRC_BASE)
 /** Array initializer of CRC peripheral base addresses */
 #define CRC_BASE_ADDRS                           { CRC_BASE }
 /** Array initializer of CRC peripheral base pointers */
@@ -3610,7 +4384,7 @@ typedef struct {
   __IO uint8_t C0;                                 /**< DAC Control Register, offset: 0x21 */
   __IO uint8_t C1;                                 /**< DAC Control Register 1, offset: 0x22 */
   __IO uint8_t C2;                                 /**< DAC Control Register 2, offset: 0x23 */
-} DAC_Type;
+} DAC_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- DAC Register Masks
@@ -3624,7 +4398,8 @@ typedef struct {
 /*! @name DATL - DAC Data Low Register */
 #define DAC_DATL_DATA0_MASK                      (0xFFU)
 #define DAC_DATL_DATA0_SHIFT                     (0U)
-#define DAC_DATL_DATA0(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
+#define DAC_DATL_DATA0_SET(x)                    (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
+#define DAC_DATL_DATA0 DAC_DATL_DATA0_MASK
 
 /* The count of DAC_DATL */
 #define DAC_DATL_COUNT                           (16U)
@@ -3632,7 +4407,8 @@ typedef struct {
 /*! @name DATH - DAC Data High Register */
 #define DAC_DATH_DATA1_MASK                      (0xFU)
 #define DAC_DATH_DATA1_SHIFT                     (0U)
-#define DAC_DATH_DATA1(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
+#define DAC_DATH_DATA1_SET(x)                    (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
+#define DAC_DATH_DATA1 DAC_DATH_DATA1_MASK
 
 /* The count of DAC_DATH */
 #define DAC_DATH_COUNT                           (16U)
@@ -3640,61 +4416,74 @@ typedef struct {
 /*! @name SR - DAC Status Register */
 #define DAC_SR_DACBFRPBF_MASK                    (0x1U)
 #define DAC_SR_DACBFRPBF_SHIFT                   (0U)
-#define DAC_SR_DACBFRPBF(x)                      (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
+#define DAC_SR_DACBFRPBF_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
+#define DAC_SR_DACBFRPBF DAC_SR_DACBFRPBF_MASK
 #define DAC_SR_DACBFRPTF_MASK                    (0x2U)
 #define DAC_SR_DACBFRPTF_SHIFT                   (1U)
-#define DAC_SR_DACBFRPTF(x)                      (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
+#define DAC_SR_DACBFRPTF_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
+#define DAC_SR_DACBFRPTF DAC_SR_DACBFRPTF_MASK
 #define DAC_SR_DACBFWMF_MASK                     (0x4U)
 #define DAC_SR_DACBFWMF_SHIFT                    (2U)
-#define DAC_SR_DACBFWMF(x)                       (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK)
+#define DAC_SR_DACBFWMF_SET(x)                   (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK)
+#define DAC_SR_DACBFWMF DAC_SR_DACBFWMF_MASK
 
 /*! @name C0 - DAC Control Register */
 #define DAC_C0_DACBBIEN_MASK                     (0x1U)
 #define DAC_C0_DACBBIEN_SHIFT                    (0U)
-#define DAC_C0_DACBBIEN(x)                       (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
+#define DAC_C0_DACBBIEN_SET(x)                   (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
+#define DAC_C0_DACBBIEN DAC_C0_DACBBIEN_MASK
 #define DAC_C0_DACBTIEN_MASK                     (0x2U)
 #define DAC_C0_DACBTIEN_SHIFT                    (1U)
-#define DAC_C0_DACBTIEN(x)                       (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
+#define DAC_C0_DACBTIEN_SET(x)                   (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
+#define DAC_C0_DACBTIEN DAC_C0_DACBTIEN_MASK
 #define DAC_C0_DACBWIEN_MASK                     (0x4U)
 #define DAC_C0_DACBWIEN_SHIFT                    (2U)
-#define DAC_C0_DACBWIEN(x)                       (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK)
+#define DAC_C0_DACBWIEN_SET(x)                   (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK)
+#define DAC_C0_DACBWIEN DAC_C0_DACBWIEN_MASK
 #define DAC_C0_LPEN_MASK                         (0x8U)
 #define DAC_C0_LPEN_SHIFT                        (3U)
-#define DAC_C0_LPEN(x)                           (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
+#define DAC_C0_LPEN_SET(x)                       (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
+#define DAC_C0_LPEN DAC_C0_LPEN_MASK
 #define DAC_C0_DACSWTRG_MASK                     (0x10U)
 #define DAC_C0_DACSWTRG_SHIFT                    (4U)
-#define DAC_C0_DACSWTRG(x)                       (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
+#define DAC_C0_DACSWTRG_SET(x)                   (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
+#define DAC_C0_DACSWTRG DAC_C0_DACSWTRG_MASK
 #define DAC_C0_DACTRGSEL_MASK                    (0x20U)
 #define DAC_C0_DACTRGSEL_SHIFT                   (5U)
-#define DAC_C0_DACTRGSEL(x)                      (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
+#define DAC_C0_DACTRGSEL_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
+#define DAC_C0_DACTRGSEL DAC_C0_DACTRGSEL_MASK
 #define DAC_C0_DACRFS_MASK                       (0x40U)
 #define DAC_C0_DACRFS_SHIFT                      (6U)
-#define DAC_C0_DACRFS(x)                         (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
+#define DAC_C0_DACRFS_SET(x)                     (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
+#define DAC_C0_DACRFS DAC_C0_DACRFS_MASK
 #define DAC_C0_DACEN_MASK                        (0x80U)
 #define DAC_C0_DACEN_SHIFT                       (7U)
-#define DAC_C0_DACEN(x)                          (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
+#define DAC_C0_DACEN_SET(x)                      (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
+#define DAC_C0_DACEN DAC_C0_DACEN_MASK
 
 /*! @name C1 - DAC Control Register 1 */
 #define DAC_C1_DACBFEN_MASK                      (0x1U)
 #define DAC_C1_DACBFEN_SHIFT                     (0U)
-#define DAC_C1_DACBFEN(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
+#define DAC_C1_DACBFEN_SET(x)                    (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
+#define DAC_C1_DACBFEN DAC_C1_DACBFEN_MASK
 #define DAC_C1_DACBFMD_MASK                      (0x6U)
 #define DAC_C1_DACBFMD_SHIFT                     (1U)
-#define DAC_C1_DACBFMD(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
+#define DAC_C1_DACBFMD(x)                    (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
 #define DAC_C1_DACBFWM_MASK                      (0x18U)
 #define DAC_C1_DACBFWM_SHIFT                     (3U)
-#define DAC_C1_DACBFWM(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK)
+#define DAC_C1_DACBFWM(x)                    (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK)
 #define DAC_C1_DMAEN_MASK                        (0x80U)
 #define DAC_C1_DMAEN_SHIFT                       (7U)
-#define DAC_C1_DMAEN(x)                          (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
+#define DAC_C1_DMAEN_SET(x)                      (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
+#define DAC_C1_DMAEN DAC_C1_DMAEN_MASK
 
 /*! @name C2 - DAC Control Register 2 */
 #define DAC_C2_DACBFUP_MASK                      (0xFU)
 #define DAC_C2_DACBFUP_SHIFT                     (0U)
-#define DAC_C2_DACBFUP(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
+#define DAC_C2_DACBFUP(x)                    (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
 #define DAC_C2_DACBFRP_MASK                      (0xF0U)
 #define DAC_C2_DACBFRP_SHIFT                     (4U)
-#define DAC_C2_DACBFRP(x)                        (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
+#define DAC_C2_DACBFRP(x)                    (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
 
 
 /*!
@@ -3706,11 +4495,11 @@ typedef struct {
 /** Peripheral DAC0 base address */
 #define DAC0_BASE                                (0x400CC000u)
 /** Peripheral DAC0 base pointer */
-#define DAC0                                     ((DAC_Type *)DAC0_BASE)
+#define DAC0                                     ((DAC_TypeDef *)DAC0_BASE)
 /** Peripheral DAC1 base address */
 #define DAC1_BASE                                (0x400CD000u)
 /** Peripheral DAC1 base pointer */
-#define DAC1                                     ((DAC_Type *)DAC1_BASE)
+#define DAC1                                     ((DAC_TypeDef *)DAC1_BASE)
 /** Array initializer of DAC peripheral base addresses */
 #define DAC_BASE_ADDRS                           { DAC0_BASE, DAC1_BASE }
 /** Array initializer of DAC peripheral base pointers */
@@ -3806,14 +4595,14 @@ typedef struct {
       __IO uint16_t CITER_ELINKNO;                     /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
       __IO uint16_t CITER_ELINKYES;                    /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
     };
-    __IO uint32_t DLAST_SGA;                         /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
+    __IO uint32_t DLASTSGA;                         /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
     __IO uint16_t CSR;                               /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
     union {                                          /* offset: 0x101E, array step: 0x20 */
       __IO uint16_t BITER_ELINKNO;                     /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
       __IO uint16_t BITER_ELINKYES;                    /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
     };
   } TCD[32];
-} DMA_Type;
+} DMA_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- DMA Register Masks
@@ -3827,1207 +4616,1576 @@ typedef struct {
 /*! @name CR - Control Register */
 #define DMA_CR_EDBG_MASK                         (0x2U)
 #define DMA_CR_EDBG_SHIFT                        (1U)
-#define DMA_CR_EDBG(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
+#define DMA_CR_EDBG_SET(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
+#define DMA_CR_EDBG DMA_CR_EDBG_MASK
 #define DMA_CR_ERCA_MASK                         (0x4U)
 #define DMA_CR_ERCA_SHIFT                        (2U)
-#define DMA_CR_ERCA(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
+#define DMA_CR_ERCA_SET(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
+#define DMA_CR_ERCA DMA_CR_ERCA_MASK
 #define DMA_CR_ERGA_MASK                         (0x8U)
 #define DMA_CR_ERGA_SHIFT                        (3U)
-#define DMA_CR_ERGA(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)
+#define DMA_CR_ERGA_SET(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)
+#define DMA_CR_ERGA DMA_CR_ERGA_MASK
 #define DMA_CR_HOE_MASK                          (0x10U)
 #define DMA_CR_HOE_SHIFT                         (4U)
-#define DMA_CR_HOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
+#define DMA_CR_HOE_SET(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
+#define DMA_CR_HOE DMA_CR_HOE_MASK
 #define DMA_CR_HALT_MASK                         (0x20U)
 #define DMA_CR_HALT_SHIFT                        (5U)
-#define DMA_CR_HALT(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
+#define DMA_CR_HALT_SET(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
+#define DMA_CR_HALT DMA_CR_HALT_MASK
 #define DMA_CR_CLM_MASK                          (0x40U)
 #define DMA_CR_CLM_SHIFT                         (6U)
-#define DMA_CR_CLM(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
+#define DMA_CR_CLM_SET(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
+#define DMA_CR_CLM DMA_CR_CLM_MASK
 #define DMA_CR_EMLM_MASK                         (0x80U)
 #define DMA_CR_EMLM_SHIFT                        (7U)
-#define DMA_CR_EMLM(x)                           (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
+#define DMA_CR_EMLM_SET(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
+#define DMA_CR_EMLM DMA_CR_EMLM_MASK
 #define DMA_CR_GRP0PRI_MASK                      (0x100U)
 #define DMA_CR_GRP0PRI_SHIFT                     (8U)
-#define DMA_CR_GRP0PRI(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)
+#define DMA_CR_GRP0PRI_SET(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)
+#define DMA_CR_GRP0PRI DMA_CR_GRP0PRI_MASK
 #define DMA_CR_GRP1PRI_MASK                      (0x400U)
 #define DMA_CR_GRP1PRI_SHIFT                     (10U)
-#define DMA_CR_GRP1PRI(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)
+#define DMA_CR_GRP1PRI_SET(x)                    (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)
+#define DMA_CR_GRP1PRI DMA_CR_GRP1PRI_MASK
 #define DMA_CR_ECX_MASK                          (0x10000U)
 #define DMA_CR_ECX_SHIFT                         (16U)
-#define DMA_CR_ECX(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
+#define DMA_CR_ECX_SET(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
+#define DMA_CR_ECX DMA_CR_ECX_MASK
 #define DMA_CR_CX_MASK                           (0x20000U)
 #define DMA_CR_CX_SHIFT                          (17U)
-#define DMA_CR_CX(x)                             (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
+#define DMA_CR_CX_SET(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
+#define DMA_CR_CX DMA_CR_CX_MASK
 
 /*! @name ES - Error Status Register */
 #define DMA_ES_DBE_MASK                          (0x1U)
 #define DMA_ES_DBE_SHIFT                         (0U)
-#define DMA_ES_DBE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
+#define DMA_ES_DBE_SET(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
+#define DMA_ES_DBE DMA_ES_DBE_MASK
 #define DMA_ES_SBE_MASK                          (0x2U)
 #define DMA_ES_SBE_SHIFT                         (1U)
-#define DMA_ES_SBE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
+#define DMA_ES_SBE_SET(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
+#define DMA_ES_SBE DMA_ES_SBE_MASK
 #define DMA_ES_SGE_MASK                          (0x4U)
 #define DMA_ES_SGE_SHIFT                         (2U)
-#define DMA_ES_SGE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
+#define DMA_ES_SGE_SET(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
+#define DMA_ES_SGE DMA_ES_SGE_MASK
 #define DMA_ES_NCE_MASK                          (0x8U)
 #define DMA_ES_NCE_SHIFT                         (3U)
-#define DMA_ES_NCE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
+#define DMA_ES_NCE_SET(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
+#define DMA_ES_NCE DMA_ES_NCE_MASK
 #define DMA_ES_DOE_MASK                          (0x10U)
 #define DMA_ES_DOE_SHIFT                         (4U)
-#define DMA_ES_DOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
+#define DMA_ES_DOE_SET(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
+#define DMA_ES_DOE DMA_ES_DOE_MASK
 #define DMA_ES_DAE_MASK                          (0x20U)
 #define DMA_ES_DAE_SHIFT                         (5U)
-#define DMA_ES_DAE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
+#define DMA_ES_DAE_SET(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
+#define DMA_ES_DAE DMA_ES_DAE_MASK
 #define DMA_ES_SOE_MASK                          (0x40U)
 #define DMA_ES_SOE_SHIFT                         (6U)
-#define DMA_ES_SOE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
+#define DMA_ES_SOE_SET(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
+#define DMA_ES_SOE DMA_ES_SOE_MASK
 #define DMA_ES_SAE_MASK                          (0x80U)
 #define DMA_ES_SAE_SHIFT                         (7U)
-#define DMA_ES_SAE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
+#define DMA_ES_SAE_SET(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
+#define DMA_ES_SAE DMA_ES_SAE_MASK
 #define DMA_ES_ERRCHN_MASK                       (0x1F00U)
 #define DMA_ES_ERRCHN_SHIFT                      (8U)
-#define DMA_ES_ERRCHN(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
+#define DMA_ES_ERRCHN_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
+#define DMA_ES_ERRCHN DMA_ES_ERRCHN_MASK
 #define DMA_ES_CPE_MASK                          (0x4000U)
 #define DMA_ES_CPE_SHIFT                         (14U)
-#define DMA_ES_CPE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
+#define DMA_ES_CPE_SET(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
+#define DMA_ES_CPE DMA_ES_CPE_MASK
 #define DMA_ES_GPE_MASK                          (0x8000U)
 #define DMA_ES_GPE_SHIFT                         (15U)
-#define DMA_ES_GPE(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)
+#define DMA_ES_GPE_SET(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)
+#define DMA_ES_GPE DMA_ES_GPE_MASK
 #define DMA_ES_ECX_MASK                          (0x10000U)
 #define DMA_ES_ECX_SHIFT                         (16U)
-#define DMA_ES_ECX(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
+#define DMA_ES_ECX_SET(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
+#define DMA_ES_ECX DMA_ES_ECX_MASK
 #define DMA_ES_VLD_MASK                          (0x80000000U)
 #define DMA_ES_VLD_SHIFT                         (31U)
-#define DMA_ES_VLD(x)                            (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
+#define DMA_ES_VLD_SET(x)                        (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
+#define DMA_ES_VLD DMA_ES_VLD_MASK
 
 /*! @name ERQ - Enable Request Register */
 #define DMA_ERQ_ERQ0_MASK                        (0x1U)
 #define DMA_ERQ_ERQ0_SHIFT                       (0U)
-#define DMA_ERQ_ERQ0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
+#define DMA_ERQ_ERQ0_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
+#define DMA_ERQ_ERQ0 DMA_ERQ_ERQ0_MASK
 #define DMA_ERQ_ERQ1_MASK                        (0x2U)
 #define DMA_ERQ_ERQ1_SHIFT                       (1U)
-#define DMA_ERQ_ERQ1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
+#define DMA_ERQ_ERQ1_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
+#define DMA_ERQ_ERQ1 DMA_ERQ_ERQ1_MASK
 #define DMA_ERQ_ERQ2_MASK                        (0x4U)
 #define DMA_ERQ_ERQ2_SHIFT                       (2U)
-#define DMA_ERQ_ERQ2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
+#define DMA_ERQ_ERQ2_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
+#define DMA_ERQ_ERQ2 DMA_ERQ_ERQ2_MASK
 #define DMA_ERQ_ERQ3_MASK                        (0x8U)
 #define DMA_ERQ_ERQ3_SHIFT                       (3U)
-#define DMA_ERQ_ERQ3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
+#define DMA_ERQ_ERQ3_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
+#define DMA_ERQ_ERQ3 DMA_ERQ_ERQ3_MASK
 #define DMA_ERQ_ERQ4_MASK                        (0x10U)
 #define DMA_ERQ_ERQ4_SHIFT                       (4U)
-#define DMA_ERQ_ERQ4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
+#define DMA_ERQ_ERQ4_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
+#define DMA_ERQ_ERQ4 DMA_ERQ_ERQ4_MASK
 #define DMA_ERQ_ERQ5_MASK                        (0x20U)
 #define DMA_ERQ_ERQ5_SHIFT                       (5U)
-#define DMA_ERQ_ERQ5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
+#define DMA_ERQ_ERQ5_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
+#define DMA_ERQ_ERQ5 DMA_ERQ_ERQ5_MASK
 #define DMA_ERQ_ERQ6_MASK                        (0x40U)
 #define DMA_ERQ_ERQ6_SHIFT                       (6U)
-#define DMA_ERQ_ERQ6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
+#define DMA_ERQ_ERQ6_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
+#define DMA_ERQ_ERQ6 DMA_ERQ_ERQ6_MASK
 #define DMA_ERQ_ERQ7_MASK                        (0x80U)
 #define DMA_ERQ_ERQ7_SHIFT                       (7U)
-#define DMA_ERQ_ERQ7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
+#define DMA_ERQ_ERQ7_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
+#define DMA_ERQ_ERQ7 DMA_ERQ_ERQ7_MASK
 #define DMA_ERQ_ERQ8_MASK                        (0x100U)
 #define DMA_ERQ_ERQ8_SHIFT                       (8U)
-#define DMA_ERQ_ERQ8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
+#define DMA_ERQ_ERQ8_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
+#define DMA_ERQ_ERQ8 DMA_ERQ_ERQ8_MASK
 #define DMA_ERQ_ERQ9_MASK                        (0x200U)
 #define DMA_ERQ_ERQ9_SHIFT                       (9U)
-#define DMA_ERQ_ERQ9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
+#define DMA_ERQ_ERQ9_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
+#define DMA_ERQ_ERQ9 DMA_ERQ_ERQ9_MASK
 #define DMA_ERQ_ERQ10_MASK                       (0x400U)
 #define DMA_ERQ_ERQ10_SHIFT                      (10U)
-#define DMA_ERQ_ERQ10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
+#define DMA_ERQ_ERQ10_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
+#define DMA_ERQ_ERQ10 DMA_ERQ_ERQ10_MASK
 #define DMA_ERQ_ERQ11_MASK                       (0x800U)
 #define DMA_ERQ_ERQ11_SHIFT                      (11U)
-#define DMA_ERQ_ERQ11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
+#define DMA_ERQ_ERQ11_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
+#define DMA_ERQ_ERQ11 DMA_ERQ_ERQ11_MASK
 #define DMA_ERQ_ERQ12_MASK                       (0x1000U)
 #define DMA_ERQ_ERQ12_SHIFT                      (12U)
-#define DMA_ERQ_ERQ12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
+#define DMA_ERQ_ERQ12_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
+#define DMA_ERQ_ERQ12 DMA_ERQ_ERQ12_MASK
 #define DMA_ERQ_ERQ13_MASK                       (0x2000U)
 #define DMA_ERQ_ERQ13_SHIFT                      (13U)
-#define DMA_ERQ_ERQ13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
+#define DMA_ERQ_ERQ13_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
+#define DMA_ERQ_ERQ13 DMA_ERQ_ERQ13_MASK
 #define DMA_ERQ_ERQ14_MASK                       (0x4000U)
 #define DMA_ERQ_ERQ14_SHIFT                      (14U)
-#define DMA_ERQ_ERQ14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
+#define DMA_ERQ_ERQ14_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
+#define DMA_ERQ_ERQ14 DMA_ERQ_ERQ14_MASK
 #define DMA_ERQ_ERQ15_MASK                       (0x8000U)
 #define DMA_ERQ_ERQ15_SHIFT                      (15U)
-#define DMA_ERQ_ERQ15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
+#define DMA_ERQ_ERQ15_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
+#define DMA_ERQ_ERQ15 DMA_ERQ_ERQ15_MASK
 #define DMA_ERQ_ERQ16_MASK                       (0x10000U)
 #define DMA_ERQ_ERQ16_SHIFT                      (16U)
-#define DMA_ERQ_ERQ16(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)
+#define DMA_ERQ_ERQ16_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)
+#define DMA_ERQ_ERQ16 DMA_ERQ_ERQ16_MASK
 #define DMA_ERQ_ERQ17_MASK                       (0x20000U)
 #define DMA_ERQ_ERQ17_SHIFT                      (17U)
-#define DMA_ERQ_ERQ17(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)
+#define DMA_ERQ_ERQ17_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)
+#define DMA_ERQ_ERQ17 DMA_ERQ_ERQ17_MASK
 #define DMA_ERQ_ERQ18_MASK                       (0x40000U)
 #define DMA_ERQ_ERQ18_SHIFT                      (18U)
-#define DMA_ERQ_ERQ18(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)
+#define DMA_ERQ_ERQ18_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)
+#define DMA_ERQ_ERQ18 DMA_ERQ_ERQ18_MASK
 #define DMA_ERQ_ERQ19_MASK                       (0x80000U)
 #define DMA_ERQ_ERQ19_SHIFT                      (19U)
-#define DMA_ERQ_ERQ19(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)
+#define DMA_ERQ_ERQ19_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)
+#define DMA_ERQ_ERQ19 DMA_ERQ_ERQ19_MASK
 #define DMA_ERQ_ERQ20_MASK                       (0x100000U)
 #define DMA_ERQ_ERQ20_SHIFT                      (20U)
-#define DMA_ERQ_ERQ20(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)
+#define DMA_ERQ_ERQ20_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)
+#define DMA_ERQ_ERQ20 DMA_ERQ_ERQ20_MASK
 #define DMA_ERQ_ERQ21_MASK                       (0x200000U)
 #define DMA_ERQ_ERQ21_SHIFT                      (21U)
-#define DMA_ERQ_ERQ21(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)
+#define DMA_ERQ_ERQ21_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)
+#define DMA_ERQ_ERQ21 DMA_ERQ_ERQ21_MASK
 #define DMA_ERQ_ERQ22_MASK                       (0x400000U)
 #define DMA_ERQ_ERQ22_SHIFT                      (22U)
-#define DMA_ERQ_ERQ22(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)
+#define DMA_ERQ_ERQ22_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)
+#define DMA_ERQ_ERQ22 DMA_ERQ_ERQ22_MASK
 #define DMA_ERQ_ERQ23_MASK                       (0x800000U)
 #define DMA_ERQ_ERQ23_SHIFT                      (23U)
-#define DMA_ERQ_ERQ23(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)
+#define DMA_ERQ_ERQ23_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)
+#define DMA_ERQ_ERQ23 DMA_ERQ_ERQ23_MASK
 #define DMA_ERQ_ERQ24_MASK                       (0x1000000U)
 #define DMA_ERQ_ERQ24_SHIFT                      (24U)
-#define DMA_ERQ_ERQ24(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)
+#define DMA_ERQ_ERQ24_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)
+#define DMA_ERQ_ERQ24 DMA_ERQ_ERQ24_MASK
 #define DMA_ERQ_ERQ25_MASK                       (0x2000000U)
 #define DMA_ERQ_ERQ25_SHIFT                      (25U)
-#define DMA_ERQ_ERQ25(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)
+#define DMA_ERQ_ERQ25_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)
+#define DMA_ERQ_ERQ25 DMA_ERQ_ERQ25_MASK
 #define DMA_ERQ_ERQ26_MASK                       (0x4000000U)
 #define DMA_ERQ_ERQ26_SHIFT                      (26U)
-#define DMA_ERQ_ERQ26(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)
+#define DMA_ERQ_ERQ26_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)
+#define DMA_ERQ_ERQ26 DMA_ERQ_ERQ26_MASK
 #define DMA_ERQ_ERQ27_MASK                       (0x8000000U)
 #define DMA_ERQ_ERQ27_SHIFT                      (27U)
-#define DMA_ERQ_ERQ27(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)
+#define DMA_ERQ_ERQ27_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)
+#define DMA_ERQ_ERQ27 DMA_ERQ_ERQ27_MASK
 #define DMA_ERQ_ERQ28_MASK                       (0x10000000U)
 #define DMA_ERQ_ERQ28_SHIFT                      (28U)
-#define DMA_ERQ_ERQ28(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)
+#define DMA_ERQ_ERQ28_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)
+#define DMA_ERQ_ERQ28 DMA_ERQ_ERQ28_MASK
 #define DMA_ERQ_ERQ29_MASK                       (0x20000000U)
 #define DMA_ERQ_ERQ29_SHIFT                      (29U)
-#define DMA_ERQ_ERQ29(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)
+#define DMA_ERQ_ERQ29_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)
+#define DMA_ERQ_ERQ29 DMA_ERQ_ERQ29_MASK
 #define DMA_ERQ_ERQ30_MASK                       (0x40000000U)
 #define DMA_ERQ_ERQ30_SHIFT                      (30U)
-#define DMA_ERQ_ERQ30(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)
+#define DMA_ERQ_ERQ30_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)
+#define DMA_ERQ_ERQ30 DMA_ERQ_ERQ30_MASK
 #define DMA_ERQ_ERQ31_MASK                       (0x80000000U)
 #define DMA_ERQ_ERQ31_SHIFT                      (31U)
-#define DMA_ERQ_ERQ31(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)
+#define DMA_ERQ_ERQ31_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)
+#define DMA_ERQ_ERQ31 DMA_ERQ_ERQ31_MASK
 
 /*! @name EEI - Enable Error Interrupt Register */
 #define DMA_EEI_EEI0_MASK                        (0x1U)
 #define DMA_EEI_EEI0_SHIFT                       (0U)
-#define DMA_EEI_EEI0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
+#define DMA_EEI_EEI0_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
+#define DMA_EEI_EEI0 DMA_EEI_EEI0_MASK
 #define DMA_EEI_EEI1_MASK                        (0x2U)
 #define DMA_EEI_EEI1_SHIFT                       (1U)
-#define DMA_EEI_EEI1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
+#define DMA_EEI_EEI1_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
+#define DMA_EEI_EEI1 DMA_EEI_EEI1_MASK
 #define DMA_EEI_EEI2_MASK                        (0x4U)
 #define DMA_EEI_EEI2_SHIFT                       (2U)
-#define DMA_EEI_EEI2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
+#define DMA_EEI_EEI2_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
+#define DMA_EEI_EEI2 DMA_EEI_EEI2_MASK
 #define DMA_EEI_EEI3_MASK                        (0x8U)
 #define DMA_EEI_EEI3_SHIFT                       (3U)
-#define DMA_EEI_EEI3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
+#define DMA_EEI_EEI3_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
+#define DMA_EEI_EEI3 DMA_EEI_EEI3_MASK
 #define DMA_EEI_EEI4_MASK                        (0x10U)
 #define DMA_EEI_EEI4_SHIFT                       (4U)
-#define DMA_EEI_EEI4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
+#define DMA_EEI_EEI4_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
+#define DMA_EEI_EEI4 DMA_EEI_EEI4_MASK
 #define DMA_EEI_EEI5_MASK                        (0x20U)
 #define DMA_EEI_EEI5_SHIFT                       (5U)
-#define DMA_EEI_EEI5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
+#define DMA_EEI_EEI5_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
+#define DMA_EEI_EEI5 DMA_EEI_EEI5_MASK
 #define DMA_EEI_EEI6_MASK                        (0x40U)
 #define DMA_EEI_EEI6_SHIFT                       (6U)
-#define DMA_EEI_EEI6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
+#define DMA_EEI_EEI6_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
+#define DMA_EEI_EEI6 DMA_EEI_EEI6_MASK
 #define DMA_EEI_EEI7_MASK                        (0x80U)
 #define DMA_EEI_EEI7_SHIFT                       (7U)
-#define DMA_EEI_EEI7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
+#define DMA_EEI_EEI7_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
+#define DMA_EEI_EEI7 DMA_EEI_EEI7_MASK
 #define DMA_EEI_EEI8_MASK                        (0x100U)
 #define DMA_EEI_EEI8_SHIFT                       (8U)
-#define DMA_EEI_EEI8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
+#define DMA_EEI_EEI8_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
+#define DMA_EEI_EEI8 DMA_EEI_EEI8_MASK
 #define DMA_EEI_EEI9_MASK                        (0x200U)
 #define DMA_EEI_EEI9_SHIFT                       (9U)
-#define DMA_EEI_EEI9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
+#define DMA_EEI_EEI9_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
+#define DMA_EEI_EEI9 DMA_EEI_EEI9_MASK
 #define DMA_EEI_EEI10_MASK                       (0x400U)
 #define DMA_EEI_EEI10_SHIFT                      (10U)
-#define DMA_EEI_EEI10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
+#define DMA_EEI_EEI10_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
+#define DMA_EEI_EEI10 DMA_EEI_EEI10_MASK
 #define DMA_EEI_EEI11_MASK                       (0x800U)
 #define DMA_EEI_EEI11_SHIFT                      (11U)
-#define DMA_EEI_EEI11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
+#define DMA_EEI_EEI11_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
+#define DMA_EEI_EEI11 DMA_EEI_EEI11_MASK
 #define DMA_EEI_EEI12_MASK                       (0x1000U)
 #define DMA_EEI_EEI12_SHIFT                      (12U)
-#define DMA_EEI_EEI12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
+#define DMA_EEI_EEI12_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
+#define DMA_EEI_EEI12 DMA_EEI_EEI12_MASK
 #define DMA_EEI_EEI13_MASK                       (0x2000U)
 #define DMA_EEI_EEI13_SHIFT                      (13U)
-#define DMA_EEI_EEI13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
+#define DMA_EEI_EEI13_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
+#define DMA_EEI_EEI13 DMA_EEI_EEI13_MASK
 #define DMA_EEI_EEI14_MASK                       (0x4000U)
 #define DMA_EEI_EEI14_SHIFT                      (14U)
-#define DMA_EEI_EEI14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
+#define DMA_EEI_EEI14_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
+#define DMA_EEI_EEI14 DMA_EEI_EEI14_MASK
 #define DMA_EEI_EEI15_MASK                       (0x8000U)
 #define DMA_EEI_EEI15_SHIFT                      (15U)
-#define DMA_EEI_EEI15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
+#define DMA_EEI_EEI15_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
+#define DMA_EEI_EEI15 DMA_EEI_EEI15_MASK
 #define DMA_EEI_EEI16_MASK                       (0x10000U)
 #define DMA_EEI_EEI16_SHIFT                      (16U)
-#define DMA_EEI_EEI16(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)
+#define DMA_EEI_EEI16_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)
+#define DMA_EEI_EEI16 DMA_EEI_EEI16_MASK
 #define DMA_EEI_EEI17_MASK                       (0x20000U)
 #define DMA_EEI_EEI17_SHIFT                      (17U)
-#define DMA_EEI_EEI17(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)
+#define DMA_EEI_EEI17_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)
+#define DMA_EEI_EEI17 DMA_EEI_EEI17_MASK
 #define DMA_EEI_EEI18_MASK                       (0x40000U)
 #define DMA_EEI_EEI18_SHIFT                      (18U)
-#define DMA_EEI_EEI18(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)
+#define DMA_EEI_EEI18_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)
+#define DMA_EEI_EEI18 DMA_EEI_EEI18_MASK
 #define DMA_EEI_EEI19_MASK                       (0x80000U)
 #define DMA_EEI_EEI19_SHIFT                      (19U)
-#define DMA_EEI_EEI19(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)
+#define DMA_EEI_EEI19_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)
+#define DMA_EEI_EEI19 DMA_EEI_EEI19_MASK
 #define DMA_EEI_EEI20_MASK                       (0x100000U)
 #define DMA_EEI_EEI20_SHIFT                      (20U)
-#define DMA_EEI_EEI20(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)
+#define DMA_EEI_EEI20_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)
+#define DMA_EEI_EEI20 DMA_EEI_EEI20_MASK
 #define DMA_EEI_EEI21_MASK                       (0x200000U)
 #define DMA_EEI_EEI21_SHIFT                      (21U)
-#define DMA_EEI_EEI21(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)
+#define DMA_EEI_EEI21_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)
+#define DMA_EEI_EEI21 DMA_EEI_EEI21_MASK
 #define DMA_EEI_EEI22_MASK                       (0x400000U)
 #define DMA_EEI_EEI22_SHIFT                      (22U)
-#define DMA_EEI_EEI22(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)
+#define DMA_EEI_EEI22_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)
+#define DMA_EEI_EEI22 DMA_EEI_EEI22_MASK
 #define DMA_EEI_EEI23_MASK                       (0x800000U)
 #define DMA_EEI_EEI23_SHIFT                      (23U)
-#define DMA_EEI_EEI23(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)
+#define DMA_EEI_EEI23_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)
+#define DMA_EEI_EEI23 DMA_EEI_EEI23_MASK
 #define DMA_EEI_EEI24_MASK                       (0x1000000U)
 #define DMA_EEI_EEI24_SHIFT                      (24U)
-#define DMA_EEI_EEI24(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)
+#define DMA_EEI_EEI24_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)
+#define DMA_EEI_EEI24 DMA_EEI_EEI24_MASK
 #define DMA_EEI_EEI25_MASK                       (0x2000000U)
 #define DMA_EEI_EEI25_SHIFT                      (25U)
-#define DMA_EEI_EEI25(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)
+#define DMA_EEI_EEI25_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)
+#define DMA_EEI_EEI25 DMA_EEI_EEI25_MASK
 #define DMA_EEI_EEI26_MASK                       (0x4000000U)
 #define DMA_EEI_EEI26_SHIFT                      (26U)
-#define DMA_EEI_EEI26(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)
+#define DMA_EEI_EEI26_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)
+#define DMA_EEI_EEI26 DMA_EEI_EEI26_MASK
 #define DMA_EEI_EEI27_MASK                       (0x8000000U)
 #define DMA_EEI_EEI27_SHIFT                      (27U)
-#define DMA_EEI_EEI27(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)
+#define DMA_EEI_EEI27_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)
+#define DMA_EEI_EEI27 DMA_EEI_EEI27_MASK
 #define DMA_EEI_EEI28_MASK                       (0x10000000U)
 #define DMA_EEI_EEI28_SHIFT                      (28U)
-#define DMA_EEI_EEI28(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)
+#define DMA_EEI_EEI28_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)
+#define DMA_EEI_EEI28 DMA_EEI_EEI28_MASK
 #define DMA_EEI_EEI29_MASK                       (0x20000000U)
 #define DMA_EEI_EEI29_SHIFT                      (29U)
-#define DMA_EEI_EEI29(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)
+#define DMA_EEI_EEI29_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)
+#define DMA_EEI_EEI29 DMA_EEI_EEI29_MASK
 #define DMA_EEI_EEI30_MASK                       (0x40000000U)
 #define DMA_EEI_EEI30_SHIFT                      (30U)
-#define DMA_EEI_EEI30(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)
+#define DMA_EEI_EEI30_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)
+#define DMA_EEI_EEI30 DMA_EEI_EEI30_MASK
 #define DMA_EEI_EEI31_MASK                       (0x80000000U)
 #define DMA_EEI_EEI31_SHIFT                      (31U)
-#define DMA_EEI_EEI31(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)
+#define DMA_EEI_EEI31_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)
+#define DMA_EEI_EEI31 DMA_EEI_EEI31_MASK
 
 /*! @name CEEI - Clear Enable Error Interrupt Register */
 #define DMA_CEEI_CEEI_MASK                       (0x1FU)
 #define DMA_CEEI_CEEI_SHIFT                      (0U)
-#define DMA_CEEI_CEEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
+#define DMA_CEEI_CEEI_SET(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
+#define DMA_CEEI_CEEI DMA_CEEI_CEEI_MASK
 #define DMA_CEEI_CAEE_MASK                       (0x40U)
 #define DMA_CEEI_CAEE_SHIFT                      (6U)
-#define DMA_CEEI_CAEE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
+#define DMA_CEEI_CAEE_SET(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
+#define DMA_CEEI_CAEE DMA_CEEI_CAEE_MASK
 #define DMA_CEEI_NOP_MASK                        (0x80U)
 #define DMA_CEEI_NOP_SHIFT                       (7U)
-#define DMA_CEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
+#define DMA_CEEI_NOP_SET(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
+#define DMA_CEEI_NOP DMA_CEEI_NOP_MASK
 
 /*! @name SEEI - Set Enable Error Interrupt Register */
 #define DMA_SEEI_SEEI_MASK                       (0x1FU)
 #define DMA_SEEI_SEEI_SHIFT                      (0U)
-#define DMA_SEEI_SEEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
+#define DMA_SEEI_SEEI_SET(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
+#define DMA_SEEI_SEEI DMA_SEEI_SEEI_MASK
 #define DMA_SEEI_SAEE_MASK                       (0x40U)
 #define DMA_SEEI_SAEE_SHIFT                      (6U)
-#define DMA_SEEI_SAEE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
+#define DMA_SEEI_SAEE_SET(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
+#define DMA_SEEI_SAEE DMA_SEEI_SAEE_MASK
 #define DMA_SEEI_NOP_MASK                        (0x80U)
 #define DMA_SEEI_NOP_SHIFT                       (7U)
-#define DMA_SEEI_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
+#define DMA_SEEI_NOP_SET(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
+#define DMA_SEEI_NOP DMA_SEEI_NOP_MASK
 
 /*! @name CERQ - Clear Enable Request Register */
 #define DMA_CERQ_CERQ_MASK                       (0x1FU)
 #define DMA_CERQ_CERQ_SHIFT                      (0U)
-#define DMA_CERQ_CERQ(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
+#define DMA_CERQ_CERQ_SET(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
+#define DMA_CERQ_CERQ DMA_CERQ_CERQ_MASK
 #define DMA_CERQ_CAER_MASK                       (0x40U)
 #define DMA_CERQ_CAER_SHIFT                      (6U)
-#define DMA_CERQ_CAER(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
+#define DMA_CERQ_CAER_SET(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
+#define DMA_CERQ_CAER DMA_CERQ_CAER_MASK
 #define DMA_CERQ_NOP_MASK                        (0x80U)
 #define DMA_CERQ_NOP_SHIFT                       (7U)
-#define DMA_CERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
+#define DMA_CERQ_NOP_SET(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
+#define DMA_CERQ_NOP DMA_CERQ_NOP_MASK
 
 /*! @name SERQ - Set Enable Request Register */
 #define DMA_SERQ_SERQ_MASK                       (0x1FU)
 #define DMA_SERQ_SERQ_SHIFT                      (0U)
-#define DMA_SERQ_SERQ(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
+#define DMA_SERQ_SERQ_SET(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
+#define DMA_SERQ_SERQ DMA_SERQ_SERQ_MASK
 #define DMA_SERQ_SAER_MASK                       (0x40U)
 #define DMA_SERQ_SAER_SHIFT                      (6U)
-#define DMA_SERQ_SAER(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
+#define DMA_SERQ_SAER_SET(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
+#define DMA_SERQ_SAER DMA_SERQ_SAER_MASK
 #define DMA_SERQ_NOP_MASK                        (0x80U)
 #define DMA_SERQ_NOP_SHIFT                       (7U)
-#define DMA_SERQ_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
+#define DMA_SERQ_NOP_SET(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
+#define DMA_SERQ_NOP DMA_SERQ_NOP_MASK
 
 /*! @name CDNE - Clear DONE Status Bit Register */
 #define DMA_CDNE_CDNE_MASK                       (0x1FU)
 #define DMA_CDNE_CDNE_SHIFT                      (0U)
-#define DMA_CDNE_CDNE(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
+#define DMA_CDNE_CDNE_SET(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
+#define DMA_CDNE_CDNE DMA_CDNE_CDNE_MASK
 #define DMA_CDNE_CADN_MASK                       (0x40U)
 #define DMA_CDNE_CADN_SHIFT                      (6U)
-#define DMA_CDNE_CADN(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
+#define DMA_CDNE_CADN_SET(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
+#define DMA_CDNE_CADN DMA_CDNE_CADN_MASK
 #define DMA_CDNE_NOP_MASK                        (0x80U)
 #define DMA_CDNE_NOP_SHIFT                       (7U)
-#define DMA_CDNE_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
+#define DMA_CDNE_NOP_SET(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
+#define DMA_CDNE_NOP DMA_CDNE_NOP_MASK
 
 /*! @name SSRT - Set START Bit Register */
 #define DMA_SSRT_SSRT_MASK                       (0x1FU)
 #define DMA_SSRT_SSRT_SHIFT                      (0U)
-#define DMA_SSRT_SSRT(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
+#define DMA_SSRT_SSRT_SET(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
+#define DMA_SSRT_SSRT DMA_SSRT_SSRT_MASK
 #define DMA_SSRT_SAST_MASK                       (0x40U)
 #define DMA_SSRT_SAST_SHIFT                      (6U)
-#define DMA_SSRT_SAST(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
+#define DMA_SSRT_SAST_SET(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
+#define DMA_SSRT_SAST DMA_SSRT_SAST_MASK
 #define DMA_SSRT_NOP_MASK                        (0x80U)
 #define DMA_SSRT_NOP_SHIFT                       (7U)
-#define DMA_SSRT_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
+#define DMA_SSRT_NOP_SET(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
+#define DMA_SSRT_NOP DMA_SSRT_NOP_MASK
 
 /*! @name CERR - Clear Error Register */
 #define DMA_CERR_CERR_MASK                       (0x1FU)
 #define DMA_CERR_CERR_SHIFT                      (0U)
-#define DMA_CERR_CERR(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
+#define DMA_CERR_CERR_SET(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
+#define DMA_CERR_CERR DMA_CERR_CERR_MASK
 #define DMA_CERR_CAEI_MASK                       (0x40U)
 #define DMA_CERR_CAEI_SHIFT                      (6U)
-#define DMA_CERR_CAEI(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
+#define DMA_CERR_CAEI_SET(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
+#define DMA_CERR_CAEI DMA_CERR_CAEI_MASK
 #define DMA_CERR_NOP_MASK                        (0x80U)
 #define DMA_CERR_NOP_SHIFT                       (7U)
-#define DMA_CERR_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
+#define DMA_CERR_NOP_SET(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
+#define DMA_CERR_NOP DMA_CERR_NOP_MASK
 
 /*! @name CINT - Clear Interrupt Request Register */
 #define DMA_CINT_CINT_MASK                       (0x1FU)
 #define DMA_CINT_CINT_SHIFT                      (0U)
-#define DMA_CINT_CINT(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
+#define DMA_CINT_CINT_SET(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
+#define DMA_CINT_CINT DMA_CINT_CINT_MASK
 #define DMA_CINT_CAIR_MASK                       (0x40U)
 #define DMA_CINT_CAIR_SHIFT                      (6U)
-#define DMA_CINT_CAIR(x)                         (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
+#define DMA_CINT_CAIR_SET(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
+#define DMA_CINT_CAIR DMA_CINT_CAIR_MASK
 #define DMA_CINT_NOP_MASK                        (0x80U)
 #define DMA_CINT_NOP_SHIFT                       (7U)
-#define DMA_CINT_NOP(x)                          (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
+#define DMA_CINT_NOP_SET(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
+#define DMA_CINT_NOP DMA_CINT_NOP_MASK
 
 /*! @name INT - Interrupt Request Register */
 #define DMA_INT_INT0_MASK                        (0x1U)
 #define DMA_INT_INT0_SHIFT                       (0U)
-#define DMA_INT_INT0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
+#define DMA_INT_INT0_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
+#define DMA_INT_INT0 DMA_INT_INT0_MASK
 #define DMA_INT_INT1_MASK                        (0x2U)
 #define DMA_INT_INT1_SHIFT                       (1U)
-#define DMA_INT_INT1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
+#define DMA_INT_INT1_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
+#define DMA_INT_INT1 DMA_INT_INT1_MASK
 #define DMA_INT_INT2_MASK                        (0x4U)
 #define DMA_INT_INT2_SHIFT                       (2U)
-#define DMA_INT_INT2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
+#define DMA_INT_INT2_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
+#define DMA_INT_INT2 DMA_INT_INT2_MASK
 #define DMA_INT_INT3_MASK                        (0x8U)
 #define DMA_INT_INT3_SHIFT                       (3U)
-#define DMA_INT_INT3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
+#define DMA_INT_INT3_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
+#define DMA_INT_INT3 DMA_INT_INT3_MASK
 #define DMA_INT_INT4_MASK                        (0x10U)
 #define DMA_INT_INT4_SHIFT                       (4U)
-#define DMA_INT_INT4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
+#define DMA_INT_INT4_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
+#define DMA_INT_INT4 DMA_INT_INT4_MASK
 #define DMA_INT_INT5_MASK                        (0x20U)
 #define DMA_INT_INT5_SHIFT                       (5U)
-#define DMA_INT_INT5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
+#define DMA_INT_INT5_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
+#define DMA_INT_INT5 DMA_INT_INT5_MASK
 #define DMA_INT_INT6_MASK                        (0x40U)
 #define DMA_INT_INT6_SHIFT                       (6U)
-#define DMA_INT_INT6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
+#define DMA_INT_INT6_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
+#define DMA_INT_INT6 DMA_INT_INT6_MASK
 #define DMA_INT_INT7_MASK                        (0x80U)
 #define DMA_INT_INT7_SHIFT                       (7U)
-#define DMA_INT_INT7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
+#define DMA_INT_INT7_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
+#define DMA_INT_INT7 DMA_INT_INT7_MASK
 #define DMA_INT_INT8_MASK                        (0x100U)
 #define DMA_INT_INT8_SHIFT                       (8U)
-#define DMA_INT_INT8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
+#define DMA_INT_INT8_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
+#define DMA_INT_INT8 DMA_INT_INT8_MASK
 #define DMA_INT_INT9_MASK                        (0x200U)
 #define DMA_INT_INT9_SHIFT                       (9U)
-#define DMA_INT_INT9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
+#define DMA_INT_INT9_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
+#define DMA_INT_INT9 DMA_INT_INT9_MASK
 #define DMA_INT_INT10_MASK                       (0x400U)
 #define DMA_INT_INT10_SHIFT                      (10U)
-#define DMA_INT_INT10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
+#define DMA_INT_INT10_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
+#define DMA_INT_INT10 DMA_INT_INT10_MASK
 #define DMA_INT_INT11_MASK                       (0x800U)
 #define DMA_INT_INT11_SHIFT                      (11U)
-#define DMA_INT_INT11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
+#define DMA_INT_INT11_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
+#define DMA_INT_INT11 DMA_INT_INT11_MASK
 #define DMA_INT_INT12_MASK                       (0x1000U)
 #define DMA_INT_INT12_SHIFT                      (12U)
-#define DMA_INT_INT12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
+#define DMA_INT_INT12_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
+#define DMA_INT_INT12 DMA_INT_INT12_MASK
 #define DMA_INT_INT13_MASK                       (0x2000U)
 #define DMA_INT_INT13_SHIFT                      (13U)
-#define DMA_INT_INT13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
+#define DMA_INT_INT13_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
+#define DMA_INT_INT13 DMA_INT_INT13_MASK
 #define DMA_INT_INT14_MASK                       (0x4000U)
 #define DMA_INT_INT14_SHIFT                      (14U)
-#define DMA_INT_INT14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
+#define DMA_INT_INT14_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
+#define DMA_INT_INT14 DMA_INT_INT14_MASK
 #define DMA_INT_INT15_MASK                       (0x8000U)
 #define DMA_INT_INT15_SHIFT                      (15U)
-#define DMA_INT_INT15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
+#define DMA_INT_INT15_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
+#define DMA_INT_INT15 DMA_INT_INT15_MASK
 #define DMA_INT_INT16_MASK                       (0x10000U)
 #define DMA_INT_INT16_SHIFT                      (16U)
-#define DMA_INT_INT16(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)
+#define DMA_INT_INT16_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)
+#define DMA_INT_INT16 DMA_INT_INT16_MASK
 #define DMA_INT_INT17_MASK                       (0x20000U)
 #define DMA_INT_INT17_SHIFT                      (17U)
-#define DMA_INT_INT17(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)
+#define DMA_INT_INT17_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)
+#define DMA_INT_INT17 DMA_INT_INT17_MASK
 #define DMA_INT_INT18_MASK                       (0x40000U)
 #define DMA_INT_INT18_SHIFT                      (18U)
-#define DMA_INT_INT18(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)
+#define DMA_INT_INT18_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)
+#define DMA_INT_INT18 DMA_INT_INT18_MASK
 #define DMA_INT_INT19_MASK                       (0x80000U)
 #define DMA_INT_INT19_SHIFT                      (19U)
-#define DMA_INT_INT19(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)
+#define DMA_INT_INT19_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)
+#define DMA_INT_INT19 DMA_INT_INT19_MASK
 #define DMA_INT_INT20_MASK                       (0x100000U)
 #define DMA_INT_INT20_SHIFT                      (20U)
-#define DMA_INT_INT20(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)
+#define DMA_INT_INT20_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)
+#define DMA_INT_INT20 DMA_INT_INT20_MASK
 #define DMA_INT_INT21_MASK                       (0x200000U)
 #define DMA_INT_INT21_SHIFT                      (21U)
-#define DMA_INT_INT21(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)
+#define DMA_INT_INT21_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)
+#define DMA_INT_INT21 DMA_INT_INT21_MASK
 #define DMA_INT_INT22_MASK                       (0x400000U)
 #define DMA_INT_INT22_SHIFT                      (22U)
-#define DMA_INT_INT22(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)
+#define DMA_INT_INT22_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)
+#define DMA_INT_INT22 DMA_INT_INT22_MASK
 #define DMA_INT_INT23_MASK                       (0x800000U)
 #define DMA_INT_INT23_SHIFT                      (23U)
-#define DMA_INT_INT23(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)
+#define DMA_INT_INT23_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)
+#define DMA_INT_INT23 DMA_INT_INT23_MASK
 #define DMA_INT_INT24_MASK                       (0x1000000U)
 #define DMA_INT_INT24_SHIFT                      (24U)
-#define DMA_INT_INT24(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)
+#define DMA_INT_INT24_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)
+#define DMA_INT_INT24 DMA_INT_INT24_MASK
 #define DMA_INT_INT25_MASK                       (0x2000000U)
 #define DMA_INT_INT25_SHIFT                      (25U)
-#define DMA_INT_INT25(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)
+#define DMA_INT_INT25_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)
+#define DMA_INT_INT25 DMA_INT_INT25_MASK
 #define DMA_INT_INT26_MASK                       (0x4000000U)
 #define DMA_INT_INT26_SHIFT                      (26U)
-#define DMA_INT_INT26(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)
+#define DMA_INT_INT26_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)
+#define DMA_INT_INT26 DMA_INT_INT26_MASK
 #define DMA_INT_INT27_MASK                       (0x8000000U)
 #define DMA_INT_INT27_SHIFT                      (27U)
-#define DMA_INT_INT27(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)
+#define DMA_INT_INT27_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)
+#define DMA_INT_INT27 DMA_INT_INT27_MASK
 #define DMA_INT_INT28_MASK                       (0x10000000U)
 #define DMA_INT_INT28_SHIFT                      (28U)
-#define DMA_INT_INT28(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)
+#define DMA_INT_INT28_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)
+#define DMA_INT_INT28 DMA_INT_INT28_MASK
 #define DMA_INT_INT29_MASK                       (0x20000000U)
 #define DMA_INT_INT29_SHIFT                      (29U)
-#define DMA_INT_INT29(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)
+#define DMA_INT_INT29_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)
+#define DMA_INT_INT29 DMA_INT_INT29_MASK
 #define DMA_INT_INT30_MASK                       (0x40000000U)
 #define DMA_INT_INT30_SHIFT                      (30U)
-#define DMA_INT_INT30(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)
+#define DMA_INT_INT30_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)
+#define DMA_INT_INT30 DMA_INT_INT30_MASK
 #define DMA_INT_INT31_MASK                       (0x80000000U)
 #define DMA_INT_INT31_SHIFT                      (31U)
-#define DMA_INT_INT31(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)
+#define DMA_INT_INT31_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)
+#define DMA_INT_INT31 DMA_INT_INT31_MASK
 
 /*! @name ERR - Error Register */
 #define DMA_ERR_ERR0_MASK                        (0x1U)
 #define DMA_ERR_ERR0_SHIFT                       (0U)
-#define DMA_ERR_ERR0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
+#define DMA_ERR_ERR0_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
+#define DMA_ERR_ERR0 DMA_ERR_ERR0_MASK
 #define DMA_ERR_ERR1_MASK                        (0x2U)
 #define DMA_ERR_ERR1_SHIFT                       (1U)
-#define DMA_ERR_ERR1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
+#define DMA_ERR_ERR1_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
+#define DMA_ERR_ERR1 DMA_ERR_ERR1_MASK
 #define DMA_ERR_ERR2_MASK                        (0x4U)
 #define DMA_ERR_ERR2_SHIFT                       (2U)
-#define DMA_ERR_ERR2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
+#define DMA_ERR_ERR2_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
+#define DMA_ERR_ERR2 DMA_ERR_ERR2_MASK
 #define DMA_ERR_ERR3_MASK                        (0x8U)
 #define DMA_ERR_ERR3_SHIFT                       (3U)
-#define DMA_ERR_ERR3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
+#define DMA_ERR_ERR3_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
+#define DMA_ERR_ERR3 DMA_ERR_ERR3_MASK
 #define DMA_ERR_ERR4_MASK                        (0x10U)
 #define DMA_ERR_ERR4_SHIFT                       (4U)
-#define DMA_ERR_ERR4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
+#define DMA_ERR_ERR4_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
+#define DMA_ERR_ERR4 DMA_ERR_ERR4_MASK
 #define DMA_ERR_ERR5_MASK                        (0x20U)
 #define DMA_ERR_ERR5_SHIFT                       (5U)
-#define DMA_ERR_ERR5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
+#define DMA_ERR_ERR5_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
+#define DMA_ERR_ERR5 DMA_ERR_ERR5_MASK
 #define DMA_ERR_ERR6_MASK                        (0x40U)
 #define DMA_ERR_ERR6_SHIFT                       (6U)
-#define DMA_ERR_ERR6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
+#define DMA_ERR_ERR6_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
+#define DMA_ERR_ERR6 DMA_ERR_ERR6_MASK
 #define DMA_ERR_ERR7_MASK                        (0x80U)
 #define DMA_ERR_ERR7_SHIFT                       (7U)
-#define DMA_ERR_ERR7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
+#define DMA_ERR_ERR7_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
+#define DMA_ERR_ERR7 DMA_ERR_ERR7_MASK
 #define DMA_ERR_ERR8_MASK                        (0x100U)
 #define DMA_ERR_ERR8_SHIFT                       (8U)
-#define DMA_ERR_ERR8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
+#define DMA_ERR_ERR8_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
+#define DMA_ERR_ERR8 DMA_ERR_ERR8_MASK
 #define DMA_ERR_ERR9_MASK                        (0x200U)
 #define DMA_ERR_ERR9_SHIFT                       (9U)
-#define DMA_ERR_ERR9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
+#define DMA_ERR_ERR9_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
+#define DMA_ERR_ERR9 DMA_ERR_ERR9_MASK
 #define DMA_ERR_ERR10_MASK                       (0x400U)
 #define DMA_ERR_ERR10_SHIFT                      (10U)
-#define DMA_ERR_ERR10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
+#define DMA_ERR_ERR10_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
+#define DMA_ERR_ERR10 DMA_ERR_ERR10_MASK
 #define DMA_ERR_ERR11_MASK                       (0x800U)
 #define DMA_ERR_ERR11_SHIFT                      (11U)
-#define DMA_ERR_ERR11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
+#define DMA_ERR_ERR11_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
+#define DMA_ERR_ERR11 DMA_ERR_ERR11_MASK
 #define DMA_ERR_ERR12_MASK                       (0x1000U)
 #define DMA_ERR_ERR12_SHIFT                      (12U)
-#define DMA_ERR_ERR12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
+#define DMA_ERR_ERR12_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
+#define DMA_ERR_ERR12 DMA_ERR_ERR12_MASK
 #define DMA_ERR_ERR13_MASK                       (0x2000U)
 #define DMA_ERR_ERR13_SHIFT                      (13U)
-#define DMA_ERR_ERR13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
+#define DMA_ERR_ERR13_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
+#define DMA_ERR_ERR13 DMA_ERR_ERR13_MASK
 #define DMA_ERR_ERR14_MASK                       (0x4000U)
 #define DMA_ERR_ERR14_SHIFT                      (14U)
-#define DMA_ERR_ERR14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
+#define DMA_ERR_ERR14_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
+#define DMA_ERR_ERR14 DMA_ERR_ERR14_MASK
 #define DMA_ERR_ERR15_MASK                       (0x8000U)
 #define DMA_ERR_ERR15_SHIFT                      (15U)
-#define DMA_ERR_ERR15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
+#define DMA_ERR_ERR15_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
+#define DMA_ERR_ERR15 DMA_ERR_ERR15_MASK
 #define DMA_ERR_ERR16_MASK                       (0x10000U)
 #define DMA_ERR_ERR16_SHIFT                      (16U)
-#define DMA_ERR_ERR16(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)
+#define DMA_ERR_ERR16_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)
+#define DMA_ERR_ERR16 DMA_ERR_ERR16_MASK
 #define DMA_ERR_ERR17_MASK                       (0x20000U)
 #define DMA_ERR_ERR17_SHIFT                      (17U)
-#define DMA_ERR_ERR17(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)
+#define DMA_ERR_ERR17_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)
+#define DMA_ERR_ERR17 DMA_ERR_ERR17_MASK
 #define DMA_ERR_ERR18_MASK                       (0x40000U)
 #define DMA_ERR_ERR18_SHIFT                      (18U)
-#define DMA_ERR_ERR18(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)
+#define DMA_ERR_ERR18_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)
+#define DMA_ERR_ERR18 DMA_ERR_ERR18_MASK
 #define DMA_ERR_ERR19_MASK                       (0x80000U)
 #define DMA_ERR_ERR19_SHIFT                      (19U)
-#define DMA_ERR_ERR19(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)
+#define DMA_ERR_ERR19_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)
+#define DMA_ERR_ERR19 DMA_ERR_ERR19_MASK
 #define DMA_ERR_ERR20_MASK                       (0x100000U)
 #define DMA_ERR_ERR20_SHIFT                      (20U)
-#define DMA_ERR_ERR20(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)
+#define DMA_ERR_ERR20_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)
+#define DMA_ERR_ERR20 DMA_ERR_ERR20_MASK
 #define DMA_ERR_ERR21_MASK                       (0x200000U)
 #define DMA_ERR_ERR21_SHIFT                      (21U)
-#define DMA_ERR_ERR21(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)
+#define DMA_ERR_ERR21_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)
+#define DMA_ERR_ERR21 DMA_ERR_ERR21_MASK
 #define DMA_ERR_ERR22_MASK                       (0x400000U)
 #define DMA_ERR_ERR22_SHIFT                      (22U)
-#define DMA_ERR_ERR22(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)
+#define DMA_ERR_ERR22_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)
+#define DMA_ERR_ERR22 DMA_ERR_ERR22_MASK
 #define DMA_ERR_ERR23_MASK                       (0x800000U)
 #define DMA_ERR_ERR23_SHIFT                      (23U)
-#define DMA_ERR_ERR23(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)
+#define DMA_ERR_ERR23_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)
+#define DMA_ERR_ERR23 DMA_ERR_ERR23_MASK
 #define DMA_ERR_ERR24_MASK                       (0x1000000U)
 #define DMA_ERR_ERR24_SHIFT                      (24U)
-#define DMA_ERR_ERR24(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)
+#define DMA_ERR_ERR24_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)
+#define DMA_ERR_ERR24 DMA_ERR_ERR24_MASK
 #define DMA_ERR_ERR25_MASK                       (0x2000000U)
 #define DMA_ERR_ERR25_SHIFT                      (25U)
-#define DMA_ERR_ERR25(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)
+#define DMA_ERR_ERR25_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)
+#define DMA_ERR_ERR25 DMA_ERR_ERR25_MASK
 #define DMA_ERR_ERR26_MASK                       (0x4000000U)
 #define DMA_ERR_ERR26_SHIFT                      (26U)
-#define DMA_ERR_ERR26(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)
+#define DMA_ERR_ERR26_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)
+#define DMA_ERR_ERR26 DMA_ERR_ERR26_MASK
 #define DMA_ERR_ERR27_MASK                       (0x8000000U)
 #define DMA_ERR_ERR27_SHIFT                      (27U)
-#define DMA_ERR_ERR27(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)
+#define DMA_ERR_ERR27_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)
+#define DMA_ERR_ERR27 DMA_ERR_ERR27_MASK
 #define DMA_ERR_ERR28_MASK                       (0x10000000U)
 #define DMA_ERR_ERR28_SHIFT                      (28U)
-#define DMA_ERR_ERR28(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)
+#define DMA_ERR_ERR28_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)
+#define DMA_ERR_ERR28 DMA_ERR_ERR28_MASK
 #define DMA_ERR_ERR29_MASK                       (0x20000000U)
 #define DMA_ERR_ERR29_SHIFT                      (29U)
-#define DMA_ERR_ERR29(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)
+#define DMA_ERR_ERR29_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)
+#define DMA_ERR_ERR29 DMA_ERR_ERR29_MASK
 #define DMA_ERR_ERR30_MASK                       (0x40000000U)
 #define DMA_ERR_ERR30_SHIFT                      (30U)
-#define DMA_ERR_ERR30(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)
+#define DMA_ERR_ERR30_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)
+#define DMA_ERR_ERR30 DMA_ERR_ERR30_MASK
 #define DMA_ERR_ERR31_MASK                       (0x80000000U)
 #define DMA_ERR_ERR31_SHIFT                      (31U)
-#define DMA_ERR_ERR31(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)
+#define DMA_ERR_ERR31_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)
+#define DMA_ERR_ERR31 DMA_ERR_ERR31_MASK
 
 /*! @name HRS - Hardware Request Status Register */
 #define DMA_HRS_HRS0_MASK                        (0x1U)
 #define DMA_HRS_HRS0_SHIFT                       (0U)
-#define DMA_HRS_HRS0(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
+#define DMA_HRS_HRS0_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
+#define DMA_HRS_HRS0 DMA_HRS_HRS0_MASK
 #define DMA_HRS_HRS1_MASK                        (0x2U)
 #define DMA_HRS_HRS1_SHIFT                       (1U)
-#define DMA_HRS_HRS1(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
+#define DMA_HRS_HRS1_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
+#define DMA_HRS_HRS1 DMA_HRS_HRS1_MASK
 #define DMA_HRS_HRS2_MASK                        (0x4U)
 #define DMA_HRS_HRS2_SHIFT                       (2U)
-#define DMA_HRS_HRS2(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
+#define DMA_HRS_HRS2_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
+#define DMA_HRS_HRS2 DMA_HRS_HRS2_MASK
 #define DMA_HRS_HRS3_MASK                        (0x8U)
 #define DMA_HRS_HRS3_SHIFT                       (3U)
-#define DMA_HRS_HRS3(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
+#define DMA_HRS_HRS3_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
+#define DMA_HRS_HRS3 DMA_HRS_HRS3_MASK
 #define DMA_HRS_HRS4_MASK                        (0x10U)
 #define DMA_HRS_HRS4_SHIFT                       (4U)
-#define DMA_HRS_HRS4(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
+#define DMA_HRS_HRS4_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
+#define DMA_HRS_HRS4 DMA_HRS_HRS4_MASK
 #define DMA_HRS_HRS5_MASK                        (0x20U)
 #define DMA_HRS_HRS5_SHIFT                       (5U)
-#define DMA_HRS_HRS5(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
+#define DMA_HRS_HRS5_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
+#define DMA_HRS_HRS5 DMA_HRS_HRS5_MASK
 #define DMA_HRS_HRS6_MASK                        (0x40U)
 #define DMA_HRS_HRS6_SHIFT                       (6U)
-#define DMA_HRS_HRS6(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
+#define DMA_HRS_HRS6_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
+#define DMA_HRS_HRS6 DMA_HRS_HRS6_MASK
 #define DMA_HRS_HRS7_MASK                        (0x80U)
 #define DMA_HRS_HRS7_SHIFT                       (7U)
-#define DMA_HRS_HRS7(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
+#define DMA_HRS_HRS7_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
+#define DMA_HRS_HRS7 DMA_HRS_HRS7_MASK
 #define DMA_HRS_HRS8_MASK                        (0x100U)
 #define DMA_HRS_HRS8_SHIFT                       (8U)
-#define DMA_HRS_HRS8(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
+#define DMA_HRS_HRS8_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
+#define DMA_HRS_HRS8 DMA_HRS_HRS8_MASK
 #define DMA_HRS_HRS9_MASK                        (0x200U)
 #define DMA_HRS_HRS9_SHIFT                       (9U)
-#define DMA_HRS_HRS9(x)                          (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
+#define DMA_HRS_HRS9_SET(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
+#define DMA_HRS_HRS9 DMA_HRS_HRS9_MASK
 #define DMA_HRS_HRS10_MASK                       (0x400U)
 #define DMA_HRS_HRS10_SHIFT                      (10U)
-#define DMA_HRS_HRS10(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
+#define DMA_HRS_HRS10_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
+#define DMA_HRS_HRS10 DMA_HRS_HRS10_MASK
 #define DMA_HRS_HRS11_MASK                       (0x800U)
 #define DMA_HRS_HRS11_SHIFT                      (11U)
-#define DMA_HRS_HRS11(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
+#define DMA_HRS_HRS11_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
+#define DMA_HRS_HRS11 DMA_HRS_HRS11_MASK
 #define DMA_HRS_HRS12_MASK                       (0x1000U)
 #define DMA_HRS_HRS12_SHIFT                      (12U)
-#define DMA_HRS_HRS12(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
+#define DMA_HRS_HRS12_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
+#define DMA_HRS_HRS12 DMA_HRS_HRS12_MASK
 #define DMA_HRS_HRS13_MASK                       (0x2000U)
 #define DMA_HRS_HRS13_SHIFT                      (13U)
-#define DMA_HRS_HRS13(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
+#define DMA_HRS_HRS13_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
+#define DMA_HRS_HRS13 DMA_HRS_HRS13_MASK
 #define DMA_HRS_HRS14_MASK                       (0x4000U)
 #define DMA_HRS_HRS14_SHIFT                      (14U)
-#define DMA_HRS_HRS14(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
+#define DMA_HRS_HRS14_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
+#define DMA_HRS_HRS14 DMA_HRS_HRS14_MASK
 #define DMA_HRS_HRS15_MASK                       (0x8000U)
 #define DMA_HRS_HRS15_SHIFT                      (15U)
-#define DMA_HRS_HRS15(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
+#define DMA_HRS_HRS15_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
+#define DMA_HRS_HRS15 DMA_HRS_HRS15_MASK
 #define DMA_HRS_HRS16_MASK                       (0x10000U)
 #define DMA_HRS_HRS16_SHIFT                      (16U)
-#define DMA_HRS_HRS16(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)
+#define DMA_HRS_HRS16_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)
+#define DMA_HRS_HRS16 DMA_HRS_HRS16_MASK
 #define DMA_HRS_HRS17_MASK                       (0x20000U)
 #define DMA_HRS_HRS17_SHIFT                      (17U)
-#define DMA_HRS_HRS17(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)
+#define DMA_HRS_HRS17_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)
+#define DMA_HRS_HRS17 DMA_HRS_HRS17_MASK
 #define DMA_HRS_HRS18_MASK                       (0x40000U)
 #define DMA_HRS_HRS18_SHIFT                      (18U)
-#define DMA_HRS_HRS18(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)
+#define DMA_HRS_HRS18_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)
+#define DMA_HRS_HRS18 DMA_HRS_HRS18_MASK
 #define DMA_HRS_HRS19_MASK                       (0x80000U)
 #define DMA_HRS_HRS19_SHIFT                      (19U)
-#define DMA_HRS_HRS19(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)
+#define DMA_HRS_HRS19_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)
+#define DMA_HRS_HRS19 DMA_HRS_HRS19_MASK
 #define DMA_HRS_HRS20_MASK                       (0x100000U)
 #define DMA_HRS_HRS20_SHIFT                      (20U)
-#define DMA_HRS_HRS20(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)
+#define DMA_HRS_HRS20_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)
+#define DMA_HRS_HRS20 DMA_HRS_HRS20_MASK
 #define DMA_HRS_HRS21_MASK                       (0x200000U)
 #define DMA_HRS_HRS21_SHIFT                      (21U)
-#define DMA_HRS_HRS21(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)
+#define DMA_HRS_HRS21_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)
+#define DMA_HRS_HRS21 DMA_HRS_HRS21_MASK
 #define DMA_HRS_HRS22_MASK                       (0x400000U)
 #define DMA_HRS_HRS22_SHIFT                      (22U)
-#define DMA_HRS_HRS22(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)
+#define DMA_HRS_HRS22_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)
+#define DMA_HRS_HRS22 DMA_HRS_HRS22_MASK
 #define DMA_HRS_HRS23_MASK                       (0x800000U)
 #define DMA_HRS_HRS23_SHIFT                      (23U)
-#define DMA_HRS_HRS23(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)
+#define DMA_HRS_HRS23_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)
+#define DMA_HRS_HRS23 DMA_HRS_HRS23_MASK
 #define DMA_HRS_HRS24_MASK                       (0x1000000U)
 #define DMA_HRS_HRS24_SHIFT                      (24U)
-#define DMA_HRS_HRS24(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)
+#define DMA_HRS_HRS24_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)
+#define DMA_HRS_HRS24 DMA_HRS_HRS24_MASK
 #define DMA_HRS_HRS25_MASK                       (0x2000000U)
 #define DMA_HRS_HRS25_SHIFT                      (25U)
-#define DMA_HRS_HRS25(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)
+#define DMA_HRS_HRS25_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)
+#define DMA_HRS_HRS25 DMA_HRS_HRS25_MASK
 #define DMA_HRS_HRS26_MASK                       (0x4000000U)
 #define DMA_HRS_HRS26_SHIFT                      (26U)
-#define DMA_HRS_HRS26(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)
+#define DMA_HRS_HRS26_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)
+#define DMA_HRS_HRS26 DMA_HRS_HRS26_MASK
 #define DMA_HRS_HRS27_MASK                       (0x8000000U)
 #define DMA_HRS_HRS27_SHIFT                      (27U)
-#define DMA_HRS_HRS27(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)
+#define DMA_HRS_HRS27_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)
+#define DMA_HRS_HRS27 DMA_HRS_HRS27_MASK
 #define DMA_HRS_HRS28_MASK                       (0x10000000U)
 #define DMA_HRS_HRS28_SHIFT                      (28U)
-#define DMA_HRS_HRS28(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)
+#define DMA_HRS_HRS28_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)
+#define DMA_HRS_HRS28 DMA_HRS_HRS28_MASK
 #define DMA_HRS_HRS29_MASK                       (0x20000000U)
 #define DMA_HRS_HRS29_SHIFT                      (29U)
-#define DMA_HRS_HRS29(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)
+#define DMA_HRS_HRS29_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)
+#define DMA_HRS_HRS29 DMA_HRS_HRS29_MASK
 #define DMA_HRS_HRS30_MASK                       (0x40000000U)
 #define DMA_HRS_HRS30_SHIFT                      (30U)
-#define DMA_HRS_HRS30(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)
+#define DMA_HRS_HRS30_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)
+#define DMA_HRS_HRS30 DMA_HRS_HRS30_MASK
 #define DMA_HRS_HRS31_MASK                       (0x80000000U)
 #define DMA_HRS_HRS31_SHIFT                      (31U)
-#define DMA_HRS_HRS31(x)                         (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)
+#define DMA_HRS_HRS31_SET(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)
+#define DMA_HRS_HRS31 DMA_HRS_HRS31_MASK
 
 /*! @name EARS - Enable Asynchronous Request in Stop Register */
 #define DMA_EARS_EDREQ_0_MASK                    (0x1U)
 #define DMA_EARS_EDREQ_0_SHIFT                   (0U)
-#define DMA_EARS_EDREQ_0(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
+#define DMA_EARS_EDREQ_0_SET(x)                  (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
+#define DMA_EARS_EDREQ_0 DMA_EARS_EDREQ_0_MASK
 #define DMA_EARS_EDREQ_1_MASK                    (0x2U)
 #define DMA_EARS_EDREQ_1_SHIFT                   (1U)
-#define DMA_EARS_EDREQ_1(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
+#define DMA_EARS_EDREQ_1_SET(x)                  (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
+#define DMA_EARS_EDREQ_1 DMA_EARS_EDREQ_1_MASK
 #define DMA_EARS_EDREQ_2_MASK                    (0x4U)
 #define DMA_EARS_EDREQ_2_SHIFT                   (2U)
-#define DMA_EARS_EDREQ_2(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
+#define DMA_EARS_EDREQ_2_SET(x)                  (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
+#define DMA_EARS_EDREQ_2 DMA_EARS_EDREQ_2_MASK
 #define DMA_EARS_EDREQ_3_MASK                    (0x8U)
 #define DMA_EARS_EDREQ_3_SHIFT                   (3U)
-#define DMA_EARS_EDREQ_3(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
+#define DMA_EARS_EDREQ_3_SET(x)                  (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
+#define DMA_EARS_EDREQ_3 DMA_EARS_EDREQ_3_MASK
 #define DMA_EARS_EDREQ_4_MASK                    (0x10U)
 #define DMA_EARS_EDREQ_4_SHIFT                   (4U)
-#define DMA_EARS_EDREQ_4(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
+#define DMA_EARS_EDREQ_4_SET(x)                  (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
+#define DMA_EARS_EDREQ_4 DMA_EARS_EDREQ_4_MASK
 #define DMA_EARS_EDREQ_5_MASK                    (0x20U)
 #define DMA_EARS_EDREQ_5_SHIFT                   (5U)
-#define DMA_EARS_EDREQ_5(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
+#define DMA_EARS_EDREQ_5_SET(x)                  (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
+#define DMA_EARS_EDREQ_5 DMA_EARS_EDREQ_5_MASK
 #define DMA_EARS_EDREQ_6_MASK                    (0x40U)
 #define DMA_EARS_EDREQ_6_SHIFT                   (6U)
-#define DMA_EARS_EDREQ_6(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
+#define DMA_EARS_EDREQ_6_SET(x)                  (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
+#define DMA_EARS_EDREQ_6 DMA_EARS_EDREQ_6_MASK
 #define DMA_EARS_EDREQ_7_MASK                    (0x80U)
 #define DMA_EARS_EDREQ_7_SHIFT                   (7U)
-#define DMA_EARS_EDREQ_7(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
+#define DMA_EARS_EDREQ_7_SET(x)                  (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
+#define DMA_EARS_EDREQ_7 DMA_EARS_EDREQ_7_MASK
 #define DMA_EARS_EDREQ_8_MASK                    (0x100U)
 #define DMA_EARS_EDREQ_8_SHIFT                   (8U)
-#define DMA_EARS_EDREQ_8(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)
+#define DMA_EARS_EDREQ_8_SET(x)                  (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)
+#define DMA_EARS_EDREQ_8 DMA_EARS_EDREQ_8_MASK
 #define DMA_EARS_EDREQ_9_MASK                    (0x200U)
 #define DMA_EARS_EDREQ_9_SHIFT                   (9U)
-#define DMA_EARS_EDREQ_9(x)                      (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)
+#define DMA_EARS_EDREQ_9_SET(x)                  (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)
+#define DMA_EARS_EDREQ_9 DMA_EARS_EDREQ_9_MASK
 #define DMA_EARS_EDREQ_10_MASK                   (0x400U)
 #define DMA_EARS_EDREQ_10_SHIFT                  (10U)
-#define DMA_EARS_EDREQ_10(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)
+#define DMA_EARS_EDREQ_10_SET(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)
+#define DMA_EARS_EDREQ_10 DMA_EARS_EDREQ_10_MASK
 #define DMA_EARS_EDREQ_11_MASK                   (0x800U)
 #define DMA_EARS_EDREQ_11_SHIFT                  (11U)
-#define DMA_EARS_EDREQ_11(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)
+#define DMA_EARS_EDREQ_11_SET(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)
+#define DMA_EARS_EDREQ_11 DMA_EARS_EDREQ_11_MASK
 #define DMA_EARS_EDREQ_12_MASK                   (0x1000U)
 #define DMA_EARS_EDREQ_12_SHIFT                  (12U)
-#define DMA_EARS_EDREQ_12(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)
+#define DMA_EARS_EDREQ_12_SET(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)
+#define DMA_EARS_EDREQ_12 DMA_EARS_EDREQ_12_MASK
 #define DMA_EARS_EDREQ_13_MASK                   (0x2000U)
 #define DMA_EARS_EDREQ_13_SHIFT                  (13U)
-#define DMA_EARS_EDREQ_13(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)
+#define DMA_EARS_EDREQ_13_SET(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)
+#define DMA_EARS_EDREQ_13 DMA_EARS_EDREQ_13_MASK
 #define DMA_EARS_EDREQ_14_MASK                   (0x4000U)
 #define DMA_EARS_EDREQ_14_SHIFT                  (14U)
-#define DMA_EARS_EDREQ_14(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)
+#define DMA_EARS_EDREQ_14_SET(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)
+#define DMA_EARS_EDREQ_14 DMA_EARS_EDREQ_14_MASK
 #define DMA_EARS_EDREQ_15_MASK                   (0x8000U)
 #define DMA_EARS_EDREQ_15_SHIFT                  (15U)
-#define DMA_EARS_EDREQ_15(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)
+#define DMA_EARS_EDREQ_15_SET(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)
+#define DMA_EARS_EDREQ_15 DMA_EARS_EDREQ_15_MASK
 #define DMA_EARS_EDREQ_16_MASK                   (0x10000U)
 #define DMA_EARS_EDREQ_16_SHIFT                  (16U)
-#define DMA_EARS_EDREQ_16(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)
+#define DMA_EARS_EDREQ_16_SET(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)
+#define DMA_EARS_EDREQ_16 DMA_EARS_EDREQ_16_MASK
 #define DMA_EARS_EDREQ_17_MASK                   (0x20000U)
 #define DMA_EARS_EDREQ_17_SHIFT                  (17U)
-#define DMA_EARS_EDREQ_17(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)
+#define DMA_EARS_EDREQ_17_SET(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)
+#define DMA_EARS_EDREQ_17 DMA_EARS_EDREQ_17_MASK
 #define DMA_EARS_EDREQ_18_MASK                   (0x40000U)
 #define DMA_EARS_EDREQ_18_SHIFT                  (18U)
-#define DMA_EARS_EDREQ_18(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)
+#define DMA_EARS_EDREQ_18_SET(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)
+#define DMA_EARS_EDREQ_18 DMA_EARS_EDREQ_18_MASK
 #define DMA_EARS_EDREQ_19_MASK                   (0x80000U)
 #define DMA_EARS_EDREQ_19_SHIFT                  (19U)
-#define DMA_EARS_EDREQ_19(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)
+#define DMA_EARS_EDREQ_19_SET(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)
+#define DMA_EARS_EDREQ_19 DMA_EARS_EDREQ_19_MASK
 #define DMA_EARS_EDREQ_20_MASK                   (0x100000U)
 #define DMA_EARS_EDREQ_20_SHIFT                  (20U)
-#define DMA_EARS_EDREQ_20(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)
+#define DMA_EARS_EDREQ_20_SET(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)
+#define DMA_EARS_EDREQ_20 DMA_EARS_EDREQ_20_MASK
 #define DMA_EARS_EDREQ_21_MASK                   (0x200000U)
 #define DMA_EARS_EDREQ_21_SHIFT                  (21U)
-#define DMA_EARS_EDREQ_21(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)
+#define DMA_EARS_EDREQ_21_SET(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)
+#define DMA_EARS_EDREQ_21 DMA_EARS_EDREQ_21_MASK
 #define DMA_EARS_EDREQ_22_MASK                   (0x400000U)
 #define DMA_EARS_EDREQ_22_SHIFT                  (22U)
-#define DMA_EARS_EDREQ_22(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)
+#define DMA_EARS_EDREQ_22_SET(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)
+#define DMA_EARS_EDREQ_22 DMA_EARS_EDREQ_22_MASK
 #define DMA_EARS_EDREQ_23_MASK                   (0x800000U)
 #define DMA_EARS_EDREQ_23_SHIFT                  (23U)
-#define DMA_EARS_EDREQ_23(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)
+#define DMA_EARS_EDREQ_23_SET(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)
+#define DMA_EARS_EDREQ_23 DMA_EARS_EDREQ_23_MASK
 #define DMA_EARS_EDREQ_24_MASK                   (0x1000000U)
 #define DMA_EARS_EDREQ_24_SHIFT                  (24U)
-#define DMA_EARS_EDREQ_24(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)
+#define DMA_EARS_EDREQ_24_SET(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)
+#define DMA_EARS_EDREQ_24 DMA_EARS_EDREQ_24_MASK
 #define DMA_EARS_EDREQ_25_MASK                   (0x2000000U)
 #define DMA_EARS_EDREQ_25_SHIFT                  (25U)
-#define DMA_EARS_EDREQ_25(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)
+#define DMA_EARS_EDREQ_25_SET(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)
+#define DMA_EARS_EDREQ_25 DMA_EARS_EDREQ_25_MASK
 #define DMA_EARS_EDREQ_26_MASK                   (0x4000000U)
 #define DMA_EARS_EDREQ_26_SHIFT                  (26U)
-#define DMA_EARS_EDREQ_26(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)
+#define DMA_EARS_EDREQ_26_SET(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)
+#define DMA_EARS_EDREQ_26 DMA_EARS_EDREQ_26_MASK
 #define DMA_EARS_EDREQ_27_MASK                   (0x8000000U)
 #define DMA_EARS_EDREQ_27_SHIFT                  (27U)
-#define DMA_EARS_EDREQ_27(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)
+#define DMA_EARS_EDREQ_27_SET(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)
+#define DMA_EARS_EDREQ_27 DMA_EARS_EDREQ_27_MASK
 #define DMA_EARS_EDREQ_28_MASK                   (0x10000000U)
 #define DMA_EARS_EDREQ_28_SHIFT                  (28U)
-#define DMA_EARS_EDREQ_28(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)
+#define DMA_EARS_EDREQ_28_SET(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)
+#define DMA_EARS_EDREQ_28 DMA_EARS_EDREQ_28_MASK
 #define DMA_EARS_EDREQ_29_MASK                   (0x20000000U)
 #define DMA_EARS_EDREQ_29_SHIFT                  (29U)
-#define DMA_EARS_EDREQ_29(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)
+#define DMA_EARS_EDREQ_29_SET(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)
+#define DMA_EARS_EDREQ_29 DMA_EARS_EDREQ_29_MASK
 #define DMA_EARS_EDREQ_30_MASK                   (0x40000000U)
 #define DMA_EARS_EDREQ_30_SHIFT                  (30U)
-#define DMA_EARS_EDREQ_30(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)
+#define DMA_EARS_EDREQ_30_SET(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)
+#define DMA_EARS_EDREQ_30 DMA_EARS_EDREQ_30_MASK
 #define DMA_EARS_EDREQ_31_MASK                   (0x80000000U)
 #define DMA_EARS_EDREQ_31_SHIFT                  (31U)
-#define DMA_EARS_EDREQ_31(x)                     (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)
+#define DMA_EARS_EDREQ_31_SET(x)                 (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)
+#define DMA_EARS_EDREQ_31 DMA_EARS_EDREQ_31_MASK
 
 /*! @name DCHPRI3 - Channel n Priority Register */
 #define DMA_DCHPRI3_CHPRI_MASK                   (0xFU)
 #define DMA_DCHPRI3_CHPRI_SHIFT                  (0U)
-#define DMA_DCHPRI3_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
+#define DMA_DCHPRI3_CHPRI_SET(x)                 (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
+#define DMA_DCHPRI3_CHPRI DMA_DCHPRI3_CHPRI_MASK
 #define DMA_DCHPRI3_GRPPRI_MASK                  (0x30U)
 #define DMA_DCHPRI3_GRPPRI_SHIFT                 (4U)
-#define DMA_DCHPRI3_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)
+#define DMA_DCHPRI3_GRPPRI_SET(x)                (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)
+#define DMA_DCHPRI3_GRPPRI DMA_DCHPRI3_GRPPRI_MASK
 #define DMA_DCHPRI3_DPA_MASK                     (0x40U)
 #define DMA_DCHPRI3_DPA_SHIFT                    (6U)
-#define DMA_DCHPRI3_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
+#define DMA_DCHPRI3_DPA_SET(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
+#define DMA_DCHPRI3_DPA DMA_DCHPRI3_DPA_MASK
 #define DMA_DCHPRI3_ECP_MASK                     (0x80U)
 #define DMA_DCHPRI3_ECP_SHIFT                    (7U)
-#define DMA_DCHPRI3_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
+#define DMA_DCHPRI3_ECP_SET(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
+#define DMA_DCHPRI3_ECP DMA_DCHPRI3_ECP_MASK
 
 /*! @name DCHPRI2 - Channel n Priority Register */
 #define DMA_DCHPRI2_CHPRI_MASK                   (0xFU)
 #define DMA_DCHPRI2_CHPRI_SHIFT                  (0U)
-#define DMA_DCHPRI2_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
+#define DMA_DCHPRI2_CHPRI_SET(x)                 (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
+#define DMA_DCHPRI2_CHPRI DMA_DCHPRI2_CHPRI_MASK
 #define DMA_DCHPRI2_GRPPRI_MASK                  (0x30U)
 #define DMA_DCHPRI2_GRPPRI_SHIFT                 (4U)
-#define DMA_DCHPRI2_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)
+#define DMA_DCHPRI2_GRPPRI_SET(x)                (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)
+#define DMA_DCHPRI2_GRPPRI DMA_DCHPRI2_GRPPRI_MASK
 #define DMA_DCHPRI2_DPA_MASK                     (0x40U)
 #define DMA_DCHPRI2_DPA_SHIFT                    (6U)
-#define DMA_DCHPRI2_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
+#define DMA_DCHPRI2_DPA_SET(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
+#define DMA_DCHPRI2_DPA DMA_DCHPRI2_DPA_MASK
 #define DMA_DCHPRI2_ECP_MASK                     (0x80U)
 #define DMA_DCHPRI2_ECP_SHIFT                    (7U)
-#define DMA_DCHPRI2_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
+#define DMA_DCHPRI2_ECP_SET(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
+#define DMA_DCHPRI2_ECP DMA_DCHPRI2_ECP_MASK
 
 /*! @name DCHPRI1 - Channel n Priority Register */
 #define DMA_DCHPRI1_CHPRI_MASK                   (0xFU)
 #define DMA_DCHPRI1_CHPRI_SHIFT                  (0U)
-#define DMA_DCHPRI1_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
+#define DMA_DCHPRI1_CHPRI_SET(x)                 (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
+#define DMA_DCHPRI1_CHPRI DMA_DCHPRI1_CHPRI_MASK
 #define DMA_DCHPRI1_GRPPRI_MASK                  (0x30U)
 #define DMA_DCHPRI1_GRPPRI_SHIFT                 (4U)
-#define DMA_DCHPRI1_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)
+#define DMA_DCHPRI1_GRPPRI_SET(x)                (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)
+#define DMA_DCHPRI1_GRPPRI DMA_DCHPRI1_GRPPRI_MASK
 #define DMA_DCHPRI1_DPA_MASK                     (0x40U)
 #define DMA_DCHPRI1_DPA_SHIFT                    (6U)
-#define DMA_DCHPRI1_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
+#define DMA_DCHPRI1_DPA_SET(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
+#define DMA_DCHPRI1_DPA DMA_DCHPRI1_DPA_MASK
 #define DMA_DCHPRI1_ECP_MASK                     (0x80U)
 #define DMA_DCHPRI1_ECP_SHIFT                    (7U)
-#define DMA_DCHPRI1_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
+#define DMA_DCHPRI1_ECP_SET(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
+#define DMA_DCHPRI1_ECP DMA_DCHPRI1_ECP_MASK
 
 /*! @name DCHPRI0 - Channel n Priority Register */
 #define DMA_DCHPRI0_CHPRI_MASK                   (0xFU)
 #define DMA_DCHPRI0_CHPRI_SHIFT                  (0U)
-#define DMA_DCHPRI0_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
+#define DMA_DCHPRI0_CHPRI_SET(x)                 (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
+#define DMA_DCHPRI0_CHPRI DMA_DCHPRI0_CHPRI_MASK
 #define DMA_DCHPRI0_GRPPRI_MASK                  (0x30U)
 #define DMA_DCHPRI0_GRPPRI_SHIFT                 (4U)
-#define DMA_DCHPRI0_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)
+#define DMA_DCHPRI0_GRPPRI_SET(x)                (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)
+#define DMA_DCHPRI0_GRPPRI DMA_DCHPRI0_GRPPRI_MASK
 #define DMA_DCHPRI0_DPA_MASK                     (0x40U)
 #define DMA_DCHPRI0_DPA_SHIFT                    (6U)
-#define DMA_DCHPRI0_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
+#define DMA_DCHPRI0_DPA_SET(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
+#define DMA_DCHPRI0_DPA DMA_DCHPRI0_DPA_MASK
 #define DMA_DCHPRI0_ECP_MASK                     (0x80U)
 #define DMA_DCHPRI0_ECP_SHIFT                    (7U)
-#define DMA_DCHPRI0_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
+#define DMA_DCHPRI0_ECP_SET(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
+#define DMA_DCHPRI0_ECP DMA_DCHPRI0_ECP_MASK
 
 /*! @name DCHPRI7 - Channel n Priority Register */
 #define DMA_DCHPRI7_CHPRI_MASK                   (0xFU)
 #define DMA_DCHPRI7_CHPRI_SHIFT                  (0U)
-#define DMA_DCHPRI7_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
+#define DMA_DCHPRI7_CHPRI_SET(x)                 (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
+#define DMA_DCHPRI7_CHPRI DMA_DCHPRI7_CHPRI_MASK
 #define DMA_DCHPRI7_GRPPRI_MASK                  (0x30U)
 #define DMA_DCHPRI7_GRPPRI_SHIFT                 (4U)
-#define DMA_DCHPRI7_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)
+#define DMA_DCHPRI7_GRPPRI_SET(x)                (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)
+#define DMA_DCHPRI7_GRPPRI DMA_DCHPRI7_GRPPRI_MASK
 #define DMA_DCHPRI7_DPA_MASK                     (0x40U)
 #define DMA_DCHPRI7_DPA_SHIFT                    (6U)
-#define DMA_DCHPRI7_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
+#define DMA_DCHPRI7_DPA_SET(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
+#define DMA_DCHPRI7_DPA DMA_DCHPRI7_DPA_MASK
 #define DMA_DCHPRI7_ECP_MASK                     (0x80U)
 #define DMA_DCHPRI7_ECP_SHIFT                    (7U)
-#define DMA_DCHPRI7_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
+#define DMA_DCHPRI7_ECP_SET(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
+#define DMA_DCHPRI7_ECP DMA_DCHPRI7_ECP_MASK
 
 /*! @name DCHPRI6 - Channel n Priority Register */
 #define DMA_DCHPRI6_CHPRI_MASK                   (0xFU)
 #define DMA_DCHPRI6_CHPRI_SHIFT                  (0U)
-#define DMA_DCHPRI6_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
+#define DMA_DCHPRI6_CHPRI_SET(x)                 (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
+#define DMA_DCHPRI6_CHPRI DMA_DCHPRI6_CHPRI_MASK
 #define DMA_DCHPRI6_GRPPRI_MASK                  (0x30U)
 #define DMA_DCHPRI6_GRPPRI_SHIFT                 (4U)
-#define DMA_DCHPRI6_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)
+#define DMA_DCHPRI6_GRPPRI_SET(x)                (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)
+#define DMA_DCHPRI6_GRPPRI DMA_DCHPRI6_GRPPRI_MASK
 #define DMA_DCHPRI6_DPA_MASK                     (0x40U)
 #define DMA_DCHPRI6_DPA_SHIFT                    (6U)
-#define DMA_DCHPRI6_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
+#define DMA_DCHPRI6_DPA_SET(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
+#define DMA_DCHPRI6_DPA DMA_DCHPRI6_DPA_MASK
 #define DMA_DCHPRI6_ECP_MASK                     (0x80U)
 #define DMA_DCHPRI6_ECP_SHIFT                    (7U)
-#define DMA_DCHPRI6_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
+#define DMA_DCHPRI6_ECP_SET(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
+#define DMA_DCHPRI6_ECP DMA_DCHPRI6_ECP_MASK
 
 /*! @name DCHPRI5 - Channel n Priority Register */
 #define DMA_DCHPRI5_CHPRI_MASK                   (0xFU)
 #define DMA_DCHPRI5_CHPRI_SHIFT                  (0U)
-#define DMA_DCHPRI5_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
+#define DMA_DCHPRI5_CHPRI_SET(x)                 (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
+#define DMA_DCHPRI5_CHPRI DMA_DCHPRI5_CHPRI_MASK
 #define DMA_DCHPRI5_GRPPRI_MASK                  (0x30U)
 #define DMA_DCHPRI5_GRPPRI_SHIFT                 (4U)
-#define DMA_DCHPRI5_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)
+#define DMA_DCHPRI5_GRPPRI_SET(x)                (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)
+#define DMA_DCHPRI5_GRPPRI DMA_DCHPRI5_GRPPRI_MASK
 #define DMA_DCHPRI5_DPA_MASK                     (0x40U)
 #define DMA_DCHPRI5_DPA_SHIFT                    (6U)
-#define DMA_DCHPRI5_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
+#define DMA_DCHPRI5_DPA_SET(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
+#define DMA_DCHPRI5_DPA DMA_DCHPRI5_DPA_MASK
 #define DMA_DCHPRI5_ECP_MASK                     (0x80U)
 #define DMA_DCHPRI5_ECP_SHIFT                    (7U)
-#define DMA_DCHPRI5_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
+#define DMA_DCHPRI5_ECP_SET(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
+#define DMA_DCHPRI5_ECP DMA_DCHPRI5_ECP_MASK
 
 /*! @name DCHPRI4 - Channel n Priority Register */
 #define DMA_DCHPRI4_CHPRI_MASK                   (0xFU)
 #define DMA_DCHPRI4_CHPRI_SHIFT                  (0U)
-#define DMA_DCHPRI4_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
+#define DMA_DCHPRI4_CHPRI_SET(x)                 (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
+#define DMA_DCHPRI4_CHPRI DMA_DCHPRI4_CHPRI_MASK
 #define DMA_DCHPRI4_GRPPRI_MASK                  (0x30U)
 #define DMA_DCHPRI4_GRPPRI_SHIFT                 (4U)
-#define DMA_DCHPRI4_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)
+#define DMA_DCHPRI4_GRPPRI_SET(x)                (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)
+#define DMA_DCHPRI4_GRPPRI DMA_DCHPRI4_GRPPRI_MASK
 #define DMA_DCHPRI4_DPA_MASK                     (0x40U)
 #define DMA_DCHPRI4_DPA_SHIFT                    (6U)
-#define DMA_DCHPRI4_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
+#define DMA_DCHPRI4_DPA_SET(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
+#define DMA_DCHPRI4_DPA DMA_DCHPRI4_DPA_MASK
 #define DMA_DCHPRI4_ECP_MASK                     (0x80U)
 #define DMA_DCHPRI4_ECP_SHIFT                    (7U)
-#define DMA_DCHPRI4_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
+#define DMA_DCHPRI4_ECP_SET(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
+#define DMA_DCHPRI4_ECP DMA_DCHPRI4_ECP_MASK
 
 /*! @name DCHPRI11 - Channel n Priority Register */
 #define DMA_DCHPRI11_CHPRI_MASK                  (0xFU)
 #define DMA_DCHPRI11_CHPRI_SHIFT                 (0U)
-#define DMA_DCHPRI11_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
+#define DMA_DCHPRI11_CHPRI_SET(x)                (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
+#define DMA_DCHPRI11_CHPRI DMA_DCHPRI11_CHPRI_MASK
 #define DMA_DCHPRI11_GRPPRI_MASK                 (0x30U)
 #define DMA_DCHPRI11_GRPPRI_SHIFT                (4U)
-#define DMA_DCHPRI11_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)
+#define DMA_DCHPRI11_GRPPRI_SET(x)               (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)
+#define DMA_DCHPRI11_GRPPRI DMA_DCHPRI11_GRPPRI_MASK
 #define DMA_DCHPRI11_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI11_DPA_SHIFT                   (6U)
-#define DMA_DCHPRI11_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
+#define DMA_DCHPRI11_DPA_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
+#define DMA_DCHPRI11_DPA DMA_DCHPRI11_DPA_MASK
 #define DMA_DCHPRI11_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI11_ECP_SHIFT                   (7U)
-#define DMA_DCHPRI11_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
+#define DMA_DCHPRI11_ECP_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
+#define DMA_DCHPRI11_ECP DMA_DCHPRI11_ECP_MASK
 
 /*! @name DCHPRI10 - Channel n Priority Register */
 #define DMA_DCHPRI10_CHPRI_MASK                  (0xFU)
 #define DMA_DCHPRI10_CHPRI_SHIFT                 (0U)
-#define DMA_DCHPRI10_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
+#define DMA_DCHPRI10_CHPRI_SET(x)                (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
+#define DMA_DCHPRI10_CHPRI DMA_DCHPRI10_CHPRI_MASK
 #define DMA_DCHPRI10_GRPPRI_MASK                 (0x30U)
 #define DMA_DCHPRI10_GRPPRI_SHIFT                (4U)
-#define DMA_DCHPRI10_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)
+#define DMA_DCHPRI10_GRPPRI_SET(x)               (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)
+#define DMA_DCHPRI10_GRPPRI DMA_DCHPRI10_GRPPRI_MASK
 #define DMA_DCHPRI10_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI10_DPA_SHIFT                   (6U)
-#define DMA_DCHPRI10_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
+#define DMA_DCHPRI10_DPA_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
+#define DMA_DCHPRI10_DPA DMA_DCHPRI10_DPA_MASK
 #define DMA_DCHPRI10_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI10_ECP_SHIFT                   (7U)
-#define DMA_DCHPRI10_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
+#define DMA_DCHPRI10_ECP_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
+#define DMA_DCHPRI10_ECP DMA_DCHPRI10_ECP_MASK
 
 /*! @name DCHPRI9 - Channel n Priority Register */
 #define DMA_DCHPRI9_CHPRI_MASK                   (0xFU)
 #define DMA_DCHPRI9_CHPRI_SHIFT                  (0U)
-#define DMA_DCHPRI9_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
+#define DMA_DCHPRI9_CHPRI_SET(x)                 (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
+#define DMA_DCHPRI9_CHPRI DMA_DCHPRI9_CHPRI_MASK
 #define DMA_DCHPRI9_GRPPRI_MASK                  (0x30U)
 #define DMA_DCHPRI9_GRPPRI_SHIFT                 (4U)
-#define DMA_DCHPRI9_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)
+#define DMA_DCHPRI9_GRPPRI_SET(x)                (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)
+#define DMA_DCHPRI9_GRPPRI DMA_DCHPRI9_GRPPRI_MASK
 #define DMA_DCHPRI9_DPA_MASK                     (0x40U)
 #define DMA_DCHPRI9_DPA_SHIFT                    (6U)
-#define DMA_DCHPRI9_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
+#define DMA_DCHPRI9_DPA_SET(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
+#define DMA_DCHPRI9_DPA DMA_DCHPRI9_DPA_MASK
 #define DMA_DCHPRI9_ECP_MASK                     (0x80U)
 #define DMA_DCHPRI9_ECP_SHIFT                    (7U)
-#define DMA_DCHPRI9_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
+#define DMA_DCHPRI9_ECP_SET(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
+#define DMA_DCHPRI9_ECP DMA_DCHPRI9_ECP_MASK
 
 /*! @name DCHPRI8 - Channel n Priority Register */
 #define DMA_DCHPRI8_CHPRI_MASK                   (0xFU)
 #define DMA_DCHPRI8_CHPRI_SHIFT                  (0U)
-#define DMA_DCHPRI8_CHPRI(x)                     (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
+#define DMA_DCHPRI8_CHPRI_SET(x)                 (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
+#define DMA_DCHPRI8_CHPRI DMA_DCHPRI8_CHPRI_MASK
 #define DMA_DCHPRI8_GRPPRI_MASK                  (0x30U)
 #define DMA_DCHPRI8_GRPPRI_SHIFT                 (4U)
-#define DMA_DCHPRI8_GRPPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)
+#define DMA_DCHPRI8_GRPPRI_SET(x)                (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)
+#define DMA_DCHPRI8_GRPPRI DMA_DCHPRI8_GRPPRI_MASK
 #define DMA_DCHPRI8_DPA_MASK                     (0x40U)
 #define DMA_DCHPRI8_DPA_SHIFT                    (6U)
-#define DMA_DCHPRI8_DPA(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
+#define DMA_DCHPRI8_DPA_SET(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
+#define DMA_DCHPRI8_DPA DMA_DCHPRI8_DPA_MASK
 #define DMA_DCHPRI8_ECP_MASK                     (0x80U)
 #define DMA_DCHPRI8_ECP_SHIFT                    (7U)
-#define DMA_DCHPRI8_ECP(x)                       (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
+#define DMA_DCHPRI8_ECP_SET(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
+#define DMA_DCHPRI8_ECP DMA_DCHPRI8_ECP_MASK
 
 /*! @name DCHPRI15 - Channel n Priority Register */
 #define DMA_DCHPRI15_CHPRI_MASK                  (0xFU)
 #define DMA_DCHPRI15_CHPRI_SHIFT                 (0U)
-#define DMA_DCHPRI15_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
+#define DMA_DCHPRI15_CHPRI_SET(x)                (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
+#define DMA_DCHPRI15_CHPRI DMA_DCHPRI15_CHPRI_MASK
 #define DMA_DCHPRI15_GRPPRI_MASK                 (0x30U)
 #define DMA_DCHPRI15_GRPPRI_SHIFT                (4U)
-#define DMA_DCHPRI15_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)
+#define DMA_DCHPRI15_GRPPRI_SET(x)               (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)
+#define DMA_DCHPRI15_GRPPRI DMA_DCHPRI15_GRPPRI_MASK
 #define DMA_DCHPRI15_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI15_DPA_SHIFT                   (6U)
-#define DMA_DCHPRI15_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
+#define DMA_DCHPRI15_DPA_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
+#define DMA_DCHPRI15_DPA DMA_DCHPRI15_DPA_MASK
 #define DMA_DCHPRI15_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI15_ECP_SHIFT                   (7U)
-#define DMA_DCHPRI15_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
+#define DMA_DCHPRI15_ECP_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
+#define DMA_DCHPRI15_ECP DMA_DCHPRI15_ECP_MASK
 
 /*! @name DCHPRI14 - Channel n Priority Register */
 #define DMA_DCHPRI14_CHPRI_MASK                  (0xFU)
 #define DMA_DCHPRI14_CHPRI_SHIFT                 (0U)
-#define DMA_DCHPRI14_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
+#define DMA_DCHPRI14_CHPRI_SET(x)                (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
+#define DMA_DCHPRI14_CHPRI DMA_DCHPRI14_CHPRI_MASK
 #define DMA_DCHPRI14_GRPPRI_MASK                 (0x30U)
 #define DMA_DCHPRI14_GRPPRI_SHIFT                (4U)
-#define DMA_DCHPRI14_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)
+#define DMA_DCHPRI14_GRPPRI_SET(x)               (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)
+#define DMA_DCHPRI14_GRPPRI DMA_DCHPRI14_GRPPRI_MASK
 #define DMA_DCHPRI14_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI14_DPA_SHIFT                   (6U)
-#define DMA_DCHPRI14_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
+#define DMA_DCHPRI14_DPA_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
+#define DMA_DCHPRI14_DPA DMA_DCHPRI14_DPA_MASK
 #define DMA_DCHPRI14_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI14_ECP_SHIFT                   (7U)
-#define DMA_DCHPRI14_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
+#define DMA_DCHPRI14_ECP_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
+#define DMA_DCHPRI14_ECP DMA_DCHPRI14_ECP_MASK
 
 /*! @name DCHPRI13 - Channel n Priority Register */
 #define DMA_DCHPRI13_CHPRI_MASK                  (0xFU)
 #define DMA_DCHPRI13_CHPRI_SHIFT                 (0U)
-#define DMA_DCHPRI13_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
+#define DMA_DCHPRI13_CHPRI_SET(x)                (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
+#define DMA_DCHPRI13_CHPRI DMA_DCHPRI13_CHPRI_MASK
 #define DMA_DCHPRI13_GRPPRI_MASK                 (0x30U)
 #define DMA_DCHPRI13_GRPPRI_SHIFT                (4U)
-#define DMA_DCHPRI13_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)
+#define DMA_DCHPRI13_GRPPRI_SET(x)               (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)
+#define DMA_DCHPRI13_GRPPRI DMA_DCHPRI13_GRPPRI_MASK
 #define DMA_DCHPRI13_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI13_DPA_SHIFT                   (6U)
-#define DMA_DCHPRI13_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
+#define DMA_DCHPRI13_DPA_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
+#define DMA_DCHPRI13_DPA DMA_DCHPRI13_DPA_MASK
 #define DMA_DCHPRI13_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI13_ECP_SHIFT                   (7U)
-#define DMA_DCHPRI13_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
+#define DMA_DCHPRI13_ECP_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
+#define DMA_DCHPRI13_ECP DMA_DCHPRI13_ECP_MASK
 
 /*! @name DCHPRI12 - Channel n Priority Register */
 #define DMA_DCHPRI12_CHPRI_MASK                  (0xFU)
 #define DMA_DCHPRI12_CHPRI_SHIFT                 (0U)
-#define DMA_DCHPRI12_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
+#define DMA_DCHPRI12_CHPRI_SET(x)                (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
+#define DMA_DCHPRI12_CHPRI DMA_DCHPRI12_CHPRI_MASK
 #define DMA_DCHPRI12_GRPPRI_MASK                 (0x30U)
 #define DMA_DCHPRI12_GRPPRI_SHIFT                (4U)
-#define DMA_DCHPRI12_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)
+#define DMA_DCHPRI12_GRPPRI_SET(x)               (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)
+#define DMA_DCHPRI12_GRPPRI DMA_DCHPRI12_GRPPRI_MASK
 #define DMA_DCHPRI12_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI12_DPA_SHIFT                   (6U)
-#define DMA_DCHPRI12_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
+#define DMA_DCHPRI12_DPA_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
+#define DMA_DCHPRI12_DPA DMA_DCHPRI12_DPA_MASK
 #define DMA_DCHPRI12_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI12_ECP_SHIFT                   (7U)
-#define DMA_DCHPRI12_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
+#define DMA_DCHPRI12_ECP_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
+#define DMA_DCHPRI12_ECP DMA_DCHPRI12_ECP_MASK
 
 /*! @name DCHPRI19 - Channel n Priority Register */
 #define DMA_DCHPRI19_CHPRI_MASK                  (0xFU)
 #define DMA_DCHPRI19_CHPRI_SHIFT                 (0U)
-#define DMA_DCHPRI19_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)
+#define DMA_DCHPRI19_CHPRI_SET(x)                (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)
+#define DMA_DCHPRI19_CHPRI DMA_DCHPRI19_CHPRI_MASK
 #define DMA_DCHPRI19_GRPPRI_MASK                 (0x30U)
 #define DMA_DCHPRI19_GRPPRI_SHIFT                (4U)
-#define DMA_DCHPRI19_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)
+#define DMA_DCHPRI19_GRPPRI_SET(x)               (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)
+#define DMA_DCHPRI19_GRPPRI DMA_DCHPRI19_GRPPRI_MASK
 #define DMA_DCHPRI19_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI19_DPA_SHIFT                   (6U)
-#define DMA_DCHPRI19_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)
+#define DMA_DCHPRI19_DPA_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)
+#define DMA_DCHPRI19_DPA DMA_DCHPRI19_DPA_MASK
 #define DMA_DCHPRI19_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI19_ECP_SHIFT                   (7U)
-#define DMA_DCHPRI19_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)
+#define DMA_DCHPRI19_ECP_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)
+#define DMA_DCHPRI19_ECP DMA_DCHPRI19_ECP_MASK
 
 /*! @name DCHPRI18 - Channel n Priority Register */
 #define DMA_DCHPRI18_CHPRI_MASK                  (0xFU)
 #define DMA_DCHPRI18_CHPRI_SHIFT                 (0U)
-#define DMA_DCHPRI18_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)
+#define DMA_DCHPRI18_CHPRI_SET(x)                (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)
+#define DMA_DCHPRI18_CHPRI DMA_DCHPRI18_CHPRI_MASK
 #define DMA_DCHPRI18_GRPPRI_MASK                 (0x30U)
 #define DMA_DCHPRI18_GRPPRI_SHIFT                (4U)
-#define DMA_DCHPRI18_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)
+#define DMA_DCHPRI18_GRPPRI_SET(x)               (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)
+#define DMA_DCHPRI18_GRPPRI DMA_DCHPRI18_GRPPRI_MASK
 #define DMA_DCHPRI18_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI18_DPA_SHIFT                   (6U)
-#define DMA_DCHPRI18_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)
+#define DMA_DCHPRI18_DPA_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)
+#define DMA_DCHPRI18_DPA DMA_DCHPRI18_DPA_MASK
 #define DMA_DCHPRI18_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI18_ECP_SHIFT                   (7U)
-#define DMA_DCHPRI18_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)
+#define DMA_DCHPRI18_ECP_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)
+#define DMA_DCHPRI18_ECP DMA_DCHPRI18_ECP_MASK
 
 /*! @name DCHPRI17 - Channel n Priority Register */
 #define DMA_DCHPRI17_CHPRI_MASK                  (0xFU)
 #define DMA_DCHPRI17_CHPRI_SHIFT                 (0U)
-#define DMA_DCHPRI17_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)
+#define DMA_DCHPRI17_CHPRI_SET(x)                (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)
+#define DMA_DCHPRI17_CHPRI DMA_DCHPRI17_CHPRI_MASK
 #define DMA_DCHPRI17_GRPPRI_MASK                 (0x30U)
 #define DMA_DCHPRI17_GRPPRI_SHIFT                (4U)
-#define DMA_DCHPRI17_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)
+#define DMA_DCHPRI17_GRPPRI_SET(x)               (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)
+#define DMA_DCHPRI17_GRPPRI DMA_DCHPRI17_GRPPRI_MASK
 #define DMA_DCHPRI17_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI17_DPA_SHIFT                   (6U)
-#define DMA_DCHPRI17_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)
+#define DMA_DCHPRI17_DPA_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)
+#define DMA_DCHPRI17_DPA DMA_DCHPRI17_DPA_MASK
 #define DMA_DCHPRI17_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI17_ECP_SHIFT                   (7U)
-#define DMA_DCHPRI17_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)
+#define DMA_DCHPRI17_ECP_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)
+#define DMA_DCHPRI17_ECP DMA_DCHPRI17_ECP_MASK
 
 /*! @name DCHPRI16 - Channel n Priority Register */
 #define DMA_DCHPRI16_CHPRI_MASK                  (0xFU)
 #define DMA_DCHPRI16_CHPRI_SHIFT                 (0U)
-#define DMA_DCHPRI16_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)
+#define DMA_DCHPRI16_CHPRI_SET(x)                (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)
+#define DMA_DCHPRI16_CHPRI DMA_DCHPRI16_CHPRI_MASK
 #define DMA_DCHPRI16_GRPPRI_MASK                 (0x30U)
 #define DMA_DCHPRI16_GRPPRI_SHIFT                (4U)
-#define DMA_DCHPRI16_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)
+#define DMA_DCHPRI16_GRPPRI_SET(x)               (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)
+#define DMA_DCHPRI16_GRPPRI DMA_DCHPRI16_GRPPRI_MASK
 #define DMA_DCHPRI16_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI16_DPA_SHIFT                   (6U)
-#define DMA_DCHPRI16_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)
+#define DMA_DCHPRI16_DPA_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)
+#define DMA_DCHPRI16_DPA DMA_DCHPRI16_DPA_MASK
 #define DMA_DCHPRI16_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI16_ECP_SHIFT                   (7U)
-#define DMA_DCHPRI16_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)
+#define DMA_DCHPRI16_ECP_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)
+#define DMA_DCHPRI16_ECP DMA_DCHPRI16_ECP_MASK
 
 /*! @name DCHPRI23 - Channel n Priority Register */
 #define DMA_DCHPRI23_CHPRI_MASK                  (0xFU)
 #define DMA_DCHPRI23_CHPRI_SHIFT                 (0U)
-#define DMA_DCHPRI23_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)
+#define DMA_DCHPRI23_CHPRI_SET(x)                (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)
+#define DMA_DCHPRI23_CHPRI DMA_DCHPRI23_CHPRI_MASK
 #define DMA_DCHPRI23_GRPPRI_MASK                 (0x30U)
 #define DMA_DCHPRI23_GRPPRI_SHIFT                (4U)
-#define DMA_DCHPRI23_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)
+#define DMA_DCHPRI23_GRPPRI_SET(x)               (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)
+#define DMA_DCHPRI23_GRPPRI DMA_DCHPRI23_GRPPRI_MASK
 #define DMA_DCHPRI23_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI23_DPA_SHIFT                   (6U)
-#define DMA_DCHPRI23_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)
+#define DMA_DCHPRI23_DPA_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)
+#define DMA_DCHPRI23_DPA DMA_DCHPRI23_DPA_MASK
 #define DMA_DCHPRI23_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI23_ECP_SHIFT                   (7U)
-#define DMA_DCHPRI23_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)
+#define DMA_DCHPRI23_ECP_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)
+#define DMA_DCHPRI23_ECP DMA_DCHPRI23_ECP_MASK
 
 /*! @name DCHPRI22 - Channel n Priority Register */
 #define DMA_DCHPRI22_CHPRI_MASK                  (0xFU)
 #define DMA_DCHPRI22_CHPRI_SHIFT                 (0U)
-#define DMA_DCHPRI22_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)
+#define DMA_DCHPRI22_CHPRI_SET(x)                (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)
+#define DMA_DCHPRI22_CHPRI DMA_DCHPRI22_CHPRI_MASK
 #define DMA_DCHPRI22_GRPPRI_MASK                 (0x30U)
 #define DMA_DCHPRI22_GRPPRI_SHIFT                (4U)
-#define DMA_DCHPRI22_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)
+#define DMA_DCHPRI22_GRPPRI_SET(x)               (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)
+#define DMA_DCHPRI22_GRPPRI DMA_DCHPRI22_GRPPRI_MASK
 #define DMA_DCHPRI22_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI22_DPA_SHIFT                   (6U)
-#define DMA_DCHPRI22_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)
+#define DMA_DCHPRI22_DPA_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)
+#define DMA_DCHPRI22_DPA DMA_DCHPRI22_DPA_MASK
 #define DMA_DCHPRI22_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI22_ECP_SHIFT                   (7U)
-#define DMA_DCHPRI22_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)
+#define DMA_DCHPRI22_ECP_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)
+#define DMA_DCHPRI22_ECP DMA_DCHPRI22_ECP_MASK
 
 /*! @name DCHPRI21 - Channel n Priority Register */
 #define DMA_DCHPRI21_CHPRI_MASK                  (0xFU)
 #define DMA_DCHPRI21_CHPRI_SHIFT                 (0U)
-#define DMA_DCHPRI21_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)
+#define DMA_DCHPRI21_CHPRI_SET(x)                (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)
+#define DMA_DCHPRI21_CHPRI DMA_DCHPRI21_CHPRI_MASK
 #define DMA_DCHPRI21_GRPPRI_MASK                 (0x30U)
 #define DMA_DCHPRI21_GRPPRI_SHIFT                (4U)
-#define DMA_DCHPRI21_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)
+#define DMA_DCHPRI21_GRPPRI_SET(x)               (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)
+#define DMA_DCHPRI21_GRPPRI DMA_DCHPRI21_GRPPRI_MASK
 #define DMA_DCHPRI21_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI21_DPA_SHIFT                   (6U)
-#define DMA_DCHPRI21_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)
+#define DMA_DCHPRI21_DPA_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)
+#define DMA_DCHPRI21_DPA DMA_DCHPRI21_DPA_MASK
 #define DMA_DCHPRI21_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI21_ECP_SHIFT                   (7U)
-#define DMA_DCHPRI21_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)
+#define DMA_DCHPRI21_ECP_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)
+#define DMA_DCHPRI21_ECP DMA_DCHPRI21_ECP_MASK
 
 /*! @name DCHPRI20 - Channel n Priority Register */
 #define DMA_DCHPRI20_CHPRI_MASK                  (0xFU)
 #define DMA_DCHPRI20_CHPRI_SHIFT                 (0U)
-#define DMA_DCHPRI20_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)
+#define DMA_DCHPRI20_CHPRI_SET(x)                (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)
+#define DMA_DCHPRI20_CHPRI DMA_DCHPRI20_CHPRI_MASK
 #define DMA_DCHPRI20_GRPPRI_MASK                 (0x30U)
 #define DMA_DCHPRI20_GRPPRI_SHIFT                (4U)
-#define DMA_DCHPRI20_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)
+#define DMA_DCHPRI20_GRPPRI_SET(x)               (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)
+#define DMA_DCHPRI20_GRPPRI DMA_DCHPRI20_GRPPRI_MASK
 #define DMA_DCHPRI20_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI20_DPA_SHIFT                   (6U)
-#define DMA_DCHPRI20_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)
+#define DMA_DCHPRI20_DPA_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)
+#define DMA_DCHPRI20_DPA DMA_DCHPRI20_DPA_MASK
 #define DMA_DCHPRI20_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI20_ECP_SHIFT                   (7U)
-#define DMA_DCHPRI20_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)
+#define DMA_DCHPRI20_ECP_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)
+#define DMA_DCHPRI20_ECP DMA_DCHPRI20_ECP_MASK
 
 /*! @name DCHPRI27 - Channel n Priority Register */
 #define DMA_DCHPRI27_CHPRI_MASK                  (0xFU)
 #define DMA_DCHPRI27_CHPRI_SHIFT                 (0U)
-#define DMA_DCHPRI27_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)
+#define DMA_DCHPRI27_CHPRI_SET(x)                (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)
+#define DMA_DCHPRI27_CHPRI DMA_DCHPRI27_CHPRI_MASK
 #define DMA_DCHPRI27_GRPPRI_MASK                 (0x30U)
 #define DMA_DCHPRI27_GRPPRI_SHIFT                (4U)
-#define DMA_DCHPRI27_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)
+#define DMA_DCHPRI27_GRPPRI_SET(x)               (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)
+#define DMA_DCHPRI27_GRPPRI DMA_DCHPRI27_GRPPRI_MASK
 #define DMA_DCHPRI27_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI27_DPA_SHIFT                   (6U)
-#define DMA_DCHPRI27_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)
+#define DMA_DCHPRI27_DPA_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)
+#define DMA_DCHPRI27_DPA DMA_DCHPRI27_DPA_MASK
 #define DMA_DCHPRI27_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI27_ECP_SHIFT                   (7U)
-#define DMA_DCHPRI27_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)
+#define DMA_DCHPRI27_ECP_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)
+#define DMA_DCHPRI27_ECP DMA_DCHPRI27_ECP_MASK
 
 /*! @name DCHPRI26 - Channel n Priority Register */
 #define DMA_DCHPRI26_CHPRI_MASK                  (0xFU)
 #define DMA_DCHPRI26_CHPRI_SHIFT                 (0U)
-#define DMA_DCHPRI26_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)
+#define DMA_DCHPRI26_CHPRI_SET(x)                (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)
+#define DMA_DCHPRI26_CHPRI DMA_DCHPRI26_CHPRI_MASK
 #define DMA_DCHPRI26_GRPPRI_MASK                 (0x30U)
 #define DMA_DCHPRI26_GRPPRI_SHIFT                (4U)
-#define DMA_DCHPRI26_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)
+#define DMA_DCHPRI26_GRPPRI_SET(x)               (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)
+#define DMA_DCHPRI26_GRPPRI DMA_DCHPRI26_GRPPRI_MASK
 #define DMA_DCHPRI26_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI26_DPA_SHIFT                   (6U)
-#define DMA_DCHPRI26_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)
+#define DMA_DCHPRI26_DPA_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)
+#define DMA_DCHPRI26_DPA DMA_DCHPRI26_DPA_MASK
 #define DMA_DCHPRI26_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI26_ECP_SHIFT                   (7U)
-#define DMA_DCHPRI26_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)
+#define DMA_DCHPRI26_ECP_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)
+#define DMA_DCHPRI26_ECP DMA_DCHPRI26_ECP_MASK
 
 /*! @name DCHPRI25 - Channel n Priority Register */
 #define DMA_DCHPRI25_CHPRI_MASK                  (0xFU)
 #define DMA_DCHPRI25_CHPRI_SHIFT                 (0U)
-#define DMA_DCHPRI25_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)
+#define DMA_DCHPRI25_CHPRI_SET(x)                (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)
+#define DMA_DCHPRI25_CHPRI DMA_DCHPRI25_CHPRI_MASK
 #define DMA_DCHPRI25_GRPPRI_MASK                 (0x30U)
 #define DMA_DCHPRI25_GRPPRI_SHIFT                (4U)
-#define DMA_DCHPRI25_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)
+#define DMA_DCHPRI25_GRPPRI_SET(x)               (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)
+#define DMA_DCHPRI25_GRPPRI DMA_DCHPRI25_GRPPRI_MASK
 #define DMA_DCHPRI25_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI25_DPA_SHIFT                   (6U)
-#define DMA_DCHPRI25_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)
+#define DMA_DCHPRI25_DPA_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)
+#define DMA_DCHPRI25_DPA DMA_DCHPRI25_DPA_MASK
 #define DMA_DCHPRI25_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI25_ECP_SHIFT                   (7U)
-#define DMA_DCHPRI25_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)
+#define DMA_DCHPRI25_ECP_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)
+#define DMA_DCHPRI25_ECP DMA_DCHPRI25_ECP_MASK
 
 /*! @name DCHPRI24 - Channel n Priority Register */
 #define DMA_DCHPRI24_CHPRI_MASK                  (0xFU)
 #define DMA_DCHPRI24_CHPRI_SHIFT                 (0U)
-#define DMA_DCHPRI24_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)
+#define DMA_DCHPRI24_CHPRI_SET(x)                (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)
+#define DMA_DCHPRI24_CHPRI DMA_DCHPRI24_CHPRI_MASK
 #define DMA_DCHPRI24_GRPPRI_MASK                 (0x30U)
 #define DMA_DCHPRI24_GRPPRI_SHIFT                (4U)
-#define DMA_DCHPRI24_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)
+#define DMA_DCHPRI24_GRPPRI_SET(x)               (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)
+#define DMA_DCHPRI24_GRPPRI DMA_DCHPRI24_GRPPRI_MASK
 #define DMA_DCHPRI24_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI24_DPA_SHIFT                   (6U)
-#define DMA_DCHPRI24_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)
+#define DMA_DCHPRI24_DPA_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)
+#define DMA_DCHPRI24_DPA DMA_DCHPRI24_DPA_MASK
 #define DMA_DCHPRI24_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI24_ECP_SHIFT                   (7U)
-#define DMA_DCHPRI24_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)
+#define DMA_DCHPRI24_ECP_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)
+#define DMA_DCHPRI24_ECP DMA_DCHPRI24_ECP_MASK
 
 /*! @name DCHPRI31 - Channel n Priority Register */
 #define DMA_DCHPRI31_CHPRI_MASK                  (0xFU)
 #define DMA_DCHPRI31_CHPRI_SHIFT                 (0U)
-#define DMA_DCHPRI31_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
+#define DMA_DCHPRI31_CHPRI_SET(x)                (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
+#define DMA_DCHPRI31_CHPRI DMA_DCHPRI31_CHPRI_MASK
 #define DMA_DCHPRI31_GRPPRI_MASK                 (0x30U)
 #define DMA_DCHPRI31_GRPPRI_SHIFT                (4U)
-#define DMA_DCHPRI31_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)
+#define DMA_DCHPRI31_GRPPRI_SET(x)               (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)
+#define DMA_DCHPRI31_GRPPRI DMA_DCHPRI31_GRPPRI_MASK
 #define DMA_DCHPRI31_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI31_DPA_SHIFT                   (6U)
-#define DMA_DCHPRI31_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)
+#define DMA_DCHPRI31_DPA_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)
+#define DMA_DCHPRI31_DPA DMA_DCHPRI31_DPA_MASK
 #define DMA_DCHPRI31_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI31_ECP_SHIFT                   (7U)
-#define DMA_DCHPRI31_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)
+#define DMA_DCHPRI31_ECP_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)
+#define DMA_DCHPRI31_ECP DMA_DCHPRI31_ECP_MASK
 
 /*! @name DCHPRI30 - Channel n Priority Register */
 #define DMA_DCHPRI30_CHPRI_MASK                  (0xFU)
 #define DMA_DCHPRI30_CHPRI_SHIFT                 (0U)
-#define DMA_DCHPRI30_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)
+#define DMA_DCHPRI30_CHPRI_SET(x)                (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)
+#define DMA_DCHPRI30_CHPRI DMA_DCHPRI30_CHPRI_MASK
 #define DMA_DCHPRI30_GRPPRI_MASK                 (0x30U)
 #define DMA_DCHPRI30_GRPPRI_SHIFT                (4U)
-#define DMA_DCHPRI30_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)
+#define DMA_DCHPRI30_GRPPRI_SET(x)               (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)
+#define DMA_DCHPRI30_GRPPRI DMA_DCHPRI30_GRPPRI_MASK
 #define DMA_DCHPRI30_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI30_DPA_SHIFT                   (6U)
-#define DMA_DCHPRI30_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)
+#define DMA_DCHPRI30_DPA_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)
+#define DMA_DCHPRI30_DPA DMA_DCHPRI30_DPA_MASK
 #define DMA_DCHPRI30_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI30_ECP_SHIFT                   (7U)
-#define DMA_DCHPRI30_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)
+#define DMA_DCHPRI30_ECP_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)
+#define DMA_DCHPRI30_ECP DMA_DCHPRI30_ECP_MASK
 
 /*! @name DCHPRI29 - Channel n Priority Register */
 #define DMA_DCHPRI29_CHPRI_MASK                  (0xFU)
 #define DMA_DCHPRI29_CHPRI_SHIFT                 (0U)
-#define DMA_DCHPRI29_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)
+#define DMA_DCHPRI29_CHPRI_SET(x)                (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)
+#define DMA_DCHPRI29_CHPRI DMA_DCHPRI29_CHPRI_MASK
 #define DMA_DCHPRI29_GRPPRI_MASK                 (0x30U)
 #define DMA_DCHPRI29_GRPPRI_SHIFT                (4U)
-#define DMA_DCHPRI29_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)
+#define DMA_DCHPRI29_GRPPRI_SET(x)               (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)
+#define DMA_DCHPRI29_GRPPRI DMA_DCHPRI29_GRPPRI_MASK
 #define DMA_DCHPRI29_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI29_DPA_SHIFT                   (6U)
-#define DMA_DCHPRI29_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)
+#define DMA_DCHPRI29_DPA_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)
+#define DMA_DCHPRI29_DPA DMA_DCHPRI29_DPA_MASK
 #define DMA_DCHPRI29_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI29_ECP_SHIFT                   (7U)
-#define DMA_DCHPRI29_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)
+#define DMA_DCHPRI29_ECP_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)
+#define DMA_DCHPRI29_ECP DMA_DCHPRI29_ECP_MASK
 
 /*! @name DCHPRI28 - Channel n Priority Register */
 #define DMA_DCHPRI28_CHPRI_MASK                  (0xFU)
 #define DMA_DCHPRI28_CHPRI_SHIFT                 (0U)
-#define DMA_DCHPRI28_CHPRI(x)                    (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)
+#define DMA_DCHPRI28_CHPRI_SET(x)                (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)
+#define DMA_DCHPRI28_CHPRI DMA_DCHPRI28_CHPRI_MASK
 #define DMA_DCHPRI28_GRPPRI_MASK                 (0x30U)
 #define DMA_DCHPRI28_GRPPRI_SHIFT                (4U)
-#define DMA_DCHPRI28_GRPPRI(x)                   (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)
+#define DMA_DCHPRI28_GRPPRI_SET(x)               (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)
+#define DMA_DCHPRI28_GRPPRI DMA_DCHPRI28_GRPPRI_MASK
 #define DMA_DCHPRI28_DPA_MASK                    (0x40U)
 #define DMA_DCHPRI28_DPA_SHIFT                   (6U)
-#define DMA_DCHPRI28_DPA(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)
+#define DMA_DCHPRI28_DPA_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)
+#define DMA_DCHPRI28_DPA DMA_DCHPRI28_DPA_MASK
 #define DMA_DCHPRI28_ECP_MASK                    (0x80U)
 #define DMA_DCHPRI28_ECP_SHIFT                   (7U)
-#define DMA_DCHPRI28_ECP(x)                      (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)
+#define DMA_DCHPRI28_ECP_SET(x)                  (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)
+#define DMA_DCHPRI28_ECP DMA_DCHPRI28_ECP_MASK
 
 /*! @name SADDR - TCD Source Address */
 #define DMA_SADDR_SADDR_MASK                     (0xFFFFFFFFU)
 #define DMA_SADDR_SADDR_SHIFT                    (0U)
-#define DMA_SADDR_SADDR(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
+#define DMA_SADDR_SADDR_SET(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
+#define DMA_SADDR_SADDR DMA_SADDR_SADDR_MASK
 
 /* The count of DMA_SADDR */
 #define DMA_SADDR_COUNT                          (32U)
@@ -5035,7 +6193,8 @@ typedef struct {
 /*! @name SOFF - TCD Signed Source Address Offset */
 #define DMA_SOFF_SOFF_MASK                       (0xFFFFU)
 #define DMA_SOFF_SOFF_SHIFT                      (0U)
-#define DMA_SOFF_SOFF(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
+#define DMA_SOFF_SOFF_SET(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
+#define DMA_SOFF_SOFF DMA_SOFF_SOFF_MASK
 
 /* The count of DMA_SOFF */
 #define DMA_SOFF_COUNT                           (32U)
@@ -5043,16 +6202,16 @@ typedef struct {
 /*! @name ATTR - TCD Transfer Attributes */
 #define DMA_ATTR_DSIZE_MASK                      (0x7U)
 #define DMA_ATTR_DSIZE_SHIFT                     (0U)
-#define DMA_ATTR_DSIZE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
+#define DMA_ATTR_DSIZE(x)                    (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
 #define DMA_ATTR_DMOD_MASK                       (0xF8U)
 #define DMA_ATTR_DMOD_SHIFT                      (3U)
-#define DMA_ATTR_DMOD(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
+#define DMA_ATTR_DMOD(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
 #define DMA_ATTR_SSIZE_MASK                      (0x700U)
 #define DMA_ATTR_SSIZE_SHIFT                     (8U)
-#define DMA_ATTR_SSIZE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
+#define DMA_ATTR_SSIZE(x)                    (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
 #define DMA_ATTR_SMOD_MASK                       (0xF800U)
 #define DMA_ATTR_SMOD_SHIFT                      (11U)
-#define DMA_ATTR_SMOD(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
+#define DMA_ATTR_SMOD(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
 
 /* The count of DMA_ATTR */
 #define DMA_ATTR_COUNT                           (32U)
@@ -5060,7 +6219,8 @@ typedef struct {
 /*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */
 #define DMA_NBYTES_MLNO_NBYTES_MASK              (0xFFFFFFFFU)
 #define DMA_NBYTES_MLNO_NBYTES_SHIFT             (0U)
-#define DMA_NBYTES_MLNO_NBYTES(x)                (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
+#define DMA_NBYTES_MLNO_NBYTES_SET(x)            (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
+#define DMA_NBYTES_MLNO_NBYTES DMA_NBYTES_MLNO_NBYTES_MASK
 
 /* The count of DMA_NBYTES_MLNO */
 #define DMA_NBYTES_MLNO_COUNT                    (32U)
@@ -5068,13 +6228,16 @@ typedef struct {
 /*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */
 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK           (0x3FFFFFFFU)
 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT          (0U)
-#define DMA_NBYTES_MLOFFNO_NBYTES(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFNO_NBYTES_SET(x)         (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFNO_NBYTES DMA_NBYTES_MLOFFNO_NBYTES_MASK
 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK            (0x40000000U)
 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT           (30U)
-#define DMA_NBYTES_MLOFFNO_DMLOE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
+#define DMA_NBYTES_MLOFFNO_DMLOE_SET(x)          (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
+#define DMA_NBYTES_MLOFFNO_DMLOE DMA_NBYTES_MLOFFNO_DMLOE_MASK
 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK            (0x80000000U)
 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT           (31U)
-#define DMA_NBYTES_MLOFFNO_SMLOE(x)              (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
+#define DMA_NBYTES_MLOFFNO_SMLOE_SET(x)          (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
+#define DMA_NBYTES_MLOFFNO_SMLOE DMA_NBYTES_MLOFFNO_SMLOE_MASK
 
 /* The count of DMA_NBYTES_MLOFFNO */
 #define DMA_NBYTES_MLOFFNO_COUNT                 (32U)
@@ -5082,16 +6245,20 @@ typedef struct {
 /*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */
 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK          (0x3FFU)
 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT         (0U)
-#define DMA_NBYTES_MLOFFYES_NBYTES(x)            (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFYES_NBYTES_SET(x)        (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
+#define DMA_NBYTES_MLOFFYES_NBYTES DMA_NBYTES_MLOFFYES_NBYTES_MASK
 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK           (0x3FFFFC00U)
 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT          (10U)
-#define DMA_NBYTES_MLOFFYES_MLOFF(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
+#define DMA_NBYTES_MLOFFYES_MLOFF_SET(x)         (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
+#define DMA_NBYTES_MLOFFYES_MLOFF DMA_NBYTES_MLOFFYES_MLOFF_MASK
 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK           (0x40000000U)
 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT          (30U)
-#define DMA_NBYTES_MLOFFYES_DMLOE(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
+#define DMA_NBYTES_MLOFFYES_DMLOE_SET(x)         (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
+#define DMA_NBYTES_MLOFFYES_DMLOE DMA_NBYTES_MLOFFYES_DMLOE_MASK
 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK           (0x80000000U)
 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT          (31U)
-#define DMA_NBYTES_MLOFFYES_SMLOE(x)             (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
+#define DMA_NBYTES_MLOFFYES_SMLOE_SET(x)         (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
+#define DMA_NBYTES_MLOFFYES_SMLOE DMA_NBYTES_MLOFFYES_SMLOE_MASK
 
 /* The count of DMA_NBYTES_MLOFFYES */
 #define DMA_NBYTES_MLOFFYES_COUNT                (32U)
@@ -5099,7 +6266,8 @@ typedef struct {
 /*! @name SLAST - TCD Last Source Address Adjustment */
 #define DMA_SLAST_SLAST_MASK                     (0xFFFFFFFFU)
 #define DMA_SLAST_SLAST_SHIFT                    (0U)
-#define DMA_SLAST_SLAST(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
+#define DMA_SLAST_SLAST_SET(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
+#define DMA_SLAST_SLAST DMA_SLAST_SLAST_MASK
 
 /* The count of DMA_SLAST */
 #define DMA_SLAST_COUNT                          (32U)
@@ -5107,7 +6275,8 @@ typedef struct {
 /*! @name DADDR - TCD Destination Address */
 #define DMA_DADDR_DADDR_MASK                     (0xFFFFFFFFU)
 #define DMA_DADDR_DADDR_SHIFT                    (0U)
-#define DMA_DADDR_DADDR(x)                       (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
+#define DMA_DADDR_DADDR_SET(x)                   (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
+#define DMA_DADDR_DADDR DMA_DADDR_DADDR_MASK
 
 /* The count of DMA_DADDR */
 #define DMA_DADDR_COUNT                          (32U)
@@ -5115,7 +6284,8 @@ typedef struct {
 /*! @name DOFF - TCD Signed Destination Address Offset */
 #define DMA_DOFF_DOFF_MASK                       (0xFFFFU)
 #define DMA_DOFF_DOFF_SHIFT                      (0U)
-#define DMA_DOFF_DOFF(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
+#define DMA_DOFF_DOFF_SET(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
+#define DMA_DOFF_DOFF DMA_DOFF_DOFF_MASK
 
 /* The count of DMA_DOFF */
 #define DMA_DOFF_COUNT                           (32U)
@@ -5123,10 +6293,12 @@ typedef struct {
 /*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
 #define DMA_CITER_ELINKNO_CITER_MASK             (0x7FFFU)
 #define DMA_CITER_ELINKNO_CITER_SHIFT            (0U)
-#define DMA_CITER_ELINKNO_CITER(x)               (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
+#define DMA_CITER_ELINKNO_CITER_SET(x)           (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
+#define DMA_CITER_ELINKNO_CITER DMA_CITER_ELINKNO_CITER_MASK
 #define DMA_CITER_ELINKNO_ELINK_MASK             (0x8000U)
 #define DMA_CITER_ELINKNO_ELINK_SHIFT            (15U)
-#define DMA_CITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
+#define DMA_CITER_ELINKNO_ELINK_SET(x)           (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
+#define DMA_CITER_ELINKNO_ELINK DMA_CITER_ELINKNO_ELINK_MASK
 
 /* The count of DMA_CITER_ELINKNO */
 #define DMA_CITER_ELINKNO_COUNT                  (32U)
@@ -5134,13 +6306,16 @@ typedef struct {
 /*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
 #define DMA_CITER_ELINKYES_CITER_MASK            (0x1FFU)
 #define DMA_CITER_ELINKYES_CITER_SHIFT           (0U)
-#define DMA_CITER_ELINKYES_CITER(x)              (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
+#define DMA_CITER_ELINKYES_CITER_SET(x)          (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
+#define DMA_CITER_ELINKYES_CITER DMA_CITER_ELINKYES_CITER_MASK
 #define DMA_CITER_ELINKYES_LINKCH_MASK           (0x3E00U)
 #define DMA_CITER_ELINKYES_LINKCH_SHIFT          (9U)
-#define DMA_CITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
+#define DMA_CITER_ELINKYES_LINKCH_SET(x)         (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
+#define DMA_CITER_ELINKYES_LINKCH DMA_CITER_ELINKYES_LINKCH_MASK
 #define DMA_CITER_ELINKYES_ELINK_MASK            (0x8000U)
 #define DMA_CITER_ELINKYES_ELINK_SHIFT           (15U)
-#define DMA_CITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
+#define DMA_CITER_ELINKYES_ELINK_SET(x)          (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
+#define DMA_CITER_ELINKYES_ELINK DMA_CITER_ELINKYES_ELINK_MASK
 
 /* The count of DMA_CITER_ELINKYES */
 #define DMA_CITER_ELINKYES_COUNT                 (32U)
@@ -5148,7 +6323,8 @@ typedef struct {
 /*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
 #define DMA_DLAST_SGA_DLASTSGA_MASK              (0xFFFFFFFFU)
 #define DMA_DLAST_SGA_DLASTSGA_SHIFT             (0U)
-#define DMA_DLAST_SGA_DLASTSGA(x)                (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
+#define DMA_DLAST_SGA_DLASTSGA_SET(x)            (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
+#define DMA_DLAST_SGA_DLASTSGA DMA_DLAST_SGA_DLASTSGA_MASK
 
 /* The count of DMA_DLAST_SGA */
 #define DMA_DLAST_SGA_COUNT                      (32U)
@@ -5156,34 +6332,44 @@ typedef struct {
 /*! @name CSR - TCD Control and Status */
 #define DMA_CSR_START_MASK                       (0x1U)
 #define DMA_CSR_START_SHIFT                      (0U)
-#define DMA_CSR_START(x)                         (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
+#define DMA_CSR_START_SET(x)                     (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
+#define DMA_CSR_START DMA_CSR_START_MASK
 #define DMA_CSR_INTMAJOR_MASK                    (0x2U)
 #define DMA_CSR_INTMAJOR_SHIFT                   (1U)
-#define DMA_CSR_INTMAJOR(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
+#define DMA_CSR_INTMAJOR_SET(x)                  (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
+#define DMA_CSR_INTMAJOR DMA_CSR_INTMAJOR_MASK
 #define DMA_CSR_INTHALF_MASK                     (0x4U)
 #define DMA_CSR_INTHALF_SHIFT                    (2U)
-#define DMA_CSR_INTHALF(x)                       (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
+#define DMA_CSR_INTHALF_SET(x)                   (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
+#define DMA_CSR_INTHALF DMA_CSR_INTHALF_MASK
 #define DMA_CSR_DREQ_MASK                        (0x8U)
 #define DMA_CSR_DREQ_SHIFT                       (3U)
-#define DMA_CSR_DREQ(x)                          (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
+#define DMA_CSR_DREQ_SET(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
+#define DMA_CSR_DREQ DMA_CSR_DREQ_MASK
 #define DMA_CSR_ESG_MASK                         (0x10U)
 #define DMA_CSR_ESG_SHIFT                        (4U)
-#define DMA_CSR_ESG(x)                           (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
+#define DMA_CSR_ESG_SET(x)                       (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
+#define DMA_CSR_ESG DMA_CSR_ESG_MASK
 #define DMA_CSR_MAJORELINK_MASK                  (0x20U)
 #define DMA_CSR_MAJORELINK_SHIFT                 (5U)
-#define DMA_CSR_MAJORELINK(x)                    (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
+#define DMA_CSR_MAJORELINK_SET(x)                (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
+#define DMA_CSR_MAJORELINK DMA_CSR_MAJORELINK_MASK
 #define DMA_CSR_ACTIVE_MASK                      (0x40U)
 #define DMA_CSR_ACTIVE_SHIFT                     (6U)
-#define DMA_CSR_ACTIVE(x)                        (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
+#define DMA_CSR_ACTIVE_SET(x)                    (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
+#define DMA_CSR_ACTIVE DMA_CSR_ACTIVE_MASK
 #define DMA_CSR_DONE_MASK                        (0x80U)
 #define DMA_CSR_DONE_SHIFT                       (7U)
-#define DMA_CSR_DONE(x)                          (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
+#define DMA_CSR_DONE_SET(x)                      (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
+#define DMA_CSR_DONE DMA_CSR_DONE_MASK
 #define DMA_CSR_MAJORLINKCH_MASK                 (0x1F00U)
 #define DMA_CSR_MAJORLINKCH_SHIFT                (8U)
-#define DMA_CSR_MAJORLINKCH(x)                   (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
+#define DMA_CSR_MAJORLINKCH_SET(x)               (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
+#define DMA_CSR_MAJORLINKCH DMA_CSR_MAJORLINKCH_MASK
 #define DMA_CSR_BWC_MASK                         (0xC000U)
 #define DMA_CSR_BWC_SHIFT                        (14U)
-#define DMA_CSR_BWC(x)                           (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
+#define DMA_CSR_BWC_SET(x)                       (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
+#define DMA_CSR_BWC DMA_CSR_BWC_MASK
 
 /* The count of DMA_CSR */
 #define DMA_CSR_COUNT                            (32U)
@@ -5191,10 +6377,12 @@ typedef struct {
 /*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
 #define DMA_BITER_ELINKNO_BITER_MASK             (0x7FFFU)
 #define DMA_BITER_ELINKNO_BITER_SHIFT            (0U)
-#define DMA_BITER_ELINKNO_BITER(x)               (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
+#define DMA_BITER_ELINKNO_BITER_SET(x)           (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
+#define DMA_BITER_ELINKNO_BITER DMA_BITER_ELINKNO_BITER_MASK
 #define DMA_BITER_ELINKNO_ELINK_MASK             (0x8000U)
 #define DMA_BITER_ELINKNO_ELINK_SHIFT            (15U)
-#define DMA_BITER_ELINKNO_ELINK(x)               (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
+#define DMA_BITER_ELINKNO_ELINK_SET(x)           (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
+#define DMA_BITER_ELINKNO_ELINK DMA_BITER_ELINKNO_ELINK_MASK
 
 /* The count of DMA_BITER_ELINKNO */
 #define DMA_BITER_ELINKNO_COUNT                  (32U)
@@ -5202,13 +6390,16 @@ typedef struct {
 /*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
 #define DMA_BITER_ELINKYES_BITER_MASK            (0x1FFU)
 #define DMA_BITER_ELINKYES_BITER_SHIFT           (0U)
-#define DMA_BITER_ELINKYES_BITER(x)              (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
+#define DMA_BITER_ELINKYES_BITER_SET(x)          (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
+#define DMA_BITER_ELINKYES_BITER DMA_BITER_ELINKYES_BITER_MASK
 #define DMA_BITER_ELINKYES_LINKCH_MASK           (0x3E00U)
 #define DMA_BITER_ELINKYES_LINKCH_SHIFT          (9U)
-#define DMA_BITER_ELINKYES_LINKCH(x)             (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
+#define DMA_BITER_ELINKYES_LINKCH_SET(x)         (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
+#define DMA_BITER_ELINKYES_LINKCH DMA_BITER_ELINKYES_LINKCH_MASK
 #define DMA_BITER_ELINKYES_ELINK_MASK            (0x8000U)
 #define DMA_BITER_ELINKYES_ELINK_SHIFT           (15U)
-#define DMA_BITER_ELINKYES_ELINK(x)              (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
+#define DMA_BITER_ELINKYES_ELINK_SET(x)          (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
+#define DMA_BITER_ELINKYES_ELINK DMA_BITER_ELINKYES_ELINK_MASK
 
 /* The count of DMA_BITER_ELINKYES */
 #define DMA_BITER_ELINKYES_COUNT                 (32U)
@@ -5223,7 +6414,8 @@ typedef struct {
 /** Peripheral DMA base address */
 #define DMA_BASE                                 (0x40008000u)
 /** Peripheral DMA base pointer */
-#define DMA0                                     ((DMA_Type *)DMA_BASE)
+#define DMA0                                     ((DMA_TypeDef *)DMA_BASE)
+#define DMA DMA0
 /** Array initializer of DMA peripheral base addresses */
 #define DMA_BASE_ADDRS                           { DMA_BASE }
 /** Array initializer of DMA peripheral base pointers */
@@ -5249,7 +6441,7 @@ typedef struct {
 /** DMAMUX - Register Layout Typedef */
 typedef struct {
   __IO uint8_t CHCFG[32];                          /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
-} DMAMUX_Type;
+} DMAMUX_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- DMAMUX Register Masks
@@ -5261,18 +6453,19 @@ typedef struct {
  */
 
 /*! @name CHCFG - Channel Configuration register */
-#define DMAMUX_CHCFG_SOURCE_MASK                 (0x3FU)
-#define DMAMUX_CHCFG_SOURCE_SHIFT                (0U)
-#define DMAMUX_CHCFG_SOURCE(x)                   (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
-#define DMAMUX_CHCFG_TRIG_MASK                   (0x40U)
-#define DMAMUX_CHCFG_TRIG_SHIFT                  (6U)
-#define DMAMUX_CHCFG_TRIG(x)                     (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
-#define DMAMUX_CHCFG_ENBL_MASK                   (0x80U)
-#define DMAMUX_CHCFG_ENBL_SHIFT                  (7U)
-#define DMAMUX_CHCFG_ENBL(x)                     (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
+#define DMAMUX_CHCFGn_SOURCE_MASK                 (0x3FU)
+#define DMAMUX_CHCFGn_SOURCE_SHIFT                (0U)
+#define DMAMUX_CHCFGn_SOURCE(x)               (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFGn_SOURCE_SHIFT)) & DMAMUX_CHCFGn_SOURCE_MASK)
+#define DMAMUX_CHCFGn_TRIG_MASK                   (0x40U)
+#define DMAMUX_CHCFGn_TRIG_SHIFT                  (6U)
+#define DMAMUX_CHCFGn_TRIG(x)                 (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFGn_TRIG_SHIFT)) & DMAMUX_CHCFGn_TRIG_MASK)
+#define DMAMUX_CHCFGn_ENBL_MASK                   (0x80U)
+#define DMAMUX_CHCFGn_ENBL_SHIFT                  (7U)
+#define DMAMUX_CHCFGn_ENBL_SET(x)                 (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFGn_ENBL_SHIFT)) & DMAMUX_CHCFGn_ENBL_MASK)
+#define DMAMUX_CHCFGn_ENBL DMAMUX_CHCFGn_ENBL_MASK
 
 /* The count of DMAMUX_CHCFG */
-#define DMAMUX_CHCFG_COUNT                       (32U)
+#define DMAMUX_CHCFGn_COUNT                       (32U)
 
 
 /*!
@@ -5284,7 +6477,7 @@ typedef struct {
 /** Peripheral DMAMUX base address */
 #define DMAMUX_BASE                              (0x40021000u)
 /** Peripheral DMAMUX base pointer */
-#define DMAMUX                                   ((DMAMUX_Type *)DMAMUX_BASE)
+#define DMAMUX                                   ((DMAMUX_TypeDef *)DMAMUX_BASE)
 /** Array initializer of DMAMUX peripheral base addresses */
 #define DMAMUX_BASE_ADDRS                        { DMAMUX_BASE }
 /** Array initializer of DMAMUX peripheral base pointers */
@@ -5421,7 +6614,7 @@ typedef struct {
     __IO uint32_t TCSR;                              /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
     __IO uint32_t TCCR;                              /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
   } CHANNEL[4];
-} ENET_Type;
+} ENET_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- ENET Register Masks
@@ -5435,732 +6628,914 @@ typedef struct {
 /*! @name EIR - Interrupt Event Register */
 #define ENET_EIR_TS_TIMER_MASK                   (0x8000U)
 #define ENET_EIR_TS_TIMER_SHIFT                  (15U)
-#define ENET_EIR_TS_TIMER(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
+#define ENET_EIR_TS_TIMER_SET(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
+#define ENET_EIR_TS_TIMER ENET_EIR_TS_TIMER_MASK
 #define ENET_EIR_TS_AVAIL_MASK                   (0x10000U)
 #define ENET_EIR_TS_AVAIL_SHIFT                  (16U)
-#define ENET_EIR_TS_AVAIL(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
+#define ENET_EIR_TS_AVAIL_SET(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
+#define ENET_EIR_TS_AVAIL ENET_EIR_TS_AVAIL_MASK
 #define ENET_EIR_WAKEUP_MASK                     (0x20000U)
 #define ENET_EIR_WAKEUP_SHIFT                    (17U)
-#define ENET_EIR_WAKEUP(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
+#define ENET_EIR_WAKEUP_SET(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
+#define ENET_EIR_WAKEUP ENET_EIR_WAKEUP_MASK
 #define ENET_EIR_PLR_MASK                        (0x40000U)
 #define ENET_EIR_PLR_SHIFT                       (18U)
-#define ENET_EIR_PLR(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
+#define ENET_EIR_PLR_SET(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
+#define ENET_EIR_PLR ENET_EIR_PLR_MASK
 #define ENET_EIR_UN_MASK                         (0x80000U)
 #define ENET_EIR_UN_SHIFT                        (19U)
-#define ENET_EIR_UN(x)                           (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
+#define ENET_EIR_UN_SET(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
+#define ENET_EIR_UN ENET_EIR_UN_MASK
 #define ENET_EIR_RL_MASK                         (0x100000U)
 #define ENET_EIR_RL_SHIFT                        (20U)
-#define ENET_EIR_RL(x)                           (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
+#define ENET_EIR_RL_SET(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
+#define ENET_EIR_RL ENET_EIR_RL_MASK
 #define ENET_EIR_LC_MASK                         (0x200000U)
 #define ENET_EIR_LC_SHIFT                        (21U)
-#define ENET_EIR_LC(x)                           (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
+#define ENET_EIR_LC_SET(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
+#define ENET_EIR_LC ENET_EIR_LC_MASK
 #define ENET_EIR_EBERR_MASK                      (0x400000U)
 #define ENET_EIR_EBERR_SHIFT                     (22U)
-#define ENET_EIR_EBERR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
+#define ENET_EIR_EBERR_SET(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
+#define ENET_EIR_EBERR ENET_EIR_EBERR_MASK
 #define ENET_EIR_MII_MASK                        (0x800000U)
 #define ENET_EIR_MII_SHIFT                       (23U)
-#define ENET_EIR_MII(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
+#define ENET_EIR_MII_SET(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
+#define ENET_EIR_MII ENET_EIR_MII_MASK
 #define ENET_EIR_RXB_MASK                        (0x1000000U)
 #define ENET_EIR_RXB_SHIFT                       (24U)
-#define ENET_EIR_RXB(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
+#define ENET_EIR_RXB_SET(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
+#define ENET_EIR_RXB ENET_EIR_RXB_MASK
 #define ENET_EIR_RXF_MASK                        (0x2000000U)
 #define ENET_EIR_RXF_SHIFT                       (25U)
-#define ENET_EIR_RXF(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
+#define ENET_EIR_RXF_SET(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
+#define ENET_EIR_RXF ENET_EIR_RXF_MASK
 #define ENET_EIR_TXB_MASK                        (0x4000000U)
 #define ENET_EIR_TXB_SHIFT                       (26U)
-#define ENET_EIR_TXB(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
+#define ENET_EIR_TXB_SET(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
+#define ENET_EIR_TXB ENET_EIR_TXB_MASK
 #define ENET_EIR_TXF_MASK                        (0x8000000U)
 #define ENET_EIR_TXF_SHIFT                       (27U)
-#define ENET_EIR_TXF(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
+#define ENET_EIR_TXF_SET(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
+#define ENET_EIR_TXF ENET_EIR_TXF_MASK
 #define ENET_EIR_GRA_MASK                        (0x10000000U)
 #define ENET_EIR_GRA_SHIFT                       (28U)
-#define ENET_EIR_GRA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
+#define ENET_EIR_GRA_SET(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
+#define ENET_EIR_GRA ENET_EIR_GRA_MASK
 #define ENET_EIR_BABT_MASK                       (0x20000000U)
 #define ENET_EIR_BABT_SHIFT                      (29U)
-#define ENET_EIR_BABT(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
+#define ENET_EIR_BABT_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
+#define ENET_EIR_BABT ENET_EIR_BABT_MASK
 #define ENET_EIR_BABR_MASK                       (0x40000000U)
 #define ENET_EIR_BABR_SHIFT                      (30U)
-#define ENET_EIR_BABR(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
+#define ENET_EIR_BABR_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
+#define ENET_EIR_BABR ENET_EIR_BABR_MASK
 
 /*! @name EIMR - Interrupt Mask Register */
 #define ENET_EIMR_TS_TIMER_MASK                  (0x8000U)
 #define ENET_EIMR_TS_TIMER_SHIFT                 (15U)
-#define ENET_EIMR_TS_TIMER(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
+#define ENET_EIMR_TS_TIMER_SET(x)                (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
+#define ENET_EIMR_TS_TIMER ENET_EIMR_TS_TIMER_MASK
 #define ENET_EIMR_TS_AVAIL_MASK                  (0x10000U)
 #define ENET_EIMR_TS_AVAIL_SHIFT                 (16U)
-#define ENET_EIMR_TS_AVAIL(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
+#define ENET_EIMR_TS_AVAIL_SET(x)                (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
+#define ENET_EIMR_TS_AVAIL ENET_EIMR_TS_AVAIL_MASK
 #define ENET_EIMR_WAKEUP_MASK                    (0x20000U)
 #define ENET_EIMR_WAKEUP_SHIFT                   (17U)
-#define ENET_EIMR_WAKEUP(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
+#define ENET_EIMR_WAKEUP_SET(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
+#define ENET_EIMR_WAKEUP ENET_EIMR_WAKEUP_MASK
 #define ENET_EIMR_PLR_MASK                       (0x40000U)
 #define ENET_EIMR_PLR_SHIFT                      (18U)
-#define ENET_EIMR_PLR(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
+#define ENET_EIMR_PLR_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
+#define ENET_EIMR_PLR ENET_EIMR_PLR_MASK
 #define ENET_EIMR_UN_MASK                        (0x80000U)
 #define ENET_EIMR_UN_SHIFT                       (19U)
-#define ENET_EIMR_UN(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
+#define ENET_EIMR_UN_SET(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
+#define ENET_EIMR_UN ENET_EIMR_UN_MASK
 #define ENET_EIMR_RL_MASK                        (0x100000U)
 #define ENET_EIMR_RL_SHIFT                       (20U)
-#define ENET_EIMR_RL(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
+#define ENET_EIMR_RL_SET(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
+#define ENET_EIMR_RL ENET_EIMR_RL_MASK
 #define ENET_EIMR_LC_MASK                        (0x200000U)
 #define ENET_EIMR_LC_SHIFT                       (21U)
-#define ENET_EIMR_LC(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
+#define ENET_EIMR_LC_SET(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
+#define ENET_EIMR_LC ENET_EIMR_LC_MASK
 #define ENET_EIMR_EBERR_MASK                     (0x400000U)
 #define ENET_EIMR_EBERR_SHIFT                    (22U)
-#define ENET_EIMR_EBERR(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
+#define ENET_EIMR_EBERR_SET(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
+#define ENET_EIMR_EBERR ENET_EIMR_EBERR_MASK
 #define ENET_EIMR_MII_MASK                       (0x800000U)
 #define ENET_EIMR_MII_SHIFT                      (23U)
-#define ENET_EIMR_MII(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
+#define ENET_EIMR_MII_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
+#define ENET_EIMR_MII ENET_EIMR_MII_MASK
 #define ENET_EIMR_RXB_MASK                       (0x1000000U)
 #define ENET_EIMR_RXB_SHIFT                      (24U)
-#define ENET_EIMR_RXB(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
+#define ENET_EIMR_RXB_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
+#define ENET_EIMR_RXB ENET_EIMR_RXB_MASK
 #define ENET_EIMR_RXF_MASK                       (0x2000000U)
 #define ENET_EIMR_RXF_SHIFT                      (25U)
-#define ENET_EIMR_RXF(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
+#define ENET_EIMR_RXF_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
+#define ENET_EIMR_RXF ENET_EIMR_RXF_MASK
 #define ENET_EIMR_TXB_MASK                       (0x4000000U)
 #define ENET_EIMR_TXB_SHIFT                      (26U)
-#define ENET_EIMR_TXB(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
+#define ENET_EIMR_TXB_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
+#define ENET_EIMR_TXB ENET_EIMR_TXB_MASK
 #define ENET_EIMR_TXF_MASK                       (0x8000000U)
 #define ENET_EIMR_TXF_SHIFT                      (27U)
-#define ENET_EIMR_TXF(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
+#define ENET_EIMR_TXF_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
+#define ENET_EIMR_TXF ENET_EIMR_TXF_MASK
 #define ENET_EIMR_GRA_MASK                       (0x10000000U)
 #define ENET_EIMR_GRA_SHIFT                      (28U)
-#define ENET_EIMR_GRA(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
+#define ENET_EIMR_GRA_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
+#define ENET_EIMR_GRA ENET_EIMR_GRA_MASK
 #define ENET_EIMR_BABT_MASK                      (0x20000000U)
 #define ENET_EIMR_BABT_SHIFT                     (29U)
-#define ENET_EIMR_BABT(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
+#define ENET_EIMR_BABT_SET(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
+#define ENET_EIMR_BABT ENET_EIMR_BABT_MASK
 #define ENET_EIMR_BABR_MASK                      (0x40000000U)
 #define ENET_EIMR_BABR_SHIFT                     (30U)
-#define ENET_EIMR_BABR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
+#define ENET_EIMR_BABR_SET(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
+#define ENET_EIMR_BABR ENET_EIMR_BABR_MASK
 
 /*! @name RDAR - Receive Descriptor Active Register */
 #define ENET_RDAR_RDAR_MASK                      (0x1000000U)
 #define ENET_RDAR_RDAR_SHIFT                     (24U)
-#define ENET_RDAR_RDAR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
+#define ENET_RDAR_RDAR_SET(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
+#define ENET_RDAR_RDAR ENET_RDAR_RDAR_MASK
 
 /*! @name TDAR - Transmit Descriptor Active Register */
 #define ENET_TDAR_TDAR_MASK                      (0x1000000U)
 #define ENET_TDAR_TDAR_SHIFT                     (24U)
-#define ENET_TDAR_TDAR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
+#define ENET_TDAR_TDAR_SET(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
+#define ENET_TDAR_TDAR ENET_TDAR_TDAR_MASK
 
 /*! @name ECR - Ethernet Control Register */
 #define ENET_ECR_RESET_MASK                      (0x1U)
 #define ENET_ECR_RESET_SHIFT                     (0U)
-#define ENET_ECR_RESET(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
+#define ENET_ECR_RESET_SET(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
+#define ENET_ECR_RESET ENET_ECR_RESET_MASK
 #define ENET_ECR_ETHEREN_MASK                    (0x2U)
 #define ENET_ECR_ETHEREN_SHIFT                   (1U)
-#define ENET_ECR_ETHEREN(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
+#define ENET_ECR_ETHEREN_SET(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
+#define ENET_ECR_ETHEREN ENET_ECR_ETHEREN_MASK
 #define ENET_ECR_MAGICEN_MASK                    (0x4U)
 #define ENET_ECR_MAGICEN_SHIFT                   (2U)
-#define ENET_ECR_MAGICEN(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
+#define ENET_ECR_MAGICEN_SET(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
+#define ENET_ECR_MAGICEN ENET_ECR_MAGICEN_MASK
 #define ENET_ECR_SLEEP_MASK                      (0x8U)
 #define ENET_ECR_SLEEP_SHIFT                     (3U)
-#define ENET_ECR_SLEEP(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
+#define ENET_ECR_SLEEP_SET(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
+#define ENET_ECR_SLEEP ENET_ECR_SLEEP_MASK
 #define ENET_ECR_EN1588_MASK                     (0x10U)
 #define ENET_ECR_EN1588_SHIFT                    (4U)
-#define ENET_ECR_EN1588(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
+#define ENET_ECR_EN1588_SET(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
+#define ENET_ECR_EN1588 ENET_ECR_EN1588_MASK
 #define ENET_ECR_DBGEN_MASK                      (0x40U)
 #define ENET_ECR_DBGEN_SHIFT                     (6U)
-#define ENET_ECR_DBGEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
+#define ENET_ECR_DBGEN_SET(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
+#define ENET_ECR_DBGEN ENET_ECR_DBGEN_MASK
 #define ENET_ECR_STOPEN_MASK                     (0x80U)
 #define ENET_ECR_STOPEN_SHIFT                    (7U)
-#define ENET_ECR_STOPEN(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ECR_STOPEN_SHIFT)) & ENET_ECR_STOPEN_MASK)
+#define ENET_ECR_STOPEN_SET(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_ECR_STOPEN_SHIFT)) & ENET_ECR_STOPEN_MASK)
+#define ENET_ECR_STOPEN ENET_ECR_STOPEN_MASK
 #define ENET_ECR_DBSWP_MASK                      (0x100U)
 #define ENET_ECR_DBSWP_SHIFT                     (8U)
-#define ENET_ECR_DBSWP(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
+#define ENET_ECR_DBSWP_SET(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
+#define ENET_ECR_DBSWP ENET_ECR_DBSWP_MASK
 
 /*! @name MMFR - MII Management Frame Register */
 #define ENET_MMFR_DATA_MASK                      (0xFFFFU)
 #define ENET_MMFR_DATA_SHIFT                     (0U)
-#define ENET_MMFR_DATA(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
+#define ENET_MMFR_DATA_SET(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
+#define ENET_MMFR_DATA ENET_MMFR_DATA_MASK
 #define ENET_MMFR_TA_MASK                        (0x30000U)
 #define ENET_MMFR_TA_SHIFT                       (16U)
-#define ENET_MMFR_TA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
+#define ENET_MMFR_TA_SET(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
+#define ENET_MMFR_TA ENET_MMFR_TA_MASK
 #define ENET_MMFR_RA_MASK                        (0x7C0000U)
 #define ENET_MMFR_RA_SHIFT                       (18U)
-#define ENET_MMFR_RA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
+#define ENET_MMFR_RA_SET(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
+#define ENET_MMFR_RA ENET_MMFR_RA_MASK
 #define ENET_MMFR_PA_MASK                        (0xF800000U)
 #define ENET_MMFR_PA_SHIFT                       (23U)
-#define ENET_MMFR_PA(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
+#define ENET_MMFR_PA_SET(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
+#define ENET_MMFR_PA ENET_MMFR_PA_MASK
 #define ENET_MMFR_OP_MASK                        (0x30000000U)
 #define ENET_MMFR_OP_SHIFT                       (28U)
-#define ENET_MMFR_OP(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
+#define ENET_MMFR_OP_SET(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
+#define ENET_MMFR_OP ENET_MMFR_OP_MASK
 #define ENET_MMFR_ST_MASK                        (0xC0000000U)
 #define ENET_MMFR_ST_SHIFT                       (30U)
-#define ENET_MMFR_ST(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
+#define ENET_MMFR_ST_SET(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
+#define ENET_MMFR_ST ENET_MMFR_ST_MASK
 
 /*! @name MSCR - MII Speed Control Register */
 #define ENET_MSCR_MII_SPEED_MASK                 (0x7EU)
 #define ENET_MSCR_MII_SPEED_SHIFT                (1U)
-#define ENET_MSCR_MII_SPEED(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
+#define ENET_MSCR_MII_SPEED_SET(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
+#define ENET_MSCR_MII_SPEED ENET_MSCR_MII_SPEED_MASK
 #define ENET_MSCR_DIS_PRE_MASK                   (0x80U)
 #define ENET_MSCR_DIS_PRE_SHIFT                  (7U)
-#define ENET_MSCR_DIS_PRE(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
+#define ENET_MSCR_DIS_PRE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
+#define ENET_MSCR_DIS_PRE ENET_MSCR_DIS_PRE_MASK
 #define ENET_MSCR_HOLDTIME_MASK                  (0x700U)
 #define ENET_MSCR_HOLDTIME_SHIFT                 (8U)
-#define ENET_MSCR_HOLDTIME(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
+#define ENET_MSCR_HOLDTIME_SET(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
+#define ENET_MSCR_HOLDTIME ENET_MSCR_HOLDTIME_MASK
 
 /*! @name MIBC - MIB Control Register */
 #define ENET_MIBC_MIB_CLEAR_MASK                 (0x20000000U)
 #define ENET_MIBC_MIB_CLEAR_SHIFT                (29U)
-#define ENET_MIBC_MIB_CLEAR(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
+#define ENET_MIBC_MIB_CLEAR_SET(x)               (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
+#define ENET_MIBC_MIB_CLEAR ENET_MIBC_MIB_CLEAR_MASK
 #define ENET_MIBC_MIB_IDLE_MASK                  (0x40000000U)
 #define ENET_MIBC_MIB_IDLE_SHIFT                 (30U)
-#define ENET_MIBC_MIB_IDLE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
+#define ENET_MIBC_MIB_IDLE_SET(x)                (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
+#define ENET_MIBC_MIB_IDLE ENET_MIBC_MIB_IDLE_MASK
 #define ENET_MIBC_MIB_DIS_MASK                   (0x80000000U)
 #define ENET_MIBC_MIB_DIS_SHIFT                  (31U)
-#define ENET_MIBC_MIB_DIS(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
+#define ENET_MIBC_MIB_DIS_SET(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
+#define ENET_MIBC_MIB_DIS ENET_MIBC_MIB_DIS_MASK
 
 /*! @name RCR - Receive Control Register */
 #define ENET_RCR_LOOP_MASK                       (0x1U)
 #define ENET_RCR_LOOP_SHIFT                      (0U)
-#define ENET_RCR_LOOP(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
+#define ENET_RCR_LOOP_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
+#define ENET_RCR_LOOP ENET_RCR_LOOP_MASK
 #define ENET_RCR_DRT_MASK                        (0x2U)
 #define ENET_RCR_DRT_SHIFT                       (1U)
-#define ENET_RCR_DRT(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
+#define ENET_RCR_DRT_SET(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
+#define ENET_RCR_DRT ENET_RCR_DRT_MASK
 #define ENET_RCR_MII_MODE_MASK                   (0x4U)
 #define ENET_RCR_MII_MODE_SHIFT                  (2U)
-#define ENET_RCR_MII_MODE(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
+#define ENET_RCR_MII_MODE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
+#define ENET_RCR_MII_MODE ENET_RCR_MII_MODE_MASK
 #define ENET_RCR_PROM_MASK                       (0x8U)
 #define ENET_RCR_PROM_SHIFT                      (3U)
-#define ENET_RCR_PROM(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
+#define ENET_RCR_PROM_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
+#define ENET_RCR_PROM ENET_RCR_PROM_MASK
 #define ENET_RCR_BC_REJ_MASK                     (0x10U)
 #define ENET_RCR_BC_REJ_SHIFT                    (4U)
-#define ENET_RCR_BC_REJ(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
+#define ENET_RCR_BC_REJ_SET(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
+#define ENET_RCR_BC_REJ ENET_RCR_BC_REJ_MASK
 #define ENET_RCR_FCE_MASK                        (0x20U)
 #define ENET_RCR_FCE_SHIFT                       (5U)
-#define ENET_RCR_FCE(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
+#define ENET_RCR_FCE_SET(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
+#define ENET_RCR_FCE ENET_RCR_FCE_MASK
 #define ENET_RCR_RMII_MODE_MASK                  (0x100U)
 #define ENET_RCR_RMII_MODE_SHIFT                 (8U)
-#define ENET_RCR_RMII_MODE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
+#define ENET_RCR_RMII_MODE_SET(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
+#define ENET_RCR_RMII_MODE ENET_RCR_RMII_MODE_MASK
 #define ENET_RCR_RMII_10T_MASK                   (0x200U)
 #define ENET_RCR_RMII_10T_SHIFT                  (9U)
-#define ENET_RCR_RMII_10T(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
+#define ENET_RCR_RMII_10T_SET(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
+#define ENET_RCR_RMII_10T ENET_RCR_RMII_10T_MASK
 #define ENET_RCR_PADEN_MASK                      (0x1000U)
 #define ENET_RCR_PADEN_SHIFT                     (12U)
-#define ENET_RCR_PADEN(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
+#define ENET_RCR_PADEN_SET(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
+#define ENET_RCR_PADEN ENET_RCR_PADEN_MASK
 #define ENET_RCR_PAUFWD_MASK                     (0x2000U)
 #define ENET_RCR_PAUFWD_SHIFT                    (13U)
-#define ENET_RCR_PAUFWD(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
+#define ENET_RCR_PAUFWD_SET(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
+#define ENET_RCR_PAUFWD ENET_RCR_PAUFWD_MASK
 #define ENET_RCR_CRCFWD_MASK                     (0x4000U)
 #define ENET_RCR_CRCFWD_SHIFT                    (14U)
-#define ENET_RCR_CRCFWD(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
+#define ENET_RCR_CRCFWD_SET(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
+#define ENET_RCR_CRCFWD ENET_RCR_CRCFWD_MASK
 #define ENET_RCR_CFEN_MASK                       (0x8000U)
 #define ENET_RCR_CFEN_SHIFT                      (15U)
-#define ENET_RCR_CFEN(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
+#define ENET_RCR_CFEN_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
+#define ENET_RCR_CFEN ENET_RCR_CFEN_MASK
 #define ENET_RCR_MAX_FL_MASK                     (0x3FFF0000U)
 #define ENET_RCR_MAX_FL_SHIFT                    (16U)
-#define ENET_RCR_MAX_FL(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
+#define ENET_RCR_MAX_FL_SET(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
+#define ENET_RCR_MAX_FL ENET_RCR_MAX_FL_MASK
 #define ENET_RCR_NLC_MASK                        (0x40000000U)
 #define ENET_RCR_NLC_SHIFT                       (30U)
-#define ENET_RCR_NLC(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
+#define ENET_RCR_NLC_SET(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
+#define ENET_RCR_NLC ENET_RCR_NLC_MASK
 #define ENET_RCR_GRS_MASK                        (0x80000000U)
 #define ENET_RCR_GRS_SHIFT                       (31U)
-#define ENET_RCR_GRS(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
+#define ENET_RCR_GRS_SET(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
+#define ENET_RCR_GRS ENET_RCR_GRS_MASK
 
 /*! @name TCR - Transmit Control Register */
 #define ENET_TCR_GTS_MASK                        (0x1U)
 #define ENET_TCR_GTS_SHIFT                       (0U)
-#define ENET_TCR_GTS(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
+#define ENET_TCR_GTS_SET(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
+#define ENET_TCR_GTS ENET_TCR_GTS_MASK
 #define ENET_TCR_FDEN_MASK                       (0x4U)
 #define ENET_TCR_FDEN_SHIFT                      (2U)
-#define ENET_TCR_FDEN(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
+#define ENET_TCR_FDEN_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
+#define ENET_TCR_FDEN ENET_TCR_FDEN_MASK
 #define ENET_TCR_TFC_PAUSE_MASK                  (0x8U)
 #define ENET_TCR_TFC_PAUSE_SHIFT                 (3U)
-#define ENET_TCR_TFC_PAUSE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
+#define ENET_TCR_TFC_PAUSE_SET(x)                (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
+#define ENET_TCR_TFC_PAUSE ENET_TCR_TFC_PAUSE_MASK
 #define ENET_TCR_RFC_PAUSE_MASK                  (0x10U)
 #define ENET_TCR_RFC_PAUSE_SHIFT                 (4U)
-#define ENET_TCR_RFC_PAUSE(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
+#define ENET_TCR_RFC_PAUSE_SET(x)                (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
+#define ENET_TCR_RFC_PAUSE ENET_TCR_RFC_PAUSE_MASK
 #define ENET_TCR_ADDSEL_MASK                     (0xE0U)
 #define ENET_TCR_ADDSEL_SHIFT                    (5U)
-#define ENET_TCR_ADDSEL(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
+#define ENET_TCR_ADDSEL_SET(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
+#define ENET_TCR_ADDSEL ENET_TCR_ADDSEL_MASK
 #define ENET_TCR_ADDINS_MASK                     (0x100U)
 #define ENET_TCR_ADDINS_SHIFT                    (8U)
-#define ENET_TCR_ADDINS(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
+#define ENET_TCR_ADDINS_SET(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
+#define ENET_TCR_ADDINS ENET_TCR_ADDINS_MASK
 #define ENET_TCR_CRCFWD_MASK                     (0x200U)
 #define ENET_TCR_CRCFWD_SHIFT                    (9U)
-#define ENET_TCR_CRCFWD(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
+#define ENET_TCR_CRCFWD_SET(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
+#define ENET_TCR_CRCFWD ENET_TCR_CRCFWD_MASK
 
 /*! @name PALR - Physical Address Lower Register */
 #define ENET_PALR_PADDR1_MASK                    (0xFFFFFFFFU)
 #define ENET_PALR_PADDR1_SHIFT                   (0U)
-#define ENET_PALR_PADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
+#define ENET_PALR_PADDR1_SET(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
+#define ENET_PALR_PADDR1 ENET_PALR_PADDR1_MASK
 
 /*! @name PAUR - Physical Address Upper Register */
 #define ENET_PAUR_TYPE_MASK                      (0xFFFFU)
 #define ENET_PAUR_TYPE_SHIFT                     (0U)
-#define ENET_PAUR_TYPE(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
+#define ENET_PAUR_TYPE_SET(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
+#define ENET_PAUR_TYPE ENET_PAUR_TYPE_MASK
 #define ENET_PAUR_PADDR2_MASK                    (0xFFFF0000U)
 #define ENET_PAUR_PADDR2_SHIFT                   (16U)
-#define ENET_PAUR_PADDR2(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
+#define ENET_PAUR_PADDR2_SET(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
+#define ENET_PAUR_PADDR2 ENET_PAUR_PADDR2_MASK
 
 /*! @name OPD - Opcode/Pause Duration Register */
 #define ENET_OPD_PAUSE_DUR_MASK                  (0xFFFFU)
 #define ENET_OPD_PAUSE_DUR_SHIFT                 (0U)
-#define ENET_OPD_PAUSE_DUR(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
+#define ENET_OPD_PAUSE_DUR_SET(x)                (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
+#define ENET_OPD_PAUSE_DUR ENET_OPD_PAUSE_DUR_MASK
 #define ENET_OPD_OPCODE_MASK                     (0xFFFF0000U)
 #define ENET_OPD_OPCODE_SHIFT                    (16U)
-#define ENET_OPD_OPCODE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
+#define ENET_OPD_OPCODE_SET(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
+#define ENET_OPD_OPCODE ENET_OPD_OPCODE_MASK
 
 /*! @name IAUR - Descriptor Individual Upper Address Register */
 #define ENET_IAUR_IADDR1_MASK                    (0xFFFFFFFFU)
 #define ENET_IAUR_IADDR1_SHIFT                   (0U)
-#define ENET_IAUR_IADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
+#define ENET_IAUR_IADDR1_SET(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
+#define ENET_IAUR_IADDR1 ENET_IAUR_IADDR1_MASK
 
 /*! @name IALR - Descriptor Individual Lower Address Register */
 #define ENET_IALR_IADDR2_MASK                    (0xFFFFFFFFU)
 #define ENET_IALR_IADDR2_SHIFT                   (0U)
-#define ENET_IALR_IADDR2(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
+#define ENET_IALR_IADDR2_SET(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
+#define ENET_IALR_IADDR2 ENET_IALR_IADDR2_MASK
 
 /*! @name GAUR - Descriptor Group Upper Address Register */
 #define ENET_GAUR_GADDR1_MASK                    (0xFFFFFFFFU)
 #define ENET_GAUR_GADDR1_SHIFT                   (0U)
-#define ENET_GAUR_GADDR1(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
+#define ENET_GAUR_GADDR1_SET(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
+#define ENET_GAUR_GADDR1 ENET_GAUR_GADDR1_MASK
 
 /*! @name GALR - Descriptor Group Lower Address Register */
 #define ENET_GALR_GADDR2_MASK                    (0xFFFFFFFFU)
 #define ENET_GALR_GADDR2_SHIFT                   (0U)
-#define ENET_GALR_GADDR2(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
+#define ENET_GALR_GADDR2_SET(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
+#define ENET_GALR_GADDR2 ENET_GALR_GADDR2_MASK
 
 /*! @name TFWR - Transmit FIFO Watermark Register */
 #define ENET_TFWR_TFWR_MASK                      (0x3FU)
 #define ENET_TFWR_TFWR_SHIFT                     (0U)
-#define ENET_TFWR_TFWR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
+#define ENET_TFWR_TFWR_SET(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
+#define ENET_TFWR_TFWR ENET_TFWR_TFWR_MASK
 #define ENET_TFWR_STRFWD_MASK                    (0x100U)
 #define ENET_TFWR_STRFWD_SHIFT                   (8U)
-#define ENET_TFWR_STRFWD(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
+#define ENET_TFWR_STRFWD_SET(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
+#define ENET_TFWR_STRFWD ENET_TFWR_STRFWD_MASK
 
 /*! @name RDSR - Receive Descriptor Ring Start Register */
 #define ENET_RDSR_R_DES_START_MASK               (0xFFFFFFF8U)
 #define ENET_RDSR_R_DES_START_SHIFT              (3U)
-#define ENET_RDSR_R_DES_START(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
+#define ENET_RDSR_R_DES_START_SET(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
+#define ENET_RDSR_R_DES_START ENET_RDSR_R_DES_START_MASK
 
 /*! @name TDSR - Transmit Buffer Descriptor Ring Start Register */
 #define ENET_TDSR_X_DES_START_MASK               (0xFFFFFFF8U)
 #define ENET_TDSR_X_DES_START_SHIFT              (3U)
-#define ENET_TDSR_X_DES_START(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
+#define ENET_TDSR_X_DES_START_SET(x)             (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
+#define ENET_TDSR_X_DES_START ENET_TDSR_X_DES_START_MASK
 
 /*! @name MRBR - Maximum Receive Buffer Size Register */
 #define ENET_MRBR_R_BUF_SIZE_MASK                (0x7F0U)
 #define ENET_MRBR_R_BUF_SIZE_SHIFT               (4U)
-#define ENET_MRBR_R_BUF_SIZE(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)
+#define ENET_MRBR_R_BUF_SIZE_SET(x)              (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK)
+#define ENET_MRBR_R_BUF_SIZE ENET_MRBR_R_BUF_SIZE_MASK
 
 /*! @name RSFL - Receive FIFO Section Full Threshold */
 #define ENET_RSFL_RX_SECTION_FULL_MASK           (0xFFU)
 #define ENET_RSFL_RX_SECTION_FULL_SHIFT          (0U)
-#define ENET_RSFL_RX_SECTION_FULL(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)
+#define ENET_RSFL_RX_SECTION_FULL_SET(x)         (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK)
+#define ENET_RSFL_RX_SECTION_FULL ENET_RSFL_RX_SECTION_FULL_MASK
 
 /*! @name RSEM - Receive FIFO Section Empty Threshold */
 #define ENET_RSEM_RX_SECTION_EMPTY_MASK          (0xFFU)
 #define ENET_RSEM_RX_SECTION_EMPTY_SHIFT         (0U)
-#define ENET_RSEM_RX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
+#define ENET_RSEM_RX_SECTION_EMPTY_SET(x)        (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK)
+#define ENET_RSEM_RX_SECTION_EMPTY ENET_RSEM_RX_SECTION_EMPTY_MASK
 #define ENET_RSEM_STAT_SECTION_EMPTY_MASK        (0x1F0000U)
 #define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT       (16U)
-#define ENET_RSEM_STAT_SECTION_EMPTY(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
+#define ENET_RSEM_STAT_SECTION_EMPTY_SET(x)      (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
+#define ENET_RSEM_STAT_SECTION_EMPTY ENET_RSEM_STAT_SECTION_EMPTY_MASK
 
 /*! @name RAEM - Receive FIFO Almost Empty Threshold */
 #define ENET_RAEM_RX_ALMOST_EMPTY_MASK           (0xFFU)
 #define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT          (0U)
-#define ENET_RAEM_RX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)
+#define ENET_RAEM_RX_ALMOST_EMPTY_SET(x)         (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK)
+#define ENET_RAEM_RX_ALMOST_EMPTY ENET_RAEM_RX_ALMOST_EMPTY_MASK
 
 /*! @name RAFL - Receive FIFO Almost Full Threshold */
 #define ENET_RAFL_RX_ALMOST_FULL_MASK            (0xFFU)
 #define ENET_RAFL_RX_ALMOST_FULL_SHIFT           (0U)
-#define ENET_RAFL_RX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)
+#define ENET_RAFL_RX_ALMOST_FULL_SET(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK)
+#define ENET_RAFL_RX_ALMOST_FULL ENET_RAFL_RX_ALMOST_FULL_MASK
 
 /*! @name TSEM - Transmit FIFO Section Empty Threshold */
 #define ENET_TSEM_TX_SECTION_EMPTY_MASK          (0xFFU)
 #define ENET_TSEM_TX_SECTION_EMPTY_SHIFT         (0U)
-#define ENET_TSEM_TX_SECTION_EMPTY(x)            (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)
+#define ENET_TSEM_TX_SECTION_EMPTY_SET(x)        (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK)
+#define ENET_TSEM_TX_SECTION_EMPTY ENET_TSEM_TX_SECTION_EMPTY_MASK
 
 /*! @name TAEM - Transmit FIFO Almost Empty Threshold */
 #define ENET_TAEM_TX_ALMOST_EMPTY_MASK           (0xFFU)
 #define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT          (0U)
-#define ENET_TAEM_TX_ALMOST_EMPTY(x)             (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)
+#define ENET_TAEM_TX_ALMOST_EMPTY_SET(x)         (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK)
+#define ENET_TAEM_TX_ALMOST_EMPTY ENET_TAEM_TX_ALMOST_EMPTY_MASK
 
 /*! @name TAFL - Transmit FIFO Almost Full Threshold */
 #define ENET_TAFL_TX_ALMOST_FULL_MASK            (0xFFU)
 #define ENET_TAFL_TX_ALMOST_FULL_SHIFT           (0U)
-#define ENET_TAFL_TX_ALMOST_FULL(x)              (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)
+#define ENET_TAFL_TX_ALMOST_FULL_SET(x)          (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK)
+#define ENET_TAFL_TX_ALMOST_FULL ENET_TAFL_TX_ALMOST_FULL_MASK
 
 /*! @name TIPG - Transmit Inter-Packet Gap */
 #define ENET_TIPG_IPG_MASK                       (0x1FU)
 #define ENET_TIPG_IPG_SHIFT                      (0U)
-#define ENET_TIPG_IPG(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
+#define ENET_TIPG_IPG_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
+#define ENET_TIPG_IPG ENET_TIPG_IPG_MASK
 
 /*! @name FTRL - Frame Truncation Length */
 #define ENET_FTRL_TRUNC_FL_MASK                  (0x3FFFU)
 #define ENET_FTRL_TRUNC_FL_SHIFT                 (0U)
-#define ENET_FTRL_TRUNC_FL(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
+#define ENET_FTRL_TRUNC_FL_SET(x)                (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
+#define ENET_FTRL_TRUNC_FL ENET_FTRL_TRUNC_FL_MASK
 
 /*! @name TACC - Transmit Accelerator Function Configuration */
 #define ENET_TACC_SHIFT16_MASK                   (0x1U)
 #define ENET_TACC_SHIFT16_SHIFT                  (0U)
-#define ENET_TACC_SHIFT16(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
+#define ENET_TACC_SHIFT16_SET(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
+#define ENET_TACC_SHIFT16 ENET_TACC_SHIFT16_MASK
 #define ENET_TACC_IPCHK_MASK                     (0x8U)
 #define ENET_TACC_IPCHK_SHIFT                    (3U)
-#define ENET_TACC_IPCHK(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
+#define ENET_TACC_IPCHK_SET(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
+#define ENET_TACC_IPCHK ENET_TACC_IPCHK_MASK
 #define ENET_TACC_PROCHK_MASK                    (0x10U)
 #define ENET_TACC_PROCHK_SHIFT                   (4U)
-#define ENET_TACC_PROCHK(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
+#define ENET_TACC_PROCHK_SET(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
+#define ENET_TACC_PROCHK ENET_TACC_PROCHK_MASK
 
 /*! @name RACC - Receive Accelerator Function Configuration */
 #define ENET_RACC_PADREM_MASK                    (0x1U)
 #define ENET_RACC_PADREM_SHIFT                   (0U)
-#define ENET_RACC_PADREM(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
+#define ENET_RACC_PADREM_SET(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
+#define ENET_RACC_PADREM ENET_RACC_PADREM_MASK
 #define ENET_RACC_IPDIS_MASK                     (0x2U)
 #define ENET_RACC_IPDIS_SHIFT                    (1U)
-#define ENET_RACC_IPDIS(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
+#define ENET_RACC_IPDIS_SET(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
+#define ENET_RACC_IPDIS ENET_RACC_IPDIS_MASK
 #define ENET_RACC_PRODIS_MASK                    (0x4U)
 #define ENET_RACC_PRODIS_SHIFT                   (2U)
-#define ENET_RACC_PRODIS(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
+#define ENET_RACC_PRODIS_SET(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
+#define ENET_RACC_PRODIS ENET_RACC_PRODIS_MASK
 #define ENET_RACC_LINEDIS_MASK                   (0x40U)
 #define ENET_RACC_LINEDIS_SHIFT                  (6U)
-#define ENET_RACC_LINEDIS(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
+#define ENET_RACC_LINEDIS_SET(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
+#define ENET_RACC_LINEDIS ENET_RACC_LINEDIS_MASK
 #define ENET_RACC_SHIFT16_MASK                   (0x80U)
 #define ENET_RACC_SHIFT16_SHIFT                  (7U)
-#define ENET_RACC_SHIFT16(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
+#define ENET_RACC_SHIFT16_SET(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
+#define ENET_RACC_SHIFT16 ENET_RACC_SHIFT16_MASK
 
 /*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */
 #define ENET_RMON_T_PACKETS_TXPKTS_MASK          (0xFFFFU)
 #define ENET_RMON_T_PACKETS_TXPKTS_SHIFT         (0U)
-#define ENET_RMON_T_PACKETS_TXPKTS(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
+#define ENET_RMON_T_PACKETS_TXPKTS_SET(x)        (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
+#define ENET_RMON_T_PACKETS_TXPKTS ENET_RMON_T_PACKETS_TXPKTS_MASK
 
 /*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */
 #define ENET_RMON_T_BC_PKT_TXPKTS_MASK           (0xFFFFU)
 #define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT          (0U)
-#define ENET_RMON_T_BC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
+#define ENET_RMON_T_BC_PKT_TXPKTS_SET(x)         (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
+#define ENET_RMON_T_BC_PKT_TXPKTS ENET_RMON_T_BC_PKT_TXPKTS_MASK
 
 /*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */
 #define ENET_RMON_T_MC_PKT_TXPKTS_MASK           (0xFFFFU)
 #define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT          (0U)
-#define ENET_RMON_T_MC_PKT_TXPKTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
+#define ENET_RMON_T_MC_PKT_TXPKTS_SET(x)         (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
+#define ENET_RMON_T_MC_PKT_TXPKTS ENET_RMON_T_MC_PKT_TXPKTS_MASK
 
 /*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */
 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK        (0xFFFFU)
 #define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT       (0U)
-#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SET(x)      (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
+#define ENET_RMON_T_CRC_ALIGN_TXPKTS ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK
 
 /*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */
 #define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK        (0xFFFFU)
 #define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT       (0U)
-#define ENET_RMON_T_UNDERSIZE_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
+#define ENET_RMON_T_UNDERSIZE_TXPKTS_SET(x)      (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
+#define ENET_RMON_T_UNDERSIZE_TXPKTS ENET_RMON_T_UNDERSIZE_TXPKTS_MASK
 
 /*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */
 #define ENET_RMON_T_OVERSIZE_TXPKTS_MASK         (0xFFFFU)
 #define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT        (0U)
-#define ENET_RMON_T_OVERSIZE_TXPKTS(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
+#define ENET_RMON_T_OVERSIZE_TXPKTS_SET(x)       (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
+#define ENET_RMON_T_OVERSIZE_TXPKTS ENET_RMON_T_OVERSIZE_TXPKTS_MASK
 
 /*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
 #define ENET_RMON_T_FRAG_TXPKTS_MASK             (0xFFFFU)
 #define ENET_RMON_T_FRAG_TXPKTS_SHIFT            (0U)
-#define ENET_RMON_T_FRAG_TXPKTS(x)               (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
+#define ENET_RMON_T_FRAG_TXPKTS_SET(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
+#define ENET_RMON_T_FRAG_TXPKTS ENET_RMON_T_FRAG_TXPKTS_MASK
 
 /*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */
 #define ENET_RMON_T_JAB_TXPKTS_MASK              (0xFFFFU)
 #define ENET_RMON_T_JAB_TXPKTS_SHIFT             (0U)
-#define ENET_RMON_T_JAB_TXPKTS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
+#define ENET_RMON_T_JAB_TXPKTS_SET(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
+#define ENET_RMON_T_JAB_TXPKTS ENET_RMON_T_JAB_TXPKTS_MASK
 
 /*! @name RMON_T_COL - Tx Collision Count Statistic Register */
 #define ENET_RMON_T_COL_TXPKTS_MASK              (0xFFFFU)
 #define ENET_RMON_T_COL_TXPKTS_SHIFT             (0U)
-#define ENET_RMON_T_COL_TXPKTS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
+#define ENET_RMON_T_COL_TXPKTS_SET(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
+#define ENET_RMON_T_COL_TXPKTS ENET_RMON_T_COL_TXPKTS_MASK
 
 /*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */
 #define ENET_RMON_T_P64_TXPKTS_MASK              (0xFFFFU)
 #define ENET_RMON_T_P64_TXPKTS_SHIFT             (0U)
-#define ENET_RMON_T_P64_TXPKTS(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
+#define ENET_RMON_T_P64_TXPKTS_SET(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
+#define ENET_RMON_T_P64_TXPKTS ENET_RMON_T_P64_TXPKTS_MASK
 
 /*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */
 #define ENET_RMON_T_P65TO127_TXPKTS_MASK         (0xFFFFU)
 #define ENET_RMON_T_P65TO127_TXPKTS_SHIFT        (0U)
-#define ENET_RMON_T_P65TO127_TXPKTS(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
+#define ENET_RMON_T_P65TO127_TXPKTS_SET(x)       (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
+#define ENET_RMON_T_P65TO127_TXPKTS ENET_RMON_T_P65TO127_TXPKTS_MASK
 
 /*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */
 #define ENET_RMON_T_P128TO255_TXPKTS_MASK        (0xFFFFU)
 #define ENET_RMON_T_P128TO255_TXPKTS_SHIFT       (0U)
-#define ENET_RMON_T_P128TO255_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
+#define ENET_RMON_T_P128TO255_TXPKTS_SET(x)      (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
+#define ENET_RMON_T_P128TO255_TXPKTS ENET_RMON_T_P128TO255_TXPKTS_MASK
 
 /*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */
 #define ENET_RMON_T_P256TO511_TXPKTS_MASK        (0xFFFFU)
 #define ENET_RMON_T_P256TO511_TXPKTS_SHIFT       (0U)
-#define ENET_RMON_T_P256TO511_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
+#define ENET_RMON_T_P256TO511_TXPKTS_SET(x)      (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
+#define ENET_RMON_T_P256TO511_TXPKTS ENET_RMON_T_P256TO511_TXPKTS_MASK
 
 /*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */
 #define ENET_RMON_T_P512TO1023_TXPKTS_MASK       (0xFFFFU)
 #define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT      (0U)
-#define ENET_RMON_T_P512TO1023_TXPKTS(x)         (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
+#define ENET_RMON_T_P512TO1023_TXPKTS_SET(x)     (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
+#define ENET_RMON_T_P512TO1023_TXPKTS ENET_RMON_T_P512TO1023_TXPKTS_MASK
 
 /*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */
 #define ENET_RMON_T_P1024TO2047_TXPKTS_MASK      (0xFFFFU)
 #define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT     (0U)
-#define ENET_RMON_T_P1024TO2047_TXPKTS(x)        (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
+#define ENET_RMON_T_P1024TO2047_TXPKTS_SET(x)    (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
+#define ENET_RMON_T_P1024TO2047_TXPKTS ENET_RMON_T_P1024TO2047_TXPKTS_MASK
 
 /*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */
 #define ENET_RMON_T_P_GTE2048_TXPKTS_MASK        (0xFFFFU)
 #define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT       (0U)
-#define ENET_RMON_T_P_GTE2048_TXPKTS(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
+#define ENET_RMON_T_P_GTE2048_TXPKTS_SET(x)      (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
+#define ENET_RMON_T_P_GTE2048_TXPKTS ENET_RMON_T_P_GTE2048_TXPKTS_MASK
 
 /*! @name RMON_T_OCTETS - Tx Octets Statistic Register */
 #define ENET_RMON_T_OCTETS_TXOCTS_MASK           (0xFFFFFFFFU)
 #define ENET_RMON_T_OCTETS_TXOCTS_SHIFT          (0U)
-#define ENET_RMON_T_OCTETS_TXOCTS(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
+#define ENET_RMON_T_OCTETS_TXOCTS_SET(x)         (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
+#define ENET_RMON_T_OCTETS_TXOCTS ENET_RMON_T_OCTETS_TXOCTS_MASK
 
 /*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */
 #define ENET_IEEE_T_FRAME_OK_COUNT_MASK          (0xFFFFU)
 #define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT         (0U)
-#define ENET_IEEE_T_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
+#define ENET_IEEE_T_FRAME_OK_COUNT_SET(x)        (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
+#define ENET_IEEE_T_FRAME_OK_COUNT ENET_IEEE_T_FRAME_OK_COUNT_MASK
 
 /*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */
 #define ENET_IEEE_T_1COL_COUNT_MASK              (0xFFFFU)
 #define ENET_IEEE_T_1COL_COUNT_SHIFT             (0U)
-#define ENET_IEEE_T_1COL_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
+#define ENET_IEEE_T_1COL_COUNT_SET(x)            (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
+#define ENET_IEEE_T_1COL_COUNT ENET_IEEE_T_1COL_COUNT_MASK
 
 /*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */
 #define ENET_IEEE_T_MCOL_COUNT_MASK              (0xFFFFU)
 #define ENET_IEEE_T_MCOL_COUNT_SHIFT             (0U)
-#define ENET_IEEE_T_MCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
+#define ENET_IEEE_T_MCOL_COUNT_SET(x)            (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
+#define ENET_IEEE_T_MCOL_COUNT ENET_IEEE_T_MCOL_COUNT_MASK
 
 /*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */
 #define ENET_IEEE_T_DEF_COUNT_MASK               (0xFFFFU)
 #define ENET_IEEE_T_DEF_COUNT_SHIFT              (0U)
-#define ENET_IEEE_T_DEF_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
+#define ENET_IEEE_T_DEF_COUNT_SET(x)             (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
+#define ENET_IEEE_T_DEF_COUNT ENET_IEEE_T_DEF_COUNT_MASK
 
 /*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */
 #define ENET_IEEE_T_LCOL_COUNT_MASK              (0xFFFFU)
 #define ENET_IEEE_T_LCOL_COUNT_SHIFT             (0U)
-#define ENET_IEEE_T_LCOL_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
+#define ENET_IEEE_T_LCOL_COUNT_SET(x)            (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
+#define ENET_IEEE_T_LCOL_COUNT ENET_IEEE_T_LCOL_COUNT_MASK
 
 /*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */
 #define ENET_IEEE_T_EXCOL_COUNT_MASK             (0xFFFFU)
 #define ENET_IEEE_T_EXCOL_COUNT_SHIFT            (0U)
-#define ENET_IEEE_T_EXCOL_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
+#define ENET_IEEE_T_EXCOL_COUNT_SET(x)           (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
+#define ENET_IEEE_T_EXCOL_COUNT ENET_IEEE_T_EXCOL_COUNT_MASK
 
 /*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */
 #define ENET_IEEE_T_MACERR_COUNT_MASK            (0xFFFFU)
 #define ENET_IEEE_T_MACERR_COUNT_SHIFT           (0U)
-#define ENET_IEEE_T_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
+#define ENET_IEEE_T_MACERR_COUNT_SET(x)          (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
+#define ENET_IEEE_T_MACERR_COUNT ENET_IEEE_T_MACERR_COUNT_MASK
 
 /*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */
 #define ENET_IEEE_T_CSERR_COUNT_MASK             (0xFFFFU)
 #define ENET_IEEE_T_CSERR_COUNT_SHIFT            (0U)
-#define ENET_IEEE_T_CSERR_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
+#define ENET_IEEE_T_CSERR_COUNT_SET(x)           (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
+#define ENET_IEEE_T_CSERR_COUNT ENET_IEEE_T_CSERR_COUNT_MASK
 
 /*! @name IEEE_T_SQE -  */
 #define ENET_IEEE_T_SQE_COUNT_MASK               (0xFFFFU)
 #define ENET_IEEE_T_SQE_COUNT_SHIFT              (0U)
-#define ENET_IEEE_T_SQE_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)
+#define ENET_IEEE_T_SQE_COUNT_SET(x)             (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)
+#define ENET_IEEE_T_SQE_COUNT ENET_IEEE_T_SQE_COUNT_MASK
 
 /*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */
 #define ENET_IEEE_T_FDXFC_COUNT_MASK             (0xFFFFU)
 #define ENET_IEEE_T_FDXFC_COUNT_SHIFT            (0U)
-#define ENET_IEEE_T_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
+#define ENET_IEEE_T_FDXFC_COUNT_SET(x)           (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
+#define ENET_IEEE_T_FDXFC_COUNT ENET_IEEE_T_FDXFC_COUNT_MASK
 
 /*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */
 #define ENET_IEEE_T_OCTETS_OK_COUNT_MASK         (0xFFFFFFFFU)
 #define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT        (0U)
-#define ENET_IEEE_T_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
+#define ENET_IEEE_T_OCTETS_OK_COUNT_SET(x)       (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
+#define ENET_IEEE_T_OCTETS_OK_COUNT ENET_IEEE_T_OCTETS_OK_COUNT_MASK
 
 /*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */
 #define ENET_RMON_R_PACKETS_COUNT_MASK           (0xFFFFU)
 #define ENET_RMON_R_PACKETS_COUNT_SHIFT          (0U)
-#define ENET_RMON_R_PACKETS_COUNT(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
+#define ENET_RMON_R_PACKETS_COUNT_SET(x)         (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
+#define ENET_RMON_R_PACKETS_COUNT ENET_RMON_R_PACKETS_COUNT_MASK
 
 /*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */
 #define ENET_RMON_R_BC_PKT_COUNT_MASK            (0xFFFFU)
 #define ENET_RMON_R_BC_PKT_COUNT_SHIFT           (0U)
-#define ENET_RMON_R_BC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
+#define ENET_RMON_R_BC_PKT_COUNT_SET(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
+#define ENET_RMON_R_BC_PKT_COUNT ENET_RMON_R_BC_PKT_COUNT_MASK
 
 /*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */
 #define ENET_RMON_R_MC_PKT_COUNT_MASK            (0xFFFFU)
 #define ENET_RMON_R_MC_PKT_COUNT_SHIFT           (0U)
-#define ENET_RMON_R_MC_PKT_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
+#define ENET_RMON_R_MC_PKT_COUNT_SET(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
+#define ENET_RMON_R_MC_PKT_COUNT ENET_RMON_R_MC_PKT_COUNT_MASK
 
 /*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */
 #define ENET_RMON_R_CRC_ALIGN_COUNT_MASK         (0xFFFFU)
 #define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT        (0U)
-#define ENET_RMON_R_CRC_ALIGN_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
+#define ENET_RMON_R_CRC_ALIGN_COUNT_SET(x)       (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
+#define ENET_RMON_R_CRC_ALIGN_COUNT ENET_RMON_R_CRC_ALIGN_COUNT_MASK
 
 /*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */
 #define ENET_RMON_R_UNDERSIZE_COUNT_MASK         (0xFFFFU)
 #define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT        (0U)
-#define ENET_RMON_R_UNDERSIZE_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
+#define ENET_RMON_R_UNDERSIZE_COUNT_SET(x)       (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
+#define ENET_RMON_R_UNDERSIZE_COUNT ENET_RMON_R_UNDERSIZE_COUNT_MASK
 
 /*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */
 #define ENET_RMON_R_OVERSIZE_COUNT_MASK          (0xFFFFU)
 #define ENET_RMON_R_OVERSIZE_COUNT_SHIFT         (0U)
-#define ENET_RMON_R_OVERSIZE_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
+#define ENET_RMON_R_OVERSIZE_COUNT_SET(x)        (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
+#define ENET_RMON_R_OVERSIZE_COUNT ENET_RMON_R_OVERSIZE_COUNT_MASK
 
 /*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
 #define ENET_RMON_R_FRAG_COUNT_MASK              (0xFFFFU)
 #define ENET_RMON_R_FRAG_COUNT_SHIFT             (0U)
-#define ENET_RMON_R_FRAG_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
+#define ENET_RMON_R_FRAG_COUNT_SET(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
+#define ENET_RMON_R_FRAG_COUNT ENET_RMON_R_FRAG_COUNT_MASK
 
 /*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */
 #define ENET_RMON_R_JAB_COUNT_MASK               (0xFFFFU)
 #define ENET_RMON_R_JAB_COUNT_SHIFT              (0U)
-#define ENET_RMON_R_JAB_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
+#define ENET_RMON_R_JAB_COUNT_SET(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
+#define ENET_RMON_R_JAB_COUNT ENET_RMON_R_JAB_COUNT_MASK
 
 /*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */
 #define ENET_RMON_R_P64_COUNT_MASK               (0xFFFFU)
 #define ENET_RMON_R_P64_COUNT_SHIFT              (0U)
-#define ENET_RMON_R_P64_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
+#define ENET_RMON_R_P64_COUNT_SET(x)             (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
+#define ENET_RMON_R_P64_COUNT ENET_RMON_R_P64_COUNT_MASK
 
 /*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */
 #define ENET_RMON_R_P65TO127_COUNT_MASK          (0xFFFFU)
 #define ENET_RMON_R_P65TO127_COUNT_SHIFT         (0U)
-#define ENET_RMON_R_P65TO127_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
+#define ENET_RMON_R_P65TO127_COUNT_SET(x)        (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
+#define ENET_RMON_R_P65TO127_COUNT ENET_RMON_R_P65TO127_COUNT_MASK
 
 /*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */
 #define ENET_RMON_R_P128TO255_COUNT_MASK         (0xFFFFU)
 #define ENET_RMON_R_P128TO255_COUNT_SHIFT        (0U)
-#define ENET_RMON_R_P128TO255_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
+#define ENET_RMON_R_P128TO255_COUNT_SET(x)       (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
+#define ENET_RMON_R_P128TO255_COUNT ENET_RMON_R_P128TO255_COUNT_MASK
 
 /*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */
 #define ENET_RMON_R_P256TO511_COUNT_MASK         (0xFFFFU)
 #define ENET_RMON_R_P256TO511_COUNT_SHIFT        (0U)
-#define ENET_RMON_R_P256TO511_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
+#define ENET_RMON_R_P256TO511_COUNT_SET(x)       (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
+#define ENET_RMON_R_P256TO511_COUNT ENET_RMON_R_P256TO511_COUNT_MASK
 
 /*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */
 #define ENET_RMON_R_P512TO1023_COUNT_MASK        (0xFFFFU)
 #define ENET_RMON_R_P512TO1023_COUNT_SHIFT       (0U)
-#define ENET_RMON_R_P512TO1023_COUNT(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
+#define ENET_RMON_R_P512TO1023_COUNT_SET(x)      (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
+#define ENET_RMON_R_P512TO1023_COUNT ENET_RMON_R_P512TO1023_COUNT_MASK
 
 /*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */
 #define ENET_RMON_R_P1024TO2047_COUNT_MASK       (0xFFFFU)
 #define ENET_RMON_R_P1024TO2047_COUNT_SHIFT      (0U)
-#define ENET_RMON_R_P1024TO2047_COUNT(x)         (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
+#define ENET_RMON_R_P1024TO2047_COUNT_SET(x)     (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
+#define ENET_RMON_R_P1024TO2047_COUNT ENET_RMON_R_P1024TO2047_COUNT_MASK
 
 /*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */
 #define ENET_RMON_R_P_GTE2048_COUNT_MASK         (0xFFFFU)
 #define ENET_RMON_R_P_GTE2048_COUNT_SHIFT        (0U)
-#define ENET_RMON_R_P_GTE2048_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
+#define ENET_RMON_R_P_GTE2048_COUNT_SET(x)       (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
+#define ENET_RMON_R_P_GTE2048_COUNT ENET_RMON_R_P_GTE2048_COUNT_MASK
 
 /*! @name RMON_R_OCTETS - Rx Octets Statistic Register */
 #define ENET_RMON_R_OCTETS_COUNT_MASK            (0xFFFFFFFFU)
 #define ENET_RMON_R_OCTETS_COUNT_SHIFT           (0U)
-#define ENET_RMON_R_OCTETS_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
+#define ENET_RMON_R_OCTETS_COUNT_SET(x)          (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
+#define ENET_RMON_R_OCTETS_COUNT ENET_RMON_R_OCTETS_COUNT_MASK
 
 /*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */
 #define ENET_IEEE_R_DROP_COUNT_MASK              (0xFFFFU)
 #define ENET_IEEE_R_DROP_COUNT_SHIFT             (0U)
-#define ENET_IEEE_R_DROP_COUNT(x)                (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
+#define ENET_IEEE_R_DROP_COUNT_SET(x)            (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
+#define ENET_IEEE_R_DROP_COUNT ENET_IEEE_R_DROP_COUNT_MASK
 
 /*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */
 #define ENET_IEEE_R_FRAME_OK_COUNT_MASK          (0xFFFFU)
 #define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT         (0U)
-#define ENET_IEEE_R_FRAME_OK_COUNT(x)            (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
+#define ENET_IEEE_R_FRAME_OK_COUNT_SET(x)        (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
+#define ENET_IEEE_R_FRAME_OK_COUNT ENET_IEEE_R_FRAME_OK_COUNT_MASK
 
 /*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */
 #define ENET_IEEE_R_CRC_COUNT_MASK               (0xFFFFU)
 #define ENET_IEEE_R_CRC_COUNT_SHIFT              (0U)
-#define ENET_IEEE_R_CRC_COUNT(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
+#define ENET_IEEE_R_CRC_COUNT_SET(x)             (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
+#define ENET_IEEE_R_CRC_COUNT ENET_IEEE_R_CRC_COUNT_MASK
 
 /*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */
 #define ENET_IEEE_R_ALIGN_COUNT_MASK             (0xFFFFU)
 #define ENET_IEEE_R_ALIGN_COUNT_SHIFT            (0U)
-#define ENET_IEEE_R_ALIGN_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
+#define ENET_IEEE_R_ALIGN_COUNT_SET(x)           (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
+#define ENET_IEEE_R_ALIGN_COUNT ENET_IEEE_R_ALIGN_COUNT_MASK
 
 /*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */
 #define ENET_IEEE_R_MACERR_COUNT_MASK            (0xFFFFU)
 #define ENET_IEEE_R_MACERR_COUNT_SHIFT           (0U)
-#define ENET_IEEE_R_MACERR_COUNT(x)              (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
+#define ENET_IEEE_R_MACERR_COUNT_SET(x)          (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
+#define ENET_IEEE_R_MACERR_COUNT ENET_IEEE_R_MACERR_COUNT_MASK
 
 /*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */
 #define ENET_IEEE_R_FDXFC_COUNT_MASK             (0xFFFFU)
 #define ENET_IEEE_R_FDXFC_COUNT_SHIFT            (0U)
-#define ENET_IEEE_R_FDXFC_COUNT(x)               (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
+#define ENET_IEEE_R_FDXFC_COUNT_SET(x)           (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
+#define ENET_IEEE_R_FDXFC_COUNT ENET_IEEE_R_FDXFC_COUNT_MASK
 
 /*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */
 #define ENET_IEEE_R_OCTETS_OK_COUNT_MASK         (0xFFFFFFFFU)
 #define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT        (0U)
-#define ENET_IEEE_R_OCTETS_OK_COUNT(x)           (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
+#define ENET_IEEE_R_OCTETS_OK_COUNT_SET(x)       (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
+#define ENET_IEEE_R_OCTETS_OK_COUNT ENET_IEEE_R_OCTETS_OK_COUNT_MASK
 
 /*! @name ATCR - Adjustable Timer Control Register */
 #define ENET_ATCR_EN_MASK                        (0x1U)
 #define ENET_ATCR_EN_SHIFT                       (0U)
-#define ENET_ATCR_EN(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
+#define ENET_ATCR_EN_SET(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
+#define ENET_ATCR_EN ENET_ATCR_EN_MASK
 #define ENET_ATCR_OFFEN_MASK                     (0x4U)
 #define ENET_ATCR_OFFEN_SHIFT                    (2U)
-#define ENET_ATCR_OFFEN(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
+#define ENET_ATCR_OFFEN_SET(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
+#define ENET_ATCR_OFFEN ENET_ATCR_OFFEN_MASK
 #define ENET_ATCR_OFFRST_MASK                    (0x8U)
 #define ENET_ATCR_OFFRST_SHIFT                   (3U)
-#define ENET_ATCR_OFFRST(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
+#define ENET_ATCR_OFFRST_SET(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
+#define ENET_ATCR_OFFRST ENET_ATCR_OFFRST_MASK
 #define ENET_ATCR_PEREN_MASK                     (0x10U)
 #define ENET_ATCR_PEREN_SHIFT                    (4U)
-#define ENET_ATCR_PEREN(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
+#define ENET_ATCR_PEREN_SET(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
+#define ENET_ATCR_PEREN ENET_ATCR_PEREN_MASK
 #define ENET_ATCR_PINPER_MASK                    (0x80U)
 #define ENET_ATCR_PINPER_SHIFT                   (7U)
-#define ENET_ATCR_PINPER(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
+#define ENET_ATCR_PINPER_SET(x)                  (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
+#define ENET_ATCR_PINPER ENET_ATCR_PINPER_MASK
 #define ENET_ATCR_RESTART_MASK                   (0x200U)
 #define ENET_ATCR_RESTART_SHIFT                  (9U)
-#define ENET_ATCR_RESTART(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
+#define ENET_ATCR_RESTART_SET(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
+#define ENET_ATCR_RESTART ENET_ATCR_RESTART_MASK
 #define ENET_ATCR_CAPTURE_MASK                   (0x800U)
 #define ENET_ATCR_CAPTURE_SHIFT                  (11U)
-#define ENET_ATCR_CAPTURE(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
+#define ENET_ATCR_CAPTURE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
+#define ENET_ATCR_CAPTURE ENET_ATCR_CAPTURE_MASK
 #define ENET_ATCR_SLAVE_MASK                     (0x2000U)
 #define ENET_ATCR_SLAVE_SHIFT                    (13U)
-#define ENET_ATCR_SLAVE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
+#define ENET_ATCR_SLAVE_SET(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
+#define ENET_ATCR_SLAVE ENET_ATCR_SLAVE_MASK
 
 /*! @name ATVR - Timer Value Register */
 #define ENET_ATVR_ATIME_MASK                     (0xFFFFFFFFU)
 #define ENET_ATVR_ATIME_SHIFT                    (0U)
-#define ENET_ATVR_ATIME(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
+#define ENET_ATVR_ATIME_SET(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
+#define ENET_ATVR_ATIME ENET_ATVR_ATIME_MASK
 
 /*! @name ATOFF - Timer Offset Register */
 #define ENET_ATOFF_OFFSET_MASK                   (0xFFFFFFFFU)
 #define ENET_ATOFF_OFFSET_SHIFT                  (0U)
-#define ENET_ATOFF_OFFSET(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
+#define ENET_ATOFF_OFFSET_SET(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
+#define ENET_ATOFF_OFFSET ENET_ATOFF_OFFSET_MASK
 
 /*! @name ATPER - Timer Period Register */
 #define ENET_ATPER_PERIOD_MASK                   (0xFFFFFFFFU)
 #define ENET_ATPER_PERIOD_SHIFT                  (0U)
-#define ENET_ATPER_PERIOD(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
+#define ENET_ATPER_PERIOD_SET(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
+#define ENET_ATPER_PERIOD ENET_ATPER_PERIOD_MASK
 
 /*! @name ATCOR - Timer Correction Register */
 #define ENET_ATCOR_COR_MASK                      (0x7FFFFFFFU)
 #define ENET_ATCOR_COR_SHIFT                     (0U)
-#define ENET_ATCOR_COR(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
+#define ENET_ATCOR_COR_SET(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
+#define ENET_ATCOR_COR ENET_ATCOR_COR_MASK
 
 /*! @name ATINC - Time-Stamping Clock Period Register */
 #define ENET_ATINC_INC_MASK                      (0x7FU)
 #define ENET_ATINC_INC_SHIFT                     (0U)
-#define ENET_ATINC_INC(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
+#define ENET_ATINC_INC_SET(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
+#define ENET_ATINC_INC ENET_ATINC_INC_MASK
 #define ENET_ATINC_INC_CORR_MASK                 (0x7F00U)
 #define ENET_ATINC_INC_CORR_SHIFT                (8U)
-#define ENET_ATINC_INC_CORR(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
+#define ENET_ATINC_INC_CORR_SET(x)               (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
+#define ENET_ATINC_INC_CORR ENET_ATINC_INC_CORR_MASK
 
 /*! @name ATSTMP - Timestamp of Last Transmitted Frame */
 #define ENET_ATSTMP_TIMESTAMP_MASK               (0xFFFFFFFFU)
 #define ENET_ATSTMP_TIMESTAMP_SHIFT              (0U)
-#define ENET_ATSTMP_TIMESTAMP(x)                 (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
+#define ENET_ATSTMP_TIMESTAMP_SET(x)             (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
+#define ENET_ATSTMP_TIMESTAMP ENET_ATSTMP_TIMESTAMP_MASK
 
 /*! @name TGSR - Timer Global Status Register */
 #define ENET_TGSR_TF0_MASK                       (0x1U)
 #define ENET_TGSR_TF0_SHIFT                      (0U)
-#define ENET_TGSR_TF0(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
+#define ENET_TGSR_TF0_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
+#define ENET_TGSR_TF0 ENET_TGSR_TF0_MASK
 #define ENET_TGSR_TF1_MASK                       (0x2U)
 #define ENET_TGSR_TF1_SHIFT                      (1U)
-#define ENET_TGSR_TF1(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
+#define ENET_TGSR_TF1_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
+#define ENET_TGSR_TF1 ENET_TGSR_TF1_MASK
 #define ENET_TGSR_TF2_MASK                       (0x4U)
 #define ENET_TGSR_TF2_SHIFT                      (2U)
-#define ENET_TGSR_TF2(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
+#define ENET_TGSR_TF2_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
+#define ENET_TGSR_TF2 ENET_TGSR_TF2_MASK
 #define ENET_TGSR_TF3_MASK                       (0x8U)
 #define ENET_TGSR_TF3_SHIFT                      (3U)
-#define ENET_TGSR_TF3(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
+#define ENET_TGSR_TF3_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
+#define ENET_TGSR_TF3 ENET_TGSR_TF3_MASK
 
 /*! @name TCSR - Timer Control Status Register */
 #define ENET_TCSR_TDRE_MASK                      (0x1U)
 #define ENET_TCSR_TDRE_SHIFT                     (0U)
-#define ENET_TCSR_TDRE(x)                        (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
+#define ENET_TCSR_TDRE_SET(x)                    (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
+#define ENET_TCSR_TDRE ENET_TCSR_TDRE_MASK
 #define ENET_TCSR_TMODE_MASK                     (0x3CU)
 #define ENET_TCSR_TMODE_SHIFT                    (2U)
-#define ENET_TCSR_TMODE(x)                       (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
+#define ENET_TCSR_TMODE_SET(x)                   (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
+#define ENET_TCSR_TMODE ENET_TCSR_TMODE_MASK
 #define ENET_TCSR_TIE_MASK                       (0x40U)
 #define ENET_TCSR_TIE_SHIFT                      (6U)
-#define ENET_TCSR_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
+#define ENET_TCSR_TIE_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
+#define ENET_TCSR_TIE ENET_TCSR_TIE_MASK
 #define ENET_TCSR_TF_MASK                        (0x80U)
 #define ENET_TCSR_TF_SHIFT                       (7U)
-#define ENET_TCSR_TF(x)                          (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
+#define ENET_TCSR_TF_SET(x)                      (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
+#define ENET_TCSR_TF ENET_TCSR_TF_MASK
 
 /* The count of ENET_TCSR */
 #define ENET_TCSR_COUNT                          (4U)
@@ -6168,7 +7543,8 @@ typedef struct {
 /*! @name TCCR - Timer Compare Capture Register */
 #define ENET_TCCR_TCC_MASK                       (0xFFFFFFFFU)
 #define ENET_TCCR_TCC_SHIFT                      (0U)
-#define ENET_TCCR_TCC(x)                         (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
+#define ENET_TCCR_TCC_SET(x)                     (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
+#define ENET_TCCR_TCC ENET_TCCR_TCC_MASK
 
 /* The count of ENET_TCCR */
 #define ENET_TCCR_COUNT                          (4U)
@@ -6183,7 +7559,7 @@ typedef struct {
 /** Peripheral ENET base address */
 #define ENET_BASE                                (0x400C0000u)
 /** Peripheral ENET base pointer */
-#define ENET                                     ((ENET_Type *)ENET_BASE)
+#define ENET                                     ((ENET_TypeDef *)ENET_BASE)
 /** Array initializer of ENET peripheral base addresses */
 #define ENET_BASE_ADDRS                          { ENET_BASE }
 /** Array initializer of ENET peripheral base pointers */
@@ -6217,7 +7593,7 @@ typedef struct {
   __O  uint8_t SERV;                               /**< Service Register, offset: 0x1 */
   __IO uint8_t CMPL;                               /**< Compare Low Register, offset: 0x2 */
   __IO uint8_t CMPH;                               /**< Compare High Register, offset: 0x3 */
-} EWM_Type;
+} EWM_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- EWM Register Masks
@@ -6231,31 +7607,38 @@ typedef struct {
 /*! @name CTRL - Control Register */
 #define EWM_CTRL_EWMEN_MASK                      (0x1U)
 #define EWM_CTRL_EWMEN_SHIFT                     (0U)
-#define EWM_CTRL_EWMEN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
+#define EWM_CTRL_EWMEN_SET(x)                    (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
+#define EWM_CTRL_EWMEN EWM_CTRL_EWMEN_MASK
 #define EWM_CTRL_ASSIN_MASK                      (0x2U)
 #define EWM_CTRL_ASSIN_SHIFT                     (1U)
-#define EWM_CTRL_ASSIN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
+#define EWM_CTRL_ASSIN_SET(x)                    (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
+#define EWM_CTRL_ASSIN EWM_CTRL_ASSIN_MASK
 #define EWM_CTRL_INEN_MASK                       (0x4U)
 #define EWM_CTRL_INEN_SHIFT                      (2U)
-#define EWM_CTRL_INEN(x)                         (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
+#define EWM_CTRL_INEN_SET(x)                     (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
+#define EWM_CTRL_INEN EWM_CTRL_INEN_MASK
 #define EWM_CTRL_INTEN_MASK                      (0x8U)
 #define EWM_CTRL_INTEN_SHIFT                     (3U)
-#define EWM_CTRL_INTEN(x)                        (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
+#define EWM_CTRL_INTEN_SET(x)                    (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
+#define EWM_CTRL_INTEN EWM_CTRL_INTEN_MASK
 
 /*! @name SERV - Service Register */
 #define EWM_SERV_SERVICE_MASK                    (0xFFU)
 #define EWM_SERV_SERVICE_SHIFT                   (0U)
-#define EWM_SERV_SERVICE(x)                      (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
+#define EWM_SERV_SERVICE_SET(x)                  (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
+#define EWM_SERV_SERVICE EWM_SERV_SERVICE_MASK
 
 /*! @name CMPL - Compare Low Register */
 #define EWM_CMPL_COMPAREL_MASK                   (0xFFU)
 #define EWM_CMPL_COMPAREL_SHIFT                  (0U)
-#define EWM_CMPL_COMPAREL(x)                     (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
+#define EWM_CMPL_COMPAREL_SET(x)                 (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
+#define EWM_CMPL_COMPAREL EWM_CMPL_COMPAREL_MASK
 
 /*! @name CMPH - Compare High Register */
 #define EWM_CMPH_COMPAREH_MASK                   (0xFFU)
 #define EWM_CMPH_COMPAREH_SHIFT                  (0U)
-#define EWM_CMPH_COMPAREH(x)                     (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
+#define EWM_CMPH_COMPAREH_SET(x)                 (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
+#define EWM_CMPH_COMPAREH EWM_CMPH_COMPAREH_MASK
 
 
 /*!
@@ -6267,7 +7650,7 @@ typedef struct {
 /** Peripheral EWM base address */
 #define EWM_BASE                                 (0x40061000u)
 /** Peripheral EWM base pointer */
-#define EWM                                      ((EWM_Type *)EWM_BASE)
+#define EWM                                      ((EWM_TypeDef *)EWM_BASE)
 /** Array initializer of EWM peripheral base addresses */
 #define EWM_BASE_ADDRS                           { EWM_BASE }
 /** Array initializer of EWM peripheral base pointers */
@@ -6298,7 +7681,7 @@ typedef struct {
   } CS[6];
        uint8_t RESERVED_0[24];
   __IO uint32_t CSPMCR;                            /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
-} FB_Type;
+} FB_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- FB Register Masks
@@ -6312,7 +7695,8 @@ typedef struct {
 /*! @name CSAR - Chip Select Address Register */
 #define FB_CSAR_BA_MASK                          (0xFFFF0000U)
 #define FB_CSAR_BA_SHIFT                         (16U)
-#define FB_CSAR_BA(x)                            (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK)
+#define FB_CSAR_BA_SET(x)                        (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK)
+#define FB_CSAR_BA FB_CSAR_BA_MASK
 
 /* The count of FB_CSAR */
 #define FB_CSAR_COUNT                            (6U)
@@ -6320,13 +7704,16 @@ typedef struct {
 /*! @name CSMR - Chip Select Mask Register */
 #define FB_CSMR_V_MASK                           (0x1U)
 #define FB_CSMR_V_SHIFT                          (0U)
-#define FB_CSMR_V(x)                             (((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK)
+#define FB_CSMR_V_SET(x)                         (((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK)
+#define FB_CSMR_V FB_CSMR_V_MASK
 #define FB_CSMR_WP_MASK                          (0x100U)
 #define FB_CSMR_WP_SHIFT                         (8U)
-#define FB_CSMR_WP(x)                            (((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK)
+#define FB_CSMR_WP_SET(x)                        (((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK)
+#define FB_CSMR_WP FB_CSMR_WP_MASK
 #define FB_CSMR_BAM_MASK                         (0xFFFF0000U)
 #define FB_CSMR_BAM_SHIFT                        (16U)
-#define FB_CSMR_BAM(x)                           (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK)
+#define FB_CSMR_BAM_SET(x)                       (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK)
+#define FB_CSMR_BAM FB_CSMR_BAM_MASK
 
 /* The count of FB_CSMR */
 #define FB_CSMR_COUNT                            (6U)
@@ -6334,43 +7721,56 @@ typedef struct {
 /*! @name CSCR - Chip Select Control Register */
 #define FB_CSCR_BSTW_MASK                        (0x8U)
 #define FB_CSCR_BSTW_SHIFT                       (3U)
-#define FB_CSCR_BSTW(x)                          (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK)
+#define FB_CSCR_BSTW_SET(x)                      (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK)
+#define FB_CSCR_BSTW FB_CSCR_BSTW_MASK
 #define FB_CSCR_BSTR_MASK                        (0x10U)
 #define FB_CSCR_BSTR_SHIFT                       (4U)
-#define FB_CSCR_BSTR(x)                          (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK)
+#define FB_CSCR_BSTR_SET(x)                      (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK)
+#define FB_CSCR_BSTR FB_CSCR_BSTR_MASK
 #define FB_CSCR_BEM_MASK                         (0x20U)
 #define FB_CSCR_BEM_SHIFT                        (5U)
-#define FB_CSCR_BEM(x)                           (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK)
+#define FB_CSCR_BEM_SET(x)                       (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK)
+#define FB_CSCR_BEM FB_CSCR_BEM_MASK
 #define FB_CSCR_PS_MASK                          (0xC0U)
 #define FB_CSCR_PS_SHIFT                         (6U)
-#define FB_CSCR_PS(x)                            (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK)
+#define FB_CSCR_PS_SET(x)                        (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK)
+#define FB_CSCR_PS FB_CSCR_PS_MASK
 #define FB_CSCR_AA_MASK                          (0x100U)
 #define FB_CSCR_AA_SHIFT                         (8U)
-#define FB_CSCR_AA(x)                            (((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK)
+#define FB_CSCR_AA_SET(x)                        (((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK)
+#define FB_CSCR_AA FB_CSCR_AA_MASK
 #define FB_CSCR_BLS_MASK                         (0x200U)
 #define FB_CSCR_BLS_SHIFT                        (9U)
-#define FB_CSCR_BLS(x)                           (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK)
+#define FB_CSCR_BLS_SET(x)                       (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK)
+#define FB_CSCR_BLS FB_CSCR_BLS_MASK
 #define FB_CSCR_WS_MASK                          (0xFC00U)
 #define FB_CSCR_WS_SHIFT                         (10U)
-#define FB_CSCR_WS(x)                            (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK)
+#define FB_CSCR_WS_SET(x)                        (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK)
+#define FB_CSCR_WS FB_CSCR_WS_MASK
 #define FB_CSCR_WRAH_MASK                        (0x30000U)
 #define FB_CSCR_WRAH_SHIFT                       (16U)
-#define FB_CSCR_WRAH(x)                          (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK)
+#define FB_CSCR_WRAH_SET(x)                      (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK)
+#define FB_CSCR_WRAH FB_CSCR_WRAH_MASK
 #define FB_CSCR_RDAH_MASK                        (0xC0000U)
 #define FB_CSCR_RDAH_SHIFT                       (18U)
-#define FB_CSCR_RDAH(x)                          (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK)
+#define FB_CSCR_RDAH_SET(x)                      (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK)
+#define FB_CSCR_RDAH FB_CSCR_RDAH_MASK
 #define FB_CSCR_ASET_MASK                        (0x300000U)
 #define FB_CSCR_ASET_SHIFT                       (20U)
-#define FB_CSCR_ASET(x)                          (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK)
+#define FB_CSCR_ASET_SET(x)                      (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK)
+#define FB_CSCR_ASET FB_CSCR_ASET_MASK
 #define FB_CSCR_EXTS_MASK                        (0x400000U)
 #define FB_CSCR_EXTS_SHIFT                       (22U)
-#define FB_CSCR_EXTS(x)                          (((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK)
+#define FB_CSCR_EXTS_SET(x)                      (((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK)
+#define FB_CSCR_EXTS FB_CSCR_EXTS_MASK
 #define FB_CSCR_SWSEN_MASK                       (0x800000U)
 #define FB_CSCR_SWSEN_SHIFT                      (23U)
-#define FB_CSCR_SWSEN(x)                         (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK)
+#define FB_CSCR_SWSEN_SET(x)                     (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK)
+#define FB_CSCR_SWSEN FB_CSCR_SWSEN_MASK
 #define FB_CSCR_SWS_MASK                         (0xFC000000U)
 #define FB_CSCR_SWS_SHIFT                        (26U)
-#define FB_CSCR_SWS(x)                           (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK)
+#define FB_CSCR_SWS_SET(x)                       (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK)
+#define FB_CSCR_SWS FB_CSCR_SWS_MASK
 
 /* The count of FB_CSCR */
 #define FB_CSCR_COUNT                            (6U)
@@ -6378,19 +7778,24 @@ typedef struct {
 /*! @name CSPMCR - Chip Select port Multiplexing Control Register */
 #define FB_CSPMCR_GROUP5_MASK                    (0xF000U)
 #define FB_CSPMCR_GROUP5_SHIFT                   (12U)
-#define FB_CSPMCR_GROUP5(x)                      (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK)
+#define FB_CSPMCR_GROUP5_SET(x)                  (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK)
+#define FB_CSPMCR_GROUP5 FB_CSPMCR_GROUP5_MASK
 #define FB_CSPMCR_GROUP4_MASK                    (0xF0000U)
 #define FB_CSPMCR_GROUP4_SHIFT                   (16U)
-#define FB_CSPMCR_GROUP4(x)                      (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK)
+#define FB_CSPMCR_GROUP4_SET(x)                  (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK)
+#define FB_CSPMCR_GROUP4 FB_CSPMCR_GROUP4_MASK
 #define FB_CSPMCR_GROUP3_MASK                    (0xF00000U)
 #define FB_CSPMCR_GROUP3_SHIFT                   (20U)
-#define FB_CSPMCR_GROUP3(x)                      (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK)
+#define FB_CSPMCR_GROUP3_SET(x)                  (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK)
+#define FB_CSPMCR_GROUP3 FB_CSPMCR_GROUP3_MASK
 #define FB_CSPMCR_GROUP2_MASK                    (0xF000000U)
 #define FB_CSPMCR_GROUP2_SHIFT                   (24U)
-#define FB_CSPMCR_GROUP2(x)                      (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK)
+#define FB_CSPMCR_GROUP2_SET(x)                  (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK)
+#define FB_CSPMCR_GROUP2 FB_CSPMCR_GROUP2_MASK
 #define FB_CSPMCR_GROUP1_MASK                    (0xF0000000U)
 #define FB_CSPMCR_GROUP1_SHIFT                   (28U)
-#define FB_CSPMCR_GROUP1(x)                      (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK)
+#define FB_CSPMCR_GROUP1_SET(x)                  (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK)
+#define FB_CSPMCR_GROUP1 FB_CSPMCR_GROUP1_MASK
 
 
 /*!
@@ -6402,7 +7807,7 @@ typedef struct {
 /** Peripheral FB base address */
 #define FB_BASE                                  (0x4000C000u)
 /** Peripheral FB base pointer */
-#define FB                                       ((FB_Type *)FB_BASE)
+#define FB                                       ((FB_TypeDef *)FB_BASE)
 /** Array initializer of FB peripheral base addresses */
 #define FB_BASE_ADDRS                            { FB_BASE }
 /** Array initializer of FB peripheral base pointers */
@@ -6439,7 +7844,7 @@ typedef struct {
     __IO uint32_t DATA_ML;                           /**< Cache Data Storage (mid-lower word), array offset: 0x208, array step: index*0x40, index2*0x10 */
     __IO uint32_t DATA_LM;                           /**< Cache Data Storage (lowermost word), array offset: 0x20C, array step: index*0x40, index2*0x10 */
   } SET[4][4];
-} FMC_Type;
+} FMC_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- FMC Register Masks
@@ -6453,118 +7858,154 @@ typedef struct {
 /*! @name PFAPR - Flash Access Protection Register */
 #define FMC_PFAPR_M0AP_MASK                      (0x3U)
 #define FMC_PFAPR_M0AP_SHIFT                     (0U)
-#define FMC_PFAPR_M0AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)
+#define FMC_PFAPR_M0AP_SET(x)                    (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)
+#define FMC_PFAPR_M0AP FMC_PFAPR_M0AP_MASK
 #define FMC_PFAPR_M1AP_MASK                      (0xCU)
 #define FMC_PFAPR_M1AP_SHIFT                     (2U)
-#define FMC_PFAPR_M1AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)
+#define FMC_PFAPR_M1AP_SET(x)                    (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)
+#define FMC_PFAPR_M1AP FMC_PFAPR_M1AP_MASK
 #define FMC_PFAPR_M2AP_MASK                      (0x30U)
 #define FMC_PFAPR_M2AP_SHIFT                     (4U)
-#define FMC_PFAPR_M2AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)
+#define FMC_PFAPR_M2AP_SET(x)                    (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)
+#define FMC_PFAPR_M2AP FMC_PFAPR_M2AP_MASK
 #define FMC_PFAPR_M3AP_MASK                      (0xC0U)
 #define FMC_PFAPR_M3AP_SHIFT                     (6U)
-#define FMC_PFAPR_M3AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)
+#define FMC_PFAPR_M3AP_SET(x)                    (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)
+#define FMC_PFAPR_M3AP FMC_PFAPR_M3AP_MASK
 #define FMC_PFAPR_M4AP_MASK                      (0x300U)
 #define FMC_PFAPR_M4AP_SHIFT                     (8U)
-#define FMC_PFAPR_M4AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK)
+#define FMC_PFAPR_M4AP_SET(x)                    (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK)
+#define FMC_PFAPR_M4AP FMC_PFAPR_M4AP_MASK
 #define FMC_PFAPR_M5AP_MASK                      (0xC00U)
 #define FMC_PFAPR_M5AP_SHIFT                     (10U)
-#define FMC_PFAPR_M5AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK)
+#define FMC_PFAPR_M5AP_SET(x)                    (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK)
+#define FMC_PFAPR_M5AP FMC_PFAPR_M5AP_MASK
 #define FMC_PFAPR_M6AP_MASK                      (0x3000U)
 #define FMC_PFAPR_M6AP_SHIFT                     (12U)
-#define FMC_PFAPR_M6AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK)
+#define FMC_PFAPR_M6AP_SET(x)                    (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK)
+#define FMC_PFAPR_M6AP FMC_PFAPR_M6AP_MASK
 #define FMC_PFAPR_M7AP_MASK                      (0xC000U)
 #define FMC_PFAPR_M7AP_SHIFT                     (14U)
-#define FMC_PFAPR_M7AP(x)                        (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK)
+#define FMC_PFAPR_M7AP_SET(x)                    (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK)
+#define FMC_PFAPR_M7AP FMC_PFAPR_M7AP_MASK
 #define FMC_PFAPR_M0PFD_MASK                     (0x10000U)
 #define FMC_PFAPR_M0PFD_SHIFT                    (16U)
-#define FMC_PFAPR_M0PFD(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)
+#define FMC_PFAPR_M0PFD_SET(x)                   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)
+#define FMC_PFAPR_M0PFD FMC_PFAPR_M0PFD_MASK
 #define FMC_PFAPR_M1PFD_MASK                     (0x20000U)
 #define FMC_PFAPR_M1PFD_SHIFT                    (17U)
-#define FMC_PFAPR_M1PFD(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)
+#define FMC_PFAPR_M1PFD_SET(x)                   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)
+#define FMC_PFAPR_M1PFD FMC_PFAPR_M1PFD_MASK
 #define FMC_PFAPR_M2PFD_MASK                     (0x40000U)
 #define FMC_PFAPR_M2PFD_SHIFT                    (18U)
-#define FMC_PFAPR_M2PFD(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)
+#define FMC_PFAPR_M2PFD_SET(x)                   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)
+#define FMC_PFAPR_M2PFD FMC_PFAPR_M2PFD_MASK
 #define FMC_PFAPR_M3PFD_MASK                     (0x80000U)
 #define FMC_PFAPR_M3PFD_SHIFT                    (19U)
-#define FMC_PFAPR_M3PFD(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)
+#define FMC_PFAPR_M3PFD_SET(x)                   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)
+#define FMC_PFAPR_M3PFD FMC_PFAPR_M3PFD_MASK
 #define FMC_PFAPR_M4PFD_MASK                     (0x100000U)
 #define FMC_PFAPR_M4PFD_SHIFT                    (20U)
-#define FMC_PFAPR_M4PFD(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK)
+#define FMC_PFAPR_M4PFD_SET(x)                   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK)
+#define FMC_PFAPR_M4PFD FMC_PFAPR_M4PFD_MASK
 #define FMC_PFAPR_M5PFD_MASK                     (0x200000U)
 #define FMC_PFAPR_M5PFD_SHIFT                    (21U)
-#define FMC_PFAPR_M5PFD(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5PFD_SHIFT)) & FMC_PFAPR_M5PFD_MASK)
+#define FMC_PFAPR_M5PFD_SET(x)                   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5PFD_SHIFT)) & FMC_PFAPR_M5PFD_MASK)
+#define FMC_PFAPR_M5PFD FMC_PFAPR_M5PFD_MASK
 #define FMC_PFAPR_M6PFD_MASK                     (0x400000U)
 #define FMC_PFAPR_M6PFD_SHIFT                    (22U)
-#define FMC_PFAPR_M6PFD(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6PFD_SHIFT)) & FMC_PFAPR_M6PFD_MASK)
+#define FMC_PFAPR_M6PFD_SET(x)                   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6PFD_SHIFT)) & FMC_PFAPR_M6PFD_MASK)
+#define FMC_PFAPR_M6PFD FMC_PFAPR_M6PFD_MASK
 #define FMC_PFAPR_M7PFD_MASK                     (0x800000U)
 #define FMC_PFAPR_M7PFD_SHIFT                    (23U)
-#define FMC_PFAPR_M7PFD(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7PFD_SHIFT)) & FMC_PFAPR_M7PFD_MASK)
+#define FMC_PFAPR_M7PFD_SET(x)                   (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7PFD_SHIFT)) & FMC_PFAPR_M7PFD_MASK)
+#define FMC_PFAPR_M7PFD FMC_PFAPR_M7PFD_MASK
 
 /*! @name PFB01CR - Flash Bank 0-1 Control Register */
 #define FMC_PFB01CR_RFU_MASK                     (0x1U)
 #define FMC_PFB01CR_RFU_SHIFT                    (0U)
-#define FMC_PFB01CR_RFU(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_RFU_SHIFT)) & FMC_PFB01CR_RFU_MASK)
+#define FMC_PFB01CR_RFU_SET(x)                   (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_RFU_SHIFT)) & FMC_PFB01CR_RFU_MASK)
+#define FMC_PFB01CR_RFU FMC_PFB01CR_RFU_MASK
 #define FMC_PFB01CR_B0IPE_MASK                   (0x2U)
 #define FMC_PFB01CR_B0IPE_SHIFT                  (1U)
-#define FMC_PFB01CR_B0IPE(x)                     (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0IPE_SHIFT)) & FMC_PFB01CR_B0IPE_MASK)
+#define FMC_PFB01CR_B0IPE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0IPE_SHIFT)) & FMC_PFB01CR_B0IPE_MASK)
+#define FMC_PFB01CR_B0IPE FMC_PFB01CR_B0IPE_MASK
 #define FMC_PFB01CR_B0DPE_MASK                   (0x4U)
 #define FMC_PFB01CR_B0DPE_SHIFT                  (2U)
-#define FMC_PFB01CR_B0DPE(x)                     (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0DPE_SHIFT)) & FMC_PFB01CR_B0DPE_MASK)
+#define FMC_PFB01CR_B0DPE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0DPE_SHIFT)) & FMC_PFB01CR_B0DPE_MASK)
+#define FMC_PFB01CR_B0DPE FMC_PFB01CR_B0DPE_MASK
 #define FMC_PFB01CR_B0ICE_MASK                   (0x8U)
 #define FMC_PFB01CR_B0ICE_SHIFT                  (3U)
-#define FMC_PFB01CR_B0ICE(x)                     (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0ICE_SHIFT)) & FMC_PFB01CR_B0ICE_MASK)
+#define FMC_PFB01CR_B0ICE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0ICE_SHIFT)) & FMC_PFB01CR_B0ICE_MASK)
+#define FMC_PFB01CR_B0ICE FMC_PFB01CR_B0ICE_MASK
 #define FMC_PFB01CR_B0DCE_MASK                   (0x10U)
 #define FMC_PFB01CR_B0DCE_SHIFT                  (4U)
-#define FMC_PFB01CR_B0DCE(x)                     (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0DCE_SHIFT)) & FMC_PFB01CR_B0DCE_MASK)
+#define FMC_PFB01CR_B0DCE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0DCE_SHIFT)) & FMC_PFB01CR_B0DCE_MASK)
+#define FMC_PFB01CR_B0DCE FMC_PFB01CR_B0DCE_MASK
 #define FMC_PFB01CR_CRC_MASK                     (0xE0U)
 #define FMC_PFB01CR_CRC_SHIFT                    (5U)
-#define FMC_PFB01CR_CRC(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_CRC_SHIFT)) & FMC_PFB01CR_CRC_MASK)
+#define FMC_PFB01CR_CRC_SET(x)                   (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_CRC_SHIFT)) & FMC_PFB01CR_CRC_MASK)
+#define FMC_PFB01CR_CRC FMC_PFB01CR_CRC_MASK
 #define FMC_PFB01CR_B0MW_MASK                    (0x60000U)
 #define FMC_PFB01CR_B0MW_SHIFT                   (17U)
-#define FMC_PFB01CR_B0MW(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0MW_SHIFT)) & FMC_PFB01CR_B0MW_MASK)
+#define FMC_PFB01CR_B0MW_SET(x)                  (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0MW_SHIFT)) & FMC_PFB01CR_B0MW_MASK)
+#define FMC_PFB01CR_B0MW FMC_PFB01CR_B0MW_MASK
 #define FMC_PFB01CR_S_B_INV_MASK                 (0x80000U)
 #define FMC_PFB01CR_S_B_INV_SHIFT                (19U)
-#define FMC_PFB01CR_S_B_INV(x)                   (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_S_B_INV_SHIFT)) & FMC_PFB01CR_S_B_INV_MASK)
+#define FMC_PFB01CR_S_B_INV_SET(x)               (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_S_B_INV_SHIFT)) & FMC_PFB01CR_S_B_INV_MASK)
+#define FMC_PFB01CR_S_B_INV FMC_PFB01CR_S_B_INV_MASK
 #define FMC_PFB01CR_CINV_WAY_MASK                (0xF00000U)
 #define FMC_PFB01CR_CINV_WAY_SHIFT               (20U)
-#define FMC_PFB01CR_CINV_WAY(x)                  (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_CINV_WAY_SHIFT)) & FMC_PFB01CR_CINV_WAY_MASK)
+#define FMC_PFB01CR_CINV_WAY_SET(x)              (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_CINV_WAY_SHIFT)) & FMC_PFB01CR_CINV_WAY_MASK)
+#define FMC_PFB01CR_CINV_WAY FMC_PFB01CR_CINV_WAY_MASK
 #define FMC_PFB01CR_CLCK_WAY_MASK                (0xF000000U)
 #define FMC_PFB01CR_CLCK_WAY_SHIFT               (24U)
-#define FMC_PFB01CR_CLCK_WAY(x)                  (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_CLCK_WAY_SHIFT)) & FMC_PFB01CR_CLCK_WAY_MASK)
+#define FMC_PFB01CR_CLCK_WAY_SET(x)              (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_CLCK_WAY_SHIFT)) & FMC_PFB01CR_CLCK_WAY_MASK)
+#define FMC_PFB01CR_CLCK_WAY FMC_PFB01CR_CLCK_WAY_MASK
 #define FMC_PFB01CR_B0RWSC_MASK                  (0xF0000000U)
 #define FMC_PFB01CR_B0RWSC_SHIFT                 (28U)
-#define FMC_PFB01CR_B0RWSC(x)                    (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0RWSC_SHIFT)) & FMC_PFB01CR_B0RWSC_MASK)
+#define FMC_PFB01CR_B0RWSC_SET(x)                (((uint32_t)(((uint32_t)(x)) << FMC_PFB01CR_B0RWSC_SHIFT)) & FMC_PFB01CR_B0RWSC_MASK)
+#define FMC_PFB01CR_B0RWSC FMC_PFB01CR_B0RWSC_MASK
 
 /*! @name PFB23CR - Flash Bank 2-3 Control Register */
 #define FMC_PFB23CR_RFU_MASK                     (0x1U)
 #define FMC_PFB23CR_RFU_SHIFT                    (0U)
-#define FMC_PFB23CR_RFU(x)                       (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_RFU_SHIFT)) & FMC_PFB23CR_RFU_MASK)
+#define FMC_PFB23CR_RFU_SET(x)                   (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_RFU_SHIFT)) & FMC_PFB23CR_RFU_MASK)
+#define FMC_PFB23CR_RFU FMC_PFB23CR_RFU_MASK
 #define FMC_PFB23CR_B1IPE_MASK                   (0x2U)
 #define FMC_PFB23CR_B1IPE_SHIFT                  (1U)
-#define FMC_PFB23CR_B1IPE(x)                     (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1IPE_SHIFT)) & FMC_PFB23CR_B1IPE_MASK)
+#define FMC_PFB23CR_B1IPE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1IPE_SHIFT)) & FMC_PFB23CR_B1IPE_MASK)
+#define FMC_PFB23CR_B1IPE FMC_PFB23CR_B1IPE_MASK
 #define FMC_PFB23CR_B1DPE_MASK                   (0x4U)
 #define FMC_PFB23CR_B1DPE_SHIFT                  (2U)
-#define FMC_PFB23CR_B1DPE(x)                     (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1DPE_SHIFT)) & FMC_PFB23CR_B1DPE_MASK)
+#define FMC_PFB23CR_B1DPE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1DPE_SHIFT)) & FMC_PFB23CR_B1DPE_MASK)
+#define FMC_PFB23CR_B1DPE FMC_PFB23CR_B1DPE_MASK
 #define FMC_PFB23CR_B1ICE_MASK                   (0x8U)
 #define FMC_PFB23CR_B1ICE_SHIFT                  (3U)
-#define FMC_PFB23CR_B1ICE(x)                     (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1ICE_SHIFT)) & FMC_PFB23CR_B1ICE_MASK)
+#define FMC_PFB23CR_B1ICE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1ICE_SHIFT)) & FMC_PFB23CR_B1ICE_MASK)
+#define FMC_PFB23CR_B1ICE FMC_PFB23CR_B1ICE_MASK
 #define FMC_PFB23CR_B1DCE_MASK                   (0x10U)
 #define FMC_PFB23CR_B1DCE_SHIFT                  (4U)
-#define FMC_PFB23CR_B1DCE(x)                     (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1DCE_SHIFT)) & FMC_PFB23CR_B1DCE_MASK)
+#define FMC_PFB23CR_B1DCE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1DCE_SHIFT)) & FMC_PFB23CR_B1DCE_MASK)
+#define FMC_PFB23CR_B1DCE FMC_PFB23CR_B1DCE_MASK
 #define FMC_PFB23CR_B1MW_MASK                    (0x60000U)
 #define FMC_PFB23CR_B1MW_SHIFT                   (17U)
-#define FMC_PFB23CR_B1MW(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1MW_SHIFT)) & FMC_PFB23CR_B1MW_MASK)
+#define FMC_PFB23CR_B1MW_SET(x)                  (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1MW_SHIFT)) & FMC_PFB23CR_B1MW_MASK)
+#define FMC_PFB23CR_B1MW FMC_PFB23CR_B1MW_MASK
 #define FMC_PFB23CR_B1RWSC_MASK                  (0xF0000000U)
 #define FMC_PFB23CR_B1RWSC_SHIFT                 (28U)
-#define FMC_PFB23CR_B1RWSC(x)                    (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1RWSC_SHIFT)) & FMC_PFB23CR_B1RWSC_MASK)
+#define FMC_PFB23CR_B1RWSC_SET(x)                (((uint32_t)(((uint32_t)(x)) << FMC_PFB23CR_B1RWSC_SHIFT)) & FMC_PFB23CR_B1RWSC_MASK)
+#define FMC_PFB23CR_B1RWSC FMC_PFB23CR_B1RWSC_MASK
 
 /*! @name TAGVDW0S - Cache Tag Storage */
 #define FMC_TAGVDW0S_valid_MASK                  (0x1U)
 #define FMC_TAGVDW0S_valid_SHIFT                 (0U)
-#define FMC_TAGVDW0S_valid(x)                    (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_valid_SHIFT)) & FMC_TAGVDW0S_valid_MASK)
+#define FMC_TAGVDW0S_valid_SET(x)                (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_valid_SHIFT)) & FMC_TAGVDW0S_valid_MASK)
+#define FMC_TAGVDW0S_valid FMC_TAGVDW0S_valid_MASK
 #define FMC_TAGVDW0S_tag_MASK                    (0x3FFFC0U)
 #define FMC_TAGVDW0S_tag_SHIFT                   (6U)
-#define FMC_TAGVDW0S_tag(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_tag_SHIFT)) & FMC_TAGVDW0S_tag_MASK)
+#define FMC_TAGVDW0S_tag_SET(x)                  (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_tag_SHIFT)) & FMC_TAGVDW0S_tag_MASK)
+#define FMC_TAGVDW0S_tag FMC_TAGVDW0S_tag_MASK
 
 /* The count of FMC_TAGVDW0S */
 #define FMC_TAGVDW0S_COUNT                       (4U)
@@ -6572,10 +8013,12 @@ typedef struct {
 /*! @name TAGVDW1S - Cache Tag Storage */
 #define FMC_TAGVDW1S_valid_MASK                  (0x1U)
 #define FMC_TAGVDW1S_valid_SHIFT                 (0U)
-#define FMC_TAGVDW1S_valid(x)                    (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_valid_SHIFT)) & FMC_TAGVDW1S_valid_MASK)
+#define FMC_TAGVDW1S_valid_SET(x)                (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_valid_SHIFT)) & FMC_TAGVDW1S_valid_MASK)
+#define FMC_TAGVDW1S_valid FMC_TAGVDW1S_valid_MASK
 #define FMC_TAGVDW1S_tag_MASK                    (0x3FFFC0U)
 #define FMC_TAGVDW1S_tag_SHIFT                   (6U)
-#define FMC_TAGVDW1S_tag(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_tag_SHIFT)) & FMC_TAGVDW1S_tag_MASK)
+#define FMC_TAGVDW1S_tag_SET(x)                  (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_tag_SHIFT)) & FMC_TAGVDW1S_tag_MASK)
+#define FMC_TAGVDW1S_tag FMC_TAGVDW1S_tag_MASK
 
 /* The count of FMC_TAGVDW1S */
 #define FMC_TAGVDW1S_COUNT                       (4U)
@@ -6583,10 +8026,12 @@ typedef struct {
 /*! @name TAGVDW2S - Cache Tag Storage */
 #define FMC_TAGVDW2S_valid_MASK                  (0x1U)
 #define FMC_TAGVDW2S_valid_SHIFT                 (0U)
-#define FMC_TAGVDW2S_valid(x)                    (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_valid_SHIFT)) & FMC_TAGVDW2S_valid_MASK)
+#define FMC_TAGVDW2S_valid_SET(x)                (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_valid_SHIFT)) & FMC_TAGVDW2S_valid_MASK)
+#define FMC_TAGVDW2S_valid FMC_TAGVDW2S_valid_MASK
 #define FMC_TAGVDW2S_tag_MASK                    (0x3FFFC0U)
 #define FMC_TAGVDW2S_tag_SHIFT                   (6U)
-#define FMC_TAGVDW2S_tag(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_tag_SHIFT)) & FMC_TAGVDW2S_tag_MASK)
+#define FMC_TAGVDW2S_tag_SET(x)                  (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_tag_SHIFT)) & FMC_TAGVDW2S_tag_MASK)
+#define FMC_TAGVDW2S_tag FMC_TAGVDW2S_tag_MASK
 
 /* The count of FMC_TAGVDW2S */
 #define FMC_TAGVDW2S_COUNT                       (4U)
@@ -6594,10 +8039,12 @@ typedef struct {
 /*! @name TAGVDW3S - Cache Tag Storage */
 #define FMC_TAGVDW3S_valid_MASK                  (0x1U)
 #define FMC_TAGVDW3S_valid_SHIFT                 (0U)
-#define FMC_TAGVDW3S_valid(x)                    (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_valid_SHIFT)) & FMC_TAGVDW3S_valid_MASK)
+#define FMC_TAGVDW3S_valid_SET(x)                (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_valid_SHIFT)) & FMC_TAGVDW3S_valid_MASK)
+#define FMC_TAGVDW3S_valid FMC_TAGVDW3S_valid_MASK
 #define FMC_TAGVDW3S_tag_MASK                    (0x3FFFC0U)
 #define FMC_TAGVDW3S_tag_SHIFT                   (6U)
-#define FMC_TAGVDW3S_tag(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_tag_SHIFT)) & FMC_TAGVDW3S_tag_MASK)
+#define FMC_TAGVDW3S_tag_SET(x)                  (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_tag_SHIFT)) & FMC_TAGVDW3S_tag_MASK)
+#define FMC_TAGVDW3S_tag FMC_TAGVDW3S_tag_MASK
 
 /* The count of FMC_TAGVDW3S */
 #define FMC_TAGVDW3S_COUNT                       (4U)
@@ -6605,7 +8052,8 @@ typedef struct {
 /*! @name DATA_UM - Cache Data Storage (uppermost word) */
 #define FMC_DATA_UM_data_MASK                    (0xFFFFFFFFU)
 #define FMC_DATA_UM_data_SHIFT                   (0U)
-#define FMC_DATA_UM_data(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_DATA_UM_data_SHIFT)) & FMC_DATA_UM_data_MASK)
+#define FMC_DATA_UM_data_SET(x)                  (((uint32_t)(((uint32_t)(x)) << FMC_DATA_UM_data_SHIFT)) & FMC_DATA_UM_data_MASK)
+#define FMC_DATA_UM_data FMC_DATA_UM_data_MASK
 
 /* The count of FMC_DATA_UM */
 #define FMC_DATA_UM_COUNT                        (4U)
@@ -6616,7 +8064,8 @@ typedef struct {
 /*! @name DATA_MU - Cache Data Storage (mid-upper word) */
 #define FMC_DATA_MU_data_MASK                    (0xFFFFFFFFU)
 #define FMC_DATA_MU_data_SHIFT                   (0U)
-#define FMC_DATA_MU_data(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_DATA_MU_data_SHIFT)) & FMC_DATA_MU_data_MASK)
+#define FMC_DATA_MU_data_SET(x)                  (((uint32_t)(((uint32_t)(x)) << FMC_DATA_MU_data_SHIFT)) & FMC_DATA_MU_data_MASK)
+#define FMC_DATA_MU_data FMC_DATA_MU_data_MASK
 
 /* The count of FMC_DATA_MU */
 #define FMC_DATA_MU_COUNT                        (4U)
@@ -6627,7 +8076,8 @@ typedef struct {
 /*! @name DATA_ML - Cache Data Storage (mid-lower word) */
 #define FMC_DATA_ML_data_MASK                    (0xFFFFFFFFU)
 #define FMC_DATA_ML_data_SHIFT                   (0U)
-#define FMC_DATA_ML_data(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_DATA_ML_data_SHIFT)) & FMC_DATA_ML_data_MASK)
+#define FMC_DATA_ML_data_SET(x)                  (((uint32_t)(((uint32_t)(x)) << FMC_DATA_ML_data_SHIFT)) & FMC_DATA_ML_data_MASK)
+#define FMC_DATA_ML_data FMC_DATA_ML_data_MASK
 
 /* The count of FMC_DATA_ML */
 #define FMC_DATA_ML_COUNT                        (4U)
@@ -6638,7 +8088,8 @@ typedef struct {
 /*! @name DATA_LM - Cache Data Storage (lowermost word) */
 #define FMC_DATA_LM_data_MASK                    (0xFFFFFFFFU)
 #define FMC_DATA_LM_data_SHIFT                   (0U)
-#define FMC_DATA_LM_data(x)                      (((uint32_t)(((uint32_t)(x)) << FMC_DATA_LM_data_SHIFT)) & FMC_DATA_LM_data_MASK)
+#define FMC_DATA_LM_data_SET(x)                  (((uint32_t)(((uint32_t)(x)) << FMC_DATA_LM_data_SHIFT)) & FMC_DATA_LM_data_MASK)
+#define FMC_DATA_LM_data FMC_DATA_LM_data_MASK
 
 /* The count of FMC_DATA_LM */
 #define FMC_DATA_LM_COUNT                        (4U)
@@ -6656,7 +8107,7 @@ typedef struct {
 /** Peripheral FMC base address */
 #define FMC_BASE                                 (0x4001F000u)
 /** Peripheral FMC base pointer */
-#define FMC                                      ((FMC_Type *)FMC_BASE)
+#define FMC                                      ((FMC_TypeDef *)FMC_BASE)
 /** Array initializer of FMC peripheral base addresses */
 #define FMC_BASE_ADDRS                           { FMC_BASE }
 /** Array initializer of FMC peripheral base pointers */
@@ -6720,7 +8171,7 @@ typedef struct {
   __I  uint8_t FACSS;                              /**< Flash Access Segment Size Register, offset: 0x28 */
        uint8_t RESERVED_1[2];
   __I  uint8_t FACSN;                              /**< Flash Access Segment Number Register, offset: 0x2B */
-} FTFE_Type;
+} FTFE_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- FTFE Register Masks
@@ -6734,249 +8185,298 @@ typedef struct {
 /*! @name FSTAT - Flash Status Register */
 #define FTFE_FSTAT_MGSTAT0_MASK                  (0x1U)
 #define FTFE_FSTAT_MGSTAT0_SHIFT                 (0U)
-#define FTFE_FSTAT_MGSTAT0(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_MGSTAT0_SHIFT)) & FTFE_FSTAT_MGSTAT0_MASK)
+#define FTFE_FSTAT_MGSTAT0_SET(x)                (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_MGSTAT0_SHIFT)) & FTFE_FSTAT_MGSTAT0_MASK)
+#define FTFE_FSTAT_MGSTAT0 FTFE_FSTAT_MGSTAT0_MASK
 #define FTFE_FSTAT_FPVIOL_MASK                   (0x10U)
 #define FTFE_FSTAT_FPVIOL_SHIFT                  (4U)
-#define FTFE_FSTAT_FPVIOL(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_FPVIOL_SHIFT)) & FTFE_FSTAT_FPVIOL_MASK)
+#define FTFE_FSTAT_FPVIOL(x)                 (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_FPVIOL_SHIFT)) & FTFE_FSTAT_FPVIOL_MASK)
 #define FTFL_FSTAT_FPVIOL                        FTFE_FSTAT_FPVIOL(1)
 #define FTFE_FSTAT_ACCERR_MASK                   (0x20U)
 #define FTFE_FSTAT_ACCERR_SHIFT                  (5U)
-#define FTFE_FSTAT_ACCERR(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_ACCERR_SHIFT)) & FTFE_FSTAT_ACCERR_MASK)
+#define FTFE_FSTAT_ACCERR(x)                 (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_ACCERR_SHIFT)) & FTFE_FSTAT_ACCERR_MASK)
 #define FTFL_FSTAT_ACCERR                        FTFE_FSTAT_ACCERR(1)
 #define FTFE_FSTAT_RDCOLERR_MASK                 (0x40U)
 #define FTFE_FSTAT_RDCOLERR_SHIFT                (6U)
-#define FTFE_FSTAT_RDCOLERR(x)                   (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_RDCOLERR_SHIFT)) & FTFE_FSTAT_RDCOLERR_MASK)
+#define FTFE_FSTAT_RDCOLERR(x)               (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_RDCOLERR_SHIFT)) & FTFE_FSTAT_RDCOLERR_MASK)
 #define FTFL_FSTAT_RDCOLERR                      FTFE_FSTAT_RDCOLERR(1)
 #define FTFE_FSTAT_CCIF_MASK                     (0x80U)
 #define FTFE_FSTAT_CCIF_SHIFT                    (7U)
-#define FTFE_FSTAT_CCIF(x)                       (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_CCIF_SHIFT)) & FTFE_FSTAT_CCIF_MASK)
+#define FTFE_FSTAT_CCIF_SET(x)                   (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_CCIF_SHIFT)) & FTFE_FSTAT_CCIF_MASK)
+#define FTFE_FSTAT_CCIF FTFE_FSTAT_CCIF_MASK
 
 /*! @name FCNFG - Flash Configuration Register */
 #define FTFE_FCNFG_EEERDY_MASK                   (0x1U)
 #define FTFE_FCNFG_EEERDY_SHIFT                  (0U)
-#define FTFE_FCNFG_EEERDY(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_EEERDY_SHIFT)) & FTFE_FCNFG_EEERDY_MASK)
+#define FTFE_FCNFG_EEERDY(x)                 (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_EEERDY_SHIFT)) & FTFE_FCNFG_EEERDY_MASK)
 #define FTFL_FCNFG_EEERDY                        FTFE_FCNFG_EEERDY(1)
 #define FTFE_FCNFG_RAMRDY_MASK                   (0x2U)
 #define FTFE_FCNFG_RAMRDY_SHIFT                  (1U)
-#define FTFE_FCNFG_RAMRDY(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RAMRDY_SHIFT)) & FTFE_FCNFG_RAMRDY_MASK)
+#define FTFE_FCNFG_RAMRDY(x)                 (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RAMRDY_SHIFT)) & FTFE_FCNFG_RAMRDY_MASK)
 #define FTFL_FCNFG_RAMRDY                        FTFE_FCNFG_RAMRDY(1)
 #define FTFE_FCNFG_PFLSH_MASK                    (0x4U)
 #define FTFE_FCNFG_PFLSH_SHIFT                   (2U)
-#define FTFE_FCNFG_PFLSH(x)                      (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_PFLSH_SHIFT)) & FTFE_FCNFG_PFLSH_MASK)
+#define FTFE_FCNFG_PFLSH_SET(x)                  (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_PFLSH_SHIFT)) & FTFE_FCNFG_PFLSH_MASK)
+#define FTFE_FCNFG_PFLSH FTFE_FCNFG_PFLSH_MASK
 #define FTFE_FCNFG_SWAP_MASK                     (0x8U)
 #define FTFE_FCNFG_SWAP_SHIFT                    (3U)
-#define FTFE_FCNFG_SWAP(x)                       (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_SWAP_SHIFT)) & FTFE_FCNFG_SWAP_MASK)
+#define FTFE_FCNFG_SWAP_SET(x)                   (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_SWAP_SHIFT)) & FTFE_FCNFG_SWAP_MASK)
+#define FTFE_FCNFG_SWAP FTFE_FCNFG_SWAP_MASK
 #define FTFE_FCNFG_ERSSUSP_MASK                  (0x10U)
 #define FTFE_FCNFG_ERSSUSP_SHIFT                 (4U)
-#define FTFE_FCNFG_ERSSUSP(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSSUSP_SHIFT)) & FTFE_FCNFG_ERSSUSP_MASK)
+#define FTFE_FCNFG_ERSSUSP_SET(x)                (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSSUSP_SHIFT)) & FTFE_FCNFG_ERSSUSP_MASK)
+#define FTFE_FCNFG_ERSSUSP FTFE_FCNFG_ERSSUSP_MASK
 #define FTFE_FCNFG_ERSAREQ_MASK                  (0x20U)
 #define FTFE_FCNFG_ERSAREQ_SHIFT                 (5U)
-#define FTFE_FCNFG_ERSAREQ(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSAREQ_SHIFT)) & FTFE_FCNFG_ERSAREQ_MASK)
+#define FTFE_FCNFG_ERSAREQ_SET(x)                (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSAREQ_SHIFT)) & FTFE_FCNFG_ERSAREQ_MASK)
+#define FTFE_FCNFG_ERSAREQ FTFE_FCNFG_ERSAREQ_MASK
 #define FTFE_FCNFG_RDCOLLIE_MASK                 (0x40U)
 #define FTFE_FCNFG_RDCOLLIE_SHIFT                (6U)
-#define FTFE_FCNFG_RDCOLLIE(x)                   (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RDCOLLIE_SHIFT)) & FTFE_FCNFG_RDCOLLIE_MASK)
+#define FTFE_FCNFG_RDCOLLIE_SET(x)               (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RDCOLLIE_SHIFT)) & FTFE_FCNFG_RDCOLLIE_MASK)
+#define FTFE_FCNFG_RDCOLLIE FTFE_FCNFG_RDCOLLIE_MASK
 #define FTFE_FCNFG_CCIE_MASK                     (0x80U)
 #define FTFE_FCNFG_CCIE_SHIFT                    (7U)
-#define FTFE_FCNFG_CCIE(x)                       (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CCIE_SHIFT)) & FTFE_FCNFG_CCIE_MASK)
+#define FTFE_FCNFG_CCIE_SET(x)                   (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CCIE_SHIFT)) & FTFE_FCNFG_CCIE_MASK)
+#define FTFE_FCNFG_CCIE FTFE_FCNFG_CCIE_MASK
 
 /*! @name FSEC - Flash Security Register */
 #define FTFE_FSEC_SEC_MASK                       (0x3U)
 #define FTFE_FSEC_SEC_SHIFT                      (0U)
-#define FTFE_FSEC_SEC(x)                         (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_SEC_SHIFT)) & FTFE_FSEC_SEC_MASK)
+#define FTFE_FSEC_SEC_SET(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_SEC_SHIFT)) & FTFE_FSEC_SEC_MASK)
+#define FTFE_FSEC_SEC FTFE_FSEC_SEC_MASK
 #define FTFE_FSEC_FSLACC_MASK                    (0xCU)
 #define FTFE_FSEC_FSLACC_SHIFT                   (2U)
-#define FTFE_FSEC_FSLACC(x)                      (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_FSLACC_SHIFT)) & FTFE_FSEC_FSLACC_MASK)
+#define FTFE_FSEC_FSLACC_SET(x)                  (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_FSLACC_SHIFT)) & FTFE_FSEC_FSLACC_MASK)
+#define FTFE_FSEC_FSLACC FTFE_FSEC_FSLACC_MASK
 #define FTFE_FSEC_MEEN_MASK                      (0x30U)
 #define FTFE_FSEC_MEEN_SHIFT                     (4U)
-#define FTFE_FSEC_MEEN(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_MEEN_SHIFT)) & FTFE_FSEC_MEEN_MASK)
+#define FTFE_FSEC_MEEN_SET(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_MEEN_SHIFT)) & FTFE_FSEC_MEEN_MASK)
+#define FTFE_FSEC_MEEN FTFE_FSEC_MEEN_MASK
 #define FTFE_FSEC_KEYEN_MASK                     (0xC0U)
 #define FTFE_FSEC_KEYEN_SHIFT                    (6U)
-#define FTFE_FSEC_KEYEN(x)                       (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_KEYEN_SHIFT)) & FTFE_FSEC_KEYEN_MASK)
+#define FTFE_FSEC_KEYEN_SET(x)                   (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_KEYEN_SHIFT)) & FTFE_FSEC_KEYEN_MASK)
+#define FTFE_FSEC_KEYEN FTFE_FSEC_KEYEN_MASK
 
 /*! @name FOPT - Flash Option Register */
 #define FTFE_FOPT_OPT_MASK                       (0xFFU)
 #define FTFE_FOPT_OPT_SHIFT                      (0U)
-#define FTFE_FOPT_OPT(x)                         (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT_OPT_SHIFT)) & FTFE_FOPT_OPT_MASK)
+#define FTFE_FOPT_OPT_SET(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT_OPT_SHIFT)) & FTFE_FOPT_OPT_MASK)
+#define FTFE_FOPT_OPT FTFE_FOPT_OPT_MASK
 
 /*! @name FCCOB3 - Flash Common Command Object Registers */
 #define FTFE_FCCOB3_CCOBn_MASK                   (0xFFU)
 #define FTFE_FCCOB3_CCOBn_SHIFT                  (0U)
-#define FTFE_FCCOB3_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB3_CCOBn_SHIFT)) & FTFE_FCCOB3_CCOBn_MASK)
+#define FTFE_FCCOB3_CCOBn_SET(x)                 (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB3_CCOBn_SHIFT)) & FTFE_FCCOB3_CCOBn_MASK)
+#define FTFE_FCCOB3_CCOBn FTFE_FCCOB3_CCOBn_MASK
 
 /*! @name FCCOB2 - Flash Common Command Object Registers */
 #define FTFE_FCCOB2_CCOBn_MASK                   (0xFFU)
 #define FTFE_FCCOB2_CCOBn_SHIFT                  (0U)
-#define FTFE_FCCOB2_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB2_CCOBn_SHIFT)) & FTFE_FCCOB2_CCOBn_MASK)
+#define FTFE_FCCOB2_CCOBn_SET(x)                 (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB2_CCOBn_SHIFT)) & FTFE_FCCOB2_CCOBn_MASK)
+#define FTFE_FCCOB2_CCOBn FTFE_FCCOB2_CCOBn_MASK
 
 /*! @name FCCOB1 - Flash Common Command Object Registers */
 #define FTFE_FCCOB1_CCOBn_MASK                   (0xFFU)
 #define FTFE_FCCOB1_CCOBn_SHIFT                  (0U)
-#define FTFE_FCCOB1_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB1_CCOBn_SHIFT)) & FTFE_FCCOB1_CCOBn_MASK)
+#define FTFE_FCCOB1_CCOBn_SET(x)                 (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB1_CCOBn_SHIFT)) & FTFE_FCCOB1_CCOBn_MASK)
+#define FTFE_FCCOB1_CCOBn FTFE_FCCOB1_CCOBn_MASK
 
 /*! @name FCCOB0 - Flash Common Command Object Registers */
 #define FTFE_FCCOB0_CCOBn_MASK                   (0xFFU)
 #define FTFE_FCCOB0_CCOBn_SHIFT                  (0U)
-#define FTFE_FCCOB0_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB0_CCOBn_SHIFT)) & FTFE_FCCOB0_CCOBn_MASK)
+#define FTFE_FCCOB0_CCOBn_SET(x)                 (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB0_CCOBn_SHIFT)) & FTFE_FCCOB0_CCOBn_MASK)
+#define FTFE_FCCOB0_CCOBn FTFE_FCCOB0_CCOBn_MASK
 
 /*! @name FCCOB7 - Flash Common Command Object Registers */
 #define FTFE_FCCOB7_CCOBn_MASK                   (0xFFU)
 #define FTFE_FCCOB7_CCOBn_SHIFT                  (0U)
-#define FTFE_FCCOB7_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB7_CCOBn_SHIFT)) & FTFE_FCCOB7_CCOBn_MASK)
+#define FTFE_FCCOB7_CCOBn_SET(x)                 (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB7_CCOBn_SHIFT)) & FTFE_FCCOB7_CCOBn_MASK)
+#define FTFE_FCCOB7_CCOBn FTFE_FCCOB7_CCOBn_MASK
 
 /*! @name FCCOB6 - Flash Common Command Object Registers */
 #define FTFE_FCCOB6_CCOBn_MASK                   (0xFFU)
 #define FTFE_FCCOB6_CCOBn_SHIFT                  (0U)
-#define FTFE_FCCOB6_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB6_CCOBn_SHIFT)) & FTFE_FCCOB6_CCOBn_MASK)
+#define FTFE_FCCOB6_CCOBn_SET(x)                 (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB6_CCOBn_SHIFT)) & FTFE_FCCOB6_CCOBn_MASK)
+#define FTFE_FCCOB6_CCOBn FTFE_FCCOB6_CCOBn_MASK
 
 /*! @name FCCOB5 - Flash Common Command Object Registers */
 #define FTFE_FCCOB5_CCOBn_MASK                   (0xFFU)
 #define FTFE_FCCOB5_CCOBn_SHIFT                  (0U)
-#define FTFE_FCCOB5_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB5_CCOBn_SHIFT)) & FTFE_FCCOB5_CCOBn_MASK)
+#define FTFE_FCCOB5_CCOBn_SET(x)                 (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB5_CCOBn_SHIFT)) & FTFE_FCCOB5_CCOBn_MASK)
+#define FTFE_FCCOB5_CCOBn FTFE_FCCOB5_CCOBn_MASK
 
 /*! @name FCCOB4 - Flash Common Command Object Registers */
 #define FTFE_FCCOB4_CCOBn_MASK                   (0xFFU)
 #define FTFE_FCCOB4_CCOBn_SHIFT                  (0U)
-#define FTFE_FCCOB4_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB4_CCOBn_SHIFT)) & FTFE_FCCOB4_CCOBn_MASK)
+#define FTFE_FCCOB4_CCOBn_SET(x)                 (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB4_CCOBn_SHIFT)) & FTFE_FCCOB4_CCOBn_MASK)
+#define FTFE_FCCOB4_CCOBn FTFE_FCCOB4_CCOBn_MASK
 
 /*! @name FCCOBB - Flash Common Command Object Registers */
 #define FTFE_FCCOBB_CCOBn_MASK                   (0xFFU)
 #define FTFE_FCCOBB_CCOBn_SHIFT                  (0U)
-#define FTFE_FCCOBB_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBB_CCOBn_SHIFT)) & FTFE_FCCOBB_CCOBn_MASK)
+#define FTFE_FCCOBB_CCOBn_SET(x)                 (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBB_CCOBn_SHIFT)) & FTFE_FCCOBB_CCOBn_MASK)
+#define FTFE_FCCOBB_CCOBn FTFE_FCCOBB_CCOBn_MASK
 
 /*! @name FCCOBA - Flash Common Command Object Registers */
 #define FTFE_FCCOBA_CCOBn_MASK                   (0xFFU)
 #define FTFE_FCCOBA_CCOBn_SHIFT                  (0U)
-#define FTFE_FCCOBA_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBA_CCOBn_SHIFT)) & FTFE_FCCOBA_CCOBn_MASK)
+#define FTFE_FCCOBA_CCOBn_SET(x)                 (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBA_CCOBn_SHIFT)) & FTFE_FCCOBA_CCOBn_MASK)
+#define FTFE_FCCOBA_CCOBn FTFE_FCCOBA_CCOBn_MASK
 
 /*! @name FCCOB9 - Flash Common Command Object Registers */
 #define FTFE_FCCOB9_CCOBn_MASK                   (0xFFU)
 #define FTFE_FCCOB9_CCOBn_SHIFT                  (0U)
-#define FTFE_FCCOB9_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB9_CCOBn_SHIFT)) & FTFE_FCCOB9_CCOBn_MASK)
+#define FTFE_FCCOB9_CCOBn_SET(x)                 (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB9_CCOBn_SHIFT)) & FTFE_FCCOB9_CCOBn_MASK)
+#define FTFE_FCCOB9_CCOBn FTFE_FCCOB9_CCOBn_MASK
 
 /*! @name FCCOB8 - Flash Common Command Object Registers */
 #define FTFE_FCCOB8_CCOBn_MASK                   (0xFFU)
 #define FTFE_FCCOB8_CCOBn_SHIFT                  (0U)
-#define FTFE_FCCOB8_CCOBn(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB8_CCOBn_SHIFT)) & FTFE_FCCOB8_CCOBn_MASK)
+#define FTFE_FCCOB8_CCOBn_SET(x)                 (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB8_CCOBn_SHIFT)) & FTFE_FCCOB8_CCOBn_MASK)
+#define FTFE_FCCOB8_CCOBn FTFE_FCCOB8_CCOBn_MASK
 
 /*! @name FPROT3 - Program Flash Protection Registers */
 #define FTFE_FPROT3_PROT_MASK                    (0xFFU)
 #define FTFE_FPROT3_PROT_SHIFT                   (0U)
-#define FTFE_FPROT3_PROT(x)                      (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT3_PROT_SHIFT)) & FTFE_FPROT3_PROT_MASK)
+#define FTFE_FPROT3_PROT_SET(x)                  (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT3_PROT_SHIFT)) & FTFE_FPROT3_PROT_MASK)
+#define FTFE_FPROT3_PROT FTFE_FPROT3_PROT_MASK
 
 /*! @name FPROT2 - Program Flash Protection Registers */
 #define FTFE_FPROT2_PROT_MASK                    (0xFFU)
 #define FTFE_FPROT2_PROT_SHIFT                   (0U)
-#define FTFE_FPROT2_PROT(x)                      (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT2_PROT_SHIFT)) & FTFE_FPROT2_PROT_MASK)
+#define FTFE_FPROT2_PROT_SET(x)                  (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT2_PROT_SHIFT)) & FTFE_FPROT2_PROT_MASK)
+#define FTFE_FPROT2_PROT FTFE_FPROT2_PROT_MASK
 
 /*! @name FPROT1 - Program Flash Protection Registers */
 #define FTFE_FPROT1_PROT_MASK                    (0xFFU)
 #define FTFE_FPROT1_PROT_SHIFT                   (0U)
-#define FTFE_FPROT1_PROT(x)                      (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT1_PROT_SHIFT)) & FTFE_FPROT1_PROT_MASK)
+#define FTFE_FPROT1_PROT_SET(x)                  (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT1_PROT_SHIFT)) & FTFE_FPROT1_PROT_MASK)
+#define FTFE_FPROT1_PROT FTFE_FPROT1_PROT_MASK
 
 /*! @name FPROT0 - Program Flash Protection Registers */
 #define FTFE_FPROT0_PROT_MASK                    (0xFFU)
 #define FTFE_FPROT0_PROT_SHIFT                   (0U)
-#define FTFE_FPROT0_PROT(x)                      (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT0_PROT_SHIFT)) & FTFE_FPROT0_PROT_MASK)
+#define FTFE_FPROT0_PROT_SET(x)                  (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT0_PROT_SHIFT)) & FTFE_FPROT0_PROT_MASK)
+#define FTFE_FPROT0_PROT FTFE_FPROT0_PROT_MASK
 
 /*! @name FEPROT - EEPROM Protection Register */
 #define FTFE_FEPROT_EPROT_MASK                   (0xFFU)
 #define FTFE_FEPROT_EPROT_SHIFT                  (0U)
-#define FTFE_FEPROT_EPROT(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FEPROT_EPROT_SHIFT)) & FTFE_FEPROT_EPROT_MASK)
+#define FTFE_FEPROT_EPROT_SET(x)                 (((uint8_t)(((uint8_t)(x)) << FTFE_FEPROT_EPROT_SHIFT)) & FTFE_FEPROT_EPROT_MASK)
+#define FTFE_FEPROT_EPROT FTFE_FEPROT_EPROT_MASK
 
 /*! @name FDPROT - Data Flash Protection Register */
 #define FTFE_FDPROT_DPROT_MASK                   (0xFFU)
 #define FTFE_FDPROT_DPROT_SHIFT                  (0U)
-#define FTFE_FDPROT_DPROT(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FDPROT_DPROT_SHIFT)) & FTFE_FDPROT_DPROT_MASK)
+#define FTFE_FDPROT_DPROT_SET(x)                 (((uint8_t)(((uint8_t)(x)) << FTFE_FDPROT_DPROT_SHIFT)) & FTFE_FDPROT_DPROT_MASK)
+#define FTFE_FDPROT_DPROT FTFE_FDPROT_DPROT_MASK
 
 /*! @name XACCH3 - Execute-only Access Registers */
 #define FTFE_XACCH3_XA_MASK                      (0xFFU)
 #define FTFE_XACCH3_XA_SHIFT                     (0U)
-#define FTFE_XACCH3_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH3_XA_SHIFT)) & FTFE_XACCH3_XA_MASK)
+#define FTFE_XACCH3_XA_SET(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH3_XA_SHIFT)) & FTFE_XACCH3_XA_MASK)
+#define FTFE_XACCH3_XA FTFE_XACCH3_XA_MASK
 
 /*! @name XACCH2 - Execute-only Access Registers */
 #define FTFE_XACCH2_XA_MASK                      (0xFFU)
 #define FTFE_XACCH2_XA_SHIFT                     (0U)
-#define FTFE_XACCH2_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH2_XA_SHIFT)) & FTFE_XACCH2_XA_MASK)
+#define FTFE_XACCH2_XA_SET(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH2_XA_SHIFT)) & FTFE_XACCH2_XA_MASK)
+#define FTFE_XACCH2_XA FTFE_XACCH2_XA_MASK
 
 /*! @name XACCH1 - Execute-only Access Registers */
 #define FTFE_XACCH1_XA_MASK                      (0xFFU)
 #define FTFE_XACCH1_XA_SHIFT                     (0U)
-#define FTFE_XACCH1_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH1_XA_SHIFT)) & FTFE_XACCH1_XA_MASK)
+#define FTFE_XACCH1_XA_SET(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH1_XA_SHIFT)) & FTFE_XACCH1_XA_MASK)
+#define FTFE_XACCH1_XA FTFE_XACCH1_XA_MASK
 
 /*! @name XACCH0 - Execute-only Access Registers */
 #define FTFE_XACCH0_XA_MASK                      (0xFFU)
 #define FTFE_XACCH0_XA_SHIFT                     (0U)
-#define FTFE_XACCH0_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH0_XA_SHIFT)) & FTFE_XACCH0_XA_MASK)
+#define FTFE_XACCH0_XA_SET(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_XACCH0_XA_SHIFT)) & FTFE_XACCH0_XA_MASK)
+#define FTFE_XACCH0_XA FTFE_XACCH0_XA_MASK
 
 /*! @name XACCL3 - Execute-only Access Registers */
 #define FTFE_XACCL3_XA_MASK                      (0xFFU)
 #define FTFE_XACCL3_XA_SHIFT                     (0U)
-#define FTFE_XACCL3_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL3_XA_SHIFT)) & FTFE_XACCL3_XA_MASK)
+#define FTFE_XACCL3_XA_SET(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL3_XA_SHIFT)) & FTFE_XACCL3_XA_MASK)
+#define FTFE_XACCL3_XA FTFE_XACCL3_XA_MASK
 
 /*! @name XACCL2 - Execute-only Access Registers */
 #define FTFE_XACCL2_XA_MASK                      (0xFFU)
 #define FTFE_XACCL2_XA_SHIFT                     (0U)
-#define FTFE_XACCL2_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL2_XA_SHIFT)) & FTFE_XACCL2_XA_MASK)
+#define FTFE_XACCL2_XA_SET(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL2_XA_SHIFT)) & FTFE_XACCL2_XA_MASK)
+#define FTFE_XACCL2_XA FTFE_XACCL2_XA_MASK
 
 /*! @name XACCL1 - Execute-only Access Registers */
 #define FTFE_XACCL1_XA_MASK                      (0xFFU)
 #define FTFE_XACCL1_XA_SHIFT                     (0U)
-#define FTFE_XACCL1_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL1_XA_SHIFT)) & FTFE_XACCL1_XA_MASK)
+#define FTFE_XACCL1_XA_SET(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL1_XA_SHIFT)) & FTFE_XACCL1_XA_MASK)
+#define FTFE_XACCL1_XA FTFE_XACCL1_XA_MASK
 
 /*! @name XACCL0 - Execute-only Access Registers */
 #define FTFE_XACCL0_XA_MASK                      (0xFFU)
 #define FTFE_XACCL0_XA_SHIFT                     (0U)
-#define FTFE_XACCL0_XA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL0_XA_SHIFT)) & FTFE_XACCL0_XA_MASK)
+#define FTFE_XACCL0_XA_SET(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_XACCL0_XA_SHIFT)) & FTFE_XACCL0_XA_MASK)
+#define FTFE_XACCL0_XA FTFE_XACCL0_XA_MASK
 
 /*! @name SACCH3 - Supervisor-only Access Registers */
 #define FTFE_SACCH3_SA_MASK                      (0xFFU)
 #define FTFE_SACCH3_SA_SHIFT                     (0U)
-#define FTFE_SACCH3_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH3_SA_SHIFT)) & FTFE_SACCH3_SA_MASK)
+#define FTFE_SACCH3_SA_SET(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH3_SA_SHIFT)) & FTFE_SACCH3_SA_MASK)
+#define FTFE_SACCH3_SA FTFE_SACCH3_SA_MASK
 
 /*! @name SACCH2 - Supervisor-only Access Registers */
 #define FTFE_SACCH2_SA_MASK                      (0xFFU)
 #define FTFE_SACCH2_SA_SHIFT                     (0U)
-#define FTFE_SACCH2_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH2_SA_SHIFT)) & FTFE_SACCH2_SA_MASK)
+#define FTFE_SACCH2_SA_SET(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH2_SA_SHIFT)) & FTFE_SACCH2_SA_MASK)
+#define FTFE_SACCH2_SA FTFE_SACCH2_SA_MASK
 
 /*! @name SACCH1 - Supervisor-only Access Registers */
 #define FTFE_SACCH1_SA_MASK                      (0xFFU)
 #define FTFE_SACCH1_SA_SHIFT                     (0U)
-#define FTFE_SACCH1_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH1_SA_SHIFT)) & FTFE_SACCH1_SA_MASK)
+#define FTFE_SACCH1_SA_SET(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH1_SA_SHIFT)) & FTFE_SACCH1_SA_MASK)
+#define FTFE_SACCH1_SA FTFE_SACCH1_SA_MASK
 
 /*! @name SACCH0 - Supervisor-only Access Registers */
 #define FTFE_SACCH0_SA_MASK                      (0xFFU)
 #define FTFE_SACCH0_SA_SHIFT                     (0U)
-#define FTFE_SACCH0_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH0_SA_SHIFT)) & FTFE_SACCH0_SA_MASK)
+#define FTFE_SACCH0_SA_SET(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_SACCH0_SA_SHIFT)) & FTFE_SACCH0_SA_MASK)
+#define FTFE_SACCH0_SA FTFE_SACCH0_SA_MASK
 
 /*! @name SACCL3 - Supervisor-only Access Registers */
 #define FTFE_SACCL3_SA_MASK                      (0xFFU)
 #define FTFE_SACCL3_SA_SHIFT                     (0U)
-#define FTFE_SACCL3_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL3_SA_SHIFT)) & FTFE_SACCL3_SA_MASK)
+#define FTFE_SACCL3_SA_SET(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL3_SA_SHIFT)) & FTFE_SACCL3_SA_MASK)
+#define FTFE_SACCL3_SA FTFE_SACCL3_SA_MASK
 
 /*! @name SACCL2 - Supervisor-only Access Registers */
 #define FTFE_SACCL2_SA_MASK                      (0xFFU)
 #define FTFE_SACCL2_SA_SHIFT                     (0U)
-#define FTFE_SACCL2_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL2_SA_SHIFT)) & FTFE_SACCL2_SA_MASK)
+#define FTFE_SACCL2_SA_SET(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL2_SA_SHIFT)) & FTFE_SACCL2_SA_MASK)
+#define FTFE_SACCL2_SA FTFE_SACCL2_SA_MASK
 
 /*! @name SACCL1 - Supervisor-only Access Registers */
 #define FTFE_SACCL1_SA_MASK                      (0xFFU)
 #define FTFE_SACCL1_SA_SHIFT                     (0U)
-#define FTFE_SACCL1_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL1_SA_SHIFT)) & FTFE_SACCL1_SA_MASK)
+#define FTFE_SACCL1_SA_SET(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL1_SA_SHIFT)) & FTFE_SACCL1_SA_MASK)
+#define FTFE_SACCL1_SA FTFE_SACCL1_SA_MASK
 
 /*! @name SACCL0 - Supervisor-only Access Registers */
 #define FTFE_SACCL0_SA_MASK                      (0xFFU)
 #define FTFE_SACCL0_SA_SHIFT                     (0U)
-#define FTFE_SACCL0_SA(x)                        (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL0_SA_SHIFT)) & FTFE_SACCL0_SA_MASK)
+#define FTFE_SACCL0_SA_SET(x)                    (((uint8_t)(((uint8_t)(x)) << FTFE_SACCL0_SA_SHIFT)) & FTFE_SACCL0_SA_MASK)
+#define FTFE_SACCL0_SA FTFE_SACCL0_SA_MASK
 
 /*! @name FACSS - Flash Access Segment Size Register */
 #define FTFE_FACSS_SGSIZE_MASK                   (0xFFU)
 #define FTFE_FACSS_SGSIZE_SHIFT                  (0U)
-#define FTFE_FACSS_SGSIZE(x)                     (((uint8_t)(((uint8_t)(x)) << FTFE_FACSS_SGSIZE_SHIFT)) & FTFE_FACSS_SGSIZE_MASK)
+#define FTFE_FACSS_SGSIZE_SET(x)                 (((uint8_t)(((uint8_t)(x)) << FTFE_FACSS_SGSIZE_SHIFT)) & FTFE_FACSS_SGSIZE_MASK)
+#define FTFE_FACSS_SGSIZE FTFE_FACSS_SGSIZE_MASK
 
 /*! @name FACSN - Flash Access Segment Number Register */
 #define FTFE_FACSN_NUMSG_MASK                    (0xFFU)
 #define FTFE_FACSN_NUMSG_SHIFT                   (0U)
-#define FTFE_FACSN_NUMSG(x)                      (((uint8_t)(((uint8_t)(x)) << FTFE_FACSN_NUMSG_SHIFT)) & FTFE_FACSN_NUMSG_MASK)
+#define FTFE_FACSN_NUMSG_SET(x)                  (((uint8_t)(((uint8_t)(x)) << FTFE_FACSN_NUMSG_SHIFT)) & FTFE_FACSN_NUMSG_MASK)
+#define FTFE_FACSN_NUMSG FTFE_FACSN_NUMSG_MASK
 
 
 /*!
@@ -6988,8 +8488,8 @@ typedef struct {
 /** Peripheral FTFE base address */
 #define FTFE_BASE                                (0x40020000u)
 /** Peripheral FTFE base pointer */
-#define FTFE                                     ((FTFE_Type *)FTFE_BASE)
-#define FTFL                                     ((FTFE_Type *)FTFE_BASE)
+#define FTFE                                     ((FTFE_TypeDef *)FTFE_BASE)
+#define FTFL                                     ((FTFE_TypeDef *)FTFE_BASE)
 /** Array initializer of FTFE peripheral base addresses */
 #define FTFE_BASE_ADDRS                          { FTFE_BASE }
 /** Array initializer of FTFE peripheral base pointers */
@@ -7020,7 +8520,7 @@ typedef struct {
   struct {                                         /* offset: 0xC, array step: 0x8 */
     __IO uint32_t CnSC;                              /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
     __IO uint32_t CnV;                               /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
-  } CONTROLS[8];
+  } CHANNEL[8];
   __IO uint32_t CNTIN;                             /**< Counter Initial Value, offset: 0x4C */
   __IO uint32_t STATUS;                            /**< Capture And Compare Status, offset: 0x50 */
   __IO uint32_t MODE;                              /**< Features Mode Selection, offset: 0x54 */
@@ -7041,7 +8541,7 @@ typedef struct {
   __IO uint32_t INVCTRL;                           /**< FTM Inverting Control, offset: 0x90 */
   __IO uint32_t SWOCTRL;                           /**< FTM Software Output Control, offset: 0x94 */
   __IO uint32_t PWMLOAD;                           /**< FTM PWM Load, offset: 0x98 */
-} FTM_Type;
+} FTM_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- FTM Register Masks
@@ -7061,46 +8561,58 @@ typedef struct {
 #define FTM_SC_CLKS(x)                           (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)
 #define FTM_SC_CPWMS_MASK                        (0x20U)
 #define FTM_SC_CPWMS_SHIFT                       (5U)
-#define FTM_SC_CPWMS(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)
+#define FTM_SC_CPWMS_SET(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)
+#define FTM_SC_CPWMS FTM_SC_CPWMS_MASK
 #define FTM_SC_TOIE_MASK                         (0x40U)
 #define FTM_SC_TOIE_SHIFT                        (6U)
-#define FTM_SC_TOIE(x)                           (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)
+#define FTM_SC_TOIE_SET(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)
+#define FTM_SC_TOIE FTM_SC_TOIE_MASK
 #define FTM_SC_TOF_MASK                          (0x80U)
 #define FTM_SC_TOF_SHIFT                         (7U)
-#define FTM_SC_TOF(x)                            (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)
+#define FTM_SC_TOF_SET(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)
+#define FTM_SC_TOF FTM_SC_TOF_MASK
 
 /*! @name CNT - Counter */
 #define FTM_CNT_COUNT_MASK                       (0xFFFFU)
 #define FTM_CNT_COUNT_SHIFT                      (0U)
-#define FTM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
+#define FTM_CNT_COUNT_SET(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
+#define FTM_CNT_COUNT FTM_CNT_COUNT_MASK
 
 /*! @name MOD - Modulo */
 #define FTM_MOD_MOD_MASK                         (0xFFFFU)
 #define FTM_MOD_MOD_SHIFT                        (0U)
-#define FTM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
+#define FTM_MOD_MOD_SET(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
+#define FTM_MOD_MOD FTM_MOD_MOD_MASK
 
 /*! @name CnSC - Channel (n) Status And Control */
 #define FTM_CnSC_DMA_MASK                        (0x1U)
 #define FTM_CnSC_DMA_SHIFT                       (0U)
-#define FTM_CnSC_DMA(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)
+#define FTM_CnSC_DMA_SET(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)
+#define FTM_CnSC_DMA FTM_CnSC_DMA_MASK
 #define FTM_CnSC_ELSA_MASK                       (0x4U)
 #define FTM_CnSC_ELSA_SHIFT                      (2U)
-#define FTM_CnSC_ELSA(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK)
+#define FTM_CnSC_ELSA_SET(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK)
+#define FTM_CnSC_ELSA FTM_CnSC_ELSA_MASK
 #define FTM_CnSC_ELSB_MASK                       (0x8U)
 #define FTM_CnSC_ELSB_SHIFT                      (3U)
-#define FTM_CnSC_ELSB(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK)
+#define FTM_CnSC_ELSB_SET(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK)
+#define FTM_CnSC_ELSB FTM_CnSC_ELSB_MASK
 #define FTM_CnSC_MSA_MASK                        (0x10U)
 #define FTM_CnSC_MSA_SHIFT                       (4U)
-#define FTM_CnSC_MSA(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK)
+#define FTM_CnSC_MSA_SET(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK)
+#define FTM_CnSC_MSA FTM_CnSC_MSA_MASK
 #define FTM_CnSC_MSB_MASK                        (0x20U)
 #define FTM_CnSC_MSB_SHIFT                       (5U)
-#define FTM_CnSC_MSB(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK)
+#define FTM_CnSC_MSB_SET(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK)
+#define FTM_CnSC_MSB FTM_CnSC_MSB_MASK
 #define FTM_CnSC_CHIE_MASK                       (0x40U)
 #define FTM_CnSC_CHIE_SHIFT                      (6U)
-#define FTM_CnSC_CHIE(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)
+#define FTM_CnSC_CHIE_SET(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)
+#define FTM_CnSC_CHIE FTM_CnSC_CHIE_MASK
 #define FTM_CnSC_CHF_MASK                        (0x80U)
 #define FTM_CnSC_CHF_SHIFT                       (7U)
-#define FTM_CnSC_CHF(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)
+#define FTM_CnSC_CHF_SET(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)
+#define FTM_CnSC_CHF FTM_CnSC_CHF_MASK
 
 /* The count of FTM_CnSC */
 #define FTM_CnSC_COUNT                           (8U)
@@ -7108,7 +8620,8 @@ typedef struct {
 /*! @name CnV - Channel (n) Value */
 #define FTM_CnV_VAL_MASK                         (0xFFFFU)
 #define FTM_CnV_VAL_SHIFT                        (0U)
-#define FTM_CnV_VAL(x)                           (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
+#define FTM_CnV_VAL_SET(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
+#define FTM_CnV_VAL FTM_CnV_VAL_MASK
 
 /* The count of FTM_CnV */
 #define FTM_CnV_COUNT                            (8U)
@@ -7116,540 +8629,706 @@ typedef struct {
 /*! @name CNTIN - Counter Initial Value */
 #define FTM_CNTIN_INIT_MASK                      (0xFFFFU)
 #define FTM_CNTIN_INIT_SHIFT                     (0U)
-#define FTM_CNTIN_INIT(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
+#define FTM_CNTIN_INIT_SET(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
+#define FTM_CNTIN_INIT FTM_CNTIN_INIT_MASK
 
 /*! @name STATUS - Capture And Compare Status */
 #define FTM_STATUS_CH0F_MASK                     (0x1U)
 #define FTM_STATUS_CH0F_SHIFT                    (0U)
-#define FTM_STATUS_CH0F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)
+#define FTM_STATUS_CH0F_SET(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)
+#define FTM_STATUS_CH0F FTM_STATUS_CH0F_MASK
 #define FTM_STATUS_CH1F_MASK                     (0x2U)
 #define FTM_STATUS_CH1F_SHIFT                    (1U)
-#define FTM_STATUS_CH1F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)
+#define FTM_STATUS_CH1F_SET(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)
+#define FTM_STATUS_CH1F FTM_STATUS_CH1F_MASK
 #define FTM_STATUS_CH2F_MASK                     (0x4U)
 #define FTM_STATUS_CH2F_SHIFT                    (2U)
-#define FTM_STATUS_CH2F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)
+#define FTM_STATUS_CH2F_SET(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)
+#define FTM_STATUS_CH2F FTM_STATUS_CH2F_MASK
 #define FTM_STATUS_CH3F_MASK                     (0x8U)
 #define FTM_STATUS_CH3F_SHIFT                    (3U)
-#define FTM_STATUS_CH3F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)
+#define FTM_STATUS_CH3F_SET(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)
+#define FTM_STATUS_CH3F FTM_STATUS_CH3F_MASK
 #define FTM_STATUS_CH4F_MASK                     (0x10U)
 #define FTM_STATUS_CH4F_SHIFT                    (4U)
-#define FTM_STATUS_CH4F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)
+#define FTM_STATUS_CH4F_SET(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)
+#define FTM_STATUS_CH4F FTM_STATUS_CH4F_MASK
 #define FTM_STATUS_CH5F_MASK                     (0x20U)
 #define FTM_STATUS_CH5F_SHIFT                    (5U)
-#define FTM_STATUS_CH5F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)
+#define FTM_STATUS_CH5F_SET(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)
+#define FTM_STATUS_CH5F FTM_STATUS_CH5F_MASK
 #define FTM_STATUS_CH6F_MASK                     (0x40U)
 #define FTM_STATUS_CH6F_SHIFT                    (6U)
-#define FTM_STATUS_CH6F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)
+#define FTM_STATUS_CH6F_SET(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)
+#define FTM_STATUS_CH6F FTM_STATUS_CH6F_MASK
 #define FTM_STATUS_CH7F_MASK                     (0x80U)
 #define FTM_STATUS_CH7F_SHIFT                    (7U)
-#define FTM_STATUS_CH7F(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)
+#define FTM_STATUS_CH7F_SET(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)
+#define FTM_STATUS_CH7F FTM_STATUS_CH7F_MASK
 
 /*! @name MODE - Features Mode Selection */
 #define FTM_MODE_FTMEN_MASK                      (0x1U)
 #define FTM_MODE_FTMEN_SHIFT                     (0U)
-#define FTM_MODE_FTMEN(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)
+#define FTM_MODE_FTMEN_SET(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)
+#define FTM_MODE_FTMEN FTM_MODE_FTMEN_MASK
 #define FTM_MODE_INIT_MASK                       (0x2U)
 #define FTM_MODE_INIT_SHIFT                      (1U)
-#define FTM_MODE_INIT(x)                         (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK)
+#define FTM_MODE_INIT_SET(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK)
+#define FTM_MODE_INIT FTM_MODE_INIT_MASK
 #define FTM_MODE_WPDIS_MASK                      (0x4U)
 #define FTM_MODE_WPDIS_SHIFT                     (2U)
-#define FTM_MODE_WPDIS(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)
+#define FTM_MODE_WPDIS_SET(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)
+#define FTM_MODE_WPDIS FTM_MODE_WPDIS_MASK
 #define FTM_MODE_PWMSYNC_MASK                    (0x8U)
 #define FTM_MODE_PWMSYNC_SHIFT                   (3U)
-#define FTM_MODE_PWMSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)
+#define FTM_MODE_PWMSYNC_SET(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)
+#define FTM_MODE_PWMSYNC FTM_MODE_PWMSYNC_MASK
 #define FTM_MODE_CAPTEST_MASK                    (0x10U)
 #define FTM_MODE_CAPTEST_SHIFT                   (4U)
-#define FTM_MODE_CAPTEST(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)
+#define FTM_MODE_CAPTEST_SET(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)
+#define FTM_MODE_CAPTEST FTM_MODE_CAPTEST_MASK
 #define FTM_MODE_FAULTM_MASK                     (0x60U)
 #define FTM_MODE_FAULTM_SHIFT                    (5U)
-#define FTM_MODE_FAULTM(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
+#define FTM_MODE_FAULTM_SET(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
+#define FTM_MODE_FAULTM FTM_MODE_FAULTM_MASK
 #define FTM_MODE_FAULTIE_MASK                    (0x80U)
 #define FTM_MODE_FAULTIE_SHIFT                   (7U)
-#define FTM_MODE_FAULTIE(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)
+#define FTM_MODE_FAULTIE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)
+#define FTM_MODE_FAULTIE FTM_MODE_FAULTIE_MASK
 
 /*! @name SYNC - Synchronization */
 #define FTM_SYNC_CNTMIN_MASK                     (0x1U)
 #define FTM_SYNC_CNTMIN_SHIFT                    (0U)
-#define FTM_SYNC_CNTMIN(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)
+#define FTM_SYNC_CNTMIN_SET(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)
+#define FTM_SYNC_CNTMIN FTM_SYNC_CNTMIN_MASK
 #define FTM_SYNC_CNTMAX_MASK                     (0x2U)
 #define FTM_SYNC_CNTMAX_SHIFT                    (1U)
-#define FTM_SYNC_CNTMAX(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)
+#define FTM_SYNC_CNTMAX_SET(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)
+#define FTM_SYNC_CNTMAX FTM_SYNC_CNTMAX_MASK
 #define FTM_SYNC_REINIT_MASK                     (0x4U)
 #define FTM_SYNC_REINIT_SHIFT                    (2U)
-#define FTM_SYNC_REINIT(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)
+#define FTM_SYNC_REINIT_SET(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)
+#define FTM_SYNC_REINIT FTM_SYNC_REINIT_MASK
 #define FTM_SYNC_SYNCHOM_MASK                    (0x8U)
 #define FTM_SYNC_SYNCHOM_SHIFT                   (3U)
-#define FTM_SYNC_SYNCHOM(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)
+#define FTM_SYNC_SYNCHOM_SET(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)
+#define FTM_SYNC_SYNCHOM FTM_SYNC_SYNCHOM_MASK
 #define FTM_SYNC_TRIG0_MASK                      (0x10U)
 #define FTM_SYNC_TRIG0_SHIFT                     (4U)
-#define FTM_SYNC_TRIG0(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)
+#define FTM_SYNC_TRIG0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)
+#define FTM_SYNC_TRIG0 FTM_SYNC_TRIG0_MASK
 #define FTM_SYNC_TRIG1_MASK                      (0x20U)
 #define FTM_SYNC_TRIG1_SHIFT                     (5U)
-#define FTM_SYNC_TRIG1(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)
+#define FTM_SYNC_TRIG1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)
+#define FTM_SYNC_TRIG1 FTM_SYNC_TRIG1_MASK
 #define FTM_SYNC_TRIG2_MASK                      (0x40U)
 #define FTM_SYNC_TRIG2_SHIFT                     (6U)
-#define FTM_SYNC_TRIG2(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)
+#define FTM_SYNC_TRIG2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)
+#define FTM_SYNC_TRIG2 FTM_SYNC_TRIG2_MASK
 #define FTM_SYNC_SWSYNC_MASK                     (0x80U)
 #define FTM_SYNC_SWSYNC_SHIFT                    (7U)
-#define FTM_SYNC_SWSYNC(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)
+#define FTM_SYNC_SWSYNC_SET(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)
+#define FTM_SYNC_SWSYNC FTM_SYNC_SWSYNC_MASK
 
 /*! @name OUTINIT - Initial State For Channels Output */
 #define FTM_OUTINIT_CH0OI_MASK                   (0x1U)
 #define FTM_OUTINIT_CH0OI_SHIFT                  (0U)
-#define FTM_OUTINIT_CH0OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)
+#define FTM_OUTINIT_CH0OI_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)
+#define FTM_OUTINIT_CH0OI FTM_OUTINIT_CH0OI_MASK
 #define FTM_OUTINIT_CH1OI_MASK                   (0x2U)
 #define FTM_OUTINIT_CH1OI_SHIFT                  (1U)
-#define FTM_OUTINIT_CH1OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)
+#define FTM_OUTINIT_CH1OI_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)
+#define FTM_OUTINIT_CH1OI FTM_OUTINIT_CH1OI_MASK
 #define FTM_OUTINIT_CH2OI_MASK                   (0x4U)
 #define FTM_OUTINIT_CH2OI_SHIFT                  (2U)
-#define FTM_OUTINIT_CH2OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)
+#define FTM_OUTINIT_CH2OI_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)
+#define FTM_OUTINIT_CH2OI FTM_OUTINIT_CH2OI_MASK
 #define FTM_OUTINIT_CH3OI_MASK                   (0x8U)
 #define FTM_OUTINIT_CH3OI_SHIFT                  (3U)
-#define FTM_OUTINIT_CH3OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)
+#define FTM_OUTINIT_CH3OI_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)
+#define FTM_OUTINIT_CH3OI FTM_OUTINIT_CH3OI_MASK
 #define FTM_OUTINIT_CH4OI_MASK                   (0x10U)
 #define FTM_OUTINIT_CH4OI_SHIFT                  (4U)
-#define FTM_OUTINIT_CH4OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)
+#define FTM_OUTINIT_CH4OI_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)
+#define FTM_OUTINIT_CH4OI FTM_OUTINIT_CH4OI_MASK
 #define FTM_OUTINIT_CH5OI_MASK                   (0x20U)
 #define FTM_OUTINIT_CH5OI_SHIFT                  (5U)
-#define FTM_OUTINIT_CH5OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)
+#define FTM_OUTINIT_CH5OI_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)
+#define FTM_OUTINIT_CH5OI FTM_OUTINIT_CH5OI_MASK
 #define FTM_OUTINIT_CH6OI_MASK                   (0x40U)
 #define FTM_OUTINIT_CH6OI_SHIFT                  (6U)
-#define FTM_OUTINIT_CH6OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)
+#define FTM_OUTINIT_CH6OI_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)
+#define FTM_OUTINIT_CH6OI FTM_OUTINIT_CH6OI_MASK
 #define FTM_OUTINIT_CH7OI_MASK                   (0x80U)
 #define FTM_OUTINIT_CH7OI_SHIFT                  (7U)
-#define FTM_OUTINIT_CH7OI(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)
+#define FTM_OUTINIT_CH7OI_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)
+#define FTM_OUTINIT_CH7OI FTM_OUTINIT_CH7OI_MASK
 
 /*! @name OUTMASK - Output Mask */
 #define FTM_OUTMASK_CH0OM_MASK                   (0x1U)
 #define FTM_OUTMASK_CH0OM_SHIFT                  (0U)
-#define FTM_OUTMASK_CH0OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)
+#define FTM_OUTMASK_CH0OM_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)
+#define FTM_OUTMASK_CH0OM FTM_OUTMASK_CH0OM_MASK
 #define FTM_OUTMASK_CH1OM_MASK                   (0x2U)
 #define FTM_OUTMASK_CH1OM_SHIFT                  (1U)
-#define FTM_OUTMASK_CH1OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)
+#define FTM_OUTMASK_CH1OM_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)
+#define FTM_OUTMASK_CH1OM FTM_OUTMASK_CH1OM_MASK
 #define FTM_OUTMASK_CH2OM_MASK                   (0x4U)
 #define FTM_OUTMASK_CH2OM_SHIFT                  (2U)
-#define FTM_OUTMASK_CH2OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)
+#define FTM_OUTMASK_CH2OM_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)
+#define FTM_OUTMASK_CH2OM FTM_OUTMASK_CH2OM_MASK
 #define FTM_OUTMASK_CH3OM_MASK                   (0x8U)
 #define FTM_OUTMASK_CH3OM_SHIFT                  (3U)
-#define FTM_OUTMASK_CH3OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)
+#define FTM_OUTMASK_CH3OM_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)
+#define FTM_OUTMASK_CH3OM FTM_OUTMASK_CH3OM_MASK
 #define FTM_OUTMASK_CH4OM_MASK                   (0x10U)
 #define FTM_OUTMASK_CH4OM_SHIFT                  (4U)
-#define FTM_OUTMASK_CH4OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)
+#define FTM_OUTMASK_CH4OM_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)
+#define FTM_OUTMASK_CH4OM FTM_OUTMASK_CH4OM_MASK
 #define FTM_OUTMASK_CH5OM_MASK                   (0x20U)
 #define FTM_OUTMASK_CH5OM_SHIFT                  (5U)
-#define FTM_OUTMASK_CH5OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)
+#define FTM_OUTMASK_CH5OM_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)
+#define FTM_OUTMASK_CH5OM FTM_OUTMASK_CH5OM_MASK
 #define FTM_OUTMASK_CH6OM_MASK                   (0x40U)
 #define FTM_OUTMASK_CH6OM_SHIFT                  (6U)
-#define FTM_OUTMASK_CH6OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)
+#define FTM_OUTMASK_CH6OM_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)
+#define FTM_OUTMASK_CH6OM FTM_OUTMASK_CH6OM_MASK
 #define FTM_OUTMASK_CH7OM_MASK                   (0x80U)
 #define FTM_OUTMASK_CH7OM_SHIFT                  (7U)
-#define FTM_OUTMASK_CH7OM(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)
+#define FTM_OUTMASK_CH7OM_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)
+#define FTM_OUTMASK_CH7OM FTM_OUTMASK_CH7OM_MASK
 
 /*! @name COMBINE - Function For Linked Channels */
 #define FTM_COMBINE_COMBINE0_MASK                (0x1U)
 #define FTM_COMBINE_COMBINE0_SHIFT               (0U)
-#define FTM_COMBINE_COMBINE0(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)
+#define FTM_COMBINE_COMBINE0_SET(x)              (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)
+#define FTM_COMBINE_COMBINE0 FTM_COMBINE_COMBINE0_MASK
 #define FTM_COMBINE_COMP0_MASK                   (0x2U)
 #define FTM_COMBINE_COMP0_SHIFT                  (1U)
-#define FTM_COMBINE_COMP0(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)
+#define FTM_COMBINE_COMP0_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)
+#define FTM_COMBINE_COMP0 FTM_COMBINE_COMP0_MASK
 #define FTM_COMBINE_DECAPEN0_MASK                (0x4U)
 #define FTM_COMBINE_DECAPEN0_SHIFT               (2U)
-#define FTM_COMBINE_DECAPEN0(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)
+#define FTM_COMBINE_DECAPEN0_SET(x)              (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)
+#define FTM_COMBINE_DECAPEN0 FTM_COMBINE_DECAPEN0_MASK
 #define FTM_COMBINE_DECAP0_MASK                  (0x8U)
 #define FTM_COMBINE_DECAP0_SHIFT                 (3U)
-#define FTM_COMBINE_DECAP0(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)
+#define FTM_COMBINE_DECAP0_SET(x)                (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)
+#define FTM_COMBINE_DECAP0 FTM_COMBINE_DECAP0_MASK
 #define FTM_COMBINE_DTEN0_MASK                   (0x10U)
 #define FTM_COMBINE_DTEN0_SHIFT                  (4U)
-#define FTM_COMBINE_DTEN0(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)
+#define FTM_COMBINE_DTEN0_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)
+#define FTM_COMBINE_DTEN0 FTM_COMBINE_DTEN0_MASK
 #define FTM_COMBINE_SYNCEN0_MASK                 (0x20U)
 #define FTM_COMBINE_SYNCEN0_SHIFT                (5U)
-#define FTM_COMBINE_SYNCEN0(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)
+#define FTM_COMBINE_SYNCEN0_SET(x)               (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)
+#define FTM_COMBINE_SYNCEN0 FTM_COMBINE_SYNCEN0_MASK
 #define FTM_COMBINE_FAULTEN0_MASK                (0x40U)
 #define FTM_COMBINE_FAULTEN0_SHIFT               (6U)
-#define FTM_COMBINE_FAULTEN0(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)
+#define FTM_COMBINE_FAULTEN0_SET(x)              (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)
+#define FTM_COMBINE_FAULTEN0 FTM_COMBINE_FAULTEN0_MASK
 #define FTM_COMBINE_COMBINE1_MASK                (0x100U)
 #define FTM_COMBINE_COMBINE1_SHIFT               (8U)
-#define FTM_COMBINE_COMBINE1(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)
+#define FTM_COMBINE_COMBINE1_SET(x)              (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)
+#define FTM_COMBINE_COMBINE1 FTM_COMBINE_COMBINE1_MASK
 #define FTM_COMBINE_COMP1_MASK                   (0x200U)
 #define FTM_COMBINE_COMP1_SHIFT                  (9U)
-#define FTM_COMBINE_COMP1(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)
+#define FTM_COMBINE_COMP1_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)
+#define FTM_COMBINE_COMP1 FTM_COMBINE_COMP1_MASK
 #define FTM_COMBINE_DECAPEN1_MASK                (0x400U)
 #define FTM_COMBINE_DECAPEN1_SHIFT               (10U)
-#define FTM_COMBINE_DECAPEN1(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)
+#define FTM_COMBINE_DECAPEN1_SET(x)              (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)
+#define FTM_COMBINE_DECAPEN1 FTM_COMBINE_DECAPEN1_MASK
 #define FTM_COMBINE_DECAP1_MASK                  (0x800U)
 #define FTM_COMBINE_DECAP1_SHIFT                 (11U)
-#define FTM_COMBINE_DECAP1(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)
+#define FTM_COMBINE_DECAP1_SET(x)                (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)
+#define FTM_COMBINE_DECAP1 FTM_COMBINE_DECAP1_MASK
 #define FTM_COMBINE_DTEN1_MASK                   (0x1000U)
 #define FTM_COMBINE_DTEN1_SHIFT                  (12U)
-#define FTM_COMBINE_DTEN1(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)
+#define FTM_COMBINE_DTEN1_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)
+#define FTM_COMBINE_DTEN1 FTM_COMBINE_DTEN1_MASK
 #define FTM_COMBINE_SYNCEN1_MASK                 (0x2000U)
 #define FTM_COMBINE_SYNCEN1_SHIFT                (13U)
-#define FTM_COMBINE_SYNCEN1(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)
+#define FTM_COMBINE_SYNCEN1_SET(x)               (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)
+#define FTM_COMBINE_SYNCEN1 FTM_COMBINE_SYNCEN1_MASK
 #define FTM_COMBINE_FAULTEN1_MASK                (0x4000U)
 #define FTM_COMBINE_FAULTEN1_SHIFT               (14U)
-#define FTM_COMBINE_FAULTEN1(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)
+#define FTM_COMBINE_FAULTEN1_SET(x)              (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)
+#define FTM_COMBINE_FAULTEN1 FTM_COMBINE_FAULTEN1_MASK
 #define FTM_COMBINE_COMBINE2_MASK                (0x10000U)
 #define FTM_COMBINE_COMBINE2_SHIFT               (16U)
-#define FTM_COMBINE_COMBINE2(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)
+#define FTM_COMBINE_COMBINE2_SET(x)              (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)
+#define FTM_COMBINE_COMBINE2 FTM_COMBINE_COMBINE2_MASK
 #define FTM_COMBINE_COMP2_MASK                   (0x20000U)
 #define FTM_COMBINE_COMP2_SHIFT                  (17U)
-#define FTM_COMBINE_COMP2(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)
+#define FTM_COMBINE_COMP2_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)
+#define FTM_COMBINE_COMP2 FTM_COMBINE_COMP2_MASK
 #define FTM_COMBINE_DECAPEN2_MASK                (0x40000U)
 #define FTM_COMBINE_DECAPEN2_SHIFT               (18U)
-#define FTM_COMBINE_DECAPEN2(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)
+#define FTM_COMBINE_DECAPEN2_SET(x)              (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)
+#define FTM_COMBINE_DECAPEN2 FTM_COMBINE_DECAPEN2_MASK
 #define FTM_COMBINE_DECAP2_MASK                  (0x80000U)
 #define FTM_COMBINE_DECAP2_SHIFT                 (19U)
-#define FTM_COMBINE_DECAP2(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)
+#define FTM_COMBINE_DECAP2_SET(x)                (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)
+#define FTM_COMBINE_DECAP2 FTM_COMBINE_DECAP2_MASK
 #define FTM_COMBINE_DTEN2_MASK                   (0x100000U)
 #define FTM_COMBINE_DTEN2_SHIFT                  (20U)
-#define FTM_COMBINE_DTEN2(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)
+#define FTM_COMBINE_DTEN2_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)
+#define FTM_COMBINE_DTEN2 FTM_COMBINE_DTEN2_MASK
 #define FTM_COMBINE_SYNCEN2_MASK                 (0x200000U)
 #define FTM_COMBINE_SYNCEN2_SHIFT                (21U)
-#define FTM_COMBINE_SYNCEN2(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)
+#define FTM_COMBINE_SYNCEN2_SET(x)               (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)
+#define FTM_COMBINE_SYNCEN2 FTM_COMBINE_SYNCEN2_MASK
 #define FTM_COMBINE_FAULTEN2_MASK                (0x400000U)
 #define FTM_COMBINE_FAULTEN2_SHIFT               (22U)
-#define FTM_COMBINE_FAULTEN2(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)
+#define FTM_COMBINE_FAULTEN2_SET(x)              (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)
+#define FTM_COMBINE_FAULTEN2 FTM_COMBINE_FAULTEN2_MASK
 #define FTM_COMBINE_COMBINE3_MASK                (0x1000000U)
 #define FTM_COMBINE_COMBINE3_SHIFT               (24U)
-#define FTM_COMBINE_COMBINE3(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)
+#define FTM_COMBINE_COMBINE3_SET(x)              (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)
+#define FTM_COMBINE_COMBINE3 FTM_COMBINE_COMBINE3_MASK
 #define FTM_COMBINE_COMP3_MASK                   (0x2000000U)
 #define FTM_COMBINE_COMP3_SHIFT                  (25U)
-#define FTM_COMBINE_COMP3(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)
+#define FTM_COMBINE_COMP3_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)
+#define FTM_COMBINE_COMP3 FTM_COMBINE_COMP3_MASK
 #define FTM_COMBINE_DECAPEN3_MASK                (0x4000000U)
 #define FTM_COMBINE_DECAPEN3_SHIFT               (26U)
-#define FTM_COMBINE_DECAPEN3(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)
+#define FTM_COMBINE_DECAPEN3_SET(x)              (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)
+#define FTM_COMBINE_DECAPEN3 FTM_COMBINE_DECAPEN3_MASK
 #define FTM_COMBINE_DECAP3_MASK                  (0x8000000U)
 #define FTM_COMBINE_DECAP3_SHIFT                 (27U)
-#define FTM_COMBINE_DECAP3(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)
+#define FTM_COMBINE_DECAP3_SET(x)                (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)
+#define FTM_COMBINE_DECAP3 FTM_COMBINE_DECAP3_MASK
 #define FTM_COMBINE_DTEN3_MASK                   (0x10000000U)
 #define FTM_COMBINE_DTEN3_SHIFT                  (28U)
-#define FTM_COMBINE_DTEN3(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)
+#define FTM_COMBINE_DTEN3_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)
+#define FTM_COMBINE_DTEN3 FTM_COMBINE_DTEN3_MASK
 #define FTM_COMBINE_SYNCEN3_MASK                 (0x20000000U)
 #define FTM_COMBINE_SYNCEN3_SHIFT                (29U)
-#define FTM_COMBINE_SYNCEN3(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)
+#define FTM_COMBINE_SYNCEN3_SET(x)               (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)
+#define FTM_COMBINE_SYNCEN3 FTM_COMBINE_SYNCEN3_MASK
 #define FTM_COMBINE_FAULTEN3_MASK                (0x40000000U)
 #define FTM_COMBINE_FAULTEN3_SHIFT               (30U)
-#define FTM_COMBINE_FAULTEN3(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)
+#define FTM_COMBINE_FAULTEN3_SET(x)              (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)
+#define FTM_COMBINE_FAULTEN3 FTM_COMBINE_FAULTEN3_MASK
 
 /*! @name DEADTIME - Deadtime Insertion Control */
 #define FTM_DEADTIME_DTVAL_MASK                  (0x3FU)
 #define FTM_DEADTIME_DTVAL_SHIFT                 (0U)
-#define FTM_DEADTIME_DTVAL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
+#define FTM_DEADTIME_DTVAL_SET(x)                (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
+#define FTM_DEADTIME_DTVAL FTM_DEADTIME_DTVAL_MASK
 #define FTM_DEADTIME_DTPS_MASK                   (0xC0U)
 #define FTM_DEADTIME_DTPS_SHIFT                  (6U)
-#define FTM_DEADTIME_DTPS(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
+#define FTM_DEADTIME_DTPS_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
+#define FTM_DEADTIME_DTPS FTM_DEADTIME_DTPS_MASK
 
 /*! @name EXTTRIG - FTM External Trigger */
 #define FTM_EXTTRIG_CH2TRIG_MASK                 (0x1U)
 #define FTM_EXTTRIG_CH2TRIG_SHIFT                (0U)
-#define FTM_EXTTRIG_CH2TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)
+#define FTM_EXTTRIG_CH2TRIG_SET(x)               (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)
+#define FTM_EXTTRIG_CH2TRIG FTM_EXTTRIG_CH2TRIG_MASK
 #define FTM_EXTTRIG_CH3TRIG_MASK                 (0x2U)
 #define FTM_EXTTRIG_CH3TRIG_SHIFT                (1U)
-#define FTM_EXTTRIG_CH3TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)
+#define FTM_EXTTRIG_CH3TRIG_SET(x)               (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)
+#define FTM_EXTTRIG_CH3TRIG FTM_EXTTRIG_CH3TRIG_MASK
 #define FTM_EXTTRIG_CH4TRIG_MASK                 (0x4U)
 #define FTM_EXTTRIG_CH4TRIG_SHIFT                (2U)
-#define FTM_EXTTRIG_CH4TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)
+#define FTM_EXTTRIG_CH4TRIG_SET(x)               (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)
+#define FTM_EXTTRIG_CH4TRIG FTM_EXTTRIG_CH4TRIG_MASK
 #define FTM_EXTTRIG_CH5TRIG_MASK                 (0x8U)
 #define FTM_EXTTRIG_CH5TRIG_SHIFT                (3U)
-#define FTM_EXTTRIG_CH5TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)
+#define FTM_EXTTRIG_CH5TRIG_SET(x)               (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)
+#define FTM_EXTTRIG_CH5TRIG FTM_EXTTRIG_CH5TRIG_MASK
 #define FTM_EXTTRIG_CH0TRIG_MASK                 (0x10U)
 #define FTM_EXTTRIG_CH0TRIG_SHIFT                (4U)
-#define FTM_EXTTRIG_CH0TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)
+#define FTM_EXTTRIG_CH0TRIG_SET(x)               (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)
+#define FTM_EXTTRIG_CH0TRIG FTM_EXTTRIG_CH0TRIG_MASK
 #define FTM_EXTTRIG_CH1TRIG_MASK                 (0x20U)
 #define FTM_EXTTRIG_CH1TRIG_SHIFT                (5U)
-#define FTM_EXTTRIG_CH1TRIG(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)
+#define FTM_EXTTRIG_CH1TRIG_SET(x)               (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)
+#define FTM_EXTTRIG_CH1TRIG FTM_EXTTRIG_CH1TRIG_MASK
 #define FTM_EXTTRIG_INITTRIGEN_MASK              (0x40U)
 #define FTM_EXTTRIG_INITTRIGEN_SHIFT             (6U)
-#define FTM_EXTTRIG_INITTRIGEN(x)                (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)
+#define FTM_EXTTRIG_INITTRIGEN_SET(x)            (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)
+#define FTM_EXTTRIG_INITTRIGEN FTM_EXTTRIG_INITTRIGEN_MASK
 #define FTM_EXTTRIG_TRIGF_MASK                   (0x80U)
 #define FTM_EXTTRIG_TRIGF_SHIFT                  (7U)
-#define FTM_EXTTRIG_TRIGF(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)
+#define FTM_EXTTRIG_TRIGF_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)
+#define FTM_EXTTRIG_TRIGF FTM_EXTTRIG_TRIGF_MASK
 
 /*! @name POL - Channels Polarity */
 #define FTM_POL_POL0_MASK                        (0x1U)
 #define FTM_POL_POL0_SHIFT                       (0U)
-#define FTM_POL_POL0(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)
+#define FTM_POL_POL0_SET(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)
+#define FTM_POL_POL0 FTM_POL_POL0_MASK
 #define FTM_POL_POL1_MASK                        (0x2U)
 #define FTM_POL_POL1_SHIFT                       (1U)
-#define FTM_POL_POL1(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)
+#define FTM_POL_POL1_SET(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)
+#define FTM_POL_POL1 FTM_POL_POL1_MASK
 #define FTM_POL_POL2_MASK                        (0x4U)
 #define FTM_POL_POL2_SHIFT                       (2U)
-#define FTM_POL_POL2(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)
+#define FTM_POL_POL2_SET(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)
+#define FTM_POL_POL2 FTM_POL_POL2_MASK
 #define FTM_POL_POL3_MASK                        (0x8U)
 #define FTM_POL_POL3_SHIFT                       (3U)
-#define FTM_POL_POL3(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)
+#define FTM_POL_POL3_SET(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)
+#define FTM_POL_POL3 FTM_POL_POL3_MASK
 #define FTM_POL_POL4_MASK                        (0x10U)
 #define FTM_POL_POL4_SHIFT                       (4U)
-#define FTM_POL_POL4(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)
+#define FTM_POL_POL4_SET(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)
+#define FTM_POL_POL4 FTM_POL_POL4_MASK
 #define FTM_POL_POL5_MASK                        (0x20U)
 #define FTM_POL_POL5_SHIFT                       (5U)
-#define FTM_POL_POL5(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)
+#define FTM_POL_POL5_SET(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)
+#define FTM_POL_POL5 FTM_POL_POL5_MASK
 #define FTM_POL_POL6_MASK                        (0x40U)
 #define FTM_POL_POL6_SHIFT                       (6U)
-#define FTM_POL_POL6(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)
+#define FTM_POL_POL6_SET(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)
+#define FTM_POL_POL6 FTM_POL_POL6_MASK
 #define FTM_POL_POL7_MASK                        (0x80U)
 #define FTM_POL_POL7_SHIFT                       (7U)
-#define FTM_POL_POL7(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)
+#define FTM_POL_POL7_SET(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)
+#define FTM_POL_POL7 FTM_POL_POL7_MASK
 
 /*! @name FMS - Fault Mode Status */
 #define FTM_FMS_FAULTF0_MASK                     (0x1U)
 #define FTM_FMS_FAULTF0_SHIFT                    (0U)
-#define FTM_FMS_FAULTF0(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)
+#define FTM_FMS_FAULTF0_SET(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)
+#define FTM_FMS_FAULTF0 FTM_FMS_FAULTF0_MASK
 #define FTM_FMS_FAULTF1_MASK                     (0x2U)
 #define FTM_FMS_FAULTF1_SHIFT                    (1U)
-#define FTM_FMS_FAULTF1(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)
+#define FTM_FMS_FAULTF1_SET(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)
+#define FTM_FMS_FAULTF1 FTM_FMS_FAULTF1_MASK
 #define FTM_FMS_FAULTF2_MASK                     (0x4U)
 #define FTM_FMS_FAULTF2_SHIFT                    (2U)
-#define FTM_FMS_FAULTF2(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)
+#define FTM_FMS_FAULTF2_SET(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)
+#define FTM_FMS_FAULTF2 FTM_FMS_FAULTF2_MASK
 #define FTM_FMS_FAULTF3_MASK                     (0x8U)
 #define FTM_FMS_FAULTF3_SHIFT                    (3U)
-#define FTM_FMS_FAULTF3(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)
+#define FTM_FMS_FAULTF3_SET(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)
+#define FTM_FMS_FAULTF3 FTM_FMS_FAULTF3_MASK
 #define FTM_FMS_FAULTIN_MASK                     (0x20U)
 #define FTM_FMS_FAULTIN_SHIFT                    (5U)
-#define FTM_FMS_FAULTIN(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)
+#define FTM_FMS_FAULTIN_SET(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)
+#define FTM_FMS_FAULTIN FTM_FMS_FAULTIN_MASK
 #define FTM_FMS_WPEN_MASK                        (0x40U)
 #define FTM_FMS_WPEN_SHIFT                       (6U)
-#define FTM_FMS_WPEN(x)                          (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)
+#define FTM_FMS_WPEN_SET(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)
+#define FTM_FMS_WPEN FTM_FMS_WPEN_MASK
 #define FTM_FMS_FAULTF_MASK                      (0x80U)
 #define FTM_FMS_FAULTF_SHIFT                     (7U)
-#define FTM_FMS_FAULTF(x)                        (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)
+#define FTM_FMS_FAULTF_SET(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)
+#define FTM_FMS_FAULTF FTM_FMS_FAULTF_MASK
 
 /*! @name FILTER - Input Capture Filter Control */
 #define FTM_FILTER_CH0FVAL_MASK                  (0xFU)
 #define FTM_FILTER_CH0FVAL_SHIFT                 (0U)
-#define FTM_FILTER_CH0FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
+#define FTM_FILTER_CH0FVAL_SET(x)                (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
+#define FTM_FILTER_CH0FVAL FTM_FILTER_CH0FVAL_MASK
 #define FTM_FILTER_CH1FVAL_MASK                  (0xF0U)
 #define FTM_FILTER_CH1FVAL_SHIFT                 (4U)
-#define FTM_FILTER_CH1FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
+#define FTM_FILTER_CH1FVAL_SET(x)                (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
+#define FTM_FILTER_CH1FVAL FTM_FILTER_CH1FVAL_MASK
 #define FTM_FILTER_CH2FVAL_MASK                  (0xF00U)
 #define FTM_FILTER_CH2FVAL_SHIFT                 (8U)
-#define FTM_FILTER_CH2FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
+#define FTM_FILTER_CH2FVAL_SET(x)                (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
+#define FTM_FILTER_CH2FVAL FTM_FILTER_CH2FVAL_MASK
 #define FTM_FILTER_CH3FVAL_MASK                  (0xF000U)
 #define FTM_FILTER_CH3FVAL_SHIFT                 (12U)
-#define FTM_FILTER_CH3FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
+#define FTM_FILTER_CH3FVAL_SET(x)                (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
+#define FTM_FILTER_CH3FVAL FTM_FILTER_CH3FVAL_MASK
 
 /*! @name FLTCTRL - Fault Control */
 #define FTM_FLTCTRL_FAULT0EN_MASK                (0x1U)
 #define FTM_FLTCTRL_FAULT0EN_SHIFT               (0U)
-#define FTM_FLTCTRL_FAULT0EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)
+#define FTM_FLTCTRL_FAULT0EN_SET(x)              (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)
+#define FTM_FLTCTRL_FAULT0EN FTM_FLTCTRL_FAULT0EN_MASK
 #define FTM_FLTCTRL_FAULT1EN_MASK                (0x2U)
 #define FTM_FLTCTRL_FAULT1EN_SHIFT               (1U)
-#define FTM_FLTCTRL_FAULT1EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)
+#define FTM_FLTCTRL_FAULT1EN_SET(x)              (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)
+#define FTM_FLTCTRL_FAULT1EN FTM_FLTCTRL_FAULT1EN_MASK
 #define FTM_FLTCTRL_FAULT2EN_MASK                (0x4U)
 #define FTM_FLTCTRL_FAULT2EN_SHIFT               (2U)
-#define FTM_FLTCTRL_FAULT2EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)
+#define FTM_FLTCTRL_FAULT2EN_SET(x)              (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)
+#define FTM_FLTCTRL_FAULT2EN FTM_FLTCTRL_FAULT2EN_MASK
 #define FTM_FLTCTRL_FAULT3EN_MASK                (0x8U)
 #define FTM_FLTCTRL_FAULT3EN_SHIFT               (3U)
-#define FTM_FLTCTRL_FAULT3EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)
+#define FTM_FLTCTRL_FAULT3EN_SET(x)              (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)
+#define FTM_FLTCTRL_FAULT3EN FTM_FLTCTRL_FAULT3EN_MASK
 #define FTM_FLTCTRL_FFLTR0EN_MASK                (0x10U)
 #define FTM_FLTCTRL_FFLTR0EN_SHIFT               (4U)
-#define FTM_FLTCTRL_FFLTR0EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)
+#define FTM_FLTCTRL_FFLTR0EN_SET(x)              (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)
+#define FTM_FLTCTRL_FFLTR0EN FTM_FLTCTRL_FFLTR0EN_MASK
 #define FTM_FLTCTRL_FFLTR1EN_MASK                (0x20U)
 #define FTM_FLTCTRL_FFLTR1EN_SHIFT               (5U)
-#define FTM_FLTCTRL_FFLTR1EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)
+#define FTM_FLTCTRL_FFLTR1EN_SET(x)              (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)
+#define FTM_FLTCTRL_FFLTR1EN FTM_FLTCTRL_FFLTR1EN_MASK
 #define FTM_FLTCTRL_FFLTR2EN_MASK                (0x40U)
 #define FTM_FLTCTRL_FFLTR2EN_SHIFT               (6U)
-#define FTM_FLTCTRL_FFLTR2EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)
+#define FTM_FLTCTRL_FFLTR2EN_SET(x)              (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)
+#define FTM_FLTCTRL_FFLTR2EN FTM_FLTCTRL_FFLTR2EN_MASK
 #define FTM_FLTCTRL_FFLTR3EN_MASK                (0x80U)
 #define FTM_FLTCTRL_FFLTR3EN_SHIFT               (7U)
-#define FTM_FLTCTRL_FFLTR3EN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)
+#define FTM_FLTCTRL_FFLTR3EN_SET(x)              (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)
+#define FTM_FLTCTRL_FFLTR3EN FTM_FLTCTRL_FFLTR3EN_MASK
 #define FTM_FLTCTRL_FFVAL_MASK                   (0xF00U)
 #define FTM_FLTCTRL_FFVAL_SHIFT                  (8U)
-#define FTM_FLTCTRL_FFVAL(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
+#define FTM_FLTCTRL_FFVAL_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
+#define FTM_FLTCTRL_FFVAL FTM_FLTCTRL_FFVAL_MASK
 
 /*! @name QDCTRL - Quadrature Decoder Control And Status */
 #define FTM_QDCTRL_QUADEN_MASK                   (0x1U)
 #define FTM_QDCTRL_QUADEN_SHIFT                  (0U)
-#define FTM_QDCTRL_QUADEN(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)
+#define FTM_QDCTRL_QUADEN_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)
+#define FTM_QDCTRL_QUADEN FTM_QDCTRL_QUADEN_MASK
 #define FTM_QDCTRL_TOFDIR_MASK                   (0x2U)
 #define FTM_QDCTRL_TOFDIR_SHIFT                  (1U)
-#define FTM_QDCTRL_TOFDIR(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)
+#define FTM_QDCTRL_TOFDIR_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)
+#define FTM_QDCTRL_TOFDIR FTM_QDCTRL_TOFDIR_MASK
 #define FTM_QDCTRL_QUADIR_MASK                   (0x4U)
 #define FTM_QDCTRL_QUADIR_SHIFT                  (2U)
-#define FTM_QDCTRL_QUADIR(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)
+#define FTM_QDCTRL_QUADIR_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)
+#define FTM_QDCTRL_QUADIR FTM_QDCTRL_QUADIR_MASK
 #define FTM_QDCTRL_QUADMODE_MASK                 (0x8U)
 #define FTM_QDCTRL_QUADMODE_SHIFT                (3U)
-#define FTM_QDCTRL_QUADMODE(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)
+#define FTM_QDCTRL_QUADMODE_SET(x)               (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)
+#define FTM_QDCTRL_QUADMODE FTM_QDCTRL_QUADMODE_MASK
 #define FTM_QDCTRL_PHBPOL_MASK                   (0x10U)
 #define FTM_QDCTRL_PHBPOL_SHIFT                  (4U)
-#define FTM_QDCTRL_PHBPOL(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)
+#define FTM_QDCTRL_PHBPOL_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)
+#define FTM_QDCTRL_PHBPOL FTM_QDCTRL_PHBPOL_MASK
 #define FTM_QDCTRL_PHAPOL_MASK                   (0x20U)
 #define FTM_QDCTRL_PHAPOL_SHIFT                  (5U)
-#define FTM_QDCTRL_PHAPOL(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)
+#define FTM_QDCTRL_PHAPOL_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)
+#define FTM_QDCTRL_PHAPOL FTM_QDCTRL_PHAPOL_MASK
 #define FTM_QDCTRL_PHBFLTREN_MASK                (0x40U)
 #define FTM_QDCTRL_PHBFLTREN_SHIFT               (6U)
-#define FTM_QDCTRL_PHBFLTREN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)
+#define FTM_QDCTRL_PHBFLTREN_SET(x)              (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)
+#define FTM_QDCTRL_PHBFLTREN FTM_QDCTRL_PHBFLTREN_MASK
 #define FTM_QDCTRL_PHAFLTREN_MASK                (0x80U)
 #define FTM_QDCTRL_PHAFLTREN_SHIFT               (7U)
-#define FTM_QDCTRL_PHAFLTREN(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
+#define FTM_QDCTRL_PHAFLTREN_SET(x)              (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
+#define FTM_QDCTRL_PHAFLTREN FTM_QDCTRL_PHAFLTREN_MASK
 
 /*! @name CONF - Configuration */
 #define FTM_CONF_NUMTOF_MASK                     (0x1FU)
 #define FTM_CONF_NUMTOF_SHIFT                    (0U)
-#define FTM_CONF_NUMTOF(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK)
+#define FTM_CONF_NUMTOF_SET(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK)
+#define FTM_CONF_NUMTOF FTM_CONF_NUMTOF_MASK
 #define FTM_CONF_BDMMODE_MASK                    (0xC0U)
 #define FTM_CONF_BDMMODE_SHIFT                   (6U)
-#define FTM_CONF_BDMMODE(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
+#define FTM_CONF_BDMMODE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
+#define FTM_CONF_BDMMODE FTM_CONF_BDMMODE_MASK
 #define FTM_CONF_GTBEEN_MASK                     (0x200U)
 #define FTM_CONF_GTBEEN_SHIFT                    (9U)
-#define FTM_CONF_GTBEEN(x)                       (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)
+#define FTM_CONF_GTBEEN_SET(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)
+#define FTM_CONF_GTBEEN FTM_CONF_GTBEEN_MASK
 #define FTM_CONF_GTBEOUT_MASK                    (0x400U)
 #define FTM_CONF_GTBEOUT_SHIFT                   (10U)
-#define FTM_CONF_GTBEOUT(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)
+#define FTM_CONF_GTBEOUT_SET(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)
+#define FTM_CONF_GTBEOUT FTM_CONF_GTBEOUT_MASK
 
 /*! @name FLTPOL - FTM Fault Input Polarity */
 #define FTM_FLTPOL_FLT0POL_MASK                  (0x1U)
 #define FTM_FLTPOL_FLT0POL_SHIFT                 (0U)
-#define FTM_FLTPOL_FLT0POL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)
+#define FTM_FLTPOL_FLT0POL_SET(x)                (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)
+#define FTM_FLTPOL_FLT0POL FTM_FLTPOL_FLT0POL_MASK
 #define FTM_FLTPOL_FLT1POL_MASK                  (0x2U)
 #define FTM_FLTPOL_FLT1POL_SHIFT                 (1U)
-#define FTM_FLTPOL_FLT1POL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)
+#define FTM_FLTPOL_FLT1POL_SET(x)                (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)
+#define FTM_FLTPOL_FLT1POL FTM_FLTPOL_FLT1POL_MASK
 #define FTM_FLTPOL_FLT2POL_MASK                  (0x4U)
 #define FTM_FLTPOL_FLT2POL_SHIFT                 (2U)
-#define FTM_FLTPOL_FLT2POL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)
+#define FTM_FLTPOL_FLT2POL_SET(x)                (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)
+#define FTM_FLTPOL_FLT2POL FTM_FLTPOL_FLT2POL_MASK
 #define FTM_FLTPOL_FLT3POL_MASK                  (0x8U)
 #define FTM_FLTPOL_FLT3POL_SHIFT                 (3U)
-#define FTM_FLTPOL_FLT3POL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)
+#define FTM_FLTPOL_FLT3POL_SET(x)                (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)
+#define FTM_FLTPOL_FLT3POL FTM_FLTPOL_FLT3POL_MASK
 
 /*! @name SYNCONF - Synchronization Configuration */
 #define FTM_SYNCONF_HWTRIGMODE_MASK              (0x1U)
 #define FTM_SYNCONF_HWTRIGMODE_SHIFT             (0U)
-#define FTM_SYNCONF_HWTRIGMODE(x)                (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)
+#define FTM_SYNCONF_HWTRIGMODE_SET(x)            (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)
+#define FTM_SYNCONF_HWTRIGMODE FTM_SYNCONF_HWTRIGMODE_MASK
 #define FTM_SYNCONF_CNTINC_MASK                  (0x4U)
 #define FTM_SYNCONF_CNTINC_SHIFT                 (2U)
-#define FTM_SYNCONF_CNTINC(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)
+#define FTM_SYNCONF_CNTINC_SET(x)                (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)
+#define FTM_SYNCONF_CNTINC FTM_SYNCONF_CNTINC_MASK
 #define FTM_SYNCONF_INVC_MASK                    (0x10U)
 #define FTM_SYNCONF_INVC_SHIFT                   (4U)
-#define FTM_SYNCONF_INVC(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)
+#define FTM_SYNCONF_INVC_SET(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)
+#define FTM_SYNCONF_INVC FTM_SYNCONF_INVC_MASK
 #define FTM_SYNCONF_SWOC_MASK                    (0x20U)
 #define FTM_SYNCONF_SWOC_SHIFT                   (5U)
-#define FTM_SYNCONF_SWOC(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)
+#define FTM_SYNCONF_SWOC_SET(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)
+#define FTM_SYNCONF_SWOC FTM_SYNCONF_SWOC_MASK
 #define FTM_SYNCONF_SYNCMODE_MASK                (0x80U)
 #define FTM_SYNCONF_SYNCMODE_SHIFT               (7U)
-#define FTM_SYNCONF_SYNCMODE(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)
+#define FTM_SYNCONF_SYNCMODE_SET(x)              (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)
+#define FTM_SYNCONF_SYNCMODE FTM_SYNCONF_SYNCMODE_MASK
 #define FTM_SYNCONF_SWRSTCNT_MASK                (0x100U)
 #define FTM_SYNCONF_SWRSTCNT_SHIFT               (8U)
-#define FTM_SYNCONF_SWRSTCNT(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)
+#define FTM_SYNCONF_SWRSTCNT_SET(x)              (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)
+#define FTM_SYNCONF_SWRSTCNT FTM_SYNCONF_SWRSTCNT_MASK
 #define FTM_SYNCONF_SWWRBUF_MASK                 (0x200U)
 #define FTM_SYNCONF_SWWRBUF_SHIFT                (9U)
-#define FTM_SYNCONF_SWWRBUF(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)
+#define FTM_SYNCONF_SWWRBUF_SET(x)               (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)
+#define FTM_SYNCONF_SWWRBUF FTM_SYNCONF_SWWRBUF_MASK
 #define FTM_SYNCONF_SWOM_MASK                    (0x400U)
 #define FTM_SYNCONF_SWOM_SHIFT                   (10U)
-#define FTM_SYNCONF_SWOM(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)
+#define FTM_SYNCONF_SWOM_SET(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)
+#define FTM_SYNCONF_SWOM FTM_SYNCONF_SWOM_MASK
 #define FTM_SYNCONF_SWINVC_MASK                  (0x800U)
 #define FTM_SYNCONF_SWINVC_SHIFT                 (11U)
-#define FTM_SYNCONF_SWINVC(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)
+#define FTM_SYNCONF_SWINVC_SET(x)                (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)
+#define FTM_SYNCONF_SWINVC FTM_SYNCONF_SWINVC_MASK
 #define FTM_SYNCONF_SWSOC_MASK                   (0x1000U)
 #define FTM_SYNCONF_SWSOC_SHIFT                  (12U)
-#define FTM_SYNCONF_SWSOC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)
+#define FTM_SYNCONF_SWSOC_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)
+#define FTM_SYNCONF_SWSOC FTM_SYNCONF_SWSOC_MASK
 #define FTM_SYNCONF_HWRSTCNT_MASK                (0x10000U)
 #define FTM_SYNCONF_HWRSTCNT_SHIFT               (16U)
-#define FTM_SYNCONF_HWRSTCNT(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)
+#define FTM_SYNCONF_HWRSTCNT_SET(x)              (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)
+#define FTM_SYNCONF_HWRSTCNT FTM_SYNCONF_HWRSTCNT_MASK
 #define FTM_SYNCONF_HWWRBUF_MASK                 (0x20000U)
 #define FTM_SYNCONF_HWWRBUF_SHIFT                (17U)
-#define FTM_SYNCONF_HWWRBUF(x)                   (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)
+#define FTM_SYNCONF_HWWRBUF_SET(x)               (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)
+#define FTM_SYNCONF_HWWRBUF FTM_SYNCONF_HWWRBUF_MASK
 #define FTM_SYNCONF_HWOM_MASK                    (0x40000U)
 #define FTM_SYNCONF_HWOM_SHIFT                   (18U)
-#define FTM_SYNCONF_HWOM(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)
+#define FTM_SYNCONF_HWOM_SET(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)
+#define FTM_SYNCONF_HWOM FTM_SYNCONF_HWOM_MASK
 #define FTM_SYNCONF_HWINVC_MASK                  (0x80000U)
 #define FTM_SYNCONF_HWINVC_SHIFT                 (19U)
-#define FTM_SYNCONF_HWINVC(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)
+#define FTM_SYNCONF_HWINVC_SET(x)                (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)
+#define FTM_SYNCONF_HWINVC FTM_SYNCONF_HWINVC_MASK
 #define FTM_SYNCONF_HWSOC_MASK                   (0x100000U)
 #define FTM_SYNCONF_HWSOC_SHIFT                  (20U)
-#define FTM_SYNCONF_HWSOC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)
+#define FTM_SYNCONF_HWSOC_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)
+#define FTM_SYNCONF_HWSOC FTM_SYNCONF_HWSOC_MASK
 
 /*! @name INVCTRL - FTM Inverting Control */
 #define FTM_INVCTRL_INV0EN_MASK                  (0x1U)
 #define FTM_INVCTRL_INV0EN_SHIFT                 (0U)
-#define FTM_INVCTRL_INV0EN(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)
+#define FTM_INVCTRL_INV0EN_SET(x)                (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)
+#define FTM_INVCTRL_INV0EN FTM_INVCTRL_INV0EN_MASK
 #define FTM_INVCTRL_INV1EN_MASK                  (0x2U)
 #define FTM_INVCTRL_INV1EN_SHIFT                 (1U)
-#define FTM_INVCTRL_INV1EN(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)
+#define FTM_INVCTRL_INV1EN_SET(x)                (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)
+#define FTM_INVCTRL_INV1EN FTM_INVCTRL_INV1EN_MASK
 #define FTM_INVCTRL_INV2EN_MASK                  (0x4U)
 #define FTM_INVCTRL_INV2EN_SHIFT                 (2U)
-#define FTM_INVCTRL_INV2EN(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)
+#define FTM_INVCTRL_INV2EN_SET(x)                (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)
+#define FTM_INVCTRL_INV2EN FTM_INVCTRL_INV2EN_MASK
 #define FTM_INVCTRL_INV3EN_MASK                  (0x8U)
 #define FTM_INVCTRL_INV3EN_SHIFT                 (3U)
-#define FTM_INVCTRL_INV3EN(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)
+#define FTM_INVCTRL_INV3EN_SET(x)                (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)
+#define FTM_INVCTRL_INV3EN FTM_INVCTRL_INV3EN_MASK
 
 /*! @name SWOCTRL - FTM Software Output Control */
 #define FTM_SWOCTRL_CH0OC_MASK                   (0x1U)
 #define FTM_SWOCTRL_CH0OC_SHIFT                  (0U)
-#define FTM_SWOCTRL_CH0OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)
+#define FTM_SWOCTRL_CH0OC_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)
+#define FTM_SWOCTRL_CH0OC FTM_SWOCTRL_CH0OC_MASK
 #define FTM_SWOCTRL_CH1OC_MASK                   (0x2U)
 #define FTM_SWOCTRL_CH1OC_SHIFT                  (1U)
-#define FTM_SWOCTRL_CH1OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)
+#define FTM_SWOCTRL_CH1OC_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)
+#define FTM_SWOCTRL_CH1OC FTM_SWOCTRL_CH1OC_MASK
 #define FTM_SWOCTRL_CH2OC_MASK                   (0x4U)
 #define FTM_SWOCTRL_CH2OC_SHIFT                  (2U)
-#define FTM_SWOCTRL_CH2OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)
+#define FTM_SWOCTRL_CH2OC_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)
+#define FTM_SWOCTRL_CH2OC FTM_SWOCTRL_CH2OC_MASK
 #define FTM_SWOCTRL_CH3OC_MASK                   (0x8U)
 #define FTM_SWOCTRL_CH3OC_SHIFT                  (3U)
-#define FTM_SWOCTRL_CH3OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)
+#define FTM_SWOCTRL_CH3OC_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)
+#define FTM_SWOCTRL_CH3OC FTM_SWOCTRL_CH3OC_MASK
 #define FTM_SWOCTRL_CH4OC_MASK                   (0x10U)
 #define FTM_SWOCTRL_CH4OC_SHIFT                  (4U)
-#define FTM_SWOCTRL_CH4OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)
+#define FTM_SWOCTRL_CH4OC_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)
+#define FTM_SWOCTRL_CH4OC FTM_SWOCTRL_CH4OC_MASK
 #define FTM_SWOCTRL_CH5OC_MASK                   (0x20U)
 #define FTM_SWOCTRL_CH5OC_SHIFT                  (5U)
-#define FTM_SWOCTRL_CH5OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)
+#define FTM_SWOCTRL_CH5OC_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)
+#define FTM_SWOCTRL_CH5OC FTM_SWOCTRL_CH5OC_MASK
 #define FTM_SWOCTRL_CH6OC_MASK                   (0x40U)
 #define FTM_SWOCTRL_CH6OC_SHIFT                  (6U)
-#define FTM_SWOCTRL_CH6OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)
+#define FTM_SWOCTRL_CH6OC_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)
+#define FTM_SWOCTRL_CH6OC FTM_SWOCTRL_CH6OC_MASK
 #define FTM_SWOCTRL_CH7OC_MASK                   (0x80U)
 #define FTM_SWOCTRL_CH7OC_SHIFT                  (7U)
-#define FTM_SWOCTRL_CH7OC(x)                     (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)
+#define FTM_SWOCTRL_CH7OC_SET(x)                 (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)
+#define FTM_SWOCTRL_CH7OC FTM_SWOCTRL_CH7OC_MASK
 #define FTM_SWOCTRL_CH0OCV_MASK                  (0x100U)
 #define FTM_SWOCTRL_CH0OCV_SHIFT                 (8U)
-#define FTM_SWOCTRL_CH0OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)
+#define FTM_SWOCTRL_CH0OCV_SET(x)                (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)
+#define FTM_SWOCTRL_CH0OCV FTM_SWOCTRL_CH0OCV_MASK
 #define FTM_SWOCTRL_CH1OCV_MASK                  (0x200U)
 #define FTM_SWOCTRL_CH1OCV_SHIFT                 (9U)
-#define FTM_SWOCTRL_CH1OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)
+#define FTM_SWOCTRL_CH1OCV_SET(x)                (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)
+#define FTM_SWOCTRL_CH1OCV FTM_SWOCTRL_CH1OCV_MASK
 #define FTM_SWOCTRL_CH2OCV_MASK                  (0x400U)
 #define FTM_SWOCTRL_CH2OCV_SHIFT                 (10U)
-#define FTM_SWOCTRL_CH2OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)
+#define FTM_SWOCTRL_CH2OCV_SET(x)                (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)
+#define FTM_SWOCTRL_CH2OCV FTM_SWOCTRL_CH2OCV_MASK
 #define FTM_SWOCTRL_CH3OCV_MASK                  (0x800U)
 #define FTM_SWOCTRL_CH3OCV_SHIFT                 (11U)
-#define FTM_SWOCTRL_CH3OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)
+#define FTM_SWOCTRL_CH3OCV_SET(x)                (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)
+#define FTM_SWOCTRL_CH3OCV FTM_SWOCTRL_CH3OCV_MASK
 #define FTM_SWOCTRL_CH4OCV_MASK                  (0x1000U)
 #define FTM_SWOCTRL_CH4OCV_SHIFT                 (12U)
-#define FTM_SWOCTRL_CH4OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)
+#define FTM_SWOCTRL_CH4OCV_SET(x)                (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)
+#define FTM_SWOCTRL_CH4OCV FTM_SWOCTRL_CH4OCV_MASK
 #define FTM_SWOCTRL_CH5OCV_MASK                  (0x2000U)
 #define FTM_SWOCTRL_CH5OCV_SHIFT                 (13U)
-#define FTM_SWOCTRL_CH5OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)
+#define FTM_SWOCTRL_CH5OCV_SET(x)                (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)
+#define FTM_SWOCTRL_CH5OCV FTM_SWOCTRL_CH5OCV_MASK
 #define FTM_SWOCTRL_CH6OCV_MASK                  (0x4000U)
 #define FTM_SWOCTRL_CH6OCV_SHIFT                 (14U)
-#define FTM_SWOCTRL_CH6OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)
+#define FTM_SWOCTRL_CH6OCV_SET(x)                (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)
+#define FTM_SWOCTRL_CH6OCV FTM_SWOCTRL_CH6OCV_MASK
 #define FTM_SWOCTRL_CH7OCV_MASK                  (0x8000U)
 #define FTM_SWOCTRL_CH7OCV_SHIFT                 (15U)
-#define FTM_SWOCTRL_CH7OCV(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)
+#define FTM_SWOCTRL_CH7OCV_SET(x)                (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)
+#define FTM_SWOCTRL_CH7OCV FTM_SWOCTRL_CH7OCV_MASK
 
 /*! @name PWMLOAD - FTM PWM Load */
 #define FTM_PWMLOAD_CH0SEL_MASK                  (0x1U)
 #define FTM_PWMLOAD_CH0SEL_SHIFT                 (0U)
-#define FTM_PWMLOAD_CH0SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)
+#define FTM_PWMLOAD_CH0SEL_SET(x)                (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)
+#define FTM_PWMLOAD_CH0SEL FTM_PWMLOAD_CH0SEL_MASK
 #define FTM_PWMLOAD_CH1SEL_MASK                  (0x2U)
 #define FTM_PWMLOAD_CH1SEL_SHIFT                 (1U)
-#define FTM_PWMLOAD_CH1SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)
+#define FTM_PWMLOAD_CH1SEL_SET(x)                (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)
+#define FTM_PWMLOAD_CH1SEL FTM_PWMLOAD_CH1SEL_MASK
 #define FTM_PWMLOAD_CH2SEL_MASK                  (0x4U)
 #define FTM_PWMLOAD_CH2SEL_SHIFT                 (2U)
-#define FTM_PWMLOAD_CH2SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)
+#define FTM_PWMLOAD_CH2SEL_SET(x)                (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)
+#define FTM_PWMLOAD_CH2SEL FTM_PWMLOAD_CH2SEL_MASK
 #define FTM_PWMLOAD_CH3SEL_MASK                  (0x8U)
 #define FTM_PWMLOAD_CH3SEL_SHIFT                 (3U)
-#define FTM_PWMLOAD_CH3SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)
+#define FTM_PWMLOAD_CH3SEL_SET(x)                (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)
+#define FTM_PWMLOAD_CH3SEL FTM_PWMLOAD_CH3SEL_MASK
 #define FTM_PWMLOAD_CH4SEL_MASK                  (0x10U)
 #define FTM_PWMLOAD_CH4SEL_SHIFT                 (4U)
-#define FTM_PWMLOAD_CH4SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)
+#define FTM_PWMLOAD_CH4SEL_SET(x)                (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)
+#define FTM_PWMLOAD_CH4SEL FTM_PWMLOAD_CH4SEL_MASK
 #define FTM_PWMLOAD_CH5SEL_MASK                  (0x20U)
 #define FTM_PWMLOAD_CH5SEL_SHIFT                 (5U)
-#define FTM_PWMLOAD_CH5SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)
+#define FTM_PWMLOAD_CH5SEL_SET(x)                (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)
+#define FTM_PWMLOAD_CH5SEL FTM_PWMLOAD_CH5SEL_MASK
 #define FTM_PWMLOAD_CH6SEL_MASK                  (0x40U)
 #define FTM_PWMLOAD_CH6SEL_SHIFT                 (6U)
-#define FTM_PWMLOAD_CH6SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)
+#define FTM_PWMLOAD_CH6SEL_SET(x)                (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)
+#define FTM_PWMLOAD_CH6SEL FTM_PWMLOAD_CH6SEL_MASK
 #define FTM_PWMLOAD_CH7SEL_MASK                  (0x80U)
 #define FTM_PWMLOAD_CH7SEL_SHIFT                 (7U)
-#define FTM_PWMLOAD_CH7SEL(x)                    (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)
+#define FTM_PWMLOAD_CH7SEL_SET(x)                (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)
+#define FTM_PWMLOAD_CH7SEL FTM_PWMLOAD_CH7SEL_MASK
 #define FTM_PWMLOAD_LDOK_MASK                    (0x200U)
 #define FTM_PWMLOAD_LDOK_SHIFT                   (9U)
-#define FTM_PWMLOAD_LDOK(x)                      (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)
+#define FTM_PWMLOAD_LDOK_SET(x)                  (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)
+#define FTM_PWMLOAD_LDOK FTM_PWMLOAD_LDOK_MASK
 
 
 /*!
@@ -7661,19 +9340,19 @@ typedef struct {
 /** Peripheral FTM0 base address */
 #define FTM0_BASE                                (0x40038000u)
 /** Peripheral FTM0 base pointer */
-#define FTM0                                     ((FTM_Type *)FTM0_BASE)
+#define FTM0                                     ((FTM_TypeDef *)FTM0_BASE)
 /** Peripheral FTM1 base address */
 #define FTM1_BASE                                (0x40039000u)
 /** Peripheral FTM1 base pointer */
-#define FTM1                                     ((FTM_Type *)FTM1_BASE)
+#define FTM1                                     ((FTM_TypeDef *)FTM1_BASE)
 /** Peripheral FTM2 base address */
 #define FTM2_BASE                                (0x4003A000u)
 /** Peripheral FTM2 base pointer */
-#define FTM2                                     ((FTM_Type *)FTM2_BASE)
+#define FTM2                                     ((FTM_TypeDef *)FTM2_BASE)
 /** Peripheral FTM3 base address */
 #define FTM3_BASE                                (0x400B9000u)
 /** Peripheral FTM3 base pointer */
-#define FTM3                                     ((FTM_Type *)FTM3_BASE)
+#define FTM3                                     ((FTM_TypeDef *)FTM3_BASE)
 /** Array initializer of FTM peripheral base addresses */
 #define FTM_BASE_ADDRS                           { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
 /** Array initializer of FTM peripheral base pointers */
@@ -7717,32 +9396,38 @@ typedef struct {
 /*! @name PDOR - Port Data Output Register */
 #define GPIO_PDOR_PDO_MASK                       (0xFFFFFFFFU)
 #define GPIO_PDOR_PDO_SHIFT                      (0U)
-#define GPIO_PDOR_PDO(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
+#define GPIO_PDOR_PDO_SET(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
+#define GPIO_PDOR_PDO GPIO_PDOR_PDO_MASK
 
 /*! @name PSOR - Port Set Output Register */
 #define GPIO_PSOR_PTSO_MASK                      (0xFFFFFFFFU)
 #define GPIO_PSOR_PTSO_SHIFT                     (0U)
-#define GPIO_PSOR_PTSO(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
+#define GPIO_PSOR_PTSO_SET(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
+#define GPIO_PSOR_PTSO GPIO_PSOR_PTSO_MASK
 
 /*! @name PCOR - Port Clear Output Register */
 #define GPIO_PCOR_PTCO_MASK                      (0xFFFFFFFFU)
 #define GPIO_PCOR_PTCO_SHIFT                     (0U)
-#define GPIO_PCOR_PTCO(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
+#define GPIO_PCOR_PTCO_SET(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
+#define GPIO_PCOR_PTCO GPIO_PCOR_PTCO_MASK
 
 /*! @name PTOR - Port Toggle Output Register */
 #define GPIO_PTOR_PTTO_MASK                      (0xFFFFFFFFU)
 #define GPIO_PTOR_PTTO_SHIFT                     (0U)
-#define GPIO_PTOR_PTTO(x)                        (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
+#define GPIO_PTOR_PTTO_SET(x)                    (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
+#define GPIO_PTOR_PTTO GPIO_PTOR_PTTO_MASK
 
 /*! @name PDIR - Port Data Input Register */
 #define GPIO_PDIR_PDI_MASK                       (0xFFFFFFFFU)
 #define GPIO_PDIR_PDI_SHIFT                      (0U)
-#define GPIO_PDIR_PDI(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
+#define GPIO_PDIR_PDI_SET(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
+#define GPIO_PDIR_PDI GPIO_PDIR_PDI_MASK
 
 /*! @name PDDR - Port Data Direction Register */
 #define GPIO_PDDR_PDD_MASK                       (0xFFFFFFFFU)
 #define GPIO_PDDR_PDD_SHIFT                      (0U)
-#define GPIO_PDDR_PDD(x)                         (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
+#define GPIO_PDDR_PDD_SET(x)                     (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
+#define GPIO_PDDR_PDD GPIO_PDDR_PDD_MASK
 
 
 /*!
@@ -7786,7 +9471,7 @@ typedef struct {
    ---------------------------------------------------------------------------- */
 
 /*!
- * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @addtogroup I2Cx_Peripheral_Access_Layer I2C Peripheral Access Layer
  * @{
  */
 
@@ -7804,203 +9489,246 @@ typedef struct {
   __IO uint8_t A2;                                 /**< I2C Address Register 2, offset: 0x9 */
   __IO uint8_t SLTH;                               /**< I2C SCL Low Timeout Register High, offset: 0xA */
   __IO uint8_t SLTL;                               /**< I2C SCL Low Timeout Register Low, offset: 0xB */
-} I2C_Type;
+} I2C_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- I2C Register Masks
    ---------------------------------------------------------------------------- */
 
 /*!
- * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @addtogroup I2Cx_Register_Masks I2C Register Masks
  * @{
  */
 
 /*! @name A1 - I2C Address Register 1 */
-#define I2C_A1_AD_MASK                           (0xFEU)
-#define I2C_A1_AD_SHIFT                          (1U)
-#define I2C_A1_AD(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
+#define I2Cx_A1_AD_MASK                           (0xFEU)
+#define I2Cx_A1_AD_SHIFT                          (1U)
+#define I2Cx_A1_AD_SET(x)                         (((uint8_t)(((uint8_t)(x)) << I2Cx_A1_AD_SHIFT)) & I2Cx_A1_AD_MASK)
+#define I2Cx_A1_AD I2Cx_A1_AD_MASK
 
 /*! @name F - I2C Frequency Divider register */
-#define I2C_F_ICR_MASK                           (0x3FU)
-#define I2C_F_ICR_SHIFT                          (0U)
-#define I2C_F_ICR(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
-#define I2C_F_MULT_MASK                          (0xC0U)
-#define I2C_F_MULT_SHIFT                         (6U)
-#define I2C_F_MULT(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
+#define I2Cx_F_ICR_MASK                           (0x3FU)
+#define I2Cx_F_ICR_SHIFT                          (0U)
+#define I2Cx_F_ICR_SET(x)                         (((uint8_t)(((uint8_t)(x)) << I2Cx_F_ICR_SHIFT)) & I2Cx_F_ICR_MASK)
+#define I2Cx_F_ICR I2Cx_F_ICR_MASK
+#define I2Cx_F_MULT_MASK                          (0xC0U)
+#define I2Cx_F_MULT_SHIFT                         (6U)
+#define I2Cx_F_MULT_SET(x)                        (((uint8_t)(((uint8_t)(x)) << I2Cx_F_MULT_SHIFT)) & I2Cx_F_MULT_MASK)
+#define I2Cx_F_MULT I2Cx_F_MULT_MASK
 
 /*! @name C1 - I2C Control Register 1 */
-#define I2C_C1_DMAEN_MASK                        (0x1U)
-#define I2C_C1_DMAEN_SHIFT                       (0U)
-#define I2C_C1_DMAEN(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
-#define I2C_C1_WUEN_MASK                         (0x2U)
-#define I2C_C1_WUEN_SHIFT                        (1U)
-#define I2C_C1_WUEN(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
-#define I2C_C1_RSTA_MASK                         (0x4U)
-#define I2C_C1_RSTA_SHIFT                        (2U)
-#define I2C_C1_RSTA(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
-#define I2C_C1_TXAK_MASK                         (0x8U)
-#define I2C_C1_TXAK_SHIFT                        (3U)
-#define I2C_C1_TXAK(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
-#define I2C_C1_TX_MASK                           (0x10U)
-#define I2C_C1_TX_SHIFT                          (4U)
-#define I2C_C1_TX(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
-#define I2C_C1_MST_MASK                          (0x20U)
-#define I2C_C1_MST_SHIFT                         (5U)
-#define I2C_C1_MST(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
-#define I2C_C1_IICIE_MASK                        (0x40U)
-#define I2C_C1_IICIE_SHIFT                       (6U)
-#define I2C_C1_IICIE(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
-#define I2C_C1_IICEN_MASK                        (0x80U)
-#define I2C_C1_IICEN_SHIFT                       (7U)
-#define I2C_C1_IICEN(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
+#define I2Cx_C1_DMAEN_MASK                        (0x1U)
+#define I2Cx_C1_DMAEN_SHIFT                       (0U)
+#define I2Cx_C1_DMAEN_SET(x)                      (((uint8_t)(((uint8_t)(x)) << I2Cx_C1_DMAEN_SHIFT)) & I2Cx_C1_DMAEN_MASK)
+#define I2Cx_C1_DMAEN I2Cx_C1_DMAEN_MASK
+#define I2Cx_C1_WUEN_MASK                         (0x2U)
+#define I2Cx_C1_WUEN_SHIFT                        (1U)
+#define I2Cx_C1_WUEN_SET(x)                       (((uint8_t)(((uint8_t)(x)) << I2Cx_C1_WUEN_SHIFT)) & I2Cx_C1_WUEN_MASK)
+#define I2Cx_C1_WUEN I2Cx_C1_WUEN_MASK
+#define I2Cx_C1_RSTA_MASK                         (0x4U)
+#define I2Cx_C1_RSTA_SHIFT                        (2U)
+#define I2Cx_C1_RSTA_SET(x)                       (((uint8_t)(((uint8_t)(x)) << I2Cx_C1_RSTA_SHIFT)) & I2Cx_C1_RSTA_MASK)
+#define I2Cx_C1_RSTA I2Cx_C1_RSTA_MASK
+#define I2Cx_C1_TXAK_MASK                         (0x8U)
+#define I2Cx_C1_TXAK_SHIFT                        (3U)
+#define I2Cx_C1_TXAK_SET(x)                       (((uint8_t)(((uint8_t)(x)) << I2Cx_C1_TXAK_SHIFT)) & I2Cx_C1_TXAK_MASK)
+#define I2Cx_C1_TXAK I2Cx_C1_TXAK_MASK
+#define I2Cx_C1_TX_MASK                           (0x10U)
+#define I2Cx_C1_TX_SHIFT                          (4U)
+#define I2Cx_C1_TX_SET(x)                         (((uint8_t)(((uint8_t)(x)) << I2Cx_C1_TX_SHIFT)) & I2Cx_C1_TX_MASK)
+#define I2Cx_C1_TX I2Cx_C1_TX_MASK
+#define I2Cx_C1_MST_MASK                          (0x20U)
+#define I2Cx_C1_MST_SHIFT                         (5U)
+#define I2Cx_C1_MST_SET(x)                        (((uint8_t)(((uint8_t)(x)) << I2Cx_C1_MST_SHIFT)) & I2Cx_C1_MST_MASK)
+#define I2Cx_C1_MST I2Cx_C1_MST_MASK
+#define I2Cx_C1_IICIE_MASK                        (0x40U)
+#define I2Cx_C1_IICIE_SHIFT                       (6U)
+#define I2Cx_C1_IICIE_SET(x)                      (((uint8_t)(((uint8_t)(x)) << I2Cx_C1_IICIE_SHIFT)) & I2Cx_C1_IICIE_MASK)
+#define I2Cx_C1_IICIE I2Cx_C1_IICIE_MASK
+#define I2Cx_C1_IICEN_MASK                        (0x80U)
+#define I2Cx_C1_IICEN_SHIFT                       (7U)
+#define I2Cx_C1_IICEN_SET(x)                      (((uint8_t)(((uint8_t)(x)) << I2Cx_C1_IICEN_SHIFT)) & I2Cx_C1_IICEN_MASK)
+#define I2Cx_C1_IICEN I2Cx_C1_IICEN_MASK
 
 /*! @name S - I2C Status register */
-#define I2C_S_RXAK_MASK                          (0x1U)
-#define I2C_S_RXAK_SHIFT                         (0U)
-#define I2C_S_RXAK(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
-#define I2C_S_IICIF_MASK                         (0x2U)
-#define I2C_S_IICIF_SHIFT                        (1U)
-#define I2C_S_IICIF(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
-#define I2C_S_SRW_MASK                           (0x4U)
-#define I2C_S_SRW_SHIFT                          (2U)
-#define I2C_S_SRW(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
-#define I2C_S_RAM_MASK                           (0x8U)
-#define I2C_S_RAM_SHIFT                          (3U)
-#define I2C_S_RAM(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
-#define I2C_S_ARBL_MASK                          (0x10U)
-#define I2C_S_ARBL_SHIFT                         (4U)
-#define I2C_S_ARBL(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
-#define I2C_S_BUSY_MASK                          (0x20U)
-#define I2C_S_BUSY_SHIFT                         (5U)
-#define I2C_S_BUSY(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
-#define I2C_S_IAAS_MASK                          (0x40U)
-#define I2C_S_IAAS_SHIFT                         (6U)
-#define I2C_S_IAAS(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
-#define I2C_S_TCF_MASK                           (0x80U)
-#define I2C_S_TCF_SHIFT                          (7U)
-#define I2C_S_TCF(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
+#define I2Cx_S_RXAK_MASK                          (0x1U)
+#define I2Cx_S_RXAK_SHIFT                         (0U)
+#define I2Cx_S_RXAK_SET(x)                        (((uint8_t)(((uint8_t)(x)) << I2Cx_S_RXAK_SHIFT)) & I2Cx_S_RXAK_MASK)
+#define I2Cx_S_RXAK I2Cx_S_RXAK_MASK
+#define I2Cx_S_IICIF_MASK                         (0x2U)
+#define I2Cx_S_IICIF_SHIFT                        (1U)
+#define I2Cx_S_IICIF_SET(x)                       (((uint8_t)(((uint8_t)(x)) << I2Cx_S_IICIF_SHIFT)) & I2Cx_S_IICIF_MASK)
+#define I2Cx_S_IICIF I2Cx_S_IICIF_MASK
+#define I2Cx_S_SRW_MASK                           (0x4U)
+#define I2Cx_S_SRW_SHIFT                          (2U)
+#define I2Cx_S_SRW_SET(x)                         (((uint8_t)(((uint8_t)(x)) << I2Cx_S_SRW_SHIFT)) & I2Cx_S_SRW_MASK)
+#define I2Cx_S_SRW I2Cx_S_SRW_MASK
+#define I2Cx_S_RAM_MASK                           (0x8U)
+#define I2Cx_S_RAM_SHIFT                          (3U)
+#define I2Cx_S_RAM_SET(x)                         (((uint8_t)(((uint8_t)(x)) << I2Cx_S_RAM_SHIFT)) & I2Cx_S_RAM_MASK)
+#define I2Cx_S_RAM I2Cx_S_RAM_MASK
+#define I2Cx_S_ARBL_MASK                          (0x10U)
+#define I2Cx_S_ARBL_SHIFT                         (4U)
+#define I2Cx_S_ARBL_SET(x)                        (((uint8_t)(((uint8_t)(x)) << I2Cx_S_ARBL_SHIFT)) & I2Cx_S_ARBL_MASK)
+#define I2Cx_S_ARBL I2Cx_S_ARBL_MASK
+#define I2Cx_S_BUSY_MASK                          (0x20U)
+#define I2Cx_S_BUSY_SHIFT                         (5U)
+#define I2Cx_S_BUSY_SET(x)                        (((uint8_t)(((uint8_t)(x)) << I2Cx_S_BUSY_SHIFT)) & I2Cx_S_BUSY_MASK)
+#define I2Cx_S_BUSY I2Cx_S_BUSY_MASK
+#define I2Cx_S_IAAS_MASK                          (0x40U)
+#define I2Cx_S_IAAS_SHIFT                         (6U)
+#define I2Cx_S_IAAS_SET(x)                        (((uint8_t)(((uint8_t)(x)) << I2Cx_S_IAAS_SHIFT)) & I2Cx_S_IAAS_MASK)
+#define I2Cx_S_IAAS I2Cx_S_IAAS_MASK
+#define I2Cx_S_TCF_MASK                           (0x80U)
+#define I2Cx_S_TCF_SHIFT                          (7U)
+#define I2Cx_S_TCF_SET(x)                         (((uint8_t)(((uint8_t)(x)) << I2Cx_S_TCF_SHIFT)) & I2Cx_S_TCF_MASK)
+#define I2Cx_S_TCF I2Cx_S_TCF_MASK
 
 /*! @name D - I2C Data I/O register */
-#define I2C_D_DATA_MASK                          (0xFFU)
-#define I2C_D_DATA_SHIFT                         (0U)
-#define I2C_D_DATA(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
+#define I2Cx_D_DATA_MASK                          (0xFFU)
+#define I2Cx_D_DATA_SHIFT                         (0U)
+#define I2Cx_D_DATA_SET(x)                        (((uint8_t)(((uint8_t)(x)) << I2Cx_D_DATA_SHIFT)) & I2Cx_D_DATA_MASK)
+#define I2Cx_D_DATA I2Cx_D_DATA_MASK
 
 /*! @name C2 - I2C Control Register 2 */
-#define I2C_C2_AD_MASK                           (0x7U)
-#define I2C_C2_AD_SHIFT                          (0U)
-#define I2C_C2_AD(x)                             (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
-#define I2C_C2_RMEN_MASK                         (0x8U)
-#define I2C_C2_RMEN_SHIFT                        (3U)
-#define I2C_C2_RMEN(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
-#define I2C_C2_SBRC_MASK                         (0x10U)
-#define I2C_C2_SBRC_SHIFT                        (4U)
-#define I2C_C2_SBRC(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
-#define I2C_C2_HDRS_MASK                         (0x20U)
-#define I2C_C2_HDRS_SHIFT                        (5U)
-#define I2C_C2_HDRS(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
-#define I2C_C2_ADEXT_MASK                        (0x40U)
-#define I2C_C2_ADEXT_SHIFT                       (6U)
-#define I2C_C2_ADEXT(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
-#define I2C_C2_GCAEN_MASK                        (0x80U)
-#define I2C_C2_GCAEN_SHIFT                       (7U)
-#define I2C_C2_GCAEN(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
+#define I2Cx_C2_AD_MASK                           (0x7U)
+#define I2Cx_C2_AD_SHIFT                          (0U)
+#define I2Cx_C2_AD_SET(x)                         (((uint8_t)(((uint8_t)(x)) << I2Cx_C2_AD_SHIFT)) & I2Cx_C2_AD_MASK)
+#define I2Cx_C2_AD I2Cx_C2_AD_MASK
+#define I2Cx_C2_RMEN_MASK                         (0x8U)
+#define I2Cx_C2_RMEN_SHIFT                        (3U)
+#define I2Cx_C2_RMEN_SET(x)                       (((uint8_t)(((uint8_t)(x)) << I2Cx_C2_RMEN_SHIFT)) & I2Cx_C2_RMEN_MASK)
+#define I2Cx_C2_RMEN I2Cx_C2_RMEN_MASK
+#define I2Cx_C2_SBRC_MASK                         (0x10U)
+#define I2Cx_C2_SBRC_SHIFT                        (4U)
+#define I2Cx_C2_SBRC_SET(x)                       (((uint8_t)(((uint8_t)(x)) << I2Cx_C2_SBRC_SHIFT)) & I2Cx_C2_SBRC_MASK)
+#define I2Cx_C2_SBRC I2Cx_C2_SBRC_MASK
+#define I2Cx_C2_HDRS_MASK                         (0x20U)
+#define I2Cx_C2_HDRS_SHIFT                        (5U)
+#define I2Cx_C2_HDRS_SET(x)                       (((uint8_t)(((uint8_t)(x)) << I2Cx_C2_HDRS_SHIFT)) & I2Cx_C2_HDRS_MASK)
+#define I2Cx_C2_HDRS I2Cx_C2_HDRS_MASK
+#define I2Cx_C2_ADEXT_MASK                        (0x40U)
+#define I2Cx_C2_ADEXT_SHIFT                       (6U)
+#define I2Cx_C2_ADEXT_SET(x)                      (((uint8_t)(((uint8_t)(x)) << I2Cx_C2_ADEXT_SHIFT)) & I2Cx_C2_ADEXT_MASK)
+#define I2Cx_C2_ADEXT I2Cx_C2_ADEXT_MASK
+#define I2Cx_C2_GCAEN_MASK                        (0x80U)
+#define I2Cx_C2_GCAEN_SHIFT                       (7U)
+#define I2Cx_C2_GCAEN_SET(x)                      (((uint8_t)(((uint8_t)(x)) << I2Cx_C2_GCAEN_SHIFT)) & I2Cx_C2_GCAEN_MASK)
+#define I2Cx_C2_GCAEN I2Cx_C2_GCAEN_MASK
 
 /*! @name FLT - I2C Programmable Input Glitch Filter Register */
-#define I2C_FLT_FLT_MASK                         (0xFU)
-#define I2C_FLT_FLT_SHIFT                        (0U)
-#define I2C_FLT_FLT(x)                           (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
-#define I2C_FLT_STARTF_MASK                      (0x10U)
-#define I2C_FLT_STARTF_SHIFT                     (4U)
-#define I2C_FLT_STARTF(x)                        (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
-#define I2C_FLT_SSIE_MASK                        (0x20U)
-#define I2C_FLT_SSIE_SHIFT                       (5U)
-#define I2C_FLT_SSIE(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
-#define I2C_FLT_STOPF_MASK                       (0x40U)
-#define I2C_FLT_STOPF_SHIFT                      (6U)
-#define I2C_FLT_STOPF(x)                         (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
-#define I2C_FLT_SHEN_MASK                        (0x80U)
-#define I2C_FLT_SHEN_SHIFT                       (7U)
-#define I2C_FLT_SHEN(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
+#define I2Cx_FLT_FLT_MASK                         (0xFU)
+#define I2Cx_FLT_FLT_SHIFT                        (0U)
+#define I2Cx_FLT_FLT_SET(x)                       (((uint8_t)(((uint8_t)(x)) << I2Cx_FLT_FLT_SHIFT)) & I2Cx_FLT_FLT_MASK)
+#define I2Cx_FLT_FLT I2Cx_FLT_FLT_MASK
+#define I2Cx_FLT_STARTF_MASK                      (0x10U)
+#define I2Cx_FLT_STARTF_SHIFT                     (4U)
+#define I2Cx_FLT_STARTF_SET(x)                    (((uint8_t)(((uint8_t)(x)) << I2Cx_FLT_STARTF_SHIFT)) & I2Cx_FLT_STARTF_MASK)
+#define I2Cx_FLT_STARTF I2Cx_FLT_STARTF_MASK
+#define I2Cx_FLT_SSIE_MASK                        (0x20U)
+#define I2Cx_FLT_SSIE_SHIFT                       (5U)
+#define I2Cx_FLT_SSIE_SET(x)                      (((uint8_t)(((uint8_t)(x)) << I2Cx_FLT_SSIE_SHIFT)) & I2Cx_FLT_SSIE_MASK)
+#define I2Cx_FLT_SSIE I2Cx_FLT_SSIE_MASK
+#define I2Cx_FLT_STOPF_MASK                       (0x40U)
+#define I2Cx_FLT_STOPF_SHIFT                      (6U)
+#define I2Cx_FLT_STOPF_SET(x)                     (((uint8_t)(((uint8_t)(x)) << I2Cx_FLT_STOPF_SHIFT)) & I2Cx_FLT_STOPF_MASK)
+#define I2Cx_FLT_STOPF I2Cx_FLT_STOPF_MASK
+#define I2Cx_FLT_SHEN_MASK                        (0x80U)
+#define I2Cx_FLT_SHEN_SHIFT                       (7U)
+#define I2Cx_FLT_SHEN_SET(x)                      (((uint8_t)(((uint8_t)(x)) << I2Cx_FLT_SHEN_SHIFT)) & I2Cx_FLT_SHEN_MASK)
+#define I2Cx_FLT_SHEN I2Cx_FLT_SHEN_MASK
 
 /*! @name RA - I2C Range Address register */
-#define I2C_RA_RAD_MASK                          (0xFEU)
-#define I2C_RA_RAD_SHIFT                         (1U)
-#define I2C_RA_RAD(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
+#define I2Cx_RA_RAD_MASK                          (0xFEU)
+#define I2Cx_RA_RAD_SHIFT                         (1U)
+#define I2Cx_RA_RAD_SET(x)                        (((uint8_t)(((uint8_t)(x)) << I2Cx_RA_RAD_SHIFT)) & I2Cx_RA_RAD_MASK)
+#define I2Cx_RA_RAD I2Cx_RA_RAD_MASK
 
 /*! @name SMB - I2C SMBus Control and Status register */
-#define I2C_SMB_SHTF2IE_MASK                     (0x1U)
-#define I2C_SMB_SHTF2IE_SHIFT                    (0U)
-#define I2C_SMB_SHTF2IE(x)                       (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
-#define I2C_SMB_SHTF2_MASK                       (0x2U)
-#define I2C_SMB_SHTF2_SHIFT                      (1U)
-#define I2C_SMB_SHTF2(x)                         (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
-#define I2C_SMB_SHTF1_MASK                       (0x4U)
-#define I2C_SMB_SHTF1_SHIFT                      (2U)
-#define I2C_SMB_SHTF1(x)                         (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
-#define I2C_SMB_SLTF_MASK                        (0x8U)
-#define I2C_SMB_SLTF_SHIFT                       (3U)
-#define I2C_SMB_SLTF(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
-#define I2C_SMB_TCKSEL_MASK                      (0x10U)
-#define I2C_SMB_TCKSEL_SHIFT                     (4U)
-#define I2C_SMB_TCKSEL(x)                        (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
-#define I2C_SMB_SIICAEN_MASK                     (0x20U)
-#define I2C_SMB_SIICAEN_SHIFT                    (5U)
-#define I2C_SMB_SIICAEN(x)                       (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
-#define I2C_SMB_ALERTEN_MASK                     (0x40U)
-#define I2C_SMB_ALERTEN_SHIFT                    (6U)
-#define I2C_SMB_ALERTEN(x)                       (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
-#define I2C_SMB_FACK_MASK                        (0x80U)
-#define I2C_SMB_FACK_SHIFT                       (7U)
-#define I2C_SMB_FACK(x)                          (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
+#define I2Cx_SMB_SHTF2IE_MASK                     (0x1U)
+#define I2Cx_SMB_SHTF2IE_SHIFT                    (0U)
+#define I2Cx_SMB_SHTF2IE_SET(x)                   (((uint8_t)(((uint8_t)(x)) << I2Cx_SMB_SHTF2IE_SHIFT)) & I2Cx_SMB_SHTF2IE_MASK)
+#define I2Cx_SMB_SHTF2IE I2Cx_SMB_SHTF2IE_MASK
+#define I2Cx_SMB_SHTF2_MASK                       (0x2U)
+#define I2Cx_SMB_SHTF2_SHIFT                      (1U)
+#define I2Cx_SMB_SHTF2_SET(x)                     (((uint8_t)(((uint8_t)(x)) << I2Cx_SMB_SHTF2_SHIFT)) & I2Cx_SMB_SHTF2_MASK)
+#define I2Cx_SMB_SHTF2 I2Cx_SMB_SHTF2_MASK
+#define I2Cx_SMB_SHTF1_MASK                       (0x4U)
+#define I2Cx_SMB_SHTF1_SHIFT                      (2U)
+#define I2Cx_SMB_SHTF1_SET(x)                     (((uint8_t)(((uint8_t)(x)) << I2Cx_SMB_SHTF1_SHIFT)) & I2Cx_SMB_SHTF1_MASK)
+#define I2Cx_SMB_SHTF1 I2Cx_SMB_SHTF1_MASK
+#define I2Cx_SMB_SLTF_MASK                        (0x8U)
+#define I2Cx_SMB_SLTF_SHIFT                       (3U)
+#define I2Cx_SMB_SLTF_SET(x)                      (((uint8_t)(((uint8_t)(x)) << I2Cx_SMB_SLTF_SHIFT)) & I2Cx_SMB_SLTF_MASK)
+#define I2Cx_SMB_SLTF I2Cx_SMB_SLTF_MASK
+#define I2Cx_SMB_TCKSEL_MASK                      (0x10U)
+#define I2Cx_SMB_TCKSEL_SHIFT                     (4U)
+#define I2Cx_SMB_TCKSEL_SET(x)                    (((uint8_t)(((uint8_t)(x)) << I2Cx_SMB_TCKSEL_SHIFT)) & I2Cx_SMB_TCKSEL_MASK)
+#define I2Cx_SMB_TCKSEL I2Cx_SMB_TCKSEL_MASK
+#define I2Cx_SMB_SIICAEN_MASK                     (0x20U)
+#define I2Cx_SMB_SIICAEN_SHIFT                    (5U)
+#define I2Cx_SMB_SIICAEN_SET(x)                   (((uint8_t)(((uint8_t)(x)) << I2Cx_SMB_SIICAEN_SHIFT)) & I2Cx_SMB_SIICAEN_MASK)
+#define I2Cx_SMB_SIICAEN I2Cx_SMB_SIICAEN_MASK
+#define I2Cx_SMB_ALERTEN_MASK                     (0x40U)
+#define I2Cx_SMB_ALERTEN_SHIFT                    (6U)
+#define I2Cx_SMB_ALERTEN_SET(x)                   (((uint8_t)(((uint8_t)(x)) << I2Cx_SMB_ALERTEN_SHIFT)) & I2Cx_SMB_ALERTEN_MASK)
+#define I2Cx_SMB_ALERTEN I2Cx_SMB_ALERTEN_MASK
+#define I2Cx_SMB_FACK_MASK                        (0x80U)
+#define I2Cx_SMB_FACK_SHIFT                       (7U)
+#define I2Cx_SMB_FACK_SET(x)                      (((uint8_t)(((uint8_t)(x)) << I2Cx_SMB_FACK_SHIFT)) & I2Cx_SMB_FACK_MASK)
+#define I2Cx_SMB_FACK I2Cx_SMB_FACK_MASK
 
 /*! @name A2 - I2C Address Register 2 */
-#define I2C_A2_SAD_MASK                          (0xFEU)
-#define I2C_A2_SAD_SHIFT                         (1U)
-#define I2C_A2_SAD(x)                            (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
+#define I2Cx_A2_SAD_MASK                          (0xFEU)
+#define I2Cx_A2_SAD_SHIFT                         (1U)
+#define I2Cx_A2_SAD_SET(x)                        (((uint8_t)(((uint8_t)(x)) << I2Cx_A2_SAD_SHIFT)) & I2Cx_A2_SAD_MASK)
+#define I2Cx_A2_SAD I2Cx_A2_SAD_MASK
 
 /*! @name SLTH - I2C SCL Low Timeout Register High */
-#define I2C_SLTH_SSLT_MASK                       (0xFFU)
-#define I2C_SLTH_SSLT_SHIFT                      (0U)
-#define I2C_SLTH_SSLT(x)                         (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
+#define I2Cx_SLTH_SSLT_MASK                       (0xFFU)
+#define I2Cx_SLTH_SSLT_SHIFT                      (0U)
+#define I2Cx_SLTH_SSLT_SET(x)                     (((uint8_t)(((uint8_t)(x)) << I2Cx_SLTH_SSLT_SHIFT)) & I2Cx_SLTH_SSLT_MASK)
+#define I2Cx_SLTH_SSLT I2Cx_SLTH_SSLT_MASK
 
 /*! @name SLTL - I2C SCL Low Timeout Register Low */
-#define I2C_SLTL_SSLT_MASK                       (0xFFU)
-#define I2C_SLTL_SSLT_SHIFT                      (0U)
-#define I2C_SLTL_SSLT(x)                         (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
+#define I2Cx_SLTL_SSLT_MASK                       (0xFFU)
+#define I2Cx_SLTL_SSLT_SHIFT                      (0U)
+#define I2Cx_SLTL_SSLT_SET(x)                     (((uint8_t)(((uint8_t)(x)) << I2Cx_SLTL_SSLT_SHIFT)) & I2Cx_SLTL_SSLT_MASK)
+#define I2Cx_SLTL_SSLT I2Cx_SLTL_SSLT_MASK
 
 
 /*!
  * @}
- */ /* end of group I2C_Register_Masks */
+ */ /* end of group I2Cx_Register_Masks */
 
 
 /* I2C - Peripheral instance base addresses */
 /** Peripheral I2C0 base address */
 #define I2C0_BASE                                (0x40066000u)
 /** Peripheral I2C0 base pointer */
-#define I2C0                                     ((I2C_Type *)I2C0_BASE)
+#define I2C0                                     ((I2C_TypeDef *)I2C0_BASE)
 /** Peripheral I2C1 base address */
 #define I2C1_BASE                                (0x40067000u)
 /** Peripheral I2C1 base pointer */
-#define I2C1                                     ((I2C_Type *)I2C1_BASE)
+#define I2C1                                     ((I2C_TypeDef *)I2C1_BASE)
 /** Peripheral I2C2 base address */
 #define I2C2_BASE                                (0x400E6000u)
 /** Peripheral I2C2 base pointer */
-#define I2C2                                     ((I2C_Type *)I2C2_BASE)
+#define I2C2                                     ((I2C_TypeDef *)I2C2_BASE)
 /** Peripheral I2C3 base address */
 #define I2C3_BASE                                (0x400E7000u)
 /** Peripheral I2C3 base pointer */
-#define I2C3                                     ((I2C_Type *)I2C3_BASE)
+#define I2C3                                     ((I2C_TypeDef *)I2C3_BASE)
 /** Array initializer of I2C peripheral base addresses */
-#define I2C_BASE_ADDRS                           { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE }
+#define I2Cx_BASE_ADDRS                           { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE }
 /** Array initializer of I2C peripheral base pointers */
-#define I2C_BASE_PTRS                            { I2C0, I2C1, I2C2, I2C3 }
+#define I2Cx_BASE_PTRS                            { I2C0, I2C1, I2C2, I2C3 }
 /** Interrupt vectors for the I2C peripheral type */
-#define I2C_IRQS                                 { I2C0_IRQn, I2C1_IRQn, I2C2_IRQn, I2C3_IRQn }
+#define I2Cx_IRQS                                 { I2C0_IRQn, I2C1_IRQn, I2C2_IRQn, I2C3_IRQn }
 
 /*!
  * @}
- */ /* end of group I2C_Peripheral_Access_Layer */
+ */ /* end of group I2Cx_Peripheral_Access_Layer */
 
 
 /* ----------------------------------------------------------------------------
@@ -8042,7 +9770,7 @@ typedef struct {
        uint8_t RESERVED_7[28];
   __IO uint32_t MCR;                               /**< SAI MCLK Control Register, offset: 0x100 */
   __IO uint32_t MDR;                               /**< SAI MCLK Divide Register, offset: 0x104 */
-} I2S_Type;
+} I2S_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- I2S Register Masks
@@ -8056,145 +9784,188 @@ typedef struct {
 /*! @name TCSR - SAI Transmit Control Register */
 #define I2S_TCSR_FRDE_MASK                       (0x1U)
 #define I2S_TCSR_FRDE_SHIFT                      (0U)
-#define I2S_TCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
+#define I2S_TCSR_FRDE_SET(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
+#define I2S_TCSR_FRDE I2S_TCSR_FRDE_MASK
 #define I2S_TCSR_FWDE_MASK                       (0x2U)
 #define I2S_TCSR_FWDE_SHIFT                      (1U)
-#define I2S_TCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
+#define I2S_TCSR_FWDE_SET(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
+#define I2S_TCSR_FWDE I2S_TCSR_FWDE_MASK
 #define I2S_TCSR_FRIE_MASK                       (0x100U)
 #define I2S_TCSR_FRIE_SHIFT                      (8U)
-#define I2S_TCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
+#define I2S_TCSR_FRIE_SET(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
+#define I2S_TCSR_FRIE I2S_TCSR_FRIE_MASK
 #define I2S_TCSR_FWIE_MASK                       (0x200U)
 #define I2S_TCSR_FWIE_SHIFT                      (9U)
-#define I2S_TCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
+#define I2S_TCSR_FWIE_SET(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
+#define I2S_TCSR_FWIE I2S_TCSR_FWIE_MASK
 #define I2S_TCSR_FEIE_MASK                       (0x400U)
 #define I2S_TCSR_FEIE_SHIFT                      (10U)
-#define I2S_TCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
+#define I2S_TCSR_FEIE_SET(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
+#define I2S_TCSR_FEIE I2S_TCSR_FEIE_MASK
 #define I2S_TCSR_SEIE_MASK                       (0x800U)
 #define I2S_TCSR_SEIE_SHIFT                      (11U)
-#define I2S_TCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
+#define I2S_TCSR_SEIE_SET(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
+#define I2S_TCSR_SEIE I2S_TCSR_SEIE_MASK
 #define I2S_TCSR_WSIE_MASK                       (0x1000U)
 #define I2S_TCSR_WSIE_SHIFT                      (12U)
-#define I2S_TCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
+#define I2S_TCSR_WSIE_SET(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
+#define I2S_TCSR_WSIE I2S_TCSR_WSIE_MASK
 #define I2S_TCSR_FRF_MASK                        (0x10000U)
 #define I2S_TCSR_FRF_SHIFT                       (16U)
-#define I2S_TCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
+#define I2S_TCSR_FRF_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
+#define I2S_TCSR_FRF I2S_TCSR_FRF_MASK
 #define I2S_TCSR_FWF_MASK                        (0x20000U)
 #define I2S_TCSR_FWF_SHIFT                       (17U)
-#define I2S_TCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
+#define I2S_TCSR_FWF_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
+#define I2S_TCSR_FWF I2S_TCSR_FWF_MASK
 #define I2S_TCSR_FEF_MASK                        (0x40000U)
 #define I2S_TCSR_FEF_SHIFT                       (18U)
-#define I2S_TCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
+#define I2S_TCSR_FEF_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
+#define I2S_TCSR_FEF I2S_TCSR_FEF_MASK
 #define I2S_TCSR_SEF_MASK                        (0x80000U)
 #define I2S_TCSR_SEF_SHIFT                       (19U)
-#define I2S_TCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
+#define I2S_TCSR_SEF_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
+#define I2S_TCSR_SEF I2S_TCSR_SEF_MASK
 #define I2S_TCSR_WSF_MASK                        (0x100000U)
 #define I2S_TCSR_WSF_SHIFT                       (20U)
-#define I2S_TCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
+#define I2S_TCSR_WSF_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
+#define I2S_TCSR_WSF I2S_TCSR_WSF_MASK
 #define I2S_TCSR_SR_MASK                         (0x1000000U)
 #define I2S_TCSR_SR_SHIFT                        (24U)
-#define I2S_TCSR_SR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
+#define I2S_TCSR_SR_SET(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
+#define I2S_TCSR_SR I2S_TCSR_SR_MASK
 #define I2S_TCSR_FR_MASK                         (0x2000000U)
 #define I2S_TCSR_FR_SHIFT                        (25U)
-#define I2S_TCSR_FR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
+#define I2S_TCSR_FR_SET(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
+#define I2S_TCSR_FR I2S_TCSR_FR_MASK
 #define I2S_TCSR_BCE_MASK                        (0x10000000U)
 #define I2S_TCSR_BCE_SHIFT                       (28U)
-#define I2S_TCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
+#define I2S_TCSR_BCE_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
+#define I2S_TCSR_BCE I2S_TCSR_BCE_MASK
 #define I2S_TCSR_DBGE_MASK                       (0x20000000U)
 #define I2S_TCSR_DBGE_SHIFT                      (29U)
-#define I2S_TCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
+#define I2S_TCSR_DBGE_SET(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
+#define I2S_TCSR_DBGE I2S_TCSR_DBGE_MASK
 #define I2S_TCSR_STOPE_MASK                      (0x40000000U)
 #define I2S_TCSR_STOPE_SHIFT                     (30U)
-#define I2S_TCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
+#define I2S_TCSR_STOPE_SET(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
+#define I2S_TCSR_STOPE I2S_TCSR_STOPE_MASK
 #define I2S_TCSR_TE_MASK                         (0x80000000U)
 #define I2S_TCSR_TE_SHIFT                        (31U)
-#define I2S_TCSR_TE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
+#define I2S_TCSR_TE_SET(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
+#define I2S_TCSR_TE I2S_TCSR_TE_MASK
 
 /*! @name TCR1 - SAI Transmit Configuration 1 Register */
 #define I2S_TCR1_TFW_MASK                        (0x7U)
 #define I2S_TCR1_TFW_SHIFT                       (0U)
-#define I2S_TCR1_TFW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
+#define I2S_TCR1_TFW_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
+#define I2S_TCR1_TFW I2S_TCR1_TFW_MASK
 
 /*! @name TCR2 - SAI Transmit Configuration 2 Register */
 #define I2S_TCR2_DIV_MASK                        (0xFFU)
 #define I2S_TCR2_DIV_SHIFT                       (0U)
-#define I2S_TCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
+#define I2S_TCR2_DIV_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
+#define I2S_TCR2_DIV I2S_TCR2_DIV_MASK
 #define I2S_TCR2_BCD_MASK                        (0x1000000U)
 #define I2S_TCR2_BCD_SHIFT                       (24U)
-#define I2S_TCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
+#define I2S_TCR2_BCD_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
+#define I2S_TCR2_BCD I2S_TCR2_BCD_MASK
 #define I2S_TCR2_BCP_MASK                        (0x2000000U)
 #define I2S_TCR2_BCP_SHIFT                       (25U)
-#define I2S_TCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
+#define I2S_TCR2_BCP_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
+#define I2S_TCR2_BCP I2S_TCR2_BCP_MASK
 #define I2S_TCR2_MSEL_MASK                       (0xC000000U)
 #define I2S_TCR2_MSEL_SHIFT                      (26U)
-#define I2S_TCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
+#define I2S_TCR2_MSEL_SET(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
+#define I2S_TCR2_MSEL I2S_TCR2_MSEL_MASK
 #define I2S_TCR2_BCI_MASK                        (0x10000000U)
 #define I2S_TCR2_BCI_SHIFT                       (28U)
-#define I2S_TCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
+#define I2S_TCR2_BCI_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
+#define I2S_TCR2_BCI I2S_TCR2_BCI_MASK
 #define I2S_TCR2_BCS_MASK                        (0x20000000U)
 #define I2S_TCR2_BCS_SHIFT                       (29U)
-#define I2S_TCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
+#define I2S_TCR2_BCS_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
+#define I2S_TCR2_BCS I2S_TCR2_BCS_MASK
 #define I2S_TCR2_SYNC_MASK                       (0xC0000000U)
 #define I2S_TCR2_SYNC_SHIFT                      (30U)
-#define I2S_TCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
+#define I2S_TCR2_SYNC_SET(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
+#define I2S_TCR2_SYNC I2S_TCR2_SYNC_MASK
 
 /*! @name TCR3 - SAI Transmit Configuration 3 Register */
 #define I2S_TCR3_WDFL_MASK                       (0x1FU)
 #define I2S_TCR3_WDFL_SHIFT                      (0U)
-#define I2S_TCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
+#define I2S_TCR3_WDFL_SET(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
+#define I2S_TCR3_WDFL I2S_TCR3_WDFL_MASK
 #define I2S_TCR3_TCE_MASK                        (0x30000U)
 #define I2S_TCR3_TCE_SHIFT                       (16U)
-#define I2S_TCR3_TCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
+#define I2S_TCR3_TCE_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
+#define I2S_TCR3_TCE I2S_TCR3_TCE_MASK
 #define I2S_TCR3_CFR_MASK                        (0x3000000U)
 #define I2S_TCR3_CFR_SHIFT                       (24U)
-#define I2S_TCR3_CFR(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)
+#define I2S_TCR3_CFR_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)
+#define I2S_TCR3_CFR I2S_TCR3_CFR_MASK
 
 /*! @name TCR4 - SAI Transmit Configuration 4 Register */
 #define I2S_TCR4_FSD_MASK                        (0x1U)
 #define I2S_TCR4_FSD_SHIFT                       (0U)
-#define I2S_TCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
+#define I2S_TCR4_FSD_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
+#define I2S_TCR4_FSD I2S_TCR4_FSD_MASK
 #define I2S_TCR4_FSP_MASK                        (0x2U)
 #define I2S_TCR4_FSP_SHIFT                       (1U)
-#define I2S_TCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
+#define I2S_TCR4_FSP_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
+#define I2S_TCR4_FSP I2S_TCR4_FSP_MASK
 #define I2S_TCR4_ONDEM_MASK                      (0x4U)
 #define I2S_TCR4_ONDEM_SHIFT                     (2U)
-#define I2S_TCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
+#define I2S_TCR4_ONDEM_SET(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
+#define I2S_TCR4_ONDEM I2S_TCR4_ONDEM_MASK
 #define I2S_TCR4_FSE_MASK                        (0x8U)
 #define I2S_TCR4_FSE_SHIFT                       (3U)
-#define I2S_TCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
+#define I2S_TCR4_FSE_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
+#define I2S_TCR4_FSE I2S_TCR4_FSE_MASK
 #define I2S_TCR4_MF_MASK                         (0x10U)
 #define I2S_TCR4_MF_SHIFT                        (4U)
-#define I2S_TCR4_MF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
+#define I2S_TCR4_MF_SET(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
+#define I2S_TCR4_MF I2S_TCR4_MF_MASK
 #define I2S_TCR4_SYWD_MASK                       (0x1F00U)
 #define I2S_TCR4_SYWD_SHIFT                      (8U)
-#define I2S_TCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
+#define I2S_TCR4_SYWD_SET(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
+#define I2S_TCR4_SYWD I2S_TCR4_SYWD_MASK
 #define I2S_TCR4_FRSZ_MASK                       (0x1F0000U)
 #define I2S_TCR4_FRSZ_SHIFT                      (16U)
-#define I2S_TCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
+#define I2S_TCR4_FRSZ_SET(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
+#define I2S_TCR4_FRSZ I2S_TCR4_FRSZ_MASK
 #define I2S_TCR4_FPACK_MASK                      (0x3000000U)
 #define I2S_TCR4_FPACK_SHIFT                     (24U)
-#define I2S_TCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
+#define I2S_TCR4_FPACK_SET(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
+#define I2S_TCR4_FPACK I2S_TCR4_FPACK_MASK
 #define I2S_TCR4_FCOMB_MASK                      (0xC000000U)
 #define I2S_TCR4_FCOMB_SHIFT                     (26U)
-#define I2S_TCR4_FCOMB(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
+#define I2S_TCR4_FCOMB_SET(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
+#define I2S_TCR4_FCOMB I2S_TCR4_FCOMB_MASK
 #define I2S_TCR4_FCONT_MASK                      (0x10000000U)
 #define I2S_TCR4_FCONT_SHIFT                     (28U)
-#define I2S_TCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
+#define I2S_TCR4_FCONT_SET(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
+#define I2S_TCR4_FCONT I2S_TCR4_FCONT_MASK
 
 /*! @name TCR5 - SAI Transmit Configuration 5 Register */
 #define I2S_TCR5_FBT_MASK                        (0x1F00U)
 #define I2S_TCR5_FBT_SHIFT                       (8U)
-#define I2S_TCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
+#define I2S_TCR5_FBT_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
+#define I2S_TCR5_FBT I2S_TCR5_FBT_MASK
 #define I2S_TCR5_W0W_MASK                        (0x1F0000U)
 #define I2S_TCR5_W0W_SHIFT                       (16U)
-#define I2S_TCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
+#define I2S_TCR5_W0W_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
+#define I2S_TCR5_W0W I2S_TCR5_W0W_MASK
 #define I2S_TCR5_WNW_MASK                        (0x1F000000U)
 #define I2S_TCR5_WNW_SHIFT                       (24U)
-#define I2S_TCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
+#define I2S_TCR5_WNW_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
+#define I2S_TCR5_WNW I2S_TCR5_WNW_MASK
 
 /*! @name TDR - SAI Transmit Data Register */
 #define I2S_TDR_TDR_MASK                         (0xFFFFFFFFU)
 #define I2S_TDR_TDR_SHIFT                        (0U)
-#define I2S_TDR_TDR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
+#define I2S_TDR_TDR_SET(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
+#define I2S_TDR_TDR I2S_TDR_TDR_MASK
 
 /* The count of I2S_TDR */
 #define I2S_TDR_COUNT                            (2U)
@@ -8202,13 +9973,16 @@ typedef struct {
 /*! @name TFR - SAI Transmit FIFO Register */
 #define I2S_TFR_RFP_MASK                         (0xFU)
 #define I2S_TFR_RFP_SHIFT                        (0U)
-#define I2S_TFR_RFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
+#define I2S_TFR_RFP_SET(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
+#define I2S_TFR_RFP I2S_TFR_RFP_MASK
 #define I2S_TFR_WFP_MASK                         (0xF0000U)
 #define I2S_TFR_WFP_SHIFT                        (16U)
-#define I2S_TFR_WFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
+#define I2S_TFR_WFP_SET(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
+#define I2S_TFR_WFP I2S_TFR_WFP_MASK
 #define I2S_TFR_WCP_MASK                         (0x80000000U)
 #define I2S_TFR_WCP_SHIFT                        (31U)
-#define I2S_TFR_WCP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
+#define I2S_TFR_WCP_SET(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
+#define I2S_TFR_WCP I2S_TFR_WCP_MASK
 
 /* The count of I2S_TFR */
 #define I2S_TFR_COUNT                            (2U)
@@ -8216,150 +9990,194 @@ typedef struct {
 /*! @name TMR - SAI Transmit Mask Register */
 #define I2S_TMR_TWM_MASK                         (0xFFFFFFFFU)
 #define I2S_TMR_TWM_SHIFT                        (0U)
-#define I2S_TMR_TWM(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
+#define I2S_TMR_TWM_SET(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
+#define I2S_TMR_TWM I2S_TMR_TWM_MASK
 
 /*! @name RCSR - SAI Receive Control Register */
 #define I2S_RCSR_FRDE_MASK                       (0x1U)
 #define I2S_RCSR_FRDE_SHIFT                      (0U)
-#define I2S_RCSR_FRDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
+#define I2S_RCSR_FRDE_SET(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
+#define I2S_RCSR_FRDE I2S_RCSR_FRDE_MASK
 #define I2S_RCSR_FWDE_MASK                       (0x2U)
 #define I2S_RCSR_FWDE_SHIFT                      (1U)
-#define I2S_RCSR_FWDE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
+#define I2S_RCSR_FWDE_SET(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
+#define I2S_RCSR_FWDE I2S_RCSR_FWDE_MASK
 #define I2S_RCSR_FRIE_MASK                       (0x100U)
 #define I2S_RCSR_FRIE_SHIFT                      (8U)
-#define I2S_RCSR_FRIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
+#define I2S_RCSR_FRIE_SET(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
+#define I2S_RCSR_FRIE I2S_RCSR_FRIE_MASK
 #define I2S_RCSR_FWIE_MASK                       (0x200U)
 #define I2S_RCSR_FWIE_SHIFT                      (9U)
-#define I2S_RCSR_FWIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
+#define I2S_RCSR_FWIE_SET(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
+#define I2S_RCSR_FWIE I2S_RCSR_FWIE_MASK
 #define I2S_RCSR_FEIE_MASK                       (0x400U)
 #define I2S_RCSR_FEIE_SHIFT                      (10U)
-#define I2S_RCSR_FEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
+#define I2S_RCSR_FEIE_SET(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
+#define I2S_RCSR_FEIE I2S_RCSR_FEIE_MASK
 #define I2S_RCSR_SEIE_MASK                       (0x800U)
 #define I2S_RCSR_SEIE_SHIFT                      (11U)
-#define I2S_RCSR_SEIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
+#define I2S_RCSR_SEIE_SET(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
+#define I2S_RCSR_SEIE I2S_RCSR_SEIE_MASK
 #define I2S_RCSR_WSIE_MASK                       (0x1000U)
 #define I2S_RCSR_WSIE_SHIFT                      (12U)
-#define I2S_RCSR_WSIE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
+#define I2S_RCSR_WSIE_SET(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
+#define I2S_RCSR_WSIE I2S_RCSR_WSIE_MASK
 #define I2S_RCSR_FRF_MASK                        (0x10000U)
 #define I2S_RCSR_FRF_SHIFT                       (16U)
-#define I2S_RCSR_FRF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
+#define I2S_RCSR_FRF_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
+#define I2S_RCSR_FRF I2S_RCSR_FRF_MASK
 #define I2S_RCSR_FWF_MASK                        (0x20000U)
 #define I2S_RCSR_FWF_SHIFT                       (17U)
-#define I2S_RCSR_FWF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
+#define I2S_RCSR_FWF_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
+#define I2S_RCSR_FWF I2S_RCSR_FWF_MASK
 #define I2S_RCSR_FEF_MASK                        (0x40000U)
 #define I2S_RCSR_FEF_SHIFT                       (18U)
-#define I2S_RCSR_FEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
+#define I2S_RCSR_FEF_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
+#define I2S_RCSR_FEF I2S_RCSR_FEF_MASK
 #define I2S_RCSR_SEF_MASK                        (0x80000U)
 #define I2S_RCSR_SEF_SHIFT                       (19U)
-#define I2S_RCSR_SEF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
+#define I2S_RCSR_SEF_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
+#define I2S_RCSR_SEF I2S_RCSR_SEF_MASK
 #define I2S_RCSR_WSF_MASK                        (0x100000U)
 #define I2S_RCSR_WSF_SHIFT                       (20U)
-#define I2S_RCSR_WSF(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
+#define I2S_RCSR_WSF_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
+#define I2S_RCSR_WSF I2S_RCSR_WSF_MASK
 #define I2S_RCSR_SR_MASK                         (0x1000000U)
 #define I2S_RCSR_SR_SHIFT                        (24U)
-#define I2S_RCSR_SR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
+#define I2S_RCSR_SR_SET(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
+#define I2S_RCSR_SR I2S_RCSR_SR_MASK
 #define I2S_RCSR_FR_MASK                         (0x2000000U)
 #define I2S_RCSR_FR_SHIFT                        (25U)
-#define I2S_RCSR_FR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
+#define I2S_RCSR_FR_SET(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
+#define I2S_RCSR_FR I2S_RCSR_FR_MASK
 #define I2S_RCSR_BCE_MASK                        (0x10000000U)
 #define I2S_RCSR_BCE_SHIFT                       (28U)
-#define I2S_RCSR_BCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
+#define I2S_RCSR_BCE_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
+#define I2S_RCSR_BCE I2S_RCSR_BCE_MASK
 #define I2S_RCSR_DBGE_MASK                       (0x20000000U)
 #define I2S_RCSR_DBGE_SHIFT                      (29U)
-#define I2S_RCSR_DBGE(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
+#define I2S_RCSR_DBGE_SET(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
+#define I2S_RCSR_DBGE I2S_RCSR_DBGE_MASK
 #define I2S_RCSR_STOPE_MASK                      (0x40000000U)
 #define I2S_RCSR_STOPE_SHIFT                     (30U)
-#define I2S_RCSR_STOPE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
+#define I2S_RCSR_STOPE_SET(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
+#define I2S_RCSR_STOPE I2S_RCSR_STOPE_MASK
 #define I2S_RCSR_RE_MASK                         (0x80000000U)
 #define I2S_RCSR_RE_SHIFT                        (31U)
-#define I2S_RCSR_RE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
+#define I2S_RCSR_RE_SET(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
+#define I2S_RCSR_RE I2S_RCSR_RE_MASK
 
 /*! @name RCR1 - SAI Receive Configuration 1 Register */
 #define I2S_RCR1_RFW_MASK                        (0x7U)
 #define I2S_RCR1_RFW_SHIFT                       (0U)
-#define I2S_RCR1_RFW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
+#define I2S_RCR1_RFW_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
+#define I2S_RCR1_RFW I2S_RCR1_RFW_MASK
 
 /*! @name RCR2 - SAI Receive Configuration 2 Register */
 #define I2S_RCR2_DIV_MASK                        (0xFFU)
 #define I2S_RCR2_DIV_SHIFT                       (0U)
-#define I2S_RCR2_DIV(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
+#define I2S_RCR2_DIV_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
+#define I2S_RCR2_DIV I2S_RCR2_DIV_MASK
 #define I2S_RCR2_BCD_MASK                        (0x1000000U)
 #define I2S_RCR2_BCD_SHIFT                       (24U)
-#define I2S_RCR2_BCD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
+#define I2S_RCR2_BCD_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
+#define I2S_RCR2_BCD I2S_RCR2_BCD_MASK
 #define I2S_RCR2_BCP_MASK                        (0x2000000U)
 #define I2S_RCR2_BCP_SHIFT                       (25U)
-#define I2S_RCR2_BCP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
+#define I2S_RCR2_BCP_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
+#define I2S_RCR2_BCP I2S_RCR2_BCP_MASK
 #define I2S_RCR2_MSEL_MASK                       (0xC000000U)
 #define I2S_RCR2_MSEL_SHIFT                      (26U)
-#define I2S_RCR2_MSEL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
+#define I2S_RCR2_MSEL_SET(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
+#define I2S_RCR2_MSEL I2S_RCR2_MSEL_MASK
 #define I2S_RCR2_BCI_MASK                        (0x10000000U)
 #define I2S_RCR2_BCI_SHIFT                       (28U)
-#define I2S_RCR2_BCI(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
+#define I2S_RCR2_BCI_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
+#define I2S_RCR2_BCI I2S_RCR2_BCI_MASK
 #define I2S_RCR2_BCS_MASK                        (0x20000000U)
 #define I2S_RCR2_BCS_SHIFT                       (29U)
-#define I2S_RCR2_BCS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
+#define I2S_RCR2_BCS_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
+#define I2S_RCR2_BCS I2S_RCR2_BCS_MASK
 #define I2S_RCR2_SYNC_MASK                       (0xC0000000U)
 #define I2S_RCR2_SYNC_SHIFT                      (30U)
-#define I2S_RCR2_SYNC(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
+#define I2S_RCR2_SYNC_SET(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
+#define I2S_RCR2_SYNC I2S_RCR2_SYNC_MASK
 
 /*! @name RCR3 - SAI Receive Configuration 3 Register */
 #define I2S_RCR3_WDFL_MASK                       (0x1FU)
 #define I2S_RCR3_WDFL_SHIFT                      (0U)
-#define I2S_RCR3_WDFL(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
+#define I2S_RCR3_WDFL_SET(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
+#define I2S_RCR3_WDFL I2S_RCR3_WDFL_MASK
 #define I2S_RCR3_RCE_MASK                        (0x30000U)
 #define I2S_RCR3_RCE_SHIFT                       (16U)
-#define I2S_RCR3_RCE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
+#define I2S_RCR3_RCE_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
+#define I2S_RCR3_RCE I2S_RCR3_RCE_MASK
 #define I2S_RCR3_CFR_MASK                        (0x3000000U)
 #define I2S_RCR3_CFR_SHIFT                       (24U)
-#define I2S_RCR3_CFR(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)
+#define I2S_RCR3_CFR_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)
+#define I2S_RCR3_CFR I2S_RCR3_CFR_MASK
 
 /*! @name RCR4 - SAI Receive Configuration 4 Register */
 #define I2S_RCR4_FSD_MASK                        (0x1U)
 #define I2S_RCR4_FSD_SHIFT                       (0U)
-#define I2S_RCR4_FSD(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
+#define I2S_RCR4_FSD_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
+#define I2S_RCR4_FSD I2S_RCR4_FSD_MASK
 #define I2S_RCR4_FSP_MASK                        (0x2U)
 #define I2S_RCR4_FSP_SHIFT                       (1U)
-#define I2S_RCR4_FSP(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
+#define I2S_RCR4_FSP_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
+#define I2S_RCR4_FSP I2S_RCR4_FSP_MASK
 #define I2S_RCR4_ONDEM_MASK                      (0x4U)
 #define I2S_RCR4_ONDEM_SHIFT                     (2U)
-#define I2S_RCR4_ONDEM(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
+#define I2S_RCR4_ONDEM_SET(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
+#define I2S_RCR4_ONDEM I2S_RCR4_ONDEM_MASK
 #define I2S_RCR4_FSE_MASK                        (0x8U)
 #define I2S_RCR4_FSE_SHIFT                       (3U)
-#define I2S_RCR4_FSE(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
+#define I2S_RCR4_FSE_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
+#define I2S_RCR4_FSE I2S_RCR4_FSE_MASK
 #define I2S_RCR4_MF_MASK                         (0x10U)
 #define I2S_RCR4_MF_SHIFT                        (4U)
-#define I2S_RCR4_MF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
+#define I2S_RCR4_MF_SET(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
+#define I2S_RCR4_MF I2S_RCR4_MF_MASK
 #define I2S_RCR4_SYWD_MASK                       (0x1F00U)
 #define I2S_RCR4_SYWD_SHIFT                      (8U)
-#define I2S_RCR4_SYWD(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
+#define I2S_RCR4_SYWD_SET(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
+#define I2S_RCR4_SYWD I2S_RCR4_SYWD_MASK
 #define I2S_RCR4_FRSZ_MASK                       (0x1F0000U)
 #define I2S_RCR4_FRSZ_SHIFT                      (16U)
-#define I2S_RCR4_FRSZ(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
+#define I2S_RCR4_FRSZ_SET(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
+#define I2S_RCR4_FRSZ I2S_RCR4_FRSZ_MASK
 #define I2S_RCR4_FPACK_MASK                      (0x3000000U)
 #define I2S_RCR4_FPACK_SHIFT                     (24U)
-#define I2S_RCR4_FPACK(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
+#define I2S_RCR4_FPACK_SET(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
+#define I2S_RCR4_FPACK I2S_RCR4_FPACK_MASK
 #define I2S_RCR4_FCOMB_MASK                      (0xC000000U)
 #define I2S_RCR4_FCOMB_SHIFT                     (26U)
-#define I2S_RCR4_FCOMB(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
+#define I2S_RCR4_FCOMB_SET(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
+#define I2S_RCR4_FCOMB I2S_RCR4_FCOMB_MASK
 #define I2S_RCR4_FCONT_MASK                      (0x10000000U)
 #define I2S_RCR4_FCONT_SHIFT                     (28U)
-#define I2S_RCR4_FCONT(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
+#define I2S_RCR4_FCONT_SET(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
+#define I2S_RCR4_FCONT I2S_RCR4_FCONT_MASK
 
 /*! @name RCR5 - SAI Receive Configuration 5 Register */
 #define I2S_RCR5_FBT_MASK                        (0x1F00U)
 #define I2S_RCR5_FBT_SHIFT                       (8U)
-#define I2S_RCR5_FBT(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
+#define I2S_RCR5_FBT_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
+#define I2S_RCR5_FBT I2S_RCR5_FBT_MASK
 #define I2S_RCR5_W0W_MASK                        (0x1F0000U)
 #define I2S_RCR5_W0W_SHIFT                       (16U)
-#define I2S_RCR5_W0W(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
+#define I2S_RCR5_W0W_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
+#define I2S_RCR5_W0W I2S_RCR5_W0W_MASK
 #define I2S_RCR5_WNW_MASK                        (0x1F000000U)
 #define I2S_RCR5_WNW_SHIFT                       (24U)
-#define I2S_RCR5_WNW(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
+#define I2S_RCR5_WNW_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
+#define I2S_RCR5_WNW I2S_RCR5_WNW_MASK
 
 /*! @name RDR - SAI Receive Data Register */
 #define I2S_RDR_RDR_MASK                         (0xFFFFFFFFU)
 #define I2S_RDR_RDR_SHIFT                        (0U)
-#define I2S_RDR_RDR(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
+#define I2S_RDR_RDR_SET(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
+#define I2S_RDR_RDR I2S_RDR_RDR_MASK
 
 /* The count of I2S_RDR */
 #define I2S_RDR_COUNT                            (2U)
@@ -8367,13 +10185,16 @@ typedef struct {
 /*! @name RFR - SAI Receive FIFO Register */
 #define I2S_RFR_RFP_MASK                         (0xFU)
 #define I2S_RFR_RFP_SHIFT                        (0U)
-#define I2S_RFR_RFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
+#define I2S_RFR_RFP_SET(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
+#define I2S_RFR_RFP I2S_RFR_RFP_MASK
 #define I2S_RFR_RCP_MASK                         (0x8000U)
 #define I2S_RFR_RCP_SHIFT                        (15U)
-#define I2S_RFR_RCP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
+#define I2S_RFR_RCP_SET(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
+#define I2S_RFR_RCP I2S_RFR_RCP_MASK
 #define I2S_RFR_WFP_MASK                         (0xF0000U)
 #define I2S_RFR_WFP_SHIFT                        (16U)
-#define I2S_RFR_WFP(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
+#define I2S_RFR_WFP_SET(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
+#define I2S_RFR_WFP I2S_RFR_WFP_MASK
 
 /* The count of I2S_RFR */
 #define I2S_RFR_COUNT                            (2U)
@@ -8381,26 +10202,32 @@ typedef struct {
 /*! @name RMR - SAI Receive Mask Register */
 #define I2S_RMR_RWM_MASK                         (0xFFFFFFFFU)
 #define I2S_RMR_RWM_SHIFT                        (0U)
-#define I2S_RMR_RWM(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
+#define I2S_RMR_RWM_SET(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
+#define I2S_RMR_RWM I2S_RMR_RWM_MASK
 
 /*! @name MCR - SAI MCLK Control Register */
 #define I2S_MCR_MICS_MASK                        (0x3000000U)
 #define I2S_MCR_MICS_SHIFT                       (24U)
-#define I2S_MCR_MICS(x)                          (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)
+#define I2S_MCR_MICS_SET(x)                      (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)
+#define I2S_MCR_MICS I2S_MCR_MICS_MASK
 #define I2S_MCR_MOE_MASK                         (0x40000000U)
 #define I2S_MCR_MOE_SHIFT                        (30U)
-#define I2S_MCR_MOE(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
+#define I2S_MCR_MOE_SET(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
+#define I2S_MCR_MOE I2S_MCR_MOE_MASK
 #define I2S_MCR_DUF_MASK                         (0x80000000U)
 #define I2S_MCR_DUF_SHIFT                        (31U)
-#define I2S_MCR_DUF(x)                           (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)
+#define I2S_MCR_DUF_SET(x)                       (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)
+#define I2S_MCR_DUF I2S_MCR_DUF_MASK
 
 /*! @name MDR - SAI MCLK Divide Register */
 #define I2S_MDR_DIVIDE_MASK                      (0xFFFU)
 #define I2S_MDR_DIVIDE_SHIFT                     (0U)
-#define I2S_MDR_DIVIDE(x)                        (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK)
+#define I2S_MDR_DIVIDE_SET(x)                    (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK)
+#define I2S_MDR_DIVIDE I2S_MDR_DIVIDE_MASK
 #define I2S_MDR_FRACT_MASK                       (0xFF000U)
 #define I2S_MDR_FRACT_SHIFT                      (12U)
-#define I2S_MDR_FRACT(x)                         (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK)
+#define I2S_MDR_FRACT_SET(x)                     (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK)
+#define I2S_MDR_FRACT I2S_MDR_FRACT_MASK
 
 
 /*!
@@ -8412,7 +10239,7 @@ typedef struct {
 /** Peripheral I2S0 base address */
 #define I2S0_BASE                                (0x4002F000u)
 /** Peripheral I2S0 base pointer */
-#define I2S0                                     ((I2S_Type *)I2S0_BASE)
+#define I2S0                                     ((I2S_TypeDef *)I2S0_BASE)
 /** Array initializer of I2S peripheral base addresses */
 #define I2S_BASE_ADDRS                           { I2S0_BASE }
 /** Array initializer of I2S peripheral base pointers */
@@ -8455,7 +10282,7 @@ typedef struct {
   __IO uint8_t FILT2;                              /**< LLWU Pin Filter 2 register, offset: 0xF */
   __IO uint8_t FILT3;                              /**< LLWU Pin Filter 3 register, offset: 0x10 */
   __IO uint8_t FILT4;                              /**< LLWU Pin Filter 4 register, offset: 0x11 */
-} LLWU_Type;
+} LLWU_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- LLWU Register Masks
@@ -8469,314 +10296,406 @@ typedef struct {
 /*! @name PE1 - LLWU Pin Enable 1 register */
 #define LLWU_PE1_WUPE0_MASK                      (0x3U)
 #define LLWU_PE1_WUPE0_SHIFT                     (0U)
-#define LLWU_PE1_WUPE0(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE0_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
+#define LLWU_PE1_WUPE0 LLWU_PE1_WUPE0_MASK
 #define LLWU_PE1_WUPE1_MASK                      (0xCU)
 #define LLWU_PE1_WUPE1_SHIFT                     (2U)
-#define LLWU_PE1_WUPE1(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE1_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
+#define LLWU_PE1_WUPE1 LLWU_PE1_WUPE1_MASK
 #define LLWU_PE1_WUPE2_MASK                      (0x30U)
 #define LLWU_PE1_WUPE2_SHIFT                     (4U)
-#define LLWU_PE1_WUPE2(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE2_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
+#define LLWU_PE1_WUPE2 LLWU_PE1_WUPE2_MASK
 #define LLWU_PE1_WUPE3_MASK                      (0xC0U)
 #define LLWU_PE1_WUPE3_SHIFT                     (6U)
-#define LLWU_PE1_WUPE3(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
+#define LLWU_PE1_WUPE3_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
+#define LLWU_PE1_WUPE3 LLWU_PE1_WUPE3_MASK
 
 /*! @name PE2 - LLWU Pin Enable 2 register */
 #define LLWU_PE2_WUPE4_MASK                      (0x3U)
 #define LLWU_PE2_WUPE4_SHIFT                     (0U)
-#define LLWU_PE2_WUPE4(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE4_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
+#define LLWU_PE2_WUPE4 LLWU_PE2_WUPE4_MASK
 #define LLWU_PE2_WUPE5_MASK                      (0xCU)
 #define LLWU_PE2_WUPE5_SHIFT                     (2U)
-#define LLWU_PE2_WUPE5(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE5_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
+#define LLWU_PE2_WUPE5 LLWU_PE2_WUPE5_MASK
 #define LLWU_PE2_WUPE6_MASK                      (0x30U)
 #define LLWU_PE2_WUPE6_SHIFT                     (4U)
-#define LLWU_PE2_WUPE6(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE6_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
+#define LLWU_PE2_WUPE6 LLWU_PE2_WUPE6_MASK
 #define LLWU_PE2_WUPE7_MASK                      (0xC0U)
 #define LLWU_PE2_WUPE7_SHIFT                     (6U)
-#define LLWU_PE2_WUPE7(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
+#define LLWU_PE2_WUPE7_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
+#define LLWU_PE2_WUPE7 LLWU_PE2_WUPE7_MASK
 
 /*! @name PE3 - LLWU Pin Enable 3 register */
 #define LLWU_PE3_WUPE8_MASK                      (0x3U)
 #define LLWU_PE3_WUPE8_SHIFT                     (0U)
-#define LLWU_PE3_WUPE8(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE8_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
+#define LLWU_PE3_WUPE8 LLWU_PE3_WUPE8_MASK
 #define LLWU_PE3_WUPE9_MASK                      (0xCU)
 #define LLWU_PE3_WUPE9_SHIFT                     (2U)
-#define LLWU_PE3_WUPE9(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE9_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
+#define LLWU_PE3_WUPE9 LLWU_PE3_WUPE9_MASK
 #define LLWU_PE3_WUPE10_MASK                     (0x30U)
 #define LLWU_PE3_WUPE10_SHIFT                    (4U)
-#define LLWU_PE3_WUPE10(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE10_SET(x)                   (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
+#define LLWU_PE3_WUPE10 LLWU_PE3_WUPE10_MASK
 #define LLWU_PE3_WUPE11_MASK                     (0xC0U)
 #define LLWU_PE3_WUPE11_SHIFT                    (6U)
-#define LLWU_PE3_WUPE11(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
+#define LLWU_PE3_WUPE11_SET(x)                   (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
+#define LLWU_PE3_WUPE11 LLWU_PE3_WUPE11_MASK
 
 /*! @name PE4 - LLWU Pin Enable 4 register */
 #define LLWU_PE4_WUPE12_MASK                     (0x3U)
 #define LLWU_PE4_WUPE12_SHIFT                    (0U)
-#define LLWU_PE4_WUPE12(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE12_SET(x)                   (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
+#define LLWU_PE4_WUPE12 LLWU_PE4_WUPE12_MASK
 #define LLWU_PE4_WUPE13_MASK                     (0xCU)
 #define LLWU_PE4_WUPE13_SHIFT                    (2U)
-#define LLWU_PE4_WUPE13(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE13_SET(x)                   (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
+#define LLWU_PE4_WUPE13 LLWU_PE4_WUPE13_MASK
 #define LLWU_PE4_WUPE14_MASK                     (0x30U)
 #define LLWU_PE4_WUPE14_SHIFT                    (4U)
-#define LLWU_PE4_WUPE14(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE14_SET(x)                   (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
+#define LLWU_PE4_WUPE14 LLWU_PE4_WUPE14_MASK
 #define LLWU_PE4_WUPE15_MASK                     (0xC0U)
 #define LLWU_PE4_WUPE15_SHIFT                    (6U)
-#define LLWU_PE4_WUPE15(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
+#define LLWU_PE4_WUPE15_SET(x)                   (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
+#define LLWU_PE4_WUPE15 LLWU_PE4_WUPE15_MASK
 
 /*! @name PE5 - LLWU Pin Enable 5 register */
 #define LLWU_PE5_WUPE16_MASK                     (0x3U)
 #define LLWU_PE5_WUPE16_SHIFT                    (0U)
-#define LLWU_PE5_WUPE16(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE16_SHIFT)) & LLWU_PE5_WUPE16_MASK)
+#define LLWU_PE5_WUPE16_SET(x)                   (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE16_SHIFT)) & LLWU_PE5_WUPE16_MASK)
+#define LLWU_PE5_WUPE16 LLWU_PE5_WUPE16_MASK
 #define LLWU_PE5_WUPE17_MASK                     (0xCU)
 #define LLWU_PE5_WUPE17_SHIFT                    (2U)
-#define LLWU_PE5_WUPE17(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE17_SHIFT)) & LLWU_PE5_WUPE17_MASK)
+#define LLWU_PE5_WUPE17_SET(x)                   (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE17_SHIFT)) & LLWU_PE5_WUPE17_MASK)
+#define LLWU_PE5_WUPE17 LLWU_PE5_WUPE17_MASK
 #define LLWU_PE5_WUPE18_MASK                     (0x30U)
 #define LLWU_PE5_WUPE18_SHIFT                    (4U)
-#define LLWU_PE5_WUPE18(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE18_SHIFT)) & LLWU_PE5_WUPE18_MASK)
+#define LLWU_PE5_WUPE18_SET(x)                   (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE18_SHIFT)) & LLWU_PE5_WUPE18_MASK)
+#define LLWU_PE5_WUPE18 LLWU_PE5_WUPE18_MASK
 #define LLWU_PE5_WUPE19_MASK                     (0xC0U)
 #define LLWU_PE5_WUPE19_SHIFT                    (6U)
-#define LLWU_PE5_WUPE19(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE19_SHIFT)) & LLWU_PE5_WUPE19_MASK)
+#define LLWU_PE5_WUPE19_SET(x)                   (((uint8_t)(((uint8_t)(x)) << LLWU_PE5_WUPE19_SHIFT)) & LLWU_PE5_WUPE19_MASK)
+#define LLWU_PE5_WUPE19 LLWU_PE5_WUPE19_MASK
 
 /*! @name PE6 - LLWU Pin Enable 6 register */
 #define LLWU_PE6_WUPE20_MASK                     (0x3U)
 #define LLWU_PE6_WUPE20_SHIFT                    (0U)
-#define LLWU_PE6_WUPE20(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE20_SHIFT)) & LLWU_PE6_WUPE20_MASK)
+#define LLWU_PE6_WUPE20_SET(x)                   (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE20_SHIFT)) & LLWU_PE6_WUPE20_MASK)
+#define LLWU_PE6_WUPE20 LLWU_PE6_WUPE20_MASK
 #define LLWU_PE6_WUPE21_MASK                     (0xCU)
 #define LLWU_PE6_WUPE21_SHIFT                    (2U)
-#define LLWU_PE6_WUPE21(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE21_SHIFT)) & LLWU_PE6_WUPE21_MASK)
+#define LLWU_PE6_WUPE21_SET(x)                   (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE21_SHIFT)) & LLWU_PE6_WUPE21_MASK)
+#define LLWU_PE6_WUPE21 LLWU_PE6_WUPE21_MASK
 #define LLWU_PE6_WUPE22_MASK                     (0x30U)
 #define LLWU_PE6_WUPE22_SHIFT                    (4U)
-#define LLWU_PE6_WUPE22(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE22_SHIFT)) & LLWU_PE6_WUPE22_MASK)
+#define LLWU_PE6_WUPE22_SET(x)                   (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE22_SHIFT)) & LLWU_PE6_WUPE22_MASK)
+#define LLWU_PE6_WUPE22 LLWU_PE6_WUPE22_MASK
 #define LLWU_PE6_WUPE23_MASK                     (0xC0U)
 #define LLWU_PE6_WUPE23_SHIFT                    (6U)
-#define LLWU_PE6_WUPE23(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE23_SHIFT)) & LLWU_PE6_WUPE23_MASK)
+#define LLWU_PE6_WUPE23_SET(x)                   (((uint8_t)(((uint8_t)(x)) << LLWU_PE6_WUPE23_SHIFT)) & LLWU_PE6_WUPE23_MASK)
+#define LLWU_PE6_WUPE23 LLWU_PE6_WUPE23_MASK
 
 /*! @name PE7 - LLWU Pin Enable 7 register */
 #define LLWU_PE7_WUPE24_MASK                     (0x3U)
 #define LLWU_PE7_WUPE24_SHIFT                    (0U)
-#define LLWU_PE7_WUPE24(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE24_SHIFT)) & LLWU_PE7_WUPE24_MASK)
+#define LLWU_PE7_WUPE24_SET(x)                   (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE24_SHIFT)) & LLWU_PE7_WUPE24_MASK)
+#define LLWU_PE7_WUPE24 LLWU_PE7_WUPE24_MASK
 #define LLWU_PE7_WUPE25_MASK                     (0xCU)
 #define LLWU_PE7_WUPE25_SHIFT                    (2U)
-#define LLWU_PE7_WUPE25(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE25_SHIFT)) & LLWU_PE7_WUPE25_MASK)
+#define LLWU_PE7_WUPE25_SET(x)                   (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE25_SHIFT)) & LLWU_PE7_WUPE25_MASK)
+#define LLWU_PE7_WUPE25 LLWU_PE7_WUPE25_MASK
 #define LLWU_PE7_WUPE26_MASK                     (0x30U)
 #define LLWU_PE7_WUPE26_SHIFT                    (4U)
-#define LLWU_PE7_WUPE26(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE26_SHIFT)) & LLWU_PE7_WUPE26_MASK)
+#define LLWU_PE7_WUPE26_SET(x)                   (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE26_SHIFT)) & LLWU_PE7_WUPE26_MASK)
+#define LLWU_PE7_WUPE26 LLWU_PE7_WUPE26_MASK
 #define LLWU_PE7_WUPE27_MASK                     (0xC0U)
 #define LLWU_PE7_WUPE27_SHIFT                    (6U)
-#define LLWU_PE7_WUPE27(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE27_SHIFT)) & LLWU_PE7_WUPE27_MASK)
+#define LLWU_PE7_WUPE27_SET(x)                   (((uint8_t)(((uint8_t)(x)) << LLWU_PE7_WUPE27_SHIFT)) & LLWU_PE7_WUPE27_MASK)
+#define LLWU_PE7_WUPE27 LLWU_PE7_WUPE27_MASK
 
 /*! @name PE8 - LLWU Pin Enable 8 register */
 #define LLWU_PE8_WUPE28_MASK                     (0x3U)
 #define LLWU_PE8_WUPE28_SHIFT                    (0U)
-#define LLWU_PE8_WUPE28(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE28_SHIFT)) & LLWU_PE8_WUPE28_MASK)
+#define LLWU_PE8_WUPE28_SET(x)                   (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE28_SHIFT)) & LLWU_PE8_WUPE28_MASK)
+#define LLWU_PE8_WUPE28 LLWU_PE8_WUPE28_MASK
 #define LLWU_PE8_WUPE29_MASK                     (0xCU)
 #define LLWU_PE8_WUPE29_SHIFT                    (2U)
-#define LLWU_PE8_WUPE29(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE29_SHIFT)) & LLWU_PE8_WUPE29_MASK)
+#define LLWU_PE8_WUPE29_SET(x)                   (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE29_SHIFT)) & LLWU_PE8_WUPE29_MASK)
+#define LLWU_PE8_WUPE29 LLWU_PE8_WUPE29_MASK
 #define LLWU_PE8_WUPE30_MASK                     (0x30U)
 #define LLWU_PE8_WUPE30_SHIFT                    (4U)
-#define LLWU_PE8_WUPE30(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE30_SHIFT)) & LLWU_PE8_WUPE30_MASK)
+#define LLWU_PE8_WUPE30_SET(x)                   (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE30_SHIFT)) & LLWU_PE8_WUPE30_MASK)
+#define LLWU_PE8_WUPE30 LLWU_PE8_WUPE30_MASK
 #define LLWU_PE8_WUPE31_MASK                     (0xC0U)
 #define LLWU_PE8_WUPE31_SHIFT                    (6U)
-#define LLWU_PE8_WUPE31(x)                       (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE31_SHIFT)) & LLWU_PE8_WUPE31_MASK)
+#define LLWU_PE8_WUPE31_SET(x)                   (((uint8_t)(((uint8_t)(x)) << LLWU_PE8_WUPE31_SHIFT)) & LLWU_PE8_WUPE31_MASK)
+#define LLWU_PE8_WUPE31 LLWU_PE8_WUPE31_MASK
 
 /*! @name ME - LLWU Module Enable register */
 #define LLWU_ME_WUME0_MASK                       (0x1U)
 #define LLWU_ME_WUME0_SHIFT                      (0U)
-#define LLWU_ME_WUME0(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
+#define LLWU_ME_WUME0_SET(x)                     (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
+#define LLWU_ME_WUME0 LLWU_ME_WUME0_MASK
 #define LLWU_ME_WUME1_MASK                       (0x2U)
 #define LLWU_ME_WUME1_SHIFT                      (1U)
-#define LLWU_ME_WUME1(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
+#define LLWU_ME_WUME1_SET(x)                     (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
+#define LLWU_ME_WUME1 LLWU_ME_WUME1_MASK
 #define LLWU_ME_WUME2_MASK                       (0x4U)
 #define LLWU_ME_WUME2_SHIFT                      (2U)
-#define LLWU_ME_WUME2(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
+#define LLWU_ME_WUME2_SET(x)                     (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
+#define LLWU_ME_WUME2 LLWU_ME_WUME2_MASK
 #define LLWU_ME_WUME3_MASK                       (0x8U)
 #define LLWU_ME_WUME3_SHIFT                      (3U)
-#define LLWU_ME_WUME3(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
+#define LLWU_ME_WUME3_SET(x)                     (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
+#define LLWU_ME_WUME3 LLWU_ME_WUME3_MASK
 #define LLWU_ME_WUME4_MASK                       (0x10U)
 #define LLWU_ME_WUME4_SHIFT                      (4U)
-#define LLWU_ME_WUME4(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
+#define LLWU_ME_WUME4_SET(x)                     (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
+#define LLWU_ME_WUME4 LLWU_ME_WUME4_MASK
 #define LLWU_ME_WUME5_MASK                       (0x20U)
 #define LLWU_ME_WUME5_SHIFT                      (5U)
-#define LLWU_ME_WUME5(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
+#define LLWU_ME_WUME5_SET(x)                     (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
+#define LLWU_ME_WUME5 LLWU_ME_WUME5_MASK
 #define LLWU_ME_WUME6_MASK                       (0x40U)
 #define LLWU_ME_WUME6_SHIFT                      (6U)
-#define LLWU_ME_WUME6(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
+#define LLWU_ME_WUME6_SET(x)                     (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
+#define LLWU_ME_WUME6 LLWU_ME_WUME6_MASK
 #define LLWU_ME_WUME7_MASK                       (0x80U)
 #define LLWU_ME_WUME7_SHIFT                      (7U)
-#define LLWU_ME_WUME7(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
+#define LLWU_ME_WUME7_SET(x)                     (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
+#define LLWU_ME_WUME7 LLWU_ME_WUME7_MASK
 
 /*! @name PF1 - LLWU Pin Flag 1 register */
 #define LLWU_PF1_WUF0_MASK                       (0x1U)
 #define LLWU_PF1_WUF0_SHIFT                      (0U)
-#define LLWU_PF1_WUF0(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF0_SHIFT)) & LLWU_PF1_WUF0_MASK)
+#define LLWU_PF1_WUF0_SET(x)                     (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF0_SHIFT)) & LLWU_PF1_WUF0_MASK)
+#define LLWU_PF1_WUF0 LLWU_PF1_WUF0_MASK
 #define LLWU_PF1_WUF1_MASK                       (0x2U)
 #define LLWU_PF1_WUF1_SHIFT                      (1U)
-#define LLWU_PF1_WUF1(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF1_SHIFT)) & LLWU_PF1_WUF1_MASK)
+#define LLWU_PF1_WUF1_SET(x)                     (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF1_SHIFT)) & LLWU_PF1_WUF1_MASK)
+#define LLWU_PF1_WUF1 LLWU_PF1_WUF1_MASK
 #define LLWU_PF1_WUF2_MASK                       (0x4U)
 #define LLWU_PF1_WUF2_SHIFT                      (2U)
-#define LLWU_PF1_WUF2(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF2_SHIFT)) & LLWU_PF1_WUF2_MASK)
+#define LLWU_PF1_WUF2_SET(x)                     (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF2_SHIFT)) & LLWU_PF1_WUF2_MASK)
+#define LLWU_PF1_WUF2 LLWU_PF1_WUF2_MASK
 #define LLWU_PF1_WUF3_MASK                       (0x8U)
 #define LLWU_PF1_WUF3_SHIFT                      (3U)
-#define LLWU_PF1_WUF3(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF3_SHIFT)) & LLWU_PF1_WUF3_MASK)
+#define LLWU_PF1_WUF3_SET(x)                     (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF3_SHIFT)) & LLWU_PF1_WUF3_MASK)
+#define LLWU_PF1_WUF3 LLWU_PF1_WUF3_MASK
 #define LLWU_PF1_WUF4_MASK                       (0x10U)
 #define LLWU_PF1_WUF4_SHIFT                      (4U)
-#define LLWU_PF1_WUF4(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF4_SHIFT)) & LLWU_PF1_WUF4_MASK)
+#define LLWU_PF1_WUF4_SET(x)                     (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF4_SHIFT)) & LLWU_PF1_WUF4_MASK)
+#define LLWU_PF1_WUF4 LLWU_PF1_WUF4_MASK
 #define LLWU_PF1_WUF5_MASK                       (0x20U)
 #define LLWU_PF1_WUF5_SHIFT                      (5U)
-#define LLWU_PF1_WUF5(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF5_SHIFT)) & LLWU_PF1_WUF5_MASK)
+#define LLWU_PF1_WUF5_SET(x)                     (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF5_SHIFT)) & LLWU_PF1_WUF5_MASK)
+#define LLWU_PF1_WUF5 LLWU_PF1_WUF5_MASK
 #define LLWU_PF1_WUF6_MASK                       (0x40U)
 #define LLWU_PF1_WUF6_SHIFT                      (6U)
-#define LLWU_PF1_WUF6(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF6_SHIFT)) & LLWU_PF1_WUF6_MASK)
+#define LLWU_PF1_WUF6_SET(x)                     (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF6_SHIFT)) & LLWU_PF1_WUF6_MASK)
+#define LLWU_PF1_WUF6 LLWU_PF1_WUF6_MASK
 #define LLWU_PF1_WUF7_MASK                       (0x80U)
 #define LLWU_PF1_WUF7_SHIFT                      (7U)
-#define LLWU_PF1_WUF7(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF7_SHIFT)) & LLWU_PF1_WUF7_MASK)
+#define LLWU_PF1_WUF7_SET(x)                     (((uint8_t)(((uint8_t)(x)) << LLWU_PF1_WUF7_SHIFT)) & LLWU_PF1_WUF7_MASK)
+#define LLWU_PF1_WUF7 LLWU_PF1_WUF7_MASK
 
 /*! @name PF2 - LLWU Pin Flag 2 register */
 #define LLWU_PF2_WUF8_MASK                       (0x1U)
 #define LLWU_PF2_WUF8_SHIFT                      (0U)
-#define LLWU_PF2_WUF8(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF8_SHIFT)) & LLWU_PF2_WUF8_MASK)
+#define LLWU_PF2_WUF8_SET(x)                     (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF8_SHIFT)) & LLWU_PF2_WUF8_MASK)
+#define LLWU_PF2_WUF8 LLWU_PF2_WUF8_MASK
 #define LLWU_PF2_WUF9_MASK                       (0x2U)
 #define LLWU_PF2_WUF9_SHIFT                      (1U)
-#define LLWU_PF2_WUF9(x)                         (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF9_SHIFT)) & LLWU_PF2_WUF9_MASK)
+#define LLWU_PF2_WUF9_SET(x)                     (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF9_SHIFT)) & LLWU_PF2_WUF9_MASK)
+#define LLWU_PF2_WUF9 LLWU_PF2_WUF9_MASK
 #define LLWU_PF2_WUF10_MASK                      (0x4U)
 #define LLWU_PF2_WUF10_SHIFT                     (2U)
-#define LLWU_PF2_WUF10(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF10_SHIFT)) & LLWU_PF2_WUF10_MASK)
+#define LLWU_PF2_WUF10_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF10_SHIFT)) & LLWU_PF2_WUF10_MASK)
+#define LLWU_PF2_WUF10 LLWU_PF2_WUF10_MASK
 #define LLWU_PF2_WUF11_MASK                      (0x8U)
 #define LLWU_PF2_WUF11_SHIFT                     (3U)
-#define LLWU_PF2_WUF11(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF11_SHIFT)) & LLWU_PF2_WUF11_MASK)
+#define LLWU_PF2_WUF11_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF11_SHIFT)) & LLWU_PF2_WUF11_MASK)
+#define LLWU_PF2_WUF11 LLWU_PF2_WUF11_MASK
 #define LLWU_PF2_WUF12_MASK                      (0x10U)
 #define LLWU_PF2_WUF12_SHIFT                     (4U)
-#define LLWU_PF2_WUF12(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF12_SHIFT)) & LLWU_PF2_WUF12_MASK)
+#define LLWU_PF2_WUF12_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF12_SHIFT)) & LLWU_PF2_WUF12_MASK)
+#define LLWU_PF2_WUF12 LLWU_PF2_WUF12_MASK
 #define LLWU_PF2_WUF13_MASK                      (0x20U)
 #define LLWU_PF2_WUF13_SHIFT                     (5U)
-#define LLWU_PF2_WUF13(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF13_SHIFT)) & LLWU_PF2_WUF13_MASK)
+#define LLWU_PF2_WUF13_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF13_SHIFT)) & LLWU_PF2_WUF13_MASK)
+#define LLWU_PF2_WUF13 LLWU_PF2_WUF13_MASK
 #define LLWU_PF2_WUF14_MASK                      (0x40U)
 #define LLWU_PF2_WUF14_SHIFT                     (6U)
-#define LLWU_PF2_WUF14(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF14_SHIFT)) & LLWU_PF2_WUF14_MASK)
+#define LLWU_PF2_WUF14_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF14_SHIFT)) & LLWU_PF2_WUF14_MASK)
+#define LLWU_PF2_WUF14 LLWU_PF2_WUF14_MASK
 #define LLWU_PF2_WUF15_MASK                      (0x80U)
 #define LLWU_PF2_WUF15_SHIFT                     (7U)
-#define LLWU_PF2_WUF15(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF15_SHIFT)) & LLWU_PF2_WUF15_MASK)
+#define LLWU_PF2_WUF15_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_PF2_WUF15_SHIFT)) & LLWU_PF2_WUF15_MASK)
+#define LLWU_PF2_WUF15 LLWU_PF2_WUF15_MASK
 
 /*! @name PF3 - LLWU Pin Flag 3 register */
 #define LLWU_PF3_WUF16_MASK                      (0x1U)
 #define LLWU_PF3_WUF16_SHIFT                     (0U)
-#define LLWU_PF3_WUF16(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF16_SHIFT)) & LLWU_PF3_WUF16_MASK)
+#define LLWU_PF3_WUF16_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF16_SHIFT)) & LLWU_PF3_WUF16_MASK)
+#define LLWU_PF3_WUF16 LLWU_PF3_WUF16_MASK
 #define LLWU_PF3_WUF17_MASK                      (0x2U)
 #define LLWU_PF3_WUF17_SHIFT                     (1U)
-#define LLWU_PF3_WUF17(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF17_SHIFT)) & LLWU_PF3_WUF17_MASK)
+#define LLWU_PF3_WUF17_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF17_SHIFT)) & LLWU_PF3_WUF17_MASK)
+#define LLWU_PF3_WUF17 LLWU_PF3_WUF17_MASK
 #define LLWU_PF3_WUF18_MASK                      (0x4U)
 #define LLWU_PF3_WUF18_SHIFT                     (2U)
-#define LLWU_PF3_WUF18(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF18_SHIFT)) & LLWU_PF3_WUF18_MASK)
+#define LLWU_PF3_WUF18_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF18_SHIFT)) & LLWU_PF3_WUF18_MASK)
+#define LLWU_PF3_WUF18 LLWU_PF3_WUF18_MASK
 #define LLWU_PF3_WUF19_MASK                      (0x8U)
 #define LLWU_PF3_WUF19_SHIFT                     (3U)
-#define LLWU_PF3_WUF19(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF19_SHIFT)) & LLWU_PF3_WUF19_MASK)
+#define LLWU_PF3_WUF19_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF19_SHIFT)) & LLWU_PF3_WUF19_MASK)
+#define LLWU_PF3_WUF19 LLWU_PF3_WUF19_MASK
 #define LLWU_PF3_WUF20_MASK                      (0x10U)
 #define LLWU_PF3_WUF20_SHIFT                     (4U)
-#define LLWU_PF3_WUF20(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF20_SHIFT)) & LLWU_PF3_WUF20_MASK)
+#define LLWU_PF3_WUF20_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF20_SHIFT)) & LLWU_PF3_WUF20_MASK)
+#define LLWU_PF3_WUF20 LLWU_PF3_WUF20_MASK
 #define LLWU_PF3_WUF21_MASK                      (0x20U)
 #define LLWU_PF3_WUF21_SHIFT                     (5U)
-#define LLWU_PF3_WUF21(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF21_SHIFT)) & LLWU_PF3_WUF21_MASK)
+#define LLWU_PF3_WUF21_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF21_SHIFT)) & LLWU_PF3_WUF21_MASK)
+#define LLWU_PF3_WUF21 LLWU_PF3_WUF21_MASK
 #define LLWU_PF3_WUF22_MASK                      (0x40U)
 #define LLWU_PF3_WUF22_SHIFT                     (6U)
-#define LLWU_PF3_WUF22(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF22_SHIFT)) & LLWU_PF3_WUF22_MASK)
+#define LLWU_PF3_WUF22_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF22_SHIFT)) & LLWU_PF3_WUF22_MASK)
+#define LLWU_PF3_WUF22 LLWU_PF3_WUF22_MASK
 #define LLWU_PF3_WUF23_MASK                      (0x80U)
 #define LLWU_PF3_WUF23_SHIFT                     (7U)
-#define LLWU_PF3_WUF23(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF23_SHIFT)) & LLWU_PF3_WUF23_MASK)
+#define LLWU_PF3_WUF23_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_PF3_WUF23_SHIFT)) & LLWU_PF3_WUF23_MASK)
+#define LLWU_PF3_WUF23 LLWU_PF3_WUF23_MASK
 
 /*! @name PF4 - LLWU Pin Flag 4 register */
 #define LLWU_PF4_WUF24_MASK                      (0x1U)
 #define LLWU_PF4_WUF24_SHIFT                     (0U)
-#define LLWU_PF4_WUF24(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF24_SHIFT)) & LLWU_PF4_WUF24_MASK)
+#define LLWU_PF4_WUF24_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF24_SHIFT)) & LLWU_PF4_WUF24_MASK)
+#define LLWU_PF4_WUF24 LLWU_PF4_WUF24_MASK
 #define LLWU_PF4_WUF25_MASK                      (0x2U)
 #define LLWU_PF4_WUF25_SHIFT                     (1U)
-#define LLWU_PF4_WUF25(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF25_SHIFT)) & LLWU_PF4_WUF25_MASK)
+#define LLWU_PF4_WUF25_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF25_SHIFT)) & LLWU_PF4_WUF25_MASK)
+#define LLWU_PF4_WUF25 LLWU_PF4_WUF25_MASK
 #define LLWU_PF4_WUF26_MASK                      (0x4U)
 #define LLWU_PF4_WUF26_SHIFT                     (2U)
-#define LLWU_PF4_WUF26(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF26_SHIFT)) & LLWU_PF4_WUF26_MASK)
+#define LLWU_PF4_WUF26_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF26_SHIFT)) & LLWU_PF4_WUF26_MASK)
+#define LLWU_PF4_WUF26 LLWU_PF4_WUF26_MASK
 #define LLWU_PF4_WUF27_MASK                      (0x8U)
 #define LLWU_PF4_WUF27_SHIFT                     (3U)
-#define LLWU_PF4_WUF27(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF27_SHIFT)) & LLWU_PF4_WUF27_MASK)
+#define LLWU_PF4_WUF27_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF27_SHIFT)) & LLWU_PF4_WUF27_MASK)
+#define LLWU_PF4_WUF27 LLWU_PF4_WUF27_MASK
 #define LLWU_PF4_WUF28_MASK                      (0x10U)
 #define LLWU_PF4_WUF28_SHIFT                     (4U)
-#define LLWU_PF4_WUF28(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF28_SHIFT)) & LLWU_PF4_WUF28_MASK)
+#define LLWU_PF4_WUF28_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF28_SHIFT)) & LLWU_PF4_WUF28_MASK)
+#define LLWU_PF4_WUF28 LLWU_PF4_WUF28_MASK
 #define LLWU_PF4_WUF29_MASK                      (0x20U)
 #define LLWU_PF4_WUF29_SHIFT                     (5U)
-#define LLWU_PF4_WUF29(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF29_SHIFT)) & LLWU_PF4_WUF29_MASK)
+#define LLWU_PF4_WUF29_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF29_SHIFT)) & LLWU_PF4_WUF29_MASK)
+#define LLWU_PF4_WUF29 LLWU_PF4_WUF29_MASK
 #define LLWU_PF4_WUF30_MASK                      (0x40U)
 #define LLWU_PF4_WUF30_SHIFT                     (6U)
-#define LLWU_PF4_WUF30(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF30_SHIFT)) & LLWU_PF4_WUF30_MASK)
+#define LLWU_PF4_WUF30_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF30_SHIFT)) & LLWU_PF4_WUF30_MASK)
+#define LLWU_PF4_WUF30 LLWU_PF4_WUF30_MASK
 #define LLWU_PF4_WUF31_MASK                      (0x80U)
 #define LLWU_PF4_WUF31_SHIFT                     (7U)
-#define LLWU_PF4_WUF31(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF31_SHIFT)) & LLWU_PF4_WUF31_MASK)
+#define LLWU_PF4_WUF31_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_PF4_WUF31_SHIFT)) & LLWU_PF4_WUF31_MASK)
+#define LLWU_PF4_WUF31 LLWU_PF4_WUF31_MASK
 
 /*! @name MF5 - LLWU Module Flag 5 register */
 #define LLWU_MF5_MWUF0_MASK                      (0x1U)
 #define LLWU_MF5_MWUF0_SHIFT                     (0U)
-#define LLWU_MF5_MWUF0(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF0_SHIFT)) & LLWU_MF5_MWUF0_MASK)
+#define LLWU_MF5_MWUF0_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF0_SHIFT)) & LLWU_MF5_MWUF0_MASK)
+#define LLWU_MF5_MWUF0 LLWU_MF5_MWUF0_MASK
 #define LLWU_MF5_MWUF1_MASK                      (0x2U)
 #define LLWU_MF5_MWUF1_SHIFT                     (1U)
-#define LLWU_MF5_MWUF1(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF1_SHIFT)) & LLWU_MF5_MWUF1_MASK)
+#define LLWU_MF5_MWUF1_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF1_SHIFT)) & LLWU_MF5_MWUF1_MASK)
+#define LLWU_MF5_MWUF1 LLWU_MF5_MWUF1_MASK
 #define LLWU_MF5_MWUF2_MASK                      (0x4U)
 #define LLWU_MF5_MWUF2_SHIFT                     (2U)
-#define LLWU_MF5_MWUF2(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF2_SHIFT)) & LLWU_MF5_MWUF2_MASK)
+#define LLWU_MF5_MWUF2_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF2_SHIFT)) & LLWU_MF5_MWUF2_MASK)
+#define LLWU_MF5_MWUF2 LLWU_MF5_MWUF2_MASK
 #define LLWU_MF5_MWUF3_MASK                      (0x8U)
 #define LLWU_MF5_MWUF3_SHIFT                     (3U)
-#define LLWU_MF5_MWUF3(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF3_SHIFT)) & LLWU_MF5_MWUF3_MASK)
+#define LLWU_MF5_MWUF3_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF3_SHIFT)) & LLWU_MF5_MWUF3_MASK)
+#define LLWU_MF5_MWUF3 LLWU_MF5_MWUF3_MASK
 #define LLWU_MF5_MWUF4_MASK                      (0x10U)
 #define LLWU_MF5_MWUF4_SHIFT                     (4U)
-#define LLWU_MF5_MWUF4(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF4_SHIFT)) & LLWU_MF5_MWUF4_MASK)
+#define LLWU_MF5_MWUF4_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF4_SHIFT)) & LLWU_MF5_MWUF4_MASK)
+#define LLWU_MF5_MWUF4 LLWU_MF5_MWUF4_MASK
 #define LLWU_MF5_MWUF5_MASK                      (0x20U)
 #define LLWU_MF5_MWUF5_SHIFT                     (5U)
-#define LLWU_MF5_MWUF5(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF5_SHIFT)) & LLWU_MF5_MWUF5_MASK)
+#define LLWU_MF5_MWUF5_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF5_SHIFT)) & LLWU_MF5_MWUF5_MASK)
+#define LLWU_MF5_MWUF5 LLWU_MF5_MWUF5_MASK
 #define LLWU_MF5_MWUF6_MASK                      (0x40U)
 #define LLWU_MF5_MWUF6_SHIFT                     (6U)
-#define LLWU_MF5_MWUF6(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF6_SHIFT)) & LLWU_MF5_MWUF6_MASK)
+#define LLWU_MF5_MWUF6_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF6_SHIFT)) & LLWU_MF5_MWUF6_MASK)
+#define LLWU_MF5_MWUF6 LLWU_MF5_MWUF6_MASK
 #define LLWU_MF5_MWUF7_MASK                      (0x80U)
 #define LLWU_MF5_MWUF7_SHIFT                     (7U)
-#define LLWU_MF5_MWUF7(x)                        (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF7_SHIFT)) & LLWU_MF5_MWUF7_MASK)
+#define LLWU_MF5_MWUF7_SET(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_MF5_MWUF7_SHIFT)) & LLWU_MF5_MWUF7_MASK)
+#define LLWU_MF5_MWUF7 LLWU_MF5_MWUF7_MASK
 
 /*! @name FILT1 - LLWU Pin Filter 1 register */
 #define LLWU_FILT1_FILTSEL_MASK                  (0x1FU)
 #define LLWU_FILT1_FILTSEL_SHIFT                 (0U)
-#define LLWU_FILT1_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTSEL_SET(x)                (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
+#define LLWU_FILT1_FILTSEL LLWU_FILT1_FILTSEL_MASK
 #define LLWU_FILT1_FILTE_MASK                    (0x60U)
 #define LLWU_FILT1_FILTE_SHIFT                   (5U)
-#define LLWU_FILT1_FILTE(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTE_SET(x)                  (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
+#define LLWU_FILT1_FILTE LLWU_FILT1_FILTE_MASK
 #define LLWU_FILT1_FILTF_MASK                    (0x80U)
 #define LLWU_FILT1_FILTF_SHIFT                   (7U)
-#define LLWU_FILT1_FILTF(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
+#define LLWU_FILT1_FILTF_SET(x)                  (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
+#define LLWU_FILT1_FILTF LLWU_FILT1_FILTF_MASK
 
 /*! @name FILT2 - LLWU Pin Filter 2 register */
 #define LLWU_FILT2_FILTSEL_MASK                  (0x1FU)
 #define LLWU_FILT2_FILTSEL_SHIFT                 (0U)
-#define LLWU_FILT2_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTSEL_SET(x)                (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
+#define LLWU_FILT2_FILTSEL LLWU_FILT2_FILTSEL_MASK
 #define LLWU_FILT2_FILTE_MASK                    (0x60U)
 #define LLWU_FILT2_FILTE_SHIFT                   (5U)
-#define LLWU_FILT2_FILTE(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTE_SET(x)                  (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
+#define LLWU_FILT2_FILTE LLWU_FILT2_FILTE_MASK
 #define LLWU_FILT2_FILTF_MASK                    (0x80U)
 #define LLWU_FILT2_FILTF_SHIFT                   (7U)
-#define LLWU_FILT2_FILTF(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
+#define LLWU_FILT2_FILTF_SET(x)                  (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
+#define LLWU_FILT2_FILTF LLWU_FILT2_FILTF_MASK
 
 /*! @name FILT3 - LLWU Pin Filter 3 register */
 #define LLWU_FILT3_FILTSEL_MASK                  (0x1FU)
 #define LLWU_FILT3_FILTSEL_SHIFT                 (0U)
-#define LLWU_FILT3_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTSEL_SHIFT)) & LLWU_FILT3_FILTSEL_MASK)
+#define LLWU_FILT3_FILTSEL_SET(x)                (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTSEL_SHIFT)) & LLWU_FILT3_FILTSEL_MASK)
+#define LLWU_FILT3_FILTSEL LLWU_FILT3_FILTSEL_MASK
 #define LLWU_FILT3_FILTE_MASK                    (0x60U)
 #define LLWU_FILT3_FILTE_SHIFT                   (5U)
-#define LLWU_FILT3_FILTE(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTE_SHIFT)) & LLWU_FILT3_FILTE_MASK)
+#define LLWU_FILT3_FILTE_SET(x)                  (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTE_SHIFT)) & LLWU_FILT3_FILTE_MASK)
+#define LLWU_FILT3_FILTE LLWU_FILT3_FILTE_MASK
 #define LLWU_FILT3_FILTF_MASK                    (0x80U)
 #define LLWU_FILT3_FILTF_SHIFT                   (7U)
-#define LLWU_FILT3_FILTF(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTF_SHIFT)) & LLWU_FILT3_FILTF_MASK)
+#define LLWU_FILT3_FILTF_SET(x)                  (((uint8_t)(((uint8_t)(x)) << LLWU_FILT3_FILTF_SHIFT)) & LLWU_FILT3_FILTF_MASK)
+#define LLWU_FILT3_FILTF LLWU_FILT3_FILTF_MASK
 
 /*! @name FILT4 - LLWU Pin Filter 4 register */
 #define LLWU_FILT4_FILTSEL_MASK                  (0x1FU)
 #define LLWU_FILT4_FILTSEL_SHIFT                 (0U)
-#define LLWU_FILT4_FILTSEL(x)                    (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTSEL_SHIFT)) & LLWU_FILT4_FILTSEL_MASK)
+#define LLWU_FILT4_FILTSEL_SET(x)                (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTSEL_SHIFT)) & LLWU_FILT4_FILTSEL_MASK)
+#define LLWU_FILT4_FILTSEL LLWU_FILT4_FILTSEL_MASK
 #define LLWU_FILT4_FILTE_MASK                    (0x60U)
 #define LLWU_FILT4_FILTE_SHIFT                   (5U)
-#define LLWU_FILT4_FILTE(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTE_SHIFT)) & LLWU_FILT4_FILTE_MASK)
+#define LLWU_FILT4_FILTE_SET(x)                  (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTE_SHIFT)) & LLWU_FILT4_FILTE_MASK)
+#define LLWU_FILT4_FILTE LLWU_FILT4_FILTE_MASK
 #define LLWU_FILT4_FILTF_MASK                    (0x80U)
 #define LLWU_FILT4_FILTF_SHIFT                   (7U)
-#define LLWU_FILT4_FILTF(x)                      (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTF_SHIFT)) & LLWU_FILT4_FILTF_MASK)
+#define LLWU_FILT4_FILTF_SET(x)                  (((uint8_t)(((uint8_t)(x)) << LLWU_FILT4_FILTF_SHIFT)) & LLWU_FILT4_FILTF_MASK)
+#define LLWU_FILT4_FILTF LLWU_FILT4_FILTF_MASK
 
 
 /*!
@@ -8788,7 +10707,7 @@ typedef struct {
 /** Peripheral LLWU base address */
 #define LLWU_BASE                                (0x4007C000u)
 /** Peripheral LLWU base pointer */
-#define LLWU                                     ((LLWU_Type *)LLWU_BASE)
+#define LLWU                                     ((LLWU_TypeDef *)LLWU_BASE)
 /** Array initializer of LLWU peripheral base addresses */
 #define LLWU_BASE_ADDRS                          { LLWU_BASE }
 /** Array initializer of LLWU peripheral base pointers */
@@ -8818,7 +10737,7 @@ typedef struct {
   __IO uint32_t PCCCVR;                            /**< Cache read/write value register, offset: 0xC */
        uint8_t RESERVED_0[16];
   __IO uint32_t PCCRMR;                            /**< Cache regions mode register, offset: 0x20 */
-} LMEM_Type;
+} LMEM_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- LMEM Register Masks
@@ -8832,126 +10751,164 @@ typedef struct {
 /*! @name PCCCR - Cache control register */
 #define LMEM_PCCCR_ENCACHE_MASK                  (0x1U)
 #define LMEM_PCCCR_ENCACHE_SHIFT                 (0U)
-#define LMEM_PCCCR_ENCACHE(x)                    (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENCACHE_SHIFT)) & LMEM_PCCCR_ENCACHE_MASK)
+#define LMEM_PCCCR_ENCACHE_SET(x)                (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENCACHE_SHIFT)) & LMEM_PCCCR_ENCACHE_MASK)
+#define LMEM_PCCCR_ENCACHE LMEM_PCCCR_ENCACHE_MASK
 #define LMEM_PCCCR_ENWRBUF_MASK                  (0x2U)
 #define LMEM_PCCCR_ENWRBUF_SHIFT                 (1U)
-#define LMEM_PCCCR_ENWRBUF(x)                    (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENWRBUF_SHIFT)) & LMEM_PCCCR_ENWRBUF_MASK)
+#define LMEM_PCCCR_ENWRBUF_SET(x)                (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_ENWRBUF_SHIFT)) & LMEM_PCCCR_ENWRBUF_MASK)
+#define LMEM_PCCCR_ENWRBUF LMEM_PCCCR_ENWRBUF_MASK
 #define LMEM_PCCCR_PCCR2_MASK                    (0x4U)
 #define LMEM_PCCCR_PCCR2_SHIFT                   (2U)
-#define LMEM_PCCCR_PCCR2(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR2_SHIFT)) & LMEM_PCCCR_PCCR2_MASK)
+#define LMEM_PCCCR_PCCR2_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR2_SHIFT)) & LMEM_PCCCR_PCCR2_MASK)
+#define LMEM_PCCCR_PCCR2 LMEM_PCCCR_PCCR2_MASK
 #define LMEM_PCCCR_PCCR3_MASK                    (0x8U)
 #define LMEM_PCCCR_PCCR3_SHIFT                   (3U)
-#define LMEM_PCCCR_PCCR3(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR3_SHIFT)) & LMEM_PCCCR_PCCR3_MASK)
+#define LMEM_PCCCR_PCCR3_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PCCR3_SHIFT)) & LMEM_PCCCR_PCCR3_MASK)
+#define LMEM_PCCCR_PCCR3 LMEM_PCCCR_PCCR3_MASK
 #define LMEM_PCCCR_INVW0_MASK                    (0x1000000U)
 #define LMEM_PCCCR_INVW0_SHIFT                   (24U)
-#define LMEM_PCCCR_INVW0(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW0_SHIFT)) & LMEM_PCCCR_INVW0_MASK)
+#define LMEM_PCCCR_INVW0_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW0_SHIFT)) & LMEM_PCCCR_INVW0_MASK)
+#define LMEM_PCCCR_INVW0 LMEM_PCCCR_INVW0_MASK
 #define LMEM_PCCCR_PUSHW0_MASK                   (0x2000000U)
 #define LMEM_PCCCR_PUSHW0_SHIFT                  (25U)
-#define LMEM_PCCCR_PUSHW0(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW0_SHIFT)) & LMEM_PCCCR_PUSHW0_MASK)
+#define LMEM_PCCCR_PUSHW0_SET(x)                 (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW0_SHIFT)) & LMEM_PCCCR_PUSHW0_MASK)
+#define LMEM_PCCCR_PUSHW0 LMEM_PCCCR_PUSHW0_MASK
 #define LMEM_PCCCR_INVW1_MASK                    (0x4000000U)
 #define LMEM_PCCCR_INVW1_SHIFT                   (26U)
-#define LMEM_PCCCR_INVW1(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW1_SHIFT)) & LMEM_PCCCR_INVW1_MASK)
+#define LMEM_PCCCR_INVW1_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_INVW1_SHIFT)) & LMEM_PCCCR_INVW1_MASK)
+#define LMEM_PCCCR_INVW1 LMEM_PCCCR_INVW1_MASK
 #define LMEM_PCCCR_PUSHW1_MASK                   (0x8000000U)
 #define LMEM_PCCCR_PUSHW1_SHIFT                  (27U)
-#define LMEM_PCCCR_PUSHW1(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW1_SHIFT)) & LMEM_PCCCR_PUSHW1_MASK)
+#define LMEM_PCCCR_PUSHW1_SET(x)                 (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_PUSHW1_SHIFT)) & LMEM_PCCCR_PUSHW1_MASK)
+#define LMEM_PCCCR_PUSHW1 LMEM_PCCCR_PUSHW1_MASK
 #define LMEM_PCCCR_GO_MASK                       (0x80000000U)
 #define LMEM_PCCCR_GO_SHIFT                      (31U)
-#define LMEM_PCCCR_GO(x)                         (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_GO_SHIFT)) & LMEM_PCCCR_GO_MASK)
+#define LMEM_PCCCR_GO_SET(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCR_GO_SHIFT)) & LMEM_PCCCR_GO_MASK)
+#define LMEM_PCCCR_GO LMEM_PCCCR_GO_MASK
 
 /*! @name PCCLCR - Cache line control register */
 #define LMEM_PCCLCR_LGO_MASK                     (0x1U)
 #define LMEM_PCCLCR_LGO_SHIFT                    (0U)
-#define LMEM_PCCLCR_LGO(x)                       (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LGO_SHIFT)) & LMEM_PCCLCR_LGO_MASK)
+#define LMEM_PCCLCR_LGO_SET(x)                   (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LGO_SHIFT)) & LMEM_PCCLCR_LGO_MASK)
+#define LMEM_PCCLCR_LGO LMEM_PCCLCR_LGO_MASK
 #define LMEM_PCCLCR_CACHEADDR_MASK               (0xFFCU)
 #define LMEM_PCCLCR_CACHEADDR_SHIFT              (2U)
-#define LMEM_PCCLCR_CACHEADDR(x)                 (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_CACHEADDR_SHIFT)) & LMEM_PCCLCR_CACHEADDR_MASK)
+#define LMEM_PCCLCR_CACHEADDR_SET(x)             (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_CACHEADDR_SHIFT)) & LMEM_PCCLCR_CACHEADDR_MASK)
+#define LMEM_PCCLCR_CACHEADDR LMEM_PCCLCR_CACHEADDR_MASK
 #define LMEM_PCCLCR_WSEL_MASK                    (0x4000U)
 #define LMEM_PCCLCR_WSEL_SHIFT                   (14U)
-#define LMEM_PCCLCR_WSEL(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_WSEL_SHIFT)) & LMEM_PCCLCR_WSEL_MASK)
+#define LMEM_PCCLCR_WSEL_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_WSEL_SHIFT)) & LMEM_PCCLCR_WSEL_MASK)
+#define LMEM_PCCLCR_WSEL LMEM_PCCLCR_WSEL_MASK
 #define LMEM_PCCLCR_TDSEL_MASK                   (0x10000U)
 #define LMEM_PCCLCR_TDSEL_SHIFT                  (16U)
-#define LMEM_PCCLCR_TDSEL(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_TDSEL_SHIFT)) & LMEM_PCCLCR_TDSEL_MASK)
+#define LMEM_PCCLCR_TDSEL_SET(x)                 (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_TDSEL_SHIFT)) & LMEM_PCCLCR_TDSEL_MASK)
+#define LMEM_PCCLCR_TDSEL LMEM_PCCLCR_TDSEL_MASK
 #define LMEM_PCCLCR_LCIVB_MASK                   (0x100000U)
 #define LMEM_PCCLCR_LCIVB_SHIFT                  (20U)
-#define LMEM_PCCLCR_LCIVB(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIVB_SHIFT)) & LMEM_PCCLCR_LCIVB_MASK)
+#define LMEM_PCCLCR_LCIVB_SET(x)                 (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIVB_SHIFT)) & LMEM_PCCLCR_LCIVB_MASK)
+#define LMEM_PCCLCR_LCIVB LMEM_PCCLCR_LCIVB_MASK
 #define LMEM_PCCLCR_LCIMB_MASK                   (0x200000U)
 #define LMEM_PCCLCR_LCIMB_SHIFT                  (21U)
-#define LMEM_PCCLCR_LCIMB(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIMB_SHIFT)) & LMEM_PCCLCR_LCIMB_MASK)
+#define LMEM_PCCLCR_LCIMB_SET(x)                 (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCIMB_SHIFT)) & LMEM_PCCLCR_LCIMB_MASK)
+#define LMEM_PCCLCR_LCIMB LMEM_PCCLCR_LCIMB_MASK
 #define LMEM_PCCLCR_LCWAY_MASK                   (0x400000U)
 #define LMEM_PCCLCR_LCWAY_SHIFT                  (22U)
-#define LMEM_PCCLCR_LCWAY(x)                     (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCWAY_SHIFT)) & LMEM_PCCLCR_LCWAY_MASK)
+#define LMEM_PCCLCR_LCWAY_SET(x)                 (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCWAY_SHIFT)) & LMEM_PCCLCR_LCWAY_MASK)
+#define LMEM_PCCLCR_LCWAY LMEM_PCCLCR_LCWAY_MASK
 #define LMEM_PCCLCR_LCMD_MASK                    (0x3000000U)
 #define LMEM_PCCLCR_LCMD_SHIFT                   (24U)
-#define LMEM_PCCLCR_LCMD(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCMD_SHIFT)) & LMEM_PCCLCR_LCMD_MASK)
+#define LMEM_PCCLCR_LCMD_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LCMD_SHIFT)) & LMEM_PCCLCR_LCMD_MASK)
+#define LMEM_PCCLCR_LCMD LMEM_PCCLCR_LCMD_MASK
 #define LMEM_PCCLCR_LADSEL_MASK                  (0x4000000U)
 #define LMEM_PCCLCR_LADSEL_SHIFT                 (26U)
-#define LMEM_PCCLCR_LADSEL(x)                    (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LADSEL_SHIFT)) & LMEM_PCCLCR_LADSEL_MASK)
+#define LMEM_PCCLCR_LADSEL_SET(x)                (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LADSEL_SHIFT)) & LMEM_PCCLCR_LADSEL_MASK)
+#define LMEM_PCCLCR_LADSEL LMEM_PCCLCR_LADSEL_MASK
 #define LMEM_PCCLCR_LACC_MASK                    (0x8000000U)
 #define LMEM_PCCLCR_LACC_SHIFT                   (27U)
-#define LMEM_PCCLCR_LACC(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LACC_SHIFT)) & LMEM_PCCLCR_LACC_MASK)
+#define LMEM_PCCLCR_LACC_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LMEM_PCCLCR_LACC_SHIFT)) & LMEM_PCCLCR_LACC_MASK)
+#define LMEM_PCCLCR_LACC LMEM_PCCLCR_LACC_MASK
 
 /*! @name PCCSAR - Cache search address register */
 #define LMEM_PCCSAR_LGO_MASK                     (0x1U)
 #define LMEM_PCCSAR_LGO_SHIFT                    (0U)
-#define LMEM_PCCSAR_LGO(x)                       (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_LGO_SHIFT)) & LMEM_PCCSAR_LGO_MASK)
+#define LMEM_PCCSAR_LGO_SET(x)                   (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_LGO_SHIFT)) & LMEM_PCCSAR_LGO_MASK)
+#define LMEM_PCCSAR_LGO LMEM_PCCSAR_LGO_MASK
 #define LMEM_PCCSAR_PHYADDR_MASK                 (0xFFFFFFFCU)
 #define LMEM_PCCSAR_PHYADDR_SHIFT                (2U)
-#define LMEM_PCCSAR_PHYADDR(x)                   (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK)
+#define LMEM_PCCSAR_PHYADDR_SET(x)               (((uint32_t)(((uint32_t)(x)) << LMEM_PCCSAR_PHYADDR_SHIFT)) & LMEM_PCCSAR_PHYADDR_MASK)
+#define LMEM_PCCSAR_PHYADDR LMEM_PCCSAR_PHYADDR_MASK
 
 /*! @name PCCCVR - Cache read/write value register */
 #define LMEM_PCCCVR_DATA_MASK                    (0xFFFFFFFFU)
 #define LMEM_PCCCVR_DATA_SHIFT                   (0U)
-#define LMEM_PCCCVR_DATA(x)                      (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCVR_DATA_SHIFT)) & LMEM_PCCCVR_DATA_MASK)
+#define LMEM_PCCCVR_DATA_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LMEM_PCCCVR_DATA_SHIFT)) & LMEM_PCCCVR_DATA_MASK)
+#define LMEM_PCCCVR_DATA LMEM_PCCCVR_DATA_MASK
 
 /*! @name PCCRMR - Cache regions mode register */
 #define LMEM_PCCRMR_R15_MASK                     (0x3U)
 #define LMEM_PCCRMR_R15_SHIFT                    (0U)
-#define LMEM_PCCRMR_R15(x)                       (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R15_SHIFT)) & LMEM_PCCRMR_R15_MASK)
+#define LMEM_PCCRMR_R15_SET(x)                   (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R15_SHIFT)) & LMEM_PCCRMR_R15_MASK)
+#define LMEM_PCCRMR_R15 LMEM_PCCRMR_R15_MASK
 #define LMEM_PCCRMR_R14_MASK                     (0xCU)
 #define LMEM_PCCRMR_R14_SHIFT                    (2U)
-#define LMEM_PCCRMR_R14(x)                       (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R14_SHIFT)) & LMEM_PCCRMR_R14_MASK)
+#define LMEM_PCCRMR_R14_SET(x)                   (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R14_SHIFT)) & LMEM_PCCRMR_R14_MASK)
+#define LMEM_PCCRMR_R14 LMEM_PCCRMR_R14_MASK
 #define LMEM_PCCRMR_R13_MASK                     (0x30U)
 #define LMEM_PCCRMR_R13_SHIFT                    (4U)
-#define LMEM_PCCRMR_R13(x)                       (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R13_SHIFT)) & LMEM_PCCRMR_R13_MASK)
+#define LMEM_PCCRMR_R13_SET(x)                   (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R13_SHIFT)) & LMEM_PCCRMR_R13_MASK)
+#define LMEM_PCCRMR_R13 LMEM_PCCRMR_R13_MASK
 #define LMEM_PCCRMR_R12_MASK                     (0xC0U)
 #define LMEM_PCCRMR_R12_SHIFT                    (6U)
-#define LMEM_PCCRMR_R12(x)                       (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R12_SHIFT)) & LMEM_PCCRMR_R12_MASK)
+#define LMEM_PCCRMR_R12_SET(x)                   (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R12_SHIFT)) & LMEM_PCCRMR_R12_MASK)
+#define LMEM_PCCRMR_R12 LMEM_PCCRMR_R12_MASK
 #define LMEM_PCCRMR_R11_MASK                     (0x300U)
 #define LMEM_PCCRMR_R11_SHIFT                    (8U)
-#define LMEM_PCCRMR_R11(x)                       (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R11_SHIFT)) & LMEM_PCCRMR_R11_MASK)
+#define LMEM_PCCRMR_R11_SET(x)                   (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R11_SHIFT)) & LMEM_PCCRMR_R11_MASK)
+#define LMEM_PCCRMR_R11 LMEM_PCCRMR_R11_MASK
 #define LMEM_PCCRMR_R10_MASK                     (0xC00U)
 #define LMEM_PCCRMR_R10_SHIFT                    (10U)
-#define LMEM_PCCRMR_R10(x)                       (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R10_SHIFT)) & LMEM_PCCRMR_R10_MASK)
+#define LMEM_PCCRMR_R10_SET(x)                   (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R10_SHIFT)) & LMEM_PCCRMR_R10_MASK)
+#define LMEM_PCCRMR_R10 LMEM_PCCRMR_R10_MASK
 #define LMEM_PCCRMR_R9_MASK                      (0x3000U)
 #define LMEM_PCCRMR_R9_SHIFT                     (12U)
-#define LMEM_PCCRMR_R9(x)                        (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R9_SHIFT)) & LMEM_PCCRMR_R9_MASK)
+#define LMEM_PCCRMR_R9_SET(x)                    (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R9_SHIFT)) & LMEM_PCCRMR_R9_MASK)
+#define LMEM_PCCRMR_R9 LMEM_PCCRMR_R9_MASK
 #define LMEM_PCCRMR_R8_MASK                      (0xC000U)
 #define LMEM_PCCRMR_R8_SHIFT                     (14U)
-#define LMEM_PCCRMR_R8(x)                        (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R8_SHIFT)) & LMEM_PCCRMR_R8_MASK)
+#define LMEM_PCCRMR_R8_SET(x)                    (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R8_SHIFT)) & LMEM_PCCRMR_R8_MASK)
+#define LMEM_PCCRMR_R8 LMEM_PCCRMR_R8_MASK
 #define LMEM_PCCRMR_R7_MASK                      (0x30000U)
 #define LMEM_PCCRMR_R7_SHIFT                     (16U)
-#define LMEM_PCCRMR_R7(x)                        (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R7_SHIFT)) & LMEM_PCCRMR_R7_MASK)
+#define LMEM_PCCRMR_R7_SET(x)                    (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R7_SHIFT)) & LMEM_PCCRMR_R7_MASK)
+#define LMEM_PCCRMR_R7 LMEM_PCCRMR_R7_MASK
 #define LMEM_PCCRMR_R6_MASK                      (0xC0000U)
 #define LMEM_PCCRMR_R6_SHIFT                     (18U)
-#define LMEM_PCCRMR_R6(x)                        (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R6_SHIFT)) & LMEM_PCCRMR_R6_MASK)
+#define LMEM_PCCRMR_R6_SET(x)                    (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R6_SHIFT)) & LMEM_PCCRMR_R6_MASK)
+#define LMEM_PCCRMR_R6 LMEM_PCCRMR_R6_MASK
 #define LMEM_PCCRMR_R5_MASK                      (0x300000U)
 #define LMEM_PCCRMR_R5_SHIFT                     (20U)
-#define LMEM_PCCRMR_R5(x)                        (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R5_SHIFT)) & LMEM_PCCRMR_R5_MASK)
+#define LMEM_PCCRMR_R5_SET(x)                    (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R5_SHIFT)) & LMEM_PCCRMR_R5_MASK)
+#define LMEM_PCCRMR_R5 LMEM_PCCRMR_R5_MASK
 #define LMEM_PCCRMR_R4_MASK                      (0xC00000U)
 #define LMEM_PCCRMR_R4_SHIFT                     (22U)
-#define LMEM_PCCRMR_R4(x)                        (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R4_SHIFT)) & LMEM_PCCRMR_R4_MASK)
+#define LMEM_PCCRMR_R4_SET(x)                    (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R4_SHIFT)) & LMEM_PCCRMR_R4_MASK)
+#define LMEM_PCCRMR_R4 LMEM_PCCRMR_R4_MASK
 #define LMEM_PCCRMR_R3_MASK                      (0x3000000U)
 #define LMEM_PCCRMR_R3_SHIFT                     (24U)
-#define LMEM_PCCRMR_R3(x)                        (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R3_SHIFT)) & LMEM_PCCRMR_R3_MASK)
+#define LMEM_PCCRMR_R3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R3_SHIFT)) & LMEM_PCCRMR_R3_MASK)
+#define LMEM_PCCRMR_R3 LMEM_PCCRMR_R3_MASK
 #define LMEM_PCCRMR_R2_MASK                      (0xC000000U)
 #define LMEM_PCCRMR_R2_SHIFT                     (26U)
-#define LMEM_PCCRMR_R2(x)                        (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R2_SHIFT)) & LMEM_PCCRMR_R2_MASK)
+#define LMEM_PCCRMR_R2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R2_SHIFT)) & LMEM_PCCRMR_R2_MASK)
+#define LMEM_PCCRMR_R2 LMEM_PCCRMR_R2_MASK
 #define LMEM_PCCRMR_R1_MASK                      (0x30000000U)
 #define LMEM_PCCRMR_R1_SHIFT                     (28U)
-#define LMEM_PCCRMR_R1(x)                        (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R1_SHIFT)) & LMEM_PCCRMR_R1_MASK)
+#define LMEM_PCCRMR_R1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R1_SHIFT)) & LMEM_PCCRMR_R1_MASK)
+#define LMEM_PCCRMR_R1 LMEM_PCCRMR_R1_MASK
 #define LMEM_PCCRMR_R0_MASK                      (0xC0000000U)
 #define LMEM_PCCRMR_R0_SHIFT                     (30U)
-#define LMEM_PCCRMR_R0(x)                        (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R0_SHIFT)) & LMEM_PCCRMR_R0_MASK)
+#define LMEM_PCCRMR_R0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << LMEM_PCCRMR_R0_SHIFT)) & LMEM_PCCRMR_R0_MASK)
+#define LMEM_PCCRMR_R0 LMEM_PCCRMR_R0_MASK
 
 
 /*!
@@ -8963,7 +10920,7 @@ typedef struct {
 /** Peripheral LMEM base address */
 #define LMEM_BASE                                (0xE0082000u)
 /** Peripheral LMEM base pointer */
-#define LMEM                                     ((LMEM_Type *)LMEM_BASE)
+#define LMEM                                     ((LMEM_TypeDef *)LMEM_BASE)
 /** Array initializer of LMEM peripheral base addresses */
 #define LMEM_BASE_ADDRS                          { LMEM_BASE }
 /** Array initializer of LMEM peripheral base pointers */
@@ -8989,7 +10946,7 @@ typedef struct {
   __IO uint32_t PSR;                               /**< Low Power Timer Prescale Register, offset: 0x4 */
   __IO uint32_t CMR;                               /**< Low Power Timer Compare Register, offset: 0x8 */
   __IO uint32_t CNR;                               /**< Low Power Timer Counter Register, offset: 0xC */
-} LPTMR_Type;
+} LPTMR_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- LPTMR Register Masks
@@ -9007,16 +10964,20 @@ typedef struct {
 #define LPTMRx_CSR_TEN                            LPTMRx_CSR_TEN_SET(1)
 #define LPTMRx_CSR_TMS_MASK                       (0x2U)
 #define LPTMRx_CSR_TMS_SHIFT                      (1U)
-#define LPTMRx_CSR_TMS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMRx_CSR_TMS_SHIFT)) & LPTMRx_CSR_TMS_MASK)
+#define LPTMRx_CSR_TMS_SET(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMRx_CSR_TMS_SHIFT)) & LPTMRx_CSR_TMS_MASK)
+#define LPTMRx_CSR_TMS LPTMRx_CSR_TMS_MASK
 #define LPTMRx_CSR_TFC_MASK                       (0x4U)
 #define LPTMRx_CSR_TFC_SHIFT                      (2U)
-#define LPTMRx_CSR_TFC(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMRx_CSR_TFC_SHIFT)) & LPTMRx_CSR_TFC_MASK)
+#define LPTMRx_CSR_TFC_SET(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMRx_CSR_TFC_SHIFT)) & LPTMRx_CSR_TFC_MASK)
+#define LPTMRx_CSR_TFC LPTMRx_CSR_TFC_MASK
 #define LPTMRx_CSR_TPP_MASK                       (0x8U)
 #define LPTMRx_CSR_TPP_SHIFT                      (3U)
-#define LPTMRx_CSR_TPP(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMRx_CSR_TPP_SHIFT)) & LPTMRx_CSR_TPP_MASK)
+#define LPTMRx_CSR_TPP_SET(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMRx_CSR_TPP_SHIFT)) & LPTMRx_CSR_TPP_MASK)
+#define LPTMRx_CSR_TPP LPTMRx_CSR_TPP_MASK
 #define LPTMRx_CSR_TPS_MASK                       (0x30U)
 #define LPTMRx_CSR_TPS_SHIFT                      (4U)
-#define LPTMRx_CSR_TPS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMRx_CSR_TPS_SHIFT)) & LPTMRx_CSR_TPS_MASK)
+#define LPTMRx_CSR_TPS_SET(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMRx_CSR_TPS_SHIFT)) & LPTMRx_CSR_TPS_MASK)
+#define LPTMRx_CSR_TPS LPTMRx_CSR_TPS_MASK
 #define LPTMRx_CSR_TIE_MASK                       (0x40U)
 #define LPTMRx_CSR_TIE_SHIFT                      (6U)
 #define LPTMRx_CSR_TIE_SET(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMRx_CSR_TIE_SHIFT)) & LPTMRx_CSR_TIE_MASK)
@@ -9029,23 +10990,26 @@ typedef struct {
 /*! @name PSR - Low Power Timer Prescale Register */
 #define LPTMRx_PSR_PCS_MASK                       (0x3U)
 #define LPTMRx_PSR_PCS_SHIFT                      (0U)
-#define LPTMRx_PSR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << LPTMRx_PSR_PCS_SHIFT)) & LPTMRx_PSR_PCS_MASK)
+#define LPTMRx_PSR_PCS(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMRx_PSR_PCS_SHIFT)) & LPTMRx_PSR_PCS_MASK)
 #define LPTMRx_PSR_PBYP_MASK                      (0x4U)
 #define LPTMRx_PSR_PBYP_SHIFT                     (2U)
-#define LPTMRx_PSR_PBYP(x)                        (((uint32_t)(((uint32_t)(x)) << LPTMRx_PSR_PBYP_SHIFT)) & LPTMRx_PSR_PBYP_MASK)
+#define LPTMRx_PSR_PBYP_SET(x)                    (((uint32_t)(((uint32_t)(x)) << LPTMRx_PSR_PBYP_SHIFT)) & LPTMRx_PSR_PBYP_MASK)
+#define LPTMRx_PSR_PBYP LPTMRx_PSR_PBYP_MASK
 #define LPTMRx_PSR_PRESCALE_MASK                  (0x78U)
- #define LPTMRx_PSR_PRESCALE_SHIFT                 (3U)
-#define LPTMRx_PSR_PRESCALE(x)                    (((uint32_t)(((uint32_t)(x)) << LPTMRx_PSR_PRESCALE_SHIFT)) & LPTMRx_PSR_PRESCALE_MASK)
+#define LPTMRx_PSR_PRESCALE_SHIFT                 (3U)
+#define LPTMRx_PSR_PRESCALE(x)                (((uint32_t)(((uint32_t)(x)) << LPTMRx_PSR_PRESCALE_SHIFT)) & LPTMRx_PSR_PRESCALE_MASK)
 
 /*! @name CMR - Low Power Timer Compare Register */
 #define LPTMRx_CMR_COMPARE_MASK                   (0xFFFFU)
 #define LPTMRx_CMR_COMPARE_SHIFT                  (0U)
-#define LPTMRx_CMR_COMPARE(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
+#define LPTMRx_CMR_COMPARE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
+#define LPTMRx_CMR_COMPARE LPTMRx_CMR_COMPARE_MASK
 
 /*! @name CNR - Low Power Timer Counter Register */
 #define LPTMRx_CNR_COUNTER_MASK                   (0xFFFFU)
 #define LPTMRx_CNR_COUNTER_SHIFT                  (0U)
-#define LPTMRx_CNR_COUNTER(x)                     (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
+#define LPTMRx_CNR_COUNTER_SET(x)                 (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
+#define LPTMRx_CNR_COUNTER LPTMRx_CNR_COUNTER_MASK
 
 
 /*!
@@ -9057,7 +11021,7 @@ typedef struct {
 /** Peripheral LPTMR0 base address */
 #define LPTMR0_BASE                              (0x40040000u)
 /** Peripheral LPTMR0 base pointer */
-#define LPTMR0                                   ((LPTMR_Type *)LPTMR0_BASE)
+#define LPTMR0                                   ((LPTMR_TypeDef *)LPTMR0_BASE)
 /** Array initializer of LPTMR peripheral base addresses */
 #define LPTMRx_BASE_ADDRS                         { LPTMR0_BASE }
 /** Array initializer of LPTMR peripheral base pointers */
@@ -9075,7 +11039,7 @@ typedef struct {
    ---------------------------------------------------------------------------- */
 
 /*!
- * @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
+ * @addtogroup LPUARTx_Peripheral_Access_Layer LPUART Peripheral Access Layer
  * @{
  */
 
@@ -9087,300 +11051,383 @@ typedef struct {
   __IO uint32_t DATA;                              /**< LPUART Data Register, offset: 0xC */
   __IO uint32_t MATCH;                             /**< LPUART Match Address Register, offset: 0x10 */
   __IO uint32_t MODIR;                             /**< LPUART Modem IrDA Register, offset: 0x14 */
-} LPUART_Type;
+} LPUART_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- LPUART Register Masks
    ---------------------------------------------------------------------------- */
 
 /*!
- * @addtogroup LPUART_Register_Masks LPUART Register Masks
+ * @addtogroup LPUARTx_Register_Masks LPUART Register Masks
  * @{
  */
 
 /*! @name BAUD - LPUART Baud Rate Register */
-#define LPUART_BAUD_SBR_MASK                     (0x1FFFU)
-#define LPUART_BAUD_SBR_SHIFT                    (0U)
-#define LPUART_BAUD_SBR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
-#define LPUART_BAUD_SBNS_MASK                    (0x2000U)
-#define LPUART_BAUD_SBNS_SHIFT                   (13U)
-#define LPUART_BAUD_SBNS(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
-#define LPUART_BAUD_RXEDGIE_MASK                 (0x4000U)
-#define LPUART_BAUD_RXEDGIE_SHIFT                (14U)
-#define LPUART_BAUD_RXEDGIE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
-#define LPUART_BAUD_LBKDIE_MASK                  (0x8000U)
-#define LPUART_BAUD_LBKDIE_SHIFT                 (15U)
-#define LPUART_BAUD_LBKDIE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
-#define LPUART_BAUD_RESYNCDIS_MASK               (0x10000U)
-#define LPUART_BAUD_RESYNCDIS_SHIFT              (16U)
-#define LPUART_BAUD_RESYNCDIS(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
-#define LPUART_BAUD_BOTHEDGE_MASK                (0x20000U)
-#define LPUART_BAUD_BOTHEDGE_SHIFT               (17U)
-#define LPUART_BAUD_BOTHEDGE(x)                  (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
-#define LPUART_BAUD_MATCFG_MASK                  (0xC0000U)
-#define LPUART_BAUD_MATCFG_SHIFT                 (18U)
-#define LPUART_BAUD_MATCFG(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
-#define LPUART_BAUD_RDMAE_MASK                   (0x200000U)
-#define LPUART_BAUD_RDMAE_SHIFT                  (21U)
-#define LPUART_BAUD_RDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
-#define LPUART_BAUD_TDMAE_MASK                   (0x800000U)
-#define LPUART_BAUD_TDMAE_SHIFT                  (23U)
-#define LPUART_BAUD_TDMAE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
-#define LPUART_BAUD_OSR_MASK                     (0x1F000000U)
-#define LPUART_BAUD_OSR_SHIFT                    (24U)
-#define LPUART_BAUD_OSR(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
-#define LPUART_BAUD_M10_MASK                     (0x20000000U)
-#define LPUART_BAUD_M10_SHIFT                    (29U)
-#define LPUART_BAUD_M10(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
-#define LPUART_BAUD_MAEN2_MASK                   (0x40000000U)
-#define LPUART_BAUD_MAEN2_SHIFT                  (30U)
-#define LPUART_BAUD_MAEN2(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
-#define LPUART_BAUD_MAEN1_MASK                   (0x80000000U)
-#define LPUART_BAUD_MAEN1_SHIFT                  (31U)
-#define LPUART_BAUD_MAEN1(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
+#define LPUARTx_BAUD_SBR_MASK                     (0x1FFFU)
+#define LPUARTx_BAUD_SBR_SHIFT                    (0U)
+#define LPUARTx_BAUD_SBR_SET(x)                   (((uint32_t)(((uint32_t)(x)) << LPUARTx_BAUD_SBR_SHIFT)) & LPUARTx_BAUD_SBR_MASK)
+#define LPUARTx_BAUD_SBR LPUARTx_BAUD_SBR_MASK
+#define LPUARTx_BAUD_SBNS_MASK                    (0x2000U)
+#define LPUARTx_BAUD_SBNS_SHIFT                   (13U)
+#define LPUARTx_BAUD_SBNS_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LPUARTx_BAUD_SBNS_SHIFT)) & LPUARTx_BAUD_SBNS_MASK)
+#define LPUARTx_BAUD_SBNS LPUARTx_BAUD_SBNS_MASK
+#define LPUARTx_BAUD_RXEDGIE_MASK                 (0x4000U)
+#define LPUARTx_BAUD_RXEDGIE_SHIFT                (14U)
+#define LPUARTx_BAUD_RXEDGIE_SET(x)               (((uint32_t)(((uint32_t)(x)) << LPUARTx_BAUD_RXEDGIE_SHIFT)) & LPUARTx_BAUD_RXEDGIE_MASK)
+#define LPUARTx_BAUD_RXEDGIE LPUARTx_BAUD_RXEDGIE_MASK
+#define LPUARTx_BAUD_LBKDIE_MASK                  (0x8000U)
+#define LPUARTx_BAUD_LBKDIE_SHIFT                 (15U)
+#define LPUARTx_BAUD_LBKDIE_SET(x)                (((uint32_t)(((uint32_t)(x)) << LPUARTx_BAUD_LBKDIE_SHIFT)) & LPUARTx_BAUD_LBKDIE_MASK)
+#define LPUARTx_BAUD_LBKDIE LPUARTx_BAUD_LBKDIE_MASK
+#define LPUARTx_BAUD_RESYNCDIS_MASK               (0x10000U)
+#define LPUARTx_BAUD_RESYNCDIS_SHIFT              (16U)
+#define LPUARTx_BAUD_RESYNCDIS_SET(x)             (((uint32_t)(((uint32_t)(x)) << LPUARTx_BAUD_RESYNCDIS_SHIFT)) & LPUARTx_BAUD_RESYNCDIS_MASK)
+#define LPUARTx_BAUD_RESYNCDIS LPUARTx_BAUD_RESYNCDIS_MASK
+#define LPUARTx_BAUD_BOTHEDGE_MASK                (0x20000U)
+#define LPUARTx_BAUD_BOTHEDGE_SHIFT               (17U)
+#define LPUARTx_BAUD_BOTHEDGE_SET(x)              (((uint32_t)(((uint32_t)(x)) << LPUARTx_BAUD_BOTHEDGE_SHIFT)) & LPUARTx_BAUD_BOTHEDGE_MASK)
+#define LPUARTx_BAUD_BOTHEDGE LPUARTx_BAUD_BOTHEDGE_MASK
+#define LPUARTx_BAUD_MATCFG_MASK                  (0xC0000U)
+#define LPUARTx_BAUD_MATCFG_SHIFT                 (18U)
+#define LPUARTx_BAUD_MATCFG_SET(x)                (((uint32_t)(((uint32_t)(x)) << LPUARTx_BAUD_MATCFG_SHIFT)) & LPUARTx_BAUD_MATCFG_MASK)
+#define LPUARTx_BAUD_MATCFG LPUARTx_BAUD_MATCFG_MASK
+#define LPUARTx_BAUD_RDMAE_MASK                   (0x200000U)
+#define LPUARTx_BAUD_RDMAE_SHIFT                  (21U)
+#define LPUARTx_BAUD_RDMAE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << LPUARTx_BAUD_RDMAE_SHIFT)) & LPUARTx_BAUD_RDMAE_MASK)
+#define LPUARTx_BAUD_RDMAE LPUARTx_BAUD_RDMAE_MASK
+#define LPUARTx_BAUD_TDMAE_MASK                   (0x800000U)
+#define LPUARTx_BAUD_TDMAE_SHIFT                  (23U)
+#define LPUARTx_BAUD_TDMAE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << LPUARTx_BAUD_TDMAE_SHIFT)) & LPUARTx_BAUD_TDMAE_MASK)
+#define LPUARTx_BAUD_TDMAE LPUARTx_BAUD_TDMAE_MASK
+#define LPUARTx_BAUD_OSR_MASK                     (0x1F000000U)
+#define LPUARTx_BAUD_OSR_SHIFT                    (24U)
+#define LPUARTx_BAUD_OSR_SET(x)                   (((uint32_t)(((uint32_t)(x)) << LPUARTx_BAUD_OSR_SHIFT)) & LPUARTx_BAUD_OSR_MASK)
+#define LPUARTx_BAUD_OSR LPUARTx_BAUD_OSR_MASK
+#define LPUARTx_BAUD_M10_MASK                     (0x20000000U)
+#define LPUARTx_BAUD_M10_SHIFT                    (29U)
+#define LPUARTx_BAUD_M10_SET(x)                   (((uint32_t)(((uint32_t)(x)) << LPUARTx_BAUD_M10_SHIFT)) & LPUARTx_BAUD_M10_MASK)
+#define LPUARTx_BAUD_M10 LPUARTx_BAUD_M10_MASK
+#define LPUARTx_BAUD_MAEN2_MASK                   (0x40000000U)
+#define LPUARTx_BAUD_MAEN2_SHIFT                  (30U)
+#define LPUARTx_BAUD_MAEN2_SET(x)                 (((uint32_t)(((uint32_t)(x)) << LPUARTx_BAUD_MAEN2_SHIFT)) & LPUARTx_BAUD_MAEN2_MASK)
+#define LPUARTx_BAUD_MAEN2 LPUARTx_BAUD_MAEN2_MASK
+#define LPUARTx_BAUD_MAEN1_MASK                   (0x80000000U)
+#define LPUARTx_BAUD_MAEN1_SHIFT                  (31U)
+#define LPUARTx_BAUD_MAEN1_SET(x)                 (((uint32_t)(((uint32_t)(x)) << LPUARTx_BAUD_MAEN1_SHIFT)) & LPUARTx_BAUD_MAEN1_MASK)
+#define LPUARTx_BAUD_MAEN1 LPUARTx_BAUD_MAEN1_MASK
 
 /*! @name STAT - LPUART Status Register */
-#define LPUART_STAT_MA2F_MASK                    (0x4000U)
-#define LPUART_STAT_MA2F_SHIFT                   (14U)
-#define LPUART_STAT_MA2F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
-#define LPUART_STAT_MA1F_MASK                    (0x8000U)
-#define LPUART_STAT_MA1F_SHIFT                   (15U)
-#define LPUART_STAT_MA1F(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
-#define LPUART_STAT_PF_MASK                      (0x10000U)
-#define LPUART_STAT_PF_SHIFT                     (16U)
-#define LPUART_STAT_PF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
-#define LPUART_STAT_FE_MASK                      (0x20000U)
-#define LPUART_STAT_FE_SHIFT                     (17U)
-#define LPUART_STAT_FE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
-#define LPUART_STAT_NF_MASK                      (0x40000U)
-#define LPUART_STAT_NF_SHIFT                     (18U)
-#define LPUART_STAT_NF(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
-#define LPUART_STAT_OR_MASK                      (0x80000U)
-#define LPUART_STAT_OR_SHIFT                     (19U)
-#define LPUART_STAT_OR(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
-#define LPUART_STAT_IDLE_MASK                    (0x100000U)
-#define LPUART_STAT_IDLE_SHIFT                   (20U)
-#define LPUART_STAT_IDLE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
-#define LPUART_STAT_RDRF_MASK                    (0x200000U)
-#define LPUART_STAT_RDRF_SHIFT                   (21U)
-#define LPUART_STAT_RDRF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
-#define LPUART_STAT_TC_MASK                      (0x400000U)
-#define LPUART_STAT_TC_SHIFT                     (22U)
-#define LPUART_STAT_TC(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
-#define LPUART_STAT_TDRE_MASK                    (0x800000U)
-#define LPUART_STAT_TDRE_SHIFT                   (23U)
-#define LPUART_STAT_TDRE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
-#define LPUART_STAT_RAF_MASK                     (0x1000000U)
-#define LPUART_STAT_RAF_SHIFT                    (24U)
-#define LPUART_STAT_RAF(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
-#define LPUART_STAT_LBKDE_MASK                   (0x2000000U)
-#define LPUART_STAT_LBKDE_SHIFT                  (25U)
-#define LPUART_STAT_LBKDE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
-#define LPUART_STAT_BRK13_MASK                   (0x4000000U)
-#define LPUART_STAT_BRK13_SHIFT                  (26U)
-#define LPUART_STAT_BRK13(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
-#define LPUART_STAT_RWUID_MASK                   (0x8000000U)
-#define LPUART_STAT_RWUID_SHIFT                  (27U)
-#define LPUART_STAT_RWUID(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
-#define LPUART_STAT_RXINV_MASK                   (0x10000000U)
-#define LPUART_STAT_RXINV_SHIFT                  (28U)
-#define LPUART_STAT_RXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
-#define LPUART_STAT_MSBF_MASK                    (0x20000000U)
-#define LPUART_STAT_MSBF_SHIFT                   (29U)
-#define LPUART_STAT_MSBF(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
-#define LPUART_STAT_RXEDGIF_MASK                 (0x40000000U)
-#define LPUART_STAT_RXEDGIF_SHIFT                (30U)
-#define LPUART_STAT_RXEDGIF(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
-#define LPUART_STAT_LBKDIF_MASK                  (0x80000000U)
-#define LPUART_STAT_LBKDIF_SHIFT                 (31U)
-#define LPUART_STAT_LBKDIF(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
+#define LPUARTx_STAT_MA2F_MASK                    (0x4000U)
+#define LPUARTx_STAT_MA2F_SHIFT                   (14U)
+#define LPUARTx_STAT_MA2F_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LPUARTx_STAT_MA2F_SHIFT)) & LPUARTx_STAT_MA2F_MASK)
+#define LPUARTx_STAT_MA2F LPUARTx_STAT_MA2F_MASK
+#define LPUARTx_STAT_MA1F_MASK                    (0x8000U)
+#define LPUARTx_STAT_MA1F_SHIFT                   (15U)
+#define LPUARTx_STAT_MA1F_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LPUARTx_STAT_MA1F_SHIFT)) & LPUARTx_STAT_MA1F_MASK)
+#define LPUARTx_STAT_MA1F LPUARTx_STAT_MA1F_MASK
+#define LPUARTx_STAT_PF_MASK                      (0x10000U)
+#define LPUARTx_STAT_PF_SHIFT                     (16U)
+#define LPUARTx_STAT_PF_SET(x)                    (((uint32_t)(((uint32_t)(x)) << LPUARTx_STAT_PF_SHIFT)) & LPUARTx_STAT_PF_MASK)
+#define LPUARTx_STAT_PF LPUARTx_STAT_PF_MASK
+#define LPUARTx_STAT_FE_MASK                      (0x20000U)
+#define LPUARTx_STAT_FE_SHIFT                     (17U)
+#define LPUARTx_STAT_FE_SET(x)                    (((uint32_t)(((uint32_t)(x)) << LPUARTx_STAT_FE_SHIFT)) & LPUARTx_STAT_FE_MASK)
+#define LPUARTx_STAT_FE LPUARTx_STAT_FE_MASK
+#define LPUARTx_STAT_NF_MASK                      (0x40000U)
+#define LPUARTx_STAT_NF_SHIFT                     (18U)
+#define LPUARTx_STAT_NF_SET(x)                    (((uint32_t)(((uint32_t)(x)) << LPUARTx_STAT_NF_SHIFT)) & LPUARTx_STAT_NF_MASK)
+#define LPUARTx_STAT_NF LPUARTx_STAT_NF_MASK
+#define LPUARTx_STAT_OR_MASK                      (0x80000U)
+#define LPUARTx_STAT_OR_SHIFT                     (19U)
+#define LPUARTx_STAT_OR_SET(x)                    (((uint32_t)(((uint32_t)(x)) << LPUARTx_STAT_OR_SHIFT)) & LPUARTx_STAT_OR_MASK)
+#define LPUARTx_STAT_OR LPUARTx_STAT_OR_MASK
+#define LPUARTx_STAT_IDLE_MASK                    (0x100000U)
+#define LPUARTx_STAT_IDLE_SHIFT                   (20U)
+#define LPUARTx_STAT_IDLE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LPUARTx_STAT_IDLE_SHIFT)) & LPUARTx_STAT_IDLE_MASK)
+#define LPUARTx_STAT_IDLE LPUARTx_STAT_IDLE_MASK
+#define LPUARTx_STAT_RDRF_MASK                    (0x200000U)
+#define LPUARTx_STAT_RDRF_SHIFT                   (21U)
+#define LPUARTx_STAT_RDRF_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LPUARTx_STAT_RDRF_SHIFT)) & LPUARTx_STAT_RDRF_MASK)
+#define LPUARTx_STAT_RDRF LPUARTx_STAT_RDRF_MASK
+#define LPUARTx_STAT_TC_MASK                      (0x400000U)
+#define LPUARTx_STAT_TC_SHIFT                     (22U)
+#define LPUARTx_STAT_TC_SET(x)                    (((uint32_t)(((uint32_t)(x)) << LPUARTx_STAT_TC_SHIFT)) & LPUARTx_STAT_TC_MASK)
+#define LPUARTx_STAT_TC LPUARTx_STAT_TC_MASK
+#define LPUARTx_STAT_TDRE_MASK                    (0x800000U)
+#define LPUARTx_STAT_TDRE_SHIFT                   (23U)
+#define LPUARTx_STAT_TDRE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LPUARTx_STAT_TDRE_SHIFT)) & LPUARTx_STAT_TDRE_MASK)
+#define LPUARTx_STAT_TDRE LPUARTx_STAT_TDRE_MASK
+#define LPUARTx_STAT_RAF_MASK                     (0x1000000U)
+#define LPUARTx_STAT_RAF_SHIFT                    (24U)
+#define LPUARTx_STAT_RAF_SET(x)                   (((uint32_t)(((uint32_t)(x)) << LPUARTx_STAT_RAF_SHIFT)) & LPUARTx_STAT_RAF_MASK)
+#define LPUARTx_STAT_RAF LPUARTx_STAT_RAF_MASK
+#define LPUARTx_STAT_LBKDE_MASK                   (0x2000000U)
+#define LPUARTx_STAT_LBKDE_SHIFT                  (25U)
+#define LPUARTx_STAT_LBKDE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << LPUARTx_STAT_LBKDE_SHIFT)) & LPUARTx_STAT_LBKDE_MASK)
+#define LPUARTx_STAT_LBKDE LPUARTx_STAT_LBKDE_MASK
+#define LPUARTx_STAT_BRK13_MASK                   (0x4000000U)
+#define LPUARTx_STAT_BRK13_SHIFT                  (26U)
+#define LPUARTx_STAT_BRK13_SET(x)                 (((uint32_t)(((uint32_t)(x)) << LPUARTx_STAT_BRK13_SHIFT)) & LPUARTx_STAT_BRK13_MASK)
+#define LPUARTx_STAT_BRK13 LPUARTx_STAT_BRK13_MASK
+#define LPUARTx_STAT_RWUID_MASK                   (0x8000000U)
+#define LPUARTx_STAT_RWUID_SHIFT                  (27U)
+#define LPUARTx_STAT_RWUID_SET(x)                 (((uint32_t)(((uint32_t)(x)) << LPUARTx_STAT_RWUID_SHIFT)) & LPUARTx_STAT_RWUID_MASK)
+#define LPUARTx_STAT_RWUID LPUARTx_STAT_RWUID_MASK
+#define LPUARTx_STAT_RXINV_MASK                   (0x10000000U)
+#define LPUARTx_STAT_RXINV_SHIFT                  (28U)
+#define LPUARTx_STAT_RXINV_SET(x)                 (((uint32_t)(((uint32_t)(x)) << LPUARTx_STAT_RXINV_SHIFT)) & LPUARTx_STAT_RXINV_MASK)
+#define LPUARTx_STAT_RXINV LPUARTx_STAT_RXINV_MASK
+#define LPUARTx_STAT_MSBF_MASK                    (0x20000000U)
+#define LPUARTx_STAT_MSBF_SHIFT                   (29U)
+#define LPUARTx_STAT_MSBF_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LPUARTx_STAT_MSBF_SHIFT)) & LPUARTx_STAT_MSBF_MASK)
+#define LPUARTx_STAT_MSBF LPUARTx_STAT_MSBF_MASK
+#define LPUARTx_STAT_RXEDGIF_MASK                 (0x40000000U)
+#define LPUARTx_STAT_RXEDGIF_SHIFT                (30U)
+#define LPUARTx_STAT_RXEDGIF_SET(x)               (((uint32_t)(((uint32_t)(x)) << LPUARTx_STAT_RXEDGIF_SHIFT)) & LPUARTx_STAT_RXEDGIF_MASK)
+#define LPUARTx_STAT_RXEDGIF LPUARTx_STAT_RXEDGIF_MASK
+#define LPUARTx_STAT_LBKDIF_MASK                  (0x80000000U)
+#define LPUARTx_STAT_LBKDIF_SHIFT                 (31U)
+#define LPUARTx_STAT_LBKDIF_SET(x)                (((uint32_t)(((uint32_t)(x)) << LPUARTx_STAT_LBKDIF_SHIFT)) & LPUARTx_STAT_LBKDIF_MASK)
+#define LPUARTx_STAT_LBKDIF LPUARTx_STAT_LBKDIF_MASK
 
 /*! @name CTRL - LPUART Control Register */
-#define LPUART_CTRL_PT_MASK                      (0x1U)
-#define LPUART_CTRL_PT_SHIFT                     (0U)
-#define LPUART_CTRL_PT(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
-#define LPUART_CTRL_PE_MASK                      (0x2U)
-#define LPUART_CTRL_PE_SHIFT                     (1U)
-#define LPUART_CTRL_PE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
-#define LPUART_CTRL_ILT_MASK                     (0x4U)
-#define LPUART_CTRL_ILT_SHIFT                    (2U)
-#define LPUART_CTRL_ILT(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
-#define LPUART_CTRL_WAKE_MASK                    (0x8U)
-#define LPUART_CTRL_WAKE_SHIFT                   (3U)
-#define LPUART_CTRL_WAKE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
-#define LPUART_CTRL_M_MASK                       (0x10U)
-#define LPUART_CTRL_M_SHIFT                      (4U)
-#define LPUART_CTRL_M(x)                         (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
-#define LPUART_CTRL_RSRC_MASK                    (0x20U)
-#define LPUART_CTRL_RSRC_SHIFT                   (5U)
-#define LPUART_CTRL_RSRC(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
-#define LPUART_CTRL_DOZEEN_MASK                  (0x40U)
-#define LPUART_CTRL_DOZEEN_SHIFT                 (6U)
-#define LPUART_CTRL_DOZEEN(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
-#define LPUART_CTRL_LOOPS_MASK                   (0x80U)
-#define LPUART_CTRL_LOOPS_SHIFT                  (7U)
-#define LPUART_CTRL_LOOPS(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
-#define LPUART_CTRL_IDLECFG_MASK                 (0x700U)
-#define LPUART_CTRL_IDLECFG_SHIFT                (8U)
-#define LPUART_CTRL_IDLECFG(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
-#define LPUART_CTRL_MA2IE_MASK                   (0x4000U)
-#define LPUART_CTRL_MA2IE_SHIFT                  (14U)
-#define LPUART_CTRL_MA2IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
-#define LPUART_CTRL_MA1IE_MASK                   (0x8000U)
-#define LPUART_CTRL_MA1IE_SHIFT                  (15U)
-#define LPUART_CTRL_MA1IE(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
-#define LPUART_CTRL_SBK_MASK                     (0x10000U)
-#define LPUART_CTRL_SBK_SHIFT                    (16U)
-#define LPUART_CTRL_SBK(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
-#define LPUART_CTRL_RWU_MASK                     (0x20000U)
-#define LPUART_CTRL_RWU_SHIFT                    (17U)
-#define LPUART_CTRL_RWU(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
-#define LPUART_CTRL_RE_MASK                      (0x40000U)
-#define LPUART_CTRL_RE_SHIFT                     (18U)
-#define LPUART_CTRL_RE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
-#define LPUART_CTRL_TE_MASK                      (0x80000U)
-#define LPUART_CTRL_TE_SHIFT                     (19U)
-#define LPUART_CTRL_TE(x)                        (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
-#define LPUART_CTRL_ILIE_MASK                    (0x100000U)
-#define LPUART_CTRL_ILIE_SHIFT                   (20U)
-#define LPUART_CTRL_ILIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
-#define LPUART_CTRL_RIE_MASK                     (0x200000U)
-#define LPUART_CTRL_RIE_SHIFT                    (21U)
-#define LPUART_CTRL_RIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
-#define LPUART_CTRL_TCIE_MASK                    (0x400000U)
-#define LPUART_CTRL_TCIE_SHIFT                   (22U)
-#define LPUART_CTRL_TCIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
-#define LPUART_CTRL_TIE_MASK                     (0x800000U)
-#define LPUART_CTRL_TIE_SHIFT                    (23U)
-#define LPUART_CTRL_TIE(x)                       (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
-#define LPUART_CTRL_PEIE_MASK                    (0x1000000U)
-#define LPUART_CTRL_PEIE_SHIFT                   (24U)
-#define LPUART_CTRL_PEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
-#define LPUART_CTRL_FEIE_MASK                    (0x2000000U)
-#define LPUART_CTRL_FEIE_SHIFT                   (25U)
-#define LPUART_CTRL_FEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
-#define LPUART_CTRL_NEIE_MASK                    (0x4000000U)
-#define LPUART_CTRL_NEIE_SHIFT                   (26U)
-#define LPUART_CTRL_NEIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
-#define LPUART_CTRL_ORIE_MASK                    (0x8000000U)
-#define LPUART_CTRL_ORIE_SHIFT                   (27U)
-#define LPUART_CTRL_ORIE(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
-#define LPUART_CTRL_TXINV_MASK                   (0x10000000U)
-#define LPUART_CTRL_TXINV_SHIFT                  (28U)
-#define LPUART_CTRL_TXINV(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
-#define LPUART_CTRL_TXDIR_MASK                   (0x20000000U)
-#define LPUART_CTRL_TXDIR_SHIFT                  (29U)
-#define LPUART_CTRL_TXDIR(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
-#define LPUART_CTRL_R9T8_MASK                    (0x40000000U)
-#define LPUART_CTRL_R9T8_SHIFT                   (30U)
-#define LPUART_CTRL_R9T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
-#define LPUART_CTRL_R8T9_MASK                    (0x80000000U)
-#define LPUART_CTRL_R8T9_SHIFT                   (31U)
-#define LPUART_CTRL_R8T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
+#define LPUARTx_CTRL_PT_MASK                      (0x1U)
+#define LPUARTx_CTRL_PT_SHIFT                     (0U)
+#define LPUARTx_CTRL_PT_SET(x)                    (((uint32_t)(((uint32_t)(x)) << LPUARTx_CTRL_PT_SHIFT)) & LPUARTx_CTRL_PT_MASK)
+#define LPUARTx_CTRL_PT LPUARTx_CTRL_PT_MASK
+#define LPUARTx_CTRL_PE_MASK                      (0x2U)
+#define LPUARTx_CTRL_PE_SHIFT                     (1U)
+#define LPUARTx_CTRL_PE_SET(x)                    (((uint32_t)(((uint32_t)(x)) << LPUARTx_CTRL_PE_SHIFT)) & LPUARTx_CTRL_PE_MASK)
+#define LPUARTx_CTRL_PE LPUARTx_CTRL_PE_MASK
+#define LPUARTx_CTRL_ILT_MASK                     (0x4U)
+#define LPUARTx_CTRL_ILT_SHIFT                    (2U)
+#define LPUARTx_CTRL_ILT_SET(x)                   (((uint32_t)(((uint32_t)(x)) << LPUARTx_CTRL_ILT_SHIFT)) & LPUARTx_CTRL_ILT_MASK)
+#define LPUARTx_CTRL_ILT LPUARTx_CTRL_ILT_MASK
+#define LPUARTx_CTRL_WAKE_MASK                    (0x8U)
+#define LPUARTx_CTRL_WAKE_SHIFT                   (3U)
+#define LPUARTx_CTRL_WAKE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LPUARTx_CTRL_WAKE_SHIFT)) & LPUARTx_CTRL_WAKE_MASK)
+#define LPUARTx_CTRL_WAKE LPUARTx_CTRL_WAKE_MASK
+#define LPUARTx_CTRL_M_MASK                       (0x10U)
+#define LPUARTx_CTRL_M_SHIFT                      (4U)
+#define LPUARTx_CTRL_M_SET(x)                     (((uint32_t)(((uint32_t)(x)) << LPUARTx_CTRL_M_SHIFT)) & LPUARTx_CTRL_M_MASK)
+#define LPUARTx_CTRL_M LPUARTx_CTRL_M_MASK
+#define LPUARTx_CTRL_RSRC_MASK                    (0x20U)
+#define LPUARTx_CTRL_RSRC_SHIFT                   (5U)
+#define LPUARTx_CTRL_RSRC_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LPUARTx_CTRL_RSRC_SHIFT)) & LPUARTx_CTRL_RSRC_MASK)
+#define LPUARTx_CTRL_RSRC LPUARTx_CTRL_RSRC_MASK
+#define LPUARTx_CTRL_DOZEEN_MASK                  (0x40U)
+#define LPUARTx_CTRL_DOZEEN_SHIFT                 (6U)
+#define LPUARTx_CTRL_DOZEEN_SET(x)                (((uint32_t)(((uint32_t)(x)) << LPUARTx_CTRL_DOZEEN_SHIFT)) & LPUARTx_CTRL_DOZEEN_MASK)
+#define LPUARTx_CTRL_DOZEEN LPUARTx_CTRL_DOZEEN_MASK
+#define LPUARTx_CTRL_LOOPS_MASK                   (0x80U)
+#define LPUARTx_CTRL_LOOPS_SHIFT                  (7U)
+#define LPUARTx_CTRL_LOOPS_SET(x)                 (((uint32_t)(((uint32_t)(x)) << LPUARTx_CTRL_LOOPS_SHIFT)) & LPUARTx_CTRL_LOOPS_MASK)
+#define LPUARTx_CTRL_LOOPS LPUARTx_CTRL_LOOPS_MASK
+#define LPUARTx_CTRL_IDLECFG_MASK                 (0x700U)
+#define LPUARTx_CTRL_IDLECFG_SHIFT                (8U)
+#define LPUARTx_CTRL_IDLECFG_SET(x)               (((uint32_t)(((uint32_t)(x)) << LPUARTx_CTRL_IDLECFG_SHIFT)) & LPUARTx_CTRL_IDLECFG_MASK)
+#define LPUARTx_CTRL_IDLECFG LPUARTx_CTRL_IDLECFG_MASK
+#define LPUARTx_CTRL_MA2IE_MASK                   (0x4000U)
+#define LPUARTx_CTRL_MA2IE_SHIFT                  (14U)
+#define LPUARTx_CTRL_MA2IE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << LPUARTx_CTRL_MA2IE_SHIFT)) & LPUARTx_CTRL_MA2IE_MASK)
+#define LPUARTx_CTRL_MA2IE LPUARTx_CTRL_MA2IE_MASK
+#define LPUARTx_CTRL_MA1IE_MASK                   (0x8000U)
+#define LPUARTx_CTRL_MA1IE_SHIFT                  (15U)
+#define LPUARTx_CTRL_MA1IE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << LPUARTx_CTRL_MA1IE_SHIFT)) & LPUARTx_CTRL_MA1IE_MASK)
+#define LPUARTx_CTRL_MA1IE LPUARTx_CTRL_MA1IE_MASK
+#define LPUARTx_CTRL_SBK_MASK                     (0x10000U)
+#define LPUARTx_CTRL_SBK_SHIFT                    (16U)
+#define LPUARTx_CTRL_SBK_SET(x)                   (((uint32_t)(((uint32_t)(x)) << LPUARTx_CTRL_SBK_SHIFT)) & LPUARTx_CTRL_SBK_MASK)
+#define LPUARTx_CTRL_SBK LPUARTx_CTRL_SBK_MASK
+#define LPUARTx_CTRL_RWU_MASK                     (0x20000U)
+#define LPUARTx_CTRL_RWU_SHIFT                    (17U)
+#define LPUARTx_CTRL_RWU_SET(x)                   (((uint32_t)(((uint32_t)(x)) << LPUARTx_CTRL_RWU_SHIFT)) & LPUARTx_CTRL_RWU_MASK)
+#define LPUARTx_CTRL_RWU LPUARTx_CTRL_RWU_MASK
+#define LPUARTx_CTRL_RE_MASK                      (0x40000U)
+#define LPUARTx_CTRL_RE_SHIFT                     (18U)
+#define LPUARTx_CTRL_RE_SET(x)                    (((uint32_t)(((uint32_t)(x)) << LPUARTx_CTRL_RE_SHIFT)) & LPUARTx_CTRL_RE_MASK)
+#define LPUARTx_CTRL_RE LPUARTx_CTRL_RE_MASK
+#define LPUARTx_CTRL_TE_MASK                      (0x80000U)
+#define LPUARTx_CTRL_TE_SHIFT                     (19U)
+#define LPUARTx_CTRL_TE_SET(x)                    (((uint32_t)(((uint32_t)(x)) << LPUARTx_CTRL_TE_SHIFT)) & LPUARTx_CTRL_TE_MASK)
+#define LPUARTx_CTRL_TE LPUARTx_CTRL_TE_MASK
+#define LPUARTx_CTRL_ILIE_MASK                    (0x100000U)
+#define LPUARTx_CTRL_ILIE_SHIFT                   (20U)
+#define LPUARTx_CTRL_ILIE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LPUARTx_CTRL_ILIE_SHIFT)) & LPUARTx_CTRL_ILIE_MASK)
+#define LPUARTx_CTRL_ILIE LPUARTx_CTRL_ILIE_MASK
+#define LPUARTx_CTRL_RIE_MASK                     (0x200000U)
+#define LPUARTx_CTRL_RIE_SHIFT                    (21U)
+#define LPUARTx_CTRL_RIE_SET(x)                   (((uint32_t)(((uint32_t)(x)) << LPUARTx_CTRL_RIE_SHIFT)) & LPUARTx_CTRL_RIE_MASK)
+#define LPUARTx_CTRL_RIE LPUARTx_CTRL_RIE_MASK
+#define LPUARTx_CTRL_TCIE_MASK                    (0x400000U)
+#define LPUARTx_CTRL_TCIE_SHIFT                   (22U)
+#define LPUARTx_CTRL_TCIE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LPUARTx_CTRL_TCIE_SHIFT)) & LPUARTx_CTRL_TCIE_MASK)
+#define LPUARTx_CTRL_TCIE LPUARTx_CTRL_TCIE_MASK
+#define LPUARTx_CTRL_TIE_MASK                     (0x800000U)
+#define LPUARTx_CTRL_TIE_SHIFT                    (23U)
+#define LPUARTx_CTRL_TIE_SET(x)                   (((uint32_t)(((uint32_t)(x)) << LPUARTx_CTRL_TIE_SHIFT)) & LPUARTx_CTRL_TIE_MASK)
+#define LPUARTx_CTRL_TIE LPUARTx_CTRL_TIE_MASK
+#define LPUARTx_CTRL_PEIE_MASK                    (0x1000000U)
+#define LPUARTx_CTRL_PEIE_SHIFT                   (24U)
+#define LPUARTx_CTRL_PEIE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LPUARTx_CTRL_PEIE_SHIFT)) & LPUARTx_CTRL_PEIE_MASK)
+#define LPUARTx_CTRL_PEIE LPUARTx_CTRL_PEIE_MASK
+#define LPUARTx_CTRL_FEIE_MASK                    (0x2000000U)
+#define LPUARTx_CTRL_FEIE_SHIFT                   (25U)
+#define LPUARTx_CTRL_FEIE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LPUARTx_CTRL_FEIE_SHIFT)) & LPUARTx_CTRL_FEIE_MASK)
+#define LPUARTx_CTRL_FEIE LPUARTx_CTRL_FEIE_MASK
+#define LPUARTx_CTRL_NEIE_MASK                    (0x4000000U)
+#define LPUARTx_CTRL_NEIE_SHIFT                   (26U)
+#define LPUARTx_CTRL_NEIE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LPUARTx_CTRL_NEIE_SHIFT)) & LPUARTx_CTRL_NEIE_MASK)
+#define LPUARTx_CTRL_NEIE LPUARTx_CTRL_NEIE_MASK
+#define LPUARTx_CTRL_ORIE_MASK                    (0x8000000U)
+#define LPUARTx_CTRL_ORIE_SHIFT                   (27U)
+#define LPUARTx_CTRL_ORIE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LPUARTx_CTRL_ORIE_SHIFT)) & LPUARTx_CTRL_ORIE_MASK)
+#define LPUARTx_CTRL_ORIE LPUARTx_CTRL_ORIE_MASK
+#define LPUARTx_CTRL_TXINV_MASK                   (0x10000000U)
+#define LPUARTx_CTRL_TXINV_SHIFT                  (28U)
+#define LPUARTx_CTRL_TXINV_SET(x)                 (((uint32_t)(((uint32_t)(x)) << LPUARTx_CTRL_TXINV_SHIFT)) & LPUARTx_CTRL_TXINV_MASK)
+#define LPUARTx_CTRL_TXINV LPUARTx_CTRL_TXINV_MASK
+#define LPUARTx_CTRL_TXDIR_MASK                   (0x20000000U)
+#define LPUARTx_CTRL_TXDIR_SHIFT                  (29U)
+#define LPUARTx_CTRL_TXDIR_SET(x)                 (((uint32_t)(((uint32_t)(x)) << LPUARTx_CTRL_TXDIR_SHIFT)) & LPUARTx_CTRL_TXDIR_MASK)
+#define LPUARTx_CTRL_TXDIR LPUARTx_CTRL_TXDIR_MASK
+#define LPUARTx_CTRL_R9T8_MASK                    (0x40000000U)
+#define LPUARTx_CTRL_R9T8_SHIFT                   (30U)
+#define LPUARTx_CTRL_R9T8_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LPUARTx_CTRL_R9T8_SHIFT)) & LPUARTx_CTRL_R9T8_MASK)
+#define LPUARTx_CTRL_R9T8 LPUARTx_CTRL_R9T8_MASK
+#define LPUARTx_CTRL_R8T9_MASK                    (0x80000000U)
+#define LPUARTx_CTRL_R8T9_SHIFT                   (31U)
+#define LPUARTx_CTRL_R8T9_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LPUARTx_CTRL_R8T9_SHIFT)) & LPUARTx_CTRL_R8T9_MASK)
+#define LPUARTx_CTRL_R8T9 LPUARTx_CTRL_R8T9_MASK
 
 /*! @name DATA - LPUART Data Register */
-#define LPUART_DATA_R0T0_MASK                    (0x1U)
-#define LPUART_DATA_R0T0_SHIFT                   (0U)
-#define LPUART_DATA_R0T0(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
-#define LPUART_DATA_R1T1_MASK                    (0x2U)
-#define LPUART_DATA_R1T1_SHIFT                   (1U)
-#define LPUART_DATA_R1T1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
-#define LPUART_DATA_R2T2_MASK                    (0x4U)
-#define LPUART_DATA_R2T2_SHIFT                   (2U)
-#define LPUART_DATA_R2T2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
-#define LPUART_DATA_R3T3_MASK                    (0x8U)
-#define LPUART_DATA_R3T3_SHIFT                   (3U)
-#define LPUART_DATA_R3T3(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
-#define LPUART_DATA_R4T4_MASK                    (0x10U)
-#define LPUART_DATA_R4T4_SHIFT                   (4U)
-#define LPUART_DATA_R4T4(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
-#define LPUART_DATA_R5T5_MASK                    (0x20U)
-#define LPUART_DATA_R5T5_SHIFT                   (5U)
-#define LPUART_DATA_R5T5(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
-#define LPUART_DATA_R6T6_MASK                    (0x40U)
-#define LPUART_DATA_R6T6_SHIFT                   (6U)
-#define LPUART_DATA_R6T6(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
-#define LPUART_DATA_R7T7_MASK                    (0x80U)
-#define LPUART_DATA_R7T7_SHIFT                   (7U)
-#define LPUART_DATA_R7T7(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
-#define LPUART_DATA_R8T8_MASK                    (0x100U)
-#define LPUART_DATA_R8T8_SHIFT                   (8U)
-#define LPUART_DATA_R8T8(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
-#define LPUART_DATA_R9T9_MASK                    (0x200U)
-#define LPUART_DATA_R9T9_SHIFT                   (9U)
-#define LPUART_DATA_R9T9(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
-#define LPUART_DATA_IDLINE_MASK                  (0x800U)
-#define LPUART_DATA_IDLINE_SHIFT                 (11U)
-#define LPUART_DATA_IDLINE(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
-#define LPUART_DATA_RXEMPT_MASK                  (0x1000U)
-#define LPUART_DATA_RXEMPT_SHIFT                 (12U)
-#define LPUART_DATA_RXEMPT(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
-#define LPUART_DATA_FRETSC_MASK                  (0x2000U)
-#define LPUART_DATA_FRETSC_SHIFT                 (13U)
-#define LPUART_DATA_FRETSC(x)                    (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
-#define LPUART_DATA_PARITYE_MASK                 (0x4000U)
-#define LPUART_DATA_PARITYE_SHIFT                (14U)
-#define LPUART_DATA_PARITYE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
-#define LPUART_DATA_NOISY_MASK                   (0x8000U)
-#define LPUART_DATA_NOISY_SHIFT                  (15U)
-#define LPUART_DATA_NOISY(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
+#define LPUARTx_DATA_R0T0_MASK                    (0x1U)
+#define LPUARTx_DATA_R0T0_SHIFT                   (0U)
+#define LPUARTx_DATA_R0T0_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LPUARTx_DATA_R0T0_SHIFT)) & LPUARTx_DATA_R0T0_MASK)
+#define LPUARTx_DATA_R0T0 LPUARTx_DATA_R0T0_MASK
+#define LPUARTx_DATA_R1T1_MASK                    (0x2U)
+#define LPUARTx_DATA_R1T1_SHIFT                   (1U)
+#define LPUARTx_DATA_R1T1_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LPUARTx_DATA_R1T1_SHIFT)) & LPUARTx_DATA_R1T1_MASK)
+#define LPUARTx_DATA_R1T1 LPUARTx_DATA_R1T1_MASK
+#define LPUARTx_DATA_R2T2_MASK                    (0x4U)
+#define LPUARTx_DATA_R2T2_SHIFT                   (2U)
+#define LPUARTx_DATA_R2T2_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LPUARTx_DATA_R2T2_SHIFT)) & LPUARTx_DATA_R2T2_MASK)
+#define LPUARTx_DATA_R2T2 LPUARTx_DATA_R2T2_MASK
+#define LPUARTx_DATA_R3T3_MASK                    (0x8U)
+#define LPUARTx_DATA_R3T3_SHIFT                   (3U)
+#define LPUARTx_DATA_R3T3_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LPUARTx_DATA_R3T3_SHIFT)) & LPUARTx_DATA_R3T3_MASK)
+#define LPUARTx_DATA_R3T3 LPUARTx_DATA_R3T3_MASK
+#define LPUARTx_DATA_R4T4_MASK                    (0x10U)
+#define LPUARTx_DATA_R4T4_SHIFT                   (4U)
+#define LPUARTx_DATA_R4T4_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LPUARTx_DATA_R4T4_SHIFT)) & LPUARTx_DATA_R4T4_MASK)
+#define LPUARTx_DATA_R4T4 LPUARTx_DATA_R4T4_MASK
+#define LPUARTx_DATA_R5T5_MASK                    (0x20U)
+#define LPUARTx_DATA_R5T5_SHIFT                   (5U)
+#define LPUARTx_DATA_R5T5_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LPUARTx_DATA_R5T5_SHIFT)) & LPUARTx_DATA_R5T5_MASK)
+#define LPUARTx_DATA_R5T5 LPUARTx_DATA_R5T5_MASK
+#define LPUARTx_DATA_R6T6_MASK                    (0x40U)
+#define LPUARTx_DATA_R6T6_SHIFT                   (6U)
+#define LPUARTx_DATA_R6T6_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LPUARTx_DATA_R6T6_SHIFT)) & LPUARTx_DATA_R6T6_MASK)
+#define LPUARTx_DATA_R6T6 LPUARTx_DATA_R6T6_MASK
+#define LPUARTx_DATA_R7T7_MASK                    (0x80U)
+#define LPUARTx_DATA_R7T7_SHIFT                   (7U)
+#define LPUARTx_DATA_R7T7_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LPUARTx_DATA_R7T7_SHIFT)) & LPUARTx_DATA_R7T7_MASK)
+#define LPUARTx_DATA_R7T7 LPUARTx_DATA_R7T7_MASK
+#define LPUARTx_DATA_R8T8_MASK                    (0x100U)
+#define LPUARTx_DATA_R8T8_SHIFT                   (8U)
+#define LPUARTx_DATA_R8T8_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LPUARTx_DATA_R8T8_SHIFT)) & LPUARTx_DATA_R8T8_MASK)
+#define LPUARTx_DATA_R8T8 LPUARTx_DATA_R8T8_MASK
+#define LPUARTx_DATA_R9T9_MASK                    (0x200U)
+#define LPUARTx_DATA_R9T9_SHIFT                   (9U)
+#define LPUARTx_DATA_R9T9_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LPUARTx_DATA_R9T9_SHIFT)) & LPUARTx_DATA_R9T9_MASK)
+#define LPUARTx_DATA_R9T9 LPUARTx_DATA_R9T9_MASK
+#define LPUARTx_DATA_IDLINE_MASK                  (0x800U)
+#define LPUARTx_DATA_IDLINE_SHIFT                 (11U)
+#define LPUARTx_DATA_IDLINE_SET(x)                (((uint32_t)(((uint32_t)(x)) << LPUARTx_DATA_IDLINE_SHIFT)) & LPUARTx_DATA_IDLINE_MASK)
+#define LPUARTx_DATA_IDLINE LPUARTx_DATA_IDLINE_MASK
+#define LPUARTx_DATA_RXEMPT_MASK                  (0x1000U)
+#define LPUARTx_DATA_RXEMPT_SHIFT                 (12U)
+#define LPUARTx_DATA_RXEMPT_SET(x)                (((uint32_t)(((uint32_t)(x)) << LPUARTx_DATA_RXEMPT_SHIFT)) & LPUARTx_DATA_RXEMPT_MASK)
+#define LPUARTx_DATA_RXEMPT LPUARTx_DATA_RXEMPT_MASK
+#define LPUARTx_DATA_FRETSC_MASK                  (0x2000U)
+#define LPUARTx_DATA_FRETSC_SHIFT                 (13U)
+#define LPUARTx_DATA_FRETSC_SET(x)                (((uint32_t)(((uint32_t)(x)) << LPUARTx_DATA_FRETSC_SHIFT)) & LPUARTx_DATA_FRETSC_MASK)
+#define LPUARTx_DATA_FRETSC LPUARTx_DATA_FRETSC_MASK
+#define LPUARTx_DATA_PARITYE_MASK                 (0x4000U)
+#define LPUARTx_DATA_PARITYE_SHIFT                (14U)
+#define LPUARTx_DATA_PARITYE_SET(x)               (((uint32_t)(((uint32_t)(x)) << LPUARTx_DATA_PARITYE_SHIFT)) & LPUARTx_DATA_PARITYE_MASK)
+#define LPUARTx_DATA_PARITYE LPUARTx_DATA_PARITYE_MASK
+#define LPUARTx_DATA_NOISY_MASK                   (0x8000U)
+#define LPUARTx_DATA_NOISY_SHIFT                  (15U)
+#define LPUARTx_DATA_NOISY_SET(x)                 (((uint32_t)(((uint32_t)(x)) << LPUARTx_DATA_NOISY_SHIFT)) & LPUARTx_DATA_NOISY_MASK)
+#define LPUARTx_DATA_NOISY LPUARTx_DATA_NOISY_MASK
 
 /*! @name MATCH - LPUART Match Address Register */
-#define LPUART_MATCH_MA1_MASK                    (0x3FFU)
-#define LPUART_MATCH_MA1_SHIFT                   (0U)
-#define LPUART_MATCH_MA1(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
-#define LPUART_MATCH_MA2_MASK                    (0x3FF0000U)
-#define LPUART_MATCH_MA2_SHIFT                   (16U)
-#define LPUART_MATCH_MA2(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
+#define LPUARTx_MATCH_MA1_MASK                    (0x3FFU)
+#define LPUARTx_MATCH_MA1_SHIFT                   (0U)
+#define LPUARTx_MATCH_MA1_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LPUARTx_MATCH_MA1_SHIFT)) & LPUARTx_MATCH_MA1_MASK)
+#define LPUARTx_MATCH_MA1 LPUARTx_MATCH_MA1_MASK
+#define LPUARTx_MATCH_MA2_MASK                    (0x3FF0000U)
+#define LPUARTx_MATCH_MA2_SHIFT                   (16U)
+#define LPUARTx_MATCH_MA2_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LPUARTx_MATCH_MA2_SHIFT)) & LPUARTx_MATCH_MA2_MASK)
+#define LPUARTx_MATCH_MA2 LPUARTx_MATCH_MA2_MASK
 
 /*! @name MODIR - LPUART Modem IrDA Register */
-#define LPUART_MODIR_TXCTSE_MASK                 (0x1U)
-#define LPUART_MODIR_TXCTSE_SHIFT                (0U)
-#define LPUART_MODIR_TXCTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
-#define LPUART_MODIR_TXRTSE_MASK                 (0x2U)
-#define LPUART_MODIR_TXRTSE_SHIFT                (1U)
-#define LPUART_MODIR_TXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
-#define LPUART_MODIR_TXRTSPOL_MASK               (0x4U)
-#define LPUART_MODIR_TXRTSPOL_SHIFT              (2U)
-#define LPUART_MODIR_TXRTSPOL(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
-#define LPUART_MODIR_RXRTSE_MASK                 (0x8U)
-#define LPUART_MODIR_RXRTSE_SHIFT                (3U)
-#define LPUART_MODIR_RXRTSE(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
-#define LPUART_MODIR_TXCTSC_MASK                 (0x10U)
-#define LPUART_MODIR_TXCTSC_SHIFT                (4U)
-#define LPUART_MODIR_TXCTSC(x)                   (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
-#define LPUART_MODIR_TXCTSSRC_MASK               (0x20U)
-#define LPUART_MODIR_TXCTSSRC_SHIFT              (5U)
-#define LPUART_MODIR_TXCTSSRC(x)                 (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
-#define LPUART_MODIR_TNP_MASK                    (0x30000U)
-#define LPUART_MODIR_TNP_SHIFT                   (16U)
-#define LPUART_MODIR_TNP(x)                      (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
-#define LPUART_MODIR_IREN_MASK                   (0x40000U)
-#define LPUART_MODIR_IREN_SHIFT                  (18U)
-#define LPUART_MODIR_IREN(x)                     (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
+#define LPUARTx_MODIR_TXCTSE_MASK                 (0x1U)
+#define LPUARTx_MODIR_TXCTSE_SHIFT                (0U)
+#define LPUARTx_MODIR_TXCTSE_SET(x)               (((uint32_t)(((uint32_t)(x)) << LPUARTx_MODIR_TXCTSE_SHIFT)) & LPUARTx_MODIR_TXCTSE_MASK)
+#define LPUARTx_MODIR_TXCTSE LPUARTx_MODIR_TXCTSE_MASK
+#define LPUARTx_MODIR_TXRTSE_MASK                 (0x2U)
+#define LPUARTx_MODIR_TXRTSE_SHIFT                (1U)
+#define LPUARTx_MODIR_TXRTSE_SET(x)               (((uint32_t)(((uint32_t)(x)) << LPUARTx_MODIR_TXRTSE_SHIFT)) & LPUARTx_MODIR_TXRTSE_MASK)
+#define LPUARTx_MODIR_TXRTSE LPUARTx_MODIR_TXRTSE_MASK
+#define LPUARTx_MODIR_TXRTSPOL_MASK               (0x4U)
+#define LPUARTx_MODIR_TXRTSPOL_SHIFT              (2U)
+#define LPUARTx_MODIR_TXRTSPOL_SET(x)             (((uint32_t)(((uint32_t)(x)) << LPUARTx_MODIR_TXRTSPOL_SHIFT)) & LPUARTx_MODIR_TXRTSPOL_MASK)
+#define LPUARTx_MODIR_TXRTSPOL LPUARTx_MODIR_TXRTSPOL_MASK
+#define LPUARTx_MODIR_RXRTSE_MASK                 (0x8U)
+#define LPUARTx_MODIR_RXRTSE_SHIFT                (3U)
+#define LPUARTx_MODIR_RXRTSE_SET(x)               (((uint32_t)(((uint32_t)(x)) << LPUARTx_MODIR_RXRTSE_SHIFT)) & LPUARTx_MODIR_RXRTSE_MASK)
+#define LPUARTx_MODIR_RXRTSE LPUARTx_MODIR_RXRTSE_MASK
+#define LPUARTx_MODIR_TXCTSC_MASK                 (0x10U)
+#define LPUARTx_MODIR_TXCTSC_SHIFT                (4U)
+#define LPUARTx_MODIR_TXCTSC_SET(x)               (((uint32_t)(((uint32_t)(x)) << LPUARTx_MODIR_TXCTSC_SHIFT)) & LPUARTx_MODIR_TXCTSC_MASK)
+#define LPUARTx_MODIR_TXCTSC LPUARTx_MODIR_TXCTSC_MASK
+#define LPUARTx_MODIR_TXCTSSRC_MASK               (0x20U)
+#define LPUARTx_MODIR_TXCTSSRC_SHIFT              (5U)
+#define LPUARTx_MODIR_TXCTSSRC_SET(x)             (((uint32_t)(((uint32_t)(x)) << LPUARTx_MODIR_TXCTSSRC_SHIFT)) & LPUARTx_MODIR_TXCTSSRC_MASK)
+#define LPUARTx_MODIR_TXCTSSRC LPUARTx_MODIR_TXCTSSRC_MASK
+#define LPUARTx_MODIR_TNP_MASK                    (0x30000U)
+#define LPUARTx_MODIR_TNP_SHIFT                   (16U)
+#define LPUARTx_MODIR_TNP_SET(x)                  (((uint32_t)(((uint32_t)(x)) << LPUARTx_MODIR_TNP_SHIFT)) & LPUARTx_MODIR_TNP_MASK)
+#define LPUARTx_MODIR_TNP LPUARTx_MODIR_TNP_MASK
+#define LPUARTx_MODIR_IREN_MASK                   (0x40000U)
+#define LPUARTx_MODIR_IREN_SHIFT                  (18U)
+#define LPUARTx_MODIR_IREN_SET(x)                 (((uint32_t)(((uint32_t)(x)) << LPUARTx_MODIR_IREN_SHIFT)) & LPUARTx_MODIR_IREN_MASK)
+#define LPUARTx_MODIR_IREN LPUARTx_MODIR_IREN_MASK
 
 
 /*!
  * @}
- */ /* end of group LPUART_Register_Masks */
+ */ /* end of group LPUARTx_Register_Masks */
 
 
 /* LPUART - Peripheral instance base addresses */
 /** Peripheral LPUART0 base address */
 #define LPUART0_BASE                             (0x400C4000u)
 /** Peripheral LPUART0 base pointer */
-#define LPUART0                                  ((LPUART_Type *)LPUART0_BASE)
+#define LPUART0                                  ((LPUART_TypeDef *)LPUART0_BASE)
 /** Array initializer of LPUART peripheral base addresses */
-#define LPUART_BASE_ADDRS                        { LPUART0_BASE }
+#define LPUARTx_BASE_ADDRS                        { LPUART0_BASE }
 /** Array initializer of LPUART peripheral base pointers */
-#define LPUART_BASE_PTRS                         { LPUART0 }
+#define LPUARTx_BASE_PTRS                         { LPUART0 }
 /** Interrupt vectors for the LPUART peripheral type */
-#define LPUART_RX_TX_IRQS                        { LPUART0_IRQn }
-#define LPUART_ERR_IRQS                          { LPUART0_IRQn }
+#define LPUARTx_RX_TX_IRQS                        { LPUART0_IRQn }
+#define LPUARTx_ERR_IRQS                          { LPUART0_IRQn }
 
 /*!
  * @}
- */ /* end of group LPUART_Peripheral_Access_Layer */
+ */ /* end of group LPUARTx_Peripheral_Access_Layer */
 
 
 /* ----------------------------------------------------------------------------
@@ -9413,7 +11460,7 @@ typedef struct {
   __IO uint8_t C11;                                /**< MCG Control 11 Register, offset: 0x10 */
        uint8_t RESERVED_3[1];
   __I  uint8_t S2;                                 /**< MCG Status 2 Register, offset: 0x12 */
-} MCG_Type;
+} MCG_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- MCG Register Masks
@@ -9427,20 +11474,24 @@ typedef struct {
 /*! @name C1 - MCG Control 1 Register */
 #define MCG_C1_IREFSTEN_MASK                     (0x1U)
 #define MCG_C1_IREFSTEN_SHIFT                    (0U)
-#define MCG_C1_IREFSTEN(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
+#define MCG_C1_IREFSTEN_SET(x)                   (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
+#define MCG_C1_IREFSTEN MCG_C1_IREFSTEN_MASK
 #define MCG_C1_IRCLKEN_MASK                      (0x2U)
 #define MCG_C1_IRCLKEN_SHIFT                     (1U)
 #define MCG_C1_IRCLKEN_SET(x)                    (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
 #define MCG_C1_IRCLKEN                           MCG_C1_IRCLKEN_SET(1)
 #define MCG_C1_IREFS_MASK                        (0x4U)
 #define MCG_C1_IREFS_SHIFT                       (2U)
-#define MCG_C1_IREFS(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
+#define MCG_C1_IREFS_SET(x)                      (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
+#define MCG_C1_IREFS MCG_C1_IREFS_MASK
 #define MCG_C1_FRDIV_MASK                        (0x38U)
 #define MCG_C1_FRDIV_SHIFT                       (3U)
-#define MCG_C1_FRDIV(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
+#define MCG_C1_FRDIV_SET(x)                      (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
+#define MCG_C1_FRDIV MCG_C1_FRDIV_MASK
 #define MCG_C1_CLKS_MASK                         (0xC0U)
 #define MCG_C1_CLKS_SHIFT                        (6U)
-#define MCG_C1_CLKS(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
+#define MCG_C1_CLKS_SET(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
+#define MCG_C1_CLKS MCG_C1_CLKS_MASK
 
 /*! @name C2 - MCG Control 2 Register */
 #define MCG_C2_IRCS_MASK                         (0x1U)
@@ -9449,7 +11500,8 @@ typedef struct {
 #define MCG_C2_IRCS                              MCG_C2_IRCS_SET(1)
 #define MCG_C2_LP_MASK                           (0x2U)
 #define MCG_C2_LP_SHIFT                          (1U)
-#define MCG_C2_LP(x)                             (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
+#define MCG_C2_LP_SET(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
+#define MCG_C2_LP MCG_C2_LP_MASK
 #define MCG_C2_EREFS_MASK                        (0x4U)
 #define MCG_C2_EREFS_SHIFT                       (2U)
 #define MCG_C2_EREFS_SET(x)                      (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK)
@@ -9457,13 +11509,16 @@ typedef struct {
 #define MCG_C2_EREFS0                            MCG_C2_EREFS_SET(1)
 #define MCG_C2_HGO_MASK                          (0x8U)
 #define MCG_C2_HGO_SHIFT                         (3U)
-#define MCG_C2_HGO(x)                            (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK)
+#define MCG_C2_HGO_SET(x)                        (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK)
+#define MCG_C2_HGO MCG_C2_HGO_MASK
 #define MCG_C2_RANGE_MASK                        (0x30U)
 #define MCG_C2_RANGE_SHIFT                       (4U)
-#define MCG_C2_RANGE(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK)
+#define MCG_C2_RANGE_SET(x)                      (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK)
+#define MCG_C2_RANGE MCG_C2_RANGE_MASK
 #define MCG_C2_FCFTRIM_MASK                      (0x40U)
 #define MCG_C2_FCFTRIM_SHIFT                     (6U)
-#define MCG_C2_FCFTRIM(x)                        (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK)
+#define MCG_C2_FCFTRIM_SET(x)                    (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK)
+#define MCG_C2_FCFTRIM MCG_C2_FCFTRIM_MASK
 #define MCG_C2_LOCRE0_MASK                       (0x80U)
 #define MCG_C2_LOCRE0_SHIFT                      (7U)
 #define MCG_C2_LOCRE0_SET(x)                     (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
@@ -9472,18 +11527,21 @@ typedef struct {
 /*! @name C3 - MCG Control 3 Register */
 #define MCG_C3_SCTRIM_MASK                       (0xFFU)
 #define MCG_C3_SCTRIM_SHIFT                      (0U)
-#define MCG_C3_SCTRIM(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
+#define MCG_C3_SCTRIM_SET(x)                     (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
+#define MCG_C3_SCTRIM MCG_C3_SCTRIM_MASK
 
 /*! @name C4 - MCG Control 4 Register */
 #define MCG_C4_SCFTRIM_MASK                      (0x1U)
 #define MCG_C4_SCFTRIM_SHIFT                     (0U)
-#define MCG_C4_SCFTRIM(x)                        (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
+#define MCG_C4_SCFTRIM_SET(x)                    (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
+#define MCG_C4_SCFTRIM MCG_C4_SCFTRIM_MASK
 #define MCG_C4_FCTRIM_MASK                       (0x1EU)
 #define MCG_C4_FCTRIM_SHIFT                      (1U)
-#define MCG_C4_FCTRIM(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
+#define MCG_C4_FCTRIM_SET(x)                     (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
+#define MCG_C4_FCTRIM MCG_C4_FCTRIM_MASK
 #define MCG_C4_DRST_DRS_MASK                     (0x60U)
 #define MCG_C4_DRST_DRS_SHIFT                    (5U)
-#define MCG_C4_DRST_DRS(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
+#define MCG_C4_DRST_DRS(x)                   (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
 #define MCG_C4_DMX32_MASK                        (0x80U)
 #define MCG_C4_DMX32_SHIFT                       (7U)
 #define MCG_C4_DMX32_SET(x)                      (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
@@ -9492,40 +11550,48 @@ typedef struct {
 /*! @name C5 - MCG Control 5 Register */
 #define MCG_C5_PRDIV_MASK                        (0x7U)
 #define MCG_C5_PRDIV_SHIFT                       (0U)
-#define MCG_C5_PRDIV(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV_SHIFT)) & MCG_C5_PRDIV_MASK)
+#define MCG_C5_PRDIV_SET(x)                      (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV_SHIFT)) & MCG_C5_PRDIV_MASK)
+#define MCG_C5_PRDIV MCG_C5_PRDIV_MASK
 #define MCG_C5_PLLSTEN_MASK                      (0x20U)
 #define MCG_C5_PLLSTEN_SHIFT                     (5U)
-#define MCG_C5_PLLSTEN(x)                        (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN_SHIFT)) & MCG_C5_PLLSTEN_MASK)
+#define MCG_C5_PLLSTEN_SET(x)                    (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN_SHIFT)) & MCG_C5_PLLSTEN_MASK)
+#define MCG_C5_PLLSTEN MCG_C5_PLLSTEN_MASK
 #define MCG_C5_PLLCLKEN_MASK                     (0x40U)
 #define MCG_C5_PLLCLKEN_SHIFT                    (6U)
-#define MCG_C5_PLLCLKEN(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN_SHIFT)) & MCG_C5_PLLCLKEN_MASK)
+#define MCG_C5_PLLCLKEN_SET(x)                   (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN_SHIFT)) & MCG_C5_PLLCLKEN_MASK)
+#define MCG_C5_PLLCLKEN MCG_C5_PLLCLKEN_MASK
 
 /*! @name C6 - MCG Control 6 Register */
 #define MCG_C6_VDIV_MASK                         (0x1FU)
 #define MCG_C6_VDIV_SHIFT                        (0U)
-#define MCG_C6_VDIV(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV_SHIFT)) & MCG_C6_VDIV_MASK)
+#define MCG_C6_VDIV_SET(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV_SHIFT)) & MCG_C6_VDIV_MASK)
+#define MCG_C6_VDIV MCG_C6_VDIV_MASK
 #define MCG_C6_CME0_MASK                         (0x20U)
 #define MCG_C6_CME0_SHIFT                        (5U)
-#define MCG_C6_CME0(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)
+#define MCG_C6_CME0_SET(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)
+#define MCG_C6_CME0 MCG_C6_CME0_MASK
 #define MCG_C6_PLLS_MASK                         (0x40U)
 #define MCG_C6_PLLS_SHIFT                        (6U)
 #define MCG_C6_PLLS_SET(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)
 #define MCG_C6_PLLS                              MCG_C6_PLLS_SET(1)
 #define MCG_C6_LOLIE0_MASK                       (0x80U)
 #define MCG_C6_LOLIE0_SHIFT                      (7U)
-#define MCG_C6_LOLIE0(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)
+#define MCG_C6_LOLIE0_SET(x)                     (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)
+#define MCG_C6_LOLIE0 MCG_C6_LOLIE0_MASK
 
 /*! @name S - MCG Status Register */
 #define MCG_S_IRCST_MASK                         (0x1U)
 #define MCG_S_IRCST_SHIFT                        (0U)
-#define MCG_S_IRCST(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
+#define MCG_S_IRCST_SET(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
+#define MCG_S_IRCST MCG_S_IRCST_MASK
 #define MCG_S_OSCINIT0_MASK                      (0x2U)
 #define MCG_S_OSCINIT0_SHIFT                     (1U)
 #define MCG_S_OSCINIT0_SET(x)                    (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
 #define MCG_S_OSCINIT0                           MCG_S_OSCINIT0_SET(1)
 #define MCG_S_CLKST_MASK                         (0xCU)
 #define MCG_S_CLKST_SHIFT                        (2U)
-#define MCG_S_CLKST(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
+#define MCG_S_CLKST_SET(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
+#define MCG_S_CLKST MCG_S_CLKST_MASK
 #define MCG_S_CLKST_PLL                          MCG_S_CLKST(3)   /*!< Output of the PLL is selected */
 #define MCG_S_IREFST_MASK                        (0x10U)
 #define MCG_S_IREFST_SHIFT                       (4U)
@@ -9541,77 +11607,96 @@ typedef struct {
 #define MCG_S_LOCK0                              MCG_S_LOCK0_SET(1)
 #define MCG_S_LOLS0_MASK                         (0x80U)
 #define MCG_S_LOLS0_SHIFT                        (7U)
-#define MCG_S_LOLS0(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK)
+#define MCG_S_LOLS0_SET(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK)
+#define MCG_S_LOLS0 MCG_S_LOLS0_MASK
 
 /*! @name SC - MCG Status and Control Register */
 #define MCG_SC_LOCS0_MASK                        (0x1U)
 #define MCG_SC_LOCS0_SHIFT                       (0U)
-#define MCG_SC_LOCS0(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
+#define MCG_SC_LOCS0_SET(x)                      (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
+#define MCG_SC_LOCS0 MCG_SC_LOCS0_MASK
 #define MCG_SC_FCRDIV_MASK                       (0xEU)
 #define MCG_SC_FCRDIV_SHIFT                      (1U)
-#define MCG_SC_FCRDIV(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
+#define MCG_SC_FCRDIV_SET(x)                     (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
+#define MCG_SC_FCRDIV MCG_SC_FCRDIV_MASK
 #define MCG_SC_FLTPRSRV_MASK                     (0x10U)
 #define MCG_SC_FLTPRSRV_SHIFT                    (4U)
-#define MCG_SC_FLTPRSRV(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
+#define MCG_SC_FLTPRSRV_SET(x)                   (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
+#define MCG_SC_FLTPRSRV MCG_SC_FLTPRSRV_MASK
 #define MCG_SC_ATMF_MASK                         (0x20U)
 #define MCG_SC_ATMF_SHIFT                        (5U)
-#define MCG_SC_ATMF(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
+#define MCG_SC_ATMF_SET(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
+#define MCG_SC_ATMF MCG_SC_ATMF_MASK
 #define MCG_SC_ATMS_MASK                         (0x40U)
 #define MCG_SC_ATMS_SHIFT                        (6U)
-#define MCG_SC_ATMS(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
+#define MCG_SC_ATMS_SET(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
+#define MCG_SC_ATMS MCG_SC_ATMS_MASK
 #define MCG_SC_ATME_MASK                         (0x80U)
 #define MCG_SC_ATME_SHIFT                        (7U)
-#define MCG_SC_ATME(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
+#define MCG_SC_ATME_SET(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
+#define MCG_SC_ATME MCG_SC_ATME_MASK
 
 /*! @name ATCVH - MCG Auto Trim Compare Value High Register */
 #define MCG_ATCVH_ATCVH_MASK                     (0xFFU)
 #define MCG_ATCVH_ATCVH_SHIFT                    (0U)
-#define MCG_ATCVH_ATCVH(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
+#define MCG_ATCVH_ATCVH_SET(x)                   (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
+#define MCG_ATCVH_ATCVH MCG_ATCVH_ATCVH_MASK
 
 /*! @name ATCVL - MCG Auto Trim Compare Value Low Register */
 #define MCG_ATCVL_ATCVL_MASK                     (0xFFU)
 #define MCG_ATCVL_ATCVL_SHIFT                    (0U)
-#define MCG_ATCVL_ATCVL(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
+#define MCG_ATCVL_ATCVL_SET(x)                   (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
+#define MCG_ATCVL_ATCVL MCG_ATCVL_ATCVL_MASK
 
 /*! @name C7 - MCG Control 7 Register */
 #define MCG_C7_OSCSEL_MASK                       (0x3U)
 #define MCG_C7_OSCSEL_SHIFT                      (0U)
-#define MCG_C7_OSCSEL(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
+#define MCG_C7_OSCSEL_SET(x)                     (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
+#define MCG_C7_OSCSEL MCG_C7_OSCSEL_MASK
 
 /*! @name C8 - MCG Control 8 Register */
 #define MCG_C8_LOCS1_MASK                        (0x1U)
 #define MCG_C8_LOCS1_SHIFT                       (0U)
-#define MCG_C8_LOCS1(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)
+#define MCG_C8_LOCS1_SET(x)                      (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)
+#define MCG_C8_LOCS1 MCG_C8_LOCS1_MASK
 #define MCG_C8_CME1_MASK                         (0x20U)
 #define MCG_C8_CME1_SHIFT                        (5U)
-#define MCG_C8_CME1(x)                           (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)
+#define MCG_C8_CME1_SET(x)                       (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)
+#define MCG_C8_CME1 MCG_C8_CME1_MASK
 #define MCG_C8_LOLRE_MASK                        (0x40U)
 #define MCG_C8_LOLRE_SHIFT                       (6U)
-#define MCG_C8_LOLRE(x)                          (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)
+#define MCG_C8_LOLRE_SET(x)                      (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)
+#define MCG_C8_LOLRE MCG_C8_LOLRE_MASK
 #define MCG_C8_LOCRE1_MASK                       (0x80U)
 #define MCG_C8_LOCRE1_SHIFT                      (7U)
-#define MCG_C8_LOCRE1(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)
+#define MCG_C8_LOCRE1_SET(x)                     (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)
+#define MCG_C8_LOCRE1 MCG_C8_LOCRE1_MASK
 
 /*! @name C9 - MCG Control 9 Register */
 #define MCG_C9_EXT_PLL_LOCS_MASK                 (0x1U)
 #define MCG_C9_EXT_PLL_LOCS_SHIFT                (0U)
-#define MCG_C9_EXT_PLL_LOCS(x)                   (((uint8_t)(((uint8_t)(x)) << MCG_C9_EXT_PLL_LOCS_SHIFT)) & MCG_C9_EXT_PLL_LOCS_MASK)
+#define MCG_C9_EXT_PLL_LOCS_SET(x)               (((uint8_t)(((uint8_t)(x)) << MCG_C9_EXT_PLL_LOCS_SHIFT)) & MCG_C9_EXT_PLL_LOCS_MASK)
+#define MCG_C9_EXT_PLL_LOCS MCG_C9_EXT_PLL_LOCS_MASK
 #define MCG_C9_PLL_LOCRE_MASK                    (0x10U)
 #define MCG_C9_PLL_LOCRE_SHIFT                   (4U)
-#define MCG_C9_PLL_LOCRE(x)                      (((uint8_t)(((uint8_t)(x)) << MCG_C9_PLL_LOCRE_SHIFT)) & MCG_C9_PLL_LOCRE_MASK)
+#define MCG_C9_PLL_LOCRE_SET(x)                  (((uint8_t)(((uint8_t)(x)) << MCG_C9_PLL_LOCRE_SHIFT)) & MCG_C9_PLL_LOCRE_MASK)
+#define MCG_C9_PLL_LOCRE MCG_C9_PLL_LOCRE_MASK
 #define MCG_C9_PLL_CME_MASK                      (0x20U)
 #define MCG_C9_PLL_CME_SHIFT                     (5U)
-#define MCG_C9_PLL_CME(x)                        (((uint8_t)(((uint8_t)(x)) << MCG_C9_PLL_CME_SHIFT)) & MCG_C9_PLL_CME_MASK)
+#define MCG_C9_PLL_CME_SET(x)                    (((uint8_t)(((uint8_t)(x)) << MCG_C9_PLL_CME_SHIFT)) & MCG_C9_PLL_CME_MASK)
+#define MCG_C9_PLL_CME MCG_C9_PLL_CME_MASK
 
 /*! @name C11 - MCG Control 11 Register */
 #define MCG_C11_PLLCS_MASK                       (0x10U)
 #define MCG_C11_PLLCS_SHIFT                      (4U)
-#define MCG_C11_PLLCS(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_C11_PLLCS_SHIFT)) & MCG_C11_PLLCS_MASK)
+#define MCG_C11_PLLCS_SET(x)                     (((uint8_t)(((uint8_t)(x)) << MCG_C11_PLLCS_SHIFT)) & MCG_C11_PLLCS_MASK)
+#define MCG_C11_PLLCS MCG_C11_PLLCS_MASK
 
 /*! @name S2 - MCG Status 2 Register */
 #define MCG_S2_PLLCST_MASK                       (0x10U)
 #define MCG_S2_PLLCST_SHIFT                      (4U)
-#define MCG_S2_PLLCST(x)                         (((uint8_t)(((uint8_t)(x)) << MCG_S2_PLLCST_SHIFT)) & MCG_S2_PLLCST_MASK)
+#define MCG_S2_PLLCST_SET(x)                     (((uint8_t)(((uint8_t)(x)) << MCG_S2_PLLCST_SHIFT)) & MCG_S2_PLLCST_MASK)
+#define MCG_S2_PLLCST MCG_S2_PLLCST_MASK
 
 
 /*!
@@ -9623,7 +11708,7 @@ typedef struct {
 /** Peripheral MCG base address */
 #define MCG_BASE                                 (0x40064000u)
 /** Peripheral MCG base pointer */
-#define MCG                                      ((MCG_Type *)MCG_BASE)
+#define MCG                                      ((MCG_TypeDef *)MCG_BASE)
 /** Array initializer of MCG peripheral base addresses */
 #define MCG_BASE_ADDRS                           { MCG_BASE }
 /** Array initializer of MCG peripheral base pointers */
@@ -9632,25 +11717,29 @@ typedef struct {
 #define MCG_C5_PLLCLKEN0_MASK         (MCG_C5_PLLCLKEN_MASK)
 #define MCG_C5_PLLCLKEN0_SHIFT        (MCG_C5_PLLCLKEN_SHIFT)
 #define MCG_C5_PLLCLKEN0_WIDTH        (MCG_C5_PLLCLKEN_WIDTH)
-#define MCG_C5_PLLCLKEN0(x)           (MCG_C5_PLLCLKEN(x))
+#define MCG_C5_PLLCLKEN0_SET(x)       (MCG_C5_PLLCLKEN(x))
+#define MCG_C5_PLLCLKEN0 MCG_C5_PLLCLKEN0_MASK
 
 /* MCG C5[PLLSTEN0] backward compatibility */
 #define MCG_C5_PLLSTEN0_MASK         (MCG_C5_PLLSTEN_MASK)
 #define MCG_C5_PLLSTEN0_SHIFT        (MCG_C5_PLLSTEN_SHIFT)
 #define MCG_C5_PLLSTEN0_WIDTH        (MCG_C5_PLLSTEN_WIDTH)
-#define MCG_C5_PLLSTEN0(x)           (MCG_C5_PLLSTEN(x))
+#define MCG_C5_PLLSTEN0_SET(x)       (MCG_C5_PLLSTEN(x))
+#define MCG_C5_PLLSTEN0 MCG_C5_PLLSTEN0_MASK
 
 /* MCG C5[PRDIV0] backward compatibility */
 #define MCG_C5_PRDIV0_MASK         (MCG_C5_PRDIV_MASK)
 #define MCG_C5_PRDIV0_SHIFT        (MCG_C5_PRDIV_SHIFT)
 #define MCG_C5_PRDIV0_WIDTH        (MCG_C5_PRDIV_WIDTH)
-#define MCG_C5_PRDIV0(x)           (MCG_C5_PRDIV(x))
+#define MCG_C5_PRDIV0_SET(x)       (MCG_C5_PRDIV(x))
+#define MCG_C5_PRDIV0 MCG_C5_PRDIV0_MASK
 
 /* MCG C6[VDIV0] backward compatibility */
 #define MCG_C6_VDIV0_MASK         (MCG_C6_VDIV_MASK)
 #define MCG_C6_VDIV0_SHIFT        (MCG_C6_VDIV_SHIFT)
 #define MCG_C6_VDIV0_WIDTH        (MCG_C6_VDIV_WIDTH)
-#define MCG_C6_VDIV0(x)           (MCG_C6_VDIV(x))
+#define MCG_C6_VDIV0_SET(x)       (MCG_C6_VDIV(x))
+#define MCG_C6_VDIV0 MCG_C6_VDIV0_MASK
 
 
 /*!
@@ -9684,7 +11773,7 @@ typedef struct {
   __IO uint32_t PID;                               /**< Process ID register, offset: 0x30 */
        uint8_t RESERVED_2[12];
   __IO uint32_t CPO;                               /**< Compute Operation Control Register, offset: 0x40 */
-} MCM_Type;
+} MCM_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- MCM Register Masks
@@ -9698,146 +11787,186 @@ typedef struct {
 /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
 #define MCM_PLASC_ASC_MASK                       (0xFFU)
 #define MCM_PLASC_ASC_SHIFT                      (0U)
-#define MCM_PLASC_ASC(x)                         (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
+#define MCM_PLASC_ASC_SET(x)                     (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
+#define MCM_PLASC_ASC MCM_PLASC_ASC_MASK
 
 /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
 #define MCM_PLAMC_AMC_MASK                       (0xFFU)
 #define MCM_PLAMC_AMC_SHIFT                      (0U)
-#define MCM_PLAMC_AMC(x)                         (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
+#define MCM_PLAMC_AMC_SET(x)                     (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
+#define MCM_PLAMC_AMC MCM_PLAMC_AMC_MASK
 
 /*! @name CR - Control Register */
 #define MCM_CR_SRAMUAP_MASK                      (0x3000000U)
 #define MCM_CR_SRAMUAP_SHIFT                     (24U)
-#define MCM_CR_SRAMUAP(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUAP_SHIFT)) & MCM_CR_SRAMUAP_MASK)
+#define MCM_CR_SRAMUAP_SET(x)                    (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUAP_SHIFT)) & MCM_CR_SRAMUAP_MASK)
+#define MCM_CR_SRAMUAP MCM_CR_SRAMUAP_MASK
 #define MCM_CR_SRAMUWP_MASK                      (0x4000000U)
 #define MCM_CR_SRAMUWP_SHIFT                     (26U)
-#define MCM_CR_SRAMUWP(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUWP_SHIFT)) & MCM_CR_SRAMUWP_MASK)
+#define MCM_CR_SRAMUWP_SET(x)                    (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUWP_SHIFT)) & MCM_CR_SRAMUWP_MASK)
+#define MCM_CR_SRAMUWP MCM_CR_SRAMUWP_MASK
 #define MCM_CR_SRAMLAP_MASK                      (0x30000000U)
 #define MCM_CR_SRAMLAP_SHIFT                     (28U)
-#define MCM_CR_SRAMLAP(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLAP_SHIFT)) & MCM_CR_SRAMLAP_MASK)
+#define MCM_CR_SRAMLAP_SET(x)                    (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLAP_SHIFT)) & MCM_CR_SRAMLAP_MASK)
+#define MCM_CR_SRAMLAP MCM_CR_SRAMLAP_MASK
 #define MCM_CR_SRAMLWP_MASK                      (0x40000000U)
 #define MCM_CR_SRAMLWP_SHIFT                     (30U)
-#define MCM_CR_SRAMLWP(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLWP_SHIFT)) & MCM_CR_SRAMLWP_MASK)
+#define MCM_CR_SRAMLWP_SET(x)                    (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLWP_SHIFT)) & MCM_CR_SRAMLWP_MASK)
+#define MCM_CR_SRAMLWP MCM_CR_SRAMLWP_MASK
 
 /*! @name ISCR - Interrupt Status Register */
 #define MCM_ISCR_IRQ_MASK                        (0x2U)
 #define MCM_ISCR_IRQ_SHIFT                       (1U)
-#define MCM_ISCR_IRQ(x)                          (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_IRQ_SHIFT)) & MCM_ISCR_IRQ_MASK)
+#define MCM_ISCR_IRQ_SET(x)                      (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_IRQ_SHIFT)) & MCM_ISCR_IRQ_MASK)
+#define MCM_ISCR_IRQ MCM_ISCR_IRQ_MASK
 #define MCM_ISCR_NMI_MASK                        (0x4U)
 #define MCM_ISCR_NMI_SHIFT                       (2U)
-#define MCM_ISCR_NMI(x)                          (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_NMI_SHIFT)) & MCM_ISCR_NMI_MASK)
+#define MCM_ISCR_NMI_SET(x)                      (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_NMI_SHIFT)) & MCM_ISCR_NMI_MASK)
+#define MCM_ISCR_NMI MCM_ISCR_NMI_MASK
 #define MCM_ISCR_DHREQ_MASK                      (0x8U)
 #define MCM_ISCR_DHREQ_SHIFT                     (3U)
-#define MCM_ISCR_DHREQ(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_DHREQ_SHIFT)) & MCM_ISCR_DHREQ_MASK)
+#define MCM_ISCR_DHREQ_SET(x)                    (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_DHREQ_SHIFT)) & MCM_ISCR_DHREQ_MASK)
+#define MCM_ISCR_DHREQ MCM_ISCR_DHREQ_MASK
 #define MCM_ISCR_FIOC_MASK                       (0x100U)
 #define MCM_ISCR_FIOC_SHIFT                      (8U)
-#define MCM_ISCR_FIOC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)
+#define MCM_ISCR_FIOC_SET(x)                     (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)
+#define MCM_ISCR_FIOC MCM_ISCR_FIOC_MASK
 #define MCM_ISCR_FDZC_MASK                       (0x200U)
 #define MCM_ISCR_FDZC_SHIFT                      (9U)
-#define MCM_ISCR_FDZC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)
+#define MCM_ISCR_FDZC_SET(x)                     (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)
+#define MCM_ISCR_FDZC MCM_ISCR_FDZC_MASK
 #define MCM_ISCR_FOFC_MASK                       (0x400U)
 #define MCM_ISCR_FOFC_SHIFT                      (10U)
-#define MCM_ISCR_FOFC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)
+#define MCM_ISCR_FOFC_SET(x)                     (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)
+#define MCM_ISCR_FOFC MCM_ISCR_FOFC_MASK
 #define MCM_ISCR_FUFC_MASK                       (0x800U)
 #define MCM_ISCR_FUFC_SHIFT                      (11U)
-#define MCM_ISCR_FUFC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)
+#define MCM_ISCR_FUFC_SET(x)                     (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)
+#define MCM_ISCR_FUFC MCM_ISCR_FUFC_MASK
 #define MCM_ISCR_FIXC_MASK                       (0x1000U)
 #define MCM_ISCR_FIXC_SHIFT                      (12U)
-#define MCM_ISCR_FIXC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)
+#define MCM_ISCR_FIXC_SET(x)                     (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)
+#define MCM_ISCR_FIXC MCM_ISCR_FIXC_MASK
 #define MCM_ISCR_FIDC_MASK                       (0x8000U)
 #define MCM_ISCR_FIDC_SHIFT                      (15U)
-#define MCM_ISCR_FIDC(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)
+#define MCM_ISCR_FIDC_SET(x)                     (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)
+#define MCM_ISCR_FIDC MCM_ISCR_FIDC_MASK
 #define MCM_ISCR_FIOCE_MASK                      (0x1000000U)
 #define MCM_ISCR_FIOCE_SHIFT                     (24U)
-#define MCM_ISCR_FIOCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)
+#define MCM_ISCR_FIOCE_SET(x)                    (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)
+#define MCM_ISCR_FIOCE MCM_ISCR_FIOCE_MASK
 #define MCM_ISCR_FDZCE_MASK                      (0x2000000U)
 #define MCM_ISCR_FDZCE_SHIFT                     (25U)
-#define MCM_ISCR_FDZCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)
+#define MCM_ISCR_FDZCE_SET(x)                    (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)
+#define MCM_ISCR_FDZCE MCM_ISCR_FDZCE_MASK
 #define MCM_ISCR_FOFCE_MASK                      (0x4000000U)
 #define MCM_ISCR_FOFCE_SHIFT                     (26U)
-#define MCM_ISCR_FOFCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)
+#define MCM_ISCR_FOFCE_SET(x)                    (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)
+#define MCM_ISCR_FOFCE MCM_ISCR_FOFCE_MASK
 #define MCM_ISCR_FUFCE_MASK                      (0x8000000U)
 #define MCM_ISCR_FUFCE_SHIFT                     (27U)
-#define MCM_ISCR_FUFCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)
+#define MCM_ISCR_FUFCE_SET(x)                    (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)
+#define MCM_ISCR_FUFCE MCM_ISCR_FUFCE_MASK
 #define MCM_ISCR_FIXCE_MASK                      (0x10000000U)
 #define MCM_ISCR_FIXCE_SHIFT                     (28U)
-#define MCM_ISCR_FIXCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)
+#define MCM_ISCR_FIXCE_SET(x)                    (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)
+#define MCM_ISCR_FIXCE MCM_ISCR_FIXCE_MASK
 #define MCM_ISCR_FIDCE_MASK                      (0x80000000U)
 #define MCM_ISCR_FIDCE_SHIFT                     (31U)
-#define MCM_ISCR_FIDCE(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)
+#define MCM_ISCR_FIDCE_SET(x)                    (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)
+#define MCM_ISCR_FIDCE MCM_ISCR_FIDCE_MASK
 
 /*! @name ETBCC - ETB Counter Control register */
 #define MCM_ETBCC_CNTEN_MASK                     (0x1U)
 #define MCM_ETBCC_CNTEN_SHIFT                    (0U)
-#define MCM_ETBCC_CNTEN(x)                       (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_CNTEN_SHIFT)) & MCM_ETBCC_CNTEN_MASK)
+#define MCM_ETBCC_CNTEN_SET(x)                   (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_CNTEN_SHIFT)) & MCM_ETBCC_CNTEN_MASK)
+#define MCM_ETBCC_CNTEN MCM_ETBCC_CNTEN_MASK
 #define MCM_ETBCC_RSPT_MASK                      (0x6U)
 #define MCM_ETBCC_RSPT_SHIFT                     (1U)
-#define MCM_ETBCC_RSPT(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RSPT_SHIFT)) & MCM_ETBCC_RSPT_MASK)
+#define MCM_ETBCC_RSPT_SET(x)                    (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RSPT_SHIFT)) & MCM_ETBCC_RSPT_MASK)
+#define MCM_ETBCC_RSPT MCM_ETBCC_RSPT_MASK
 #define MCM_ETBCC_RLRQ_MASK                      (0x8U)
 #define MCM_ETBCC_RLRQ_SHIFT                     (3U)
-#define MCM_ETBCC_RLRQ(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RLRQ_SHIFT)) & MCM_ETBCC_RLRQ_MASK)
+#define MCM_ETBCC_RLRQ_SET(x)                    (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RLRQ_SHIFT)) & MCM_ETBCC_RLRQ_MASK)
+#define MCM_ETBCC_RLRQ MCM_ETBCC_RLRQ_MASK
 #define MCM_ETBCC_ETDIS_MASK                     (0x10U)
 #define MCM_ETBCC_ETDIS_SHIFT                    (4U)
-#define MCM_ETBCC_ETDIS(x)                       (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ETDIS_SHIFT)) & MCM_ETBCC_ETDIS_MASK)
+#define MCM_ETBCC_ETDIS_SET(x)                   (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ETDIS_SHIFT)) & MCM_ETBCC_ETDIS_MASK)
+#define MCM_ETBCC_ETDIS MCM_ETBCC_ETDIS_MASK
 #define MCM_ETBCC_ITDIS_MASK                     (0x20U)
 #define MCM_ETBCC_ITDIS_SHIFT                    (5U)
-#define MCM_ETBCC_ITDIS(x)                       (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ITDIS_SHIFT)) & MCM_ETBCC_ITDIS_MASK)
+#define MCM_ETBCC_ITDIS_SET(x)                   (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ITDIS_SHIFT)) & MCM_ETBCC_ITDIS_MASK)
+#define MCM_ETBCC_ITDIS MCM_ETBCC_ITDIS_MASK
 
 /*! @name ETBRL - ETB Reload register */
 #define MCM_ETBRL_RELOAD_MASK                    (0x7FFU)
 #define MCM_ETBRL_RELOAD_SHIFT                   (0U)
-#define MCM_ETBRL_RELOAD(x)                      (((uint32_t)(((uint32_t)(x)) << MCM_ETBRL_RELOAD_SHIFT)) & MCM_ETBRL_RELOAD_MASK)
+#define MCM_ETBRL_RELOAD_SET(x)                  (((uint32_t)(((uint32_t)(x)) << MCM_ETBRL_RELOAD_SHIFT)) & MCM_ETBRL_RELOAD_MASK)
+#define MCM_ETBRL_RELOAD MCM_ETBRL_RELOAD_MASK
 
 /*! @name ETBCNT - ETB Counter Value register */
 #define MCM_ETBCNT_COUNTER_MASK                  (0x7FFU)
 #define MCM_ETBCNT_COUNTER_SHIFT                 (0U)
-#define MCM_ETBCNT_COUNTER(x)                    (((uint32_t)(((uint32_t)(x)) << MCM_ETBCNT_COUNTER_SHIFT)) & MCM_ETBCNT_COUNTER_MASK)
+#define MCM_ETBCNT_COUNTER_SET(x)                (((uint32_t)(((uint32_t)(x)) << MCM_ETBCNT_COUNTER_SHIFT)) & MCM_ETBCNT_COUNTER_MASK)
+#define MCM_ETBCNT_COUNTER MCM_ETBCNT_COUNTER_MASK
 
 /*! @name FADR - Fault address register */
 #define MCM_FADR_ADDRESS_MASK                    (0xFFFFFFFFU)
 #define MCM_FADR_ADDRESS_SHIFT                   (0U)
-#define MCM_FADR_ADDRESS(x)                      (((uint32_t)(((uint32_t)(x)) << MCM_FADR_ADDRESS_SHIFT)) & MCM_FADR_ADDRESS_MASK)
+#define MCM_FADR_ADDRESS_SET(x)                  (((uint32_t)(((uint32_t)(x)) << MCM_FADR_ADDRESS_SHIFT)) & MCM_FADR_ADDRESS_MASK)
+#define MCM_FADR_ADDRESS MCM_FADR_ADDRESS_MASK
 
 /*! @name FATR - Fault attributes register */
 #define MCM_FATR_BEDA_MASK                       (0x1U)
 #define MCM_FATR_BEDA_SHIFT                      (0U)
-#define MCM_FATR_BEDA(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEDA_SHIFT)) & MCM_FATR_BEDA_MASK)
+#define MCM_FATR_BEDA_SET(x)                     (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEDA_SHIFT)) & MCM_FATR_BEDA_MASK)
+#define MCM_FATR_BEDA MCM_FATR_BEDA_MASK
 #define MCM_FATR_BEMD_MASK                       (0x2U)
 #define MCM_FATR_BEMD_SHIFT                      (1U)
-#define MCM_FATR_BEMD(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMD_SHIFT)) & MCM_FATR_BEMD_MASK)
+#define MCM_FATR_BEMD_SET(x)                     (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMD_SHIFT)) & MCM_FATR_BEMD_MASK)
+#define MCM_FATR_BEMD MCM_FATR_BEMD_MASK
 #define MCM_FATR_BESZ_MASK                       (0x30U)
 #define MCM_FATR_BESZ_SHIFT                      (4U)
-#define MCM_FATR_BESZ(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BESZ_SHIFT)) & MCM_FATR_BESZ_MASK)
+#define MCM_FATR_BESZ_SET(x)                     (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BESZ_SHIFT)) & MCM_FATR_BESZ_MASK)
+#define MCM_FATR_BESZ MCM_FATR_BESZ_MASK
 #define MCM_FATR_BEWT_MASK                       (0x80U)
 #define MCM_FATR_BEWT_SHIFT                      (7U)
-#define MCM_FATR_BEWT(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEWT_SHIFT)) & MCM_FATR_BEWT_MASK)
+#define MCM_FATR_BEWT_SET(x)                     (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEWT_SHIFT)) & MCM_FATR_BEWT_MASK)
+#define MCM_FATR_BEWT MCM_FATR_BEWT_MASK
 #define MCM_FATR_BEMN_MASK                       (0xF00U)
 #define MCM_FATR_BEMN_SHIFT                      (8U)
-#define MCM_FATR_BEMN(x)                         (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMN_SHIFT)) & MCM_FATR_BEMN_MASK)
+#define MCM_FATR_BEMN_SET(x)                     (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEMN_SHIFT)) & MCM_FATR_BEMN_MASK)
+#define MCM_FATR_BEMN MCM_FATR_BEMN_MASK
 #define MCM_FATR_BEOVR_MASK                      (0x80000000U)
 #define MCM_FATR_BEOVR_SHIFT                     (31U)
-#define MCM_FATR_BEOVR(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEOVR_SHIFT)) & MCM_FATR_BEOVR_MASK)
+#define MCM_FATR_BEOVR_SET(x)                    (((uint32_t)(((uint32_t)(x)) << MCM_FATR_BEOVR_SHIFT)) & MCM_FATR_BEOVR_MASK)
+#define MCM_FATR_BEOVR MCM_FATR_BEOVR_MASK
 
 /*! @name FDR - Fault data register */
 #define MCM_FDR_DATA_MASK                        (0xFFFFFFFFU)
 #define MCM_FDR_DATA_SHIFT                       (0U)
-#define MCM_FDR_DATA(x)                          (((uint32_t)(((uint32_t)(x)) << MCM_FDR_DATA_SHIFT)) & MCM_FDR_DATA_MASK)
+#define MCM_FDR_DATA_SET(x)                      (((uint32_t)(((uint32_t)(x)) << MCM_FDR_DATA_SHIFT)) & MCM_FDR_DATA_MASK)
+#define MCM_FDR_DATA MCM_FDR_DATA_MASK
 
 /*! @name PID - Process ID register */
 #define MCM_PID_PID_MASK                         (0xFFU)
 #define MCM_PID_PID_SHIFT                        (0U)
-#define MCM_PID_PID(x)                           (((uint32_t)(((uint32_t)(x)) << MCM_PID_PID_SHIFT)) & MCM_PID_PID_MASK)
+#define MCM_PID_PID_SET(x)                       (((uint32_t)(((uint32_t)(x)) << MCM_PID_PID_SHIFT)) & MCM_PID_PID_MASK)
+#define MCM_PID_PID MCM_PID_PID_MASK
 
 /*! @name CPO - Compute Operation Control Register */
 #define MCM_CPO_CPOREQ_MASK                      (0x1U)
 #define MCM_CPO_CPOREQ_SHIFT                     (0U)
-#define MCM_CPO_CPOREQ(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)
+#define MCM_CPO_CPOREQ_SET(x)                    (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOREQ_SHIFT)) & MCM_CPO_CPOREQ_MASK)
+#define MCM_CPO_CPOREQ MCM_CPO_CPOREQ_MASK
 #define MCM_CPO_CPOACK_MASK                      (0x2U)
 #define MCM_CPO_CPOACK_SHIFT                     (1U)
-#define MCM_CPO_CPOACK(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)
+#define MCM_CPO_CPOACK_SET(x)                    (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOACK_SHIFT)) & MCM_CPO_CPOACK_MASK)
+#define MCM_CPO_CPOACK MCM_CPO_CPOACK_MASK
 #define MCM_CPO_CPOWOI_MASK                      (0x4U)
 #define MCM_CPO_CPOWOI_SHIFT                     (2U)
-#define MCM_CPO_CPOWOI(x)                        (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK)
+#define MCM_CPO_CPOWOI_SET(x)                    (((uint32_t)(((uint32_t)(x)) << MCM_CPO_CPOWOI_SHIFT)) & MCM_CPO_CPOWOI_MASK)
+#define MCM_CPO_CPOWOI MCM_CPO_CPOWOI_MASK
 
 
 /*!
@@ -9849,7 +11978,7 @@ typedef struct {
 /** Peripheral MCM base address */
 #define MCM_BASE                                 (0xE0080000u)
 /** Peripheral MCM base pointer */
-#define MCM                                      ((MCM_Type *)MCM_BASE)
+#define MCM                                      ((MCM_TypeDef *)MCM_BASE)
 /** Array initializer of MCM peripheral base addresses */
 #define MCM_BASE_ADDRS                           { MCM_BASE }
 /** Array initializer of MCM peripheral base pointers */
@@ -9889,7 +12018,7 @@ typedef struct {
   __I  uint8_t FOPT;                               /**< Non-volatile Flash Option Register, offset: 0xD */
   __I  uint8_t FEPROT;                             /**< Non-volatile EERAM Protection Register, offset: 0xE */
   __I  uint8_t FDPROT;                             /**< Non-volatile D-Flash Protection Register, offset: 0xF */
-} NV_Type;
+} NV_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- NV Register Masks
@@ -9903,97 +12032,118 @@ typedef struct {
 /*! @name BACKKEY3 - Backdoor Comparison Key 3. */
 #define NV_BACKKEY3_KEY_MASK                     (0xFFU)
 #define NV_BACKKEY3_KEY_SHIFT                    (0U)
-#define NV_BACKKEY3_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
+#define NV_BACKKEY3_KEY_SET(x)                   (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
+#define NV_BACKKEY3_KEY NV_BACKKEY3_KEY_MASK
 
 /*! @name BACKKEY2 - Backdoor Comparison Key 2. */
 #define NV_BACKKEY2_KEY_MASK                     (0xFFU)
 #define NV_BACKKEY2_KEY_SHIFT                    (0U)
-#define NV_BACKKEY2_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
+#define NV_BACKKEY2_KEY_SET(x)                   (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
+#define NV_BACKKEY2_KEY NV_BACKKEY2_KEY_MASK
 
 /*! @name BACKKEY1 - Backdoor Comparison Key 1. */
 #define NV_BACKKEY1_KEY_MASK                     (0xFFU)
 #define NV_BACKKEY1_KEY_SHIFT                    (0U)
-#define NV_BACKKEY1_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
+#define NV_BACKKEY1_KEY_SET(x)                   (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
+#define NV_BACKKEY1_KEY NV_BACKKEY1_KEY_MASK
 
 /*! @name BACKKEY0 - Backdoor Comparison Key 0. */
 #define NV_BACKKEY0_KEY_MASK                     (0xFFU)
 #define NV_BACKKEY0_KEY_SHIFT                    (0U)
-#define NV_BACKKEY0_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
+#define NV_BACKKEY0_KEY_SET(x)                   (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
+#define NV_BACKKEY0_KEY NV_BACKKEY0_KEY_MASK
 
 /*! @name BACKKEY7 - Backdoor Comparison Key 7. */
 #define NV_BACKKEY7_KEY_MASK                     (0xFFU)
 #define NV_BACKKEY7_KEY_SHIFT                    (0U)
-#define NV_BACKKEY7_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
+#define NV_BACKKEY7_KEY_SET(x)                   (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
+#define NV_BACKKEY7_KEY NV_BACKKEY7_KEY_MASK
 
 /*! @name BACKKEY6 - Backdoor Comparison Key 6. */
 #define NV_BACKKEY6_KEY_MASK                     (0xFFU)
 #define NV_BACKKEY6_KEY_SHIFT                    (0U)
-#define NV_BACKKEY6_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
+#define NV_BACKKEY6_KEY_SET(x)                   (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
+#define NV_BACKKEY6_KEY NV_BACKKEY6_KEY_MASK
 
 /*! @name BACKKEY5 - Backdoor Comparison Key 5. */
 #define NV_BACKKEY5_KEY_MASK                     (0xFFU)
 #define NV_BACKKEY5_KEY_SHIFT                    (0U)
-#define NV_BACKKEY5_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
+#define NV_BACKKEY5_KEY_SET(x)                   (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
+#define NV_BACKKEY5_KEY NV_BACKKEY5_KEY_MASK
 
 /*! @name BACKKEY4 - Backdoor Comparison Key 4. */
 #define NV_BACKKEY4_KEY_MASK                     (0xFFU)
 #define NV_BACKKEY4_KEY_SHIFT                    (0U)
-#define NV_BACKKEY4_KEY(x)                       (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
+#define NV_BACKKEY4_KEY_SET(x)                   (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
+#define NV_BACKKEY4_KEY NV_BACKKEY4_KEY_MASK
 
 /*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */
 #define NV_FPROT3_PROT_MASK                      (0xFFU)
 #define NV_FPROT3_PROT_SHIFT                     (0U)
-#define NV_FPROT3_PROT(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
+#define NV_FPROT3_PROT_SET(x)                    (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
+#define NV_FPROT3_PROT NV_FPROT3_PROT_MASK
 
 /*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */
 #define NV_FPROT2_PROT_MASK                      (0xFFU)
 #define NV_FPROT2_PROT_SHIFT                     (0U)
-#define NV_FPROT2_PROT(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
+#define NV_FPROT2_PROT_SET(x)                    (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
+#define NV_FPROT2_PROT NV_FPROT2_PROT_MASK
 
 /*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */
 #define NV_FPROT1_PROT_MASK                      (0xFFU)
 #define NV_FPROT1_PROT_SHIFT                     (0U)
-#define NV_FPROT1_PROT(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
+#define NV_FPROT1_PROT_SET(x)                    (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
+#define NV_FPROT1_PROT NV_FPROT1_PROT_MASK
 
 /*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */
 #define NV_FPROT0_PROT_MASK                      (0xFFU)
 #define NV_FPROT0_PROT_SHIFT                     (0U)
-#define NV_FPROT0_PROT(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
+#define NV_FPROT0_PROT_SET(x)                    (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
+#define NV_FPROT0_PROT NV_FPROT0_PROT_MASK
 
 /*! @name FSEC - Non-volatile Flash Security Register */
 #define NV_FSEC_SEC_MASK                         (0x3U)
 #define NV_FSEC_SEC_SHIFT                        (0U)
-#define NV_FSEC_SEC(x)                           (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
+#define NV_FSEC_SEC_SET(x)                       (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
+#define NV_FSEC_SEC NV_FSEC_SEC_MASK
 #define NV_FSEC_FSLACC_MASK                      (0xCU)
 #define NV_FSEC_FSLACC_SHIFT                     (2U)
-#define NV_FSEC_FSLACC(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_FSLACC_SET(x)                    (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
+#define NV_FSEC_FSLACC NV_FSEC_FSLACC_MASK
 #define NV_FSEC_MEEN_MASK                        (0x30U)
 #define NV_FSEC_MEEN_SHIFT                       (4U)
-#define NV_FSEC_MEEN(x)                          (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
+#define NV_FSEC_MEEN_SET(x)                      (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
+#define NV_FSEC_MEEN NV_FSEC_MEEN_MASK
 #define NV_FSEC_KEYEN_MASK                       (0xC0U)
 #define NV_FSEC_KEYEN_SHIFT                      (6U)
-#define NV_FSEC_KEYEN(x)                         (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
+#define NV_FSEC_KEYEN_SET(x)                     (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
+#define NV_FSEC_KEYEN NV_FSEC_KEYEN_MASK
 
 /*! @name FOPT - Non-volatile Flash Option Register */
 #define NV_FOPT_LPBOOT_MASK                      (0x1U)
 #define NV_FOPT_LPBOOT_SHIFT                     (0U)
-#define NV_FOPT_LPBOOT(x)                        (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK)
+#define NV_FOPT_LPBOOT_SET(x)                    (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK)
+#define NV_FOPT_LPBOOT NV_FOPT_LPBOOT_MASK
 #define NV_FOPT_EZPORT_DIS_MASK                  (0x2U)
 #define NV_FOPT_EZPORT_DIS_SHIFT                 (1U)
-#define NV_FOPT_EZPORT_DIS(x)                    (((uint8_t)(((uint8_t)(x)) << NV_FOPT_EZPORT_DIS_SHIFT)) & NV_FOPT_EZPORT_DIS_MASK)
+#define NV_FOPT_EZPORT_DIS_SET(x)                (((uint8_t)(((uint8_t)(x)) << NV_FOPT_EZPORT_DIS_SHIFT)) & NV_FOPT_EZPORT_DIS_MASK)
+#define NV_FOPT_EZPORT_DIS NV_FOPT_EZPORT_DIS_MASK
 #define NV_FOPT_NMI_DIS_MASK                     (0x4U)
 #define NV_FOPT_NMI_DIS_SHIFT                    (2U)
-#define NV_FOPT_NMI_DIS(x)                       (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
+#define NV_FOPT_NMI_DIS_SET(x)                   (((uint8_t)(((uint8_t)(x)) << NV_FOPT_NMI_DIS_SHIFT)) & NV_FOPT_NMI_DIS_MASK)
+#define NV_FOPT_NMI_DIS NV_FOPT_NMI_DIS_MASK
 
 /*! @name FEPROT - Non-volatile EERAM Protection Register */
 #define NV_FEPROT_EPROT_MASK                     (0xFFU)
 #define NV_FEPROT_EPROT_SHIFT                    (0U)
-#define NV_FEPROT_EPROT(x)                       (((uint8_t)(((uint8_t)(x)) << NV_FEPROT_EPROT_SHIFT)) & NV_FEPROT_EPROT_MASK)
+#define NV_FEPROT_EPROT_SET(x)                   (((uint8_t)(((uint8_t)(x)) << NV_FEPROT_EPROT_SHIFT)) & NV_FEPROT_EPROT_MASK)
+#define NV_FEPROT_EPROT NV_FEPROT_EPROT_MASK
 
 /*! @name FDPROT - Non-volatile D-Flash Protection Register */
 #define NV_FDPROT_DPROT_MASK                     (0xFFU)
 #define NV_FDPROT_DPROT_SHIFT                    (0U)
-#define NV_FDPROT_DPROT(x)                       (((uint8_t)(((uint8_t)(x)) << NV_FDPROT_DPROT_SHIFT)) & NV_FDPROT_DPROT_MASK)
+#define NV_FDPROT_DPROT_SET(x)                   (((uint8_t)(((uint8_t)(x)) << NV_FDPROT_DPROT_SHIFT)) & NV_FDPROT_DPROT_MASK)
+#define NV_FDPROT_DPROT NV_FDPROT_DPROT_MASK
 
 
 /*!
@@ -10005,7 +12155,7 @@ typedef struct {
 /** Peripheral FTFE_FlashConfig base address */
 #define FTFE_FlashConfig_BASE                    (0x400u)
 /** Peripheral FTFE_FlashConfig base pointer */
-#define FTFE_FlashConfig                         ((NV_Type *)FTFE_FlashConfig_BASE)
+#define FTFE_FlashConfig                         ((NV_TypeDef *)FTFE_FlashConfig_BASE)
 /** Array initializer of NV peripheral base addresses */
 #define NV_BASE_ADDRS                            { FTFE_FlashConfig_BASE }
 /** Array initializer of NV peripheral base pointers */
@@ -10030,7 +12180,7 @@ typedef struct {
   __IO uint8_t CR;                                 /**< OSC Control Register, offset: 0x0 */
        uint8_t RESERVED_0[1];
   __IO uint8_t DIV;                                /**< OSC0_DIV, offset: 0x2 */
-} OSC0_Type;
+} OSC0_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- OSC Register Masks
@@ -10044,30 +12194,37 @@ typedef struct {
 /*! @name CR - OSC Control Register */
 #define OSC0_CR_SC16P_MASK                        (0x1U)
 #define OSC0_CR_SC16P_SHIFT                       (0U)
-#define OSC0_CR_SC16P(x)                          (((uint8_t)(((uint8_t)(x)) << OSC0_CR_SC16P_SHIFT)) & OSC0_CR_SC16P_MASK)
+#define OSC0_CR_SC16P_SET(x)                      (((uint8_t)(((uint8_t)(x)) << OSC0_CR_SC16P_SHIFT)) & OSC0_CR_SC16P_MASK)
+#define OSC0_CR_SC16P OSC0_CR_SC16P_MASK
 #define OSC0_CR_SC8P_MASK                         (0x2U)
 #define OSC0_CR_SC8P_SHIFT                        (1U)
-#define OSC0_CR_SC8P(x)                           (((uint8_t)(((uint8_t)(x)) << OSC0_CR_SC8P_SHIFT)) & OSC0_CR_SC8P_MASK)
+#define OSC0_CR_SC8P_SET(x)                       (((uint8_t)(((uint8_t)(x)) << OSC0_CR_SC8P_SHIFT)) & OSC0_CR_SC8P_MASK)
+#define OSC0_CR_SC8P OSC0_CR_SC8P_MASK
 #define OSC_CR_SC8P                               OSC0_CR_SC8P(1)
 #define OSC0_CR_SC4P_MASK                         (0x4U)
 #define OSC0_CR_SC4P_SHIFT                        (2U)
-#define OSC0_CR_SC4P(x)                           (((uint8_t)(((uint8_t)(x)) << OSC0_CR_SC4P_SHIFT)) & OSC0_CR_SC4P_MASK)
+#define OSC0_CR_SC4P_SET(x)                       (((uint8_t)(((uint8_t)(x)) << OSC0_CR_SC4P_SHIFT)) & OSC0_CR_SC4P_MASK)
+#define OSC0_CR_SC4P OSC0_CR_SC4P_MASK
 #define OSC_CR_SC4P                               OSC0_CR_SC4P(1)
 #define OSC0_CR_SC2P_MASK                         (0x8U)
 #define OSC0_CR_SC2P_SHIFT                        (3U)
-#define OSC0_CR_SC2P(x)                           (((uint8_t)(((uint8_t)(x)) << OSC0_CR_SC2P_SHIFT)) & OSC0_CR_SC2P_MASK)
+#define OSC0_CR_SC2P_SET(x)                       (((uint8_t)(((uint8_t)(x)) << OSC0_CR_SC2P_SHIFT)) & OSC0_CR_SC2P_MASK)
+#define OSC0_CR_SC2P OSC0_CR_SC2P_MASK
 #define OSC_CR_SC2P                               OSC0_CR_SC2P(1)
 #define OSC0_CR_EREFSTEN_MASK                     (0x20U)
 #define OSC0_CR_EREFSTEN_SHIFT                    (5U)
-#define OSC0_CR_EREFSTEN(x)                       (((uint8_t)(((uint8_t)(x)) << OSC0_CR_EREFSTEN_SHIFT)) & OSC0_CR_EREFSTEN_MASK)
+#define OSC0_CR_EREFSTEN_SET(x)                   (((uint8_t)(((uint8_t)(x)) << OSC0_CR_EREFSTEN_SHIFT)) & OSC0_CR_EREFSTEN_MASK)
+#define OSC0_CR_EREFSTEN OSC0_CR_EREFSTEN_MASK
 #define OSC0_CR_ERCLKEN_MASK                      (0x80U)
 #define OSC0_CR_ERCLKEN_SHIFT                     (7U)
-#define OSC0_CR_ERCLKEN(x)                        (((uint8_t)(((uint8_t)(x)) << OSC0_CR_ERCLKEN_SHIFT)) & OSC0_CR_ERCLKEN_MASK)
+#define OSC0_CR_ERCLKEN_SET(x)                    (((uint8_t)(((uint8_t)(x)) << OSC0_CR_ERCLKEN_SHIFT)) & OSC0_CR_ERCLKEN_MASK)
+#define OSC0_CR_ERCLKEN OSC0_CR_ERCLKEN_MASK
 
 /*! @name DIV - OSC0_DIV */
 #define OSC0_DIV_ERPS_MASK                        (0xC0U)
 #define OSC0_DIV_ERPS_SHIFT                       (6U)
-#define OSC0_DIV_ERPS(x)                          (((uint8_t)(((uint8_t)(x)) << OSC0_DIV_ERPS_SHIFT)) & OSC0_DIV_ERPS_MASK)
+#define OSC0_DIV_ERPS_SET(x)                      (((uint8_t)(((uint8_t)(x)) << OSC0_DIV_ERPS_SHIFT)) & OSC0_DIV_ERPS_MASK)
+#define OSC0_DIV_ERPS OSC0_DIV_ERPS_MASK
 
 
 /*!
@@ -10079,7 +12236,7 @@ typedef struct {
 /** Peripheral OSC base address */
 #define OSC0_BASE                                 (0x40065000u)
 /** Peripheral OSC base pointer */
-#define OSC0                                      ((OSC0_Type *)OSC0_BASE)
+#define OSC0                                      ((OSC0_TypeDef *)OSC0_BASE)
 /** Array initializer of OSC peripheral base addresses */
 #define OSC0_BASE_ADDRS                           { OSC0_BASE }
 /** Array initializer of OSC peripheral base pointers */
@@ -10119,7 +12276,7 @@ typedef struct {
        uint8_t RESERVED_1[48];
   __IO uint32_t POEN;                              /**< Pulse-Out n Enable register, offset: 0x190 */
   __IO uint32_t PODLY[4];                          /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
-} PDB_Type;
+} PDB_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- PDB Register Masks
@@ -10133,66 +12290,84 @@ typedef struct {
 /*! @name SC - Status and Control register */
 #define PDB_SC_LDOK_MASK                         (0x1U)
 #define PDB_SC_LDOK_SHIFT                        (0U)
-#define PDB_SC_LDOK(x)                           (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK)
+#define PDB_SC_LDOK_SET(x)                       (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK)
+#define PDB_SC_LDOK PDB_SC_LDOK_MASK
 #define PDB_SC_CONT_MASK                         (0x2U)
 #define PDB_SC_CONT_SHIFT                        (1U)
-#define PDB_SC_CONT(x)                           (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK)
+#define PDB_SC_CONT_SET(x)                       (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK)
+#define PDB_SC_CONT PDB_SC_CONT_MASK
 #define PDB_SC_MULT_MASK                         (0xCU)
 #define PDB_SC_MULT_SHIFT                        (2U)
-#define PDB_SC_MULT(x)                           (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK)
+#define PDB_SC_MULT_SET(x)                       (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK)
+#define PDB_SC_MULT PDB_SC_MULT_MASK
 #define PDB_SC_PDBIE_MASK                        (0x20U)
 #define PDB_SC_PDBIE_SHIFT                       (5U)
-#define PDB_SC_PDBIE(x)                          (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK)
+#define PDB_SC_PDBIE_SET(x)                      (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK)
+#define PDB_SC_PDBIE PDB_SC_PDBIE_MASK
 #define PDB_SC_PDBIF_MASK                        (0x40U)
 #define PDB_SC_PDBIF_SHIFT                       (6U)
-#define PDB_SC_PDBIF(x)                          (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK)
+#define PDB_SC_PDBIF_SET(x)                      (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK)
+#define PDB_SC_PDBIF PDB_SC_PDBIF_MASK
 #define PDB_SC_PDBEN_MASK                        (0x80U)
 #define PDB_SC_PDBEN_SHIFT                       (7U)
-#define PDB_SC_PDBEN(x)                          (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK)
+#define PDB_SC_PDBEN_SET(x)                      (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK)
+#define PDB_SC_PDBEN PDB_SC_PDBEN_MASK
 #define PDB_SC_TRGSEL_MASK                       (0xF00U)
 #define PDB_SC_TRGSEL_SHIFT                      (8U)
-#define PDB_SC_TRGSEL(x)                         (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK)
+#define PDB_SC_TRGSEL_SET(x)                     (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK)
+#define PDB_SC_TRGSEL PDB_SC_TRGSEL_MASK
 #define PDB_SC_PRESCALER_MASK                    (0x7000U)
 #define PDB_SC_PRESCALER_SHIFT                   (12U)
-#define PDB_SC_PRESCALER(x)                      (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK)
+#define PDB_SC_PRESCALER_SET(x)                  (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK)
+#define PDB_SC_PRESCALER PDB_SC_PRESCALER_MASK
 #define PDB_SC_DMAEN_MASK                        (0x8000U)
 #define PDB_SC_DMAEN_SHIFT                       (15U)
-#define PDB_SC_DMAEN(x)                          (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK)
+#define PDB_SC_DMAEN_SET(x)                      (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK)
+#define PDB_SC_DMAEN PDB_SC_DMAEN_MASK
 #define PDB_SC_SWTRIG_MASK                       (0x10000U)
 #define PDB_SC_SWTRIG_SHIFT                      (16U)
-#define PDB_SC_SWTRIG(x)                         (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK)
+#define PDB_SC_SWTRIG_SET(x)                     (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK)
+#define PDB_SC_SWTRIG PDB_SC_SWTRIG_MASK
 #define PDB_SC_PDBEIE_MASK                       (0x20000U)
 #define PDB_SC_PDBEIE_SHIFT                      (17U)
-#define PDB_SC_PDBEIE(x)                         (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK)
+#define PDB_SC_PDBEIE_SET(x)                     (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK)
+#define PDB_SC_PDBEIE PDB_SC_PDBEIE_MASK
 #define PDB_SC_LDMOD_MASK                        (0xC0000U)
 #define PDB_SC_LDMOD_SHIFT                       (18U)
-#define PDB_SC_LDMOD(x)                          (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK)
+#define PDB_SC_LDMOD_SET(x)                      (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK)
+#define PDB_SC_LDMOD PDB_SC_LDMOD_MASK
 
 /*! @name MOD - Modulus register */
 #define PDB_MOD_MOD_MASK                         (0xFFFFU)
 #define PDB_MOD_MOD_SHIFT                        (0U)
-#define PDB_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK)
+#define PDB_MOD_MOD_SET(x)                       (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK)
+#define PDB_MOD_MOD PDB_MOD_MOD_MASK
 
 /*! @name CNT - Counter register */
 #define PDB_CNT_CNT_MASK                         (0xFFFFU)
 #define PDB_CNT_CNT_SHIFT                        (0U)
-#define PDB_CNT_CNT(x)                           (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK)
+#define PDB_CNT_CNT_SET(x)                       (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK)
+#define PDB_CNT_CNT PDB_CNT_CNT_MASK
 
 /*! @name IDLY - Interrupt Delay register */
 #define PDB_IDLY_IDLY_MASK                       (0xFFFFU)
 #define PDB_IDLY_IDLY_SHIFT                      (0U)
-#define PDB_IDLY_IDLY(x)                         (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK)
+#define PDB_IDLY_IDLY_SET(x)                     (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK)
+#define PDB_IDLY_IDLY PDB_IDLY_IDLY_MASK
 
 /*! @name C1 - Channel n Control register 1 */
 #define PDB_C1_EN_MASK                           (0xFFU)
 #define PDB_C1_EN_SHIFT                          (0U)
-#define PDB_C1_EN(x)                             (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK)
+#define PDB_C1_EN_SET(x)                         (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK)
+#define PDB_C1_EN PDB_C1_EN_MASK
 #define PDB_C1_TOS_MASK                          (0xFF00U)
 #define PDB_C1_TOS_SHIFT                         (8U)
-#define PDB_C1_TOS(x)                            (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK)
+#define PDB_C1_TOS_SET(x)                        (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK)
+#define PDB_C1_TOS PDB_C1_TOS_MASK
 #define PDB_C1_BB_MASK                           (0xFF0000U)
 #define PDB_C1_BB_SHIFT                          (16U)
-#define PDB_C1_BB(x)                             (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK)
+#define PDB_C1_BB_SET(x)                         (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK)
+#define PDB_C1_BB PDB_C1_BB_MASK
 
 /* The count of PDB_C1 */
 #define PDB_C1_COUNT                             (2U)
@@ -10200,10 +12375,12 @@ typedef struct {
 /*! @name S - Channel n Status register */
 #define PDB_S_ERR_MASK                           (0xFFU)
 #define PDB_S_ERR_SHIFT                          (0U)
-#define PDB_S_ERR(x)                             (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK)
+#define PDB_S_ERR_SET(x)                         (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK)
+#define PDB_S_ERR PDB_S_ERR_MASK
 #define PDB_S_CF_MASK                            (0xFF0000U)
 #define PDB_S_CF_SHIFT                           (16U)
-#define PDB_S_CF(x)                              (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK)
+#define PDB_S_CF_SET(x)                          (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK)
+#define PDB_S_CF PDB_S_CF_MASK
 
 /* The count of PDB_S */
 #define PDB_S_COUNT                              (2U)
@@ -10211,7 +12388,8 @@ typedef struct {
 /*! @name DLY - Channel n Delay 0 register..Channel n Delay 1 register */
 #define PDB_DLY_DLY_MASK                         (0xFFFFU)
 #define PDB_DLY_DLY_SHIFT                        (0U)
-#define PDB_DLY_DLY(x)                           (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK)
+#define PDB_DLY_DLY_SET(x)                       (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK)
+#define PDB_DLY_DLY PDB_DLY_DLY_MASK
 
 /* The count of PDB_DLY */
 #define PDB_DLY_COUNT                            (2U)
@@ -10222,10 +12400,12 @@ typedef struct {
 /*! @name INTC - DAC Interval Trigger n Control register */
 #define PDB_INTC_TOE_MASK                        (0x1U)
 #define PDB_INTC_TOE_SHIFT                       (0U)
-#define PDB_INTC_TOE(x)                          (((uint32_t)(((uint32_t)(x)) << PDB_INTC_TOE_SHIFT)) & PDB_INTC_TOE_MASK)
+#define PDB_INTC_TOE_SET(x)                      (((uint32_t)(((uint32_t)(x)) << PDB_INTC_TOE_SHIFT)) & PDB_INTC_TOE_MASK)
+#define PDB_INTC_TOE PDB_INTC_TOE_MASK
 #define PDB_INTC_EXT_MASK                        (0x2U)
 #define PDB_INTC_EXT_SHIFT                       (1U)
-#define PDB_INTC_EXT(x)                          (((uint32_t)(((uint32_t)(x)) << PDB_INTC_EXT_SHIFT)) & PDB_INTC_EXT_MASK)
+#define PDB_INTC_EXT_SET(x)                      (((uint32_t)(((uint32_t)(x)) << PDB_INTC_EXT_SHIFT)) & PDB_INTC_EXT_MASK)
+#define PDB_INTC_EXT PDB_INTC_EXT_MASK
 
 /* The count of PDB_INTC */
 #define PDB_INTC_COUNT                           (2U)
@@ -10233,7 +12413,8 @@ typedef struct {
 /*! @name INT - DAC Interval n register */
 #define PDB_INT_INT_MASK                         (0xFFFFU)
 #define PDB_INT_INT_SHIFT                        (0U)
-#define PDB_INT_INT(x)                           (((uint32_t)(((uint32_t)(x)) << PDB_INT_INT_SHIFT)) & PDB_INT_INT_MASK)
+#define PDB_INT_INT_SET(x)                       (((uint32_t)(((uint32_t)(x)) << PDB_INT_INT_SHIFT)) & PDB_INT_INT_MASK)
+#define PDB_INT_INT PDB_INT_INT_MASK
 
 /* The count of PDB_INT */
 #define PDB_INT_COUNT                            (2U)
@@ -10241,15 +12422,18 @@ typedef struct {
 /*! @name POEN - Pulse-Out n Enable register */
 #define PDB_POEN_POEN_MASK                       (0xFFU)
 #define PDB_POEN_POEN_SHIFT                      (0U)
-#define PDB_POEN_POEN(x)                         (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK)
+#define PDB_POEN_POEN_SET(x)                     (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK)
+#define PDB_POEN_POEN PDB_POEN_POEN_MASK
 
 /*! @name PODLY - Pulse-Out n Delay register */
 #define PDB_PODLY_DLY2_MASK                      (0xFFFFU)
 #define PDB_PODLY_DLY2_SHIFT                     (0U)
-#define PDB_PODLY_DLY2(x)                        (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK)
+#define PDB_PODLY_DLY2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK)
+#define PDB_PODLY_DLY2 PDB_PODLY_DLY2_MASK
 #define PDB_PODLY_DLY1_MASK                      (0xFFFF0000U)
 #define PDB_PODLY_DLY1_SHIFT                     (16U)
-#define PDB_PODLY_DLY1(x)                        (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK)
+#define PDB_PODLY_DLY1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK)
+#define PDB_PODLY_DLY1 PDB_PODLY_DLY1_MASK
 
 /* The count of PDB_PODLY */
 #define PDB_PODLY_COUNT                          (4U)
@@ -10264,7 +12448,7 @@ typedef struct {
 /** Peripheral PDB0 base address */
 #define PDB0_BASE                                (0x40036000u)
 /** Peripheral PDB0 base pointer */
-#define PDB0                                     ((PDB_Type *)PDB0_BASE)
+#define PDB0                                     ((PDB_TypeDef *)PDB0_BASE)
 /** Array initializer of PDB peripheral base addresses */
 #define PDB_BASE_ADDRS                           { PDB0_BASE }
 /** Array initializer of PDB peripheral base pointers */
@@ -10293,13 +12477,13 @@ typedef struct {
   __I  uint32_t LTMR64H;                           /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
   __I  uint32_t LTMR64L;                           /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
        uint8_t RESERVED_1[24];
-  struct {                                         /* offset: 0x100, array step: 0x10 */
+  struct PIT_CHANNEL{                                         /* offset: 0x100, array step: 0x10 */
     __IO uint32_t LDVAL;                             /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
     __I  uint32_t CVAL;                              /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
     __IO uint32_t TCTRL;                             /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
     __IO uint32_t TFLG;                              /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
   } CHANNEL[4];
-} PIT_Type;
+} PIT_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- PIT Register Masks
@@ -10313,25 +12497,30 @@ typedef struct {
 /*! @name MCR - PIT Module Control Register */
 #define PIT_MCR_FRZ_MASK                         (0x1U)
 #define PIT_MCR_FRZ_SHIFT                        (0U)
-#define PIT_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
+#define PIT_MCR_FRZ_SET(x)                       (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
+#define PIT_MCR_FRZ PIT_MCR_FRZ_MASK
 #define PIT_MCR_MDIS_MASK                        (0x2U)
 #define PIT_MCR_MDIS_SHIFT                       (1U)
-#define PIT_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
+#define PIT_MCR_MDIS_SET(x)                      (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
+#define PIT_MCR_MDIS PIT_MCR_MDIS_MASK
 
 /*! @name LTMR64H - PIT Upper Lifetime Timer Register */
 #define PIT_LTMR64H_LTH_MASK                     (0xFFFFFFFFU)
 #define PIT_LTMR64H_LTH_SHIFT                    (0U)
-#define PIT_LTMR64H_LTH(x)                       (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
+#define PIT_LTMR64H_LTH_SET(x)                   (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
+#define PIT_LTMR64H_LTH PIT_LTMR64H_LTH_MASK
 
 /*! @name LTMR64L - PIT Lower Lifetime Timer Register */
 #define PIT_LTMR64L_LTL_MASK                     (0xFFFFFFFFU)
 #define PIT_LTMR64L_LTL_SHIFT                    (0U)
-#define PIT_LTMR64L_LTL(x)                       (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
+#define PIT_LTMR64L_LTL_SET(x)                   (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
+#define PIT_LTMR64L_LTL PIT_LTMR64L_LTL_MASK
 
 /*! @name LDVAL - Timer Load Value Register */
 #define PIT_LDVAL_TSV_MASK                       (0xFFFFFFFFU)
 #define PIT_LDVAL_TSV_SHIFT                      (0U)
-#define PIT_LDVAL_TSV(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
+#define PIT_LDVAL_TSV_SET(x)                     (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
+#define PIT_LDVAL_TSV PIT_LDVAL_TSV_MASK
 
 /* The count of PIT_LDVAL */
 #define PIT_LDVAL_COUNT                          (4U)
@@ -10339,32 +12528,37 @@ typedef struct {
 /*! @name CVAL - Current Timer Value Register */
 #define PIT_CVAL_TVL_MASK                        (0xFFFFFFFFU)
 #define PIT_CVAL_TVL_SHIFT                       (0U)
-#define PIT_CVAL_TVL(x)                          (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
+#define PIT_CVAL_TVL_SET(x)                      (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
+#define PIT_CVAL_TVL PIT_CVAL_TVL_MASK
 
 /* The count of PIT_CVAL */
 #define PIT_CVAL_COUNT                           (4U)
 
 /*! @name TCTRL - Timer Control Register */
-#define PIT_TCTRL_TEN_MASK                       (0x1U)
-#define PIT_TCTRL_TEN_SHIFT                      (0U)
-#define PIT_TCTRL_TEN(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
-#define PIT_TCTRL_TIE_MASK                       (0x2U)
-#define PIT_TCTRL_TIE_SHIFT                      (1U)
-#define PIT_TCTRL_TIE(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
-#define PIT_TCTRL_CHN_MASK                       (0x4U)
-#define PIT_TCTRL_CHN_SHIFT                      (2U)
-#define PIT_TCTRL_CHN(x)                         (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
+#define PIT_TCTRLn_TEN_MASK                       (0x1U)
+#define PIT_TCTRLn_TEN_SHIFT                      (0U)
+#define PIT_TCTRLn_TEN_SET(x)                     (((uint32_t)(((uint32_t)(x)) << PIT_TCTRLn_TEN_SHIFT)) & PIT_TCTRLn_TEN_MASK)
+#define PIT_TCTRLn_TEN PIT_TCTRLn_TEN_MASK
+#define PIT_TCTRLn_TIE_MASK                       (0x2U)
+#define PIT_TCTRLn_TIE_SHIFT                      (1U)
+#define PIT_TCTRLn_TIE_SET(x)                     (((uint32_t)(((uint32_t)(x)) << PIT_TCTRLn_TIE_SHIFT)) & PIT_TCTRLn_TIE_MASK)
+#define PIT_TCTRLn_TIE PIT_TCTRLn_TIE_MASK
+#define PIT_TCTRLn_CHN_MASK                       (0x4U)
+#define PIT_TCTRLn_CHN_SHIFT                      (2U)
+#define PIT_TCTRLn_CHN_SET(x)                     (((uint32_t)(((uint32_t)(x)) << PIT_TCTRLn_CHN_SHIFT)) & PIT_TCTRLn_CHN_MASK)
+#define PIT_TCTRLn_CHN PIT_TCTRLn_CHN_MASK
 
 /* The count of PIT_TCTRL */
-#define PIT_TCTRL_COUNT                          (4U)
+#define PIT_TCTRLn_COUNT                          (4U)
 
 /*! @name TFLG - Timer Flag Register */
-#define PIT_TFLG_TIF_MASK                        (0x1U)
-#define PIT_TFLG_TIF_SHIFT                       (0U)
-#define PIT_TFLG_TIF(x)                          (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
+#define PIT_TFLGn_TIF_MASK                        (0x1U)
+#define PIT_TFLGn_TIF_SHIFT                       (0U)
+#define PIT_TFLGn_TIF_SET(x)                      (((uint32_t)(((uint32_t)(x)) << PIT_TFLGn_TIF_SHIFT)) & PIT_TFLGn_TIF_MASK)
+#define PIT_TFLGn_TIF PIT_TFLGn_TIF_MASK
 
 /* The count of PIT_TFLG */
-#define PIT_TFLG_COUNT                           (4U)
+#define PIT_TFLGn_COUNT                           (4U)
 
 
 /*!
@@ -10376,7 +12570,7 @@ typedef struct {
 /** Peripheral PIT base address */
 #define PIT_BASE                                 (0x40037000u)
 /** Peripheral PIT base pointer */
-#define PIT                                      ((PIT_Type *)PIT_BASE)
+#define PIT                                      ((PIT_TypeDef *)PIT_BASE)
 /** Array initializer of PIT peripheral base addresses */
 #define PIT_BASE_ADDRS                           { PIT_BASE }
 /** Array initializer of PIT peripheral base pointers */
@@ -10403,7 +12597,7 @@ typedef struct {
   __IO uint8_t LVDSC1;                             /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
   __IO uint8_t LVDSC2;                             /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
   __IO uint8_t REGSC;                              /**< Regulator Status And Control register, offset: 0x2 */
-} PMC_Type;
+} PMC_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- PMC Register Masks
@@ -10417,47 +12611,60 @@ typedef struct {
 /*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */
 #define PMC_LVDSC1_LVDV_MASK                     (0x3U)
 #define PMC_LVDSC1_LVDV_SHIFT                    (0U)
-#define PMC_LVDSC1_LVDV(x)                       (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDV_SET(x)                   (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
+#define PMC_LVDSC1_LVDV PMC_LVDSC1_LVDV_MASK
 #define PMC_LVDSC1_LVDRE_MASK                    (0x10U)
 #define PMC_LVDSC1_LVDRE_SHIFT                   (4U)
-#define PMC_LVDSC1_LVDRE(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
+#define PMC_LVDSC1_LVDRE_SET(x)                  (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
+#define PMC_LVDSC1_LVDRE PMC_LVDSC1_LVDRE_MASK
 #define PMC_LVDSC1_LVDIE_MASK                    (0x20U)
 #define PMC_LVDSC1_LVDIE_SHIFT                   (5U)
-#define PMC_LVDSC1_LVDIE(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
+#define PMC_LVDSC1_LVDIE_SET(x)                  (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
+#define PMC_LVDSC1_LVDIE PMC_LVDSC1_LVDIE_MASK
 #define PMC_LVDSC1_LVDACK_MASK                   (0x40U)
 #define PMC_LVDSC1_LVDACK_SHIFT                  (6U)
-#define PMC_LVDSC1_LVDACK(x)                     (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
+#define PMC_LVDSC1_LVDACK_SET(x)                 (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
+#define PMC_LVDSC1_LVDACK PMC_LVDSC1_LVDACK_MASK
 #define PMC_LVDSC1_LVDF_MASK                     (0x80U)
 #define PMC_LVDSC1_LVDF_SHIFT                    (7U)
-#define PMC_LVDSC1_LVDF(x)                       (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
+#define PMC_LVDSC1_LVDF_SET(x)                   (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
+#define PMC_LVDSC1_LVDF PMC_LVDSC1_LVDF_MASK
 
 /*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */
 #define PMC_LVDSC2_LVWV_MASK                     (0x3U)
 #define PMC_LVDSC2_LVWV_SHIFT                    (0U)
-#define PMC_LVDSC2_LVWV(x)                       (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWV_SET(x)                   (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
+#define PMC_LVDSC2_LVWV PMC_LVDSC2_LVWV_MASK
 #define PMC_LVDSC2_LVWIE_MASK                    (0x20U)
 #define PMC_LVDSC2_LVWIE_SHIFT                   (5U)
-#define PMC_LVDSC2_LVWIE(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
+#define PMC_LVDSC2_LVWIE_SET(x)                  (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
+#define PMC_LVDSC2_LVWIE PMC_LVDSC2_LVWIE_MASK
 #define PMC_LVDSC2_LVWACK_MASK                   (0x40U)
 #define PMC_LVDSC2_LVWACK_SHIFT                  (6U)
-#define PMC_LVDSC2_LVWACK(x)                     (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
+#define PMC_LVDSC2_LVWACK_SET(x)                 (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
+#define PMC_LVDSC2_LVWACK PMC_LVDSC2_LVWACK_MASK
 #define PMC_LVDSC2_LVWF_MASK                     (0x80U)
 #define PMC_LVDSC2_LVWF_SHIFT                    (7U)
-#define PMC_LVDSC2_LVWF(x)                       (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
+#define PMC_LVDSC2_LVWF_SET(x)                   (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
+#define PMC_LVDSC2_LVWF PMC_LVDSC2_LVWF_MASK
 
 /*! @name REGSC - Regulator Status And Control register */
 #define PMC_REGSC_BGBE_MASK                      (0x1U)
 #define PMC_REGSC_BGBE_SHIFT                     (0U)
-#define PMC_REGSC_BGBE(x)                        (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
+#define PMC_REGSC_BGBE_SET(x)                    (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
+#define PMC_REGSC_BGBE PMC_REGSC_BGBE_MASK
 #define PMC_REGSC_REGONS_MASK                    (0x4U)
 #define PMC_REGSC_REGONS_SHIFT                   (2U)
-#define PMC_REGSC_REGONS(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
+#define PMC_REGSC_REGONS_SET(x)                  (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
+#define PMC_REGSC_REGONS PMC_REGSC_REGONS_MASK
 #define PMC_REGSC_ACKISO_MASK                    (0x8U)
 #define PMC_REGSC_ACKISO_SHIFT                   (3U)
-#define PMC_REGSC_ACKISO(x)                      (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
+#define PMC_REGSC_ACKISO_SET(x)                  (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
+#define PMC_REGSC_ACKISO PMC_REGSC_ACKISO_MASK
 #define PMC_REGSC_BGEN_MASK                      (0x10U)
 #define PMC_REGSC_BGEN_SHIFT                     (4U)
-#define PMC_REGSC_BGEN(x)                        (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
+#define PMC_REGSC_BGEN_SET(x)                    (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
+#define PMC_REGSC_BGEN PMC_REGSC_BGEN_MASK
 
 
 /*!
@@ -10469,7 +12676,7 @@ typedef struct {
 /** Peripheral PMC base address */
 #define PMC_BASE                                 (0x4007D000u)
 /** Peripheral PMC base pointer */
-#define PMC                                      ((PMC_Type *)PMC_BASE)
+#define PMC                                      ((PMC_TypeDef *)PMC_BASE)
 /** Array initializer of PMC peripheral base addresses */
 #define PMC_BASE_ADDRS                           { PMC_BASE }
 /** Array initializer of PMC peripheral base pointers */
@@ -10524,29 +12731,34 @@ typedef struct {
 #define PORTx_PCRn_PE                              PORTx_PCRn_PE_SET(1)
 #define PORTx_PCRn_SRE_MASK                        (0x4U)
 #define PORTx_PCRn_SRE_SHIFT                       (2U)
-#define PORTx_PCRn_SRE(x)                          (((uint32_t)(((uint32_t)(x)) << PORTx_PCRn_SRE_SHIFT)) & PORTx_PCRn_SRE_MASK)
+#define PORTx_PCRn_SRE_SET(x)                      (((uint32_t)(((uint32_t)(x)) << PORTx_PCRn_SRE_SHIFT)) & PORTx_PCRn_SRE_MASK)
+#define PORTx_PCRn_SRE PORTx_PCRn_SRE_MASK
 #define PORTx_PCRn_PFE_MASK                        (0x10U)
 #define PORTx_PCRn_PFE_SHIFT                       (4U)
-#define PORTx_PCRn_PFE(x)                          (((uint32_t)(((uint32_t)(x)) << PORTx_PCRn_PFE_SHIFT)) & PORTx_PCRn_PFE_MASK)
+#define PORTx_PCRn_PFE_SET(x)                      (((uint32_t)(((uint32_t)(x)) << PORTx_PCRn_PFE_SHIFT)) & PORTx_PCRn_PFE_MASK)
+#define PORTx_PCRn_PFE PORTx_PCRn_PFE_MASK
 #define PORTx_PCRn_ODE_MASK                        (0x20U)
 #define PORTx_PCRn_ODE_SHIFT                       (5U)
 #define PORTx_PCRn_ODE_SET(x)                      (((uint32_t)(((uint32_t)(x)) << PORTx_PCRn_ODE_SHIFT)) & PORTx_PCRn_ODE_MASK)
 #define PORTx_PCRn_ODE                             PORTx_PCRn_ODE_SET(1)
 #define PORTx_PCRn_DSE_MASK                        (0x40U)
 #define PORTx_PCRn_DSE_SHIFT                       (6U)
-#define PORTx_PCRn_DSE(x)                          (((uint32_t)(((uint32_t)(x)) << PORTx_PCRn_DSE_SHIFT)) & PORTx_PCRn_DSE_MASK)
+#define PORTx_PCRn_DSE_SET(x)                      (((uint32_t)(((uint32_t)(x)) << PORTx_PCRn_DSE_SHIFT)) & PORTx_PCRn_DSE_MASK)
+#define PORTx_PCRn_DSE PORTx_PCRn_DSE_MASK
 #define PORTx_PCRn_MUX_MASK                        (0x700U)
 #define PORTx_PCRn_MUX_SHIFT                       (8U)
 #define PORTx_PCRn_MUX(x)                          (((uint32_t)(((uint32_t)(x)) << PORTx_PCRn_MUX_SHIFT)) & PORTx_PCRn_MUX_MASK)
 #define PORTx_PCRn_LK_MASK                         (0x8000U)
 #define PORTx_PCRn_LK_SHIFT                        (15U)
-#define PORTx_PCRn_LK(x)                           (((uint32_t)(((uint32_t)(x)) << PORTx_PCRn_LK_SHIFT)) & PORTx_PCRn_LK_MASK)
+#define PORTx_PCRn_LK_SET(x)                       (((uint32_t)(((uint32_t)(x)) << PORTx_PCRn_LK_SHIFT)) & PORTx_PCRn_LK_MASK)
+#define PORTx_PCRn_LK PORTx_PCRn_LK_MASK
 #define PORTx_PCRn_IRQC_MASK                       (0xF0000U)
 #define PORTx_PCRn_IRQC_SHIFT                      (16U)
 #define PORTx_PCRn_IRQC(x)                         (((uint32_t)(((uint32_t)(x)) << PORTx_PCRn_IRQC_SHIFT)) & PORTx_PCRn_IRQC_MASK)
 #define PORTx_PCRn_ISF_MASK                        (0x1000000U)
 #define PORTx_PCRn_ISF_SHIFT                       (24U)
-#define PORTx_PCRn_ISF(x)                          (((uint32_t)(((uint32_t)(x)) << PORTx_PCRn_ISF_SHIFT)) & PORTx_PCRn_ISF_MASK)
+#define PORTx_PCRn_ISF_SET(x)                      (((uint32_t)(((uint32_t)(x)) << PORTx_PCRn_ISF_SHIFT)) & PORTx_PCRn_ISF_MASK)
+#define PORTx_PCRn_ISF PORTx_PCRn_ISF_MASK
 
 /* The count of PORT_PCR */
 #define PORTx_PCRn_COUNT                           (32U)
@@ -10554,38 +12766,46 @@ typedef struct {
 /*! @name GPCLR - Global Pin Control Low Register */
 #define PORT_GPCLR_GPWD_MASK                     (0xFFFFU)
 #define PORT_GPCLR_GPWD_SHIFT                    (0U)
-#define PORT_GPCLR_GPWD(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWD_SET(x)                   (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
+#define PORT_GPCLR_GPWD PORT_GPCLR_GPWD_MASK
 #define PORT_GPCLR_GPWE_MASK                     (0xFFFF0000U)
 #define PORT_GPCLR_GPWE_SHIFT                    (16U)
-#define PORT_GPCLR_GPWE(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
+#define PORT_GPCLR_GPWE_SET(x)                   (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
+#define PORT_GPCLR_GPWE PORT_GPCLR_GPWE_MASK
 
 /*! @name GPCHR - Global Pin Control High Register */
 #define PORT_GPCHR_GPWD_MASK                     (0xFFFFU)
 #define PORT_GPCHR_GPWD_SHIFT                    (0U)
-#define PORT_GPCHR_GPWD(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWD_SET(x)                   (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
+#define PORT_GPCHR_GPWD PORT_GPCHR_GPWD_MASK
 #define PORT_GPCHR_GPWE_MASK                     (0xFFFF0000U)
 #define PORT_GPCHR_GPWE_SHIFT                    (16U)
-#define PORT_GPCHR_GPWE(x)                       (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
+#define PORT_GPCHR_GPWE_SET(x)                   (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
+#define PORT_GPCHR_GPWE PORT_GPCHR_GPWE_MASK
 
 /*! @name ISFR - Interrupt Status Flag Register */
 #define PORT_ISFR_ISF_MASK                       (0xFFFFFFFFU)
 #define PORT_ISFR_ISF_SHIFT                      (0U)
-#define PORT_ISFR_ISF(x)                         (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
+#define PORT_ISFR_ISF_SET(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
+#define PORT_ISFR_ISF PORT_ISFR_ISF_MASK
 
 /*! @name DFER - Digital Filter Enable Register */
 #define PORT_DFER_DFE_MASK                       (0xFFFFFFFFU)
 #define PORT_DFER_DFE_SHIFT                      (0U)
-#define PORT_DFER_DFE(x)                         (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)
+#define PORT_DFER_DFE_SET(x)                     (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)
+#define PORT_DFER_DFE PORT_DFER_DFE_MASK
 
 /*! @name DFCR - Digital Filter Clock Register */
 #define PORT_DFCR_CS_MASK                        (0x1U)
 #define PORT_DFCR_CS_SHIFT                       (0U)
-#define PORT_DFCR_CS(x)                          (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)
+#define PORT_DFCR_CS_SET(x)                      (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)
+#define PORT_DFCR_CS PORT_DFCR_CS_MASK
 
 /*! @name DFWR - Digital Filter Width Register */
 #define PORT_DFWR_FILT_MASK                      (0x1FU)
 #define PORT_DFWR_FILT_SHIFT                     (0U)
-#define PORT_DFWR_FILT(x)                        (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)
+#define PORT_DFWR_FILT_SET(x)                    (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)
+#define PORT_DFWR_FILT PORT_DFWR_FILT_MASK
 
 
 /*!
@@ -10646,7 +12866,7 @@ typedef struct {
   __I  uint8_t MR;                                 /**< Mode Register, offset: 0x7 */
   __IO uint8_t SSRS0;                              /**< Sticky System Reset Status Register 0, offset: 0x8 */
   __IO uint8_t SSRS1;                              /**< Sticky System Reset Status Register 1, offset: 0x9 */
-} RCM_Type;
+} RCM_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- RCM Register Masks
@@ -10660,106 +12880,136 @@ typedef struct {
 /*! @name SRS0 - System Reset Status Register 0 */
 #define RCM_SRS0_WAKEUP_MASK                     (0x1U)
 #define RCM_SRS0_WAKEUP_SHIFT                    (0U)
-#define RCM_SRS0_WAKEUP(x)                       (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
+#define RCM_SRS0_WAKEUP_SET(x)                   (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
+#define RCM_SRS0_WAKEUP RCM_SRS0_WAKEUP_MASK
 #define RCM_SRS0_LVD_MASK                        (0x2U)
 #define RCM_SRS0_LVD_SHIFT                       (1U)
-#define RCM_SRS0_LVD(x)                          (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
+#define RCM_SRS0_LVD_SET(x)                      (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
+#define RCM_SRS0_LVD RCM_SRS0_LVD_MASK
 #define RCM_SRS0_LOC_MASK                        (0x4U)
 #define RCM_SRS0_LOC_SHIFT                       (2U)
-#define RCM_SRS0_LOC(x)                          (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK)
+#define RCM_SRS0_LOC_SET(x)                      (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK)
+#define RCM_SRS0_LOC RCM_SRS0_LOC_MASK
 #define RCM_SRS0_LOL_MASK                        (0x8U)
 #define RCM_SRS0_LOL_SHIFT                       (3U)
-#define RCM_SRS0_LOL(x)                          (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK)
+#define RCM_SRS0_LOL_SET(x)                      (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK)
+#define RCM_SRS0_LOL RCM_SRS0_LOL_MASK
 #define RCM_SRS0_WDOG_MASK                       (0x20U)
 #define RCM_SRS0_WDOG_SHIFT                      (5U)
-#define RCM_SRS0_WDOG(x)                         (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
+#define RCM_SRS0_WDOG_SET(x)                     (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
+#define RCM_SRS0_WDOG RCM_SRS0_WDOG_MASK
 #define RCM_SRS0_PIN_MASK                        (0x40U)
 #define RCM_SRS0_PIN_SHIFT                       (6U)
-#define RCM_SRS0_PIN(x)                          (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
+#define RCM_SRS0_PIN_SET(x)                      (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
+#define RCM_SRS0_PIN RCM_SRS0_PIN_MASK
 #define RCM_SRS0_POR_MASK                        (0x80U)
 #define RCM_SRS0_POR_SHIFT                       (7U)
-#define RCM_SRS0_POR(x)                          (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
+#define RCM_SRS0_POR_SET(x)                      (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
+#define RCM_SRS0_POR RCM_SRS0_POR_MASK
 
 /*! @name SRS1 - System Reset Status Register 1 */
 #define RCM_SRS1_JTAG_MASK                       (0x1U)
 #define RCM_SRS1_JTAG_SHIFT                      (0U)
-#define RCM_SRS1_JTAG(x)                         (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_JTAG_SHIFT)) & RCM_SRS1_JTAG_MASK)
+#define RCM_SRS1_JTAG_SET(x)                     (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_JTAG_SHIFT)) & RCM_SRS1_JTAG_MASK)
+#define RCM_SRS1_JTAG RCM_SRS1_JTAG_MASK
 #define RCM_SRS1_LOCKUP_MASK                     (0x2U)
 #define RCM_SRS1_LOCKUP_SHIFT                    (1U)
-#define RCM_SRS1_LOCKUP(x)                       (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
+#define RCM_SRS1_LOCKUP_SET(x)                   (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
+#define RCM_SRS1_LOCKUP RCM_SRS1_LOCKUP_MASK
 #define RCM_SRS1_SW_MASK                         (0x4U)
 #define RCM_SRS1_SW_SHIFT                        (2U)
-#define RCM_SRS1_SW(x)                           (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
+#define RCM_SRS1_SW_SET(x)                       (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
+#define RCM_SRS1_SW RCM_SRS1_SW_MASK
 #define RCM_SRS1_MDM_AP_MASK                     (0x8U)
 #define RCM_SRS1_MDM_AP_SHIFT                    (3U)
-#define RCM_SRS1_MDM_AP(x)                       (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
+#define RCM_SRS1_MDM_AP_SET(x)                   (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
+#define RCM_SRS1_MDM_AP RCM_SRS1_MDM_AP_MASK
 #define RCM_SRS1_EZPT_MASK                       (0x10U)
 #define RCM_SRS1_EZPT_SHIFT                      (4U)
-#define RCM_SRS1_EZPT(x)                         (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_EZPT_SHIFT)) & RCM_SRS1_EZPT_MASK)
+#define RCM_SRS1_EZPT_SET(x)                     (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_EZPT_SHIFT)) & RCM_SRS1_EZPT_MASK)
+#define RCM_SRS1_EZPT RCM_SRS1_EZPT_MASK
 #define RCM_SRS1_SACKERR_MASK                    (0x20U)
 #define RCM_SRS1_SACKERR_SHIFT                   (5U)
-#define RCM_SRS1_SACKERR(x)                      (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
+#define RCM_SRS1_SACKERR_SET(x)                  (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
+#define RCM_SRS1_SACKERR RCM_SRS1_SACKERR_MASK
 
 /*! @name RPFC - Reset Pin Filter Control register */
 #define RCM_RPFC_RSTFLTSRW_MASK                  (0x3U)
 #define RCM_RPFC_RSTFLTSRW_SHIFT                 (0U)
-#define RCM_RPFC_RSTFLTSRW(x)                    (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSRW_SET(x)                (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
+#define RCM_RPFC_RSTFLTSRW RCM_RPFC_RSTFLTSRW_MASK
 #define RCM_RPFC_RSTFLTSS_MASK                   (0x4U)
 #define RCM_RPFC_RSTFLTSS_SHIFT                  (2U)
-#define RCM_RPFC_RSTFLTSS(x)                     (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
+#define RCM_RPFC_RSTFLTSS_SET(x)                 (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
+#define RCM_RPFC_RSTFLTSS RCM_RPFC_RSTFLTSS_MASK
 
 /*! @name RPFW - Reset Pin Filter Width register */
 #define RCM_RPFW_RSTFLTSEL_MASK                  (0x1FU)
 #define RCM_RPFW_RSTFLTSEL_SHIFT                 (0U)
-#define RCM_RPFW_RSTFLTSEL(x)                    (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
+#define RCM_RPFW_RSTFLTSEL_SET(x)                (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
+#define RCM_RPFW_RSTFLTSEL RCM_RPFW_RSTFLTSEL_MASK
 
 /*! @name MR - Mode Register */
 #define RCM_MR_EZP_MS_MASK                       (0x2U)
 #define RCM_MR_EZP_MS_SHIFT                      (1U)
-#define RCM_MR_EZP_MS(x)                         (((uint8_t)(((uint8_t)(x)) << RCM_MR_EZP_MS_SHIFT)) & RCM_MR_EZP_MS_MASK)
+#define RCM_MR_EZP_MS_SET(x)                     (((uint8_t)(((uint8_t)(x)) << RCM_MR_EZP_MS_SHIFT)) & RCM_MR_EZP_MS_MASK)
+#define RCM_MR_EZP_MS RCM_MR_EZP_MS_MASK
 
 /*! @name SSRS0 - Sticky System Reset Status Register 0 */
 #define RCM_SSRS0_SWAKEUP_MASK                   (0x1U)
 #define RCM_SSRS0_SWAKEUP_SHIFT                  (0U)
-#define RCM_SSRS0_SWAKEUP(x)                     (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWAKEUP_SHIFT)) & RCM_SSRS0_SWAKEUP_MASK)
+#define RCM_SSRS0_SWAKEUP_SET(x)                 (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWAKEUP_SHIFT)) & RCM_SSRS0_SWAKEUP_MASK)
+#define RCM_SSRS0_SWAKEUP RCM_SSRS0_SWAKEUP_MASK
 #define RCM_SSRS0_SLVD_MASK                      (0x2U)
 #define RCM_SSRS0_SLVD_SHIFT                     (1U)
-#define RCM_SSRS0_SLVD(x)                        (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLVD_SHIFT)) & RCM_SSRS0_SLVD_MASK)
+#define RCM_SSRS0_SLVD_SET(x)                    (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLVD_SHIFT)) & RCM_SSRS0_SLVD_MASK)
+#define RCM_SSRS0_SLVD RCM_SSRS0_SLVD_MASK
 #define RCM_SSRS0_SLOC_MASK                      (0x4U)
 #define RCM_SSRS0_SLOC_SHIFT                     (2U)
-#define RCM_SSRS0_SLOC(x)                        (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOC_SHIFT)) & RCM_SSRS0_SLOC_MASK)
+#define RCM_SSRS0_SLOC_SET(x)                    (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOC_SHIFT)) & RCM_SSRS0_SLOC_MASK)
+#define RCM_SSRS0_SLOC RCM_SSRS0_SLOC_MASK
 #define RCM_SSRS0_SLOL_MASK                      (0x8U)
 #define RCM_SSRS0_SLOL_SHIFT                     (3U)
-#define RCM_SSRS0_SLOL(x)                        (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOL_SHIFT)) & RCM_SSRS0_SLOL_MASK)
+#define RCM_SSRS0_SLOL_SET(x)                    (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SLOL_SHIFT)) & RCM_SSRS0_SLOL_MASK)
+#define RCM_SSRS0_SLOL RCM_SSRS0_SLOL_MASK
 #define RCM_SSRS0_SWDOG_MASK                     (0x20U)
 #define RCM_SSRS0_SWDOG_SHIFT                    (5U)
-#define RCM_SSRS0_SWDOG(x)                       (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWDOG_SHIFT)) & RCM_SSRS0_SWDOG_MASK)
+#define RCM_SSRS0_SWDOG_SET(x)                   (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SWDOG_SHIFT)) & RCM_SSRS0_SWDOG_MASK)
+#define RCM_SSRS0_SWDOG RCM_SSRS0_SWDOG_MASK
 #define RCM_SSRS0_SPIN_MASK                      (0x40U)
 #define RCM_SSRS0_SPIN_SHIFT                     (6U)
-#define RCM_SSRS0_SPIN(x)                        (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPIN_SHIFT)) & RCM_SSRS0_SPIN_MASK)
+#define RCM_SSRS0_SPIN_SET(x)                    (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPIN_SHIFT)) & RCM_SSRS0_SPIN_MASK)
+#define RCM_SSRS0_SPIN RCM_SSRS0_SPIN_MASK
 #define RCM_SSRS0_SPOR_MASK                      (0x80U)
 #define RCM_SSRS0_SPOR_SHIFT                     (7U)
-#define RCM_SSRS0_SPOR(x)                        (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPOR_SHIFT)) & RCM_SSRS0_SPOR_MASK)
+#define RCM_SSRS0_SPOR_SET(x)                    (((uint8_t)(((uint8_t)(x)) << RCM_SSRS0_SPOR_SHIFT)) & RCM_SSRS0_SPOR_MASK)
+#define RCM_SSRS0_SPOR RCM_SSRS0_SPOR_MASK
 
 /*! @name SSRS1 - Sticky System Reset Status Register 1 */
 #define RCM_SSRS1_SJTAG_MASK                     (0x1U)
 #define RCM_SSRS1_SJTAG_SHIFT                    (0U)
-#define RCM_SSRS1_SJTAG(x)                       (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SJTAG_SHIFT)) & RCM_SSRS1_SJTAG_MASK)
+#define RCM_SSRS1_SJTAG_SET(x)                   (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SJTAG_SHIFT)) & RCM_SSRS1_SJTAG_MASK)
+#define RCM_SSRS1_SJTAG RCM_SSRS1_SJTAG_MASK
 #define RCM_SSRS1_SLOCKUP_MASK                   (0x2U)
 #define RCM_SSRS1_SLOCKUP_SHIFT                  (1U)
-#define RCM_SSRS1_SLOCKUP(x)                     (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SLOCKUP_SHIFT)) & RCM_SSRS1_SLOCKUP_MASK)
+#define RCM_SSRS1_SLOCKUP_SET(x)                 (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SLOCKUP_SHIFT)) & RCM_SSRS1_SLOCKUP_MASK)
+#define RCM_SSRS1_SLOCKUP RCM_SSRS1_SLOCKUP_MASK
 #define RCM_SSRS1_SSW_MASK                       (0x4U)
 #define RCM_SSRS1_SSW_SHIFT                      (2U)
-#define RCM_SSRS1_SSW(x)                         (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSW_SHIFT)) & RCM_SSRS1_SSW_MASK)
+#define RCM_SSRS1_SSW_SET(x)                     (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSW_SHIFT)) & RCM_SSRS1_SSW_MASK)
+#define RCM_SSRS1_SSW RCM_SSRS1_SSW_MASK
 #define RCM_SSRS1_SMDM_AP_MASK                   (0x8U)
 #define RCM_SSRS1_SMDM_AP_SHIFT                  (3U)
-#define RCM_SSRS1_SMDM_AP(x)                     (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SMDM_AP_SHIFT)) & RCM_SSRS1_SMDM_AP_MASK)
+#define RCM_SSRS1_SMDM_AP_SET(x)                 (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SMDM_AP_SHIFT)) & RCM_SSRS1_SMDM_AP_MASK)
+#define RCM_SSRS1_SMDM_AP RCM_SSRS1_SMDM_AP_MASK
 #define RCM_SSRS1_SEZPT_MASK                     (0x10U)
 #define RCM_SSRS1_SEZPT_SHIFT                    (4U)
-#define RCM_SSRS1_SEZPT(x)                       (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SEZPT_SHIFT)) & RCM_SSRS1_SEZPT_MASK)
+#define RCM_SSRS1_SEZPT_SET(x)                   (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SEZPT_SHIFT)) & RCM_SSRS1_SEZPT_MASK)
+#define RCM_SSRS1_SEZPT RCM_SSRS1_SEZPT_MASK
 #define RCM_SSRS1_SSACKERR_MASK                  (0x20U)
 #define RCM_SSRS1_SSACKERR_SHIFT                 (5U)
-#define RCM_SSRS1_SSACKERR(x)                    (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSACKERR_SHIFT)) & RCM_SSRS1_SSACKERR_MASK)
+#define RCM_SSRS1_SSACKERR_SET(x)                (((uint8_t)(((uint8_t)(x)) << RCM_SSRS1_SSACKERR_SHIFT)) & RCM_SSRS1_SSACKERR_MASK)
+#define RCM_SSRS1_SSACKERR RCM_SSRS1_SSACKERR_MASK
 
 
 /*!
@@ -10771,7 +13021,7 @@ typedef struct {
 /** Peripheral RCM base address */
 #define RCM_BASE                                 (0x4007F000u)
 /** Peripheral RCM base pointer */
-#define RCM                                      ((RCM_Type *)RCM_BASE)
+#define RCM                                      ((RCM_TypeDef *)RCM_BASE)
 /** Array initializer of RCM peripheral base addresses */
 #define RCM_BASE_ADDRS                           { RCM_BASE }
 /** Array initializer of RCM peripheral base pointers */
@@ -10794,7 +13044,7 @@ typedef struct {
 /** RFSYS - Register Layout Typedef */
 typedef struct {
   __IO uint32_t REG[8];                            /**< Register file register, array offset: 0x0, array step: 0x4 */
-} RFSYS_Type;
+} RFSYS_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- RFSYS Register Masks
@@ -10808,16 +13058,20 @@ typedef struct {
 /*! @name REG - Register file register */
 #define RFSYS_REG_LL_MASK                        (0xFFU)
 #define RFSYS_REG_LL_SHIFT                       (0U)
-#define RFSYS_REG_LL(x)                          (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
+#define RFSYS_REG_LL_SET(x)                      (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
+#define RFSYS_REG_LL RFSYS_REG_LL_MASK
 #define RFSYS_REG_LH_MASK                        (0xFF00U)
 #define RFSYS_REG_LH_SHIFT                       (8U)
-#define RFSYS_REG_LH(x)                          (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
+#define RFSYS_REG_LH_SET(x)                      (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
+#define RFSYS_REG_LH RFSYS_REG_LH_MASK
 #define RFSYS_REG_HL_MASK                        (0xFF0000U)
 #define RFSYS_REG_HL_SHIFT                       (16U)
-#define RFSYS_REG_HL(x)                          (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
+#define RFSYS_REG_HL_SET(x)                      (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
+#define RFSYS_REG_HL RFSYS_REG_HL_MASK
 #define RFSYS_REG_HH_MASK                        (0xFF000000U)
 #define RFSYS_REG_HH_SHIFT                       (24U)
-#define RFSYS_REG_HH(x)                          (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
+#define RFSYS_REG_HH_SET(x)                      (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
+#define RFSYS_REG_HH RFSYS_REG_HH_MASK
 
 /* The count of RFSYS_REG */
 #define RFSYS_REG_COUNT                          (8U)
@@ -10832,7 +13086,7 @@ typedef struct {
 /** Peripheral RFSYS base address */
 #define RFSYS_BASE                               (0x40041000u)
 /** Peripheral RFSYS base pointer */
-#define RFSYS                                    ((RFSYS_Type *)RFSYS_BASE)
+#define RFSYS                                    ((RFSYS_TypeDef *)RFSYS_BASE)
 /** Array initializer of RFSYS peripheral base addresses */
 #define RFSYS_BASE_ADDRS                         { RFSYS_BASE }
 /** Array initializer of RFSYS peripheral base pointers */
@@ -10855,7 +13109,7 @@ typedef struct {
 /** RFVBAT - Register Layout Typedef */
 typedef struct {
   __IO uint32_t REG[8];                            /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
-} RFVBAT_Type;
+} RFVBAT_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- RFVBAT Register Masks
@@ -10869,16 +13123,20 @@ typedef struct {
 /*! @name REG - VBAT register file register */
 #define RFVBAT_REG_LL_MASK                       (0xFFU)
 #define RFVBAT_REG_LL_SHIFT                      (0U)
-#define RFVBAT_REG_LL(x)                         (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LL_SHIFT)) & RFVBAT_REG_LL_MASK)
+#define RFVBAT_REG_LL_SET(x)                     (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LL_SHIFT)) & RFVBAT_REG_LL_MASK)
+#define RFVBAT_REG_LL RFVBAT_REG_LL_MASK
 #define RFVBAT_REG_LH_MASK                       (0xFF00U)
 #define RFVBAT_REG_LH_SHIFT                      (8U)
-#define RFVBAT_REG_LH(x)                         (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LH_SHIFT)) & RFVBAT_REG_LH_MASK)
+#define RFVBAT_REG_LH_SET(x)                     (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LH_SHIFT)) & RFVBAT_REG_LH_MASK)
+#define RFVBAT_REG_LH RFVBAT_REG_LH_MASK
 #define RFVBAT_REG_HL_MASK                       (0xFF0000U)
 #define RFVBAT_REG_HL_SHIFT                      (16U)
-#define RFVBAT_REG_HL(x)                         (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HL_SHIFT)) & RFVBAT_REG_HL_MASK)
+#define RFVBAT_REG_HL_SET(x)                     (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HL_SHIFT)) & RFVBAT_REG_HL_MASK)
+#define RFVBAT_REG_HL RFVBAT_REG_HL_MASK
 #define RFVBAT_REG_HH_MASK                       (0xFF000000U)
 #define RFVBAT_REG_HH_SHIFT                      (24U)
-#define RFVBAT_REG_HH(x)                         (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HH_SHIFT)) & RFVBAT_REG_HH_MASK)
+#define RFVBAT_REG_HH_SET(x)                     (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HH_SHIFT)) & RFVBAT_REG_HH_MASK)
+#define RFVBAT_REG_HH RFVBAT_REG_HH_MASK
 
 /* The count of RFVBAT_REG */
 #define RFVBAT_REG_COUNT                         (8U)
@@ -10893,7 +13151,7 @@ typedef struct {
 /** Peripheral RFVBAT base address */
 #define RFVBAT_BASE                              (0x4003E000u)
 /** Peripheral RFVBAT base pointer */
-#define RFVBAT                                   ((RFVBAT_Type *)RFVBAT_BASE)
+#define RFVBAT                                   ((RFVBAT_TypeDef *)RFVBAT_BASE)
 /** Array initializer of RFVBAT peripheral base addresses */
 #define RFVBAT_BASE_ADDRS                        { RFVBAT_BASE }
 /** Array initializer of RFVBAT peripheral base pointers */
@@ -10919,7 +13177,7 @@ typedef struct {
   __I  uint32_t SR;                                /**< RNGA Status Register, offset: 0x4 */
   __O  uint32_t ER;                                /**< RNGA Entropy Register, offset: 0x8 */
   __I  uint32_t OR;                                /**< RNGA Output Register, offset: 0xC */
-} RNG_Type;
+} RNG_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- RNG Register Masks
@@ -10933,52 +13191,66 @@ typedef struct {
 /*! @name CR - RNGA Control Register */
 #define RNG_CR_GO_MASK                           (0x1U)
 #define RNG_CR_GO_SHIFT                          (0U)
-#define RNG_CR_GO(x)                             (((uint32_t)(((uint32_t)(x)) << RNG_CR_GO_SHIFT)) & RNG_CR_GO_MASK)
+#define RNG_CR_GO_SET(x)                         (((uint32_t)(((uint32_t)(x)) << RNG_CR_GO_SHIFT)) & RNG_CR_GO_MASK)
+#define RNG_CR_GO RNG_CR_GO_MASK
 #define RNG_CR_HA_MASK                           (0x2U)
 #define RNG_CR_HA_SHIFT                          (1U)
-#define RNG_CR_HA(x)                             (((uint32_t)(((uint32_t)(x)) << RNG_CR_HA_SHIFT)) & RNG_CR_HA_MASK)
+#define RNG_CR_HA_SET(x)                         (((uint32_t)(((uint32_t)(x)) << RNG_CR_HA_SHIFT)) & RNG_CR_HA_MASK)
+#define RNG_CR_HA RNG_CR_HA_MASK
 #define RNG_CR_INTM_MASK                         (0x4U)
 #define RNG_CR_INTM_SHIFT                        (2U)
-#define RNG_CR_INTM(x)                           (((uint32_t)(((uint32_t)(x)) << RNG_CR_INTM_SHIFT)) & RNG_CR_INTM_MASK)
+#define RNG_CR_INTM_SET(x)                       (((uint32_t)(((uint32_t)(x)) << RNG_CR_INTM_SHIFT)) & RNG_CR_INTM_MASK)
+#define RNG_CR_INTM RNG_CR_INTM_MASK
 #define RNG_CR_CLRI_MASK                         (0x8U)
 #define RNG_CR_CLRI_SHIFT                        (3U)
-#define RNG_CR_CLRI(x)                           (((uint32_t)(((uint32_t)(x)) << RNG_CR_CLRI_SHIFT)) & RNG_CR_CLRI_MASK)
+#define RNG_CR_CLRI_SET(x)                       (((uint32_t)(((uint32_t)(x)) << RNG_CR_CLRI_SHIFT)) & RNG_CR_CLRI_MASK)
+#define RNG_CR_CLRI RNG_CR_CLRI_MASK
 #define RNG_CR_SLP_MASK                          (0x10U)
 #define RNG_CR_SLP_SHIFT                         (4U)
-#define RNG_CR_SLP(x)                            (((uint32_t)(((uint32_t)(x)) << RNG_CR_SLP_SHIFT)) & RNG_CR_SLP_MASK)
+#define RNG_CR_SLP_SET(x)                        (((uint32_t)(((uint32_t)(x)) << RNG_CR_SLP_SHIFT)) & RNG_CR_SLP_MASK)
+#define RNG_CR_SLP RNG_CR_SLP_MASK
 
 /*! @name SR - RNGA Status Register */
 #define RNG_SR_SECV_MASK                         (0x1U)
 #define RNG_SR_SECV_SHIFT                        (0U)
-#define RNG_SR_SECV(x)                           (((uint32_t)(((uint32_t)(x)) << RNG_SR_SECV_SHIFT)) & RNG_SR_SECV_MASK)
+#define RNG_SR_SECV_SET(x)                       (((uint32_t)(((uint32_t)(x)) << RNG_SR_SECV_SHIFT)) & RNG_SR_SECV_MASK)
+#define RNG_SR_SECV RNG_SR_SECV_MASK
 #define RNG_SR_LRS_MASK                          (0x2U)
 #define RNG_SR_LRS_SHIFT                         (1U)
-#define RNG_SR_LRS(x)                            (((uint32_t)(((uint32_t)(x)) << RNG_SR_LRS_SHIFT)) & RNG_SR_LRS_MASK)
+#define RNG_SR_LRS_SET(x)                        (((uint32_t)(((uint32_t)(x)) << RNG_SR_LRS_SHIFT)) & RNG_SR_LRS_MASK)
+#define RNG_SR_LRS RNG_SR_LRS_MASK
 #define RNG_SR_ORU_MASK                          (0x4U)
 #define RNG_SR_ORU_SHIFT                         (2U)
-#define RNG_SR_ORU(x)                            (((uint32_t)(((uint32_t)(x)) << RNG_SR_ORU_SHIFT)) & RNG_SR_ORU_MASK)
+#define RNG_SR_ORU_SET(x)                        (((uint32_t)(((uint32_t)(x)) << RNG_SR_ORU_SHIFT)) & RNG_SR_ORU_MASK)
+#define RNG_SR_ORU RNG_SR_ORU_MASK
 #define RNG_SR_ERRI_MASK                         (0x8U)
 #define RNG_SR_ERRI_SHIFT                        (3U)
-#define RNG_SR_ERRI(x)                           (((uint32_t)(((uint32_t)(x)) << RNG_SR_ERRI_SHIFT)) & RNG_SR_ERRI_MASK)
+#define RNG_SR_ERRI_SET(x)                       (((uint32_t)(((uint32_t)(x)) << RNG_SR_ERRI_SHIFT)) & RNG_SR_ERRI_MASK)
+#define RNG_SR_ERRI RNG_SR_ERRI_MASK
 #define RNG_SR_SLP_MASK                          (0x10U)
 #define RNG_SR_SLP_SHIFT                         (4U)
-#define RNG_SR_SLP(x)                            (((uint32_t)(((uint32_t)(x)) << RNG_SR_SLP_SHIFT)) & RNG_SR_SLP_MASK)
+#define RNG_SR_SLP_SET(x)                        (((uint32_t)(((uint32_t)(x)) << RNG_SR_SLP_SHIFT)) & RNG_SR_SLP_MASK)
+#define RNG_SR_SLP RNG_SR_SLP_MASK
 #define RNG_SR_OREG_LVL_MASK                     (0xFF00U)
 #define RNG_SR_OREG_LVL_SHIFT                    (8U)
-#define RNG_SR_OREG_LVL(x)                       (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_LVL_SHIFT)) & RNG_SR_OREG_LVL_MASK)
+#define RNG_SR_OREG_LVL_SET(x)                   (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_LVL_SHIFT)) & RNG_SR_OREG_LVL_MASK)
+#define RNG_SR_OREG_LVL RNG_SR_OREG_LVL_MASK
 #define RNG_SR_OREG_SIZE_MASK                    (0xFF0000U)
 #define RNG_SR_OREG_SIZE_SHIFT                   (16U)
-#define RNG_SR_OREG_SIZE(x)                      (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_SIZE_SHIFT)) & RNG_SR_OREG_SIZE_MASK)
+#define RNG_SR_OREG_SIZE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_SIZE_SHIFT)) & RNG_SR_OREG_SIZE_MASK)
+#define RNG_SR_OREG_SIZE RNG_SR_OREG_SIZE_MASK
 
 /*! @name ER - RNGA Entropy Register */
 #define RNG_ER_EXT_ENT_MASK                      (0xFFFFFFFFU)
 #define RNG_ER_EXT_ENT_SHIFT                     (0U)
-#define RNG_ER_EXT_ENT(x)                        (((uint32_t)(((uint32_t)(x)) << RNG_ER_EXT_ENT_SHIFT)) & RNG_ER_EXT_ENT_MASK)
+#define RNG_ER_EXT_ENT_SET(x)                    (((uint32_t)(((uint32_t)(x)) << RNG_ER_EXT_ENT_SHIFT)) & RNG_ER_EXT_ENT_MASK)
+#define RNG_ER_EXT_ENT RNG_ER_EXT_ENT_MASK
 
 /*! @name OR - RNGA Output Register */
 #define RNG_OR_RANDOUT_MASK                      (0xFFFFFFFFU)
 #define RNG_OR_RANDOUT_SHIFT                     (0U)
-#define RNG_OR_RANDOUT(x)                        (((uint32_t)(((uint32_t)(x)) << RNG_OR_RANDOUT_SHIFT)) & RNG_OR_RANDOUT_MASK)
+#define RNG_OR_RANDOUT_SET(x)                    (((uint32_t)(((uint32_t)(x)) << RNG_OR_RANDOUT_SHIFT)) & RNG_OR_RANDOUT_MASK)
+#define RNG_OR_RANDOUT RNG_OR_RANDOUT_MASK
 
 
 /*!
@@ -10990,7 +13262,7 @@ typedef struct {
 /** Peripheral RNG base address */
 #define RNG_BASE                                 (0x400A0000u)
 /** Peripheral RNG base pointer */
-#define RNG                                      ((RNG_Type *)RNG_BASE)
+#define RNG                                      ((RNG_TypeDef *)RNG_BASE)
 /** Array initializer of RNG peripheral base addresses */
 #define RNG_BASE_ADDRS                           { RNG_BASE }
 /** Array initializer of RNG peripheral base pointers */
@@ -11029,7 +13301,7 @@ typedef struct {
        uint8_t RESERVED_0[2000];
   __IO uint32_t WAR;                               /**< RTC Write Access Register, offset: 0x800 */
   __IO uint32_t RAR;                               /**< RTC Read Access Register, offset: 0x804 */
-} RTC_Type;
+} RTC_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- RTC Register Masks
@@ -11043,225 +13315,290 @@ typedef struct {
 /*! @name TSR - RTC Time Seconds Register */
 #define RTC_TSR_TSR_MASK                         (0xFFFFFFFFU)
 #define RTC_TSR_TSR_SHIFT                        (0U)
-#define RTC_TSR_TSR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
+#define RTC_TSR_TSR_SET(x)                       (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
+#define RTC_TSR_TSR RTC_TSR_TSR_MASK
 
 /*! @name TPR - RTC Time Prescaler Register */
 #define RTC_TPR_TPR_MASK                         (0xFFFFU)
 #define RTC_TPR_TPR_SHIFT                        (0U)
-#define RTC_TPR_TPR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
+#define RTC_TPR_TPR_SET(x)                       (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
+#define RTC_TPR_TPR RTC_TPR_TPR_MASK
 
 /*! @name TAR - RTC Time Alarm Register */
 #define RTC_TAR_TAR_MASK                         (0xFFFFFFFFU)
 #define RTC_TAR_TAR_SHIFT                        (0U)
-#define RTC_TAR_TAR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
+#define RTC_TAR_TAR_SET(x)                       (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
+#define RTC_TAR_TAR RTC_TAR_TAR_MASK
 
 /*! @name TCR - RTC Time Compensation Register */
 #define RTC_TCR_TCR_MASK                         (0xFFU)
 #define RTC_TCR_TCR_SHIFT                        (0U)
-#define RTC_TCR_TCR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
+#define RTC_TCR_TCR_SET(x)                       (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
+#define RTC_TCR_TCR RTC_TCR_TCR_MASK
 #define RTC_TCR_CIR_MASK                         (0xFF00U)
 #define RTC_TCR_CIR_SHIFT                        (8U)
-#define RTC_TCR_CIR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
+#define RTC_TCR_CIR_SET(x)                       (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
+#define RTC_TCR_CIR RTC_TCR_CIR_MASK
 #define RTC_TCR_TCV_MASK                         (0xFF0000U)
 #define RTC_TCR_TCV_SHIFT                        (16U)
-#define RTC_TCR_TCV(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
+#define RTC_TCR_TCV_SET(x)                       (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
+#define RTC_TCR_TCV RTC_TCR_TCV_MASK
 #define RTC_TCR_CIC_MASK                         (0xFF000000U)
 #define RTC_TCR_CIC_SHIFT                        (24U)
-#define RTC_TCR_CIC(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
+#define RTC_TCR_CIC_SET(x)                       (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
+#define RTC_TCR_CIC RTC_TCR_CIC_MASK
 
 /*! @name CR - RTC Control Register */
 #define RTC_CR_SWR_MASK                          (0x1U)
 #define RTC_CR_SWR_SHIFT                         (0U)
-#define RTC_CR_SWR(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
+#define RTC_CR_SWR_SET(x)                        (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
+#define RTC_CR_SWR RTC_CR_SWR_MASK
 #define RTC_CR_WPE_MASK                          (0x2U)
 #define RTC_CR_WPE_SHIFT                         (1U)
-#define RTC_CR_WPE(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
+#define RTC_CR_WPE_SET(x)                        (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
+#define RTC_CR_WPE RTC_CR_WPE_MASK
 #define RTC_CR_SUP_MASK                          (0x4U)
 #define RTC_CR_SUP_SHIFT                         (2U)
-#define RTC_CR_SUP(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
+#define RTC_CR_SUP_SET(x)                        (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
+#define RTC_CR_SUP RTC_CR_SUP_MASK
 #define RTC_CR_UM_MASK                           (0x8U)
 #define RTC_CR_UM_SHIFT                          (3U)
-#define RTC_CR_UM(x)                             (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
+#define RTC_CR_UM_SET(x)                         (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
+#define RTC_CR_UM RTC_CR_UM_MASK
 #define RTC_CR_WPS_MASK                          (0x10U)
 #define RTC_CR_WPS_SHIFT                         (4U)
-#define RTC_CR_WPS(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
+#define RTC_CR_WPS_SET(x)                        (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
+#define RTC_CR_WPS RTC_CR_WPS_MASK
 #define RTC_CR_OSCE_MASK                         (0x100U)
 #define RTC_CR_OSCE_SHIFT                        (8U)
-#define RTC_CR_OSCE(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
+#define RTC_CR_OSCE_SET(x)                       (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
+#define RTC_CR_OSCE RTC_CR_OSCE_MASK
 #define RTC_CR_CLKO_MASK                         (0x200U)
 #define RTC_CR_CLKO_SHIFT                        (9U)
-#define RTC_CR_CLKO(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
+#define RTC_CR_CLKO_SET(x)                       (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
+#define RTC_CR_CLKO RTC_CR_CLKO_MASK
 #define RTC_CR_SC16P_MASK                        (0x400U)
 #define RTC_CR_SC16P_SHIFT                       (10U)
-#define RTC_CR_SC16P(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
+#define RTC_CR_SC16P_SET(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
+#define RTC_CR_SC16P RTC_CR_SC16P_MASK
 #define RTC_CR_SC8P_MASK                         (0x800U)
 #define RTC_CR_SC8P_SHIFT                        (11U)
-#define RTC_CR_SC8P(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
+#define RTC_CR_SC8P_SET(x)                       (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
+#define RTC_CR_SC8P RTC_CR_SC8P_MASK
 #define RTC_CR_SC4P_MASK                         (0x1000U)
 #define RTC_CR_SC4P_SHIFT                        (12U)
-#define RTC_CR_SC4P(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
+#define RTC_CR_SC4P_SET(x)                       (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
+#define RTC_CR_SC4P RTC_CR_SC4P_MASK
 #define RTC_CR_SC2P_MASK                         (0x2000U)
 #define RTC_CR_SC2P_SHIFT                        (13U)
-#define RTC_CR_SC2P(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
+#define RTC_CR_SC2P_SET(x)                       (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
+#define RTC_CR_SC2P RTC_CR_SC2P_MASK
 
 /*! @name SR - RTC Status Register */
 #define RTC_SR_TIF_MASK                          (0x1U)
 #define RTC_SR_TIF_SHIFT                         (0U)
-#define RTC_SR_TIF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
+#define RTC_SR_TIF_SET(x)                        (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
+#define RTC_SR_TIF RTC_SR_TIF_MASK
 #define RTC_SR_TOF_MASK                          (0x2U)
 #define RTC_SR_TOF_SHIFT                         (1U)
-#define RTC_SR_TOF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
+#define RTC_SR_TOF_SET(x)                        (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
+#define RTC_SR_TOF RTC_SR_TOF_MASK
 #define RTC_SR_TAF_MASK                          (0x4U)
 #define RTC_SR_TAF_SHIFT                         (2U)
-#define RTC_SR_TAF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
+#define RTC_SR_TAF_SET(x)                        (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
+#define RTC_SR_TAF RTC_SR_TAF_MASK
 #define RTC_SR_MOF_MASK                          (0x8U)
 #define RTC_SR_MOF_SHIFT                         (3U)
-#define RTC_SR_MOF(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_MOF_SHIFT)) & RTC_SR_MOF_MASK)
+#define RTC_SR_MOF_SET(x)                        (((uint32_t)(((uint32_t)(x)) << RTC_SR_MOF_SHIFT)) & RTC_SR_MOF_MASK)
+#define RTC_SR_MOF RTC_SR_MOF_MASK
 #define RTC_SR_TCE_MASK                          (0x10U)
 #define RTC_SR_TCE_SHIFT                         (4U)
-#define RTC_SR_TCE(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
+#define RTC_SR_TCE_SET(x)                        (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
+#define RTC_SR_TCE RTC_SR_TCE_MASK
 
 /*! @name LR - RTC Lock Register */
 #define RTC_LR_TCL_MASK                          (0x8U)
 #define RTC_LR_TCL_SHIFT                         (3U)
-#define RTC_LR_TCL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
+#define RTC_LR_TCL_SET(x)                        (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
+#define RTC_LR_TCL RTC_LR_TCL_MASK
 #define RTC_LR_CRL_MASK                          (0x10U)
 #define RTC_LR_CRL_SHIFT                         (4U)
-#define RTC_LR_CRL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
+#define RTC_LR_CRL_SET(x)                        (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
+#define RTC_LR_CRL RTC_LR_CRL_MASK
 #define RTC_LR_SRL_MASK                          (0x20U)
 #define RTC_LR_SRL_SHIFT                         (5U)
-#define RTC_LR_SRL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
+#define RTC_LR_SRL_SET(x)                        (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
+#define RTC_LR_SRL RTC_LR_SRL_MASK
 #define RTC_LR_LRL_MASK                          (0x40U)
 #define RTC_LR_LRL_SHIFT                         (6U)
-#define RTC_LR_LRL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
+#define RTC_LR_LRL_SET(x)                        (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
+#define RTC_LR_LRL RTC_LR_LRL_MASK
 #define RTC_LR_TTSL_MASK                         (0x100U)
 #define RTC_LR_TTSL_SHIFT                        (8U)
-#define RTC_LR_TTSL(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_LR_TTSL_SHIFT)) & RTC_LR_TTSL_MASK)
+#define RTC_LR_TTSL_SET(x)                       (((uint32_t)(((uint32_t)(x)) << RTC_LR_TTSL_SHIFT)) & RTC_LR_TTSL_MASK)
+#define RTC_LR_TTSL RTC_LR_TTSL_MASK
 #define RTC_LR_MEL_MASK                          (0x200U)
 #define RTC_LR_MEL_SHIFT                         (9U)
-#define RTC_LR_MEL(x)                            (((uint32_t)(((uint32_t)(x)) << RTC_LR_MEL_SHIFT)) & RTC_LR_MEL_MASK)
+#define RTC_LR_MEL_SET(x)                        (((uint32_t)(((uint32_t)(x)) << RTC_LR_MEL_SHIFT)) & RTC_LR_MEL_MASK)
+#define RTC_LR_MEL RTC_LR_MEL_MASK
 #define RTC_LR_MCLL_MASK                         (0x400U)
 #define RTC_LR_MCLL_SHIFT                        (10U)
-#define RTC_LR_MCLL(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCLL_SHIFT)) & RTC_LR_MCLL_MASK)
+#define RTC_LR_MCLL_SET(x)                       (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCLL_SHIFT)) & RTC_LR_MCLL_MASK)
+#define RTC_LR_MCLL RTC_LR_MCLL_MASK
 #define RTC_LR_MCHL_MASK                         (0x800U)
 #define RTC_LR_MCHL_SHIFT                        (11U)
-#define RTC_LR_MCHL(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCHL_SHIFT)) & RTC_LR_MCHL_MASK)
+#define RTC_LR_MCHL_SET(x)                       (((uint32_t)(((uint32_t)(x)) << RTC_LR_MCHL_SHIFT)) & RTC_LR_MCHL_MASK)
+#define RTC_LR_MCHL RTC_LR_MCHL_MASK
 
 /*! @name IER - RTC Interrupt Enable Register */
 #define RTC_IER_TIIE_MASK                        (0x1U)
 #define RTC_IER_TIIE_SHIFT                       (0U)
-#define RTC_IER_TIIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
+#define RTC_IER_TIIE_SET(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
+#define RTC_IER_TIIE RTC_IER_TIIE_MASK
 #define RTC_IER_TOIE_MASK                        (0x2U)
 #define RTC_IER_TOIE_SHIFT                       (1U)
-#define RTC_IER_TOIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
+#define RTC_IER_TOIE_SET(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
+#define RTC_IER_TOIE RTC_IER_TOIE_MASK
 #define RTC_IER_TAIE_MASK                        (0x4U)
 #define RTC_IER_TAIE_SHIFT                       (2U)
-#define RTC_IER_TAIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
+#define RTC_IER_TAIE_SET(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
+#define RTC_IER_TAIE RTC_IER_TAIE_MASK
 #define RTC_IER_MOIE_MASK                        (0x8U)
 #define RTC_IER_MOIE_SHIFT                       (3U)
-#define RTC_IER_MOIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_MOIE_SHIFT)) & RTC_IER_MOIE_MASK)
+#define RTC_IER_MOIE_SET(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_IER_MOIE_SHIFT)) & RTC_IER_MOIE_MASK)
+#define RTC_IER_MOIE RTC_IER_MOIE_MASK
 #define RTC_IER_TSIE_MASK                        (0x10U)
 #define RTC_IER_TSIE_SHIFT                       (4U)
-#define RTC_IER_TSIE(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
+#define RTC_IER_TSIE_SET(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
+#define RTC_IER_TSIE RTC_IER_TSIE_MASK
 #define RTC_IER_WPON_MASK                        (0x80U)
 #define RTC_IER_WPON_SHIFT                       (7U)
-#define RTC_IER_WPON(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
+#define RTC_IER_WPON_SET(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
+#define RTC_IER_WPON RTC_IER_WPON_MASK
 
 /*! @name TTSR - RTC Tamper Time Seconds Register */
 #define RTC_TTSR_TTS_MASK                        (0xFFFFFFFFU)
 #define RTC_TTSR_TTS_SHIFT                       (0U)
-#define RTC_TTSR_TTS(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_TTSR_TTS_SHIFT)) & RTC_TTSR_TTS_MASK)
+#define RTC_TTSR_TTS_SET(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_TTSR_TTS_SHIFT)) & RTC_TTSR_TTS_MASK)
+#define RTC_TTSR_TTS RTC_TTSR_TTS_MASK
 
 /*! @name MER - RTC Monotonic Enable Register */
 #define RTC_MER_MCE_MASK                         (0x10U)
 #define RTC_MER_MCE_SHIFT                        (4U)
-#define RTC_MER_MCE(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_MER_MCE_SHIFT)) & RTC_MER_MCE_MASK)
+#define RTC_MER_MCE_SET(x)                       (((uint32_t)(((uint32_t)(x)) << RTC_MER_MCE_SHIFT)) & RTC_MER_MCE_MASK)
+#define RTC_MER_MCE RTC_MER_MCE_MASK
 
 /*! @name MCLR - RTC Monotonic Counter Low Register */
 #define RTC_MCLR_MCL_MASK                        (0xFFFFFFFFU)
 #define RTC_MCLR_MCL_SHIFT                       (0U)
-#define RTC_MCLR_MCL(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_MCLR_MCL_SHIFT)) & RTC_MCLR_MCL_MASK)
+#define RTC_MCLR_MCL_SET(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_MCLR_MCL_SHIFT)) & RTC_MCLR_MCL_MASK)
+#define RTC_MCLR_MCL RTC_MCLR_MCL_MASK
 
 /*! @name MCHR - RTC Monotonic Counter High Register */
 #define RTC_MCHR_MCH_MASK                        (0xFFFFFFFFU)
 #define RTC_MCHR_MCH_SHIFT                       (0U)
-#define RTC_MCHR_MCH(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_MCHR_MCH_SHIFT)) & RTC_MCHR_MCH_MASK)
+#define RTC_MCHR_MCH_SET(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_MCHR_MCH_SHIFT)) & RTC_MCHR_MCH_MASK)
+#define RTC_MCHR_MCH RTC_MCHR_MCH_MASK
 
 /*! @name WAR - RTC Write Access Register */
 #define RTC_WAR_TSRW_MASK                        (0x1U)
 #define RTC_WAR_TSRW_SHIFT                       (0U)
-#define RTC_WAR_TSRW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK)
+#define RTC_WAR_TSRW_SET(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK)
+#define RTC_WAR_TSRW RTC_WAR_TSRW_MASK
 #define RTC_WAR_TPRW_MASK                        (0x2U)
 #define RTC_WAR_TPRW_SHIFT                       (1U)
-#define RTC_WAR_TPRW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK)
+#define RTC_WAR_TPRW_SET(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK)
+#define RTC_WAR_TPRW RTC_WAR_TPRW_MASK
 #define RTC_WAR_TARW_MASK                        (0x4U)
 #define RTC_WAR_TARW_SHIFT                       (2U)
-#define RTC_WAR_TARW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK)
+#define RTC_WAR_TARW_SET(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK)
+#define RTC_WAR_TARW RTC_WAR_TARW_MASK
 #define RTC_WAR_TCRW_MASK                        (0x8U)
 #define RTC_WAR_TCRW_SHIFT                       (3U)
-#define RTC_WAR_TCRW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK)
+#define RTC_WAR_TCRW_SET(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK)
+#define RTC_WAR_TCRW RTC_WAR_TCRW_MASK
 #define RTC_WAR_CRW_MASK                         (0x10U)
 #define RTC_WAR_CRW_SHIFT                        (4U)
-#define RTC_WAR_CRW(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK)
+#define RTC_WAR_CRW_SET(x)                       (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK)
+#define RTC_WAR_CRW RTC_WAR_CRW_MASK
 #define RTC_WAR_SRW_MASK                         (0x20U)
 #define RTC_WAR_SRW_SHIFT                        (5U)
-#define RTC_WAR_SRW(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK)
+#define RTC_WAR_SRW_SET(x)                       (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK)
+#define RTC_WAR_SRW RTC_WAR_SRW_MASK
 #define RTC_WAR_LRW_MASK                         (0x40U)
 #define RTC_WAR_LRW_SHIFT                        (6U)
-#define RTC_WAR_LRW(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK)
+#define RTC_WAR_LRW_SET(x)                       (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK)
+#define RTC_WAR_LRW RTC_WAR_LRW_MASK
 #define RTC_WAR_IERW_MASK                        (0x80U)
 #define RTC_WAR_IERW_SHIFT                       (7U)
-#define RTC_WAR_IERW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK)
+#define RTC_WAR_IERW_SET(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK)
+#define RTC_WAR_IERW RTC_WAR_IERW_MASK
 #define RTC_WAR_TTSW_MASK                        (0x100U)
 #define RTC_WAR_TTSW_SHIFT                       (8U)
-#define RTC_WAR_TTSW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TTSW_SHIFT)) & RTC_WAR_TTSW_MASK)
+#define RTC_WAR_TTSW_SET(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TTSW_SHIFT)) & RTC_WAR_TTSW_MASK)
+#define RTC_WAR_TTSW RTC_WAR_TTSW_MASK
 #define RTC_WAR_MERW_MASK                        (0x200U)
 #define RTC_WAR_MERW_SHIFT                       (9U)
-#define RTC_WAR_MERW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MERW_SHIFT)) & RTC_WAR_MERW_MASK)
+#define RTC_WAR_MERW_SET(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MERW_SHIFT)) & RTC_WAR_MERW_MASK)
+#define RTC_WAR_MERW RTC_WAR_MERW_MASK
 #define RTC_WAR_MCLW_MASK                        (0x400U)
 #define RTC_WAR_MCLW_SHIFT                       (10U)
-#define RTC_WAR_MCLW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCLW_SHIFT)) & RTC_WAR_MCLW_MASK)
+#define RTC_WAR_MCLW_SET(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCLW_SHIFT)) & RTC_WAR_MCLW_MASK)
+#define RTC_WAR_MCLW RTC_WAR_MCLW_MASK
 #define RTC_WAR_MCHW_MASK                        (0x800U)
 #define RTC_WAR_MCHW_SHIFT                       (11U)
-#define RTC_WAR_MCHW(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCHW_SHIFT)) & RTC_WAR_MCHW_MASK)
+#define RTC_WAR_MCHW_SET(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_WAR_MCHW_SHIFT)) & RTC_WAR_MCHW_MASK)
+#define RTC_WAR_MCHW RTC_WAR_MCHW_MASK
 
 /*! @name RAR - RTC Read Access Register */
 #define RTC_RAR_TSRR_MASK                        (0x1U)
 #define RTC_RAR_TSRR_SHIFT                       (0U)
-#define RTC_RAR_TSRR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK)
+#define RTC_RAR_TSRR_SET(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK)
+#define RTC_RAR_TSRR RTC_RAR_TSRR_MASK
 #define RTC_RAR_TPRR_MASK                        (0x2U)
 #define RTC_RAR_TPRR_SHIFT                       (1U)
-#define RTC_RAR_TPRR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK)
+#define RTC_RAR_TPRR_SET(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK)
+#define RTC_RAR_TPRR RTC_RAR_TPRR_MASK
 #define RTC_RAR_TARR_MASK                        (0x4U)
 #define RTC_RAR_TARR_SHIFT                       (2U)
-#define RTC_RAR_TARR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK)
+#define RTC_RAR_TARR_SET(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK)
+#define RTC_RAR_TARR RTC_RAR_TARR_MASK
 #define RTC_RAR_TCRR_MASK                        (0x8U)
 #define RTC_RAR_TCRR_SHIFT                       (3U)
-#define RTC_RAR_TCRR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK)
+#define RTC_RAR_TCRR_SET(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK)
+#define RTC_RAR_TCRR RTC_RAR_TCRR_MASK
 #define RTC_RAR_CRR_MASK                         (0x10U)
 #define RTC_RAR_CRR_SHIFT                        (4U)
-#define RTC_RAR_CRR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK)
+#define RTC_RAR_CRR_SET(x)                       (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK)
+#define RTC_RAR_CRR RTC_RAR_CRR_MASK
 #define RTC_RAR_SRR_MASK                         (0x20U)
 #define RTC_RAR_SRR_SHIFT                        (5U)
-#define RTC_RAR_SRR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK)
+#define RTC_RAR_SRR_SET(x)                       (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK)
+#define RTC_RAR_SRR RTC_RAR_SRR_MASK
 #define RTC_RAR_LRR_MASK                         (0x40U)
 #define RTC_RAR_LRR_SHIFT                        (6U)
-#define RTC_RAR_LRR(x)                           (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK)
+#define RTC_RAR_LRR_SET(x)                       (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK)
+#define RTC_RAR_LRR RTC_RAR_LRR_MASK
 #define RTC_RAR_IERR_MASK                        (0x80U)
 #define RTC_RAR_IERR_SHIFT                       (7U)
-#define RTC_RAR_IERR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK)
+#define RTC_RAR_IERR_SET(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK)
+#define RTC_RAR_IERR RTC_RAR_IERR_MASK
 #define RTC_RAR_TTSR_MASK                        (0x100U)
 #define RTC_RAR_TTSR_SHIFT                       (8U)
-#define RTC_RAR_TTSR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TTSR_SHIFT)) & RTC_RAR_TTSR_MASK)
+#define RTC_RAR_TTSR_SET(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TTSR_SHIFT)) & RTC_RAR_TTSR_MASK)
+#define RTC_RAR_TTSR RTC_RAR_TTSR_MASK
 #define RTC_RAR_MERR_MASK                        (0x200U)
 #define RTC_RAR_MERR_SHIFT                       (9U)
-#define RTC_RAR_MERR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MERR_SHIFT)) & RTC_RAR_MERR_MASK)
+#define RTC_RAR_MERR_SET(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MERR_SHIFT)) & RTC_RAR_MERR_MASK)
+#define RTC_RAR_MERR RTC_RAR_MERR_MASK
 #define RTC_RAR_MCLR_MASK                        (0x400U)
 #define RTC_RAR_MCLR_SHIFT                       (10U)
-#define RTC_RAR_MCLR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCLR_SHIFT)) & RTC_RAR_MCLR_MASK)
+#define RTC_RAR_MCLR_SET(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCLR_SHIFT)) & RTC_RAR_MCLR_MASK)
+#define RTC_RAR_MCLR RTC_RAR_MCLR_MASK
 #define RTC_RAR_MCHR_MASK                        (0x800U)
 #define RTC_RAR_MCHR_SHIFT                       (11U)
-#define RTC_RAR_MCHR(x)                          (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCHR_SHIFT)) & RTC_RAR_MCHR_MASK)
+#define RTC_RAR_MCHR_SET(x)                      (((uint32_t)(((uint32_t)(x)) << RTC_RAR_MCHR_SHIFT)) & RTC_RAR_MCHR_MASK)
+#define RTC_RAR_MCHR RTC_RAR_MCHR_MASK
 
 
 /*!
@@ -11273,7 +13610,7 @@ typedef struct {
 /** Peripheral RTC base address */
 #define RTC_BASE                                 (0x4003D000u)
 /** Peripheral RTC base pointer */
-#define RTC                                      ((RTC_Type *)RTC_BASE)
+#define RTC                                      ((RTC_TypeDef *)RTC_BASE)
 /** Array initializer of RTC peripheral base addresses */
 #define RTC_BASE_ADDRS                           { RTC_BASE }
 /** Array initializer of RTC peripheral base pointers */
@@ -11322,7 +13659,7 @@ typedef struct {
   __IO uint32_t MMCBOOT;                           /**< MMC Boot register, offset: 0xC4 */
        uint8_t RESERVED_2[52];
   __I  uint32_t HOSTVER;                           /**< Host Controller Version, offset: 0xFC */
-} SDHC_Type;
+} SDHC_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- SDHC Register Masks
@@ -11336,69 +13673,83 @@ typedef struct {
 /*! @name DSADDR - DMA System Address register */
 #define SDHC_DSADDR_DSADDR_MASK                  (0xFFFFFFFCU)
 #define SDHC_DSADDR_DSADDR_SHIFT                 (2U)
-#define SDHC_DSADDR_DSADDR(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_DSADDR_DSADDR_SHIFT)) & SDHC_DSADDR_DSADDR_MASK)
+#define SDHC_DSADDR_DSADDR_SET(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_DSADDR_DSADDR_SHIFT)) & SDHC_DSADDR_DSADDR_MASK)
+#define SDHC_DSADDR_DSADDR SDHC_DSADDR_DSADDR_MASK
 
 /*! @name BLKATTR - Block Attributes register */
 #define SDHC_BLKATTR_BLKSIZE_MASK                (0x1FFFU)
 #define SDHC_BLKATTR_BLKSIZE_SHIFT               (0U)
-#define SDHC_BLKATTR_BLKSIZE(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKSIZE_SHIFT)) & SDHC_BLKATTR_BLKSIZE_MASK)
+#define SDHC_BLKATTR_BLKSIZE(x)              (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKSIZE_SHIFT)) & SDHC_BLKATTR_BLKSIZE_MASK)
 #define SDHC_BLKATTR_BLKCNT_MASK                 (0xFFFF0000U)
 #define SDHC_BLKATTR_BLKCNT_SHIFT                (16U)
-#define SDHC_BLKATTR_BLKCNT(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKCNT_SHIFT)) & SDHC_BLKATTR_BLKCNT_MASK)
+#define SDHC_BLKATTR_BLKCNT(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKCNT_SHIFT)) & SDHC_BLKATTR_BLKCNT_MASK)
 
 /*! @name CMDARG - Command Argument register */
 #define SDHC_CMDARG_CMDARG_MASK                  (0xFFFFFFFFU)
 #define SDHC_CMDARG_CMDARG_SHIFT                 (0U)
-#define SDHC_CMDARG_CMDARG(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_CMDARG_CMDARG_SHIFT)) & SDHC_CMDARG_CMDARG_MASK)
+#define SDHC_CMDARG_CMDARG_SET(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_CMDARG_CMDARG_SHIFT)) & SDHC_CMDARG_CMDARG_MASK)
+#define SDHC_CMDARG_CMDARG SDHC_CMDARG_CMDARG_MASK
 
 /*! @name XFERTYP - Transfer Type register */
 #define SDHC_XFERTYP_DMAEN_MASK                  (0x1U)
 #define SDHC_XFERTYP_DMAEN_SHIFT                 (0U)
-#define SDHC_XFERTYP_DMAEN(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DMAEN_SHIFT)) & SDHC_XFERTYP_DMAEN_MASK)
+#define SDHC_XFERTYP_DMAEN_SET(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DMAEN_SHIFT)) & SDHC_XFERTYP_DMAEN_MASK)
+#define SDHC_XFERTYP_DMAEN SDHC_XFERTYP_DMAEN_MASK
 #define SDHC_XFERTYP_BCEN_MASK                   (0x2U)
 #define SDHC_XFERTYP_BCEN_SHIFT                  (1U)
-#define SDHC_XFERTYP_BCEN(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_BCEN_SHIFT)) & SDHC_XFERTYP_BCEN_MASK)
+#define SDHC_XFERTYP_BCEN_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_BCEN_SHIFT)) & SDHC_XFERTYP_BCEN_MASK)
+#define SDHC_XFERTYP_BCEN SDHC_XFERTYP_BCEN_MASK
 #define SDHC_XFERTYP_AC12EN_MASK                 (0x4U)
 #define SDHC_XFERTYP_AC12EN_SHIFT                (2U)
-#define SDHC_XFERTYP_AC12EN(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_AC12EN_SHIFT)) & SDHC_XFERTYP_AC12EN_MASK)
+#define SDHC_XFERTYP_AC12EN_SET(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_AC12EN_SHIFT)) & SDHC_XFERTYP_AC12EN_MASK)
+#define SDHC_XFERTYP_AC12EN SDHC_XFERTYP_AC12EN_MASK
 #define SDHC_XFERTYP_DTDSEL_MASK                 (0x10U)
 #define SDHC_XFERTYP_DTDSEL_SHIFT                (4U)
-#define SDHC_XFERTYP_DTDSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DTDSEL_SHIFT)) & SDHC_XFERTYP_DTDSEL_MASK)
+#define SDHC_XFERTYP_DTDSEL_SET(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DTDSEL_SHIFT)) & SDHC_XFERTYP_DTDSEL_MASK)
+#define SDHC_XFERTYP_DTDSEL SDHC_XFERTYP_DTDSEL_MASK
 #define SDHC_XFERTYP_MSBSEL_MASK                 (0x20U)
 #define SDHC_XFERTYP_MSBSEL_SHIFT                (5U)
-#define SDHC_XFERTYP_MSBSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_MSBSEL_SHIFT)) & SDHC_XFERTYP_MSBSEL_MASK)
+#define SDHC_XFERTYP_MSBSEL_SET(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_MSBSEL_SHIFT)) & SDHC_XFERTYP_MSBSEL_MASK)
+#define SDHC_XFERTYP_MSBSEL SDHC_XFERTYP_MSBSEL_MASK
 #define SDHC_XFERTYP_RSPTYP_MASK                 (0x30000U)
 #define SDHC_XFERTYP_RSPTYP_SHIFT                (16U)
-#define SDHC_XFERTYP_RSPTYP(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_RSPTYP_SHIFT)) & SDHC_XFERTYP_RSPTYP_MASK)
+#define SDHC_XFERTYP_RSPTYP(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_RSPTYP_SHIFT)) & SDHC_XFERTYP_RSPTYP_MASK)
 #define SDHC_XFERTYP_CCCEN_MASK                  (0x80000U)
 #define SDHC_XFERTYP_CCCEN_SHIFT                 (19U)
-#define SDHC_XFERTYP_CCCEN(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CCCEN_SHIFT)) & SDHC_XFERTYP_CCCEN_MASK)
+#define SDHC_XFERTYP_CCCEN_SET(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CCCEN_SHIFT)) & SDHC_XFERTYP_CCCEN_MASK)
+#define SDHC_XFERTYP_CCCEN SDHC_XFERTYP_CCCEN_MASK
 #define SDHC_XFERTYP_CICEN_MASK                  (0x100000U)
 #define SDHC_XFERTYP_CICEN_SHIFT                 (20U)
-#define SDHC_XFERTYP_CICEN(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CICEN_SHIFT)) & SDHC_XFERTYP_CICEN_MASK)
+#define SDHC_XFERTYP_CICEN_SET(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CICEN_SHIFT)) & SDHC_XFERTYP_CICEN_MASK)
+#define SDHC_XFERTYP_CICEN SDHC_XFERTYP_CICEN_MASK
 #define SDHC_XFERTYP_DPSEL_MASK                  (0x200000U)
 #define SDHC_XFERTYP_DPSEL_SHIFT                 (21U)
-#define SDHC_XFERTYP_DPSEL(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DPSEL_SHIFT)) & SDHC_XFERTYP_DPSEL_MASK)
+#define SDHC_XFERTYP_DPSEL_SET(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DPSEL_SHIFT)) & SDHC_XFERTYP_DPSEL_MASK)
+#define SDHC_XFERTYP_DPSEL SDHC_XFERTYP_DPSEL_MASK
 #define SDHC_XFERTYP_CMDTYP_MASK                 (0xC00000U)
 #define SDHC_XFERTYP_CMDTYP_SHIFT                (22U)
-#define SDHC_XFERTYP_CMDTYP(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDTYP_SHIFT)) & SDHC_XFERTYP_CMDTYP_MASK)
+#define SDHC_XFERTYP_CMDTYP(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDTYP_SHIFT)) & SDHC_XFERTYP_CMDTYP_MASK)
 #define SDHC_XFERTYP_CMDINX_MASK                 (0x3F000000U)
 #define SDHC_XFERTYP_CMDINX_SHIFT                (24U)
-#define SDHC_XFERTYP_CMDINX(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDINX_SHIFT)) & SDHC_XFERTYP_CMDINX_MASK)
+#define SDHC_XFERTYP_CMDINX(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDINX_SHIFT)) & SDHC_XFERTYP_CMDINX_MASK)
 
 /*! @name CMDRSP - Command Response 0..Command Response 3 */
 #define SDHC_CMDRSP_CMDRSP0_MASK                 (0xFFFFFFFFU)
 #define SDHC_CMDRSP_CMDRSP0_SHIFT                (0U)
-#define SDHC_CMDRSP_CMDRSP0(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP0_SHIFT)) & SDHC_CMDRSP_CMDRSP0_MASK)
+#define SDHC_CMDRSP_CMDRSP0_SET(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP0_SHIFT)) & SDHC_CMDRSP_CMDRSP0_MASK)
+#define SDHC_CMDRSP_CMDRSP0 SDHC_CMDRSP_CMDRSP0_MASK
 #define SDHC_CMDRSP_CMDRSP1_MASK                 (0xFFFFFFFFU)
 #define SDHC_CMDRSP_CMDRSP1_SHIFT                (0U)
-#define SDHC_CMDRSP_CMDRSP1(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP1_SHIFT)) & SDHC_CMDRSP_CMDRSP1_MASK)
+#define SDHC_CMDRSP_CMDRSP1_SET(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP1_SHIFT)) & SDHC_CMDRSP_CMDRSP1_MASK)
+#define SDHC_CMDRSP_CMDRSP1 SDHC_CMDRSP_CMDRSP1_MASK
 #define SDHC_CMDRSP_CMDRSP2_MASK                 (0xFFFFFFFFU)
 #define SDHC_CMDRSP_CMDRSP2_SHIFT                (0U)
-#define SDHC_CMDRSP_CMDRSP2(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP2_SHIFT)) & SDHC_CMDRSP_CMDRSP2_MASK)
+#define SDHC_CMDRSP_CMDRSP2_SET(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP2_SHIFT)) & SDHC_CMDRSP_CMDRSP2_MASK)
+#define SDHC_CMDRSP_CMDRSP2 SDHC_CMDRSP_CMDRSP2_MASK
 #define SDHC_CMDRSP_CMDRSP3_MASK                 (0xFFFFFFFFU)
 #define SDHC_CMDRSP_CMDRSP3_SHIFT                (0U)
-#define SDHC_CMDRSP_CMDRSP3(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP3_SHIFT)) & SDHC_CMDRSP_CMDRSP3_MASK)
+#define SDHC_CMDRSP_CMDRSP3_SET(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP3_SHIFT)) & SDHC_CMDRSP_CMDRSP3_MASK)
+#define SDHC_CMDRSP_CMDRSP3 SDHC_CMDRSP_CMDRSP3_MASK
 
 /* The count of SDHC_CMDRSP */
 #define SDHC_CMDRSP_COUNT                        (4U)
@@ -11406,451 +13757,586 @@ typedef struct {
 /*! @name DATPORT - Buffer Data Port register */
 #define SDHC_DATPORT_DATCONT_MASK                (0xFFFFFFFFU)
 #define SDHC_DATPORT_DATCONT_SHIFT               (0U)
-#define SDHC_DATPORT_DATCONT(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_DATPORT_DATCONT_SHIFT)) & SDHC_DATPORT_DATCONT_MASK)
+#define SDHC_DATPORT_DATCONT_SET(x)              (((uint32_t)(((uint32_t)(x)) << SDHC_DATPORT_DATCONT_SHIFT)) & SDHC_DATPORT_DATCONT_MASK)
+#define SDHC_DATPORT_DATCONT SDHC_DATPORT_DATCONT_MASK
 
 /*! @name PRSSTAT - Present State register */
 #define SDHC_PRSSTAT_CIHB_MASK                   (0x1U)
 #define SDHC_PRSSTAT_CIHB_SHIFT                  (0U)
-#define SDHC_PRSSTAT_CIHB(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CIHB_SHIFT)) & SDHC_PRSSTAT_CIHB_MASK)
+#define SDHC_PRSSTAT_CIHB_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CIHB_SHIFT)) & SDHC_PRSSTAT_CIHB_MASK)
+#define SDHC_PRSSTAT_CIHB SDHC_PRSSTAT_CIHB_MASK
 #define SDHC_PRSSTAT_CDIHB_MASK                  (0x2U)
 #define SDHC_PRSSTAT_CDIHB_SHIFT                 (1U)
-#define SDHC_PRSSTAT_CDIHB(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CDIHB_SHIFT)) & SDHC_PRSSTAT_CDIHB_MASK)
+#define SDHC_PRSSTAT_CDIHB_SET(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CDIHB_SHIFT)) & SDHC_PRSSTAT_CDIHB_MASK)
+#define SDHC_PRSSTAT_CDIHB SDHC_PRSSTAT_CDIHB_MASK
 #define SDHC_PRSSTAT_DLA_MASK                    (0x4U)
 #define SDHC_PRSSTAT_DLA_SHIFT                   (2U)
-#define SDHC_PRSSTAT_DLA(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLA_SHIFT)) & SDHC_PRSSTAT_DLA_MASK)
+#define SDHC_PRSSTAT_DLA_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLA_SHIFT)) & SDHC_PRSSTAT_DLA_MASK)
+#define SDHC_PRSSTAT_DLA SDHC_PRSSTAT_DLA_MASK
 #define SDHC_PRSSTAT_SDSTB_MASK                  (0x8U)
 #define SDHC_PRSSTAT_SDSTB_SHIFT                 (3U)
-#define SDHC_PRSSTAT_SDSTB(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDSTB_SHIFT)) & SDHC_PRSSTAT_SDSTB_MASK)
+#define SDHC_PRSSTAT_SDSTB_SET(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDSTB_SHIFT)) & SDHC_PRSSTAT_SDSTB_MASK)
+#define SDHC_PRSSTAT_SDSTB SDHC_PRSSTAT_SDSTB_MASK
 #define SDHC_PRSSTAT_IPGOFF_MASK                 (0x10U)
 #define SDHC_PRSSTAT_IPGOFF_SHIFT                (4U)
-#define SDHC_PRSSTAT_IPGOFF(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_IPGOFF_SHIFT)) & SDHC_PRSSTAT_IPGOFF_MASK)
+#define SDHC_PRSSTAT_IPGOFF_SET(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_IPGOFF_SHIFT)) & SDHC_PRSSTAT_IPGOFF_MASK)
+#define SDHC_PRSSTAT_IPGOFF SDHC_PRSSTAT_IPGOFF_MASK
 #define SDHC_PRSSTAT_HCKOFF_MASK                 (0x20U)
 #define SDHC_PRSSTAT_HCKOFF_SHIFT                (5U)
-#define SDHC_PRSSTAT_HCKOFF(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_HCKOFF_SHIFT)) & SDHC_PRSSTAT_HCKOFF_MASK)
+#define SDHC_PRSSTAT_HCKOFF_SET(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_HCKOFF_SHIFT)) & SDHC_PRSSTAT_HCKOFF_MASK)
+#define SDHC_PRSSTAT_HCKOFF SDHC_PRSSTAT_HCKOFF_MASK
 #define SDHC_PRSSTAT_PEROFF_MASK                 (0x40U)
 #define SDHC_PRSSTAT_PEROFF_SHIFT                (6U)
-#define SDHC_PRSSTAT_PEROFF(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_PEROFF_SHIFT)) & SDHC_PRSSTAT_PEROFF_MASK)
+#define SDHC_PRSSTAT_PEROFF_SET(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_PEROFF_SHIFT)) & SDHC_PRSSTAT_PEROFF_MASK)
+#define SDHC_PRSSTAT_PEROFF SDHC_PRSSTAT_PEROFF_MASK
 #define SDHC_PRSSTAT_SDOFF_MASK                  (0x80U)
 #define SDHC_PRSSTAT_SDOFF_SHIFT                 (7U)
-#define SDHC_PRSSTAT_SDOFF(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDOFF_SHIFT)) & SDHC_PRSSTAT_SDOFF_MASK)
+#define SDHC_PRSSTAT_SDOFF_SET(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDOFF_SHIFT)) & SDHC_PRSSTAT_SDOFF_MASK)
+#define SDHC_PRSSTAT_SDOFF SDHC_PRSSTAT_SDOFF_MASK
 #define SDHC_PRSSTAT_WTA_MASK                    (0x100U)
 #define SDHC_PRSSTAT_WTA_SHIFT                   (8U)
-#define SDHC_PRSSTAT_WTA(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_WTA_SHIFT)) & SDHC_PRSSTAT_WTA_MASK)
+#define SDHC_PRSSTAT_WTA_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_WTA_SHIFT)) & SDHC_PRSSTAT_WTA_MASK)
+#define SDHC_PRSSTAT_WTA SDHC_PRSSTAT_WTA_MASK
 #define SDHC_PRSSTAT_RTA_MASK                    (0x200U)
 #define SDHC_PRSSTAT_RTA_SHIFT                   (9U)
-#define SDHC_PRSSTAT_RTA(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_RTA_SHIFT)) & SDHC_PRSSTAT_RTA_MASK)
+#define SDHC_PRSSTAT_RTA_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_RTA_SHIFT)) & SDHC_PRSSTAT_RTA_MASK)
+#define SDHC_PRSSTAT_RTA SDHC_PRSSTAT_RTA_MASK
 #define SDHC_PRSSTAT_BWEN_MASK                   (0x400U)
 #define SDHC_PRSSTAT_BWEN_SHIFT                  (10U)
-#define SDHC_PRSSTAT_BWEN(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BWEN_SHIFT)) & SDHC_PRSSTAT_BWEN_MASK)
+#define SDHC_PRSSTAT_BWEN_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BWEN_SHIFT)) & SDHC_PRSSTAT_BWEN_MASK)
+#define SDHC_PRSSTAT_BWEN SDHC_PRSSTAT_BWEN_MASK
 #define SDHC_PRSSTAT_BREN_MASK                   (0x800U)
 #define SDHC_PRSSTAT_BREN_SHIFT                  (11U)
-#define SDHC_PRSSTAT_BREN(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BREN_SHIFT)) & SDHC_PRSSTAT_BREN_MASK)
+#define SDHC_PRSSTAT_BREN_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BREN_SHIFT)) & SDHC_PRSSTAT_BREN_MASK)
+#define SDHC_PRSSTAT_BREN SDHC_PRSSTAT_BREN_MASK
 #define SDHC_PRSSTAT_CINS_MASK                   (0x10000U)
 #define SDHC_PRSSTAT_CINS_SHIFT                  (16U)
-#define SDHC_PRSSTAT_CINS(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CINS_SHIFT)) & SDHC_PRSSTAT_CINS_MASK)
+#define SDHC_PRSSTAT_CINS_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CINS_SHIFT)) & SDHC_PRSSTAT_CINS_MASK)
+#define SDHC_PRSSTAT_CINS SDHC_PRSSTAT_CINS_MASK
 #define SDHC_PRSSTAT_CLSL_MASK                   (0x800000U)
 #define SDHC_PRSSTAT_CLSL_SHIFT                  (23U)
-#define SDHC_PRSSTAT_CLSL(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CLSL_SHIFT)) & SDHC_PRSSTAT_CLSL_MASK)
+#define SDHC_PRSSTAT_CLSL_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CLSL_SHIFT)) & SDHC_PRSSTAT_CLSL_MASK)
+#define SDHC_PRSSTAT_CLSL SDHC_PRSSTAT_CLSL_MASK
 #define SDHC_PRSSTAT_DLSL_MASK                   (0xFF000000U)
 #define SDHC_PRSSTAT_DLSL_SHIFT                  (24U)
-#define SDHC_PRSSTAT_DLSL(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLSL_SHIFT)) & SDHC_PRSSTAT_DLSL_MASK)
+#define SDHC_PRSSTAT_DLSL_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLSL_SHIFT)) & SDHC_PRSSTAT_DLSL_MASK)
+#define SDHC_PRSSTAT_DLSL SDHC_PRSSTAT_DLSL_MASK
 
 /*! @name PROCTL - Protocol Control register */
 #define SDHC_PROCTL_LCTL_MASK                    (0x1U)
 #define SDHC_PROCTL_LCTL_SHIFT                   (0U)
-#define SDHC_PROCTL_LCTL(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_LCTL_SHIFT)) & SDHC_PROCTL_LCTL_MASK)
+#define SDHC_PROCTL_LCTL_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_LCTL_SHIFT)) & SDHC_PROCTL_LCTL_MASK)
+#define SDHC_PROCTL_LCTL SDHC_PROCTL_LCTL_MASK
 #define SDHC_PROCTL_DTW_MASK                     (0x6U)
 #define SDHC_PROCTL_DTW_SHIFT                    (1U)
-#define SDHC_PROCTL_DTW(x)                       (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DTW_SHIFT)) & SDHC_PROCTL_DTW_MASK)
+#define SDHC_PROCTL_DTW(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DTW_SHIFT)) & SDHC_PROCTL_DTW_MASK)
 #define SDHC_PROCTL_D3CD_MASK                    (0x8U)
 #define SDHC_PROCTL_D3CD_SHIFT                   (3U)
-#define SDHC_PROCTL_D3CD(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_D3CD_SHIFT)) & SDHC_PROCTL_D3CD_MASK)
+#define SDHC_PROCTL_D3CD_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_D3CD_SHIFT)) & SDHC_PROCTL_D3CD_MASK)
+#define SDHC_PROCTL_D3CD SDHC_PROCTL_D3CD_MASK
 #define SDHC_PROCTL_EMODE_MASK                   (0x30U)
 #define SDHC_PROCTL_EMODE_SHIFT                  (4U)
-#define SDHC_PROCTL_EMODE(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_EMODE_SHIFT)) & SDHC_PROCTL_EMODE_MASK)
+#define SDHC_PROCTL_EMODE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_EMODE_SHIFT)) & SDHC_PROCTL_EMODE_MASK)
+#define SDHC_PROCTL_EMODE SDHC_PROCTL_EMODE_MASK
 #define SDHC_PROCTL_CDTL_MASK                    (0x40U)
 #define SDHC_PROCTL_CDTL_SHIFT                   (6U)
-#define SDHC_PROCTL_CDTL(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDTL_SHIFT)) & SDHC_PROCTL_CDTL_MASK)
+#define SDHC_PROCTL_CDTL_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDTL_SHIFT)) & SDHC_PROCTL_CDTL_MASK)
+#define SDHC_PROCTL_CDTL SDHC_PROCTL_CDTL_MASK
 #define SDHC_PROCTL_CDSS_MASK                    (0x80U)
 #define SDHC_PROCTL_CDSS_SHIFT                   (7U)
-#define SDHC_PROCTL_CDSS(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDSS_SHIFT)) & SDHC_PROCTL_CDSS_MASK)
+#define SDHC_PROCTL_CDSS_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDSS_SHIFT)) & SDHC_PROCTL_CDSS_MASK)
+#define SDHC_PROCTL_CDSS SDHC_PROCTL_CDSS_MASK
 #define SDHC_PROCTL_DMAS_MASK                    (0x300U)
 #define SDHC_PROCTL_DMAS_SHIFT                   (8U)
-#define SDHC_PROCTL_DMAS(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DMAS_SHIFT)) & SDHC_PROCTL_DMAS_MASK)
+#define SDHC_PROCTL_DMAS_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DMAS_SHIFT)) & SDHC_PROCTL_DMAS_MASK)
+#define SDHC_PROCTL_DMAS SDHC_PROCTL_DMAS_MASK
 #define SDHC_PROCTL_SABGREQ_MASK                 (0x10000U)
 #define SDHC_PROCTL_SABGREQ_SHIFT                (16U)
-#define SDHC_PROCTL_SABGREQ(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_SABGREQ_SHIFT)) & SDHC_PROCTL_SABGREQ_MASK)
+#define SDHC_PROCTL_SABGREQ_SET(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_SABGREQ_SHIFT)) & SDHC_PROCTL_SABGREQ_MASK)
+#define SDHC_PROCTL_SABGREQ SDHC_PROCTL_SABGREQ_MASK
 #define SDHC_PROCTL_CREQ_MASK                    (0x20000U)
 #define SDHC_PROCTL_CREQ_SHIFT                   (17U)
-#define SDHC_PROCTL_CREQ(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CREQ_SHIFT)) & SDHC_PROCTL_CREQ_MASK)
+#define SDHC_PROCTL_CREQ_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CREQ_SHIFT)) & SDHC_PROCTL_CREQ_MASK)
+#define SDHC_PROCTL_CREQ SDHC_PROCTL_CREQ_MASK
 #define SDHC_PROCTL_RWCTL_MASK                   (0x40000U)
 #define SDHC_PROCTL_RWCTL_SHIFT                  (18U)
-#define SDHC_PROCTL_RWCTL(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_RWCTL_SHIFT)) & SDHC_PROCTL_RWCTL_MASK)
+#define SDHC_PROCTL_RWCTL_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_RWCTL_SHIFT)) & SDHC_PROCTL_RWCTL_MASK)
+#define SDHC_PROCTL_RWCTL SDHC_PROCTL_RWCTL_MASK
 #define SDHC_PROCTL_IABG_MASK                    (0x80000U)
 #define SDHC_PROCTL_IABG_SHIFT                   (19U)
-#define SDHC_PROCTL_IABG(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_IABG_SHIFT)) & SDHC_PROCTL_IABG_MASK)
+#define SDHC_PROCTL_IABG_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_IABG_SHIFT)) & SDHC_PROCTL_IABG_MASK)
+#define SDHC_PROCTL_IABG SDHC_PROCTL_IABG_MASK
 #define SDHC_PROCTL_WECINT_MASK                  (0x1000000U)
 #define SDHC_PROCTL_WECINT_SHIFT                 (24U)
-#define SDHC_PROCTL_WECINT(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINT_SHIFT)) & SDHC_PROCTL_WECINT_MASK)
+#define SDHC_PROCTL_WECINT_SET(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINT_SHIFT)) & SDHC_PROCTL_WECINT_MASK)
+#define SDHC_PROCTL_WECINT SDHC_PROCTL_WECINT_MASK
 #define SDHC_PROCTL_WECINS_MASK                  (0x2000000U)
 #define SDHC_PROCTL_WECINS_SHIFT                 (25U)
-#define SDHC_PROCTL_WECINS(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINS_SHIFT)) & SDHC_PROCTL_WECINS_MASK)
+#define SDHC_PROCTL_WECINS_SET(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINS_SHIFT)) & SDHC_PROCTL_WECINS_MASK)
+#define SDHC_PROCTL_WECINS SDHC_PROCTL_WECINS_MASK
 #define SDHC_PROCTL_WECRM_MASK                   (0x4000000U)
 #define SDHC_PROCTL_WECRM_SHIFT                  (26U)
-#define SDHC_PROCTL_WECRM(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECRM_SHIFT)) & SDHC_PROCTL_WECRM_MASK)
+#define SDHC_PROCTL_WECRM_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECRM_SHIFT)) & SDHC_PROCTL_WECRM_MASK)
+#define SDHC_PROCTL_WECRM SDHC_PROCTL_WECRM_MASK
 
 /*! @name SYSCTL - System Control register */
 #define SDHC_SYSCTL_IPGEN_MASK                   (0x1U)
 #define SDHC_SYSCTL_IPGEN_SHIFT                  (0U)
-#define SDHC_SYSCTL_IPGEN(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_IPGEN_SHIFT)) & SDHC_SYSCTL_IPGEN_MASK)
+#define SDHC_SYSCTL_IPGEN_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_IPGEN_SHIFT)) & SDHC_SYSCTL_IPGEN_MASK)
+#define SDHC_SYSCTL_IPGEN SDHC_SYSCTL_IPGEN_MASK
 #define SDHC_SYSCTL_HCKEN_MASK                   (0x2U)
 #define SDHC_SYSCTL_HCKEN_SHIFT                  (1U)
-#define SDHC_SYSCTL_HCKEN(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_HCKEN_SHIFT)) & SDHC_SYSCTL_HCKEN_MASK)
+#define SDHC_SYSCTL_HCKEN_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_HCKEN_SHIFT)) & SDHC_SYSCTL_HCKEN_MASK)
+#define SDHC_SYSCTL_HCKEN SDHC_SYSCTL_HCKEN_MASK
 #define SDHC_SYSCTL_PEREN_MASK                   (0x4U)
 #define SDHC_SYSCTL_PEREN_SHIFT                  (2U)
-#define SDHC_SYSCTL_PEREN(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_PEREN_SHIFT)) & SDHC_SYSCTL_PEREN_MASK)
+#define SDHC_SYSCTL_PEREN_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_PEREN_SHIFT)) & SDHC_SYSCTL_PEREN_MASK)
+#define SDHC_SYSCTL_PEREN SDHC_SYSCTL_PEREN_MASK
 #define SDHC_SYSCTL_SDCLKEN_MASK                 (0x8U)
 #define SDHC_SYSCTL_SDCLKEN_SHIFT                (3U)
-#define SDHC_SYSCTL_SDCLKEN(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKEN_SHIFT)) & SDHC_SYSCTL_SDCLKEN_MASK)
+#define SDHC_SYSCTL_SDCLKEN_SET(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKEN_SHIFT)) & SDHC_SYSCTL_SDCLKEN_MASK)
+#define SDHC_SYSCTL_SDCLKEN SDHC_SYSCTL_SDCLKEN_MASK
 #define SDHC_SYSCTL_DVS_MASK                     (0xF0U)
 #define SDHC_SYSCTL_DVS_SHIFT                    (4U)
-#define SDHC_SYSCTL_DVS(x)                       (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DVS_SHIFT)) & SDHC_SYSCTL_DVS_MASK)
+#define SDHC_SYSCTL_DVS(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DVS_SHIFT)) & SDHC_SYSCTL_DVS_MASK)
 #define SDHC_SYSCTL_SDCLKFS_MASK                 (0xFF00U)
 #define SDHC_SYSCTL_SDCLKFS_SHIFT                (8U)
-#define SDHC_SYSCTL_SDCLKFS(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKFS_SHIFT)) & SDHC_SYSCTL_SDCLKFS_MASK)
+#define SDHC_SYSCTL_SDCLKFS(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKFS_SHIFT)) & SDHC_SYSCTL_SDCLKFS_MASK)
 #define SDHC_SYSCTL_DTOCV_MASK                   (0xF0000U)
 #define SDHC_SYSCTL_DTOCV_SHIFT                  (16U)
-#define SDHC_SYSCTL_DTOCV(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DTOCV_SHIFT)) & SDHC_SYSCTL_DTOCV_MASK)
+#define SDHC_SYSCTL_DTOCV(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DTOCV_SHIFT)) & SDHC_SYSCTL_DTOCV_MASK)
 #define SDHC_SYSCTL_RSTA_MASK                    (0x1000000U)
 #define SDHC_SYSCTL_RSTA_SHIFT                   (24U)
-#define SDHC_SYSCTL_RSTA(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTA_SHIFT)) & SDHC_SYSCTL_RSTA_MASK)
+#define SDHC_SYSCTL_RSTA_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTA_SHIFT)) & SDHC_SYSCTL_RSTA_MASK)
+#define SDHC_SYSCTL_RSTA SDHC_SYSCTL_RSTA_MASK
 #define SDHC_SYSCTL_RSTC_MASK                    (0x2000000U)
 #define SDHC_SYSCTL_RSTC_SHIFT                   (25U)
-#define SDHC_SYSCTL_RSTC(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTC_SHIFT)) & SDHC_SYSCTL_RSTC_MASK)
+#define SDHC_SYSCTL_RSTC_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTC_SHIFT)) & SDHC_SYSCTL_RSTC_MASK)
+#define SDHC_SYSCTL_RSTC SDHC_SYSCTL_RSTC_MASK
 #define SDHC_SYSCTL_RSTD_MASK                    (0x4000000U)
 #define SDHC_SYSCTL_RSTD_SHIFT                   (26U)
-#define SDHC_SYSCTL_RSTD(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTD_SHIFT)) & SDHC_SYSCTL_RSTD_MASK)
+#define SDHC_SYSCTL_RSTD_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTD_SHIFT)) & SDHC_SYSCTL_RSTD_MASK)
+#define SDHC_SYSCTL_RSTD SDHC_SYSCTL_RSTD_MASK
 #define SDHC_SYSCTL_INITA_MASK                   (0x8000000U)
 #define SDHC_SYSCTL_INITA_SHIFT                  (27U)
-#define SDHC_SYSCTL_INITA(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_INITA_SHIFT)) & SDHC_SYSCTL_INITA_MASK)
+#define SDHC_SYSCTL_INITA_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_INITA_SHIFT)) & SDHC_SYSCTL_INITA_MASK)
+#define SDHC_SYSCTL_INITA SDHC_SYSCTL_INITA_MASK
 
 /*! @name IRQSTAT - Interrupt Status register */
 #define SDHC_IRQSTAT_CC_MASK                     (0x1U)
 #define SDHC_IRQSTAT_CC_SHIFT                    (0U)
-#define SDHC_IRQSTAT_CC(x)                       (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CC_SHIFT)) & SDHC_IRQSTAT_CC_MASK)
+#define SDHC_IRQSTAT_CC_SET(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CC_SHIFT)) & SDHC_IRQSTAT_CC_MASK)
+#define SDHC_IRQSTAT_CC SDHC_IRQSTAT_CC_MASK
 #define SDHC_IRQSTAT_TC_MASK                     (0x2U)
 #define SDHC_IRQSTAT_TC_SHIFT                    (1U)
-#define SDHC_IRQSTAT_TC(x)                       (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_TC_SHIFT)) & SDHC_IRQSTAT_TC_MASK)
+#define SDHC_IRQSTAT_TC_SET(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_TC_SHIFT)) & SDHC_IRQSTAT_TC_MASK)
+#define SDHC_IRQSTAT_TC SDHC_IRQSTAT_TC_MASK
 #define SDHC_IRQSTAT_BGE_MASK                    (0x4U)
 #define SDHC_IRQSTAT_BGE_SHIFT                   (2U)
-#define SDHC_IRQSTAT_BGE(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BGE_SHIFT)) & SDHC_IRQSTAT_BGE_MASK)
+#define SDHC_IRQSTAT_BGE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BGE_SHIFT)) & SDHC_IRQSTAT_BGE_MASK)
+#define SDHC_IRQSTAT_BGE SDHC_IRQSTAT_BGE_MASK
 #define SDHC_IRQSTAT_DINT_MASK                   (0x8U)
 #define SDHC_IRQSTAT_DINT_SHIFT                  (3U)
-#define SDHC_IRQSTAT_DINT(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DINT_SHIFT)) & SDHC_IRQSTAT_DINT_MASK)
+#define SDHC_IRQSTAT_DINT_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DINT_SHIFT)) & SDHC_IRQSTAT_DINT_MASK)
+#define SDHC_IRQSTAT_DINT SDHC_IRQSTAT_DINT_MASK
 #define SDHC_IRQSTAT_BWR_MASK                    (0x10U)
 #define SDHC_IRQSTAT_BWR_SHIFT                   (4U)
-#define SDHC_IRQSTAT_BWR(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BWR_SHIFT)) & SDHC_IRQSTAT_BWR_MASK)
+#define SDHC_IRQSTAT_BWR_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BWR_SHIFT)) & SDHC_IRQSTAT_BWR_MASK)
+#define SDHC_IRQSTAT_BWR SDHC_IRQSTAT_BWR_MASK
 #define SDHC_IRQSTAT_BRR_MASK                    (0x20U)
 #define SDHC_IRQSTAT_BRR_SHIFT                   (5U)
-#define SDHC_IRQSTAT_BRR(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BRR_SHIFT)) & SDHC_IRQSTAT_BRR_MASK)
+#define SDHC_IRQSTAT_BRR_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BRR_SHIFT)) & SDHC_IRQSTAT_BRR_MASK)
+#define SDHC_IRQSTAT_BRR SDHC_IRQSTAT_BRR_MASK
 #define SDHC_IRQSTAT_CINS_MASK                   (0x40U)
 #define SDHC_IRQSTAT_CINS_SHIFT                  (6U)
-#define SDHC_IRQSTAT_CINS(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINS_SHIFT)) & SDHC_IRQSTAT_CINS_MASK)
+#define SDHC_IRQSTAT_CINS_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINS_SHIFT)) & SDHC_IRQSTAT_CINS_MASK)
+#define SDHC_IRQSTAT_CINS SDHC_IRQSTAT_CINS_MASK
 #define SDHC_IRQSTAT_CRM_MASK                    (0x80U)
 #define SDHC_IRQSTAT_CRM_SHIFT                   (7U)
-#define SDHC_IRQSTAT_CRM(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CRM_SHIFT)) & SDHC_IRQSTAT_CRM_MASK)
+#define SDHC_IRQSTAT_CRM_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CRM_SHIFT)) & SDHC_IRQSTAT_CRM_MASK)
+#define SDHC_IRQSTAT_CRM SDHC_IRQSTAT_CRM_MASK
 #define SDHC_IRQSTAT_CINT_MASK                   (0x100U)
 #define SDHC_IRQSTAT_CINT_SHIFT                  (8U)
-#define SDHC_IRQSTAT_CINT(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINT_SHIFT)) & SDHC_IRQSTAT_CINT_MASK)
+#define SDHC_IRQSTAT_CINT_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINT_SHIFT)) & SDHC_IRQSTAT_CINT_MASK)
+#define SDHC_IRQSTAT_CINT SDHC_IRQSTAT_CINT_MASK
 #define SDHC_IRQSTAT_CTOE_MASK                   (0x10000U)
 #define SDHC_IRQSTAT_CTOE_SHIFT                  (16U)
-#define SDHC_IRQSTAT_CTOE(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CTOE_SHIFT)) & SDHC_IRQSTAT_CTOE_MASK)
+#define SDHC_IRQSTAT_CTOE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CTOE_SHIFT)) & SDHC_IRQSTAT_CTOE_MASK)
+#define SDHC_IRQSTAT_CTOE SDHC_IRQSTAT_CTOE_MASK
 #define SDHC_IRQSTAT_CCE_MASK                    (0x20000U)
 #define SDHC_IRQSTAT_CCE_SHIFT                   (17U)
-#define SDHC_IRQSTAT_CCE(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CCE_SHIFT)) & SDHC_IRQSTAT_CCE_MASK)
+#define SDHC_IRQSTAT_CCE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CCE_SHIFT)) & SDHC_IRQSTAT_CCE_MASK)
+#define SDHC_IRQSTAT_CCE SDHC_IRQSTAT_CCE_MASK
 #define SDHC_IRQSTAT_CEBE_MASK                   (0x40000U)
 #define SDHC_IRQSTAT_CEBE_SHIFT                  (18U)
-#define SDHC_IRQSTAT_CEBE(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CEBE_SHIFT)) & SDHC_IRQSTAT_CEBE_MASK)
+#define SDHC_IRQSTAT_CEBE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CEBE_SHIFT)) & SDHC_IRQSTAT_CEBE_MASK)
+#define SDHC_IRQSTAT_CEBE SDHC_IRQSTAT_CEBE_MASK
 #define SDHC_IRQSTAT_CIE_MASK                    (0x80000U)
 #define SDHC_IRQSTAT_CIE_SHIFT                   (19U)
-#define SDHC_IRQSTAT_CIE(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CIE_SHIFT)) & SDHC_IRQSTAT_CIE_MASK)
+#define SDHC_IRQSTAT_CIE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CIE_SHIFT)) & SDHC_IRQSTAT_CIE_MASK)
+#define SDHC_IRQSTAT_CIE SDHC_IRQSTAT_CIE_MASK
 #define SDHC_IRQSTAT_DTOE_MASK                   (0x100000U)
 #define SDHC_IRQSTAT_DTOE_SHIFT                  (20U)
-#define SDHC_IRQSTAT_DTOE(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DTOE_SHIFT)) & SDHC_IRQSTAT_DTOE_MASK)
+#define SDHC_IRQSTAT_DTOE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DTOE_SHIFT)) & SDHC_IRQSTAT_DTOE_MASK)
+#define SDHC_IRQSTAT_DTOE SDHC_IRQSTAT_DTOE_MASK
 #define SDHC_IRQSTAT_DCE_MASK                    (0x200000U)
 #define SDHC_IRQSTAT_DCE_SHIFT                   (21U)
-#define SDHC_IRQSTAT_DCE(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DCE_SHIFT)) & SDHC_IRQSTAT_DCE_MASK)
+#define SDHC_IRQSTAT_DCE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DCE_SHIFT)) & SDHC_IRQSTAT_DCE_MASK)
+#define SDHC_IRQSTAT_DCE SDHC_IRQSTAT_DCE_MASK
 #define SDHC_IRQSTAT_DEBE_MASK                   (0x400000U)
 #define SDHC_IRQSTAT_DEBE_SHIFT                  (22U)
-#define SDHC_IRQSTAT_DEBE(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DEBE_SHIFT)) & SDHC_IRQSTAT_DEBE_MASK)
+#define SDHC_IRQSTAT_DEBE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DEBE_SHIFT)) & SDHC_IRQSTAT_DEBE_MASK)
+#define SDHC_IRQSTAT_DEBE SDHC_IRQSTAT_DEBE_MASK
 #define SDHC_IRQSTAT_AC12E_MASK                  (0x1000000U)
 #define SDHC_IRQSTAT_AC12E_SHIFT                 (24U)
-#define SDHC_IRQSTAT_AC12E(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_AC12E_SHIFT)) & SDHC_IRQSTAT_AC12E_MASK)
+#define SDHC_IRQSTAT_AC12E_SET(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_AC12E_SHIFT)) & SDHC_IRQSTAT_AC12E_MASK)
+#define SDHC_IRQSTAT_AC12E SDHC_IRQSTAT_AC12E_MASK
 #define SDHC_IRQSTAT_DMAE_MASK                   (0x10000000U)
 #define SDHC_IRQSTAT_DMAE_SHIFT                  (28U)
-#define SDHC_IRQSTAT_DMAE(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DMAE_SHIFT)) & SDHC_IRQSTAT_DMAE_MASK)
+#define SDHC_IRQSTAT_DMAE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DMAE_SHIFT)) & SDHC_IRQSTAT_DMAE_MASK)
+#define SDHC_IRQSTAT_DMAE SDHC_IRQSTAT_DMAE_MASK
 
 /*! @name IRQSTATEN - Interrupt Status Enable register */
 #define SDHC_IRQSTATEN_CCSEN_MASK                (0x1U)
 #define SDHC_IRQSTATEN_CCSEN_SHIFT               (0U)
-#define SDHC_IRQSTATEN_CCSEN(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCSEN_SHIFT)) & SDHC_IRQSTATEN_CCSEN_MASK)
+#define SDHC_IRQSTATEN_CCSEN_SET(x)              (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCSEN_SHIFT)) & SDHC_IRQSTATEN_CCSEN_MASK)
+#define SDHC_IRQSTATEN_CCSEN SDHC_IRQSTATEN_CCSEN_MASK
 #define SDHC_IRQSTATEN_TCSEN_MASK                (0x2U)
 #define SDHC_IRQSTATEN_TCSEN_SHIFT               (1U)
-#define SDHC_IRQSTATEN_TCSEN(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_TCSEN_SHIFT)) & SDHC_IRQSTATEN_TCSEN_MASK)
+#define SDHC_IRQSTATEN_TCSEN_SET(x)              (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_TCSEN_SHIFT)) & SDHC_IRQSTATEN_TCSEN_MASK)
+#define SDHC_IRQSTATEN_TCSEN SDHC_IRQSTATEN_TCSEN_MASK
 #define SDHC_IRQSTATEN_BGESEN_MASK               (0x4U)
 #define SDHC_IRQSTATEN_BGESEN_SHIFT              (2U)
-#define SDHC_IRQSTATEN_BGESEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BGESEN_SHIFT)) & SDHC_IRQSTATEN_BGESEN_MASK)
+#define SDHC_IRQSTATEN_BGESEN_SET(x)             (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BGESEN_SHIFT)) & SDHC_IRQSTATEN_BGESEN_MASK)
+#define SDHC_IRQSTATEN_BGESEN SDHC_IRQSTATEN_BGESEN_MASK
 #define SDHC_IRQSTATEN_DINTSEN_MASK              (0x8U)
 #define SDHC_IRQSTATEN_DINTSEN_SHIFT             (3U)
-#define SDHC_IRQSTATEN_DINTSEN(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DINTSEN_SHIFT)) & SDHC_IRQSTATEN_DINTSEN_MASK)
+#define SDHC_IRQSTATEN_DINTSEN_SET(x)            (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DINTSEN_SHIFT)) & SDHC_IRQSTATEN_DINTSEN_MASK)
+#define SDHC_IRQSTATEN_DINTSEN SDHC_IRQSTATEN_DINTSEN_MASK
 #define SDHC_IRQSTATEN_BWRSEN_MASK               (0x10U)
 #define SDHC_IRQSTATEN_BWRSEN_SHIFT              (4U)
-#define SDHC_IRQSTATEN_BWRSEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BWRSEN_SHIFT)) & SDHC_IRQSTATEN_BWRSEN_MASK)
+#define SDHC_IRQSTATEN_BWRSEN_SET(x)             (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BWRSEN_SHIFT)) & SDHC_IRQSTATEN_BWRSEN_MASK)
+#define SDHC_IRQSTATEN_BWRSEN SDHC_IRQSTATEN_BWRSEN_MASK
 #define SDHC_IRQSTATEN_BRRSEN_MASK               (0x20U)
 #define SDHC_IRQSTATEN_BRRSEN_SHIFT              (5U)
-#define SDHC_IRQSTATEN_BRRSEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BRRSEN_SHIFT)) & SDHC_IRQSTATEN_BRRSEN_MASK)
+#define SDHC_IRQSTATEN_BRRSEN_SET(x)             (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BRRSEN_SHIFT)) & SDHC_IRQSTATEN_BRRSEN_MASK)
+#define SDHC_IRQSTATEN_BRRSEN SDHC_IRQSTATEN_BRRSEN_MASK
 #define SDHC_IRQSTATEN_CINSEN_MASK               (0x40U)
 #define SDHC_IRQSTATEN_CINSEN_SHIFT              (6U)
-#define SDHC_IRQSTATEN_CINSEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINSEN_SHIFT)) & SDHC_IRQSTATEN_CINSEN_MASK)
+#define SDHC_IRQSTATEN_CINSEN_SET(x)             (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINSEN_SHIFT)) & SDHC_IRQSTATEN_CINSEN_MASK)
+#define SDHC_IRQSTATEN_CINSEN SDHC_IRQSTATEN_CINSEN_MASK
 #define SDHC_IRQSTATEN_CRMSEN_MASK               (0x80U)
 #define SDHC_IRQSTATEN_CRMSEN_SHIFT              (7U)
-#define SDHC_IRQSTATEN_CRMSEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CRMSEN_SHIFT)) & SDHC_IRQSTATEN_CRMSEN_MASK)
+#define SDHC_IRQSTATEN_CRMSEN_SET(x)             (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CRMSEN_SHIFT)) & SDHC_IRQSTATEN_CRMSEN_MASK)
+#define SDHC_IRQSTATEN_CRMSEN SDHC_IRQSTATEN_CRMSEN_MASK
 #define SDHC_IRQSTATEN_CINTSEN_MASK              (0x100U)
 #define SDHC_IRQSTATEN_CINTSEN_SHIFT             (8U)
-#define SDHC_IRQSTATEN_CINTSEN(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINTSEN_SHIFT)) & SDHC_IRQSTATEN_CINTSEN_MASK)
+#define SDHC_IRQSTATEN_CINTSEN_SET(x)            (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINTSEN_SHIFT)) & SDHC_IRQSTATEN_CINTSEN_MASK)
+#define SDHC_IRQSTATEN_CINTSEN SDHC_IRQSTATEN_CINTSEN_MASK
 #define SDHC_IRQSTATEN_CTOESEN_MASK              (0x10000U)
 #define SDHC_IRQSTATEN_CTOESEN_SHIFT             (16U)
-#define SDHC_IRQSTATEN_CTOESEN(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CTOESEN_SHIFT)) & SDHC_IRQSTATEN_CTOESEN_MASK)
+#define SDHC_IRQSTATEN_CTOESEN_SET(x)            (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CTOESEN_SHIFT)) & SDHC_IRQSTATEN_CTOESEN_MASK)
+#define SDHC_IRQSTATEN_CTOESEN SDHC_IRQSTATEN_CTOESEN_MASK
 #define SDHC_IRQSTATEN_CCESEN_MASK               (0x20000U)
 #define SDHC_IRQSTATEN_CCESEN_SHIFT              (17U)
-#define SDHC_IRQSTATEN_CCESEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCESEN_SHIFT)) & SDHC_IRQSTATEN_CCESEN_MASK)
+#define SDHC_IRQSTATEN_CCESEN_SET(x)             (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCESEN_SHIFT)) & SDHC_IRQSTATEN_CCESEN_MASK)
+#define SDHC_IRQSTATEN_CCESEN SDHC_IRQSTATEN_CCESEN_MASK
 #define SDHC_IRQSTATEN_CEBESEN_MASK              (0x40000U)
 #define SDHC_IRQSTATEN_CEBESEN_SHIFT             (18U)
-#define SDHC_IRQSTATEN_CEBESEN(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CEBESEN_SHIFT)) & SDHC_IRQSTATEN_CEBESEN_MASK)
+#define SDHC_IRQSTATEN_CEBESEN_SET(x)            (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CEBESEN_SHIFT)) & SDHC_IRQSTATEN_CEBESEN_MASK)
+#define SDHC_IRQSTATEN_CEBESEN SDHC_IRQSTATEN_CEBESEN_MASK
 #define SDHC_IRQSTATEN_CIESEN_MASK               (0x80000U)
 #define SDHC_IRQSTATEN_CIESEN_SHIFT              (19U)
-#define SDHC_IRQSTATEN_CIESEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CIESEN_SHIFT)) & SDHC_IRQSTATEN_CIESEN_MASK)
+#define SDHC_IRQSTATEN_CIESEN_SET(x)             (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CIESEN_SHIFT)) & SDHC_IRQSTATEN_CIESEN_MASK)
+#define SDHC_IRQSTATEN_CIESEN SDHC_IRQSTATEN_CIESEN_MASK
 #define SDHC_IRQSTATEN_DTOESEN_MASK              (0x100000U)
 #define SDHC_IRQSTATEN_DTOESEN_SHIFT             (20U)
-#define SDHC_IRQSTATEN_DTOESEN(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DTOESEN_SHIFT)) & SDHC_IRQSTATEN_DTOESEN_MASK)
+#define SDHC_IRQSTATEN_DTOESEN_SET(x)            (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DTOESEN_SHIFT)) & SDHC_IRQSTATEN_DTOESEN_MASK)
+#define SDHC_IRQSTATEN_DTOESEN SDHC_IRQSTATEN_DTOESEN_MASK
 #define SDHC_IRQSTATEN_DCESEN_MASK               (0x200000U)
 #define SDHC_IRQSTATEN_DCESEN_SHIFT              (21U)
-#define SDHC_IRQSTATEN_DCESEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DCESEN_SHIFT)) & SDHC_IRQSTATEN_DCESEN_MASK)
+#define SDHC_IRQSTATEN_DCESEN_SET(x)             (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DCESEN_SHIFT)) & SDHC_IRQSTATEN_DCESEN_MASK)
+#define SDHC_IRQSTATEN_DCESEN SDHC_IRQSTATEN_DCESEN_MASK
 #define SDHC_IRQSTATEN_DEBESEN_MASK              (0x400000U)
 #define SDHC_IRQSTATEN_DEBESEN_SHIFT             (22U)
-#define SDHC_IRQSTATEN_DEBESEN(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DEBESEN_SHIFT)) & SDHC_IRQSTATEN_DEBESEN_MASK)
+#define SDHC_IRQSTATEN_DEBESEN_SET(x)            (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DEBESEN_SHIFT)) & SDHC_IRQSTATEN_DEBESEN_MASK)
+#define SDHC_IRQSTATEN_DEBESEN SDHC_IRQSTATEN_DEBESEN_MASK
 #define SDHC_IRQSTATEN_AC12ESEN_MASK             (0x1000000U)
 #define SDHC_IRQSTATEN_AC12ESEN_SHIFT            (24U)
-#define SDHC_IRQSTATEN_AC12ESEN(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_AC12ESEN_SHIFT)) & SDHC_IRQSTATEN_AC12ESEN_MASK)
+#define SDHC_IRQSTATEN_AC12ESEN_SET(x)           (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_AC12ESEN_SHIFT)) & SDHC_IRQSTATEN_AC12ESEN_MASK)
+#define SDHC_IRQSTATEN_AC12ESEN SDHC_IRQSTATEN_AC12ESEN_MASK
 #define SDHC_IRQSTATEN_DMAESEN_MASK              (0x10000000U)
 #define SDHC_IRQSTATEN_DMAESEN_SHIFT             (28U)
-#define SDHC_IRQSTATEN_DMAESEN(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DMAESEN_SHIFT)) & SDHC_IRQSTATEN_DMAESEN_MASK)
+#define SDHC_IRQSTATEN_DMAESEN_SET(x)            (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DMAESEN_SHIFT)) & SDHC_IRQSTATEN_DMAESEN_MASK)
+#define SDHC_IRQSTATEN_DMAESEN SDHC_IRQSTATEN_DMAESEN_MASK
 
 /*! @name IRQSIGEN - Interrupt Signal Enable register */
 #define SDHC_IRQSIGEN_CCIEN_MASK                 (0x1U)
 #define SDHC_IRQSIGEN_CCIEN_SHIFT                (0U)
-#define SDHC_IRQSIGEN_CCIEN(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCIEN_SHIFT)) & SDHC_IRQSIGEN_CCIEN_MASK)
+#define SDHC_IRQSIGEN_CCIEN_SET(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCIEN_SHIFT)) & SDHC_IRQSIGEN_CCIEN_MASK)
+#define SDHC_IRQSIGEN_CCIEN SDHC_IRQSIGEN_CCIEN_MASK
 #define SDHC_IRQSIGEN_TCIEN_MASK                 (0x2U)
 #define SDHC_IRQSIGEN_TCIEN_SHIFT                (1U)
-#define SDHC_IRQSIGEN_TCIEN(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_TCIEN_SHIFT)) & SDHC_IRQSIGEN_TCIEN_MASK)
+#define SDHC_IRQSIGEN_TCIEN_SET(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_TCIEN_SHIFT)) & SDHC_IRQSIGEN_TCIEN_MASK)
+#define SDHC_IRQSIGEN_TCIEN SDHC_IRQSIGEN_TCIEN_MASK
 #define SDHC_IRQSIGEN_BGEIEN_MASK                (0x4U)
 #define SDHC_IRQSIGEN_BGEIEN_SHIFT               (2U)
-#define SDHC_IRQSIGEN_BGEIEN(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BGEIEN_SHIFT)) & SDHC_IRQSIGEN_BGEIEN_MASK)
+#define SDHC_IRQSIGEN_BGEIEN_SET(x)              (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BGEIEN_SHIFT)) & SDHC_IRQSIGEN_BGEIEN_MASK)
+#define SDHC_IRQSIGEN_BGEIEN SDHC_IRQSIGEN_BGEIEN_MASK
 #define SDHC_IRQSIGEN_DINTIEN_MASK               (0x8U)
 #define SDHC_IRQSIGEN_DINTIEN_SHIFT              (3U)
-#define SDHC_IRQSIGEN_DINTIEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DINTIEN_SHIFT)) & SDHC_IRQSIGEN_DINTIEN_MASK)
+#define SDHC_IRQSIGEN_DINTIEN_SET(x)             (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DINTIEN_SHIFT)) & SDHC_IRQSIGEN_DINTIEN_MASK)
+#define SDHC_IRQSIGEN_DINTIEN SDHC_IRQSIGEN_DINTIEN_MASK
 #define SDHC_IRQSIGEN_BWRIEN_MASK                (0x10U)
 #define SDHC_IRQSIGEN_BWRIEN_SHIFT               (4U)
-#define SDHC_IRQSIGEN_BWRIEN(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BWRIEN_SHIFT)) & SDHC_IRQSIGEN_BWRIEN_MASK)
+#define SDHC_IRQSIGEN_BWRIEN_SET(x)              (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BWRIEN_SHIFT)) & SDHC_IRQSIGEN_BWRIEN_MASK)
+#define SDHC_IRQSIGEN_BWRIEN SDHC_IRQSIGEN_BWRIEN_MASK
 #define SDHC_IRQSIGEN_BRRIEN_MASK                (0x20U)
 #define SDHC_IRQSIGEN_BRRIEN_SHIFT               (5U)
-#define SDHC_IRQSIGEN_BRRIEN(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BRRIEN_SHIFT)) & SDHC_IRQSIGEN_BRRIEN_MASK)
+#define SDHC_IRQSIGEN_BRRIEN_SET(x)              (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BRRIEN_SHIFT)) & SDHC_IRQSIGEN_BRRIEN_MASK)
+#define SDHC_IRQSIGEN_BRRIEN SDHC_IRQSIGEN_BRRIEN_MASK
 #define SDHC_IRQSIGEN_CINSIEN_MASK               (0x40U)
 #define SDHC_IRQSIGEN_CINSIEN_SHIFT              (6U)
-#define SDHC_IRQSIGEN_CINSIEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINSIEN_SHIFT)) & SDHC_IRQSIGEN_CINSIEN_MASK)
+#define SDHC_IRQSIGEN_CINSIEN_SET(x)             (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINSIEN_SHIFT)) & SDHC_IRQSIGEN_CINSIEN_MASK)
+#define SDHC_IRQSIGEN_CINSIEN SDHC_IRQSIGEN_CINSIEN_MASK
 #define SDHC_IRQSIGEN_CRMIEN_MASK                (0x80U)
 #define SDHC_IRQSIGEN_CRMIEN_SHIFT               (7U)
-#define SDHC_IRQSIGEN_CRMIEN(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CRMIEN_SHIFT)) & SDHC_IRQSIGEN_CRMIEN_MASK)
+#define SDHC_IRQSIGEN_CRMIEN_SET(x)              (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CRMIEN_SHIFT)) & SDHC_IRQSIGEN_CRMIEN_MASK)
+#define SDHC_IRQSIGEN_CRMIEN SDHC_IRQSIGEN_CRMIEN_MASK
 #define SDHC_IRQSIGEN_CINTIEN_MASK               (0x100U)
 #define SDHC_IRQSIGEN_CINTIEN_SHIFT              (8U)
-#define SDHC_IRQSIGEN_CINTIEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINTIEN_SHIFT)) & SDHC_IRQSIGEN_CINTIEN_MASK)
+#define SDHC_IRQSIGEN_CINTIEN_SET(x)             (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINTIEN_SHIFT)) & SDHC_IRQSIGEN_CINTIEN_MASK)
+#define SDHC_IRQSIGEN_CINTIEN SDHC_IRQSIGEN_CINTIEN_MASK
 #define SDHC_IRQSIGEN_CTOEIEN_MASK               (0x10000U)
 #define SDHC_IRQSIGEN_CTOEIEN_SHIFT              (16U)
-#define SDHC_IRQSIGEN_CTOEIEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CTOEIEN_SHIFT)) & SDHC_IRQSIGEN_CTOEIEN_MASK)
+#define SDHC_IRQSIGEN_CTOEIEN_SET(x)             (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CTOEIEN_SHIFT)) & SDHC_IRQSIGEN_CTOEIEN_MASK)
+#define SDHC_IRQSIGEN_CTOEIEN SDHC_IRQSIGEN_CTOEIEN_MASK
 #define SDHC_IRQSIGEN_CCEIEN_MASK                (0x20000U)
 #define SDHC_IRQSIGEN_CCEIEN_SHIFT               (17U)
-#define SDHC_IRQSIGEN_CCEIEN(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCEIEN_SHIFT)) & SDHC_IRQSIGEN_CCEIEN_MASK)
+#define SDHC_IRQSIGEN_CCEIEN_SET(x)              (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCEIEN_SHIFT)) & SDHC_IRQSIGEN_CCEIEN_MASK)
+#define SDHC_IRQSIGEN_CCEIEN SDHC_IRQSIGEN_CCEIEN_MASK
 #define SDHC_IRQSIGEN_CEBEIEN_MASK               (0x40000U)
 #define SDHC_IRQSIGEN_CEBEIEN_SHIFT              (18U)
-#define SDHC_IRQSIGEN_CEBEIEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CEBEIEN_SHIFT)) & SDHC_IRQSIGEN_CEBEIEN_MASK)
+#define SDHC_IRQSIGEN_CEBEIEN_SET(x)             (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CEBEIEN_SHIFT)) & SDHC_IRQSIGEN_CEBEIEN_MASK)
+#define SDHC_IRQSIGEN_CEBEIEN SDHC_IRQSIGEN_CEBEIEN_MASK
 #define SDHC_IRQSIGEN_CIEIEN_MASK                (0x80000U)
 #define SDHC_IRQSIGEN_CIEIEN_SHIFT               (19U)
-#define SDHC_IRQSIGEN_CIEIEN(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CIEIEN_SHIFT)) & SDHC_IRQSIGEN_CIEIEN_MASK)
+#define SDHC_IRQSIGEN_CIEIEN_SET(x)              (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CIEIEN_SHIFT)) & SDHC_IRQSIGEN_CIEIEN_MASK)
+#define SDHC_IRQSIGEN_CIEIEN SDHC_IRQSIGEN_CIEIEN_MASK
 #define SDHC_IRQSIGEN_DTOEIEN_MASK               (0x100000U)
 #define SDHC_IRQSIGEN_DTOEIEN_SHIFT              (20U)
-#define SDHC_IRQSIGEN_DTOEIEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DTOEIEN_SHIFT)) & SDHC_IRQSIGEN_DTOEIEN_MASK)
+#define SDHC_IRQSIGEN_DTOEIEN_SET(x)             (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DTOEIEN_SHIFT)) & SDHC_IRQSIGEN_DTOEIEN_MASK)
+#define SDHC_IRQSIGEN_DTOEIEN SDHC_IRQSIGEN_DTOEIEN_MASK
 #define SDHC_IRQSIGEN_DCEIEN_MASK                (0x200000U)
 #define SDHC_IRQSIGEN_DCEIEN_SHIFT               (21U)
-#define SDHC_IRQSIGEN_DCEIEN(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DCEIEN_SHIFT)) & SDHC_IRQSIGEN_DCEIEN_MASK)
+#define SDHC_IRQSIGEN_DCEIEN_SET(x)              (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DCEIEN_SHIFT)) & SDHC_IRQSIGEN_DCEIEN_MASK)
+#define SDHC_IRQSIGEN_DCEIEN SDHC_IRQSIGEN_DCEIEN_MASK
 #define SDHC_IRQSIGEN_DEBEIEN_MASK               (0x400000U)
 #define SDHC_IRQSIGEN_DEBEIEN_SHIFT              (22U)
-#define SDHC_IRQSIGEN_DEBEIEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DEBEIEN_SHIFT)) & SDHC_IRQSIGEN_DEBEIEN_MASK)
+#define SDHC_IRQSIGEN_DEBEIEN_SET(x)             (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DEBEIEN_SHIFT)) & SDHC_IRQSIGEN_DEBEIEN_MASK)
+#define SDHC_IRQSIGEN_DEBEIEN SDHC_IRQSIGEN_DEBEIEN_MASK
 #define SDHC_IRQSIGEN_AC12EIEN_MASK              (0x1000000U)
 #define SDHC_IRQSIGEN_AC12EIEN_SHIFT             (24U)
-#define SDHC_IRQSIGEN_AC12EIEN(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_AC12EIEN_SHIFT)) & SDHC_IRQSIGEN_AC12EIEN_MASK)
+#define SDHC_IRQSIGEN_AC12EIEN_SET(x)            (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_AC12EIEN_SHIFT)) & SDHC_IRQSIGEN_AC12EIEN_MASK)
+#define SDHC_IRQSIGEN_AC12EIEN SDHC_IRQSIGEN_AC12EIEN_MASK
 #define SDHC_IRQSIGEN_DMAEIEN_MASK               (0x10000000U)
 #define SDHC_IRQSIGEN_DMAEIEN_SHIFT              (28U)
-#define SDHC_IRQSIGEN_DMAEIEN(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DMAEIEN_SHIFT)) & SDHC_IRQSIGEN_DMAEIEN_MASK)
+#define SDHC_IRQSIGEN_DMAEIEN_SET(x)             (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DMAEIEN_SHIFT)) & SDHC_IRQSIGEN_DMAEIEN_MASK)
+#define SDHC_IRQSIGEN_DMAEIEN SDHC_IRQSIGEN_DMAEIEN_MASK
 
 /*! @name AC12ERR - Auto CMD12 Error Status Register */
 #define SDHC_AC12ERR_AC12NE_MASK                 (0x1U)
 #define SDHC_AC12ERR_AC12NE_SHIFT                (0U)
-#define SDHC_AC12ERR_AC12NE(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12NE_SHIFT)) & SDHC_AC12ERR_AC12NE_MASK)
+#define SDHC_AC12ERR_AC12NE_SET(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12NE_SHIFT)) & SDHC_AC12ERR_AC12NE_MASK)
+#define SDHC_AC12ERR_AC12NE SDHC_AC12ERR_AC12NE_MASK
 #define SDHC_AC12ERR_AC12TOE_MASK                (0x2U)
 #define SDHC_AC12ERR_AC12TOE_SHIFT               (1U)
-#define SDHC_AC12ERR_AC12TOE(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12TOE_SHIFT)) & SDHC_AC12ERR_AC12TOE_MASK)
+#define SDHC_AC12ERR_AC12TOE_SET(x)              (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12TOE_SHIFT)) & SDHC_AC12ERR_AC12TOE_MASK)
+#define SDHC_AC12ERR_AC12TOE SDHC_AC12ERR_AC12TOE_MASK
 #define SDHC_AC12ERR_AC12EBE_MASK                (0x4U)
 #define SDHC_AC12ERR_AC12EBE_SHIFT               (2U)
-#define SDHC_AC12ERR_AC12EBE(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12EBE_SHIFT)) & SDHC_AC12ERR_AC12EBE_MASK)
+#define SDHC_AC12ERR_AC12EBE_SET(x)              (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12EBE_SHIFT)) & SDHC_AC12ERR_AC12EBE_MASK)
+#define SDHC_AC12ERR_AC12EBE SDHC_AC12ERR_AC12EBE_MASK
 #define SDHC_AC12ERR_AC12CE_MASK                 (0x8U)
 #define SDHC_AC12ERR_AC12CE_SHIFT                (3U)
-#define SDHC_AC12ERR_AC12CE(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12CE_SHIFT)) & SDHC_AC12ERR_AC12CE_MASK)
+#define SDHC_AC12ERR_AC12CE_SET(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12CE_SHIFT)) & SDHC_AC12ERR_AC12CE_MASK)
+#define SDHC_AC12ERR_AC12CE SDHC_AC12ERR_AC12CE_MASK
 #define SDHC_AC12ERR_AC12IE_MASK                 (0x10U)
 #define SDHC_AC12ERR_AC12IE_SHIFT                (4U)
-#define SDHC_AC12ERR_AC12IE(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12IE_SHIFT)) & SDHC_AC12ERR_AC12IE_MASK)
+#define SDHC_AC12ERR_AC12IE_SET(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12IE_SHIFT)) & SDHC_AC12ERR_AC12IE_MASK)
+#define SDHC_AC12ERR_AC12IE SDHC_AC12ERR_AC12IE_MASK
 #define SDHC_AC12ERR_CNIBAC12E_MASK              (0x80U)
 #define SDHC_AC12ERR_CNIBAC12E_SHIFT             (7U)
-#define SDHC_AC12ERR_CNIBAC12E(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_CNIBAC12E_SHIFT)) & SDHC_AC12ERR_CNIBAC12E_MASK)
+#define SDHC_AC12ERR_CNIBAC12E_SET(x)            (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_CNIBAC12E_SHIFT)) & SDHC_AC12ERR_CNIBAC12E_MASK)
+#define SDHC_AC12ERR_CNIBAC12E SDHC_AC12ERR_CNIBAC12E_MASK
 
 /*! @name HTCAPBLT - Host Controller Capabilities */
 #define SDHC_HTCAPBLT_MBL_MASK                   (0x70000U)
 #define SDHC_HTCAPBLT_MBL_SHIFT                  (16U)
-#define SDHC_HTCAPBLT_MBL(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_MBL_SHIFT)) & SDHC_HTCAPBLT_MBL_MASK)
+#define SDHC_HTCAPBLT_MBL_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_MBL_SHIFT)) & SDHC_HTCAPBLT_MBL_MASK)
+#define SDHC_HTCAPBLT_MBL SDHC_HTCAPBLT_MBL_MASK
 #define SDHC_HTCAPBLT_ADMAS_MASK                 (0x100000U)
 #define SDHC_HTCAPBLT_ADMAS_SHIFT                (20U)
-#define SDHC_HTCAPBLT_ADMAS(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_ADMAS_SHIFT)) & SDHC_HTCAPBLT_ADMAS_MASK)
+#define SDHC_HTCAPBLT_ADMAS_SET(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_ADMAS_SHIFT)) & SDHC_HTCAPBLT_ADMAS_MASK)
+#define SDHC_HTCAPBLT_ADMAS SDHC_HTCAPBLT_ADMAS_MASK
 #define SDHC_HTCAPBLT_HSS_MASK                   (0x200000U)
 #define SDHC_HTCAPBLT_HSS_SHIFT                  (21U)
-#define SDHC_HTCAPBLT_HSS(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_HSS_SHIFT)) & SDHC_HTCAPBLT_HSS_MASK)
+#define SDHC_HTCAPBLT_HSS_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_HSS_SHIFT)) & SDHC_HTCAPBLT_HSS_MASK)
+#define SDHC_HTCAPBLT_HSS SDHC_HTCAPBLT_HSS_MASK
 #define SDHC_HTCAPBLT_DMAS_MASK                  (0x400000U)
 #define SDHC_HTCAPBLT_DMAS_SHIFT                 (22U)
-#define SDHC_HTCAPBLT_DMAS(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_DMAS_SHIFT)) & SDHC_HTCAPBLT_DMAS_MASK)
+#define SDHC_HTCAPBLT_DMAS_SET(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_DMAS_SHIFT)) & SDHC_HTCAPBLT_DMAS_MASK)
+#define SDHC_HTCAPBLT_DMAS SDHC_HTCAPBLT_DMAS_MASK
 #define SDHC_HTCAPBLT_SRS_MASK                   (0x800000U)
 #define SDHC_HTCAPBLT_SRS_SHIFT                  (23U)
-#define SDHC_HTCAPBLT_SRS(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_SRS_SHIFT)) & SDHC_HTCAPBLT_SRS_MASK)
+#define SDHC_HTCAPBLT_SRS_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_SRS_SHIFT)) & SDHC_HTCAPBLT_SRS_MASK)
+#define SDHC_HTCAPBLT_SRS SDHC_HTCAPBLT_SRS_MASK
 #define SDHC_HTCAPBLT_VS33_MASK                  (0x1000000U)
 #define SDHC_HTCAPBLT_VS33_SHIFT                 (24U)
-#define SDHC_HTCAPBLT_VS33(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_VS33_SHIFT)) & SDHC_HTCAPBLT_VS33_MASK)
+#define SDHC_HTCAPBLT_VS33_SET(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_VS33_SHIFT)) & SDHC_HTCAPBLT_VS33_MASK)
+#define SDHC_HTCAPBLT_VS33 SDHC_HTCAPBLT_VS33_MASK
 
 /*! @name WML - Watermark Level Register */
 #define SDHC_WML_RDWML_MASK                      (0xFFU)
 #define SDHC_WML_RDWML_SHIFT                     (0U)
-#define SDHC_WML_RDWML(x)                        (((uint32_t)(((uint32_t)(x)) << SDHC_WML_RDWML_SHIFT)) & SDHC_WML_RDWML_MASK)
+#define SDHC_WML_RDWML_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_WML_RDWML_SHIFT)) & SDHC_WML_RDWML_MASK)
+#define SDHC_WML_RDWML SDHC_WML_RDWML_MASK
 #define SDHC_WML_WRWML_MASK                      (0xFF0000U)
 #define SDHC_WML_WRWML_SHIFT                     (16U)
-#define SDHC_WML_WRWML(x)                        (((uint32_t)(((uint32_t)(x)) << SDHC_WML_WRWML_SHIFT)) & SDHC_WML_WRWML_MASK)
+#define SDHC_WML_WRWML_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_WML_WRWML_SHIFT)) & SDHC_WML_WRWML_MASK)
+#define SDHC_WML_WRWML SDHC_WML_WRWML_MASK
 
 /*! @name FEVT - Force Event register */
 #define SDHC_FEVT_AC12NE_MASK                    (0x1U)
 #define SDHC_FEVT_AC12NE_SHIFT                   (0U)
-#define SDHC_FEVT_AC12NE(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12NE_SHIFT)) & SDHC_FEVT_AC12NE_MASK)
+#define SDHC_FEVT_AC12NE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12NE_SHIFT)) & SDHC_FEVT_AC12NE_MASK)
+#define SDHC_FEVT_AC12NE SDHC_FEVT_AC12NE_MASK
 #define SDHC_FEVT_AC12TOE_MASK                   (0x2U)
 #define SDHC_FEVT_AC12TOE_SHIFT                  (1U)
-#define SDHC_FEVT_AC12TOE(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12TOE_SHIFT)) & SDHC_FEVT_AC12TOE_MASK)
+#define SDHC_FEVT_AC12TOE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12TOE_SHIFT)) & SDHC_FEVT_AC12TOE_MASK)
+#define SDHC_FEVT_AC12TOE SDHC_FEVT_AC12TOE_MASK
 #define SDHC_FEVT_AC12CE_MASK                    (0x4U)
 #define SDHC_FEVT_AC12CE_SHIFT                   (2U)
-#define SDHC_FEVT_AC12CE(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12CE_SHIFT)) & SDHC_FEVT_AC12CE_MASK)
+#define SDHC_FEVT_AC12CE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12CE_SHIFT)) & SDHC_FEVT_AC12CE_MASK)
+#define SDHC_FEVT_AC12CE SDHC_FEVT_AC12CE_MASK
 #define SDHC_FEVT_AC12EBE_MASK                   (0x8U)
 #define SDHC_FEVT_AC12EBE_SHIFT                  (3U)
-#define SDHC_FEVT_AC12EBE(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12EBE_SHIFT)) & SDHC_FEVT_AC12EBE_MASK)
+#define SDHC_FEVT_AC12EBE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12EBE_SHIFT)) & SDHC_FEVT_AC12EBE_MASK)
+#define SDHC_FEVT_AC12EBE SDHC_FEVT_AC12EBE_MASK
 #define SDHC_FEVT_AC12IE_MASK                    (0x10U)
 #define SDHC_FEVT_AC12IE_SHIFT                   (4U)
-#define SDHC_FEVT_AC12IE(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12IE_SHIFT)) & SDHC_FEVT_AC12IE_MASK)
+#define SDHC_FEVT_AC12IE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12IE_SHIFT)) & SDHC_FEVT_AC12IE_MASK)
+#define SDHC_FEVT_AC12IE SDHC_FEVT_AC12IE_MASK
 #define SDHC_FEVT_CNIBAC12E_MASK                 (0x80U)
 #define SDHC_FEVT_CNIBAC12E_SHIFT                (7U)
-#define SDHC_FEVT_CNIBAC12E(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CNIBAC12E_SHIFT)) & SDHC_FEVT_CNIBAC12E_MASK)
+#define SDHC_FEVT_CNIBAC12E_SET(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CNIBAC12E_SHIFT)) & SDHC_FEVT_CNIBAC12E_MASK)
+#define SDHC_FEVT_CNIBAC12E SDHC_FEVT_CNIBAC12E_MASK
 #define SDHC_FEVT_CTOE_MASK                      (0x10000U)
 #define SDHC_FEVT_CTOE_SHIFT                     (16U)
-#define SDHC_FEVT_CTOE(x)                        (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CTOE_SHIFT)) & SDHC_FEVT_CTOE_MASK)
+#define SDHC_FEVT_CTOE_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CTOE_SHIFT)) & SDHC_FEVT_CTOE_MASK)
+#define SDHC_FEVT_CTOE SDHC_FEVT_CTOE_MASK
 #define SDHC_FEVT_CCE_MASK                       (0x20000U)
 #define SDHC_FEVT_CCE_SHIFT                      (17U)
-#define SDHC_FEVT_CCE(x)                         (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CCE_SHIFT)) & SDHC_FEVT_CCE_MASK)
+#define SDHC_FEVT_CCE_SET(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CCE_SHIFT)) & SDHC_FEVT_CCE_MASK)
+#define SDHC_FEVT_CCE SDHC_FEVT_CCE_MASK
 #define SDHC_FEVT_CEBE_MASK                      (0x40000U)
 #define SDHC_FEVT_CEBE_SHIFT                     (18U)
-#define SDHC_FEVT_CEBE(x)                        (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CEBE_SHIFT)) & SDHC_FEVT_CEBE_MASK)
+#define SDHC_FEVT_CEBE_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CEBE_SHIFT)) & SDHC_FEVT_CEBE_MASK)
+#define SDHC_FEVT_CEBE SDHC_FEVT_CEBE_MASK
 #define SDHC_FEVT_CIE_MASK                       (0x80000U)
 #define SDHC_FEVT_CIE_SHIFT                      (19U)
-#define SDHC_FEVT_CIE(x)                         (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CIE_SHIFT)) & SDHC_FEVT_CIE_MASK)
+#define SDHC_FEVT_CIE_SET(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CIE_SHIFT)) & SDHC_FEVT_CIE_MASK)
+#define SDHC_FEVT_CIE SDHC_FEVT_CIE_MASK
 #define SDHC_FEVT_DTOE_MASK                      (0x100000U)
 #define SDHC_FEVT_DTOE_SHIFT                     (20U)
-#define SDHC_FEVT_DTOE(x)                        (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DTOE_SHIFT)) & SDHC_FEVT_DTOE_MASK)
+#define SDHC_FEVT_DTOE_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DTOE_SHIFT)) & SDHC_FEVT_DTOE_MASK)
+#define SDHC_FEVT_DTOE SDHC_FEVT_DTOE_MASK
 #define SDHC_FEVT_DCE_MASK                       (0x200000U)
 #define SDHC_FEVT_DCE_SHIFT                      (21U)
-#define SDHC_FEVT_DCE(x)                         (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DCE_SHIFT)) & SDHC_FEVT_DCE_MASK)
+#define SDHC_FEVT_DCE_SET(x)                     (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DCE_SHIFT)) & SDHC_FEVT_DCE_MASK)
+#define SDHC_FEVT_DCE SDHC_FEVT_DCE_MASK
 #define SDHC_FEVT_DEBE_MASK                      (0x400000U)
 #define SDHC_FEVT_DEBE_SHIFT                     (22U)
-#define SDHC_FEVT_DEBE(x)                        (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DEBE_SHIFT)) & SDHC_FEVT_DEBE_MASK)
+#define SDHC_FEVT_DEBE_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DEBE_SHIFT)) & SDHC_FEVT_DEBE_MASK)
+#define SDHC_FEVT_DEBE SDHC_FEVT_DEBE_MASK
 #define SDHC_FEVT_AC12E_MASK                     (0x1000000U)
 #define SDHC_FEVT_AC12E_SHIFT                    (24U)
-#define SDHC_FEVT_AC12E(x)                       (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12E_SHIFT)) & SDHC_FEVT_AC12E_MASK)
+#define SDHC_FEVT_AC12E_SET(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12E_SHIFT)) & SDHC_FEVT_AC12E_MASK)
+#define SDHC_FEVT_AC12E SDHC_FEVT_AC12E_MASK
 #define SDHC_FEVT_DMAE_MASK                      (0x10000000U)
 #define SDHC_FEVT_DMAE_SHIFT                     (28U)
-#define SDHC_FEVT_DMAE(x)                        (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DMAE_SHIFT)) & SDHC_FEVT_DMAE_MASK)
+#define SDHC_FEVT_DMAE_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DMAE_SHIFT)) & SDHC_FEVT_DMAE_MASK)
+#define SDHC_FEVT_DMAE SDHC_FEVT_DMAE_MASK
 #define SDHC_FEVT_CINT_MASK                      (0x80000000U)
 #define SDHC_FEVT_CINT_SHIFT                     (31U)
-#define SDHC_FEVT_CINT(x)                        (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CINT_SHIFT)) & SDHC_FEVT_CINT_MASK)
+#define SDHC_FEVT_CINT_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CINT_SHIFT)) & SDHC_FEVT_CINT_MASK)
+#define SDHC_FEVT_CINT SDHC_FEVT_CINT_MASK
 
 /*! @name ADMAES - ADMA Error Status register */
 #define SDHC_ADMAES_ADMAES_MASK                  (0x3U)
 #define SDHC_ADMAES_ADMAES_SHIFT                 (0U)
-#define SDHC_ADMAES_ADMAES(x)                    (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMAES_SHIFT)) & SDHC_ADMAES_ADMAES_MASK)
+#define SDHC_ADMAES_ADMAES_SET(x)                (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMAES_SHIFT)) & SDHC_ADMAES_ADMAES_MASK)
+#define SDHC_ADMAES_ADMAES SDHC_ADMAES_ADMAES_MASK
 #define SDHC_ADMAES_ADMALME_MASK                 (0x4U)
 #define SDHC_ADMAES_ADMALME_SHIFT                (2U)
-#define SDHC_ADMAES_ADMALME(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMALME_SHIFT)) & SDHC_ADMAES_ADMALME_MASK)
+#define SDHC_ADMAES_ADMALME_SET(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMALME_SHIFT)) & SDHC_ADMAES_ADMALME_MASK)
+#define SDHC_ADMAES_ADMALME SDHC_ADMAES_ADMALME_MASK
 #define SDHC_ADMAES_ADMADCE_MASK                 (0x8U)
 #define SDHC_ADMAES_ADMADCE_SHIFT                (3U)
-#define SDHC_ADMAES_ADMADCE(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMADCE_SHIFT)) & SDHC_ADMAES_ADMADCE_MASK)
+#define SDHC_ADMAES_ADMADCE_SET(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMADCE_SHIFT)) & SDHC_ADMAES_ADMADCE_MASK)
+#define SDHC_ADMAES_ADMADCE SDHC_ADMAES_ADMADCE_MASK
 
 /*! @name ADSADDR - ADMA System Addressregister */
 #define SDHC_ADSADDR_ADSADDR_MASK                (0xFFFFFFFCU)
 #define SDHC_ADSADDR_ADSADDR_SHIFT               (2U)
-#define SDHC_ADSADDR_ADSADDR(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_ADSADDR_ADSADDR_SHIFT)) & SDHC_ADSADDR_ADSADDR_MASK)
+#define SDHC_ADSADDR_ADSADDR_SET(x)              (((uint32_t)(((uint32_t)(x)) << SDHC_ADSADDR_ADSADDR_SHIFT)) & SDHC_ADSADDR_ADSADDR_MASK)
+#define SDHC_ADSADDR_ADSADDR SDHC_ADSADDR_ADSADDR_MASK
 
 /*! @name VENDOR - Vendor Specific register */
 #define SDHC_VENDOR_EXBLKNU_MASK                 (0x2U)
 #define SDHC_VENDOR_EXBLKNU_SHIFT                (1U)
-#define SDHC_VENDOR_EXBLKNU(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXBLKNU_SHIFT)) & SDHC_VENDOR_EXBLKNU_MASK)
+#define SDHC_VENDOR_EXBLKNU_SET(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXBLKNU_SHIFT)) & SDHC_VENDOR_EXBLKNU_MASK)
+#define SDHC_VENDOR_EXBLKNU SDHC_VENDOR_EXBLKNU_MASK
 #define SDHC_VENDOR_INTSTVAL_MASK                (0xFF0000U)
 #define SDHC_VENDOR_INTSTVAL_SHIFT               (16U)
-#define SDHC_VENDOR_INTSTVAL(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_INTSTVAL_SHIFT)) & SDHC_VENDOR_INTSTVAL_MASK)
+#define SDHC_VENDOR_INTSTVAL_SET(x)              (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_INTSTVAL_SHIFT)) & SDHC_VENDOR_INTSTVAL_MASK)
+#define SDHC_VENDOR_INTSTVAL SDHC_VENDOR_INTSTVAL_MASK
 
 /*! @name MMCBOOT - MMC Boot register */
 #define SDHC_MMCBOOT_DTOCVACK_MASK               (0xFU)
 #define SDHC_MMCBOOT_DTOCVACK_SHIFT              (0U)
-#define SDHC_MMCBOOT_DTOCVACK(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_DTOCVACK_SHIFT)) & SDHC_MMCBOOT_DTOCVACK_MASK)
+#define SDHC_MMCBOOT_DTOCVACK_SET(x)             (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_DTOCVACK_SHIFT)) & SDHC_MMCBOOT_DTOCVACK_MASK)
+#define SDHC_MMCBOOT_DTOCVACK SDHC_MMCBOOT_DTOCVACK_MASK
 #define SDHC_MMCBOOT_BOOTACK_MASK                (0x10U)
 #define SDHC_MMCBOOT_BOOTACK_SHIFT               (4U)
-#define SDHC_MMCBOOT_BOOTACK(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTACK_SHIFT)) & SDHC_MMCBOOT_BOOTACK_MASK)
+#define SDHC_MMCBOOT_BOOTACK_SET(x)              (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTACK_SHIFT)) & SDHC_MMCBOOT_BOOTACK_MASK)
+#define SDHC_MMCBOOT_BOOTACK SDHC_MMCBOOT_BOOTACK_MASK
 #define SDHC_MMCBOOT_BOOTMODE_MASK               (0x20U)
 #define SDHC_MMCBOOT_BOOTMODE_SHIFT              (5U)
-#define SDHC_MMCBOOT_BOOTMODE(x)                 (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTMODE_SHIFT)) & SDHC_MMCBOOT_BOOTMODE_MASK)
+#define SDHC_MMCBOOT_BOOTMODE_SET(x)             (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTMODE_SHIFT)) & SDHC_MMCBOOT_BOOTMODE_MASK)
+#define SDHC_MMCBOOT_BOOTMODE SDHC_MMCBOOT_BOOTMODE_MASK
 #define SDHC_MMCBOOT_BOOTEN_MASK                 (0x40U)
 #define SDHC_MMCBOOT_BOOTEN_SHIFT                (6U)
-#define SDHC_MMCBOOT_BOOTEN(x)                   (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTEN_SHIFT)) & SDHC_MMCBOOT_BOOTEN_MASK)
+#define SDHC_MMCBOOT_BOOTEN_SET(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTEN_SHIFT)) & SDHC_MMCBOOT_BOOTEN_MASK)
+#define SDHC_MMCBOOT_BOOTEN SDHC_MMCBOOT_BOOTEN_MASK
 #define SDHC_MMCBOOT_AUTOSABGEN_MASK             (0x80U)
 #define SDHC_MMCBOOT_AUTOSABGEN_SHIFT            (7U)
-#define SDHC_MMCBOOT_AUTOSABGEN(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_AUTOSABGEN_SHIFT)) & SDHC_MMCBOOT_AUTOSABGEN_MASK)
+#define SDHC_MMCBOOT_AUTOSABGEN_SET(x)           (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_AUTOSABGEN_SHIFT)) & SDHC_MMCBOOT_AUTOSABGEN_MASK)
+#define SDHC_MMCBOOT_AUTOSABGEN SDHC_MMCBOOT_AUTOSABGEN_MASK
 #define SDHC_MMCBOOT_BOOTBLKCNT_MASK             (0xFFFF0000U)
 #define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT            (16U)
-#define SDHC_MMCBOOT_BOOTBLKCNT(x)               (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTBLKCNT_SHIFT)) & SDHC_MMCBOOT_BOOTBLKCNT_MASK)
+#define SDHC_MMCBOOT_BOOTBLKCNT_SET(x)           (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTBLKCNT_SHIFT)) & SDHC_MMCBOOT_BOOTBLKCNT_MASK)
+#define SDHC_MMCBOOT_BOOTBLKCNT SDHC_MMCBOOT_BOOTBLKCNT_MASK
 
 /*! @name HOSTVER - Host Controller Version */
 #define SDHC_HOSTVER_SVN_MASK                    (0xFFU)
 #define SDHC_HOSTVER_SVN_SHIFT                   (0U)
-#define SDHC_HOSTVER_SVN(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_SVN_SHIFT)) & SDHC_HOSTVER_SVN_MASK)
+#define SDHC_HOSTVER_SVN_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_SVN_SHIFT)) & SDHC_HOSTVER_SVN_MASK)
+#define SDHC_HOSTVER_SVN SDHC_HOSTVER_SVN_MASK
 #define SDHC_HOSTVER_VVN_MASK                    (0xFF00U)
 #define SDHC_HOSTVER_VVN_SHIFT                   (8U)
-#define SDHC_HOSTVER_VVN(x)                      (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_VVN_SHIFT)) & SDHC_HOSTVER_VVN_MASK)
+#define SDHC_HOSTVER_VVN_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_VVN_SHIFT)) & SDHC_HOSTVER_VVN_MASK)
+#define SDHC_HOSTVER_VVN SDHC_HOSTVER_VVN_MASK
 
 
 /*!
@@ -11862,7 +14348,7 @@ typedef struct {
 /** Peripheral SDHC base address */
 #define SDHC_BASE                                (0x400B1000u)
 /** Peripheral SDHC base pointer */
-#define SDHC                                     ((SDHC_Type *)SDHC_BASE)
+#define SDHC                                     ((SDHC_TypeDef *)SDHC_BASE)
 /** Array initializer of SDHC peripheral base addresses */
 #define SDHC_BASE_ADDRS                          { SDHC_BASE }
 /** Array initializer of SDHC peripheral base pointers */
@@ -11893,7 +14379,7 @@ typedef struct {
     __IO uint32_t AC;                                /**< Address and Control Register, array offset: 0x48, array step: 0x8 */
     __IO uint32_t CM;                                /**< Control Mask, array offset: 0x4C, array step: 0x8 */
   } BLOCK[2];
-} SDRAM_Type;
+} SDRAM_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- SDRAM Register Masks
@@ -11907,36 +14393,46 @@ typedef struct {
 /*! @name CTRL - Control Register */
 #define SDRAM_CTRL_RC_MASK                       (0x1FFU)
 #define SDRAM_CTRL_RC_SHIFT                      (0U)
-#define SDRAM_CTRL_RC(x)                         (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_RC_SHIFT)) & SDRAM_CTRL_RC_MASK)
+#define SDRAM_CTRL_RC_SET(x)                     (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_RC_SHIFT)) & SDRAM_CTRL_RC_MASK)
+#define SDRAM_CTRL_RC SDRAM_CTRL_RC_MASK
 #define SDRAM_CTRL_RTIM_MASK                     (0x600U)
 #define SDRAM_CTRL_RTIM_SHIFT                    (9U)
-#define SDRAM_CTRL_RTIM(x)                       (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_RTIM_SHIFT)) & SDRAM_CTRL_RTIM_MASK)
+#define SDRAM_CTRL_RTIM_SET(x)                   (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_RTIM_SHIFT)) & SDRAM_CTRL_RTIM_MASK)
+#define SDRAM_CTRL_RTIM SDRAM_CTRL_RTIM_MASK
 #define SDRAM_CTRL_IS_MASK                       (0x800U)
 #define SDRAM_CTRL_IS_SHIFT                      (11U)
-#define SDRAM_CTRL_IS(x)                         (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_IS_SHIFT)) & SDRAM_CTRL_IS_MASK)
+#define SDRAM_CTRL_IS_SET(x)                     (((uint16_t)(((uint16_t)(x)) << SDRAM_CTRL_IS_SHIFT)) & SDRAM_CTRL_IS_MASK)
+#define SDRAM_CTRL_IS SDRAM_CTRL_IS_MASK
 
 /*! @name AC - Address and Control Register */
 #define SDRAM_AC_IP_MASK                         (0x8U)
 #define SDRAM_AC_IP_SHIFT                        (3U)
-#define SDRAM_AC_IP(x)                           (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_IP_SHIFT)) & SDRAM_AC_IP_MASK)
+#define SDRAM_AC_IP_SET(x)                       (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_IP_SHIFT)) & SDRAM_AC_IP_MASK)
+#define SDRAM_AC_IP SDRAM_AC_IP_MASK
 #define SDRAM_AC_PS_MASK                         (0x30U)
 #define SDRAM_AC_PS_SHIFT                        (4U)
-#define SDRAM_AC_PS(x)                           (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_PS_SHIFT)) & SDRAM_AC_PS_MASK)
+#define SDRAM_AC_PS_SET(x)                       (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_PS_SHIFT)) & SDRAM_AC_PS_MASK)
+#define SDRAM_AC_PS SDRAM_AC_PS_MASK
 #define SDRAM_AC_IMRS_MASK                       (0x40U)
 #define SDRAM_AC_IMRS_SHIFT                      (6U)
-#define SDRAM_AC_IMRS(x)                         (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_IMRS_SHIFT)) & SDRAM_AC_IMRS_MASK)
+#define SDRAM_AC_IMRS_SET(x)                     (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_IMRS_SHIFT)) & SDRAM_AC_IMRS_MASK)
+#define SDRAM_AC_IMRS SDRAM_AC_IMRS_MASK
 #define SDRAM_AC_CBM_MASK                        (0x700U)
 #define SDRAM_AC_CBM_SHIFT                       (8U)
-#define SDRAM_AC_CBM(x)                          (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_CBM_SHIFT)) & SDRAM_AC_CBM_MASK)
+#define SDRAM_AC_CBM_SET(x)                      (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_CBM_SHIFT)) & SDRAM_AC_CBM_MASK)
+#define SDRAM_AC_CBM SDRAM_AC_CBM_MASK
 #define SDRAM_AC_CASL_MASK                       (0x3000U)
 #define SDRAM_AC_CASL_SHIFT                      (12U)
-#define SDRAM_AC_CASL(x)                         (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_CASL_SHIFT)) & SDRAM_AC_CASL_MASK)
+#define SDRAM_AC_CASL_SET(x)                     (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_CASL_SHIFT)) & SDRAM_AC_CASL_MASK)
+#define SDRAM_AC_CASL SDRAM_AC_CASL_MASK
 #define SDRAM_AC_RE_MASK                         (0x8000U)
 #define SDRAM_AC_RE_SHIFT                        (15U)
-#define SDRAM_AC_RE(x)                           (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_RE_SHIFT)) & SDRAM_AC_RE_MASK)
+#define SDRAM_AC_RE_SET(x)                       (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_RE_SHIFT)) & SDRAM_AC_RE_MASK)
+#define SDRAM_AC_RE SDRAM_AC_RE_MASK
 #define SDRAM_AC_BA_MASK                         (0xFFFC0000U)
 #define SDRAM_AC_BA_SHIFT                        (18U)
-#define SDRAM_AC_BA(x)                           (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_BA_SHIFT)) & SDRAM_AC_BA_MASK)
+#define SDRAM_AC_BA_SET(x)                       (((uint32_t)(((uint32_t)(x)) << SDRAM_AC_BA_SHIFT)) & SDRAM_AC_BA_MASK)
+#define SDRAM_AC_BA SDRAM_AC_BA_MASK
 
 /* The count of SDRAM_AC */
 #define SDRAM_AC_COUNT                           (2U)
@@ -11944,13 +14440,16 @@ typedef struct {
 /*! @name CM - Control Mask */
 #define SDRAM_CM_V_MASK                          (0x1U)
 #define SDRAM_CM_V_SHIFT                         (0U)
-#define SDRAM_CM_V(x)                            (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_V_SHIFT)) & SDRAM_CM_V_MASK)
+#define SDRAM_CM_V_SET(x)                        (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_V_SHIFT)) & SDRAM_CM_V_MASK)
+#define SDRAM_CM_V SDRAM_CM_V_MASK
 #define SDRAM_CM_WP_MASK                         (0x100U)
 #define SDRAM_CM_WP_SHIFT                        (8U)
-#define SDRAM_CM_WP(x)                           (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_WP_SHIFT)) & SDRAM_CM_WP_MASK)
+#define SDRAM_CM_WP_SET(x)                       (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_WP_SHIFT)) & SDRAM_CM_WP_MASK)
+#define SDRAM_CM_WP SDRAM_CM_WP_MASK
 #define SDRAM_CM_BAM_MASK                        (0xFFFC0000U)
 #define SDRAM_CM_BAM_SHIFT                       (18U)
-#define SDRAM_CM_BAM(x)                          (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_BAM_SHIFT)) & SDRAM_CM_BAM_MASK)
+#define SDRAM_CM_BAM_SET(x)                      (((uint32_t)(((uint32_t)(x)) << SDRAM_CM_BAM_SHIFT)) & SDRAM_CM_BAM_MASK)
+#define SDRAM_CM_BAM SDRAM_CM_BAM_MASK
 
 /* The count of SDRAM_CM */
 #define SDRAM_CM_COUNT                           (2U)
@@ -11965,7 +14464,7 @@ typedef struct {
 /** Peripheral SDRAM base address */
 #define SDRAM_BASE                               (0x4000F000u)
 /** Peripheral SDRAM base pointer */
-#define SDRAM                                    ((SDRAM_Type *)SDRAM_BASE)
+#define SDRAM                                    ((SDRAM_TypeDef *)SDRAM_BASE)
 /** Array initializer of SDRAM peripheral base addresses */
 #define SDRAM_BASE_ADDRS                         { SDRAM_BASE }
 /** Array initializer of SDRAM peripheral base pointers */
@@ -12017,7 +14516,7 @@ typedef struct {
   __I  uint32_t UIDL;                              /**< Unique Identification Register Low, offset: 0x1060 */
   __IO uint32_t CLKDIV3;                           /**< System Clock Divider Register 3, offset: 0x1064 */
   __IO uint32_t CLKDIV4;                           /**< System Clock Divider Register 4, offset: 0x1068 */
-} SIM_Type;
+} SIM_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- SIM Register Masks
@@ -12031,16 +14530,20 @@ typedef struct {
 /*! @name SOPT1 - System Options Register 1 */
 #define SIM_SOPT1_RAMSIZE_MASK                   (0xF000U)
 #define SIM_SOPT1_RAMSIZE_SHIFT                  (12U)
-#define SIM_SOPT1_RAMSIZE(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)
+#define SIM_SOPT1_RAMSIZE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)
+#define SIM_SOPT1_RAMSIZE SIM_SOPT1_RAMSIZE_MASK
 #define SIM_SOPT1_OSC32KSEL_MASK                 (0xC0000U)
 #define SIM_SOPT1_OSC32KSEL_SHIFT                (18U)
-#define SIM_SOPT1_OSC32KSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
+#define SIM_SOPT1_OSC32KSEL_SET(x)               (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
+#define SIM_SOPT1_OSC32KSEL SIM_SOPT1_OSC32KSEL_MASK
 #define SIM_SOPT1_USBVSTBY_MASK                  (0x20000000U)
 #define SIM_SOPT1_USBVSTBY_SHIFT                 (29U)
-#define SIM_SOPT1_USBVSTBY(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)
+#define SIM_SOPT1_USBVSTBY_SET(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)
+#define SIM_SOPT1_USBVSTBY SIM_SOPT1_USBVSTBY_MASK
 #define SIM_SOPT1_USBSSTBY_MASK                  (0x40000000U)
 #define SIM_SOPT1_USBSSTBY_SHIFT                 (30U)
-#define SIM_SOPT1_USBSSTBY(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)
+#define SIM_SOPT1_USBSSTBY_SET(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)
+#define SIM_SOPT1_USBSSTBY SIM_SOPT1_USBSSTBY_MASK
 #define SIM_SOPT1_USBREGEN_MASK                  (0x80000000U)
 #define SIM_SOPT1_USBREGEN_SHIFT                 (31U)
 #define SIM_SOPT1_USBREGEN_SET(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)
@@ -12049,24 +14552,30 @@ typedef struct {
 /*! @name SOPT1CFG - SOPT1 Configuration Register */
 #define SIM_SOPT1CFG_URWE_MASK                   (0x1000000U)
 #define SIM_SOPT1CFG_URWE_SHIFT                  (24U)
-#define SIM_SOPT1CFG_URWE(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
+#define SIM_SOPT1CFG_URWE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
+#define SIM_SOPT1CFG_URWE SIM_SOPT1CFG_URWE_MASK
 #define SIM_SOPT1CFG_UVSWE_MASK                  (0x2000000U)
 #define SIM_SOPT1CFG_UVSWE_SHIFT                 (25U)
-#define SIM_SOPT1CFG_UVSWE(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)
+#define SIM_SOPT1CFG_UVSWE_SET(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)
+#define SIM_SOPT1CFG_UVSWE SIM_SOPT1CFG_UVSWE_MASK
 #define SIM_SOPT1CFG_USSWE_MASK                  (0x4000000U)
 #define SIM_SOPT1CFG_USSWE_SHIFT                 (26U)
-#define SIM_SOPT1CFG_USSWE(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)
+#define SIM_SOPT1CFG_USSWE_SET(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)
+#define SIM_SOPT1CFG_USSWE SIM_SOPT1CFG_USSWE_MASK
 
 /*! @name USBPHYCTL - USB PHY Control Register */
 #define SIM_USBPHYCTL_USBVREGSEL_MASK            (0x100U)
 #define SIM_USBPHYCTL_USBVREGSEL_SHIFT           (8U)
-#define SIM_USBPHYCTL_USBVREGSEL(x)              (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBVREGSEL_SHIFT)) & SIM_USBPHYCTL_USBVREGSEL_MASK)
+#define SIM_USBPHYCTL_USBVREGSEL_SET(x)          (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBVREGSEL_SHIFT)) & SIM_USBPHYCTL_USBVREGSEL_MASK)
+#define SIM_USBPHYCTL_USBVREGSEL SIM_USBPHYCTL_USBVREGSEL_MASK
 #define SIM_USBPHYCTL_USBVREGPD_MASK             (0x200U)
 #define SIM_USBPHYCTL_USBVREGPD_SHIFT            (9U)
-#define SIM_USBPHYCTL_USBVREGPD(x)               (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBVREGPD_SHIFT)) & SIM_USBPHYCTL_USBVREGPD_MASK)
+#define SIM_USBPHYCTL_USBVREGPD_SET(x)           (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBVREGPD_SHIFT)) & SIM_USBPHYCTL_USBVREGPD_MASK)
+#define SIM_USBPHYCTL_USBVREGPD SIM_USBPHYCTL_USBVREGPD_MASK
 #define SIM_USBPHYCTL_USB3VOUTTRG_MASK           (0x700000U)
 #define SIM_USBPHYCTL_USB3VOUTTRG_SHIFT          (20U)
-#define SIM_USBPHYCTL_USB3VOUTTRG(x)             (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USB3VOUTTRG_SHIFT)) & SIM_USBPHYCTL_USB3VOUTTRG_MASK)
+#define SIM_USBPHYCTL_USB3VOUTTRG_SET(x)         (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USB3VOUTTRG_SHIFT)) & SIM_USBPHYCTL_USB3VOUTTRG_MASK)
+#define SIM_USBPHYCTL_USB3VOUTTRG SIM_USBPHYCTL_USB3VOUTTRG_MASK
 #define SIM_USBPHYCTL_USBDISILIM_MASK            (0x800000U)
 #define SIM_USBPHYCTL_USBDISILIM_SHIFT           (23U)
 #define SIM_USBPHYCTL_USBDISILIM_SET(x)          (((uint32_t)(((uint32_t)(x)) << SIM_USBPHYCTL_USBDISILIM_SHIFT)) & SIM_USBPHYCTL_USBDISILIM_MASK)
@@ -12075,23 +14584,28 @@ typedef struct {
 /*! @name SOPT2 - System Options Register 2 */
 #define SIM_SOPT2_USBSLSRC_MASK                  (0x1U)
 #define SIM_SOPT2_USBSLSRC_SHIFT                 (0U)
-#define SIM_SOPT2_USBSLSRC(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSLSRC_SHIFT)) & SIM_SOPT2_USBSLSRC_MASK)
+#define SIM_SOPT2_USBSLSRC_SET(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSLSRC_SHIFT)) & SIM_SOPT2_USBSLSRC_MASK)
+#define SIM_SOPT2_USBSLSRC SIM_SOPT2_USBSLSRC_MASK
 #define SIM_SOPT2_USBREGEN_MASK                  (0x2U)
 #define SIM_SOPT2_USBREGEN_SHIFT                 (1U)
 #define SIM_SOPT2_USBREGEN_SET(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBREGEN_SHIFT)) & SIM_SOPT2_USBREGEN_MASK)
 #define SIM_SOPT2_USBREGEN                       SIM_SOPT2_USBREGEN_SET(1)
 #define SIM_SOPT2_RTCCLKOUTSEL_MASK              (0x10U)
 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT             (4U)
-#define SIM_SOPT2_RTCCLKOUTSEL(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
+#define SIM_SOPT2_RTCCLKOUTSEL_SET(x)            (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
+#define SIM_SOPT2_RTCCLKOUTSEL SIM_SOPT2_RTCCLKOUTSEL_MASK
 #define SIM_SOPT2_CLKOUTSEL_MASK                 (0xE0U)
 #define SIM_SOPT2_CLKOUTSEL_SHIFT                (5U)
-#define SIM_SOPT2_CLKOUTSEL(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_CLKOUTSEL_SET(x)               (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
+#define SIM_SOPT2_CLKOUTSEL SIM_SOPT2_CLKOUTSEL_MASK
 #define SIM_SOPT2_FBSL_MASK                      (0x300U)
 #define SIM_SOPT2_FBSL_SHIFT                     (8U)
-#define SIM_SOPT2_FBSL(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FBSL_SHIFT)) & SIM_SOPT2_FBSL_MASK)
+#define SIM_SOPT2_FBSL_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FBSL_SHIFT)) & SIM_SOPT2_FBSL_MASK)
+#define SIM_SOPT2_FBSL SIM_SOPT2_FBSL_MASK
 #define SIM_SOPT2_TRACECLKSEL_MASK               (0x1000U)
 #define SIM_SOPT2_TRACECLKSEL_SHIFT              (12U)
-#define SIM_SOPT2_TRACECLKSEL(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)
+#define SIM_SOPT2_TRACECLKSEL_SET(x)             (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)
+#define SIM_SOPT2_TRACECLKSEL SIM_SOPT2_TRACECLKSEL_MASK
 #define SIM_SOPT2_PLLFLLSEL_MASK                 (0x30000U)
 #define SIM_SOPT2_PLLFLLSEL_SHIFT                (16U)
 #define SIM_SOPT2_PLLFLLSEL_SET(x)               (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
@@ -12102,314 +14616,407 @@ typedef struct {
 #define SIM_SOPT2_USBSRC                         SIM_SOPT2_USBSRC_SET(1)
 #define SIM_SOPT2_RMIISRC_MASK                   (0x80000U)
 #define SIM_SOPT2_RMIISRC_SHIFT                  (19U)
-#define SIM_SOPT2_RMIISRC(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RMIISRC_SHIFT)) & SIM_SOPT2_RMIISRC_MASK)
+#define SIM_SOPT2_RMIISRC_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RMIISRC_SHIFT)) & SIM_SOPT2_RMIISRC_MASK)
+#define SIM_SOPT2_RMIISRC SIM_SOPT2_RMIISRC_MASK
 #define SIM_SOPT2_TIMESRC_MASK                   (0x300000U)
 #define SIM_SOPT2_TIMESRC_SHIFT                  (20U)
-#define SIM_SOPT2_TIMESRC(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TIMESRC_SHIFT)) & SIM_SOPT2_TIMESRC_MASK)
+#define SIM_SOPT2_TIMESRC_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TIMESRC_SHIFT)) & SIM_SOPT2_TIMESRC_MASK)
+#define SIM_SOPT2_TIMESRC SIM_SOPT2_TIMESRC_MASK
 #define SIM_SOPT2_TPMSRC_MASK                    (0x3000000U)
 #define SIM_SOPT2_TPMSRC_SHIFT                   (24U)
-#define SIM_SOPT2_TPMSRC(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TPMSRC_SHIFT)) & SIM_SOPT2_TPMSRC_MASK)
+#define SIM_SOPT2_TPMSRC_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TPMSRC_SHIFT)) & SIM_SOPT2_TPMSRC_MASK)
+#define SIM_SOPT2_TPMSRC SIM_SOPT2_TPMSRC_MASK
 #define SIM_SOPT2_LPUARTSRC_MASK                 (0xC000000U)
 #define SIM_SOPT2_LPUARTSRC_SHIFT                (26U)
-#define SIM_SOPT2_LPUARTSRC(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUARTSRC_SHIFT)) & SIM_SOPT2_LPUARTSRC_MASK)
+#define SIM_SOPT2_LPUARTSRC_SET(x)               (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_LPUARTSRC_SHIFT)) & SIM_SOPT2_LPUARTSRC_MASK)
+#define SIM_SOPT2_LPUARTSRC SIM_SOPT2_LPUARTSRC_MASK
 #define SIM_SOPT2_SDHCSRC_MASK                   (0x30000000U)
 #define SIM_SOPT2_SDHCSRC_SHIFT                  (28U)
-#define SIM_SOPT2_SDHCSRC(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_SDHCSRC_SHIFT)) & SIM_SOPT2_SDHCSRC_MASK)
+#define SIM_SOPT2_SDHCSRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_SDHCSRC_SHIFT)) & SIM_SOPT2_SDHCSRC_MASK)
 
 /*! @name SOPT4 - System Options Register 4 */
 #define SIM_SOPT4_FTM0FLT0_MASK                  (0x1U)
 #define SIM_SOPT4_FTM0FLT0_SHIFT                 (0U)
-#define SIM_SOPT4_FTM0FLT0(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)
+#define SIM_SOPT4_FTM0FLT0_SET(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)
+#define SIM_SOPT4_FTM0FLT0 SIM_SOPT4_FTM0FLT0_MASK
 #define SIM_SOPT4_FTM0FLT1_MASK                  (0x2U)
 #define SIM_SOPT4_FTM0FLT1_SHIFT                 (1U)
-#define SIM_SOPT4_FTM0FLT1(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)
+#define SIM_SOPT4_FTM0FLT1_SET(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)
+#define SIM_SOPT4_FTM0FLT1 SIM_SOPT4_FTM0FLT1_MASK
 #define SIM_SOPT4_FTM0FLT2_MASK                  (0x4U)
 #define SIM_SOPT4_FTM0FLT2_SHIFT                 (2U)
-#define SIM_SOPT4_FTM0FLT2(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT2_SHIFT)) & SIM_SOPT4_FTM0FLT2_MASK)
+#define SIM_SOPT4_FTM0FLT2_SET(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT2_SHIFT)) & SIM_SOPT4_FTM0FLT2_MASK)
+#define SIM_SOPT4_FTM0FLT2 SIM_SOPT4_FTM0FLT2_MASK
 #define SIM_SOPT4_FTM0FLT3_MASK                  (0x8U)
 #define SIM_SOPT4_FTM0FLT3_SHIFT                 (3U)
-#define SIM_SOPT4_FTM0FLT3(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT3_SHIFT)) & SIM_SOPT4_FTM0FLT3_MASK)
+#define SIM_SOPT4_FTM0FLT3_SET(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT3_SHIFT)) & SIM_SOPT4_FTM0FLT3_MASK)
+#define SIM_SOPT4_FTM0FLT3 SIM_SOPT4_FTM0FLT3_MASK
 #define SIM_SOPT4_FTM1FLT0_MASK                  (0x10U)
 #define SIM_SOPT4_FTM1FLT0_SHIFT                 (4U)
-#define SIM_SOPT4_FTM1FLT0(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)
+#define SIM_SOPT4_FTM1FLT0_SET(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)
+#define SIM_SOPT4_FTM1FLT0 SIM_SOPT4_FTM1FLT0_MASK
 #define SIM_SOPT4_FTM2FLT0_MASK                  (0x100U)
 #define SIM_SOPT4_FTM2FLT0_SHIFT                 (8U)
-#define SIM_SOPT4_FTM2FLT0(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK)
+#define SIM_SOPT4_FTM2FLT0_SET(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK)
+#define SIM_SOPT4_FTM2FLT0 SIM_SOPT4_FTM2FLT0_MASK
 #define SIM_SOPT4_FTM3FLT0_MASK                  (0x1000U)
 #define SIM_SOPT4_FTM3FLT0_SHIFT                 (12U)
-#define SIM_SOPT4_FTM3FLT0(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3FLT0_SHIFT)) & SIM_SOPT4_FTM3FLT0_MASK)
+#define SIM_SOPT4_FTM3FLT0_SET(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3FLT0_SHIFT)) & SIM_SOPT4_FTM3FLT0_MASK)
+#define SIM_SOPT4_FTM3FLT0 SIM_SOPT4_FTM3FLT0_MASK
 #define SIM_SOPT4_FTM1CH0SRC_MASK                (0xC0000U)
 #define SIM_SOPT4_FTM1CH0SRC_SHIFT               (18U)
-#define SIM_SOPT4_FTM1CH0SRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK)
+#define SIM_SOPT4_FTM1CH0SRC_SET(x)              (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK)
+#define SIM_SOPT4_FTM1CH0SRC SIM_SOPT4_FTM1CH0SRC_MASK
 #define SIM_SOPT4_FTM2CH0SRC_MASK                (0x300000U)
 #define SIM_SOPT4_FTM2CH0SRC_SHIFT               (20U)
-#define SIM_SOPT4_FTM2CH0SRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK)
+#define SIM_SOPT4_FTM2CH0SRC_SET(x)              (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK)
+#define SIM_SOPT4_FTM2CH0SRC SIM_SOPT4_FTM2CH0SRC_MASK
 #define SIM_SOPT4_FTM2CH1SRC_MASK                (0x400000U)
 #define SIM_SOPT4_FTM2CH1SRC_SHIFT               (22U)
-#define SIM_SOPT4_FTM2CH1SRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH1SRC_SHIFT)) & SIM_SOPT4_FTM2CH1SRC_MASK)
+#define SIM_SOPT4_FTM2CH1SRC_SET(x)              (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH1SRC_SHIFT)) & SIM_SOPT4_FTM2CH1SRC_MASK)
+#define SIM_SOPT4_FTM2CH1SRC SIM_SOPT4_FTM2CH1SRC_MASK
 #define SIM_SOPT4_FTM0CLKSEL_MASK                (0x1000000U)
 #define SIM_SOPT4_FTM0CLKSEL_SHIFT               (24U)
-#define SIM_SOPT4_FTM0CLKSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK)
+#define SIM_SOPT4_FTM0CLKSEL_SET(x)              (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK)
+#define SIM_SOPT4_FTM0CLKSEL SIM_SOPT4_FTM0CLKSEL_MASK
 #define SIM_SOPT4_FTM1CLKSEL_MASK                (0x2000000U)
 #define SIM_SOPT4_FTM1CLKSEL_SHIFT               (25U)
-#define SIM_SOPT4_FTM1CLKSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK)
+#define SIM_SOPT4_FTM1CLKSEL_SET(x)              (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK)
+#define SIM_SOPT4_FTM1CLKSEL SIM_SOPT4_FTM1CLKSEL_MASK
 #define SIM_SOPT4_FTM2CLKSEL_MASK                (0x4000000U)
 #define SIM_SOPT4_FTM2CLKSEL_SHIFT               (26U)
-#define SIM_SOPT4_FTM2CLKSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK)
+#define SIM_SOPT4_FTM2CLKSEL_SET(x)              (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK)
+#define SIM_SOPT4_FTM2CLKSEL SIM_SOPT4_FTM2CLKSEL_MASK
 #define SIM_SOPT4_FTM3CLKSEL_MASK                (0x8000000U)
 #define SIM_SOPT4_FTM3CLKSEL_SHIFT               (27U)
-#define SIM_SOPT4_FTM3CLKSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3CLKSEL_SHIFT)) & SIM_SOPT4_FTM3CLKSEL_MASK)
+#define SIM_SOPT4_FTM3CLKSEL_SET(x)              (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3CLKSEL_SHIFT)) & SIM_SOPT4_FTM3CLKSEL_MASK)
+#define SIM_SOPT4_FTM3CLKSEL SIM_SOPT4_FTM3CLKSEL_MASK
 #define SIM_SOPT4_FTM0TRG0SRC_MASK               (0x10000000U)
 #define SIM_SOPT4_FTM0TRG0SRC_SHIFT              (28U)
-#define SIM_SOPT4_FTM0TRG0SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)
+#define SIM_SOPT4_FTM0TRG0SRC_SET(x)             (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)
+#define SIM_SOPT4_FTM0TRG0SRC SIM_SOPT4_FTM0TRG0SRC_MASK
 #define SIM_SOPT4_FTM0TRG1SRC_MASK               (0x20000000U)
 #define SIM_SOPT4_FTM0TRG1SRC_SHIFT              (29U)
-#define SIM_SOPT4_FTM0TRG1SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK)
+#define SIM_SOPT4_FTM0TRG1SRC_SET(x)             (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK)
+#define SIM_SOPT4_FTM0TRG1SRC SIM_SOPT4_FTM0TRG1SRC_MASK
 #define SIM_SOPT4_FTM3TRG0SRC_MASK               (0x40000000U)
 #define SIM_SOPT4_FTM3TRG0SRC_SHIFT              (30U)
-#define SIM_SOPT4_FTM3TRG0SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG0SRC_SHIFT)) & SIM_SOPT4_FTM3TRG0SRC_MASK)
+#define SIM_SOPT4_FTM3TRG0SRC_SET(x)             (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG0SRC_SHIFT)) & SIM_SOPT4_FTM3TRG0SRC_MASK)
+#define SIM_SOPT4_FTM3TRG0SRC SIM_SOPT4_FTM3TRG0SRC_MASK
 #define SIM_SOPT4_FTM3TRG1SRC_MASK               (0x80000000U)
 #define SIM_SOPT4_FTM3TRG1SRC_SHIFT              (31U)
-#define SIM_SOPT4_FTM3TRG1SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG1SRC_SHIFT)) & SIM_SOPT4_FTM3TRG1SRC_MASK)
+#define SIM_SOPT4_FTM3TRG1SRC_SET(x)             (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG1SRC_SHIFT)) & SIM_SOPT4_FTM3TRG1SRC_MASK)
+#define SIM_SOPT4_FTM3TRG1SRC SIM_SOPT4_FTM3TRG1SRC_MASK
 
 /*! @name SOPT5 - System Options Register 5 */
 #define SIM_SOPT5_UART0TXSRC_MASK                (0x3U)
 #define SIM_SOPT5_UART0TXSRC_SHIFT               (0U)
-#define SIM_SOPT5_UART0TXSRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
+#define SIM_SOPT5_UART0TXSRC_SET(x)              (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
+#define SIM_SOPT5_UART0TXSRC SIM_SOPT5_UART0TXSRC_MASK
 #define SIM_SOPT5_UART0RXSRC_MASK                (0xCU)
 #define SIM_SOPT5_UART0RXSRC_SHIFT               (2U)
-#define SIM_SOPT5_UART0RXSRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
+#define SIM_SOPT5_UART0RXSRC_SET(x)              (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
+#define SIM_SOPT5_UART0RXSRC SIM_SOPT5_UART0RXSRC_MASK
 #define SIM_SOPT5_UART1TXSRC_MASK                (0x30U)
 #define SIM_SOPT5_UART1TXSRC_SHIFT               (4U)
-#define SIM_SOPT5_UART1TXSRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
+#define SIM_SOPT5_UART1TXSRC_SET(x)              (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
+#define SIM_SOPT5_UART1TXSRC SIM_SOPT5_UART1TXSRC_MASK
 #define SIM_SOPT5_UART1RXSRC_MASK                (0xC0U)
 #define SIM_SOPT5_UART1RXSRC_SHIFT               (6U)
-#define SIM_SOPT5_UART1RXSRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
+#define SIM_SOPT5_UART1RXSRC_SET(x)              (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
+#define SIM_SOPT5_UART1RXSRC SIM_SOPT5_UART1RXSRC_MASK
 #define SIM_SOPT5_LPUART0TXSRC_MASK              (0x30000U)
 #define SIM_SOPT5_LPUART0TXSRC_SHIFT             (16U)
-#define SIM_SOPT5_LPUART0TXSRC(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0TXSRC_SHIFT)) & SIM_SOPT5_LPUART0TXSRC_MASK)
+#define SIM_SOPT5_LPUART0TXSRC_SET(x)            (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0TXSRC_SHIFT)) & SIM_SOPT5_LPUART0TXSRC_MASK)
+#define SIM_SOPT5_LPUART0TXSRC SIM_SOPT5_LPUART0TXSRC_MASK
 #define SIM_SOPT5_LPUART0RXSRC_MASK              (0xC0000U)
 #define SIM_SOPT5_LPUART0RXSRC_SHIFT             (18U)
-#define SIM_SOPT5_LPUART0RXSRC(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0RXSRC_SHIFT)) & SIM_SOPT5_LPUART0RXSRC_MASK)
+#define SIM_SOPT5_LPUART0RXSRC_SET(x)            (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_LPUART0RXSRC_SHIFT)) & SIM_SOPT5_LPUART0RXSRC_MASK)
+#define SIM_SOPT5_LPUART0RXSRC SIM_SOPT5_LPUART0RXSRC_MASK
 
 /*! @name SOPT7 - System Options Register 7 */
 #define SIM_SOPT7_ADC0TRGSEL_MASK                (0xFU)
 #define SIM_SOPT7_ADC0TRGSEL_SHIFT               (0U)
-#define SIM_SOPT7_ADC0TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0TRGSEL_SET(x)              (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
+#define SIM_SOPT7_ADC0TRGSEL SIM_SOPT7_ADC0TRGSEL_MASK
 #define SIM_SOPT7_ADC0PRETRGSEL_MASK             (0x10U)
 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT            (4U)
-#define SIM_SOPT7_ADC0PRETRGSEL(x)               (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL_SET(x)           (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
+#define SIM_SOPT7_ADC0PRETRGSEL SIM_SOPT7_ADC0PRETRGSEL_MASK
 #define SIM_SOPT7_ADC0ALTTRGEN_MASK              (0x80U)
 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT             (7U)
-#define SIM_SOPT7_ADC0ALTTRGEN(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
+#define SIM_SOPT7_ADC0ALTTRGEN_SET(x)            (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
+#define SIM_SOPT7_ADC0ALTTRGEN SIM_SOPT7_ADC0ALTTRGEN_MASK
 #define SIM_SOPT7_ADC1TRGSEL_MASK                (0xF00U)
 #define SIM_SOPT7_ADC1TRGSEL_SHIFT               (8U)
-#define SIM_SOPT7_ADC1TRGSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1TRGSEL_SHIFT)) & SIM_SOPT7_ADC1TRGSEL_MASK)
+#define SIM_SOPT7_ADC1TRGSEL_SET(x)              (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1TRGSEL_SHIFT)) & SIM_SOPT7_ADC1TRGSEL_MASK)
+#define SIM_SOPT7_ADC1TRGSEL SIM_SOPT7_ADC1TRGSEL_MASK
 #define SIM_SOPT7_ADC1PRETRGSEL_MASK             (0x1000U)
 #define SIM_SOPT7_ADC1PRETRGSEL_SHIFT            (12U)
-#define SIM_SOPT7_ADC1PRETRGSEL(x)               (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC1PRETRGSEL_MASK)
+#define SIM_SOPT7_ADC1PRETRGSEL_SET(x)           (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC1PRETRGSEL_MASK)
+#define SIM_SOPT7_ADC1PRETRGSEL SIM_SOPT7_ADC1PRETRGSEL_MASK
 #define SIM_SOPT7_ADC1ALTTRGEN_MASK              (0x8000U)
 #define SIM_SOPT7_ADC1ALTTRGEN_SHIFT             (15U)
-#define SIM_SOPT7_ADC1ALTTRGEN(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC1ALTTRGEN_MASK)
+#define SIM_SOPT7_ADC1ALTTRGEN_SET(x)            (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC1ALTTRGEN_MASK)
+#define SIM_SOPT7_ADC1ALTTRGEN SIM_SOPT7_ADC1ALTTRGEN_MASK
 
 /*! @name SOPT8 - System Options Register 8 */
 #define SIM_SOPT8_FTM0SYNCBIT_MASK               (0x1U)
 #define SIM_SOPT8_FTM0SYNCBIT_SHIFT              (0U)
-#define SIM_SOPT8_FTM0SYNCBIT(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0SYNCBIT_SHIFT)) & SIM_SOPT8_FTM0SYNCBIT_MASK)
+#define SIM_SOPT8_FTM0SYNCBIT_SET(x)             (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0SYNCBIT_SHIFT)) & SIM_SOPT8_FTM0SYNCBIT_MASK)
+#define SIM_SOPT8_FTM0SYNCBIT SIM_SOPT8_FTM0SYNCBIT_MASK
 #define SIM_SOPT8_FTM1SYNCBIT_MASK               (0x2U)
 #define SIM_SOPT8_FTM1SYNCBIT_SHIFT              (1U)
-#define SIM_SOPT8_FTM1SYNCBIT(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM1SYNCBIT_SHIFT)) & SIM_SOPT8_FTM1SYNCBIT_MASK)
+#define SIM_SOPT8_FTM1SYNCBIT_SET(x)             (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM1SYNCBIT_SHIFT)) & SIM_SOPT8_FTM1SYNCBIT_MASK)
+#define SIM_SOPT8_FTM1SYNCBIT SIM_SOPT8_FTM1SYNCBIT_MASK
 #define SIM_SOPT8_FTM2SYNCBIT_MASK               (0x4U)
 #define SIM_SOPT8_FTM2SYNCBIT_SHIFT              (2U)
-#define SIM_SOPT8_FTM2SYNCBIT(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM2SYNCBIT_SHIFT)) & SIM_SOPT8_FTM2SYNCBIT_MASK)
+#define SIM_SOPT8_FTM2SYNCBIT_SET(x)             (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM2SYNCBIT_SHIFT)) & SIM_SOPT8_FTM2SYNCBIT_MASK)
+#define SIM_SOPT8_FTM2SYNCBIT SIM_SOPT8_FTM2SYNCBIT_MASK
 #define SIM_SOPT8_FTM3SYNCBIT_MASK               (0x8U)
 #define SIM_SOPT8_FTM3SYNCBIT_SHIFT              (3U)
-#define SIM_SOPT8_FTM3SYNCBIT(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3SYNCBIT_SHIFT)) & SIM_SOPT8_FTM3SYNCBIT_MASK)
+#define SIM_SOPT8_FTM3SYNCBIT_SET(x)             (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3SYNCBIT_SHIFT)) & SIM_SOPT8_FTM3SYNCBIT_MASK)
+#define SIM_SOPT8_FTM3SYNCBIT SIM_SOPT8_FTM3SYNCBIT_MASK
 #define SIM_SOPT8_FTM0OCH0SRC_MASK               (0x10000U)
 #define SIM_SOPT8_FTM0OCH0SRC_SHIFT              (16U)
-#define SIM_SOPT8_FTM0OCH0SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH0SRC_SHIFT)) & SIM_SOPT8_FTM0OCH0SRC_MASK)
+#define SIM_SOPT8_FTM0OCH0SRC_SET(x)             (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH0SRC_SHIFT)) & SIM_SOPT8_FTM0OCH0SRC_MASK)
+#define SIM_SOPT8_FTM0OCH0SRC SIM_SOPT8_FTM0OCH0SRC_MASK
 #define SIM_SOPT8_FTM0OCH1SRC_MASK               (0x20000U)
 #define SIM_SOPT8_FTM0OCH1SRC_SHIFT              (17U)
-#define SIM_SOPT8_FTM0OCH1SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH1SRC_SHIFT)) & SIM_SOPT8_FTM0OCH1SRC_MASK)
+#define SIM_SOPT8_FTM0OCH1SRC_SET(x)             (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH1SRC_SHIFT)) & SIM_SOPT8_FTM0OCH1SRC_MASK)
+#define SIM_SOPT8_FTM0OCH1SRC SIM_SOPT8_FTM0OCH1SRC_MASK
 #define SIM_SOPT8_FTM0OCH2SRC_MASK               (0x40000U)
 #define SIM_SOPT8_FTM0OCH2SRC_SHIFT              (18U)
-#define SIM_SOPT8_FTM0OCH2SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH2SRC_SHIFT)) & SIM_SOPT8_FTM0OCH2SRC_MASK)
+#define SIM_SOPT8_FTM0OCH2SRC_SET(x)             (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH2SRC_SHIFT)) & SIM_SOPT8_FTM0OCH2SRC_MASK)
+#define SIM_SOPT8_FTM0OCH2SRC SIM_SOPT8_FTM0OCH2SRC_MASK
 #define SIM_SOPT8_FTM0OCH3SRC_MASK               (0x80000U)
 #define SIM_SOPT8_FTM0OCH3SRC_SHIFT              (19U)
-#define SIM_SOPT8_FTM0OCH3SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH3SRC_SHIFT)) & SIM_SOPT8_FTM0OCH3SRC_MASK)
+#define SIM_SOPT8_FTM0OCH3SRC_SET(x)             (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH3SRC_SHIFT)) & SIM_SOPT8_FTM0OCH3SRC_MASK)
+#define SIM_SOPT8_FTM0OCH3SRC SIM_SOPT8_FTM0OCH3SRC_MASK
 #define SIM_SOPT8_FTM0OCH4SRC_MASK               (0x100000U)
 #define SIM_SOPT8_FTM0OCH4SRC_SHIFT              (20U)
-#define SIM_SOPT8_FTM0OCH4SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH4SRC_SHIFT)) & SIM_SOPT8_FTM0OCH4SRC_MASK)
+#define SIM_SOPT8_FTM0OCH4SRC_SET(x)             (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH4SRC_SHIFT)) & SIM_SOPT8_FTM0OCH4SRC_MASK)
+#define SIM_SOPT8_FTM0OCH4SRC SIM_SOPT8_FTM0OCH4SRC_MASK
 #define SIM_SOPT8_FTM0OCH5SRC_MASK               (0x200000U)
 #define SIM_SOPT8_FTM0OCH5SRC_SHIFT              (21U)
-#define SIM_SOPT8_FTM0OCH5SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH5SRC_SHIFT)) & SIM_SOPT8_FTM0OCH5SRC_MASK)
+#define SIM_SOPT8_FTM0OCH5SRC_SET(x)             (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH5SRC_SHIFT)) & SIM_SOPT8_FTM0OCH5SRC_MASK)
+#define SIM_SOPT8_FTM0OCH5SRC SIM_SOPT8_FTM0OCH5SRC_MASK
 #define SIM_SOPT8_FTM0OCH6SRC_MASK               (0x400000U)
 #define SIM_SOPT8_FTM0OCH6SRC_SHIFT              (22U)
-#define SIM_SOPT8_FTM0OCH6SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH6SRC_SHIFT)) & SIM_SOPT8_FTM0OCH6SRC_MASK)
+#define SIM_SOPT8_FTM0OCH6SRC_SET(x)             (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH6SRC_SHIFT)) & SIM_SOPT8_FTM0OCH6SRC_MASK)
+#define SIM_SOPT8_FTM0OCH6SRC SIM_SOPT8_FTM0OCH6SRC_MASK
 #define SIM_SOPT8_FTM0OCH7SRC_MASK               (0x800000U)
 #define SIM_SOPT8_FTM0OCH7SRC_SHIFT              (23U)
-#define SIM_SOPT8_FTM0OCH7SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH7SRC_SHIFT)) & SIM_SOPT8_FTM0OCH7SRC_MASK)
+#define SIM_SOPT8_FTM0OCH7SRC_SET(x)             (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM0OCH7SRC_SHIFT)) & SIM_SOPT8_FTM0OCH7SRC_MASK)
+#define SIM_SOPT8_FTM0OCH7SRC SIM_SOPT8_FTM0OCH7SRC_MASK
 #define SIM_SOPT8_FTM3OCH0SRC_MASK               (0x1000000U)
 #define SIM_SOPT8_FTM3OCH0SRC_SHIFT              (24U)
-#define SIM_SOPT8_FTM3OCH0SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH0SRC_SHIFT)) & SIM_SOPT8_FTM3OCH0SRC_MASK)
+#define SIM_SOPT8_FTM3OCH0SRC_SET(x)             (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH0SRC_SHIFT)) & SIM_SOPT8_FTM3OCH0SRC_MASK)
+#define SIM_SOPT8_FTM3OCH0SRC SIM_SOPT8_FTM3OCH0SRC_MASK
 #define SIM_SOPT8_FTM3OCH1SRC_MASK               (0x2000000U)
 #define SIM_SOPT8_FTM3OCH1SRC_SHIFT              (25U)
-#define SIM_SOPT8_FTM3OCH1SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH1SRC_SHIFT)) & SIM_SOPT8_FTM3OCH1SRC_MASK)
+#define SIM_SOPT8_FTM3OCH1SRC_SET(x)             (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH1SRC_SHIFT)) & SIM_SOPT8_FTM3OCH1SRC_MASK)
+#define SIM_SOPT8_FTM3OCH1SRC SIM_SOPT8_FTM3OCH1SRC_MASK
 #define SIM_SOPT8_FTM3OCH2SRC_MASK               (0x4000000U)
 #define SIM_SOPT8_FTM3OCH2SRC_SHIFT              (26U)
-#define SIM_SOPT8_FTM3OCH2SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH2SRC_SHIFT)) & SIM_SOPT8_FTM3OCH2SRC_MASK)
+#define SIM_SOPT8_FTM3OCH2SRC_SET(x)             (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH2SRC_SHIFT)) & SIM_SOPT8_FTM3OCH2SRC_MASK)
+#define SIM_SOPT8_FTM3OCH2SRC SIM_SOPT8_FTM3OCH2SRC_MASK
 #define SIM_SOPT8_FTM3OCH3SRC_MASK               (0x8000000U)
 #define SIM_SOPT8_FTM3OCH3SRC_SHIFT              (27U)
-#define SIM_SOPT8_FTM3OCH3SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH3SRC_SHIFT)) & SIM_SOPT8_FTM3OCH3SRC_MASK)
+#define SIM_SOPT8_FTM3OCH3SRC_SET(x)             (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH3SRC_SHIFT)) & SIM_SOPT8_FTM3OCH3SRC_MASK)
+#define SIM_SOPT8_FTM3OCH3SRC SIM_SOPT8_FTM3OCH3SRC_MASK
 #define SIM_SOPT8_FTM3OCH4SRC_MASK               (0x10000000U)
 #define SIM_SOPT8_FTM3OCH4SRC_SHIFT              (28U)
-#define SIM_SOPT8_FTM3OCH4SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH4SRC_SHIFT)) & SIM_SOPT8_FTM3OCH4SRC_MASK)
+#define SIM_SOPT8_FTM3OCH4SRC_SET(x)             (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH4SRC_SHIFT)) & SIM_SOPT8_FTM3OCH4SRC_MASK)
+#define SIM_SOPT8_FTM3OCH4SRC SIM_SOPT8_FTM3OCH4SRC_MASK
 #define SIM_SOPT8_FTM3OCH5SRC_MASK               (0x20000000U)
 #define SIM_SOPT8_FTM3OCH5SRC_SHIFT              (29U)
-#define SIM_SOPT8_FTM3OCH5SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH5SRC_SHIFT)) & SIM_SOPT8_FTM3OCH5SRC_MASK)
+#define SIM_SOPT8_FTM3OCH5SRC_SET(x)             (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH5SRC_SHIFT)) & SIM_SOPT8_FTM3OCH5SRC_MASK)
+#define SIM_SOPT8_FTM3OCH5SRC SIM_SOPT8_FTM3OCH5SRC_MASK
 #define SIM_SOPT8_FTM3OCH6SRC_MASK               (0x40000000U)
 #define SIM_SOPT8_FTM3OCH6SRC_SHIFT              (30U)
-#define SIM_SOPT8_FTM3OCH6SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH6SRC_SHIFT)) & SIM_SOPT8_FTM3OCH6SRC_MASK)
+#define SIM_SOPT8_FTM3OCH6SRC_SET(x)             (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH6SRC_SHIFT)) & SIM_SOPT8_FTM3OCH6SRC_MASK)
+#define SIM_SOPT8_FTM3OCH6SRC SIM_SOPT8_FTM3OCH6SRC_MASK
 #define SIM_SOPT8_FTM3OCH7SRC_MASK               (0x80000000U)
 #define SIM_SOPT8_FTM3OCH7SRC_SHIFT              (31U)
-#define SIM_SOPT8_FTM3OCH7SRC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH7SRC_SHIFT)) & SIM_SOPT8_FTM3OCH7SRC_MASK)
+#define SIM_SOPT8_FTM3OCH7SRC_SET(x)             (((uint32_t)(((uint32_t)(x)) << SIM_SOPT8_FTM3OCH7SRC_SHIFT)) & SIM_SOPT8_FTM3OCH7SRC_MASK)
+#define SIM_SOPT8_FTM3OCH7SRC SIM_SOPT8_FTM3OCH7SRC_MASK
 
 /*! @name SOPT9 - System Options Register 9 */
 #define SIM_SOPT9_TPM1CH0SRC_MASK                (0xC0000U)
 #define SIM_SOPT9_TPM1CH0SRC_SHIFT               (18U)
-#define SIM_SOPT9_TPM1CH0SRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM1CH0SRC_SHIFT)) & SIM_SOPT9_TPM1CH0SRC_MASK)
+#define SIM_SOPT9_TPM1CH0SRC_SET(x)              (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM1CH0SRC_SHIFT)) & SIM_SOPT9_TPM1CH0SRC_MASK)
+#define SIM_SOPT9_TPM1CH0SRC SIM_SOPT9_TPM1CH0SRC_MASK
 #define SIM_SOPT9_TPM2CH0SRC_MASK                (0x300000U)
 #define SIM_SOPT9_TPM2CH0SRC_SHIFT               (20U)
-#define SIM_SOPT9_TPM2CH0SRC(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM2CH0SRC_SHIFT)) & SIM_SOPT9_TPM2CH0SRC_MASK)
+#define SIM_SOPT9_TPM2CH0SRC_SET(x)              (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM2CH0SRC_SHIFT)) & SIM_SOPT9_TPM2CH0SRC_MASK)
+#define SIM_SOPT9_TPM2CH0SRC SIM_SOPT9_TPM2CH0SRC_MASK
 #define SIM_SOPT9_TPM1CLKSEL_MASK                (0x2000000U)
 #define SIM_SOPT9_TPM1CLKSEL_SHIFT               (25U)
-#define SIM_SOPT9_TPM1CLKSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM1CLKSEL_SHIFT)) & SIM_SOPT9_TPM1CLKSEL_MASK)
+#define SIM_SOPT9_TPM1CLKSEL_SET(x)              (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM1CLKSEL_SHIFT)) & SIM_SOPT9_TPM1CLKSEL_MASK)
+#define SIM_SOPT9_TPM1CLKSEL SIM_SOPT9_TPM1CLKSEL_MASK
 #define SIM_SOPT9_TPM2CLKSEL_MASK                (0x4000000U)
 #define SIM_SOPT9_TPM2CLKSEL_SHIFT               (26U)
-#define SIM_SOPT9_TPM2CLKSEL(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM2CLKSEL_SHIFT)) & SIM_SOPT9_TPM2CLKSEL_MASK)
+#define SIM_SOPT9_TPM2CLKSEL_SET(x)              (((uint32_t)(((uint32_t)(x)) << SIM_SOPT9_TPM2CLKSEL_SHIFT)) & SIM_SOPT9_TPM2CLKSEL_MASK)
+#define SIM_SOPT9_TPM2CLKSEL SIM_SOPT9_TPM2CLKSEL_MASK
 
 /*! @name SDID - System Device Identification Register */
 #define SIM_SDID_PINID_MASK                      (0xFU)
 #define SIM_SDID_PINID_SHIFT                     (0U)
-#define SIM_SDID_PINID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
+#define SIM_SDID_PINID_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
+#define SIM_SDID_PINID SIM_SDID_PINID_MASK
 #define SIM_SDID_FAMID_MASK                      (0x70U)
 #define SIM_SDID_FAMID_SHIFT                     (4U)
-#define SIM_SDID_FAMID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
+#define SIM_SDID_FAMID_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
+#define SIM_SDID_FAMID SIM_SDID_FAMID_MASK
 #define SIM_SDID_DIEID_MASK                      (0xF80U)
 #define SIM_SDID_DIEID_SHIFT                     (7U)
-#define SIM_SDID_DIEID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
+#define SIM_SDID_DIEID_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
+#define SIM_SDID_DIEID SIM_SDID_DIEID_MASK
 #define SIM_SDID_REVID_MASK                      (0xF000U)
 #define SIM_SDID_REVID_SHIFT                     (12U)
-#define SIM_SDID_REVID(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
+#define SIM_SDID_REVID_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
+#define SIM_SDID_REVID SIM_SDID_REVID_MASK
 #define SIM_SDID_SERIESID_MASK                   (0xF00000U)
 #define SIM_SDID_SERIESID_SHIFT                  (20U)
-#define SIM_SDID_SERIESID(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
+#define SIM_SDID_SERIESID_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
+#define SIM_SDID_SERIESID SIM_SDID_SERIESID_MASK
 #define SIM_SDID_SUBFAMID_MASK                   (0xF000000U)
 #define SIM_SDID_SUBFAMID_SHIFT                  (24U)
-#define SIM_SDID_SUBFAMID(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
+#define SIM_SDID_SUBFAMID_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
+#define SIM_SDID_SUBFAMID SIM_SDID_SUBFAMID_MASK
 #define SIM_SDID_FAMILYID_MASK                   (0xF0000000U)
 #define SIM_SDID_FAMILYID_SHIFT                  (28U)
-#define SIM_SDID_FAMILYID(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK)
+#define SIM_SDID_FAMILYID_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK)
+#define SIM_SDID_FAMILYID SIM_SDID_FAMILYID_MASK
 
 /*! @name SCGC1 - System Clock Gating Control Register 1 */
 #define SIM_SCGC1_I2C2_MASK                      (0x40U)
 #define SIM_SCGC1_I2C2_SHIFT                     (6U)
-#define SIM_SCGC1_I2C2(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C2_SHIFT)) & SIM_SCGC1_I2C2_MASK)
+#define SIM_SCGC1_I2C2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C2_SHIFT)) & SIM_SCGC1_I2C2_MASK)
+#define SIM_SCGC1_I2C2 SIM_SCGC1_I2C2_MASK
 #define SIM_SCGC1_I2C3_MASK                      (0x80U)
 #define SIM_SCGC1_I2C3_SHIFT                     (7U)
-#define SIM_SCGC1_I2C3(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C3_SHIFT)) & SIM_SCGC1_I2C3_MASK)
+#define SIM_SCGC1_I2C3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C3_SHIFT)) & SIM_SCGC1_I2C3_MASK)
+#define SIM_SCGC1_I2C3 SIM_SCGC1_I2C3_MASK
 #define SIM_SCGC1_UART4_MASK                     (0x400U)
 #define SIM_SCGC1_UART4_SHIFT                    (10U)
-#define SIM_SCGC1_UART4(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART4_SHIFT)) & SIM_SCGC1_UART4_MASK)
+#define SIM_SCGC1_UART4_SET(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART4_SHIFT)) & SIM_SCGC1_UART4_MASK)
+#define SIM_SCGC1_UART4 SIM_SCGC1_UART4_MASK
 
 /*! @name SCGC2 - System Clock Gating Control Register 2 */
 #define SIM_SCGC2_ENET_MASK                      (0x1U)
 #define SIM_SCGC2_ENET_SHIFT                     (0U)
-#define SIM_SCGC2_ENET(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_ENET_SHIFT)) & SIM_SCGC2_ENET_MASK)
+#define SIM_SCGC2_ENET_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_ENET_SHIFT)) & SIM_SCGC2_ENET_MASK)
+#define SIM_SCGC2_ENET SIM_SCGC2_ENET_MASK
 #define SIM_SCGC2_LPUART0_MASK                   (0x10U)
 #define SIM_SCGC2_LPUART0_SHIFT                  (4U)
-#define SIM_SCGC2_LPUART0(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_LPUART0_SHIFT)) & SIM_SCGC2_LPUART0_MASK)
+#define SIM_SCGC2_LPUART0_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_LPUART0_SHIFT)) & SIM_SCGC2_LPUART0_MASK)
+#define SIM_SCGC2_LPUART0 SIM_SCGC2_LPUART0_MASK
 #define SIM_SCGC2_TPM1_MASK                      (0x200U)
 #define SIM_SCGC2_TPM1_SHIFT                     (9U)
-#define SIM_SCGC2_TPM1(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_TPM1_SHIFT)) & SIM_SCGC2_TPM1_MASK)
+#define SIM_SCGC2_TPM1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_TPM1_SHIFT)) & SIM_SCGC2_TPM1_MASK)
+#define SIM_SCGC2_TPM1 SIM_SCGC2_TPM1_MASK
 #define SIM_SCGC2_TPM2_MASK                      (0x400U)
 #define SIM_SCGC2_TPM2_SHIFT                     (10U)
-#define SIM_SCGC2_TPM2(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_TPM2_SHIFT)) & SIM_SCGC2_TPM2_MASK)
+#define SIM_SCGC2_TPM2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_TPM2_SHIFT)) & SIM_SCGC2_TPM2_MASK)
+#define SIM_SCGC2_TPM2 SIM_SCGC2_TPM2_MASK
 #define SIM_SCGC2_DAC0_MASK                      (0x1000U)
 #define SIM_SCGC2_DAC0_SHIFT                     (12U)
-#define SIM_SCGC2_DAC0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC0_SHIFT)) & SIM_SCGC2_DAC0_MASK)
+#define SIM_SCGC2_DAC0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC0_SHIFT)) & SIM_SCGC2_DAC0_MASK)
+#define SIM_SCGC2_DAC0 SIM_SCGC2_DAC0_MASK
 #define SIM_SCGC2_DAC1_MASK                      (0x2000U)
 #define SIM_SCGC2_DAC1_SHIFT                     (13U)
-#define SIM_SCGC2_DAC1(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC1_SHIFT)) & SIM_SCGC2_DAC1_MASK)
+#define SIM_SCGC2_DAC1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC1_SHIFT)) & SIM_SCGC2_DAC1_MASK)
+#define SIM_SCGC2_DAC1 SIM_SCGC2_DAC1_MASK
 
 /*! @name SCGC3 - System Clock Gating Control Register 3 */
 #define SIM_SCGC3_RNGA_MASK                      (0x1U)
 #define SIM_SCGC3_RNGA_SHIFT                     (0U)
-#define SIM_SCGC3_RNGA(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_RNGA_SHIFT)) & SIM_SCGC3_RNGA_MASK)
+#define SIM_SCGC3_RNGA_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_RNGA_SHIFT)) & SIM_SCGC3_RNGA_MASK)
+#define SIM_SCGC3_RNGA SIM_SCGC3_RNGA_MASK
 #define SIM_SCGC3_USBHS_MASK                     (0x2U)
 #define SIM_SCGC3_USBHS_SHIFT                    (1U)
-#define SIM_SCGC3_USBHS(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHS_SHIFT)) & SIM_SCGC3_USBHS_MASK)
+#define SIM_SCGC3_USBHS_SET(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHS_SHIFT)) & SIM_SCGC3_USBHS_MASK)
+#define SIM_SCGC3_USBHS SIM_SCGC3_USBHS_MASK
 #define SIM_SCGC3_USBHSPHY_MASK                  (0x4U)
 #define SIM_SCGC3_USBHSPHY_SHIFT                 (2U)
 #define SIM_SCGC3_USBHSPHY_SET(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHSPHY_SHIFT)) & SIM_SCGC3_USBHSPHY_MASK)
 #define SIM_SCGC3_USBHSPHY                       SIM_SCGC3_USBHSPHY_SET(1)
 #define SIM_SCGC3_USBHSDCD_MASK                  (0x8U)
 #define SIM_SCGC3_USBHSDCD_SHIFT                 (3U)
-#define SIM_SCGC3_USBHSDCD(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHSDCD_SHIFT)) & SIM_SCGC3_USBHSDCD_MASK)
+#define SIM_SCGC3_USBHSDCD_SET(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_USBHSDCD_SHIFT)) & SIM_SCGC3_USBHSDCD_MASK)
+#define SIM_SCGC3_USBHSDCD SIM_SCGC3_USBHSDCD_MASK
 #define SIM_SCGC3_FLEXCAN1_MASK                  (0x10U)
 #define SIM_SCGC3_FLEXCAN1_SHIFT                 (4U)
-#define SIM_SCGC3_FLEXCAN1(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FLEXCAN1_SHIFT)) & SIM_SCGC3_FLEXCAN1_MASK)
+#define SIM_SCGC3_FLEXCAN1_SET(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FLEXCAN1_SHIFT)) & SIM_SCGC3_FLEXCAN1_MASK)
+#define SIM_SCGC3_FLEXCAN1 SIM_SCGC3_FLEXCAN1_MASK
 #define SIM_SCGC3_SPI2_MASK                      (0x1000U)
 #define SIM_SCGC3_SPI2_SHIFT                     (12U)
-#define SIM_SCGC3_SPI2(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SPI2_SHIFT)) & SIM_SCGC3_SPI2_MASK)
+#define SIM_SCGC3_SPI2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SPI2_SHIFT)) & SIM_SCGC3_SPI2_MASK)
+#define SIM_SCGC3_SPI2 SIM_SCGC3_SPI2_MASK
 #define SIM_SCGC3_SDHC_MASK                      (0x20000U)
 #define SIM_SCGC3_SDHC_SHIFT                     (17U)
-#define SIM_SCGC3_SDHC(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SDHC_SHIFT)) & SIM_SCGC3_SDHC_MASK)
+#define SIM_SCGC3_SDHC_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SDHC_SHIFT)) & SIM_SCGC3_SDHC_MASK)
+#define SIM_SCGC3_SDHC SIM_SCGC3_SDHC_MASK
 #define SIM_SCGC3_FTM2_MASK                      (0x1000000U)
 #define SIM_SCGC3_FTM2_SHIFT                     (24U)
-#define SIM_SCGC3_FTM2(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM2_SHIFT)) & SIM_SCGC3_FTM2_MASK)
+#define SIM_SCGC3_FTM2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM2_SHIFT)) & SIM_SCGC3_FTM2_MASK)
+#define SIM_SCGC3_FTM2 SIM_SCGC3_FTM2_MASK
 #define SIM_SCGC3_FTM3_MASK                      (0x2000000U)
 #define SIM_SCGC3_FTM3_SHIFT                     (25U)
-#define SIM_SCGC3_FTM3(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM3_SHIFT)) & SIM_SCGC3_FTM3_MASK)
+#define SIM_SCGC3_FTM3_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM3_SHIFT)) & SIM_SCGC3_FTM3_MASK)
+#define SIM_SCGC3_FTM3 SIM_SCGC3_FTM3_MASK
 #define SIM_SCGC3_ADC1_MASK                      (0x8000000U)
 #define SIM_SCGC3_ADC1_SHIFT                     (27U)
-#define SIM_SCGC3_ADC1(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_ADC1_SHIFT)) & SIM_SCGC3_ADC1_MASK)
+#define SIM_SCGC3_ADC1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_ADC1_SHIFT)) & SIM_SCGC3_ADC1_MASK)
+#define SIM_SCGC3_ADC1 SIM_SCGC3_ADC1_MASK
 
 /*! @name SCGC4 - System Clock Gating Control Register 4 */
 #define SIM_SCGC4_EWM_MASK                       (0x2U)
 #define SIM_SCGC4_EWM_SHIFT                      (1U)
-#define SIM_SCGC4_EWM(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)
+#define SIM_SCGC4_EWM_SET(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)
+#define SIM_SCGC4_EWM SIM_SCGC4_EWM_MASK
 #define SIM_SCGC4_CMT_MASK                       (0x4U)
 #define SIM_SCGC4_CMT_SHIFT                      (2U)
-#define SIM_SCGC4_CMT(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK)
+#define SIM_SCGC4_CMT_SET(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK)
+#define SIM_SCGC4_CMT SIM_SCGC4_CMT_MASK
 #define SIM_SCGC4_I2C0_MASK                      (0x40U)
 #define SIM_SCGC4_I2C0_SHIFT                     (6U)
-#define SIM_SCGC4_I2C0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
+#define SIM_SCGC4_I2C0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
+#define SIM_SCGC4_I2C0 SIM_SCGC4_I2C0_MASK
 #define SIM_SCGC4_I2C1_MASK                      (0x80U)
 #define SIM_SCGC4_I2C1_SHIFT                     (7U)
-#define SIM_SCGC4_I2C1(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
+#define SIM_SCGC4_I2C1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
+#define SIM_SCGC4_I2C1 SIM_SCGC4_I2C1_MASK
 #define SIM_SCGC4_UART0_MASK                     (0x400U)
 #define SIM_SCGC4_UART0_SHIFT                    (10U)
-#define SIM_SCGC4_UART0(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)
+#define SIM_SCGC4_UART0_SET(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)
+#define SIM_SCGC4_UART0 SIM_SCGC4_UART0_MASK
 #define SIM_SCGC4_UART1_MASK                     (0x800U)
 #define SIM_SCGC4_UART1_SHIFT                    (11U)
-#define SIM_SCGC4_UART1(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)
+#define SIM_SCGC4_UART1_SET(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)
+#define SIM_SCGC4_UART1 SIM_SCGC4_UART1_MASK
 #define SIM_SCGC4_UART2_MASK                     (0x1000U)
 #define SIM_SCGC4_UART2_SHIFT                    (12U)
-#define SIM_SCGC4_UART2(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
+#define SIM_SCGC4_UART2_SET(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
+#define SIM_SCGC4_UART2 SIM_SCGC4_UART2_MASK
 #define SIM_SCGC4_UART3_MASK                     (0x2000U)
 #define SIM_SCGC4_UART3_SHIFT                    (13U)
-#define SIM_SCGC4_UART3(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART3_SHIFT)) & SIM_SCGC4_UART3_MASK)
+#define SIM_SCGC4_UART3_SET(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART3_SHIFT)) & SIM_SCGC4_UART3_MASK)
+#define SIM_SCGC4_UART3 SIM_SCGC4_UART3_MASK
 #define SIM_SCGC4_USBOTG_MASK                    (0x40000U)
 #define SIM_SCGC4_USBOTG_SHIFT                   (18U)
 #define SIM_SCGC4_USBOTG_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK)
 #define SIM_SCGC4_USBOTG                         SIM_SCGC4_USBOTG_SET(1)
 #define SIM_SCGC4_CMP_MASK                       (0x80000U)
 #define SIM_SCGC4_CMP_SHIFT                      (19U)
-#define SIM_SCGC4_CMP(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
+#define SIM_SCGC4_CMP_SET(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
+#define SIM_SCGC4_CMP SIM_SCGC4_CMP_MASK
 #define SIM_SCGC4_VREF_MASK                      (0x100000U)
 #define SIM_SCGC4_VREF_SHIFT                     (20U)
-#define SIM_SCGC4_VREF(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
+#define SIM_SCGC4_VREF_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
+#define SIM_SCGC4_VREF SIM_SCGC4_VREF_MASK
 
 /*! @name SCGC5 - System Clock Gating Control Register 5 */
 #define SIM_SCGC5_LPTMR_MASK                     (0x1U)
@@ -12418,7 +15025,8 @@ typedef struct {
 #define SIM_SCGC5_LPTMR                          SIM_SCGC5_LPTMR_SET(1)
 #define SIM_SCGC5_TSI_MASK                       (0x20U)
 #define SIM_SCGC5_TSI_SHIFT                      (5U)
-#define SIM_SCGC5_TSI(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK)
+#define SIM_SCGC5_TSI_SET(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_TSI_SHIFT)) & SIM_SCGC5_TSI_MASK)
+#define SIM_SCGC5_TSI SIM_SCGC5_TSI_MASK
 #define SIM_SCGC5_PORTA_MASK                     (0x200U)
 #define SIM_SCGC5_PORTA_SHIFT                    (9U)
 #define SIM_SCGC5_PORTA_SET(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
@@ -12443,69 +15051,90 @@ typedef struct {
 /*! @name SCGC6 - System Clock Gating Control Register 6 */
 #define SIM_SCGC6_FTF_MASK                       (0x1U)
 #define SIM_SCGC6_FTF_SHIFT                      (0U)
-#define SIM_SCGC6_FTF(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
+#define SIM_SCGC6_FTF_SET(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
+#define SIM_SCGC6_FTF SIM_SCGC6_FTF_MASK
 #define SIM_SCGC6_DMAMUX_MASK                    (0x2U)
 #define SIM_SCGC6_DMAMUX_SHIFT                   (1U)
-#define SIM_SCGC6_DMAMUX(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
+#define SIM_SCGC6_DMAMUX_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
+#define SIM_SCGC6_DMAMUX SIM_SCGC6_DMAMUX_MASK
 #define SIM_SCGC6_FLEXCAN0_MASK                  (0x10U)
 #define SIM_SCGC6_FLEXCAN0_SHIFT                 (4U)
-#define SIM_SCGC6_FLEXCAN0(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FLEXCAN0_SHIFT)) & SIM_SCGC6_FLEXCAN0_MASK)
+#define SIM_SCGC6_FLEXCAN0_SET(x)                (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FLEXCAN0_SHIFT)) & SIM_SCGC6_FLEXCAN0_MASK)
+#define SIM_SCGC6_FLEXCAN0 SIM_SCGC6_FLEXCAN0_MASK
 #define SIM_SCGC6_RNGA_MASK                      (0x200U)
 #define SIM_SCGC6_RNGA_SHIFT                     (9U)
-#define SIM_SCGC6_RNGA(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RNGA_SHIFT)) & SIM_SCGC6_RNGA_MASK)
+#define SIM_SCGC6_RNGA_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RNGA_SHIFT)) & SIM_SCGC6_RNGA_MASK)
+#define SIM_SCGC6_RNGA SIM_SCGC6_RNGA_MASK
 #define SIM_SCGC6_SPI0_MASK                      (0x1000U)
 #define SIM_SCGC6_SPI0_SHIFT                     (12U)
-#define SIM_SCGC6_SPI0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)
+#define SIM_SCGC6_SPI0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)
+#define SIM_SCGC6_SPI0 SIM_SCGC6_SPI0_MASK
 #define SIM_SCGC6_SPI1_MASK                      (0x2000U)
 #define SIM_SCGC6_SPI1_SHIFT                     (13U)
-#define SIM_SCGC6_SPI1(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)
+#define SIM_SCGC6_SPI1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)
+#define SIM_SCGC6_SPI1 SIM_SCGC6_SPI1_MASK
 #define SIM_SCGC6_I2S_MASK                       (0x8000U)
 #define SIM_SCGC6_I2S_SHIFT                      (15U)
-#define SIM_SCGC6_I2S(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)
+#define SIM_SCGC6_I2S_SET(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)
+#define SIM_SCGC6_I2S SIM_SCGC6_I2S_MASK
 #define SIM_SCGC6_CRC_MASK                       (0x40000U)
 #define SIM_SCGC6_CRC_SHIFT                      (18U)
-#define SIM_SCGC6_CRC(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)
+#define SIM_SCGC6_CRC_SET(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)
+#define SIM_SCGC6_CRC SIM_SCGC6_CRC_MASK
 #define SIM_SCGC6_USBDCD_MASK                    (0x200000U)
 #define SIM_SCGC6_USBDCD_SHIFT                   (21U)
-#define SIM_SCGC6_USBDCD(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_USBDCD_SHIFT)) & SIM_SCGC6_USBDCD_MASK)
+#define SIM_SCGC6_USBDCD_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_USBDCD_SHIFT)) & SIM_SCGC6_USBDCD_MASK)
+#define SIM_SCGC6_USBDCD SIM_SCGC6_USBDCD_MASK
 #define SIM_SCGC6_PDB_MASK                       (0x400000U)
 #define SIM_SCGC6_PDB_SHIFT                      (22U)
-#define SIM_SCGC6_PDB(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK)
+#define SIM_SCGC6_PDB_SET(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK)
+#define SIM_SCGC6_PDB SIM_SCGC6_PDB_MASK
 #define SIM_SCGC6_PIT_MASK                       (0x800000U)
 #define SIM_SCGC6_PIT_SHIFT                      (23U)
-#define SIM_SCGC6_PIT(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
+#define SIM_SCGC6_PIT_SET(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
+#define SIM_SCGC6_PIT SIM_SCGC6_PIT_MASK
 #define SIM_SCGC6_FTM0_MASK                      (0x1000000U)
 #define SIM_SCGC6_FTM0_SHIFT                     (24U)
-#define SIM_SCGC6_FTM0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)
+#define SIM_SCGC6_FTM0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)
+#define SIM_SCGC6_FTM0 SIM_SCGC6_FTM0_MASK
 #define SIM_SCGC6_FTM1_MASK                      (0x2000000U)
 #define SIM_SCGC6_FTM1_SHIFT                     (25U)
-#define SIM_SCGC6_FTM1(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK)
+#define SIM_SCGC6_FTM1_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK)
+#define SIM_SCGC6_FTM1 SIM_SCGC6_FTM1_MASK
 #define SIM_SCGC6_FTM2_MASK                      (0x4000000U)
 #define SIM_SCGC6_FTM2_SHIFT                     (26U)
-#define SIM_SCGC6_FTM2(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK)
+#define SIM_SCGC6_FTM2_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK)
+#define SIM_SCGC6_FTM2 SIM_SCGC6_FTM2_MASK
 #define SIM_SCGC6_ADC0_MASK                      (0x8000000U)
 #define SIM_SCGC6_ADC0_SHIFT                     (27U)
-#define SIM_SCGC6_ADC0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
+#define SIM_SCGC6_ADC0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
+#define SIM_SCGC6_ADC0 SIM_SCGC6_ADC0_MASK
 #define SIM_SCGC6_RTC_MASK                       (0x20000000U)
 #define SIM_SCGC6_RTC_SHIFT                      (29U)
-#define SIM_SCGC6_RTC(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
+#define SIM_SCGC6_RTC_SET(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
+#define SIM_SCGC6_RTC SIM_SCGC6_RTC_MASK
 #define SIM_SCGC6_DAC0_MASK                      (0x80000000U)
 #define SIM_SCGC6_DAC0_SHIFT                     (31U)
-#define SIM_SCGC6_DAC0(x)                        (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)
+#define SIM_SCGC6_DAC0_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)
+#define SIM_SCGC6_DAC0 SIM_SCGC6_DAC0_MASK
 
 /*! @name SCGC7 - System Clock Gating Control Register 7 */
 #define SIM_SCGC7_FLEXBUS_MASK                   (0x1U)
 #define SIM_SCGC7_FLEXBUS_SHIFT                  (0U)
-#define SIM_SCGC7_FLEXBUS(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_FLEXBUS_SHIFT)) & SIM_SCGC7_FLEXBUS_MASK)
+#define SIM_SCGC7_FLEXBUS_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_FLEXBUS_SHIFT)) & SIM_SCGC7_FLEXBUS_MASK)
+#define SIM_SCGC7_FLEXBUS SIM_SCGC7_FLEXBUS_MASK
 #define SIM_SCGC7_DMA_MASK                       (0x2U)
 #define SIM_SCGC7_DMA_SHIFT                      (1U)
-#define SIM_SCGC7_DMA(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
+#define SIM_SCGC7_DMA_SET(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
+#define SIM_SCGC7_DMA SIM_SCGC7_DMA_MASK
 #define SIM_SCGC7_MPU_MASK                       (0x4U)
 #define SIM_SCGC7_MPU_SHIFT                      (2U)
-#define SIM_SCGC7_MPU(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_MPU_SHIFT)) & SIM_SCGC7_MPU_MASK)
+#define SIM_SCGC7_MPU_SET(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_MPU_SHIFT)) & SIM_SCGC7_MPU_MASK)
+#define SIM_SCGC7_MPU SIM_SCGC7_MPU_MASK
 #define SIM_SCGC7_SDRAMC_MASK                    (0x8U)
 #define SIM_SCGC7_SDRAMC_SHIFT                   (3U)
-#define SIM_SCGC7_SDRAMC(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_SDRAMC_SHIFT)) & SIM_SCGC7_SDRAMC_MASK)
+#define SIM_SCGC7_SDRAMC_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_SDRAMC_SHIFT)) & SIM_SCGC7_SDRAMC_MASK)
+#define SIM_SCGC7_SDRAMC SIM_SCGC7_SDRAMC_MASK
 
 /*! @name CLKDIV1 - System Clock Divider Register 1 */
 #define SIM_CLKDIV1_OUTDIV4_MASK                 (0xF0000U)
@@ -12533,72 +15162,90 @@ typedef struct {
 /*! @name FCFG1 - Flash Configuration Register 1 */
 #define SIM_FCFG1_FLASHDIS_MASK                  (0x1U)
 #define SIM_FCFG1_FLASHDIS_SHIFT                 (0U)
-#define SIM_FCFG1_FLASHDIS(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
+#define SIM_FCFG1_FLASHDIS_SET(x)                (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
+#define SIM_FCFG1_FLASHDIS SIM_FCFG1_FLASHDIS_MASK
 #define SIM_FCFG1_FLASHDOZE_MASK                 (0x2U)
 #define SIM_FCFG1_FLASHDOZE_SHIFT                (1U)
-#define SIM_FCFG1_FLASHDOZE(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
+#define SIM_FCFG1_FLASHDOZE_SET(x)               (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
+#define SIM_FCFG1_FLASHDOZE SIM_FCFG1_FLASHDOZE_MASK
 #define SIM_FCFG1_DEPART_MASK                    (0xF00U)
 #define SIM_FCFG1_DEPART_SHIFT                   (8U)
-#define SIM_FCFG1_DEPART(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_DEPART_SHIFT)) & SIM_FCFG1_DEPART_MASK)
+#define SIM_FCFG1_DEPART_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_DEPART_SHIFT)) & SIM_FCFG1_DEPART_MASK)
+#define SIM_FCFG1_DEPART SIM_FCFG1_DEPART_MASK
 #define SIM_FCFG1_EESIZE_MASK                    (0xF0000U)
 #define SIM_FCFG1_EESIZE_SHIFT                   (16U)
-#define SIM_FCFG1_EESIZE(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EESIZE_SHIFT)) & SIM_FCFG1_EESIZE_MASK)
+#define SIM_FCFG1_EESIZE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EESIZE_SHIFT)) & SIM_FCFG1_EESIZE_MASK)
+#define SIM_FCFG1_EESIZE SIM_FCFG1_EESIZE_MASK
 #define SIM_FCFG1_PFSIZE_MASK                    (0xF000000U)
 #define SIM_FCFG1_PFSIZE_SHIFT                   (24U)
-#define SIM_FCFG1_PFSIZE(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
+#define SIM_FCFG1_PFSIZE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
+#define SIM_FCFG1_PFSIZE SIM_FCFG1_PFSIZE_MASK
 #define SIM_FCFG1_NVMSIZE_MASK                   (0xF0000000U)
 #define SIM_FCFG1_NVMSIZE_SHIFT                  (28U)
-#define SIM_FCFG1_NVMSIZE(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_NVMSIZE_SHIFT)) & SIM_FCFG1_NVMSIZE_MASK)
+#define SIM_FCFG1_NVMSIZE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_NVMSIZE_SHIFT)) & SIM_FCFG1_NVMSIZE_MASK)
+#define SIM_FCFG1_NVMSIZE SIM_FCFG1_NVMSIZE_MASK
 
 /*! @name FCFG2 - Flash Configuration Register 2 */
 #define SIM_FCFG2_MAXADDR1_MASK                  (0x7F0000U)
 #define SIM_FCFG2_MAXADDR1_SHIFT                 (16U)
-#define SIM_FCFG2_MAXADDR1(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
+#define SIM_FCFG2_MAXADDR1_SET(x)                (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
+#define SIM_FCFG2_MAXADDR1 SIM_FCFG2_MAXADDR1_MASK
 #define SIM_FCFG2_PFLSH_MASK                     (0x800000U)
 #define SIM_FCFG2_PFLSH_SHIFT                    (23U)
-#define SIM_FCFG2_PFLSH(x)                       (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_PFLSH_SHIFT)) & SIM_FCFG2_PFLSH_MASK)
+#define SIM_FCFG2_PFLSH_SET(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_PFLSH_SHIFT)) & SIM_FCFG2_PFLSH_MASK)
+#define SIM_FCFG2_PFLSH SIM_FCFG2_PFLSH_MASK
 #define SIM_FCFG2_MAXADDR0_MASK                  (0x7F000000U)
 #define SIM_FCFG2_MAXADDR0_SHIFT                 (24U)
-#define SIM_FCFG2_MAXADDR0(x)                    (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
+#define SIM_FCFG2_MAXADDR0_SET(x)                (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
+#define SIM_FCFG2_MAXADDR0 SIM_FCFG2_MAXADDR0_MASK
 #define SIM_FCFG2_SWAPPFLSH_MASK                 (0x80000000U)
 #define SIM_FCFG2_SWAPPFLSH_SHIFT                (31U)
-#define SIM_FCFG2_SWAPPFLSH(x)                   (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_SWAPPFLSH_SHIFT)) & SIM_FCFG2_SWAPPFLSH_MASK)
+#define SIM_FCFG2_SWAPPFLSH_SET(x)               (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_SWAPPFLSH_SHIFT)) & SIM_FCFG2_SWAPPFLSH_MASK)
+#define SIM_FCFG2_SWAPPFLSH SIM_FCFG2_SWAPPFLSH_MASK
 
 /*! @name UIDH - Unique Identification Register High */
 #define SIM_UIDH_UID_MASK                        (0xFFFFFFFFU)
 #define SIM_UIDH_UID_SHIFT                       (0U)
-#define SIM_UIDH_UID(x)                          (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK)
+#define SIM_UIDH_UID_SET(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK)
+#define SIM_UIDH_UID SIM_UIDH_UID_MASK
 
 /*! @name UIDMH - Unique Identification Register Mid-High */
 #define SIM_UIDMH_UID_MASK                       (0xFFFFFFFFU)
 #define SIM_UIDMH_UID_SHIFT                      (0U)
-#define SIM_UIDMH_UID(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
+#define SIM_UIDMH_UID_SET(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
+#define SIM_UIDMH_UID SIM_UIDMH_UID_MASK
 
 /*! @name UIDML - Unique Identification Register Mid Low */
 #define SIM_UIDML_UID_MASK                       (0xFFFFFFFFU)
 #define SIM_UIDML_UID_SHIFT                      (0U)
-#define SIM_UIDML_UID(x)                         (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
+#define SIM_UIDML_UID_SET(x)                     (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
+#define SIM_UIDML_UID SIM_UIDML_UID_MASK
 
 /*! @name UIDL - Unique Identification Register Low */
 #define SIM_UIDL_UID_MASK                        (0xFFFFFFFFU)
 #define SIM_UIDL_UID_SHIFT                       (0U)
-#define SIM_UIDL_UID(x)                          (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
+#define SIM_UIDL_UID_SET(x)                      (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
+#define SIM_UIDL_UID SIM_UIDL_UID_MASK
 
 /*! @name CLKDIV3 - System Clock Divider Register 3 */
 #define SIM_CLKDIV3_PLLFLLFRAC_MASK              (0x1U)
 #define SIM_CLKDIV3_PLLFLLFRAC_SHIFT             (0U)
-#define SIM_CLKDIV3_PLLFLLFRAC(x)                (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV3_PLLFLLFRAC_SHIFT)) & SIM_CLKDIV3_PLLFLLFRAC_MASK)
+#define SIM_CLKDIV3_PLLFLLFRAC_SET(x)            (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV3_PLLFLLFRAC_SHIFT)) & SIM_CLKDIV3_PLLFLLFRAC_MASK)
+#define SIM_CLKDIV3_PLLFLLFRAC SIM_CLKDIV3_PLLFLLFRAC_MASK
 #define SIM_CLKDIV3_PLLFLLDIV_MASK               (0xEU)
 #define SIM_CLKDIV3_PLLFLLDIV_SHIFT              (1U)
-#define SIM_CLKDIV3_PLLFLLDIV(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV3_PLLFLLDIV_SHIFT)) & SIM_CLKDIV3_PLLFLLDIV_MASK)
+#define SIM_CLKDIV3_PLLFLLDIV_SET(x)             (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV3_PLLFLLDIV_SHIFT)) & SIM_CLKDIV3_PLLFLLDIV_MASK)
+#define SIM_CLKDIV3_PLLFLLDIV SIM_CLKDIV3_PLLFLLDIV_MASK
 
 /*! @name CLKDIV4 - System Clock Divider Register 4 */
 #define SIM_CLKDIV4_TRACEFRAC_MASK               (0x1U)
 #define SIM_CLKDIV4_TRACEFRAC_SHIFT              (0U)
-#define SIM_CLKDIV4_TRACEFRAC(x)                 (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV4_TRACEFRAC_SHIFT)) & SIM_CLKDIV4_TRACEFRAC_MASK)
+#define SIM_CLKDIV4_TRACEFRAC_SET(x)             (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV4_TRACEFRAC_SHIFT)) & SIM_CLKDIV4_TRACEFRAC_MASK)
+#define SIM_CLKDIV4_TRACEFRAC SIM_CLKDIV4_TRACEFRAC_MASK
 #define SIM_CLKDIV4_TRACEDIV_MASK                (0xEU)
 #define SIM_CLKDIV4_TRACEDIV_SHIFT               (1U)
-#define SIM_CLKDIV4_TRACEDIV(x)                  (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV4_TRACEDIV_SHIFT)) & SIM_CLKDIV4_TRACEDIV_MASK)
+#define SIM_CLKDIV4_TRACEDIV_SET(x)              (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV4_TRACEDIV_SHIFT)) & SIM_CLKDIV4_TRACEDIV_MASK)
+#define SIM_CLKDIV4_TRACEDIV SIM_CLKDIV4_TRACEDIV_MASK
 
 
 /*!
@@ -12610,7 +15257,7 @@ typedef struct {
 /** Peripheral SIM base address */
 #define SIM_BASE                                 (0x40047000u)
 /** Peripheral SIM base pointer */
-#define SIM                                      ((SIM_Type *)SIM_BASE)
+#define SIM                                      ((SIM_TypeDef *)SIM_BASE)
 /** Array initializer of SIM peripheral base addresses */
 #define SIM_BASE_ADDRS                           { SIM_BASE }
 /** Array initializer of SIM peripheral base pointers */
@@ -12636,7 +15283,7 @@ typedef struct {
   __IO uint8_t PMCTRL;                             /**< Power Mode Control register, offset: 0x1 */
   __IO uint8_t STOPCTRL;                           /**< Stop Control Register, offset: 0x2 */
   __I  uint8_t PMSTAT;                             /**< Power Mode Status register, offset: 0x3 */
-} SMC_Type;
+} SMC_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- SMC Register Masks
@@ -12650,46 +15297,58 @@ typedef struct {
 /*! @name PMPROT - Power Mode Protection register */
 #define SMC_PMPROT_AVLLS_MASK                    (0x2U)
 #define SMC_PMPROT_AVLLS_SHIFT                   (1U)
-#define SMC_PMPROT_AVLLS(x)                      (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
+#define SMC_PMPROT_AVLLS_SET(x)                  (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
+#define SMC_PMPROT_AVLLS SMC_PMPROT_AVLLS_MASK
 #define SMC_PMPROT_ALLS_MASK                     (0x8U)
 #define SMC_PMPROT_ALLS_SHIFT                    (3U)
-#define SMC_PMPROT_ALLS(x)                       (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
+#define SMC_PMPROT_ALLS_SET(x)                   (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
+#define SMC_PMPROT_ALLS SMC_PMPROT_ALLS_MASK
 #define SMC_PMPROT_AVLP_MASK                     (0x20U)
 #define SMC_PMPROT_AVLP_SHIFT                    (5U)
-#define SMC_PMPROT_AVLP(x)                       (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
+#define SMC_PMPROT_AVLP_SET(x)                   (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
+#define SMC_PMPROT_AVLP SMC_PMPROT_AVLP_MASK
 #define SMC_PMPROT_AHSRUN_MASK                   (0x80U)
 #define SMC_PMPROT_AHSRUN_SHIFT                  (7U)
-#define SMC_PMPROT_AHSRUN(x)                     (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AHSRUN_SHIFT)) & SMC_PMPROT_AHSRUN_MASK)
+#define SMC_PMPROT_AHSRUN_SET(x)                 (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AHSRUN_SHIFT)) & SMC_PMPROT_AHSRUN_MASK)
+#define SMC_PMPROT_AHSRUN SMC_PMPROT_AHSRUN_MASK
 
 /*! @name PMCTRL - Power Mode Control register */
 #define SMC_PMCTRL_STOPM_MASK                    (0x7U)
 #define SMC_PMCTRL_STOPM_SHIFT                   (0U)
-#define SMC_PMCTRL_STOPM(x)                      (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPM_SET(x)                  (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
+#define SMC_PMCTRL_STOPM SMC_PMCTRL_STOPM_MASK
 #define SMC_PMCTRL_STOPA_MASK                    (0x8U)
 #define SMC_PMCTRL_STOPA_SHIFT                   (3U)
-#define SMC_PMCTRL_STOPA(x)                      (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
+#define SMC_PMCTRL_STOPA_SET(x)                  (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
+#define SMC_PMCTRL_STOPA SMC_PMCTRL_STOPA_MASK
 #define SMC_PMCTRL_RUNM_MASK                     (0x60U)
 #define SMC_PMCTRL_RUNM_SHIFT                    (5U)
-#define SMC_PMCTRL_RUNM(x)                       (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
+#define SMC_PMCTRL_RUNM_SET(x)                   (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
+#define SMC_PMCTRL_RUNM SMC_PMCTRL_RUNM_MASK
 
 /*! @name STOPCTRL - Stop Control Register */
 #define SMC_STOPCTRL_LLSM_MASK                   (0x7U)
 #define SMC_STOPCTRL_LLSM_SHIFT                  (0U)
-#define SMC_STOPCTRL_LLSM(x)                     (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_LLSM_SHIFT)) & SMC_STOPCTRL_LLSM_MASK)
+#define SMC_STOPCTRL_LLSM_SET(x)                 (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_LLSM_SHIFT)) & SMC_STOPCTRL_LLSM_MASK)
+#define SMC_STOPCTRL_LLSM SMC_STOPCTRL_LLSM_MASK
 #define SMC_STOPCTRL_RAM2PO_MASK                 (0x10U)
 #define SMC_STOPCTRL_RAM2PO_SHIFT                (4U)
-#define SMC_STOPCTRL_RAM2PO(x)                   (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_RAM2PO_SHIFT)) & SMC_STOPCTRL_RAM2PO_MASK)
+#define SMC_STOPCTRL_RAM2PO_SET(x)               (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_RAM2PO_SHIFT)) & SMC_STOPCTRL_RAM2PO_MASK)
+#define SMC_STOPCTRL_RAM2PO SMC_STOPCTRL_RAM2PO_MASK
 #define SMC_STOPCTRL_PORPO_MASK                  (0x20U)
 #define SMC_STOPCTRL_PORPO_SHIFT                 (5U)
-#define SMC_STOPCTRL_PORPO(x)                    (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK)
+#define SMC_STOPCTRL_PORPO_SET(x)                (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PORPO_SHIFT)) & SMC_STOPCTRL_PORPO_MASK)
+#define SMC_STOPCTRL_PORPO SMC_STOPCTRL_PORPO_MASK
 #define SMC_STOPCTRL_PSTOPO_MASK                 (0xC0U)
 #define SMC_STOPCTRL_PSTOPO_SHIFT                (6U)
-#define SMC_STOPCTRL_PSTOPO(x)                   (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK)
+#define SMC_STOPCTRL_PSTOPO_SET(x)               (((uint8_t)(((uint8_t)(x)) << SMC_STOPCTRL_PSTOPO_SHIFT)) & SMC_STOPCTRL_PSTOPO_MASK)
+#define SMC_STOPCTRL_PSTOPO SMC_STOPCTRL_PSTOPO_MASK
 
 /*! @name PMSTAT - Power Mode Status register */
 #define SMC_PMSTAT_PMSTAT_MASK                   (0xFFU)
 #define SMC_PMSTAT_PMSTAT_SHIFT                  (0U)
-#define SMC_PMSTAT_PMSTAT(x)                     (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
+#define SMC_PMSTAT_PMSTAT_SET(x)                 (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
+#define SMC_PMSTAT_PMSTAT SMC_PMSTAT_PMSTAT_MASK
 
 
 /*!
@@ -12701,7 +15360,7 @@ typedef struct {
 /** Peripheral SMC base address */
 #define SMC_BASE                                 (0x4007E000u)
 /** Peripheral SMC base pointer */
-#define SMC                                      ((SMC_Type *)SMC_BASE)
+#define SMC                                      ((SMC_TypeDef *)SMC_BASE)
 /** Array initializer of SMC peripheral base addresses */
 #define SMC_BASE_ADDRS                           { SMC_BASE }
 /** Array initializer of SMC peripheral base pointers */
@@ -12717,7 +15376,7 @@ typedef struct {
    ---------------------------------------------------------------------------- */
 
 /*!
- * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @addtogroup SPIx_Peripheral_Access_Layer SPI Peripheral Access Layer
  * @{
  */
 
@@ -12747,302 +15406,362 @@ typedef struct {
   __I  uint32_t RXFR1;                             /**< Receive FIFO Registers, offset: 0x80 */
   __I  uint32_t RXFR2;                             /**< Receive FIFO Registers, offset: 0x84 */
   __I  uint32_t RXFR3;                             /**< Receive FIFO Registers, offset: 0x88 */
-} SPI_Type;
+} SPI_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- SPI Register Masks
    ---------------------------------------------------------------------------- */
 
 /*!
- * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @addtogroup SPIx_Register_Masks SPI Register Masks
  * @{
  */
 
 /*! @name MCR - Module Configuration Register */
-#define SPI_MCR_HALT_MASK                        (0x1U)
-#define SPI_MCR_HALT_SHIFT                       (0U)
-#define SPI_MCR_HALT(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
-#define SPI_MCR_SMPL_PT_MASK                     (0x300U)
-#define SPI_MCR_SMPL_PT_SHIFT                    (8U)
-#define SPI_MCR_SMPL_PT(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
-#define SPI_MCR_CLR_RXF_MASK                     (0x400U)
-#define SPI_MCR_CLR_RXF_SHIFT                    (10U)
-#define SPI_MCR_CLR_RXF(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
-#define SPI_MCR_CLR_TXF_MASK                     (0x800U)
-#define SPI_MCR_CLR_TXF_SHIFT                    (11U)
-#define SPI_MCR_CLR_TXF(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
-#define SPI_MCR_DIS_RXF_MASK                     (0x1000U)
-#define SPI_MCR_DIS_RXF_SHIFT                    (12U)
-#define SPI_MCR_DIS_RXF(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
-#define SPI_MCR_DIS_TXF_MASK                     (0x2000U)
-#define SPI_MCR_DIS_TXF_SHIFT                    (13U)
-#define SPI_MCR_DIS_TXF(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
-#define SPI_MCR_MDIS_MASK                        (0x4000U)
-#define SPI_MCR_MDIS_SHIFT                       (14U)
-#define SPI_MCR_MDIS(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
-#define SPI_MCR_DOZE_MASK                        (0x8000U)
-#define SPI_MCR_DOZE_SHIFT                       (15U)
-#define SPI_MCR_DOZE(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
-#define SPI_MCR_PCSIS_MASK                       (0x3F0000U)
-#define SPI_MCR_PCSIS_SHIFT                      (16U)
-#define SPI_MCR_PCSIS(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
-#define SPI_MCR_ROOE_MASK                        (0x1000000U)
-#define SPI_MCR_ROOE_SHIFT                       (24U)
-#define SPI_MCR_ROOE(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
-#define SPI_MCR_PCSSE_MASK                       (0x2000000U)
-#define SPI_MCR_PCSSE_SHIFT                      (25U)
-#define SPI_MCR_PCSSE(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)
-#define SPI_MCR_MTFE_MASK                        (0x4000000U)
-#define SPI_MCR_MTFE_SHIFT                       (26U)
-#define SPI_MCR_MTFE(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
-#define SPI_MCR_FRZ_MASK                         (0x8000000U)
-#define SPI_MCR_FRZ_SHIFT                        (27U)
-#define SPI_MCR_FRZ(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
-#define SPI_MCR_DCONF_MASK                       (0x30000000U)
-#define SPI_MCR_DCONF_SHIFT                      (28U)
-#define SPI_MCR_DCONF(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
-#define SPI_MCR_CONT_SCKE_MASK                   (0x40000000U)
-#define SPI_MCR_CONT_SCKE_SHIFT                  (30U)
-#define SPI_MCR_CONT_SCKE(x)                     (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
-#define SPI_MCR_MSTR_MASK                        (0x80000000U)
-#define SPI_MCR_MSTR_SHIFT                       (31U)
-#define SPI_MCR_MSTR(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)
+#define SPIx_MCR_HALT_MASK                        (0x1U)
+#define SPIx_MCR_HALT_SHIFT                       (0U)
+#define SPIx_MCR_HALT_SET(x)                      (((uint32_t)(((uint32_t)(x)) << SPIx_MCR_HALT_SHIFT)) & SPIx_MCR_HALT_MASK)
+#define SPIx_MCR_HALT SPIx_MCR_HALT_MASK
+#define SPIx_MCR_SMPL_PT_MASK                     (0x300U)
+#define SPIx_MCR_SMPL_PT_SHIFT                    (8U)
+#define SPIx_MCR_SMPL_PT_SET(x)                   (((uint32_t)(((uint32_t)(x)) << SPIx_MCR_SMPL_PT_SHIFT)) & SPIx_MCR_SMPL_PT_MASK)
+#define SPIx_MCR_SMPL_PT SPIx_MCR_SMPL_PT_MASK
+#define SPIx_MCR_CLR_RXF_MASK                     (0x400U)
+#define SPIx_MCR_CLR_RXF_SHIFT                    (10U)
+#define SPIx_MCR_CLR_RXF_SET(x)                   (((uint32_t)(((uint32_t)(x)) << SPIx_MCR_CLR_RXF_SHIFT)) & SPIx_MCR_CLR_RXF_MASK)
+#define SPIx_MCR_CLR_RXF SPIx_MCR_CLR_RXF_MASK
+#define SPIx_MCR_CLR_TXF_MASK                     (0x800U)
+#define SPIx_MCR_CLR_TXF_SHIFT                    (11U)
+#define SPIx_MCR_CLR_TXF_SET(x)                   (((uint32_t)(((uint32_t)(x)) << SPIx_MCR_CLR_TXF_SHIFT)) & SPIx_MCR_CLR_TXF_MASK)
+#define SPIx_MCR_CLR_TXF SPIx_MCR_CLR_TXF_MASK
+#define SPIx_MCR_DIS_RXF_MASK                     (0x1000U)
+#define SPIx_MCR_DIS_RXF_SHIFT                    (12U)
+#define SPIx_MCR_DIS_RXF_SET(x)                   (((uint32_t)(((uint32_t)(x)) << SPIx_MCR_DIS_RXF_SHIFT)) & SPIx_MCR_DIS_RXF_MASK)
+#define SPIx_MCR_DIS_RXF SPIx_MCR_DIS_RXF_MASK
+#define SPIx_MCR_DIS_TXF_MASK                     (0x2000U)
+#define SPIx_MCR_DIS_TXF_SHIFT                    (13U)
+#define SPIx_MCR_DIS_TXF_SET(x)                   (((uint32_t)(((uint32_t)(x)) << SPIx_MCR_DIS_TXF_SHIFT)) & SPIx_MCR_DIS_TXF_MASK)
+#define SPIx_MCR_DIS_TXF SPIx_MCR_DIS_TXF_MASK
+#define SPIx_MCR_MDIS_MASK                        (0x4000U)
+#define SPIx_MCR_MDIS_SHIFT                       (14U)
+#define SPIx_MCR_MDIS_SET(x)                      (((uint32_t)(((uint32_t)(x)) << SPIx_MCR_MDIS_SHIFT)) & SPIx_MCR_MDIS_MASK)
+#define SPIx_MCR_MDIS SPIx_MCR_MDIS_MASK
+#define SPIx_MCR_DOZE_MASK                        (0x8000U)
+#define SPIx_MCR_DOZE_SHIFT                       (15U)
+#define SPIx_MCR_DOZE_SET(x)                      (((uint32_t)(((uint32_t)(x)) << SPIx_MCR_DOZE_SHIFT)) & SPIx_MCR_DOZE_MASK)
+#define SPIx_MCR_DOZE SPIx_MCR_DOZE_MASK
+#define SPIx_MCR_PCSIS_MASK                       (0x3F0000U)
+#define SPIx_MCR_PCSIS_SHIFT                      (16U)
+#define SPIx_MCR_PCSIS_SET(x)                     (((uint32_t)(((uint32_t)(x)) << SPIx_MCR_PCSIS_SHIFT)) & SPIx_MCR_PCSIS_MASK)
+#define SPIx_MCR_PCSIS SPIx_MCR_PCSIS_MASK
+#define SPIx_MCR_ROOE_MASK                        (0x1000000U)
+#define SPIx_MCR_ROOE_SHIFT                       (24U)
+#define SPIx_MCR_ROOE_SET(x)                      (((uint32_t)(((uint32_t)(x)) << SPIx_MCR_ROOE_SHIFT)) & SPIx_MCR_ROOE_MASK)
+#define SPIx_MCR_ROOE SPIx_MCR_ROOE_MASK
+#define SPIx_MCR_PCSSE_MASK                       (0x2000000U)
+#define SPIx_MCR_PCSSE_SHIFT                      (25U)
+#define SPIx_MCR_PCSSE_SET(x)                     (((uint32_t)(((uint32_t)(x)) << SPIx_MCR_PCSSE_SHIFT)) & SPIx_MCR_PCSSE_MASK)
+#define SPIx_MCR_PCSSE SPIx_MCR_PCSSE_MASK
+#define SPIx_MCR_MTFE_MASK                        (0x4000000U)
+#define SPIx_MCR_MTFE_SHIFT                       (26U)
+#define SPIx_MCR_MTFE_SET(x)                      (((uint32_t)(((uint32_t)(x)) << SPIx_MCR_MTFE_SHIFT)) & SPIx_MCR_MTFE_MASK)
+#define SPIx_MCR_MTFE SPIx_MCR_MTFE_MASK
+#define SPIx_MCR_FRZ_MASK                         (0x8000000U)
+#define SPIx_MCR_FRZ_SHIFT                        (27U)
+#define SPIx_MCR_FRZ_SET(x)                       (((uint32_t)(((uint32_t)(x)) << SPIx_MCR_FRZ_SHIFT)) & SPIx_MCR_FRZ_MASK)
+#define SPIx_MCR_FRZ SPIx_MCR_FRZ_MASK
+#define SPIx_MCR_DCONF_MASK                       (0x30000000U)
+#define SPIx_MCR_DCONF_SHIFT                      (28U)
+#define SPIx_MCR_DCONF_SET(x)                     (((uint32_t)(((uint32_t)(x)) << SPIx_MCR_DCONF_SHIFT)) & SPIx_MCR_DCONF_MASK)
+#define SPIx_MCR_DCONF SPIx_MCR_DCONF_MASK
+#define SPIx_MCR_CONT_SCKE_MASK                   (0x40000000U)
+#define SPIx_MCR_CONT_SCKE_SHIFT                  (30U)
+#define SPIx_MCR_CONT_SCKE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SPIx_MCR_CONT_SCKE_SHIFT)) & SPIx_MCR_CONT_SCKE_MASK)
+#define SPIx_MCR_CONT_SCKE SPIx_MCR_CONT_SCKE_MASK
+#define SPIx_MCR_MSTR_MASK                        (0x80000000U)
+#define SPIx_MCR_MSTR_SHIFT                       (31U)
+#define SPIx_MCR_MSTR_SET(x)                      (((uint32_t)(((uint32_t)(x)) << SPIx_MCR_MSTR_SHIFT)) & SPIx_MCR_MSTR_MASK)
+#define SPIx_MCR_MSTR SPIx_MCR_MSTR_MASK
 
 /*! @name TCR - Transfer Count Register */
-#define SPI_TCR_SPI_TCNT_MASK                    (0xFFFF0000U)
-#define SPI_TCR_SPI_TCNT_SHIFT                   (16U)
-#define SPI_TCR_SPI_TCNT(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK)
+#define SPIx_TCR_SPIx_TCNT_MASK                    (0xFFFF0000U)
+#define SPIx_TCR_SPIx_TCNT_SHIFT                   (16U)
+#define SPIx_TCR_SPIx_TCNT_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SPIx_TCR_SPIx_TCNT_SHIFT)) & SPIx_TCR_SPIx_TCNT_MASK)
+#define SPIx_TCR_SPIx_TCNT SPIx_TCR_SPIx_TCNT_MASK
 
 /*! @name CTAR - Clock and Transfer Attributes Register (In Master Mode) */
-#define SPI_CTAR_BR_MASK                         (0xFU)
-#define SPI_CTAR_BR_SHIFT                        (0U)
-#define SPI_CTAR_BR(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK)
-#define SPI_CTAR_DT_MASK                         (0xF0U)
-#define SPI_CTAR_DT_SHIFT                        (4U)
-#define SPI_CTAR_DT(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK)
-#define SPI_CTAR_ASC_MASK                        (0xF00U)
-#define SPI_CTAR_ASC_SHIFT                       (8U)
-#define SPI_CTAR_ASC(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK)
-#define SPI_CTAR_CSSCK_MASK                      (0xF000U)
-#define SPI_CTAR_CSSCK_SHIFT                     (12U)
-#define SPI_CTAR_CSSCK(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK)
-#define SPI_CTAR_PBR_MASK                        (0x30000U)
-#define SPI_CTAR_PBR_SHIFT                       (16U)
-#define SPI_CTAR_PBR(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)
-#define SPI_CTAR_PDT_MASK                        (0xC0000U)
-#define SPI_CTAR_PDT_SHIFT                       (18U)
-#define SPI_CTAR_PDT(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)
-#define SPI_CTAR_PASC_MASK                       (0x300000U)
-#define SPI_CTAR_PASC_SHIFT                      (20U)
-#define SPI_CTAR_PASC(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)
-#define SPI_CTAR_PCSSCK_MASK                     (0xC00000U)
-#define SPI_CTAR_PCSSCK_SHIFT                    (22U)
-#define SPI_CTAR_PCSSCK(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
-#define SPI_CTAR_LSBFE_MASK                      (0x1000000U)
-#define SPI_CTAR_LSBFE_SHIFT                     (24U)
-#define SPI_CTAR_LSBFE(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)
-#define SPI_CTAR_CPHA_MASK                       (0x2000000U)
-#define SPI_CTAR_CPHA_SHIFT                      (25U)
-#define SPI_CTAR_CPHA(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)
-#define SPI_CTAR_CPOL_MASK                       (0x4000000U)
-#define SPI_CTAR_CPOL_SHIFT                      (26U)
-#define SPI_CTAR_CPOL(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)
-#define SPI_CTAR_FMSZ_MASK                       (0x78000000U)
-#define SPI_CTAR_FMSZ_SHIFT                      (27U)
-#define SPI_CTAR_FMSZ(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK)
-#define SPI_CTAR_DBR_MASK                        (0x80000000U)
-#define SPI_CTAR_DBR_SHIFT                       (31U)
-#define SPI_CTAR_DBR(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)
-
-/* The count of SPI_CTAR */
-#define SPI_CTAR_COUNT                           (2U)
+#define SPIx_CTARn_BR_MASK                         (0xFU)
+#define SPIx_CTARn_BR_SHIFT                        (0U)
+#define SPIx_CTARn_BR(x)                       (((uint32_t)(((uint32_t)(x)) << SPIx_CTARn_BR_SHIFT)) & SPIx_CTARn_BR_MASK)
+#define SPIx_CTARn_DT_MASK                         (0xF0U)
+#define SPIx_CTARn_DT_SHIFT                        (4U)
+#define SPIx_CTARn_DT(x)                       (((uint32_t)(((uint32_t)(x)) << SPIx_CTARn_DT_SHIFT)) & SPIx_CTARn_DT_MASK)
+#define SPIx_CTARn_ASC_MASK                        (0xF00U)
+#define SPIx_CTARn_ASC_SHIFT                       (8U)
+#define SPIx_CTARn_ASC(x)                      (((uint32_t)(((uint32_t)(x)) << SPIx_CTARn_ASC_SHIFT)) & SPIx_CTARn_ASC_MASK)
+#define SPIx_CTARn_CSSCK_MASK                      (0xF000U)
+#define SPIx_CTARn_CSSCK_SHIFT                     (12U)
+#define SPIx_CTARn_CSSCK(x)                    (((uint32_t)(((uint32_t)(x)) << SPIx_CTARn_CSSCK_SHIFT)) & SPIx_CTARn_CSSCK_MASK)
+#define SPIx_CTARn_PBR_MASK                        (0x30000U)
+#define SPIx_CTARn_PBR_SHIFT                       (16U)
+#define SPIx_CTARn_PBR(x)                          (((uint32_t)(((uint32_t)(x)) << SPIx_CTARn_PBR_SHIFT)) & SPIx_CTARn_PBR_MASK)
+#define SPIx_CTARn_PDT_MASK                        (0xC0000U)
+#define SPIx_CTARn_PDT_SHIFT                       (18U)
+#define SPIx_CTARn_PDT_SET(x)                      (((uint32_t)(((uint32_t)(x)) << SPIx_CTARn_PDT_SHIFT)) & SPIx_CTARn_PDT_MASK)
+#define SPIx_CTARn_PDT SPIx_CTARn_PDT_MASK
+#define SPIx_CTARn_PASC_MASK                       (0x300000U)
+#define SPIx_CTARn_PASC_SHIFT                      (20U)
+#define SPIx_CTARn_PASC_SET(x)                     (((uint32_t)(((uint32_t)(x)) << SPIx_CTARn_PASC_SHIFT)) & SPIx_CTARn_PASC_MASK)
+#define SPIx_CTARn_PASC SPIx_CTARn_PASC_MASK
+#define SPIx_CTARn_PCSSCK_MASK                     (0xC00000U)
+#define SPIx_CTARn_PCSSCK_SHIFT                    (22U)
+#define SPIx_CTARn_PCSSCK_SET(x)                   (((uint32_t)(((uint32_t)(x)) << SPIx_CTARn_PCSSCK_SHIFT)) & SPIx_CTARn_PCSSCK_MASK)
+#define SPIx_CTARn_PCSSCK SPIx_CTARn_PCSSCK_MASK
+#define SPIx_CTARn_LSBFE_MASK                      (0x1000000U)
+#define SPIx_CTARn_LSBFE_SHIFT                     (24U)
+#define SPIx_CTARn_LSBFE_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SPIx_CTARn_LSBFE_SHIFT)) & SPIx_CTARn_LSBFE_MASK)
+#define SPIx_CTARn_LSBFE SPIx_CTARn_LSBFE_MASK
+#define SPIx_CTARn_CPHA_MASK                       (0x2000000U)
+#define SPIx_CTARn_CPHA_SHIFT                      (25U)
+#define SPIx_CTARn_CPHA_SET(x)                     (((uint32_t)(((uint32_t)(x)) << SPIx_CTARn_CPHA_SHIFT)) & SPIx_CTARn_CPHA_MASK)
+#define SPIx_CTARn_CPHA SPIx_CTARn_CPHA_MASK
+#define SPIx_CTARn_CPOL_MASK                       (0x4000000U)
+#define SPIx_CTARn_CPOL_SHIFT                      (26U)
+#define SPIx_CTARn_CPOL_SET(x)                     (((uint32_t)(((uint32_t)(x)) << SPIx_CTARn_CPOL_SHIFT)) & SPIx_CTARn_CPOL_MASK)
+#define SPIx_CTARn_CPOL SPIx_CTARn_CPOL_MASK
+#define SPIx_CTARn_FMSZ_MASK                       (0x78000000U)
+#define SPIx_CTARn_FMSZ_SHIFT                      (27U)
+#define SPIx_CTARn_FMSZ(x)                         (((uint32_t)(((uint32_t)(x)) << SPIx_CTARn_FMSZ_SHIFT)) & SPIx_CTARn_FMSZ_MASK)
+#define SPIx_CTARn_DBR_MASK                        (0x80000000U)
+#define SPIx_CTARn_DBR_SHIFT                       (31U)
+#define SPIx_CTARn_DBR_SET(x)                      (((uint32_t)(((uint32_t)(x)) << SPIx_CTARn_DBR_SHIFT)) & SPIx_CTARn_DBR_MASK)
+#define SPIx_CTARn_DBR SPIx_CTARn_DBR_MASK
+
+/* The count of SPIx_CTAR */
+#define SPIx_CTARn_COUNT                           (2U)
 
 /*! @name CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) */
-#define SPI_CTAR_SLAVE_CPHA_MASK                 (0x2000000U)
-#define SPI_CTAR_SLAVE_CPHA_SHIFT                (25U)
-#define SPI_CTAR_SLAVE_CPHA(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)
-#define SPI_CTAR_SLAVE_CPOL_MASK                 (0x4000000U)
-#define SPI_CTAR_SLAVE_CPOL_SHIFT                (26U)
-#define SPI_CTAR_SLAVE_CPOL(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)
-#define SPI_CTAR_SLAVE_FMSZ_MASK                 (0x78000000U)
-#define SPI_CTAR_SLAVE_FMSZ_SHIFT                (27U)
-#define SPI_CTAR_SLAVE_FMSZ(x)                   (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK)
-
-/* The count of SPI_CTAR_SLAVE */
-#define SPI_CTAR_SLAVE_COUNT                     (1U)
+#define SPIx_CTARn_SLAVE_CPHA_MASK                 (0x2000000U)
+#define SPIx_CTARn_SLAVE_CPHA_SHIFT                (25U)
+#define SPIx_CTARn_SLAVE_CPHA_SET(x)               (((uint32_t)(((uint32_t)(x)) << SPIx_CTARn_SLAVE_CPHA_SHIFT)) & SPIx_CTARn_SLAVE_CPHA_MASK)
+#define SPIx_CTARn_SLAVE_CPHA SPIx_CTARn_SLAVE_CPHA_MASK
+#define SPIx_CTARn_SLAVE_CPOL_MASK                 (0x4000000U)
+#define SPIx_CTARn_SLAVE_CPOL_SHIFT                (26U)
+#define SPIx_CTARn_SLAVE_CPOL_SET(x)               (((uint32_t)(((uint32_t)(x)) << SPIx_CTARn_SLAVE_CPOL_SHIFT)) & SPIx_CTARn_SLAVE_CPOL_MASK)
+#define SPIx_CTARn_SLAVE_CPOL SPIx_CTARn_SLAVE_CPOL_MASK
+#define SPIx_CTARn_SLAVE_FMSZ_MASK                 (0x78000000U)
+#define SPIx_CTARn_SLAVE_FMSZ_SHIFT                (27U)
+#define SPIx_CTARn_SLAVE_FMSZ_SET(x)               (((uint32_t)(((uint32_t)(x)) << SPIx_CTARn_SLAVE_FMSZ_SHIFT)) & SPIx_CTARn_SLAVE_FMSZ_MASK)
+#define SPIx_CTARn_SLAVE_FMSZ SPIx_CTARn_SLAVE_FMSZ_MASK
+
+/* The count of SPIx_CTARn_SLAVE */
+#define SPIx_CTARn_SLAVE_COUNT                     (1U)
 
 /*! @name SR - Status Register */
-#define SPI_SR_POPNXTPTR_MASK                    (0xFU)
-#define SPI_SR_POPNXTPTR_SHIFT                   (0U)
-#define SPI_SR_POPNXTPTR(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK)
-#define SPI_SR_RXCTR_MASK                        (0xF0U)
-#define SPI_SR_RXCTR_SHIFT                       (4U)
-#define SPI_SR_RXCTR(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK)
-#define SPI_SR_TXNXTPTR_MASK                     (0xF00U)
-#define SPI_SR_TXNXTPTR_SHIFT                    (8U)
-#define SPI_SR_TXNXTPTR(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK)
-#define SPI_SR_TXCTR_MASK                        (0xF000U)
-#define SPI_SR_TXCTR_SHIFT                       (12U)
-#define SPI_SR_TXCTR(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK)
-#define SPI_SR_RFDF_MASK                         (0x20000U)
-#define SPI_SR_RFDF_SHIFT                        (17U)
-#define SPI_SR_RFDF(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)
-#define SPI_SR_RFOF_MASK                         (0x80000U)
-#define SPI_SR_RFOF_SHIFT                        (19U)
-#define SPI_SR_RFOF(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)
-#define SPI_SR_TFFF_MASK                         (0x2000000U)
-#define SPI_SR_TFFF_SHIFT                        (25U)
-#define SPI_SR_TFFF(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
-#define SPI_SR_TFUF_MASK                         (0x8000000U)
-#define SPI_SR_TFUF_SHIFT                        (27U)
-#define SPI_SR_TFUF(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)
-#define SPI_SR_EOQF_MASK                         (0x10000000U)
-#define SPI_SR_EOQF_SHIFT                        (28U)
-#define SPI_SR_EOQF(x)                           (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)
-#define SPI_SR_TXRXS_MASK                        (0x40000000U)
-#define SPI_SR_TXRXS_SHIFT                       (30U)
-#define SPI_SR_TXRXS(x)                          (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)
-#define SPI_SR_TCF_MASK                          (0x80000000U)
-#define SPI_SR_TCF_SHIFT                         (31U)
-#define SPI_SR_TCF(x)                            (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)
+#define SPIx_SR_POPNXTPTR_MASK                    (0xFU)
+#define SPIx_SR_POPNXTPTR_SHIFT                   (0U)
+#define SPIx_SR_POPNXTPTR_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SPIx_SR_POPNXTPTR_SHIFT)) & SPIx_SR_POPNXTPTR_MASK)
+#define SPIx_SR_POPNXTPTR SPIx_SR_POPNXTPTR_MASK
+#define SPIx_SR_RXCTR_MASK                        (0xF0U)
+#define SPIx_SR_RXCTR_SHIFT                       (4U)
+#define SPIx_SR_RXCTR_SET(x)                      (((uint32_t)(((uint32_t)(x)) << SPIx_SR_RXCTR_SHIFT)) & SPIx_SR_RXCTR_MASK)
+#define SPIx_SR_RXCTR SPIx_SR_RXCTR_MASK
+#define SPIx_SR_TXNXTPTR_MASK                     (0xF00U)
+#define SPIx_SR_TXNXTPTR_SHIFT                    (8U)
+#define SPIx_SR_TXNXTPTR_SET(x)                   (((uint32_t)(((uint32_t)(x)) << SPIx_SR_TXNXTPTR_SHIFT)) & SPIx_SR_TXNXTPTR_MASK)
+#define SPIx_SR_TXNXTPTR SPIx_SR_TXNXTPTR_MASK
+#define SPIx_SR_TXCTR_MASK                        (0xF000U)
+#define SPIx_SR_TXCTR_SHIFT                       (12U)
+#define SPIx_SR_TXCTR_SET(x)                      (((uint32_t)(((uint32_t)(x)) << SPIx_SR_TXCTR_SHIFT)) & SPIx_SR_TXCTR_MASK)
+#define SPIx_SR_TXCTR SPIx_SR_TXCTR_MASK
+#define SPIx_SR_RFDF_MASK                         (0x20000U)
+#define SPIx_SR_RFDF_SHIFT                        (17U)
+#define SPIx_SR_RFDF_SET(x)                       (((uint32_t)(((uint32_t)(x)) << SPIx_SR_RFDF_SHIFT)) & SPIx_SR_RFDF_MASK)
+#define SPIx_SR_RFDF SPIx_SR_RFDF_MASK
+#define SPIx_SR_RFOF_MASK                         (0x80000U)
+#define SPIx_SR_RFOF_SHIFT                        (19U)
+#define SPIx_SR_RFOF_SET(x)                       (((uint32_t)(((uint32_t)(x)) << SPIx_SR_RFOF_SHIFT)) & SPIx_SR_RFOF_MASK)
+#define SPIx_SR_RFOF SPIx_SR_RFOF_MASK
+#define SPIx_SR_TFFF_MASK                         (0x2000000U)
+#define SPIx_SR_TFFF_SHIFT                        (25U)
+#define SPIx_SR_TFFF_SET(x)                       (((uint32_t)(((uint32_t)(x)) << SPIx_SR_TFFF_SHIFT)) & SPIx_SR_TFFF_MASK)
+#define SPIx_SR_TFFF SPIx_SR_TFFF_MASK
+#define SPIx_SR_TFUF_MASK                         (0x8000000U)
+#define SPIx_SR_TFUF_SHIFT                        (27U)
+#define SPIx_SR_TFUF_SET(x)                       (((uint32_t)(((uint32_t)(x)) << SPIx_SR_TFUF_SHIFT)) & SPIx_SR_TFUF_MASK)
+#define SPIx_SR_TFUF SPIx_SR_TFUF_MASK
+#define SPIx_SR_EOQF_MASK                         (0x10000000U)
+#define SPIx_SR_EOQF_SHIFT                        (28U)
+#define SPIx_SR_EOQF_SET(x)                       (((uint32_t)(((uint32_t)(x)) << SPIx_SR_EOQF_SHIFT)) & SPIx_SR_EOQF_MASK)
+#define SPIx_SR_EOQF SPIx_SR_EOQF_MASK
+#define SPIx_SR_TXRXS_MASK                        (0x40000000U)
+#define SPIx_SR_TXRXS_SHIFT                       (30U)
+#define SPIx_SR_TXRXS_SET(x)                      (((uint32_t)(((uint32_t)(x)) << SPIx_SR_TXRXS_SHIFT)) & SPIx_SR_TXRXS_MASK)
+#define SPIx_SR_TXRXS SPIx_SR_TXRXS_MASK
+#define SPIx_SR_TCF_MASK                          (0x80000000U)
+#define SPIx_SR_TCF_SHIFT                         (31U)
+#define SPIx_SR_TCF_SET(x)                        (((uint32_t)(((uint32_t)(x)) << SPIx_SR_TCF_SHIFT)) & SPIx_SR_TCF_MASK)
+#define SPIx_SR_TCF SPIx_SR_TCF_MASK
 
 /*! @name RSER - DMA/Interrupt Request Select and Enable Register */
-#define SPI_RSER_RFDF_DIRS_MASK                  (0x10000U)
-#define SPI_RSER_RFDF_DIRS_SHIFT                 (16U)
-#define SPI_RSER_RFDF_DIRS(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)
-#define SPI_RSER_RFDF_RE_MASK                    (0x20000U)
-#define SPI_RSER_RFDF_RE_SHIFT                   (17U)
-#define SPI_RSER_RFDF_RE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)
-#define SPI_RSER_RFOF_RE_MASK                    (0x80000U)
-#define SPI_RSER_RFOF_RE_SHIFT                   (19U)
-#define SPI_RSER_RFOF_RE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)
-#define SPI_RSER_TFFF_DIRS_MASK                  (0x1000000U)
-#define SPI_RSER_TFFF_DIRS_SHIFT                 (24U)
-#define SPI_RSER_TFFF_DIRS(x)                    (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)
-#define SPI_RSER_TFFF_RE_MASK                    (0x2000000U)
-#define SPI_RSER_TFFF_RE_SHIFT                   (25U)
-#define SPI_RSER_TFFF_RE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
-#define SPI_RSER_TFUF_RE_MASK                    (0x8000000U)
-#define SPI_RSER_TFUF_RE_SHIFT                   (27U)
-#define SPI_RSER_TFUF_RE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)
-#define SPI_RSER_EOQF_RE_MASK                    (0x10000000U)
-#define SPI_RSER_EOQF_RE_SHIFT                   (28U)
-#define SPI_RSER_EOQF_RE(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)
-#define SPI_RSER_TCF_RE_MASK                     (0x80000000U)
-#define SPI_RSER_TCF_RE_SHIFT                    (31U)
-#define SPI_RSER_TCF_RE(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)
+#define SPIx_RSER_RFDF_DIRS_MASK                  (0x10000U)
+#define SPIx_RSER_RFDF_DIRS_SHIFT                 (16U)
+#define SPIx_RSER_RFDF_DIRS_SET(x)                (((uint32_t)(((uint32_t)(x)) << SPIx_RSER_RFDF_DIRS_SHIFT)) & SPIx_RSER_RFDF_DIRS_MASK)
+#define SPIx_RSER_RFDF_DIRS SPIx_RSER_RFDF_DIRS_MASK
+#define SPIx_RSER_RFDF_RE_MASK                    (0x20000U)
+#define SPIx_RSER_RFDF_RE_SHIFT                   (17U)
+#define SPIx_RSER_RFDF_RE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SPIx_RSER_RFDF_RE_SHIFT)) & SPIx_RSER_RFDF_RE_MASK)
+#define SPIx_RSER_RFDF_RE SPIx_RSER_RFDF_RE_MASK
+#define SPIx_RSER_RFOF_RE_MASK                    (0x80000U)
+#define SPIx_RSER_RFOF_RE_SHIFT                   (19U)
+#define SPIx_RSER_RFOF_RE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SPIx_RSER_RFOF_RE_SHIFT)) & SPIx_RSER_RFOF_RE_MASK)
+#define SPIx_RSER_RFOF_RE SPIx_RSER_RFOF_RE_MASK
+#define SPIx_RSER_TFFF_DIRS_MASK                  (0x1000000U)
+#define SPIx_RSER_TFFF_DIRS_SHIFT                 (24U)
+#define SPIx_RSER_TFFF_DIRS_SET(x)                (((uint32_t)(((uint32_t)(x)) << SPIx_RSER_TFFF_DIRS_SHIFT)) & SPIx_RSER_TFFF_DIRS_MASK)
+#define SPIx_RSER_TFFF_DIRS SPIx_RSER_TFFF_DIRS_MASK
+#define SPIx_RSER_TFFF_RE_MASK                    (0x2000000U)
+#define SPIx_RSER_TFFF_RE_SHIFT                   (25U)
+#define SPIx_RSER_TFFF_RE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SPIx_RSER_TFFF_RE_SHIFT)) & SPIx_RSER_TFFF_RE_MASK)
+#define SPIx_RSER_TFFF_RE SPIx_RSER_TFFF_RE_MASK
+#define SPIx_RSER_TFUF_RE_MASK                    (0x8000000U)
+#define SPIx_RSER_TFUF_RE_SHIFT                   (27U)
+#define SPIx_RSER_TFUF_RE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SPIx_RSER_TFUF_RE_SHIFT)) & SPIx_RSER_TFUF_RE_MASK)
+#define SPIx_RSER_TFUF_RE SPIx_RSER_TFUF_RE_MASK
+#define SPIx_RSER_EOQF_RE_MASK                    (0x10000000U)
+#define SPIx_RSER_EOQF_RE_SHIFT                   (28U)
+#define SPIx_RSER_EOQF_RE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SPIx_RSER_EOQF_RE_SHIFT)) & SPIx_RSER_EOQF_RE_MASK)
+#define SPIx_RSER_EOQF_RE SPIx_RSER_EOQF_RE_MASK
+#define SPIx_RSER_TCF_RE_MASK                     (0x80000000U)
+#define SPIx_RSER_TCF_RE_SHIFT                    (31U)
+#define SPIx_RSER_TCF_RE_SET(x)                   (((uint32_t)(((uint32_t)(x)) << SPIx_RSER_TCF_RE_SHIFT)) & SPIx_RSER_TCF_RE_MASK)
+#define SPIx_RSER_TCF_RE SPIx_RSER_TCF_RE_MASK
 
 /*! @name PUSHR - PUSH TX FIFO Register In Master Mode */
-#define SPI_PUSHR_TXDATA_MASK                    (0xFFFFU)
-#define SPI_PUSHR_TXDATA_SHIFT                   (0U)
-#define SPI_PUSHR_TXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK)
-#define SPI_PUSHR_PCS_MASK                       (0x3F0000U)
-#define SPI_PUSHR_PCS_SHIFT                      (16U)
-#define SPI_PUSHR_PCS(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)
-#define SPI_PUSHR_CTCNT_MASK                     (0x4000000U)
-#define SPI_PUSHR_CTCNT_SHIFT                    (26U)
-#define SPI_PUSHR_CTCNT(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)
-#define SPI_PUSHR_EOQ_MASK                       (0x8000000U)
-#define SPI_PUSHR_EOQ_SHIFT                      (27U)
-#define SPI_PUSHR_EOQ(x)                         (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)
-#define SPI_PUSHR_CTAS_MASK                      (0x70000000U)
-#define SPI_PUSHR_CTAS_SHIFT                     (28U)
-#define SPI_PUSHR_CTAS(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)
-#define SPI_PUSHR_CONT_MASK                      (0x80000000U)
-#define SPI_PUSHR_CONT_SHIFT                     (31U)
-#define SPI_PUSHR_CONT(x)                        (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)
+#define SPIx_PUSHR_TXDATA_MASK                    (0xFFFFU)
+#define SPIx_PUSHR_TXDATA_SHIFT                   (0U)
+#define SPIx_PUSHR_TXDATA(x)                  (((uint32_t)(((uint32_t)(x)) << SPIx_PUSHR_TXDATA_SHIFT)) & SPIx_PUSHR_TXDATA_MASK)
+#define SPIx_PUSHR_PCS_MASK                       (0x3F0000U)
+#define SPIx_PUSHR_PCS_SHIFT                      (16U)
+#define SPIx_PUSHR_PCS(x)                     (((uint32_t)(((uint32_t)(x)) << SPIx_PUSHR_PCS_SHIFT)) & SPIx_PUSHR_PCS_MASK)
+#define SPIx_PUSHR_CTCNT_MASK                     (0x4000000U)
+#define SPIx_PUSHR_CTCNT_SHIFT                    (26U)
+#define SPIx_PUSHR_CTCNT(x)                   (((uint32_t)(((uint32_t)(x)) << SPIx_PUSHR_CTCNT_SHIFT)) & SPIx_PUSHR_CTCNT_MASK)
+#define SPIx_PUSHR_EOQ_MASK                       (0x8000000U)
+#define SPIx_PUSHR_EOQ_SHIFT                      (27U)
+#define SPIx_PUSHR_EOQ(x)                     (((uint32_t)(((uint32_t)(x)) << SPIx_PUSHR_EOQ_SHIFT)) & SPIx_PUSHR_EOQ_MASK)
+#define SPIx_PUSHR_CTAS_MASK                      (0x70000000U)
+#define SPIx_PUSHR_CTAS_SHIFT                     (28U)
+#define SPIx_PUSHR_CTAS(x)                    (((uint32_t)(((uint32_t)(x)) << SPIx_PUSHR_CTAS_SHIFT)) & SPIx_PUSHR_CTAS_MASK)
+#define SPIx_PUSHR_CONT_MASK                      (0x80000000U)
+#define SPIx_PUSHR_CONT_SHIFT                     (31U)
+#define SPIx_PUSHR_CONT(x)                    (((uint32_t)(((uint32_t)(x)) << SPIx_PUSHR_CONT_SHIFT)) & SPIx_PUSHR_CONT_MASK)
 
 /*! @name PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode */
-#define SPI_PUSHR_SLAVE_TXDATA_MASK              (0xFFFFFFFFU)
-#define SPI_PUSHR_SLAVE_TXDATA_SHIFT             (0U)
-#define SPI_PUSHR_SLAVE_TXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK)
+#define SPIx_PUSHR_SLAVE_TXDATA_MASK              (0xFFFFFFFFU)
+#define SPIx_PUSHR_SLAVE_TXDATA_SHIFT             (0U)
+#define SPIx_PUSHR_SLAVE_TXDATA_SET(x)            (((uint32_t)(((uint32_t)(x)) << SPIx_PUSHR_SLAVE_TXDATA_SHIFT)) & SPIx_PUSHR_SLAVE_TXDATA_MASK)
+#define SPIx_PUSHR_SLAVE_TXDATA SPIx_PUSHR_SLAVE_TXDATA_MASK
 
 /*! @name POPR - POP RX FIFO Register */
-#define SPI_POPR_RXDATA_MASK                     (0xFFFFFFFFU)
-#define SPI_POPR_RXDATA_SHIFT                    (0U)
-#define SPI_POPR_RXDATA(x)                       (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK)
+#define SPIx_POPR_RXDATA_MASK                     (0xFFFFFFFFU)
+#define SPIx_POPR_RXDATA_SHIFT                    (0U)
+#define SPIx_POPR_RXDATA_SET(x)                   (((uint32_t)(((uint32_t)(x)) << SPIx_POPR_RXDATA_SHIFT)) & SPIx_POPR_RXDATA_MASK)
+#define SPIx_POPR_RXDATA SPIx_POPR_RXDATA_MASK
 
 /*! @name TXFR0 - Transmit FIFO Registers */
-#define SPI_TXFR0_TXDATA_MASK                    (0xFFFFU)
-#define SPI_TXFR0_TXDATA_SHIFT                   (0U)
-#define SPI_TXFR0_TXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK)
-#define SPI_TXFR0_TXCMD_TXDATA_MASK              (0xFFFF0000U)
-#define SPI_TXFR0_TXCMD_TXDATA_SHIFT             (16U)
-#define SPI_TXFR0_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK)
+#define SPIx_TXFR0_TXDATA_MASK                    (0xFFFFU)
+#define SPIx_TXFR0_TXDATA_SHIFT                   (0U)
+#define SPIx_TXFR0_TXDATA_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SPIx_TXFR0_TXDATA_SHIFT)) & SPIx_TXFR0_TXDATA_MASK)
+#define SPIx_TXFR0_TXDATA SPIx_TXFR0_TXDATA_MASK
+#define SPIx_TXFR0_TXCMD_TXDATA_MASK              (0xFFFF0000U)
+#define SPIx_TXFR0_TXCMD_TXDATA_SHIFT             (16U)
+#define SPIx_TXFR0_TXCMD_TXDATA_SET(x)            (((uint32_t)(((uint32_t)(x)) << SPIx_TXFR0_TXCMD_TXDATA_SHIFT)) & SPIx_TXFR0_TXCMD_TXDATA_MASK)
+#define SPIx_TXFR0_TXCMD_TXDATA SPIx_TXFR0_TXCMD_TXDATA_MASK
 
 /*! @name TXFR1 - Transmit FIFO Registers */
-#define SPI_TXFR1_TXDATA_MASK                    (0xFFFFU)
-#define SPI_TXFR1_TXDATA_SHIFT                   (0U)
-#define SPI_TXFR1_TXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK)
-#define SPI_TXFR1_TXCMD_TXDATA_MASK              (0xFFFF0000U)
-#define SPI_TXFR1_TXCMD_TXDATA_SHIFT             (16U)
-#define SPI_TXFR1_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK)
+#define SPIx_TXFR1_TXDATA_MASK                    (0xFFFFU)
+#define SPIx_TXFR1_TXDATA_SHIFT                   (0U)
+#define SPIx_TXFR1_TXDATA_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SPIx_TXFR1_TXDATA_SHIFT)) & SPIx_TXFR1_TXDATA_MASK)
+#define SPIx_TXFR1_TXDATA SPIx_TXFR1_TXDATA_MASK
+#define SPIx_TXFR1_TXCMD_TXDATA_MASK              (0xFFFF0000U)
+#define SPIx_TXFR1_TXCMD_TXDATA_SHIFT             (16U)
+#define SPIx_TXFR1_TXCMD_TXDATA_SET(x)            (((uint32_t)(((uint32_t)(x)) << SPIx_TXFR1_TXCMD_TXDATA_SHIFT)) & SPIx_TXFR1_TXCMD_TXDATA_MASK)
+#define SPIx_TXFR1_TXCMD_TXDATA SPIx_TXFR1_TXCMD_TXDATA_MASK
 
 /*! @name TXFR2 - Transmit FIFO Registers */
-#define SPI_TXFR2_TXDATA_MASK                    (0xFFFFU)
-#define SPI_TXFR2_TXDATA_SHIFT                   (0U)
-#define SPI_TXFR2_TXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK)
-#define SPI_TXFR2_TXCMD_TXDATA_MASK              (0xFFFF0000U)
-#define SPI_TXFR2_TXCMD_TXDATA_SHIFT             (16U)
-#define SPI_TXFR2_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK)
+#define SPIx_TXFR2_TXDATA_MASK                    (0xFFFFU)
+#define SPIx_TXFR2_TXDATA_SHIFT                   (0U)
+#define SPIx_TXFR2_TXDATA_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SPIx_TXFR2_TXDATA_SHIFT)) & SPIx_TXFR2_TXDATA_MASK)
+#define SPIx_TXFR2_TXDATA SPIx_TXFR2_TXDATA_MASK
+#define SPIx_TXFR2_TXCMD_TXDATA_MASK              (0xFFFF0000U)
+#define SPIx_TXFR2_TXCMD_TXDATA_SHIFT             (16U)
+#define SPIx_TXFR2_TXCMD_TXDATA_SET(x)            (((uint32_t)(((uint32_t)(x)) << SPIx_TXFR2_TXCMD_TXDATA_SHIFT)) & SPIx_TXFR2_TXCMD_TXDATA_MASK)
+#define SPIx_TXFR2_TXCMD_TXDATA SPIx_TXFR2_TXCMD_TXDATA_MASK
 
 /*! @name TXFR3 - Transmit FIFO Registers */
-#define SPI_TXFR3_TXDATA_MASK                    (0xFFFFU)
-#define SPI_TXFR3_TXDATA_SHIFT                   (0U)
-#define SPI_TXFR3_TXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK)
-#define SPI_TXFR3_TXCMD_TXDATA_MASK              (0xFFFF0000U)
-#define SPI_TXFR3_TXCMD_TXDATA_SHIFT             (16U)
-#define SPI_TXFR3_TXCMD_TXDATA(x)                (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK)
+#define SPIx_TXFR3_TXDATA_MASK                    (0xFFFFU)
+#define SPIx_TXFR3_TXDATA_SHIFT                   (0U)
+#define SPIx_TXFR3_TXDATA_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SPIx_TXFR3_TXDATA_SHIFT)) & SPIx_TXFR3_TXDATA_MASK)
+#define SPIx_TXFR3_TXDATA SPIx_TXFR3_TXDATA_MASK
+#define SPIx_TXFR3_TXCMD_TXDATA_MASK              (0xFFFF0000U)
+#define SPIx_TXFR3_TXCMD_TXDATA_SHIFT             (16U)
+#define SPIx_TXFR3_TXCMD_TXDATA_SET(x)            (((uint32_t)(((uint32_t)(x)) << SPIx_TXFR3_TXCMD_TXDATA_SHIFT)) & SPIx_TXFR3_TXCMD_TXDATA_MASK)
+#define SPIx_TXFR3_TXCMD_TXDATA SPIx_TXFR3_TXCMD_TXDATA_MASK
 
 /*! @name RXFR0 - Receive FIFO Registers */
-#define SPI_RXFR0_RXDATA_MASK                    (0xFFFFFFFFU)
-#define SPI_RXFR0_RXDATA_SHIFT                   (0U)
-#define SPI_RXFR0_RXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK)
+#define SPIx_RXFR0_RXDATA_MASK                    (0xFFFFFFFFU)
+#define SPIx_RXFR0_RXDATA_SHIFT                   (0U)
+#define SPIx_RXFR0_RXDATA_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SPIx_RXFR0_RXDATA_SHIFT)) & SPIx_RXFR0_RXDATA_MASK)
+#define SPIx_RXFR0_RXDATA SPIx_RXFR0_RXDATA_MASK
 
 /*! @name RXFR1 - Receive FIFO Registers */
-#define SPI_RXFR1_RXDATA_MASK                    (0xFFFFFFFFU)
-#define SPI_RXFR1_RXDATA_SHIFT                   (0U)
-#define SPI_RXFR1_RXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK)
+#define SPIx_RXFR1_RXDATA_MASK                    (0xFFFFFFFFU)
+#define SPIx_RXFR1_RXDATA_SHIFT                   (0U)
+#define SPIx_RXFR1_RXDATA_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SPIx_RXFR1_RXDATA_SHIFT)) & SPIx_RXFR1_RXDATA_MASK)
+#define SPIx_RXFR1_RXDATA SPIx_RXFR1_RXDATA_MASK
 
 /*! @name RXFR2 - Receive FIFO Registers */
-#define SPI_RXFR2_RXDATA_MASK                    (0xFFFFFFFFU)
-#define SPI_RXFR2_RXDATA_SHIFT                   (0U)
-#define SPI_RXFR2_RXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK)
+#define SPIx_RXFR2_RXDATA_MASK                    (0xFFFFFFFFU)
+#define SPIx_RXFR2_RXDATA_SHIFT                   (0U)
+#define SPIx_RXFR2_RXDATA_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SPIx_RXFR2_RXDATA_SHIFT)) & SPIx_RXFR2_RXDATA_MASK)
+#define SPIx_RXFR2_RXDATA SPIx_RXFR2_RXDATA_MASK
 
 /*! @name RXFR3 - Receive FIFO Registers */
-#define SPI_RXFR3_RXDATA_MASK                    (0xFFFFFFFFU)
-#define SPI_RXFR3_RXDATA_SHIFT                   (0U)
-#define SPI_RXFR3_RXDATA(x)                      (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK)
+#define SPIx_RXFR3_RXDATA_MASK                    (0xFFFFFFFFU)
+#define SPIx_RXFR3_RXDATA_SHIFT                   (0U)
+#define SPIx_RXFR3_RXDATA_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SPIx_RXFR3_RXDATA_SHIFT)) & SPIx_RXFR3_RXDATA_MASK)
+#define SPIx_RXFR3_RXDATA SPIx_RXFR3_RXDATA_MASK
 
 
 /*!
  * @}
- */ /* end of group SPI_Register_Masks */
+ */ /* end of group SPIx_Register_Masks */
 
 
 /* SPI - Peripheral instance base addresses */
 /** Peripheral SPI0 base address */
 #define SPI0_BASE                                (0x4002C000u)
 /** Peripheral SPI0 base pointer */
-#define SPI0                                     ((SPI_Type *)SPI0_BASE)
+#define SPI0                                     ((SPI_TypeDef *)SPI0_BASE)
 /** Peripheral SPI1 base address */
 #define SPI1_BASE                                (0x4002D000u)
 /** Peripheral SPI1 base pointer */
-#define SPI1                                     ((SPI_Type *)SPI1_BASE)
+#define SPI1                                     ((SPI_TypeDef *)SPI1_BASE)
 /** Peripheral SPI2 base address */
 #define SPI2_BASE                                (0x400AC000u)
 /** Peripheral SPI2 base pointer */
-#define SPI2                                     ((SPI_Type *)SPI2_BASE)
+#define SPI2                                     ((SPI_TypeDef *)SPI2_BASE)
 /** Array initializer of SPI peripheral base addresses */
-#define SPI_BASE_ADDRS                           { SPI0_BASE, SPI1_BASE, SPI2_BASE }
+#define SPIx_BASE_ADDRS                           { SPI0_BASE, SPI1_BASE, SPI2_BASE }
 /** Array initializer of SPI peripheral base pointers */
-#define SPI_BASE_PTRS                            { SPI0, SPI1, SPI2 }
+#define SPIx_BASE_PTRS                            { SPI0, SPI1, SPI2 }
 /** Interrupt vectors for the SPI peripheral type */
-#define SPI_IRQS                                 { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }
+#define SPIx_IRQS                                 { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }
 
 /*!
  * @}
- */ /* end of group SPI_Peripheral_Access_Layer */
+ */ /* end of group SPIx_Peripheral_Access_Layer */
 
 
 /* ----------------------------------------------------------------------------
@@ -13066,7 +15785,7 @@ typedef struct {
   __IO uint32_t WORD[12][4];                       /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
        uint8_t RESERVED_2[832];
   __IO uint32_t RGDAAC[12];                        /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
-} SYSMPU_Type;
+} SYSMPU_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- SYSMPU Register Masks
@@ -13080,24 +15799,30 @@ typedef struct {
 /*! @name CESR - Control/Error Status Register */
 #define SYSMPU_CESR_VLD_MASK                     (0x1U)
 #define SYSMPU_CESR_VLD_SHIFT                    (0U)
-#define SYSMPU_CESR_VLD(x)                       (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_VLD_SHIFT)) & SYSMPU_CESR_VLD_MASK)
+#define SYSMPU_CESR_VLD_SET(x)                   (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_VLD_SHIFT)) & SYSMPU_CESR_VLD_MASK)
+#define SYSMPU_CESR_VLD SYSMPU_CESR_VLD_MASK
 #define SYSMPU_CESR_NRGD_MASK                    (0xF00U)
 #define SYSMPU_CESR_NRGD_SHIFT                   (8U)
-#define SYSMPU_CESR_NRGD(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NRGD_SHIFT)) & SYSMPU_CESR_NRGD_MASK)
+#define SYSMPU_CESR_NRGD_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NRGD_SHIFT)) & SYSMPU_CESR_NRGD_MASK)
+#define SYSMPU_CESR_NRGD SYSMPU_CESR_NRGD_MASK
 #define SYSMPU_CESR_NSP_MASK                     (0xF000U)
 #define SYSMPU_CESR_NSP_SHIFT                    (12U)
-#define SYSMPU_CESR_NSP(x)                       (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NSP_SHIFT)) & SYSMPU_CESR_NSP_MASK)
+#define SYSMPU_CESR_NSP_SET(x)                   (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NSP_SHIFT)) & SYSMPU_CESR_NSP_MASK)
+#define SYSMPU_CESR_NSP SYSMPU_CESR_NSP_MASK
 #define SYSMPU_CESR_HRL_MASK                     (0xF0000U)
 #define SYSMPU_CESR_HRL_SHIFT                    (16U)
-#define SYSMPU_CESR_HRL(x)                       (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_HRL_SHIFT)) & SYSMPU_CESR_HRL_MASK)
+#define SYSMPU_CESR_HRL_SET(x)                   (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_HRL_SHIFT)) & SYSMPU_CESR_HRL_MASK)
+#define SYSMPU_CESR_HRL SYSMPU_CESR_HRL_MASK
 #define SYSMPU_CESR_SPERR_MASK                   (0xF8000000U)
 #define SYSMPU_CESR_SPERR_SHIFT                  (27U)
-#define SYSMPU_CESR_SPERR(x)                     (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_SPERR_SHIFT)) & SYSMPU_CESR_SPERR_MASK)
+#define SYSMPU_CESR_SPERR_SET(x)                 (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_SPERR_SHIFT)) & SYSMPU_CESR_SPERR_MASK)
+#define SYSMPU_CESR_SPERR SYSMPU_CESR_SPERR_MASK
 
 /*! @name EAR - Error Address Register, slave port n */
 #define SYSMPU_EAR_EADDR_MASK                    (0xFFFFFFFFU)
 #define SYSMPU_EAR_EADDR_SHIFT                   (0U)
-#define SYSMPU_EAR_EADDR(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_EAR_EADDR_SHIFT)) & SYSMPU_EAR_EADDR_MASK)
+#define SYSMPU_EAR_EADDR_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SYSMPU_EAR_EADDR_SHIFT)) & SYSMPU_EAR_EADDR_MASK)
+#define SYSMPU_EAR_EADDR SYSMPU_EAR_EADDR_MASK
 
 /* The count of SYSMPU_EAR */
 #define SYSMPU_EAR_COUNT                         (5U)
@@ -13105,19 +15830,24 @@ typedef struct {
 /*! @name EDR - Error Detail Register, slave port n */
 #define SYSMPU_EDR_ERW_MASK                      (0x1U)
 #define SYSMPU_EDR_ERW_SHIFT                     (0U)
-#define SYSMPU_EDR_ERW(x)                        (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_ERW_SHIFT)) & SYSMPU_EDR_ERW_MASK)
+#define SYSMPU_EDR_ERW_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_ERW_SHIFT)) & SYSMPU_EDR_ERW_MASK)
+#define SYSMPU_EDR_ERW SYSMPU_EDR_ERW_MASK
 #define SYSMPU_EDR_EATTR_MASK                    (0xEU)
 #define SYSMPU_EDR_EATTR_SHIFT                   (1U)
-#define SYSMPU_EDR_EATTR(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EATTR_SHIFT)) & SYSMPU_EDR_EATTR_MASK)
+#define SYSMPU_EDR_EATTR_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EATTR_SHIFT)) & SYSMPU_EDR_EATTR_MASK)
+#define SYSMPU_EDR_EATTR SYSMPU_EDR_EATTR_MASK
 #define SYSMPU_EDR_EMN_MASK                      (0xF0U)
 #define SYSMPU_EDR_EMN_SHIFT                     (4U)
-#define SYSMPU_EDR_EMN(x)                        (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EMN_SHIFT)) & SYSMPU_EDR_EMN_MASK)
+#define SYSMPU_EDR_EMN_SET(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EMN_SHIFT)) & SYSMPU_EDR_EMN_MASK)
+#define SYSMPU_EDR_EMN SYSMPU_EDR_EMN_MASK
 #define SYSMPU_EDR_EPID_MASK                     (0xFF00U)
 #define SYSMPU_EDR_EPID_SHIFT                    (8U)
-#define SYSMPU_EDR_EPID(x)                       (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EPID_SHIFT)) & SYSMPU_EDR_EPID_MASK)
+#define SYSMPU_EDR_EPID_SET(x)                   (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EPID_SHIFT)) & SYSMPU_EDR_EPID_MASK)
+#define SYSMPU_EDR_EPID SYSMPU_EDR_EPID_MASK
 #define SYSMPU_EDR_EACD_MASK                     (0xFFFF0000U)
 #define SYSMPU_EDR_EACD_SHIFT                    (16U)
-#define SYSMPU_EDR_EACD(x)                       (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EACD_SHIFT)) & SYSMPU_EDR_EACD_MASK)
+#define SYSMPU_EDR_EACD_SET(x)                   (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EACD_SHIFT)) & SYSMPU_EDR_EACD_MASK)
+#define SYSMPU_EDR_EACD SYSMPU_EDR_EACD_MASK
 
 /* The count of SYSMPU_EDR */
 #define SYSMPU_EDR_COUNT                         (5U)
@@ -13125,79 +15855,104 @@ typedef struct {
 /*! @name WORD - Region Descriptor n, Word 0..Region Descriptor n, Word 3 */
 #define SYSMPU_WORD_VLD_MASK                     (0x1U)
 #define SYSMPU_WORD_VLD_SHIFT                    (0U)
-#define SYSMPU_WORD_VLD(x)                       (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_VLD_SHIFT)) & SYSMPU_WORD_VLD_MASK)
+#define SYSMPU_WORD_VLD_SET(x)                   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_VLD_SHIFT)) & SYSMPU_WORD_VLD_MASK)
+#define SYSMPU_WORD_VLD SYSMPU_WORD_VLD_MASK
 #define SYSMPU_WORD_M0UM_MASK                    (0x7U)
 #define SYSMPU_WORD_M0UM_SHIFT                   (0U)
-#define SYSMPU_WORD_M0UM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0UM_SHIFT)) & SYSMPU_WORD_M0UM_MASK)
+#define SYSMPU_WORD_M0UM_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0UM_SHIFT)) & SYSMPU_WORD_M0UM_MASK)
+#define SYSMPU_WORD_M0UM SYSMPU_WORD_M0UM_MASK
 #define SYSMPU_WORD_M0SM_MASK                    (0x18U)
 #define SYSMPU_WORD_M0SM_SHIFT                   (3U)
-#define SYSMPU_WORD_M0SM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0SM_SHIFT)) & SYSMPU_WORD_M0SM_MASK)
+#define SYSMPU_WORD_M0SM_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0SM_SHIFT)) & SYSMPU_WORD_M0SM_MASK)
+#define SYSMPU_WORD_M0SM SYSMPU_WORD_M0SM_MASK
 #define SYSMPU_WORD_M0PE_MASK                    (0x20U)
 #define SYSMPU_WORD_M0PE_SHIFT                   (5U)
-#define SYSMPU_WORD_M0PE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0PE_SHIFT)) & SYSMPU_WORD_M0PE_MASK)
+#define SYSMPU_WORD_M0PE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0PE_SHIFT)) & SYSMPU_WORD_M0PE_MASK)
+#define SYSMPU_WORD_M0PE SYSMPU_WORD_M0PE_MASK
 #define SYSMPU_WORD_ENDADDR_MASK                 (0xFFFFFFE0U)
 #define SYSMPU_WORD_ENDADDR_SHIFT                (5U)
-#define SYSMPU_WORD_ENDADDR(x)                   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_ENDADDR_SHIFT)) & SYSMPU_WORD_ENDADDR_MASK)
+#define SYSMPU_WORD_ENDADDR_SET(x)               (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_ENDADDR_SHIFT)) & SYSMPU_WORD_ENDADDR_MASK)
+#define SYSMPU_WORD_ENDADDR SYSMPU_WORD_ENDADDR_MASK
 #define SYSMPU_WORD_SRTADDR_MASK                 (0xFFFFFFE0U)
 #define SYSMPU_WORD_SRTADDR_SHIFT                (5U)
-#define SYSMPU_WORD_SRTADDR(x)                   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_SRTADDR_SHIFT)) & SYSMPU_WORD_SRTADDR_MASK)
+#define SYSMPU_WORD_SRTADDR_SET(x)               (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_SRTADDR_SHIFT)) & SYSMPU_WORD_SRTADDR_MASK)
+#define SYSMPU_WORD_SRTADDR SYSMPU_WORD_SRTADDR_MASK
 #define SYSMPU_WORD_M1UM_MASK                    (0x1C0U)
 #define SYSMPU_WORD_M1UM_SHIFT                   (6U)
-#define SYSMPU_WORD_M1UM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1UM_SHIFT)) & SYSMPU_WORD_M1UM_MASK)
+#define SYSMPU_WORD_M1UM_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1UM_SHIFT)) & SYSMPU_WORD_M1UM_MASK)
+#define SYSMPU_WORD_M1UM SYSMPU_WORD_M1UM_MASK
 #define SYSMPU_WORD_M1SM_MASK                    (0x600U)
 #define SYSMPU_WORD_M1SM_SHIFT                   (9U)
-#define SYSMPU_WORD_M1SM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1SM_SHIFT)) & SYSMPU_WORD_M1SM_MASK)
+#define SYSMPU_WORD_M1SM_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1SM_SHIFT)) & SYSMPU_WORD_M1SM_MASK)
+#define SYSMPU_WORD_M1SM SYSMPU_WORD_M1SM_MASK
 #define SYSMPU_WORD_M1PE_MASK                    (0x800U)
 #define SYSMPU_WORD_M1PE_SHIFT                   (11U)
-#define SYSMPU_WORD_M1PE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1PE_SHIFT)) & SYSMPU_WORD_M1PE_MASK)
+#define SYSMPU_WORD_M1PE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1PE_SHIFT)) & SYSMPU_WORD_M1PE_MASK)
+#define SYSMPU_WORD_M1PE SYSMPU_WORD_M1PE_MASK
 #define SYSMPU_WORD_M2UM_MASK                    (0x7000U)
 #define SYSMPU_WORD_M2UM_SHIFT                   (12U)
-#define SYSMPU_WORD_M2UM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2UM_SHIFT)) & SYSMPU_WORD_M2UM_MASK)
+#define SYSMPU_WORD_M2UM_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2UM_SHIFT)) & SYSMPU_WORD_M2UM_MASK)
+#define SYSMPU_WORD_M2UM SYSMPU_WORD_M2UM_MASK
 #define SYSMPU_WORD_M2SM_MASK                    (0x18000U)
 #define SYSMPU_WORD_M2SM_SHIFT                   (15U)
-#define SYSMPU_WORD_M2SM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2SM_SHIFT)) & SYSMPU_WORD_M2SM_MASK)
+#define SYSMPU_WORD_M2SM_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2SM_SHIFT)) & SYSMPU_WORD_M2SM_MASK)
+#define SYSMPU_WORD_M2SM SYSMPU_WORD_M2SM_MASK
 #define SYSMPU_WORD_PIDMASK_MASK                 (0xFF0000U)
 #define SYSMPU_WORD_PIDMASK_SHIFT                (16U)
-#define SYSMPU_WORD_PIDMASK(x)                   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PIDMASK_SHIFT)) & SYSMPU_WORD_PIDMASK_MASK)
+#define SYSMPU_WORD_PIDMASK_SET(x)               (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PIDMASK_SHIFT)) & SYSMPU_WORD_PIDMASK_MASK)
+#define SYSMPU_WORD_PIDMASK SYSMPU_WORD_PIDMASK_MASK
 #define SYSMPU_WORD_M2PE_MASK                    (0x20000U)
 #define SYSMPU_WORD_M2PE_SHIFT                   (17U)
-#define SYSMPU_WORD_M2PE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2PE_SHIFT)) & SYSMPU_WORD_M2PE_MASK)
+#define SYSMPU_WORD_M2PE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2PE_SHIFT)) & SYSMPU_WORD_M2PE_MASK)
+#define SYSMPU_WORD_M2PE SYSMPU_WORD_M2PE_MASK
 #define SYSMPU_WORD_M3UM_MASK                    (0x1C0000U)
 #define SYSMPU_WORD_M3UM_SHIFT                   (18U)
-#define SYSMPU_WORD_M3UM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3UM_SHIFT)) & SYSMPU_WORD_M3UM_MASK)
+#define SYSMPU_WORD_M3UM_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3UM_SHIFT)) & SYSMPU_WORD_M3UM_MASK)
+#define SYSMPU_WORD_M3UM SYSMPU_WORD_M3UM_MASK
 #define SYSMPU_WORD_M3SM_MASK                    (0x600000U)
 #define SYSMPU_WORD_M3SM_SHIFT                   (21U)
-#define SYSMPU_WORD_M3SM(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3SM_SHIFT)) & SYSMPU_WORD_M3SM_MASK)
+#define SYSMPU_WORD_M3SM_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3SM_SHIFT)) & SYSMPU_WORD_M3SM_MASK)
+#define SYSMPU_WORD_M3SM SYSMPU_WORD_M3SM_MASK
 #define SYSMPU_WORD_M3PE_MASK                    (0x800000U)
 #define SYSMPU_WORD_M3PE_SHIFT                   (23U)
-#define SYSMPU_WORD_M3PE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3PE_SHIFT)) & SYSMPU_WORD_M3PE_MASK)
+#define SYSMPU_WORD_M3PE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3PE_SHIFT)) & SYSMPU_WORD_M3PE_MASK)
+#define SYSMPU_WORD_M3PE SYSMPU_WORD_M3PE_MASK
 #define SYSMPU_WORD_PID_MASK                     (0xFF000000U)
 #define SYSMPU_WORD_PID_SHIFT                    (24U)
-#define SYSMPU_WORD_PID(x)                       (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PID_SHIFT)) & SYSMPU_WORD_PID_MASK)
+#define SYSMPU_WORD_PID_SET(x)                   (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PID_SHIFT)) & SYSMPU_WORD_PID_MASK)
+#define SYSMPU_WORD_PID SYSMPU_WORD_PID_MASK
 #define SYSMPU_WORD_M4WE_MASK                    (0x1000000U)
 #define SYSMPU_WORD_M4WE_SHIFT                   (24U)
-#define SYSMPU_WORD_M4WE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4WE_SHIFT)) & SYSMPU_WORD_M4WE_MASK)
+#define SYSMPU_WORD_M4WE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4WE_SHIFT)) & SYSMPU_WORD_M4WE_MASK)
+#define SYSMPU_WORD_M4WE SYSMPU_WORD_M4WE_MASK
 #define SYSMPU_WORD_M4RE_MASK                    (0x2000000U)
 #define SYSMPU_WORD_M4RE_SHIFT                   (25U)
-#define SYSMPU_WORD_M4RE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4RE_SHIFT)) & SYSMPU_WORD_M4RE_MASK)
+#define SYSMPU_WORD_M4RE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4RE_SHIFT)) & SYSMPU_WORD_M4RE_MASK)
+#define SYSMPU_WORD_M4RE SYSMPU_WORD_M4RE_MASK
 #define SYSMPU_WORD_M5WE_MASK                    (0x4000000U)
 #define SYSMPU_WORD_M5WE_SHIFT                   (26U)
-#define SYSMPU_WORD_M5WE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5WE_SHIFT)) & SYSMPU_WORD_M5WE_MASK)
+#define SYSMPU_WORD_M5WE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5WE_SHIFT)) & SYSMPU_WORD_M5WE_MASK)
+#define SYSMPU_WORD_M5WE SYSMPU_WORD_M5WE_MASK
 #define SYSMPU_WORD_M5RE_MASK                    (0x8000000U)
 #define SYSMPU_WORD_M5RE_SHIFT                   (27U)
-#define SYSMPU_WORD_M5RE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5RE_SHIFT)) & SYSMPU_WORD_M5RE_MASK)
+#define SYSMPU_WORD_M5RE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5RE_SHIFT)) & SYSMPU_WORD_M5RE_MASK)
+#define SYSMPU_WORD_M5RE SYSMPU_WORD_M5RE_MASK
 #define SYSMPU_WORD_M6WE_MASK                    (0x10000000U)
 #define SYSMPU_WORD_M6WE_SHIFT                   (28U)
-#define SYSMPU_WORD_M6WE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6WE_SHIFT)) & SYSMPU_WORD_M6WE_MASK)
+#define SYSMPU_WORD_M6WE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6WE_SHIFT)) & SYSMPU_WORD_M6WE_MASK)
+#define SYSMPU_WORD_M6WE SYSMPU_WORD_M6WE_MASK
 #define SYSMPU_WORD_M6RE_MASK                    (0x20000000U)
 #define SYSMPU_WORD_M6RE_SHIFT                   (29U)
-#define SYSMPU_WORD_M6RE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6RE_SHIFT)) & SYSMPU_WORD_M6RE_MASK)
+#define SYSMPU_WORD_M6RE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6RE_SHIFT)) & SYSMPU_WORD_M6RE_MASK)
+#define SYSMPU_WORD_M6RE SYSMPU_WORD_M6RE_MASK
 #define SYSMPU_WORD_M7WE_MASK                    (0x40000000U)
 #define SYSMPU_WORD_M7WE_SHIFT                   (30U)
-#define SYSMPU_WORD_M7WE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7WE_SHIFT)) & SYSMPU_WORD_M7WE_MASK)
+#define SYSMPU_WORD_M7WE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7WE_SHIFT)) & SYSMPU_WORD_M7WE_MASK)
+#define SYSMPU_WORD_M7WE SYSMPU_WORD_M7WE_MASK
 #define SYSMPU_WORD_M7RE_MASK                    (0x80000000U)
 #define SYSMPU_WORD_M7RE_SHIFT                   (31U)
-#define SYSMPU_WORD_M7RE(x)                      (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7RE_SHIFT)) & SYSMPU_WORD_M7RE_MASK)
+#define SYSMPU_WORD_M7RE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7RE_SHIFT)) & SYSMPU_WORD_M7RE_MASK)
+#define SYSMPU_WORD_M7RE SYSMPU_WORD_M7RE_MASK
 
 /* The count of SYSMPU_WORD */
 #define SYSMPU_WORD_COUNT                        (12U)
@@ -13208,64 +15963,84 @@ typedef struct {
 /*! @name RGDAAC - Region Descriptor Alternate Access Control n */
 #define SYSMPU_RGDAAC_M0UM_MASK                  (0x7U)
 #define SYSMPU_RGDAAC_M0UM_SHIFT                 (0U)
-#define SYSMPU_RGDAAC_M0UM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0UM_SHIFT)) & SYSMPU_RGDAAC_M0UM_MASK)
+#define SYSMPU_RGDAAC_M0UM_SET(x)                (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0UM_SHIFT)) & SYSMPU_RGDAAC_M0UM_MASK)
+#define SYSMPU_RGDAAC_M0UM SYSMPU_RGDAAC_M0UM_MASK
 #define SYSMPU_RGDAAC_M0SM_MASK                  (0x18U)
 #define SYSMPU_RGDAAC_M0SM_SHIFT                 (3U)
-#define SYSMPU_RGDAAC_M0SM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0SM_SHIFT)) & SYSMPU_RGDAAC_M0SM_MASK)
+#define SYSMPU_RGDAAC_M0SM_SET(x)                (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0SM_SHIFT)) & SYSMPU_RGDAAC_M0SM_MASK)
+#define SYSMPU_RGDAAC_M0SM SYSMPU_RGDAAC_M0SM_MASK
 #define SYSMPU_RGDAAC_M0PE_MASK                  (0x20U)
 #define SYSMPU_RGDAAC_M0PE_SHIFT                 (5U)
-#define SYSMPU_RGDAAC_M0PE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0PE_SHIFT)) & SYSMPU_RGDAAC_M0PE_MASK)
+#define SYSMPU_RGDAAC_M0PE_SET(x)                (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0PE_SHIFT)) & SYSMPU_RGDAAC_M0PE_MASK)
+#define SYSMPU_RGDAAC_M0PE SYSMPU_RGDAAC_M0PE_MASK
 #define SYSMPU_RGDAAC_M1UM_MASK                  (0x1C0U)
 #define SYSMPU_RGDAAC_M1UM_SHIFT                 (6U)
-#define SYSMPU_RGDAAC_M1UM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1UM_SHIFT)) & SYSMPU_RGDAAC_M1UM_MASK)
+#define SYSMPU_RGDAAC_M1UM_SET(x)                (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1UM_SHIFT)) & SYSMPU_RGDAAC_M1UM_MASK)
+#define SYSMPU_RGDAAC_M1UM SYSMPU_RGDAAC_M1UM_MASK
 #define SYSMPU_RGDAAC_M1SM_MASK                  (0x600U)
 #define SYSMPU_RGDAAC_M1SM_SHIFT                 (9U)
-#define SYSMPU_RGDAAC_M1SM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1SM_SHIFT)) & SYSMPU_RGDAAC_M1SM_MASK)
+#define SYSMPU_RGDAAC_M1SM_SET(x)                (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1SM_SHIFT)) & SYSMPU_RGDAAC_M1SM_MASK)
+#define SYSMPU_RGDAAC_M1SM SYSMPU_RGDAAC_M1SM_MASK
 #define SYSMPU_RGDAAC_M1PE_MASK                  (0x800U)
 #define SYSMPU_RGDAAC_M1PE_SHIFT                 (11U)
-#define SYSMPU_RGDAAC_M1PE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1PE_SHIFT)) & SYSMPU_RGDAAC_M1PE_MASK)
+#define SYSMPU_RGDAAC_M1PE_SET(x)                (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1PE_SHIFT)) & SYSMPU_RGDAAC_M1PE_MASK)
+#define SYSMPU_RGDAAC_M1PE SYSMPU_RGDAAC_M1PE_MASK
 #define SYSMPU_RGDAAC_M2UM_MASK                  (0x7000U)
 #define SYSMPU_RGDAAC_M2UM_SHIFT                 (12U)
-#define SYSMPU_RGDAAC_M2UM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2UM_SHIFT)) & SYSMPU_RGDAAC_M2UM_MASK)
+#define SYSMPU_RGDAAC_M2UM_SET(x)                (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2UM_SHIFT)) & SYSMPU_RGDAAC_M2UM_MASK)
+#define SYSMPU_RGDAAC_M2UM SYSMPU_RGDAAC_M2UM_MASK
 #define SYSMPU_RGDAAC_M2SM_MASK                  (0x18000U)
 #define SYSMPU_RGDAAC_M2SM_SHIFT                 (15U)
-#define SYSMPU_RGDAAC_M2SM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2SM_SHIFT)) & SYSMPU_RGDAAC_M2SM_MASK)
+#define SYSMPU_RGDAAC_M2SM_SET(x)                (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2SM_SHIFT)) & SYSMPU_RGDAAC_M2SM_MASK)
+#define SYSMPU_RGDAAC_M2SM SYSMPU_RGDAAC_M2SM_MASK
 #define SYSMPU_RGDAAC_M2PE_MASK                  (0x20000U)
 #define SYSMPU_RGDAAC_M2PE_SHIFT                 (17U)
-#define SYSMPU_RGDAAC_M2PE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2PE_SHIFT)) & SYSMPU_RGDAAC_M2PE_MASK)
+#define SYSMPU_RGDAAC_M2PE_SET(x)                (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2PE_SHIFT)) & SYSMPU_RGDAAC_M2PE_MASK)
+#define SYSMPU_RGDAAC_M2PE SYSMPU_RGDAAC_M2PE_MASK
 #define SYSMPU_RGDAAC_M3UM_MASK                  (0x1C0000U)
 #define SYSMPU_RGDAAC_M3UM_SHIFT                 (18U)
-#define SYSMPU_RGDAAC_M3UM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3UM_SHIFT)) & SYSMPU_RGDAAC_M3UM_MASK)
+#define SYSMPU_RGDAAC_M3UM_SET(x)                (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3UM_SHIFT)) & SYSMPU_RGDAAC_M3UM_MASK)
+#define SYSMPU_RGDAAC_M3UM SYSMPU_RGDAAC_M3UM_MASK
 #define SYSMPU_RGDAAC_M3SM_MASK                  (0x600000U)
 #define SYSMPU_RGDAAC_M3SM_SHIFT                 (21U)
-#define SYSMPU_RGDAAC_M3SM(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3SM_SHIFT)) & SYSMPU_RGDAAC_M3SM_MASK)
+#define SYSMPU_RGDAAC_M3SM_SET(x)                (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3SM_SHIFT)) & SYSMPU_RGDAAC_M3SM_MASK)
+#define SYSMPU_RGDAAC_M3SM SYSMPU_RGDAAC_M3SM_MASK
 #define SYSMPU_RGDAAC_M3PE_MASK                  (0x800000U)
 #define SYSMPU_RGDAAC_M3PE_SHIFT                 (23U)
-#define SYSMPU_RGDAAC_M3PE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3PE_SHIFT)) & SYSMPU_RGDAAC_M3PE_MASK)
+#define SYSMPU_RGDAAC_M3PE_SET(x)                (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3PE_SHIFT)) & SYSMPU_RGDAAC_M3PE_MASK)
+#define SYSMPU_RGDAAC_M3PE SYSMPU_RGDAAC_M3PE_MASK
 #define SYSMPU_RGDAAC_M4WE_MASK                  (0x1000000U)
 #define SYSMPU_RGDAAC_M4WE_SHIFT                 (24U)
-#define SYSMPU_RGDAAC_M4WE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4WE_SHIFT)) & SYSMPU_RGDAAC_M4WE_MASK)
+#define SYSMPU_RGDAAC_M4WE_SET(x)                (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4WE_SHIFT)) & SYSMPU_RGDAAC_M4WE_MASK)
+#define SYSMPU_RGDAAC_M4WE SYSMPU_RGDAAC_M4WE_MASK
 #define SYSMPU_RGDAAC_M4RE_MASK                  (0x2000000U)
 #define SYSMPU_RGDAAC_M4RE_SHIFT                 (25U)
-#define SYSMPU_RGDAAC_M4RE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4RE_SHIFT)) & SYSMPU_RGDAAC_M4RE_MASK)
+#define SYSMPU_RGDAAC_M4RE_SET(x)                (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4RE_SHIFT)) & SYSMPU_RGDAAC_M4RE_MASK)
+#define SYSMPU_RGDAAC_M4RE SYSMPU_RGDAAC_M4RE_MASK
 #define SYSMPU_RGDAAC_M5WE_MASK                  (0x4000000U)
 #define SYSMPU_RGDAAC_M5WE_SHIFT                 (26U)
-#define SYSMPU_RGDAAC_M5WE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5WE_SHIFT)) & SYSMPU_RGDAAC_M5WE_MASK)
+#define SYSMPU_RGDAAC_M5WE_SET(x)                (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5WE_SHIFT)) & SYSMPU_RGDAAC_M5WE_MASK)
+#define SYSMPU_RGDAAC_M5WE SYSMPU_RGDAAC_M5WE_MASK
 #define SYSMPU_RGDAAC_M5RE_MASK                  (0x8000000U)
 #define SYSMPU_RGDAAC_M5RE_SHIFT                 (27U)
-#define SYSMPU_RGDAAC_M5RE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5RE_SHIFT)) & SYSMPU_RGDAAC_M5RE_MASK)
+#define SYSMPU_RGDAAC_M5RE_SET(x)                (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5RE_SHIFT)) & SYSMPU_RGDAAC_M5RE_MASK)
+#define SYSMPU_RGDAAC_M5RE SYSMPU_RGDAAC_M5RE_MASK
 #define SYSMPU_RGDAAC_M6WE_MASK                  (0x10000000U)
 #define SYSMPU_RGDAAC_M6WE_SHIFT                 (28U)
-#define SYSMPU_RGDAAC_M6WE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6WE_SHIFT)) & SYSMPU_RGDAAC_M6WE_MASK)
+#define SYSMPU_RGDAAC_M6WE_SET(x)                (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6WE_SHIFT)) & SYSMPU_RGDAAC_M6WE_MASK)
+#define SYSMPU_RGDAAC_M6WE SYSMPU_RGDAAC_M6WE_MASK
 #define SYSMPU_RGDAAC_M6RE_MASK                  (0x20000000U)
 #define SYSMPU_RGDAAC_M6RE_SHIFT                 (29U)
-#define SYSMPU_RGDAAC_M6RE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6RE_SHIFT)) & SYSMPU_RGDAAC_M6RE_MASK)
+#define SYSMPU_RGDAAC_M6RE_SET(x)                (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6RE_SHIFT)) & SYSMPU_RGDAAC_M6RE_MASK)
+#define SYSMPU_RGDAAC_M6RE SYSMPU_RGDAAC_M6RE_MASK
 #define SYSMPU_RGDAAC_M7WE_MASK                  (0x40000000U)
 #define SYSMPU_RGDAAC_M7WE_SHIFT                 (30U)
-#define SYSMPU_RGDAAC_M7WE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7WE_SHIFT)) & SYSMPU_RGDAAC_M7WE_MASK)
+#define SYSMPU_RGDAAC_M7WE_SET(x)                (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7WE_SHIFT)) & SYSMPU_RGDAAC_M7WE_MASK)
+#define SYSMPU_RGDAAC_M7WE SYSMPU_RGDAAC_M7WE_MASK
 #define SYSMPU_RGDAAC_M7RE_MASK                  (0x80000000U)
 #define SYSMPU_RGDAAC_M7RE_SHIFT                 (31U)
-#define SYSMPU_RGDAAC_M7RE(x)                    (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7RE_SHIFT)) & SYSMPU_RGDAAC_M7RE_MASK)
+#define SYSMPU_RGDAAC_M7RE_SET(x)                (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7RE_SHIFT)) & SYSMPU_RGDAAC_M7RE_MASK)
+#define SYSMPU_RGDAAC_M7RE SYSMPU_RGDAAC_M7RE_MASK
 
 /* The count of SYSMPU_RGDAAC */
 #define SYSMPU_RGDAAC_COUNT                      (12U)
@@ -13280,7 +16055,7 @@ typedef struct {
 /** Peripheral SYSMPU base address */
 #define SYSMPU_BASE                              (0x4000D000u)
 /** Peripheral SYSMPU base pointer */
-#define SYSMPU                                   ((SYSMPU_Type *)SYSMPU_BASE)
+#define SYSMPU                                   ((SYSMPU_TypeDef *)SYSMPU_BASE)
 /** Array initializer of SYSMPU peripheral base addresses */
 #define SYSMPU_BASE_ADDRS                        { SYSMPU_BASE }
 /** Array initializer of SYSMPU peripheral base pointers */
@@ -13320,7 +16095,7 @@ typedef struct {
        uint8_t RESERVED_4[4];
   __IO uint32_t QDCTRL;                            /**< Quadrature Decoder Control and Status, offset: 0x80 */
   __IO uint32_t CONF;                              /**< Configuration, offset: 0x84 */
-} TPM_Type;
+} TPM_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- TPM Register Masks
@@ -13334,55 +16109,70 @@ typedef struct {
 /*! @name SC - Status and Control */
 #define TPM_SC_PS_MASK                           (0x7U)
 #define TPM_SC_PS_SHIFT                          (0U)
-#define TPM_SC_PS(x)                             (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK)
+#define TPM_SC_PS_SET(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_SC_PS_SHIFT)) & TPM_SC_PS_MASK)
+#define TPM_SC_PS TPM_SC_PS_MASK
 #define TPM_SC_CMOD_MASK                         (0x18U)
 #define TPM_SC_CMOD_SHIFT                        (3U)
-#define TPM_SC_CMOD(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK)
+#define TPM_SC_CMOD_SET(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_SC_CMOD_SHIFT)) & TPM_SC_CMOD_MASK)
+#define TPM_SC_CMOD TPM_SC_CMOD_MASK
 #define TPM_SC_CPWMS_MASK                        (0x20U)
 #define TPM_SC_CPWMS_SHIFT                       (5U)
-#define TPM_SC_CPWMS(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK)
+#define TPM_SC_CPWMS_SET(x)                      (((uint32_t)(((uint32_t)(x)) << TPM_SC_CPWMS_SHIFT)) & TPM_SC_CPWMS_MASK)
+#define TPM_SC_CPWMS TPM_SC_CPWMS_MASK
 #define TPM_SC_TOIE_MASK                         (0x40U)
 #define TPM_SC_TOIE_SHIFT                        (6U)
-#define TPM_SC_TOIE(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK)
+#define TPM_SC_TOIE_SET(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOIE_SHIFT)) & TPM_SC_TOIE_MASK)
+#define TPM_SC_TOIE TPM_SC_TOIE_MASK
 #define TPM_SC_TOF_MASK                          (0x80U)
 #define TPM_SC_TOF_SHIFT                         (7U)
-#define TPM_SC_TOF(x)                            (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK)
+#define TPM_SC_TOF_SET(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_SC_TOF_SHIFT)) & TPM_SC_TOF_MASK)
+#define TPM_SC_TOF TPM_SC_TOF_MASK
 #define TPM_SC_DMA_MASK                          (0x100U)
 #define TPM_SC_DMA_SHIFT                         (8U)
-#define TPM_SC_DMA(x)                            (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK)
+#define TPM_SC_DMA_SET(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_SC_DMA_SHIFT)) & TPM_SC_DMA_MASK)
+#define TPM_SC_DMA TPM_SC_DMA_MASK
 
 /*! @name CNT - Counter */
 #define TPM_CNT_COUNT_MASK                       (0xFFFFU)
 #define TPM_CNT_COUNT_SHIFT                      (0U)
-#define TPM_CNT_COUNT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK)
+#define TPM_CNT_COUNT_SET(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_CNT_COUNT_SHIFT)) & TPM_CNT_COUNT_MASK)
+#define TPM_CNT_COUNT TPM_CNT_COUNT_MASK
 
 /*! @name MOD - Modulo */
 #define TPM_MOD_MOD_MASK                         (0xFFFFU)
 #define TPM_MOD_MOD_SHIFT                        (0U)
-#define TPM_MOD_MOD(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK)
+#define TPM_MOD_MOD_SET(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_MOD_MOD_SHIFT)) & TPM_MOD_MOD_MASK)
+#define TPM_MOD_MOD TPM_MOD_MOD_MASK
 
 /*! @name CnSC - Channel (n) Status and Control */
 #define TPM_CnSC_DMA_MASK                        (0x1U)
 #define TPM_CnSC_DMA_SHIFT                       (0U)
-#define TPM_CnSC_DMA(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK)
+#define TPM_CnSC_DMA_SET(x)                      (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_DMA_SHIFT)) & TPM_CnSC_DMA_MASK)
+#define TPM_CnSC_DMA TPM_CnSC_DMA_MASK
 #define TPM_CnSC_ELSA_MASK                       (0x4U)
 #define TPM_CnSC_ELSA_SHIFT                      (2U)
-#define TPM_CnSC_ELSA(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK)
+#define TPM_CnSC_ELSA_SET(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSA_SHIFT)) & TPM_CnSC_ELSA_MASK)
+#define TPM_CnSC_ELSA TPM_CnSC_ELSA_MASK
 #define TPM_CnSC_ELSB_MASK                       (0x8U)
 #define TPM_CnSC_ELSB_SHIFT                      (3U)
-#define TPM_CnSC_ELSB(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK)
+#define TPM_CnSC_ELSB_SET(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_ELSB_SHIFT)) & TPM_CnSC_ELSB_MASK)
+#define TPM_CnSC_ELSB TPM_CnSC_ELSB_MASK
 #define TPM_CnSC_MSA_MASK                        (0x10U)
 #define TPM_CnSC_MSA_SHIFT                       (4U)
-#define TPM_CnSC_MSA(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK)
+#define TPM_CnSC_MSA_SET(x)                      (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSA_SHIFT)) & TPM_CnSC_MSA_MASK)
+#define TPM_CnSC_MSA TPM_CnSC_MSA_MASK
 #define TPM_CnSC_MSB_MASK                        (0x20U)
 #define TPM_CnSC_MSB_SHIFT                       (5U)
-#define TPM_CnSC_MSB(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK)
+#define TPM_CnSC_MSB_SET(x)                      (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_MSB_SHIFT)) & TPM_CnSC_MSB_MASK)
+#define TPM_CnSC_MSB TPM_CnSC_MSB_MASK
 #define TPM_CnSC_CHIE_MASK                       (0x40U)
 #define TPM_CnSC_CHIE_SHIFT                      (6U)
-#define TPM_CnSC_CHIE(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK)
+#define TPM_CnSC_CHIE_SET(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHIE_SHIFT)) & TPM_CnSC_CHIE_MASK)
+#define TPM_CnSC_CHIE TPM_CnSC_CHIE_MASK
 #define TPM_CnSC_CHF_MASK                        (0x80U)
 #define TPM_CnSC_CHF_SHIFT                       (7U)
-#define TPM_CnSC_CHF(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK)
+#define TPM_CnSC_CHF_SET(x)                      (((uint32_t)(((uint32_t)(x)) << TPM_CnSC_CHF_SHIFT)) & TPM_CnSC_CHF_MASK)
+#define TPM_CnSC_CHF TPM_CnSC_CHF_MASK
 
 /* The count of TPM_CnSC */
 #define TPM_CnSC_COUNT                           (2U)
@@ -13390,7 +16180,8 @@ typedef struct {
 /*! @name CnV - Channel (n) Value */
 #define TPM_CnV_VAL_MASK                         (0xFFFFU)
 #define TPM_CnV_VAL_SHIFT                        (0U)
-#define TPM_CnV_VAL(x)                           (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK)
+#define TPM_CnV_VAL_SET(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CnV_VAL_SHIFT)) & TPM_CnV_VAL_MASK)
+#define TPM_CnV_VAL TPM_CnV_VAL_MASK
 
 /* The count of TPM_CnV */
 #define TPM_CnV_COUNT                            (2U)
@@ -13398,86 +16189,110 @@ typedef struct {
 /*! @name STATUS - Capture and Compare Status */
 #define TPM_STATUS_CH0F_MASK                     (0x1U)
 #define TPM_STATUS_CH0F_SHIFT                    (0U)
-#define TPM_STATUS_CH0F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK)
+#define TPM_STATUS_CH0F_SET(x)                   (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH0F_SHIFT)) & TPM_STATUS_CH0F_MASK)
+#define TPM_STATUS_CH0F TPM_STATUS_CH0F_MASK
 #define TPM_STATUS_CH1F_MASK                     (0x2U)
 #define TPM_STATUS_CH1F_SHIFT                    (1U)
-#define TPM_STATUS_CH1F(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK)
+#define TPM_STATUS_CH1F_SET(x)                   (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_CH1F_SHIFT)) & TPM_STATUS_CH1F_MASK)
+#define TPM_STATUS_CH1F TPM_STATUS_CH1F_MASK
 #define TPM_STATUS_TOF_MASK                      (0x100U)
 #define TPM_STATUS_TOF_SHIFT                     (8U)
-#define TPM_STATUS_TOF(x)                        (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK)
+#define TPM_STATUS_TOF_SET(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_STATUS_TOF_SHIFT)) & TPM_STATUS_TOF_MASK)
+#define TPM_STATUS_TOF TPM_STATUS_TOF_MASK
 
 /*! @name COMBINE - Combine Channel Register */
 #define TPM_COMBINE_COMBINE0_MASK                (0x1U)
 #define TPM_COMBINE_COMBINE0_SHIFT               (0U)
-#define TPM_COMBINE_COMBINE0(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE0_SHIFT)) & TPM_COMBINE_COMBINE0_MASK)
+#define TPM_COMBINE_COMBINE0_SET(x)              (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMBINE0_SHIFT)) & TPM_COMBINE_COMBINE0_MASK)
+#define TPM_COMBINE_COMBINE0 TPM_COMBINE_COMBINE0_MASK
 #define TPM_COMBINE_COMSWAP0_MASK                (0x2U)
 #define TPM_COMBINE_COMSWAP0_SHIFT               (1U)
-#define TPM_COMBINE_COMSWAP0(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP0_SHIFT)) & TPM_COMBINE_COMSWAP0_MASK)
+#define TPM_COMBINE_COMSWAP0_SET(x)              (((uint32_t)(((uint32_t)(x)) << TPM_COMBINE_COMSWAP0_SHIFT)) & TPM_COMBINE_COMSWAP0_MASK)
+#define TPM_COMBINE_COMSWAP0 TPM_COMBINE_COMSWAP0_MASK
 
 /*! @name POL - Channel Polarity */
 #define TPM_POL_POL0_MASK                        (0x1U)
 #define TPM_POL_POL0_SHIFT                       (0U)
-#define TPM_POL_POL0(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK)
+#define TPM_POL_POL0_SET(x)                      (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL0_SHIFT)) & TPM_POL_POL0_MASK)
+#define TPM_POL_POL0 TPM_POL_POL0_MASK
 #define TPM_POL_POL1_MASK                        (0x2U)
 #define TPM_POL_POL1_SHIFT                       (1U)
-#define TPM_POL_POL1(x)                          (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK)
+#define TPM_POL_POL1_SET(x)                      (((uint32_t)(((uint32_t)(x)) << TPM_POL_POL1_SHIFT)) & TPM_POL_POL1_MASK)
+#define TPM_POL_POL1 TPM_POL_POL1_MASK
 
 /*! @name FILTER - Filter Control */
 #define TPM_FILTER_CH0FVAL_MASK                  (0xFU)
 #define TPM_FILTER_CH0FVAL_SHIFT                 (0U)
-#define TPM_FILTER_CH0FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH0FVAL_SHIFT)) & TPM_FILTER_CH0FVAL_MASK)
+#define TPM_FILTER_CH0FVAL_SET(x)                (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH0FVAL_SHIFT)) & TPM_FILTER_CH0FVAL_MASK)
+#define TPM_FILTER_CH0FVAL TPM_FILTER_CH0FVAL_MASK
 #define TPM_FILTER_CH1FVAL_MASK                  (0xF0U)
 #define TPM_FILTER_CH1FVAL_SHIFT                 (4U)
-#define TPM_FILTER_CH1FVAL(x)                    (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH1FVAL_SHIFT)) & TPM_FILTER_CH1FVAL_MASK)
+#define TPM_FILTER_CH1FVAL_SET(x)                (((uint32_t)(((uint32_t)(x)) << TPM_FILTER_CH1FVAL_SHIFT)) & TPM_FILTER_CH1FVAL_MASK)
+#define TPM_FILTER_CH1FVAL TPM_FILTER_CH1FVAL_MASK
 
 /*! @name QDCTRL - Quadrature Decoder Control and Status */
 #define TPM_QDCTRL_QUADEN_MASK                   (0x1U)
 #define TPM_QDCTRL_QUADEN_SHIFT                  (0U)
-#define TPM_QDCTRL_QUADEN(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADEN_SHIFT)) & TPM_QDCTRL_QUADEN_MASK)
+#define TPM_QDCTRL_QUADEN_SET(x)                 (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADEN_SHIFT)) & TPM_QDCTRL_QUADEN_MASK)
+#define TPM_QDCTRL_QUADEN TPM_QDCTRL_QUADEN_MASK
 #define TPM_QDCTRL_TOFDIR_MASK                   (0x2U)
 #define TPM_QDCTRL_TOFDIR_SHIFT                  (1U)
-#define TPM_QDCTRL_TOFDIR(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_TOFDIR_SHIFT)) & TPM_QDCTRL_TOFDIR_MASK)
+#define TPM_QDCTRL_TOFDIR_SET(x)                 (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_TOFDIR_SHIFT)) & TPM_QDCTRL_TOFDIR_MASK)
+#define TPM_QDCTRL_TOFDIR TPM_QDCTRL_TOFDIR_MASK
 #define TPM_QDCTRL_QUADIR_MASK                   (0x4U)
 #define TPM_QDCTRL_QUADIR_SHIFT                  (2U)
-#define TPM_QDCTRL_QUADIR(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADIR_SHIFT)) & TPM_QDCTRL_QUADIR_MASK)
+#define TPM_QDCTRL_QUADIR_SET(x)                 (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADIR_SHIFT)) & TPM_QDCTRL_QUADIR_MASK)
+#define TPM_QDCTRL_QUADIR TPM_QDCTRL_QUADIR_MASK
 #define TPM_QDCTRL_QUADMODE_MASK                 (0x8U)
 #define TPM_QDCTRL_QUADMODE_SHIFT                (3U)
-#define TPM_QDCTRL_QUADMODE(x)                   (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADMODE_SHIFT)) & TPM_QDCTRL_QUADMODE_MASK)
+#define TPM_QDCTRL_QUADMODE_SET(x)               (((uint32_t)(((uint32_t)(x)) << TPM_QDCTRL_QUADMODE_SHIFT)) & TPM_QDCTRL_QUADMODE_MASK)
+#define TPM_QDCTRL_QUADMODE TPM_QDCTRL_QUADMODE_MASK
 
 /*! @name CONF - Configuration */
 #define TPM_CONF_DOZEEN_MASK                     (0x20U)
 #define TPM_CONF_DOZEEN_SHIFT                    (5U)
-#define TPM_CONF_DOZEEN(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK)
+#define TPM_CONF_DOZEEN_SET(x)                   (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DOZEEN_SHIFT)) & TPM_CONF_DOZEEN_MASK)
+#define TPM_CONF_DOZEEN TPM_CONF_DOZEEN_MASK
 #define TPM_CONF_DBGMODE_MASK                    (0xC0U)
 #define TPM_CONF_DBGMODE_SHIFT                   (6U)
-#define TPM_CONF_DBGMODE(x)                      (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK)
+#define TPM_CONF_DBGMODE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_CONF_DBGMODE_SHIFT)) & TPM_CONF_DBGMODE_MASK)
+#define TPM_CONF_DBGMODE TPM_CONF_DBGMODE_MASK
 #define TPM_CONF_GTBSYNC_MASK                    (0x100U)
 #define TPM_CONF_GTBSYNC_SHIFT                   (8U)
-#define TPM_CONF_GTBSYNC(x)                      (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK)
+#define TPM_CONF_GTBSYNC_SET(x)                  (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBSYNC_SHIFT)) & TPM_CONF_GTBSYNC_MASK)
+#define TPM_CONF_GTBSYNC TPM_CONF_GTBSYNC_MASK
 #define TPM_CONF_GTBEEN_MASK                     (0x200U)
 #define TPM_CONF_GTBEEN_SHIFT                    (9U)
-#define TPM_CONF_GTBEEN(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK)
+#define TPM_CONF_GTBEEN_SET(x)                   (((uint32_t)(((uint32_t)(x)) << TPM_CONF_GTBEEN_SHIFT)) & TPM_CONF_GTBEEN_MASK)
+#define TPM_CONF_GTBEEN TPM_CONF_GTBEEN_MASK
 #define TPM_CONF_CSOT_MASK                       (0x10000U)
 #define TPM_CONF_CSOT_SHIFT                      (16U)
-#define TPM_CONF_CSOT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK)
+#define TPM_CONF_CSOT_SET(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOT_SHIFT)) & TPM_CONF_CSOT_MASK)
+#define TPM_CONF_CSOT TPM_CONF_CSOT_MASK
 #define TPM_CONF_CSOO_MASK                       (0x20000U)
 #define TPM_CONF_CSOO_SHIFT                      (17U)
-#define TPM_CONF_CSOO(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK)
+#define TPM_CONF_CSOO_SET(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CSOO_SHIFT)) & TPM_CONF_CSOO_MASK)
+#define TPM_CONF_CSOO TPM_CONF_CSOO_MASK
 #define TPM_CONF_CROT_MASK                       (0x40000U)
 #define TPM_CONF_CROT_SHIFT                      (18U)
-#define TPM_CONF_CROT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK)
+#define TPM_CONF_CROT_SET(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CROT_SHIFT)) & TPM_CONF_CROT_MASK)
+#define TPM_CONF_CROT TPM_CONF_CROT_MASK
 #define TPM_CONF_CPOT_MASK                       (0x80000U)
 #define TPM_CONF_CPOT_SHIFT                      (19U)
-#define TPM_CONF_CPOT(x)                         (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK)
+#define TPM_CONF_CPOT_SET(x)                     (((uint32_t)(((uint32_t)(x)) << TPM_CONF_CPOT_SHIFT)) & TPM_CONF_CPOT_MASK)
+#define TPM_CONF_CPOT TPM_CONF_CPOT_MASK
 #define TPM_CONF_TRGPOL_MASK                     (0x400000U)
 #define TPM_CONF_TRGPOL_SHIFT                    (22U)
-#define TPM_CONF_TRGPOL(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK)
+#define TPM_CONF_TRGPOL_SET(x)                   (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGPOL_SHIFT)) & TPM_CONF_TRGPOL_MASK)
+#define TPM_CONF_TRGPOL TPM_CONF_TRGPOL_MASK
 #define TPM_CONF_TRGSRC_MASK                     (0x800000U)
 #define TPM_CONF_TRGSRC_SHIFT                    (23U)
-#define TPM_CONF_TRGSRC(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK)
+#define TPM_CONF_TRGSRC_SET(x)                   (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSRC_SHIFT)) & TPM_CONF_TRGSRC_MASK)
+#define TPM_CONF_TRGSRC TPM_CONF_TRGSRC_MASK
 #define TPM_CONF_TRGSEL_MASK                     (0xF000000U)
 #define TPM_CONF_TRGSEL_SHIFT                    (24U)
-#define TPM_CONF_TRGSEL(x)                       (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK)
+#define TPM_CONF_TRGSEL_SET(x)                   (((uint32_t)(((uint32_t)(x)) << TPM_CONF_TRGSEL_SHIFT)) & TPM_CONF_TRGSEL_MASK)
+#define TPM_CONF_TRGSEL TPM_CONF_TRGSEL_MASK
 
 
 /*!
@@ -13489,15 +16304,15 @@ typedef struct {
 /** Peripheral TPM1 base address */
 #define TPM1_BASE                                (0x400C9000u)
 /** Peripheral TPM1 base pointer */
-#define TPM1                                     ((TPM_Type *)TPM1_BASE)
+#define TPM1                                     ((TPM_TypeDef *)TPM1_BASE)
 /** Peripheral TPM2 base address */
 #define TPM2_BASE                                (0x400CA000u)
 /** Peripheral TPM2 base pointer */
-#define TPM2                                     ((TPM_Type *)TPM2_BASE)
+#define TPM2                                     ((TPM_TypeDef *)TPM2_BASE)
 /** Array initializer of TPM peripheral base addresses */
 #define TPM_BASE_ADDRS                           { 0u, TPM1_BASE, TPM2_BASE }
 /** Array initializer of TPM peripheral base pointers */
-#define TPM_BASE_PTRS                            { (TPM_Type *)0u, TPM1, TPM2 }
+#define TPM_BASE_PTRS                            { (TPM_TypeDef *)0u, TPM1, TPM2 }
 /** Interrupt vectors for the TPM peripheral type */
 #define TPM_IRQS                                 { NotAvail_IRQn, TPM1_IRQn, TPM2_IRQn }
 
@@ -13520,7 +16335,7 @@ typedef struct {
   __IO uint32_t GENCS;                             /**< TSI General Control and Status Register, offset: 0x0 */
   __IO uint32_t DATA;                              /**< TSI DATA Register, offset: 0x4 */
   __IO uint32_t TSHD;                              /**< TSI Threshold Register, offset: 0x8 */
-} TSI_Type;
+} TSI_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- TSI Register Masks
@@ -13534,74 +16349,96 @@ typedef struct {
 /*! @name GENCS - TSI General Control and Status Register */
 #define TSI_GENCS_EOSDMEO_MASK                   (0x1U)
 #define TSI_GENCS_EOSDMEO_SHIFT                  (0U)
-#define TSI_GENCS_EOSDMEO(x)                     (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSDMEO_SHIFT)) & TSI_GENCS_EOSDMEO_MASK)
+#define TSI_GENCS_EOSDMEO_SET(x)                 (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSDMEO_SHIFT)) & TSI_GENCS_EOSDMEO_MASK)
+#define TSI_GENCS_EOSDMEO TSI_GENCS_EOSDMEO_MASK
 #define TSI_GENCS_CURSW_MASK                     (0x2U)
 #define TSI_GENCS_CURSW_SHIFT                    (1U)
-#define TSI_GENCS_CURSW(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_CURSW_SHIFT)) & TSI_GENCS_CURSW_MASK)
+#define TSI_GENCS_CURSW_SET(x)                   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_CURSW_SHIFT)) & TSI_GENCS_CURSW_MASK)
+#define TSI_GENCS_CURSW TSI_GENCS_CURSW_MASK
 #define TSI_GENCS_EOSF_MASK                      (0x4U)
 #define TSI_GENCS_EOSF_SHIFT                     (2U)
-#define TSI_GENCS_EOSF(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK)
+#define TSI_GENCS_EOSF_SET(x)                    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EOSF_SHIFT)) & TSI_GENCS_EOSF_MASK)
+#define TSI_GENCS_EOSF TSI_GENCS_EOSF_MASK
 #define TSI_GENCS_SCNIP_MASK                     (0x8U)
 #define TSI_GENCS_SCNIP_SHIFT                    (3U)
-#define TSI_GENCS_SCNIP(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK)
+#define TSI_GENCS_SCNIP_SET(x)                   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_SCNIP_SHIFT)) & TSI_GENCS_SCNIP_MASK)
+#define TSI_GENCS_SCNIP TSI_GENCS_SCNIP_MASK
 #define TSI_GENCS_STM_MASK                       (0x10U)
 #define TSI_GENCS_STM_SHIFT                      (4U)
-#define TSI_GENCS_STM(x)                         (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK)
+#define TSI_GENCS_STM_SET(x)                     (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STM_SHIFT)) & TSI_GENCS_STM_MASK)
+#define TSI_GENCS_STM TSI_GENCS_STM_MASK
 #define TSI_GENCS_STPE_MASK                      (0x20U)
 #define TSI_GENCS_STPE_SHIFT                     (5U)
-#define TSI_GENCS_STPE(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK)
+#define TSI_GENCS_STPE_SET(x)                    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_STPE_SHIFT)) & TSI_GENCS_STPE_MASK)
+#define TSI_GENCS_STPE TSI_GENCS_STPE_MASK
 #define TSI_GENCS_TSIIEN_MASK                    (0x40U)
 #define TSI_GENCS_TSIIEN_SHIFT                   (6U)
-#define TSI_GENCS_TSIIEN(x)                      (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIEN_SHIFT)) & TSI_GENCS_TSIIEN_MASK)
+#define TSI_GENCS_TSIIEN_SET(x)                  (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIIEN_SHIFT)) & TSI_GENCS_TSIIEN_MASK)
+#define TSI_GENCS_TSIIEN TSI_GENCS_TSIIEN_MASK
 #define TSI_GENCS_TSIEN_MASK                     (0x80U)
 #define TSI_GENCS_TSIEN_SHIFT                    (7U)
-#define TSI_GENCS_TSIEN(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK)
+#define TSI_GENCS_TSIEN_SET(x)                   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_TSIEN_SHIFT)) & TSI_GENCS_TSIEN_MASK)
+#define TSI_GENCS_TSIEN TSI_GENCS_TSIEN_MASK
 #define TSI_GENCS_NSCN_MASK                      (0x1F00U)
 #define TSI_GENCS_NSCN_SHIFT                     (8U)
-#define TSI_GENCS_NSCN(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_NSCN_SHIFT)) & TSI_GENCS_NSCN_MASK)
+#define TSI_GENCS_NSCN_SET(x)                    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_NSCN_SHIFT)) & TSI_GENCS_NSCN_MASK)
+#define TSI_GENCS_NSCN TSI_GENCS_NSCN_MASK
 #define TSI_GENCS_PS_MASK                        (0xE000U)
 #define TSI_GENCS_PS_SHIFT                       (13U)
-#define TSI_GENCS_PS(x)                          (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_PS_SHIFT)) & TSI_GENCS_PS_MASK)
+#define TSI_GENCS_PS_SET(x)                      (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_PS_SHIFT)) & TSI_GENCS_PS_MASK)
+#define TSI_GENCS_PS TSI_GENCS_PS_MASK
 #define TSI_GENCS_EXTCHRG_MASK                   (0x70000U)
 #define TSI_GENCS_EXTCHRG_SHIFT                  (16U)
-#define TSI_GENCS_EXTCHRG(x)                     (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EXTCHRG_SHIFT)) & TSI_GENCS_EXTCHRG_MASK)
+#define TSI_GENCS_EXTCHRG_SET(x)                 (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_EXTCHRG_SHIFT)) & TSI_GENCS_EXTCHRG_MASK)
+#define TSI_GENCS_EXTCHRG TSI_GENCS_EXTCHRG_MASK
 #define TSI_GENCS_DVOLT_MASK                     (0x180000U)
 #define TSI_GENCS_DVOLT_SHIFT                    (19U)
-#define TSI_GENCS_DVOLT(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DVOLT_SHIFT)) & TSI_GENCS_DVOLT_MASK)
+#define TSI_GENCS_DVOLT_SET(x)                   (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_DVOLT_SHIFT)) & TSI_GENCS_DVOLT_MASK)
+#define TSI_GENCS_DVOLT TSI_GENCS_DVOLT_MASK
 #define TSI_GENCS_REFCHRG_MASK                   (0xE00000U)
 #define TSI_GENCS_REFCHRG_SHIFT                  (21U)
-#define TSI_GENCS_REFCHRG(x)                     (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_REFCHRG_SHIFT)) & TSI_GENCS_REFCHRG_MASK)
+#define TSI_GENCS_REFCHRG_SET(x)                 (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_REFCHRG_SHIFT)) & TSI_GENCS_REFCHRG_MASK)
+#define TSI_GENCS_REFCHRG TSI_GENCS_REFCHRG_MASK
 #define TSI_GENCS_MODE_MASK                      (0xF000000U)
 #define TSI_GENCS_MODE_SHIFT                     (24U)
-#define TSI_GENCS_MODE(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_MODE_SHIFT)) & TSI_GENCS_MODE_MASK)
+#define TSI_GENCS_MODE_SET(x)                    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_MODE_SHIFT)) & TSI_GENCS_MODE_MASK)
+#define TSI_GENCS_MODE TSI_GENCS_MODE_MASK
 #define TSI_GENCS_ESOR_MASK                      (0x10000000U)
 #define TSI_GENCS_ESOR_SHIFT                     (28U)
-#define TSI_GENCS_ESOR(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK)
+#define TSI_GENCS_ESOR_SET(x)                    (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_ESOR_SHIFT)) & TSI_GENCS_ESOR_MASK)
+#define TSI_GENCS_ESOR TSI_GENCS_ESOR_MASK
 #define TSI_GENCS_OUTRGF_MASK                    (0x80000000U)
 #define TSI_GENCS_OUTRGF_SHIFT                   (31U)
-#define TSI_GENCS_OUTRGF(x)                      (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRGF_SHIFT)) & TSI_GENCS_OUTRGF_MASK)
+#define TSI_GENCS_OUTRGF_SET(x)                  (((uint32_t)(((uint32_t)(x)) << TSI_GENCS_OUTRGF_SHIFT)) & TSI_GENCS_OUTRGF_MASK)
+#define TSI_GENCS_OUTRGF TSI_GENCS_OUTRGF_MASK
 
 /*! @name DATA - TSI DATA Register */
 #define TSI_DATA_TSICNT_MASK                     (0xFFFFU)
 #define TSI_DATA_TSICNT_SHIFT                    (0U)
-#define TSI_DATA_TSICNT(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICNT_SHIFT)) & TSI_DATA_TSICNT_MASK)
+#define TSI_DATA_TSICNT_SET(x)                   (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICNT_SHIFT)) & TSI_DATA_TSICNT_MASK)
+#define TSI_DATA_TSICNT TSI_DATA_TSICNT_MASK
 #define TSI_DATA_SWTS_MASK                       (0x400000U)
 #define TSI_DATA_SWTS_SHIFT                      (22U)
-#define TSI_DATA_SWTS(x)                         (((uint32_t)(((uint32_t)(x)) << TSI_DATA_SWTS_SHIFT)) & TSI_DATA_SWTS_MASK)
+#define TSI_DATA_SWTS_SET(x)                     (((uint32_t)(((uint32_t)(x)) << TSI_DATA_SWTS_SHIFT)) & TSI_DATA_SWTS_MASK)
+#define TSI_DATA_SWTS TSI_DATA_SWTS_MASK
 #define TSI_DATA_DMAEN_MASK                      (0x800000U)
 #define TSI_DATA_DMAEN_SHIFT                     (23U)
-#define TSI_DATA_DMAEN(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_DATA_DMAEN_SHIFT)) & TSI_DATA_DMAEN_MASK)
+#define TSI_DATA_DMAEN_SET(x)                    (((uint32_t)(((uint32_t)(x)) << TSI_DATA_DMAEN_SHIFT)) & TSI_DATA_DMAEN_MASK)
+#define TSI_DATA_DMAEN TSI_DATA_DMAEN_MASK
 #define TSI_DATA_TSICH_MASK                      (0xF0000000U)
 #define TSI_DATA_TSICH_SHIFT                     (28U)
-#define TSI_DATA_TSICH(x)                        (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICH_SHIFT)) & TSI_DATA_TSICH_MASK)
+#define TSI_DATA_TSICH_SET(x)                    (((uint32_t)(((uint32_t)(x)) << TSI_DATA_TSICH_SHIFT)) & TSI_DATA_TSICH_MASK)
+#define TSI_DATA_TSICH TSI_DATA_TSICH_MASK
 
 /*! @name TSHD - TSI Threshold Register */
 #define TSI_TSHD_THRESL_MASK                     (0xFFFFU)
 #define TSI_TSHD_THRESL_SHIFT                    (0U)
-#define TSI_TSHD_THRESL(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESL_SHIFT)) & TSI_TSHD_THRESL_MASK)
+#define TSI_TSHD_THRESL_SET(x)                   (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESL_SHIFT)) & TSI_TSHD_THRESL_MASK)
+#define TSI_TSHD_THRESL TSI_TSHD_THRESL_MASK
 #define TSI_TSHD_THRESH_MASK                     (0xFFFF0000U)
 #define TSI_TSHD_THRESH_SHIFT                    (16U)
-#define TSI_TSHD_THRESH(x)                       (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESH_SHIFT)) & TSI_TSHD_THRESH_MASK)
+#define TSI_TSHD_THRESH_SET(x)                   (((uint32_t)(((uint32_t)(x)) << TSI_TSHD_THRESH_SHIFT)) & TSI_TSHD_THRESH_MASK)
+#define TSI_TSHD_THRESH TSI_TSHD_THRESH_MASK
 
 
 /*!
@@ -13613,7 +16450,7 @@ typedef struct {
 /** Peripheral TSI0 base address */
 #define TSI0_BASE                                (0x40045000u)
 /** Peripheral TSI0 base pointer */
-#define TSI0                                     ((TSI_Type *)TSI0_BASE)
+#define TSI0                                     ((TSI_TypeDef *)TSI0_BASE)
 /** Array initializer of TSI peripheral base addresses */
 #define TSI_BASE_ADDRS                           { TSI0_BASE }
 /** Array initializer of TSI peripheral base pointers */
@@ -13631,7 +16468,7 @@ typedef struct {
    ---------------------------------------------------------------------------- */
 
 /*!
- * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
+ * @addtogroup UARTx_Peripheral_Access_Layer UART Peripheral Access Layer
  * @{
  */
 
@@ -13684,479 +16521,593 @@ typedef struct {
   };
   __IO uint8_t WGP7816_T1;                         /**< UART 7816 Wait and Guard Parameter Register, offset: 0x3E */
   __IO uint8_t WP7816C_T1;                         /**< UART 7816 Wait Parameter Register C, offset: 0x3F */
-} UART_Type;
+} UART_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- UART Register Masks
    ---------------------------------------------------------------------------- */
 
 /*!
- * @addtogroup UART_Register_Masks UART Register Masks
+ * @addtogroup UARTx_Register_Masks UART Register Masks
  * @{
  */
 
 /*! @name BDH - UART Baud Rate Registers: High */
-#define UART_BDH_SBR_MASK                        (0x1FU)
-#define UART_BDH_SBR_SHIFT                       (0U)
-#define UART_BDH_SBR(x)                          (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK)
-#define UART_BDH_SBNS_MASK                       (0x20U)
-#define UART_BDH_SBNS_SHIFT                      (5U)
-#define UART_BDH_SBNS(x)                         (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBNS_SHIFT)) & UART_BDH_SBNS_MASK)
-#define UART_BDH_RXEDGIE_MASK                    (0x40U)
-#define UART_BDH_RXEDGIE_SHIFT                   (6U)
-#define UART_BDH_RXEDGIE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK)
-#define UART_BDH_LBKDIE_MASK                     (0x80U)
-#define UART_BDH_LBKDIE_SHIFT                    (7U)
-#define UART_BDH_LBKDIE(x)                       (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK)
+#define UARTx_BDH_SBR_MASK                        (0x1FU)
+#define UARTx_BDH_SBR_SHIFT                       (0U)
+#define UARTx_BDH_SBR(x)                          (((uint8_t)(((uint8_t)(x)) << UARTx_BDH_SBR_SHIFT)) & UARTx_BDH_SBR_MASK)
+#define UARTx_BDH_SBNS_MASK                       (0x20U)
+#define UARTx_BDH_SBNS_SHIFT                      (5U)
+#define UARTx_BDH_SBNS_SET(x)                     (((uint8_t)(((uint8_t)(x)) << UARTx_BDH_SBNS_SHIFT)) & UARTx_BDH_SBNS_MASK)
+#define UARTx_BDH_SBNS UARTx_BDH_SBNS_MASK
+#define UARTx_BDH_RXEDGIE_MASK                    (0x40U)
+#define UARTx_BDH_RXEDGIE_SHIFT                   (6U)
+#define UARTx_BDH_RXEDGIE_SET(x)                  (((uint8_t)(((uint8_t)(x)) << UARTx_BDH_RXEDGIE_SHIFT)) & UARTx_BDH_RXEDGIE_MASK)
+#define UARTx_BDH_RXEDGIE UARTx_BDH_RXEDGIE_MASK
+#define UARTx_BDH_LBKDIE_MASK                     (0x80U)
+#define UARTx_BDH_LBKDIE_SHIFT                    (7U)
+#define UARTx_BDH_LBKDIE_SET(x)                   (((uint8_t)(((uint8_t)(x)) << UARTx_BDH_LBKDIE_SHIFT)) & UARTx_BDH_LBKDIE_MASK)
+#define UARTx_BDH_LBKDIE UARTx_BDH_LBKDIE_MASK
 
 /*! @name BDL - UART Baud Rate Registers: Low */
-#define UART_BDL_SBR_MASK                        (0xFFU)
-#define UART_BDL_SBR_SHIFT                       (0U)
-#define UART_BDL_SBR(x)                          (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK)
+#define UARTx_BDL_SBR_MASK                        (0xFFU)
+#define UARTx_BDL_SBR_SHIFT                       (0U)
+#define UARTx_BDL_SBR(x)                          (((uint8_t)(((uint8_t)(x)) << UARTx_BDL_SBR_SHIFT)) & UARTx_BDL_SBR_MASK)
 
 /*! @name C1 - UART Control Register 1 */
-#define UART_C1_PT_MASK                          (0x1U)
-#define UART_C1_PT_SHIFT                         (0U)
-#define UART_C1_PT(x)                            (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK)
-#define UART_C1_PE_MASK                          (0x2U)
-#define UART_C1_PE_SHIFT                         (1U)
-#define UART_C1_PE(x)                            (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK)
-#define UART_C1_ILT_MASK                         (0x4U)
-#define UART_C1_ILT_SHIFT                        (2U)
-#define UART_C1_ILT(x)                           (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK)
-#define UART_C1_WAKE_MASK                        (0x8U)
-#define UART_C1_WAKE_SHIFT                       (3U)
-#define UART_C1_WAKE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK)
-#define UART_C1_M_MASK                           (0x10U)
-#define UART_C1_M_SHIFT                          (4U)
-#define UART_C1_M(x)                             (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK)
-#define UART_C1_RSRC_MASK                        (0x20U)
-#define UART_C1_RSRC_SHIFT                       (5U)
-#define UART_C1_RSRC(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK)
-#define UART_C1_UARTSWAI_MASK                    (0x40U)
-#define UART_C1_UARTSWAI_SHIFT                   (6U)
-#define UART_C1_UARTSWAI(x)                      (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK)
-#define UART_C1_LOOPS_MASK                       (0x80U)
-#define UART_C1_LOOPS_SHIFT                      (7U)
-#define UART_C1_LOOPS(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK)
+#define UARTx_C1_PT_MASK                          (0x1U)
+#define UARTx_C1_PT_SHIFT                         (0U)
+#define UARTx_C1_PT_SET(x)                        (((uint8_t)(((uint8_t)(x)) << UARTx_C1_PT_SHIFT)) & UARTx_C1_PT_MASK)
+#define UARTx_C1_PT UARTx_C1_PT_MASK
+#define UARTx_C1_PE_MASK                          (0x2U)
+#define UARTx_C1_PE_SHIFT                         (1U)
+#define UARTx_C1_PE_SET(x)                        (((uint8_t)(((uint8_t)(x)) << UARTx_C1_PE_SHIFT)) & UARTx_C1_PE_MASK)
+#define UARTx_C1_PE UARTx_C1_PE_MASK
+#define UARTx_C1_ILT_MASK                         (0x4U)
+#define UARTx_C1_ILT_SHIFT                        (2U)
+#define UARTx_C1_ILT_SET(x)                       (((uint8_t)(((uint8_t)(x)) << UARTx_C1_ILT_SHIFT)) & UARTx_C1_ILT_MASK)
+#define UARTx_C1_ILT UARTx_C1_ILT_MASK
+#define UARTx_C1_WAKE_MASK                        (0x8U)
+#define UARTx_C1_WAKE_SHIFT                       (3U)
+#define UARTx_C1_WAKE_SET(x)                      (((uint8_t)(((uint8_t)(x)) << UARTx_C1_WAKE_SHIFT)) & UARTx_C1_WAKE_MASK)
+#define UARTx_C1_WAKE UARTx_C1_WAKE_MASK
+#define UARTx_C1_M_MASK                           (0x10U)
+#define UARTx_C1_M_SHIFT                          (4U)
+#define UARTx_C1_M_SET(x)                         (((uint8_t)(((uint8_t)(x)) << UARTx_C1_M_SHIFT)) & UARTx_C1_M_MASK)
+#define UARTx_C1_M UARTx_C1_M_MASK
+#define UARTx_C1_RSRC_MASK                        (0x20U)
+#define UARTx_C1_RSRC_SHIFT                       (5U)
+#define UARTx_C1_RSRC_SET(x)                      (((uint8_t)(((uint8_t)(x)) << UARTx_C1_RSRC_SHIFT)) & UARTx_C1_RSRC_MASK)
+#define UARTx_C1_RSRC UARTx_C1_RSRC_MASK
+#define UARTx_C1_UARTSWAI_MASK                    (0x40U)
+#define UARTx_C1_UARTSWAI_SHIFT                   (6U)
+#define UARTx_C1_UARTSWAI_SET(x)                  (((uint8_t)(((uint8_t)(x)) << UARTx_C1_UARTSWAI_SHIFT)) & UARTx_C1_UARTSWAI_MASK)
+#define UARTx_C1_UARTSWAI UARTx_C1_UARTSWAI_MASK
+#define UARTx_C1_LOOPS_MASK                       (0x80U)
+#define UARTx_C1_LOOPS_SHIFT                      (7U)
+#define UARTx_C1_LOOPS_SET(x)                     (((uint8_t)(((uint8_t)(x)) << UARTx_C1_LOOPS_SHIFT)) & UARTx_C1_LOOPS_MASK)
+#define UARTx_C1_LOOPS UARTx_C1_LOOPS_MASK
 
 /*! @name C2 - UART Control Register 2 */
-#define UART_C2_SBK_MASK                         (0x1U)
-#define UART_C2_SBK_SHIFT                        (0U)
-#define UART_C2_SBK(x)                           (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK)
-#define UART_C2_RWU_MASK                         (0x2U)
-#define UART_C2_RWU_SHIFT                        (1U)
-#define UART_C2_RWU(x)                           (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK)
-#define UART_C2_RE_MASK                          (0x4U)
-#define UART_C2_RE_SHIFT                         (2U)
-#define UART_C2_RE(x)                            (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK)
-#define UART_C2_TE_MASK                          (0x8U)
-#define UART_C2_TE_SHIFT                         (3U)
-#define UART_C2_TE(x)                            (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK)
-#define UART_C2_ILIE_MASK                        (0x10U)
-#define UART_C2_ILIE_SHIFT                       (4U)
-#define UART_C2_ILIE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK)
-#define UART_C2_RIE_MASK                         (0x20U)
-#define UART_C2_RIE_SHIFT                        (5U)
-#define UART_C2_RIE(x)                           (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK)
-#define UART_C2_TCIE_MASK                        (0x40U)
-#define UART_C2_TCIE_SHIFT                       (6U)
-#define UART_C2_TCIE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK)
-#define UART_C2_TIE_MASK                         (0x80U)
-#define UART_C2_TIE_SHIFT                        (7U)
-#define UART_C2_TIE(x)                           (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK)
+#define UARTx_C2_SBK_MASK                         (0x1U)
+#define UARTx_C2_SBK_SHIFT                        (0U)
+#define UARTx_C2_SBK_SET(x)                       (((uint8_t)(((uint8_t)(x)) << UARTx_C2_SBK_SHIFT)) & UARTx_C2_SBK_MASK)
+#define UARTx_C2_SBK UARTx_C2_SBK_MASK
+#define UARTx_C2_RWU_MASK                         (0x2U)
+#define UARTx_C2_RWU_SHIFT                        (1U)
+#define UARTx_C2_RWU_SET(x)                       (((uint8_t)(((uint8_t)(x)) << UARTx_C2_RWU_SHIFT)) & UARTx_C2_RWU_MASK)
+#define UARTx_C2_RWU UARTx_C2_RWU_MASK
+#define UARTx_C2_RE_MASK                          (0x4U)
+#define UARTx_C2_RE_SHIFT                         (2U)
+#define UARTx_C2_RE_SET(x)                        (((uint8_t)(((uint8_t)(x)) << UARTx_C2_RE_SHIFT)) & UARTx_C2_RE_MASK)
+#define UARTx_C2_RE UARTx_C2_RE_MASK
+#define UARTx_C2_TE_MASK                          (0x8U)
+#define UARTx_C2_TE_SHIFT                         (3U)
+#define UARTx_C2_TE_SET(x)                        (((uint8_t)(((uint8_t)(x)) << UARTx_C2_TE_SHIFT)) & UARTx_C2_TE_MASK)
+#define UARTx_C2_TE UARTx_C2_TE_MASK
+#define UARTx_C2_ILIE_MASK                        (0x10U)
+#define UARTx_C2_ILIE_SHIFT                       (4U)
+#define UARTx_C2_ILIE_SET(x)                      (((uint8_t)(((uint8_t)(x)) << UARTx_C2_ILIE_SHIFT)) & UARTx_C2_ILIE_MASK)
+#define UARTx_C2_ILIE UARTx_C2_ILIE_MASK
+#define UARTx_C2_RIE_MASK                         (0x20U)
+#define UARTx_C2_RIE_SHIFT                        (5U)
+#define UARTx_C2_RIE_SET(x)                       (((uint8_t)(((uint8_t)(x)) << UARTx_C2_RIE_SHIFT)) & UARTx_C2_RIE_MASK)
+#define UARTx_C2_RIE UARTx_C2_RIE_MASK
+#define UARTx_C2_TCIE_MASK                        (0x40U)
+#define UARTx_C2_TCIE_SHIFT                       (6U)
+#define UARTx_C2_TCIE_SET(x)                      (((uint8_t)(((uint8_t)(x)) << UARTx_C2_TCIE_SHIFT)) & UARTx_C2_TCIE_MASK)
+#define UARTx_C2_TCIE UARTx_C2_TCIE_MASK
+#define UARTx_C2_TIE_MASK                         (0x80U)
+#define UARTx_C2_TIE_SHIFT                        (7U)
+#define UARTx_C2_TIE_SET(x)                       (((uint8_t)(((uint8_t)(x)) << UARTx_C2_TIE_SHIFT)) & UARTx_C2_TIE_MASK)
+#define UARTx_C2_TIE UARTx_C2_TIE_MASK
 
 /*! @name S1 - UART Status Register 1 */
-#define UART_S1_PF_MASK                          (0x1U)
-#define UART_S1_PF_SHIFT                         (0U)
-#define UART_S1_PF(x)                            (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK)
-#define UART_S1_FE_MASK                          (0x2U)
-#define UART_S1_FE_SHIFT                         (1U)
-#define UART_S1_FE(x)                            (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK)
-#define UART_S1_NF_MASK                          (0x4U)
-#define UART_S1_NF_SHIFT                         (2U)
-#define UART_S1_NF(x)                            (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK)
-#define UART_S1_OR_MASK                          (0x8U)
-#define UART_S1_OR_SHIFT                         (3U)
-#define UART_S1_OR(x)                            (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK)
-#define UART_S1_IDLE_MASK                        (0x10U)
-#define UART_S1_IDLE_SHIFT                       (4U)
-#define UART_S1_IDLE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK)
-#define UART_S1_RDRF_MASK                        (0x20U)
-#define UART_S1_RDRF_SHIFT                       (5U)
-#define UART_S1_RDRF(x)                          (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK)
-#define UART_S1_TC_MASK                          (0x40U)
-#define UART_S1_TC_SHIFT                         (6U)
-#define UART_S1_TC(x)                            (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK)
-#define UART_S1_TDRE_MASK                        (0x80U)
-#define UART_S1_TDRE_SHIFT                       (7U)
-#define UART_S1_TDRE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK)
+#define UARTx_S1_PF_MASK                          (0x1U)
+#define UARTx_S1_PF_SHIFT                         (0U)
+#define UARTx_S1_PF_SET(x)                        (((uint8_t)(((uint8_t)(x)) << UARTx_S1_PF_SHIFT)) & UARTx_S1_PF_MASK)
+#define UARTx_S1_PF UARTx_S1_PF_MASK
+#define UARTx_S1_FE_MASK                          (0x2U)
+#define UARTx_S1_FE_SHIFT                         (1U)
+#define UARTx_S1_FE_SET(x)                        (((uint8_t)(((uint8_t)(x)) << UARTx_S1_FE_SHIFT)) & UARTx_S1_FE_MASK)
+#define UARTx_S1_FE UARTx_S1_FE_MASK
+#define UARTx_S1_NF_MASK                          (0x4U)
+#define UARTx_S1_NF_SHIFT                         (2U)
+#define UARTx_S1_NF_SET(x)                        (((uint8_t)(((uint8_t)(x)) << UARTx_S1_NF_SHIFT)) & UARTx_S1_NF_MASK)
+#define UARTx_S1_NF UARTx_S1_NF_MASK
+#define UARTx_S1_OR_MASK                          (0x8U)
+#define UARTx_S1_OR_SHIFT                         (3U)
+#define UARTx_S1_OR_SET(x)                        (((uint8_t)(((uint8_t)(x)) << UARTx_S1_OR_SHIFT)) & UARTx_S1_OR_MASK)
+#define UARTx_S1_OR UARTx_S1_OR_MASK
+#define UARTx_S1_IDLE_MASK                        (0x10U)
+#define UARTx_S1_IDLE_SHIFT                       (4U)
+#define UARTx_S1_IDLE_SET(x)                      (((uint8_t)(((uint8_t)(x)) << UARTx_S1_IDLE_SHIFT)) & UARTx_S1_IDLE_MASK)
+#define UARTx_S1_IDLE UARTx_S1_IDLE_MASK
+#define UARTx_S1_RDRF_MASK                        (0x20U)
+#define UARTx_S1_RDRF_SHIFT                       (5U)
+#define UARTx_S1_RDRF_SET(x)                      (((uint8_t)(((uint8_t)(x)) << UARTx_S1_RDRF_SHIFT)) & UARTx_S1_RDRF_MASK)
+#define UARTx_S1_RDRF UARTx_S1_RDRF_MASK
+#define UARTx_S1_TC_MASK                          (0x40U)
+#define UARTx_S1_TC_SHIFT                         (6U)
+#define UARTx_S1_TC_SET(x)                        (((uint8_t)(((uint8_t)(x)) << UARTx_S1_TC_SHIFT)) & UARTx_S1_TC_MASK)
+#define UARTx_S1_TC UARTx_S1_TC_MASK
+#define UARTx_S1_TDRE_MASK                        (0x80U)
+#define UARTx_S1_TDRE_SHIFT                       (7U)
+#define UARTx_S1_TDRE_SET(x)                      (((uint8_t)(((uint8_t)(x)) << UARTx_S1_TDRE_SHIFT)) & UARTx_S1_TDRE_MASK)
+#define UARTx_S1_TDRE UARTx_S1_TDRE_MASK
 
 /*! @name S2 - UART Status Register 2 */
-#define UART_S2_RAF_MASK                         (0x1U)
-#define UART_S2_RAF_SHIFT                        (0U)
-#define UART_S2_RAF(x)                           (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK)
-#define UART_S2_LBKDE_MASK                       (0x2U)
-#define UART_S2_LBKDE_SHIFT                      (1U)
-#define UART_S2_LBKDE(x)                         (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK)
-#define UART_S2_BRK13_MASK                       (0x4U)
-#define UART_S2_BRK13_SHIFT                      (2U)
-#define UART_S2_BRK13(x)                         (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK)
-#define UART_S2_RWUID_MASK                       (0x8U)
-#define UART_S2_RWUID_SHIFT                      (3U)
-#define UART_S2_RWUID(x)                         (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK)
-#define UART_S2_RXINV_MASK                       (0x10U)
-#define UART_S2_RXINV_SHIFT                      (4U)
-#define UART_S2_RXINV(x)                         (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK)
-#define UART_S2_MSBF_MASK                        (0x20U)
-#define UART_S2_MSBF_SHIFT                       (5U)
-#define UART_S2_MSBF(x)                          (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK)
-#define UART_S2_RXEDGIF_MASK                     (0x40U)
-#define UART_S2_RXEDGIF_SHIFT                    (6U)
-#define UART_S2_RXEDGIF(x)                       (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK)
-#define UART_S2_LBKDIF_MASK                      (0x80U)
-#define UART_S2_LBKDIF_SHIFT                     (7U)
-#define UART_S2_LBKDIF(x)                        (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK)
+#define UARTx_S2_RAF_MASK                         (0x1U)
+#define UARTx_S2_RAF_SHIFT                        (0U)
+#define UARTx_S2_RAF_SET(x)                       (((uint8_t)(((uint8_t)(x)) << UARTx_S2_RAF_SHIFT)) & UARTx_S2_RAF_MASK)
+#define UARTx_S2_RAF UARTx_S2_RAF_MASK
+#define UARTx_S2_LBKDE_MASK                       (0x2U)
+#define UARTx_S2_LBKDE_SHIFT                      (1U)
+#define UARTx_S2_LBKDE_SET(x)                     (((uint8_t)(((uint8_t)(x)) << UARTx_S2_LBKDE_SHIFT)) & UARTx_S2_LBKDE_MASK)
+#define UARTx_S2_LBKDE UARTx_S2_LBKDE_MASK
+#define UARTx_S2_BRK13_MASK                       (0x4U)
+#define UARTx_S2_BRK13_SHIFT                      (2U)
+#define UARTx_S2_BRK13_SET(x)                     (((uint8_t)(((uint8_t)(x)) << UARTx_S2_BRK13_SHIFT)) & UARTx_S2_BRK13_MASK)
+#define UARTx_S2_BRK13 UARTx_S2_BRK13_MASK
+#define UARTx_S2_RWUID_MASK                       (0x8U)
+#define UARTx_S2_RWUID_SHIFT                      (3U)
+#define UARTx_S2_RWUID_SET(x)                     (((uint8_t)(((uint8_t)(x)) << UARTx_S2_RWUID_SHIFT)) & UARTx_S2_RWUID_MASK)
+#define UARTx_S2_RWUID UARTx_S2_RWUID_MASK
+#define UARTx_S2_RXINV_MASK                       (0x10U)
+#define UARTx_S2_RXINV_SHIFT                      (4U)
+#define UARTx_S2_RXINV_SET(x)                     (((uint8_t)(((uint8_t)(x)) << UARTx_S2_RXINV_SHIFT)) & UARTx_S2_RXINV_MASK)
+#define UARTx_S2_RXINV UARTx_S2_RXINV_MASK
+#define UARTx_S2_MSBF_MASK                        (0x20U)
+#define UARTx_S2_MSBF_SHIFT                       (5U)
+#define UARTx_S2_MSBF_SET(x)                      (((uint8_t)(((uint8_t)(x)) << UARTx_S2_MSBF_SHIFT)) & UARTx_S2_MSBF_MASK)
+#define UARTx_S2_MSBF UARTx_S2_MSBF_MASK
+#define UARTx_S2_RXEDGIF_MASK                     (0x40U)
+#define UARTx_S2_RXEDGIF_SHIFT                    (6U)
+#define UARTx_S2_RXEDGIF_SET(x)                   (((uint8_t)(((uint8_t)(x)) << UARTx_S2_RXEDGIF_SHIFT)) & UARTx_S2_RXEDGIF_MASK)
+#define UARTx_S2_RXEDGIF UARTx_S2_RXEDGIF_MASK
+#define UARTx_S2_LBKDIF_MASK                      (0x80U)
+#define UARTx_S2_LBKDIF_SHIFT                     (7U)
+#define UARTx_S2_LBKDIF_SET(x)                    (((uint8_t)(((uint8_t)(x)) << UARTx_S2_LBKDIF_SHIFT)) & UARTx_S2_LBKDIF_MASK)
+#define UARTx_S2_LBKDIF UARTx_S2_LBKDIF_MASK
 
 /*! @name C3 - UART Control Register 3 */
-#define UART_C3_PEIE_MASK                        (0x1U)
-#define UART_C3_PEIE_SHIFT                       (0U)
-#define UART_C3_PEIE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK)
-#define UART_C3_FEIE_MASK                        (0x2U)
-#define UART_C3_FEIE_SHIFT                       (1U)
-#define UART_C3_FEIE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK)
-#define UART_C3_NEIE_MASK                        (0x4U)
-#define UART_C3_NEIE_SHIFT                       (2U)
-#define UART_C3_NEIE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK)
-#define UART_C3_ORIE_MASK                        (0x8U)
-#define UART_C3_ORIE_SHIFT                       (3U)
-#define UART_C3_ORIE(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK)
-#define UART_C3_TXINV_MASK                       (0x10U)
-#define UART_C3_TXINV_SHIFT                      (4U)
-#define UART_C3_TXINV(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK)
-#define UART_C3_TXDIR_MASK                       (0x20U)
-#define UART_C3_TXDIR_SHIFT                      (5U)
-#define UART_C3_TXDIR(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK)
-#define UART_C3_T8_MASK                          (0x40U)
-#define UART_C3_T8_SHIFT                         (6U)
-#define UART_C3_T8(x)                            (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK)
-#define UART_C3_R8_MASK                          (0x80U)
-#define UART_C3_R8_SHIFT                         (7U)
-#define UART_C3_R8(x)                            (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK)
+#define UARTx_C3_PEIE_MASK                        (0x1U)
+#define UARTx_C3_PEIE_SHIFT                       (0U)
+#define UARTx_C3_PEIE_SET(x)                      (((uint8_t)(((uint8_t)(x)) << UARTx_C3_PEIE_SHIFT)) & UARTx_C3_PEIE_MASK)
+#define UARTx_C3_PEIE UARTx_C3_PEIE_MASK
+#define UARTx_C3_FEIE_MASK                        (0x2U)
+#define UARTx_C3_FEIE_SHIFT                       (1U)
+#define UARTx_C3_FEIE_SET(x)                      (((uint8_t)(((uint8_t)(x)) << UARTx_C3_FEIE_SHIFT)) & UARTx_C3_FEIE_MASK)
+#define UARTx_C3_FEIE UARTx_C3_FEIE_MASK
+#define UARTx_C3_NEIE_MASK                        (0x4U)
+#define UARTx_C3_NEIE_SHIFT                       (2U)
+#define UARTx_C3_NEIE_SET(x)                      (((uint8_t)(((uint8_t)(x)) << UARTx_C3_NEIE_SHIFT)) & UARTx_C3_NEIE_MASK)
+#define UARTx_C3_NEIE UARTx_C3_NEIE_MASK
+#define UARTx_C3_ORIE_MASK                        (0x8U)
+#define UARTx_C3_ORIE_SHIFT                       (3U)
+#define UARTx_C3_ORIE_SET(x)                      (((uint8_t)(((uint8_t)(x)) << UARTx_C3_ORIE_SHIFT)) & UARTx_C3_ORIE_MASK)
+#define UARTx_C3_ORIE UARTx_C3_ORIE_MASK
+#define UARTx_C3_TXINV_MASK                       (0x10U)
+#define UARTx_C3_TXINV_SHIFT                      (4U)
+#define UARTx_C3_TXINV_SET(x)                     (((uint8_t)(((uint8_t)(x)) << UARTx_C3_TXINV_SHIFT)) & UARTx_C3_TXINV_MASK)
+#define UARTx_C3_TXINV UARTx_C3_TXINV_MASK
+#define UARTx_C3_TXDIR_MASK                       (0x20U)
+#define UARTx_C3_TXDIR_SHIFT                      (5U)
+#define UARTx_C3_TXDIR_SET(x)                     (((uint8_t)(((uint8_t)(x)) << UARTx_C3_TXDIR_SHIFT)) & UARTx_C3_TXDIR_MASK)
+#define UARTx_C3_TXDIR UARTx_C3_TXDIR_MASK
+#define UARTx_C3_T8_MASK                          (0x40U)
+#define UARTx_C3_T8_SHIFT                         (6U)
+#define UARTx_C3_T8_SET(x)                        (((uint8_t)(((uint8_t)(x)) << UARTx_C3_T8_SHIFT)) & UARTx_C3_T8_MASK)
+#define UARTx_C3_T8 UARTx_C3_T8_MASK
+#define UARTx_C3_R8_MASK                          (0x80U)
+#define UARTx_C3_R8_SHIFT                         (7U)
+#define UARTx_C3_R8_SET(x)                        (((uint8_t)(((uint8_t)(x)) << UARTx_C3_R8_SHIFT)) & UARTx_C3_R8_MASK)
+#define UARTx_C3_R8 UARTx_C3_R8_MASK
 
 /*! @name D - UART Data Register */
-#define UART_D_RT_MASK                           (0xFFU)
-#define UART_D_RT_SHIFT                          (0U)
-#define UART_D_RT(x)                             (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK)
+#define UARTx_D_RT_MASK                           (0xFFU)
+#define UARTx_D_RT_SHIFT                          (0U)
+#define UARTx_D_RT_SET(x)                         (((uint8_t)(((uint8_t)(x)) << UARTx_D_RT_SHIFT)) & UARTx_D_RT_MASK)
+#define UARTx_D_RT UARTx_D_RT_MASK
 
 /*! @name MA1 - UART Match Address Registers 1 */
-#define UART_MA1_MA_MASK                         (0xFFU)
-#define UART_MA1_MA_SHIFT                        (0U)
-#define UART_MA1_MA(x)                           (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK)
+#define UARTx_MA1_MA_MASK                         (0xFFU)
+#define UARTx_MA1_MA_SHIFT                        (0U)
+#define UARTx_MA1_MA_SET(x)                       (((uint8_t)(((uint8_t)(x)) << UARTx_MA1_MA_SHIFT)) & UARTx_MA1_MA_MASK)
+#define UARTx_MA1_MA UARTx_MA1_MA_MASK
 
 /*! @name MA2 - UART Match Address Registers 2 */
-#define UART_MA2_MA_MASK                         (0xFFU)
-#define UART_MA2_MA_SHIFT                        (0U)
-#define UART_MA2_MA(x)                           (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK)
+#define UARTx_MA2_MA_MASK                         (0xFFU)
+#define UARTx_MA2_MA_SHIFT                        (0U)
+#define UARTx_MA2_MA_SET(x)                       (((uint8_t)(((uint8_t)(x)) << UARTx_MA2_MA_SHIFT)) & UARTx_MA2_MA_MASK)
+#define UARTx_MA2_MA UARTx_MA2_MA_MASK
 
 /*! @name C4 - UART Control Register 4 */
-#define UART_C4_BRFA_MASK                        (0x1FU)
-#define UART_C4_BRFA_SHIFT                       (0U)
-#define UART_C4_BRFA(x)                          (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK)
-#define UART_C4_M10_MASK                         (0x20U)
-#define UART_C4_M10_SHIFT                        (5U)
-#define UART_C4_M10(x)                           (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK)
-#define UART_C4_MAEN2_MASK                       (0x40U)
-#define UART_C4_MAEN2_SHIFT                      (6U)
-#define UART_C4_MAEN2(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK)
-#define UART_C4_MAEN1_MASK                       (0x80U)
-#define UART_C4_MAEN1_SHIFT                      (7U)
-#define UART_C4_MAEN1(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK)
+#define UARTx_C4_BRFA_MASK                        (0x1FU)
+#define UARTx_C4_BRFA_SHIFT                       (0U)
+#define UARTx_C4_BRFA_SET(x)                      (((uint8_t)(((uint8_t)(x)) << UARTx_C4_BRFA_SHIFT)) & UARTx_C4_BRFA_MASK)
+#define UARTx_C4_BRFA UARTx_C4_BRFA_MASK
+#define UARTx_C4_M10_MASK                         (0x20U)
+#define UARTx_C4_M10_SHIFT                        (5U)
+#define UARTx_C4_M10_SET(x)                       (((uint8_t)(((uint8_t)(x)) << UARTx_C4_M10_SHIFT)) & UARTx_C4_M10_MASK)
+#define UARTx_C4_M10 UARTx_C4_M10_MASK
+#define UARTx_C4_MAEN2_MASK                       (0x40U)
+#define UARTx_C4_MAEN2_SHIFT                      (6U)
+#define UARTx_C4_MAEN2_SET(x)                     (((uint8_t)(((uint8_t)(x)) << UARTx_C4_MAEN2_SHIFT)) & UARTx_C4_MAEN2_MASK)
+#define UARTx_C4_MAEN2 UARTx_C4_MAEN2_MASK
+#define UARTx_C4_MAEN1_MASK                       (0x80U)
+#define UARTx_C4_MAEN1_SHIFT                      (7U)
+#define UARTx_C4_MAEN1_SET(x)                     (((uint8_t)(((uint8_t)(x)) << UARTx_C4_MAEN1_SHIFT)) & UARTx_C4_MAEN1_MASK)
+#define UARTx_C4_MAEN1 UARTx_C4_MAEN1_MASK
 
 /*! @name C5 - UART Control Register 5 */
-#define UART_C5_RDMAS_MASK                       (0x20U)
-#define UART_C5_RDMAS_SHIFT                      (5U)
-#define UART_C5_RDMAS(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK)
-#define UART_C5_TDMAS_MASK                       (0x80U)
-#define UART_C5_TDMAS_SHIFT                      (7U)
-#define UART_C5_TDMAS(x)                         (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK)
+#define UARTx_C5_RDMAS_MASK                       (0x20U)
+#define UARTx_C5_RDMAS_SHIFT                      (5U)
+#define UARTx_C5_RDMAS_SET(x)                     (((uint8_t)(((uint8_t)(x)) << UARTx_C5_RDMAS_SHIFT)) & UARTx_C5_RDMAS_MASK)
+#define UARTx_C5_RDMAS UARTx_C5_RDMAS_MASK
+#define UARTx_C5_TDMAS_MASK                       (0x80U)
+#define UARTx_C5_TDMAS_SHIFT                      (7U)
+#define UARTx_C5_TDMAS_SET(x)                     (((uint8_t)(((uint8_t)(x)) << UARTx_C5_TDMAS_SHIFT)) & UARTx_C5_TDMAS_MASK)
+#define UARTx_C5_TDMAS UARTx_C5_TDMAS_MASK
 
 /*! @name ED - UART Extended Data Register */
-#define UART_ED_PARITYE_MASK                     (0x40U)
-#define UART_ED_PARITYE_SHIFT                    (6U)
-#define UART_ED_PARITYE(x)                       (((uint8_t)(((uint8_t)(x)) << UART_ED_PARITYE_SHIFT)) & UART_ED_PARITYE_MASK)
-#define UART_ED_NOISY_MASK                       (0x80U)
-#define UART_ED_NOISY_SHIFT                      (7U)
-#define UART_ED_NOISY(x)                         (((uint8_t)(((uint8_t)(x)) << UART_ED_NOISY_SHIFT)) & UART_ED_NOISY_MASK)
+#define UARTx_ED_PARITYE_MASK                     (0x40U)
+#define UARTx_ED_PARITYE_SHIFT                    (6U)
+#define UARTx_ED_PARITYE_SET(x)                   (((uint8_t)(((uint8_t)(x)) << UARTx_ED_PARITYE_SHIFT)) & UARTx_ED_PARITYE_MASK)
+#define UARTx_ED_PARITYE UARTx_ED_PARITYE_MASK
+#define UARTx_ED_NOISY_MASK                       (0x80U)
+#define UARTx_ED_NOISY_SHIFT                      (7U)
+#define UARTx_ED_NOISY_SET(x)                     (((uint8_t)(((uint8_t)(x)) << UARTx_ED_NOISY_SHIFT)) & UARTx_ED_NOISY_MASK)
+#define UARTx_ED_NOISY UARTx_ED_NOISY_MASK
 
 /*! @name MODEM - UART Modem Register */
-#define UART_MODEM_TXCTSE_MASK                   (0x1U)
-#define UART_MODEM_TXCTSE_SHIFT                  (0U)
-#define UART_MODEM_TXCTSE(x)                     (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXCTSE_SHIFT)) & UART_MODEM_TXCTSE_MASK)
-#define UART_MODEM_TXRTSE_MASK                   (0x2U)
-#define UART_MODEM_TXRTSE_SHIFT                  (1U)
-#define UART_MODEM_TXRTSE(x)                     (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSE_SHIFT)) & UART_MODEM_TXRTSE_MASK)
-#define UART_MODEM_TXRTSPOL_MASK                 (0x4U)
-#define UART_MODEM_TXRTSPOL_SHIFT                (2U)
-#define UART_MODEM_TXRTSPOL(x)                   (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSPOL_SHIFT)) & UART_MODEM_TXRTSPOL_MASK)
-#define UART_MODEM_RXRTSE_MASK                   (0x8U)
-#define UART_MODEM_RXRTSE_SHIFT                  (3U)
-#define UART_MODEM_RXRTSE(x)                     (((uint8_t)(((uint8_t)(x)) << UART_MODEM_RXRTSE_SHIFT)) & UART_MODEM_RXRTSE_MASK)
+#define UARTx_MODEM_TXCTSE_MASK                   (0x1U)
+#define UARTx_MODEM_TXCTSE_SHIFT                  (0U)
+#define UARTx_MODEM_TXCTSE_SET(x)                 (((uint8_t)(((uint8_t)(x)) << UARTx_MODEM_TXCTSE_SHIFT)) & UARTx_MODEM_TXCTSE_MASK)
+#define UARTx_MODEM_TXCTSE UARTx_MODEM_TXCTSE_MASK
+#define UARTx_MODEM_TXRTSE_MASK                   (0x2U)
+#define UARTx_MODEM_TXRTSE_SHIFT                  (1U)
+#define UARTx_MODEM_TXRTSE_SET(x)                 (((uint8_t)(((uint8_t)(x)) << UARTx_MODEM_TXRTSE_SHIFT)) & UARTx_MODEM_TXRTSE_MASK)
+#define UARTx_MODEM_TXRTSE UARTx_MODEM_TXRTSE_MASK
+#define UARTx_MODEM_TXRTSPOL_MASK                 (0x4U)
+#define UARTx_MODEM_TXRTSPOL_SHIFT                (2U)
+#define UARTx_MODEM_TXRTSPOL_SET(x)               (((uint8_t)(((uint8_t)(x)) << UARTx_MODEM_TXRTSPOL_SHIFT)) & UARTx_MODEM_TXRTSPOL_MASK)
+#define UARTx_MODEM_TXRTSPOL UARTx_MODEM_TXRTSPOL_MASK
+#define UARTx_MODEM_RXRTSE_MASK                   (0x8U)
+#define UARTx_MODEM_RXRTSE_SHIFT                  (3U)
+#define UARTx_MODEM_RXRTSE_SET(x)                 (((uint8_t)(((uint8_t)(x)) << UARTx_MODEM_RXRTSE_SHIFT)) & UARTx_MODEM_RXRTSE_MASK)
+#define UARTx_MODEM_RXRTSE UARTx_MODEM_RXRTSE_MASK
 
 /*! @name IR - UART Infrared Register */
-#define UART_IR_TNP_MASK                         (0x3U)
-#define UART_IR_TNP_SHIFT                        (0U)
-#define UART_IR_TNP(x)                           (((uint8_t)(((uint8_t)(x)) << UART_IR_TNP_SHIFT)) & UART_IR_TNP_MASK)
-#define UART_IR_IREN_MASK                        (0x4U)
-#define UART_IR_IREN_SHIFT                       (2U)
-#define UART_IR_IREN(x)                          (((uint8_t)(((uint8_t)(x)) << UART_IR_IREN_SHIFT)) & UART_IR_IREN_MASK)
+#define UARTx_IR_TNP_MASK                         (0x3U)
+#define UARTx_IR_TNP_SHIFT                        (0U)
+#define UARTx_IR_TNP_SET(x)                       (((uint8_t)(((uint8_t)(x)) << UARTx_IR_TNP_SHIFT)) & UARTx_IR_TNP_MASK)
+#define UARTx_IR_TNP UARTx_IR_TNP_MASK
+#define UARTx_IR_IREN_MASK                        (0x4U)
+#define UARTx_IR_IREN_SHIFT                       (2U)
+#define UARTx_IR_IREN_SET(x)                      (((uint8_t)(((uint8_t)(x)) << UARTx_IR_IREN_SHIFT)) & UARTx_IR_IREN_MASK)
+#define UARTx_IR_IREN UARTx_IR_IREN_MASK
 
 /*! @name PFIFO - UART FIFO Parameters */
-#define UART_PFIFO_RXFIFOSIZE_MASK               (0x7U)
-#define UART_PFIFO_RXFIFOSIZE_SHIFT              (0U)
-#define UART_PFIFO_RXFIFOSIZE(x)                 (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFIFOSIZE_SHIFT)) & UART_PFIFO_RXFIFOSIZE_MASK)
-#define UART_PFIFO_RXFE_MASK                     (0x8U)
-#define UART_PFIFO_RXFE_SHIFT                    (3U)
-#define UART_PFIFO_RXFE(x)                       (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFE_SHIFT)) & UART_PFIFO_RXFE_MASK)
-#define UART_PFIFO_TXFIFOSIZE_MASK               (0x70U)
-#define UART_PFIFO_TXFIFOSIZE_SHIFT              (4U)
-#define UART_PFIFO_TXFIFOSIZE(x)                 (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFIFOSIZE_SHIFT)) & UART_PFIFO_TXFIFOSIZE_MASK)
-#define UART_PFIFO_TXFE_MASK                     (0x80U)
-#define UART_PFIFO_TXFE_SHIFT                    (7U)
-#define UART_PFIFO_TXFE(x)                       (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFE_SHIFT)) & UART_PFIFO_TXFE_MASK)
+#define UARTx_PFIFO_RXFIFOSIZE_MASK               (0x7U)
+#define UARTx_PFIFO_RXFIFOSIZE_SHIFT              (0U)
+#define UARTx_PFIFO_RXFIFOSIZE_SET(x)             (((uint8_t)(((uint8_t)(x)) << UARTx_PFIFO_RXFIFOSIZE_SHIFT)) & UARTx_PFIFO_RXFIFOSIZE_MASK)
+#define UARTx_PFIFO_RXFIFOSIZE UARTx_PFIFO_RXFIFOSIZE_MASK
+#define UARTx_PFIFO_RXFE_MASK                     (0x8U)
+#define UARTx_PFIFO_RXFE_SHIFT                    (3U)
+#define UARTx_PFIFO_RXFE_SET(x)                   (((uint8_t)(((uint8_t)(x)) << UARTx_PFIFO_RXFE_SHIFT)) & UARTx_PFIFO_RXFE_MASK)
+#define UARTx_PFIFO_RXFE UARTx_PFIFO_RXFE_MASK
+#define UARTx_PFIFO_TXFIFOSIZE_MASK               (0x70U)
+#define UARTx_PFIFO_TXFIFOSIZE_SHIFT              (4U)
+#define UARTx_PFIFO_TXFIFOSIZE_SET(x)             (((uint8_t)(((uint8_t)(x)) << UARTx_PFIFO_TXFIFOSIZE_SHIFT)) & UARTx_PFIFO_TXFIFOSIZE_MASK)
+#define UARTx_PFIFO_TXFIFOSIZE UARTx_PFIFO_TXFIFOSIZE_MASK
+#define UARTx_PFIFO_TXFE_MASK                     (0x80U)
+#define UARTx_PFIFO_TXFE_SHIFT                    (7U)
+#define UARTx_PFIFO_TXFE_SET(x)                   (((uint8_t)(((uint8_t)(x)) << UARTx_PFIFO_TXFE_SHIFT)) & UARTx_PFIFO_TXFE_MASK)
+#define UARTx_PFIFO_TXFE UARTx_PFIFO_TXFE_MASK
 
 /*! @name CFIFO - UART FIFO Control Register */
-#define UART_CFIFO_RXUFE_MASK                    (0x1U)
-#define UART_CFIFO_RXUFE_SHIFT                   (0U)
-#define UART_CFIFO_RXUFE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXUFE_SHIFT)) & UART_CFIFO_RXUFE_MASK)
-#define UART_CFIFO_TXOFE_MASK                    (0x2U)
-#define UART_CFIFO_TXOFE_SHIFT                   (1U)
-#define UART_CFIFO_TXOFE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXOFE_SHIFT)) & UART_CFIFO_TXOFE_MASK)
-#define UART_CFIFO_RXOFE_MASK                    (0x4U)
-#define UART_CFIFO_RXOFE_SHIFT                   (2U)
-#define UART_CFIFO_RXOFE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXOFE_SHIFT)) & UART_CFIFO_RXOFE_MASK)
-#define UART_CFIFO_RXFLUSH_MASK                  (0x40U)
-#define UART_CFIFO_RXFLUSH_SHIFT                 (6U)
-#define UART_CFIFO_RXFLUSH(x)                    (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXFLUSH_SHIFT)) & UART_CFIFO_RXFLUSH_MASK)
-#define UART_CFIFO_TXFLUSH_MASK                  (0x80U)
-#define UART_CFIFO_TXFLUSH_SHIFT                 (7U)
-#define UART_CFIFO_TXFLUSH(x)                    (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXFLUSH_SHIFT)) & UART_CFIFO_TXFLUSH_MASK)
+#define UARTx_CFIFO_RXUFE_MASK                    (0x1U)
+#define UARTx_CFIFO_RXUFE_SHIFT                   (0U)
+#define UARTx_CFIFO_RXUFE_SET(x)                  (((uint8_t)(((uint8_t)(x)) << UARTx_CFIFO_RXUFE_SHIFT)) & UARTx_CFIFO_RXUFE_MASK)
+#define UARTx_CFIFO_RXUFE UARTx_CFIFO_RXUFE_MASK
+#define UARTx_CFIFO_TXOFE_MASK                    (0x2U)
+#define UARTx_CFIFO_TXOFE_SHIFT                   (1U)
+#define UARTx_CFIFO_TXOFE_SET(x)                  (((uint8_t)(((uint8_t)(x)) << UARTx_CFIFO_TXOFE_SHIFT)) & UARTx_CFIFO_TXOFE_MASK)
+#define UARTx_CFIFO_TXOFE UARTx_CFIFO_TXOFE_MASK
+#define UARTx_CFIFO_RXOFE_MASK                    (0x4U)
+#define UARTx_CFIFO_RXOFE_SHIFT                   (2U)
+#define UARTx_CFIFO_RXOFE_SET(x)                  (((uint8_t)(((uint8_t)(x)) << UARTx_CFIFO_RXOFE_SHIFT)) & UARTx_CFIFO_RXOFE_MASK)
+#define UARTx_CFIFO_RXOFE UARTx_CFIFO_RXOFE_MASK
+#define UARTx_CFIFO_RXFLUSH_MASK                  (0x40U)
+#define UARTx_CFIFO_RXFLUSH_SHIFT                 (6U)
+#define UARTx_CFIFO_RXFLUSH_SET(x)                (((uint8_t)(((uint8_t)(x)) << UARTx_CFIFO_RXFLUSH_SHIFT)) & UARTx_CFIFO_RXFLUSH_MASK)
+#define UARTx_CFIFO_RXFLUSH UARTx_CFIFO_RXFLUSH_MASK
+#define UARTx_CFIFO_TXFLUSH_MASK                  (0x80U)
+#define UARTx_CFIFO_TXFLUSH_SHIFT                 (7U)
+#define UARTx_CFIFO_TXFLUSH_SET(x)                (((uint8_t)(((uint8_t)(x)) << UARTx_CFIFO_TXFLUSH_SHIFT)) & UARTx_CFIFO_TXFLUSH_MASK)
+#define UARTx_CFIFO_TXFLUSH UARTx_CFIFO_TXFLUSH_MASK
 
 /*! @name SFIFO - UART FIFO Status Register */
-#define UART_SFIFO_RXUF_MASK                     (0x1U)
-#define UART_SFIFO_RXUF_SHIFT                    (0U)
-#define UART_SFIFO_RXUF(x)                       (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXUF_SHIFT)) & UART_SFIFO_RXUF_MASK)
-#define UART_SFIFO_TXOF_MASK                     (0x2U)
-#define UART_SFIFO_TXOF_SHIFT                    (1U)
-#define UART_SFIFO_TXOF(x)                       (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXOF_SHIFT)) & UART_SFIFO_TXOF_MASK)
-#define UART_SFIFO_RXOF_MASK                     (0x4U)
-#define UART_SFIFO_RXOF_SHIFT                    (2U)
-#define UART_SFIFO_RXOF(x)                       (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXOF_SHIFT)) & UART_SFIFO_RXOF_MASK)
-#define UART_SFIFO_RXEMPT_MASK                   (0x40U)
-#define UART_SFIFO_RXEMPT_SHIFT                  (6U)
-#define UART_SFIFO_RXEMPT(x)                     (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXEMPT_SHIFT)) & UART_SFIFO_RXEMPT_MASK)
-#define UART_SFIFO_TXEMPT_MASK                   (0x80U)
-#define UART_SFIFO_TXEMPT_SHIFT                  (7U)
-#define UART_SFIFO_TXEMPT(x)                     (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXEMPT_SHIFT)) & UART_SFIFO_TXEMPT_MASK)
+#define UARTx_SFIFO_RXUF_MASK                     (0x1U)
+#define UARTx_SFIFO_RXUF_SHIFT                    (0U)
+#define UARTx_SFIFO_RXUF_SET(x)                   (((uint8_t)(((uint8_t)(x)) << UARTx_SFIFO_RXUF_SHIFT)) & UARTx_SFIFO_RXUF_MASK)
+#define UARTx_SFIFO_RXUF UARTx_SFIFO_RXUF_MASK
+#define UARTx_SFIFO_TXOF_MASK                     (0x2U)
+#define UARTx_SFIFO_TXOF_SHIFT                    (1U)
+#define UARTx_SFIFO_TXOF_SET(x)                   (((uint8_t)(((uint8_t)(x)) << UARTx_SFIFO_TXOF_SHIFT)) & UARTx_SFIFO_TXOF_MASK)
+#define UARTx_SFIFO_TXOF UARTx_SFIFO_TXOF_MASK
+#define UARTx_SFIFO_RXOF_MASK                     (0x4U)
+#define UARTx_SFIFO_RXOF_SHIFT                    (2U)
+#define UARTx_SFIFO_RXOF_SET(x)                   (((uint8_t)(((uint8_t)(x)) << UARTx_SFIFO_RXOF_SHIFT)) & UARTx_SFIFO_RXOF_MASK)
+#define UARTx_SFIFO_RXOF UARTx_SFIFO_RXOF_MASK
+#define UARTx_SFIFO_RXEMPT_MASK                   (0x40U)
+#define UARTx_SFIFO_RXEMPT_SHIFT                  (6U)
+#define UARTx_SFIFO_RXEMPT_SET(x)                 (((uint8_t)(((uint8_t)(x)) << UARTx_SFIFO_RXEMPT_SHIFT)) & UARTx_SFIFO_RXEMPT_MASK)
+#define UARTx_SFIFO_RXEMPT UARTx_SFIFO_RXEMPT_MASK
+#define UARTx_SFIFO_TXEMPT_MASK                   (0x80U)
+#define UARTx_SFIFO_TXEMPT_SHIFT                  (7U)
+#define UARTx_SFIFO_TXEMPT_SET(x)                 (((uint8_t)(((uint8_t)(x)) << UARTx_SFIFO_TXEMPT_SHIFT)) & UARTx_SFIFO_TXEMPT_MASK)
+#define UARTx_SFIFO_TXEMPT UARTx_SFIFO_TXEMPT_MASK
 
 /*! @name TWFIFO - UART FIFO Transmit Watermark */
-#define UART_TWFIFO_TXWATER_MASK                 (0xFFU)
-#define UART_TWFIFO_TXWATER_SHIFT                (0U)
-#define UART_TWFIFO_TXWATER(x)                   (((uint8_t)(((uint8_t)(x)) << UART_TWFIFO_TXWATER_SHIFT)) & UART_TWFIFO_TXWATER_MASK)
+#define UARTx_TWFIFO_TXWATER_MASK                 (0xFFU)
+#define UARTx_TWFIFO_TXWATER_SHIFT                (0U)
+#define UARTx_TWFIFO_TXWATER_SET(x)               (((uint8_t)(((uint8_t)(x)) << UARTx_TWFIFO_TXWATER_SHIFT)) & UARTx_TWFIFO_TXWATER_MASK)
+#define UARTx_TWFIFO_TXWATER UARTx_TWFIFO_TXWATER_MASK
 
 /*! @name TCFIFO - UART FIFO Transmit Count */
-#define UART_TCFIFO_TXCOUNT_MASK                 (0xFFU)
-#define UART_TCFIFO_TXCOUNT_SHIFT                (0U)
-#define UART_TCFIFO_TXCOUNT(x)                   (((uint8_t)(((uint8_t)(x)) << UART_TCFIFO_TXCOUNT_SHIFT)) & UART_TCFIFO_TXCOUNT_MASK)
+#define UARTx_TCFIFO_TXCOUNT_MASK                 (0xFFU)
+#define UARTx_TCFIFO_TXCOUNT_SHIFT                (0U)
+#define UARTx_TCFIFO_TXCOUNT_SET(x)               (((uint8_t)(((uint8_t)(x)) << UARTx_TCFIFO_TXCOUNT_SHIFT)) & UARTx_TCFIFO_TXCOUNT_MASK)
+#define UARTx_TCFIFO_TXCOUNT UARTx_TCFIFO_TXCOUNT_MASK
 
 /*! @name RWFIFO - UART FIFO Receive Watermark */
-#define UART_RWFIFO_RXWATER_MASK                 (0xFFU)
-#define UART_RWFIFO_RXWATER_SHIFT                (0U)
-#define UART_RWFIFO_RXWATER(x)                   (((uint8_t)(((uint8_t)(x)) << UART_RWFIFO_RXWATER_SHIFT)) & UART_RWFIFO_RXWATER_MASK)
+#define UARTx_RWFIFO_RXWATER_MASK                 (0xFFU)
+#define UARTx_RWFIFO_RXWATER_SHIFT                (0U)
+#define UARTx_RWFIFO_RXWATER_SET(x)               (((uint8_t)(((uint8_t)(x)) << UARTx_RWFIFO_RXWATER_SHIFT)) & UARTx_RWFIFO_RXWATER_MASK)
+#define UARTx_RWFIFO_RXWATER UARTx_RWFIFO_RXWATER_MASK
 
 /*! @name RCFIFO - UART FIFO Receive Count */
-#define UART_RCFIFO_RXCOUNT_MASK                 (0xFFU)
-#define UART_RCFIFO_RXCOUNT_SHIFT                (0U)
-#define UART_RCFIFO_RXCOUNT(x)                   (((uint8_t)(((uint8_t)(x)) << UART_RCFIFO_RXCOUNT_SHIFT)) & UART_RCFIFO_RXCOUNT_MASK)
+#define UARTx_RCFIFO_RXCOUNT_MASK                 (0xFFU)
+#define UARTx_RCFIFO_RXCOUNT_SHIFT                (0U)
+#define UARTx_RCFIFO_RXCOUNT_SET(x)               (((uint8_t)(((uint8_t)(x)) << UARTx_RCFIFO_RXCOUNT_SHIFT)) & UARTx_RCFIFO_RXCOUNT_MASK)
+#define UARTx_RCFIFO_RXCOUNT UARTx_RCFIFO_RXCOUNT_MASK
 
 /*! @name C7816 - UART 7816 Control Register */
-#define UART_C7816_ISO_7816E_MASK                (0x1U)
-#define UART_C7816_ISO_7816E_SHIFT               (0U)
-#define UART_C7816_ISO_7816E(x)                  (((uint8_t)(((uint8_t)(x)) << UART_C7816_ISO_7816E_SHIFT)) & UART_C7816_ISO_7816E_MASK)
-#define UART_C7816_TTYPE_MASK                    (0x2U)
-#define UART_C7816_TTYPE_SHIFT                   (1U)
-#define UART_C7816_TTYPE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_C7816_TTYPE_SHIFT)) & UART_C7816_TTYPE_MASK)
-#define UART_C7816_INIT_MASK                     (0x4U)
-#define UART_C7816_INIT_SHIFT                    (2U)
-#define UART_C7816_INIT(x)                       (((uint8_t)(((uint8_t)(x)) << UART_C7816_INIT_SHIFT)) & UART_C7816_INIT_MASK)
-#define UART_C7816_ANACK_MASK                    (0x8U)
-#define UART_C7816_ANACK_SHIFT                   (3U)
-#define UART_C7816_ANACK(x)                      (((uint8_t)(((uint8_t)(x)) << UART_C7816_ANACK_SHIFT)) & UART_C7816_ANACK_MASK)
-#define UART_C7816_ONACK_MASK                    (0x10U)
-#define UART_C7816_ONACK_SHIFT                   (4U)
-#define UART_C7816_ONACK(x)                      (((uint8_t)(((uint8_t)(x)) << UART_C7816_ONACK_SHIFT)) & UART_C7816_ONACK_MASK)
+#define UARTx_C7816_ISO_7816E_MASK                (0x1U)
+#define UARTx_C7816_ISO_7816E_SHIFT               (0U)
+#define UARTx_C7816_ISO_7816E_SET(x)              (((uint8_t)(((uint8_t)(x)) << UARTx_C7816_ISO_7816E_SHIFT)) & UARTx_C7816_ISO_7816E_MASK)
+#define UARTx_C7816_ISO_7816E UARTx_C7816_ISO_7816E_MASK
+#define UARTx_C7816_TTYPE_MASK                    (0x2U)
+#define UARTx_C7816_TTYPE_SHIFT                   (1U)
+#define UARTx_C7816_TTYPE_SET(x)                  (((uint8_t)(((uint8_t)(x)) << UARTx_C7816_TTYPE_SHIFT)) & UARTx_C7816_TTYPE_MASK)
+#define UARTx_C7816_TTYPE UARTx_C7816_TTYPE_MASK
+#define UARTx_C7816_INIT_MASK                     (0x4U)
+#define UARTx_C7816_INIT_SHIFT                    (2U)
+#define UARTx_C7816_INIT_SET(x)                   (((uint8_t)(((uint8_t)(x)) << UARTx_C7816_INIT_SHIFT)) & UARTx_C7816_INIT_MASK)
+#define UARTx_C7816_INIT UARTx_C7816_INIT_MASK
+#define UARTx_C7816_ANACK_MASK                    (0x8U)
+#define UARTx_C7816_ANACK_SHIFT                   (3U)
+#define UARTx_C7816_ANACK_SET(x)                  (((uint8_t)(((uint8_t)(x)) << UARTx_C7816_ANACK_SHIFT)) & UARTx_C7816_ANACK_MASK)
+#define UARTx_C7816_ANACK UARTx_C7816_ANACK_MASK
+#define UARTx_C7816_ONACK_MASK                    (0x10U)
+#define UARTx_C7816_ONACK_SHIFT                   (4U)
+#define UARTx_C7816_ONACK_SET(x)                  (((uint8_t)(((uint8_t)(x)) << UARTx_C7816_ONACK_SHIFT)) & UARTx_C7816_ONACK_MASK)
+#define UARTx_C7816_ONACK UARTx_C7816_ONACK_MASK
 
 /*! @name IE7816 - UART 7816 Interrupt Enable Register */
-#define UART_IE7816_RXTE_MASK                    (0x1U)
-#define UART_IE7816_RXTE_SHIFT                   (0U)
-#define UART_IE7816_RXTE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_IE7816_RXTE_SHIFT)) & UART_IE7816_RXTE_MASK)
-#define UART_IE7816_TXTE_MASK                    (0x2U)
-#define UART_IE7816_TXTE_SHIFT                   (1U)
-#define UART_IE7816_TXTE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_IE7816_TXTE_SHIFT)) & UART_IE7816_TXTE_MASK)
-#define UART_IE7816_GTVE_MASK                    (0x4U)
-#define UART_IE7816_GTVE_SHIFT                   (2U)
-#define UART_IE7816_GTVE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_IE7816_GTVE_SHIFT)) & UART_IE7816_GTVE_MASK)
-#define UART_IE7816_ADTE_MASK                    (0x8U)
-#define UART_IE7816_ADTE_SHIFT                   (3U)
-#define UART_IE7816_ADTE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_IE7816_ADTE_SHIFT)) & UART_IE7816_ADTE_MASK)
-#define UART_IE7816_INITDE_MASK                  (0x10U)
-#define UART_IE7816_INITDE_SHIFT                 (4U)
-#define UART_IE7816_INITDE(x)                    (((uint8_t)(((uint8_t)(x)) << UART_IE7816_INITDE_SHIFT)) & UART_IE7816_INITDE_MASK)
-#define UART_IE7816_BWTE_MASK                    (0x20U)
-#define UART_IE7816_BWTE_SHIFT                   (5U)
-#define UART_IE7816_BWTE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_IE7816_BWTE_SHIFT)) & UART_IE7816_BWTE_MASK)
-#define UART_IE7816_CWTE_MASK                    (0x40U)
-#define UART_IE7816_CWTE_SHIFT                   (6U)
-#define UART_IE7816_CWTE(x)                      (((uint8_t)(((uint8_t)(x)) << UART_IE7816_CWTE_SHIFT)) & UART_IE7816_CWTE_MASK)
-#define UART_IE7816_WTE_MASK                     (0x80U)
-#define UART_IE7816_WTE_SHIFT                    (7U)
-#define UART_IE7816_WTE(x)                       (((uint8_t)(((uint8_t)(x)) << UART_IE7816_WTE_SHIFT)) & UART_IE7816_WTE_MASK)
+#define UARTx_IE7816_RXTE_MASK                    (0x1U)
+#define UARTx_IE7816_RXTE_SHIFT                   (0U)
+#define UARTx_IE7816_RXTE_SET(x)                  (((uint8_t)(((uint8_t)(x)) << UARTx_IE7816_RXTE_SHIFT)) & UARTx_IE7816_RXTE_MASK)
+#define UARTx_IE7816_RXTE UARTx_IE7816_RXTE_MASK
+#define UARTx_IE7816_TXTE_MASK                    (0x2U)
+#define UARTx_IE7816_TXTE_SHIFT                   (1U)
+#define UARTx_IE7816_TXTE_SET(x)                  (((uint8_t)(((uint8_t)(x)) << UARTx_IE7816_TXTE_SHIFT)) & UARTx_IE7816_TXTE_MASK)
+#define UARTx_IE7816_TXTE UARTx_IE7816_TXTE_MASK
+#define UARTx_IE7816_GTVE_MASK                    (0x4U)
+#define UARTx_IE7816_GTVE_SHIFT                   (2U)
+#define UARTx_IE7816_GTVE_SET(x)                  (((uint8_t)(((uint8_t)(x)) << UARTx_IE7816_GTVE_SHIFT)) & UARTx_IE7816_GTVE_MASK)
+#define UARTx_IE7816_GTVE UARTx_IE7816_GTVE_MASK
+#define UARTx_IE7816_ADTE_MASK                    (0x8U)
+#define UARTx_IE7816_ADTE_SHIFT                   (3U)
+#define UARTx_IE7816_ADTE_SET(x)                  (((uint8_t)(((uint8_t)(x)) << UARTx_IE7816_ADTE_SHIFT)) & UARTx_IE7816_ADTE_MASK)
+#define UARTx_IE7816_ADTE UARTx_IE7816_ADTE_MASK
+#define UARTx_IE7816_INITDE_MASK                  (0x10U)
+#define UARTx_IE7816_INITDE_SHIFT                 (4U)
+#define UARTx_IE7816_INITDE_SET(x)                (((uint8_t)(((uint8_t)(x)) << UARTx_IE7816_INITDE_SHIFT)) & UARTx_IE7816_INITDE_MASK)
+#define UARTx_IE7816_INITDE UARTx_IE7816_INITDE_MASK
+#define UARTx_IE7816_BWTE_MASK                    (0x20U)
+#define UARTx_IE7816_BWTE_SHIFT                   (5U)
+#define UARTx_IE7816_BWTE_SET(x)                  (((uint8_t)(((uint8_t)(x)) << UARTx_IE7816_BWTE_SHIFT)) & UARTx_IE7816_BWTE_MASK)
+#define UARTx_IE7816_BWTE UARTx_IE7816_BWTE_MASK
+#define UARTx_IE7816_CWTE_MASK                    (0x40U)
+#define UARTx_IE7816_CWTE_SHIFT                   (6U)
+#define UARTx_IE7816_CWTE_SET(x)                  (((uint8_t)(((uint8_t)(x)) << UARTx_IE7816_CWTE_SHIFT)) & UARTx_IE7816_CWTE_MASK)
+#define UARTx_IE7816_CWTE UARTx_IE7816_CWTE_MASK
+#define UARTx_IE7816_WTE_MASK                     (0x80U)
+#define UARTx_IE7816_WTE_SHIFT                    (7U)
+#define UARTx_IE7816_WTE_SET(x)                   (((uint8_t)(((uint8_t)(x)) << UARTx_IE7816_WTE_SHIFT)) & UARTx_IE7816_WTE_MASK)
+#define UARTx_IE7816_WTE UARTx_IE7816_WTE_MASK
 
 /*! @name IS7816 - UART 7816 Interrupt Status Register */
-#define UART_IS7816_RXT_MASK                     (0x1U)
-#define UART_IS7816_RXT_SHIFT                    (0U)
-#define UART_IS7816_RXT(x)                       (((uint8_t)(((uint8_t)(x)) << UART_IS7816_RXT_SHIFT)) & UART_IS7816_RXT_MASK)
-#define UART_IS7816_TXT_MASK                     (0x2U)
-#define UART_IS7816_TXT_SHIFT                    (1U)
-#define UART_IS7816_TXT(x)                       (((uint8_t)(((uint8_t)(x)) << UART_IS7816_TXT_SHIFT)) & UART_IS7816_TXT_MASK)
-#define UART_IS7816_GTV_MASK                     (0x4U)
-#define UART_IS7816_GTV_SHIFT                    (2U)
-#define UART_IS7816_GTV(x)                       (((uint8_t)(((uint8_t)(x)) << UART_IS7816_GTV_SHIFT)) & UART_IS7816_GTV_MASK)
-#define UART_IS7816_ADT_MASK                     (0x8U)
-#define UART_IS7816_ADT_SHIFT                    (3U)
-#define UART_IS7816_ADT(x)                       (((uint8_t)(((uint8_t)(x)) << UART_IS7816_ADT_SHIFT)) & UART_IS7816_ADT_MASK)
-#define UART_IS7816_INITD_MASK                   (0x10U)
-#define UART_IS7816_INITD_SHIFT                  (4U)
-#define UART_IS7816_INITD(x)                     (((uint8_t)(((uint8_t)(x)) << UART_IS7816_INITD_SHIFT)) & UART_IS7816_INITD_MASK)
-#define UART_IS7816_BWT_MASK                     (0x20U)
-#define UART_IS7816_BWT_SHIFT                    (5U)
-#define UART_IS7816_BWT(x)                       (((uint8_t)(((uint8_t)(x)) << UART_IS7816_BWT_SHIFT)) & UART_IS7816_BWT_MASK)
-#define UART_IS7816_CWT_MASK                     (0x40U)
-#define UART_IS7816_CWT_SHIFT                    (6U)
-#define UART_IS7816_CWT(x)                       (((uint8_t)(((uint8_t)(x)) << UART_IS7816_CWT_SHIFT)) & UART_IS7816_CWT_MASK)
-#define UART_IS7816_WT_MASK                      (0x80U)
-#define UART_IS7816_WT_SHIFT                     (7U)
-#define UART_IS7816_WT(x)                        (((uint8_t)(((uint8_t)(x)) << UART_IS7816_WT_SHIFT)) & UART_IS7816_WT_MASK)
+#define UARTx_IS7816_RXT_MASK                     (0x1U)
+#define UARTx_IS7816_RXT_SHIFT                    (0U)
+#define UARTx_IS7816_RXT_SET(x)                   (((uint8_t)(((uint8_t)(x)) << UARTx_IS7816_RXT_SHIFT)) & UARTx_IS7816_RXT_MASK)
+#define UARTx_IS7816_RXT UARTx_IS7816_RXT_MASK
+#define UARTx_IS7816_TXT_MASK                     (0x2U)
+#define UARTx_IS7816_TXT_SHIFT                    (1U)
+#define UARTx_IS7816_TXT_SET(x)                   (((uint8_t)(((uint8_t)(x)) << UARTx_IS7816_TXT_SHIFT)) & UARTx_IS7816_TXT_MASK)
+#define UARTx_IS7816_TXT UARTx_IS7816_TXT_MASK
+#define UARTx_IS7816_GTV_MASK                     (0x4U)
+#define UARTx_IS7816_GTV_SHIFT                    (2U)
+#define UARTx_IS7816_GTV_SET(x)                   (((uint8_t)(((uint8_t)(x)) << UARTx_IS7816_GTV_SHIFT)) & UARTx_IS7816_GTV_MASK)
+#define UARTx_IS7816_GTV UARTx_IS7816_GTV_MASK
+#define UARTx_IS7816_ADT_MASK                     (0x8U)
+#define UARTx_IS7816_ADT_SHIFT                    (3U)
+#define UARTx_IS7816_ADT_SET(x)                   (((uint8_t)(((uint8_t)(x)) << UARTx_IS7816_ADT_SHIFT)) & UARTx_IS7816_ADT_MASK)
+#define UARTx_IS7816_ADT UARTx_IS7816_ADT_MASK
+#define UARTx_IS7816_INITD_MASK                   (0x10U)
+#define UARTx_IS7816_INITD_SHIFT                  (4U)
+#define UARTx_IS7816_INITD_SET(x)                 (((uint8_t)(((uint8_t)(x)) << UARTx_IS7816_INITD_SHIFT)) & UARTx_IS7816_INITD_MASK)
+#define UARTx_IS7816_INITD UARTx_IS7816_INITD_MASK
+#define UARTx_IS7816_BWT_MASK                     (0x20U)
+#define UARTx_IS7816_BWT_SHIFT                    (5U)
+#define UARTx_IS7816_BWT_SET(x)                   (((uint8_t)(((uint8_t)(x)) << UARTx_IS7816_BWT_SHIFT)) & UARTx_IS7816_BWT_MASK)
+#define UARTx_IS7816_BWT UARTx_IS7816_BWT_MASK
+#define UARTx_IS7816_CWT_MASK                     (0x40U)
+#define UARTx_IS7816_CWT_SHIFT                    (6U)
+#define UARTx_IS7816_CWT_SET(x)                   (((uint8_t)(((uint8_t)(x)) << UARTx_IS7816_CWT_SHIFT)) & UARTx_IS7816_CWT_MASK)
+#define UARTx_IS7816_CWT UARTx_IS7816_CWT_MASK
+#define UARTx_IS7816_WT_MASK                      (0x80U)
+#define UARTx_IS7816_WT_SHIFT                     (7U)
+#define UARTx_IS7816_WT_SET(x)                    (((uint8_t)(((uint8_t)(x)) << UARTx_IS7816_WT_SHIFT)) & UARTx_IS7816_WT_MASK)
+#define UARTx_IS7816_WT UARTx_IS7816_WT_MASK
 
 /*! @name WP7816 - UART 7816 Wait Parameter Register */
-#define UART_WP7816_WTX_MASK                     (0xFFU)
-#define UART_WP7816_WTX_SHIFT                    (0U)
-#define UART_WP7816_WTX(x)                       (((uint8_t)(((uint8_t)(x)) << UART_WP7816_WTX_SHIFT)) & UART_WP7816_WTX_MASK)
+#define UARTx_WP7816_WTX_MASK                     (0xFFU)
+#define UARTx_WP7816_WTX_SHIFT                    (0U)
+#define UARTx_WP7816_WTX_SET(x)                   (((uint8_t)(((uint8_t)(x)) << UARTx_WP7816_WTX_SHIFT)) & UARTx_WP7816_WTX_MASK)
+#define UARTx_WP7816_WTX UARTx_WP7816_WTX_MASK
 
 /*! @name WN7816 - UART 7816 Wait N Register */
-#define UART_WN7816_GTN_MASK                     (0xFFU)
-#define UART_WN7816_GTN_SHIFT                    (0U)
-#define UART_WN7816_GTN(x)                       (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK)
+#define UARTx_WN7816_GTN_MASK                     (0xFFU)
+#define UARTx_WN7816_GTN_SHIFT                    (0U)
+#define UARTx_WN7816_GTN_SET(x)                   (((uint8_t)(((uint8_t)(x)) << UARTx_WN7816_GTN_SHIFT)) & UARTx_WN7816_GTN_MASK)
+#define UARTx_WN7816_GTN UARTx_WN7816_GTN_MASK
 
 /*! @name WF7816 - UART 7816 Wait FD Register */
-#define UART_WF7816_GTFD_MASK                    (0xFFU)
-#define UART_WF7816_GTFD_SHIFT                   (0U)
-#define UART_WF7816_GTFD(x)                      (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK)
+#define UARTx_WF7816_GTFD_MASK                    (0xFFU)
+#define UARTx_WF7816_GTFD_SHIFT                   (0U)
+#define UARTx_WF7816_GTFD_SET(x)                  (((uint8_t)(((uint8_t)(x)) << UARTx_WF7816_GTFD_SHIFT)) & UARTx_WF7816_GTFD_MASK)
+#define UARTx_WF7816_GTFD UARTx_WF7816_GTFD_MASK
 
 /*! @name ET7816 - UART 7816 Error Threshold Register */
-#define UART_ET7816_RXTHRESHOLD_MASK             (0xFU)
-#define UART_ET7816_RXTHRESHOLD_SHIFT            (0U)
-#define UART_ET7816_RXTHRESHOLD(x)               (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK)
-#define UART_ET7816_TXTHRESHOLD_MASK             (0xF0U)
-#define UART_ET7816_TXTHRESHOLD_SHIFT            (4U)
-#define UART_ET7816_TXTHRESHOLD(x)               (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK)
+#define UARTx_ET7816_RXTHRESHOLD_MASK             (0xFU)
+#define UARTx_ET7816_RXTHRESHOLD_SHIFT            (0U)
+#define UARTx_ET7816_RXTHRESHOLD_SET(x)           (((uint8_t)(((uint8_t)(x)) << UARTx_ET7816_RXTHRESHOLD_SHIFT)) & UARTx_ET7816_RXTHRESHOLD_MASK)
+#define UARTx_ET7816_RXTHRESHOLD UARTx_ET7816_RXTHRESHOLD_MASK
+#define UARTx_ET7816_TXTHRESHOLD_MASK             (0xF0U)
+#define UARTx_ET7816_TXTHRESHOLD_SHIFT            (4U)
+#define UARTx_ET7816_TXTHRESHOLD_SET(x)           (((uint8_t)(((uint8_t)(x)) << UARTx_ET7816_TXTHRESHOLD_SHIFT)) & UARTx_ET7816_TXTHRESHOLD_MASK)
+#define UARTx_ET7816_TXTHRESHOLD UARTx_ET7816_TXTHRESHOLD_MASK
 
 /*! @name TL7816 - UART 7816 Transmit Length Register */
-#define UART_TL7816_TLEN_MASK                    (0xFFU)
-#define UART_TL7816_TLEN_SHIFT                   (0U)
-#define UART_TL7816_TLEN(x)                      (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK)
+#define UARTx_TL7816_TLEN_MASK                    (0xFFU)
+#define UARTx_TL7816_TLEN_SHIFT                   (0U)
+#define UARTx_TL7816_TLEN_SET(x)                  (((uint8_t)(((uint8_t)(x)) << UARTx_TL7816_TLEN_SHIFT)) & UARTx_TL7816_TLEN_MASK)
+#define UARTx_TL7816_TLEN UARTx_TL7816_TLEN_MASK
 
 /*! @name AP7816A_T0 - UART 7816 ATR Duration Timer Register A */
-#define UART_AP7816A_T0_ADTI_H_MASK              (0xFFU)
-#define UART_AP7816A_T0_ADTI_H_SHIFT             (0U)
-#define UART_AP7816A_T0_ADTI_H(x)                (((uint8_t)(((uint8_t)(x)) << UART_AP7816A_T0_ADTI_H_SHIFT)) & UART_AP7816A_T0_ADTI_H_MASK)
+#define UARTx_AP7816A_T0_ADTI_H_MASK              (0xFFU)
+#define UARTx_AP7816A_T0_ADTI_H_SHIFT             (0U)
+#define UARTx_AP7816A_T0_ADTI_H_SET(x)            (((uint8_t)(((uint8_t)(x)) << UARTx_AP7816A_T0_ADTI_H_SHIFT)) & UARTx_AP7816A_T0_ADTI_H_MASK)
+#define UARTx_AP7816A_T0_ADTI_H UARTx_AP7816A_T0_ADTI_H_MASK
 
 /*! @name AP7816B_T0 - UART 7816 ATR Duration Timer Register B */
-#define UART_AP7816B_T0_ADTI_L_MASK              (0xFFU)
-#define UART_AP7816B_T0_ADTI_L_SHIFT             (0U)
-#define UART_AP7816B_T0_ADTI_L(x)                (((uint8_t)(((uint8_t)(x)) << UART_AP7816B_T0_ADTI_L_SHIFT)) & UART_AP7816B_T0_ADTI_L_MASK)
+#define UARTx_AP7816B_T0_ADTI_L_MASK              (0xFFU)
+#define UARTx_AP7816B_T0_ADTI_L_SHIFT             (0U)
+#define UARTx_AP7816B_T0_ADTI_L_SET(x)            (((uint8_t)(((uint8_t)(x)) << UARTx_AP7816B_T0_ADTI_L_SHIFT)) & UARTx_AP7816B_T0_ADTI_L_MASK)
+#define UARTx_AP7816B_T0_ADTI_L UARTx_AP7816B_T0_ADTI_L_MASK
 
 /*! @name WP7816A_T0 - UART 7816 Wait Parameter Register A */
-#define UART_WP7816A_T0_WI_H_MASK                (0xFFU)
-#define UART_WP7816A_T0_WI_H_SHIFT               (0U)
-#define UART_WP7816A_T0_WI_H(x)                  (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T0_WI_H_SHIFT)) & UART_WP7816A_T0_WI_H_MASK)
+#define UARTx_WP7816A_T0_WI_H_MASK                (0xFFU)
+#define UARTx_WP7816A_T0_WI_H_SHIFT               (0U)
+#define UARTx_WP7816A_T0_WI_H_SET(x)              (((uint8_t)(((uint8_t)(x)) << UARTx_WP7816A_T0_WI_H_SHIFT)) & UARTx_WP7816A_T0_WI_H_MASK)
+#define UARTx_WP7816A_T0_WI_H UARTx_WP7816A_T0_WI_H_MASK
 
 /*! @name WP7816B_T0 - UART 7816 Wait Parameter Register B */
-#define UART_WP7816B_T0_WI_L_MASK                (0xFFU)
-#define UART_WP7816B_T0_WI_L_SHIFT               (0U)
-#define UART_WP7816B_T0_WI_L(x)                  (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T0_WI_L_SHIFT)) & UART_WP7816B_T0_WI_L_MASK)
+#define UARTx_WP7816B_T0_WI_L_MASK                (0xFFU)
+#define UARTx_WP7816B_T0_WI_L_SHIFT               (0U)
+#define UARTx_WP7816B_T0_WI_L_SET(x)              (((uint8_t)(((uint8_t)(x)) << UARTx_WP7816B_T0_WI_L_SHIFT)) & UARTx_WP7816B_T0_WI_L_MASK)
+#define UARTx_WP7816B_T0_WI_L UARTx_WP7816B_T0_WI_L_MASK
 
 /*! @name WP7816A_T1 - UART 7816 Wait Parameter Register A */
-#define UART_WP7816A_T1_BWI_H_MASK               (0xFFU)
-#define UART_WP7816A_T1_BWI_H_SHIFT              (0U)
-#define UART_WP7816A_T1_BWI_H(x)                 (((uint8_t)(((uint8_t)(x)) << UART_WP7816A_T1_BWI_H_SHIFT)) & UART_WP7816A_T1_BWI_H_MASK)
+#define UARTx_WP7816A_T1_BWI_H_MASK               (0xFFU)
+#define UARTx_WP7816A_T1_BWI_H_SHIFT              (0U)
+#define UARTx_WP7816A_T1_BWI_H_SET(x)             (((uint8_t)(((uint8_t)(x)) << UARTx_WP7816A_T1_BWI_H_SHIFT)) & UARTx_WP7816A_T1_BWI_H_MASK)
+#define UARTx_WP7816A_T1_BWI_H UARTx_WP7816A_T1_BWI_H_MASK
 
 /*! @name WP7816B_T1 - UART 7816 Wait Parameter Register B */
-#define UART_WP7816B_T1_BWI_L_MASK               (0xFFU)
-#define UART_WP7816B_T1_BWI_L_SHIFT              (0U)
-#define UART_WP7816B_T1_BWI_L(x)                 (((uint8_t)(((uint8_t)(x)) << UART_WP7816B_T1_BWI_L_SHIFT)) & UART_WP7816B_T1_BWI_L_MASK)
+#define UARTx_WP7816B_T1_BWI_L_MASK               (0xFFU)
+#define UARTx_WP7816B_T1_BWI_L_SHIFT              (0U)
+#define UARTx_WP7816B_T1_BWI_L_SET(x)             (((uint8_t)(((uint8_t)(x)) << UARTx_WP7816B_T1_BWI_L_SHIFT)) & UARTx_WP7816B_T1_BWI_L_MASK)
+#define UARTx_WP7816B_T1_BWI_L UARTx_WP7816B_T1_BWI_L_MASK
 
 /*! @name WGP7816_T1 - UART 7816 Wait and Guard Parameter Register */
-#define UART_WGP7816_T1_BGI_MASK                 (0xFU)
-#define UART_WGP7816_T1_BGI_SHIFT                (0U)
-#define UART_WGP7816_T1_BGI(x)                   (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_BGI_SHIFT)) & UART_WGP7816_T1_BGI_MASK)
-#define UART_WGP7816_T1_CWI1_MASK                (0xF0U)
-#define UART_WGP7816_T1_CWI1_SHIFT               (4U)
-#define UART_WGP7816_T1_CWI1(x)                  (((uint8_t)(((uint8_t)(x)) << UART_WGP7816_T1_CWI1_SHIFT)) & UART_WGP7816_T1_CWI1_MASK)
+#define UARTx_WGP7816_T1_BGI_MASK                 (0xFU)
+#define UARTx_WGP7816_T1_BGI_SHIFT                (0U)
+#define UARTx_WGP7816_T1_BGI_SET(x)               (((uint8_t)(((uint8_t)(x)) << UARTx_WGP7816_T1_BGI_SHIFT)) & UARTx_WGP7816_T1_BGI_MASK)
+#define UARTx_WGP7816_T1_BGI UARTx_WGP7816_T1_BGI_MASK
+#define UARTx_WGP7816_T1_CWI1_MASK                (0xF0U)
+#define UARTx_WGP7816_T1_CWI1_SHIFT               (4U)
+#define UARTx_WGP7816_T1_CWI1_SET(x)              (((uint8_t)(((uint8_t)(x)) << UARTx_WGP7816_T1_CWI1_SHIFT)) & UARTx_WGP7816_T1_CWI1_MASK)
+#define UARTx_WGP7816_T1_CWI1 UARTx_WGP7816_T1_CWI1_MASK
 
 /*! @name WP7816C_T1 - UART 7816 Wait Parameter Register C */
-#define UART_WP7816C_T1_CWI2_MASK                (0x1FU)
-#define UART_WP7816C_T1_CWI2_SHIFT               (0U)
-#define UART_WP7816C_T1_CWI2(x)                  (((uint8_t)(((uint8_t)(x)) << UART_WP7816C_T1_CWI2_SHIFT)) & UART_WP7816C_T1_CWI2_MASK)
+#define UARTx_WP7816C_T1_CWI2_MASK                (0x1FU)
+#define UARTx_WP7816C_T1_CWI2_SHIFT               (0U)
+#define UARTx_WP7816C_T1_CWI2_SET(x)              (((uint8_t)(((uint8_t)(x)) << UARTx_WP7816C_T1_CWI2_SHIFT)) & UARTx_WP7816C_T1_CWI2_MASK)
+#define UARTx_WP7816C_T1_CWI2 UARTx_WP7816C_T1_CWI2_MASK
 
 
 /*!
  * @}
- */ /* end of group UART_Register_Masks */
+ */ /* end of group UARTx_Register_Masks */
 
 
 /* UART - Peripheral instance base addresses */
 /** Peripheral UART0 base address */
 #define UART0_BASE                               (0x4006A000u)
 /** Peripheral UART0 base pointer */
-#define UART0                                    ((UART_Type *)UART0_BASE)
+#define UART0                                    ((UART_TypeDef *)UART0_BASE)
 /** Peripheral UART1 base address */
 #define UART1_BASE                               (0x4006B000u)
 /** Peripheral UART1 base pointer */
-#define UART1                                    ((UART_Type *)UART1_BASE)
+#define UART1                                    ((UART_TypeDef *)UART1_BASE)
 /** Peripheral UART2 base address */
 #define UART2_BASE                               (0x4006C000u)
 /** Peripheral UART2 base pointer */
-#define UART2                                    ((UART_Type *)UART2_BASE)
+#define UART2                                    ((UART_TypeDef *)UART2_BASE)
 /** Peripheral UART3 base address */
 #define UART3_BASE                               (0x4006D000u)
 /** Peripheral UART3 base pointer */
-#define UART3                                    ((UART_Type *)UART3_BASE)
+#define UART3                                    ((UART_TypeDef *)UART3_BASE)
 /** Peripheral UART4 base address */
 #define UART4_BASE                               (0x400EA000u)
 /** Peripheral UART4 base pointer */
-#define UART4                                    ((UART_Type *)UART4_BASE)
+#define UART4                                    ((UARTTypeDef *)UART4_BASE)
 /** Array initializer of UART peripheral base addresses */
-#define UART_BASE_ADDRS                          { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE }
+#define UARTx_BASE_ADDRS                          { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE }
 /** Array initializer of UART peripheral base pointers */
-#define UART_BASE_PTRS                           { UART0, UART1, UART2, UART3, UART4 }
+#define UARTx_BASE_PTRS                           { UART0, UART1, UART2, UART3, UART4 }
 /** Interrupt vectors for the UART peripheral type */
-#define UART_RX_TX_IRQS                          { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn, UART3_RX_TX_IRQn, UART4_RX_TX_IRQn }
-#define UART_ERR_IRQS                            { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn, UART3_ERR_IRQn, UART4_ERR_IRQn }
+#define UARTx_RX_TX_IRQS                          { UART0Status_IRQn, UART1Status_IRQn, UART2Status_IRQn, UART3Status_IRQn, UART4Status_IRQn }
+#define UARTx_ERR_IRQS                            { UART0Error_IRQn, UART1Error_IRQn, UART2Error_IRQn, UART3Error_IRQn, UART4Error_IRQn }
 
 /*!
  * @}
- */ /* end of group UART_Peripheral_Access_Layer */
+ */ /* end of group UARTx_Peripheral_Access_Layer */
 
 
 /* ----------------------------------------------------------------------------
@@ -14235,7 +17186,7 @@ typedef struct {
   __IO uint8_t CLK_RECOVER_INT_EN;                 /**< Clock recovery combined interrupt enable, offset: 0x154 */
        uint8_t RESERVED_29[7];
   __IO uint8_t CLK_RECOVER_INT_STATUS;             /**< Clock recovery separated interrupt status, offset: 0x15C */
-} USBx_Type;
+} USBx_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- USB Register Masks
@@ -14249,96 +17200,122 @@ typedef struct {
 /*! @name PERID - Peripheral ID register */
 #define USBx_PERID_ID_MASK                        (0x3FU)
 #define USBx_PERID_ID_SHIFT                       (0U)
-#define USBx_PERID_ID(x)                          (((uint8_t)(((uint8_t)(x)) << USBx_PERID_ID_SHIFT)) & USBx_PERID_ID_MASK)
+#define USBx_PERID_ID_SET(x)                      (((uint8_t)(((uint8_t)(x)) << USBx_PERID_ID_SHIFT)) & USBx_PERID_ID_MASK)
+#define USBx_PERID_ID USBx_PERID_ID_MASK
 
 /*! @name IDCOMP - Peripheral ID Complement register */
 #define USBx_IDCOMP_NID_MASK                      (0x3FU)
 #define USBx_IDCOMP_NID_SHIFT                     (0U)
-#define USBx_IDCOMP_NID(x)                        (((uint8_t)(((uint8_t)(x)) << USBx_IDCOMP_NID_SHIFT)) & USBx_IDCOMP_NID_MASK)
+#define USBx_IDCOMP_NID_SET(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_IDCOMP_NID_SHIFT)) & USBx_IDCOMP_NID_MASK)
+#define USBx_IDCOMP_NID USBx_IDCOMP_NID_MASK
 
 /*! @name REV - Peripheral Revision register */
 #define USBx_REV_REV_MASK                         (0xFFU)
 #define USBx_REV_REV_SHIFT                        (0U)
-#define USBx_REV_REV(x)                           (((uint8_t)(((uint8_t)(x)) << USBx_REV_REV_SHIFT)) & USBx_REV_REV_MASK)
+#define USBx_REV_REV_SET(x)                       (((uint8_t)(((uint8_t)(x)) << USBx_REV_REV_SHIFT)) & USBx_REV_REV_MASK)
+#define USBx_REV_REV USBx_REV_REV_MASK
 
 /*! @name ADDINFO - Peripheral Additional Info register */
 #define USBx_ADDINFO_IEHOST_MASK                  (0x1U)
 #define USBx_ADDINFO_IEHOST_SHIFT                 (0U)
-#define USBx_ADDINFO_IEHOST(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_ADDINFO_IEHOST_SHIFT)) & USBx_ADDINFO_IEHOST_MASK)
+#define USBx_ADDINFO_IEHOST_SET(x)                (((uint8_t)(((uint8_t)(x)) << USBx_ADDINFO_IEHOST_SHIFT)) & USBx_ADDINFO_IEHOST_MASK)
+#define USBx_ADDINFO_IEHOST USBx_ADDINFO_IEHOST_MASK
 
 /*! @name OTGISTAT - OTG Interrupt Status register */
 #define USBx_OTGISTAT_AVBUSCHG_MASK               (0x1U)
 #define USBx_OTGISTAT_AVBUSCHG_SHIFT              (0U)
-#define USBx_OTGISTAT_AVBUSCHG(x)                 (((uint8_t)(((uint8_t)(x)) << USBx_OTGISTAT_AVBUSCHG_SHIFT)) & USBx_OTGISTAT_AVBUSCHG_MASK)
+#define USBx_OTGISTAT_AVBUSCHG_SET(x)             (((uint8_t)(((uint8_t)(x)) << USBx_OTGISTAT_AVBUSCHG_SHIFT)) & USBx_OTGISTAT_AVBUSCHG_MASK)
+#define USBx_OTGISTAT_AVBUSCHG USBx_OTGISTAT_AVBUSCHG_MASK
 #define USBx_OTGISTAT_B_SESS_CHG_MASK             (0x4U)
 #define USBx_OTGISTAT_B_SESS_CHG_SHIFT            (2U)
-#define USBx_OTGISTAT_B_SESS_CHG(x)               (((uint8_t)(((uint8_t)(x)) << USBx_OTGISTAT_B_SESS_CHG_SHIFT)) & USBx_OTGISTAT_B_SESS_CHG_MASK)
+#define USBx_OTGISTAT_B_SESS_CHG_SET(x)           (((uint8_t)(((uint8_t)(x)) << USBx_OTGISTAT_B_SESS_CHG_SHIFT)) & USBx_OTGISTAT_B_SESS_CHG_MASK)
+#define USBx_OTGISTAT_B_SESS_CHG USBx_OTGISTAT_B_SESS_CHG_MASK
 #define USBx_OTGISTAT_SESSVLDCHG_MASK             (0x8U)
 #define USBx_OTGISTAT_SESSVLDCHG_SHIFT            (3U)
-#define USBx_OTGISTAT_SESSVLDCHG(x)               (((uint8_t)(((uint8_t)(x)) << USBx_OTGISTAT_SESSVLDCHG_SHIFT)) & USBx_OTGISTAT_SESSVLDCHG_MASK)
+#define USBx_OTGISTAT_SESSVLDCHG_SET(x)           (((uint8_t)(((uint8_t)(x)) << USBx_OTGISTAT_SESSVLDCHG_SHIFT)) & USBx_OTGISTAT_SESSVLDCHG_MASK)
+#define USBx_OTGISTAT_SESSVLDCHG USBx_OTGISTAT_SESSVLDCHG_MASK
 #define USBx_OTGISTAT_LINE_STATE_CHG_MASK         (0x20U)
 #define USBx_OTGISTAT_LINE_STATE_CHG_SHIFT        (5U)
-#define USBx_OTGISTAT_LINE_STATE_CHG(x)           (((uint8_t)(((uint8_t)(x)) << USBx_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USBx_OTGISTAT_LINE_STATE_CHG_MASK)
+#define USBx_OTGISTAT_LINE_STATE_CHG_SET(x)       (((uint8_t)(((uint8_t)(x)) << USBx_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USBx_OTGISTAT_LINE_STATE_CHG_MASK)
+#define USBx_OTGISTAT_LINE_STATE_CHG USBx_OTGISTAT_LINE_STATE_CHG_MASK
 #define USBx_OTGISTAT_ONEMSEC_MASK                (0x40U)
 #define USBx_OTGISTAT_ONEMSEC_SHIFT               (6U)
-#define USBx_OTGISTAT_ONEMSEC(x)                  (((uint8_t)(((uint8_t)(x)) << USBx_OTGISTAT_ONEMSEC_SHIFT)) & USBx_OTGISTAT_ONEMSEC_MASK)
+#define USBx_OTGISTAT_ONEMSEC_SET(x)              (((uint8_t)(((uint8_t)(x)) << USBx_OTGISTAT_ONEMSEC_SHIFT)) & USBx_OTGISTAT_ONEMSEC_MASK)
+#define USBx_OTGISTAT_ONEMSEC USBx_OTGISTAT_ONEMSEC_MASK
 #define USBx_OTGISTAT_IDCHG_MASK                  (0x80U)
 #define USBx_OTGISTAT_IDCHG_SHIFT                 (7U)
-#define USBx_OTGISTAT_IDCHG(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_OTGISTAT_IDCHG_SHIFT)) & USBx_OTGISTAT_IDCHG_MASK)
+#define USBx_OTGISTAT_IDCHG_SET(x)                (((uint8_t)(((uint8_t)(x)) << USBx_OTGISTAT_IDCHG_SHIFT)) & USBx_OTGISTAT_IDCHG_MASK)
+#define USBx_OTGISTAT_IDCHG USBx_OTGISTAT_IDCHG_MASK
 
 /*! @name OTGICR - OTG Interrupt Control register */
 #define USBx_OTGICR_AVBUSEN_MASK                  (0x1U)
 #define USBx_OTGICR_AVBUSEN_SHIFT                 (0U)
-#define USBx_OTGICR_AVBUSEN(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_OTGICR_AVBUSEN_SHIFT)) & USBx_OTGICR_AVBUSEN_MASK)
+#define USBx_OTGICR_AVBUSEN_SET(x)                (((uint8_t)(((uint8_t)(x)) << USBx_OTGICR_AVBUSEN_SHIFT)) & USBx_OTGICR_AVBUSEN_MASK)
+#define USBx_OTGICR_AVBUSEN USBx_OTGICR_AVBUSEN_MASK
 #define USBx_OTGICR_BSESSEN_MASK                  (0x4U)
 #define USBx_OTGICR_BSESSEN_SHIFT                 (2U)
-#define USBx_OTGICR_BSESSEN(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_OTGICR_BSESSEN_SHIFT)) & USBx_OTGICR_BSESSEN_MASK)
+#define USBx_OTGICR_BSESSEN_SET(x)                (((uint8_t)(((uint8_t)(x)) << USBx_OTGICR_BSESSEN_SHIFT)) & USBx_OTGICR_BSESSEN_MASK)
+#define USBx_OTGICR_BSESSEN USBx_OTGICR_BSESSEN_MASK
 #define USBx_OTGICR_SESSVLDEN_MASK                (0x8U)
 #define USBx_OTGICR_SESSVLDEN_SHIFT               (3U)
-#define USBx_OTGICR_SESSVLDEN(x)                  (((uint8_t)(((uint8_t)(x)) << USBx_OTGICR_SESSVLDEN_SHIFT)) & USBx_OTGICR_SESSVLDEN_MASK)
+#define USBx_OTGICR_SESSVLDEN_SET(x)              (((uint8_t)(((uint8_t)(x)) << USBx_OTGICR_SESSVLDEN_SHIFT)) & USBx_OTGICR_SESSVLDEN_MASK)
+#define USBx_OTGICR_SESSVLDEN USBx_OTGICR_SESSVLDEN_MASK
 #define USBx_OTGICR_LINESTATEEN_MASK              (0x20U)
 #define USBx_OTGICR_LINESTATEEN_SHIFT             (5U)
-#define USBx_OTGICR_LINESTATEEN(x)                (((uint8_t)(((uint8_t)(x)) << USBx_OTGICR_LINESTATEEN_SHIFT)) & USBx_OTGICR_LINESTATEEN_MASK)
+#define USBx_OTGICR_LINESTATEEN_SET(x)            (((uint8_t)(((uint8_t)(x)) << USBx_OTGICR_LINESTATEEN_SHIFT)) & USBx_OTGICR_LINESTATEEN_MASK)
+#define USBx_OTGICR_LINESTATEEN USBx_OTGICR_LINESTATEEN_MASK
 #define USBx_OTGICR_ONEMSECEN_MASK                (0x40U)
 #define USBx_OTGICR_ONEMSECEN_SHIFT               (6U)
-#define USBx_OTGICR_ONEMSECEN(x)                  (((uint8_t)(((uint8_t)(x)) << USBx_OTGICR_ONEMSECEN_SHIFT)) & USBx_OTGICR_ONEMSECEN_MASK)
+#define USBx_OTGICR_ONEMSECEN_SET(x)              (((uint8_t)(((uint8_t)(x)) << USBx_OTGICR_ONEMSECEN_SHIFT)) & USBx_OTGICR_ONEMSECEN_MASK)
+#define USBx_OTGICR_ONEMSECEN USBx_OTGICR_ONEMSECEN_MASK
 #define USBx_OTGICR_IDEN_MASK                     (0x80U)
 #define USBx_OTGICR_IDEN_SHIFT                    (7U)
-#define USBx_OTGICR_IDEN(x)                       (((uint8_t)(((uint8_t)(x)) << USBx_OTGICR_IDEN_SHIFT)) & USBx_OTGICR_IDEN_MASK)
+#define USBx_OTGICR_IDEN_SET(x)                   (((uint8_t)(((uint8_t)(x)) << USBx_OTGICR_IDEN_SHIFT)) & USBx_OTGICR_IDEN_MASK)
+#define USBx_OTGICR_IDEN USBx_OTGICR_IDEN_MASK
 
 /*! @name OTGSTAT - OTG Status register */
 #define USBx_OTGSTAT_AVBUSVLD_MASK                (0x1U)
 #define USBx_OTGSTAT_AVBUSVLD_SHIFT               (0U)
-#define USBx_OTGSTAT_AVBUSVLD(x)                  (((uint8_t)(((uint8_t)(x)) << USBx_OTGSTAT_AVBUSVLD_SHIFT)) & USBx_OTGSTAT_AVBUSVLD_MASK)
+#define USBx_OTGSTAT_AVBUSVLD_SET(x)              (((uint8_t)(((uint8_t)(x)) << USBx_OTGSTAT_AVBUSVLD_SHIFT)) & USBx_OTGSTAT_AVBUSVLD_MASK)
+#define USBx_OTGSTAT_AVBUSVLD USBx_OTGSTAT_AVBUSVLD_MASK
 #define USBx_OTGSTAT_BSESSEND_MASK                (0x4U)
 #define USBx_OTGSTAT_BSESSEND_SHIFT               (2U)
-#define USBx_OTGSTAT_BSESSEND(x)                  (((uint8_t)(((uint8_t)(x)) << USBx_OTGSTAT_BSESSEND_SHIFT)) & USBx_OTGSTAT_BSESSEND_MASK)
+#define USBx_OTGSTAT_BSESSEND_SET(x)              (((uint8_t)(((uint8_t)(x)) << USBx_OTGSTAT_BSESSEND_SHIFT)) & USBx_OTGSTAT_BSESSEND_MASK)
+#define USBx_OTGSTAT_BSESSEND USBx_OTGSTAT_BSESSEND_MASK
 #define USBx_OTGSTAT_SESS_VLD_MASK                (0x8U)
 #define USBx_OTGSTAT_SESS_VLD_SHIFT               (3U)
-#define USBx_OTGSTAT_SESS_VLD(x)                  (((uint8_t)(((uint8_t)(x)) << USBx_OTGSTAT_SESS_VLD_SHIFT)) & USBx_OTGSTAT_SESS_VLD_MASK)
+#define USBx_OTGSTAT_SESS_VLD_SET(x)              (((uint8_t)(((uint8_t)(x)) << USBx_OTGSTAT_SESS_VLD_SHIFT)) & USBx_OTGSTAT_SESS_VLD_MASK)
+#define USBx_OTGSTAT_SESS_VLD USBx_OTGSTAT_SESS_VLD_MASK
 #define USBx_OTGSTAT_LINESTATESTABLE_MASK         (0x20U)
 #define USBx_OTGSTAT_LINESTATESTABLE_SHIFT        (5U)
-#define USBx_OTGSTAT_LINESTATESTABLE(x)           (((uint8_t)(((uint8_t)(x)) << USBx_OTGSTAT_LINESTATESTABLE_SHIFT)) & USBx_OTGSTAT_LINESTATESTABLE_MASK)
+#define USBx_OTGSTAT_LINESTATESTABLE_SET(x)       (((uint8_t)(((uint8_t)(x)) << USBx_OTGSTAT_LINESTATESTABLE_SHIFT)) & USBx_OTGSTAT_LINESTATESTABLE_MASK)
+#define USBx_OTGSTAT_LINESTATESTABLE USBx_OTGSTAT_LINESTATESTABLE_MASK
 #define USBx_OTGSTAT_ONEMSECEN_MASK               (0x40U)
 #define USBx_OTGSTAT_ONEMSECEN_SHIFT              (6U)
-#define USBx_OTGSTAT_ONEMSECEN(x)                 (((uint8_t)(((uint8_t)(x)) << USBx_OTGSTAT_ONEMSECEN_SHIFT)) & USBx_OTGSTAT_ONEMSECEN_MASK)
+#define USBx_OTGSTAT_ONEMSECEN_SET(x)             (((uint8_t)(((uint8_t)(x)) << USBx_OTGSTAT_ONEMSECEN_SHIFT)) & USBx_OTGSTAT_ONEMSECEN_MASK)
+#define USBx_OTGSTAT_ONEMSECEN USBx_OTGSTAT_ONEMSECEN_MASK
 #define USBx_OTGSTAT_ID_MASK                      (0x80U)
 #define USBx_OTGSTAT_ID_SHIFT                     (7U)
-#define USBx_OTGSTAT_ID(x)                        (((uint8_t)(((uint8_t)(x)) << USBx_OTGSTAT_ID_SHIFT)) & USBx_OTGSTAT_ID_MASK)
+#define USBx_OTGSTAT_ID_SET(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_OTGSTAT_ID_SHIFT)) & USBx_OTGSTAT_ID_MASK)
+#define USBx_OTGSTAT_ID USBx_OTGSTAT_ID_MASK
 
 /*! @name OTGCTL - OTG Control register */
 #define USBx_OTGCTL_OTGEN_MASK                    (0x4U)
 #define USBx_OTGCTL_OTGEN_SHIFT                   (2U)
-#define USBx_OTGCTL_OTGEN(x)                      (((uint8_t)(((uint8_t)(x)) << USBx_OTGCTL_OTGEN_SHIFT)) & USBx_OTGCTL_OTGEN_MASK)
+#define USBx_OTGCTL_OTGEN_SET(x)                  (((uint8_t)(((uint8_t)(x)) << USBx_OTGCTL_OTGEN_SHIFT)) & USBx_OTGCTL_OTGEN_MASK)
+#define USBx_OTGCTL_OTGEN USBx_OTGCTL_OTGEN_MASK
 #define USBx_OTGCTL_DMLOW_MASK                    (0x10U)
 #define USBx_OTGCTL_DMLOW_SHIFT                   (4U)
-#define USBx_OTGCTL_DMLOW(x)                      (((uint8_t)(((uint8_t)(x)) << USBx_OTGCTL_DMLOW_SHIFT)) & USBx_OTGCTL_DMLOW_MASK)
+#define USBx_OTGCTL_DMLOW_SET(x)                  (((uint8_t)(((uint8_t)(x)) << USBx_OTGCTL_DMLOW_SHIFT)) & USBx_OTGCTL_DMLOW_MASK)
+#define USBx_OTGCTL_DMLOW USBx_OTGCTL_DMLOW_MASK
 #define USBx_OTGCTL_DPLOW_MASK                    (0x20U)
 #define USBx_OTGCTL_DPLOW_SHIFT                   (5U)
-#define USBx_OTGCTL_DPLOW(x)                      (((uint8_t)(((uint8_t)(x)) << USBx_OTGCTL_DPLOW_SHIFT)) & USBx_OTGCTL_DPLOW_MASK)
+#define USBx_OTGCTL_DPLOW_SET(x)                  (((uint8_t)(((uint8_t)(x)) << USBx_OTGCTL_DPLOW_SHIFT)) & USBx_OTGCTL_DPLOW_MASK)
+#define USBx_OTGCTL_DPLOW USBx_OTGCTL_DPLOW_MASK
 #define USBx_OTGCTL_DPHIGH_MASK                   (0x80U)
 #define USBx_OTGCTL_DPHIGH_SHIFT                  (7U)
-#define USBx_OTGCTL_DPHIGH(x)                     (((uint8_t)(((uint8_t)(x)) << USBx_OTGCTL_DPHIGH_SHIFT)) & USBx_OTGCTL_DPHIGH_MASK)
+#define USBx_OTGCTL_DPHIGH_SET(x)                 (((uint8_t)(((uint8_t)(x)) << USBx_OTGCTL_DPHIGH_SHIFT)) & USBx_OTGCTL_DPHIGH_MASK)
+#define USBx_OTGCTL_DPHIGH USBx_OTGCTL_DPHIGH_MASK
 
 /*! @name ISTAT - Interrupt Status register */
 #define USBx_ISTAT_USBRST_MASK                    (0x1U)
@@ -14367,7 +17344,8 @@ typedef struct {
 #define USBx_ISTAT_RESUME                         USBx_ISTAT_RESUME_SET(1)
 #define USBx_ISTAT_ATTACH_MASK                    (0x40U)
 #define USBx_ISTAT_ATTACH_SHIFT                   (6U)
-#define USBx_ISTAT_ATTACH(x)                      (((uint8_t)(((uint8_t)(x)) << USBx_ISTAT_ATTACH_SHIFT)) & USBx_ISTAT_ATTACH_MASK)
+#define USBx_ISTAT_ATTACH_SET(x)                  (((uint8_t)(((uint8_t)(x)) << USBx_ISTAT_ATTACH_SHIFT)) & USBx_ISTAT_ATTACH_MASK)
+#define USBx_ISTAT_ATTACH USBx_ISTAT_ATTACH_MASK
 #define USBx_ISTAT_STALL_MASK                     (0x80U)
 #define USBx_ISTAT_STALL_SHIFT                    (7U)
 #define USBx_ISTAT_STALL_SET(x)                   (((uint8_t)(((uint8_t)(x)) << USBx_ISTAT_STALL_SHIFT)) & USBx_ISTAT_STALL_MASK)
@@ -14400,7 +17378,8 @@ typedef struct {
 #define USBx_INTEN_RESUMEEN                       USBx_INTEN_RESUMEEN_SET(1)
 #define USBx_INTEN_ATTACHEN_MASK                  (0x40U)
 #define USBx_INTEN_ATTACHEN_SHIFT                 (6U)
-#define USBx_INTEN_ATTACHEN(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_INTEN_ATTACHEN_SHIFT)) & USBx_INTEN_ATTACHEN_MASK)
+#define USBx_INTEN_ATTACHEN_SET(x)                (((uint8_t)(((uint8_t)(x)) << USBx_INTEN_ATTACHEN_SHIFT)) & USBx_INTEN_ATTACHEN_MASK)
+#define USBx_INTEN_ATTACHEN USBx_INTEN_ATTACHEN_MASK
 #define USBx_INTEN_STALLEN_MASK                   (0x80U)
 #define USBx_INTEN_STALLEN_SHIFT                  (7U)
 #define USBx_INTEN_STALLEN_SET(x)                 (((uint8_t)(((uint8_t)(x)) << USBx_INTEN_STALLEN_SHIFT)) & USBx_INTEN_STALLEN_MASK)
@@ -14409,59 +17388,76 @@ typedef struct {
 /*! @name ERRSTAT - Error Interrupt Status register */
 #define USBx_ERRSTAT_PIDERR_MASK                  (0x1U)
 #define USBx_ERRSTAT_PIDERR_SHIFT                 (0U)
-#define USBx_ERRSTAT_PIDERR(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_ERRSTAT_PIDERR_SHIFT)) & USBx_ERRSTAT_PIDERR_MASK)
+#define USBx_ERRSTAT_PIDERR_SET(x)                (((uint8_t)(((uint8_t)(x)) << USBx_ERRSTAT_PIDERR_SHIFT)) & USBx_ERRSTAT_PIDERR_MASK)
+#define USBx_ERRSTAT_PIDERR USBx_ERRSTAT_PIDERR_MASK
 #define USBx_ERRSTAT_CRC5EOF_MASK                 (0x2U)
 #define USBx_ERRSTAT_CRC5EOF_SHIFT                (1U)
-#define USBx_ERRSTAT_CRC5EOF(x)                   (((uint8_t)(((uint8_t)(x)) << USBx_ERRSTAT_CRC5EOF_SHIFT)) & USBx_ERRSTAT_CRC5EOF_MASK)
+#define USBx_ERRSTAT_CRC5EOF_SET(x)               (((uint8_t)(((uint8_t)(x)) << USBx_ERRSTAT_CRC5EOF_SHIFT)) & USBx_ERRSTAT_CRC5EOF_MASK)
+#define USBx_ERRSTAT_CRC5EOF USBx_ERRSTAT_CRC5EOF_MASK
 #define USBx_ERRSTAT_CRC16_MASK                   (0x4U)
 #define USBx_ERRSTAT_CRC16_SHIFT                  (2U)
-#define USBx_ERRSTAT_CRC16(x)                     (((uint8_t)(((uint8_t)(x)) << USBx_ERRSTAT_CRC16_SHIFT)) & USBx_ERRSTAT_CRC16_MASK)
+#define USBx_ERRSTAT_CRC16_SET(x)                 (((uint8_t)(((uint8_t)(x)) << USBx_ERRSTAT_CRC16_SHIFT)) & USBx_ERRSTAT_CRC16_MASK)
+#define USBx_ERRSTAT_CRC16 USBx_ERRSTAT_CRC16_MASK
 #define USBx_ERRSTAT_DFN8_MASK                    (0x8U)
 #define USBx_ERRSTAT_DFN8_SHIFT                   (3U)
-#define USBx_ERRSTAT_DFN8(x)                      (((uint8_t)(((uint8_t)(x)) << USBx_ERRSTAT_DFN8_SHIFT)) & USBx_ERRSTAT_DFN8_MASK)
+#define USBx_ERRSTAT_DFN8_SET(x)                  (((uint8_t)(((uint8_t)(x)) << USBx_ERRSTAT_DFN8_SHIFT)) & USBx_ERRSTAT_DFN8_MASK)
+#define USBx_ERRSTAT_DFN8 USBx_ERRSTAT_DFN8_MASK
 #define USBx_ERRSTAT_BTOERR_MASK                  (0x10U)
 #define USBx_ERRSTAT_BTOERR_SHIFT                 (4U)
-#define USBx_ERRSTAT_BTOERR(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_ERRSTAT_BTOERR_SHIFT)) & USBx_ERRSTAT_BTOERR_MASK)
+#define USBx_ERRSTAT_BTOERR_SET(x)                (((uint8_t)(((uint8_t)(x)) << USBx_ERRSTAT_BTOERR_SHIFT)) & USBx_ERRSTAT_BTOERR_MASK)
+#define USBx_ERRSTAT_BTOERR USBx_ERRSTAT_BTOERR_MASK
 #define USBx_ERRSTAT_DMAERR_MASK                  (0x20U)
 #define USBx_ERRSTAT_DMAERR_SHIFT                 (5U)
-#define USBx_ERRSTAT_DMAERR(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_ERRSTAT_DMAERR_SHIFT)) & USBx_ERRSTAT_DMAERR_MASK)
+#define USBx_ERRSTAT_DMAERR_SET(x)                (((uint8_t)(((uint8_t)(x)) << USBx_ERRSTAT_DMAERR_SHIFT)) & USBx_ERRSTAT_DMAERR_MASK)
+#define USBx_ERRSTAT_DMAERR USBx_ERRSTAT_DMAERR_MASK
 #define USBx_ERRSTAT_BTSERR_MASK                  (0x80U)
 #define USBx_ERRSTAT_BTSERR_SHIFT                 (7U)
-#define USBx_ERRSTAT_BTSERR(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_ERRSTAT_BTSERR_SHIFT)) & USBx_ERRSTAT_BTSERR_MASK)
+#define USBx_ERRSTAT_BTSERR_SET(x)                (((uint8_t)(((uint8_t)(x)) << USBx_ERRSTAT_BTSERR_SHIFT)) & USBx_ERRSTAT_BTSERR_MASK)
+#define USBx_ERRSTAT_BTSERR USBx_ERRSTAT_BTSERR_MASK
 
 /*! @name ERREN - Error Interrupt Enable register */
 #define USBx_ERREN_PIDERREN_MASK                  (0x1U)
 #define USBx_ERREN_PIDERREN_SHIFT                 (0U)
-#define USBx_ERREN_PIDERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_ERREN_PIDERREN_SHIFT)) & USBx_ERREN_PIDERREN_MASK)
+#define USBx_ERREN_PIDERREN_SET(x)                (((uint8_t)(((uint8_t)(x)) << USBx_ERREN_PIDERREN_SHIFT)) & USBx_ERREN_PIDERREN_MASK)
+#define USBx_ERREN_PIDERREN USBx_ERREN_PIDERREN_MASK
 #define USBx_ERREN_CRC5EOFEN_MASK                 (0x2U)
 #define USBx_ERREN_CRC5EOFEN_SHIFT                (1U)
-#define USBx_ERREN_CRC5EOFEN(x)                   (((uint8_t)(((uint8_t)(x)) << USBx_ERREN_CRC5EOFEN_SHIFT)) & USBx_ERREN_CRC5EOFEN_MASK)
+#define USBx_ERREN_CRC5EOFEN_SET(x)               (((uint8_t)(((uint8_t)(x)) << USBx_ERREN_CRC5EOFEN_SHIFT)) & USBx_ERREN_CRC5EOFEN_MASK)
+#define USBx_ERREN_CRC5EOFEN USBx_ERREN_CRC5EOFEN_MASK
 #define USBx_ERREN_CRC16EN_MASK                   (0x4U)
 #define USBx_ERREN_CRC16EN_SHIFT                  (2U)
-#define USBx_ERREN_CRC16EN(x)                     (((uint8_t)(((uint8_t)(x)) << USBx_ERREN_CRC16EN_SHIFT)) & USBx_ERREN_CRC16EN_MASK)
+#define USBx_ERREN_CRC16EN_SET(x)                 (((uint8_t)(((uint8_t)(x)) << USBx_ERREN_CRC16EN_SHIFT)) & USBx_ERREN_CRC16EN_MASK)
+#define USBx_ERREN_CRC16EN USBx_ERREN_CRC16EN_MASK
 #define USBx_ERREN_DFN8EN_MASK                    (0x8U)
 #define USBx_ERREN_DFN8EN_SHIFT                   (3U)
-#define USBx_ERREN_DFN8EN(x)                      (((uint8_t)(((uint8_t)(x)) << USBx_ERREN_DFN8EN_SHIFT)) & USBx_ERREN_DFN8EN_MASK)
+#define USBx_ERREN_DFN8EN_SET(x)                  (((uint8_t)(((uint8_t)(x)) << USBx_ERREN_DFN8EN_SHIFT)) & USBx_ERREN_DFN8EN_MASK)
+#define USBx_ERREN_DFN8EN USBx_ERREN_DFN8EN_MASK
 #define USBx_ERREN_BTOERREN_MASK                  (0x10U)
 #define USBx_ERREN_BTOERREN_SHIFT                 (4U)
-#define USBx_ERREN_BTOERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_ERREN_BTOERREN_SHIFT)) & USBx_ERREN_BTOERREN_MASK)
+#define USBx_ERREN_BTOERREN_SET(x)                (((uint8_t)(((uint8_t)(x)) << USBx_ERREN_BTOERREN_SHIFT)) & USBx_ERREN_BTOERREN_MASK)
+#define USBx_ERREN_BTOERREN USBx_ERREN_BTOERREN_MASK
 #define USBx_ERREN_DMAERREN_MASK                  (0x20U)
 #define USBx_ERREN_DMAERREN_SHIFT                 (5U)
-#define USBx_ERREN_DMAERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_ERREN_DMAERREN_SHIFT)) & USBx_ERREN_DMAERREN_MASK)
+#define USBx_ERREN_DMAERREN_SET(x)                (((uint8_t)(((uint8_t)(x)) << USBx_ERREN_DMAERREN_SHIFT)) & USBx_ERREN_DMAERREN_MASK)
+#define USBx_ERREN_DMAERREN USBx_ERREN_DMAERREN_MASK
 #define USBx_ERREN_BTSERREN_MASK                  (0x80U)
 #define USBx_ERREN_BTSERREN_SHIFT                 (7U)
-#define USBx_ERREN_BTSERREN(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_ERREN_BTSERREN_SHIFT)) & USBx_ERREN_BTSERREN_MASK)
+#define USBx_ERREN_BTSERREN_SET(x)                (((uint8_t)(((uint8_t)(x)) << USBx_ERREN_BTSERREN_SHIFT)) & USBx_ERREN_BTSERREN_MASK)
+#define USBx_ERREN_BTSERREN USBx_ERREN_BTSERREN_MASK
 
 /*! @name STAT - Status register */
 #define USBx_STAT_ODD_MASK                        (0x4U)
 #define USBx_STAT_ODD_SHIFT                       (2U)
-#define USBx_STAT_ODD(x)                          (((uint8_t)(((uint8_t)(x)) << USBx_STAT_ODD_SHIFT)) & USBx_STAT_ODD_MASK)
+#define USBx_STAT_ODD_SET(x)                      (((uint8_t)(((uint8_t)(x)) << USBx_STAT_ODD_SHIFT)) & USBx_STAT_ODD_MASK)
+#define USBx_STAT_ODD USBx_STAT_ODD_MASK
 #define USBx_STAT_TX_MASK                         (0x8U)
 #define USBx_STAT_TX_SHIFT                        (3U)
-#define USBx_STAT_TX(x)                           (((uint8_t)(((uint8_t)(x)) << USBx_STAT_TX_SHIFT)) & USBx_STAT_TX_MASK)
+#define USBx_STAT_TX_SET(x)                       (((uint8_t)(((uint8_t)(x)) << USBx_STAT_TX_SHIFT)) & USBx_STAT_TX_MASK)
+#define USBx_STAT_TX USBx_STAT_TX_MASK
 #define USBx_STAT_ENDP_MASK                       (0xF0U)
 #define USBx_STAT_ENDP_SHIFT                      (4U)
-#define USBx_STAT_ENDP(x)                         (((uint8_t)(((uint8_t)(x)) << USBx_STAT_ENDP_SHIFT)) & USBx_STAT_ENDP_MASK)
+#define USBx_STAT_ENDP_SET(x)                     (((uint8_t)(((uint8_t)(x)) << USBx_STAT_ENDP_SHIFT)) & USBx_STAT_ENDP_MASK)
+#define USBx_STAT_ENDP USBx_STAT_ENDP_MASK
 
 /*! @name CTL - Control register */
 #define USBx_CTL_USBENSOFEN_MASK                  (0x1U)
@@ -14482,63 +17478,76 @@ typedef struct {
 #define USBx_CTL_HOSTMODEEN                       USBx_CTL_HOSTMODEEN_SET(1) 
 #define USBx_CTL_RESET_MASK                       (0x10U)
 #define USBx_CTL_RESET_SHIFT                      (4U)
-#define USBx_CTL_RESET(x)                         (((uint8_t)(((uint8_t)(x)) << USBx_CTL_RESET_SHIFT)) & USBx_CTL_RESET_MASK)
+#define USBx_CTL_RESET_SET(x)                     (((uint8_t)(((uint8_t)(x)) << USBx_CTL_RESET_SHIFT)) & USBx_CTL_RESET_MASK)
+#define USBx_CTL_RESET USBx_CTL_RESET_MASK
 #define USBx_CTL_TXSUSPENDTOKENBUSY_MASK          (0x20U)
 #define USBx_CTL_TXSUSPENDTOKENBUSY_SHIFT         (5U)
 #define USBx_CTL_TXSUSPENDTOKENBUSY_SET(x)        (((uint8_t)(((uint8_t)(x)) << USBx_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USBx_CTL_TXSUSPENDTOKENBUSY_MASK)
 #define USBx_CTL_TXSUSPENDTOKENBUSY               USBx_CTL_TXSUSPENDTOKENBUSY_SET(1)
 #define USBx_CTL_SE0_MASK                         (0x40U)
 #define USBx_CTL_SE0_SHIFT                        (6U)
-#define USBx_CTL_SE0(x)                           (((uint8_t)(((uint8_t)(x)) << USBx_CTL_SE0_SHIFT)) & USBx_CTL_SE0_MASK)
+#define USBx_CTL_SE0_SET(x)                       (((uint8_t)(((uint8_t)(x)) << USBx_CTL_SE0_SHIFT)) & USBx_CTL_SE0_MASK)
+#define USBx_CTL_SE0 USBx_CTL_SE0_MASK
 #define USBx_CTL_JSTATE_MASK                      (0x80U)
 #define USBx_CTL_JSTATE_SHIFT                     (7U)
-#define USBx_CTL_JSTATE(x)                        (((uint8_t)(((uint8_t)(x)) << USBx_CTL_JSTATE_SHIFT)) & USBx_CTL_JSTATE_MASK)
+#define USBx_CTL_JSTATE_SET(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_CTL_JSTATE_SHIFT)) & USBx_CTL_JSTATE_MASK)
+#define USBx_CTL_JSTATE USBx_CTL_JSTATE_MASK
 
 /*! @name ADDR - Address register */
 #define USBx_ADDR_ADDR_MASK                       (0x7FU)
 #define USBx_ADDR_ADDR_SHIFT                      (0U)
-#define USBx_ADDR_ADDR(x)                         (((uint8_t)(((uint8_t)(x)) << USBx_ADDR_ADDR_SHIFT)) & USBx_ADDR_ADDR_MASK)
+#define USBx_ADDR_ADDR_SET(x)                     (((uint8_t)(((uint8_t)(x)) << USBx_ADDR_ADDR_SHIFT)) & USBx_ADDR_ADDR_MASK)
+#define USBx_ADDR_ADDR USBx_ADDR_ADDR_MASK
 #define USBx_ADDR_LSEN_MASK                       (0x80U)
 #define USBx_ADDR_LSEN_SHIFT                      (7U)
-#define USBx_ADDR_LSEN(x)                         (((uint8_t)(((uint8_t)(x)) << USBx_ADDR_LSEN_SHIFT)) & USBx_ADDR_LSEN_MASK)
+#define USBx_ADDR_LSEN_SET(x)                     (((uint8_t)(((uint8_t)(x)) << USBx_ADDR_LSEN_SHIFT)) & USBx_ADDR_LSEN_MASK)
+#define USBx_ADDR_LSEN USBx_ADDR_LSEN_MASK
 
 /*! @name BDTPAGE1 - BDT Page register 1 */
 #define USBx_BDTPAGE1_BDTBA_MASK                  (0xFEU)
 #define USBx_BDTPAGE1_BDTBA_SHIFT                 (1U)
-#define USBx_BDTPAGE1_BDTBA(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_BDTPAGE1_BDTBA_SHIFT)) & USBx_BDTPAGE1_BDTBA_MASK)
+#define USBx_BDTPAGE1_BDTBA_SET(x)                (((uint8_t)(((uint8_t)(x)) << USBx_BDTPAGE1_BDTBA_SHIFT)) & USBx_BDTPAGE1_BDTBA_MASK)
+#define USBx_BDTPAGE1_BDTBA USBx_BDTPAGE1_BDTBA_MASK
 
 /*! @name FRMNUML - Frame Number register Low */
 #define USBx_FRMNUML_FRM_MASK                     (0xFFU)
 #define USBx_FRMNUML_FRM_SHIFT                    (0U)
-#define USBx_FRMNUML_FRM(x)                       (((uint8_t)(((uint8_t)(x)) << USBx_FRMNUML_FRM_SHIFT)) & USBx_FRMNUML_FRM_MASK)
+#define USBx_FRMNUML_FRM_SET(x)                   (((uint8_t)(((uint8_t)(x)) << USBx_FRMNUML_FRM_SHIFT)) & USBx_FRMNUML_FRM_MASK)
+#define USBx_FRMNUML_FRM USBx_FRMNUML_FRM_MASK
 
 /*! @name FRMNUMH - Frame Number register High */
 #define USBx_FRMNUMH_FRM_MASK                     (0x7U)
 #define USBx_FRMNUMH_FRM_SHIFT                    (0U)
-#define USBx_FRMNUMH_FRM(x)                       (((uint8_t)(((uint8_t)(x)) << USBx_FRMNUMH_FRM_SHIFT)) & USBx_FRMNUMH_FRM_MASK)
+#define USBx_FRMNUMH_FRM_SET(x)                   (((uint8_t)(((uint8_t)(x)) << USBx_FRMNUMH_FRM_SHIFT)) & USBx_FRMNUMH_FRM_MASK)
+#define USBx_FRMNUMH_FRM USBx_FRMNUMH_FRM_MASK
 
 /*! @name TOKEN - Token register */
 #define USBx_TOKEN_TOKENENDPT_MASK                (0xFU)
 #define USBx_TOKEN_TOKENENDPT_SHIFT               (0U)
-#define USBx_TOKEN_TOKENENDPT(x)                  (((uint8_t)(((uint8_t)(x)) << USBx_TOKEN_TOKENENDPT_SHIFT)) & USBx_TOKEN_TOKENENDPT_MASK)
+#define USBx_TOKEN_TOKENENDPT_SET(x)              (((uint8_t)(((uint8_t)(x)) << USBx_TOKEN_TOKENENDPT_SHIFT)) & USBx_TOKEN_TOKENENDPT_MASK)
+#define USBx_TOKEN_TOKENENDPT USBx_TOKEN_TOKENENDPT_MASK
 #define USBx_TOKEN_TOKENPID_MASK                  (0xF0U)
 #define USBx_TOKEN_TOKENPID_SHIFT                 (4U)
-#define USBx_TOKEN_TOKENPID(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_TOKEN_TOKENPID_SHIFT)) & USBx_TOKEN_TOKENPID_MASK)
+#define USBx_TOKEN_TOKENPID_SET(x)                (((uint8_t)(((uint8_t)(x)) << USBx_TOKEN_TOKENPID_SHIFT)) & USBx_TOKEN_TOKENPID_MASK)
+#define USBx_TOKEN_TOKENPID USBx_TOKEN_TOKENPID_MASK
 
 /*! @name SOFTHLD - SOF Threshold register */
 #define USBx_SOFTHLD_CNT_MASK                     (0xFFU)
 #define USBx_SOFTHLD_CNT_SHIFT                    (0U)
-#define USBx_SOFTHLD_CNT(x)                       (((uint8_t)(((uint8_t)(x)) << USBx_SOFTHLD_CNT_SHIFT)) & USBx_SOFTHLD_CNT_MASK)
+#define USBx_SOFTHLD_CNT_SET(x)                   (((uint8_t)(((uint8_t)(x)) << USBx_SOFTHLD_CNT_SHIFT)) & USBx_SOFTHLD_CNT_MASK)
+#define USBx_SOFTHLD_CNT USBx_SOFTHLD_CNT_MASK
 
 /*! @name BDTPAGE2 - BDT Page Register 2 */
 #define USBx_BDTPAGE2_BDTBA_MASK                  (0xFFU)
 #define USBx_BDTPAGE2_BDTBA_SHIFT                 (0U)
-#define USBx_BDTPAGE2_BDTBA(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_BDTPAGE2_BDTBA_SHIFT)) & USBx_BDTPAGE2_BDTBA_MASK)
+#define USBx_BDTPAGE2_BDTBA_SET(x)                (((uint8_t)(((uint8_t)(x)) << USBx_BDTPAGE2_BDTBA_SHIFT)) & USBx_BDTPAGE2_BDTBA_MASK)
+#define USBx_BDTPAGE2_BDTBA USBx_BDTPAGE2_BDTBA_MASK
 
 /*! @name BDTPAGE3 - BDT Page Register 3 */
 #define USBx_BDTPAGE3_BDTBA_MASK                  (0xFFU)
 #define USBx_BDTPAGE3_BDTBA_SHIFT                 (0U)
-#define USBx_BDTPAGE3_BDTBA(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_BDTPAGE3_BDTBA_SHIFT)) & USBx_BDTPAGE3_BDTBA_MASK)
+#define USBx_BDTPAGE3_BDTBA_SET(x)                (((uint8_t)(((uint8_t)(x)) << USBx_BDTPAGE3_BDTBA_SHIFT)) & USBx_BDTPAGE3_BDTBA_MASK)
+#define USBx_BDTPAGE3_BDTBA USBx_BDTPAGE3_BDTBA_MASK
 
 /*! @name ENDPT - Endpoint Control register */
 #define USBx_ENDPTn_EPHSHK_MASK                    (0x1U)
@@ -14563,10 +17572,12 @@ typedef struct {
 #define USBx_ENDPTn_EPCTLDIS                       USBx_ENDPTn_EPCTLDIS_SET(1)
 #define USBx_ENDPTn_RETRYDIS_MASK                  (0x40U)
 #define USBx_ENDPTn_RETRYDIS_SHIFT                 (6U)
-#define USBx_ENDPTn_RETRYDIS(x)                    (((uint8_t)(((uint8_t)(x)) << USBx_ENDPTn_RETRYDIS_SHIFT)) & USBx_ENDPTn_RETRYDIS_MASK)
+#define USBx_ENDPTn_RETRYDIS_SET(x)                (((uint8_t)(((uint8_t)(x)) << USBx_ENDPTn_RETRYDIS_SHIFT)) & USBx_ENDPTn_RETRYDIS_MASK)
+#define USBx_ENDPTn_RETRYDIS USBx_ENDPTn_RETRYDIS_MASK
 #define USBx_ENDPTn_HOSTWOHUB_MASK                 (0x80U)
 #define USBx_ENDPTn_HOSTWOHUB_SHIFT                (7U)
-#define USBx_ENDPTn_HOSTWOHUB(x)                   (((uint8_t)(((uint8_t)(x)) << USBx_ENDPTn_HOSTWOHUB_SHIFT)) & USBx_ENDPTn_HOSTWOHUB_MASK)
+#define USBx_ENDPTn_HOSTWOHUB_SET(x)               (((uint8_t)(((uint8_t)(x)) << USBx_ENDPTn_HOSTWOHUB_SHIFT)) & USBx_ENDPTn_HOSTWOHUB_MASK)
+#define USBx_ENDPTn_HOSTWOHUB USBx_ENDPTn_HOSTWOHUB_MASK
 
 /* The count of USBx_ENDPT */
 #define USBx_ENDPTn_COUNT                          (16U)
@@ -14574,21 +17585,26 @@ typedef struct {
 /*! @name USBCTRL - USB Control register */
 #define USBx_USBCTRL_PDE_MASK                     (0x40U)
 #define USBx_USBCTRL_PDE_SHIFT                    (6U)
-#define USBx_USBCTRL_PDE(x)                       (((uint8_t)(((uint8_t)(x)) << USBx_USBCTRL_PDE_SHIFT)) & USBx_USBCTRL_PDE_MASK)
+#define USBx_USBCTRL_PDE_SET(x)                   (((uint8_t)(((uint8_t)(x)) << USBx_USBCTRL_PDE_SHIFT)) & USBx_USBCTRL_PDE_MASK)
+#define USBx_USBCTRL_PDE USBx_USBCTRL_PDE_MASK
 #define USBx_USBCTRL_SUSP_MASK                    (0x80U)
 #define USBx_USBCTRL_SUSP_SHIFT                   (7U)
-#define USBx_USBCTRL_SUSP(x)                      (((uint8_t)(((uint8_t)(x)) << USBx_USBCTRL_SUSP_SHIFT)) & USBx_USBCTRL_SUSP_MASK)
+#define USBx_USBCTRL_SUSP_SET(x)                  (((uint8_t)(((uint8_t)(x)) << USBx_USBCTRL_SUSP_SHIFT)) & USBx_USBCTRL_SUSP_MASK)
+#define USBx_USBCTRL_SUSP USBx_USBCTRL_SUSP_MASK
 
 /*! @name OBSERVE - USB OTG Observe register */
 #define USBx_OBSERVE_DMPD_MASK                    (0x10U)
 #define USBx_OBSERVE_DMPD_SHIFT                   (4U)
-#define USBx_OBSERVE_DMPD(x)                      (((uint8_t)(((uint8_t)(x)) << USBx_OBSERVE_DMPD_SHIFT)) & USBx_OBSERVE_DMPD_MASK)
+#define USBx_OBSERVE_DMPD_SET(x)                  (((uint8_t)(((uint8_t)(x)) << USBx_OBSERVE_DMPD_SHIFT)) & USBx_OBSERVE_DMPD_MASK)
+#define USBx_OBSERVE_DMPD USBx_OBSERVE_DMPD_MASK
 #define USBx_OBSERVE_DPPD_MASK                    (0x40U)
 #define USBx_OBSERVE_DPPD_SHIFT                   (6U)
-#define USBx_OBSERVE_DPPD(x)                      (((uint8_t)(((uint8_t)(x)) << USBx_OBSERVE_DPPD_SHIFT)) & USBx_OBSERVE_DPPD_MASK)
+#define USBx_OBSERVE_DPPD_SET(x)                  (((uint8_t)(((uint8_t)(x)) << USBx_OBSERVE_DPPD_SHIFT)) & USBx_OBSERVE_DPPD_MASK)
+#define USBx_OBSERVE_DPPD USBx_OBSERVE_DPPD_MASK
 #define USBx_OBSERVE_DPPU_MASK                    (0x80U)
 #define USBx_OBSERVE_DPPU_SHIFT                   (7U)
-#define USBx_OBSERVE_DPPU(x)                      (((uint8_t)(((uint8_t)(x)) << USBx_OBSERVE_DPPU_SHIFT)) & USBx_OBSERVE_DPPU_MASK)
+#define USBx_OBSERVE_DPPU_SET(x)                  (((uint8_t)(((uint8_t)(x)) << USBx_OBSERVE_DPPU_SHIFT)) & USBx_OBSERVE_DPPU_MASK)
+#define USBx_OBSERVE_DPPU USBx_OBSERVE_DPPU_MASK
 
 /*! @name CONTROL - USB OTG Control register */
 #define USBx_CONTROL_DPPULLUPNONOTG_MASK          (0x10U)
@@ -14599,16 +17615,20 @@ typedef struct {
 /*! @name USBTRC0 - USB Transceiver Control register 0 */
 #define USBx_USBTRC0_USBx_RESUME_INT_MASK          (0x1U)
 #define USBx_USBTRC0_USBx_RESUME_INT_SHIFT         (0U)
-#define USBx_USBTRC0_USBx_RESUME_INT(x)            (((uint8_t)(((uint8_t)(x)) << USBx_USBTRC0_USBx_RESUME_INT_SHIFT)) & USBx_USBTRC0_USBx_RESUME_INT_MASK)
+#define USBx_USBTRC0_USBx_RESUME_INT_SET(x)        (((uint8_t)(((uint8_t)(x)) << USBx_USBTRC0_USBx_RESUME_INT_SHIFT)) & USBx_USBTRC0_USBx_RESUME_INT_MASK)
+#define USBx_USBTRC0_USBx_RESUME_INT USBx_USBTRC0_USBx_RESUME_INT_MASK
 #define USBx_USBTRC0_SYNC_DET_MASK                (0x2U)
 #define USBx_USBTRC0_SYNC_DET_SHIFT               (1U)
-#define USBx_USBTRC0_SYNC_DET(x)                  (((uint8_t)(((uint8_t)(x)) << USBx_USBTRC0_SYNC_DET_SHIFT)) & USBx_USBTRC0_SYNC_DET_MASK)
+#define USBx_USBTRC0_SYNC_DET_SET(x)              (((uint8_t)(((uint8_t)(x)) << USBx_USBTRC0_SYNC_DET_SHIFT)) & USBx_USBTRC0_SYNC_DET_MASK)
+#define USBx_USBTRC0_SYNC_DET USBx_USBTRC0_SYNC_DET_MASK
 #define USBx_USBTRC0_USBx_CLK_RECOVERY_INT_MASK    (0x4U)
 #define USBx_USBTRC0_USBx_CLK_RECOVERY_INT_SHIFT   (2U)
-#define USBx_USBTRC0_USBx_CLK_RECOVERY_INT(x)      (((uint8_t)(((uint8_t)(x)) << USBx_USBTRC0_USBx_CLK_RECOVERY_INT_SHIFT)) & USBx_USBTRC0_USBx_CLK_RECOVERY_INT_MASK)
+#define USBx_USBTRC0_USBx_CLK_RECOVERY_INT_SET(x)  (((uint8_t)(((uint8_t)(x)) << USBx_USBTRC0_USBx_CLK_RECOVERY_INT_SHIFT)) & USBx_USBTRC0_USBx_CLK_RECOVERY_INT_MASK)
+#define USBx_USBTRC0_USBx_CLK_RECOVERY_INT USBx_USBTRC0_USBx_CLK_RECOVERY_INT_MASK
 #define USBx_USBTRC0_USBRESMEN_MASK               (0x20U)
 #define USBx_USBTRC0_USBRESMEN_SHIFT              (5U)
-#define USBx_USBTRC0_USBRESMEN(x)                 (((uint8_t)(((uint8_t)(x)) << USBx_USBTRC0_USBRESMEN_SHIFT)) & USBx_USBTRC0_USBRESMEN_MASK)
+#define USBx_USBTRC0_USBRESMEN_SET(x)             (((uint8_t)(((uint8_t)(x)) << USBx_USBTRC0_USBRESMEN_SHIFT)) & USBx_USBTRC0_USBRESMEN_MASK)
+#define USBx_USBTRC0_USBRESMEN USBx_USBTRC0_USBRESMEN_MASK
 #define USBx_USBTRC0_USBRESET_MASK                (0x80U)
 #define USBx_USBTRC0_USBRESET_SHIFT               (7U)
 #define USBx_USBTRC0_USBRESET_SET(x)              (((uint8_t)(((uint8_t)(x)) << USBx_USBTRC0_USBRESET_SHIFT)) & USBx_USBTRC0_USBRESET_MASK)
@@ -14617,7 +17637,8 @@ typedef struct {
 /*! @name USBFRMADJUST - Frame Adjust Register */
 #define USBx_USBFRMADJUST_ADJ_MASK                (0xFFU)
 #define USBx_USBFRMADJUST_ADJ_SHIFT               (0U)
-#define USBx_USBFRMADJUST_ADJ(x)                  (((uint8_t)(((uint8_t)(x)) << USBx_USBFRMADJUST_ADJ_SHIFT)) & USBx_USBFRMADJUST_ADJ_MASK)
+#define USBx_USBFRMADJUST_ADJ_SET(x)              (((uint8_t)(((uint8_t)(x)) << USBx_USBFRMADJUST_ADJ_SHIFT)) & USBx_USBFRMADJUST_ADJ_MASK)
+#define USBx_USBFRMADJUST_ADJ USBx_USBFRMADJUST_ADJ_MASK
 
 /*! @name CLK_RECOVER_CTRL - USB Clock recovery control */
 #define USBx_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U)
@@ -14661,7 +17682,7 @@ typedef struct {
 /** Peripheral USB0 base address */
 #define USB0_BASE                                (0x40072000u)
 /** Peripheral USB0 base pointer */
-#define USB0                                     ((USBx_Type *)USB0_BASE)
+#define USB0                                     ((USBx_TypeDef *)USB0_BASE)
 /** Array initializer of USB peripheral base addresses */
 #define USBx_BASE_ADDRS                           { USB0_BASE }
 /** Array initializer of USB peripheral base pointers */
@@ -14695,7 +17716,7 @@ typedef struct {
     __IO uint32_t TIMER2_BC11;                       /**< TIMER2_BC11 register, offset: 0x18 */
     __IO uint32_t TIMER2_BC12;                       /**< TIMER2_BC12 register, offset: 0x18 */
   };
-} USBDCD_Type;
+} USBDCD_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- USBDCD Register Masks
@@ -14709,84 +17730,106 @@ typedef struct {
 /*! @name CONTROL - Control register */
 #define USBDCD_CONTROL_IACK_MASK                 (0x1U)
 #define USBDCD_CONTROL_IACK_SHIFT                (0U)
-#define USBDCD_CONTROL_IACK(x)                   (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IACK_SHIFT)) & USBDCD_CONTROL_IACK_MASK)
+#define USBDCD_CONTROL_IACK_SET(x)               (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IACK_SHIFT)) & USBDCD_CONTROL_IACK_MASK)
+#define USBDCD_CONTROL_IACK USBDCD_CONTROL_IACK_MASK
 #define USBDCD_CONTROL_IF_MASK                   (0x100U)
 #define USBDCD_CONTROL_IF_SHIFT                  (8U)
-#define USBDCD_CONTROL_IF(x)                     (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IF_SHIFT)) & USBDCD_CONTROL_IF_MASK)
+#define USBDCD_CONTROL_IF_SET(x)                 (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IF_SHIFT)) & USBDCD_CONTROL_IF_MASK)
+#define USBDCD_CONTROL_IF USBDCD_CONTROL_IF_MASK
 #define USBDCD_CONTROL_IE_MASK                   (0x10000U)
 #define USBDCD_CONTROL_IE_SHIFT                  (16U)
-#define USBDCD_CONTROL_IE(x)                     (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IE_SHIFT)) & USBDCD_CONTROL_IE_MASK)
+#define USBDCD_CONTROL_IE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IE_SHIFT)) & USBDCD_CONTROL_IE_MASK)
+#define USBDCD_CONTROL_IE USBDCD_CONTROL_IE_MASK
 #define USBDCD_CONTROL_BC12_MASK                 (0x20000U)
 #define USBDCD_CONTROL_BC12_SHIFT                (17U)
-#define USBDCD_CONTROL_BC12(x)                   (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_BC12_SHIFT)) & USBDCD_CONTROL_BC12_MASK)
+#define USBDCD_CONTROL_BC12_SET(x)               (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_BC12_SHIFT)) & USBDCD_CONTROL_BC12_MASK)
+#define USBDCD_CONTROL_BC12 USBDCD_CONTROL_BC12_MASK
 #define USBDCD_CONTROL_START_MASK                (0x1000000U)
 #define USBDCD_CONTROL_START_SHIFT               (24U)
-#define USBDCD_CONTROL_START(x)                  (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_START_SHIFT)) & USBDCD_CONTROL_START_MASK)
+#define USBDCD_CONTROL_START_SET(x)              (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_START_SHIFT)) & USBDCD_CONTROL_START_MASK)
+#define USBDCD_CONTROL_START USBDCD_CONTROL_START_MASK
 #define USBDCD_CONTROL_SR_MASK                   (0x2000000U)
 #define USBDCD_CONTROL_SR_SHIFT                  (25U)
-#define USBDCD_CONTROL_SR(x)                     (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_SR_SHIFT)) & USBDCD_CONTROL_SR_MASK)
+#define USBDCD_CONTROL_SR_SET(x)                 (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_SR_SHIFT)) & USBDCD_CONTROL_SR_MASK)
+#define USBDCD_CONTROL_SR USBDCD_CONTROL_SR_MASK
 
 /*! @name CLOCK - Clock register */
 #define USBDCD_CLOCK_CLOCK_UNIT_MASK             (0x1U)
 #define USBDCD_CLOCK_CLOCK_UNIT_SHIFT            (0U)
-#define USBDCD_CLOCK_CLOCK_UNIT(x)               (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBDCD_CLOCK_CLOCK_UNIT_MASK)
+#define USBDCD_CLOCK_CLOCK_UNIT_SET(x)           (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBDCD_CLOCK_CLOCK_UNIT_MASK)
+#define USBDCD_CLOCK_CLOCK_UNIT USBDCD_CLOCK_CLOCK_UNIT_MASK
 #define USBDCD_CLOCK_CLOCK_SPEED_MASK            (0xFFCU)
 #define USBDCD_CLOCK_CLOCK_SPEED_SHIFT           (2U)
-#define USBDCD_CLOCK_CLOCK_SPEED(x)              (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBDCD_CLOCK_CLOCK_SPEED_MASK)
+#define USBDCD_CLOCK_CLOCK_SPEED_SET(x)          (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBDCD_CLOCK_CLOCK_SPEED_MASK)
+#define USBDCD_CLOCK_CLOCK_SPEED USBDCD_CLOCK_CLOCK_SPEED_MASK
 
 /*! @name STATUS - Status register */
 #define USBDCD_STATUS_SEQ_RES_MASK               (0x30000U)
 #define USBDCD_STATUS_SEQ_RES_SHIFT              (16U)
-#define USBDCD_STATUS_SEQ_RES(x)                 (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_RES_SHIFT)) & USBDCD_STATUS_SEQ_RES_MASK)
+#define USBDCD_STATUS_SEQ_RES_SET(x)             (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_RES_SHIFT)) & USBDCD_STATUS_SEQ_RES_MASK)
+#define USBDCD_STATUS_SEQ_RES USBDCD_STATUS_SEQ_RES_MASK
 #define USBDCD_STATUS_SEQ_STAT_MASK              (0xC0000U)
 #define USBDCD_STATUS_SEQ_STAT_SHIFT             (18U)
-#define USBDCD_STATUS_SEQ_STAT(x)                (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_STAT_SHIFT)) & USBDCD_STATUS_SEQ_STAT_MASK)
+#define USBDCD_STATUS_SEQ_STAT_SET(x)            (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_STAT_SHIFT)) & USBDCD_STATUS_SEQ_STAT_MASK)
+#define USBDCD_STATUS_SEQ_STAT USBDCD_STATUS_SEQ_STAT_MASK
 #define USBDCD_STATUS_ERR_MASK                   (0x100000U)
 #define USBDCD_STATUS_ERR_SHIFT                  (20U)
-#define USBDCD_STATUS_ERR(x)                     (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ERR_SHIFT)) & USBDCD_STATUS_ERR_MASK)
+#define USBDCD_STATUS_ERR_SET(x)                 (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ERR_SHIFT)) & USBDCD_STATUS_ERR_MASK)
+#define USBDCD_STATUS_ERR USBDCD_STATUS_ERR_MASK
 #define USBDCD_STATUS_TO_MASK                    (0x200000U)
 #define USBDCD_STATUS_TO_SHIFT                   (21U)
-#define USBDCD_STATUS_TO(x)                      (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_TO_SHIFT)) & USBDCD_STATUS_TO_MASK)
+#define USBDCD_STATUS_TO_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_TO_SHIFT)) & USBDCD_STATUS_TO_MASK)
+#define USBDCD_STATUS_TO USBDCD_STATUS_TO_MASK
 #define USBDCD_STATUS_ACTIVE_MASK                (0x400000U)
 #define USBDCD_STATUS_ACTIVE_SHIFT               (22U)
-#define USBDCD_STATUS_ACTIVE(x)                  (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ACTIVE_SHIFT)) & USBDCD_STATUS_ACTIVE_MASK)
+#define USBDCD_STATUS_ACTIVE_SET(x)              (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ACTIVE_SHIFT)) & USBDCD_STATUS_ACTIVE_MASK)
+#define USBDCD_STATUS_ACTIVE USBDCD_STATUS_ACTIVE_MASK
 
 /*! @name SIGNAL_OVERRIDE - Signal Override Register */
 #define USBDCD_SIGNAL_OVERRIDE_PS_MASK           (0x3U)
 #define USBDCD_SIGNAL_OVERRIDE_PS_SHIFT          (0U)
-#define USBDCD_SIGNAL_OVERRIDE_PS(x)             (((uint32_t)(((uint32_t)(x)) << USBDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBDCD_SIGNAL_OVERRIDE_PS_MASK)
+#define USBDCD_SIGNAL_OVERRIDE_PS_SET(x)         (((uint32_t)(((uint32_t)(x)) << USBDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBDCD_SIGNAL_OVERRIDE_PS_MASK)
+#define USBDCD_SIGNAL_OVERRIDE_PS USBDCD_SIGNAL_OVERRIDE_PS_MASK
 
 /*! @name TIMER0 - TIMER0 register */
 #define USBDCD_TIMER0_TUNITCON_MASK              (0xFFFU)
 #define USBDCD_TIMER0_TUNITCON_SHIFT             (0U)
-#define USBDCD_TIMER0_TUNITCON(x)                (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TUNITCON_SHIFT)) & USBDCD_TIMER0_TUNITCON_MASK)
+#define USBDCD_TIMER0_TUNITCON_SET(x)            (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TUNITCON_SHIFT)) & USBDCD_TIMER0_TUNITCON_MASK)
+#define USBDCD_TIMER0_TUNITCON USBDCD_TIMER0_TUNITCON_MASK
 #define USBDCD_TIMER0_TSEQ_INIT_MASK             (0x3FF0000U)
 #define USBDCD_TIMER0_TSEQ_INIT_SHIFT            (16U)
-#define USBDCD_TIMER0_TSEQ_INIT(x)               (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBDCD_TIMER0_TSEQ_INIT_MASK)
+#define USBDCD_TIMER0_TSEQ_INIT_SET(x)           (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBDCD_TIMER0_TSEQ_INIT_MASK)
+#define USBDCD_TIMER0_TSEQ_INIT USBDCD_TIMER0_TSEQ_INIT_MASK
 
 /*! @name TIMER1 - TIMER1 register */
 #define USBDCD_TIMER1_TVDPSRC_ON_MASK            (0x3FFU)
 #define USBDCD_TIMER1_TVDPSRC_ON_SHIFT           (0U)
-#define USBDCD_TIMER1_TVDPSRC_ON(x)              (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBDCD_TIMER1_TVDPSRC_ON_MASK)
+#define USBDCD_TIMER1_TVDPSRC_ON_SET(x)          (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBDCD_TIMER1_TVDPSRC_ON_MASK)
+#define USBDCD_TIMER1_TVDPSRC_ON USBDCD_TIMER1_TVDPSRC_ON_MASK
 #define USBDCD_TIMER1_TDCD_DBNC_MASK             (0x3FF0000U)
 #define USBDCD_TIMER1_TDCD_DBNC_SHIFT            (16U)
-#define USBDCD_TIMER1_TDCD_DBNC(x)               (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBDCD_TIMER1_TDCD_DBNC_MASK)
+#define USBDCD_TIMER1_TDCD_DBNC_SET(x)           (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBDCD_TIMER1_TDCD_DBNC_MASK)
+#define USBDCD_TIMER1_TDCD_DBNC USBDCD_TIMER1_TDCD_DBNC_MASK
 
 /*! @name TIMER2_BC11 - TIMER2_BC11 register */
 #define USBDCD_TIMER2_BC11_CHECK_DM_MASK         (0xFU)
 #define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT        (0U)
-#define USBDCD_TIMER2_BC11_CHECK_DM(x)           (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBDCD_TIMER2_BC11_CHECK_DM_MASK)
+#define USBDCD_TIMER2_BC11_CHECK_DM_SET(x)       (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBDCD_TIMER2_BC11_CHECK_DM_MASK)
+#define USBDCD_TIMER2_BC11_CHECK_DM USBDCD_TIMER2_BC11_CHECK_DM_MASK
 #define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK      (0x3FF0000U)
 #define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT     (16U)
-#define USBDCD_TIMER2_BC11_TVDPSRC_CON(x)        (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON_SET(x)    (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
+#define USBDCD_TIMER2_BC11_TVDPSRC_CON USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK
 
 /*! @name TIMER2_BC12 - TIMER2_BC12 register */
 #define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK       (0x3FFU)
 #define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT      (0U)
-#define USBDCD_TIMER2_BC12_TVDMSRC_ON(x)         (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON_SET(x)     (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
+#define USBDCD_TIMER2_BC12_TVDMSRC_ON USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK
 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK  (0x3FF0000U)
 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
-#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x)    (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SET(x)(((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
+#define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK
 
 
 /*!
@@ -14798,7 +17841,7 @@ typedef struct {
 /** Peripheral USBDCD base address */
 #define USBDCD_BASE                              (0x40035000u)
 /** Peripheral USBDCD base pointer */
-#define USBDCD                                   ((USBDCD_Type *)USBDCD_BASE)
+#define USBDCD                                   ((USBDCD_TypeDef *)USBDCD_BASE)
 /** Array initializer of USBDCD peripheral base addresses */
 #define USBDCD_BASE_ADDRS                        { USBDCD_BASE }
 /** Array initializer of USBDCD peripheral base pointers */
@@ -14875,7 +17918,7 @@ typedef struct {
   __IO uint32_t EPCR[7];                           /**< Endpoint Control Register n, array offset: 0x1C4, array step: 0x4 */
        uint8_t RESERVED_7[32];
   __IO uint32_t USBGENCTRL;                        /**< USB General Control Register, offset: 0x200 */
-} USBHS_Type;
+} USBHS_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- USBHS Register Masks
@@ -14889,665 +17932,860 @@ typedef struct {
 /*! @name ID - Identification Register */
 #define USBHS_ID_ID_MASK                         (0x3FU)
 #define USBHS_ID_ID_SHIFT                        (0U)
-#define USBHS_ID_ID(x)                           (((uint32_t)(((uint32_t)(x)) << USBHS_ID_ID_SHIFT)) & USBHS_ID_ID_MASK)
+#define USBHS_ID_ID_SET(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_ID_ID_SHIFT)) & USBHS_ID_ID_MASK)
+#define USBHS_ID_ID USBHS_ID_ID_MASK
 #define USBHS_ID_NID_MASK                        (0x3F00U)
 #define USBHS_ID_NID_SHIFT                       (8U)
-#define USBHS_ID_NID(x)                          (((uint32_t)(((uint32_t)(x)) << USBHS_ID_NID_SHIFT)) & USBHS_ID_NID_MASK)
+#define USBHS_ID_NID_SET(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_ID_NID_SHIFT)) & USBHS_ID_NID_MASK)
+#define USBHS_ID_NID USBHS_ID_NID_MASK
 #define USBHS_ID_TAG_MASK                        (0x1F0000U)
 #define USBHS_ID_TAG_SHIFT                       (16U)
-#define USBHS_ID_TAG(x)                          (((uint32_t)(((uint32_t)(x)) << USBHS_ID_TAG_SHIFT)) & USBHS_ID_TAG_MASK)
+#define USBHS_ID_TAG_SET(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_ID_TAG_SHIFT)) & USBHS_ID_TAG_MASK)
+#define USBHS_ID_TAG USBHS_ID_TAG_MASK
 #define USBHS_ID_REVISION_MASK                   (0x1E00000U)
 #define USBHS_ID_REVISION_SHIFT                  (21U)
-#define USBHS_ID_REVISION(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_ID_REVISION_SHIFT)) & USBHS_ID_REVISION_MASK)
+#define USBHS_ID_REVISION_SET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_ID_REVISION_SHIFT)) & USBHS_ID_REVISION_MASK)
+#define USBHS_ID_REVISION USBHS_ID_REVISION_MASK
 #define USBHS_ID_VERSION_MASK                    (0x1E000000U)
 #define USBHS_ID_VERSION_SHIFT                   (25U)
-#define USBHS_ID_VERSION(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_ID_VERSION_SHIFT)) & USBHS_ID_VERSION_MASK)
+#define USBHS_ID_VERSION_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_ID_VERSION_SHIFT)) & USBHS_ID_VERSION_MASK)
+#define USBHS_ID_VERSION USBHS_ID_VERSION_MASK
 #define USBHS_ID_VERSIONID_MASK                  (0xE0000000U)
 #define USBHS_ID_VERSIONID_SHIFT                 (29U)
-#define USBHS_ID_VERSIONID(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_ID_VERSIONID_SHIFT)) & USBHS_ID_VERSIONID_MASK)
+#define USBHS_ID_VERSIONID_SET(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_ID_VERSIONID_SHIFT)) & USBHS_ID_VERSIONID_MASK)
+#define USBHS_ID_VERSIONID USBHS_ID_VERSIONID_MASK
 
 /*! @name HWGENERAL - General Hardware Parameters Register */
 #define USBHS_HWGENERAL_PHYW_MASK                (0x30U)
 #define USBHS_HWGENERAL_PHYW_SHIFT               (4U)
-#define USBHS_HWGENERAL_PHYW(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_PHYW_SHIFT)) & USBHS_HWGENERAL_PHYW_MASK)
+#define USBHS_HWGENERAL_PHYW_SET(x)              (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_PHYW_SHIFT)) & USBHS_HWGENERAL_PHYW_MASK)
+#define USBHS_HWGENERAL_PHYW USBHS_HWGENERAL_PHYW_MASK
 #define USBHS_HWGENERAL_PHYM_MASK                (0x1C0U)
 #define USBHS_HWGENERAL_PHYM_SHIFT               (6U)
-#define USBHS_HWGENERAL_PHYM(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_PHYM_SHIFT)) & USBHS_HWGENERAL_PHYM_MASK)
+#define USBHS_HWGENERAL_PHYM_SET(x)              (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_PHYM_SHIFT)) & USBHS_HWGENERAL_PHYM_MASK)
+#define USBHS_HWGENERAL_PHYM USBHS_HWGENERAL_PHYM_MASK
 #define USBHS_HWGENERAL_SM_MASK                  (0x600U)
 #define USBHS_HWGENERAL_SM_SHIFT                 (9U)
-#define USBHS_HWGENERAL_SM(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_SM_SHIFT)) & USBHS_HWGENERAL_SM_MASK)
+#define USBHS_HWGENERAL_SM_SET(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_HWGENERAL_SM_SHIFT)) & USBHS_HWGENERAL_SM_MASK)
+#define USBHS_HWGENERAL_SM USBHS_HWGENERAL_SM_MASK
 
 /*! @name HWHOST - Host Hardware Parameters Register */
 #define USBHS_HWHOST_HC_MASK                     (0x1U)
 #define USBHS_HWHOST_HC_SHIFT                    (0U)
-#define USBHS_HWHOST_HC(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_HC_SHIFT)) & USBHS_HWHOST_HC_MASK)
+#define USBHS_HWHOST_HC_SET(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_HC_SHIFT)) & USBHS_HWHOST_HC_MASK)
+#define USBHS_HWHOST_HC USBHS_HWHOST_HC_MASK
 #define USBHS_HWHOST_NPORT_MASK                  (0xEU)
 #define USBHS_HWHOST_NPORT_SHIFT                 (1U)
-#define USBHS_HWHOST_NPORT(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_NPORT_SHIFT)) & USBHS_HWHOST_NPORT_MASK)
+#define USBHS_HWHOST_NPORT_SET(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_NPORT_SHIFT)) & USBHS_HWHOST_NPORT_MASK)
+#define USBHS_HWHOST_NPORT USBHS_HWHOST_NPORT_MASK
 #define USBHS_HWHOST_TTASY_MASK                  (0xFF0000U)
 #define USBHS_HWHOST_TTASY_SHIFT                 (16U)
-#define USBHS_HWHOST_TTASY(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_TTASY_SHIFT)) & USBHS_HWHOST_TTASY_MASK)
+#define USBHS_HWHOST_TTASY_SET(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_TTASY_SHIFT)) & USBHS_HWHOST_TTASY_MASK)
+#define USBHS_HWHOST_TTASY USBHS_HWHOST_TTASY_MASK
 #define USBHS_HWHOST_TTPER_MASK                  (0xFF000000U)
 #define USBHS_HWHOST_TTPER_SHIFT                 (24U)
-#define USBHS_HWHOST_TTPER(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_TTPER_SHIFT)) & USBHS_HWHOST_TTPER_MASK)
+#define USBHS_HWHOST_TTPER_SET(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_HWHOST_TTPER_SHIFT)) & USBHS_HWHOST_TTPER_MASK)
+#define USBHS_HWHOST_TTPER USBHS_HWHOST_TTPER_MASK
 
 /*! @name HWDEVICE - Device Hardware Parameters Register */
 #define USBHS_HWDEVICE_DC_MASK                   (0x1U)
 #define USBHS_HWDEVICE_DC_SHIFT                  (0U)
-#define USBHS_HWDEVICE_DC(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_HWDEVICE_DC_SHIFT)) & USBHS_HWDEVICE_DC_MASK)
+#define USBHS_HWDEVICE_DC_SET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_HWDEVICE_DC_SHIFT)) & USBHS_HWDEVICE_DC_MASK)
+#define USBHS_HWDEVICE_DC USBHS_HWDEVICE_DC_MASK
 #define USBHS_HWDEVICE_DEVEP_MASK                (0x3EU)
 #define USBHS_HWDEVICE_DEVEP_SHIFT               (1U)
-#define USBHS_HWDEVICE_DEVEP(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_HWDEVICE_DEVEP_SHIFT)) & USBHS_HWDEVICE_DEVEP_MASK)
+#define USBHS_HWDEVICE_DEVEP_SET(x)              (((uint32_t)(((uint32_t)(x)) << USBHS_HWDEVICE_DEVEP_SHIFT)) & USBHS_HWDEVICE_DEVEP_MASK)
+#define USBHS_HWDEVICE_DEVEP USBHS_HWDEVICE_DEVEP_MASK
 
 /*! @name HWTXBUF - Transmit Buffer Hardware Parameters Register */
 #define USBHS_HWTXBUF_TXBURST_MASK               (0xFFU)
 #define USBHS_HWTXBUF_TXBURST_SHIFT              (0U)
-#define USBHS_HWTXBUF_TXBURST(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXBURST_SHIFT)) & USBHS_HWTXBUF_TXBURST_MASK)
+#define USBHS_HWTXBUF_TXBURST_SET(x)             (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXBURST_SHIFT)) & USBHS_HWTXBUF_TXBURST_MASK)
+#define USBHS_HWTXBUF_TXBURST USBHS_HWTXBUF_TXBURST_MASK
 #define USBHS_HWTXBUF_TXADD_MASK                 (0xFF00U)
 #define USBHS_HWTXBUF_TXADD_SHIFT                (8U)
-#define USBHS_HWTXBUF_TXADD(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXADD_SHIFT)) & USBHS_HWTXBUF_TXADD_MASK)
+#define USBHS_HWTXBUF_TXADD_SET(x)               (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXADD_SHIFT)) & USBHS_HWTXBUF_TXADD_MASK)
+#define USBHS_HWTXBUF_TXADD USBHS_HWTXBUF_TXADD_MASK
 #define USBHS_HWTXBUF_TXCHANADD_MASK             (0xFF0000U)
 #define USBHS_HWTXBUF_TXCHANADD_SHIFT            (16U)
-#define USBHS_HWTXBUF_TXCHANADD(x)               (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXCHANADD_SHIFT)) & USBHS_HWTXBUF_TXCHANADD_MASK)
+#define USBHS_HWTXBUF_TXCHANADD_SET(x)           (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXCHANADD_SHIFT)) & USBHS_HWTXBUF_TXCHANADD_MASK)
+#define USBHS_HWTXBUF_TXCHANADD USBHS_HWTXBUF_TXCHANADD_MASK
 #define USBHS_HWTXBUF_TXLC_MASK                  (0x80000000U)
 #define USBHS_HWTXBUF_TXLC_SHIFT                 (31U)
-#define USBHS_HWTXBUF_TXLC(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXLC_SHIFT)) & USBHS_HWTXBUF_TXLC_MASK)
+#define USBHS_HWTXBUF_TXLC_SET(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_HWTXBUF_TXLC_SHIFT)) & USBHS_HWTXBUF_TXLC_MASK)
+#define USBHS_HWTXBUF_TXLC USBHS_HWTXBUF_TXLC_MASK
 
 /*! @name HWRXBUF - Receive Buffer Hardware Parameters Register */
 #define USBHS_HWRXBUF_RXBURST_MASK               (0xFFU)
 #define USBHS_HWRXBUF_RXBURST_SHIFT              (0U)
-#define USBHS_HWRXBUF_RXBURST(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_HWRXBUF_RXBURST_SHIFT)) & USBHS_HWRXBUF_RXBURST_MASK)
+#define USBHS_HWRXBUF_RXBURST_SET(x)             (((uint32_t)(((uint32_t)(x)) << USBHS_HWRXBUF_RXBURST_SHIFT)) & USBHS_HWRXBUF_RXBURST_MASK)
+#define USBHS_HWRXBUF_RXBURST USBHS_HWRXBUF_RXBURST_MASK
 #define USBHS_HWRXBUF_RXADD_MASK                 (0xFF00U)
 #define USBHS_HWRXBUF_RXADD_SHIFT                (8U)
-#define USBHS_HWRXBUF_RXADD(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_HWRXBUF_RXADD_SHIFT)) & USBHS_HWRXBUF_RXADD_MASK)
+#define USBHS_HWRXBUF_RXADD_SET(x)               (((uint32_t)(((uint32_t)(x)) << USBHS_HWRXBUF_RXADD_SHIFT)) & USBHS_HWRXBUF_RXADD_MASK)
+#define USBHS_HWRXBUF_RXADD USBHS_HWRXBUF_RXADD_MASK
 
 /*! @name GPTIMER0LD - General Purpose Timer n Load Register */
 #define USBHS_GPTIMER0LD_GPTLD_MASK              (0xFFFFFFU)
 #define USBHS_GPTIMER0LD_GPTLD_SHIFT             (0U)
-#define USBHS_GPTIMER0LD_GPTLD(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0LD_GPTLD_SHIFT)) & USBHS_GPTIMER0LD_GPTLD_MASK)
+#define USBHS_GPTIMER0LD_GPTLD_SET(x)            (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0LD_GPTLD_SHIFT)) & USBHS_GPTIMER0LD_GPTLD_MASK)
+#define USBHS_GPTIMER0LD_GPTLD USBHS_GPTIMER0LD_GPTLD_MASK
 
 /*! @name GPTIMER0CTL - General Purpose Timer n Control Register */
 #define USBHS_GPTIMER0CTL_GPTCNT_MASK            (0xFFFFFFU)
 #define USBHS_GPTIMER0CTL_GPTCNT_SHIFT           (0U)
-#define USBHS_GPTIMER0CTL_GPTCNT(x)              (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_GPTCNT_SHIFT)) & USBHS_GPTIMER0CTL_GPTCNT_MASK)
+#define USBHS_GPTIMER0CTL_GPTCNT_SET(x)          (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_GPTCNT_SHIFT)) & USBHS_GPTIMER0CTL_GPTCNT_MASK)
+#define USBHS_GPTIMER0CTL_GPTCNT USBHS_GPTIMER0CTL_GPTCNT_MASK
 #define USBHS_GPTIMER0CTL_MODE_MASK              (0x1000000U)
 #define USBHS_GPTIMER0CTL_MODE_SHIFT             (24U)
-#define USBHS_GPTIMER0CTL_MODE(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_MODE_SHIFT)) & USBHS_GPTIMER0CTL_MODE_MASK)
+#define USBHS_GPTIMER0CTL_MODE_SET(x)            (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_MODE_SHIFT)) & USBHS_GPTIMER0CTL_MODE_MASK)
+#define USBHS_GPTIMER0CTL_MODE USBHS_GPTIMER0CTL_MODE_MASK
 #define USBHS_GPTIMER0CTL_RST_MASK               (0x40000000U)
 #define USBHS_GPTIMER0CTL_RST_SHIFT              (30U)
-#define USBHS_GPTIMER0CTL_RST(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_RST_SHIFT)) & USBHS_GPTIMER0CTL_RST_MASK)
+#define USBHS_GPTIMER0CTL_RST_SET(x)             (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_RST_SHIFT)) & USBHS_GPTIMER0CTL_RST_MASK)
+#define USBHS_GPTIMER0CTL_RST USBHS_GPTIMER0CTL_RST_MASK
 #define USBHS_GPTIMER0CTL_RUN_MASK               (0x80000000U)
 #define USBHS_GPTIMER0CTL_RUN_SHIFT              (31U)
-#define USBHS_GPTIMER0CTL_RUN(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_RUN_SHIFT)) & USBHS_GPTIMER0CTL_RUN_MASK)
+#define USBHS_GPTIMER0CTL_RUN_SET(x)             (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER0CTL_RUN_SHIFT)) & USBHS_GPTIMER0CTL_RUN_MASK)
+#define USBHS_GPTIMER0CTL_RUN USBHS_GPTIMER0CTL_RUN_MASK
 
 /*! @name GPTIMER1LD - General Purpose Timer n Load Register */
 #define USBHS_GPTIMER1LD_GPTLD_MASK              (0xFFFFFFU)
 #define USBHS_GPTIMER1LD_GPTLD_SHIFT             (0U)
-#define USBHS_GPTIMER1LD_GPTLD(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1LD_GPTLD_SHIFT)) & USBHS_GPTIMER1LD_GPTLD_MASK)
+#define USBHS_GPTIMER1LD_GPTLD_SET(x)            (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1LD_GPTLD_SHIFT)) & USBHS_GPTIMER1LD_GPTLD_MASK)
+#define USBHS_GPTIMER1LD_GPTLD USBHS_GPTIMER1LD_GPTLD_MASK
 
 /*! @name GPTIMER1CTL - General Purpose Timer n Control Register */
 #define USBHS_GPTIMER1CTL_GPTCNT_MASK            (0xFFFFFFU)
 #define USBHS_GPTIMER1CTL_GPTCNT_SHIFT           (0U)
-#define USBHS_GPTIMER1CTL_GPTCNT(x)              (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_GPTCNT_SHIFT)) & USBHS_GPTIMER1CTL_GPTCNT_MASK)
+#define USBHS_GPTIMER1CTL_GPTCNT_SET(x)          (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_GPTCNT_SHIFT)) & USBHS_GPTIMER1CTL_GPTCNT_MASK)
+#define USBHS_GPTIMER1CTL_GPTCNT USBHS_GPTIMER1CTL_GPTCNT_MASK
 #define USBHS_GPTIMER1CTL_MODE_MASK              (0x1000000U)
 #define USBHS_GPTIMER1CTL_MODE_SHIFT             (24U)
-#define USBHS_GPTIMER1CTL_MODE(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_MODE_SHIFT)) & USBHS_GPTIMER1CTL_MODE_MASK)
+#define USBHS_GPTIMER1CTL_MODE_SET(x)            (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_MODE_SHIFT)) & USBHS_GPTIMER1CTL_MODE_MASK)
+#define USBHS_GPTIMER1CTL_MODE USBHS_GPTIMER1CTL_MODE_MASK
 #define USBHS_GPTIMER1CTL_RST_MASK               (0x40000000U)
 #define USBHS_GPTIMER1CTL_RST_SHIFT              (30U)
-#define USBHS_GPTIMER1CTL_RST(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_RST_SHIFT)) & USBHS_GPTIMER1CTL_RST_MASK)
+#define USBHS_GPTIMER1CTL_RST_SET(x)             (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_RST_SHIFT)) & USBHS_GPTIMER1CTL_RST_MASK)
+#define USBHS_GPTIMER1CTL_RST USBHS_GPTIMER1CTL_RST_MASK
 #define USBHS_GPTIMER1CTL_RUN_MASK               (0x80000000U)
 #define USBHS_GPTIMER1CTL_RUN_SHIFT              (31U)
-#define USBHS_GPTIMER1CTL_RUN(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_RUN_SHIFT)) & USBHS_GPTIMER1CTL_RUN_MASK)
+#define USBHS_GPTIMER1CTL_RUN_SET(x)             (((uint32_t)(((uint32_t)(x)) << USBHS_GPTIMER1CTL_RUN_SHIFT)) & USBHS_GPTIMER1CTL_RUN_MASK)
+#define USBHS_GPTIMER1CTL_RUN USBHS_GPTIMER1CTL_RUN_MASK
 
 /*! @name USBx_SBUSCFG - System Bus Interface Configuration Register */
 #define USBHS_USBx_SBUSCFG_BURSTMODE_MASK         (0x7U)
 #define USBHS_USBx_SBUSCFG_BURSTMODE_SHIFT        (0U)
-#define USBHS_USBx_SBUSCFG_BURSTMODE(x)           (((uint32_t)(((uint32_t)(x)) << USBHS_USBx_SBUSCFG_BURSTMODE_SHIFT)) & USBHS_USBx_SBUSCFG_BURSTMODE_MASK)
+#define USBHS_USBx_SBUSCFG_BURSTMODE_SET(x)       (((uint32_t)(((uint32_t)(x)) << USBHS_USBx_SBUSCFG_BURSTMODE_SHIFT)) & USBHS_USBx_SBUSCFG_BURSTMODE_MASK)
+#define USBHS_USBx_SBUSCFG_BURSTMODE USBHS_USBx_SBUSCFG_BURSTMODE_MASK
 
 /*! @name HCIVERSION - Host Controller Interface Version and Capability Registers Length Register */
 #define USBHS_HCIVERSION_CAPLENGTH_MASK          (0xFFU)
 #define USBHS_HCIVERSION_CAPLENGTH_SHIFT         (0U)
-#define USBHS_HCIVERSION_CAPLENGTH(x)            (((uint32_t)(((uint32_t)(x)) << USBHS_HCIVERSION_CAPLENGTH_SHIFT)) & USBHS_HCIVERSION_CAPLENGTH_MASK)
+#define USBHS_HCIVERSION_CAPLENGTH_SET(x)        (((uint32_t)(((uint32_t)(x)) << USBHS_HCIVERSION_CAPLENGTH_SHIFT)) & USBHS_HCIVERSION_CAPLENGTH_MASK)
+#define USBHS_HCIVERSION_CAPLENGTH USBHS_HCIVERSION_CAPLENGTH_MASK
 #define USBHS_HCIVERSION_HCIVERSION_MASK         (0xFFFF0000U)
 #define USBHS_HCIVERSION_HCIVERSION_SHIFT        (16U)
-#define USBHS_HCIVERSION_HCIVERSION(x)           (((uint32_t)(((uint32_t)(x)) << USBHS_HCIVERSION_HCIVERSION_SHIFT)) & USBHS_HCIVERSION_HCIVERSION_MASK)
+#define USBHS_HCIVERSION_HCIVERSION_SET(x)       (((uint32_t)(((uint32_t)(x)) << USBHS_HCIVERSION_HCIVERSION_SHIFT)) & USBHS_HCIVERSION_HCIVERSION_MASK)
+#define USBHS_HCIVERSION_HCIVERSION USBHS_HCIVERSION_HCIVERSION_MASK
 
 /*! @name HCSPARAMS - Host Controller Structural Parameters Register */
 #define USBHS_HCSPARAMS_N_PORTS_MASK             (0xFU)
 #define USBHS_HCSPARAMS_N_PORTS_SHIFT            (0U)
-#define USBHS_HCSPARAMS_N_PORTS(x)               (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PORTS_SHIFT)) & USBHS_HCSPARAMS_N_PORTS_MASK)
+#define USBHS_HCSPARAMS_N_PORTS_SET(x)           (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PORTS_SHIFT)) & USBHS_HCSPARAMS_N_PORTS_MASK)
+#define USBHS_HCSPARAMS_N_PORTS USBHS_HCSPARAMS_N_PORTS_MASK
 #define USBHS_HCSPARAMS_PPC_MASK                 (0x10U)
 #define USBHS_HCSPARAMS_PPC_SHIFT                (4U)
-#define USBHS_HCSPARAMS_PPC(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PPC_SHIFT)) & USBHS_HCSPARAMS_PPC_MASK)
+#define USBHS_HCSPARAMS_PPC_SET(x)               (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PPC_SHIFT)) & USBHS_HCSPARAMS_PPC_MASK)
+#define USBHS_HCSPARAMS_PPC USBHS_HCSPARAMS_PPC_MASK
 #define USBHS_HCSPARAMS_N_PCC_MASK               (0xF00U)
 #define USBHS_HCSPARAMS_N_PCC_SHIFT              (8U)
-#define USBHS_HCSPARAMS_N_PCC(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PCC_SHIFT)) & USBHS_HCSPARAMS_N_PCC_MASK)
+#define USBHS_HCSPARAMS_N_PCC_SET(x)             (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PCC_SHIFT)) & USBHS_HCSPARAMS_N_PCC_MASK)
+#define USBHS_HCSPARAMS_N_PCC USBHS_HCSPARAMS_N_PCC_MASK
 #define USBHS_HCSPARAMS_N_CC_MASK                (0xF000U)
 #define USBHS_HCSPARAMS_N_CC_SHIFT               (12U)
-#define USBHS_HCSPARAMS_N_CC(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_CC_SHIFT)) & USBHS_HCSPARAMS_N_CC_MASK)
+#define USBHS_HCSPARAMS_N_CC_SET(x)              (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_CC_SHIFT)) & USBHS_HCSPARAMS_N_CC_MASK)
+#define USBHS_HCSPARAMS_N_CC USBHS_HCSPARAMS_N_CC_MASK
 #define USBHS_HCSPARAMS_PI_MASK                  (0x10000U)
 #define USBHS_HCSPARAMS_PI_SHIFT                 (16U)
-#define USBHS_HCSPARAMS_PI(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PI_SHIFT)) & USBHS_HCSPARAMS_PI_MASK)
+#define USBHS_HCSPARAMS_PI_SET(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_PI_SHIFT)) & USBHS_HCSPARAMS_PI_MASK)
+#define USBHS_HCSPARAMS_PI USBHS_HCSPARAMS_PI_MASK
 #define USBHS_HCSPARAMS_N_PTT_MASK               (0xF00000U)
 #define USBHS_HCSPARAMS_N_PTT_SHIFT              (20U)
-#define USBHS_HCSPARAMS_N_PTT(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PTT_SHIFT)) & USBHS_HCSPARAMS_N_PTT_MASK)
+#define USBHS_HCSPARAMS_N_PTT_SET(x)             (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_PTT_SHIFT)) & USBHS_HCSPARAMS_N_PTT_MASK)
+#define USBHS_HCSPARAMS_N_PTT USBHS_HCSPARAMS_N_PTT_MASK
 #define USBHS_HCSPARAMS_N_TT_MASK                (0xF000000U)
 #define USBHS_HCSPARAMS_N_TT_SHIFT               (24U)
-#define USBHS_HCSPARAMS_N_TT(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_TT_SHIFT)) & USBHS_HCSPARAMS_N_TT_MASK)
+#define USBHS_HCSPARAMS_N_TT_SET(x)              (((uint32_t)(((uint32_t)(x)) << USBHS_HCSPARAMS_N_TT_SHIFT)) & USBHS_HCSPARAMS_N_TT_MASK)
+#define USBHS_HCSPARAMS_N_TT USBHS_HCSPARAMS_N_TT_MASK
 
 /*! @name HCCPARAMS - Host Controller Capability Parameters Register */
-#define USBHS_HCCPARAMS_ADC_MASK                 (0x1U)
-#define USBHS_HCCPARAMS_ADC_SHIFT                (0U)
-#define USBHS_HCCPARAMS_ADC(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_ADC_SHIFT)) & USBHS_HCCPARAMS_ADC_MASK)
+#define USBHS_HCCPARAMS_ADCx_MASK                 (0x1U)
+#define USBHS_HCCPARAMS_ADCx_SHIFT                (0U)
+#define USBHS_HCCPARAMS_ADCx_SET(x)               (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_ADCx_SHIFT)) & USBHS_HCCPARAMS_ADCx_MASK)
+#define USBHS_HCCPARAMS_ADC USBHS_HCCPARAMS_ADCx_MASK
 #define USBHS_HCCPARAMS_PFL_MASK                 (0x2U)
 #define USBHS_HCCPARAMS_PFL_SHIFT                (1U)
-#define USBHS_HCCPARAMS_PFL(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_PFL_SHIFT)) & USBHS_HCCPARAMS_PFL_MASK)
+#define USBHS_HCCPARAMS_PFL_SET(x)               (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_PFL_SHIFT)) & USBHS_HCCPARAMS_PFL_MASK)
+#define USBHS_HCCPARAMS_PFL USBHS_HCCPARAMS_PFL_MASK
 #define USBHS_HCCPARAMS_ASP_MASK                 (0x4U)
 #define USBHS_HCCPARAMS_ASP_SHIFT                (2U)
-#define USBHS_HCCPARAMS_ASP(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_ASP_SHIFT)) & USBHS_HCCPARAMS_ASP_MASK)
+#define USBHS_HCCPARAMS_ASP_SET(x)               (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_ASP_SHIFT)) & USBHS_HCCPARAMS_ASP_MASK)
+#define USBHS_HCCPARAMS_ASP USBHS_HCCPARAMS_ASP_MASK
 #define USBHS_HCCPARAMS_IST_MASK                 (0xF0U)
 #define USBHS_HCCPARAMS_IST_SHIFT                (4U)
-#define USBHS_HCCPARAMS_IST(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_IST_SHIFT)) & USBHS_HCCPARAMS_IST_MASK)
+#define USBHS_HCCPARAMS_IST_SET(x)               (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_IST_SHIFT)) & USBHS_HCCPARAMS_IST_MASK)
+#define USBHS_HCCPARAMS_IST USBHS_HCCPARAMS_IST_MASK
 #define USBHS_HCCPARAMS_EECP_MASK                (0xFF00U)
 #define USBHS_HCCPARAMS_EECP_SHIFT               (8U)
-#define USBHS_HCCPARAMS_EECP(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_EECP_SHIFT)) & USBHS_HCCPARAMS_EECP_MASK)
+#define USBHS_HCCPARAMS_EECP_SET(x)              (((uint32_t)(((uint32_t)(x)) << USBHS_HCCPARAMS_EECP_SHIFT)) & USBHS_HCCPARAMS_EECP_MASK)
+#define USBHS_HCCPARAMS_EECP USBHS_HCCPARAMS_EECP_MASK
 
 /*! @name DCIVERSION - Device Controller Interface Version */
 #define USBHS_DCIVERSION_DCIVERSION_MASK         (0xFFFFU)
 #define USBHS_DCIVERSION_DCIVERSION_SHIFT        (0U)
-#define USBHS_DCIVERSION_DCIVERSION(x)           (((uint16_t)(((uint16_t)(x)) << USBHS_DCIVERSION_DCIVERSION_SHIFT)) & USBHS_DCIVERSION_DCIVERSION_MASK)
+#define USBHS_DCIVERSION_DCIVERSION_SET(x)       (((uint16_t)(((uint16_t)(x)) << USBHS_DCIVERSION_DCIVERSION_SHIFT)) & USBHS_DCIVERSION_DCIVERSION_MASK)
+#define USBHS_DCIVERSION_DCIVERSION USBHS_DCIVERSION_DCIVERSION_MASK
 
 /*! @name DCCPARAMS - Device Controller Capability Parameters */
 #define USBHS_DCCPARAMS_DEN_MASK                 (0x1FU)
 #define USBHS_DCCPARAMS_DEN_SHIFT                (0U)
-#define USBHS_DCCPARAMS_DEN(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_DEN_SHIFT)) & USBHS_DCCPARAMS_DEN_MASK)
+#define USBHS_DCCPARAMS_DEN_SET(x)               (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_DEN_SHIFT)) & USBHS_DCCPARAMS_DEN_MASK)
+#define USBHS_DCCPARAMS_DEN USBHS_DCCPARAMS_DEN_MASK
 #define USBHS_DCCPARAMS_DC_MASK                  (0x80U)
 #define USBHS_DCCPARAMS_DC_SHIFT                 (7U)
-#define USBHS_DCCPARAMS_DC(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_DC_SHIFT)) & USBHS_DCCPARAMS_DC_MASK)
+#define USBHS_DCCPARAMS_DC_SET(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_DC_SHIFT)) & USBHS_DCCPARAMS_DC_MASK)
+#define USBHS_DCCPARAMS_DC USBHS_DCCPARAMS_DC_MASK
 #define USBHS_DCCPARAMS_HC_MASK                  (0x100U)
 #define USBHS_DCCPARAMS_HC_SHIFT                 (8U)
-#define USBHS_DCCPARAMS_HC(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_HC_SHIFT)) & USBHS_DCCPARAMS_HC_MASK)
+#define USBHS_DCCPARAMS_HC_SET(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_DCCPARAMS_HC_SHIFT)) & USBHS_DCCPARAMS_HC_MASK)
+#define USBHS_DCCPARAMS_HC USBHS_DCCPARAMS_HC_MASK
 
 /*! @name USBCMD - USB Command Register */
 #define USBHS_USBCMD_RS_MASK                     (0x1U)
 #define USBHS_USBCMD_RS_SHIFT                    (0U)
-#define USBHS_USBCMD_RS(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_RS_SHIFT)) & USBHS_USBCMD_RS_MASK)
+#define USBHS_USBCMD_RS_SET(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_RS_SHIFT)) & USBHS_USBCMD_RS_MASK)
+#define USBHS_USBCMD_RS USBHS_USBCMD_RS_MASK
 #define USBHS_USBCMD_RST_MASK                    (0x2U)
 #define USBHS_USBCMD_RST_SHIFT                   (1U)
-#define USBHS_USBCMD_RST(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_RST_SHIFT)) & USBHS_USBCMD_RST_MASK)
+#define USBHS_USBCMD_RST_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_RST_SHIFT)) & USBHS_USBCMD_RST_MASK)
+#define USBHS_USBCMD_RST USBHS_USBCMD_RST_MASK
 #define USBHS_USBCMD_FS_MASK                     (0xCU)
 #define USBHS_USBCMD_FS_SHIFT                    (2U)
-#define USBHS_USBCMD_FS(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_FS_SHIFT)) & USBHS_USBCMD_FS_MASK)
+#define USBHS_USBCMD_FS_SET(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_FS_SHIFT)) & USBHS_USBCMD_FS_MASK)
+#define USBHS_USBCMD_FS USBHS_USBCMD_FS_MASK
 #define USBHS_USBCMD_PSE_MASK                    (0x10U)
 #define USBHS_USBCMD_PSE_SHIFT                   (4U)
-#define USBHS_USBCMD_PSE(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_PSE_SHIFT)) & USBHS_USBCMD_PSE_MASK)
+#define USBHS_USBCMD_PSE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_PSE_SHIFT)) & USBHS_USBCMD_PSE_MASK)
+#define USBHS_USBCMD_PSE USBHS_USBCMD_PSE_MASK
 #define USBHS_USBCMD_ASE_MASK                    (0x20U)
 #define USBHS_USBCMD_ASE_SHIFT                   (5U)
-#define USBHS_USBCMD_ASE(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASE_SHIFT)) & USBHS_USBCMD_ASE_MASK)
+#define USBHS_USBCMD_ASE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASE_SHIFT)) & USBHS_USBCMD_ASE_MASK)
+#define USBHS_USBCMD_ASE USBHS_USBCMD_ASE_MASK
 #define USBHS_USBCMD_IAA_MASK                    (0x40U)
 #define USBHS_USBCMD_IAA_SHIFT                   (6U)
-#define USBHS_USBCMD_IAA(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_IAA_SHIFT)) & USBHS_USBCMD_IAA_MASK)
+#define USBHS_USBCMD_IAA_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_IAA_SHIFT)) & USBHS_USBCMD_IAA_MASK)
+#define USBHS_USBCMD_IAA USBHS_USBCMD_IAA_MASK
 #define USBHS_USBCMD_ASP_MASK                    (0x300U)
 #define USBHS_USBCMD_ASP_SHIFT                   (8U)
-#define USBHS_USBCMD_ASP(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASP_SHIFT)) & USBHS_USBCMD_ASP_MASK)
+#define USBHS_USBCMD_ASP_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASP_SHIFT)) & USBHS_USBCMD_ASP_MASK)
+#define USBHS_USBCMD_ASP USBHS_USBCMD_ASP_MASK
 #define USBHS_USBCMD_ASPE_MASK                   (0x800U)
 #define USBHS_USBCMD_ASPE_SHIFT                  (11U)
-#define USBHS_USBCMD_ASPE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASPE_SHIFT)) & USBHS_USBCMD_ASPE_MASK)
+#define USBHS_USBCMD_ASPE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ASPE_SHIFT)) & USBHS_USBCMD_ASPE_MASK)
+#define USBHS_USBCMD_ASPE USBHS_USBCMD_ASPE_MASK
 #define USBHS_USBCMD_SUTW_MASK                   (0x2000U)
 #define USBHS_USBCMD_SUTW_SHIFT                  (13U)
-#define USBHS_USBCMD_SUTW(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_SUTW_SHIFT)) & USBHS_USBCMD_SUTW_MASK)
+#define USBHS_USBCMD_SUTW_SET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_SUTW_SHIFT)) & USBHS_USBCMD_SUTW_MASK)
+#define USBHS_USBCMD_SUTW USBHS_USBCMD_SUTW_MASK
 #define USBHS_USBCMD_ATDTW_MASK                  (0x4000U)
 #define USBHS_USBCMD_ATDTW_SHIFT                 (14U)
-#define USBHS_USBCMD_ATDTW(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ATDTW_SHIFT)) & USBHS_USBCMD_ATDTW_MASK)
+#define USBHS_USBCMD_ATDTW_SET(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ATDTW_SHIFT)) & USBHS_USBCMD_ATDTW_MASK)
+#define USBHS_USBCMD_ATDTW USBHS_USBCMD_ATDTW_MASK
 #define USBHS_USBCMD_FS2_MASK                    (0x8000U)
 #define USBHS_USBCMD_FS2_SHIFT                   (15U)
-#define USBHS_USBCMD_FS2(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_FS2_SHIFT)) & USBHS_USBCMD_FS2_MASK)
+#define USBHS_USBCMD_FS2_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_FS2_SHIFT)) & USBHS_USBCMD_FS2_MASK)
+#define USBHS_USBCMD_FS2 USBHS_USBCMD_FS2_MASK
 #define USBHS_USBCMD_ITC_MASK                    (0xFF0000U)
 #define USBHS_USBCMD_ITC_SHIFT                   (16U)
-#define USBHS_USBCMD_ITC(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ITC_SHIFT)) & USBHS_USBCMD_ITC_MASK)
+#define USBHS_USBCMD_ITC_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_USBCMD_ITC_SHIFT)) & USBHS_USBCMD_ITC_MASK)
+#define USBHS_USBCMD_ITC USBHS_USBCMD_ITC_MASK
 
 /*! @name USBSTS - USB Status Register */
 #define USBHS_USBSTS_UI_MASK                     (0x1U)
 #define USBHS_USBSTS_UI_SHIFT                    (0U)
-#define USBHS_USBSTS_UI(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UI_SHIFT)) & USBHS_USBSTS_UI_MASK)
+#define USBHS_USBSTS_UI_SET(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UI_SHIFT)) & USBHS_USBSTS_UI_MASK)
+#define USBHS_USBSTS_UI USBHS_USBSTS_UI_MASK
 #define USBHS_USBSTS_UEI_MASK                    (0x2U)
 #define USBHS_USBSTS_UEI_SHIFT                   (1U)
-#define USBHS_USBSTS_UEI(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UEI_SHIFT)) & USBHS_USBSTS_UEI_MASK)
+#define USBHS_USBSTS_UEI_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UEI_SHIFT)) & USBHS_USBSTS_UEI_MASK)
+#define USBHS_USBSTS_UEI USBHS_USBSTS_UEI_MASK
 #define USBHS_USBSTS_PCI_MASK                    (0x4U)
 #define USBHS_USBSTS_PCI_SHIFT                   (2U)
-#define USBHS_USBSTS_PCI(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_PCI_SHIFT)) & USBHS_USBSTS_PCI_MASK)
+#define USBHS_USBSTS_PCI_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_PCI_SHIFT)) & USBHS_USBSTS_PCI_MASK)
+#define USBHS_USBSTS_PCI USBHS_USBSTS_PCI_MASK
 #define USBHS_USBSTS_FRI_MASK                    (0x8U)
 #define USBHS_USBSTS_FRI_SHIFT                   (3U)
-#define USBHS_USBSTS_FRI(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_FRI_SHIFT)) & USBHS_USBSTS_FRI_MASK)
+#define USBHS_USBSTS_FRI_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_FRI_SHIFT)) & USBHS_USBSTS_FRI_MASK)
+#define USBHS_USBSTS_FRI USBHS_USBSTS_FRI_MASK
 #define USBHS_USBSTS_SEI_MASK                    (0x10U)
 #define USBHS_USBSTS_SEI_SHIFT                   (4U)
-#define USBHS_USBSTS_SEI(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SEI_SHIFT)) & USBHS_USBSTS_SEI_MASK)
+#define USBHS_USBSTS_SEI_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SEI_SHIFT)) & USBHS_USBSTS_SEI_MASK)
+#define USBHS_USBSTS_SEI USBHS_USBSTS_SEI_MASK
 #define USBHS_USBSTS_AAI_MASK                    (0x20U)
 #define USBHS_USBSTS_AAI_SHIFT                   (5U)
-#define USBHS_USBSTS_AAI(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AAI_SHIFT)) & USBHS_USBSTS_AAI_MASK)
+#define USBHS_USBSTS_AAI_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AAI_SHIFT)) & USBHS_USBSTS_AAI_MASK)
+#define USBHS_USBSTS_AAI USBHS_USBSTS_AAI_MASK
 #define USBHS_USBSTS_URI_MASK                    (0x40U)
 #define USBHS_USBSTS_URI_SHIFT                   (6U)
-#define USBHS_USBSTS_URI(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_URI_SHIFT)) & USBHS_USBSTS_URI_MASK)
+#define USBHS_USBSTS_URI_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_URI_SHIFT)) & USBHS_USBSTS_URI_MASK)
+#define USBHS_USBSTS_URI USBHS_USBSTS_URI_MASK
 #define USBHS_USBSTS_SRI_MASK                    (0x80U)
 #define USBHS_USBSTS_SRI_SHIFT                   (7U)
-#define USBHS_USBSTS_SRI(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SRI_SHIFT)) & USBHS_USBSTS_SRI_MASK)
+#define USBHS_USBSTS_SRI_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SRI_SHIFT)) & USBHS_USBSTS_SRI_MASK)
+#define USBHS_USBSTS_SRI USBHS_USBSTS_SRI_MASK
 #define USBHS_USBSTS_SLI_MASK                    (0x100U)
 #define USBHS_USBSTS_SLI_SHIFT                   (8U)
-#define USBHS_USBSTS_SLI(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SLI_SHIFT)) & USBHS_USBSTS_SLI_MASK)
+#define USBHS_USBSTS_SLI_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_SLI_SHIFT)) & USBHS_USBSTS_SLI_MASK)
+#define USBHS_USBSTS_SLI USBHS_USBSTS_SLI_MASK
 #define USBHS_USBSTS_HCH_MASK                    (0x1000U)
 #define USBHS_USBSTS_HCH_SHIFT                   (12U)
-#define USBHS_USBSTS_HCH(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_HCH_SHIFT)) & USBHS_USBSTS_HCH_MASK)
+#define USBHS_USBSTS_HCH_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_HCH_SHIFT)) & USBHS_USBSTS_HCH_MASK)
+#define USBHS_USBSTS_HCH USBHS_USBSTS_HCH_MASK
 #define USBHS_USBSTS_RCL_MASK                    (0x2000U)
 #define USBHS_USBSTS_RCL_SHIFT                   (13U)
-#define USBHS_USBSTS_RCL(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_RCL_SHIFT)) & USBHS_USBSTS_RCL_MASK)
+#define USBHS_USBSTS_RCL_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_RCL_SHIFT)) & USBHS_USBSTS_RCL_MASK)
+#define USBHS_USBSTS_RCL USBHS_USBSTS_RCL_MASK
 #define USBHS_USBSTS_PS_MASK                     (0x4000U)
 #define USBHS_USBSTS_PS_SHIFT                    (14U)
-#define USBHS_USBSTS_PS(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_PS_SHIFT)) & USBHS_USBSTS_PS_MASK)
+#define USBHS_USBSTS_PS_SET(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_PS_SHIFT)) & USBHS_USBSTS_PS_MASK)
+#define USBHS_USBSTS_PS USBHS_USBSTS_PS_MASK
 #define USBHS_USBSTS_AS_MASK                     (0x8000U)
 #define USBHS_USBSTS_AS_SHIFT                    (15U)
-#define USBHS_USBSTS_AS(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AS_SHIFT)) & USBHS_USBSTS_AS_MASK)
+#define USBHS_USBSTS_AS_SET(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_AS_SHIFT)) & USBHS_USBSTS_AS_MASK)
+#define USBHS_USBSTS_AS USBHS_USBSTS_AS_MASK
 #define USBHS_USBSTS_NAKI_MASK                   (0x10000U)
 #define USBHS_USBSTS_NAKI_SHIFT                  (16U)
-#define USBHS_USBSTS_NAKI(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_NAKI_SHIFT)) & USBHS_USBSTS_NAKI_MASK)
+#define USBHS_USBSTS_NAKI_SET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_NAKI_SHIFT)) & USBHS_USBSTS_NAKI_MASK)
+#define USBHS_USBSTS_NAKI USBHS_USBSTS_NAKI_MASK
 #define USBHS_USBSTS_UAI_MASK                    (0x40000U)
 #define USBHS_USBSTS_UAI_SHIFT                   (18U)
-#define USBHS_USBSTS_UAI(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UAI_SHIFT)) & USBHS_USBSTS_UAI_MASK)
+#define USBHS_USBSTS_UAI_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UAI_SHIFT)) & USBHS_USBSTS_UAI_MASK)
+#define USBHS_USBSTS_UAI USBHS_USBSTS_UAI_MASK
 #define USBHS_USBSTS_UPI_MASK                    (0x80000U)
 #define USBHS_USBSTS_UPI_SHIFT                   (19U)
-#define USBHS_USBSTS_UPI(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UPI_SHIFT)) & USBHS_USBSTS_UPI_MASK)
+#define USBHS_USBSTS_UPI_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_UPI_SHIFT)) & USBHS_USBSTS_UPI_MASK)
+#define USBHS_USBSTS_UPI USBHS_USBSTS_UPI_MASK
 #define USBHS_USBSTS_TI0_MASK                    (0x1000000U)
 #define USBHS_USBSTS_TI0_SHIFT                   (24U)
-#define USBHS_USBSTS_TI0(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI0_SHIFT)) & USBHS_USBSTS_TI0_MASK)
+#define USBHS_USBSTS_TI0_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI0_SHIFT)) & USBHS_USBSTS_TI0_MASK)
+#define USBHS_USBSTS_TI0 USBHS_USBSTS_TI0_MASK
 #define USBHS_USBSTS_TI1_MASK                    (0x2000000U)
 #define USBHS_USBSTS_TI1_SHIFT                   (25U)
-#define USBHS_USBSTS_TI1(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI1_SHIFT)) & USBHS_USBSTS_TI1_MASK)
+#define USBHS_USBSTS_TI1_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_USBSTS_TI1_SHIFT)) & USBHS_USBSTS_TI1_MASK)
+#define USBHS_USBSTS_TI1 USBHS_USBSTS_TI1_MASK
 
 /*! @name USBINTR - USB Interrupt Enable Register */
 #define USBHS_USBINTR_UE_MASK                    (0x1U)
 #define USBHS_USBINTR_UE_SHIFT                   (0U)
-#define USBHS_USBINTR_UE(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UE_SHIFT)) & USBHS_USBINTR_UE_MASK)
+#define USBHS_USBINTR_UE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UE_SHIFT)) & USBHS_USBINTR_UE_MASK)
+#define USBHS_USBINTR_UE USBHS_USBINTR_UE_MASK
 #define USBHS_USBINTR_UEE_MASK                   (0x2U)
 #define USBHS_USBINTR_UEE_SHIFT                  (1U)
-#define USBHS_USBINTR_UEE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UEE_SHIFT)) & USBHS_USBINTR_UEE_MASK)
+#define USBHS_USBINTR_UEE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UEE_SHIFT)) & USBHS_USBINTR_UEE_MASK)
+#define USBHS_USBINTR_UEE USBHS_USBINTR_UEE_MASK
 #define USBHS_USBINTR_PCE_MASK                   (0x4U)
 #define USBHS_USBINTR_PCE_SHIFT                  (2U)
-#define USBHS_USBINTR_PCE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_PCE_SHIFT)) & USBHS_USBINTR_PCE_MASK)
+#define USBHS_USBINTR_PCE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_PCE_SHIFT)) & USBHS_USBINTR_PCE_MASK)
+#define USBHS_USBINTR_PCE USBHS_USBINTR_PCE_MASK
 #define USBHS_USBINTR_FRE_MASK                   (0x8U)
 #define USBHS_USBINTR_FRE_SHIFT                  (3U)
-#define USBHS_USBINTR_FRE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_FRE_SHIFT)) & USBHS_USBINTR_FRE_MASK)
+#define USBHS_USBINTR_FRE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_FRE_SHIFT)) & USBHS_USBINTR_FRE_MASK)
+#define USBHS_USBINTR_FRE USBHS_USBINTR_FRE_MASK
 #define USBHS_USBINTR_SEE_MASK                   (0x10U)
 #define USBHS_USBINTR_SEE_SHIFT                  (4U)
-#define USBHS_USBINTR_SEE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SEE_SHIFT)) & USBHS_USBINTR_SEE_MASK)
+#define USBHS_USBINTR_SEE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SEE_SHIFT)) & USBHS_USBINTR_SEE_MASK)
+#define USBHS_USBINTR_SEE USBHS_USBINTR_SEE_MASK
 #define USBHS_USBINTR_AAE_MASK                   (0x20U)
 #define USBHS_USBINTR_AAE_SHIFT                  (5U)
-#define USBHS_USBINTR_AAE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_AAE_SHIFT)) & USBHS_USBINTR_AAE_MASK)
+#define USBHS_USBINTR_AAE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_AAE_SHIFT)) & USBHS_USBINTR_AAE_MASK)
+#define USBHS_USBINTR_AAE USBHS_USBINTR_AAE_MASK
 #define USBHS_USBINTR_URE_MASK                   (0x40U)
 #define USBHS_USBINTR_URE_SHIFT                  (6U)
-#define USBHS_USBINTR_URE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_URE_SHIFT)) & USBHS_USBINTR_URE_MASK)
+#define USBHS_USBINTR_URE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_URE_SHIFT)) & USBHS_USBINTR_URE_MASK)
+#define USBHS_USBINTR_URE USBHS_USBINTR_URE_MASK
 #define USBHS_USBINTR_SRE_MASK                   (0x80U)
 #define USBHS_USBINTR_SRE_SHIFT                  (7U)
-#define USBHS_USBINTR_SRE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SRE_SHIFT)) & USBHS_USBINTR_SRE_MASK)
+#define USBHS_USBINTR_SRE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SRE_SHIFT)) & USBHS_USBINTR_SRE_MASK)
+#define USBHS_USBINTR_SRE USBHS_USBINTR_SRE_MASK
 #define USBHS_USBINTR_SLE_MASK                   (0x100U)
 #define USBHS_USBINTR_SLE_SHIFT                  (8U)
-#define USBHS_USBINTR_SLE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SLE_SHIFT)) & USBHS_USBINTR_SLE_MASK)
+#define USBHS_USBINTR_SLE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_SLE_SHIFT)) & USBHS_USBINTR_SLE_MASK)
+#define USBHS_USBINTR_SLE USBHS_USBINTR_SLE_MASK
 #define USBHS_USBINTR_NAKE_MASK                  (0x10000U)
 #define USBHS_USBINTR_NAKE_SHIFT                 (16U)
-#define USBHS_USBINTR_NAKE(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_NAKE_SHIFT)) & USBHS_USBINTR_NAKE_MASK)
+#define USBHS_USBINTR_NAKE_SET(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_NAKE_SHIFT)) & USBHS_USBINTR_NAKE_MASK)
+#define USBHS_USBINTR_NAKE USBHS_USBINTR_NAKE_MASK
 #define USBHS_USBINTR_UAIE_MASK                  (0x40000U)
 #define USBHS_USBINTR_UAIE_SHIFT                 (18U)
-#define USBHS_USBINTR_UAIE(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UAIE_SHIFT)) & USBHS_USBINTR_UAIE_MASK)
+#define USBHS_USBINTR_UAIE_SET(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UAIE_SHIFT)) & USBHS_USBINTR_UAIE_MASK)
+#define USBHS_USBINTR_UAIE USBHS_USBINTR_UAIE_MASK
 #define USBHS_USBINTR_UPIE_MASK                  (0x80000U)
 #define USBHS_USBINTR_UPIE_SHIFT                 (19U)
-#define USBHS_USBINTR_UPIE(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UPIE_SHIFT)) & USBHS_USBINTR_UPIE_MASK)
+#define USBHS_USBINTR_UPIE_SET(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_UPIE_SHIFT)) & USBHS_USBINTR_UPIE_MASK)
+#define USBHS_USBINTR_UPIE USBHS_USBINTR_UPIE_MASK
 #define USBHS_USBINTR_TIE0_MASK                  (0x1000000U)
 #define USBHS_USBINTR_TIE0_SHIFT                 (24U)
-#define USBHS_USBINTR_TIE0(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE0_SHIFT)) & USBHS_USBINTR_TIE0_MASK)
+#define USBHS_USBINTR_TIE0_SET(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE0_SHIFT)) & USBHS_USBINTR_TIE0_MASK)
+#define USBHS_USBINTR_TIE0 USBHS_USBINTR_TIE0_MASK
 #define USBHS_USBINTR_TIE1_MASK                  (0x2000000U)
 #define USBHS_USBINTR_TIE1_SHIFT                 (25U)
-#define USBHS_USBINTR_TIE1(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE1_SHIFT)) & USBHS_USBINTR_TIE1_MASK)
+#define USBHS_USBINTR_TIE1_SET(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_USBINTR_TIE1_SHIFT)) & USBHS_USBINTR_TIE1_MASK)
+#define USBHS_USBINTR_TIE1 USBHS_USBINTR_TIE1_MASK
 
 /*! @name FRINDEX - Frame Index Register */
 #define USBHS_FRINDEX_FRINDEX_MASK               (0x3FFFU)
 #define USBHS_FRINDEX_FRINDEX_SHIFT              (0U)
-#define USBHS_FRINDEX_FRINDEX(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_FRINDEX_FRINDEX_SHIFT)) & USBHS_FRINDEX_FRINDEX_MASK)
+#define USBHS_FRINDEX_FRINDEX_SET(x)             (((uint32_t)(((uint32_t)(x)) << USBHS_FRINDEX_FRINDEX_SHIFT)) & USBHS_FRINDEX_FRINDEX_MASK)
+#define USBHS_FRINDEX_FRINDEX USBHS_FRINDEX_FRINDEX_MASK
 #define USBHS_FRINDEX_Reerved_MASK               (0xFFFFC000U)
 #define USBHS_FRINDEX_Reerved_SHIFT              (14U)
-#define USBHS_FRINDEX_Reerved(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_FRINDEX_Reerved_SHIFT)) & USBHS_FRINDEX_Reerved_MASK)
+#define USBHS_FRINDEX_Reerved_SET(x)             (((uint32_t)(((uint32_t)(x)) << USBHS_FRINDEX_Reerved_SHIFT)) & USBHS_FRINDEX_Reerved_MASK)
+#define USBHS_FRINDEX_Reerved USBHS_FRINDEX_Reerved_MASK
 
 /*! @name DEVICEADDR - Device Address Register */
 #define USBHS_DEVICEADDR_USBADRA_MASK            (0x1000000U)
 #define USBHS_DEVICEADDR_USBADRA_SHIFT           (24U)
-#define USBHS_DEVICEADDR_USBADRA(x)              (((uint32_t)(((uint32_t)(x)) << USBHS_DEVICEADDR_USBADRA_SHIFT)) & USBHS_DEVICEADDR_USBADRA_MASK)
+#define USBHS_DEVICEADDR_USBADRA_SET(x)          (((uint32_t)(((uint32_t)(x)) << USBHS_DEVICEADDR_USBADRA_SHIFT)) & USBHS_DEVICEADDR_USBADRA_MASK)
+#define USBHS_DEVICEADDR_USBADRA USBHS_DEVICEADDR_USBADRA_MASK
 #define USBHS_DEVICEADDR_USBADR_MASK             (0xFE000000U)
 #define USBHS_DEVICEADDR_USBADR_SHIFT            (25U)
-#define USBHS_DEVICEADDR_USBADR(x)               (((uint32_t)(((uint32_t)(x)) << USBHS_DEVICEADDR_USBADR_SHIFT)) & USBHS_DEVICEADDR_USBADR_MASK)
+#define USBHS_DEVICEADDR_USBADR_SET(x)           (((uint32_t)(((uint32_t)(x)) << USBHS_DEVICEADDR_USBADR_SHIFT)) & USBHS_DEVICEADDR_USBADR_MASK)
+#define USBHS_DEVICEADDR_USBADR USBHS_DEVICEADDR_USBADR_MASK
 
 /*! @name PERIODICLISTBASE - Periodic Frame List Base Address Register */
 #define USBHS_PERIODICLISTBASE_PERBASE_MASK      (0xFFFFF000U)
 #define USBHS_PERIODICLISTBASE_PERBASE_SHIFT     (12U)
-#define USBHS_PERIODICLISTBASE_PERBASE(x)        (((uint32_t)(((uint32_t)(x)) << USBHS_PERIODICLISTBASE_PERBASE_SHIFT)) & USBHS_PERIODICLISTBASE_PERBASE_MASK)
+#define USBHS_PERIODICLISTBASE_PERBASE_SET(x)    (((uint32_t)(((uint32_t)(x)) << USBHS_PERIODICLISTBASE_PERBASE_SHIFT)) & USBHS_PERIODICLISTBASE_PERBASE_MASK)
+#define USBHS_PERIODICLISTBASE_PERBASE USBHS_PERIODICLISTBASE_PERBASE_MASK
 
 /*! @name ASYNCLISTADDR - Current Asynchronous List Address Register */
 #define USBHS_ASYNCLISTADDR_ASYBASE_MASK         (0xFFFFFFE0U)
 #define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT        (5U)
-#define USBHS_ASYNCLISTADDR_ASYBASE(x)           (((uint32_t)(((uint32_t)(x)) << USBHS_ASYNCLISTADDR_ASYBASE_SHIFT)) & USBHS_ASYNCLISTADDR_ASYBASE_MASK)
+#define USBHS_ASYNCLISTADDR_ASYBASE_SET(x)       (((uint32_t)(((uint32_t)(x)) << USBHS_ASYNCLISTADDR_ASYBASE_SHIFT)) & USBHS_ASYNCLISTADDR_ASYBASE_MASK)
+#define USBHS_ASYNCLISTADDR_ASYBASE USBHS_ASYNCLISTADDR_ASYBASE_MASK
 
 /*! @name EPLISTADDR - Endpoint List Address Register */
 #define USBHS_EPLISTADDR_EPBASE_MASK             (0xFFFFF800U)
 #define USBHS_EPLISTADDR_EPBASE_SHIFT            (11U)
-#define USBHS_EPLISTADDR_EPBASE(x)               (((uint32_t)(((uint32_t)(x)) << USBHS_EPLISTADDR_EPBASE_SHIFT)) & USBHS_EPLISTADDR_EPBASE_MASK)
+#define USBHS_EPLISTADDR_EPBASE_SET(x)           (((uint32_t)(((uint32_t)(x)) << USBHS_EPLISTADDR_EPBASE_SHIFT)) & USBHS_EPLISTADDR_EPBASE_MASK)
+#define USBHS_EPLISTADDR_EPBASE USBHS_EPLISTADDR_EPBASE_MASK
 
 /*! @name TTCTRL - Host TT Asynchronous Buffer Control */
 #define USBHS_TTCTRL_TTHA_MASK                   (0x7F000000U)
 #define USBHS_TTCTRL_TTHA_SHIFT                  (24U)
-#define USBHS_TTCTRL_TTHA(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_TTCTRL_TTHA_SHIFT)) & USBHS_TTCTRL_TTHA_MASK)
+#define USBHS_TTCTRL_TTHA_SET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_TTCTRL_TTHA_SHIFT)) & USBHS_TTCTRL_TTHA_MASK)
+#define USBHS_TTCTRL_TTHA USBHS_TTCTRL_TTHA_MASK
 #define USBHS_TTCTRL_Reerved_MASK                (0x80000000U)
 #define USBHS_TTCTRL_Reerved_SHIFT               (31U)
-#define USBHS_TTCTRL_Reerved(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_TTCTRL_Reerved_SHIFT)) & USBHS_TTCTRL_Reerved_MASK)
+#define USBHS_TTCTRL_Reerved_SET(x)              (((uint32_t)(((uint32_t)(x)) << USBHS_TTCTRL_Reerved_SHIFT)) & USBHS_TTCTRL_Reerved_MASK)
+#define USBHS_TTCTRL_Reerved USBHS_TTCTRL_Reerved_MASK
 
 /*! @name BURSTSIZE - Master Interface Data Burst Size Register */
 #define USBHS_BURSTSIZE_RXPBURST_MASK            (0xFFU)
 #define USBHS_BURSTSIZE_RXPBURST_SHIFT           (0U)
-#define USBHS_BURSTSIZE_RXPBURST(x)              (((uint32_t)(((uint32_t)(x)) << USBHS_BURSTSIZE_RXPBURST_SHIFT)) & USBHS_BURSTSIZE_RXPBURST_MASK)
+#define USBHS_BURSTSIZE_RXPBURST_SET(x)          (((uint32_t)(((uint32_t)(x)) << USBHS_BURSTSIZE_RXPBURST_SHIFT)) & USBHS_BURSTSIZE_RXPBURST_MASK)
+#define USBHS_BURSTSIZE_RXPBURST USBHS_BURSTSIZE_RXPBURST_MASK
 #define USBHS_BURSTSIZE_TXPBURST_MASK            (0xFF00U)
 #define USBHS_BURSTSIZE_TXPBURST_SHIFT           (8U)
-#define USBHS_BURSTSIZE_TXPBURST(x)              (((uint32_t)(((uint32_t)(x)) << USBHS_BURSTSIZE_TXPBURST_SHIFT)) & USBHS_BURSTSIZE_TXPBURST_MASK)
+#define USBHS_BURSTSIZE_TXPBURST_SET(x)          (((uint32_t)(((uint32_t)(x)) << USBHS_BURSTSIZE_TXPBURST_SHIFT)) & USBHS_BURSTSIZE_TXPBURST_MASK)
+#define USBHS_BURSTSIZE_TXPBURST USBHS_BURSTSIZE_TXPBURST_MASK
 
 /*! @name TXFILLTUNING - Transmit FIFO Tuning Control Register */
 #define USBHS_TXFILLTUNING_TXSCHOH_MASK          (0x7FU)
 #define USBHS_TXFILLTUNING_TXSCHOH_SHIFT         (0U)
-#define USBHS_TXFILLTUNING_TXSCHOH(x)            (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXSCHOH_SHIFT)) & USBHS_TXFILLTUNING_TXSCHOH_MASK)
+#define USBHS_TXFILLTUNING_TXSCHOH_SET(x)        (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXSCHOH_SHIFT)) & USBHS_TXFILLTUNING_TXSCHOH_MASK)
+#define USBHS_TXFILLTUNING_TXSCHOH USBHS_TXFILLTUNING_TXSCHOH_MASK
 #define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK      (0x1F00U)
 #define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT     (8U)
-#define USBHS_TXFILLTUNING_TXSCHHEALTH(x)        (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USBHS_TXFILLTUNING_TXSCHHEALTH_MASK)
+#define USBHS_TXFILLTUNING_TXSCHHEALTH_SET(x)    (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USBHS_TXFILLTUNING_TXSCHHEALTH_MASK)
+#define USBHS_TXFILLTUNING_TXSCHHEALTH USBHS_TXFILLTUNING_TXSCHHEALTH_MASK
 #define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK      (0x3F0000U)
 #define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT     (16U)
-#define USBHS_TXFILLTUNING_TXFIFOTHRES(x)        (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USBHS_TXFILLTUNING_TXFIFOTHRES_MASK)
+#define USBHS_TXFILLTUNING_TXFIFOTHRES_SET(x)    (((uint32_t)(((uint32_t)(x)) << USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USBHS_TXFILLTUNING_TXFIFOTHRES_MASK)
+#define USBHS_TXFILLTUNING_TXFIFOTHRES USBHS_TXFILLTUNING_TXFIFOTHRES_MASK
 
 /*! @name ENDPTNAK - Endpoint NAK Register */
 #define USBHS_ENDPTNAK_EPRN_MASK                 (0xFU)
 #define USBHS_ENDPTNAK_EPRN_SHIFT                (0U)
-#define USBHS_ENDPTNAK_EPRN(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAK_EPRN_SHIFT)) & USBHS_ENDPTNAK_EPRN_MASK)
+#define USBHS_ENDPTNAK_EPRN_SET(x)               (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAK_EPRN_SHIFT)) & USBHS_ENDPTNAK_EPRN_MASK)
+#define USBHS_ENDPTNAK_EPRN USBHS_ENDPTNAK_EPRN_MASK
 #define USBHS_ENDPTNAK_EPTN_MASK                 (0xF0000U)
 #define USBHS_ENDPTNAK_EPTN_SHIFT                (16U)
-#define USBHS_ENDPTNAK_EPTN(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAK_EPTN_SHIFT)) & USBHS_ENDPTNAK_EPTN_MASK)
+#define USBHS_ENDPTNAK_EPTN_SET(x)               (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAK_EPTN_SHIFT)) & USBHS_ENDPTNAK_EPTN_MASK)
+#define USBHS_ENDPTNAK_EPTN USBHS_ENDPTNAK_EPTN_MASK
 
 /*! @name ENDPTNAKEN - Endpoint NAK Enable Register */
 #define USBHS_ENDPTNAKEN_EPRNE_MASK              (0xFU)
 #define USBHS_ENDPTNAKEN_EPRNE_SHIFT             (0U)
-#define USBHS_ENDPTNAKEN_EPRNE(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAKEN_EPRNE_SHIFT)) & USBHS_ENDPTNAKEN_EPRNE_MASK)
+#define USBHS_ENDPTNAKEN_EPRNE_SET(x)            (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAKEN_EPRNE_SHIFT)) & USBHS_ENDPTNAKEN_EPRNE_MASK)
+#define USBHS_ENDPTNAKEN_EPRNE USBHS_ENDPTNAKEN_EPRNE_MASK
 #define USBHS_ENDPTNAKEN_EPTNE_MASK              (0xF0000U)
 #define USBHS_ENDPTNAKEN_EPTNE_SHIFT             (16U)
-#define USBHS_ENDPTNAKEN_EPTNE(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAKEN_EPTNE_SHIFT)) & USBHS_ENDPTNAKEN_EPTNE_MASK)
+#define USBHS_ENDPTNAKEN_EPTNE_SET(x)            (((uint32_t)(((uint32_t)(x)) << USBHS_ENDPTNAKEN_EPTNE_SHIFT)) & USBHS_ENDPTNAKEN_EPTNE_MASK)
+#define USBHS_ENDPTNAKEN_EPTNE USBHS_ENDPTNAKEN_EPTNE_MASK
 
 /*! @name PORTSC1 - Port Status and Control Registers */
 #define USBHS_PORTSC1_CCS_MASK                   (0x1U)
 #define USBHS_PORTSC1_CCS_SHIFT                  (0U)
-#define USBHS_PORTSC1_CCS(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CCS_SHIFT)) & USBHS_PORTSC1_CCS_MASK)
+#define USBHS_PORTSC1_CCS_SET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CCS_SHIFT)) & USBHS_PORTSC1_CCS_MASK)
+#define USBHS_PORTSC1_CCS USBHS_PORTSC1_CCS_MASK
 #define USBHS_PORTSC1_CSC_MASK                   (0x2U)
 #define USBHS_PORTSC1_CSC_SHIFT                  (1U)
-#define USBHS_PORTSC1_CSC(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CSC_SHIFT)) & USBHS_PORTSC1_CSC_MASK)
+#define USBHS_PORTSC1_CSC_SET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_CSC_SHIFT)) & USBHS_PORTSC1_CSC_MASK)
+#define USBHS_PORTSC1_CSC USBHS_PORTSC1_CSC_MASK
 #define USBHS_PORTSC1_PE_MASK                    (0x4U)
 #define USBHS_PORTSC1_PE_SHIFT                   (2U)
-#define USBHS_PORTSC1_PE(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PE_SHIFT)) & USBHS_PORTSC1_PE_MASK)
+#define USBHS_PORTSC1_PE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PE_SHIFT)) & USBHS_PORTSC1_PE_MASK)
+#define USBHS_PORTSC1_PE USBHS_PORTSC1_PE_MASK
 #define USBHS_PORTSC1_PEC_MASK                   (0x8U)
 #define USBHS_PORTSC1_PEC_SHIFT                  (3U)
-#define USBHS_PORTSC1_PEC(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PEC_SHIFT)) & USBHS_PORTSC1_PEC_MASK)
+#define USBHS_PORTSC1_PEC_SET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PEC_SHIFT)) & USBHS_PORTSC1_PEC_MASK)
+#define USBHS_PORTSC1_PEC USBHS_PORTSC1_PEC_MASK
 #define USBHS_PORTSC1_OCA_MASK                   (0x10U)
 #define USBHS_PORTSC1_OCA_SHIFT                  (4U)
-#define USBHS_PORTSC1_OCA(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCA_SHIFT)) & USBHS_PORTSC1_OCA_MASK)
+#define USBHS_PORTSC1_OCA_SET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCA_SHIFT)) & USBHS_PORTSC1_OCA_MASK)
+#define USBHS_PORTSC1_OCA USBHS_PORTSC1_OCA_MASK
 #define USBHS_PORTSC1_OCC_MASK                   (0x20U)
 #define USBHS_PORTSC1_OCC_SHIFT                  (5U)
-#define USBHS_PORTSC1_OCC(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCC_SHIFT)) & USBHS_PORTSC1_OCC_MASK)
+#define USBHS_PORTSC1_OCC_SET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_OCC_SHIFT)) & USBHS_PORTSC1_OCC_MASK)
+#define USBHS_PORTSC1_OCC USBHS_PORTSC1_OCC_MASK
 #define USBHS_PORTSC1_FPR_MASK                   (0x40U)
 #define USBHS_PORTSC1_FPR_SHIFT                  (6U)
-#define USBHS_PORTSC1_FPR(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_FPR_SHIFT)) & USBHS_PORTSC1_FPR_MASK)
+#define USBHS_PORTSC1_FPR_SET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_FPR_SHIFT)) & USBHS_PORTSC1_FPR_MASK)
+#define USBHS_PORTSC1_FPR USBHS_PORTSC1_FPR_MASK
 #define USBHS_PORTSC1_SUSP_MASK                  (0x80U)
 #define USBHS_PORTSC1_SUSP_SHIFT                 (7U)
-#define USBHS_PORTSC1_SUSP(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_SUSP_SHIFT)) & USBHS_PORTSC1_SUSP_MASK)
+#define USBHS_PORTSC1_SUSP_SET(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_SUSP_SHIFT)) & USBHS_PORTSC1_SUSP_MASK)
+#define USBHS_PORTSC1_SUSP USBHS_PORTSC1_SUSP_MASK
 #define USBHS_PORTSC1_PR_MASK                    (0x100U)
 #define USBHS_PORTSC1_PR_SHIFT                   (8U)
-#define USBHS_PORTSC1_PR(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PR_SHIFT)) & USBHS_PORTSC1_PR_MASK)
+#define USBHS_PORTSC1_PR_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PR_SHIFT)) & USBHS_PORTSC1_PR_MASK)
+#define USBHS_PORTSC1_PR USBHS_PORTSC1_PR_MASK
 #define USBHS_PORTSC1_HSP_MASK                   (0x200U)
 #define USBHS_PORTSC1_HSP_SHIFT                  (9U)
-#define USBHS_PORTSC1_HSP(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_HSP_SHIFT)) & USBHS_PORTSC1_HSP_MASK)
+#define USBHS_PORTSC1_HSP_SET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_HSP_SHIFT)) & USBHS_PORTSC1_HSP_MASK)
+#define USBHS_PORTSC1_HSP USBHS_PORTSC1_HSP_MASK
 #define USBHS_PORTSC1_LS_MASK                    (0xC00U)
 #define USBHS_PORTSC1_LS_SHIFT                   (10U)
-#define USBHS_PORTSC1_LS(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_LS_SHIFT)) & USBHS_PORTSC1_LS_MASK)
+#define USBHS_PORTSC1_LS_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_LS_SHIFT)) & USBHS_PORTSC1_LS_MASK)
+#define USBHS_PORTSC1_LS USBHS_PORTSC1_LS_MASK
 #define USBHS_PORTSC1_PP_MASK                    (0x1000U)
 #define USBHS_PORTSC1_PP_SHIFT                   (12U)
-#define USBHS_PORTSC1_PP(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PP_SHIFT)) & USBHS_PORTSC1_PP_MASK)
+#define USBHS_PORTSC1_PP_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PP_SHIFT)) & USBHS_PORTSC1_PP_MASK)
+#define USBHS_PORTSC1_PP USBHS_PORTSC1_PP_MASK
 #define USBHS_PORTSC1_PO_MASK                    (0x2000U)
 #define USBHS_PORTSC1_PO_SHIFT                   (13U)
-#define USBHS_PORTSC1_PO(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PO_SHIFT)) & USBHS_PORTSC1_PO_MASK)
+#define USBHS_PORTSC1_PO_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PO_SHIFT)) & USBHS_PORTSC1_PO_MASK)
+#define USBHS_PORTSC1_PO USBHS_PORTSC1_PO_MASK
 #define USBHS_PORTSC1_PIC_MASK                   (0xC000U)
 #define USBHS_PORTSC1_PIC_SHIFT                  (14U)
-#define USBHS_PORTSC1_PIC(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PIC_SHIFT)) & USBHS_PORTSC1_PIC_MASK)
+#define USBHS_PORTSC1_PIC_SET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PIC_SHIFT)) & USBHS_PORTSC1_PIC_MASK)
+#define USBHS_PORTSC1_PIC USBHS_PORTSC1_PIC_MASK
 #define USBHS_PORTSC1_PTC_MASK                   (0xF0000U)
 #define USBHS_PORTSC1_PTC_SHIFT                  (16U)
-#define USBHS_PORTSC1_PTC(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTC_SHIFT)) & USBHS_PORTSC1_PTC_MASK)
+#define USBHS_PORTSC1_PTC_SET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTC_SHIFT)) & USBHS_PORTSC1_PTC_MASK)
+#define USBHS_PORTSC1_PTC USBHS_PORTSC1_PTC_MASK
 #define USBHS_PORTSC1_WKCN_MASK                  (0x100000U)
 #define USBHS_PORTSC1_WKCN_SHIFT                 (20U)
-#define USBHS_PORTSC1_WKCN(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKCN_SHIFT)) & USBHS_PORTSC1_WKCN_MASK)
+#define USBHS_PORTSC1_WKCN_SET(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKCN_SHIFT)) & USBHS_PORTSC1_WKCN_MASK)
+#define USBHS_PORTSC1_WKCN USBHS_PORTSC1_WKCN_MASK
 #define USBHS_PORTSC1_WKDS_MASK                  (0x200000U)
 #define USBHS_PORTSC1_WKDS_SHIFT                 (21U)
-#define USBHS_PORTSC1_WKDS(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKDS_SHIFT)) & USBHS_PORTSC1_WKDS_MASK)
+#define USBHS_PORTSC1_WKDS_SET(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKDS_SHIFT)) & USBHS_PORTSC1_WKDS_MASK)
+#define USBHS_PORTSC1_WKDS USBHS_PORTSC1_WKDS_MASK
 #define USBHS_PORTSC1_WKOC_MASK                  (0x400000U)
 #define USBHS_PORTSC1_WKOC_SHIFT                 (22U)
-#define USBHS_PORTSC1_WKOC(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKOC_SHIFT)) & USBHS_PORTSC1_WKOC_MASK)
+#define USBHS_PORTSC1_WKOC_SET(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_WKOC_SHIFT)) & USBHS_PORTSC1_WKOC_MASK)
+#define USBHS_PORTSC1_WKOC USBHS_PORTSC1_WKOC_MASK
 #define USBHS_PORTSC1_PHCD_MASK                  (0x800000U)
 #define USBHS_PORTSC1_PHCD_SHIFT                 (23U)
-#define USBHS_PORTSC1_PHCD(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PHCD_SHIFT)) & USBHS_PORTSC1_PHCD_MASK)
+#define USBHS_PORTSC1_PHCD_SET(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PHCD_SHIFT)) & USBHS_PORTSC1_PHCD_MASK)
+#define USBHS_PORTSC1_PHCD USBHS_PORTSC1_PHCD_MASK
 #define USBHS_PORTSC1_PFSC_MASK                  (0x1000000U)
 #define USBHS_PORTSC1_PFSC_SHIFT                 (24U)
-#define USBHS_PORTSC1_PFSC(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PFSC_SHIFT)) & USBHS_PORTSC1_PFSC_MASK)
+#define USBHS_PORTSC1_PFSC_SET(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PFSC_SHIFT)) & USBHS_PORTSC1_PFSC_MASK)
+#define USBHS_PORTSC1_PFSC USBHS_PORTSC1_PFSC_MASK
 #define USBHS_PORTSC1_PTS2_MASK                  (0x2000000U)
 #define USBHS_PORTSC1_PTS2_SHIFT                 (25U)
-#define USBHS_PORTSC1_PTS2(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTS2_SHIFT)) & USBHS_PORTSC1_PTS2_MASK)
+#define USBHS_PORTSC1_PTS2_SET(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTS2_SHIFT)) & USBHS_PORTSC1_PTS2_MASK)
+#define USBHS_PORTSC1_PTS2 USBHS_PORTSC1_PTS2_MASK
 #define USBHS_PORTSC1_PSPD_MASK                  (0xC000000U)
 #define USBHS_PORTSC1_PSPD_SHIFT                 (26U)
-#define USBHS_PORTSC1_PSPD(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PSPD_SHIFT)) & USBHS_PORTSC1_PSPD_MASK)
+#define USBHS_PORTSC1_PSPD_SET(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PSPD_SHIFT)) & USBHS_PORTSC1_PSPD_MASK)
+#define USBHS_PORTSC1_PSPD USBHS_PORTSC1_PSPD_MASK
 #define USBHS_PORTSC1_PTS_MASK                   (0xC0000000U)
 #define USBHS_PORTSC1_PTS_SHIFT                  (30U)
-#define USBHS_PORTSC1_PTS(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTS_SHIFT)) & USBHS_PORTSC1_PTS_MASK)
+#define USBHS_PORTSC1_PTS_SET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_PORTSC1_PTS_SHIFT)) & USBHS_PORTSC1_PTS_MASK)
+#define USBHS_PORTSC1_PTS USBHS_PORTSC1_PTS_MASK
 
 /*! @name OTGSC - On-the-Go Status and Control Register */
 #define USBHS_OTGSC_VD_MASK                      (0x1U)
 #define USBHS_OTGSC_VD_SHIFT                     (0U)
-#define USBHS_OTGSC_VD(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_VD_SHIFT)) & USBHS_OTGSC_VD_MASK)
+#define USBHS_OTGSC_VD_SET(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_VD_SHIFT)) & USBHS_OTGSC_VD_MASK)
+#define USBHS_OTGSC_VD USBHS_OTGSC_VD_MASK
 #define USBHS_OTGSC_VC_MASK                      (0x2U)
 #define USBHS_OTGSC_VC_SHIFT                     (1U)
-#define USBHS_OTGSC_VC(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_VC_SHIFT)) & USBHS_OTGSC_VC_MASK)
+#define USBHS_OTGSC_VC_SET(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_VC_SHIFT)) & USBHS_OTGSC_VC_MASK)
+#define USBHS_OTGSC_VC USBHS_OTGSC_VC_MASK
 #define USBHS_OTGSC_HAAR_MASK                    (0x4U)
 #define USBHS_OTGSC_HAAR_SHIFT                   (2U)
-#define USBHS_OTGSC_HAAR(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_HAAR_SHIFT)) & USBHS_OTGSC_HAAR_MASK)
+#define USBHS_OTGSC_HAAR_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_HAAR_SHIFT)) & USBHS_OTGSC_HAAR_MASK)
+#define USBHS_OTGSC_HAAR USBHS_OTGSC_HAAR_MASK
 #define USBHS_OTGSC_OT_MASK                      (0x8U)
 #define USBHS_OTGSC_OT_SHIFT                     (3U)
-#define USBHS_OTGSC_OT(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_OT_SHIFT)) & USBHS_OTGSC_OT_MASK)
+#define USBHS_OTGSC_OT_SET(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_OT_SHIFT)) & USBHS_OTGSC_OT_MASK)
+#define USBHS_OTGSC_OT USBHS_OTGSC_OT_MASK
 #define USBHS_OTGSC_DP_MASK                      (0x10U)
 #define USBHS_OTGSC_DP_SHIFT                     (4U)
-#define USBHS_OTGSC_DP(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DP_SHIFT)) & USBHS_OTGSC_DP_MASK)
+#define USBHS_OTGSC_DP_SET(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DP_SHIFT)) & USBHS_OTGSC_DP_MASK)
+#define USBHS_OTGSC_DP USBHS_OTGSC_DP_MASK
 #define USBHS_OTGSC_IDPU_MASK                    (0x20U)
 #define USBHS_OTGSC_IDPU_SHIFT                   (5U)
-#define USBHS_OTGSC_IDPU(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDPU_SHIFT)) & USBHS_OTGSC_IDPU_MASK)
+#define USBHS_OTGSC_IDPU_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDPU_SHIFT)) & USBHS_OTGSC_IDPU_MASK)
+#define USBHS_OTGSC_IDPU USBHS_OTGSC_IDPU_MASK
 #define USBHS_OTGSC_HABA_MASK                    (0x80U)
 #define USBHS_OTGSC_HABA_SHIFT                   (7U)
-#define USBHS_OTGSC_HABA(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_HABA_SHIFT)) & USBHS_OTGSC_HABA_MASK)
+#define USBHS_OTGSC_HABA_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_HABA_SHIFT)) & USBHS_OTGSC_HABA_MASK)
+#define USBHS_OTGSC_HABA USBHS_OTGSC_HABA_MASK
 #define USBHS_OTGSC_ID_MASK                      (0x100U)
 #define USBHS_OTGSC_ID_SHIFT                     (8U)
-#define USBHS_OTGSC_ID(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ID_SHIFT)) & USBHS_OTGSC_ID_MASK)
+#define USBHS_OTGSC_ID_SET(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ID_SHIFT)) & USBHS_OTGSC_ID_MASK)
+#define USBHS_OTGSC_ID USBHS_OTGSC_ID_MASK
 #define USBHS_OTGSC_AVV_MASK                     (0x200U)
 #define USBHS_OTGSC_AVV_SHIFT                    (9U)
-#define USBHS_OTGSC_AVV(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVV_SHIFT)) & USBHS_OTGSC_AVV_MASK)
+#define USBHS_OTGSC_AVV_SET(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVV_SHIFT)) & USBHS_OTGSC_AVV_MASK)
+#define USBHS_OTGSC_AVV USBHS_OTGSC_AVV_MASK
 #define USBHS_OTGSC_ASV_MASK                     (0x400U)
 #define USBHS_OTGSC_ASV_SHIFT                    (10U)
-#define USBHS_OTGSC_ASV(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASV_SHIFT)) & USBHS_OTGSC_ASV_MASK)
+#define USBHS_OTGSC_ASV_SET(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASV_SHIFT)) & USBHS_OTGSC_ASV_MASK)
+#define USBHS_OTGSC_ASV USBHS_OTGSC_ASV_MASK
 #define USBHS_OTGSC_BSV_MASK                     (0x800U)
 #define USBHS_OTGSC_BSV_SHIFT                    (11U)
-#define USBHS_OTGSC_BSV(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSV_SHIFT)) & USBHS_OTGSC_BSV_MASK)
+#define USBHS_OTGSC_BSV_SET(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSV_SHIFT)) & USBHS_OTGSC_BSV_MASK)
+#define USBHS_OTGSC_BSV USBHS_OTGSC_BSV_MASK
 #define USBHS_OTGSC_BSE_MASK                     (0x1000U)
 #define USBHS_OTGSC_BSE_SHIFT                    (12U)
-#define USBHS_OTGSC_BSE(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSE_SHIFT)) & USBHS_OTGSC_BSE_MASK)
+#define USBHS_OTGSC_BSE_SET(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSE_SHIFT)) & USBHS_OTGSC_BSE_MASK)
+#define USBHS_OTGSC_BSE USBHS_OTGSC_BSE_MASK
 #define USBHS_OTGSC_MST_MASK                     (0x2000U)
 #define USBHS_OTGSC_MST_SHIFT                    (13U)
-#define USBHS_OTGSC_MST(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_MST_SHIFT)) & USBHS_OTGSC_MST_MASK)
+#define USBHS_OTGSC_MST_SET(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_MST_SHIFT)) & USBHS_OTGSC_MST_MASK)
+#define USBHS_OTGSC_MST USBHS_OTGSC_MST_MASK
 #define USBHS_OTGSC_DPS_MASK                     (0x4000U)
 #define USBHS_OTGSC_DPS_SHIFT                    (14U)
-#define USBHS_OTGSC_DPS(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPS_SHIFT)) & USBHS_OTGSC_DPS_MASK)
+#define USBHS_OTGSC_DPS_SET(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPS_SHIFT)) & USBHS_OTGSC_DPS_MASK)
+#define USBHS_OTGSC_DPS USBHS_OTGSC_DPS_MASK
 #define USBHS_OTGSC_IDIS_MASK                    (0x10000U)
 #define USBHS_OTGSC_IDIS_SHIFT                   (16U)
-#define USBHS_OTGSC_IDIS(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDIS_SHIFT)) & USBHS_OTGSC_IDIS_MASK)
+#define USBHS_OTGSC_IDIS_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDIS_SHIFT)) & USBHS_OTGSC_IDIS_MASK)
+#define USBHS_OTGSC_IDIS USBHS_OTGSC_IDIS_MASK
 #define USBHS_OTGSC_AVVIS_MASK                   (0x20000U)
 #define USBHS_OTGSC_AVVIS_SHIFT                  (17U)
-#define USBHS_OTGSC_AVVIS(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVVIS_SHIFT)) & USBHS_OTGSC_AVVIS_MASK)
+#define USBHS_OTGSC_AVVIS_SET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVVIS_SHIFT)) & USBHS_OTGSC_AVVIS_MASK)
+#define USBHS_OTGSC_AVVIS USBHS_OTGSC_AVVIS_MASK
 #define USBHS_OTGSC_ASVIS_MASK                   (0x40000U)
 #define USBHS_OTGSC_ASVIS_SHIFT                  (18U)
-#define USBHS_OTGSC_ASVIS(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASVIS_SHIFT)) & USBHS_OTGSC_ASVIS_MASK)
+#define USBHS_OTGSC_ASVIS_SET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASVIS_SHIFT)) & USBHS_OTGSC_ASVIS_MASK)
+#define USBHS_OTGSC_ASVIS USBHS_OTGSC_ASVIS_MASK
 #define USBHS_OTGSC_BSVIS_MASK                   (0x80000U)
 #define USBHS_OTGSC_BSVIS_SHIFT                  (19U)
-#define USBHS_OTGSC_BSVIS(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSVIS_SHIFT)) & USBHS_OTGSC_BSVIS_MASK)
+#define USBHS_OTGSC_BSVIS_SET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSVIS_SHIFT)) & USBHS_OTGSC_BSVIS_MASK)
+#define USBHS_OTGSC_BSVIS USBHS_OTGSC_BSVIS_MASK
 #define USBHS_OTGSC_BSEIS_MASK                   (0x100000U)
 #define USBHS_OTGSC_BSEIS_SHIFT                  (20U)
-#define USBHS_OTGSC_BSEIS(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSEIS_SHIFT)) & USBHS_OTGSC_BSEIS_MASK)
+#define USBHS_OTGSC_BSEIS_SET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSEIS_SHIFT)) & USBHS_OTGSC_BSEIS_MASK)
+#define USBHS_OTGSC_BSEIS USBHS_OTGSC_BSEIS_MASK
 #define USBHS_OTGSC_MSS_MASK                     (0x200000U)
 #define USBHS_OTGSC_MSS_SHIFT                    (21U)
-#define USBHS_OTGSC_MSS(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_MSS_SHIFT)) & USBHS_OTGSC_MSS_MASK)
+#define USBHS_OTGSC_MSS_SET(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_MSS_SHIFT)) & USBHS_OTGSC_MSS_MASK)
+#define USBHS_OTGSC_MSS USBHS_OTGSC_MSS_MASK
 #define USBHS_OTGSC_DPIS_MASK                    (0x400000U)
 #define USBHS_OTGSC_DPIS_SHIFT                   (22U)
-#define USBHS_OTGSC_DPIS(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPIS_SHIFT)) & USBHS_OTGSC_DPIS_MASK)
+#define USBHS_OTGSC_DPIS_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPIS_SHIFT)) & USBHS_OTGSC_DPIS_MASK)
+#define USBHS_OTGSC_DPIS USBHS_OTGSC_DPIS_MASK
 #define USBHS_OTGSC_IDIE_MASK                    (0x1000000U)
 #define USBHS_OTGSC_IDIE_SHIFT                   (24U)
-#define USBHS_OTGSC_IDIE(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDIE_SHIFT)) & USBHS_OTGSC_IDIE_MASK)
+#define USBHS_OTGSC_IDIE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_IDIE_SHIFT)) & USBHS_OTGSC_IDIE_MASK)
+#define USBHS_OTGSC_IDIE USBHS_OTGSC_IDIE_MASK
 #define USBHS_OTGSC_AVVIE_MASK                   (0x2000000U)
 #define USBHS_OTGSC_AVVIE_SHIFT                  (25U)
-#define USBHS_OTGSC_AVVIE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVVIE_SHIFT)) & USBHS_OTGSC_AVVIE_MASK)
+#define USBHS_OTGSC_AVVIE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_AVVIE_SHIFT)) & USBHS_OTGSC_AVVIE_MASK)
+#define USBHS_OTGSC_AVVIE USBHS_OTGSC_AVVIE_MASK
 #define USBHS_OTGSC_ASVIE_MASK                   (0x4000000U)
 #define USBHS_OTGSC_ASVIE_SHIFT                  (26U)
-#define USBHS_OTGSC_ASVIE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASVIE_SHIFT)) & USBHS_OTGSC_ASVIE_MASK)
+#define USBHS_OTGSC_ASVIE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_ASVIE_SHIFT)) & USBHS_OTGSC_ASVIE_MASK)
+#define USBHS_OTGSC_ASVIE USBHS_OTGSC_ASVIE_MASK
 #define USBHS_OTGSC_BSVIE_MASK                   (0x8000000U)
 #define USBHS_OTGSC_BSVIE_SHIFT                  (27U)
-#define USBHS_OTGSC_BSVIE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSVIE_SHIFT)) & USBHS_OTGSC_BSVIE_MASK)
+#define USBHS_OTGSC_BSVIE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSVIE_SHIFT)) & USBHS_OTGSC_BSVIE_MASK)
+#define USBHS_OTGSC_BSVIE USBHS_OTGSC_BSVIE_MASK
 #define USBHS_OTGSC_BSEIE_MASK                   (0x10000000U)
 #define USBHS_OTGSC_BSEIE_SHIFT                  (28U)
-#define USBHS_OTGSC_BSEIE(x)                     (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSEIE_SHIFT)) & USBHS_OTGSC_BSEIE_MASK)
+#define USBHS_OTGSC_BSEIE_SET(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_BSEIE_SHIFT)) & USBHS_OTGSC_BSEIE_MASK)
+#define USBHS_OTGSC_BSEIE USBHS_OTGSC_BSEIE_MASK
 #define USBHS_OTGSC_MSE_MASK                     (0x20000000U)
 #define USBHS_OTGSC_MSE_SHIFT                    (29U)
-#define USBHS_OTGSC_MSE(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_MSE_SHIFT)) & USBHS_OTGSC_MSE_MASK)
+#define USBHS_OTGSC_MSE_SET(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_MSE_SHIFT)) & USBHS_OTGSC_MSE_MASK)
+#define USBHS_OTGSC_MSE USBHS_OTGSC_MSE_MASK
 #define USBHS_OTGSC_DPIE_MASK                    (0x40000000U)
 #define USBHS_OTGSC_DPIE_SHIFT                   (30U)
-#define USBHS_OTGSC_DPIE(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPIE_SHIFT)) & USBHS_OTGSC_DPIE_MASK)
+#define USBHS_OTGSC_DPIE_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_OTGSC_DPIE_SHIFT)) & USBHS_OTGSC_DPIE_MASK)
+#define USBHS_OTGSC_DPIE USBHS_OTGSC_DPIE_MASK
 
 /*! @name USBMODE - USB Mode Register */
 #define USBHS_USBMODE_CM_MASK                    (0x3U)
 #define USBHS_USBMODE_CM_SHIFT                   (0U)
-#define USBHS_USBMODE_CM(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_CM_SHIFT)) & USBHS_USBMODE_CM_MASK)
+#define USBHS_USBMODE_CM_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_CM_SHIFT)) & USBHS_USBMODE_CM_MASK)
+#define USBHS_USBMODE_CM USBHS_USBMODE_CM_MASK
 #define USBHS_USBMODE_ES_MASK                    (0x4U)
 #define USBHS_USBMODE_ES_SHIFT                   (2U)
-#define USBHS_USBMODE_ES(x)                      (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_ES_SHIFT)) & USBHS_USBMODE_ES_MASK)
+#define USBHS_USBMODE_ES_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_ES_SHIFT)) & USBHS_USBMODE_ES_MASK)
+#define USBHS_USBMODE_ES USBHS_USBMODE_ES_MASK
 #define USBHS_USBMODE_SLOM_MASK                  (0x8U)
 #define USBHS_USBMODE_SLOM_SHIFT                 (3U)
-#define USBHS_USBMODE_SLOM(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_SLOM_SHIFT)) & USBHS_USBMODE_SLOM_MASK)
+#define USBHS_USBMODE_SLOM_SET(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_SLOM_SHIFT)) & USBHS_USBMODE_SLOM_MASK)
+#define USBHS_USBMODE_SLOM USBHS_USBMODE_SLOM_MASK
 #define USBHS_USBMODE_SDIS_MASK                  (0x10U)
 #define USBHS_USBMODE_SDIS_SHIFT                 (4U)
-#define USBHS_USBMODE_SDIS(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_SDIS_SHIFT)) & USBHS_USBMODE_SDIS_MASK)
+#define USBHS_USBMODE_SDIS_SET(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_SDIS_SHIFT)) & USBHS_USBMODE_SDIS_MASK)
+#define USBHS_USBMODE_SDIS USBHS_USBMODE_SDIS_MASK
 #define USBHS_USBMODE_TXHSD_MASK                 (0x7000U)
 #define USBHS_USBMODE_TXHSD_SHIFT                (12U)
-#define USBHS_USBMODE_TXHSD(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_TXHSD_SHIFT)) & USBHS_USBMODE_TXHSD_MASK)
+#define USBHS_USBMODE_TXHSD_SET(x)               (((uint32_t)(((uint32_t)(x)) << USBHS_USBMODE_TXHSD_SHIFT)) & USBHS_USBMODE_TXHSD_MASK)
+#define USBHS_USBMODE_TXHSD USBHS_USBMODE_TXHSD_MASK
 
 /*! @name EPSETUPSR - Endpoint Setup Status Register */
 #define USBHS_EPSETUPSR_EPSETUPSTAT_MASK         (0xFU)
 #define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT        (0U)
-#define USBHS_EPSETUPSR_EPSETUPSTAT(x)           (((uint32_t)(((uint32_t)(x)) << USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT)) & USBHS_EPSETUPSR_EPSETUPSTAT_MASK)
+#define USBHS_EPSETUPSR_EPSETUPSTAT_SET(x)       (((uint32_t)(((uint32_t)(x)) << USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT)) & USBHS_EPSETUPSR_EPSETUPSTAT_MASK)
+#define USBHS_EPSETUPSR_EPSETUPSTAT USBHS_EPSETUPSR_EPSETUPSTAT_MASK
 
 /*! @name EPPRIME - Endpoint Initialization Register */
 #define USBHS_EPPRIME_PERB_MASK                  (0xFU)
 #define USBHS_EPPRIME_PERB_SHIFT                 (0U)
-#define USBHS_EPPRIME_PERB(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_EPPRIME_PERB_SHIFT)) & USBHS_EPPRIME_PERB_MASK)
+#define USBHS_EPPRIME_PERB_SET(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_EPPRIME_PERB_SHIFT)) & USBHS_EPPRIME_PERB_MASK)
+#define USBHS_EPPRIME_PERB USBHS_EPPRIME_PERB_MASK
 #define USBHS_EPPRIME_PETB_MASK                  (0xF0000U)
 #define USBHS_EPPRIME_PETB_SHIFT                 (16U)
-#define USBHS_EPPRIME_PETB(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_EPPRIME_PETB_SHIFT)) & USBHS_EPPRIME_PETB_MASK)
+#define USBHS_EPPRIME_PETB_SET(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_EPPRIME_PETB_SHIFT)) & USBHS_EPPRIME_PETB_MASK)
+#define USBHS_EPPRIME_PETB USBHS_EPPRIME_PETB_MASK
 
 /*! @name EPFLUSH - Endpoint Flush Register */
 #define USBHS_EPFLUSH_FERB_MASK                  (0xFU)
 #define USBHS_EPFLUSH_FERB_SHIFT                 (0U)
-#define USBHS_EPFLUSH_FERB(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_EPFLUSH_FERB_SHIFT)) & USBHS_EPFLUSH_FERB_MASK)
+#define USBHS_EPFLUSH_FERB_SET(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_EPFLUSH_FERB_SHIFT)) & USBHS_EPFLUSH_FERB_MASK)
+#define USBHS_EPFLUSH_FERB USBHS_EPFLUSH_FERB_MASK
 #define USBHS_EPFLUSH_FETB_MASK                  (0xF0000U)
 #define USBHS_EPFLUSH_FETB_SHIFT                 (16U)
-#define USBHS_EPFLUSH_FETB(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_EPFLUSH_FETB_SHIFT)) & USBHS_EPFLUSH_FETB_MASK)
+#define USBHS_EPFLUSH_FETB_SET(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_EPFLUSH_FETB_SHIFT)) & USBHS_EPFLUSH_FETB_MASK)
+#define USBHS_EPFLUSH_FETB USBHS_EPFLUSH_FETB_MASK
 
 /*! @name EPSR - Endpoint Status Register */
 #define USBHS_EPSR_ERBR_MASK                     (0xFU)
 #define USBHS_EPSR_ERBR_SHIFT                    (0U)
-#define USBHS_EPSR_ERBR(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_EPSR_ERBR_SHIFT)) & USBHS_EPSR_ERBR_MASK)
+#define USBHS_EPSR_ERBR_SET(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_EPSR_ERBR_SHIFT)) & USBHS_EPSR_ERBR_MASK)
+#define USBHS_EPSR_ERBR USBHS_EPSR_ERBR_MASK
 #define USBHS_EPSR_ETBR_MASK                     (0xF0000U)
 #define USBHS_EPSR_ETBR_SHIFT                    (16U)
-#define USBHS_EPSR_ETBR(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_EPSR_ETBR_SHIFT)) & USBHS_EPSR_ETBR_MASK)
+#define USBHS_EPSR_ETBR_SET(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_EPSR_ETBR_SHIFT)) & USBHS_EPSR_ETBR_MASK)
+#define USBHS_EPSR_ETBR USBHS_EPSR_ETBR_MASK
 
 /*! @name EPCOMPLETE - Endpoint Complete Register */
 #define USBHS_EPCOMPLETE_ERCE_MASK               (0xFU)
 #define USBHS_EPCOMPLETE_ERCE_SHIFT              (0U)
-#define USBHS_EPCOMPLETE_ERCE(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_EPCOMPLETE_ERCE_SHIFT)) & USBHS_EPCOMPLETE_ERCE_MASK)
+#define USBHS_EPCOMPLETE_ERCE_SET(x)             (((uint32_t)(((uint32_t)(x)) << USBHS_EPCOMPLETE_ERCE_SHIFT)) & USBHS_EPCOMPLETE_ERCE_MASK)
+#define USBHS_EPCOMPLETE_ERCE USBHS_EPCOMPLETE_ERCE_MASK
 #define USBHS_EPCOMPLETE_ETCE_MASK               (0xF0000U)
 #define USBHS_EPCOMPLETE_ETCE_SHIFT              (16U)
-#define USBHS_EPCOMPLETE_ETCE(x)                 (((uint32_t)(((uint32_t)(x)) << USBHS_EPCOMPLETE_ETCE_SHIFT)) & USBHS_EPCOMPLETE_ETCE_MASK)
+#define USBHS_EPCOMPLETE_ETCE_SET(x)             (((uint32_t)(((uint32_t)(x)) << USBHS_EPCOMPLETE_ETCE_SHIFT)) & USBHS_EPCOMPLETE_ETCE_MASK)
+#define USBHS_EPCOMPLETE_ETCE USBHS_EPCOMPLETE_ETCE_MASK
 
 /*! @name EPCR0 - Endpoint Control Register 0 */
 #define USBHS_EPCR0_RXS_MASK                     (0x1U)
 #define USBHS_EPCR0_RXS_SHIFT                    (0U)
-#define USBHS_EPCR0_RXS(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_RXS_SHIFT)) & USBHS_EPCR0_RXS_MASK)
+#define USBHS_EPCR0_RXS_SET(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_RXS_SHIFT)) & USBHS_EPCR0_RXS_MASK)
+#define USBHS_EPCR0_RXS USBHS_EPCR0_RXS_MASK
 #define USBHS_EPCR0_RXT_MASK                     (0xCU)
 #define USBHS_EPCR0_RXT_SHIFT                    (2U)
-#define USBHS_EPCR0_RXT(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_RXT_SHIFT)) & USBHS_EPCR0_RXT_MASK)
+#define USBHS_EPCR0_RXT_SET(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_RXT_SHIFT)) & USBHS_EPCR0_RXT_MASK)
+#define USBHS_EPCR0_RXT USBHS_EPCR0_RXT_MASK
 #define USBHS_EPCR0_RXE_MASK                     (0x80U)
 #define USBHS_EPCR0_RXE_SHIFT                    (7U)
-#define USBHS_EPCR0_RXE(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_RXE_SHIFT)) & USBHS_EPCR0_RXE_MASK)
+#define USBHS_EPCR0_RXE_SET(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_RXE_SHIFT)) & USBHS_EPCR0_RXE_MASK)
+#define USBHS_EPCR0_RXE USBHS_EPCR0_RXE_MASK
 #define USBHS_EPCR0_TXS_MASK                     (0x10000U)
 #define USBHS_EPCR0_TXS_SHIFT                    (16U)
-#define USBHS_EPCR0_TXS(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_TXS_SHIFT)) & USBHS_EPCR0_TXS_MASK)
+#define USBHS_EPCR0_TXS_SET(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_TXS_SHIFT)) & USBHS_EPCR0_TXS_MASK)
+#define USBHS_EPCR0_TXS USBHS_EPCR0_TXS_MASK
 #define USBHS_EPCR0_TXT_MASK                     (0xC0000U)
 #define USBHS_EPCR0_TXT_SHIFT                    (18U)
-#define USBHS_EPCR0_TXT(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_TXT_SHIFT)) & USBHS_EPCR0_TXT_MASK)
+#define USBHS_EPCR0_TXT_SET(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_TXT_SHIFT)) & USBHS_EPCR0_TXT_MASK)
+#define USBHS_EPCR0_TXT USBHS_EPCR0_TXT_MASK
 #define USBHS_EPCR0_TXE_MASK                     (0x800000U)
 #define USBHS_EPCR0_TXE_SHIFT                    (23U)
-#define USBHS_EPCR0_TXE(x)                       (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_TXE_SHIFT)) & USBHS_EPCR0_TXE_MASK)
+#define USBHS_EPCR0_TXE_SET(x)                   (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR0_TXE_SHIFT)) & USBHS_EPCR0_TXE_MASK)
+#define USBHS_EPCR0_TXE USBHS_EPCR0_TXE_MASK
 
 /*! @name EPCR - Endpoint Control Register n */
 #define USBHS_EPCR_RXS_MASK                      (0x1U)
 #define USBHS_EPCR_RXS_SHIFT                     (0U)
-#define USBHS_EPCR_RXS(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXS_SHIFT)) & USBHS_EPCR_RXS_MASK)
+#define USBHS_EPCR_RXS_SET(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXS_SHIFT)) & USBHS_EPCR_RXS_MASK)
+#define USBHS_EPCR_RXS USBHS_EPCR_RXS_MASK
 #define USBHS_EPCR_RXD_MASK                      (0x2U)
 #define USBHS_EPCR_RXD_SHIFT                     (1U)
-#define USBHS_EPCR_RXD(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXD_SHIFT)) & USBHS_EPCR_RXD_MASK)
+#define USBHS_EPCR_RXD_SET(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXD_SHIFT)) & USBHS_EPCR_RXD_MASK)
+#define USBHS_EPCR_RXD USBHS_EPCR_RXD_MASK
 #define USBHS_EPCR_RXT_MASK                      (0xCU)
 #define USBHS_EPCR_RXT_SHIFT                     (2U)
-#define USBHS_EPCR_RXT(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXT_SHIFT)) & USBHS_EPCR_RXT_MASK)
+#define USBHS_EPCR_RXT_SET(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXT_SHIFT)) & USBHS_EPCR_RXT_MASK)
+#define USBHS_EPCR_RXT USBHS_EPCR_RXT_MASK
 #define USBHS_EPCR_RXI_MASK                      (0x20U)
 #define USBHS_EPCR_RXI_SHIFT                     (5U)
-#define USBHS_EPCR_RXI(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXI_SHIFT)) & USBHS_EPCR_RXI_MASK)
+#define USBHS_EPCR_RXI_SET(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXI_SHIFT)) & USBHS_EPCR_RXI_MASK)
+#define USBHS_EPCR_RXI USBHS_EPCR_RXI_MASK
 #define USBHS_EPCR_RXR_MASK                      (0x40U)
 #define USBHS_EPCR_RXR_SHIFT                     (6U)
-#define USBHS_EPCR_RXR(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXR_SHIFT)) & USBHS_EPCR_RXR_MASK)
+#define USBHS_EPCR_RXR_SET(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXR_SHIFT)) & USBHS_EPCR_RXR_MASK)
+#define USBHS_EPCR_RXR USBHS_EPCR_RXR_MASK
 #define USBHS_EPCR_RXE_MASK                      (0x80U)
 #define USBHS_EPCR_RXE_SHIFT                     (7U)
-#define USBHS_EPCR_RXE(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXE_SHIFT)) & USBHS_EPCR_RXE_MASK)
+#define USBHS_EPCR_RXE_SET(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_RXE_SHIFT)) & USBHS_EPCR_RXE_MASK)
+#define USBHS_EPCR_RXE USBHS_EPCR_RXE_MASK
 #define USBHS_EPCR_TXS_MASK                      (0x10000U)
 #define USBHS_EPCR_TXS_SHIFT                     (16U)
-#define USBHS_EPCR_TXS(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXS_SHIFT)) & USBHS_EPCR_TXS_MASK)
+#define USBHS_EPCR_TXS_SET(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXS_SHIFT)) & USBHS_EPCR_TXS_MASK)
+#define USBHS_EPCR_TXS USBHS_EPCR_TXS_MASK
 #define USBHS_EPCR_TXD_MASK                      (0x20000U)
 #define USBHS_EPCR_TXD_SHIFT                     (17U)
-#define USBHS_EPCR_TXD(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXD_SHIFT)) & USBHS_EPCR_TXD_MASK)
+#define USBHS_EPCR_TXD_SET(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXD_SHIFT)) & USBHS_EPCR_TXD_MASK)
+#define USBHS_EPCR_TXD USBHS_EPCR_TXD_MASK
 #define USBHS_EPCR_TXT_MASK                      (0xC0000U)
 #define USBHS_EPCR_TXT_SHIFT                     (18U)
-#define USBHS_EPCR_TXT(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXT_SHIFT)) & USBHS_EPCR_TXT_MASK)
+#define USBHS_EPCR_TXT_SET(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXT_SHIFT)) & USBHS_EPCR_TXT_MASK)
+#define USBHS_EPCR_TXT USBHS_EPCR_TXT_MASK
 #define USBHS_EPCR_TXI_MASK                      (0x200000U)
 #define USBHS_EPCR_TXI_SHIFT                     (21U)
-#define USBHS_EPCR_TXI(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXI_SHIFT)) & USBHS_EPCR_TXI_MASK)
+#define USBHS_EPCR_TXI_SET(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXI_SHIFT)) & USBHS_EPCR_TXI_MASK)
+#define USBHS_EPCR_TXI USBHS_EPCR_TXI_MASK
 #define USBHS_EPCR_TXR_MASK                      (0x400000U)
 #define USBHS_EPCR_TXR_SHIFT                     (22U)
-#define USBHS_EPCR_TXR(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXR_SHIFT)) & USBHS_EPCR_TXR_MASK)
+#define USBHS_EPCR_TXR_SET(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXR_SHIFT)) & USBHS_EPCR_TXR_MASK)
+#define USBHS_EPCR_TXR USBHS_EPCR_TXR_MASK
 #define USBHS_EPCR_TXE_MASK                      (0x800000U)
 #define USBHS_EPCR_TXE_SHIFT                     (23U)
-#define USBHS_EPCR_TXE(x)                        (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXE_SHIFT)) & USBHS_EPCR_TXE_MASK)
+#define USBHS_EPCR_TXE_SET(x)                    (((uint32_t)(((uint32_t)(x)) << USBHS_EPCR_TXE_SHIFT)) & USBHS_EPCR_TXE_MASK)
+#define USBHS_EPCR_TXE USBHS_EPCR_TXE_MASK
 
 /* The count of USBHS_EPCR */
 #define USBHS_EPCR_COUNT                         (7U)
@@ -15555,10 +18793,12 @@ typedef struct {
 /*! @name USBGENCTRL - USB General Control Register */
 #define USBHS_USBGENCTRL_WU_IE_MASK              (0x1U)
 #define USBHS_USBGENCTRL_WU_IE_SHIFT             (0U)
-#define USBHS_USBGENCTRL_WU_IE(x)                (((uint32_t)(((uint32_t)(x)) << USBHS_USBGENCTRL_WU_IE_SHIFT)) & USBHS_USBGENCTRL_WU_IE_MASK)
+#define USBHS_USBGENCTRL_WU_IE_SET(x)            (((uint32_t)(((uint32_t)(x)) << USBHS_USBGENCTRL_WU_IE_SHIFT)) & USBHS_USBGENCTRL_WU_IE_MASK)
+#define USBHS_USBGENCTRL_WU_IE USBHS_USBGENCTRL_WU_IE_MASK
 #define USBHS_USBGENCTRL_WU_INT_CLR_MASK         (0x20U)
 #define USBHS_USBGENCTRL_WU_INT_CLR_SHIFT        (5U)
-#define USBHS_USBGENCTRL_WU_INT_CLR(x)           (((uint32_t)(((uint32_t)(x)) << USBHS_USBGENCTRL_WU_INT_CLR_SHIFT)) & USBHS_USBGENCTRL_WU_INT_CLR_MASK)
+#define USBHS_USBGENCTRL_WU_INT_CLR_SET(x)       (((uint32_t)(((uint32_t)(x)) << USBHS_USBGENCTRL_WU_INT_CLR_SHIFT)) & USBHS_USBGENCTRL_WU_INT_CLR_MASK)
+#define USBHS_USBGENCTRL_WU_INT_CLR USBHS_USBGENCTRL_WU_INT_CLR_MASK
 
 
 /*!
@@ -15570,7 +18810,7 @@ typedef struct {
 /** Peripheral USBHS base address */
 #define USBHS_BASE                               (0x400A1000u)
 /** Peripheral USBHS base pointer */
-#define USBHS                                    ((USBHS_Type *)USBHS_BASE)
+#define USBHS                                    ((USBHS_TypeDef *)USBHS_BASE)
 /** Array initializer of USBHS peripheral base addresses */
 #define USBHS_BASE_ADDRS                         { USBHS_BASE }
 /** Array initializer of USBHS peripheral base pointers */
@@ -15604,7 +18844,7 @@ typedef struct {
     __IO uint32_t TIMER2_BC11;                       /**< TIMER2_BC11 register, offset: 0x18 */
     __IO uint32_t TIMER2_BC12;                       /**< TIMER2_BC12 register, offset: 0x18 */
   };
-} USBHSDCD_Type;
+} USBHSDCD_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- USBHSDCD Register Masks
@@ -15618,81 +18858,102 @@ typedef struct {
 /*! @name CONTROL - Control register */
 #define USBHSDCD_CONTROL_IACK_MASK               (0x1U)
 #define USBHSDCD_CONTROL_IACK_SHIFT              (0U)
-#define USBHSDCD_CONTROL_IACK(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IACK_SHIFT)) & USBHSDCD_CONTROL_IACK_MASK)
+#define USBHSDCD_CONTROL_IACK_SET(x)             (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IACK_SHIFT)) & USBHSDCD_CONTROL_IACK_MASK)
+#define USBHSDCD_CONTROL_IACK USBHSDCD_CONTROL_IACK_MASK
 #define USBHSDCD_CONTROL_IF_MASK                 (0x100U)
 #define USBHSDCD_CONTROL_IF_SHIFT                (8U)
-#define USBHSDCD_CONTROL_IF(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IF_SHIFT)) & USBHSDCD_CONTROL_IF_MASK)
+#define USBHSDCD_CONTROL_IF_SET(x)               (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IF_SHIFT)) & USBHSDCD_CONTROL_IF_MASK)
+#define USBHSDCD_CONTROL_IF USBHSDCD_CONTROL_IF_MASK
 #define USBHSDCD_CONTROL_IE_MASK                 (0x10000U)
 #define USBHSDCD_CONTROL_IE_SHIFT                (16U)
-#define USBHSDCD_CONTROL_IE(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IE_SHIFT)) & USBHSDCD_CONTROL_IE_MASK)
+#define USBHSDCD_CONTROL_IE_SET(x)               (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IE_SHIFT)) & USBHSDCD_CONTROL_IE_MASK)
+#define USBHSDCD_CONTROL_IE USBHSDCD_CONTROL_IE_MASK
 #define USBHSDCD_CONTROL_BC12_MASK               (0x20000U)
 #define USBHSDCD_CONTROL_BC12_SHIFT              (17U)
-#define USBHSDCD_CONTROL_BC12(x)                 (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_BC12_SHIFT)) & USBHSDCD_CONTROL_BC12_MASK)
+#define USBHSDCD_CONTROL_BC12_SET(x)             (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_BC12_SHIFT)) & USBHSDCD_CONTROL_BC12_MASK)
+#define USBHSDCD_CONTROL_BC12 USBHSDCD_CONTROL_BC12_MASK
 #define USBHSDCD_CONTROL_START_MASK              (0x1000000U)
 #define USBHSDCD_CONTROL_START_SHIFT             (24U)
-#define USBHSDCD_CONTROL_START(x)                (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_START_SHIFT)) & USBHSDCD_CONTROL_START_MASK)
+#define USBHSDCD_CONTROL_START_SET(x)            (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_START_SHIFT)) & USBHSDCD_CONTROL_START_MASK)
+#define USBHSDCD_CONTROL_START USBHSDCD_CONTROL_START_MASK
 #define USBHSDCD_CONTROL_SR_MASK                 (0x2000000U)
 #define USBHSDCD_CONTROL_SR_SHIFT                (25U)
-#define USBHSDCD_CONTROL_SR(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_SR_SHIFT)) & USBHSDCD_CONTROL_SR_MASK)
+#define USBHSDCD_CONTROL_SR_SET(x)               (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_SR_SHIFT)) & USBHSDCD_CONTROL_SR_MASK)
+#define USBHSDCD_CONTROL_SR USBHSDCD_CONTROL_SR_MASK
 
 /*! @name CLOCK - Clock register */
 #define USBHSDCD_CLOCK_CLOCK_UNIT_MASK           (0x1U)
 #define USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT          (0U)
-#define USBHSDCD_CLOCK_CLOCK_UNIT(x)             (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBHSDCD_CLOCK_CLOCK_UNIT_MASK)
+#define USBHSDCD_CLOCK_CLOCK_UNIT_SET(x)         (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBHSDCD_CLOCK_CLOCK_UNIT_MASK)
+#define USBHSDCD_CLOCK_CLOCK_UNIT USBHSDCD_CLOCK_CLOCK_UNIT_MASK
 #define USBHSDCD_CLOCK_CLOCK_SPEED_MASK          (0xFFCU)
 #define USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT         (2U)
-#define USBHSDCD_CLOCK_CLOCK_SPEED(x)            (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBHSDCD_CLOCK_CLOCK_SPEED_MASK)
+#define USBHSDCD_CLOCK_CLOCK_SPEED_SET(x)        (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBHSDCD_CLOCK_CLOCK_SPEED_MASK)
+#define USBHSDCD_CLOCK_CLOCK_SPEED USBHSDCD_CLOCK_CLOCK_SPEED_MASK
 
 /*! @name STATUS - Status register */
 #define USBHSDCD_STATUS_SEQ_RES_MASK             (0x30000U)
 #define USBHSDCD_STATUS_SEQ_RES_SHIFT            (16U)
-#define USBHSDCD_STATUS_SEQ_RES(x)               (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_RES_SHIFT)) & USBHSDCD_STATUS_SEQ_RES_MASK)
+#define USBHSDCD_STATUS_SEQ_RES_SET(x)           (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_RES_SHIFT)) & USBHSDCD_STATUS_SEQ_RES_MASK)
+#define USBHSDCD_STATUS_SEQ_RES USBHSDCD_STATUS_SEQ_RES_MASK
 #define USBHSDCD_STATUS_SEQ_STAT_MASK            (0xC0000U)
 #define USBHSDCD_STATUS_SEQ_STAT_SHIFT           (18U)
-#define USBHSDCD_STATUS_SEQ_STAT(x)              (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_STAT_SHIFT)) & USBHSDCD_STATUS_SEQ_STAT_MASK)
+#define USBHSDCD_STATUS_SEQ_STAT_SET(x)          (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_STAT_SHIFT)) & USBHSDCD_STATUS_SEQ_STAT_MASK)
+#define USBHSDCD_STATUS_SEQ_STAT USBHSDCD_STATUS_SEQ_STAT_MASK
 #define USBHSDCD_STATUS_ERR_MASK                 (0x100000U)
 #define USBHSDCD_STATUS_ERR_SHIFT                (20U)
-#define USBHSDCD_STATUS_ERR(x)                   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ERR_SHIFT)) & USBHSDCD_STATUS_ERR_MASK)
+#define USBHSDCD_STATUS_ERR_SET(x)               (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ERR_SHIFT)) & USBHSDCD_STATUS_ERR_MASK)
+#define USBHSDCD_STATUS_ERR USBHSDCD_STATUS_ERR_MASK
 #define USBHSDCD_STATUS_TO_MASK                  (0x200000U)
 #define USBHSDCD_STATUS_TO_SHIFT                 (21U)
-#define USBHSDCD_STATUS_TO(x)                    (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_TO_SHIFT)) & USBHSDCD_STATUS_TO_MASK)
+#define USBHSDCD_STATUS_TO_SET(x)                (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_TO_SHIFT)) & USBHSDCD_STATUS_TO_MASK)
+#define USBHSDCD_STATUS_TO USBHSDCD_STATUS_TO_MASK
 #define USBHSDCD_STATUS_ACTIVE_MASK              (0x400000U)
 #define USBHSDCD_STATUS_ACTIVE_SHIFT             (22U)
-#define USBHSDCD_STATUS_ACTIVE(x)                (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ACTIVE_SHIFT)) & USBHSDCD_STATUS_ACTIVE_MASK)
+#define USBHSDCD_STATUS_ACTIVE_SET(x)            (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ACTIVE_SHIFT)) & USBHSDCD_STATUS_ACTIVE_MASK)
+#define USBHSDCD_STATUS_ACTIVE USBHSDCD_STATUS_ACTIVE_MASK
 
 /*! @name SIGNAL_OVERRIDE - Signal Override Register */
 #define USBHSDCD_SIGNAL_OVERRIDE_PS_MASK         (0x3U)
 #define USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT        (0U)
-#define USBHSDCD_SIGNAL_OVERRIDE_PS(x)           (((uint32_t)(((uint32_t)(x)) << USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBHSDCD_SIGNAL_OVERRIDE_PS_MASK)
+#define USBHSDCD_SIGNAL_OVERRIDE_PS_SET(x)       (((uint32_t)(((uint32_t)(x)) << USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBHSDCD_SIGNAL_OVERRIDE_PS_MASK)
+#define USBHSDCD_SIGNAL_OVERRIDE_PS USBHSDCD_SIGNAL_OVERRIDE_PS_MASK
 
 /*! @name TIMER0 - TIMER0 register */
 #define USBHSDCD_TIMER0_TUNITCON_MASK            (0xFFFU)
 #define USBHSDCD_TIMER0_TUNITCON_SHIFT           (0U)
-#define USBHSDCD_TIMER0_TUNITCON(x)              (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TUNITCON_SHIFT)) & USBHSDCD_TIMER0_TUNITCON_MASK)
+#define USBHSDCD_TIMER0_TUNITCON_SET(x)          (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TUNITCON_SHIFT)) & USBHSDCD_TIMER0_TUNITCON_MASK)
+#define USBHSDCD_TIMER0_TUNITCON USBHSDCD_TIMER0_TUNITCON_MASK
 #define USBHSDCD_TIMER0_TSEQ_INIT_MASK           (0x3FF0000U)
 #define USBHSDCD_TIMER0_TSEQ_INIT_SHIFT          (16U)
-#define USBHSDCD_TIMER0_TSEQ_INIT(x)             (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBHSDCD_TIMER0_TSEQ_INIT_MASK)
+#define USBHSDCD_TIMER0_TSEQ_INIT_SET(x)         (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBHSDCD_TIMER0_TSEQ_INIT_MASK)
+#define USBHSDCD_TIMER0_TSEQ_INIT USBHSDCD_TIMER0_TSEQ_INIT_MASK
 
 /*! @name TIMER1 - TIMER1 register */
 #define USBHSDCD_TIMER1_TVDPSRC_ON_MASK          (0x3FFU)
 #define USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT         (0U)
-#define USBHSDCD_TIMER1_TVDPSRC_ON(x)            (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBHSDCD_TIMER1_TVDPSRC_ON_MASK)
+#define USBHSDCD_TIMER1_TVDPSRC_ON_SET(x)        (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBHSDCD_TIMER1_TVDPSRC_ON_MASK)
+#define USBHSDCD_TIMER1_TVDPSRC_ON USBHSDCD_TIMER1_TVDPSRC_ON_MASK
 #define USBHSDCD_TIMER1_TDCD_DBNC_MASK           (0x3FF0000U)
 #define USBHSDCD_TIMER1_TDCD_DBNC_SHIFT          (16U)
-#define USBHSDCD_TIMER1_TDCD_DBNC(x)             (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBHSDCD_TIMER1_TDCD_DBNC_MASK)
+#define USBHSDCD_TIMER1_TDCD_DBNC_SET(x)         (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBHSDCD_TIMER1_TDCD_DBNC_MASK)
+#define USBHSDCD_TIMER1_TDCD_DBNC USBHSDCD_TIMER1_TDCD_DBNC_MASK
 
 /*! @name TIMER2_BC11 - TIMER2_BC11 register */
 #define USBHSDCD_TIMER2_BC11_CHECK_DM_MASK       (0xFU)
 #define USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT      (0U)
-#define USBHSDCD_TIMER2_BC11_CHECK_DM(x)         (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBHSDCD_TIMER2_BC11_CHECK_DM_MASK)
+#define USBHSDCD_TIMER2_BC11_CHECK_DM_SET(x)     (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBHSDCD_TIMER2_BC11_CHECK_DM_MASK)
+#define USBHSDCD_TIMER2_BC11_CHECK_DM USBHSDCD_TIMER2_BC11_CHECK_DM_MASK
 #define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK    (0x3FF0000U)
 #define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT   (16U)
-#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON(x)      (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
+#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SET(x)  (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
+#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK
 
 /*! @name TIMER2_BC12 - TIMER2_BC12 register */
 #define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK     (0x3FFU)
 #define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT    (0U)
-#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON(x)       (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
+#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SET(x)   (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
+#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK
 #define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U)
 #define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
 #define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x)  (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
@@ -15707,7 +18968,7 @@ typedef struct {
 /** Peripheral USBHSDCD base address */
 #define USBHSDCD_BASE                            (0x400A3000u)
 /** Peripheral USBHSDCD base pointer */
-#define USBHSDCD                                 ((USBHSDCD_Type *)USBHSDCD_BASE)
+#define USBHSDCD                                 ((USBHSDCD_TypeDef *)USBHSDCD_BASE)
 /** Array initializer of USBHSDCD peripheral base addresses */
 #define USBHSDCD_BASE_ADDRS                      { USBHSDCD_BASE }
 /** Array initializer of USBHSDCD peripheral base pointers */
@@ -15790,7 +19051,7 @@ typedef struct {
   __IO uint32_t TRIM_OVERRIDE_EN_SET;              /**< USB PHY Trim Override Enable Register, offset: 0x134 */
   __IO uint32_t TRIM_OVERRIDE_EN_CLR;              /**< USB PHY Trim Override Enable Register, offset: 0x138 */
   __IO uint32_t TRIM_OVERRIDE_EN_TOG;              /**< USB PHY Trim Override Enable Register, offset: 0x13C */
-} USBPHY_Type;
+} USBPHY_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- USBPHY Register Masks
@@ -15804,382 +19065,495 @@ typedef struct {
 /*! @name PWD - USB PHY Power-Down Register */
 #define USBPHY_PWD_TXPWDFS_MASK                  (0x400U)
 #define USBPHY_PWD_TXPWDFS_SHIFT                 (10U)
-#define USBPHY_PWD_TXPWDFS(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK)
+#define USBPHY_PWD_TXPWDFS_SET(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK)
+#define USBPHY_PWD_TXPWDFS USBPHY_PWD_TXPWDFS_MASK
 #define USBPHY_PWD_TXPWDIBIAS_MASK               (0x800U)
 #define USBPHY_PWD_TXPWDIBIAS_SHIFT              (11U)
-#define USBPHY_PWD_TXPWDIBIAS(x)                 (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK)
+#define USBPHY_PWD_TXPWDIBIAS_SET(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK)
+#define USBPHY_PWD_TXPWDIBIAS USBPHY_PWD_TXPWDIBIAS_MASK
 #define USBPHY_PWD_TXPWDV2I_MASK                 (0x1000U)
 #define USBPHY_PWD_TXPWDV2I_SHIFT                (12U)
-#define USBPHY_PWD_TXPWDV2I(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK)
+#define USBPHY_PWD_TXPWDV2I_SET(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK)
+#define USBPHY_PWD_TXPWDV2I USBPHY_PWD_TXPWDV2I_MASK
 #define USBPHY_PWD_RXPWDENV_MASK                 (0x20000U)
 #define USBPHY_PWD_RXPWDENV_SHIFT                (17U)
-#define USBPHY_PWD_RXPWDENV(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK)
+#define USBPHY_PWD_RXPWDENV_SET(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK)
+#define USBPHY_PWD_RXPWDENV USBPHY_PWD_RXPWDENV_MASK
 #define USBPHY_PWD_RXPWD1PT1_MASK                (0x40000U)
 #define USBPHY_PWD_RXPWD1PT1_SHIFT               (18U)
-#define USBPHY_PWD_RXPWD1PT1(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK)
+#define USBPHY_PWD_RXPWD1PT1_SET(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK)
+#define USBPHY_PWD_RXPWD1PT1 USBPHY_PWD_RXPWD1PT1_MASK
 #define USBPHY_PWD_RXPWDDIFF_MASK                (0x80000U)
 #define USBPHY_PWD_RXPWDDIFF_SHIFT               (19U)
-#define USBPHY_PWD_RXPWDDIFF(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK)
+#define USBPHY_PWD_RXPWDDIFF_SET(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK)
+#define USBPHY_PWD_RXPWDDIFF USBPHY_PWD_RXPWDDIFF_MASK
 #define USBPHY_PWD_RXPWDRX_MASK                  (0x100000U)
 #define USBPHY_PWD_RXPWDRX_SHIFT                 (20U)
-#define USBPHY_PWD_RXPWDRX(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK)
+#define USBPHY_PWD_RXPWDRX_SET(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK)
+#define USBPHY_PWD_RXPWDRX USBPHY_PWD_RXPWDRX_MASK
 
 /*! @name PWD_SET - USB PHY Power-Down Register */
 #define USBPHY_PWD_SET_TXPWDFS_MASK              (0x400U)
 #define USBPHY_PWD_SET_TXPWDFS_SHIFT             (10U)
-#define USBPHY_PWD_SET_TXPWDFS(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK)
+#define USBPHY_PWD_SET_TXPWDFS_SET(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK)
+#define USBPHY_PWD_SET_TXPWDFS USBPHY_PWD_SET_TXPWDFS_MASK
 #define USBPHY_PWD_SET_TXPWDIBIAS_MASK           (0x800U)
 #define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT          (11U)
-#define USBPHY_PWD_SET_TXPWDIBIAS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK)
+#define USBPHY_PWD_SET_TXPWDIBIAS_SET(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK)
+#define USBPHY_PWD_SET_TXPWDIBIAS USBPHY_PWD_SET_TXPWDIBIAS_MASK
 #define USBPHY_PWD_SET_TXPWDV2I_MASK             (0x1000U)
 #define USBPHY_PWD_SET_TXPWDV2I_SHIFT            (12U)
-#define USBPHY_PWD_SET_TXPWDV2I(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK)
+#define USBPHY_PWD_SET_TXPWDV2I_SET(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK)
+#define USBPHY_PWD_SET_TXPWDV2I USBPHY_PWD_SET_TXPWDV2I_MASK
 #define USBPHY_PWD_SET_RXPWDENV_MASK             (0x20000U)
 #define USBPHY_PWD_SET_RXPWDENV_SHIFT            (17U)
-#define USBPHY_PWD_SET_RXPWDENV(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK)
+#define USBPHY_PWD_SET_RXPWDENV_SET(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK)
+#define USBPHY_PWD_SET_RXPWDENV USBPHY_PWD_SET_RXPWDENV_MASK
 #define USBPHY_PWD_SET_RXPWD1PT1_MASK            (0x40000U)
 #define USBPHY_PWD_SET_RXPWD1PT1_SHIFT           (18U)
-#define USBPHY_PWD_SET_RXPWD1PT1(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK)
+#define USBPHY_PWD_SET_RXPWD1PT1_SET(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK)
+#define USBPHY_PWD_SET_RXPWD1PT1 USBPHY_PWD_SET_RXPWD1PT1_MASK
 #define USBPHY_PWD_SET_RXPWDDIFF_MASK            (0x80000U)
 #define USBPHY_PWD_SET_RXPWDDIFF_SHIFT           (19U)
-#define USBPHY_PWD_SET_RXPWDDIFF(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK)
+#define USBPHY_PWD_SET_RXPWDDIFF_SET(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK)
+#define USBPHY_PWD_SET_RXPWDDIFF USBPHY_PWD_SET_RXPWDDIFF_MASK
 #define USBPHY_PWD_SET_RXPWDRX_MASK              (0x100000U)
 #define USBPHY_PWD_SET_RXPWDRX_SHIFT             (20U)
-#define USBPHY_PWD_SET_RXPWDRX(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK)
+#define USBPHY_PWD_SET_RXPWDRX_SET(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK)
+#define USBPHY_PWD_SET_RXPWDRX USBPHY_PWD_SET_RXPWDRX_MASK
 
 /*! @name PWD_CLR - USB PHY Power-Down Register */
 #define USBPHY_PWD_CLR_TXPWDFS_MASK              (0x400U)
 #define USBPHY_PWD_CLR_TXPWDFS_SHIFT             (10U)
-#define USBPHY_PWD_CLR_TXPWDFS(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK)
+#define USBPHY_PWD_CLR_TXPWDFS_SET(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK)
+#define USBPHY_PWD_CLR_TXPWDFS USBPHY_PWD_CLR_TXPWDFS_MASK
 #define USBPHY_PWD_CLR_TXPWDIBIAS_MASK           (0x800U)
 #define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT          (11U)
-#define USBPHY_PWD_CLR_TXPWDIBIAS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK)
+#define USBPHY_PWD_CLR_TXPWDIBIAS_SET(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK)
+#define USBPHY_PWD_CLR_TXPWDIBIAS USBPHY_PWD_CLR_TXPWDIBIAS_MASK
 #define USBPHY_PWD_CLR_TXPWDV2I_MASK             (0x1000U)
 #define USBPHY_PWD_CLR_TXPWDV2I_SHIFT            (12U)
-#define USBPHY_PWD_CLR_TXPWDV2I(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK)
+#define USBPHY_PWD_CLR_TXPWDV2I_SET(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK)
+#define USBPHY_PWD_CLR_TXPWDV2I USBPHY_PWD_CLR_TXPWDV2I_MASK
 #define USBPHY_PWD_CLR_RXPWDENV_MASK             (0x20000U)
 #define USBPHY_PWD_CLR_RXPWDENV_SHIFT            (17U)
-#define USBPHY_PWD_CLR_RXPWDENV(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK)
+#define USBPHY_PWD_CLR_RXPWDENV_SET(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK)
+#define USBPHY_PWD_CLR_RXPWDENV USBPHY_PWD_CLR_RXPWDENV_MASK
 #define USBPHY_PWD_CLR_RXPWD1PT1_MASK            (0x40000U)
 #define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT           (18U)
-#define USBPHY_PWD_CLR_RXPWD1PT1(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK)
+#define USBPHY_PWD_CLR_RXPWD1PT1_SET(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK)
+#define USBPHY_PWD_CLR_RXPWD1PT1 USBPHY_PWD_CLR_RXPWD1PT1_MASK
 #define USBPHY_PWD_CLR_RXPWDDIFF_MASK            (0x80000U)
 #define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT           (19U)
-#define USBPHY_PWD_CLR_RXPWDDIFF(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK)
+#define USBPHY_PWD_CLR_RXPWDDIFF_SET(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK)
+#define USBPHY_PWD_CLR_RXPWDDIFF USBPHY_PWD_CLR_RXPWDDIFF_MASK
 #define USBPHY_PWD_CLR_RXPWDRX_MASK              (0x100000U)
 #define USBPHY_PWD_CLR_RXPWDRX_SHIFT             (20U)
-#define USBPHY_PWD_CLR_RXPWDRX(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK)
+#define USBPHY_PWD_CLR_RXPWDRX_SET(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK)
+#define USBPHY_PWD_CLR_RXPWDRX USBPHY_PWD_CLR_RXPWDRX_MASK
 
 /*! @name PWD_TOG - USB PHY Power-Down Register */
 #define USBPHY_PWD_TOG_TXPWDFS_MASK              (0x400U)
 #define USBPHY_PWD_TOG_TXPWDFS_SHIFT             (10U)
-#define USBPHY_PWD_TOG_TXPWDFS(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK)
+#define USBPHY_PWD_TOG_TXPWDFS_SET(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK)
+#define USBPHY_PWD_TOG_TXPWDFS USBPHY_PWD_TOG_TXPWDFS_MASK
 #define USBPHY_PWD_TOG_TXPWDIBIAS_MASK           (0x800U)
 #define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT          (11U)
-#define USBPHY_PWD_TOG_TXPWDIBIAS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK)
+#define USBPHY_PWD_TOG_TXPWDIBIAS_SET(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK)
+#define USBPHY_PWD_TOG_TXPWDIBIAS USBPHY_PWD_TOG_TXPWDIBIAS_MASK
 #define USBPHY_PWD_TOG_TXPWDV2I_MASK             (0x1000U)
 #define USBPHY_PWD_TOG_TXPWDV2I_SHIFT            (12U)
-#define USBPHY_PWD_TOG_TXPWDV2I(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK)
+#define USBPHY_PWD_TOG_TXPWDV2I_SET(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK)
+#define USBPHY_PWD_TOG_TXPWDV2I USBPHY_PWD_TOG_TXPWDV2I_MASK
 #define USBPHY_PWD_TOG_RXPWDENV_MASK             (0x20000U)
 #define USBPHY_PWD_TOG_RXPWDENV_SHIFT            (17U)
-#define USBPHY_PWD_TOG_RXPWDENV(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK)
+#define USBPHY_PWD_TOG_RXPWDENV_SET(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK)
+#define USBPHY_PWD_TOG_RXPWDENV USBPHY_PWD_TOG_RXPWDENV_MASK
 #define USBPHY_PWD_TOG_RXPWD1PT1_MASK            (0x40000U)
 #define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT           (18U)
-#define USBPHY_PWD_TOG_RXPWD1PT1(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK)
+#define USBPHY_PWD_TOG_RXPWD1PT1_SET(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK)
+#define USBPHY_PWD_TOG_RXPWD1PT1 USBPHY_PWD_TOG_RXPWD1PT1_MASK
 #define USBPHY_PWD_TOG_RXPWDDIFF_MASK            (0x80000U)
 #define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT           (19U)
-#define USBPHY_PWD_TOG_RXPWDDIFF(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK)
+#define USBPHY_PWD_TOG_RXPWDDIFF_SET(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK)
+#define USBPHY_PWD_TOG_RXPWDDIFF USBPHY_PWD_TOG_RXPWDDIFF_MASK
 #define USBPHY_PWD_TOG_RXPWDRX_MASK              (0x100000U)
 #define USBPHY_PWD_TOG_RXPWDRX_SHIFT             (20U)
-#define USBPHY_PWD_TOG_RXPWDRX(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK)
+#define USBPHY_PWD_TOG_RXPWDRX_SET(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK)
+#define USBPHY_PWD_TOG_RXPWDRX USBPHY_PWD_TOG_RXPWDRX_MASK
 
 /*! @name TX - USB PHY Transmitter Control Register */
 #define USBPHY_TX_D_CAL_MASK                     (0xFU)
 #define USBPHY_TX_D_CAL_SHIFT                    (0U)
-#define USBPHY_TX_D_CAL(x)                       (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK)
+#define USBPHY_TX_D_CAL_SET(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK)
+#define USBPHY_TX_D_CAL USBPHY_TX_D_CAL_MASK
 #define USBPHY_TX_TXCAL45DM_MASK                 (0xF00U)
 #define USBPHY_TX_TXCAL45DM_SHIFT                (8U)
-#define USBPHY_TX_TXCAL45DM(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DM_SHIFT)) & USBPHY_TX_TXCAL45DM_MASK)
+#define USBPHY_TX_TXCAL45DM_SET(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DM_SHIFT)) & USBPHY_TX_TXCAL45DM_MASK)
+#define USBPHY_TX_TXCAL45DM USBPHY_TX_TXCAL45DM_MASK
 #define USBPHY_TX_TXCAL45DP_MASK                 (0xF0000U)
 #define USBPHY_TX_TXCAL45DP_SHIFT                (16U)
-#define USBPHY_TX_TXCAL45DP(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK)
+#define USBPHY_TX_TXCAL45DP_SET(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK)
+#define USBPHY_TX_TXCAL45DP USBPHY_TX_TXCAL45DP_MASK
 #define USBPHY_TX_USBPHY_TX_EDGECTRL_MASK        (0x1C000000U)
 #define USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT       (26U)
-#define USBPHY_TX_USBPHY_TX_EDGECTRL(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_USBPHY_TX_EDGECTRL_MASK)
+#define USBPHY_TX_USBPHY_TX_EDGECTRL_SET(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_USBPHY_TX_EDGECTRL_MASK)
+#define USBPHY_TX_USBPHY_TX_EDGECTRL USBPHY_TX_USBPHY_TX_EDGECTRL_MASK
 
 /*! @name TX_SET - USB PHY Transmitter Control Register */
 #define USBPHY_TX_SET_D_CAL_MASK                 (0xFU)
 #define USBPHY_TX_SET_D_CAL_SHIFT                (0U)
-#define USBPHY_TX_SET_D_CAL(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK)
+#define USBPHY_TX_SET_D_CAL_SET(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK)
+#define USBPHY_TX_SET_D_CAL USBPHY_TX_SET_D_CAL_MASK
 #define USBPHY_TX_SET_TXCAL45DM_MASK             (0xF00U)
 #define USBPHY_TX_SET_TXCAL45DM_SHIFT            (8U)
-#define USBPHY_TX_SET_TXCAL45DM(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DM_SHIFT)) & USBPHY_TX_SET_TXCAL45DM_MASK)
+#define USBPHY_TX_SET_TXCAL45DM_SET(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DM_SHIFT)) & USBPHY_TX_SET_TXCAL45DM_MASK)
+#define USBPHY_TX_SET_TXCAL45DM USBPHY_TX_SET_TXCAL45DM_MASK
 #define USBPHY_TX_SET_TXCAL45DP_MASK             (0xF0000U)
 #define USBPHY_TX_SET_TXCAL45DP_SHIFT            (16U)
-#define USBPHY_TX_SET_TXCAL45DP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK)
+#define USBPHY_TX_SET_TXCAL45DP_SET(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK)
+#define USBPHY_TX_SET_TXCAL45DP USBPHY_TX_SET_TXCAL45DP_MASK
 #define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK    (0x1C000000U)
 #define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT   (26U)
-#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK)
+#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SET(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK)
+#define USBPHY_TX_SET_USBPHY_TX_EDGECTRL USBPHY_TX_SET_USBPHY_TX_EDGECTRL_MASK
 
 /*! @name TX_CLR - USB PHY Transmitter Control Register */
 #define USBPHY_TX_CLR_D_CAL_MASK                 (0xFU)
 #define USBPHY_TX_CLR_D_CAL_SHIFT                (0U)
-#define USBPHY_TX_CLR_D_CAL(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK)
+#define USBPHY_TX_CLR_D_CAL_SET(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK)
+#define USBPHY_TX_CLR_D_CAL USBPHY_TX_CLR_D_CAL_MASK
 #define USBPHY_TX_CLR_TXCAL45DM_MASK             (0xF00U)
 #define USBPHY_TX_CLR_TXCAL45DM_SHIFT            (8U)
-#define USBPHY_TX_CLR_TXCAL45DM(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DM_SHIFT)) & USBPHY_TX_CLR_TXCAL45DM_MASK)
+#define USBPHY_TX_CLR_TXCAL45DM_SET(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DM_SHIFT)) & USBPHY_TX_CLR_TXCAL45DM_MASK)
+#define USBPHY_TX_CLR_TXCAL45DM USBPHY_TX_CLR_TXCAL45DM_MASK
 #define USBPHY_TX_CLR_TXCAL45DP_MASK             (0xF0000U)
 #define USBPHY_TX_CLR_TXCAL45DP_SHIFT            (16U)
-#define USBPHY_TX_CLR_TXCAL45DP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK)
+#define USBPHY_TX_CLR_TXCAL45DP_SET(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK)
+#define USBPHY_TX_CLR_TXCAL45DP USBPHY_TX_CLR_TXCAL45DP_MASK
 #define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK    (0x1C000000U)
 #define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT   (26U)
-#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK)
+#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SET(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK)
+#define USBPHY_TX_CLR_USBPHY_TX_EDGECTRL USBPHY_TX_CLR_USBPHY_TX_EDGECTRL_MASK
 
 /*! @name TX_TOG - USB PHY Transmitter Control Register */
 #define USBPHY_TX_TOG_D_CAL_MASK                 (0xFU)
 #define USBPHY_TX_TOG_D_CAL_SHIFT                (0U)
-#define USBPHY_TX_TOG_D_CAL(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK)
+#define USBPHY_TX_TOG_D_CAL_SET(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK)
+#define USBPHY_TX_TOG_D_CAL USBPHY_TX_TOG_D_CAL_MASK
 #define USBPHY_TX_TOG_TXCAL45DM_MASK             (0xF00U)
 #define USBPHY_TX_TOG_TXCAL45DM_SHIFT            (8U)
-#define USBPHY_TX_TOG_TXCAL45DM(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DM_SHIFT)) & USBPHY_TX_TOG_TXCAL45DM_MASK)
+#define USBPHY_TX_TOG_TXCAL45DM_SET(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DM_SHIFT)) & USBPHY_TX_TOG_TXCAL45DM_MASK)
+#define USBPHY_TX_TOG_TXCAL45DM USBPHY_TX_TOG_TXCAL45DM_MASK
 #define USBPHY_TX_TOG_TXCAL45DP_MASK             (0xF0000U)
 #define USBPHY_TX_TOG_TXCAL45DP_SHIFT            (16U)
-#define USBPHY_TX_TOG_TXCAL45DP(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK)
+#define USBPHY_TX_TOG_TXCAL45DP_SET(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK)
+#define USBPHY_TX_TOG_TXCAL45DP USBPHY_TX_TOG_TXCAL45DP_MASK
 #define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK    (0x1C000000U)
 #define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT   (26U)
-#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK)
+#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SET(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_SHIFT)) & USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK)
+#define USBPHY_TX_TOG_USBPHY_TX_EDGECTRL USBPHY_TX_TOG_USBPHY_TX_EDGECTRL_MASK
 
 /*! @name RX - USB PHY Receiver Control Register */
 #define USBPHY_RX_ENVADJ_MASK                    (0x7U)
 #define USBPHY_RX_ENVADJ_SHIFT                   (0U)
-#define USBPHY_RX_ENVADJ(x)                      (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK)
+#define USBPHY_RX_ENVADJ_SET(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK)
+#define USBPHY_RX_ENVADJ USBPHY_RX_ENVADJ_MASK
 #define USBPHY_RX_DISCONADJ_MASK                 (0x70U)
 #define USBPHY_RX_DISCONADJ_SHIFT                (4U)
-#define USBPHY_RX_DISCONADJ(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK)
+#define USBPHY_RX_DISCONADJ_SET(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK)
+#define USBPHY_RX_DISCONADJ USBPHY_RX_DISCONADJ_MASK
 #define USBPHY_RX_RXDBYPASS_MASK                 (0x400000U)
 #define USBPHY_RX_RXDBYPASS_SHIFT                (22U)
-#define USBPHY_RX_RXDBYPASS(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK)
+#define USBPHY_RX_RXDBYPASS_SET(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK)
+#define USBPHY_RX_RXDBYPASS USBPHY_RX_RXDBYPASS_MASK
 
 /*! @name RX_SET - USB PHY Receiver Control Register */
 #define USBPHY_RX_SET_ENVADJ_MASK                (0x7U)
 #define USBPHY_RX_SET_ENVADJ_SHIFT               (0U)
-#define USBPHY_RX_SET_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK)
+#define USBPHY_RX_SET_ENVADJ_SET(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK)
+#define USBPHY_RX_SET_ENVADJ USBPHY_RX_SET_ENVADJ_MASK
 #define USBPHY_RX_SET_DISCONADJ_MASK             (0x70U)
 #define USBPHY_RX_SET_DISCONADJ_SHIFT            (4U)
-#define USBPHY_RX_SET_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK)
+#define USBPHY_RX_SET_DISCONADJ_SET(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK)
+#define USBPHY_RX_SET_DISCONADJ USBPHY_RX_SET_DISCONADJ_MASK
 #define USBPHY_RX_SET_RXDBYPASS_MASK             (0x400000U)
 #define USBPHY_RX_SET_RXDBYPASS_SHIFT            (22U)
-#define USBPHY_RX_SET_RXDBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK)
+#define USBPHY_RX_SET_RXDBYPASS_SET(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK)
+#define USBPHY_RX_SET_RXDBYPASS USBPHY_RX_SET_RXDBYPASS_MASK
 
 /*! @name RX_CLR - USB PHY Receiver Control Register */
 #define USBPHY_RX_CLR_ENVADJ_MASK                (0x7U)
 #define USBPHY_RX_CLR_ENVADJ_SHIFT               (0U)
-#define USBPHY_RX_CLR_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK)
+#define USBPHY_RX_CLR_ENVADJ_SET(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK)
+#define USBPHY_RX_CLR_ENVADJ USBPHY_RX_CLR_ENVADJ_MASK
 #define USBPHY_RX_CLR_DISCONADJ_MASK             (0x70U)
 #define USBPHY_RX_CLR_DISCONADJ_SHIFT            (4U)
-#define USBPHY_RX_CLR_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK)
+#define USBPHY_RX_CLR_DISCONADJ_SET(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK)
+#define USBPHY_RX_CLR_DISCONADJ USBPHY_RX_CLR_DISCONADJ_MASK
 #define USBPHY_RX_CLR_RXDBYPASS_MASK             (0x400000U)
 #define USBPHY_RX_CLR_RXDBYPASS_SHIFT            (22U)
-#define USBPHY_RX_CLR_RXDBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK)
+#define USBPHY_RX_CLR_RXDBYPASS_SET(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK)
+#define USBPHY_RX_CLR_RXDBYPASS USBPHY_RX_CLR_RXDBYPASS_MASK
 
 /*! @name RX_TOG - USB PHY Receiver Control Register */
 #define USBPHY_RX_TOG_ENVADJ_MASK                (0x7U)
 #define USBPHY_RX_TOG_ENVADJ_SHIFT               (0U)
-#define USBPHY_RX_TOG_ENVADJ(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK)
+#define USBPHY_RX_TOG_ENVADJ_SET(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK)
+#define USBPHY_RX_TOG_ENVADJ USBPHY_RX_TOG_ENVADJ_MASK
 #define USBPHY_RX_TOG_DISCONADJ_MASK             (0x70U)
 #define USBPHY_RX_TOG_DISCONADJ_SHIFT            (4U)
-#define USBPHY_RX_TOG_DISCONADJ(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK)
+#define USBPHY_RX_TOG_DISCONADJ_SET(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK)
+#define USBPHY_RX_TOG_DISCONADJ USBPHY_RX_TOG_DISCONADJ_MASK
 #define USBPHY_RX_TOG_RXDBYPASS_MASK             (0x400000U)
 #define USBPHY_RX_TOG_RXDBYPASS_SHIFT            (22U)
-#define USBPHY_RX_TOG_RXDBYPASS(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK)
+#define USBPHY_RX_TOG_RXDBYPASS_SET(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK)
+#define USBPHY_RX_TOG_RXDBYPASS USBPHY_RX_TOG_RXDBYPASS_MASK
 
 /*! @name CTRL - USB PHY General Control Register */
 #define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK      (0x2U)
 #define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT     (1U)
-#define USBPHY_CTRL_ENHOSTDISCONDETECT(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK)
+#define USBPHY_CTRL_ENHOSTDISCONDETECT_SET(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK)
+#define USBPHY_CTRL_ENHOSTDISCONDETECT USBPHY_CTRL_ENHOSTDISCONDETECT_MASK
 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK    (0x8U)
 #define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT   (3U)
-#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK)
+#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SET(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK)
+#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK
 #define USBPHY_CTRL_ENDEVPLUGINDET_MASK          (0x10U)
 #define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT         (4U)
-#define USBPHY_CTRL_ENDEVPLUGINDET(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDET_MASK)
+#define USBPHY_CTRL_ENDEVPLUGINDET_SET(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDET_MASK)
+#define USBPHY_CTRL_ENDEVPLUGINDET USBPHY_CTRL_ENDEVPLUGINDET_MASK
 #define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK           (0x1000U)
 #define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT          (12U)
-#define USBPHY_CTRL_DEVPLUGIN_IRQ(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK)
+#define USBPHY_CTRL_DEVPLUGIN_IRQ_SET(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK)
+#define USBPHY_CTRL_DEVPLUGIN_IRQ USBPHY_CTRL_DEVPLUGIN_IRQ_MASK
 #define USBPHY_CTRL_ENUTMILEVEL2_MASK            (0x4000U)
 #define USBPHY_CTRL_ENUTMILEVEL2_SHIFT           (14U)
-#define USBPHY_CTRL_ENUTMILEVEL2(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK)
+#define USBPHY_CTRL_ENUTMILEVEL2_SET(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK)
+#define USBPHY_CTRL_ENUTMILEVEL2 USBPHY_CTRL_ENUTMILEVEL2_MASK
 #define USBPHY_CTRL_ENUTMILEVEL3_MASK            (0x8000U)
 #define USBPHY_CTRL_ENUTMILEVEL3_SHIFT           (15U)
-#define USBPHY_CTRL_ENUTMILEVEL3(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK)
+#define USBPHY_CTRL_ENUTMILEVEL3_SET(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK)
+#define USBPHY_CTRL_ENUTMILEVEL3 USBPHY_CTRL_ENUTMILEVEL3_MASK
 #define USBPHY_CTRL_AUTORESUME_EN_MASK           (0x40000U)
 #define USBPHY_CTRL_AUTORESUME_EN_SHIFT          (18U)
-#define USBPHY_CTRL_AUTORESUME_EN(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK)
+#define USBPHY_CTRL_AUTORESUME_EN_SET(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK)
+#define USBPHY_CTRL_AUTORESUME_EN USBPHY_CTRL_AUTORESUME_EN_MASK
 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK       (0x80000U)
 #define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT      (19U)
-#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK)
+#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SET(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK)
+#define USBPHY_CTRL_ENAUTOCLR_CLKGATE USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK
 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK       (0x100000U)
 #define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT      (20U)
-#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK)
+#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SET(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK)
+#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK
 #define USBPHY_CTRL_FSDLL_RST_EN_MASK            (0x1000000U)
 #define USBPHY_CTRL_FSDLL_RST_EN_SHIFT           (24U)
-#define USBPHY_CTRL_FSDLL_RST_EN(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK)
+#define USBPHY_CTRL_FSDLL_RST_EN_SET(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK)
+#define USBPHY_CTRL_FSDLL_RST_EN USBPHY_CTRL_FSDLL_RST_EN_MASK
 #define USBPHY_CTRL_OTG_ID_VALUE_MASK            (0x8000000U)
 #define USBPHY_CTRL_OTG_ID_VALUE_SHIFT           (27U)
-#define USBPHY_CTRL_OTG_ID_VALUE(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK)
+#define USBPHY_CTRL_OTG_ID_VALUE_SET(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK)
+#define USBPHY_CTRL_OTG_ID_VALUE USBPHY_CTRL_OTG_ID_VALUE_MASK
 #define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK       (0x10000000U)
 #define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT      (28U)
-#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK)
+#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SET(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK)
+#define USBPHY_CTRL_HOST_FORCE_LS_SE0 USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK
 #define USBPHY_CTRL_UTMI_SUSPENDM_MASK           (0x20000000U)
 #define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT          (29U)
-#define USBPHY_CTRL_UTMI_SUSPENDM(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK)
+#define USBPHY_CTRL_UTMI_SUSPENDM_SET(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK)
+#define USBPHY_CTRL_UTMI_SUSPENDM USBPHY_CTRL_UTMI_SUSPENDM_MASK
 #define USBPHY_CTRL_CLKGATE_MASK                 (0x40000000U)
 #define USBPHY_CTRL_CLKGATE_SHIFT                (30U)
-#define USBPHY_CTRL_CLKGATE(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK)
+#define USBPHY_CTRL_CLKGATE_SET(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK)
+#define USBPHY_CTRL_CLKGATE USBPHY_CTRL_CLKGATE_MASK
 #define USBPHY_CTRL_SFTRST_MASK                  (0x80000000U)
 #define USBPHY_CTRL_SFTRST_SHIFT                 (31U)
-#define USBPHY_CTRL_SFTRST(x)                    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK)
+#define USBPHY_CTRL_SFTRST_SET(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK)
+#define USBPHY_CTRL_SFTRST USBPHY_CTRL_SFTRST_MASK
 
 /*! @name CTRL_SET - USB PHY General Control Register */
 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK  (0x2U)
 #define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U)
-#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK)
+#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SET(x)(((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK)
+#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK
 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U)
 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U)
 #define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK)
 #define USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK      (0x10U)
 #define USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT     (4U)
-#define USBPHY_CTRL_SET_ENDEVPLUGINDET(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK)
+#define USBPHY_CTRL_SET_ENDEVPLUGINDET_SET(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK)
+#define USBPHY_CTRL_SET_ENDEVPLUGINDET USBPHY_CTRL_SET_ENDEVPLUGINDET_MASK
 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK       (0x1000U)
 #define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT      (12U)
-#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK)
+#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SET(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK)
+#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK
 #define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK        (0x4000U)
 #define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT       (14U)
-#define USBPHY_CTRL_SET_ENUTMILEVEL2(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK)
+#define USBPHY_CTRL_SET_ENUTMILEVEL2_SET(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK)
+#define USBPHY_CTRL_SET_ENUTMILEVEL2 USBPHY_CTRL_SET_ENUTMILEVEL2_MASK
 #define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK        (0x8000U)
 #define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT       (15U)
-#define USBPHY_CTRL_SET_ENUTMILEVEL3(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK)
+#define USBPHY_CTRL_SET_ENUTMILEVEL3_SET(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK)
+#define USBPHY_CTRL_SET_ENUTMILEVEL3 USBPHY_CTRL_SET_ENUTMILEVEL3_MASK
 #define USBPHY_CTRL_SET_AUTORESUME_EN_MASK       (0x40000U)
 #define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT      (18U)
-#define USBPHY_CTRL_SET_AUTORESUME_EN(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK)
+#define USBPHY_CTRL_SET_AUTORESUME_EN_SET(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK)
+#define USBPHY_CTRL_SET_AUTORESUME_EN USBPHY_CTRL_SET_AUTORESUME_EN_MASK
 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
 #define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT  (19U)
-#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK)
+#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK)
+#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK
 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
 #define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT  (20U)
-#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK)
+#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK)
+#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK
 #define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK        (0x1000000U)
 #define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT       (24U)
-#define USBPHY_CTRL_SET_FSDLL_RST_EN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK)
+#define USBPHY_CTRL_SET_FSDLL_RST_EN_SET(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK)
+#define USBPHY_CTRL_SET_FSDLL_RST_EN USBPHY_CTRL_SET_FSDLL_RST_EN_MASK
 #define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK        (0x8000000U)
 #define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT       (27U)
-#define USBPHY_CTRL_SET_OTG_ID_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK)
+#define USBPHY_CTRL_SET_OTG_ID_VALUE_SET(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK)
+#define USBPHY_CTRL_SET_OTG_ID_VALUE USBPHY_CTRL_SET_OTG_ID_VALUE_MASK
 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK   (0x10000000U)
 #define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT  (28U)
-#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK)
+#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK)
+#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0 USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK
 #define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK       (0x20000000U)
 #define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT      (29U)
-#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK)
+#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SET(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK)
+#define USBPHY_CTRL_SET_UTMI_SUSPENDM USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK
 #define USBPHY_CTRL_SET_CLKGATE_MASK             (0x40000000U)
 #define USBPHY_CTRL_SET_CLKGATE_SHIFT            (30U)
-#define USBPHY_CTRL_SET_CLKGATE(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK)
+#define USBPHY_CTRL_SET_CLKGATE_SET(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK)
+#define USBPHY_CTRL_SET_CLKGATE USBPHY_CTRL_SET_CLKGATE_MASK
 #define USBPHY_CTRL_SET_SFTRST_MASK              (0x80000000U)
 #define USBPHY_CTRL_SET_SFTRST_SHIFT             (31U)
-#define USBPHY_CTRL_SET_SFTRST(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK)
+#define USBPHY_CTRL_SET_SFTRST_SET(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK)
+#define USBPHY_CTRL_SET_SFTRST USBPHY_CTRL_SET_SFTRST_MASK
 
 /*! @name CTRL_CLR - USB PHY General Control Register */
 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK  (0x2U)
 #define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U)
-#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK)
+#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SET(x)(((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK)
+#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK
 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U)
 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U)
 #define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK)
 #define USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK      (0x10U)
 #define USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT     (4U)
-#define USBPHY_CTRL_CLR_ENDEVPLUGINDET(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK)
+#define USBPHY_CTRL_CLR_ENDEVPLUGINDET_SET(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK)
+#define USBPHY_CTRL_CLR_ENDEVPLUGINDET USBPHY_CTRL_CLR_ENDEVPLUGINDET_MASK
 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK       (0x1000U)
 #define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT      (12U)
-#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK)
+#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SET(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK)
+#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK
 #define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK        (0x4000U)
 #define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT       (14U)
-#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK)
+#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SET(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK)
+#define USBPHY_CTRL_CLR_ENUTMILEVEL2 USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK
 #define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK        (0x8000U)
 #define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT       (15U)
-#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK)
+#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SET(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK)
+#define USBPHY_CTRL_CLR_ENUTMILEVEL3 USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK
 #define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK       (0x40000U)
 #define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT      (18U)
-#define USBPHY_CTRL_CLR_AUTORESUME_EN(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK)
+#define USBPHY_CTRL_CLR_AUTORESUME_EN_SET(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK)
+#define USBPHY_CTRL_CLR_AUTORESUME_EN USBPHY_CTRL_CLR_AUTORESUME_EN_MASK
 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
 #define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT  (19U)
-#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK)
+#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK)
+#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK
 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
 #define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT  (20U)
-#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK)
+#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK)
+#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK
 #define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK        (0x1000000U)
 #define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT       (24U)
-#define USBPHY_CTRL_CLR_FSDLL_RST_EN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK)
+#define USBPHY_CTRL_CLR_FSDLL_RST_EN_SET(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK)
+#define USBPHY_CTRL_CLR_FSDLL_RST_EN USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK
 #define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK        (0x8000000U)
 #define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT       (27U)
-#define USBPHY_CTRL_CLR_OTG_ID_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK)
+#define USBPHY_CTRL_CLR_OTG_ID_VALUE_SET(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK)
+#define USBPHY_CTRL_CLR_OTG_ID_VALUE USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK
 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK   (0x10000000U)
 #define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT  (28U)
-#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK)
+#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK)
+#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0 USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK
 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK       (0x20000000U)
 #define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT      (29U)
-#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK)
+#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SET(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK)
+#define USBPHY_CTRL_CLR_UTMI_SUSPENDM USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK
 #define USBPHY_CTRL_CLR_CLKGATE_MASK             (0x40000000U)
 #define USBPHY_CTRL_CLR_CLKGATE_SHIFT            (30U)
-#define USBPHY_CTRL_CLR_CLKGATE(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK)
+#define USBPHY_CTRL_CLR_CLKGATE_SET(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK)
+#define USBPHY_CTRL_CLR_CLKGATE USBPHY_CTRL_CLR_CLKGATE_MASK
 #define USBPHY_CTRL_CLR_SFTRST_MASK              (0x80000000U)
 #define USBPHY_CTRL_CLR_SFTRST_SHIFT             (31U)
-#define USBPHY_CTRL_CLR_SFTRST(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK)
+#define USBPHY_CTRL_CLR_SFTRST_SET(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK)
+#define USBPHY_CTRL_CLR_SFTRST USBPHY_CTRL_CLR_SFTRST_MASK
 
 /*! @name CTRL_TOG - USB PHY General Control Register */
 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK  (0x2U)
 #define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U)
-#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK)
+#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SET(x)(((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK)
+#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK
 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U)
 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U)
 #define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK)
 #define USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK      (0x10U)
 #define USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT     (4U)
-#define USBPHY_CTRL_TOG_ENDEVPLUGINDET(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK)
+#define USBPHY_CTRL_TOG_ENDEVPLUGINDET_SET(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDET_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK)
+#define USBPHY_CTRL_TOG_ENDEVPLUGINDET USBPHY_CTRL_TOG_ENDEVPLUGINDET_MASK
 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK       (0x1000U)
 #define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT      (12U)
-#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK)
+#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SET(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK)
+#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK
 #define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK        (0x4000U)
 #define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT       (14U)
-#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK)
+#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SET(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK)
+#define USBPHY_CTRL_TOG_ENUTMILEVEL2 USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK
 #define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK        (0x8000U)
 #define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT       (15U)
-#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK)
+#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SET(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK)
+#define USBPHY_CTRL_TOG_ENUTMILEVEL3 USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK
 #define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK       (0x40000U)
 #define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT      (18U)
-#define USBPHY_CTRL_TOG_AUTORESUME_EN(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK)
+#define USBPHY_CTRL_TOG_AUTORESUME_EN_SET(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK)
+#define USBPHY_CTRL_TOG_AUTORESUME_EN USBPHY_CTRL_TOG_AUTORESUME_EN_MASK
 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK   (0x80000U)
 #define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT  (19U)
-#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK)
+#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK)
+#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK
 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK   (0x100000U)
 #define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT  (20U)
-#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK)
+#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK)
+#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK
 #define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK        (0x1000000U)
 #define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT       (24U)
-#define USBPHY_CTRL_TOG_FSDLL_RST_EN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK)
+#define USBPHY_CTRL_TOG_FSDLL_RST_EN_SET(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK)
+#define USBPHY_CTRL_TOG_FSDLL_RST_EN USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK
 #define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK        (0x8000000U)
 #define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT       (27U)
-#define USBPHY_CTRL_TOG_OTG_ID_VALUE(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK)
+#define USBPHY_CTRL_TOG_OTG_ID_VALUE_SET(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK)
+#define USBPHY_CTRL_TOG_OTG_ID_VALUE USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK
 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK   (0x10000000U)
 #define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT  (28U)
-#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK)
+#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK)
+#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0 USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK
 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK       (0x20000000U)
 #define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT      (29U)
-#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK)
+#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SET(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK)
+#define USBPHY_CTRL_TOG_UTMI_SUSPENDM USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK
 #define USBPHY_CTRL_TOG_CLKGATE_MASK             (0x40000000U)
 #define USBPHY_CTRL_TOG_CLKGATE_SHIFT            (30U)
-#define USBPHY_CTRL_TOG_CLKGATE(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK)
+#define USBPHY_CTRL_TOG_CLKGATE_SET(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK)
+#define USBPHY_CTRL_TOG_CLKGATE USBPHY_CTRL_TOG_CLKGATE_MASK
 #define USBPHY_CTRL_TOG_SFTRST_MASK              (0x80000000U)
 #define USBPHY_CTRL_TOG_SFTRST_SHIFT             (31U)
-#define USBPHY_CTRL_TOG_SFTRST(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK)
+#define USBPHY_CTRL_TOG_SFTRST_SET(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK)
+#define USBPHY_CTRL_TOG_SFTRST USBPHY_CTRL_TOG_SFTRST_MASK
 
 /*! @name STATUS - USB PHY Status Register */
 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U)
@@ -16187,153 +19561,194 @@ typedef struct {
 #define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK)
 #define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK      (0x40U)
 #define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT     (6U)
-#define USBPHY_STATUS_DEVPLUGIN_STATUS(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK)
+#define USBPHY_STATUS_DEVPLUGIN_STATUS_SET(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK)
+#define USBPHY_STATUS_DEVPLUGIN_STATUS USBPHY_STATUS_DEVPLUGIN_STATUS_MASK
 #define USBPHY_STATUS_OTGID_STATUS_MASK          (0x100U)
 #define USBPHY_STATUS_OTGID_STATUS_SHIFT         (8U)
-#define USBPHY_STATUS_OTGID_STATUS(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK)
+#define USBPHY_STATUS_OTGID_STATUS_SET(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK)
+#define USBPHY_STATUS_OTGID_STATUS USBPHY_STATUS_OTGID_STATUS_MASK
 #define USBPHY_STATUS_RESUME_STATUS_MASK         (0x400U)
 #define USBPHY_STATUS_RESUME_STATUS_SHIFT        (10U)
-#define USBPHY_STATUS_RESUME_STATUS(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK)
+#define USBPHY_STATUS_RESUME_STATUS_SET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK)
+#define USBPHY_STATUS_RESUME_STATUS USBPHY_STATUS_RESUME_STATUS_MASK
 
 /*! @name DEBUG - USB PHY Debug Register */
 #define USBPHY_DEBUG_OTGIDPIOLOCK_MASK           (0x1U)
 #define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT          (0U)
-#define USBPHY_DEBUG_OTGIDPIOLOCK(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK)
+#define USBPHY_DEBUG_OTGIDPIOLOCK_SET(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK)
+#define USBPHY_DEBUG_OTGIDPIOLOCK USBPHY_DEBUG_OTGIDPIOLOCK_MASK
 #define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK   (0x2U)
 #define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT  (1U)
-#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK)
+#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK)
+#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK
 #define USBPHY_DEBUG_HSTPULLDOWN_MASK            (0xCU)
 #define USBPHY_DEBUG_HSTPULLDOWN_SHIFT           (2U)
-#define USBPHY_DEBUG_HSTPULLDOWN(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK)
+#define USBPHY_DEBUG_HSTPULLDOWN_SET(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK)
+#define USBPHY_DEBUG_HSTPULLDOWN USBPHY_DEBUG_HSTPULLDOWN_MASK
 #define USBPHY_DEBUG_ENHSTPULLDOWN_MASK          (0x30U)
 #define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT         (4U)
-#define USBPHY_DEBUG_ENHSTPULLDOWN(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK)
+#define USBPHY_DEBUG_ENHSTPULLDOWN_SET(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK)
+#define USBPHY_DEBUG_ENHSTPULLDOWN USBPHY_DEBUG_ENHSTPULLDOWN_MASK
 #define USBPHY_DEBUG_TX2RXCOUNT_MASK             (0xF00U)
 #define USBPHY_DEBUG_TX2RXCOUNT_SHIFT            (8U)
-#define USBPHY_DEBUG_TX2RXCOUNT(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK)
+#define USBPHY_DEBUG_TX2RXCOUNT_SET(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK)
+#define USBPHY_DEBUG_TX2RXCOUNT USBPHY_DEBUG_TX2RXCOUNT_MASK
 #define USBPHY_DEBUG_ENTX2RXCOUNT_MASK           (0x1000U)
 #define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT          (12U)
-#define USBPHY_DEBUG_ENTX2RXCOUNT(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK)
+#define USBPHY_DEBUG_ENTX2RXCOUNT_SET(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK)
+#define USBPHY_DEBUG_ENTX2RXCOUNT USBPHY_DEBUG_ENTX2RXCOUNT_MASK
 #define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK      (0x1F0000U)
 #define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT     (16U)
-#define USBPHY_DEBUG_SQUELCHRESETCOUNT(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK)
+#define USBPHY_DEBUG_SQUELCHRESETCOUNT_SET(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK)
+#define USBPHY_DEBUG_SQUELCHRESETCOUNT USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK
 #define USBPHY_DEBUG_ENSQUELCHRESET_MASK         (0x1000000U)
 #define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT        (24U)
-#define USBPHY_DEBUG_ENSQUELCHRESET(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK)
+#define USBPHY_DEBUG_ENSQUELCHRESET_SET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK)
+#define USBPHY_DEBUG_ENSQUELCHRESET USBPHY_DEBUG_ENSQUELCHRESET_MASK
 #define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK     (0x1E000000U)
 #define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT    (25U)
-#define USBPHY_DEBUG_SQUELCHRESETLENGTH(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK)
+#define USBPHY_DEBUG_SQUELCHRESETLENGTH_SET(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK)
+#define USBPHY_DEBUG_SQUELCHRESETLENGTH USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK
 #define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK      (0x20000000U)
 #define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT     (29U)
-#define USBPHY_DEBUG_HOST_RESUME_DEBUG(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK)
+#define USBPHY_DEBUG_HOST_RESUME_DEBUG_SET(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK)
+#define USBPHY_DEBUG_HOST_RESUME_DEBUG USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK
 #define USBPHY_DEBUG_CLKGATE_MASK                (0x40000000U)
 #define USBPHY_DEBUG_CLKGATE_SHIFT               (30U)
-#define USBPHY_DEBUG_CLKGATE(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK)
+#define USBPHY_DEBUG_CLKGATE_SET(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK)
+#define USBPHY_DEBUG_CLKGATE USBPHY_DEBUG_CLKGATE_MASK
 
 /*! @name DEBUG_SET - USB PHY Debug Register */
 #define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK       (0x1U)
 #define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT      (0U)
-#define USBPHY_DEBUG_SET_OTGIDPIOLOCK(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK)
+#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SET(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK)
+#define USBPHY_DEBUG_SET_OTGIDPIOLOCK USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK
 #define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U)
 #define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U)
 #define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK)
 #define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK        (0xCU)
 #define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT       (2U)
-#define USBPHY_DEBUG_SET_HSTPULLDOWN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK)
+#define USBPHY_DEBUG_SET_HSTPULLDOWN_SET(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK)
+#define USBPHY_DEBUG_SET_HSTPULLDOWN USBPHY_DEBUG_SET_HSTPULLDOWN_MASK
 #define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK      (0x30U)
 #define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT     (4U)
-#define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK)
+#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SET(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK)
+#define USBPHY_DEBUG_SET_ENHSTPULLDOWN USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK
 #define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK         (0xF00U)
 #define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT        (8U)
-#define USBPHY_DEBUG_SET_TX2RXCOUNT(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK)
+#define USBPHY_DEBUG_SET_TX2RXCOUNT_SET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK)
+#define USBPHY_DEBUG_SET_TX2RXCOUNT USBPHY_DEBUG_SET_TX2RXCOUNT_MASK
 #define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK       (0x1000U)
 #define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT      (12U)
-#define USBPHY_DEBUG_SET_ENTX2RXCOUNT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK)
+#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SET(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK)
+#define USBPHY_DEBUG_SET_ENTX2RXCOUNT USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK
 #define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK  (0x1F0000U)
 #define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U)
-#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK)
+#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SET(x)(((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK)
+#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK
 #define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK     (0x1000000U)
 #define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT    (24U)
-#define USBPHY_DEBUG_SET_ENSQUELCHRESET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK)
+#define USBPHY_DEBUG_SET_ENSQUELCHRESET_SET(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK)
+#define USBPHY_DEBUG_SET_ENSQUELCHRESET USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK
 #define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U)
 #define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U)
 #define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK)
 #define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK  (0x20000000U)
 #define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U)
-#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK)
+#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SET(x)(((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK)
+#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK
 #define USBPHY_DEBUG_SET_CLKGATE_MASK            (0x40000000U)
 #define USBPHY_DEBUG_SET_CLKGATE_SHIFT           (30U)
-#define USBPHY_DEBUG_SET_CLKGATE(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK)
+#define USBPHY_DEBUG_SET_CLKGATE_SET(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK)
+#define USBPHY_DEBUG_SET_CLKGATE USBPHY_DEBUG_SET_CLKGATE_MASK
 
 /*! @name DEBUG_CLR - USB PHY Debug Register */
 #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK       (0x1U)
 #define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT      (0U)
-#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK)
+#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SET(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK)
+#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK
 #define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U)
 #define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U)
 #define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK)
 #define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK        (0xCU)
 #define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT       (2U)
-#define USBPHY_DEBUG_CLR_HSTPULLDOWN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK)
+#define USBPHY_DEBUG_CLR_HSTPULLDOWN_SET(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK)
+#define USBPHY_DEBUG_CLR_HSTPULLDOWN USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK
 #define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK      (0x30U)
 #define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT     (4U)
-#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK)
+#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SET(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK)
+#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK
 #define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK         (0xF00U)
 #define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT        (8U)
-#define USBPHY_DEBUG_CLR_TX2RXCOUNT(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK)
+#define USBPHY_DEBUG_CLR_TX2RXCOUNT_SET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK)
+#define USBPHY_DEBUG_CLR_TX2RXCOUNT USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK
 #define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK       (0x1000U)
 #define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT      (12U)
-#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK)
+#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SET(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK)
+#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK
 #define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK  (0x1F0000U)
 #define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U)
-#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK)
+#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SET(x)(((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK)
+#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK
 #define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK     (0x1000000U)
 #define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT    (24U)
-#define USBPHY_DEBUG_CLR_ENSQUELCHRESET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK)
+#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SET(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK)
+#define USBPHY_DEBUG_CLR_ENSQUELCHRESET USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK
 #define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U)
 #define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U)
 #define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK)
 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK  (0x20000000U)
 #define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U)
-#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)
+#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SET(x)(((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)
+#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK
 #define USBPHY_DEBUG_CLR_CLKGATE_MASK            (0x40000000U)
 #define USBPHY_DEBUG_CLR_CLKGATE_SHIFT           (30U)
-#define USBPHY_DEBUG_CLR_CLKGATE(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK)
+#define USBPHY_DEBUG_CLR_CLKGATE_SET(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK)
+#define USBPHY_DEBUG_CLR_CLKGATE USBPHY_DEBUG_CLR_CLKGATE_MASK
 
 /*! @name DEBUG_TOG - USB PHY Debug Register */
 #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK       (0x1U)
 #define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT      (0U)
-#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK)
+#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SET(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK)
+#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK
 #define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
 #define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
 #define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK)
 #define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK        (0xCU)
 #define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT       (2U)
-#define USBPHY_DEBUG_TOG_HSTPULLDOWN(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK)
+#define USBPHY_DEBUG_TOG_HSTPULLDOWN_SET(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK)
+#define USBPHY_DEBUG_TOG_HSTPULLDOWN USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK
 #define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK      (0x30U)
 #define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT     (4U)
-#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK)
+#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SET(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK)
+#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK
 #define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK         (0xF00U)
 #define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT        (8U)
-#define USBPHY_DEBUG_TOG_TX2RXCOUNT(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK)
+#define USBPHY_DEBUG_TOG_TX2RXCOUNT_SET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK)
+#define USBPHY_DEBUG_TOG_TX2RXCOUNT USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK
 #define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK       (0x1000U)
 #define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT      (12U)
-#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK)
+#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SET(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK)
+#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK
 #define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK  (0x1F0000U)
 #define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U)
-#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK)
+#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SET(x)(((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK)
+#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK
 #define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK     (0x1000000U)
 #define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT    (24U)
-#define USBPHY_DEBUG_TOG_ENSQUELCHRESET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK)
+#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SET(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK)
+#define USBPHY_DEBUG_TOG_ENSQUELCHRESET USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK
 #define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
 #define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U)
 #define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK)
 #define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK  (0x20000000U)
 #define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U)
-#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK)
+#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SET(x)(((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK)
+#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK
 #define USBPHY_DEBUG_TOG_CLKGATE_MASK            (0x40000000U)
 #define USBPHY_DEBUG_TOG_CLKGATE_SHIFT           (30U)
-#define USBPHY_DEBUG_TOG_CLKGATE(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK)
+#define USBPHY_DEBUG_TOG_CLKGATE_SET(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK)
+#define USBPHY_DEBUG_TOG_CLKGATE USBPHY_DEBUG_TOG_CLKGATE_MASK
 
 /*! @name DEBUG0_STATUS - UTMI Debug Status Register 0 */
 #define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU)
@@ -16344,130 +19759,163 @@ typedef struct {
 #define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK)
 #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK  (0xFC000000U)
 #define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U)
-#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK)
+#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SET(x)(((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK)
+#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK
 
 /*! @name DEBUG1 - UTMI Debug Status Register 1 */
 #define USBPHY_DEBUG1_ENTAILADJVD_MASK           (0x6000U)
 #define USBPHY_DEBUG1_ENTAILADJVD_SHIFT          (13U)
-#define USBPHY_DEBUG1_ENTAILADJVD(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK)
+#define USBPHY_DEBUG1_ENTAILADJVD_SET(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK)
+#define USBPHY_DEBUG1_ENTAILADJVD USBPHY_DEBUG1_ENTAILADJVD_MASK
 
 /*! @name DEBUG1_SET - UTMI Debug Status Register 1 */
 #define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK       (0x6000U)
 #define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT      (13U)
-#define USBPHY_DEBUG1_SET_ENTAILADJVD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK)
+#define USBPHY_DEBUG1_SET_ENTAILADJVD_SET(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK)
+#define USBPHY_DEBUG1_SET_ENTAILADJVD USBPHY_DEBUG1_SET_ENTAILADJVD_MASK
 
 /*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */
 #define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK       (0x6000U)
 #define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT      (13U)
-#define USBPHY_DEBUG1_CLR_ENTAILADJVD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK)
+#define USBPHY_DEBUG1_CLR_ENTAILADJVD_SET(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK)
+#define USBPHY_DEBUG1_CLR_ENTAILADJVD USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK
 
 /*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */
 #define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK       (0x6000U)
 #define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT      (13U)
-#define USBPHY_DEBUG1_TOG_ENTAILADJVD(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK)
+#define USBPHY_DEBUG1_TOG_ENTAILADJVD_SET(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK)
+#define USBPHY_DEBUG1_TOG_ENTAILADJVD USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK
 
 /*! @name VERSION - UTMI RTL Version */
 #define USBPHY_VERSION_STEP_MASK                 (0xFFFFU)
 #define USBPHY_VERSION_STEP_SHIFT                (0U)
-#define USBPHY_VERSION_STEP(x)                   (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK)
+#define USBPHY_VERSION_STEP_SET(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK)
+#define USBPHY_VERSION_STEP USBPHY_VERSION_STEP_MASK
 #define USBPHY_VERSION_MINOR_MASK                (0xFF0000U)
 #define USBPHY_VERSION_MINOR_SHIFT               (16U)
-#define USBPHY_VERSION_MINOR(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK)
+#define USBPHY_VERSION_MINOR_SET(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK)
+#define USBPHY_VERSION_MINOR USBPHY_VERSION_MINOR_MASK
 #define USBPHY_VERSION_MAJOR_MASK                (0xFF000000U)
 #define USBPHY_VERSION_MAJOR_SHIFT               (24U)
-#define USBPHY_VERSION_MAJOR(x)                  (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK)
+#define USBPHY_VERSION_MAJOR_SET(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK)
+#define USBPHY_VERSION_MAJOR USBPHY_VERSION_MAJOR_MASK
 
 /*! @name PLL_SIC - USB PHY PLL Control/Status Register */
 #define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK          (0x3U)
 #define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT         (0U)
-#define USBPHY_PLL_SIC_PLL_DIV_SEL(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)
+#define USBPHY_PLL_SIC_PLL_DIV_SEL_SET(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)
+#define USBPHY_PLL_SIC_PLL_DIV_SEL USBPHY_PLL_SIC_PLL_DIV_SEL_MASK
 #define USBPHY_PLL_SIC_PLL_EN_USBx_CLKS_MASK      (0x40U)
 #define USBPHY_PLL_SIC_PLL_EN_USBx_CLKS_SHIFT     (6U)
-#define USBPHY_PLL_SIC_PLL_EN_USBx_CLKS(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USBx_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USBx_CLKS_MASK)
+#define USBPHY_PLL_SIC_PLL_EN_USBx_CLKS_SET(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USBx_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USBx_CLKS_MASK)
+#define USBPHY_PLL_SIC_PLL_EN_USBx_CLKS USBPHY_PLL_SIC_PLL_EN_USBx_CLKS_MASK
 #define USBPHY_PLL_SIC_PLL_HOLD_RING_OFF_MASK    (0x800U)
 #define USBPHY_PLL_SIC_PLL_HOLD_RING_OFF_SHIFT   (11U)
-#define USBPHY_PLL_SIC_PLL_HOLD_RING_OFF(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_HOLD_RING_OFF_SHIFT)) & USBPHY_PLL_SIC_PLL_HOLD_RING_OFF_MASK)
+#define USBPHY_PLL_SIC_PLL_HOLD_RING_OFF_SET(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_HOLD_RING_OFF_SHIFT)) & USBPHY_PLL_SIC_PLL_HOLD_RING_OFF_MASK)
+#define USBPHY_PLL_SIC_PLL_HOLD_RING_OFF USBPHY_PLL_SIC_PLL_HOLD_RING_OFF_MASK
 #define USBPHY_PLL_SIC_PLL_POWER_MASK            (0x1000U)
 #define USBPHY_PLL_SIC_PLL_POWER_SHIFT           (12U)
-#define USBPHY_PLL_SIC_PLL_POWER(x)              (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK)
+#define USBPHY_PLL_SIC_PLL_POWER_SET(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK)
+#define USBPHY_PLL_SIC_PLL_POWER USBPHY_PLL_SIC_PLL_POWER_MASK
 #define USBPHY_PLL_SIC_PLL_ENABLE_MASK           (0x2000U)
 #define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT          (13U)
-#define USBPHY_PLL_SIC_PLL_ENABLE(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK)
+#define USBPHY_PLL_SIC_PLL_ENABLE_SET(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK)
+#define USBPHY_PLL_SIC_PLL_ENABLE USBPHY_PLL_SIC_PLL_ENABLE_MASK
 #define USBPHY_PLL_SIC_PLL_BYPASS_MASK           (0x10000U)
 #define USBPHY_PLL_SIC_PLL_BYPASS_SHIFT          (16U)
-#define USBPHY_PLL_SIC_PLL_BYPASS(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_PLL_BYPASS_MASK)
+#define USBPHY_PLL_SIC_PLL_BYPASS_SET(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_PLL_BYPASS_MASK)
+#define USBPHY_PLL_SIC_PLL_BYPASS USBPHY_PLL_SIC_PLL_BYPASS_MASK
 #define USBPHY_PLL_SIC_PLL_LOCK_MASK             (0x80000000U)
 #define USBPHY_PLL_SIC_PLL_LOCK_SHIFT            (31U)
-#define USBPHY_PLL_SIC_PLL_LOCK(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK)
+#define USBPHY_PLL_SIC_PLL_LOCK_SET(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK)
+#define USBPHY_PLL_SIC_PLL_LOCK USBPHY_PLL_SIC_PLL_LOCK_MASK
 
 /*! @name PLL_SIC_SET - USB PHY PLL Control/Status Register */
 #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK      (0x3U)
 #define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT     (0U)
-#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK)
+#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SET(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK)
+#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK
 #define USBPHY_PLL_SIC_SET_PLL_EN_USBx_CLKS_MASK  (0x40U)
 #define USBPHY_PLL_SIC_SET_PLL_EN_USBx_CLKS_SHIFT (6U)
-#define USBPHY_PLL_SIC_SET_PLL_EN_USBx_CLKS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USBx_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USBx_CLKS_MASK)
+#define USBPHY_PLL_SIC_SET_PLL_EN_USBx_CLKS_SET(x)(((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USBx_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USBx_CLKS_MASK)
+#define USBPHY_PLL_SIC_SET_PLL_EN_USBx_CLKS USBPHY_PLL_SIC_SET_PLL_EN_USBx_CLKS_MASK
 #define USBPHY_PLL_SIC_SET_PLL_HOLD_RING_OFF_MASK (0x800U)
 #define USBPHY_PLL_SIC_SET_PLL_HOLD_RING_OFF_SHIFT (11U)
 #define USBPHY_PLL_SIC_SET_PLL_HOLD_RING_OFF(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_HOLD_RING_OFF_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_HOLD_RING_OFF_MASK)
 #define USBPHY_PLL_SIC_SET_PLL_POWER_MASK        (0x1000U)
 #define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT       (12U)
-#define USBPHY_PLL_SIC_SET_PLL_POWER(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK)
+#define USBPHY_PLL_SIC_SET_PLL_POWER_SET(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK)
+#define USBPHY_PLL_SIC_SET_PLL_POWER USBPHY_PLL_SIC_SET_PLL_POWER_MASK
 #define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK       (0x2000U)
 #define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT      (13U)
-#define USBPHY_PLL_SIC_SET_PLL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK)
+#define USBPHY_PLL_SIC_SET_PLL_ENABLE_SET(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK)
+#define USBPHY_PLL_SIC_SET_PLL_ENABLE USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK
 #define USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK       (0x10000U)
 #define USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT      (16U)
-#define USBPHY_PLL_SIC_SET_PLL_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK)
+#define USBPHY_PLL_SIC_SET_PLL_BYPASS_SET(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK)
+#define USBPHY_PLL_SIC_SET_PLL_BYPASS USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK
 #define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK         (0x80000000U)
 #define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT        (31U)
-#define USBPHY_PLL_SIC_SET_PLL_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK)
+#define USBPHY_PLL_SIC_SET_PLL_LOCK_SET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK)
+#define USBPHY_PLL_SIC_SET_PLL_LOCK USBPHY_PLL_SIC_SET_PLL_LOCK_MASK
 
 /*! @name PLL_SIC_CLR - USB PHY PLL Control/Status Register */
 #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK      (0x3U)
 #define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT     (0U)
-#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK)
+#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SET(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK)
+#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK
 #define USBPHY_PLL_SIC_CLR_PLL_EN_USBx_CLKS_MASK  (0x40U)
 #define USBPHY_PLL_SIC_CLR_PLL_EN_USBx_CLKS_SHIFT (6U)
-#define USBPHY_PLL_SIC_CLR_PLL_EN_USBx_CLKS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USBx_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USBx_CLKS_MASK)
+#define USBPHY_PLL_SIC_CLR_PLL_EN_USBx_CLKS_SET(x)(((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USBx_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USBx_CLKS_MASK)
+#define USBPHY_PLL_SIC_CLR_PLL_EN_USBx_CLKS USBPHY_PLL_SIC_CLR_PLL_EN_USBx_CLKS_MASK
 #define USBPHY_PLL_SIC_CLR_PLL_HOLD_RING_OFF_MASK (0x800U)
 #define USBPHY_PLL_SIC_CLR_PLL_HOLD_RING_OFF_SHIFT (11U)
 #define USBPHY_PLL_SIC_CLR_PLL_HOLD_RING_OFF(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_HOLD_RING_OFF_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_HOLD_RING_OFF_MASK)
 #define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK        (0x1000U)
 #define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT       (12U)
-#define USBPHY_PLL_SIC_CLR_PLL_POWER(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK)
+#define USBPHY_PLL_SIC_CLR_PLL_POWER_SET(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK)
+#define USBPHY_PLL_SIC_CLR_PLL_POWER USBPHY_PLL_SIC_CLR_PLL_POWER_MASK
 #define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK       (0x2000U)
 #define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT      (13U)
-#define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK)
+#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SET(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK)
+#define USBPHY_PLL_SIC_CLR_PLL_ENABLE USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK
 #define USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK       (0x10000U)
 #define USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT      (16U)
-#define USBPHY_PLL_SIC_CLR_PLL_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK)
+#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_SET(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK)
+#define USBPHY_PLL_SIC_CLR_PLL_BYPASS USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK
 #define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK         (0x80000000U)
 #define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT        (31U)
-#define USBPHY_PLL_SIC_CLR_PLL_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK)
+#define USBPHY_PLL_SIC_CLR_PLL_LOCK_SET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK)
+#define USBPHY_PLL_SIC_CLR_PLL_LOCK USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK
 
 /*! @name PLL_SIC_TOG - USB PHY PLL Control/Status Register */
 #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK      (0x3U)
 #define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT     (0U)
-#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK)
+#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SET(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK)
+#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK
 #define USBPHY_PLL_SIC_TOG_PLL_EN_USBx_CLKS_MASK  (0x40U)
 #define USBPHY_PLL_SIC_TOG_PLL_EN_USBx_CLKS_SHIFT (6U)
-#define USBPHY_PLL_SIC_TOG_PLL_EN_USBx_CLKS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USBx_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USBx_CLKS_MASK)
+#define USBPHY_PLL_SIC_TOG_PLL_EN_USBx_CLKS_SET(x)(((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USBx_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USBx_CLKS_MASK)
+#define USBPHY_PLL_SIC_TOG_PLL_EN_USBx_CLKS USBPHY_PLL_SIC_TOG_PLL_EN_USBx_CLKS_MASK
 #define USBPHY_PLL_SIC_TOG_PLL_HOLD_RING_OFF_MASK (0x800U)
 #define USBPHY_PLL_SIC_TOG_PLL_HOLD_RING_OFF_SHIFT (11U)
 #define USBPHY_PLL_SIC_TOG_PLL_HOLD_RING_OFF(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_HOLD_RING_OFF_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_HOLD_RING_OFF_MASK)
 #define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK        (0x1000U)
 #define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT       (12U)
-#define USBPHY_PLL_SIC_TOG_PLL_POWER(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK)
+#define USBPHY_PLL_SIC_TOG_PLL_POWER_SET(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK)
+#define USBPHY_PLL_SIC_TOG_PLL_POWER USBPHY_PLL_SIC_TOG_PLL_POWER_MASK
 #define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK       (0x2000U)
 #define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT      (13U)
-#define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK)
+#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SET(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK)
+#define USBPHY_PLL_SIC_TOG_PLL_ENABLE USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK
 #define USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK       (0x10000U)
 #define USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT      (16U)
-#define USBPHY_PLL_SIC_TOG_PLL_BYPASS(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK)
+#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_SET(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK)
+#define USBPHY_PLL_SIC_TOG_PLL_BYPASS USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK
 #define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK         (0x80000000U)
 #define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT        (31U)
-#define USBPHY_PLL_SIC_TOG_PLL_LOCK(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK)
+#define USBPHY_PLL_SIC_TOG_PLL_LOCK_SET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK)
+#define USBPHY_PLL_SIC_TOG_PLL_LOCK USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK
 
 /*! @name USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register */
 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U)
@@ -16499,7 +19947,8 @@ typedef struct {
 #define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK)
 #define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK  (0x100000U)
 #define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U)
-#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK)
+#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SET(x)(((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK)
+#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK
 #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U)
 #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U)
 #define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK)
@@ -16624,13 +20073,16 @@ typedef struct {
 /*! @name USB1_VBUS_DET_STAT - USB PHY VBUS Detector Status Register */
 #define USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK   (0x1U)
 #define USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT  (0U)
-#define USBPHY_USB1_VBUS_DET_STAT_SESSEND(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK)
+#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_SET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK)
+#define USBPHY_USB1_VBUS_DET_STAT_SESSEND USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK
 #define USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK    (0x2U)
 #define USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT   (1U)
-#define USBPHY_USB1_VBUS_DET_STAT_BVALID(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK)
+#define USBPHY_USB1_VBUS_DET_STAT_BVALID_SET(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK)
+#define USBPHY_USB1_VBUS_DET_STAT_BVALID USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK
 #define USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK    (0x4U)
 #define USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT   (2U)
-#define USBPHY_USB1_VBUS_DET_STAT_AVALID(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK)
+#define USBPHY_USB1_VBUS_DET_STAT_AVALID_SET(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK)
+#define USBPHY_USB1_VBUS_DET_STAT_AVALID USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK
 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK (0x8U)
 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT (3U)
 #define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK)
@@ -16647,10 +20099,12 @@ typedef struct {
 #define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK)
 #define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK  (0x4U)
 #define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT (2U)
-#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK)
+#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SET(x)(((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DM_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK)
+#define USBPHY_USB1_CHRG_DET_STAT_DM_STATE USBPHY_USB1_CHRG_DET_STAT_DM_STATE_MASK
 #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK  (0x8U)
 #define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT (3U)
-#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK)
+#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SET(x)(((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK)
+#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK
 #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK (0x10U)
 #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT (4U)
 #define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK)
@@ -16658,118 +20112,154 @@ typedef struct {
 /*! @name ANACTRL - USB PHY Analog Control Register */
 #define USBPHY_ANACTRL_TESTCLK_SEL_MASK          (0x1U)
 #define USBPHY_ANACTRL_TESTCLK_SEL_SHIFT         (0U)
-#define USBPHY_ANACTRL_TESTCLK_SEL(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TESTCLK_SEL_SHIFT)) & USBPHY_ANACTRL_TESTCLK_SEL_MASK)
+#define USBPHY_ANACTRL_TESTCLK_SEL_SET(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TESTCLK_SEL_SHIFT)) & USBPHY_ANACTRL_TESTCLK_SEL_MASK)
+#define USBPHY_ANACTRL_TESTCLK_SEL USBPHY_ANACTRL_TESTCLK_SEL_MASK
 #define USBPHY_ANACTRL_PFD_CLKGATE_MASK          (0x2U)
 #define USBPHY_ANACTRL_PFD_CLKGATE_SHIFT         (1U)
-#define USBPHY_ANACTRL_PFD_CLKGATE(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLKGATE_SHIFT)) & USBPHY_ANACTRL_PFD_CLKGATE_MASK)
+#define USBPHY_ANACTRL_PFD_CLKGATE_SET(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLKGATE_SHIFT)) & USBPHY_ANACTRL_PFD_CLKGATE_MASK)
+#define USBPHY_ANACTRL_PFD_CLKGATE USBPHY_ANACTRL_PFD_CLKGATE_MASK
 #define USBPHY_ANACTRL_PFD_CLK_SEL_MASK          (0xCU)
 #define USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT         (2U)
-#define USBPHY_ANACTRL_PFD_CLK_SEL(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_PFD_CLK_SEL_MASK)
+#define USBPHY_ANACTRL_PFD_CLK_SEL_SET(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_PFD_CLK_SEL_MASK)
+#define USBPHY_ANACTRL_PFD_CLK_SEL USBPHY_ANACTRL_PFD_CLK_SEL_MASK
 #define USBPHY_ANACTRL_PFD_FRAC_MASK             (0x3F0U)
 #define USBPHY_ANACTRL_PFD_FRAC_SHIFT            (4U)
-#define USBPHY_ANACTRL_PFD_FRAC(x)               (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_FRAC_SHIFT)) & USBPHY_ANACTRL_PFD_FRAC_MASK)
+#define USBPHY_ANACTRL_PFD_FRAC_SET(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_FRAC_SHIFT)) & USBPHY_ANACTRL_PFD_FRAC_MASK)
+#define USBPHY_ANACTRL_PFD_FRAC USBPHY_ANACTRL_PFD_FRAC_MASK
 #define USBPHY_ANACTRL_DEV_PULLDOWN_MASK         (0x400U)
 #define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT        (10U)
-#define USBPHY_ANACTRL_DEV_PULLDOWN(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK)
+#define USBPHY_ANACTRL_DEV_PULLDOWN_SET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK)
+#define USBPHY_ANACTRL_DEV_PULLDOWN USBPHY_ANACTRL_DEV_PULLDOWN_MASK
 #define USBPHY_ANACTRL_EMPH_PULSE_CTRL_MASK      (0x1800U)
 #define USBPHY_ANACTRL_EMPH_PULSE_CTRL_SHIFT     (11U)
-#define USBPHY_ANACTRL_EMPH_PULSE_CTRL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_EMPH_PULSE_CTRL_SHIFT)) & USBPHY_ANACTRL_EMPH_PULSE_CTRL_MASK)
+#define USBPHY_ANACTRL_EMPH_PULSE_CTRL_SET(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_EMPH_PULSE_CTRL_SHIFT)) & USBPHY_ANACTRL_EMPH_PULSE_CTRL_MASK)
+#define USBPHY_ANACTRL_EMPH_PULSE_CTRL USBPHY_ANACTRL_EMPH_PULSE_CTRL_MASK
 #define USBPHY_ANACTRL_EMPH_EN_MASK              (0x2000U)
 #define USBPHY_ANACTRL_EMPH_EN_SHIFT             (13U)
-#define USBPHY_ANACTRL_EMPH_EN(x)                (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_EMPH_EN_SHIFT)) & USBPHY_ANACTRL_EMPH_EN_MASK)
+#define USBPHY_ANACTRL_EMPH_EN_SET(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_EMPH_EN_SHIFT)) & USBPHY_ANACTRL_EMPH_EN_MASK)
+#define USBPHY_ANACTRL_EMPH_EN USBPHY_ANACTRL_EMPH_EN_MASK
 #define USBPHY_ANACTRL_EMPH_CUR_CTRL_MASK        (0xC000U)
 #define USBPHY_ANACTRL_EMPH_CUR_CTRL_SHIFT       (14U)
-#define USBPHY_ANACTRL_EMPH_CUR_CTRL(x)          (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_EMPH_CUR_CTRL_SHIFT)) & USBPHY_ANACTRL_EMPH_CUR_CTRL_MASK)
+#define USBPHY_ANACTRL_EMPH_CUR_CTRL_SET(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_EMPH_CUR_CTRL_SHIFT)) & USBPHY_ANACTRL_EMPH_CUR_CTRL_MASK)
+#define USBPHY_ANACTRL_EMPH_CUR_CTRL USBPHY_ANACTRL_EMPH_CUR_CTRL_MASK
 #define USBPHY_ANACTRL_PFD_STABLE_MASK           (0x80000000U)
 #define USBPHY_ANACTRL_PFD_STABLE_SHIFT          (31U)
-#define USBPHY_ANACTRL_PFD_STABLE(x)             (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_STABLE_SHIFT)) & USBPHY_ANACTRL_PFD_STABLE_MASK)
+#define USBPHY_ANACTRL_PFD_STABLE_SET(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_PFD_STABLE_SHIFT)) & USBPHY_ANACTRL_PFD_STABLE_MASK)
+#define USBPHY_ANACTRL_PFD_STABLE USBPHY_ANACTRL_PFD_STABLE_MASK
 
 /*! @name ANACTRL_SET - USB PHY Analog Control Register */
 #define USBPHY_ANACTRL_SET_TESTCLK_SEL_MASK      (0x1U)
 #define USBPHY_ANACTRL_SET_TESTCLK_SEL_SHIFT     (0U)
-#define USBPHY_ANACTRL_SET_TESTCLK_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_TESTCLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_TESTCLK_SEL_MASK)
+#define USBPHY_ANACTRL_SET_TESTCLK_SEL_SET(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_TESTCLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_TESTCLK_SEL_MASK)
+#define USBPHY_ANACTRL_SET_TESTCLK_SEL USBPHY_ANACTRL_SET_TESTCLK_SEL_MASK
 #define USBPHY_ANACTRL_SET_PFD_CLKGATE_MASK      (0x2U)
 #define USBPHY_ANACTRL_SET_PFD_CLKGATE_SHIFT     (1U)
-#define USBPHY_ANACTRL_SET_PFD_CLKGATE(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLKGATE_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLKGATE_MASK)
+#define USBPHY_ANACTRL_SET_PFD_CLKGATE_SET(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLKGATE_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLKGATE_MASK)
+#define USBPHY_ANACTRL_SET_PFD_CLKGATE USBPHY_ANACTRL_SET_PFD_CLKGATE_MASK
 #define USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK      (0xCU)
 #define USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT     (2U)
-#define USBPHY_ANACTRL_SET_PFD_CLK_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK)
+#define USBPHY_ANACTRL_SET_PFD_CLK_SEL_SET(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK)
+#define USBPHY_ANACTRL_SET_PFD_CLK_SEL USBPHY_ANACTRL_SET_PFD_CLK_SEL_MASK
 #define USBPHY_ANACTRL_SET_PFD_FRAC_MASK         (0x3F0U)
 #define USBPHY_ANACTRL_SET_PFD_FRAC_SHIFT        (4U)
-#define USBPHY_ANACTRL_SET_PFD_FRAC(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_FRAC_SHIFT)) & USBPHY_ANACTRL_SET_PFD_FRAC_MASK)
+#define USBPHY_ANACTRL_SET_PFD_FRAC_SET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_FRAC_SHIFT)) & USBPHY_ANACTRL_SET_PFD_FRAC_MASK)
+#define USBPHY_ANACTRL_SET_PFD_FRAC USBPHY_ANACTRL_SET_PFD_FRAC_MASK
 #define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK     (0x400U)
 #define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT    (10U)
-#define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK)
+#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SET(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK)
+#define USBPHY_ANACTRL_SET_DEV_PULLDOWN USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK
 #define USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL_MASK  (0x1800U)
 #define USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL_SHIFT (11U)
-#define USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL_SHIFT)) & USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL_MASK)
+#define USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL_SET(x)(((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL_SHIFT)) & USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL_MASK)
+#define USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL USBPHY_ANACTRL_SET_EMPH_PULSE_CTRL_MASK
 #define USBPHY_ANACTRL_SET_EMPH_EN_MASK          (0x2000U)
 #define USBPHY_ANACTRL_SET_EMPH_EN_SHIFT         (13U)
-#define USBPHY_ANACTRL_SET_EMPH_EN(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_EMPH_EN_SHIFT)) & USBPHY_ANACTRL_SET_EMPH_EN_MASK)
+#define USBPHY_ANACTRL_SET_EMPH_EN_SET(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_EMPH_EN_SHIFT)) & USBPHY_ANACTRL_SET_EMPH_EN_MASK)
+#define USBPHY_ANACTRL_SET_EMPH_EN USBPHY_ANACTRL_SET_EMPH_EN_MASK
 #define USBPHY_ANACTRL_SET_EMPH_CUR_CTRL_MASK    (0xC000U)
 #define USBPHY_ANACTRL_SET_EMPH_CUR_CTRL_SHIFT   (14U)
-#define USBPHY_ANACTRL_SET_EMPH_CUR_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_EMPH_CUR_CTRL_SHIFT)) & USBPHY_ANACTRL_SET_EMPH_CUR_CTRL_MASK)
+#define USBPHY_ANACTRL_SET_EMPH_CUR_CTRL_SET(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_EMPH_CUR_CTRL_SHIFT)) & USBPHY_ANACTRL_SET_EMPH_CUR_CTRL_MASK)
+#define USBPHY_ANACTRL_SET_EMPH_CUR_CTRL USBPHY_ANACTRL_SET_EMPH_CUR_CTRL_MASK
 #define USBPHY_ANACTRL_SET_PFD_STABLE_MASK       (0x80000000U)
 #define USBPHY_ANACTRL_SET_PFD_STABLE_SHIFT      (31U)
-#define USBPHY_ANACTRL_SET_PFD_STABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_STABLE_SHIFT)) & USBPHY_ANACTRL_SET_PFD_STABLE_MASK)
+#define USBPHY_ANACTRL_SET_PFD_STABLE_SET(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_PFD_STABLE_SHIFT)) & USBPHY_ANACTRL_SET_PFD_STABLE_MASK)
+#define USBPHY_ANACTRL_SET_PFD_STABLE USBPHY_ANACTRL_SET_PFD_STABLE_MASK
 
 /*! @name ANACTRL_CLR - USB PHY Analog Control Register */
 #define USBPHY_ANACTRL_CLR_TESTCLK_SEL_MASK      (0x1U)
 #define USBPHY_ANACTRL_CLR_TESTCLK_SEL_SHIFT     (0U)
-#define USBPHY_ANACTRL_CLR_TESTCLK_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_TESTCLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_TESTCLK_SEL_MASK)
+#define USBPHY_ANACTRL_CLR_TESTCLK_SEL_SET(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_TESTCLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_TESTCLK_SEL_MASK)
+#define USBPHY_ANACTRL_CLR_TESTCLK_SEL USBPHY_ANACTRL_CLR_TESTCLK_SEL_MASK
 #define USBPHY_ANACTRL_CLR_PFD_CLKGATE_MASK      (0x2U)
 #define USBPHY_ANACTRL_CLR_PFD_CLKGATE_SHIFT     (1U)
-#define USBPHY_ANACTRL_CLR_PFD_CLKGATE(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLKGATE_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLKGATE_MASK)
+#define USBPHY_ANACTRL_CLR_PFD_CLKGATE_SET(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLKGATE_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLKGATE_MASK)
+#define USBPHY_ANACTRL_CLR_PFD_CLKGATE USBPHY_ANACTRL_CLR_PFD_CLKGATE_MASK
 #define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK      (0xCU)
 #define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT     (2U)
-#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK)
+#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SET(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK)
+#define USBPHY_ANACTRL_CLR_PFD_CLK_SEL USBPHY_ANACTRL_CLR_PFD_CLK_SEL_MASK
 #define USBPHY_ANACTRL_CLR_PFD_FRAC_MASK         (0x3F0U)
 #define USBPHY_ANACTRL_CLR_PFD_FRAC_SHIFT        (4U)
-#define USBPHY_ANACTRL_CLR_PFD_FRAC(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_FRAC_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_FRAC_MASK)
+#define USBPHY_ANACTRL_CLR_PFD_FRAC_SET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_FRAC_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_FRAC_MASK)
+#define USBPHY_ANACTRL_CLR_PFD_FRAC USBPHY_ANACTRL_CLR_PFD_FRAC_MASK
 #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK     (0x400U)
 #define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT    (10U)
-#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK)
+#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SET(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK)
+#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK
 #define USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL_MASK  (0x1800U)
 #define USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL_SHIFT (11U)
-#define USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL_SHIFT)) & USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL_MASK)
+#define USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL_SET(x)(((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL_SHIFT)) & USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL_MASK)
+#define USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL USBPHY_ANACTRL_CLR_EMPH_PULSE_CTRL_MASK
 #define USBPHY_ANACTRL_CLR_EMPH_EN_MASK          (0x2000U)
 #define USBPHY_ANACTRL_CLR_EMPH_EN_SHIFT         (13U)
-#define USBPHY_ANACTRL_CLR_EMPH_EN(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_EMPH_EN_SHIFT)) & USBPHY_ANACTRL_CLR_EMPH_EN_MASK)
+#define USBPHY_ANACTRL_CLR_EMPH_EN_SET(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_EMPH_EN_SHIFT)) & USBPHY_ANACTRL_CLR_EMPH_EN_MASK)
+#define USBPHY_ANACTRL_CLR_EMPH_EN USBPHY_ANACTRL_CLR_EMPH_EN_MASK
 #define USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL_MASK    (0xC000U)
 #define USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL_SHIFT   (14U)
-#define USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL_SHIFT)) & USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL_MASK)
+#define USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL_SET(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL_SHIFT)) & USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL_MASK)
+#define USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL USBPHY_ANACTRL_CLR_EMPH_CUR_CTRL_MASK
 #define USBPHY_ANACTRL_CLR_PFD_STABLE_MASK       (0x80000000U)
 #define USBPHY_ANACTRL_CLR_PFD_STABLE_SHIFT      (31U)
-#define USBPHY_ANACTRL_CLR_PFD_STABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_STABLE_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_STABLE_MASK)
+#define USBPHY_ANACTRL_CLR_PFD_STABLE_SET(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_PFD_STABLE_SHIFT)) & USBPHY_ANACTRL_CLR_PFD_STABLE_MASK)
+#define USBPHY_ANACTRL_CLR_PFD_STABLE USBPHY_ANACTRL_CLR_PFD_STABLE_MASK
 
 /*! @name ANACTRL_TOG - USB PHY Analog Control Register */
 #define USBPHY_ANACTRL_TOG_TESTCLK_SEL_MASK      (0x1U)
 #define USBPHY_ANACTRL_TOG_TESTCLK_SEL_SHIFT     (0U)
-#define USBPHY_ANACTRL_TOG_TESTCLK_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_TESTCLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_TESTCLK_SEL_MASK)
+#define USBPHY_ANACTRL_TOG_TESTCLK_SEL_SET(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_TESTCLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_TESTCLK_SEL_MASK)
+#define USBPHY_ANACTRL_TOG_TESTCLK_SEL USBPHY_ANACTRL_TOG_TESTCLK_SEL_MASK
 #define USBPHY_ANACTRL_TOG_PFD_CLKGATE_MASK      (0x2U)
 #define USBPHY_ANACTRL_TOG_PFD_CLKGATE_SHIFT     (1U)
-#define USBPHY_ANACTRL_TOG_PFD_CLKGATE(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLKGATE_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLKGATE_MASK)
+#define USBPHY_ANACTRL_TOG_PFD_CLKGATE_SET(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLKGATE_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLKGATE_MASK)
+#define USBPHY_ANACTRL_TOG_PFD_CLKGATE USBPHY_ANACTRL_TOG_PFD_CLKGATE_MASK
 #define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK      (0xCU)
 #define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT     (2U)
-#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK)
+#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SET(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_CLK_SEL_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK)
+#define USBPHY_ANACTRL_TOG_PFD_CLK_SEL USBPHY_ANACTRL_TOG_PFD_CLK_SEL_MASK
 #define USBPHY_ANACTRL_TOG_PFD_FRAC_MASK         (0x3F0U)
 #define USBPHY_ANACTRL_TOG_PFD_FRAC_SHIFT        (4U)
-#define USBPHY_ANACTRL_TOG_PFD_FRAC(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_FRAC_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_FRAC_MASK)
+#define USBPHY_ANACTRL_TOG_PFD_FRAC_SET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_FRAC_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_FRAC_MASK)
+#define USBPHY_ANACTRL_TOG_PFD_FRAC USBPHY_ANACTRL_TOG_PFD_FRAC_MASK
 #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK     (0x400U)
 #define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT    (10U)
-#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK)
+#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SET(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK)
+#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK
 #define USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL_MASK  (0x1800U)
 #define USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL_SHIFT (11U)
-#define USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL_SHIFT)) & USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL_MASK)
+#define USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL_SET(x)(((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL_SHIFT)) & USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL_MASK)
+#define USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL USBPHY_ANACTRL_TOG_EMPH_PULSE_CTRL_MASK
 #define USBPHY_ANACTRL_TOG_EMPH_EN_MASK          (0x2000U)
 #define USBPHY_ANACTRL_TOG_EMPH_EN_SHIFT         (13U)
-#define USBPHY_ANACTRL_TOG_EMPH_EN(x)            (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_EMPH_EN_SHIFT)) & USBPHY_ANACTRL_TOG_EMPH_EN_MASK)
+#define USBPHY_ANACTRL_TOG_EMPH_EN_SET(x)        (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_EMPH_EN_SHIFT)) & USBPHY_ANACTRL_TOG_EMPH_EN_MASK)
+#define USBPHY_ANACTRL_TOG_EMPH_EN USBPHY_ANACTRL_TOG_EMPH_EN_MASK
 #define USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL_MASK    (0xC000U)
 #define USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL_SHIFT   (14U)
-#define USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL_SHIFT)) & USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL_MASK)
+#define USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL_SET(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL_SHIFT)) & USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL_MASK)
+#define USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL USBPHY_ANACTRL_TOG_EMPH_CUR_CTRL_MASK
 #define USBPHY_ANACTRL_TOG_PFD_STABLE_MASK       (0x80000000U)
 #define USBPHY_ANACTRL_TOG_PFD_STABLE_SHIFT      (31U)
-#define USBPHY_ANACTRL_TOG_PFD_STABLE(x)         (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_STABLE_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_STABLE_MASK)
+#define USBPHY_ANACTRL_TOG_PFD_STABLE_SET(x)     (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_PFD_STABLE_SHIFT)) & USBPHY_ANACTRL_TOG_PFD_STABLE_MASK)
+#define USBPHY_ANACTRL_TOG_PFD_STABLE USBPHY_ANACTRL_TOG_PFD_STABLE_MASK
 
 /*! @name USB1_LOOPBACK - USB PHY Loopback Control/Status Register */
 #define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK (0x1U)
@@ -16777,10 +20267,12 @@ typedef struct {
 #define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK)
 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK  (0x2U)
 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT (1U)
-#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK)
+#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SET(x)(((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK)
+#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0 USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK
 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK  (0x4U)
 #define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT (2U)
-#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK)
+#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SET(x)(((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK)
+#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1 USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK
 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK (0x8U)
 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT (3U)
 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK)
@@ -16789,22 +20281,27 @@ typedef struct {
 #define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK)
 #define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK     (0x20U)
 #define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT    (5U)
-#define USBPHY_USB1_LOOPBACK_TSTI_TX_EN(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK)
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SET(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK)
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_EN USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK
 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK    (0x40U)
 #define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT   (6U)
-#define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ(x)      (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK)
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SET(x)  (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK)
+#define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK
 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK  (0x80U)
 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT (7U)
-#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK)
+#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SET(x)(((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK)
+#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0 USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK
 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK  (0x100U)
 #define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT (8U)
-#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1(x)    (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK)
+#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SET(x)(((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK)
+#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1 USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK
 #define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK (0x8000U)
 #define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT (15U)
 #define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK)
 #define USBPHY_USB1_LOOPBACK_TSTPKT_MASK         (0xFF0000U)
 #define USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT        (16U)
-#define USBPHY_USB1_LOOPBACK_TSTPKT(x)           (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTPKT_MASK)
+#define USBPHY_USB1_LOOPBACK_TSTPKT_SET(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTPKT_MASK)
+#define USBPHY_USB1_LOOPBACK_TSTPKT USBPHY_USB1_LOOPBACK_TSTPKT_MASK
 
 /*! @name USB1_LOOPBACK_SET - USB PHY Loopback Control/Status Register */
 #define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK (0x1U)
@@ -16839,7 +20336,8 @@ typedef struct {
 #define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK)
 #define USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK     (0xFF0000U)
 #define USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT    (16U)
-#define USBPHY_USB1_LOOPBACK_SET_TSTPKT(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK)
+#define USBPHY_USB1_LOOPBACK_SET_TSTPKT_SET(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK)
+#define USBPHY_USB1_LOOPBACK_SET_TSTPKT USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK
 
 /*! @name USB1_LOOPBACK_CLR - USB PHY Loopback Control/Status Register */
 #define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK (0x1U)
@@ -16874,7 +20372,8 @@ typedef struct {
 #define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK)
 #define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK     (0xFF0000U)
 #define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT    (16U)
-#define USBPHY_USB1_LOOPBACK_CLR_TSTPKT(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SET(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK)
+#define USBPHY_USB1_LOOPBACK_CLR_TSTPKT USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK
 
 /*! @name USB1_LOOPBACK_TOG - USB PHY Loopback Control/Status Register */
 #define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK (0x1U)
@@ -16909,7 +20408,8 @@ typedef struct {
 #define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK)
 #define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK     (0xFF0000U)
 #define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT    (16U)
-#define USBPHY_USB1_LOOPBACK_TOG_TSTPKT(x)       (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SET(x)   (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK)
+#define USBPHY_USB1_LOOPBACK_TOG_TSTPKT USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK
 
 /*! @name USB1_LOOPBACK_HSFSCNT - USB PHY Loopback Packet Number Select Register */
 #define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK (0xFFFFU)
@@ -17081,7 +20581,7 @@ typedef struct {
 /** Peripheral USBPHY base address */
 #define USBPHY_BASE                              (0x400A2000u)
 /** Peripheral USBPHY base pointer */
-#define USBPHY                                   ((USBPHY_Type *)USBPHY_BASE)
+#define USBPHY                                   ((USBPHY_TypeDef *)USBPHY_BASE)
 /** Array initializer of USBPHY peripheral base addresses */
 #define USBPHY_BASE_ADDRS                        { USBPHY_BASE }
 /** Array initializer of USBPHY peripheral base pointers */
@@ -17105,7 +20605,7 @@ typedef struct {
 typedef struct {
   __IO uint8_t TRM;                                /**< VREF Trim Register, offset: 0x0 */
   __IO uint8_t SC;                                 /**< VREF Status and Control Register, offset: 0x1 */
-} VREF_Type;
+} VREF_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- VREF Register Masks
@@ -17119,27 +20619,34 @@ typedef struct {
 /*! @name TRM - VREF Trim Register */
 #define VREF_TRM_TRIM_MASK                       (0x3FU)
 #define VREF_TRM_TRIM_SHIFT                      (0U)
-#define VREF_TRM_TRIM(x)                         (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK)
+#define VREF_TRM_TRIM_SET(x)                     (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK)
+#define VREF_TRM_TRIM VREF_TRM_TRIM_MASK
 #define VREF_TRM_CHOPEN_MASK                     (0x40U)
 #define VREF_TRM_CHOPEN_SHIFT                    (6U)
-#define VREF_TRM_CHOPEN(x)                       (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK)
+#define VREF_TRM_CHOPEN_SET(x)                   (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK)
+#define VREF_TRM_CHOPEN VREF_TRM_CHOPEN_MASK
 
 /*! @name SC - VREF Status and Control Register */
 #define VREF_SC_MODE_LV_MASK                     (0x3U)
 #define VREF_SC_MODE_LV_SHIFT                    (0U)
-#define VREF_SC_MODE_LV(x)                       (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK)
+#define VREF_SC_MODE_LV_SET(x)                   (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK)
+#define VREF_SC_MODE_LV VREF_SC_MODE_LV_MASK
 #define VREF_SC_VREFST_MASK                      (0x4U)
 #define VREF_SC_VREFST_SHIFT                     (2U)
-#define VREF_SC_VREFST(x)                        (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK)
+#define VREF_SC_VREFST_SET(x)                    (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK)
+#define VREF_SC_VREFST VREF_SC_VREFST_MASK
 #define VREF_SC_ICOMPEN_MASK                     (0x20U)
 #define VREF_SC_ICOMPEN_SHIFT                    (5U)
-#define VREF_SC_ICOMPEN(x)                       (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK)
+#define VREF_SC_ICOMPEN_SET(x)                   (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK)
+#define VREF_SC_ICOMPEN VREF_SC_ICOMPEN_MASK
 #define VREF_SC_REGEN_MASK                       (0x40U)
 #define VREF_SC_REGEN_SHIFT                      (6U)
-#define VREF_SC_REGEN(x)                         (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK)
+#define VREF_SC_REGEN_SET(x)                     (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK)
+#define VREF_SC_REGEN VREF_SC_REGEN_MASK
 #define VREF_SC_VREFEN_MASK                      (0x80U)
 #define VREF_SC_VREFEN_SHIFT                     (7U)
-#define VREF_SC_VREFEN(x)                        (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK)
+#define VREF_SC_VREFEN_SET(x)                    (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK)
+#define VREF_SC_VREFEN VREF_SC_VREFEN_MASK
 
 
 /*!
@@ -17151,7 +20658,7 @@ typedef struct {
 /** Peripheral VREF base address */
 #define VREF_BASE                                (0x40074000u)
 /** Peripheral VREF base pointer */
-#define VREF                                     ((VREF_Type *)VREF_BASE)
+#define VREF                                     ((VREF_TypeDef *)VREF_BASE)
 /** Array initializer of VREF peripheral base addresses */
 #define VREF_BASE_ADDRS                          { VREF_BASE }
 /** Array initializer of VREF peripheral base pointers */
@@ -17185,7 +20692,7 @@ typedef struct {
   __IO uint16_t TMROUTL;                           /**< Watchdog Timer Output Register Low, offset: 0x12 */
   __IO uint16_t RSTCNT;                            /**< Watchdog Reset Count register, offset: 0x14 */
   __IO uint16_t PRESC;                             /**< Watchdog Prescaler register, offset: 0x16 */
-} WDOG_Type;
+} WDOG_TypeDef;
 
 /* ----------------------------------------------------------------------------
    -- WDOG Register Masks
@@ -17203,92 +20710,114 @@ typedef struct {
 #define WDOG_STCTRLH_WDOGEN                      WDOG_STCTRLH_WDOGEN_SET(1)
 #define WDOG_STCTRLH_CLKSRC_MASK                 (0x2U)
 #define WDOG_STCTRLH_CLKSRC_SHIFT                (1U)
-#define WDOG_STCTRLH_CLKSRC(x)                   (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK)
+#define WDOG_STCTRLH_CLKSRC_SET(x)               (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK)
+#define WDOG_STCTRLH_CLKSRC WDOG_STCTRLH_CLKSRC_MASK
 #define WDOG_STCTRLH_IRQRSTEN_MASK               (0x4U)
 #define WDOG_STCTRLH_IRQRSTEN_SHIFT              (2U)
-#define WDOG_STCTRLH_IRQRSTEN(x)                 (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK)
+#define WDOG_STCTRLH_IRQRSTEN_SET(x)             (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK)
+#define WDOG_STCTRLH_IRQRSTEN WDOG_STCTRLH_IRQRSTEN_MASK
 #define WDOG_STCTRLH_WINEN_MASK                  (0x8U)
 #define WDOG_STCTRLH_WINEN_SHIFT                 (3U)
-#define WDOG_STCTRLH_WINEN(x)                    (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK)
+#define WDOG_STCTRLH_WINEN_SET(x)                (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK)
+#define WDOG_STCTRLH_WINEN WDOG_STCTRLH_WINEN_MASK
 #define WDOG_STCTRLH_ALLOWUPDATE_MASK            (0x10U)
 #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT           (4U)
-#define WDOG_STCTRLH_ALLOWUPDATE(x)              (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK)
+#define WDOG_STCTRLH_ALLOWUPDATE_SET(x)          (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK)
+#define WDOG_STCTRLH_ALLOWUPDATE WDOG_STCTRLH_ALLOWUPDATE_MASK
 #define WDOG_STCTRLH_DBGEN_MASK                  (0x20U)
 #define WDOG_STCTRLH_DBGEN_SHIFT                 (5U)
-#define WDOG_STCTRLH_DBGEN(x)                    (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK)
+#define WDOG_STCTRLH_DBGEN_SET(x)                (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK)
+#define WDOG_STCTRLH_DBGEN WDOG_STCTRLH_DBGEN_MASK
 #define WDOG_STCTRLH_STOPEN_MASK                 (0x40U)
 #define WDOG_STCTRLH_STOPEN_SHIFT                (6U)
-#define WDOG_STCTRLH_STOPEN(x)                   (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK)
+#define WDOG_STCTRLH_STOPEN_SET(x)               (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK)
+#define WDOG_STCTRLH_STOPEN WDOG_STCTRLH_STOPEN_MASK
 #define WDOG_STCTRLH_WAITEN_MASK                 (0x80U)
 #define WDOG_STCTRLH_WAITEN_SHIFT                (7U)
-#define WDOG_STCTRLH_WAITEN(x)                   (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WAITEN_SHIFT)) & WDOG_STCTRLH_WAITEN_MASK)
+#define WDOG_STCTRLH_WAITEN_SET(x)               (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WAITEN_SHIFT)) & WDOG_STCTRLH_WAITEN_MASK)
+#define WDOG_STCTRLH_WAITEN WDOG_STCTRLH_WAITEN_MASK
 #define WDOG_STCTRLH_TESTWDOG_MASK               (0x400U)
 #define WDOG_STCTRLH_TESTWDOG_SHIFT              (10U)
-#define WDOG_STCTRLH_TESTWDOG(x)                 (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK)
+#define WDOG_STCTRLH_TESTWDOG_SET(x)             (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK)
+#define WDOG_STCTRLH_TESTWDOG WDOG_STCTRLH_TESTWDOG_MASK
 #define WDOG_STCTRLH_TESTSEL_MASK                (0x800U)
 #define WDOG_STCTRLH_TESTSEL_SHIFT               (11U)
-#define WDOG_STCTRLH_TESTSEL(x)                  (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK)
+#define WDOG_STCTRLH_TESTSEL_SET(x)              (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK)
+#define WDOG_STCTRLH_TESTSEL WDOG_STCTRLH_TESTSEL_MASK
 #define WDOG_STCTRLH_BYTESEL_MASK                (0x3000U)
 #define WDOG_STCTRLH_BYTESEL_SHIFT               (12U)
-#define WDOG_STCTRLH_BYTESEL(x)                  (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK)
+#define WDOG_STCTRLH_BYTESEL_SET(x)              (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK)
+#define WDOG_STCTRLH_BYTESEL WDOG_STCTRLH_BYTESEL_MASK
 #define WDOG_STCTRLH_DISTESTWDOG_MASK            (0x4000U)
 #define WDOG_STCTRLH_DISTESTWDOG_SHIFT           (14U)
-#define WDOG_STCTRLH_DISTESTWDOG(x)              (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK)
+#define WDOG_STCTRLH_DISTESTWDOG_SET(x)          (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK)
+#define WDOG_STCTRLH_DISTESTWDOG WDOG_STCTRLH_DISTESTWDOG_MASK
 
 /*! @name STCTRLL - Watchdog Status and Control Register Low */
 #define WDOG_STCTRLL_INTFLG_MASK                 (0x8000U)
 #define WDOG_STCTRLL_INTFLG_SHIFT                (15U)
-#define WDOG_STCTRLL_INTFLG(x)                   (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK)
+#define WDOG_STCTRLL_INTFLG_SET(x)               (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK)
+#define WDOG_STCTRLL_INTFLG WDOG_STCTRLL_INTFLG_MASK
 
 /*! @name TOVALH - Watchdog Time-out Value Register High */
 #define WDOG_TOVALH_TOVALHIGH_MASK               (0xFFFFU)
 #define WDOG_TOVALH_TOVALHIGH_SHIFT              (0U)
-#define WDOG_TOVALH_TOVALHIGH(x)                 (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK)
+#define WDOG_TOVALH_TOVALHIGH_SET(x)             (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK)
+#define WDOG_TOVALH_TOVALHIGH WDOG_TOVALH_TOVALHIGH_MASK
 
 /*! @name TOVALL - Watchdog Time-out Value Register Low */
 #define WDOG_TOVALL_TOVALLOW_MASK                (0xFFFFU)
 #define WDOG_TOVALL_TOVALLOW_SHIFT               (0U)
-#define WDOG_TOVALL_TOVALLOW(x)                  (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK)
+#define WDOG_TOVALL_TOVALLOW_SET(x)              (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK)
+#define WDOG_TOVALL_TOVALLOW WDOG_TOVALL_TOVALLOW_MASK
 
 /*! @name WINH - Watchdog Window Register High */
 #define WDOG_WINH_WINHIGH_MASK                   (0xFFFFU)
 #define WDOG_WINH_WINHIGH_SHIFT                  (0U)
-#define WDOG_WINH_WINHIGH(x)                     (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK)
+#define WDOG_WINH_WINHIGH_SET(x)                 (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK)
+#define WDOG_WINH_WINHIGH WDOG_WINH_WINHIGH_MASK
 
 /*! @name WINL - Watchdog Window Register Low */
 #define WDOG_WINL_WINLOW_MASK                    (0xFFFFU)
 #define WDOG_WINL_WINLOW_SHIFT                   (0U)
-#define WDOG_WINL_WINLOW(x)                      (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK)
+#define WDOG_WINL_WINLOW_SET(x)                  (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK)
+#define WDOG_WINL_WINLOW WDOG_WINL_WINLOW_MASK
 
 /*! @name REFRESH - Watchdog Refresh register */
 #define WDOG_REFRESH_WDOGREFRESH_MASK            (0xFFFFU)
 #define WDOG_REFRESH_WDOGREFRESH_SHIFT           (0U)
-#define WDOG_REFRESH_WDOGREFRESH(x)              (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK)
+#define WDOG_REFRESH_WDOGREFRESH_SET(x)          (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK)
+#define WDOG_REFRESH_WDOGREFRESH WDOG_REFRESH_WDOGREFRESH_MASK
 
 /*! @name UNLOCK - Watchdog Unlock register */
 #define WDOG_UNLOCK_WDOGUNLOCK_MASK              (0xFFFFU)
 #define WDOG_UNLOCK_WDOGUNLOCK_SHIFT             (0U)
-#define WDOG_UNLOCK_WDOGUNLOCK(x)                (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK)
+#define WDOG_UNLOCK_WDOGUNLOCK_SET(x)            (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK)
+#define WDOG_UNLOCK_WDOGUNLOCK WDOG_UNLOCK_WDOGUNLOCK_MASK
 
 /*! @name TMROUTH - Watchdog Timer Output Register High */
 #define WDOG_TMROUTH_TIMEROUTHIGH_MASK           (0xFFFFU)
 #define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT          (0U)
-#define WDOG_TMROUTH_TIMEROUTHIGH(x)             (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK)
+#define WDOG_TMROUTH_TIMEROUTHIGH_SET(x)         (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK)
+#define WDOG_TMROUTH_TIMEROUTHIGH WDOG_TMROUTH_TIMEROUTHIGH_MASK
 
 /*! @name TMROUTL - Watchdog Timer Output Register Low */
 #define WDOG_TMROUTL_TIMEROUTLOW_MASK            (0xFFFFU)
 #define WDOG_TMROUTL_TIMEROUTLOW_SHIFT           (0U)
-#define WDOG_TMROUTL_TIMEROUTLOW(x)              (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK)
+#define WDOG_TMROUTL_TIMEROUTLOW_SET(x)          (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK)
+#define WDOG_TMROUTL_TIMEROUTLOW WDOG_TMROUTL_TIMEROUTLOW_MASK
 
 /*! @name RSTCNT - Watchdog Reset Count register */
 #define WDOG_RSTCNT_RSTCNT_MASK                  (0xFFFFU)
 #define WDOG_RSTCNT_RSTCNT_SHIFT                 (0U)
-#define WDOG_RSTCNT_RSTCNT(x)                    (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK)
+#define WDOG_RSTCNT_RSTCNT_SET(x)                (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK)
+#define WDOG_RSTCNT_RSTCNT WDOG_RSTCNT_RSTCNT_MASK
 
 /*! @name PRESC - Watchdog Prescaler register */
 #define WDOG_PRESC_PRESCVAL_MASK                 (0x700U)
 #define WDOG_PRESC_PRESCVAL_SHIFT                (8U)
-#define WDOG_PRESC_PRESCVAL(x)                   (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK)
+#define WDOG_PRESC_PRESCVAL_SET(x)               (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK)
+#define WDOG_PRESC_PRESCVAL WDOG_PRESC_PRESCVAL_MASK
 
 
 /*!
@@ -17300,7 +20829,7 @@ typedef struct {
 /** Peripheral WDOG base address */
 #define WDOG_BASE                                (0x40052000u)
 /** Peripheral WDOG base pointer */
-#define WDOG                                     ((WDOG_Type *)WDOG_BASE)
+#define WDOG                                     ((WDOG_TypeDef *)WDOG_BASE)
 /** Array initializer of WDOG peripheral base addresses */
 #define WDOG_BASE_ADDRS                          { WDOG_BASE }
 /** Array initializer of WDOG peripheral base pointers */
@@ -17398,21 +20927,26 @@ typedef struct {
 #define FMC_PFB0CR_B0DCE_SHIFT                   FMC_PFB01CR_B0DCE_SHIFT
 #define FMC_PFB0CR_CRC_MASK                      FMC_PFB01CR_CRC_MASK
 #define FMC_PFB0CR_CRC_SHIFT                     FMC_PFB01CR_CRC_SHIFT
-#define FMC_PFB0CR_CRC(x)                        FMC_PFB01CR_CRC(x)
+#define FMC_PFB0CR_CRC_SET(x)                    FMC_PFB01CR_CRC(x)
+#define FMC_PFB0CR_CRC FMC_PFB0CR_CRC_MASK
 #define FMC_PFB0CR_B0MW_MASK                     FMC_PFB01CR_B0MW_MASK
 #define FMC_PFB0CR_B0MW_SHIFT                    FMC_PFB01CR_B0MW_SHIFT
-#define FMC_PFB0CR_B0MW(x)                       FMC_PFB01CR_B0MW(x)
+#define FMC_PFB0CR_B0MW_SET(x)                   FMC_PFB01CR_B0MW(x)
+#define FMC_PFB0CR_B0MW FMC_PFB0CR_B0MW_MASK
 #define FMC_PFB0CR_S_B_INV_MASK                  FMC_PFB01CR_S_B_INV_MASK
 #define FMC_PFB0CR_S_B_INV_SHIFT                 FMC_PFB01CR_S_B_INV_SHIFT
 #define FMC_PFB0CR_CINV_WAY_MASK                 FMC_PFB01CR_CINV_WAY_MASK
 #define FMC_PFB0CR_CINV_WAY_SHIFT                FMC_PFB01CR_CINV_WAY_SHIFT
-#define FMC_PFB0CR_CINV_WAY(x)                   FMC_PFB01CR_CINV_WAY(x)
+#define FMC_PFB0CR_CINV_WAY_SET(x)               FMC_PFB01CR_CINV_WAY(x)
+#define FMC_PFB0CR_CINV_WAY FMC_PFB0CR_CINV_WAY_MASK
 #define FMC_PFB0CR_CLCK_WAY_MASK                 FMC_PFB01CR_CLCK_WAY_MASK
 #define FMC_PFB0CR_CLCK_WAY_SHIFT                FMC_PFB01CR_CLCK_WAY_SHIFT
-#define FMC_PFB0CR_CLCK_WAY(x)                   FMC_PFB01CR_CLCK_WAY(x)
+#define FMC_PFB0CR_CLCK_WAY_SET(x)               FMC_PFB01CR_CLCK_WAY(x)
+#define FMC_PFB0CR_CLCK_WAY FMC_PFB0CR_CLCK_WAY_MASK
 #define FMC_PFB0CR_B0RWSC_MASK                   FMC_PFB01CR_B0RWSC_MASK
 #define FMC_PFB0CR_B0RWSC_SHIFT                  FMC_PFB01CR_B0RWSC_SHIFT
-#define FMC_PFB0CR_B0RWSC(x)                     FMC_PFB01CR_B0RWSC(x)
+#define FMC_PFB0CR_B0RWSC_SET(x)                 FMC_PFB01CR_B0RWSC(x)
+#define FMC_PFB0CR_B0RWSC FMC_PFB0CR_B0RWSC_MASK
 #define FMC_PFB1CR_RFU_MASK                      FMC_PFB23CR_RFU_MASK
 #define FMC_PFB1CR_RFU_SHIFT                     FMC_PFB23CR_RFU_SHIFT
 #define FMC_PFB1CR_B1IPE_MASK                    FMC_PFB23CR_B1IPE_MASK
@@ -17425,20 +20959,24 @@ typedef struct {
 #define FMC_PFB1CR_B1DCE_SHIFT                   FMC_PFB23CR_B1DCE_SHIFT
 #define FMC_PFB1CR_B1MW_MASK                     FMC_PFB23CR_B1MW_MASK
 #define FMC_PFB1CR_B1MW_SHIFT                    FMC_PFB23CR_B1MW_SHIFT
-#define FMC_PFB1CR_B1MW(x)                       FMC_PFB23CR_B1MW(x)
+#define FMC_PFB1CR_B1MW_SET(x)                   FMC_PFB23CR_B1MW(x)
+#define FMC_PFB1CR_B1MW FMC_PFB1CR_B1MW_MASK
 #define FMC_PFB1CR_B1RWSC_MASK                   FMC_PFB23CR_B1RWSC_MASK
 #define FMC_PFB1CR_B1RWSC_SHIFT                  FMC_PFB23CR_B1RWSC_SHIFT
-#define FMC_PFB1CR_B1RWSC(x)                     FMC_PFB23CR_B1RWSC(x)
+#define FMC_PFB1CR_B1RWSC_SET(x)                 FMC_PFB23CR_B1RWSC(x)
+#define FMC_PFB1CR_B1RWSC FMC_PFB1CR_B1RWSC_MASK
 #define LLWU_PE8_WUPE130_MASK                    LLWU_PE8_WUPE30_MASK
 #define LLWU_PE8_WUPE130_SHIFT                   LLWU_PE8_WUPE30_SHIFT
-#define LLWU_PE8_WUPE130(x)                      LLWU_PE8_WUPE30(x)
+#define LLWU_PE8_WUPE130_SET(x)                  LLWU_PE8_WUPE30(x)
+#define LLWU_PE8_WUPE130 LLWU_PE8_WUPE130_MASK
 #define MCG_C2_EREFS0_MASK                       MCG_C2_EREFS_MASK
 #define MCG_C2_EREFS0_SHIFT                      MCG_C2_EREFS_SHIFT
 #define MCG_C2_HGO0_MASK                         MCG_C2_HGO_MASK
 #define MCG_C2_HGO0_SHIFT                        MCG_C2_HGO_SHIFT
 #define MCG_C2_RANGE0_MASK                       MCG_C2_RANGE_MASK
 #define MCG_C2_RANGE0_SHIFT                      MCG_C2_RANGE_SHIFT
-#define MCG_C2_RANGE0(x)                         MCG_C2_RANGE(x)
+#define MCG_C2_RANGE0_SET(x)                     MCG_C2_RANGE(x)
+#define MCG_C2_RANGE0 MCG_C2_RANGE0_MASK
 #define PMC_REGSC_BGBDS_MASK                     This_symbol_has_been_deprecated
 #define PMC_REGSC_BGBDS_SHIFT                    This_symbol_has_been_deprecated
 #define SDHC_VENDOR_EXTDMAEN_MASK                This_symbol_has_been_deprecated
@@ -17449,132 +20987,156 @@ typedef struct {
 #define SDRAM_CTRL_NAM_SHIFT                     This_symbol_has_been_deprecated
 #define SMC_STOPCTRL_LPOPO_MASK                  This_symbol_has_been_deprecated
 #define SMC_STOPCTRL_LPOPO_SHIFT                 This_symbol_has_been_deprecated
-#define UART_C6_CP_MASK                          This_symbol_has_been_deprecated
-#define UART_C6_CP_SHIFT                         This_symbol_has_been_deprecated
-#define UART_C6_CE_MASK                          This_symbol_has_been_deprecated
-#define UART_C6_CE_SHIFT                         This_symbol_has_been_deprecated
-#define UART_C6_TX709_MASK                       This_symbol_has_been_deprecated
-#define UART_C6_TX709_SHIFT                      This_symbol_has_been_deprecated
-#define UART_C6_EN709_MASK                       This_symbol_has_been_deprecated
-#define UART_C6_EN709_SHIFT                      This_symbol_has_been_deprecated
-#define UART_PCTH_PCTH_MASK                      This_symbol_has_been_deprecated
-#define UART_PCTH_PCTH_SHIFT                     This_symbol_has_been_deprecated
-#define UART_PCTH_PCTH(x)                        This_symbol_has_been_deprecated
-#define UART_PCTL_PCTL_MASK                      This_symbol_has_been_deprecated
-#define UART_PCTL_PCTL_SHIFT                     This_symbol_has_been_deprecated
-#define UART_PCTL_PCTL(x)                        This_symbol_has_been_deprecated
-#define UART_IE0_CPTXIE_MASK                     This_symbol_has_been_deprecated
-#define UART_IE0_CPTXIE_SHIFT                    This_symbol_has_been_deprecated
-#define UART_IE0_CTXDIE_MASK                     This_symbol_has_been_deprecated
-#define UART_IE0_CTXDIE_SHIFT                    This_symbol_has_been_deprecated
-#define UART_IE0_RPLOFIE_MASK                    This_symbol_has_been_deprecated
-#define UART_IE0_RPLOFIE_SHIFT                   This_symbol_has_been_deprecated
-#define UART_SDTH_SDTH_MASK                      This_symbol_has_been_deprecated
-#define UART_SDTH_SDTH_SHIFT                     This_symbol_has_been_deprecated
-#define UART_SDTH_SDTH(x)                        This_symbol_has_been_deprecated
-#define UART_SDTL_SDTL_MASK                      This_symbol_has_been_deprecated
-#define UART_SDTL_SDTL_SHIFT                     This_symbol_has_been_deprecated
-#define UART_SDTL_SDTL(x)                        This_symbol_has_been_deprecated
-#define UART_PRE_PREAMBLE_MASK                   This_symbol_has_been_deprecated
-#define UART_PRE_PREAMBLE_SHIFT                  This_symbol_has_been_deprecated
-#define UART_PRE_PREAMBLE(x)                     This_symbol_has_been_deprecated
-#define UART_TPL_TPL_MASK                        This_symbol_has_been_deprecated
-#define UART_TPL_TPL_SHIFT                       This_symbol_has_been_deprecated
-#define UART_TPL_TPL(x)                          This_symbol_has_been_deprecated
-#define UART_IE_TXDIE_MASK                       This_symbol_has_been_deprecated
-#define UART_IE_TXDIE_SHIFT                      This_symbol_has_been_deprecated
-#define UART_IE_PSIE_MASK                        This_symbol_has_been_deprecated
-#define UART_IE_PSIE_SHIFT                       This_symbol_has_been_deprecated
-#define UART_IE_PCTEIE_MASK                      This_symbol_has_been_deprecated
-#define UART_IE_PCTEIE_SHIFT                     This_symbol_has_been_deprecated
-#define UART_IE_PTXIE_MASK                       This_symbol_has_been_deprecated
-#define UART_IE_PTXIE_SHIFT                      This_symbol_has_been_deprecated
-#define UART_IE_PRXIE_MASK                       This_symbol_has_been_deprecated
-#define UART_IE_PRXIE_SHIFT                      This_symbol_has_been_deprecated
-#define UART_IE_ISDIE_MASK                       This_symbol_has_been_deprecated
-#define UART_IE_ISDIE_SHIFT                      This_symbol_has_been_deprecated
-#define UART_IE_WBEIE_MASK                       This_symbol_has_been_deprecated
-#define UART_IE_WBEIE_SHIFT                      This_symbol_has_been_deprecated
-#define UART_IE_PEIE_MASK                        This_symbol_has_been_deprecated
-#define UART_IE_PEIE_SHIFT                       This_symbol_has_been_deprecated
-#define UART_WB_WBASE_MASK                       This_symbol_has_been_deprecated
-#define UART_WB_WBASE_SHIFT                      This_symbol_has_been_deprecated
-#define UART_WB_WBASE(x)                         This_symbol_has_been_deprecated
-#define UART_S3_TXFF_MASK                        This_symbol_has_been_deprecated
-#define UART_S3_TXFF_SHIFT                       This_symbol_has_been_deprecated
-#define UART_S3_PSF_MASK                         This_symbol_has_been_deprecated
-#define UART_S3_PSF_SHIFT                        This_symbol_has_been_deprecated
-#define UART_S3_PCTEF_MASK                       This_symbol_has_been_deprecated
-#define UART_S3_PCTEF_SHIFT                      This_symbol_has_been_deprecated
-#define UART_S3_PTXF_MASK                        This_symbol_has_been_deprecated
-#define UART_S3_PTXF_SHIFT                       This_symbol_has_been_deprecated
-#define UART_S3_PRXF_MASK                        This_symbol_has_been_deprecated
-#define UART_S3_PRXF_SHIFT                       This_symbol_has_been_deprecated
-#define UART_S3_ISD_MASK                         This_symbol_has_been_deprecated
-#define UART_S3_ISD_SHIFT                        This_symbol_has_been_deprecated
-#define UART_S3_WBEF_MASK                        This_symbol_has_been_deprecated
-#define UART_S3_WBEF_SHIFT                       This_symbol_has_been_deprecated
-#define UART_S3_PEF_MASK                         This_symbol_has_been_deprecated
-#define UART_S3_PEF_SHIFT                        This_symbol_has_been_deprecated
-#define UART_S4_FE_MASK                          This_symbol_has_been_deprecated
-#define UART_S4_FE_SHIFT                         This_symbol_has_been_deprecated
-#define UART_S4_TXDF_MASK                        This_symbol_has_been_deprecated
-#define UART_S4_TXDF_SHIFT                       This_symbol_has_been_deprecated
-#define UART_S4_CDET_MASK                        This_symbol_has_been_deprecated
-#define UART_S4_CDET_SHIFT                       This_symbol_has_been_deprecated
-#define UART_S4_CDET(x)                          This_symbol_has_been_deprecated
-#define UART_S4_RPLOF_MASK                       This_symbol_has_been_deprecated
-#define UART_S4_RPLOF_SHIFT                      This_symbol_has_been_deprecated
-#define UART_S4_LNF_MASK                         This_symbol_has_been_deprecated
-#define UART_S4_LNF_SHIFT                        This_symbol_has_been_deprecated
-#define UART_RPL_RPL_MASK                        This_symbol_has_been_deprecated
-#define UART_RPL_RPL_SHIFT                       This_symbol_has_been_deprecated
-#define UART_RPL_RPL(x)                          This_symbol_has_been_deprecated
-#define UART_RPREL_RPREL_MASK                    This_symbol_has_been_deprecated
-#define UART_RPREL_RPREL_SHIFT                   This_symbol_has_been_deprecated
-#define UART_RPREL_RPREL(x)                      This_symbol_has_been_deprecated
-#define UART_CPW_CPW_MASK                        This_symbol_has_been_deprecated
-#define UART_CPW_CPW_SHIFT                       This_symbol_has_been_deprecated
-#define UART_CPW_CPW(x)                          This_symbol_has_been_deprecated
-#define UART_RIDTH_RIDTH_MASK                    This_symbol_has_been_deprecated
-#define UART_RIDTH_RIDTH_SHIFT                   This_symbol_has_been_deprecated
-#define UART_RIDTH_RIDTH(x)                      This_symbol_has_been_deprecated
-#define UART_RIDTL_RIDTL_MASK                    This_symbol_has_been_deprecated
-#define UART_RIDTL_RIDTL_SHIFT                   This_symbol_has_been_deprecated
-#define UART_RIDTL_RIDTL(x)                      This_symbol_has_been_deprecated
-#define UART_TIDTH_TIDTH_MASK                    This_symbol_has_been_deprecated
-#define UART_TIDTH_TIDTH_SHIFT                   This_symbol_has_been_deprecated
-#define UART_TIDTH_TIDTH(x)                      This_symbol_has_been_deprecated
-#define UART_TIDTL_TIDTL_MASK                    This_symbol_has_been_deprecated
-#define UART_TIDTL_TIDTL_SHIFT                   This_symbol_has_been_deprecated
-#define UART_TIDTL_TIDTL(x)                      This_symbol_has_been_deprecated
-#define UART_RB1TH_RB1TH_MASK                    This_symbol_has_been_deprecated
-#define UART_RB1TH_RB1TH_SHIFT                   This_symbol_has_been_deprecated
-#define UART_RB1TH_RB1TH(x)                      This_symbol_has_been_deprecated
-#define UART_RB1TL_RB1TL_MASK                    This_symbol_has_been_deprecated
-#define UART_RB1TL_RB1TL_SHIFT                   This_symbol_has_been_deprecated
-#define UART_RB1TL_RB1TL(x)                      This_symbol_has_been_deprecated
-#define UART_TB1TH_TB1TH_MASK                    This_symbol_has_been_deprecated
-#define UART_TB1TH_TB1TH_SHIFT                   This_symbol_has_been_deprecated
-#define UART_TB1TH_TB1TH(x)                      This_symbol_has_been_deprecated
-#define UART_TB1TL_TB1TL_MASK                    This_symbol_has_been_deprecated
-#define UART_TB1TL_TB1TL_SHIFT                   This_symbol_has_been_deprecated
-#define UART_TB1TL_TB1TL(x)                      This_symbol_has_been_deprecated
-#define UART_PROG_REG_MIN_DMC1_MASK              This_symbol_has_been_deprecated
-#define UART_PROG_REG_MIN_DMC1_SHIFT             This_symbol_has_been_deprecated
-#define UART_PROG_REG_MIN_DMC1(x)                This_symbol_has_been_deprecated
-#define UART_PROG_REG_LCV_LEN_MASK               This_symbol_has_been_deprecated
-#define UART_PROG_REG_LCV_LEN_SHIFT              This_symbol_has_been_deprecated
-#define UART_PROG_REG_LCV_LEN(x)                 This_symbol_has_been_deprecated
-#define UART_STATE_REG_SM_STATE_MASK             This_symbol_has_been_deprecated
-#define UART_STATE_REG_SM_STATE_SHIFT            This_symbol_has_been_deprecated
-#define UART_STATE_REG_SM_STATE(x)               This_symbol_has_been_deprecated
-#define UART_STATE_REG_TX_STATE_MASK             This_symbol_has_been_deprecated
-#define UART_STATE_REG_TX_STATE_SHIFT            This_symbol_has_been_deprecated
-#define UART_STATE_REG_TX_STATE(x)               This_symbol_has_been_deprecated
+#define UARTx_C6_CP_MASK                          This_symbol_has_been_deprecated
+#define UARTx_C6_CP_SHIFT                         This_symbol_has_been_deprecated
+#define UARTx_C6_CE_MASK                          This_symbol_has_been_deprecated
+#define UARTx_C6_CE_SHIFT                         This_symbol_has_been_deprecated
+#define UARTx_C6_TX709_MASK                       This_symbol_has_been_deprecated
+#define UARTx_C6_TX709_SHIFT                      This_symbol_has_been_deprecated
+#define UARTx_C6_EN709_MASK                       This_symbol_has_been_deprecated
+#define UARTx_C6_EN709_SHIFT                      This_symbol_has_been_deprecated
+#define UARTx_PCTH_PCTH_MASK                      This_symbol_has_been_deprecated
+#define UARTx_PCTH_PCTH_SHIFT                     This_symbol_has_been_deprecated
+#define UARTx_PCTH_PCTH_SET(x)                    This_symbol_has_been_deprecated
+#define UARTx_PCTH_PCTH UARTx_PCTH_PCTH_MASK
+#define UARTx_PCTL_PCTL_MASK                      This_symbol_has_been_deprecated
+#define UARTx_PCTL_PCTL_SHIFT                     This_symbol_has_been_deprecated
+#define UARTx_PCTL_PCTL_SET(x)                    This_symbol_has_been_deprecated
+#define UARTx_PCTL_PCTL UARTx_PCTL_PCTL_MASK
+#define UARTx_IE0_CPTXIE_MASK                     This_symbol_has_been_deprecated
+#define UARTx_IE0_CPTXIE_SHIFT                    This_symbol_has_been_deprecated
+#define UARTx_IE0_CTXDIE_MASK                     This_symbol_has_been_deprecated
+#define UARTx_IE0_CTXDIE_SHIFT                    This_symbol_has_been_deprecated
+#define UARTx_IE0_RPLOFIE_MASK                    This_symbol_has_been_deprecated
+#define UARTx_IE0_RPLOFIE_SHIFT                   This_symbol_has_been_deprecated
+#define UARTx_SDTH_SDTH_MASK                      This_symbol_has_been_deprecated
+#define UARTx_SDTH_SDTH_SHIFT                     This_symbol_has_been_deprecated
+#define UARTx_SDTH_SDTH_SET(x)                    This_symbol_has_been_deprecated
+#define UARTx_SDTH_SDTH UARTx_SDTH_SDTH_MASK
+#define UARTx_SDTL_SDTL_MASK                      This_symbol_has_been_deprecated
+#define UARTx_SDTL_SDTL_SHIFT                     This_symbol_has_been_deprecated
+#define UARTx_SDTL_SDTL_SET(x)                    This_symbol_has_been_deprecated
+#define UARTx_SDTL_SDTL UARTx_SDTL_SDTL_MASK
+#define UARTx_PRE_PREAMBLE_MASK                   This_symbol_has_been_deprecated
+#define UARTx_PRE_PREAMBLE_SHIFT                  This_symbol_has_been_deprecated
+#define UARTx_PRE_PREAMBLE_SET(x)                 This_symbol_has_been_deprecated
+#define UARTx_PRE_PREAMBLE UARTx_PRE_PREAMBLE_MASK
+#define UARTx_TPL_TPL_MASK                        This_symbol_has_been_deprecated
+#define UARTx_TPL_TPL_SHIFT                       This_symbol_has_been_deprecated
+#define UARTx_TPL_TPL_SET(x)                      This_symbol_has_been_deprecated
+#define UARTx_TPL_TPL UARTx_TPL_TPL_MASK
+#define UARTx_IE_TXDIE_MASK                       This_symbol_has_been_deprecated
+#define UARTx_IE_TXDIE_SHIFT                      This_symbol_has_been_deprecated
+#define UARTx_IE_PSIE_MASK                        This_symbol_has_been_deprecated
+#define UARTx_IE_PSIE_SHIFT                       This_symbol_has_been_deprecated
+#define UARTx_IE_PCTEIE_MASK                      This_symbol_has_been_deprecated
+#define UARTx_IE_PCTEIE_SHIFT                     This_symbol_has_been_deprecated
+#define UARTx_IE_PTXIE_MASK                       This_symbol_has_been_deprecated
+#define UARTx_IE_PTXIE_SHIFT                      This_symbol_has_been_deprecated
+#define UARTx_IE_PRXIE_MASK                       This_symbol_has_been_deprecated
+#define UARTx_IE_PRXIE_SHIFT                      This_symbol_has_been_deprecated
+#define UARTx_IE_ISDIE_MASK                       This_symbol_has_been_deprecated
+#define UARTx_IE_ISDIE_SHIFT                      This_symbol_has_been_deprecated
+#define UARTx_IE_WBEIE_MASK                       This_symbol_has_been_deprecated
+#define UARTx_IE_WBEIE_SHIFT                      This_symbol_has_been_deprecated
+#define UARTx_IE_PEIE_MASK                        This_symbol_has_been_deprecated
+#define UARTx_IE_PEIE_SHIFT                       This_symbol_has_been_deprecated
+#define UARTx_WB_WBASE_MASK                       This_symbol_has_been_deprecated
+#define UARTx_WB_WBASE_SHIFT                      This_symbol_has_been_deprecated
+#define UARTx_WB_WBASE_SET(x)                     This_symbol_has_been_deprecated
+#define UARTx_WB_WBASE UARTx_WB_WBASE_MASK
+#define UARTx_S3_TXFF_MASK                        This_symbol_has_been_deprecated
+#define UARTx_S3_TXFF_SHIFT                       This_symbol_has_been_deprecated
+#define UARTx_S3_PSF_MASK                         This_symbol_has_been_deprecated
+#define UARTx_S3_PSF_SHIFT                        This_symbol_has_been_deprecated
+#define UARTx_S3_PCTEF_MASK                       This_symbol_has_been_deprecated
+#define UARTx_S3_PCTEF_SHIFT                      This_symbol_has_been_deprecated
+#define UARTx_S3_PTXF_MASK                        This_symbol_has_been_deprecated
+#define UARTx_S3_PTXF_SHIFT                       This_symbol_has_been_deprecated
+#define UARTx_S3_PRXF_MASK                        This_symbol_has_been_deprecated
+#define UARTx_S3_PRXF_SHIFT                       This_symbol_has_been_deprecated
+#define UARTx_S3_ISD_MASK                         This_symbol_has_been_deprecated
+#define UARTx_S3_ISD_SHIFT                        This_symbol_has_been_deprecated
+#define UARTx_S3_WBEF_MASK                        This_symbol_has_been_deprecated
+#define UARTx_S3_WBEF_SHIFT                       This_symbol_has_been_deprecated
+#define UARTx_S3_PEF_MASK                         This_symbol_has_been_deprecated
+#define UARTx_S3_PEF_SHIFT                        This_symbol_has_been_deprecated
+#define UARTx_S4_FE_MASK                          This_symbol_has_been_deprecated
+#define UARTx_S4_FE_SHIFT                         This_symbol_has_been_deprecated
+#define UARTx_S4_TXDF_MASK                        This_symbol_has_been_deprecated
+#define UARTx_S4_TXDF_SHIFT                       This_symbol_has_been_deprecated
+#define UARTx_S4_CDET_MASK                        This_symbol_has_been_deprecated
+#define UARTx_S4_CDET_SHIFT                       This_symbol_has_been_deprecated
+#define UARTx_S4_CDET_SET(x)                      This_symbol_has_been_deprecated
+#define UARTx_S4_CDET UARTx_S4_CDET_MASK
+#define UARTx_S4_RPLOF_MASK                       This_symbol_has_been_deprecated
+#define UARTx_S4_RPLOF_SHIFT                      This_symbol_has_been_deprecated
+#define UARTx_S4_LNF_MASK                         This_symbol_has_been_deprecated
+#define UARTx_S4_LNF_SHIFT                        This_symbol_has_been_deprecated
+#define UARTx_RPL_RPL_MASK                        This_symbol_has_been_deprecated
+#define UARTx_RPL_RPL_SHIFT                       This_symbol_has_been_deprecated
+#define UARTx_RPL_RPL_SET(x)                      This_symbol_has_been_deprecated
+#define UARTx_RPL_RPL UARTx_RPL_RPL_MASK
+#define UARTx_RPREL_RPREL_MASK                    This_symbol_has_been_deprecated
+#define UARTx_RPREL_RPREL_SHIFT                   This_symbol_has_been_deprecated
+#define UARTx_RPREL_RPREL_SET(x)                  This_symbol_has_been_deprecated
+#define UARTx_RPREL_RPREL UARTx_RPREL_RPREL_MASK
+#define UARTx_CPW_CPW_MASK                        This_symbol_has_been_deprecated
+#define UARTx_CPW_CPW_SHIFT                       This_symbol_has_been_deprecated
+#define UARTx_CPW_CPW_SET(x)                      This_symbol_has_been_deprecated
+#define UARTx_CPW_CPW UARTx_CPW_CPW_MASK
+#define UARTx_RIDTH_RIDTH_MASK                    This_symbol_has_been_deprecated
+#define UARTx_RIDTH_RIDTH_SHIFT                   This_symbol_has_been_deprecated
+#define UARTx_RIDTH_RIDTH_SET(x)                  This_symbol_has_been_deprecated
+#define UARTx_RIDTH_RIDTH UARTx_RIDTH_RIDTH_MASK
+#define UARTx_RIDTL_RIDTL_MASK                    This_symbol_has_been_deprecated
+#define UARTx_RIDTL_RIDTL_SHIFT                   This_symbol_has_been_deprecated
+#define UARTx_RIDTL_RIDTL_SET(x)                  This_symbol_has_been_deprecated
+#define UARTx_RIDTL_RIDTL UARTx_RIDTL_RIDTL_MASK
+#define UARTx_TIDTH_TIDTH_MASK                    This_symbol_has_been_deprecated
+#define UARTx_TIDTH_TIDTH_SHIFT                   This_symbol_has_been_deprecated
+#define UARTx_TIDTH_TIDTH_SET(x)                  This_symbol_has_been_deprecated
+#define UARTx_TIDTH_TIDTH UARTx_TIDTH_TIDTH_MASK
+#define UARTx_TIDTL_TIDTL_MASK                    This_symbol_has_been_deprecated
+#define UARTx_TIDTL_TIDTL_SHIFT                   This_symbol_has_been_deprecated
+#define UARTx_TIDTL_TIDTL_SET(x)                  This_symbol_has_been_deprecated
+#define UARTx_TIDTL_TIDTL UARTx_TIDTL_TIDTL_MASK
+#define UARTx_RB1TH_RB1TH_MASK                    This_symbol_has_been_deprecated
+#define UARTx_RB1TH_RB1TH_SHIFT                   This_symbol_has_been_deprecated
+#define UARTx_RB1TH_RB1TH_SET(x)                  This_symbol_has_been_deprecated
+#define UARTx_RB1TH_RB1TH UARTx_RB1TH_RB1TH_MASK
+#define UARTx_RB1TL_RB1TL_MASK                    This_symbol_has_been_deprecated
+#define UARTx_RB1TL_RB1TL_SHIFT                   This_symbol_has_been_deprecated
+#define UARTx_RB1TL_RB1TL_SET(x)                  This_symbol_has_been_deprecated
+#define UARTx_RB1TL_RB1TL UARTx_RB1TL_RB1TL_MASK
+#define UARTx_TB1TH_TB1TH_MASK                    This_symbol_has_been_deprecated
+#define UARTx_TB1TH_TB1TH_SHIFT                   This_symbol_has_been_deprecated
+#define UARTx_TB1TH_TB1TH_SET(x)                  This_symbol_has_been_deprecated
+#define UARTx_TB1TH_TB1TH UARTx_TB1TH_TB1TH_MASK
+#define UARTx_TB1TL_TB1TL_MASK                    This_symbol_has_been_deprecated
+#define UARTx_TB1TL_TB1TL_SHIFT                   This_symbol_has_been_deprecated
+#define UARTx_TB1TL_TB1TL_SET(x)                  This_symbol_has_been_deprecated
+#define UARTx_TB1TL_TB1TL UARTx_TB1TL_TB1TL_MASK
+#define UARTx_PROG_REG_MIN_DMC1_MASK              This_symbol_has_been_deprecated
+#define UARTx_PROG_REG_MIN_DMC1_SHIFT             This_symbol_has_been_deprecated
+#define UARTx_PROG_REG_MIN_DMC1_SET(x)            This_symbol_has_been_deprecated
+#define UARTx_PROG_REG_MIN_DMC1 UARTx_PROG_REG_MIN_DMC1_MASK
+#define UARTx_PROG_REG_LCV_LEN_MASK               This_symbol_has_been_deprecated
+#define UARTx_PROG_REG_LCV_LEN_SHIFT              This_symbol_has_been_deprecated
+#define UARTx_PROG_REG_LCV_LEN_SET(x)             This_symbol_has_been_deprecated
+#define UARTx_PROG_REG_LCV_LEN UARTx_PROG_REG_LCV_LEN_MASK
+#define UARTx_STATE_REG_SM_STATE_MASK             This_symbol_has_been_deprecated
+#define UARTx_STATE_REG_SM_STATE_SHIFT            This_symbol_has_been_deprecated
+#define UARTx_STATE_REG_SM_STATE_SET(x)           This_symbol_has_been_deprecated
+#define UARTx_STATE_REG_SM_STATE UARTx_STATE_REG_SM_STATE_MASK
+#define UARTx_STATE_REG_TX_STATE_MASK             This_symbol_has_been_deprecated
+#define UARTx_STATE_REG_TX_STATE_SHIFT            This_symbol_has_been_deprecated
+#define UARTx_STATE_REG_TX_STATE_SET(x)           This_symbol_has_been_deprecated
+#define UARTx_STATE_REG_TX_STATE UARTx_STATE_REG_TX_STATE_MASK
 #define USBx_ADDINFO_IRQNUM_MASK                  This_symbol_has_been_deprecated
 #define USBx_ADDINFO_IRQNUM_SHIFT                 This_symbol_has_been_deprecated
-#define USBx_ADDINFO_IRQNUM(x)                    This_symbol_has_been_deprecated
+#define USBx_ADDINFO_IRQNUM_SET(x)                This_symbol_has_been_deprecated
+#define USBx_ADDINFO_IRQNUM USBx_ADDINFO_IRQNUM_MASK
 #define USBHS_USBSTS_ULPII_MASK                  This_symbol_has_been_deprecated
 #define USBHS_USBSTS_ULPII_SHIFT                 This_symbol_has_been_deprecated
 #define USBHS_USBINTR_ULPIE_MASK                 This_symbol_has_been_deprecated
diff --git a/os/common/startup/ARMCMx/compilers/GCC/ld/MK66FX1M0.ld b/os/common/startup/ARMCMx/compilers/GCC/ld/MK66FX1M0.ld
index c0e2cf2..4032c23 100644
--- a/os/common/startup/ARMCMx/compilers/GCC/ld/MK66FX1M0.ld
+++ b/os/common/startup/ARMCMx/compilers/GCC/ld/MK66FX1M0.ld
@@ -29,14 +29,10 @@ MEMORY
   flash0   : org = 0x00000000, len = 0x400
   flash1   : org = 0x00000400, len = 0x10
   flash2   : org = 0x00000410, len = 1024k - 0x410
-  flash3   : org = 0x00000000, len = 0
-  flash4   : org = 0x00000000, len = 0
-  flash5   : org = 0x00000000, len = 0
-  flash6   : org = 0x00000000, len = 0
-  flash7   : org = 0x00000000, len = 0
-  ram0     : org = 0x1FFF0000, len = 256k
-  ram1     : org = 0x00000000, len = 0
-  ram2     : org = 0x00000000, len = 0
+  flash3   : org = 0x10000000, len = 128k   /* FlexNVM */
+  ram0     : org = 0x1FFF0000, len = 64k    /* SRAM_L (code RAM) */
+  ram1     : org = 0x20000000, len = 192k   /* SRAM_U (data RAM) */
+  ram2     : org = 0x14000000, len = 4k     /* FlexRAM */
   ram3     : org = 0x00000000, len = 0
   ram4     : org = 0x00000000, len = 0
   ram5     : org = 0x00000000, len = 0
@@ -81,21 +77,21 @@ REGION_ALIAS("RAM_INIT_FLASH_LMA", flash2);
 
 /* RAM region to be used for Main stack. This stack accommodates the processing
    of all exceptions and interrupts.*/
-REGION_ALIAS("MAIN_STACK_RAM", ram0);
+REGION_ALIAS("MAIN_STACK_RAM", ram1);
 
 /* RAM region to be used for the process stack. This is the stack used by
    the main() function.*/
-REGION_ALIAS("PROCESS_STACK_RAM", ram0);
+REGION_ALIAS("PROCESS_STACK_RAM", ram1);
 
 /* RAM region to be used for data segment.*/
-REGION_ALIAS("DATA_RAM", ram0);
+REGION_ALIAS("DATA_RAM", ram1);
 REGION_ALIAS("DATA_RAM_LMA", flash2);
 
 /* RAM region to be used for BSS segment.*/
-REGION_ALIAS("BSS_RAM", ram0);
+REGION_ALIAS("BSS_RAM", ram1);
 
 /* RAM region to be used for the default heap.*/
-REGION_ALIAS("HEAP_RAM", ram0);
+REGION_ALIAS("HEAP_RAM", ram1);
 
 /* Generic rules inclusion.*/
 INCLUDE rules.ld
diff --git a/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c b/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c
index a005c32..f615dd5 100644
--- a/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c
+++ b/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c
@@ -442,7 +442,13 @@ static inline msg_t _i2c_txrx_timeout(I2CDriver *i2cp, i2caddr_t addr,
     /* wait until the bus is released */
     /* Calculating the time window for the timeout on the busy bus condition.*/
     start = osalOsGetSystemTimeX();
+#if defined(OSAL_TIME_MS2I)
     end = start + OSAL_TIME_MS2I(KINETIS_I2C_BUSY_TIMEOUT);
+#elif defined(OSAL_TIME_MS2ST)
+    end = start + OSAL_TIME_MS2ST(KINETIS_I2C_BUSY_TIMEOUT);
+#else
+    end = start + OSAL_MS2ST(KINETIS_I2C_BUSY_TIMEOUT);
+#endif
 
     while(true) {
       osalSysLock();
diff --git a/os/hal/ports/KINETIS/LLD/hal_sdc_lld.c b/os/hal/ports/KINETIS/LLD/hal_sdc_lld.c
index 1b19a90..6ba932e 100644
--- a/os/hal/ports/KINETIS/LLD/hal_sdc_lld.c
+++ b/os/hal/ports/KINETIS/LLD/hal_sdc_lld.c
@@ -29,7 +29,7 @@
  * or write).
  *
  * The SDHC signals must be routed to the desired pins, and pullups/pulldowns
- * configured.
+ * configured.
  *
  * @addtogroup SDC
  * @{
@@ -45,8 +45,13 @@
 /* Driver local definitions.                                                 */
 /*===========================================================================*/
 
+#if defined(MK66F18)
+/* Configure SDHC block to use the IRC48M clock */
+#define KINETIS_SDHC_PERIPHERAL_FREQUENCY 48000000UL
+#else
 /* We configure the SDHC block to use the system clock */
 #define KINETIS_SDHC_PERIPHERAL_FREQUENCY KINETIS_SYSCLK_FREQUENCY
+#endif
 
 #ifndef KINETIS_SDHC_PRIORITY
 #define KINETIS_SDHC_PRIORITY 12 /* TODO? Default IRQ priority for SDHC */
@@ -189,6 +194,11 @@ static void enable_clock_when_stable(uint32_t new_sysctl)
 
   /* Restart the clock */
   SDHC->SYSCTL = new_sysctl | SDHC_SYSCTL_SDCLKEN;
+
+  /* Wait for clock to stabilize again */
+  while(!(SDHC->PRSSTAT & SDHC_PRSSTAT_SDSTB)) {
+    osalThreadSleepMilliseconds(1);
+  }
 }
 
 /**
@@ -589,9 +599,15 @@ void sdc_lld_init(void) {
 void sdc_lld_start(SDCDriver *sdcp) {
 
   if (sdcp->state == BLK_STOP) {
+#if defined(MK66F18)
+    /* Use IRC48M clock for SDHC */
+    SIM->SOPT2 |= SIM_SOPT2_SDHCSRC(1);
+    SIM->SOPT2 |= SIM_SOPT2_PLLFLLSEL_SET(3);
+#else
     SIM->SOPT2 =
       (SIM->SOPT2 & ~SIM_SOPT2_SDHCSRC_MASK) |
       SIM_SOPT2_SDHCSRC(0);  /* SDHC clock source 0: Core/system clock. */
+#endif
     SIM->SCGC3 |= SIM_SCGC3_SDHC; /* Enable clock to SDHC peripheral */
 
     /* Reset the SDHC block */
diff --git a/os/hal/ports/KINETIS/LLD/hal_serial_lld.c b/os/hal/ports/KINETIS/LLD/hal_serial_lld.c
index c92fa5c..a1b6632 100644
--- a/os/hal/ports/KINETIS/LLD/hal_serial_lld.c
+++ b/os/hal/ports/KINETIS/LLD/hal_serial_lld.c
@@ -262,7 +262,7 @@ static void configure_uart(SerialDriver *sdp, const SerialConfig *config) {
   }
 #endif /* KINETIS_SERIAL_USE_UART0 */
 
-#elif defined(K20x) || defined(K60x) /* KL2x */
+#elif defined(K20x) || defined(K60x) || defined(MK66F18) /* KL2x */
 
   /* UARTs 0 and 1 are clocked from SYSCLK, others from BUSCLK on K20x and K60x. */
 #if KINETIS_SERIAL_USE_UART0
diff --git a/os/hal/ports/KINETIS/MK66F18/hal_lld.c b/os/hal/ports/KINETIS/MK66F18/hal_lld.c
index bb8991a..c9cd224 100644
--- a/os/hal/ports/KINETIS/MK66F18/hal_lld.c
+++ b/os/hal/ports/KINETIS/MK66F18/hal_lld.c
@@ -15,8 +15,8 @@
 */
 
 /**
- * @file    templates/hal_lld.c
- * @brief   HAL Driver subsystem low level driver source template.
+ * @file    MK66F18/hal_lld.c
+ * @brief   Kinetis MK66F18 HAL Driver subsystem low level driver source template.
  *
  * @addtogroup HAL
  * @{
diff --git a/os/hal/ports/KINETIS/MK66F18/platform.mk b/os/hal/ports/KINETIS/MK66F18/platform.mk
index d66a31d..0e6be12 100644
--- a/os/hal/ports/KINETIS/MK66F18/platform.mk
+++ b/os/hal/ports/KINETIS/MK66F18/platform.mk
@@ -8,6 +8,7 @@ PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \
               ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_ext_lld.c \
               ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_adc_lld.c \
               ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_gpt_lld.c \
+              ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_sdc_lld.c \
               ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/MK66F18/hal_pwm_lld.c \
               ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_st_lld.c \
               ${CHIBIOS_CONTRIB}/os/hal/ports/KINETIS/LLD/hal_usb_lld.c
-- 
cgit v1.2.3


From 8f974a83a514a0e96d0da118c9a28ce16a909783 Mon Sep 17 00:00:00 2001
From: Michael Walker <walkerstop@gmail.com>
Date: Tue, 8 May 2018 07:39:53 -0700
Subject: Adding missing interrupt vector for SDHC on MK66F18 MCU

---
 os/hal/ports/KINETIS/MK66F18/kinetis_registry.h | 4 ++++
 1 file changed, 4 insertions(+)

(limited to 'os')

diff --git a/os/hal/ports/KINETIS/MK66F18/kinetis_registry.h b/os/hal/ports/KINETIS/MK66F18/kinetis_registry.h
index 6634b10..a04012c 100644
--- a/os/hal/ports/KINETIS/MK66F18/kinetis_registry.h
+++ b/os/hal/ports/KINETIS/MK66F18/kinetis_registry.h
@@ -161,6 +161,10 @@
 /* LPTMR attributes.*/
 #define KINETIS_LPTMR0_IRQ_VECTOR   Vector128
 
+/* SDHC (SDC, MMC, SDIO) attributes */
+#define KINETIS_HAS_SDHC            TRUE
+#define KINETIS_SDHC_IRQ_VECTOR     Vector184
+
 /** @} */
 
 #endif /* KINETIS_REGISTRY_H_ */
-- 
cgit v1.2.3


From 5a19c146008b3c98ead0dd9fc03d76ee71312cd5 Mon Sep 17 00:00:00 2001
From: Vitaly Repetenko <vit.repetenko@gmail.com>
Date: Tue, 19 Jun 2018 23:43:34 +0300
Subject: Issue #162: QEI driver macros not defined error fixed

---
 os/hal/include/hal_qei.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'os')

diff --git a/os/hal/include/hal_qei.h b/os/hal/include/hal_qei.h
index ce4a089..15f24ce 100644
--- a/os/hal/include/hal_qei.h
+++ b/os/hal/include/hal_qei.h
@@ -83,10 +83,10 @@ typedef void (*qeicallback_t)(QEIDriver *qeip);
  */
 typedef enum {
   QEI_OVERFLOW_WRAP    = 0,     /**< Counter value will wrap around.        */
-#if QEI_USE_OVERFLOW_DISCARD == TRUE
+#if defined(QEI_USE_OVERFLOW_DISCARD) && QEI_USE_OVERFLOW_DISCARD == TRUE
   QEI_OVERFLOW_DISCARD = 1,     /**< Counter doesn't change.                */
 #endif
-#if QEI_USE_OVERFLOW_MINMAX == TRUE
+#if defined(QEI_USE_OVERFLOW_MINMAX) && QEI_USE_OVERFLOW_MINMAX == TRUE
   QEI_OVERFLOW_MINMAX  = 2,     /**< Counter will be updated upto min or max.*/
 #endif
 } qeioverflow_t;
-- 
cgit v1.2.3


From 6ac9e40dfa171c6093555f3f96c0116229c371ca Mon Sep 17 00:00:00 2001
From: Unknown <dominik.lechner@hale.at>
Date: Thu, 12 Jul 2018 13:58:45 +0200
Subject: Fix STM32 LLD CRCv1 large data bug in DMA mode

* STM32 DMA can only handle 65535 bytes per transfer so larger data sets
   have to split up to be correctly handled when using DMA
---
 os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c | 20 +++++++++++++++-----
 os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.h |  6 ++++++
 2 files changed, 21 insertions(+), 5 deletions(-)

(limited to 'os')

diff --git a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c
index 701b87d..180a383 100755
--- a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c
+++ b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c
@@ -121,9 +121,14 @@ static void crc_lld_serve_interrupt(CRCDriver *crcp, uint32_t flags) {
   /* Stop everything.*/
   dmaStreamDisable(crcp->dma);
 
-  /* Portable CRC ISR code defined in the high level driver, note, it is
-     a macro.*/
-  _crc_isr_code(crcp, crcp->crc->DR ^ crcp->config->final_val);
+  if (crcp->rem_data_size) {
+    /* Start DMA follow up transfer for next data chunk */
+    crc_lld_start_calc(crcp, crcp->rem_data_size,
+      (const void *)crcp->dma->channel->CPAR+0xffff);
+  } else {
+    /* Portable CRC ISR code defined in the high level driver, note, it is a macro.*/
+    _crc_isr_code(crcp, crcp->crc->DR ^ crcp->config->final_val);
+  }
 }
 #endif
 
@@ -308,12 +313,17 @@ uint32_t crc_lld_calc(CRCDriver *crcp, size_t n, const void *buf) {
 
 #if CRC_USE_DMA == TRUE
 void crc_lld_start_calc(CRCDriver *crcp, size_t n, const void *buf) {
+  /* The STM32 DMA can only handle max 65535 bytes per transfer
+   * because it's data count register has only 16 bit. */
+  size_t sz = (n > 0xffff) ? 0xffff : n;
+  crcp->rem_data_size = n-sz;
+
   dmaStreamSetPeripheral(crcp->dma, buf);
   dmaStreamSetMemory0(crcp->dma, &crcp->crc->DR);
 #if STM32_CRC_PROGRAMMABLE == TRUE
-  dmaStreamSetTransactionSize(crcp->dma, n);
+  dmaStreamSetTransactionSize(crcp->dma, sz);
 #else
-  dmaStreamSetTransactionSize(crcp->dma, (n / 4));
+  dmaStreamSetTransactionSize(crcp->dma, (sz / 4));
 #endif
   dmaStreamSetMode(crcp->dma, crcp->dmamode);
 
diff --git a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.h b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.h
index 213d346..e879103 100644
--- a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.h
+++ b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.h
@@ -202,6 +202,12 @@ struct CRCDriver {
    * @brief   Waiting thread.
    */
   thread_reference_t        thread;
+  /**
+   * @brief   Remaining data size.
+   * @note    The DMA can handle only 65535 bytes per transfer because
+   *            it's data count register is only 16 bits wide.
+   */
+  size_t rem_data_size;
   /**
    * @brief CRC DMA stream
    */
-- 
cgit v1.2.3