From d9ee72504f248b7f9edae382ff941453301bf5ad Mon Sep 17 00:00:00 2001 From: Andrew Wygle Date: Sat, 4 Jun 2016 18:26:39 -0700 Subject: Adds ADC12 support to MSP430X port. Adds support for the MSP430X's 12-bit ADC peripheral, as well as reasonably complete testing of same. Also includes fixes for several bugs and cleanup of the DMA peripheral, which used ch calls rather than osal calls and was unclear about what contexts its methods could be called from. --- os/hal/boards/EXP430FR5969/board.c | 6 +++--- os/hal/boards/EXP430FR5969/board.h | 6 ------ os/hal/boards/EXP430FR6989/board.c | 12 ++++++------ os/hal/boards/EXP430FR6989/board.h | 14 +------------- 4 files changed, 10 insertions(+), 28 deletions(-) (limited to 'os/hal/boards') diff --git a/os/hal/boards/EXP430FR5969/board.c b/os/hal/boards/EXP430FR5969/board.c index ac48ba0..0643cce 100644 --- a/os/hal/boards/EXP430FR5969/board.c +++ b/os/hal/boards/EXP430FR5969/board.c @@ -25,11 +25,11 @@ const PALConfig pal_default_config = { {VAL_IOPORT1_OUT, VAL_IOPORT1_DIR, VAL_IOPORT1_REN, VAL_IOPORT1_SEL0, - VAL_IOPORT1_SEL1, VAL_IOPORT1_IES, VAL_IOPORT1_IE}, + VAL_IOPORT1_SEL1}, {VAL_IOPORT2_OUT, VAL_IOPORT2_DIR, VAL_IOPORT2_REN, VAL_IOPORT2_SEL0, - VAL_IOPORT2_SEL1, VAL_IOPORT2_IES, VAL_IOPORT2_IE}, + VAL_IOPORT2_SEL1}, {VAL_IOPORT0_OUT, VAL_IOPORT0_DIR, VAL_IOPORT0_REN, VAL_IOPORT0_SEL0, - VAL_IOPORT0_SEL1, VAL_IOPORT0_IES, VAL_IOPORT0_IE} + VAL_IOPORT0_SEL1} }; /* Set UART TX pin correctly */ #endif /* HAL_USE_PAL */ diff --git a/os/hal/boards/EXP430FR5969/board.h b/os/hal/boards/EXP430FR5969/board.h index 97103d3..3abe1cc 100644 --- a/os/hal/boards/EXP430FR5969/board.h +++ b/os/hal/boards/EXP430FR5969/board.h @@ -65,8 +65,6 @@ #define VAL_IOPORT1_REN 0xFCFE #define VAL_IOPORT1_SEL0 0x0000 #define VAL_IOPORT1_SEL1 0x0300 -#define VAL_IOPORT1_IES 0x0000 -#define VAL_IOPORT1_IE 0x0000 /* * Port B setup: @@ -93,8 +91,6 @@ #define VAL_IOPORT2_REN 0xBDFF #define VAL_IOPORT2_SEL0 0x0000 #define VAL_IOPORT2_SEL1 0x0000 -#define VAL_IOPORT2_IES 0x0000 -#define VAL_IOPORT2_IE 0x0000 /* * Port J setup: @@ -113,8 +109,6 @@ #define VAL_IOPORT0_REN 0x00CF #define VAL_IOPORT0_SEL0 0x0030 #define VAL_IOPORT0_SEL1 0x0000 -#define VAL_IOPORT0_IES 0x0000 -#define VAL_IOPORT0_IE 0x0000 #if !defined(_FROM_ASM_) #ifdef __cplusplus diff --git a/os/hal/boards/EXP430FR6989/board.c b/os/hal/boards/EXP430FR6989/board.c index a6836cf..475a2ea 100644 --- a/os/hal/boards/EXP430FR6989/board.c +++ b/os/hal/boards/EXP430FR6989/board.c @@ -25,17 +25,17 @@ const PALConfig pal_default_config = { {VAL_IOPORT1_OUT, VAL_IOPORT1_DIR, VAL_IOPORT1_REN, VAL_IOPORT1_SEL0, - VAL_IOPORT1_SEL1, VAL_IOPORT1_IES, VAL_IOPORT1_IE}, + VAL_IOPORT1_SEL1}, {VAL_IOPORT2_OUT, VAL_IOPORT2_DIR, VAL_IOPORT2_REN, VAL_IOPORT2_SEL0, - VAL_IOPORT2_SEL1, VAL_IOPORT2_IES, VAL_IOPORT2_IE}, + VAL_IOPORT2_SEL1}, {VAL_IOPORT3_OUT, VAL_IOPORT3_DIR, VAL_IOPORT3_REN, VAL_IOPORT3_SEL0, - VAL_IOPORT3_SEL1, VAL_IOPORT3_IES, VAL_IOPORT3_IE}, + VAL_IOPORT3_SEL1}, {VAL_IOPORT4_OUT, VAL_IOPORT4_DIR, VAL_IOPORT4_REN, VAL_IOPORT4_SEL0, - VAL_IOPORT4_SEL1, VAL_IOPORT4_IES, VAL_IOPORT4_IE}, + VAL_IOPORT4_SEL1}, {VAL_IOPORT5_OUT, VAL_IOPORT5_DIR, VAL_IOPORT5_REN, VAL_IOPORT5_SEL0, - VAL_IOPORT5_SEL1, VAL_IOPORT5_IES, VAL_IOPORT5_IE}, + VAL_IOPORT5_SEL1}, {VAL_IOPORT0_OUT, VAL_IOPORT0_DIR, VAL_IOPORT0_REN, VAL_IOPORT0_SEL0, - VAL_IOPORT0_SEL1, VAL_IOPORT0_IES, VAL_IOPORT0_IE} + VAL_IOPORT0_SEL1} }; /* Set UART TX pin correctly */ #endif /* HAL_USE_PAL */ diff --git a/os/hal/boards/EXP430FR6989/board.h b/os/hal/boards/EXP430FR6989/board.h index 83b8fbb..d5afe29 100644 --- a/os/hal/boards/EXP430FR6989/board.h +++ b/os/hal/boards/EXP430FR6989/board.h @@ -69,8 +69,6 @@ #define VAL_IOPORT1_REN 0xFFFE #define VAL_IOPORT1_SEL0 0x0000 #define VAL_IOPORT1_SEL1 0x0000 -#define VAL_IOPORT1_IES 0x0006 -#define VAL_IOPORT1_IE 0x0006 /* * Port B setup: @@ -97,8 +95,6 @@ #define VAL_IOPORT2_REN 0xFFCF #define VAL_IOPORT2_SEL0 0x0030 #define VAL_IOPORT2_SEL1 0x0000 -#define VAL_IOPORT2_IES 0x0000 -#define VAL_IOPORT2_IE 0x0000 /* * Port C setup: @@ -125,8 +121,6 @@ #define VAL_IOPORT3_REN 0xFFFF #define VAL_IOPORT3_SEL0 0x0000 #define VAL_IOPORT3_SEL1 0x0000 -#define VAL_IOPORT3_IES 0x0000 -#define VAL_IOPORT3_IE 0x0000 /* * Port D setup: @@ -153,11 +147,9 @@ #define VAL_IOPORT4_REN 0xFFFF #define VAL_IOPORT4_SEL0 0x0000 #define VAL_IOPORT4_SEL1 0x0000 -#define VAL_IOPORT4_IES 0x0000 -#define VAL_IOPORT4_IE 0x0000 /* - * Port D setup: + * Port E setup: * * P9.0 - BoosterPack BP27 (input pullup) * P9.1 - BoosterPack BP28 (input pullup) @@ -181,8 +173,6 @@ #define VAL_IOPORT5_REN 0xFF7F #define VAL_IOPORT5_SEL0 0x0000 #define VAL_IOPORT5_SEL1 0x0000 -#define VAL_IOPORT5_IES 0x0000 -#define VAL_IOPORT5_IE 0x0000 /* * Port J setup: @@ -201,8 +191,6 @@ #define VAL_IOPORT0_REN 0x00CF #define VAL_IOPORT0_SEL0 0x0030 #define VAL_IOPORT0_SEL1 0x0000 -#define VAL_IOPORT0_IES 0x0000 -#define VAL_IOPORT0_IE 0x0000 #if !defined(_FROM_ASM_) #ifdef __cplusplus -- cgit v1.2.3 From 707b3a2f97ef9751e42bc377d68ff8479f3ef438 Mon Sep 17 00:00:00 2001 From: Stephane D'Alu Date: Fri, 8 Jul 2016 12:58:25 +0200 Subject: renamed port to NRF5 to make room for NRF52832 chip --- os/hal/boards/NRF51-DK/board.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'os/hal/boards') diff --git a/os/hal/boards/NRF51-DK/board.mk b/os/hal/boards/NRF51-DK/board.mk index 9619bd4..631927b 100644 --- a/os/hal/boards/NRF51-DK/board.mk +++ b/os/hal/boards/NRF51-DK/board.mk @@ -8,4 +8,4 @@ BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/NRF51-DK JLINK_DEVICE = nrf51422 JLINK_PRE_FLASH = w4 4001e504 1 JLINK_ERASE_ALL = w4 4001e504 2\nw4 4001e50c 1\nsleep 100 - +JLINK_PIN_RESET = w4 40000544 1 -- cgit v1.2.3 From ddebbfc5d2ddcde8337ff5f88359770220df9f58 Mon Sep 17 00:00:00 2001 From: Stephane D'Alu Date: Fri, 8 Jul 2016 19:46:51 +0200 Subject: NRF52 board --- os/hal/boards/NRF52-DK/board.c | 81 ++++++++++++++++ os/hal/boards/NRF52-DK/board.h | 201 ++++++++++++++++++++++++++++++++++++++++ os/hal/boards/NRF52-DK/board.mk | 12 +++ 3 files changed, 294 insertions(+) create mode 100644 os/hal/boards/NRF52-DK/board.c create mode 100644 os/hal/boards/NRF52-DK/board.h create mode 100644 os/hal/boards/NRF52-DK/board.mk (limited to 'os/hal/boards') diff --git a/os/hal/boards/NRF52-DK/board.c b/os/hal/boards/NRF52-DK/board.c new file mode 100644 index 0000000..cfbf24d --- /dev/null +++ b/os/hal/boards/NRF52-DK/board.c @@ -0,0 +1,81 @@ +/* + Copyright (C) 2016 Stéphane D'Alu + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +const PALConfig pal_default_config = +{ + .pads = { + PAL_MODE_UNCONNECTED, /* P0.0 : XTAL (32MHz) */ + PAL_MODE_UNCONNECTED, /* P0.1 : XTAL (32MHz) */ + PAL_MODE_UNCONNECTED, /* P0.2 */ + PAL_MODE_UNCONNECTED, /* P0.3 */ + PAL_MODE_UNCONNECTED, /* P0.4 */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.5 : UART_RTS */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.6 : UART_TX */ + PAL_MODE_INPUT_PULLUP, /* P0.7 : UART_CTS */ + PAL_MODE_INPUT_PULLUP, /* P0.8 : UART_RX */ + PAL_MODE_UNCONNECTED, /* P0.9 */ + PAL_MODE_UNCONNECTED, /* P0.10 */ + PAL_MODE_UNCONNECTED, /* P0.11 */ + PAL_MODE_UNCONNECTED, /* P0.12 */ + PAL_MODE_INPUT_PULLUP, /* P0.13: BTN1 */ + PAL_MODE_INPUT_PULLUP, /* P0.14: BTN2 */ + PAL_MODE_INPUT_PULLUP, /* P0.15: BTN3 */ + PAL_MODE_INPUT_PULLUP, /* P0.16: BTN4 */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.17: LED1 */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.18: LED2 */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.19: LED3 */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.20: LED4 */ + PAL_MODE_UNCONNECTED, /* P0.21 */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.22: SPI_SS */ + PAL_MODE_INPUT_PULLUP, /* P0.23: SPI_MISO */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.24: SPI_MOSI */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.25: SPI_SCK */ + PAL_MODE_OUTPUT_OPENDRAIN, /* P0.26: SDA */ + PAL_MODE_OUTPUT_OPENDRAIN, /* P0.27: SCL */ + PAL_MODE_UNCONNECTED, /* P0.28 */ + PAL_MODE_UNCONNECTED, /* P0.29 */ + PAL_MODE_UNCONNECTED, /* P0.30 */ + PAL_MODE_UNCONNECTED, /* P0.31 */ + }, +}; +#endif + +/** + * @brief Early initialization code. + * @details This initialization is performed just after reset before BSS and + * DATA segments initialization. + */ +void __early_init(void) +{ +} + +/** + * @brief Late initialization code. + * @note This initialization is performed after BSS and DATA segments + * initialization and before invoking the main() function. + */ +void boardInit(void) +{ +} diff --git a/os/hal/boards/NRF52-DK/board.h b/os/hal/boards/NRF52-DK/board.h new file mode 100644 index 0000000..ba15fa7 --- /dev/null +++ b/os/hal/boards/NRF52-DK/board.h @@ -0,0 +1,201 @@ +/* + Copyright (C) 2016 Stephane D'Alu + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* Board identifier. */ +#define BOARD_NRF52_DK +#define BOARD_NAME "nRF52 DK" + +/* Board oscillators-related settings. */ +#define NRF52_XTAL_VALUE 64000000 +#define NRF52_LFCLK_SOURCE 1 + +/* + * GPIO pins. + */ +/* Defined by board */ +#define BTN1 13U +#define BTN2 14U +#define BTN3 15U +#define BTN4 16U +#define LED1 17U +#define LED2 18U +#define LED3 19U +#define LED4 20U +#define UART_RTS 5U +#define UART_TX 6U +#define UART_CTS 7U +#define UART_RX 8U +#define NFC1 9U +#define NFC2 10U +#define I2C_SCL 27U +#define I2C_SDA 26U + +/* Our definitions */ +#define SPI_SCK 25U +#define SPI_MOSI 24U +#define SPI_MISO 23U +#define SPI_SS 22U + +/* Analog input */ +#define AIN0 2U +#define AIN1 3U +#define AIN2 4U +#define AIN3 5U +#define AIN4 28U +#define AIN5 29U +#define AIN6 30U +#define AIN7 31U +#define AREF0 AIN0 +#define AREF1 AIN1 + +/* + * IO pins assignments. + */ +/* Defined by board */ +#define IOPORT1_BTN1 13U +#define IOPORT1_BTN2 14U +#define IOPORT1_BTN3 15U +#define IOPORT1_BTN4 16U +#define IOPORT1_LED1 17U +#define IOPORT1_LED2 18U +#define IOPORT1_LED3 19U +#define IOPORT1_LED4 20U +#define IOPORT1_UART_RTS 5U +#define IOPORT1_UART_TX 6U +#define IOPORT1_UART_CTS 7U +#define IOPORT1_UART_RX 8U +#define IOPORT1_NFC1 9U +#define IOPORT1_NFC2 10U +#define IOPORT1_I2C_SCL 27U +#define IOPORT1_I2C_SDA 26U +#define IOPORT1_RESET 21U + +/* Our definitions */ +#define IOPORT1_SPI_SCK 25U +#define IOPORT1_SPI_MOSI 24U +#define IOPORT1_SPI_MISO 23U +#define IOPORT1_SPI_SS 22U + +/* Analog inpupt */ +#define IOPORT1_AIN0 2U +#define IOPORT1_AIN1 3U +#define IOPORT1_AIN2 4U +#define IOPORT1_AIN3 5U +#define IOPORT1_AIN4 28U +#define IOPORT1_AIN5 29U +#define IOPORT1_AIN6 30U +#define IOPORT1_AIN7 31U +#define IOPORT1_AREF0 IOPORT1_AIN0 +#define IOPORT1_AREF1 IOPORT1_AIN1 + +/* Arduino naming */ +#define IOPORT1_A0 3U +#define IOPORT1_A1 4U +#define IOPORT1_A2 28U +#define IOPORT1_A3 39U +#define IOPORT1_A4 30U +#define IOPORT1_A5 31U +#define IOPORT1_D0 11U +#define IOPORT1_D1 12U +#define IOPORT1_D2 13U +#define IOPORT1_D3 14U +#define IOPORT1_D4 15U +#define IOPORT1_D5 16U +#define IOPORT1_D6 17U +#define IOPORT1_D7 18U +#define IOPORT1_D8 19U +#define IOPORT1_D9 20U +#define IOPORT1_D10 22U +#define IOPORT1_D11 23U +#define IOPORT1_D12 24U +#define IOPORT1_D13 25U + + +/* + * IO lines assignments. + */ +/* Board defined */ +#define LINE_BTN1 PAL_LINE(IOPORT1, IOPORT1_BTN1) +#define LINE_BTN2 PAL_LINE(IOPORT1, IOPORT1_BTN2) +#define LINE_BTN3 PAL_LINE(IOPORT1, IOPORT1_BTN3) +#define LINE_BTN4 PAL_LINE(IOPORT1, IOPORT1_BTN4) +#define LINE_LED1 PAL_LINE(IOPORT1, IOPORT1_LED1) +#define LINE_LED2 PAL_LINE(IOPORT1, IOPORT1_LED2) +#define LINE_LED3 PAL_LINE(IOPORT1, IOPORT1_LED3) +#define LINE_LED4 PAL_LINE(IOPORT1, IOPORT1_LED4) +#define LINE_UART_RTS PAL_LINE(IOPORT1, IOPORT1_UART_RTS) +#define LINE_UART_TX PAL_LINE(IOPORT1, IOPORT1_UART_TX) +#define LINE_UART_CTS PAL_LINE(IOPORT1, IOPORT1_UART_CTS) +#define LINE_UART_RX PAL_LINE(IOPORT1, IOPORT1_UART_RX) +#define LINE_NFC1 PAL_LINE(IOPORT1, IOPORT1_NFC1) +#define LINE_NFC2 PAL_LINE(IOPORT1, IOPORT1_NFC2) +#define LINE_I2C_SCL PAL_LINE(IOPORT1, IOPORT1_I2C_SCL) +#define LINE_I2C_SDA PAL_LINE(IOPORT1, IOPORT1_I2C_SDA) + +/* Our definitions */ +#define LINE_SPI_SCK PAL_LINE(IOPORT1, IOPORT1_SPI_SCK) +#define LINE_SPI_MOSI PAL_LINE(IOPORT1, IOPORT1_SPI_MOSI) +#define LINE_SPI_MISO PAL_LINE(IOPORT1, IOPORT1_SPI_MISO) +#define LINE_SPI_SS PAL_LINE(IOPORT1, IOPORT1_SPI_SS) + +/* Analog line */ +#define LINE_AIN0 PAL_LINE(IOPORT1, IOPORT1_AIN0) +#define LINE_AIN1 PAL_LINE(IOPORT1, IOPORT1_AIN1) +#define LINE_AIN2 PAL_LINE(IOPORT1, IOPORT1_AIN2) +#define LINE_AIN3 PAL_LINE(IOPORT1, IOPORT1_AIN3) +#define LINE_AIN4 PAL_LINE(IOPORT1, IOPORT1_AIN4) +#define LINE_AIN5 PAL_LINE(IOPORT1, IOPORT1_AIN5) +#define LINE_AIN6 PAL_LINE(IOPORT1, IOPORT1_AIN6) +#define LINE_AIN7 PAL_LINE(IOPORT1, IOPORT1_AIN7) +#define LINE_AREF0 PAL_LINE(IOPORT1, IOPORT1_AREF0) +#define LINE_AREF1 PAL_LINE(IOPORT1, IOPORT1_AREF1) + +/* Arduino naming */ +#define LINE_A0 PAL_LINE(IOPORT1, IOPORT1_A0) +#define LINE_A1 PAL_LINE(IOPORT1, IOPORT1_A1) +#define LINE_A2 PAL_LINE(IOPORT1, IOPORT1_A2) +#define LINE_A3 PAL_LINE(IOPORT1, IOPORT1_A3) +#define LINE_A4 PAL_LINE(IOPORT1, IOPORT1_A4) +#define LINE_A5 PAL_LINE(IOPORT1, IOPORT1_A5) +#define LINE_D0 PAL_LINE(IOPORT1, IOPORT1_D0) +#define LINE_D1 PAL_LINE(IOPORT1, IOPORT1_D1) +#define LINE_D2 PAL_LINE(IOPORT1, IOPORT1_D2) +#define LINE_D3 PAL_LINE(IOPORT1, IOPORT1_D3) +#define LINE_D4 PAL_LINE(IOPORT1, IOPORT1_D4) +#define LINE_D5 PAL_LINE(IOPORT1, IOPORT1_D5) +#define LINE_D6 PAL_LINE(IOPORT1, IOPORT1_D6) +#define LINE_D7 PAL_LINE(IOPORT1, IOPORT1_D7) +#define LINE_D8 PAL_LINE(IOPORT1, IOPORT1_D8) +#define LINE_D9 PAL_LINE(IOPORT1, IOPORT1_D9) +#define LINE_D10 PAL_LINE(IOPORT1, IOPORT1_D10) +#define LINE_D11 PAL_LINE(IOPORT1, IOPORT1_D11) +#define LINE_D12 PAL_LINE(IOPORT1, IOPORT1_D12) +#define LINE_D13 PAL_LINE(IOPORT1, IOPORT1_D13) + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/os/hal/boards/NRF52-DK/board.mk b/os/hal/boards/NRF52-DK/board.mk new file mode 100644 index 0000000..980fcc7 --- /dev/null +++ b/os/hal/boards/NRF52-DK/board.mk @@ -0,0 +1,12 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/NRF52-DK/board.c + +# Required include directories +BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/NRF52-DK + +# Flash +JLINK_DEVICE = nrf52832 +#JLINK_PRE_FLASH = w4 4001e504 1 +#JLINK_ERASE_ALL = w4 4001e504 2\nw4 4001e50c 1\nsleep 100 +JLINK_PIN_RESET = w4 40000544 1\nsi 0\ntck0\nt0\nsleep 10\nt1 + -- cgit v1.2.3 From 5805e10f74104e3de60470c38d6643d2bdb00fe0 Mon Sep 17 00:00:00 2001 From: Stephane D'Alu Date: Sat, 9 Jul 2016 23:57:48 +0200 Subject: NRF52832 implementation --- os/hal/boards/NRF52-DK/board.mk | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'os/hal/boards') diff --git a/os/hal/boards/NRF52-DK/board.mk b/os/hal/boards/NRF52-DK/board.mk index 980fcc7..4310291 100644 --- a/os/hal/boards/NRF52-DK/board.mk +++ b/os/hal/boards/NRF52-DK/board.mk @@ -5,8 +5,8 @@ BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/NRF52-DK/board.c BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/NRF52-DK # Flash -JLINK_DEVICE = nrf52832 -#JLINK_PRE_FLASH = w4 4001e504 1 +JLINK_DEVICE = nrf52 +JLINK_PRE_FLASH = w4 4001e504 1 #JLINK_ERASE_ALL = w4 4001e504 2\nw4 4001e50c 1\nsleep 100 -JLINK_PIN_RESET = w4 40000544 1\nsi 0\ntck0\nt0\nsleep 10\nt1 +JLINK_PIN_RESET = w4 40000544 1 -- cgit v1.2.3 From 5259158d1727f3703bc90f88d50938eada316f67 Mon Sep 17 00:00:00 2001 From: Stephane D'Alu Date: Sun, 10 Jul 2016 10:48:04 +0200 Subject: renamed NRF51_* to NRF5_* --- os/hal/boards/NRF52-DK/board.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'os/hal/boards') diff --git a/os/hal/boards/NRF52-DK/board.h b/os/hal/boards/NRF52-DK/board.h index ba15fa7..5c7566a 100644 --- a/os/hal/boards/NRF52-DK/board.h +++ b/os/hal/boards/NRF52-DK/board.h @@ -22,8 +22,8 @@ #define BOARD_NAME "nRF52 DK" /* Board oscillators-related settings. */ -#define NRF52_XTAL_VALUE 64000000 -#define NRF52_LFCLK_SOURCE 1 +#define NRF5_XTAL_VALUE 32000000 +#define NRF5_LFCLK_SOURCE 1 /* * GPIO pins. -- cgit v1.2.3 From e1601e0a7d9b805422e511ea1c29ef9f5ca6000b Mon Sep 17 00:00:00 2001 From: barthess Date: Tue, 16 Aug 2016 18:00:59 +0300 Subject: [STM32 NAND] Deleted ugly hack with EXTI interrupt instead of NAND one --- os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h | 18 ++++-------------- 1 file changed, 4 insertions(+), 14 deletions(-) (limited to 'os/hal/boards') diff --git a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h index 05aeceb..0788eb7 100644 --- a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h +++ b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.h @@ -587,19 +587,14 @@ PIN_OSPEED_100M(GPIOD_MEM_D0) | \ PIN_OSPEED_100M(GPIOD_MEM_D1)) -#if STM32_NAND_USE_EXT_INT -#define NAND_RB_NWAIT_PUPDR(pin) (PIN_PUPDR_PULLUP(pin)) -#else -#define NAND_RB_NWAIT_PUPDR(pin) (PIN_PUPDR_FLOATING(pin)) -#endif #define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(GPIOD_MEM_D2) | \ PIN_PUPDR_FLOATING(GPIOD_MEM_D3) | \ PIN_PUPDR_FLOATING(GPIOD_PIN2) | \ PIN_PUPDR_FLOATING(GPIOD_PIN3) | \ PIN_PUPDR_FLOATING(GPIOD_MEM_OE) | \ PIN_PUPDR_FLOATING(GPIOD_MEM_WE) | \ - NAND_RB_NWAIT_PUPDR(GPIOD_NAND_RB_NWAIT) | \ - PIN_PUPDR_PULLUP(GPIOD_NAND_CE1) | \ + PIN_PUPDR_FLOATING(GPIOD_NAND_RB_NWAIT) |\ + PIN_PUPDR_PULLUP(GPIOD_NAND_CE1) | \ PIN_PUPDR_FLOATING(GPIOD_MEM_D13) | \ PIN_PUPDR_FLOATING(GPIOD_MEM_D14) | \ PIN_PUPDR_FLOATING(GPIOD_MEM_D15) | \ @@ -893,21 +888,16 @@ PIN_OSPEED_100M(GPIOG_PIN14) | \ PIN_OSPEED_100M(GPIOG_PIN15)) -#if STM32_NAND_USE_EXT_INT -#define NAND_RB1_PUPDR(pin) (PIN_PUPDR_FLOATING(pin)) -#else -#define NAND_RB1_PUPDR(pin) (PIN_PUPDR_PULLUP(pin)) -#endif #define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(GPIOG_MEM_A10) | \ PIN_PUPDR_FLOATING(GPIOG_MEM_A11) | \ PIN_PUPDR_FLOATING(GPIOG_MEM_A12) | \ PIN_PUPDR_FLOATING(GPIOG_MEM_A13) | \ PIN_PUPDR_FLOATING(GPIOG_MEM_A14) | \ PIN_PUPDR_FLOATING(GPIOG_MEM_A15) | \ - NAND_RB1_PUPDR(GPIOG_NAND_RB1) | \ + PIN_PUPDR_PULLUP(GPIOG_NAND_RB1) | \ PIN_PUPDR_FLOATING(GPIOG_NAND_RB2) | \ PIN_PUPDR_FLOATING(GPIOG_PIN8) | \ - PIN_PUPDR_PULLUP(GPIOG_NAND_CE2) | \ + PIN_PUPDR_PULLUP(GPIOG_NAND_CE2) | \ PIN_PUPDR_FLOATING(GPIOG_PIN10) | \ PIN_PUPDR_FLOATING(GPIOG_PIN11) | \ PIN_PUPDR_FLOATING(GPIOG_SRAM_CS1) | \ -- cgit v1.2.3 From 99a7c1518c8753b1f0a4acdccc9b7d402854f7d3 Mon Sep 17 00:00:00 2001 From: marcoveeneman Date: Wed, 24 Aug 2016 20:42:21 +0200 Subject: Added TivaWare device type to board files and removed old defines. --- os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h | 60 +++-------------------------- os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h | 29 +++----------- 2 files changed, 10 insertions(+), 79 deletions(-) (limited to 'os/hal/boards') diff --git a/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h b/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h index 367dce1..a59235a 100644 --- a/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h +++ b/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h @@ -14,8 +14,8 @@ limitations under the License. */ -#ifndef _BOARD_H_ -#define _BOARD_H_ +#ifndef BOARD_H +#define BOARD_H /* * Setup for Texas Instruments TM4C123G Launchpad Board. @@ -28,59 +28,9 @@ #define BOARD_NAME "Texas Instruments TM4C123G Launchpad" /* - * MCU type + * MCU type as defined in the TI header. */ -//#define TM4C1230C3PM -//#define TM4C1230D5PM -//#define TM4C1230E6PM -//#define TM4C1230H6PM -//#define TM4C1231C3PM -//#define TM4C1231D5PM -//#define TM4C1231D5PZ -//#define TM4C1231E6PM -//#define TM4C1231E6PZ -//#define TM4C1231H6PGE -//#define TM4C1231H6PM -//#define TM4C1231H6PZ -//#define TM4C1232C3PM -//#define TM4C1232D5PM -//#define TM4C1232E6PM -//#define TM4C1232H6PM -//#define TM4C1233C3PM -//#define TM4C1233D5PM -//#define TM4C1233D5PZ -//#define TM4C1233E6PM -//#define TM4C1233E6PZ -//#define TM4C1233H6PGE -//#define TM4C1233H6PM -//#define TM4C1233H6PZ -//#define TM4C1236D5PM -//#define TM4C1236E6PM -//#define TM4C1236H6PM -//#define TM4C1237D5PM -//#define TM4C1237D5PZ -//#define TM4C1237E6PM -//#define TM4C1237E6PZ -//#define TM4C1237H6PGE -//#define TM4C1237H6PM -//#define TM4C1237H6PZ -//#define TM4C123AE6PM -//#define TM4C123AH6PM -//#define TM4C123BE6PM -//#define TM4C123BE6PZ -//#define TM4C123BH6PGE -//#define TM4C123BH6PM -//#define TM4C123BH6PZ -//#define TM4C123BH6ZRB -//#define TM4C123FE6PM -//#define TM4C123FH6PM -//#define TM4C123GE6PM -//#define TM4C123GE6PZ -//#define TM4C123GH6PGE -#define TM4C123GH6PM -//#define TM4C123GH6PZ -//#define TM4C123GH6ZRB -//#define TM4C123GH5ZXR +#define PART_TM4C123GH6PM /* * Board oscillators-related settings. @@ -940,4 +890,4 @@ extern "C" { #endif #endif /* _FROM_ASM_ */ -#endif /* _BOARD_H_ */ +#endif /* BOARD_H */ diff --git a/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h b/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h index 08bb36f..9012f7c 100644 --- a/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h +++ b/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h @@ -14,8 +14,8 @@ limitations under the License. */ -#ifndef _BOARD_H_ -#define _BOARD_H_ +#ifndef BOARD_H +#define BOARD_H /* * Setup for Texas Instruments TM4C1294 Launchpad Board. @@ -36,28 +36,9 @@ //#define BOARD_PHY_RMII /* - * MCU type + * MCU type as defined in the TI header. */ -//#define TM4C1290NCPDT -//#define TM4C1290NCZAD -//#define TM4C1292NCPDT -//#define TM4C1292NCZAD -//#define TM4C1294KCPDT -#define TM4C1294NCPDT -//#define TM4C1294NCZAD -//#define TM4C1297NCZAD -//#define TM4C1299KCZAD -//#define TM4C1299NCZAD -//#define TM4C129CNCPDT -//#define TM4C129CNCZAD -//#define TM4C129DNCPDT -//#define TM4C129DNCZAD -//#define TM4C129EKCPDT -//#define TM4C129ENCPDT -//#define TM4C129ENCZAD -//#define TM4C129LNCZAD -//#define TM4C129XKCZAD -//#define TM4C129XNCZAD +#define PART_TM4C1294NCPDT /* * Board oscillators-related settings. @@ -426,4 +407,4 @@ extern "C" { #endif #endif /* _FROM_ASM_ */ -#endif /* _BOARD_H_ */ +#endif /* BOARD_H */ -- cgit v1.2.3 From d10aa9e7a136e41377f40a774fdf3bffb59b358b Mon Sep 17 00:00:00 2001 From: marcoveeneman Date: Sun, 30 Oct 2016 14:33:58 +0100 Subject: Defined lines in board files. --- os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h | 18 ++++++++++++++++++ os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h | 14 ++++++++++++++ 2 files changed, 32 insertions(+) (limited to 'os/hal/boards') diff --git a/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h b/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h index a59235a..c337e21 100644 --- a/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h +++ b/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h @@ -94,6 +94,24 @@ #define GPIOF_PIN6 6 #define GPIOF_PIN7 7 +/* + * IO lines assignments. + */ +#define LINE_UART0_RX PAL_LINE(GPIOA, 0U) +#define LINE_UART0_TX PAL_LINE(GPIOA, 1U) +#define LINE_SSI0_CLK PAL_LINE(GPIOA, 2U) +#define LINE_SSI0_RX PAL_LINE(GPIOA, 4U) +#define LINE_SSI0_TX PAL_LINE(GPIOA, 5U) + +#define LINE_I2C0_SCL PAL_LINE(GPIOB, 2U) +#define LINE_I2C0_SDA PAL_LINE(GPIOB, 3U) + +#define LINE_SW2 PAL_LINE(GPIOF, 0U) +#define LINE_LED_RED PAL_LINE(GPIOF, 1U) +#define LINE_LED_BLUE PAL_LINE(GPIOF, 2U) +#define LINE_LED_GREEN PAL_LINE(GPIOF, 3U) +#define LINE_SW1 PAL_LINE(GPIOF, 4U) + /* * I/O ports initial setup, this configuration is established soon after reset * in the initialization code. diff --git a/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h b/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h index 9012f7c..982fb1b 100644 --- a/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h +++ b/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h @@ -183,6 +183,20 @@ #define GPIOQ_PIN6 6 #define GPIOQ_PIN7 7 +/* + * IO lines assignments. + */ +#define LINE_UART0_RX PAL_LINE(GPIOA, 0U) +#define LINE_UART0_TX PAL_LINE(GPIOA, 1U) + +#define LINE_LED0 PAL_LINE(GPIOF, 0U) +#define LINE_LED1 PAL_LINE(GPIOF, 4U) + +#define LINE_LED2 PAL_LINE(GPION, 0U) +#define LINE_LED3 PAL_LINE(GPION, 1U) + +#define LINE_SW1 PAL_LINE(GPIOJ, 0U) + /* * I/O ports initial setup, this configuration is established soon after reset * in the initialization code. -- cgit v1.2.3 From 79fc9cfe5dd29e672511e20012e4fa699d07f678 Mon Sep 17 00:00:00 2001 From: marcoveeneman Date: Sun, 30 Oct 2016 14:38:02 +0100 Subject: Added checks and defines for device revisions. This can be used for errata workarounds in the drivers. --- os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h | 3 ++- os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h | 3 ++- 2 files changed, 4 insertions(+), 2 deletions(-) (limited to 'os/hal/boards') diff --git a/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h b/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h index c337e21..7660c09 100644 --- a/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h +++ b/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h @@ -28,9 +28,10 @@ #define BOARD_NAME "Texas Instruments TM4C123G Launchpad" /* - * MCU type as defined in the TI header. + * MCU type and revision as defined in the TI header. */ #define PART_TM4C123GH6PM +#define TARGET_IS_TM4C123_RB1 /* * Board oscillators-related settings. diff --git a/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h b/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h index 982fb1b..57fd268 100644 --- a/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h +++ b/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h @@ -36,9 +36,10 @@ //#define BOARD_PHY_RMII /* - * MCU type as defined in the TI header. + * MCU type and revision as defined in the TI header. */ #define PART_TM4C1294NCPDT +#define TARGET_IS_TM4C129_RA0 /* * Board oscillators-related settings. -- cgit v1.2.3 From 92eafe4186c4b10f991db998cb483edabb0f2ccf Mon Sep 17 00:00:00 2001 From: Stephane D'Alu Date: Wed, 16 Nov 2016 15:17:35 +0100 Subject: BBC micro:bit board --- os/hal/boards/MICROBIT/board.c | 91 +++++++++++++++++++++++++ os/hal/boards/MICROBIT/board.h | 147 ++++++++++++++++++++++++++++++++++++++++ os/hal/boards/MICROBIT/board.mk | 5 ++ 3 files changed, 243 insertions(+) create mode 100644 os/hal/boards/MICROBIT/board.c create mode 100644 os/hal/boards/MICROBIT/board.h create mode 100644 os/hal/boards/MICROBIT/board.mk (limited to 'os/hal/boards') diff --git a/os/hal/boards/MICROBIT/board.c b/os/hal/boards/MICROBIT/board.c new file mode 100644 index 0000000..12f78e2 --- /dev/null +++ b/os/hal/boards/MICROBIT/board.c @@ -0,0 +1,91 @@ +/* + Copyright (C) 2017 Stéphane D'Alu + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/* RAM Banks + * (Values are defined in Nordic gcc_startup_nrf51.s) + */ +#define NRF_POWER_RAMON_ADDRESS 0x40000524 +#define NRF_POWER_RAMONB_ADDRESS 0x40000554 +#define NRF_POWER_RAMONx_RAMxON_ONMODE_Msk 0x3 + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +const PALConfig pal_default_config = +{ + .pads = { + PAL_MODE_OUTPUT_OPENDRAIN, /* P0.0 : SCL P19 */ + PAL_MODE_UNCONNECTED, /* P0.1 : PAD1 P2 */ + PAL_MODE_UNCONNECTED, /* P0.2 : PAD2 P1 */ + PAL_MODE_UNCONNECTED, /* P0.3 : PAD3 P0 */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.4 : COL1 P3 */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.5 : COL2 P4 */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.6 : COL3 P10 */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.7 : COL4 */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.8 : COL5 */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.9 : COL6 */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.10: COL7 P9 */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.11: COL8 P7 */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.12: COL9 P6 */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.13: ROW1 */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.14: ROW2 */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.15: ROW3 */ + PAL_MODE_UNCONNECTED, /* P0.16 P16 */ + PAL_MODE_INPUT, /* P0.17: BTN_A P5 */ + PAL_MODE_UNCONNECTED, /* P0.18 P8 */ + PAL_MODE_INPUT, /* P0.19: BTN_RST */ + PAL_MODE_UNCONNECTED, /* P0.20 P12 */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.21: SPI_MOSI P15 */ + PAL_MODE_INPUT_PULLUP, /* P0.22: SPI_MISO P14 */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.23: SPI_SCK P13 */ + PAL_MODE_OUTPUT_PUSHPULL, /* P0.24: UART_TX */ + PAL_MODE_INPUT_PULLUP, /* P0.25: UART_RX */ + PAL_MODE_INPUT, /* P0.26: BTN_B P11 */ + PAL_MODE_INPUT, /* P0.27: ACC_INT2 */ + PAL_MODE_INPUT, /* P0.28: ACC_INT1 */ + PAL_MODE_INPUT, /* P0.29: MAG_INT1 */ + PAL_MODE_OUTPUT_OPENDRAIN, /* P0.30: SDA P20 */ + PAL_MODE_UNCONNECTED, /* P0.31 */ + }, +}; +#endif + +/** + * @brief Early initialization code. + * @details This initialization is performed just after reset before BSS and + * DATA segments initialization. + */ +void __early_init(void) +{ + /* Make sure ALL RAM banks are powered on */ + *(uint32_t *)NRF_POWER_RAMON_ADDRESS |= NRF_POWER_RAMONx_RAMxON_ONMODE_Msk; + *(uint32_t *)NRF_POWER_RAMONB_ADDRESS |= NRF_POWER_RAMONx_RAMxON_ONMODE_Msk; +} + +/** + * @brief Late initialization code. + * @note This initialization is performed after BSS and DATA segments + * initialization and before invoking the main() function. + */ +void boardInit(void) +{ +} diff --git a/os/hal/boards/MICROBIT/board.h b/os/hal/boards/MICROBIT/board.h new file mode 100644 index 0000000..7798634 --- /dev/null +++ b/os/hal/boards/MICROBIT/board.h @@ -0,0 +1,147 @@ +/* + Copyright (C) 2016 Stephane D'Alu + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * See: https://www.microbit.co.uk/device/pins + * https://lancaster-university.github.io/microbit-docs/ubit/display/ + */ + +/* Board identifier. */ +#define BOARD_MICROBIT +#define BOARD_NAME "micro:bit" + +/* Board oscillators-related settings. */ +#define NRF51_XTAL_VALUE 16000000 +#define NRF51_LFCLK_SOURCE 0 /* RC oscillator */ + +/* + * IO pins assignments. + */ +#define IOPORT1_P0 3U +#define IOPORT1_P1 2U +#define IOPORT1_P2 1U +#define IOPORT1_P3 4U +#define IOPORT1_P4 5U +#define IOPORT1_P5 17U +#define IOPORT1_P6 12U +#define IOPORT1_P7 11U +#define IOPORT1_P8 18U +#define IOPORT1_P9 10U +#define IOPORT1_P10 6U +#define IOPORT1_P11 26U +#define IOPORT1_P12 20U +#define IOPORT1_P13 23U +#define IOPORT1_P14 22U +#define IOPORT1_P15 21U +#define IOPORT1_P16 16U +#define IOPORT1_P19 0U +#define IOPORT1_P20 30U +#define IOPORT1_BTN_A 17U +#define IOPORT1_BTN_B 26U +#define IOPORT1_BTN_RST 19U +#define IOPORT1_LED_COL_1 4U +#define IOPORT1_LED_COL_2 5U +#define IOPORT1_LED_COL_3 6U +#define IOPORT1_LED_COL_4 7U +#define IOPORT1_LED_COL_5 8U +#define IOPORT1_LED_COL_6 9U +#define IOPORT1_LED_COL_7 10U +#define IOPORT1_LED_COL_8 11U +#define IOPORT1_LED_COL_9 12U +#define IOPORT1_LED_ROW_1 13U +#define IOPORT1_LED_ROW_2 14U +#define IOPORT1_LED_ROW_3 15U +#define IOPORT1_PAD_1 1U +#define IOPORT1_PAD_2 2U +#define IOPORT1_PAD_3 3U +#define IOPORT1_SPI_MOSI 21U +#define IOPORT1_SPI_MISO 22U +#define IOPORT1_SPI_SCK 23U +#define IOPORT1_I2C_SCL 0U +#define IOPORT1_I2C_SDA 30U +#define IOPORT1_UART_TX 24U +#define IOPORT1_UART_RX 25U +#define IOPORT1_ACC_INT1 28U +#define IOPORT1_ACC_INT2 27U +#define IOPORT1_MAG_INT1 29U + + +/* + * IO lines assignments. + */ +#define LINE_P0 PAL_LINE(IOPORT1, IOPORT1_P0) +#define LINE_P1 PAL_LINE(IOPORT1, IOPORT1_P1) +#define LINE_P2 PAL_LINE(IOPORT1, IOPORT1_P2) +#define LINE_P3 PAL_LINE(IOPORT1, IOPORT1_P3) +#define LINE_P4 PAL_LINE(IOPORT1, IOPORT1_P4) +#define LINE_P5 PAL_LINE(IOPORT1, IOPORT1_P5) +#define LINE_P6 PAL_LINE(IOPORT1, IOPORT1_P6) +#define LINE_P7 PAL_LINE(IOPORT1, IOPORT1_P7) +#define LINE_P8 PAL_LINE(IOPORT1, IOPORT1_P8) +#define LINE_P9 PAL_LINE(IOPORT1, IOPORT1_P9) +#define LINE_P10 PAL_LINE(IOPORT1, IOPORT1_P10) +#define LINE_P11 PAL_LINE(IOPORT1, IOPORT1_P11) +#define LINE_P12 PAL_LINE(IOPORT1, IOPORT1_P12) +#define LINE_P13 PAL_LINE(IOPORT1, IOPORT1_P13) +#define LINE_P14 PAL_LINE(IOPORT1, IOPORT1_P14) +#define LINE_P15 PAL_LINE(IOPORT1, IOPORT1_P15) +#define LINE_P16 PAL_LINE(IOPORT1, IOPORT1_P16) +#define LINE_P19 PAL_LINE(IOPORT1, IOPORT1_P19) +#define LINE_P20 PAL_LINE(IOPORT1, IOPORT1_P20) +#define LINE_BTN_A PAL_LINE(IOPORT1, IOPORT1_BTN_A) +#define LINE_BTN_B PAL_LINE(IOPORT1, IOPORT1_BTN_B) +#define LINE_BTN_RST PAL_LINE(IOPORT1, IOPORT1_BTN_RST) +#define LINE_LED_COL_1 PAL_LINE(IOPORT1, IOPORT1_LED_COL_1) +#define LINE_LED_COL_2 PAL_LINE(IOPORT1, IOPORT1_LED_COL_2) +#define LINE_LED_COL_3 PAL_LINE(IOPORT1, IOPORT1_LED_COL_3) +#define LINE_LED_COL_4 PAL_LINE(IOPORT1, IOPORT1_LED_COL_4) +#define LINE_LED_COL_5 PAL_LINE(IOPORT1, IOPORT1_LED_COL_5) +#define LINE_LED_COL_6 PAL_LINE(IOPORT1, IOPORT1_LED_COL_6) +#define LINE_LED_COL_7 PAL_LINE(IOPORT1, IOPORT1_LED_COL_7) +#define LINE_LED_COL_8 PAL_LINE(IOPORT1, IOPORT1_LED_COL_8) +#define LINE_LED_COL_9 PAL_LINE(IOPORT1, IOPORT1_LED_COL_9) +#define LINE_LED_ROW_1 PAL_LINE(IOPORT1, IOPORT1_LED_ROW_1) +#define LINE_LED_ROW_2 PAL_LINE(IOPORT1, IOPORT1_LED_ROW_2) +#define LINE_LED_ROW_3 PAL_LINE(IOPORT1, IOPORT1_LED_ROW_3) +#define LINE_PAD_1 PAL_LINE(IOPORT1, IOPORT1_PAD_1) +#define LINE_PAD_2 PAL_LINE(IOPORT1, IOPORT1_PAD_2) +#define LINE_PAD_3 PAL_LINE(IOPORT1, IOPORT1_PAD_3) +#define LINE_SPI_MOSI PAL_LINE(IOPORT1, IOPORT1_SPI_MOSI) +#define LINE_SPI_MISO PAL_LINE(IOPORT1, IOPORT1_SPI_MISO) +#define LINE_SPI_SCK PAL_LINE(IOPORT1, IOPORT1_SPI_SCK) +#define LINE_I2C_SCL PAL_LINE(IOPORT1, IOPORT1_I2C_SCL) +#define LINE_I2C_SDA PAL_LINE(IOPORT1, IOPORT1_I2C_SDA) +#define LINE_UART_TX PAL_LINE(IOPORT1, IOPORT1_UART_TX) +#define LINE_UART_RX PAL_LINE(IOPORT1, IOPORT1_UART_RX) +#define LINE_ACC_INT1 PAL_LINE(IOPORT1, IOPORT1_ACC_INT1) +#define LINE_ACC_INT2 PAL_LINE(IOPORT1, IOPORT1_ACC_INT2) +#define LINE_MAG_INT1 PAL_LINE(IOPORT1, IOPORT1_MAG_INT1) + + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/os/hal/boards/MICROBIT/board.mk b/os/hal/boards/MICROBIT/board.mk new file mode 100644 index 0000000..3595b1a --- /dev/null +++ b/os/hal/boards/MICROBIT/board.mk @@ -0,0 +1,5 @@ +# List of all the board related files. +BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/MICROBIT/board.c + +# Required include directories +BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/MICROBIT -- cgit v1.2.3 From 05b7f823e7f3f029267a4492624d9e190cf406dd Mon Sep 17 00:00:00 2001 From: Stephane D'Alu Date: Sun, 20 Nov 2016 16:05:35 +0100 Subject: corrected pad naming --- os/hal/boards/MICROBIT/board.h | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) (limited to 'os/hal/boards') diff --git a/os/hal/boards/MICROBIT/board.h b/os/hal/boards/MICROBIT/board.h index 7798634..157bd75 100644 --- a/os/hal/boards/MICROBIT/board.h +++ b/os/hal/boards/MICROBIT/board.h @@ -67,9 +67,9 @@ #define IOPORT1_LED_ROW_1 13U #define IOPORT1_LED_ROW_2 14U #define IOPORT1_LED_ROW_3 15U -#define IOPORT1_PAD_1 1U -#define IOPORT1_PAD_2 2U -#define IOPORT1_PAD_3 3U +#define IOPORT1_PAD_0 IOPORT1_P0 +#define IOPORT1_PAD_1 IOPORT1_P1 +#define IOPORT1_PAD_2 IOPORT1_P2 #define IOPORT1_SPI_MOSI 21U #define IOPORT1_SPI_MISO 22U #define IOPORT1_SPI_SCK 23U @@ -119,9 +119,9 @@ #define LINE_LED_ROW_1 PAL_LINE(IOPORT1, IOPORT1_LED_ROW_1) #define LINE_LED_ROW_2 PAL_LINE(IOPORT1, IOPORT1_LED_ROW_2) #define LINE_LED_ROW_3 PAL_LINE(IOPORT1, IOPORT1_LED_ROW_3) +#define LINE_PAD_0 PAL_LINE(IOPORT1, IOPORT1_PAD_0) #define LINE_PAD_1 PAL_LINE(IOPORT1, IOPORT1_PAD_1) #define LINE_PAD_2 PAL_LINE(IOPORT1, IOPORT1_PAD_2) -#define LINE_PAD_3 PAL_LINE(IOPORT1, IOPORT1_PAD_3) #define LINE_SPI_MOSI PAL_LINE(IOPORT1, IOPORT1_SPI_MOSI) #define LINE_SPI_MISO PAL_LINE(IOPORT1, IOPORT1_SPI_MISO) #define LINE_SPI_SCK PAL_LINE(IOPORT1, IOPORT1_SPI_SCK) -- cgit v1.2.3 From 2841fd88cde83b00d79c77e4d5c9441ddd9e22aa Mon Sep 17 00:00:00 2001 From: marcoveeneman Date: Thu, 20 Apr 2017 19:47:50 +0200 Subject: Updated license headers --- os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.c | 2 +- os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h | 2 +- os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.c | 2 +- os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) (limited to 'os/hal/boards') diff --git a/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.c b/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.c index 2bbbc4c..870b4cb 100644 --- a/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.c +++ b/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.c @@ -1,5 +1,5 @@ /* - Copyright (C) 2014..2016 Marco Veeneman + Copyright (C) 2014..2017 Marco Veeneman Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h b/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h index 7660c09..8f2aacf 100644 --- a/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h +++ b/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.h @@ -1,5 +1,5 @@ /* - Copyright (C) 2014..2016 Marco Veeneman + Copyright (C) 2014..2017 Marco Veeneman Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.c b/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.c index 437dcf8..bbfdb88 100644 --- a/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.c +++ b/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.c @@ -1,5 +1,5 @@ /* - Copyright (C) 2014..2016 Marco Veeneman + Copyright (C) 2014..2017 Marco Veeneman Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. diff --git a/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h b/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h index 57fd268..611a580 100644 --- a/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h +++ b/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.h @@ -1,5 +1,5 @@ /* - Copyright (C) 2014..2016 Marco Veeneman + Copyright (C) 2014..2017 Marco Veeneman Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. -- cgit v1.2.3 From ae7a4d40b84d8afc999691577210696f16e682f6 Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Thu, 8 Mar 2018 20:14:13 +0100 Subject: Fixes for STM32F0 testhal --- os/hal/boards/ST_STM32F0308_DISCOVERY/board.c | 162 ++++++++++++++++++++++++-- 1 file changed, 153 insertions(+), 9 deletions(-) (limited to 'os/hal/boards') diff --git a/os/hal/boards/ST_STM32F0308_DISCOVERY/board.c b/os/hal/boards/ST_STM32F0308_DISCOVERY/board.c index dc058f6..3412452 100644 --- a/os/hal/boards/ST_STM32F0308_DISCOVERY/board.c +++ b/os/hal/boards/ST_STM32F0308_DISCOVERY/board.c @@ -1,5 +1,5 @@ /* - ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio Licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License. @@ -14,15 +14,76 @@ limitations under the License. */ +/* + * This file has been automatically generated using ChibiStudio board + * generator plugin. Do not edit manually. + */ + #include "hal.h" +#include "stm32_gpio.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Type of STM32 GPIO port setup. + */ +typedef struct { + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t odr; + uint32_t afrl; + uint32_t afrh; +} gpio_setup_t; + +/** + * @brief Type of STM32 GPIO initialization data. + */ +typedef struct { +#if STM32_HAS_GPIOA || defined(__DOXYGEN__) + gpio_setup_t PAData; +#endif +#if STM32_HAS_GPIOB || defined(__DOXYGEN__) + gpio_setup_t PBData; +#endif +#if STM32_HAS_GPIOC || defined(__DOXYGEN__) + gpio_setup_t PCData; +#endif +#if STM32_HAS_GPIOD || defined(__DOXYGEN__) + gpio_setup_t PDData; +#endif +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) + gpio_setup_t PEData; +#endif +#if STM32_HAS_GPIOF || defined(__DOXYGEN__) + gpio_setup_t PFData; +#endif +#if STM32_HAS_GPIOG || defined(__DOXYGEN__) + gpio_setup_t PGData; +#endif +#if STM32_HAS_GPIOH || defined(__DOXYGEN__) + gpio_setup_t PHData; +#endif +#if STM32_HAS_GPIOI || defined(__DOXYGEN__) + gpio_setup_t PIData; +#endif +} gpio_config_t; -#if HAL_USE_PAL || defined(__DOXYGEN__) /** - * @brief PAL setup. - * @details Digital I/O ports static configuration as defined in @p board.h. - * This variable is used by the HAL when initializing the PAL driver. + * @brief STM32 GPIO static initialization data. */ -const PALConfig pal_default_config = { +static const gpio_config_t gpio_default_config = { #if STM32_HAS_GPIOA {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, @@ -57,21 +118,103 @@ const PALConfig pal_default_config = { #endif #if STM32_HAS_GPIOI {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, - VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH} + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, #endif }; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { + + gpiop->OTYPER = config->otyper; + gpiop->OSPEEDR = config->ospeedr; + gpiop->PUPDR = config->pupdr; + gpiop->ODR = config->odr; + gpiop->AFRL = config->afrl; + gpiop->AFRH = config->afrh; + gpiop->MODER = config->moder; +} + +static void stm32_gpio_init(void) { + + /* Enabling GPIO-related clocks, the mask comes from the + registry header file.*/ + rccResetAHB(STM32_GPIO_EN_MASK); + rccEnableAHB(STM32_GPIO_EN_MASK, true); + + /* Initializing all the defined GPIO ports.*/ +#if STM32_HAS_GPIOA + gpio_init(GPIOA, &gpio_default_config.PAData); +#endif +#if STM32_HAS_GPIOB + gpio_init(GPIOB, &gpio_default_config.PBData); #endif +#if STM32_HAS_GPIOC + gpio_init(GPIOC, &gpio_default_config.PCData); +#endif +#if STM32_HAS_GPIOD + gpio_init(GPIOD, &gpio_default_config.PDData); +#endif +#if STM32_HAS_GPIOE + gpio_init(GPIOE, &gpio_default_config.PEData); +#endif +#if STM32_HAS_GPIOF + gpio_init(GPIOF, &gpio_default_config.PFData); +#endif +#if STM32_HAS_GPIOG + gpio_init(GPIOG, &gpio_default_config.PGData); +#endif +#if STM32_HAS_GPIOH + gpio_init(GPIOH, &gpio_default_config.PHData); +#endif +#if STM32_HAS_GPIOI + gpio_init(GPIOI, &gpio_default_config.PIData); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ /** * @brief Early initialization code. - * @details This initialization must be performed just after stack setup - * and before any other initialization. + * @details GPIO ports and system clocks are initialized before everything + * else. */ void __early_init(void) { + stm32_gpio_init(); stm32_clock_init(); } +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return true; +} + +/** + * @brief SDC card write protection detection. + */ +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif /* HAL_USE_SDC */ + #if HAL_USE_MMC_SPI || defined(__DOXYGEN__) /** * @brief MMC_SPI card detection. @@ -99,4 +242,5 @@ bool mmc_lld_is_write_protected(MMCDriver *mmcp) { * @todo Add your board-specific code, if any. */ void boardInit(void) { + } -- cgit v1.2.3 From 4aa00494c2716285e85246295fb2ed86aa99a4e4 Mon Sep 17 00:00:00 2001 From: marcoveeneman Date: Sat, 10 Mar 2018 14:58:45 +0100 Subject: Added shared variables to startup, board and platform makefiles --- os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk | 4 ++++ os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk | 4 ++++ 2 files changed, 8 insertions(+) (limited to 'os/hal/boards') diff --git a/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk b/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk index 8232a30..22b5467 100644 --- a/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk +++ b/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk @@ -3,3 +3,7 @@ BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.c # Required include directories BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/TI_TM4C123G_LAUNCHPAD + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) diff --git a/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk b/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk index 56298eb..e95de0b 100644 --- a/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk +++ b/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk @@ -3,3 +3,7 @@ BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.c # Required include directories BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/TI_TM4C1294_LAUNCHPAD + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) -- cgit v1.2.3 From 6ca20973e2889ce228b41c47231a5339d8e95970 Mon Sep 17 00:00:00 2001 From: Romain Reignier Date: Mon, 12 Mar 2018 21:15:22 +0100 Subject: boards: Update board BARTHESS to newer API --- .../boards/NONSTANDARD_STM32F4_BARTHESS2/board.c | 189 +++++++++++++++++++-- 1 file changed, 171 insertions(+), 18 deletions(-) (limited to 'os/hal/boards') diff --git a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c index e6c6080..09b44f7 100644 --- a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c +++ b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c @@ -14,45 +14,197 @@ limitations under the License. */ -#include "ch.h" #include "hal.h" +#include "stm32_gpio.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Type of STM32 GPIO port setup. + */ +typedef struct { + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t odr; + uint32_t afrl; + uint32_t afrh; +} gpio_setup_t; + +/** + * @brief Type of STM32 GPIO initialization data. + */ +typedef struct { +#if STM32_HAS_GPIOA || defined(__DOXYGEN__) + gpio_setup_t PAData; +#endif +#if STM32_HAS_GPIOB || defined(__DOXYGEN__) + gpio_setup_t PBData; +#endif +#if STM32_HAS_GPIOC || defined(__DOXYGEN__) + gpio_setup_t PCData; +#endif +#if STM32_HAS_GPIOD || defined(__DOXYGEN__) + gpio_setup_t PDData; +#endif +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) + gpio_setup_t PEData; +#endif +#if STM32_HAS_GPIOF || defined(__DOXYGEN__) + gpio_setup_t PFData; +#endif +#if STM32_HAS_GPIOG || defined(__DOXYGEN__) + gpio_setup_t PGData; +#endif +#if STM32_HAS_GPIOH || defined(__DOXYGEN__) + gpio_setup_t PHData; +#endif +#if STM32_HAS_GPIOI || defined(__DOXYGEN__) + gpio_setup_t PIData; +#endif +#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) + gpio_setup_t PJData; +#endif +#if STM32_HAS_GPIOK || defined(__DOXYGEN__) + gpio_setup_t PKData; +#endif +} gpio_config_t; -#if HAL_USE_PAL || defined(__DOXYGEN__) /** - * @brief PAL setup. - * @details Digital I/O ports static configuration as defined in @p board.h. - * This variable is used by the HAL when initializing the PAL driver. + * @brief STM32 GPIO static initialization data. */ -const PALConfig pal_default_config = -{ +static const gpio_config_t gpio_default_config = { +#if STM32_HAS_GPIOA {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, +#endif +#if STM32_HAS_GPIOB {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, +#endif +#if STM32_HAS_GPIOC {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, +#endif +#if STM32_HAS_GPIOD {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, +#endif +#if STM32_HAS_GPIOE {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, +#endif +#if STM32_HAS_GPIOF {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, +#endif +#if STM32_HAS_GPIOG {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, +#endif +#if STM32_HAS_GPIOH {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, +#endif +#if STM32_HAS_GPIOI {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, - VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH} + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, +#endif +#if STM32_HAS_GPIOJ + {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, + VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, +#endif +#if STM32_HAS_GPIOK + {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, + VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} +#endif }; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { + + gpiop->OTYPER = config->otyper; + gpiop->OSPEEDR = config->ospeedr; + gpiop->PUPDR = config->pupdr; + gpiop->ODR = config->odr; + gpiop->AFRL = config->afrl; + gpiop->AFRH = config->afrh; + gpiop->MODER = config->moder; +} + +static void stm32_gpio_init(void) { + + /* Enabling GPIO-related clocks, the mask comes from the + registry header file.*/ + rccResetAHB1(STM32_GPIO_EN_MASK); + rccEnableAHB1(STM32_GPIO_EN_MASK, true); + + /* Initializing all the defined GPIO ports.*/ +#if STM32_HAS_GPIOA + gpio_init(GPIOA, &gpio_default_config.PAData); +#endif +#if STM32_HAS_GPIOB + gpio_init(GPIOB, &gpio_default_config.PBData); #endif +#if STM32_HAS_GPIOC + gpio_init(GPIOC, &gpio_default_config.PCData); +#endif +#if STM32_HAS_GPIOD + gpio_init(GPIOD, &gpio_default_config.PDData); +#endif +#if STM32_HAS_GPIOE + gpio_init(GPIOE, &gpio_default_config.PEData); +#endif +#if STM32_HAS_GPIOF + gpio_init(GPIOF, &gpio_default_config.PFData); +#endif +#if STM32_HAS_GPIOG + gpio_init(GPIOG, &gpio_default_config.PGData); +#endif +#if STM32_HAS_GPIOH + gpio_init(GPIOH, &gpio_default_config.PHData); +#endif +#if STM32_HAS_GPIOI + gpio_init(GPIOI, &gpio_default_config.PIData); +#endif +#if STM32_HAS_GPIOJ + gpio_init(GPIOJ, &gpio_default_config.PJData); +#endif +#if STM32_HAS_GPIOK + gpio_init(GPIOK, &gpio_default_config.PKData); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ /** * @brief Early initialization code. - * @details This initialization must be performed just after stack setup - * and before any other initialization. + * @details GPIO ports and system clocks are initialized before everything + * else. */ void __early_init(void) { + stm32_gpio_init(); stm32_clock_init(); } @@ -60,21 +212,21 @@ void __early_init(void) { /** * @brief SDC card detection. */ -bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) { +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { (void)sdcp; /* TODO: Fill the implementation.*/ - return TRUE; + return true; } /** * @brief SDC card write protection detection. */ -bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) { +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { (void)sdcp; /* TODO: Fill the implementation.*/ - return FALSE; + return false; } #endif /* HAL_USE_SDC */ @@ -82,21 +234,21 @@ bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) { /** * @brief MMC_SPI card detection. */ -bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) { +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { (void)mmcp; /* TODO: Fill the implementation.*/ - return TRUE; + return true; } /** * @brief MMC_SPI card write protection detection. */ -bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) { +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { (void)mmcp; /* TODO: Fill the implementation.*/ - return FALSE; + return false; } #endif @@ -105,4 +257,5 @@ bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) { * @todo Add your board-specific code, if any. */ void boardInit(void) { + } -- cgit v1.2.3