From 97b7064031ed2be5980a59cdab8174a9074febb4 Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Tue, 29 Oct 2019 19:38:09 +0100 Subject: Updating FSMC driver (SDRAM part first) --- os/hal/hal.mk | 6 +- os/hal/include/fsmc/nand.h | 293 ++++++++++ os/hal/include/fsmc/sdram.h | 173 ++++++ os/hal/include/fsmc/sram.h | 170 ++++++ os/hal/include/hal_community.h | 5 + os/hal/include/hal_fsmc.h | 400 ++++++++++++++ os/hal/ports/STM32/LLD/FSMCv1/driver.mk | 20 +- os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c | 193 ------- os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h | 351 ------------ os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.c | 590 +++++++++++++++++++++ os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.h | 289 ++++++++++ os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c | 215 -------- os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h | 175 ------ os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c | 172 ++++++ os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.h | 117 ++++ os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c | 165 ------ os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.h | 172 ------ os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.c | 165 ++++++ os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.h | 172 ++++++ os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c | 590 --------------------- os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h | 294 ---------- os/hal/src/hal_community.c | 4 + os/hal/src/hal_fsmc.c | 244 +++++++++ .../STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h | 18 +- testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c | 1 - .../STM32/STM32F4xx/FSMC_SDRAM/mcuconf_community.h | 26 +- 26 files changed, 2835 insertions(+), 2185 deletions(-) create mode 100644 os/hal/include/fsmc/nand.h create mode 100644 os/hal/include/fsmc/sdram.h create mode 100644 os/hal/include/fsmc/sram.h create mode 100644 os/hal/include/hal_fsmc.h delete mode 100644 os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c delete mode 100644 os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h create mode 100644 os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.c create mode 100644 os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.h delete mode 100644 os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c delete mode 100644 os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h create mode 100644 os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c create mode 100644 os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.h delete mode 100644 os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c delete mode 100644 os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.h create mode 100644 os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.c create mode 100644 os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.h delete mode 100644 os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c delete mode 100644 os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h create mode 100644 os/hal/src/hal_fsmc.c diff --git a/os/hal/hal.mk b/os/hal/hal.mk index ae27ea5..9908965 100644 --- a/os/hal/hal.mk +++ b/os/hal/hal.mk @@ -10,8 +10,8 @@ endif HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h $(CONFDIR)/halconf_community.h | egrep -e "\#define")) HALSRC_CONTRIB := ${CHIBIOS_CONTRIB}/os/hal/src/hal_community.c -ifneq ($(findstring HAL_USE_NAND TRUE,$(HALCONF)),) -HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_nand.c +ifneq ($(findstring HAL_USE_FSMC_SDRAM TRUE,$(HALCONF)), $(findstring HAL_USE_FSMC_SRAM TRUE,$(HALCONF)), $(findstring HAL_USE_FSMC_NAND TRUE,$(HALCONF))) +HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_fsmc.c endif ifneq ($(findstring HAL_USE_ONEWIRE TRUE,$(HALCONF)),) HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_onewire.c @@ -75,7 +75,7 @@ HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_opamp.c endif else HALSRC_CONTRIB := ${CHIBIOS_CONTRIB}/os/hal/src/hal_community.c \ - ${CHIBIOS_CONTRIB}/os/hal/src/hal_nand.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/hal_fsmc.c \ ${CHIBIOS_CONTRIB}/os/hal/src/hal_onewire.c \ ${CHIBIOS_CONTRIB}/os/hal/src/hal_eicu.c \ ${CHIBIOS_CONTRIB}/os/hal/src/hal_crc.c \ diff --git a/os/hal/include/fsmc/nand.h b/os/hal/include/fsmc/nand.h new file mode 100644 index 0000000..b2d9001 --- /dev/null +++ b/os/hal/include/fsmc/nand.h @@ -0,0 +1,293 @@ +/* + ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_nand_lld.h + * @brief NAND Driver subsystem low level driver header. + * + * @addtogroup NAND + * @{ + */ + +#ifndef NAND_H_ +#define NAND_H_ + +#include "bitmap.h" + +#if (HAL_USE_FSMC_NAND == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ +#define NAND_MIN_PAGE_SIZE 256 +#define NAND_MAX_PAGE_SIZE 8192 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief FSMC1 interrupt priority level setting. + */ +#if !defined(STM32_EMC_FSMC1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EMC_FSMC1_IRQ_PRIORITY 10 +#endif + +/** + * @brief NAND driver enable switch. + * @details If set to @p TRUE the support for NAND1 is included. + */ +#if !defined(STM32_FSMC_USE_NAND1) || defined(__DOXYGEN__) +#define STM32_FSMC_USE_NAND1 FALSE +#endif + +/** + * @brief NAND driver enable switch. + * @details If set to @p TRUE the support for NAND2 is included. + */ +#if !defined(STM32_FSMC_USE_NAND2) || defined(__DOXYGEN__) +#define STM32_FSMC_USE_NAND2 FALSE +#endif + +/** + * @brief NAND DMA error hook. + * @note The default action for DMA errors is a system halt because DMA + * error can only happen because programming errors. + */ +#if !defined(STM32_NAND_DMA_ERROR_HOOK) || defined(__DOXYGEN__) +#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure") +#endif + +/** + * @brief NAND interrupt enable switch. + * @details If set to @p TRUE the support for internal FSMC interrupt included. + */ +#if !defined(STM32_NAND_USE_INT) || defined(__DOXYGEN__) +#define STM32_NAND_USE_INT FALSE +#endif + +/** +* @brief NAND1 DMA priority (0..3|lowest..highest). +*/ +#if !defined(STM32_NAND_NAND1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_NAND_NAND1_DMA_PRIORITY 0 +#endif + +/** +* @brief NAND2 DMA priority (0..3|lowest..highest). +*/ +#if !defined(STM32_NAND_NAND2_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_NAND_NAND2_DMA_PRIORITY 0 +#endif + +/** + * @brief DMA stream used for NAND operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_NAND_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !STM32_FSMC_USE_NAND1 && !STM32_FSMC_USE_NAND2 +#error "NAND driver activated but no NAND peripheral assigned" +#endif + +#if (STM32_FSMC_USE_NAND1 || STM32_FSMC_USE_NAND2) && !STM32_HAS_FSMC +#error "FSMC not present in the selected device" +#endif + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an NAND driver. + */ +typedef struct NANDDriver NANDDriver; + +/** + * @brief Type of interrupt handler function. + */ +typedef void (*nandisrhandler_t)(NANDDriver *nandp); + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Number of erase blocks in NAND device. + */ + uint32_t blocks; + /** + * @brief Number of data bytes in page. + */ + uint32_t page_data_size; + /** + * @brief Number of spare bytes in page. + */ + uint32_t page_spare_size; + /** + * @brief Number of pages in block. + */ + uint32_t pages_per_block; + /** + * @brief Number of write cycles for row addressing. + */ + uint8_t rowcycles; + /** + * @brief Number of write cycles for column addressing. + */ + uint8_t colcycles; + + /* End of the mandatory fields.*/ + /** + * @brief Number of wait cycles. This value will be used both for + * PMEM and PATTR registers + * + * @note For proper calculation procedure please look at AN2784 document + * from STMicroelectronics. + */ + uint32_t pmem; +} NANDConfig; + +/** + * @brief Structure representing an NAND driver. + */ +struct NANDDriver { + /** + * @brief Driver state. + */ + nandstate_t state; + /** + * @brief Current configuration data. + */ + const NANDConfig *config; + /** + * @brief Array to store bad block map. + */ +#if NAND_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + mutex_t mutex; +#elif CH_CFG_USE_SEMAPHORES + semaphore_t semaphore; +#endif +#endif /* NAND_USE_MUTUAL_EXCLUSION */ + /* End of the mandatory fields.*/ + /** + * @brief Function enabling interrupts from FSMC. + */ + nandisrhandler_t isr_handler; + /** + * @brief Pointer to current transaction buffer. + */ + void *rxdata; + /** + * @brief Current transaction length in bytes. + */ + size_t datalen; + /** + * @brief DMA mode bit mask. + */ + uint32_t dmamode; + /** + * @brief DMA channel. + */ + const stm32_dma_stream_t *dma; + /** + * @brief Thread waiting for I/O completion. + */ + thread_t *thread; + /** + * @brief Pointer to the FSMC NAND registers block. + */ + FSMC_NAND_TypeDef *nand; + /** + * @brief Memory mapping for data. + */ + uint16_t *map_data; + /** + * @brief Memory mapping for commands. + */ + uint16_t *map_cmd; + /** + * @brief Memory mapping for addresses. + */ + uint16_t *map_addr; + /** + * @brief Pointer to bad block map. + * @details One bit per block. All memory allocation is user's responsibility. + */ + bitmap_t *bb_map; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_FSMC_USE_NAND1 && !defined(__DOXYGEN__) +extern NANDDriver NANDD1; +#endif + +#if STM32_FSMC_USE_NAND2 && !defined(__DOXYGEN__) +extern NANDDriver NANDD2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void nand_lld_init(void); + void nand_lld_start(NANDDriver *nandp); + void nand_lld_stop(NANDDriver *nandp); + uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen); + void nand_lld_read_data(NANDDriver *nandp, uint16_t *data, + size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc); + void nand_lld_write_addr(NANDDriver *nandp, const uint8_t *addr, size_t len); + void nand_lld_write_cmd(NANDDriver *nandp, uint8_t cmd); + uint8_t nand_lld_write_data(NANDDriver *nandp, const uint16_t *data, + size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc); + uint8_t nand_lld_read_status(NANDDriver *nandp); + void nand_lld_reset(NANDDriver *nandp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_FSMC_NAND */ + +#endif /* NAND_H_ */ + +/** @} */ diff --git a/os/hal/include/fsmc/sdram.h b/os/hal/include/fsmc/sdram.h new file mode 100644 index 0000000..83b78a6 --- /dev/null +++ b/os/hal/include/fsmc/sdram.h @@ -0,0 +1,173 @@ +/* + ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + SDRAM routines added by Nick Klimov aka progfin. + */ + +/** + * @file hal_fsmc_sdram.h + * @brief SDRAM Driver subsystem low level driver header. + * + * @addtogroup SDRAM + * @{ + */ + +#ifndef SDRAM_H_ +#define SDRAM_H_ + +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F745xx) || defined(STM32F746xx) || \ + defined(STM32F756xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || \ + defined(STM32F779xx)) + +#if (HAL_USE_FSMC_SDRAM == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ + +/** + * @brief SDRAM driver enable switch. + * @details If set to @p TRUE the support for SDRAM1 is included. + */ +#if !defined(STM32_FSMC_USE_SDRAM1) || defined(__DOXYGEN__) +#define STM32_FSMC_USE_SDRAM1 FALSE +#else +#define STM32_SDRAM1_MAP_BASE FSMC_Bank5_MAP_BASE +#endif + +/** + * @brief SDRAM driver enable switch. + * @details If set to @p TRUE the support for SDRAM2 is included. + */ +#if !defined(STM32_FSMC_USE_SDRAM2) || defined(__DOXYGEN__) +#define STM32_FSMC_USE_SDRAM2 FALSE +#else +#define STM32_SDRAM2_MAP_BASE FSMC_Bank6_MAP_BASE +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !STM32_FSMC_USE_SDRAM1 && !STM32_FSMC_USE_SDRAM2 +#error "SDRAM driver activated but no SDRAM peripheral assigned" +#endif + +#if (STM32_FSMC_USE_SDRAM1 || STM32_FSMC_USE_SDRAM2) && !STM32_HAS_FSMC +#error "FMC not present in the selected device" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ +/** + * @brief Driver state machine possible states. + */ +typedef enum { + SDRAM_UNINIT = 0, /**< Not initialized. */ + SDRAM_STOP = 1, /**< Stopped. */ + SDRAM_READY = 2, /**< Ready. */ +} sdramstate_t; + +/** + * @brief Type of a structure representing an SDRAM driver. + */ +typedef struct SDRAMDriver SDRAMDriver; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief SDRAM control register. + * @note Its value will be used for both banks. + */ + uint32_t sdcr; + + /** + * @brief SDRAM timing register. + * @note Its value will be used for both banks. + */ + uint32_t sdtr; + + /** + * @brief SDRAM command mode register. + * @note Only its MRD and NRFS bits will be used. + */ + uint32_t sdcmr; + + /** + * @brief SDRAM refresh timer register. + * @note Only its COUNT bits will be used. + */ + uint32_t sdrtr; +} SDRAMConfig; + +/** + * @brief Structure representing an SDRAM driver. + */ +struct SDRAMDriver { + /** + * @brief Driver state. + */ + sdramstate_t state; + /** + * @brief Pointer to the FMC SDRAM registers block. + */ + FSMC_SDRAM_TypeDef *sdram; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +extern SDRAMDriver SDRAMD; + +#ifdef __cplusplus +extern "C" { +#endif + void fsmcSdramInit(void); + void fsmcSdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp); + void fsmcSdramStop(SDRAMDriver *sdramp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_FSMC_SDRAM */ + +#endif /* STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx */ + +#endif /* SDRAM_H_ */ + +/** @} */ diff --git a/os/hal/include/fsmc/sram.h b/os/hal/include/fsmc/sram.h new file mode 100644 index 0000000..6eed97a --- /dev/null +++ b/os/hal/include/fsmc/sram.h @@ -0,0 +1,170 @@ +/* + ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_fsmc_sram.h + * @brief SRAM Driver subsystem low level driver header. + * + * @addtogroup SRAM + * @{ + */ + +#ifndef SRAM_H_ +#define SRAM_H_ + +#if (HAL_USE_FSMC_SRAM == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ + +/** + * @brief SRAM driver enable switch. + * @details If set to @p TRUE the support for SRAM1 is included. + */ +#if !defined(STM32_SRAM_USE_FSMC_SRAM1) || defined(__DOXYGEN__) +#define STM32_SRAM_USE_FSMC_SRAM1 FALSE +#endif + +/** + * @brief SRAM driver enable switch. + * @details If set to @p TRUE the support for SRAM2 is included. + */ +#if !defined(STM32_SRAM_USE_FSMC_SRAM2) || defined(__DOXYGEN__) +#define STM32_SRAM_USE_FSMC_SRAM2 FALSE +#endif + +/** + * @brief SRAM driver enable switch. + * @details If set to @p TRUE the support for SRAM3 is included. + */ +#if !defined(STM32_SRAM_USE_FSMC_SRAM3) || defined(__DOXYGEN__) +#define STM32_SRAM_USE_FSMC_SRAM3 FALSE +#endif + +/** + * @brief SRAM driver enable switch. + * @details If set to @p TRUE the support for SRAM4 is included. + */ +#if !defined(STM32_SRAM_USE_FSMC_SRAM4) || defined(__DOXYGEN__) +#define STM32_SRAM_USE_FSMC_SRAM4 FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !STM32_SRAM_USE_FSMC_SRAM1 && !STM32_SRAM_USE_FSMC_SRAM2 && \ + !STM32_SRAM_USE_FSMC_SRAM3 && !STM32_SRAM_USE_FSMC_SRAM4 +#error "SRAM driver activated but no SRAM peripheral assigned" +#endif + +#if (STM32_SRAM_USE_FSMC_SRAM1 || STM32_SRAM_USE_FSMC_SRAM2 || \ + STM32_SRAM_USE_FSMC_SRAM3 || STM32_SRAM_USE_FSMC_SRAM4) && !STM32_HAS_FSMC +#error "FSMC not present in the selected device" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ +/** + * @brief Driver state machine possible states. + */ +typedef enum { + SRAM_UNINIT = 0, /**< Not initialized. */ + SRAM_STOP = 1, /**< Stopped. */ + SRAM_READY = 2, /**< Ready. */ +} sramstate_t; + +/** + * @brief Type of a structure representing an NAND driver. + */ +typedef struct SRAMDriver SRAMDriver; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + * @note Some bits in BCR register will be forced by driver. + */ +typedef struct { + uint32_t bcr; + uint32_t btr; + uint32_t bwtr; +} SRAMConfig; + +/** + * @brief Structure representing an NAND driver. + */ +struct SRAMDriver { + /** + * @brief Driver state. + */ + sramstate_t state; + /** + * @brief Pointer to the FSMC SRAM registers block. + */ + FSMC_SRAM_NOR_TypeDef *sram; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_SRAM_USE_FSMC_SRAM1 && !defined(__DOXYGEN__) +extern SRAMDriver SRAMD1; +#endif + +#if STM32_SRAM_USE_FSMC_SRAM2 && !defined(__DOXYGEN__) +extern SRAMDriver SRAMD2; +#endif + +#if STM32_SRAM_USE_FSMC_SRAM3 && !defined(__DOXYGEN__) +extern SRAMDriver SRAMD3; +#endif + +#if STM32_SRAM_USE_FSMC_SRAM4 && !defined(__DOXYGEN__) +extern SRAMDriver SRAMD4; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void fsmcSramInit(void); + void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp); + void fsmcSramStop(SRAMDriver *sramp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_FSMC_SRAM */ + +#endif /* SRAM_H_ */ + +/** @} */ diff --git a/os/hal/include/hal_community.h b/os/hal/include/hal_community.h index f84e90a..ad5c472 100644 --- a/os/hal/include/hal_community.h +++ b/os/hal/include/hal_community.h @@ -79,6 +79,10 @@ #define HAL_USE_OPAMP FALSE #endif +#if !defined(HAL_USE_FSMC) +#define HAL_USE_FSMC FALSE +#endif + /* Abstract interfaces.*/ /* Shared headers.*/ @@ -99,6 +103,7 @@ #include "hal_eeprom.h" #include "hal_usb_hid.h" #include "hal_usb_msd.h" +#include "hal_fsmc.h" /*===========================================================================*/ /* Driver constants. */ diff --git a/os/hal/include/hal_fsmc.h b/os/hal/include/hal_fsmc.h new file mode 100644 index 0000000..f85079a --- /dev/null +++ b/os/hal/include/hal_fsmc.h @@ -0,0 +1,400 @@ +/* + ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_fsmc.h + * @brief FSMC Driver subsystem low level driver header. + * + * @addtogroup FSMC + * @{ + */ + +#ifndef HAL_FSMC_H_ +#define HAL_FSMC_H_ + +#include "hal.h" + +#if (HAL_USE_FSMC_SDRAM == TRUE) || (HAL_USE_FSMC_SRAM == TRUE) || (HAL_USE_FSMC_NAND == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/* + * (Re)define if needed base address constants supplied in ST's CMSIS + */ +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F745xx) || defined(STM32F746xx) || \ + defined(STM32F756xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || \ + defined(STM32F779xx)) + #if !defined(FSMC_Bank1_R_BASE) + #define FSMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) + #endif + #if !defined(FSMC_Bank1E_R_BASE) + #define FSMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) + #endif + #if !defined(FSMC_Bank2_R_BASE) + #define FSMC_Bank2_R_BASE (FMC_R_BASE + 0x0060) + #endif + #if !defined(FSMC_Bank3_R_BASE) + #define FSMC_Bank3_R_BASE (FMC_R_BASE + 0x0080) + #endif + #if !defined(FSMC_Bank4_R_BASE) + #define FSMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0) + #endif + #if !defined(FSMC_Bank5_R_BASE) + #define FSMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140) + #endif +#else + #if !defined(FSMC_Bank1_R_BASE) + #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) + #endif + #if !defined(FSMC_Bank1E_R_BASE) + #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) + #endif + #if !defined(FSMC_Bank2_R_BASE) + #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) + #endif + #if !defined(FSMC_Bank3_R_BASE) + #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) + #endif + #if !defined(FSMC_Bank4_R_BASE) + #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) + #endif +#endif + +/* + * Base bank mappings + */ +#define FSMC_Bank1_MAP_BASE ((uint32_t) 0x60000000) +#define FSMC_Bank2_MAP_BASE ((uint32_t) 0x70000000) +#define FSMC_Bank3_MAP_BASE ((uint32_t) 0x80000000) +#define FSMC_Bank4_MAP_BASE ((uint32_t) 0x90000000) +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F7)) + #define FSMC_Bank5_MAP_BASE ((uint32_t) 0xC0000000) + #define FSMC_Bank6_MAP_BASE ((uint32_t) 0xD0000000) +#endif + +/* + * Subbunks of bank1 + */ +#define FSMC_SUBBUNK_OFFSET (1024 * 1024 * 64) +#define FSMC_Bank1_1_MAP (FSMC_Bank1_MAP_BASE) +#define FSMC_Bank1_2_MAP (FSMC_Bank1_1_MAP + FSMC_SUBBUNK_OFFSET) +#define FSMC_Bank1_3_MAP (FSMC_Bank1_2_MAP + FSMC_SUBBUNK_OFFSET) +#define FSMC_Bank1_4_MAP (FSMC_Bank1_3_MAP + FSMC_SUBBUNK_OFFSET) + +/* + * Bank 2 (NAND) + */ +#define FSMC_Bank2_MAP_COMMON (FSMC_Bank2_MAP_BASE + 0) +#define FSMC_Bank2_MAP_ATTR (FSMC_Bank2_MAP_BASE + 0x8000000) + +#define FSMC_Bank2_MAP_COMMON_DATA (FSMC_Bank2_MAP_COMMON + 0) +#define FSMC_Bank2_MAP_COMMON_CMD (FSMC_Bank2_MAP_COMMON + 0x10000) +#define FSMC_Bank2_MAP_COMMON_ADDR (FSMC_Bank2_MAP_COMMON + 0x20000) + +#define FSMC_Bank2_MAP_ATTR_DATA (FSMC_Bank2_MAP_ATTR + 0) +#define FSMC_Bank2_MAP_ATTR_CMD (FSMC_Bank2_MAP_ATTR + 0x10000) +#define FSMC_Bank2_MAP_ATTR_ADDR (FSMC_Bank2_MAP_ATTR + 0x20000) + +/* + * Bank 3 (NAND) + */ +#define FSMC_Bank3_MAP_COMMON (FSMC_Bank3_MAP_BASE + 0) +#define FSMC_Bank3_MAP_ATTR (FSMC_Bank3_MAP_BASE + 0x8000000) + +#define FSMC_Bank3_MAP_COMMON_DATA (FSMC_Bank3_MAP_COMMON + 0) +#define FSMC_Bank3_MAP_COMMON_CMD (FSMC_Bank3_MAP_COMMON + 0x10000) +#define FSMC_Bank3_MAP_COMMON_ADDR (FSMC_Bank3_MAP_COMMON + 0x20000) + +#define FSMC_Bank3_MAP_ATTR_DATA (FSMC_Bank3_MAP_ATTR + 0) +#define FSMC_Bank3_MAP_ATTR_CMD (FSMC_Bank3_MAP_ATTR + 0x10000) +#define FSMC_Bank3_MAP_ATTR_ADDR (FSMC_Bank3_MAP_ATTR + 0x20000) + +/* + * Bank 4 (PC card) + */ +#define FSMC_Bank4_MAP_COMMON (FSMC_Bank4_MAP_BASE + 0) +#define FSMC_Bank4_MAP_ATTR (FSMC_Bank4_MAP_BASE + 0x8000000) +#define FSMC_Bank4_MAP_IO (FSMC_Bank4_MAP_BASE + 0xC000000) + +/* + * More convenient typedefs than CMSIS has + */ +typedef struct { + __IO uint32_t PCR; /**< NAND Flash control */ + __IO uint32_t SR; /**< NAND Flash FIFO status and interrupt */ + __IO uint32_t PMEM; /**< NAND Flash Common memory space timing */ + __IO uint32_t PATT; /**< NAND Flash Attribute memory space timing */ + uint32_t RESERVED0; /**< Reserved, 0x70 */ + __IO uint32_t ECCR; /**< NAND Flash ECC result registers */ +} FSMC_NAND_TypeDef; + +typedef struct { + __IO uint32_t PCR; /**< PC Card control */ + __IO uint32_t SR; /**< PC Card FIFO status and interrupt */ + __IO uint32_t PMEM; /**< PC Card Common memory space timing */ + __IO uint32_t PATT; /**< PC Card Attribute memory space timing */ + __IO uint32_t PIO; /**< PC Card I/O space timing */ +} FSMC_PCCard_TypeDef; + +typedef struct { + __IO uint32_t BCR; /**< SRAM/NOR chip-select control registers */ + __IO uint32_t BTR; /**< SRAM/NOR chip-select timing registers */ + uint32_t RESERVED[63]; /**< Reserved */ + __IO uint32_t BWTR; /**< SRAM/NOR write timing registers */ +} FSMC_SRAM_NOR_TypeDef; + +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F7)) + +typedef struct { + __IO uint32_t SDCR1; /**< SDRAM control register (bank 1) */ + __IO uint32_t SDCR2; /**< SDRAM control register (bank 2) */ + __IO uint32_t SDTR1; /**< SDRAM timing register (bank 1) */ + __IO uint32_t SDTR2; /**< SDRAM timing register (bank 2) */ + __IO uint32_t SDCMR; /**< SDRAM comand mode register */ + __IO uint32_t SDRTR; /**< SDRAM refresh timer register */ + __IO uint32_t SDSR; /**< SDRAM status register */ +} FSMC_SDRAM_TypeDef; + +#endif + +/** + * @brief PCR register + */ +#define FSMC_PCR_PWAITEN ((uint32_t)1 << 1) +#define FSMC_PCR_PBKEN ((uint32_t)1 << 2) +#define FSMC_PCR_PTYP ((uint32_t)1 << 3) +#define FSMC_PCR_PWID_8 ((uint32_t)0 << 4) +#define FSMC_PCR_PWID_16 ((uint32_t)1 << 4) +#define FSMC_PCR_PWID_RESERVED1 ((uint32_t)2 << 4) +#define FSMC_PCR_PWID_RESERVED2 ((uint32_t)3 << 4) +#define FSMC_PCR_PWID_MASK ((uint32_t)3 << 4) +#define FSMC_PCR_ECCEN ((uint32_t)1 << 6) +#define FSMC_PCR_PTYP_PCCARD 0 +#define FSMC_PCR_PTYP_NAND FSMC_PCR_PTYP + +/** + * @brief SR register + */ +#define FSMC_SR_IRS ((uint8_t)0x01) +#define FSMC_SR_ILS ((uint8_t)0x02) +#define FSMC_SR_IFS ((uint8_t)0x04) +#define FSMC_SR_IREN ((uint8_t)0x08) +#define FSMC_SR_ILEN ((uint8_t)0x10) +#define FSMC_SR_IFEN ((uint8_t)0x20) +#define FSMC_SR_FEMPT ((uint8_t)0x40) +#define FSMC_SR_ISR_MASK (FSMC_SR_IRS | FSMC_SR_ILS | FSMC_SR_IFS) + +/** + * @brief BCR register + */ +#define FSMC_BCR_MBKEN ((uint32_t)1 << 0) +#define FSMC_BCR_MUXEN ((uint32_t)1 << 1) +#define FSMC_BCR_MTYP_SRAM ((uint32_t)0 << 2) +#define FSMC_BCR_MTYP_PSRAM ((uint32_t)1 << 2) +#define FSMC_BCR_MTYP_NOR_NAND ((uint32_t)2 << 2) +#define FSMC_BCR_MTYP_RESERVED ((uint32_t)3 << 2) +#define FSMC_BCR_MWID_8 ((uint32_t)0 << 4) +#define FSMC_BCR_MWID_16 ((uint32_t)1 << 4) +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F7)) +#define FSMC_BCR_MWID_32 ((uint32_t)2 << 4) +#else +#define FSMC_BCR_MWID_RESERVED1 ((uint32_t)2 << 4) +#endif +#define FSMC_BCR_MWID_RESERVED2 ((uint32_t)3 << 4) +#define FSMC_BCR_FACCEN ((uint32_t)1 << 6) +#define FSMC_BCR_BURSTEN ((uint32_t)1 << 8) +#define FSMC_BCR_WAITPOL ((uint32_t)1 << 9) +#define FSMC_BCR_WRAPMOD ((uint32_t)1 << 10) +#define FSMC_BCR_WAITCFG ((uint32_t)1 << 11) +#define FSMC_BCR_WREN ((uint32_t)1 << 12) +#define FSMC_BCR_WAITEN ((uint32_t)1 << 13) +#define FSMC_BCR_EXTMOD ((uint32_t)1 << 14) +#define FSMC_BCR_ASYNCWAIT ((uint32_t)1 << 15) +#define FSMC_BCR_CBURSTRW ((uint32_t)1 << 19) +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F7)) +#define FSMC_BCR_CCLKEN ((uint32_t)1 << 20) +#endif +#if (defined(STM32F7)) +#define FSMC_BCR_WFDIS ((uint32_t)1 << 21) +#endif + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +#if !defined(STM32_DMA_REQUIRED) +#define STM32_DMA_REQUIRED +#endif + +/** + * @name Configuration options + * @{ + */ +/** + * @brief FSMC driver enable switch. + * @details If set to @p TRUE the support for FSMC is included. + */ +#if !defined(STM32_FSMC_USE_FSMC1) || defined(__DOXYGEN__) +#define STM32_FSMC_USE_FSMC1 FALSE +#endif + +/** + * @brief SDRAM driver enable switch. + * @details If set to @p TRUE the support for SDRAM is included. + */ +#if !defined(HAL_USE_FSMC_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_FSMC_SDRAM FALSE +#endif + +/** + * @brief SRAM driver enable switch. + * @details If set to @p TRUE the support for SRAM is included. + */ +#if !defined(HAL_USE_FSMC_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_FSMC_SRAM FALSE +#endif + +/** + * @brief NAND driver enable switch. + * @details If set to @p TRUE the support for NAND is included. + */ +#if !defined(HAL_USE_FSMC_NAND) || defined(__DOXYGEN__) +#define HAL_USE_FSMC_NAND FALSE +#endif + + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ +#if !STM32_FSMC_USE_FSMC1 +#error "FSMC driver activated but no FSMC peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an FSMC driver. + */ +typedef struct FSMCDriver FSMCDriver; + +/** + * @brief Driver state machine possible states. + */ +typedef enum { + FSMC_UNINIT = 0, /**< Not initialized. */ + FSMC_STOP = 1, /**< Stopped. */ + FSMC_READY = 2, /**< Ready. */ +} fsmcstate_t; + +/** + * @brief Structure representing an FSMC driver. + */ +struct FSMCDriver { + /** + * @brief Driver state. + */ + fsmcstate_t state; + /* End of the mandatory fields.*/ + +#if HAL_USE_FSMC_SRAM + #if STM32_SRAM_USE_FSMC_SRAM1 + FSMC_SRAM_NOR_TypeDef *sram1; + #endif + #if STM32_SRAM_USE_FSMC_SRAM2 + FSMC_SRAM_NOR_TypeDef *sram2; + #endif + #if STM32_SRAM_USE_FSMC_SRAM3 + FSMC_SRAM_NOR_TypeDef *sram3; + #endif + #if STM32_SRAM_USE_FSMC_SRAM4 + FSMC_SRAM_NOR_TypeDef *sram4; + #endif +#endif + +#if HAL_USE_FSMC_NAND + #if STM32_NAND_USE_FSMC_NAND1 + FSMC_NAND_TypeDef *nand1; + #endif + #if STM32_NAND_USE_FSMC_NAND2 + FSMC_NAND_TypeDef *nand2; + #endif +#endif + +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F7)) + #if HAL_USE_FSMC_SDRAM + FSMC_SDRAM_TypeDef *sdram; + #endif +#endif +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_FSMC_USE_FSMC1 && !defined(__DOXYGEN__) +extern FSMCDriver FSMCD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void fsmcInit(void); + void fsmcStart(FSMCDriver *fsmcp); + void fsmcStop(FSMCDriver *fsmcp); +#ifdef __cplusplus +} +#endif + +#if HAL_USE_FSMC_SDRAM == TRUE +#include "fsmc/sdram.h" +#endif + +#if HAL_USE_FSMC_SRAM == TRUE +#include "fsmc/sram.h" +#endif + +#if HAL_USE_FSMC_NAND == TRUE +#include "fsmc/nand.h" +#endif + +#endif /* HAL_USE_FSMC */ + +#endif /* HAL_FSMC_H_ */ + +/** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/driver.mk b/os/hal/ports/STM32/LLD/FSMCv1/driver.mk index d92230d..cffa3f7 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/driver.mk +++ b/os/hal/ports/STM32/LLD/FSMCv1/driver.mk @@ -1,17 +1,17 @@ ifeq ($(USE_SMART_BUILD),yes) -ifneq ($(findstring HAL_USE_FSMC TRUE,$(HALCONF)),) -PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c +ifneq ($(findstring HAL_USE_FSMC_SDRAM TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c endif -ifneq ($(findstring HAL_USE_NAND TRUE,$(HALCONF)),) -PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c +ifneq ($(findstring HAL_USE_FSMC_SRAM TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.c +endif +ifneq ($(findstring HAL_USE_FSMC_NAND TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.c endif else -PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.c endif PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1 diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c deleted file mode 100644 index 71c6ada..0000000 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c +++ /dev/null @@ -1,193 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_fsmc.c - * @brief FSMC Driver subsystem low level driver source template. - * - * @addtogroup FSMC - * @{ - */ -#include "hal.h" -#include "hal_fsmc.h" - -#if (HAL_USE_FSMC == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief FSMC1 driver identifier. - */ -#if STM32_FSMC_USE_FSMC1 || defined(__DOXYGEN__) -FSMCDriver FSMCD1; -#endif - -/*===========================================================================*/ -/* Driver local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level FSMC driver initialization. - * - * @notapi - */ -void fsmc_init(void) { - - if (FSMCD1.state == FSMC_UNINIT) { - FSMCD1.state = FSMC_STOP; - -#if STM32_SRAM_USE_FSMC_SRAM1 - FSMCD1.sram1 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE); -#endif - -#if STM32_SRAM_USE_FSMC_SRAM2 - FSMCD1.sram2 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8); -#endif - -#if STM32_SRAM_USE_FSMC_SRAM3 - FSMCD1.sram3 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 2); -#endif - -#if STM32_SRAM_USE_FSMC_SRAM4 - FSMCD1.sram4 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 3); -#endif - -#if STM32_NAND_USE_FSMC_NAND1 - FSMCD1.nand1 = (FSMC_NAND_TypeDef *)FSMC_Bank2_R_BASE; -#endif - -#if STM32_NAND_USE_FSMC_NAND2 - FSMCD1.nand2 = (FSMC_NAND_TypeDef *)FSMC_Bank3_R_BASE; -#endif - -#if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F745xx) || defined(STM32F746xx) || \ - defined(STM32F756xx) || defined(STM32F767xx) || \ - defined(STM32F769xx) || defined(STM32F777xx) || \ - defined(STM32F779xx)) - #if STM32_USE_FSMC_SDRAM - FSMCD1.sdram = (FSMC_SDRAM_TypeDef *)FSMC_Bank5_6_R_BASE; - #endif -#endif - } -} - -/** - * @brief Configures and activates the FSMC peripheral. - * - * @param[in] fsmcp pointer to the @p FSMCDriver object - * - * @notapi - */ -void fsmc_start(FSMCDriver *fsmcp) { - - osalDbgAssert((fsmcp->state == FSMC_STOP) || (fsmcp->state == FSMC_READY), - "invalid state"); - - if (fsmcp->state == FSMC_STOP) { - /* Enables the peripheral.*/ -#if STM32_FSMC_USE_FSMC1 - if (&FSMCD1 == fsmcp) { -#ifdef rccResetFSMC - rccResetFSMC(); -#endif - rccEnableFSMC(FALSE); -#if HAL_USE_NAND - nvicEnableVector(STM32_FSMC_NUMBER, STM32_FSMC_FSMC1_IRQ_PRIORITY); -#endif - } -#endif /* STM32_FSMC_USE_FSMC1 */ - - fsmcp->state = FSMC_READY; - } -} - -/** - * @brief Deactivates the FSMC peripheral. - * - * @param[in] emcp pointer to the @p FSMCDriver object - * - * @notapi - */ -void fsmc_stop(FSMCDriver *fsmcp) { - - if (fsmcp->state == FSMC_READY) { - /* Resets the peripheral.*/ -#ifdef rccResetFSMC - rccResetFSMC(); -#endif - - /* Disables the peripheral.*/ -#if STM32_FSMC_USE_FSMC1 - if (&FSMCD1 == fsmcp) { -#if HAL_USE_NAND - nvicDisableVector(STM32_FSMC_NUMBER); -#endif - rccDisableFSMC(); - } -#endif /* STM32_FSMC_USE_FSMC1 */ - - fsmcp->state = FSMC_STOP; - } -} - -/** - * @brief FSMC shared interrupt handler. - * - * @notapi - */ -CH_IRQ_HANDLER(STM32_FSMC_HANDLER) { - - CH_IRQ_PROLOGUE(); -#if STM32_NAND_USE_FSMC_NAND1 - if (FSMCD1.nand1->SR & FSMC_SR_ISR_MASK) { - NANDD1.isr_handler(&NANDD1); - } -#endif -#if STM32_NAND_USE_FSMC_NAND2 - if (FSMCD1.nand2->SR & FSMC_SR_ISR_MASK) { - NANDD2.isr_handler(&NANDD2); - } -#endif - CH_IRQ_EPILOGUE(); -} - -#endif /* HAL_USE_FSMC */ - -/** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h deleted file mode 100644 index 80c5d26..0000000 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h +++ /dev/null @@ -1,351 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_fsmc.h - * @brief FSMC Driver subsystem low level driver header. - * - * @addtogroup FSMC - * @{ - */ - -#ifndef HAL_FSMC_H_ -#define HAL_FSMC_H_ - -#if (HAL_USE_FSMC == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* - * (Re)define if needed base address constants supplied in ST's CMSIS - */ -#if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F745xx) || defined(STM32F746xx) || \ - defined(STM32F756xx) || defined(STM32F767xx) || \ - defined(STM32F769xx) || defined(STM32F777xx) || \ - defined(STM32F779xx)) - #if !defined(FSMC_Bank1_R_BASE) - #define FSMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) - #endif - #if !defined(FSMC_Bank1E_R_BASE) - #define FSMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104) - #endif - #if !defined(FSMC_Bank2_R_BASE) - #define FSMC_Bank2_R_BASE (FMC_R_BASE + 0x0060) - #endif - #if !defined(FSMC_Bank3_R_BASE) - #define FSMC_Bank3_R_BASE (FMC_R_BASE + 0x0080) - #endif - #if !defined(FSMC_Bank4_R_BASE) - #define FSMC_Bank4_R_BASE (FMC_R_BASE + 0x00A0) - #endif - #if !defined(FSMC_Bank5_R_BASE) - #define FSMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140) - #endif -#else - #if !defined(FSMC_Bank1_R_BASE) - #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) - #endif - #if !defined(FSMC_Bank1E_R_BASE) - #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) - #endif - #if !defined(FSMC_Bank2_R_BASE) - #define FSMC_Bank2_R_BASE (FSMC_R_BASE + 0x0060) - #endif - #if !defined(FSMC_Bank3_R_BASE) - #define FSMC_Bank3_R_BASE (FSMC_R_BASE + 0x0080) - #endif - #if !defined(FSMC_Bank4_R_BASE) - #define FSMC_Bank4_R_BASE (FSMC_R_BASE + 0x00A0) - #endif -#endif - -/* - * Base bank mappings - */ -#define FSMC_Bank1_MAP_BASE ((uint32_t) 0x60000000) -#define FSMC_Bank2_MAP_BASE ((uint32_t) 0x70000000) -#define FSMC_Bank3_MAP_BASE ((uint32_t) 0x80000000) -#define FSMC_Bank4_MAP_BASE ((uint32_t) 0x90000000) -#if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F7)) - #define FSMC_Bank5_MAP_BASE ((uint32_t) 0xC0000000) - #define FSMC_Bank6_MAP_BASE ((uint32_t) 0xD0000000) -#endif - -/* - * Subbunks of bank1 - */ -#define FSMC_SUBBUNK_OFFSET (1024 * 1024 * 64) -#define FSMC_Bank1_1_MAP (FSMC_Bank1_MAP_BASE) -#define FSMC_Bank1_2_MAP (FSMC_Bank1_1_MAP + FSMC_SUBBUNK_OFFSET) -#define FSMC_Bank1_3_MAP (FSMC_Bank1_2_MAP + FSMC_SUBBUNK_OFFSET) -#define FSMC_Bank1_4_MAP (FSMC_Bank1_3_MAP + FSMC_SUBBUNK_OFFSET) - -/* - * Bank 2 (NAND) - */ -#define FSMC_Bank2_MAP_COMMON (FSMC_Bank2_MAP_BASE + 0) -#define FSMC_Bank2_MAP_ATTR (FSMC_Bank2_MAP_BASE + 0x8000000) - -#define FSMC_Bank2_MAP_COMMON_DATA (FSMC_Bank2_MAP_COMMON + 0) -#define FSMC_Bank2_MAP_COMMON_CMD (FSMC_Bank2_MAP_COMMON + 0x10000) -#define FSMC_Bank2_MAP_COMMON_ADDR (FSMC_Bank2_MAP_COMMON + 0x20000) - -#define FSMC_Bank2_MAP_ATTR_DATA (FSMC_Bank2_MAP_ATTR + 0) -#define FSMC_Bank2_MAP_ATTR_CMD (FSMC_Bank2_MAP_ATTR + 0x10000) -#define FSMC_Bank2_MAP_ATTR_ADDR (FSMC_Bank2_MAP_ATTR + 0x20000) - -/* - * Bank 3 (NAND) - */ -#define FSMC_Bank3_MAP_COMMON (FSMC_Bank3_MAP_BASE + 0) -#define FSMC_Bank3_MAP_ATTR (FSMC_Bank3_MAP_BASE + 0x8000000) - -#define FSMC_Bank3_MAP_COMMON_DATA (FSMC_Bank3_MAP_COMMON + 0) -#define FSMC_Bank3_MAP_COMMON_CMD (FSMC_Bank3_MAP_COMMON + 0x10000) -#define FSMC_Bank3_MAP_COMMON_ADDR (FSMC_Bank3_MAP_COMMON + 0x20000) - -#define FSMC_Bank3_MAP_ATTR_DATA (FSMC_Bank3_MAP_ATTR + 0) -#define FSMC_Bank3_MAP_ATTR_CMD (FSMC_Bank3_MAP_ATTR + 0x10000) -#define FSMC_Bank3_MAP_ATTR_ADDR (FSMC_Bank3_MAP_ATTR + 0x20000) - -/* - * Bank 4 (PC card) - */ -#define FSMC_Bank4_MAP_COMMON (FSMC_Bank4_MAP_BASE + 0) -#define FSMC_Bank4_MAP_ATTR (FSMC_Bank4_MAP_BASE + 0x8000000) -#define FSMC_Bank4_MAP_IO (FSMC_Bank4_MAP_BASE + 0xC000000) - -/* - * More convenient typedefs than CMSIS has - */ -typedef struct { - __IO uint32_t PCR; /**< NAND Flash control */ - __IO uint32_t SR; /**< NAND Flash FIFO status and interrupt */ - __IO uint32_t PMEM; /**< NAND Flash Common memory space timing */ - __IO uint32_t PATT; /**< NAND Flash Attribute memory space timing */ - uint32_t RESERVED0; /**< Reserved, 0x70 */ - __IO uint32_t ECCR; /**< NAND Flash ECC result registers */ -} FSMC_NAND_TypeDef; - -typedef struct { - __IO uint32_t PCR; /**< PC Card control */ - __IO uint32_t SR; /**< PC Card FIFO status and interrupt */ - __IO uint32_t PMEM; /**< PC Card Common memory space timing */ - __IO uint32_t PATT; /**< PC Card Attribute memory space timing */ - __IO uint32_t PIO; /**< PC Card I/O space timing */ -} FSMC_PCCard_TypeDef; - -typedef struct { - __IO uint32_t BCR; /**< SRAM/NOR chip-select control registers */ - __IO uint32_t BTR; /**< SRAM/NOR chip-select timing registers */ - uint32_t RESERVED[63]; /**< Reserved */ - __IO uint32_t BWTR; /**< SRAM/NOR write timing registers */ -} FSMC_SRAM_NOR_TypeDef; - -#if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F7)) - -typedef struct { - __IO uint32_t SDCR1; /**< SDRAM control register (bank 1) */ - __IO uint32_t SDCR2; /**< SDRAM control register (bank 2) */ - __IO uint32_t SDTR1; /**< SDRAM timing register (bank 1) */ - __IO uint32_t SDTR2; /**< SDRAM timing register (bank 2) */ - __IO uint32_t SDCMR; /**< SDRAM comand mode register */ - __IO uint32_t SDRTR; /**< SDRAM refresh timer register */ - __IO uint32_t SDSR; /**< SDRAM status register */ -} FSMC_SDRAM_TypeDef; - -#endif - -/** - * @brief PCR register - */ -#define FSMC_PCR_PWAITEN ((uint32_t)1 << 1) -#define FSMC_PCR_PBKEN ((uint32_t)1 << 2) -#define FSMC_PCR_PTYP ((uint32_t)1 << 3) -#define FSMC_PCR_PWID_8 ((uint32_t)0 << 4) -#define FSMC_PCR_PWID_16 ((uint32_t)1 << 4) -#define FSMC_PCR_PWID_RESERVED1 ((uint32_t)2 << 4) -#define FSMC_PCR_PWID_RESERVED2 ((uint32_t)3 << 4) -#define FSMC_PCR_PWID_MASK ((uint32_t)3 << 4) -#define FSMC_PCR_ECCEN ((uint32_t)1 << 6) -#define FSMC_PCR_PTYP_PCCARD 0 -#define FSMC_PCR_PTYP_NAND FSMC_PCR_PTYP - -/** - * @brief SR register - */ -#define FSMC_SR_IRS ((uint8_t)0x01) -#define FSMC_SR_ILS ((uint8_t)0x02) -#define FSMC_SR_IFS ((uint8_t)0x04) -#define FSMC_SR_IREN ((uint8_t)0x08) -#define FSMC_SR_ILEN ((uint8_t)0x10) -#define FSMC_SR_IFEN ((uint8_t)0x20) -#define FSMC_SR_FEMPT ((uint8_t)0x40) -#define FSMC_SR_ISR_MASK (FSMC_SR_IRS | FSMC_SR_ILS | FSMC_SR_IFS) - -/** - * @brief BCR register - */ -#define FSMC_BCR_MBKEN ((uint32_t)1 << 0) -#define FSMC_BCR_MUXEN ((uint32_t)1 << 1) -#define FSMC_BCR_MTYP_SRAM ((uint32_t)0 << 2) -#define FSMC_BCR_MTYP_PSRAM ((uint32_t)1 << 2) -#define FSMC_BCR_MTYP_NOR_NAND ((uint32_t)2 << 2) -#define FSMC_BCR_MTYP_RESERVED ((uint32_t)3 << 2) -#define FSMC_BCR_MWID_8 ((uint32_t)0 << 4) -#define FSMC_BCR_MWID_16 ((uint32_t)1 << 4) -#if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F7)) -#define FSMC_BCR_MWID_32 ((uint32_t)2 << 4) -#else -#define FSMC_BCR_MWID_RESERVED1 ((uint32_t)2 << 4) -#endif -#define FSMC_BCR_MWID_RESERVED2 ((uint32_t)3 << 4) -#define FSMC_BCR_FACCEN ((uint32_t)1 << 6) -#define FSMC_BCR_BURSTEN ((uint32_t)1 << 8) -#define FSMC_BCR_WAITPOL ((uint32_t)1 << 9) -#define FSMC_BCR_WRAPMOD ((uint32_t)1 << 10) -#define FSMC_BCR_WAITCFG ((uint32_t)1 << 11) -#define FSMC_BCR_WREN ((uint32_t)1 << 12) -#define FSMC_BCR_WAITEN ((uint32_t)1 << 13) -#define FSMC_BCR_EXTMOD ((uint32_t)1 << 14) -#define FSMC_BCR_ASYNCWAIT ((uint32_t)1 << 15) -#define FSMC_BCR_CBURSTRW ((uint32_t)1 << 19) -#if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F7)) -#define FSMC_BCR_CCLKEN ((uint32_t)1 << 20) -#endif -#if (defined(STM32F7)) -#define FSMC_BCR_WFDIS ((uint32_t)1 << 21) -#endif - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief FSMC driver enable switch. - * @details If set to @p TRUE the support for FSMC is included. - */ -#if !defined(STM32_FSMC_USE_FSMC1) || defined(__DOXYGEN__) -#define STM32_FSMC_USE_FSMC1 FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ -#if !STM32_FSMC_USE_FSMC1 -#error "FSMC driver activated but no FSMC peripheral assigned" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a structure representing an FSMC driver. - */ -typedef struct FSMCDriver FSMCDriver; - -/** - * @brief Driver state machine possible states. - */ -typedef enum { - FSMC_UNINIT = 0, /**< Not initialized. */ - FSMC_STOP = 1, /**< Stopped. */ - FSMC_READY = 2, /**< Ready. */ -} fsmcstate_t; - -/** - * @brief Structure representing an FSMC driver. - */ -struct FSMCDriver { - /** - * @brief Driver state. - */ - fsmcstate_t state; - /* End of the mandatory fields.*/ - -#if STM32_SRAM_USE_FSMC_SRAM1 - FSMC_SRAM_NOR_TypeDef *sram1; -#endif -#if STM32_SRAM_USE_FSMC_SRAM2 - FSMC_SRAM_NOR_TypeDef *sram2; -#endif -#if STM32_SRAM_USE_FSMC_SRAM3 - FSMC_SRAM_NOR_TypeDef *sram3; -#endif -#if STM32_SRAM_USE_FSMC_SRAM4 - FSMC_SRAM_NOR_TypeDef *sram4; -#endif -#if STM32_NAND_USE_FSMC_NAND1 - FSMC_NAND_TypeDef *nand1; -#endif -#if STM32_NAND_USE_FSMC_NAND2 - FSMC_NAND_TypeDef *nand2; -#endif -#if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F7)) - #if STM32_USE_FSMC_SDRAM - FSMC_SDRAM_TypeDef *sdram; - #endif -#endif -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_FSMC_USE_FSMC1 && !defined(__DOXYGEN__) -extern FSMCDriver FSMCD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void fsmc_init(void); - void fsmc_start(FSMCDriver *fsmcp); - void fsmc_stop(FSMCDriver *fsmcp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_FSMC */ - -#endif /* HAL_FSMC_H_ */ - -/** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.c new file mode 100644 index 0000000..895fd28 --- /dev/null +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.c @@ -0,0 +1,590 @@ +/* + ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_fsmc_nand_lld.c + * @brief FSMC NAND Driver subsystem low level driver source. + * + * @addtogroup NAND + * @{ + */ + +#include "hal.h" + +#if (HAL_USE_FSMC_NAND == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ +#define NAND_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_NAND_DMA_STREAM, \ + STM32_FSMC_DMA_CHN) + +/** + * @brief Bus width of NAND IC. + * @details Must be 8 or 16 + */ +#if ! defined(STM32_NAND_BUS_WIDTH) || defined(__DOXYGEN__) +#define STM32_NAND_BUS_WIDTH 8 +#endif + +/** + * @brief DMA transaction width on AHB bus in bytes + */ +#define AHB_TRANSACTION_WIDTH 2 + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief NAND1 driver identifier. + */ +#if STM32_NAND_USE_FSMC_NAND1 || defined(__DOXYGEN__) +NANDDriver NANDD1; +#endif + +/** + * @brief NAND2 driver identifier. + */ +#if STM32_NAND_USE_FSMC_NAND2 || defined(__DOXYGEN__) +NANDDriver NANDD2; +#endif + +/*===========================================================================*/ +/* Driver local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Helper function. + * + * @notapi + */ +static void align_check(const void *ptr, uint32_t len) { + osalDbgCheck((((uint32_t)ptr % AHB_TRANSACTION_WIDTH) == 0) && + ((len % AHB_TRANSACTION_WIDTH) == 0) && + (len >= AHB_TRANSACTION_WIDTH)); + (void)ptr; + (void)len; +} + +/** + * @brief Work around errata in STM32's FSMC core. + * @details Constant output clock (if enabled) disappears when CLKDIV value + * sets to 1 (FMC_CLK period = 2 × HCLK periods) AND 8-bit async + * transaction generated on AHB. This workaround eliminates 8-bit + * transactions on bus when you use 8-bit memory. It suitable only + * for 8-bit memory (i.e. PWID bits in PCR register must be set + * to 8-bit mode). + * + * @notapi + */ +static void set_16bit_bus(NANDDriver *nandp) { +#if STM32_NAND_BUS_WIDTH + nandp->nand->PCR |= FSMC_PCR_PWID_16; +#else + (void)nandp; +#endif +} + +static void set_8bit_bus(NANDDriver *nandp) { +#if STM32_NAND_BUS_WIDTH + nandp->nand->PCR &= ~FSMC_PCR_PWID_16; +#else + (void)nandp; +#endif +} + +/** + * @brief Wakes up the waiting thread. + * + * @param[in] nandp pointer to the @p NANDDriver object + * @param[in] msg wakeup message + * + * @notapi + */ +static void wakeup_isr(NANDDriver *nandp) { + + osalDbgCheck(nandp->thread != NULL); + osalThreadResumeI(&nandp->thread, MSG_OK); +} + +/** + * @brief Put calling thread in suspend and switch driver state + * + * @param[in] nandp pointer to the @p NANDDriver object + */ +static void nand_lld_suspend_thread(NANDDriver *nandp) { + + osalThreadSuspendS(&nandp->thread); +} + +/** + * @brief Caclulate ECCPS register value + * + * @param[in] nandp pointer to the @p NANDDriver object + */ +static uint32_t calc_eccps(NANDDriver *nandp) { + + uint32_t i = 0; + uint32_t eccps = nandp->config->page_data_size; + + eccps = eccps >> 9; + while (eccps > 0){ + i++; + eccps >>= 1; + } + + return i << 17; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief Enable interrupts from NAND + * + * @param[in] nandp pointer to the @p NANDDriver object + * + * @notapi + */ +static void nand_ready_isr_enable(NANDDriver *nandp) { + + nandp->nand->SR &= ~(FSMC_SR_IRS | FSMC_SR_ILS | FSMC_SR_IFS | + FSMC_SR_ILEN | FSMC_SR_IFEN); + nandp->nand->SR |= FSMC_SR_IREN; +} + +/** + * @brief Disable interrupts from NAND + * + * @param[in] nandp pointer to the @p NANDDriver object + * + * @notapi + */ +static void nand_ready_isr_disable(NANDDriver *nandp) { + + nandp->nand->SR &= ~FSMC_SR_IREN; +} + +/** + * @brief Ready interrupt handler + * + * @param[in] nandp pointer to the @p NANDDriver object + * + * @notapi + */ +static void nand_isr_handler(NANDDriver *nandp) { + + osalSysLockFromISR(); + + osalDbgCheck(nandp->nand->SR & FSMC_SR_IRS); /* spurious interrupt happened */ + nandp->nand->SR &= ~FSMC_SR_IRS; + + switch (nandp->state){ + case NAND_READ: + nandp->state = NAND_DMA_RX; + dmaStartMemCopy(nandp->dma, nandp->dmamode, nandp->map_data, nandp->rxdata, + nandp->datalen/AHB_TRANSACTION_WIDTH); + /* thread will be waked up from DMA ISR */ + break; + + case NAND_ERASE: /* NAND reports about erase finish */ + case NAND_PROGRAM: /* NAND reports about page programming finish */ + case NAND_RESET: /* NAND reports about finished reset recover */ + nandp->state = NAND_READY; + wakeup_isr(nandp); + break; + + default: + osalSysHalt("Unhandled case"); + break; + } + osalSysUnlockFromISR(); +} + +/** + * @brief DMA RX end IRQ handler. + * + * @param[in] nandp pointer to the @p NANDDriver object + * @param[in] flags pre-shifted content of the ISR register + * + * @notapi + */ +static void nand_lld_serve_transfer_end_irq(NANDDriver *nandp, uint32_t flags) { + /* DMA errors handling.*/ +#if defined(STM32_NAND_DMA_ERROR_HOOK) + if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { + STM32_NAND_DMA_ERROR_HOOK(nandp); + } +#else + (void)flags; +#endif + + osalSysLockFromISR(); + + dmaStreamDisable(nandp->dma); + + switch (nandp->state){ + case NAND_DMA_TX: + nandp->state = NAND_PROGRAM; + nandp->map_cmd[0] = NAND_CMD_PAGEPROG; + /* thread will be woken up from ready_isr() */ + break; + + case NAND_DMA_RX: + nandp->state = NAND_READY; + nandp->rxdata = NULL; + nandp->datalen = 0; + wakeup_isr(nandp); + break; + + default: + osalSysHalt("Unhandled case"); + break; + } + + osalSysUnlockFromISR(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level NAND driver initialization. + * + * @notapi + */ +void nand_lld_init(void) { + + fsmc_init(); + +#if STM32_NAND_USE_FSMC_NAND1 + /* Driver initialization.*/ + nandObjectInit(&NANDD1); + NANDD1.rxdata = NULL; + NANDD1.datalen = 0; + NANDD1.thread = NULL; + NANDD1.dma = STM32_DMA_STREAM(STM32_NAND_DMA_STREAM); + NANDD1.nand = FSMCD1.nand1; + NANDD1.map_data = (void *)FSMC_Bank2_MAP_COMMON_DATA; + NANDD1.map_cmd = (uint16_t *)FSMC_Bank2_MAP_COMMON_CMD; + NANDD1.map_addr = (uint16_t *)FSMC_Bank2_MAP_COMMON_ADDR; + NANDD1.bb_map = NULL; +#endif /* STM32_NAND_USE_FSMC_NAND1 */ + +#if STM32_NAND_USE_FSMC_NAND2 + /* Driver initialization.*/ + nandObjectInit(&NANDD2); + NANDD2.rxdata = NULL; + NANDD2.datalen = 0; + NANDD2.thread = NULL; + NANDD2.dma = STM32_DMA_STREAM(STM32_NAND_DMA_STREAM); + NANDD2.nand = FSMCD1.nand2; + NANDD2.map_data = (void *)FSMC_Bank3_MAP_COMMON_DATA; + NANDD2.map_cmd = (uint16_t *)FSMC_Bank3_MAP_COMMON_CMD; + NANDD2.map_addr = (uint16_t *)FSMC_Bank3_MAP_COMMON_ADDR; + NANDD2.bb_map = NULL; +#endif /* STM32_NAND_USE_FSMC_NAND2 */ +} + +/** + * @brief Configures and activates the NAND peripheral. + * + * @param[in] nandp pointer to the @p NANDDriver object + * + * @notapi + */ +void nand_lld_start(NANDDriver *nandp) { + + bool b; + uint32_t dmasize; + uint32_t pcr_bus_width; + + if (FSMCD1.state == FSMC_STOP) + fsmc_start(&FSMCD1); + + if (nandp->state == NAND_STOP) { + b = dmaStreamAlloc(nandp->dma, + STM32_EMC_FSMC1_IRQ_PRIORITY, + (stm32_dmaisr_t)nand_lld_serve_transfer_end_irq, + (void *)nandp); + osalDbgAssert(!b, "stream already allocated"); + +#if AHB_TRANSACTION_WIDTH == 4 + dmasize = STM32_DMA_CR_PSIZE_WORD | STM32_DMA_CR_MSIZE_WORD; +#elif AHB_TRANSACTION_WIDTH == 2 + dmasize = STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; +#elif AHB_TRANSACTION_WIDTH == 1 + dmasize = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE; +#else +#error "Incorrect AHB_TRANSACTION_WIDTH" +#endif + + nandp->dmamode = STM32_DMA_CR_CHSEL(NAND_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_NAND_NAND1_DMA_PRIORITY) | + dmasize | + STM32_DMA_CR_DMEIE | + STM32_DMA_CR_TEIE | + STM32_DMA_CR_TCIE; + +#if STM32_NAND_BUS_WIDTH == 8 + pcr_bus_width = FSMC_PCR_PWID_8; +#elif STM32_NAND_BUS_WIDTH == 16 + pcr_bus_width = FSMC_PCR_PWID_16; +#else +#error "Bus width must be 8 or 16 bits" +#endif + nandp->nand->PCR = pcr_bus_width | calc_eccps(nandp) | + FSMC_PCR_PTYP_NAND | FSMC_PCR_PBKEN; + nandp->nand->PMEM = nandp->config->pmem; + nandp->nand->PATT = nandp->config->pmem; + nandp->isr_handler = nand_isr_handler; + nand_ready_isr_enable(nandp); + } +} + +/** + * @brief Deactivates the NAND peripheral. + * + * @param[in] nandp pointer to the @p NANDDriver object + * + * @notapi + */ +void nand_lld_stop(NANDDriver *nandp) { + + if (nandp->state == NAND_READY) { + dmaStreamFree(nandp->dma); + nandp->nand->PCR &= ~FSMC_PCR_PBKEN; + nand_ready_isr_disable(nandp); + nandp->isr_handler = NULL; + } +} + +/** + * @brief Read data from NAND. + * + * @param[in] nandp pointer to the @p NANDDriver object + * @param[out] data pointer to data buffer + * @param[in] datalen size of data buffer in bytes + * @param[in] addr pointer to address buffer + * @param[in] addrlen length of address + * @param[out] ecc pointer to store computed ECC. Ignored when NULL. + * + * @notapi + */ +void nand_lld_read_data(NANDDriver *nandp, uint16_t *data, size_t datalen, + uint8_t *addr, size_t addrlen, uint32_t *ecc){ + + align_check(data, datalen); + + nandp->state = NAND_READ; + nandp->rxdata = data; + nandp->datalen = datalen; + + set_16bit_bus(nandp); + nand_lld_write_cmd(nandp, NAND_CMD_READ0); + nand_lld_write_addr(nandp, addr, addrlen); + osalSysLock(); + nand_lld_write_cmd(nandp, NAND_CMD_READ0_CONFIRM); + set_8bit_bus(nandp); + + /* Here NAND asserts busy signal and starts transferring from memory + array to page buffer. After the end of transmission ready_isr functions + starts DMA transfer from page buffer to MCU's RAM.*/ + osalDbgAssert((nandp->nand->PCR & FSMC_PCR_ECCEN) == 0, + "State machine broken. ECCEN must be previously disabled."); + + if (NULL != ecc){ + nandp->nand->PCR |= FSMC_PCR_ECCEN; + } + + nand_lld_suspend_thread(nandp); + osalSysUnlock(); + + /* thread was woken up from DMA ISR */ + if (NULL != ecc){ + while (! (nandp->nand->SR & FSMC_SR_FEMPT)) + ; + *ecc = nandp->nand->ECCR; + nandp->nand->PCR &= ~FSMC_PCR_ECCEN; + } +} + +/** + * @brief Write data to NAND. + * + * @param[in] nandp pointer to the @p NANDDriver object + * @param[in] data buffer with data to be written + * @param[in] datalen size of data buffer in bytes + * @param[in] addr pointer to address buffer + * @param[in] addrlen length of address + * @param[out] ecc pointer to store computed ECC. Ignored when NULL. + * + * @return The operation status reported by NAND IC (0x70 command). + * + * @notapi + */ +uint8_t nand_lld_write_data(NANDDriver *nandp, const uint16_t *data, + size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc) { + + align_check(data, datalen); + + nandp->state = NAND_WRITE; + + set_16bit_bus(nandp); + nand_lld_write_cmd(nandp, NAND_CMD_WRITE); + osalSysLock(); + nand_lld_write_addr(nandp, addr, addrlen); + set_8bit_bus(nandp); + + /* Now start DMA transfer to NAND buffer and put thread in sleep state. + Tread will be woken up from ready ISR. */ + nandp->state = NAND_DMA_TX; + osalDbgAssert((nandp->nand->PCR & FSMC_PCR_ECCEN) == 0, + "State machine broken. ECCEN must be previously disabled."); + + if (NULL != ecc){ + nandp->nand->PCR |= FSMC_PCR_ECCEN; + } + + dmaStartMemCopy(nandp->dma, nandp->dmamode, data, nandp->map_data, + datalen/AHB_TRANSACTION_WIDTH); + + nand_lld_suspend_thread(nandp); + osalSysUnlock(); + + if (NULL != ecc){ + while (! (nandp->nand->SR & FSMC_SR_FEMPT)) + ; + *ecc = nandp->nand->ECCR; + nandp->nand->PCR &= ~FSMC_PCR_ECCEN; + } + + return nand_lld_read_status(nandp); +} + +/** + * @brief Soft reset NAND device. + * + * @param[in] nandp pointer to the @p NANDDriver object + * + * @notapi + */ +void nand_lld_reset(NANDDriver *nandp) { + + nandp->state = NAND_RESET; + + set_16bit_bus(nandp); + nand_lld_write_cmd(nandp, NAND_CMD_RESET); + set_8bit_bus(nandp); + + osalSysLock(); + nand_lld_suspend_thread(nandp); + osalSysUnlock(); +} + +/** + * @brief Erase block. + * + * @param[in] nandp pointer to the @p NANDDriver object + * @param[in] addr pointer to address buffer + * @param[in] addrlen length of address + * + * @return The operation status reported by NAND IC (0x70 command). + * + * @notapi + */ +uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen) { + + nandp->state = NAND_ERASE; + + set_16bit_bus(nandp); + nand_lld_write_cmd(nandp, NAND_CMD_ERASE); + nand_lld_write_addr(nandp, addr, addrlen); + osalSysLock(); + nand_lld_write_cmd(nandp, NAND_CMD_ERASE_CONFIRM); + set_8bit_bus(nandp); + + nand_lld_suspend_thread(nandp); + osalSysUnlock(); + + return nand_lld_read_status(nandp); +} + +/** + * @brief Send addres to NAND. + * + * @param[in] nandp pointer to the @p NANDDriver object + * @param[in] len length of address array + * @param[in] addr pointer to address array + * + * @notapi + */ +void nand_lld_write_addr(NANDDriver *nandp, const uint8_t *addr, size_t len) { + size_t i = 0; + + for (i=0; imap_addr[i] = addr[i]; +} + +/** + * @brief Send command to NAND. + * + * @param[in] nandp pointer to the @p NANDDriver object + * @param[in] cmd command value + * + * @notapi + */ +void nand_lld_write_cmd(NANDDriver *nandp, uint8_t cmd) { + nandp->map_cmd[0] = cmd; +} + +/** + * @brief Read status byte from NAND. + * + * @param[in] nandp pointer to the @p NANDDriver object + * + * @return Status byte. + * + * @notapi + */ +uint8_t nand_lld_read_status(NANDDriver *nandp) { + + uint16_t status; + + set_16bit_bus(nandp); + nand_lld_write_cmd(nandp, NAND_CMD_STATUS); + set_8bit_bus(nandp); + status = nandp->map_data[0]; + + return status & 0xFF; +} + +#endif /* HAL_USE_NAND */ + +/** @} */ + diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.h new file mode 100644 index 0000000..f47ee75 --- /dev/null +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.h @@ -0,0 +1,289 @@ +/* + ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_fsmc_nand_lld.h + * @brief FSMC NAND Driver subsystem low level driver header. + * + * @addtogroup NAND + * @{ + */ + +#ifndef HAL_FSMC_NAND_LLD_H_ +#define HAL_FSMC_NAND_LLD_H_ + +#include "bitmap.h" + +#if (HAL_USE_FSMC_NAND == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ +#define NAND_MIN_PAGE_SIZE 256 +#define NAND_MAX_PAGE_SIZE 8192 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief FSMC1 interrupt priority level setting. + */ +#if !defined(STM32_EMC_FSMC1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EMC_FSMC1_IRQ_PRIORITY 10 +#endif + +/** + * @brief NAND driver enable switch. + * @details If set to @p TRUE the support for NAND1 is included. + */ +#if !defined(STM32_FSMC_USE_NAND1) || defined(__DOXYGEN__) +#define STM32_FSMC_USE_NAND1 FALSE +#endif + +/** + * @brief NAND driver enable switch. + * @details If set to @p TRUE the support for NAND2 is included. + */ +#if !defined(STM32_FSMC_USE_NAND2) || defined(__DOXYGEN__) +#define STM32_FSMC_USE_NAND2 FALSE +#endif + +/** + * @brief NAND DMA error hook. + * @note The default action for DMA errors is a system halt because DMA + * error can only happen because programming errors. + */ +#if !defined(STM32_FSMC_DMA_ERROR_HOOK) || defined(__DOXYGEN__) +#define STM32_FSMC_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure") +#endif + +/** + * @brief NAND interrupt enable switch. + * @details If set to @p TRUE the support for internal FSMC interrupt included. + */ +#if !defined(STM32_FSMC_NAND_USE_INT) || defined(__DOXYGEN__) +#define STM32_FSMC_NAND_USE_INT FALSE +#endif + +/** +* @brief NAND1 DMA priority (0..3|lowest..highest). +*/ +#if !defined(STM32_FSMC_NAND1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_FSMC_NAND1_DMA_PRIORITY 0 +#endif + +/** +* @brief NAND2 DMA priority (0..3|lowest..highest). +*/ +#if !defined(STM32_FSMC_NAND2_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_FSMC_NAND2_DMA_PRIORITY 0 +#endif + +/** + * @brief DMA stream used for NAND operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_FSMC_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_FSMC_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !STM32_FSMC_USE_NAND1 && !STM32_FSMC_USE_NAND2 +#error "NAND driver activated but no NAND peripheral assigned" +#endif + +#if (STM32_FSMC_USE_NAND1 || STM32_FSMC_USE_NAND2) && !STM32_HAS_FSMC +#error "FSMC not present in the selected device" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an NAND driver. + */ +typedef struct NANDDriver NANDDriver; + +/** + * @brief Type of interrupt handler function. + */ +typedef void (*nandisrhandler_t)(NANDDriver *nandp); + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Number of erase blocks in NAND device. + */ + uint32_t blocks; + /** + * @brief Number of data bytes in page. + */ + uint32_t page_data_size; + /** + * @brief Number of spare bytes in page. + */ + uint32_t page_spare_size; + /** + * @brief Number of pages in block. + */ + uint32_t pages_per_block; + /** + * @brief Number of write cycles for row addressing. + */ + uint8_t rowcycles; + /** + * @brief Number of write cycles for column addressing. + */ + uint8_t colcycles; + + /* End of the mandatory fields.*/ + /** + * @brief Number of wait cycles. This value will be used both for + * PMEM and PATTR registers + * + * @note For proper calculation procedure please look at AN2784 document + * from STMicroelectronics. + */ + uint32_t pmem; +} NANDConfig; + +/** + * @brief Structure representing an NAND driver. + */ +struct NANDDriver { + /** + * @brief Driver state. + */ + nandstate_t state; + /** + * @brief Current configuration data. + */ + const NANDConfig *config; + /** + * @brief Array to store bad block map. + */ +#if NAND_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + mutex_t mutex; +#elif CH_CFG_USE_SEMAPHORES + semaphore_t semaphore; +#endif +#endif /* NAND_USE_MUTUAL_EXCLUSION */ + /* End of the mandatory fields.*/ + /** + * @brief Function enabling interrupts from FSMC. + */ + nandisrhandler_t isr_handler; + /** + * @brief Pointer to current transaction buffer. + */ + void *rxdata; + /** + * @brief Current transaction length in bytes. + */ + size_t datalen; + /** + * @brief DMA mode bit mask. + */ + uint32_t dmamode; + /** + * @brief DMA channel. + */ + const stm32_dma_stream_t *dma; + /** + * @brief Thread waiting for I/O completion. + */ + thread_t *thread; + /** + * @brief Pointer to the FSMC NAND registers block. + */ + FSMC_NAND_TypeDef *nand; + /** + * @brief Memory mapping for data. + */ + uint16_t *map_data; + /** + * @brief Memory mapping for commands. + */ + uint16_t *map_cmd; + /** + * @brief Memory mapping for addresses. + */ + uint16_t *map_addr; + /** + * @brief Pointer to bad block map. + * @details One bit per block. All memory allocation is user's responsibility. + */ + bitmap_t *bb_map; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_FSMC_USE_NAND1 && !defined(__DOXYGEN__) +extern NANDDriver NANDD1; +#endif + +#if STM32_FSMC_USE_NAND2 && !defined(__DOXYGEN__) +extern NANDDriver NANDD2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void nand_lld_init(void); + void nand_lld_start(NANDDriver *nandp); + void nand_lld_stop(NANDDriver *nandp); + uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen); + void nand_lld_read_data(NANDDriver *nandp, uint16_t *data, + size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc); + void nand_lld_write_addr(NANDDriver *nandp, const uint8_t *addr, size_t len); + void nand_lld_write_cmd(NANDDriver *nandp, uint8_t cmd); + uint8_t nand_lld_write_data(NANDDriver *nandp, const uint16_t *data, + size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc); + uint8_t nand_lld_read_status(NANDDriver *nandp); + void nand_lld_reset(NANDDriver *nandp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_FSMC_NAND */ + +#endif /* HAL_FSMC_NAND_LLD_H_ */ + +/** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c deleted file mode 100644 index 6d727c8..0000000 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c +++ /dev/null @@ -1,215 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - SDRAM routines added by Nick Klimov aka progfin. - */ - -/** - * @file hal_fsmc_sdram.c - * @brief SDRAM Driver subsystem low level driver source. - * - * @addtogroup SDRAM - * @{ - */ - -#include "hal.h" - -#if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F745xx) || defined(STM32F746xx) || \ - defined(STM32F756xx) || defined(STM32F767xx) || \ - defined(STM32F769xx) || defined(STM32F777xx) || \ - defined(STM32F779xx)) - -#if (STM32_USE_FSMC_SDRAM == TRUE) || defined(__DOXYGEN__) - -#include "hal_fsmc_sdram.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/** - * FMC_Command_Mode - */ -#define FMCCM_NORMAL ((uint32_t)0x00000000) -#define FMCCM_CLK_ENABLED ((uint32_t)0x00000001) -#define FMCCM_PALL ((uint32_t)0x00000002) -#define FMCCM_AUTO_REFRESH ((uint32_t)0x00000003) -#define FMCCM_LOAD_MODE ((uint32_t)0x00000004) -#define FMCCM_SELFREFRESH ((uint32_t)0x00000005) -#define FMCCM_POWER_DOWN ((uint32_t)0x00000006) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ -/** - * @brief SDRAM driver identifier. - */ -SDRAMDriver SDRAMD; - -/*===========================================================================*/ -/* Driver local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Wait until the SDRAM controller is ready. - * - * @notapi - */ -static void _sdram_wait_ready(void) { - /* Wait until the SDRAM controller is ready */ - while (SDRAMD.sdram->SDSR & FMC_SDSR_BUSY); -} - -/** - * @brief Executes the SDRAM memory initialization sequence. - * - * @param[in] cfgp pointer to the @p SDRAMConfig object - * - * @notapi - */ -static void _sdram_init_sequence(const SDRAMConfig *cfgp) { - - uint32_t command_target = 0; - -#if STM32_SDRAM_USE_FSMC_SDRAM1 - command_target |= FMC_SDCMR_CTB1; -#endif -#if STM32_SDRAM_USE_FSMC_SDRAM2 - command_target |= FMC_SDCMR_CTB2; -#endif - - /* Step 3: Configure a clock configuration enable command.*/ - _sdram_wait_ready(); - SDRAMD.sdram->SDCMR = FMCCM_CLK_ENABLED | command_target; - - /* Step 4: Insert delay (tipically 100uS).*/ - osalThreadSleepMilliseconds(1); - - /* Step 5: Configure a PALL (precharge all) command.*/ - _sdram_wait_ready(); - SDRAMD.sdram->SDCMR = FMCCM_PALL | command_target; - - /* Step 6.1: Configure a Auto-Refresh command: send the first command.*/ - _sdram_wait_ready(); - SDRAMD.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target | - (cfgp->sdcmr & FMC_SDCMR_NRFS); - - /* Step 6.2: Send the second command.*/ - _sdram_wait_ready(); - SDRAMD.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target | - (cfgp->sdcmr & FMC_SDCMR_NRFS); - - /* Step 7: Program the external memory mode register.*/ - _sdram_wait_ready(); - SDRAMD.sdram->SDCMR = FMCCM_LOAD_MODE | command_target | - (cfgp->sdcmr & FMC_SDCMR_MRD); - - /* Step 8: Set clock.*/ - _sdram_wait_ready(); - SDRAMD.sdram->SDRTR = cfgp->sdrtr & FMC_SDRTR_COUNT; - - _sdram_wait_ready(); -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level SDRAM driver initialization. - */ -void fsmcSdramInit(void) { - - fsmc_init(); - - SDRAMD.sdram = FSMCD1.sdram; - SDRAMD.state = SDRAM_STOP; -} - -/** - * @brief Configures and activates the SDRAM peripheral. - * - * @param[in] sdramp pointer to the @p SDRAMDriver object - * @param[in] cfgp pointer to the @p SDRAMConfig object - */ -void fsmcSdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp) { - - if (FSMCD1.state == FSMC_STOP) - fsmc_start(&FSMCD1); - - osalDbgAssert((sdramp->state == SDRAM_STOP) || (sdramp->state == SDRAM_READY), - "SDRAM. Invalid state."); - - if (sdramp->state == SDRAM_STOP) { - - /* Even if you need only bank2 you must properly set up SDCR and SDTR - regitsters for bank1 too. Both banks will be tuned equally assuming - connected memory ICs are equal.*/ - sdramp->sdram->SDCR1 = cfgp->sdcr; - sdramp->sdram->SDTR1 = cfgp->sdtr; - sdramp->sdram->SDCR2 = cfgp->sdcr; - sdramp->sdram->SDTR2 = cfgp->sdtr; - - _sdram_init_sequence(cfgp); - - sdramp->state = SDRAM_READY; - } -} - -/** - * @brief Deactivates the SDRAM peripheral. - * - * @param[in] sdramp pointer to the @p SDRAMDriver object - * - * @notapi - */ -void fsmcSdramStop(SDRAMDriver *sdramp) { - - uint32_t command_target = 0; - -#if STM32_SDRAM_USE_FSMC_SDRAM1 - command_target |= FMC_SDCMR_CTB1; -#endif -#if STM32_SDRAM_USE_FSMC_SDRAM2 - command_target |= FMC_SDCMR_CTB2; -#endif - - if (sdramp->state == SDRAM_READY) { - SDRAMD.sdram->SDCMR = FMCCM_POWER_DOWN | command_target; - sdramp->state = SDRAM_STOP; - } -} - -#endif /* STM32_USE_FSMC_SDRAM */ - -#endif /* STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx */ - -/** @} */ - diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h deleted file mode 100644 index c9f9de0..0000000 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h +++ /dev/null @@ -1,175 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - SDRAM routines added by Nick Klimov aka progfin. - */ - -/** - * @file hal_fsmc_sdram.h - * @brief SDRAM Driver subsystem low level driver header. - * - * @addtogroup SDRAM - * @{ - */ - -#ifndef HAL_FMC_SDRAM_H_ -#define HAL_FMC_SDRAM_H_ - -#if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F745xx) || defined(STM32F746xx) || \ - defined(STM32F756xx) || defined(STM32F767xx) || \ - defined(STM32F769xx) || defined(STM32F777xx) || \ - defined(STM32F779xx)) - -#include "hal_fsmc.h" - -#if (STM32_USE_FSMC_SDRAM == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ -/** - * @name Configuration options - * @{ - */ - -/** - * @brief SDRAM driver enable switch. - * @details If set to @p TRUE the support for SDRAM1 is included. - */ -#if !defined(STM32_SDRAM_USE_FSMC_SDRAM1) || defined(__DOXYGEN__) -#define STM32_SDRAM_USE_FSMC_SDRAM1 FALSE -#else -#define STM32_SDRAM1_MAP_BASE FSMC_Bank5_MAP_BASE -#endif - -/** - * @brief SDRAM driver enable switch. - * @details If set to @p TRUE the support for SDRAM2 is included. - */ -#if !defined(STM32_SDRAM_USE_FSMC_SDRAM2) || defined(__DOXYGEN__) -#define STM32_SDRAM_USE_FSMC_SDRAM2 FALSE -#else -#define STM32_SDRAM2_MAP_BASE FSMC_Bank6_MAP_BASE -#endif - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !STM32_SDRAM_USE_FSMC_SDRAM1 && !STM32_SDRAM_USE_FSMC_SDRAM2 -#error "SDRAM driver activated but no SDRAM peripheral assigned" -#endif - -#if (STM32_SDRAM_USE_FSMC_SDRAM1 || STM32_SDRAM_USE_FSMC_SDRAM2) && !STM32_HAS_FSMC -#error "FMC not present in the selected device" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ -/** - * @brief Driver state machine possible states. - */ -typedef enum { - SDRAM_UNINIT = 0, /**< Not initialized. */ - SDRAM_STOP = 1, /**< Stopped. */ - SDRAM_READY = 2, /**< Ready. */ -} sdramstate_t; - -/** - * @brief Type of a structure representing an SDRAM driver. - */ -typedef struct SDRAMDriver SDRAMDriver; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief SDRAM control register. - * @note Its value will be used for both banks. - */ - uint32_t sdcr; - - /** - * @brief SDRAM timing register. - * @note Its value will be used for both banks. - */ - uint32_t sdtr; - - /** - * @brief SDRAM command mode register. - * @note Only its MRD and NRFS bits will be used. - */ - uint32_t sdcmr; - - /** - * @brief SDRAM refresh timer register. - * @note Only its COUNT bits will be used. - */ - uint32_t sdrtr; -} SDRAMConfig; - -/** - * @brief Structure representing an SDRAM driver. - */ -struct SDRAMDriver { - /** - * @brief Driver state. - */ - sdramstate_t state; - /** - * @brief Pointer to the FMC SDRAM registers block. - */ - FSMC_SDRAM_TypeDef *sdram; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -extern SDRAMDriver SDRAMD; - -#ifdef __cplusplus -extern "C" { -#endif - void fsmcSdramInit(void); - void fsmcSdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp); - void fsmcSdramStop(SDRAMDriver *sdramp); -#ifdef __cplusplus -} -#endif - -#endif /* STM32_USE_FSMC_SDRAM */ - -#endif /* STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx */ - -#endif /* HAL_FMC_SDRAM_H_ */ - -/** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c new file mode 100644 index 0000000..5934f88 --- /dev/null +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c @@ -0,0 +1,172 @@ +/* + ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + SDRAM routines added by Nick Klimov aka progfin. + */ + +/** + * @file hal_fsmc_sdram.c + * @brief SDRAM Driver subsystem low level driver source. + * + * @addtogroup SDRAM + * @{ + */ + +#include "hal.h" + +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F745xx) || defined(STM32F746xx) || \ + defined(STM32F756xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || \ + defined(STM32F779xx)) + +#if (STM32_FSMC_USE_SDRAM1 == TRUE) || (STM32_FSMC_USE_SDRAM2 == TRUE) || defined(__DOXYGEN__) + +#include "hal_fsmc_sdram_lld.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/** + * FMC_Command_Mode + */ +#define FMCCM_NORMAL ((uint32_t)0x00000000) +#define FMCCM_CLK_ENABLED ((uint32_t)0x00000001) +#define FMCCM_PALL ((uint32_t)0x00000002) +#define FMCCM_AUTO_REFRESH ((uint32_t)0x00000003) +#define FMCCM_LOAD_MODE ((uint32_t)0x00000004) +#define FMCCM_SELFREFRESH ((uint32_t)0x00000005) +#define FMCCM_POWER_DOWN ((uint32_t)0x00000006) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ +/** + * @brief SDRAM driver identifier. + */ +SDRAMDriver SDRAMD; + +/*===========================================================================*/ +/* Driver local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Wait until the SDRAM controller is ready. + * + * @notapi + */ +static void lld_sdram_wait_ready(void) { + /* Wait until the SDRAM controller is ready */ + while (SDRAMD.sdram->SDSR & FMC_SDSR_BUSY); +} + +/** + * @brief Executes the SDRAM memory initialization sequence. + * + * @param[in] cfgp pointer to the @p SDRAMConfig object + * + * @notapi + */ +static void lld_sdram_init_sequence(const SDRAMConfig *cfgp) { + + uint32_t command_target = 0; + +#if STM32_FSMC_USE_SDRAM1 + command_target |= FMC_SDCMR_CTB1; +#endif +#if STM32_FSMC_USE_SDRAM2 + command_target |= FMC_SDCMR_CTB2; +#endif + + /* Step 3: Configure a clock configuration enable command.*/ + lld_sdram_wait_ready(); + SDRAMD.sdram->SDCMR = FMCCM_CLK_ENABLED | command_target; + + /* Step 4: Insert delay (tipically 100uS).*/ + osalThreadSleepMilliseconds(1); + + /* Step 5: Configure a PALL (precharge all) command.*/ + lld_sdram_wait_ready(); + SDRAMD.sdram->SDCMR = FMCCM_PALL | command_target; + + /* Step 6.1: Configure a Auto-Refresh command: send the first command.*/ + lld_sdram_wait_ready(); + SDRAMD.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target | + (cfgp->sdcmr & FMC_SDCMR_NRFS); + + /* Step 6.2: Send the second command.*/ + lld_sdram_wait_ready(); + SDRAMD.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target | + (cfgp->sdcmr & FMC_SDCMR_NRFS); + + /* Step 7: Program the external memory mode register.*/ + lld_sdram_wait_ready(); + SDRAMD.sdram->SDCMR = FMCCM_LOAD_MODE | command_target | + (cfgp->sdcmr & FMC_SDCMR_MRD); + + /* Step 8: Set clock.*/ + lld_sdram_wait_ready(); + SDRAMD.sdram->SDRTR = cfgp->sdrtr & FMC_SDRTR_COUNT; + + lld_sdram_wait_ready(); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +void lld_sdram_start(SDRAMDriver *sdramp, const SDRAMConfig *cfgp) +{ + sdramp->sdram->SDCR1 = cfgp->sdcr; + sdramp->sdram->SDTR1 = cfgp->sdtr; + sdramp->sdram->SDCR2 = cfgp->sdcr; + sdramp->sdram->SDTR2 = cfgp->sdtr; + + lld_sdram_init_sequence(cfgp); +} + +void lld_sdram_stop(SDRAMDriver *sdramp) { + uint32_t command_target = 0; + +#if STM32_FSMC_USE_SDRAM1 + command_target |= FMC_SDCMR_CTB1; +#endif +#if STM32_FSMC_USE_SDRAM2 + command_target |= FMC_SDCMR_CTB2; +#endif + + sdramp->sdram->SDCMR = FMCCM_POWER_DOWN | command_target; +} +#endif /* STM32_USE_FSMC_SDRAM */ + +#endif /* STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx */ + +/** @} */ + diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.h new file mode 100644 index 0000000..0e533b6 --- /dev/null +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.h @@ -0,0 +1,117 @@ +/* + ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + SDRAM routines added by Nick Klimov aka progfin. + */ + +/** + * @file hal_fsmc_sdram.h + * @brief SDRAM Driver subsystem low level driver header. + * + * @addtogroup SDRAM + * @{ + */ + +#ifndef HAL_FMC_SDRAM_H_ +#define HAL_FMC_SDRAM_H_ + +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F745xx) || defined(STM32F746xx) || \ + defined(STM32F756xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || \ + defined(STM32F779xx)) + +#include "hal_fsmc.h" + +#if (STM32_FSMC_USE_SDRAM1 == TRUE) || (STM32_FSMC_USE_SDRAM2 == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ + +/** + * @brief SDRAM driver enable switch. + * @details If set to @p TRUE the support for SDRAM1 is included. + */ +#if !defined(STM32_FSMC_USE_SDRAM1) || defined(__DOXYGEN__) +#define STM32_FSMC_USE_SDRAM1 FALSE +#else +#define STM32_SDRAM1_MAP_BASE FSMC_Bank5_MAP_BASE +#endif + +/** + * @brief SDRAM driver enable switch. + * @details If set to @p TRUE the support for SDRAM2 is included. + */ +#if !defined(STM32_FSMC_USE_SDRAM2) || defined(__DOXYGEN__) +#define STM32_FSMC_USE_SDRAM2 FALSE +#else +#define STM32_SDRAM2_MAP_BASE FSMC_Bank6_MAP_BASE +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !STM32_FSMC_USE_SDRAM1 && !STM32_FSMC_USE_SDRAM2 +#error "SDRAM driver activated but no SDRAM peripheral assigned" +#endif + +#if (STM32_FSMC_USE_SDRAM1 || STM32_FSMC_USE_SDRAM2) && !STM32_HAS_FSMC +#error "FMC not present in the selected device" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +extern SDRAMDriver SDRAMD; + +#ifdef __cplusplus +extern "C" { +#endif + void lld_sdram_start(SDRAMDriver *sdramp, const SDRAMConfig *cfgp); + void lld_sdram_stop(SDRAMDriver *sdramp); +#ifdef __cplusplus +} +#endif + +#endif /* STM32_FSMC_USE_SDRAM */ + +#endif /* STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx */ + +#endif /* HAL_FSMC_SDRAM_H_ */ + +/** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c deleted file mode 100644 index da13ca5..0000000 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c +++ /dev/null @@ -1,165 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_fsmc_sram.c - * @brief SRAM Driver subsystem low level driver source. - * - * @addtogroup SRAM - * @{ - */ -#include "hal.h" -#include "hal_fsmc_sram.h" - -#if (STM32_USE_FSMC_SRAM == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ -/** - * @brief SRAM1 driver identifier. - */ -#if STM32_SRAM_USE_FSMC_SRAM1 || defined(__DOXYGEN__) -SRAMDriver SRAMD1; -#endif - -/** - * @brief SRAM2 driver identifier. - */ -#if STM32_SRAM_USE_FSMC_SRAM2 || defined(__DOXYGEN__) -SRAMDriver SRAMD2; -#endif - -/** - * @brief SRAM3 driver identifier. - */ -#if STM32_SRAM_USE_FSMC_SRAM3 || defined(__DOXYGEN__) -SRAMDriver SRAMD3; -#endif - -/** - * @brief SRAM4 driver identifier. - */ -#if STM32_SRAM_USE_FSMC_SRAM4 || defined(__DOXYGEN__) -SRAMDriver SRAMD4; -#endif - -/*===========================================================================*/ -/* Driver local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level SRAM driver initialization. - * - * @notapi - */ -void fsmcSramInit(void) { - - fsmc_init(); - -#if STM32_SRAM_USE_FSMC_SRAM1 - SRAMD1.sram = FSMCD1.sram1; - SRAMD1.state = SRAM_STOP; -#endif /* STM32_SRAM_USE_FSMC_SRAM1 */ - -#if STM32_SRAM_USE_FSMC_SRAM2 - SRAMD2.sram = FSMCD1.sram2; - SRAMD2.state = SRAM_STOP; -#endif /* STM32_SRAM_USE_FSMC_SRAM2 */ - -#if STM32_SRAM_USE_FSMC_SRAM3 - SRAMD3.sram = FSMCD1.sram3; - SRAMD3.state = SRAM_STOP; -#endif /* STM32_SRAM_USE_FSMC_SRAM3 */ - -#if STM32_SRAM_USE_FSMC_SRAM4 - SRAMD4.sram = FSMCD1.sram4; - SRAMD4.state = SRAM_STOP; -#endif /* STM32_SRAM_USE_FSMC_SRAM4 */ -} - -/** - * @brief Configures and activates the SRAM peripheral. - * - * @param[in] sramp pointer to the @p SRAMDriver object - * @param[in] cfgp pointer to the @p SRAMConfig object - * - * @notapi - */ -void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp) { - - if (FSMCD1.state == FSMC_STOP) - fsmc_start(&FSMCD1); - - osalDbgAssert((sramp->state == SRAM_STOP) || (sramp->state == SRAM_READY), - "invalid state"); - - if (sramp->state == SRAM_STOP) { - sramp->sram->BTR = cfgp->btr; - sramp->sram->BWTR = cfgp->bwtr; - sramp->sram->BCR = cfgp->bcr | FSMC_BCR_MBKEN; - sramp->state = SRAM_READY; - } -} - -/** - * @brief Deactivates the SRAM peripheral. - * - * @param[in] sramp pointer to the @p SRAMDriver object - * - * @notapi - */ -void fsmcSramStop(SRAMDriver *sramp) { - - if (sramp->state == SRAM_READY) { - uint32_t mask = FSMC_BCR_MBKEN; -#if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F745xx) || defined(STM32F746xx) || \ - defined(STM32F756xx) || defined(STM32F767xx) || \ - defined(STM32F769xx) || defined(STM32F777xx) || \ - defined(STM32F779xx)) - mask |= FSMC_BCR_CCLKEN; -#endif - sramp->sram->BCR &= ~mask; - sramp->state = SRAM_STOP; - } -} - -#endif /* STM32_USE_FSMC_SRAM */ - -/** @} */ - diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.h deleted file mode 100644 index 5e749a8..0000000 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.h +++ /dev/null @@ -1,172 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_fsmc_sram.h - * @brief SRAM Driver subsystem low level driver header. - * - * @addtogroup SRAM - * @{ - */ - -#ifndef HAL_FSMC_SRAM_H_ -#define HAL_FSMC_SRAM_H_ - -#include "hal_fsmc.h" - -#if (STM32_USE_FSMC_SRAM == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ -/** - * @name Configuration options - * @{ - */ - -/** - * @brief SRAM driver enable switch. - * @details If set to @p TRUE the support for SRAM1 is included. - */ -#if !defined(STM32_SRAM_USE_FSMC_SRAM1) || defined(__DOXYGEN__) -#define STM32_SRAM_USE_FSMC_SRAM1 FALSE -#endif - -/** - * @brief SRAM driver enable switch. - * @details If set to @p TRUE the support for SRAM2 is included. - */ -#if !defined(STM32_SRAM_USE_FSMC_SRAM2) || defined(__DOXYGEN__) -#define STM32_SRAM_USE_FSMC_SRAM2 FALSE -#endif - -/** - * @brief SRAM driver enable switch. - * @details If set to @p TRUE the support for SRAM3 is included. - */ -#if !defined(STM32_SRAM_USE_FSMC_SRAM3) || defined(__DOXYGEN__) -#define STM32_SRAM_USE_FSMC_SRAM3 FALSE -#endif - -/** - * @brief SRAM driver enable switch. - * @details If set to @p TRUE the support for SRAM4 is included. - */ -#if !defined(STM32_SRAM_USE_FSMC_SRAM4) || defined(__DOXYGEN__) -#define STM32_SRAM_USE_FSMC_SRAM4 FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !STM32_SRAM_USE_FSMC_SRAM1 && !STM32_SRAM_USE_FSMC_SRAM2 && \ - !STM32_SRAM_USE_FSMC_SRAM3 && !STM32_SRAM_USE_FSMC_SRAM4 -#error "SRAM driver activated but no SRAM peripheral assigned" -#endif - -#if (STM32_SRAM_USE_FSMC_SRAM1 || STM32_SRAM_USE_FSMC_SRAM2 || \ - STM32_SRAM_USE_FSMC_SRAM3 || STM32_SRAM_USE_FSMC_SRAM4) && !STM32_HAS_FSMC -#error "FSMC not present in the selected device" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ -/** - * @brief Driver state machine possible states. - */ -typedef enum { - SRAM_UNINIT = 0, /**< Not initialized. */ - SRAM_STOP = 1, /**< Stopped. */ - SRAM_READY = 2, /**< Ready. */ -} sramstate_t; - -/** - * @brief Type of a structure representing an NAND driver. - */ -typedef struct SRAMDriver SRAMDriver; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - * @note Some bits in BCR register will be forced by driver. - */ -typedef struct { - uint32_t bcr; - uint32_t btr; - uint32_t bwtr; -} SRAMConfig; - -/** - * @brief Structure representing an NAND driver. - */ -struct SRAMDriver { - /** - * @brief Driver state. - */ - sramstate_t state; - /** - * @brief Pointer to the FSMC SRAM registers block. - */ - FSMC_SRAM_NOR_TypeDef *sram; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_SRAM_USE_FSMC_SRAM1 && !defined(__DOXYGEN__) -extern SRAMDriver SRAMD1; -#endif - -#if STM32_SRAM_USE_FSMC_SRAM2 && !defined(__DOXYGEN__) -extern SRAMDriver SRAMD2; -#endif - -#if STM32_SRAM_USE_FSMC_SRAM3 && !defined(__DOXYGEN__) -extern SRAMDriver SRAMD3; -#endif - -#if STM32_SRAM_USE_FSMC_SRAM4 && !defined(__DOXYGEN__) -extern SRAMDriver SRAMD4; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void fsmcSramInit(void); - void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp); - void fsmcSramStop(SRAMDriver *sramp); -#ifdef __cplusplus -} -#endif - -#endif /* STM32_USE_FSMC_SRAM */ - -#endif /* HAL_FSMC_SRAM_H_ */ - -/** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.c new file mode 100644 index 0000000..da13ca5 --- /dev/null +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.c @@ -0,0 +1,165 @@ +/* + ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_fsmc_sram.c + * @brief SRAM Driver subsystem low level driver source. + * + * @addtogroup SRAM + * @{ + */ +#include "hal.h" +#include "hal_fsmc_sram.h" + +#if (STM32_USE_FSMC_SRAM == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ +/** + * @brief SRAM1 driver identifier. + */ +#if STM32_SRAM_USE_FSMC_SRAM1 || defined(__DOXYGEN__) +SRAMDriver SRAMD1; +#endif + +/** + * @brief SRAM2 driver identifier. + */ +#if STM32_SRAM_USE_FSMC_SRAM2 || defined(__DOXYGEN__) +SRAMDriver SRAMD2; +#endif + +/** + * @brief SRAM3 driver identifier. + */ +#if STM32_SRAM_USE_FSMC_SRAM3 || defined(__DOXYGEN__) +SRAMDriver SRAMD3; +#endif + +/** + * @brief SRAM4 driver identifier. + */ +#if STM32_SRAM_USE_FSMC_SRAM4 || defined(__DOXYGEN__) +SRAMDriver SRAMD4; +#endif + +/*===========================================================================*/ +/* Driver local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SRAM driver initialization. + * + * @notapi + */ +void fsmcSramInit(void) { + + fsmc_init(); + +#if STM32_SRAM_USE_FSMC_SRAM1 + SRAMD1.sram = FSMCD1.sram1; + SRAMD1.state = SRAM_STOP; +#endif /* STM32_SRAM_USE_FSMC_SRAM1 */ + +#if STM32_SRAM_USE_FSMC_SRAM2 + SRAMD2.sram = FSMCD1.sram2; + SRAMD2.state = SRAM_STOP; +#endif /* STM32_SRAM_USE_FSMC_SRAM2 */ + +#if STM32_SRAM_USE_FSMC_SRAM3 + SRAMD3.sram = FSMCD1.sram3; + SRAMD3.state = SRAM_STOP; +#endif /* STM32_SRAM_USE_FSMC_SRAM3 */ + +#if STM32_SRAM_USE_FSMC_SRAM4 + SRAMD4.sram = FSMCD1.sram4; + SRAMD4.state = SRAM_STOP; +#endif /* STM32_SRAM_USE_FSMC_SRAM4 */ +} + +/** + * @brief Configures and activates the SRAM peripheral. + * + * @param[in] sramp pointer to the @p SRAMDriver object + * @param[in] cfgp pointer to the @p SRAMConfig object + * + * @notapi + */ +void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp) { + + if (FSMCD1.state == FSMC_STOP) + fsmc_start(&FSMCD1); + + osalDbgAssert((sramp->state == SRAM_STOP) || (sramp->state == SRAM_READY), + "invalid state"); + + if (sramp->state == SRAM_STOP) { + sramp->sram->BTR = cfgp->btr; + sramp->sram->BWTR = cfgp->bwtr; + sramp->sram->BCR = cfgp->bcr | FSMC_BCR_MBKEN; + sramp->state = SRAM_READY; + } +} + +/** + * @brief Deactivates the SRAM peripheral. + * + * @param[in] sramp pointer to the @p SRAMDriver object + * + * @notapi + */ +void fsmcSramStop(SRAMDriver *sramp) { + + if (sramp->state == SRAM_READY) { + uint32_t mask = FSMC_BCR_MBKEN; +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F745xx) || defined(STM32F746xx) || \ + defined(STM32F756xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || \ + defined(STM32F779xx)) + mask |= FSMC_BCR_CCLKEN; +#endif + sramp->sram->BCR &= ~mask; + sramp->state = SRAM_STOP; + } +} + +#endif /* STM32_USE_FSMC_SRAM */ + +/** @} */ + diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.h new file mode 100644 index 0000000..5e749a8 --- /dev/null +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.h @@ -0,0 +1,172 @@ +/* + ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_fsmc_sram.h + * @brief SRAM Driver subsystem low level driver header. + * + * @addtogroup SRAM + * @{ + */ + +#ifndef HAL_FSMC_SRAM_H_ +#define HAL_FSMC_SRAM_H_ + +#include "hal_fsmc.h" + +#if (STM32_USE_FSMC_SRAM == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ + +/** + * @brief SRAM driver enable switch. + * @details If set to @p TRUE the support for SRAM1 is included. + */ +#if !defined(STM32_SRAM_USE_FSMC_SRAM1) || defined(__DOXYGEN__) +#define STM32_SRAM_USE_FSMC_SRAM1 FALSE +#endif + +/** + * @brief SRAM driver enable switch. + * @details If set to @p TRUE the support for SRAM2 is included. + */ +#if !defined(STM32_SRAM_USE_FSMC_SRAM2) || defined(__DOXYGEN__) +#define STM32_SRAM_USE_FSMC_SRAM2 FALSE +#endif + +/** + * @brief SRAM driver enable switch. + * @details If set to @p TRUE the support for SRAM3 is included. + */ +#if !defined(STM32_SRAM_USE_FSMC_SRAM3) || defined(__DOXYGEN__) +#define STM32_SRAM_USE_FSMC_SRAM3 FALSE +#endif + +/** + * @brief SRAM driver enable switch. + * @details If set to @p TRUE the support for SRAM4 is included. + */ +#if !defined(STM32_SRAM_USE_FSMC_SRAM4) || defined(__DOXYGEN__) +#define STM32_SRAM_USE_FSMC_SRAM4 FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !STM32_SRAM_USE_FSMC_SRAM1 && !STM32_SRAM_USE_FSMC_SRAM2 && \ + !STM32_SRAM_USE_FSMC_SRAM3 && !STM32_SRAM_USE_FSMC_SRAM4 +#error "SRAM driver activated but no SRAM peripheral assigned" +#endif + +#if (STM32_SRAM_USE_FSMC_SRAM1 || STM32_SRAM_USE_FSMC_SRAM2 || \ + STM32_SRAM_USE_FSMC_SRAM3 || STM32_SRAM_USE_FSMC_SRAM4) && !STM32_HAS_FSMC +#error "FSMC not present in the selected device" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ +/** + * @brief Driver state machine possible states. + */ +typedef enum { + SRAM_UNINIT = 0, /**< Not initialized. */ + SRAM_STOP = 1, /**< Stopped. */ + SRAM_READY = 2, /**< Ready. */ +} sramstate_t; + +/** + * @brief Type of a structure representing an NAND driver. + */ +typedef struct SRAMDriver SRAMDriver; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + * @note Some bits in BCR register will be forced by driver. + */ +typedef struct { + uint32_t bcr; + uint32_t btr; + uint32_t bwtr; +} SRAMConfig; + +/** + * @brief Structure representing an NAND driver. + */ +struct SRAMDriver { + /** + * @brief Driver state. + */ + sramstate_t state; + /** + * @brief Pointer to the FSMC SRAM registers block. + */ + FSMC_SRAM_NOR_TypeDef *sram; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_SRAM_USE_FSMC_SRAM1 && !defined(__DOXYGEN__) +extern SRAMDriver SRAMD1; +#endif + +#if STM32_SRAM_USE_FSMC_SRAM2 && !defined(__DOXYGEN__) +extern SRAMDriver SRAMD2; +#endif + +#if STM32_SRAM_USE_FSMC_SRAM3 && !defined(__DOXYGEN__) +extern SRAMDriver SRAMD3; +#endif + +#if STM32_SRAM_USE_FSMC_SRAM4 && !defined(__DOXYGEN__) +extern SRAMDriver SRAMD4; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void fsmcSramInit(void); + void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp); + void fsmcSramStop(SRAMDriver *sramp); +#ifdef __cplusplus +} +#endif + +#endif /* STM32_USE_FSMC_SRAM */ + +#endif /* HAL_FSMC_SRAM_H_ */ + +/** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c deleted file mode 100644 index cc6dc20..0000000 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c +++ /dev/null @@ -1,590 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_nand_lld.c - * @brief NAND Driver subsystem low level driver source. - * - * @addtogroup NAND - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_NAND == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ -#define NAND_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_NAND_DMA_STREAM, \ - STM32_FSMC_DMA_CHN) - -/** - * @brief Bus width of NAND IC. - * @details Must be 8 or 16 - */ -#if ! defined(STM32_NAND_BUS_WIDTH) || defined(__DOXYGEN__) -#define STM32_NAND_BUS_WIDTH 8 -#endif - -/** - * @brief DMA transaction width on AHB bus in bytes - */ -#define AHB_TRANSACTION_WIDTH 2 - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief NAND1 driver identifier. - */ -#if STM32_NAND_USE_FSMC_NAND1 || defined(__DOXYGEN__) -NANDDriver NANDD1; -#endif - -/** - * @brief NAND2 driver identifier. - */ -#if STM32_NAND_USE_FSMC_NAND2 || defined(__DOXYGEN__) -NANDDriver NANDD2; -#endif - -/*===========================================================================*/ -/* Driver local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Helper function. - * - * @notapi - */ -static void align_check(const void *ptr, uint32_t len) { - osalDbgCheck((((uint32_t)ptr % AHB_TRANSACTION_WIDTH) == 0) && - ((len % AHB_TRANSACTION_WIDTH) == 0) && - (len >= AHB_TRANSACTION_WIDTH)); - (void)ptr; - (void)len; -} - -/** - * @brief Work around errata in STM32's FSMC core. - * @details Constant output clock (if enabled) disappears when CLKDIV value - * sets to 1 (FMC_CLK period = 2 × HCLK periods) AND 8-bit async - * transaction generated on AHB. This workaround eliminates 8-bit - * transactions on bus when you use 8-bit memory. It suitable only - * for 8-bit memory (i.e. PWID bits in PCR register must be set - * to 8-bit mode). - * - * @notapi - */ -static void set_16bit_bus(NANDDriver *nandp) { -#if STM32_NAND_BUS_WIDTH - nandp->nand->PCR |= FSMC_PCR_PWID_16; -#else - (void)nandp; -#endif -} - -static void set_8bit_bus(NANDDriver *nandp) { -#if STM32_NAND_BUS_WIDTH - nandp->nand->PCR &= ~FSMC_PCR_PWID_16; -#else - (void)nandp; -#endif -} - -/** - * @brief Wakes up the waiting thread. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] msg wakeup message - * - * @notapi - */ -static void wakeup_isr(NANDDriver *nandp) { - - osalDbgCheck(nandp->thread != NULL); - osalThreadResumeI(&nandp->thread, MSG_OK); -} - -/** - * @brief Put calling thread in suspend and switch driver state - * - * @param[in] nandp pointer to the @p NANDDriver object - */ -static void nand_lld_suspend_thread(NANDDriver *nandp) { - - osalThreadSuspendS(&nandp->thread); -} - -/** - * @brief Caclulate ECCPS register value - * - * @param[in] nandp pointer to the @p NANDDriver object - */ -static uint32_t calc_eccps(NANDDriver *nandp) { - - uint32_t i = 0; - uint32_t eccps = nandp->config->page_data_size; - - eccps = eccps >> 9; - while (eccps > 0){ - i++; - eccps >>= 1; - } - - return i << 17; -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief Enable interrupts from NAND - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @notapi - */ -static void nand_ready_isr_enable(NANDDriver *nandp) { - - nandp->nand->SR &= ~(FSMC_SR_IRS | FSMC_SR_ILS | FSMC_SR_IFS | - FSMC_SR_ILEN | FSMC_SR_IFEN); - nandp->nand->SR |= FSMC_SR_IREN; -} - -/** - * @brief Disable interrupts from NAND - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @notapi - */ -static void nand_ready_isr_disable(NANDDriver *nandp) { - - nandp->nand->SR &= ~FSMC_SR_IREN; -} - -/** - * @brief Ready interrupt handler - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @notapi - */ -static void nand_isr_handler(NANDDriver *nandp) { - - osalSysLockFromISR(); - - osalDbgCheck(nandp->nand->SR & FSMC_SR_IRS); /* spurious interrupt happened */ - nandp->nand->SR &= ~FSMC_SR_IRS; - - switch (nandp->state){ - case NAND_READ: - nandp->state = NAND_DMA_RX; - dmaStartMemCopy(nandp->dma, nandp->dmamode, nandp->map_data, nandp->rxdata, - nandp->datalen/AHB_TRANSACTION_WIDTH); - /* thread will be waked up from DMA ISR */ - break; - - case NAND_ERASE: /* NAND reports about erase finish */ - case NAND_PROGRAM: /* NAND reports about page programming finish */ - case NAND_RESET: /* NAND reports about finished reset recover */ - nandp->state = NAND_READY; - wakeup_isr(nandp); - break; - - default: - osalSysHalt("Unhandled case"); - break; - } - osalSysUnlockFromISR(); -} - -/** - * @brief DMA RX end IRQ handler. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] flags pre-shifted content of the ISR register - * - * @notapi - */ -static void nand_lld_serve_transfer_end_irq(NANDDriver *nandp, uint32_t flags) { - /* DMA errors handling.*/ -#if defined(STM32_NAND_DMA_ERROR_HOOK) - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - STM32_NAND_DMA_ERROR_HOOK(nandp); - } -#else - (void)flags; -#endif - - osalSysLockFromISR(); - - dmaStreamDisable(nandp->dma); - - switch (nandp->state){ - case NAND_DMA_TX: - nandp->state = NAND_PROGRAM; - nandp->map_cmd[0] = NAND_CMD_PAGEPROG; - /* thread will be woken up from ready_isr() */ - break; - - case NAND_DMA_RX: - nandp->state = NAND_READY; - nandp->rxdata = NULL; - nandp->datalen = 0; - wakeup_isr(nandp); - break; - - default: - osalSysHalt("Unhandled case"); - break; - } - - osalSysUnlockFromISR(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level NAND driver initialization. - * - * @notapi - */ -void nand_lld_init(void) { - - fsmc_init(); - -#if STM32_NAND_USE_FSMC_NAND1 - /* Driver initialization.*/ - nandObjectInit(&NANDD1); - NANDD1.rxdata = NULL; - NANDD1.datalen = 0; - NANDD1.thread = NULL; - NANDD1.dma = STM32_DMA_STREAM(STM32_NAND_DMA_STREAM); - NANDD1.nand = FSMCD1.nand1; - NANDD1.map_data = (void *)FSMC_Bank2_MAP_COMMON_DATA; - NANDD1.map_cmd = (uint16_t *)FSMC_Bank2_MAP_COMMON_CMD; - NANDD1.map_addr = (uint16_t *)FSMC_Bank2_MAP_COMMON_ADDR; - NANDD1.bb_map = NULL; -#endif /* STM32_NAND_USE_FSMC_NAND1 */ - -#if STM32_NAND_USE_FSMC_NAND2 - /* Driver initialization.*/ - nandObjectInit(&NANDD2); - NANDD2.rxdata = NULL; - NANDD2.datalen = 0; - NANDD2.thread = NULL; - NANDD2.dma = STM32_DMA_STREAM(STM32_NAND_DMA_STREAM); - NANDD2.nand = FSMCD1.nand2; - NANDD2.map_data = (void *)FSMC_Bank3_MAP_COMMON_DATA; - NANDD2.map_cmd = (uint16_t *)FSMC_Bank3_MAP_COMMON_CMD; - NANDD2.map_addr = (uint16_t *)FSMC_Bank3_MAP_COMMON_ADDR; - NANDD2.bb_map = NULL; -#endif /* STM32_NAND_USE_FSMC_NAND2 */ -} - -/** - * @brief Configures and activates the NAND peripheral. - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @notapi - */ -void nand_lld_start(NANDDriver *nandp) { - - bool b; - uint32_t dmasize; - uint32_t pcr_bus_width; - - if (FSMCD1.state == FSMC_STOP) - fsmc_start(&FSMCD1); - - if (nandp->state == NAND_STOP) { - b = dmaStreamAlloc(nandp->dma, - STM32_EMC_FSMC1_IRQ_PRIORITY, - (stm32_dmaisr_t)nand_lld_serve_transfer_end_irq, - (void *)nandp); - osalDbgAssert(!b, "stream already allocated"); - -#if AHB_TRANSACTION_WIDTH == 4 - dmasize = STM32_DMA_CR_PSIZE_WORD | STM32_DMA_CR_MSIZE_WORD; -#elif AHB_TRANSACTION_WIDTH == 2 - dmasize = STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; -#elif AHB_TRANSACTION_WIDTH == 1 - dmasize = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE; -#else -#error "Incorrect AHB_TRANSACTION_WIDTH" -#endif - - nandp->dmamode = STM32_DMA_CR_CHSEL(NAND_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_NAND_NAND1_DMA_PRIORITY) | - dmasize | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE | - STM32_DMA_CR_TCIE; - -#if STM32_NAND_BUS_WIDTH == 8 - pcr_bus_width = FSMC_PCR_PWID_8; -#elif STM32_NAND_BUS_WIDTH == 16 - pcr_bus_width = FSMC_PCR_PWID_16; -#else -#error "Bus width must be 8 or 16 bits" -#endif - nandp->nand->PCR = pcr_bus_width | calc_eccps(nandp) | - FSMC_PCR_PTYP_NAND | FSMC_PCR_PBKEN; - nandp->nand->PMEM = nandp->config->pmem; - nandp->nand->PATT = nandp->config->pmem; - nandp->isr_handler = nand_isr_handler; - nand_ready_isr_enable(nandp); - } -} - -/** - * @brief Deactivates the NAND peripheral. - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @notapi - */ -void nand_lld_stop(NANDDriver *nandp) { - - if (nandp->state == NAND_READY) { - dmaStreamFree(nandp->dma); - nandp->nand->PCR &= ~FSMC_PCR_PBKEN; - nand_ready_isr_disable(nandp); - nandp->isr_handler = NULL; - } -} - -/** - * @brief Read data from NAND. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[out] data pointer to data buffer - * @param[in] datalen size of data buffer in bytes - * @param[in] addr pointer to address buffer - * @param[in] addrlen length of address - * @param[out] ecc pointer to store computed ECC. Ignored when NULL. - * - * @notapi - */ -void nand_lld_read_data(NANDDriver *nandp, uint16_t *data, size_t datalen, - uint8_t *addr, size_t addrlen, uint32_t *ecc){ - - align_check(data, datalen); - - nandp->state = NAND_READ; - nandp->rxdata = data; - nandp->datalen = datalen; - - set_16bit_bus(nandp); - nand_lld_write_cmd(nandp, NAND_CMD_READ0); - nand_lld_write_addr(nandp, addr, addrlen); - osalSysLock(); - nand_lld_write_cmd(nandp, NAND_CMD_READ0_CONFIRM); - set_8bit_bus(nandp); - - /* Here NAND asserts busy signal and starts transferring from memory - array to page buffer. After the end of transmission ready_isr functions - starts DMA transfer from page buffer to MCU's RAM.*/ - osalDbgAssert((nandp->nand->PCR & FSMC_PCR_ECCEN) == 0, - "State machine broken. ECCEN must be previously disabled."); - - if (NULL != ecc){ - nandp->nand->PCR |= FSMC_PCR_ECCEN; - } - - nand_lld_suspend_thread(nandp); - osalSysUnlock(); - - /* thread was woken up from DMA ISR */ - if (NULL != ecc){ - while (! (nandp->nand->SR & FSMC_SR_FEMPT)) - ; - *ecc = nandp->nand->ECCR; - nandp->nand->PCR &= ~FSMC_PCR_ECCEN; - } -} - -/** - * @brief Write data to NAND. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] data buffer with data to be written - * @param[in] datalen size of data buffer in bytes - * @param[in] addr pointer to address buffer - * @param[in] addrlen length of address - * @param[out] ecc pointer to store computed ECC. Ignored when NULL. - * - * @return The operation status reported by NAND IC (0x70 command). - * - * @notapi - */ -uint8_t nand_lld_write_data(NANDDriver *nandp, const uint16_t *data, - size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc) { - - align_check(data, datalen); - - nandp->state = NAND_WRITE; - - set_16bit_bus(nandp); - nand_lld_write_cmd(nandp, NAND_CMD_WRITE); - osalSysLock(); - nand_lld_write_addr(nandp, addr, addrlen); - set_8bit_bus(nandp); - - /* Now start DMA transfer to NAND buffer and put thread in sleep state. - Tread will be woken up from ready ISR. */ - nandp->state = NAND_DMA_TX; - osalDbgAssert((nandp->nand->PCR & FSMC_PCR_ECCEN) == 0, - "State machine broken. ECCEN must be previously disabled."); - - if (NULL != ecc){ - nandp->nand->PCR |= FSMC_PCR_ECCEN; - } - - dmaStartMemCopy(nandp->dma, nandp->dmamode, data, nandp->map_data, - datalen/AHB_TRANSACTION_WIDTH); - - nand_lld_suspend_thread(nandp); - osalSysUnlock(); - - if (NULL != ecc){ - while (! (nandp->nand->SR & FSMC_SR_FEMPT)) - ; - *ecc = nandp->nand->ECCR; - nandp->nand->PCR &= ~FSMC_PCR_ECCEN; - } - - return nand_lld_read_status(nandp); -} - -/** - * @brief Soft reset NAND device. - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @notapi - */ -void nand_lld_reset(NANDDriver *nandp) { - - nandp->state = NAND_RESET; - - set_16bit_bus(nandp); - nand_lld_write_cmd(nandp, NAND_CMD_RESET); - set_8bit_bus(nandp); - - osalSysLock(); - nand_lld_suspend_thread(nandp); - osalSysUnlock(); -} - -/** - * @brief Erase block. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] addr pointer to address buffer - * @param[in] addrlen length of address - * - * @return The operation status reported by NAND IC (0x70 command). - * - * @notapi - */ -uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen) { - - nandp->state = NAND_ERASE; - - set_16bit_bus(nandp); - nand_lld_write_cmd(nandp, NAND_CMD_ERASE); - nand_lld_write_addr(nandp, addr, addrlen); - osalSysLock(); - nand_lld_write_cmd(nandp, NAND_CMD_ERASE_CONFIRM); - set_8bit_bus(nandp); - - nand_lld_suspend_thread(nandp); - osalSysUnlock(); - - return nand_lld_read_status(nandp); -} - -/** - * @brief Send addres to NAND. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] len length of address array - * @param[in] addr pointer to address array - * - * @notapi - */ -void nand_lld_write_addr(NANDDriver *nandp, const uint8_t *addr, size_t len) { - size_t i = 0; - - for (i=0; imap_addr[i] = addr[i]; -} - -/** - * @brief Send command to NAND. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] cmd command value - * - * @notapi - */ -void nand_lld_write_cmd(NANDDriver *nandp, uint8_t cmd) { - nandp->map_cmd[0] = cmd; -} - -/** - * @brief Read status byte from NAND. - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @return Status byte. - * - * @notapi - */ -uint8_t nand_lld_read_status(NANDDriver *nandp) { - - uint16_t status; - - set_16bit_bus(nandp); - nand_lld_write_cmd(nandp, NAND_CMD_STATUS); - set_8bit_bus(nandp); - status = nandp->map_data[0]; - - return status & 0xFF; -} - -#endif /* HAL_USE_NAND */ - -/** @} */ - diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h deleted file mode 100644 index 5266138..0000000 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h +++ /dev/null @@ -1,294 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_nand_lld.h - * @brief NAND Driver subsystem low level driver header. - * - * @addtogroup NAND - * @{ - */ - -#ifndef HAL_NAND_LLD_H_ -#define HAL_NAND_LLD_H_ - -#include "hal_fsmc.h" -#include "bitmap.h" - -#if (HAL_USE_NAND == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ -#define NAND_MIN_PAGE_SIZE 256 -#define NAND_MAX_PAGE_SIZE 8192 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief FSMC1 interrupt priority level setting. - */ -#if !defined(STM32_EMC_FSMC1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EMC_FSMC1_IRQ_PRIORITY 10 -#endif - -/** - * @brief NAND driver enable switch. - * @details If set to @p TRUE the support for NAND1 is included. - */ -#if !defined(STM32_NAND_USE_NAND1) || defined(__DOXYGEN__) -#define STM32_NAND_USE_NAND1 FALSE -#endif - -/** - * @brief NAND driver enable switch. - * @details If set to @p TRUE the support for NAND2 is included. - */ -#if !defined(STM32_NAND_USE_NAND2) || defined(__DOXYGEN__) -#define STM32_NAND_USE_NAND2 FALSE -#endif - -/** - * @brief NAND DMA error hook. - * @note The default action for DMA errors is a system halt because DMA - * error can only happen because programming errors. - */ -#if !defined(STM32_NAND_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure") -#endif - -/** - * @brief NAND interrupt enable switch. - * @details If set to @p TRUE the support for internal FSMC interrupt included. - */ -#if !defined(STM32_NAND_USE_INT) || defined(__DOXYGEN__) -#define STM32_NAND_USE_INT FALSE -#endif - -/** -* @brief NAND1 DMA priority (0..3|lowest..highest). -*/ -#if !defined(STM32_NAND_NAND1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_NAND_NAND1_DMA_PRIORITY 0 -#endif - -/** -* @brief NAND2 DMA priority (0..3|lowest..highest). -*/ -#if !defined(STM32_NAND_NAND2_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_NAND_NAND2_DMA_PRIORITY 0 -#endif - -/** - * @brief DMA stream used for NAND operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_NAND_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) -#endif - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !STM32_NAND_USE_FSMC_NAND1 && !STM32_NAND_USE_FSMC_NAND2 -#error "NAND driver activated but no NAND peripheral assigned" -#endif - -#if (STM32_NAND_USE_FSMC_NAND2 || STM32_NAND_USE_FSMC_NAND1) && !STM32_HAS_FSMC -#error "FSMC not present in the selected device" -#endif - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a structure representing an NAND driver. - */ -typedef struct NANDDriver NANDDriver; - -/** - * @brief Type of interrupt handler function. - */ -typedef void (*nandisrhandler_t)(NANDDriver *nandp); - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief Number of erase blocks in NAND device. - */ - uint32_t blocks; - /** - * @brief Number of data bytes in page. - */ - uint32_t page_data_size; - /** - * @brief Number of spare bytes in page. - */ - uint32_t page_spare_size; - /** - * @brief Number of pages in block. - */ - uint32_t pages_per_block; - /** - * @brief Number of write cycles for row addressing. - */ - uint8_t rowcycles; - /** - * @brief Number of write cycles for column addressing. - */ - uint8_t colcycles; - - /* End of the mandatory fields.*/ - /** - * @brief Number of wait cycles. This value will be used both for - * PMEM and PATTR registers - * - * @note For proper calculation procedure please look at AN2784 document - * from STMicroelectronics. - */ - uint32_t pmem; -} NANDConfig; - -/** - * @brief Structure representing an NAND driver. - */ -struct NANDDriver { - /** - * @brief Driver state. - */ - nandstate_t state; - /** - * @brief Current configuration data. - */ - const NANDConfig *config; - /** - * @brief Array to store bad block map. - */ -#if NAND_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) -#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the bus. - */ - mutex_t mutex; -#elif CH_CFG_USE_SEMAPHORES - semaphore_t semaphore; -#endif -#endif /* NAND_USE_MUTUAL_EXCLUSION */ - /* End of the mandatory fields.*/ - /** - * @brief Function enabling interrupts from FSMC. - */ - nandisrhandler_t isr_handler; - /** - * @brief Pointer to current transaction buffer. - */ - void *rxdata; - /** - * @brief Current transaction length in bytes. - */ - size_t datalen; - /** - * @brief DMA mode bit mask. - */ - uint32_t dmamode; - /** - * @brief DMA channel. - */ - const stm32_dma_stream_t *dma; - /** - * @brief Thread waiting for I/O completion. - */ - thread_t *thread; - /** - * @brief Pointer to the FSMC NAND registers block. - */ - FSMC_NAND_TypeDef *nand; - /** - * @brief Memory mapping for data. - */ - uint16_t *map_data; - /** - * @brief Memory mapping for commands. - */ - uint16_t *map_cmd; - /** - * @brief Memory mapping for addresses. - */ - uint16_t *map_addr; - /** - * @brief Pointer to bad block map. - * @details One bit per block. All memory allocation is user's responsibility. - */ - bitmap_t *bb_map; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_NAND_USE_FSMC_NAND1 && !defined(__DOXYGEN__) -extern NANDDriver NANDD1; -#endif - -#if STM32_NAND_USE_FSMC_NAND2 && !defined(__DOXYGEN__) -extern NANDDriver NANDD2; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void nand_lld_init(void); - void nand_lld_start(NANDDriver *nandp); - void nand_lld_stop(NANDDriver *nandp); - uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen); - void nand_lld_read_data(NANDDriver *nandp, uint16_t *data, - size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc); - void nand_lld_write_addr(NANDDriver *nandp, const uint8_t *addr, size_t len); - void nand_lld_write_cmd(NANDDriver *nandp, uint8_t cmd); - uint8_t nand_lld_write_data(NANDDriver *nandp, const uint16_t *data, - size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc); - uint8_t nand_lld_read_status(NANDDriver *nandp); - void nand_lld_reset(NANDDriver *nandp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_NAND */ - -#endif /* HAL_NAND_LLD_H_ */ - -/** @} */ diff --git a/os/hal/src/hal_community.c b/os/hal/src/hal_community.c index ad05fe4..02de5cd 100644 --- a/os/hal/src/hal_community.c +++ b/os/hal/src/hal_community.c @@ -84,6 +84,10 @@ void halCommunityInit(void) { #if HAL_USE_COMP || defined(__DOXYGEN__) compInit(); #endif + +#if HAL_USE_FSMC || defined(__DOXYGEN__) + fsmcInit(); +#endif } #endif /* HAL_USE_COMMUNITY */ diff --git a/os/hal/src/hal_fsmc.c b/os/hal/src/hal_fsmc.c new file mode 100644 index 0000000..7304866 --- /dev/null +++ b/os/hal/src/hal_fsmc.c @@ -0,0 +1,244 @@ +/* + ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_fsmc.c + * @brief FSMC Driver subsystem low level driver source template. + * + * @addtogroup FSMC + * @{ + */ +#include "hal.h" + +#if (HAL_USE_FSMC_SDRAM == TRUE) || (HAL_USE_FSMC_SRAM == TRUE) || (HAL_USE_FSMC_NAND == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + + + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief FSMC1 driver identifier. + */ +#if STM32_FSMC_USE_FSMC1 || defined(__DOXYGEN__) +FSMCDriver FSMCD1; +#endif + +/*===========================================================================*/ +/* Driver local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +#include "hal_fsmc_sdram_lld.h" + +/** + * @brief Low level FSMC driver initialization. + * + * @notapi + */ +void fsmcInit(void) { + + if (FSMCD1.state == FSMC_UNINIT) { + FSMCD1.state = FSMC_STOP; + +#if STM32_FSMC_USE_SRAM1 + FSMCD1.sram1 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE); +#endif + +#if STM32_FSMC_USE_SRAM2 + FSMCD1.sram2 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8); +#endif + +#if STM32_FSMC_USE_SRAM3 + FSMCD1.sram3 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 2); +#endif + +#if STM32_FSMC_USE_SRAM4 + FSMCD1.sram4 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 3); +#endif + +#if STM32_FSMC_USE_NAND1 + FSMCD1.nand1 = (FSMC_NAND_TypeDef *)FSMC_Bank2_R_BASE; +#endif + +#if STM32_FSMC_USE_NAND2 + FSMCD1.nand2 = (FSMC_NAND_TypeDef *)FSMC_Bank3_R_BASE; +#endif + +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F745xx) || defined(STM32F746xx) || \ + defined(STM32F756xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || \ + defined(STM32F779xx)) + #if STM32_FSMC_USE_SDRAM1 || STM32_FSMC_USE_SDRAM2 + FSMCD1.sdram = (FSMC_SDRAM_TypeDef *)FSMC_Bank5_6_R_BASE; + #endif +#endif + } +} + +/** + * @brief Configures and activates the FSMC peripheral. + * + * @param[in] fsmcp pointer to the @p FSMCDriver object + * + * @notapi + */ +void fsmcStart(FSMCDriver *fsmcp) { + + osalDbgAssert((fsmcp->state == FSMC_STOP) || (fsmcp->state == FSMC_READY), + "invalid state"); + + if (fsmcp->state == FSMC_STOP) { + /* Enables the peripheral.*/ +#if STM32_FSMC_USE_FSMC1 + if (&FSMCD1 == fsmcp) { +#ifdef rccResetFSMC + rccResetFSMC(); +#endif + rccEnableFSMC(FALSE); +#if HAL_USE_NAND + nvicEnableVector(STM32_FSMC_NUMBER, STM32_FSMC_FSMC1_IRQ_PRIORITY); +#endif + } +#endif /* STM32_FSMC_USE_FSMC1 */ + + fsmcp->state = FSMC_READY; + } +} + +/** + * @brief Deactivates the FSMC peripheral. + * + * @param[in] emcp pointer to the @p FSMCDriver object + * + * @notapi + */ +void fsmcStop(FSMCDriver *fsmcp) { + + if (fsmcp->state == FSMC_READY) { + /* Resets the peripheral.*/ +#ifdef rccResetFSMC + rccResetFSMC(); +#endif + + /* Disables the peripheral.*/ +#if STM32_FSMC_USE_FSMC1 + if (&FSMCD1 == fsmcp) { +#if HAL_USE_NAND + nvicDisableVector(STM32_FSMC_NUMBER); +#endif + rccDisableFSMC(); + } +#endif /* STM32_FSMC_USE_FSMC1 */ + + fsmcp->state = FSMC_STOP; + } +} + +/** + * @brief FSMC shared interrupt handler. + * + * @notapi + */ +CH_IRQ_HANDLER(STM32_FSMC_HANDLER) { + + CH_IRQ_PROLOGUE(); +#if STM32_FSMC_USE_NAND1 + if (FSMCD1.nand1->SR & FSMC_SR_ISR_MASK) { + NANDD1.isr_handler(&NANDD1); + } +#endif +#if STM32_FSMC_USE_NAND2 + if (FSMCD1.nand2->SR & FSMC_SR_ISR_MASK) { + NANDD2.isr_handler(&NANDD2); + } +#endif + CH_IRQ_EPILOGUE(); +} + + +/** + * @brief FSMC SDRAM Driver init + */ +void fsmcSdramInit(void) { + + fsmcInit(); + SDRAMD.sdram = FSMCD1.sdram; + SDRAMD.state = SDRAM_STOP; +} + +/** + * @brief Configures and activates the SDRAM peripheral. + * + * @param[in] sdramp pointer to the @p SDRAMDriver object + * @param[in] cfgp pointer to the @p SDRAMConfig object + */ +void fsmcSdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp) { + + if (FSMCD1.state == FSMC_STOP) + fsmcStart(&FSMCD1); + + osalDbgAssert((sdramp->state == SDRAM_STOP) || (sdramp->state == SDRAM_READY), + "SDRAM. Invalid state."); + + if (sdramp->state == SDRAM_STOP) { + + lld_sdram_start(sdramp, cfgp); + + sdramp->state = SDRAM_READY; + } +} + +/** + * @brief Deactivates the SDRAM peripheral. + * + * @param[in] sdramp pointer to the @p SDRAMDriver object + * + * @notapi + */ +void fsmcSdramStop(SDRAMDriver *sdramp) { + + if (sdramp->state == SDRAM_READY) { + lld_sdram_stop(sdramp); + sdramp->state = SDRAM_STOP; + } +} + +#endif /* HAL_USE_FSMC */ + +/** @} */ diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h b/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h index da9c607..d1d3ada 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h @@ -27,8 +27,22 @@ /** * @brief Enables the FSMC subsystem. */ -#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) -#define HAL_USE_FSMC TRUE +#if !defined(HAL_USE_FSMC_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_FSMC_SDRAM TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_FSMC_SRAM FALSE +#endif + +/** + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC_NAND) || defined(__DOXYGEN__) +#define HAL_USE_FSMC_NAND FALSE #endif /** diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c b/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c index 1ec34d2..45e8db6 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c +++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c @@ -23,7 +23,6 @@ #include "string.h" -#include "hal_fsmc_sdram.h" #include "membench.h" #include "memtest.h" diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf_community.h b/testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf_community.h index c8d995f..4494929 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf_community.h @@ -22,32 +22,30 @@ #define STM32_FSMC_USE_FSMC1 TRUE #define STM32_FSMC_FSMC1_IRQ_PRIORITY 10 #define STM32_FSMC_DMA_CHN 0x03010201 +#define STM32_FSMC_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_FSMC_DMA_PRIORITY 0 +#define STM32_FSMC_DMA_ERROR_HOOK(nandp) osalSysHalt("FSMC DMA failure") /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE -#define STM32_NAND_USE_EXT_INT FALSE -#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_NAND_DMA_PRIORITY 0 -#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure") +#define STM32_FSMC_USE_NAND1 FALSE +#define STM32_FSMC_USE_NAND2 FALSE +#define STM32_FSMC_USE_NAND_EXT_INT FALSE /* * FSMC SRAM driver system settings. */ -#define STM32_USE_FSMC_SRAM FALSE -#define STM32_SRAM_USE_FSMC_SRAM1 FALSE -#define STM32_SRAM_USE_FSMC_SRAM2 FALSE -#define STM32_SRAM_USE_FSMC_SRAM3 FALSE -#define STM32_SRAM_USE_FSMC_SRAM4 FALSE +#define STM32_FSMC_USE_SRAM1 FALSE +#define STM32_FSMC_USE_SRAM2 FALSE +#define STM32_FSMC_USE_SRAM3 FALSE +#define STM32_FSMC_USE_SRAM4 FALSE /* * FSMC SDRAM driver system settings. */ -#define STM32_USE_FSMC_SDRAM TRUE -#define STM32_SDRAM_USE_FSMC_SDRAM1 FALSE -#define STM32_SDRAM_USE_FSMC_SDRAM2 TRUE +#define STM32_FSMC_USE_SDRAM1 FALSE +#define STM32_FSMC_USE_SDRAM2 TRUE /* * TIMCAP driver system settings. -- cgit v1.2.3 From 90f32c35466c9edbd59716de66903b3f537f5abb Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Tue, 29 Oct 2019 20:16:08 +0100 Subject: Updating FSMC driver (SRAM part) --- os/hal/include/fsmc/sram.h | 32 +++---- os/hal/include/hal_fsmc.h | 12 +-- os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c | 2 +- os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.h | 2 +- os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.c | 61 +++----------- os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.h | 97 ++-------------------- os/hal/src/hal_fsmc.c | 79 +++++++++++++++++- .../STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h | 7 -- .../STM32/STM32F4xx/FSMC_SRAM/halconf_community.h | 17 ++-- testhal/STM32/STM32F4xx/FSMC_SRAM/main.c | 1 - .../STM32/STM32F4xx/FSMC_SRAM/mcuconf_community.h | 26 +++--- 11 files changed, 143 insertions(+), 193 deletions(-) diff --git a/os/hal/include/fsmc/sram.h b/os/hal/include/fsmc/sram.h index 6eed97a..4a19246 100644 --- a/os/hal/include/fsmc/sram.h +++ b/os/hal/include/fsmc/sram.h @@ -43,32 +43,32 @@ * @brief SRAM driver enable switch. * @details If set to @p TRUE the support for SRAM1 is included. */ -#if !defined(STM32_SRAM_USE_FSMC_SRAM1) || defined(__DOXYGEN__) -#define STM32_SRAM_USE_FSMC_SRAM1 FALSE +#if !defined(STM32_FSMC_USE_SRAM1) || defined(__DOXYGEN__) +#define STM32_FSMC_USE_SRAM1 FALSE #endif /** * @brief SRAM driver enable switch. * @details If set to @p TRUE the support for SRAM2 is included. */ -#if !defined(STM32_SRAM_USE_FSMC_SRAM2) || defined(__DOXYGEN__) -#define STM32_SRAM_USE_FSMC_SRAM2 FALSE +#if !defined(STM32_FSMC_USE_SRAM2) || defined(__DOXYGEN__) +#define STM32_FSMC_USE_SRAM2 FALSE #endif /** * @brief SRAM driver enable switch. * @details If set to @p TRUE the support for SRAM3 is included. */ -#if !defined(STM32_SRAM_USE_FSMC_SRAM3) || defined(__DOXYGEN__) -#define STM32_SRAM_USE_FSMC_SRAM3 FALSE +#if !defined(STM32_FSMC_USE_SRAM3) || defined(__DOXYGEN__) +#define STM32_FSMC_USE_SRAM3 FALSE #endif /** * @brief SRAM driver enable switch. * @details If set to @p TRUE the support for SRAM4 is included. */ -#if !defined(STM32_SRAM_USE_FSMC_SRAM4) || defined(__DOXYGEN__) -#define STM32_SRAM_USE_FSMC_SRAM4 FALSE +#if !defined(STM32_FSMC_USE_SRAM4) || defined(__DOXYGEN__) +#define STM32_FSMC_USE_SRAM4 FALSE #endif /** @} */ @@ -77,13 +77,13 @@ /* Derived constants and error checks. */ /*===========================================================================*/ -#if !STM32_SRAM_USE_FSMC_SRAM1 && !STM32_SRAM_USE_FSMC_SRAM2 && \ - !STM32_SRAM_USE_FSMC_SRAM3 && !STM32_SRAM_USE_FSMC_SRAM4 +#if !STM32_FSMC_USE_SRAM1 && !STM32_FSMC_USE_SRAM2 && \ + !STM32_FSMC_USE_SRAM3 && !STM32_FSMC_USE_SRAM4 #error "SRAM driver activated but no SRAM peripheral assigned" #endif -#if (STM32_SRAM_USE_FSMC_SRAM1 || STM32_SRAM_USE_FSMC_SRAM2 || \ - STM32_SRAM_USE_FSMC_SRAM3 || STM32_SRAM_USE_FSMC_SRAM4) && !STM32_HAS_FSMC +#if (STM32_FSMC_USE_SRAM1 || STM32_FSMC_USE_SRAM2 || \ + STM32_FSMC_USE_SRAM3 || STM32_FSMC_USE_SRAM4) && !STM32_HAS_FSMC #error "FSMC not present in the selected device" #endif @@ -137,19 +137,19 @@ struct SRAMDriver { /* External declarations. */ /*===========================================================================*/ -#if STM32_SRAM_USE_FSMC_SRAM1 && !defined(__DOXYGEN__) +#if STM32_FSMC_USE_SRAM1 && !defined(__DOXYGEN__) extern SRAMDriver SRAMD1; #endif -#if STM32_SRAM_USE_FSMC_SRAM2 && !defined(__DOXYGEN__) +#if STM32_FSMC_USE_SRAM2 && !defined(__DOXYGEN__) extern SRAMDriver SRAMD2; #endif -#if STM32_SRAM_USE_FSMC_SRAM3 && !defined(__DOXYGEN__) +#if STM32_FSMC_USE_SRAM3 && !defined(__DOXYGEN__) extern SRAMDriver SRAMD3; #endif -#if STM32_SRAM_USE_FSMC_SRAM4 && !defined(__DOXYGEN__) +#if STM32_FSMC_USE_SRAM4 && !defined(__DOXYGEN__) extern SRAMDriver SRAMD4; #endif diff --git a/os/hal/include/hal_fsmc.h b/os/hal/include/hal_fsmc.h index f85079a..834fa8d 100644 --- a/os/hal/include/hal_fsmc.h +++ b/os/hal/include/hal_fsmc.h @@ -327,25 +327,25 @@ struct FSMCDriver { /* End of the mandatory fields.*/ #if HAL_USE_FSMC_SRAM - #if STM32_SRAM_USE_FSMC_SRAM1 + #if STM32_FSMC_USE_SRAM1 FSMC_SRAM_NOR_TypeDef *sram1; #endif - #if STM32_SRAM_USE_FSMC_SRAM2 + #if STM32_FSMC_USE_SRAM2 FSMC_SRAM_NOR_TypeDef *sram2; #endif - #if STM32_SRAM_USE_FSMC_SRAM3 + #if STM32_FSMC_USE_SRAM3 FSMC_SRAM_NOR_TypeDef *sram3; #endif - #if STM32_SRAM_USE_FSMC_SRAM4 + #if STM32_FSMC_USE_SRAM4 FSMC_SRAM_NOR_TypeDef *sram4; #endif #endif #if HAL_USE_FSMC_NAND - #if STM32_NAND_USE_FSMC_NAND1 + #if STM32_FSMC_USE_NAND1 FSMC_NAND_TypeDef *nand1; #endif - #if STM32_NAND_USE_FSMC_NAND2 + #if STM32_FSMC_USE_NAND1 FSMC_NAND_TypeDef *nand2; #endif #endif diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c index 5934f88..1b0c0db 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c @@ -34,7 +34,7 @@ defined(STM32F769xx) || defined(STM32F777xx) || \ defined(STM32F779xx)) -#if (STM32_FSMC_USE_SDRAM1 == TRUE) || (STM32_FSMC_USE_SDRAM2 == TRUE) || defined(__DOXYGEN__) +#if (HAL_USE_FSMC_SDRAM == TRUE) || defined(__DOXYGEN__) #include "hal_fsmc_sdram_lld.h" diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.h index 0e533b6..1fc7993 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.h @@ -37,7 +37,7 @@ #include "hal_fsmc.h" -#if (STM32_FSMC_USE_SDRAM1 == TRUE) || (STM32_FSMC_USE_SDRAM2 == TRUE) || defined(__DOXYGEN__) +#if (HAL_USE_FSMC_SDRAM == TRUE) || defined(__DOXYGEN__) /*===========================================================================*/ /* Driver constants. */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.c index da13ca5..49b7826 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.c @@ -22,9 +22,10 @@ * @{ */ #include "hal.h" -#include "hal_fsmc_sram.h" -#if (STM32_USE_FSMC_SRAM == TRUE) || defined(__DOXYGEN__) +#if (HAL_USE_FSMC_SRAM == TRUE) || defined(__DOXYGEN__) + +#include "hal_fsmc_sram_lld.h" /*===========================================================================*/ /* Driver local definitions. */ @@ -36,28 +37,28 @@ /** * @brief SRAM1 driver identifier. */ -#if STM32_SRAM_USE_FSMC_SRAM1 || defined(__DOXYGEN__) +#if STM32_FSMC_USE_SRAM1 || defined(__DOXYGEN__) SRAMDriver SRAMD1; #endif /** * @brief SRAM2 driver identifier. */ -#if STM32_SRAM_USE_FSMC_SRAM2 || defined(__DOXYGEN__) +#if STM32_FSMC_USE_SRAM2 || defined(__DOXYGEN__) SRAMDriver SRAMD2; #endif /** * @brief SRAM3 driver identifier. */ -#if STM32_SRAM_USE_FSMC_SRAM3 || defined(__DOXYGEN__) +#if STM32_FSMC_USE_SRAM3 || defined(__DOXYGEN__) SRAMDriver SRAMD3; #endif /** * @brief SRAM4 driver identifier. */ -#if STM32_SRAM_USE_FSMC_SRAM4 || defined(__DOXYGEN__) +#if STM32_FSMC_USE_SRAM4 || defined(__DOXYGEN__) SRAMDriver SRAMD4; #endif @@ -81,36 +82,6 @@ SRAMDriver SRAMD4; /* Driver exported functions. */ /*===========================================================================*/ -/** - * @brief Low level SRAM driver initialization. - * - * @notapi - */ -void fsmcSramInit(void) { - - fsmc_init(); - -#if STM32_SRAM_USE_FSMC_SRAM1 - SRAMD1.sram = FSMCD1.sram1; - SRAMD1.state = SRAM_STOP; -#endif /* STM32_SRAM_USE_FSMC_SRAM1 */ - -#if STM32_SRAM_USE_FSMC_SRAM2 - SRAMD2.sram = FSMCD1.sram2; - SRAMD2.state = SRAM_STOP; -#endif /* STM32_SRAM_USE_FSMC_SRAM2 */ - -#if STM32_SRAM_USE_FSMC_SRAM3 - SRAMD3.sram = FSMCD1.sram3; - SRAMD3.state = SRAM_STOP; -#endif /* STM32_SRAM_USE_FSMC_SRAM3 */ - -#if STM32_SRAM_USE_FSMC_SRAM4 - SRAMD4.sram = FSMCD1.sram4; - SRAMD4.state = SRAM_STOP; -#endif /* STM32_SRAM_USE_FSMC_SRAM4 */ -} - /** * @brief Configures and activates the SRAM peripheral. * @@ -119,20 +90,11 @@ void fsmcSramInit(void) { * * @notapi */ -void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp) { - - if (FSMCD1.state == FSMC_STOP) - fsmc_start(&FSMCD1); - - osalDbgAssert((sramp->state == SRAM_STOP) || (sramp->state == SRAM_READY), - "invalid state"); +void lld_sram_start(SRAMDriver *sramp, const SRAMConfig *cfgp) { - if (sramp->state == SRAM_STOP) { sramp->sram->BTR = cfgp->btr; sramp->sram->BWTR = cfgp->bwtr; sramp->sram->BCR = cfgp->bcr | FSMC_BCR_MBKEN; - sramp->state = SRAM_READY; - } } /** @@ -142,9 +104,8 @@ void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp) { * * @notapi */ -void fsmcSramStop(SRAMDriver *sramp) { +void lld_sram_stop(SRAMDriver *sramp) { - if (sramp->state == SRAM_READY) { uint32_t mask = FSMC_BCR_MBKEN; #if (defined(STM32F427xx) || defined(STM32F437xx) || \ defined(STM32F429xx) || defined(STM32F439xx) || \ @@ -155,11 +116,9 @@ void fsmcSramStop(SRAMDriver *sramp) { mask |= FSMC_BCR_CCLKEN; #endif sramp->sram->BCR &= ~mask; - sramp->state = SRAM_STOP; - } } -#endif /* STM32_USE_FSMC_SRAM */ +#endif /* STM32_FSMC_USE_SRAM */ /** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.h index 5e749a8..bfd878f 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.h @@ -27,7 +27,7 @@ #include "hal_fsmc.h" -#if (STM32_USE_FSMC_SRAM == TRUE) || defined(__DOXYGEN__) +#if (HAL_USE_FSMC_SRAM == TRUE) || defined(__DOXYGEN__) /*===========================================================================*/ /* Driver constants. */ @@ -41,95 +41,15 @@ * @{ */ -/** - * @brief SRAM driver enable switch. - * @details If set to @p TRUE the support for SRAM1 is included. - */ -#if !defined(STM32_SRAM_USE_FSMC_SRAM1) || defined(__DOXYGEN__) -#define STM32_SRAM_USE_FSMC_SRAM1 FALSE -#endif - -/** - * @brief SRAM driver enable switch. - * @details If set to @p TRUE the support for SRAM2 is included. - */ -#if !defined(STM32_SRAM_USE_FSMC_SRAM2) || defined(__DOXYGEN__) -#define STM32_SRAM_USE_FSMC_SRAM2 FALSE -#endif - -/** - * @brief SRAM driver enable switch. - * @details If set to @p TRUE the support for SRAM3 is included. - */ -#if !defined(STM32_SRAM_USE_FSMC_SRAM3) || defined(__DOXYGEN__) -#define STM32_SRAM_USE_FSMC_SRAM3 FALSE -#endif - -/** - * @brief SRAM driver enable switch. - * @details If set to @p TRUE the support for SRAM4 is included. - */ -#if !defined(STM32_SRAM_USE_FSMC_SRAM4) || defined(__DOXYGEN__) -#define STM32_SRAM_USE_FSMC_SRAM4 FALSE -#endif - /** @} */ /*===========================================================================*/ /* Derived constants and error checks. */ /*===========================================================================*/ -#if !STM32_SRAM_USE_FSMC_SRAM1 && !STM32_SRAM_USE_FSMC_SRAM2 && \ - !STM32_SRAM_USE_FSMC_SRAM3 && !STM32_SRAM_USE_FSMC_SRAM4 -#error "SRAM driver activated but no SRAM peripheral assigned" -#endif - -#if (STM32_SRAM_USE_FSMC_SRAM1 || STM32_SRAM_USE_FSMC_SRAM2 || \ - STM32_SRAM_USE_FSMC_SRAM3 || STM32_SRAM_USE_FSMC_SRAM4) && !STM32_HAS_FSMC -#error "FSMC not present in the selected device" -#endif - /*===========================================================================*/ /* Driver data structures and types. */ /*===========================================================================*/ -/** - * @brief Driver state machine possible states. - */ -typedef enum { - SRAM_UNINIT = 0, /**< Not initialized. */ - SRAM_STOP = 1, /**< Stopped. */ - SRAM_READY = 2, /**< Ready. */ -} sramstate_t; - -/** - * @brief Type of a structure representing an NAND driver. - */ -typedef struct SRAMDriver SRAMDriver; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - * @note Some bits in BCR register will be forced by driver. - */ -typedef struct { - uint32_t bcr; - uint32_t btr; - uint32_t bwtr; -} SRAMConfig; - -/** - * @brief Structure representing an NAND driver. - */ -struct SRAMDriver { - /** - * @brief Driver state. - */ - sramstate_t state; - /** - * @brief Pointer to the FSMC SRAM registers block. - */ - FSMC_SRAM_NOR_TypeDef *sram; -}; /*===========================================================================*/ /* Driver macros. */ @@ -139,33 +59,32 @@ struct SRAMDriver { /* External declarations. */ /*===========================================================================*/ -#if STM32_SRAM_USE_FSMC_SRAM1 && !defined(__DOXYGEN__) +#if STM32_FSMC_USE_SRAM1 && !defined(__DOXYGEN__) extern SRAMDriver SRAMD1; #endif -#if STM32_SRAM_USE_FSMC_SRAM2 && !defined(__DOXYGEN__) +#if STM32_FSMC_USE_SRAM2 && !defined(__DOXYGEN__) extern SRAMDriver SRAMD2; #endif -#if STM32_SRAM_USE_FSMC_SRAM3 && !defined(__DOXYGEN__) +#if STM32_FSMC_USE_SRAM3 && !defined(__DOXYGEN__) extern SRAMDriver SRAMD3; #endif -#if STM32_SRAM_USE_FSMC_SRAM4 && !defined(__DOXYGEN__) +#if STM32_FSMC_USE_SRAM4 && !defined(__DOXYGEN__) extern SRAMDriver SRAMD4; #endif #ifdef __cplusplus extern "C" { #endif - void fsmcSramInit(void); - void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp); - void fsmcSramStop(SRAMDriver *sramp); + void lld_sram_start(SRAMDriver *sramp, const SRAMConfig *cfgp); + void lld_sram_stop(SRAMDriver *sramp); #ifdef __cplusplus } #endif -#endif /* STM32_USE_FSMC_SRAM */ +#endif /* STM32_FSMC_USE_SRAM */ #endif /* HAL_FSMC_SRAM_H_ */ diff --git a/os/hal/src/hal_fsmc.c b/os/hal/src/hal_fsmc.c index 7304866..cdbb387 100644 --- a/os/hal/src/hal_fsmc.c +++ b/os/hal/src/hal_fsmc.c @@ -62,8 +62,6 @@ FSMCDriver FSMCD1; /* Driver exported functions. */ /*===========================================================================*/ -#include "hal_fsmc_sdram_lld.h" - /** * @brief Low level FSMC driver initialization. * @@ -191,7 +189,9 @@ CH_IRQ_HANDLER(STM32_FSMC_HANDLER) { CH_IRQ_EPILOGUE(); } +#if (HAL_USE_FSMC_SDRAM == TRUE) +#include "hal_fsmc_sdram_lld.h" /** * @brief FSMC SDRAM Driver init */ @@ -238,6 +238,81 @@ void fsmcSdramStop(SDRAMDriver *sdramp) { sdramp->state = SDRAM_STOP; } } +#endif /* HAL_USE_FSMC_SDRAM == TRUE */ + + +#if (HAL_USE_FSMC_SRAM == TRUE) + +#include "hal_fsmc_sram_lld.h" + +/** + * @brief Low level SRAM driver initialization. + * + * @notapi + */ +void fsmcSramInit(void) { + + fsmcInit(); + +#if STM32_FSMC_USE_SRAM1 + SRAMD1.sram = FSMCD1.sram1; + SRAMD1.state = SRAM_STOP; +#endif /* STM32_FSMC_USE_SRAM1 */ + +#if STM32_FSMC_USE_SRAM2 + SRAMD2.sram = FSMCD1.sram2; + SRAMD2.state = SRAM_STOP; +#endif /* STM32_FSMC_USE_SRAM2 */ + +#if STM32_FSMC_USE_SRAM3 + SRAMD3.sram = FSMCD1.sram3; + SRAMD3.state = SRAM_STOP; +#endif /* STM32_FSMC_USE_SRAM3 */ + +#if STM32_FSMC_USE_SRAM4 + SRAMD4.sram = FSMCD1.sram4; + SRAMD4.state = SRAM_STOP; +#endif /* STM32_FSMC_USE_SRAM4 */ +} + +/** + * @brief Configures and activates the SRAM peripheral. + * + * @param[in] sramp pointer to the @p SRAMDriver object + * @param[in] cfgp pointer to the @p SRAMConfig object + * + * @notapi + */ +void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp) { + + if (FSMCD1.state == FSMC_STOP) + fsmcStart(&FSMCD1); + + osalDbgAssert((sramp->state == SRAM_STOP) || (sramp->state == SRAM_READY), + "invalid state"); + + if (sramp->state == SRAM_STOP) { + lld_sram_start(sramp, cfgp); + sramp->state = SRAM_READY; + } +} + +/** + * @brief Deactivates the SRAM peripheral. + * + * @param[in] sramp pointer to the @p SRAMDriver object + * + * @notapi + */ +void fsmcSramStop(SRAMDriver *sramp) { + + if (sramp->state == SRAM_READY) { + lld_sram_stop(sramp); + sramp->state = SRAM_STOP; + } +} + +#endif /* HAL_USE_FSMC_SRAM == TRUE */ #endif /* HAL_USE_FSMC */ diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h b/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h index d1d3ada..9ad41fd 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h @@ -45,13 +45,6 @@ #define HAL_USE_FSMC_NAND FALSE #endif -/** - * @brief Enables the NAND subsystem. - */ -#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) -#define HAL_USE_NAND FALSE -#endif - /** * @brief Enables the 1-wire subsystem. */ diff --git a/testhal/STM32/STM32F4xx/FSMC_SRAM/halconf_community.h b/testhal/STM32/STM32F4xx/FSMC_SRAM/halconf_community.h index da9c607..f9cfcbe 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SRAM/halconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_SRAM/halconf_community.h @@ -27,15 +27,22 @@ /** * @brief Enables the FSMC subsystem. */ -#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) -#define HAL_USE_FSMC TRUE +#if !defined(HAL_USE_FSMC_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_FSMC_SDRAM FALSE #endif /** - * @brief Enables the NAND subsystem. + * @brief Enables the FSMC subsystem. + */ +#if !defined(HAL_USE_FSMC_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_FSMC_SRAM TRUE +#endif + +/** + * @brief Enables the FSMC subsystem. */ -#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) -#define HAL_USE_NAND FALSE +#if !defined(HAL_USE_FSMC_NAND) || defined(__DOXYGEN__) +#define HAL_USE_FSMC_NAND FALSE #endif /** diff --git a/testhal/STM32/STM32F4xx/FSMC_SRAM/main.c b/testhal/STM32/STM32F4xx/FSMC_SRAM/main.c index c94bd73..6413835 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SRAM/main.c +++ b/testhal/STM32/STM32F4xx/FSMC_SRAM/main.c @@ -17,7 +17,6 @@ #include "ch.h" #include "hal.h" -#include "hal_fsmc_sram.h" #include "membench.h" #include "memtest.h" diff --git a/testhal/STM32/STM32F4xx/FSMC_SRAM/mcuconf_community.h b/testhal/STM32/STM32F4xx/FSMC_SRAM/mcuconf_community.h index 317fe5d..8abb48d 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SRAM/mcuconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_SRAM/mcuconf_community.h @@ -22,32 +22,30 @@ #define STM32_FSMC_USE_FSMC1 TRUE #define STM32_FSMC_FSMC1_IRQ_PRIORITY 10 #define STM32_FSMC_DMA_CHN 0x03010201 +#define STM32_FSMC_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_FSMC_DMA_PRIORITY 0 +#define STM32_FSMC_DMA_ERROR_HOOK(nandp) osalSysHalt("FSMC DMA failure") /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE -#define STM32_NAND_USE_EXT_INT FALSE -#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_NAND_DMA_PRIORITY 0 -#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure") +#define STM32_FSMC_USE_NAND1 FALSE +#define STM32_FSMC_USE_NAND2 FALSE +#define STM32_FSMC_USE_NAND_EXT_INT FALSE /* * FSMC SRAM driver system settings. */ -#define STM32_USE_FSMC_SRAM TRUE -#define STM32_SRAM_USE_FSMC_SRAM1 FALSE -#define STM32_SRAM_USE_FSMC_SRAM2 FALSE -#define STM32_SRAM_USE_FSMC_SRAM3 FALSE -#define STM32_SRAM_USE_FSMC_SRAM4 TRUE +#define STM32_FSMC_USE_SRAM1 FALSE +#define STM32_FSMC_USE_SRAM2 FALSE +#define STM32_FSMC_USE_SRAM3 FALSE +#define STM32_FSMC_USE_SRAM4 TRUE /* * FSMC SDRAM driver system settings. */ -#define STM32_USE_FSMC_SDRAM FALSE -#define STM32_SDRAM_USE_FSMC_SDRAM1 FALSE -#define STM32_SDRAM_USE_FSMC_SDRAM2 TRUE +#define STM32_FSMC_USE_SDRAM1 FALSE +#define STM32_FSMC_USE_SDRAM2 FALSE /* * TIMCAP driver system settings. -- cgit v1.2.3 From 13ebce61e2f0af08d6ffa0c13397da5ad31292c4 Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Wed, 30 Oct 2019 10:53:30 +0100 Subject: Moved SDRAM defines out of example --- os/hal/include/fsmc/sdram.h | 83 ++++++++++++++++++++++++++++++- testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c | 78 ----------------------------- 2 files changed, 81 insertions(+), 80 deletions(-) diff --git a/os/hal/include/fsmc/sdram.h b/os/hal/include/fsmc/sdram.h index 83b78a6..7a04bdc 100644 --- a/os/hal/include/fsmc/sdram.h +++ b/os/hal/include/fsmc/sdram.h @@ -41,6 +41,85 @@ /* Driver constants. */ /*===========================================================================*/ +/* + * FMC SDRAM Mode definition register defines + */ +#define FMC_SDCMR_MRD_BURST_LENGTH_1 ((uint16_t)0x0000) +#define FMC_SDCMR_MRD_BURST_LENGTH_2 ((uint16_t)0x0001) +#define FMC_SDCMR_MRD_BURST_LENGTH_4 ((uint16_t)0x0002) +#define FMC_SDCMR_MRD_BURST_LENGTH_8 ((uint16_t)0x0004) +#define FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) +#define FMC_SDCMR_MRD_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) +#define FMC_SDCMR_MRD_CAS_LATENCY_2 ((uint16_t)0x0020) +#define FMC_SDCMR_MRD_CAS_LATENCY_3 ((uint16_t)0x0030) +#define FMC_SDCMR_MRD_OPERATING_MODE_STANDARD ((uint16_t)0x0000) +#define FMC_SDCMR_MRD_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) +#define FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) + +/* + * FMC_ReadPipe_Delay + */ +#define FMC_ReadPipe_Delay_0 ((uint32_t)0x00000000) +#define FMC_ReadPipe_Delay_1 ((uint32_t)0x00002000) +#define FMC_ReadPipe_Delay_2 ((uint32_t)0x00004000) +#define FMC_ReadPipe_Delay_Mask ((uint32_t)0x00006000) + +/* + * FMC_Read_Burst + */ +#define FMC_Read_Burst_Disable ((uint32_t)0x00000000) +#define FMC_Read_Burst_Enable ((uint32_t)0x00001000) +#define FMC_Read_Burst_Mask ((uint32_t)0x00001000) + +/* + * FMC_SDClock_Period + */ +#define FMC_SDClock_Disable ((uint32_t)0x00000000) +#define FMC_SDClock_Period_2 ((uint32_t)0x00000800) +#define FMC_SDClock_Period_3 ((uint32_t)0x00000C00) +#define FMC_SDClock_Period_Mask ((uint32_t)0x00000C00) + +/* + * FMC_ColumnBits_Number + */ +#define FMC_ColumnBits_Number_8b ((uint32_t)0x00000000) +#define FMC_ColumnBits_Number_9b ((uint32_t)0x00000001) +#define FMC_ColumnBits_Number_10b ((uint32_t)0x00000002) +#define FMC_ColumnBits_Number_11b ((uint32_t)0x00000003) + +/* + * FMC_RowBits_Number + */ +#define FMC_RowBits_Number_11b ((uint32_t)0x00000000) +#define FMC_RowBits_Number_12b ((uint32_t)0x00000004) +#define FMC_RowBits_Number_13b ((uint32_t)0x00000008) + +/* + * FMC_SDMemory_Data_Width + */ +#define FMC_SDMemory_Width_8b ((uint32_t)0x00000000) +#define FMC_SDMemory_Width_16b ((uint32_t)0x00000010) +#define FMC_SDMemory_Width_32b ((uint32_t)0x00000020) + +/* + * FMC_InternalBank_Number + */ +#define FMC_InternalBank_Number_2 ((uint32_t)0x00000000) +#define FMC_InternalBank_Number_4 ((uint32_t)0x00000040) + +/* + * FMC_CAS_Latency + */ +#define FMC_CAS_Latency_1 ((uint32_t)0x00000080) +#define FMC_CAS_Latency_2 ((uint32_t)0x00000100) +#define FMC_CAS_Latency_3 ((uint32_t)0x00000180) + +/* + * FMC_Write_Protection + */ +#define FMC_Write_Protection_Disable ((uint32_t)0x00000000) +#define FMC_Write_Protection_Enable ((uint32_t)0x00000200) + /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ @@ -56,7 +135,7 @@ #if !defined(STM32_FSMC_USE_SDRAM1) || defined(__DOXYGEN__) #define STM32_FSMC_USE_SDRAM1 FALSE #else -#define STM32_SDRAM1_MAP_BASE FSMC_Bank5_MAP_BASE +#define STM32_SDRAM1_MAP_BASE FSMC_Bank5_MAP_BASE #endif /** @@ -66,7 +145,7 @@ #if !defined(STM32_FSMC_USE_SDRAM2) || defined(__DOXYGEN__) #define STM32_FSMC_USE_SDRAM2 FALSE #else -#define STM32_SDRAM2_MAP_BASE FSMC_Bank6_MAP_BASE +#define STM32_SDRAM2_MAP_BASE FSMC_Bank6_MAP_BASE #endif /** @} */ diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c b/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c index 45e8db6..1ff7740 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c +++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c @@ -32,84 +32,6 @@ ****************************************************************************** */ -/* - * FMC SDRAM Mode definition register defines - */ -#define FMC_SDCMR_MRD_BURST_LENGTH_1 ((uint16_t)0x0000) -#define FMC_SDCMR_MRD_BURST_LENGTH_2 ((uint16_t)0x0001) -#define FMC_SDCMR_MRD_BURST_LENGTH_4 ((uint16_t)0x0002) -#define FMC_SDCMR_MRD_BURST_LENGTH_8 ((uint16_t)0x0004) -#define FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) -#define FMC_SDCMR_MRD_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) -#define FMC_SDCMR_MRD_CAS_LATENCY_2 ((uint16_t)0x0020) -#define FMC_SDCMR_MRD_CAS_LATENCY_3 ((uint16_t)0x0030) -#define FMC_SDCMR_MRD_OPERATING_MODE_STANDARD ((uint16_t)0x0000) -#define FMC_SDCMR_MRD_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) -#define FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) - -/* - * FMC_ReadPipe_Delay - */ -#define FMC_ReadPipe_Delay_0 ((uint32_t)0x00000000) -#define FMC_ReadPipe_Delay_1 ((uint32_t)0x00002000) -#define FMC_ReadPipe_Delay_2 ((uint32_t)0x00004000) -#define FMC_ReadPipe_Delay_Mask ((uint32_t)0x00006000) - -/* - * FMC_Read_Burst - */ -#define FMC_Read_Burst_Disable ((uint32_t)0x00000000) -#define FMC_Read_Burst_Enable ((uint32_t)0x00001000) -#define FMC_Read_Burst_Mask ((uint32_t)0x00001000) - -/* - * FMC_SDClock_Period - */ -#define FMC_SDClock_Disable ((uint32_t)0x00000000) -#define FMC_SDClock_Period_2 ((uint32_t)0x00000800) -#define FMC_SDClock_Period_3 ((uint32_t)0x00000C00) -#define FMC_SDClock_Period_Mask ((uint32_t)0x00000C00) - -/* - * FMC_ColumnBits_Number - */ -#define FMC_ColumnBits_Number_8b ((uint32_t)0x00000000) -#define FMC_ColumnBits_Number_9b ((uint32_t)0x00000001) -#define FMC_ColumnBits_Number_10b ((uint32_t)0x00000002) -#define FMC_ColumnBits_Number_11b ((uint32_t)0x00000003) - -/* - * FMC_RowBits_Number - */ -#define FMC_RowBits_Number_11b ((uint32_t)0x00000000) -#define FMC_RowBits_Number_12b ((uint32_t)0x00000004) -#define FMC_RowBits_Number_13b ((uint32_t)0x00000008) - -/* - * FMC_SDMemory_Data_Width - */ -#define FMC_SDMemory_Width_8b ((uint32_t)0x00000000) -#define FMC_SDMemory_Width_16b ((uint32_t)0x00000010) -#define FMC_SDMemory_Width_32b ((uint32_t)0x00000020) - -/* - * FMC_InternalBank_Number - */ -#define FMC_InternalBank_Number_2 ((uint32_t)0x00000000) -#define FMC_InternalBank_Number_4 ((uint32_t)0x00000040) - -/* - * FMC_CAS_Latency - */ -#define FMC_CAS_Latency_1 ((uint32_t)0x00000080) -#define FMC_CAS_Latency_2 ((uint32_t)0x00000100) -#define FMC_CAS_Latency_3 ((uint32_t)0x00000180) - -/* - * FMC_Write_Protection - */ -#define FMC_Write_Protection_Disable ((uint32_t)0x00000000) -#define FMC_Write_Protection_Enable ((uint32_t)0x00000200) #define SDRAM_SIZE (8 * 1024 * 1024) #define SDRAM_START ((void *)FSMC_Bank6_MAP_BASE) -- cgit v1.2.3 From 915b474b02349add9c17fa43ff0351503c3c5020 Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Wed, 30 Oct 2019 12:52:31 +0100 Subject: Re-organised FSMC drivers --- .../RT-STM32F303-DISCOVERY-PID/mcuconf_community.h | 4 +- demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.cproject | 4 +- demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c | 4 +- .../mcuconf_community.h | 4 +- os/common/ext/CMSIS/KINETIS/MK66F18.h | 4 +- os/hal/hal.mk | 14 +- os/hal/include/fsmc/nand.h | 293 ---------- os/hal/include/fsmc/sdram.h | 252 --------- os/hal/include/fsmc/sram.h | 170 ------ os/hal/include/hal_community.h | 27 +- os/hal/include/hal_fsmc.h | 67 +-- os/hal/include/hal_sdram.h | 244 +++++++++ os/hal/include/hal_sram.h | 171 ++++++ os/hal/ports/STM32/LLD/FSMCv1/driver.mk | 18 +- os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.c | 590 -------------------- os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.h | 289 ---------- os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c | 172 ------ os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.h | 117 ---- os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.c | 124 ----- os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.h | 91 ---- os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c | 592 +++++++++++++++++++++ os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h | 290 ++++++++++ os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.c | 172 ++++++ os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h | 118 ++++ os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.c | 124 +++++ os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.h | 91 ++++ os/hal/src/hal_fsmc.c | 153 +----- os/hal/src/hal_sdram.c | 122 +++++ os/hal/src/hal_sram.c | 146 +++++ testhal/STM32/STM32F0xx/COMP/mcuconf_community.h | 4 +- testhal/STM32/STM32F0xx/crc/mcuconf_community.h | 4 +- .../STM32/STM32F0xx/onewire/mcuconf_community.h | 4 +- testhal/STM32/STM32F0xx/qei/mcuconf_community.h | 4 +- .../STM32/STM32F1xx/onewire/mcuconf_community.h | 4 +- testhal/STM32/STM32F1xx/qei/mcuconf_community.h | 4 +- testhal/STM32/STM32F3xx/COMP/mcuconf_community.h | 4 +- testhal/STM32/STM32F3xx/EEProm/mcuconf_community.h | 4 +- testhal/STM32/STM32F3xx/OPAMP/mcuconf_community.h | 4 +- testhal/STM32/STM32F3xx/TIMCAP/mcuconf_community.h | 4 +- testhal/STM32/STM32F4xx/EICU/mcuconf_community.h | 4 +- .../STM32/STM32F4xx/FSMC_NAND/halconf_community.h | 14 + testhal/STM32/STM32F4xx/FSMC_NAND/main.c | 4 +- .../STM32/STM32F4xx/FSMC_NAND/mcuconf_community.h | 18 +- .../STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h | 22 +- testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c | 4 +- .../STM32/STM32F4xx/FSMC_SDRAM/mcuconf_community.h | 24 +- .../STM32/STM32F4xx/FSMC_SRAM/halconf_community.h | 23 +- testhal/STM32/STM32F4xx/FSMC_SRAM/main.c | 4 +- .../STM32/STM32F4xx/FSMC_SRAM/mcuconf_community.h | 24 +- .../STM32/STM32F4xx/USB_HOST/mcuconf_community.h | 4 +- .../STM32/STM32F4xx/onewire/mcuconf_community.h | 4 +- .../STM32/STM32F7xx/USB_MSD/mcuconf_community.h | 4 +- testhal/STM32/STM32L0xx/COMP/mcuconf_community.h | 4 +- tools/templates/mcuconf_community.h | 4 +- 54 files changed, 2263 insertions(+), 2405 deletions(-) delete mode 100644 os/hal/include/fsmc/nand.h delete mode 100644 os/hal/include/fsmc/sdram.h delete mode 100644 os/hal/include/fsmc/sram.h create mode 100644 os/hal/include/hal_sdram.h create mode 100644 os/hal/include/hal_sram.h delete mode 100644 os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.c delete mode 100644 os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.h delete mode 100644 os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c delete mode 100644 os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.h delete mode 100644 os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.c delete mode 100644 os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.h create mode 100644 os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c create mode 100644 os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h create mode 100644 os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.c create mode 100644 os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h create mode 100644 os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.c create mode 100644 os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.h create mode 100644 os/hal/src/hal_sdram.c create mode 100644 os/hal/src/hal_sram.c diff --git a/demos/STM32/RT-STM32F303-DISCOVERY-PID/mcuconf_community.h b/demos/STM32/RT-STM32F303-DISCOVERY-PID/mcuconf_community.h index cf6a1ce..785529b 100644 --- a/demos/STM32/RT-STM32F303-DISCOVERY-PID/mcuconf_community.h +++ b/demos/STM32/RT-STM32F303-DISCOVERY-PID/mcuconf_community.h @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.cproject b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.cproject index a2a9791..ea4ffa9 100644 --- a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.cproject +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.cproject @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c index 25f42ab..55a66a5 100644 --- a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c @@ -556,8 +556,8 @@ int main(void) { /* * Initialise FSMC for SDRAM. */ - fsmcSdramInit(); - fsmcSdramStart(&SDRAMD, &sdram_cfg); + sdramInit(); + sdramStart(&SDRAMD, &sdram_cfg); sdram_bulk_erase(); /* diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf_community.h b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf_community.h index 36763de..6ecfe91 100644 --- a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf_community.h +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf_community.h @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE /* diff --git a/os/common/ext/CMSIS/KINETIS/MK66F18.h b/os/common/ext/CMSIS/KINETIS/MK66F18.h index 432944f..2fdfbbd 100644 --- a/os/common/ext/CMSIS/KINETIS/MK66F18.h +++ b/os/common/ext/CMSIS/KINETIS/MK66F18.h @@ -14379,7 +14379,7 @@ typedef struct { __IO uint32_t AC; /**< Address and Control Register, array offset: 0x48, array step: 0x8 */ __IO uint32_t CM; /**< Control Mask, array offset: 0x4C, array step: 0x8 */ } BLOCK[2]; -} SDRAM_TypeDef; +} FSMC_SDRAM_TypeDef; /* ---------------------------------------------------------------------------- -- SDRAM Register Masks @@ -14464,7 +14464,7 @@ typedef struct { /** Peripheral SDRAM base address */ #define SDRAM_BASE (0x4000F000u) /** Peripheral SDRAM base pointer */ -#define SDRAM ((SDRAM_TypeDef *)SDRAM_BASE) +#define SDRAM ((FSMC_SDRAM_TypeDef *)SDRAM_BASE) /** Array initializer of SDRAM peripheral base addresses */ #define SDRAM_BASE_ADDRS { SDRAM_BASE } /** Array initializer of SDRAM peripheral base pointers */ diff --git a/os/hal/hal.mk b/os/hal/hal.mk index 9908965..63c1fae 100644 --- a/os/hal/hal.mk +++ b/os/hal/hal.mk @@ -10,9 +10,18 @@ endif HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h $(CONFDIR)/halconf_community.h | egrep -e "\#define")) HALSRC_CONTRIB := ${CHIBIOS_CONTRIB}/os/hal/src/hal_community.c -ifneq ($(findstring HAL_USE_FSMC_SDRAM TRUE,$(HALCONF)), $(findstring HAL_USE_FSMC_SRAM TRUE,$(HALCONF)), $(findstring HAL_USE_FSMC_NAND TRUE,$(HALCONF))) +ifneq ($(findstring HAL_USE_FSMC TRUE,$(HALCONF)),) HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_fsmc.c endif +ifneq ($(findstring HAL_USE_NAND TRUE,$(HALCONF)),) +HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_nand.c +endif +ifneq ($(findstring HAL_USE_SRAM TRUE,$(HALCONF)),) +HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_sram.c +endif +ifneq ($(findstring HAL_USE_SDRAM TRUE,$(HALCONF)),) +HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_sdram.c +endif ifneq ($(findstring HAL_USE_ONEWIRE TRUE,$(HALCONF)),) HALSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/src/hal_onewire.c endif @@ -76,6 +85,9 @@ endif else HALSRC_CONTRIB := ${CHIBIOS_CONTRIB}/os/hal/src/hal_community.c \ ${CHIBIOS_CONTRIB}/os/hal/src/hal_fsmc.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/hal_nand.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/hal_sram.c \ + ${CHIBIOS_CONTRIB}/os/hal/src/hal_sdram.c \ ${CHIBIOS_CONTRIB}/os/hal/src/hal_onewire.c \ ${CHIBIOS_CONTRIB}/os/hal/src/hal_eicu.c \ ${CHIBIOS_CONTRIB}/os/hal/src/hal_crc.c \ diff --git a/os/hal/include/fsmc/nand.h b/os/hal/include/fsmc/nand.h deleted file mode 100644 index b2d9001..0000000 --- a/os/hal/include/fsmc/nand.h +++ /dev/null @@ -1,293 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_nand_lld.h - * @brief NAND Driver subsystem low level driver header. - * - * @addtogroup NAND - * @{ - */ - -#ifndef NAND_H_ -#define NAND_H_ - -#include "bitmap.h" - -#if (HAL_USE_FSMC_NAND == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ -#define NAND_MIN_PAGE_SIZE 256 -#define NAND_MAX_PAGE_SIZE 8192 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief FSMC1 interrupt priority level setting. - */ -#if !defined(STM32_EMC_FSMC1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EMC_FSMC1_IRQ_PRIORITY 10 -#endif - -/** - * @brief NAND driver enable switch. - * @details If set to @p TRUE the support for NAND1 is included. - */ -#if !defined(STM32_FSMC_USE_NAND1) || defined(__DOXYGEN__) -#define STM32_FSMC_USE_NAND1 FALSE -#endif - -/** - * @brief NAND driver enable switch. - * @details If set to @p TRUE the support for NAND2 is included. - */ -#if !defined(STM32_FSMC_USE_NAND2) || defined(__DOXYGEN__) -#define STM32_FSMC_USE_NAND2 FALSE -#endif - -/** - * @brief NAND DMA error hook. - * @note The default action for DMA errors is a system halt because DMA - * error can only happen because programming errors. - */ -#if !defined(STM32_NAND_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure") -#endif - -/** - * @brief NAND interrupt enable switch. - * @details If set to @p TRUE the support for internal FSMC interrupt included. - */ -#if !defined(STM32_NAND_USE_INT) || defined(__DOXYGEN__) -#define STM32_NAND_USE_INT FALSE -#endif - -/** -* @brief NAND1 DMA priority (0..3|lowest..highest). -*/ -#if !defined(STM32_NAND_NAND1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_NAND_NAND1_DMA_PRIORITY 0 -#endif - -/** -* @brief NAND2 DMA priority (0..3|lowest..highest). -*/ -#if !defined(STM32_NAND_NAND2_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_NAND_NAND2_DMA_PRIORITY 0 -#endif - -/** - * @brief DMA stream used for NAND operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_NAND_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) -#endif - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !STM32_FSMC_USE_NAND1 && !STM32_FSMC_USE_NAND2 -#error "NAND driver activated but no NAND peripheral assigned" -#endif - -#if (STM32_FSMC_USE_NAND1 || STM32_FSMC_USE_NAND2) && !STM32_HAS_FSMC -#error "FSMC not present in the selected device" -#endif - -#if !defined(STM32_DMA_REQUIRED) -#define STM32_DMA_REQUIRED -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a structure representing an NAND driver. - */ -typedef struct NANDDriver NANDDriver; - -/** - * @brief Type of interrupt handler function. - */ -typedef void (*nandisrhandler_t)(NANDDriver *nandp); - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief Number of erase blocks in NAND device. - */ - uint32_t blocks; - /** - * @brief Number of data bytes in page. - */ - uint32_t page_data_size; - /** - * @brief Number of spare bytes in page. - */ - uint32_t page_spare_size; - /** - * @brief Number of pages in block. - */ - uint32_t pages_per_block; - /** - * @brief Number of write cycles for row addressing. - */ - uint8_t rowcycles; - /** - * @brief Number of write cycles for column addressing. - */ - uint8_t colcycles; - - /* End of the mandatory fields.*/ - /** - * @brief Number of wait cycles. This value will be used both for - * PMEM and PATTR registers - * - * @note For proper calculation procedure please look at AN2784 document - * from STMicroelectronics. - */ - uint32_t pmem; -} NANDConfig; - -/** - * @brief Structure representing an NAND driver. - */ -struct NANDDriver { - /** - * @brief Driver state. - */ - nandstate_t state; - /** - * @brief Current configuration data. - */ - const NANDConfig *config; - /** - * @brief Array to store bad block map. - */ -#if NAND_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) -#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the bus. - */ - mutex_t mutex; -#elif CH_CFG_USE_SEMAPHORES - semaphore_t semaphore; -#endif -#endif /* NAND_USE_MUTUAL_EXCLUSION */ - /* End of the mandatory fields.*/ - /** - * @brief Function enabling interrupts from FSMC. - */ - nandisrhandler_t isr_handler; - /** - * @brief Pointer to current transaction buffer. - */ - void *rxdata; - /** - * @brief Current transaction length in bytes. - */ - size_t datalen; - /** - * @brief DMA mode bit mask. - */ - uint32_t dmamode; - /** - * @brief DMA channel. - */ - const stm32_dma_stream_t *dma; - /** - * @brief Thread waiting for I/O completion. - */ - thread_t *thread; - /** - * @brief Pointer to the FSMC NAND registers block. - */ - FSMC_NAND_TypeDef *nand; - /** - * @brief Memory mapping for data. - */ - uint16_t *map_data; - /** - * @brief Memory mapping for commands. - */ - uint16_t *map_cmd; - /** - * @brief Memory mapping for addresses. - */ - uint16_t *map_addr; - /** - * @brief Pointer to bad block map. - * @details One bit per block. All memory allocation is user's responsibility. - */ - bitmap_t *bb_map; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_FSMC_USE_NAND1 && !defined(__DOXYGEN__) -extern NANDDriver NANDD1; -#endif - -#if STM32_FSMC_USE_NAND2 && !defined(__DOXYGEN__) -extern NANDDriver NANDD2; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void nand_lld_init(void); - void nand_lld_start(NANDDriver *nandp); - void nand_lld_stop(NANDDriver *nandp); - uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen); - void nand_lld_read_data(NANDDriver *nandp, uint16_t *data, - size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc); - void nand_lld_write_addr(NANDDriver *nandp, const uint8_t *addr, size_t len); - void nand_lld_write_cmd(NANDDriver *nandp, uint8_t cmd); - uint8_t nand_lld_write_data(NANDDriver *nandp, const uint16_t *data, - size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc); - uint8_t nand_lld_read_status(NANDDriver *nandp); - void nand_lld_reset(NANDDriver *nandp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_FSMC_NAND */ - -#endif /* NAND_H_ */ - -/** @} */ diff --git a/os/hal/include/fsmc/sdram.h b/os/hal/include/fsmc/sdram.h deleted file mode 100644 index 7a04bdc..0000000 --- a/os/hal/include/fsmc/sdram.h +++ /dev/null @@ -1,252 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - SDRAM routines added by Nick Klimov aka progfin. - */ - -/** - * @file hal_fsmc_sdram.h - * @brief SDRAM Driver subsystem low level driver header. - * - * @addtogroup SDRAM - * @{ - */ - -#ifndef SDRAM_H_ -#define SDRAM_H_ - -#if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F745xx) || defined(STM32F746xx) || \ - defined(STM32F756xx) || defined(STM32F767xx) || \ - defined(STM32F769xx) || defined(STM32F777xx) || \ - defined(STM32F779xx)) - -#if (HAL_USE_FSMC_SDRAM == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/* - * FMC SDRAM Mode definition register defines - */ -#define FMC_SDCMR_MRD_BURST_LENGTH_1 ((uint16_t)0x0000) -#define FMC_SDCMR_MRD_BURST_LENGTH_2 ((uint16_t)0x0001) -#define FMC_SDCMR_MRD_BURST_LENGTH_4 ((uint16_t)0x0002) -#define FMC_SDCMR_MRD_BURST_LENGTH_8 ((uint16_t)0x0004) -#define FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) -#define FMC_SDCMR_MRD_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) -#define FMC_SDCMR_MRD_CAS_LATENCY_2 ((uint16_t)0x0020) -#define FMC_SDCMR_MRD_CAS_LATENCY_3 ((uint16_t)0x0030) -#define FMC_SDCMR_MRD_OPERATING_MODE_STANDARD ((uint16_t)0x0000) -#define FMC_SDCMR_MRD_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) -#define FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) - -/* - * FMC_ReadPipe_Delay - */ -#define FMC_ReadPipe_Delay_0 ((uint32_t)0x00000000) -#define FMC_ReadPipe_Delay_1 ((uint32_t)0x00002000) -#define FMC_ReadPipe_Delay_2 ((uint32_t)0x00004000) -#define FMC_ReadPipe_Delay_Mask ((uint32_t)0x00006000) - -/* - * FMC_Read_Burst - */ -#define FMC_Read_Burst_Disable ((uint32_t)0x00000000) -#define FMC_Read_Burst_Enable ((uint32_t)0x00001000) -#define FMC_Read_Burst_Mask ((uint32_t)0x00001000) - -/* - * FMC_SDClock_Period - */ -#define FMC_SDClock_Disable ((uint32_t)0x00000000) -#define FMC_SDClock_Period_2 ((uint32_t)0x00000800) -#define FMC_SDClock_Period_3 ((uint32_t)0x00000C00) -#define FMC_SDClock_Period_Mask ((uint32_t)0x00000C00) - -/* - * FMC_ColumnBits_Number - */ -#define FMC_ColumnBits_Number_8b ((uint32_t)0x00000000) -#define FMC_ColumnBits_Number_9b ((uint32_t)0x00000001) -#define FMC_ColumnBits_Number_10b ((uint32_t)0x00000002) -#define FMC_ColumnBits_Number_11b ((uint32_t)0x00000003) - -/* - * FMC_RowBits_Number - */ -#define FMC_RowBits_Number_11b ((uint32_t)0x00000000) -#define FMC_RowBits_Number_12b ((uint32_t)0x00000004) -#define FMC_RowBits_Number_13b ((uint32_t)0x00000008) - -/* - * FMC_SDMemory_Data_Width - */ -#define FMC_SDMemory_Width_8b ((uint32_t)0x00000000) -#define FMC_SDMemory_Width_16b ((uint32_t)0x00000010) -#define FMC_SDMemory_Width_32b ((uint32_t)0x00000020) - -/* - * FMC_InternalBank_Number - */ -#define FMC_InternalBank_Number_2 ((uint32_t)0x00000000) -#define FMC_InternalBank_Number_4 ((uint32_t)0x00000040) - -/* - * FMC_CAS_Latency - */ -#define FMC_CAS_Latency_1 ((uint32_t)0x00000080) -#define FMC_CAS_Latency_2 ((uint32_t)0x00000100) -#define FMC_CAS_Latency_3 ((uint32_t)0x00000180) - -/* - * FMC_Write_Protection - */ -#define FMC_Write_Protection_Disable ((uint32_t)0x00000000) -#define FMC_Write_Protection_Enable ((uint32_t)0x00000200) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ -/** - * @name Configuration options - * @{ - */ - -/** - * @brief SDRAM driver enable switch. - * @details If set to @p TRUE the support for SDRAM1 is included. - */ -#if !defined(STM32_FSMC_USE_SDRAM1) || defined(__DOXYGEN__) -#define STM32_FSMC_USE_SDRAM1 FALSE -#else -#define STM32_SDRAM1_MAP_BASE FSMC_Bank5_MAP_BASE -#endif - -/** - * @brief SDRAM driver enable switch. - * @details If set to @p TRUE the support for SDRAM2 is included. - */ -#if !defined(STM32_FSMC_USE_SDRAM2) || defined(__DOXYGEN__) -#define STM32_FSMC_USE_SDRAM2 FALSE -#else -#define STM32_SDRAM2_MAP_BASE FSMC_Bank6_MAP_BASE -#endif - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !STM32_FSMC_USE_SDRAM1 && !STM32_FSMC_USE_SDRAM2 -#error "SDRAM driver activated but no SDRAM peripheral assigned" -#endif - -#if (STM32_FSMC_USE_SDRAM1 || STM32_FSMC_USE_SDRAM2) && !STM32_HAS_FSMC -#error "FMC not present in the selected device" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ -/** - * @brief Driver state machine possible states. - */ -typedef enum { - SDRAM_UNINIT = 0, /**< Not initialized. */ - SDRAM_STOP = 1, /**< Stopped. */ - SDRAM_READY = 2, /**< Ready. */ -} sdramstate_t; - -/** - * @brief Type of a structure representing an SDRAM driver. - */ -typedef struct SDRAMDriver SDRAMDriver; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief SDRAM control register. - * @note Its value will be used for both banks. - */ - uint32_t sdcr; - - /** - * @brief SDRAM timing register. - * @note Its value will be used for both banks. - */ - uint32_t sdtr; - - /** - * @brief SDRAM command mode register. - * @note Only its MRD and NRFS bits will be used. - */ - uint32_t sdcmr; - - /** - * @brief SDRAM refresh timer register. - * @note Only its COUNT bits will be used. - */ - uint32_t sdrtr; -} SDRAMConfig; - -/** - * @brief Structure representing an SDRAM driver. - */ -struct SDRAMDriver { - /** - * @brief Driver state. - */ - sdramstate_t state; - /** - * @brief Pointer to the FMC SDRAM registers block. - */ - FSMC_SDRAM_TypeDef *sdram; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -extern SDRAMDriver SDRAMD; - -#ifdef __cplusplus -extern "C" { -#endif - void fsmcSdramInit(void); - void fsmcSdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp); - void fsmcSdramStop(SDRAMDriver *sdramp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_FSMC_SDRAM */ - -#endif /* STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx */ - -#endif /* SDRAM_H_ */ - -/** @} */ diff --git a/os/hal/include/fsmc/sram.h b/os/hal/include/fsmc/sram.h deleted file mode 100644 index 4a19246..0000000 --- a/os/hal/include/fsmc/sram.h +++ /dev/null @@ -1,170 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_fsmc_sram.h - * @brief SRAM Driver subsystem low level driver header. - * - * @addtogroup SRAM - * @{ - */ - -#ifndef SRAM_H_ -#define SRAM_H_ - -#if (HAL_USE_FSMC_SRAM == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ -/** - * @name Configuration options - * @{ - */ - -/** - * @brief SRAM driver enable switch. - * @details If set to @p TRUE the support for SRAM1 is included. - */ -#if !defined(STM32_FSMC_USE_SRAM1) || defined(__DOXYGEN__) -#define STM32_FSMC_USE_SRAM1 FALSE -#endif - -/** - * @brief SRAM driver enable switch. - * @details If set to @p TRUE the support for SRAM2 is included. - */ -#if !defined(STM32_FSMC_USE_SRAM2) || defined(__DOXYGEN__) -#define STM32_FSMC_USE_SRAM2 FALSE -#endif - -/** - * @brief SRAM driver enable switch. - * @details If set to @p TRUE the support for SRAM3 is included. - */ -#if !defined(STM32_FSMC_USE_SRAM3) || defined(__DOXYGEN__) -#define STM32_FSMC_USE_SRAM3 FALSE -#endif - -/** - * @brief SRAM driver enable switch. - * @details If set to @p TRUE the support for SRAM4 is included. - */ -#if !defined(STM32_FSMC_USE_SRAM4) || defined(__DOXYGEN__) -#define STM32_FSMC_USE_SRAM4 FALSE -#endif - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !STM32_FSMC_USE_SRAM1 && !STM32_FSMC_USE_SRAM2 && \ - !STM32_FSMC_USE_SRAM3 && !STM32_FSMC_USE_SRAM4 -#error "SRAM driver activated but no SRAM peripheral assigned" -#endif - -#if (STM32_FSMC_USE_SRAM1 || STM32_FSMC_USE_SRAM2 || \ - STM32_FSMC_USE_SRAM3 || STM32_FSMC_USE_SRAM4) && !STM32_HAS_FSMC -#error "FSMC not present in the selected device" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ -/** - * @brief Driver state machine possible states. - */ -typedef enum { - SRAM_UNINIT = 0, /**< Not initialized. */ - SRAM_STOP = 1, /**< Stopped. */ - SRAM_READY = 2, /**< Ready. */ -} sramstate_t; - -/** - * @brief Type of a structure representing an NAND driver. - */ -typedef struct SRAMDriver SRAMDriver; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - * @note Some bits in BCR register will be forced by driver. - */ -typedef struct { - uint32_t bcr; - uint32_t btr; - uint32_t bwtr; -} SRAMConfig; - -/** - * @brief Structure representing an NAND driver. - */ -struct SRAMDriver { - /** - * @brief Driver state. - */ - sramstate_t state; - /** - * @brief Pointer to the FSMC SRAM registers block. - */ - FSMC_SRAM_NOR_TypeDef *sram; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_FSMC_USE_SRAM1 && !defined(__DOXYGEN__) -extern SRAMDriver SRAMD1; -#endif - -#if STM32_FSMC_USE_SRAM2 && !defined(__DOXYGEN__) -extern SRAMDriver SRAMD2; -#endif - -#if STM32_FSMC_USE_SRAM3 && !defined(__DOXYGEN__) -extern SRAMDriver SRAMD3; -#endif - -#if STM32_FSMC_USE_SRAM4 && !defined(__DOXYGEN__) -extern SRAMDriver SRAMD4; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void fsmcSramInit(void); - void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp); - void fsmcSramStop(SRAMDriver *sramp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_FSMC_SRAM */ - -#endif /* SRAM_H_ */ - -/** @} */ diff --git a/os/hal/include/hal_community.h b/os/hal/include/hal_community.h index ad5c472..889da4f 100644 --- a/os/hal/include/hal_community.h +++ b/os/hal/include/hal_community.h @@ -27,6 +27,10 @@ /* Error checks on the configuration header file.*/ +#if !defined(HAL_USE_COMP) +#define HAL_USE_COMP FALSE +#endif + #if !defined(HAL_USE_CRC) #define HAL_USE_CRC FALSE #endif @@ -39,6 +43,10 @@ #define HAL_USE_EICU FALSE #endif +#if !defined(HAL_USE_FSMC) +#define HAL_USE_FSMC FALSE +#endif + #if !defined(HAL_USE_NAND) #define HAL_USE_NAND FALSE #endif @@ -47,6 +55,10 @@ #define HAL_USE_ONEWIRE FALSE #endif +#if !defined(HAL_USE_OPAMP) +#define HAL_USE_OPAMP FALSE +#endif + #if !defined(HAL_USE_QEI) #define HAL_USE_QEI FALSE #endif @@ -71,15 +83,11 @@ #define HAL_USE_USB_MSD FALSE #endif -#if !defined(HAL_USE_COMP) -#define HAL_USE_COMP FALSE -#endif - -#if !defined(HAL_USE_OPAMP) -#define HAL_USE_OPAMP FALSE +#if !defined(HAL_USE_SDRAM) +#define HAL_USE_FSMC FALSE #endif -#if !defined(HAL_USE_FSMC) +#if !defined(HAL_USE_SRAM) #define HAL_USE_FSMC FALSE #endif @@ -96,6 +104,7 @@ #include "hal_qei.h" #include "hal_comp.h" #include "hal_opamp.h" +#include "hal_fsmc.h" /* Complex drivers.*/ #include "hal_onewire.h" @@ -103,7 +112,9 @@ #include "hal_eeprom.h" #include "hal_usb_hid.h" #include "hal_usb_msd.h" -#include "hal_fsmc.h" +#include "hal_nand.h" +#include "hal_sram.h" +#include "hal_sdram.h" /*===========================================================================*/ /* Driver constants. */ diff --git a/os/hal/include/hal_fsmc.h b/os/hal/include/hal_fsmc.h index 834fa8d..3b27941 100644 --- a/os/hal/include/hal_fsmc.h +++ b/os/hal/include/hal_fsmc.h @@ -27,7 +27,7 @@ #include "hal.h" -#if (HAL_USE_FSMC_SDRAM == TRUE) || (HAL_USE_FSMC_SRAM == TRUE) || (HAL_USE_FSMC_NAND == TRUE) || defined(__DOXYGEN__) +#if (HAL_USE_FSMC == TRUE) || defined(__DOXYGEN__) /*===========================================================================*/ /* Driver constants. */ @@ -161,7 +161,7 @@ typedef struct { __IO uint32_t BTR; /**< SRAM/NOR chip-select timing registers */ uint32_t RESERVED[63]; /**< Reserved */ __IO uint32_t BWTR; /**< SRAM/NOR write timing registers */ -} FSMC_SRAM_NOR_TypeDef; +} FSMC_SRAM_TypeDef; #if (defined(STM32F427xx) || defined(STM32F437xx) || \ defined(STM32F429xx) || defined(STM32F439xx) || \ @@ -264,31 +264,6 @@ typedef struct { #define STM32_FSMC_USE_FSMC1 FALSE #endif -/** - * @brief SDRAM driver enable switch. - * @details If set to @p TRUE the support for SDRAM is included. - */ -#if !defined(HAL_USE_FSMC_SDRAM) || defined(__DOXYGEN__) -#define HAL_USE_FSMC_SDRAM FALSE -#endif - -/** - * @brief SRAM driver enable switch. - * @details If set to @p TRUE the support for SRAM is included. - */ -#if !defined(HAL_USE_FSMC_SRAM) || defined(__DOXYGEN__) -#define HAL_USE_FSMC_SRAM FALSE -#endif - -/** - * @brief NAND driver enable switch. - * @details If set to @p TRUE the support for NAND is included. - */ -#if !defined(HAL_USE_FSMC_NAND) || defined(__DOXYGEN__) -#define HAL_USE_FSMC_NAND FALSE -#endif - - /** @} */ /*===========================================================================*/ @@ -326,26 +301,26 @@ struct FSMCDriver { fsmcstate_t state; /* End of the mandatory fields.*/ -#if HAL_USE_FSMC_SRAM - #if STM32_FSMC_USE_SRAM1 - FSMC_SRAM_NOR_TypeDef *sram1; +#if HAL_USE_SRAM + #if STM32_SRAM_USE_SRAM1 + FSMC_SRAM_TypeDef *sram1; #endif - #if STM32_FSMC_USE_SRAM2 - FSMC_SRAM_NOR_TypeDef *sram2; + #if STM32_SRAM_USE_SRAM2 + FSMC_SRAM_TypeDef *sram2; #endif - #if STM32_FSMC_USE_SRAM3 - FSMC_SRAM_NOR_TypeDef *sram3; + #if STM32_SRAM_USE_SRAM3 + FSMC_SRAM_TypeDef *sram3; #endif - #if STM32_FSMC_USE_SRAM4 - FSMC_SRAM_NOR_TypeDef *sram4; + #if STM32_SRAM_USE_SRAM4 + FSMC_SRAM_TypeDef *sram4; #endif #endif -#if HAL_USE_FSMC_NAND - #if STM32_FSMC_USE_NAND1 +#if HAL_USE_NAND + #if STM32_NAND_USE_NAND1 FSMC_NAND_TypeDef *nand1; #endif - #if STM32_FSMC_USE_NAND1 + #if STM32_NAND_USE_NAND1 FSMC_NAND_TypeDef *nand2; #endif #endif @@ -353,7 +328,7 @@ struct FSMCDriver { #if (defined(STM32F427xx) || defined(STM32F437xx) || \ defined(STM32F429xx) || defined(STM32F439xx) || \ defined(STM32F7)) - #if HAL_USE_FSMC_SDRAM + #if HAL_USE_SDRAM FSMC_SDRAM_TypeDef *sdram; #endif #endif @@ -381,18 +356,6 @@ extern "C" { } #endif -#if HAL_USE_FSMC_SDRAM == TRUE -#include "fsmc/sdram.h" -#endif - -#if HAL_USE_FSMC_SRAM == TRUE -#include "fsmc/sram.h" -#endif - -#if HAL_USE_FSMC_NAND == TRUE -#include "fsmc/nand.h" -#endif - #endif /* HAL_USE_FSMC */ #endif /* HAL_FSMC_H_ */ diff --git a/os/hal/include/hal_sdram.h b/os/hal/include/hal_sdram.h new file mode 100644 index 0000000..297b715 --- /dev/null +++ b/os/hal/include/hal_sdram.h @@ -0,0 +1,244 @@ +/* + ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + SDRAM routines added by Nick Klimov aka progfin. + */ + +/** + * @file hal_fsmc_sdram.h + * @brief SDRAM Driver subsystem low level driver header. + * + * @addtogroup SDRAM + * @{ + */ + +#ifndef HAL_SDRAM_H_ +#define HAL_SDRAM_H_ + +#if (HAL_USE_SDRAM == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/* + * FMC SDRAM Mode definition register defines + */ +#define FMC_SDCMR_MRD_BURST_LENGTH_1 ((uint16_t)0x0000) +#define FMC_SDCMR_MRD_BURST_LENGTH_2 ((uint16_t)0x0001) +#define FMC_SDCMR_MRD_BURST_LENGTH_4 ((uint16_t)0x0002) +#define FMC_SDCMR_MRD_BURST_LENGTH_8 ((uint16_t)0x0004) +#define FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000) +#define FMC_SDCMR_MRD_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008) +#define FMC_SDCMR_MRD_CAS_LATENCY_2 ((uint16_t)0x0020) +#define FMC_SDCMR_MRD_CAS_LATENCY_3 ((uint16_t)0x0030) +#define FMC_SDCMR_MRD_OPERATING_MODE_STANDARD ((uint16_t)0x0000) +#define FMC_SDCMR_MRD_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000) +#define FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200) + +/* + * FMC_ReadPipe_Delay + */ +#define FMC_ReadPipe_Delay_0 ((uint32_t)0x00000000) +#define FMC_ReadPipe_Delay_1 ((uint32_t)0x00002000) +#define FMC_ReadPipe_Delay_2 ((uint32_t)0x00004000) +#define FMC_ReadPipe_Delay_Mask ((uint32_t)0x00006000) + +/* + * FMC_Read_Burst + */ +#define FMC_Read_Burst_Disable ((uint32_t)0x00000000) +#define FMC_Read_Burst_Enable ((uint32_t)0x00001000) +#define FMC_Read_Burst_Mask ((uint32_t)0x00001000) + +/* + * FMC_SDClock_Period + */ +#define FMC_SDClock_Disable ((uint32_t)0x00000000) +#define FMC_SDClock_Period_2 ((uint32_t)0x00000800) +#define FMC_SDClock_Period_3 ((uint32_t)0x00000C00) +#define FMC_SDClock_Period_Mask ((uint32_t)0x00000C00) + +/* + * FMC_ColumnBits_Number + */ +#define FMC_ColumnBits_Number_8b ((uint32_t)0x00000000) +#define FMC_ColumnBits_Number_9b ((uint32_t)0x00000001) +#define FMC_ColumnBits_Number_10b ((uint32_t)0x00000002) +#define FMC_ColumnBits_Number_11b ((uint32_t)0x00000003) + +/* + * FMC_RowBits_Number + */ +#define FMC_RowBits_Number_11b ((uint32_t)0x00000000) +#define FMC_RowBits_Number_12b ((uint32_t)0x00000004) +#define FMC_RowBits_Number_13b ((uint32_t)0x00000008) + +/* + * FMC_SDMemory_Data_Width + */ +#define FMC_SDMemory_Width_8b ((uint32_t)0x00000000) +#define FMC_SDMemory_Width_16b ((uint32_t)0x00000010) +#define FMC_SDMemory_Width_32b ((uint32_t)0x00000020) + +/* + * FMC_InternalBank_Number + */ +#define FMC_InternalBank_Number_2 ((uint32_t)0x00000000) +#define FMC_InternalBank_Number_4 ((uint32_t)0x00000040) + +/* + * FMC_CAS_Latency + */ +#define FMC_CAS_Latency_1 ((uint32_t)0x00000080) +#define FMC_CAS_Latency_2 ((uint32_t)0x00000100) +#define FMC_CAS_Latency_3 ((uint32_t)0x00000180) + +/* + * FMC_Write_Protection + */ +#define FMC_Write_Protection_Disable ((uint32_t)0x00000000) +#define FMC_Write_Protection_Enable ((uint32_t)0x00000200) + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ + +/** + * @brief SDRAM driver enable switch. + * @details If set to @p TRUE the support for SDRAM1 is included. + */ +#if !defined(STM32_SDRAM_USE_SDRAM1) || defined(__DOXYGEN__) +#define STM32_SDRAM_USE_SDRAM1 FALSE +#else +#define STM32_SDRAM1_MAP_BASE FSMC_Bank5_MAP_BASE +#endif + +/** + * @brief SDRAM driver enable switch. + * @details If set to @p TRUE the support for SDRAM2 is included. + */ +#if !defined(STM32_SDRAM_USE_SDRAM2) || defined(__DOXYGEN__) +#define STM32_SDRAM_USE_SDRAM2 FALSE +#else +#define STM32_SDRAM2_MAP_BASE FSMC_Bank6_MAP_BASE +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !STM32_SDRAM_USE_SDRAM1 && !STM32_SDRAM_USE_SDRAM2 +#error "SDRAM driver activated but no SDRAM peripheral assigned" +#endif + +#if (STM32_SDRAM_USE_SDRAM1 || STM32_SDRAM_USE_SDRAM2) && !STM32_HAS_FSMC +#error "FMC not present in the selected device" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ +/** + * @brief Driver state machine possible states. + */ +typedef enum { + SDRAM_UNINIT = 0, /**< Not initialized. */ + SDRAM_STOP = 1, /**< Stopped. */ + SDRAM_READY = 2, /**< Ready. */ +} sdramstate_t; + +/** + * @brief Type of a structure representing an SDRAM driver. + */ +typedef struct SDRAMDriver SDRAMDriver; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief SDRAM control register. + * @note Its value will be used for both banks. + */ + uint32_t sdcr; + + /** + * @brief SDRAM timing register. + * @note Its value will be used for both banks. + */ + uint32_t sdtr; + + /** + * @brief SDRAM command mode register. + * @note Only its MRD and NRFS bits will be used. + */ + uint32_t sdcmr; + + /** + * @brief SDRAM refresh timer register. + * @note Only its COUNT bits will be used. + */ + uint32_t sdrtr; +} SDRAMConfig; + +/** + * @brief Structure representing an SDRAM driver. + */ +struct SDRAMDriver { + /** + * @brief Driver state. + */ + sdramstate_t state; + /** + * @brief Pointer to the FMC SDRAM registers block. + */ + FSMC_SDRAM_TypeDef *sdram; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +extern SDRAMDriver SDRAMD1; + +#ifdef __cplusplus +extern "C" { +#endif + void sdramInit(void); + void sdramObjectInit(SDRAMDriver *sdramp); + void sdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp); + void sdramStop(SDRAMDriver *sdramp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SDRAM */ + +#endif /* SDRAM_H_ */ + +/** @} */ diff --git a/os/hal/include/hal_sram.h b/os/hal/include/hal_sram.h new file mode 100644 index 0000000..bcf362a --- /dev/null +++ b/os/hal/include/hal_sram.h @@ -0,0 +1,171 @@ +/* + ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_fsmc_sram.h + * @brief SRAM Driver subsystem low level driver header. + * + * @addtogroup SRAM + * @{ + */ + +#ifndef HAL_SRAM_H_ +#define HAL_SRAM_H_ + +#if (HAL_USE_SRAM == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ + +/** + * @brief SRAM driver enable switch. + * @details If set to @p TRUE the support for SRAM1 is included. + */ +#if !defined(STM32_SRAM_USE_SRAM1) || defined(__DOXYGEN__) +#define STM32_SRAM_USE_SRAM1 FALSE +#endif + +/** + * @brief SRAM driver enable switch. + * @details If set to @p TRUE the support for SRAM2 is included. + */ +#if !defined(STM32_SRAM_USE_SRAM2) || defined(__DOXYGEN__) +#define STM32_SRAM_USE_SRAM2 FALSE +#endif + +/** + * @brief SRAM driver enable switch. + * @details If set to @p TRUE the support for SRAM3 is included. + */ +#if !defined(STM32_SRAM_USE_SRAM3) || defined(__DOXYGEN__) +#define STM32_SRAM_USE_SRAM3 FALSE +#endif + +/** + * @brief SRAM driver enable switch. + * @details If set to @p TRUE the support for SRAM4 is included. + */ +#if !defined(STM32_SRAM_USE_SRAM4) || defined(__DOXYGEN__) +#define STM32_SRAM_USE_SRAM4 FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !STM32_SRAM_USE_SRAM1 && !STM32_SRAM_USE_SRAM2 && \ + !STM32_SRAM_USE_SRAM3 && !STM32_SRAM_USE_SRAM4 +#error "SRAM driver activated but no SRAM peripheral assigned" +#endif + +#if (STM32_SRAM_USE_SRAM1 || STM32_SRAM_USE_SRAM2 || \ + STM32_SRAM_USE_SRAM3 || STM32_SRAM_USE_SRAM4) && !STM32_HAS_FSMC +#error "FSMC not present in the selected device" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ +/** + * @brief Driver state machine possible states. + */ +typedef enum { + SRAM_UNINIT = 0, /**< Not initialized. */ + SRAM_STOP = 1, /**< Stopped. */ + SRAM_READY = 2, /**< Ready. */ +} sramstate_t; + +/** + * @brief Type of a structure representing an NAND driver. + */ +typedef struct SRAMDriver SRAMDriver; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + * @note Some bits in BCR register will be forced by driver. + */ +typedef struct { + uint32_t bcr; + uint32_t btr; + uint32_t bwtr; +} SRAMConfig; + +/** + * @brief Structure representing an NAND driver. + */ +struct SRAMDriver { + /** + * @brief Driver state. + */ + sramstate_t state; + /** + * @brief Pointer to the FSMC SRAM registers block. + */ + FSMC_SRAM_TypeDef *sram; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_SRAM_USE_SRAM1 && !defined(__DOXYGEN__) +extern SRAMDriver SRAMD1; +#endif + +#if STM32_SRAM_USE_SRAM2 && !defined(__DOXYGEN__) +extern SRAMDriver SRAMD2; +#endif + +#if STM32_SRAM_USE_SRAM3 && !defined(__DOXYGEN__) +extern SRAMDriver SRAMD3; +#endif + +#if STM32_SRAM_USE_SRAM4 && !defined(__DOXYGEN__) +extern SRAMDriver SRAMD4; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sramInit(void); + void sramObjectInit(SRAMDriver *sdramp); + void sramStart(SRAMDriver *sramp, const SRAMConfig *cfgp); + void sramStop(SRAMDriver *sramp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SRAM */ + +#endif /* HAL_SRAM_H_ */ + +/** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/driver.mk b/os/hal/ports/STM32/LLD/FSMCv1/driver.mk index cffa3f7..8c354a5 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/driver.mk +++ b/os/hal/ports/STM32/LLD/FSMCv1/driver.mk @@ -1,17 +1,17 @@ ifeq ($(USE_SMART_BUILD),yes) -ifneq ($(findstring HAL_USE_FSMC_SDRAM TRUE,$(HALCONF)),) -PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c +ifneq ($(findstring HAL_USE_SDRAM TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.c endif -ifneq ($(findstring HAL_USE_FSMC_SRAM TRUE,$(HALCONF)),) -PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.c +ifneq ($(findstring HAL_USE_SRAM TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.c endif -ifneq ($(findstring HAL_USE_FSMC_NAND TRUE,$(HALCONF)),) -PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.c +ifneq ($(findstring HAL_USE_NAND TRUE,$(HALCONF)),) +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c endif else -PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.c +PLATFORMSRC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c endif PLATFORMINC_CONTRIB += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1 diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.c deleted file mode 100644 index 895fd28..0000000 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.c +++ /dev/null @@ -1,590 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_fsmc_nand_lld.c - * @brief FSMC NAND Driver subsystem low level driver source. - * - * @addtogroup NAND - * @{ - */ - -#include "hal.h" - -#if (HAL_USE_FSMC_NAND == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ -#define NAND_DMA_CHANNEL \ - STM32_DMA_GETCHANNEL(STM32_NAND_DMA_STREAM, \ - STM32_FSMC_DMA_CHN) - -/** - * @brief Bus width of NAND IC. - * @details Must be 8 or 16 - */ -#if ! defined(STM32_NAND_BUS_WIDTH) || defined(__DOXYGEN__) -#define STM32_NAND_BUS_WIDTH 8 -#endif - -/** - * @brief DMA transaction width on AHB bus in bytes - */ -#define AHB_TRANSACTION_WIDTH 2 - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief NAND1 driver identifier. - */ -#if STM32_NAND_USE_FSMC_NAND1 || defined(__DOXYGEN__) -NANDDriver NANDD1; -#endif - -/** - * @brief NAND2 driver identifier. - */ -#if STM32_NAND_USE_FSMC_NAND2 || defined(__DOXYGEN__) -NANDDriver NANDD2; -#endif - -/*===========================================================================*/ -/* Driver local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Helper function. - * - * @notapi - */ -static void align_check(const void *ptr, uint32_t len) { - osalDbgCheck((((uint32_t)ptr % AHB_TRANSACTION_WIDTH) == 0) && - ((len % AHB_TRANSACTION_WIDTH) == 0) && - (len >= AHB_TRANSACTION_WIDTH)); - (void)ptr; - (void)len; -} - -/** - * @brief Work around errata in STM32's FSMC core. - * @details Constant output clock (if enabled) disappears when CLKDIV value - * sets to 1 (FMC_CLK period = 2 × HCLK periods) AND 8-bit async - * transaction generated on AHB. This workaround eliminates 8-bit - * transactions on bus when you use 8-bit memory. It suitable only - * for 8-bit memory (i.e. PWID bits in PCR register must be set - * to 8-bit mode). - * - * @notapi - */ -static void set_16bit_bus(NANDDriver *nandp) { -#if STM32_NAND_BUS_WIDTH - nandp->nand->PCR |= FSMC_PCR_PWID_16; -#else - (void)nandp; -#endif -} - -static void set_8bit_bus(NANDDriver *nandp) { -#if STM32_NAND_BUS_WIDTH - nandp->nand->PCR &= ~FSMC_PCR_PWID_16; -#else - (void)nandp; -#endif -} - -/** - * @brief Wakes up the waiting thread. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] msg wakeup message - * - * @notapi - */ -static void wakeup_isr(NANDDriver *nandp) { - - osalDbgCheck(nandp->thread != NULL); - osalThreadResumeI(&nandp->thread, MSG_OK); -} - -/** - * @brief Put calling thread in suspend and switch driver state - * - * @param[in] nandp pointer to the @p NANDDriver object - */ -static void nand_lld_suspend_thread(NANDDriver *nandp) { - - osalThreadSuspendS(&nandp->thread); -} - -/** - * @brief Caclulate ECCPS register value - * - * @param[in] nandp pointer to the @p NANDDriver object - */ -static uint32_t calc_eccps(NANDDriver *nandp) { - - uint32_t i = 0; - uint32_t eccps = nandp->config->page_data_size; - - eccps = eccps >> 9; - while (eccps > 0){ - i++; - eccps >>= 1; - } - - return i << 17; -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief Enable interrupts from NAND - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @notapi - */ -static void nand_ready_isr_enable(NANDDriver *nandp) { - - nandp->nand->SR &= ~(FSMC_SR_IRS | FSMC_SR_ILS | FSMC_SR_IFS | - FSMC_SR_ILEN | FSMC_SR_IFEN); - nandp->nand->SR |= FSMC_SR_IREN; -} - -/** - * @brief Disable interrupts from NAND - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @notapi - */ -static void nand_ready_isr_disable(NANDDriver *nandp) { - - nandp->nand->SR &= ~FSMC_SR_IREN; -} - -/** - * @brief Ready interrupt handler - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @notapi - */ -static void nand_isr_handler(NANDDriver *nandp) { - - osalSysLockFromISR(); - - osalDbgCheck(nandp->nand->SR & FSMC_SR_IRS); /* spurious interrupt happened */ - nandp->nand->SR &= ~FSMC_SR_IRS; - - switch (nandp->state){ - case NAND_READ: - nandp->state = NAND_DMA_RX; - dmaStartMemCopy(nandp->dma, nandp->dmamode, nandp->map_data, nandp->rxdata, - nandp->datalen/AHB_TRANSACTION_WIDTH); - /* thread will be waked up from DMA ISR */ - break; - - case NAND_ERASE: /* NAND reports about erase finish */ - case NAND_PROGRAM: /* NAND reports about page programming finish */ - case NAND_RESET: /* NAND reports about finished reset recover */ - nandp->state = NAND_READY; - wakeup_isr(nandp); - break; - - default: - osalSysHalt("Unhandled case"); - break; - } - osalSysUnlockFromISR(); -} - -/** - * @brief DMA RX end IRQ handler. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] flags pre-shifted content of the ISR register - * - * @notapi - */ -static void nand_lld_serve_transfer_end_irq(NANDDriver *nandp, uint32_t flags) { - /* DMA errors handling.*/ -#if defined(STM32_NAND_DMA_ERROR_HOOK) - if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { - STM32_NAND_DMA_ERROR_HOOK(nandp); - } -#else - (void)flags; -#endif - - osalSysLockFromISR(); - - dmaStreamDisable(nandp->dma); - - switch (nandp->state){ - case NAND_DMA_TX: - nandp->state = NAND_PROGRAM; - nandp->map_cmd[0] = NAND_CMD_PAGEPROG; - /* thread will be woken up from ready_isr() */ - break; - - case NAND_DMA_RX: - nandp->state = NAND_READY; - nandp->rxdata = NULL; - nandp->datalen = 0; - wakeup_isr(nandp); - break; - - default: - osalSysHalt("Unhandled case"); - break; - } - - osalSysUnlockFromISR(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level NAND driver initialization. - * - * @notapi - */ -void nand_lld_init(void) { - - fsmc_init(); - -#if STM32_NAND_USE_FSMC_NAND1 - /* Driver initialization.*/ - nandObjectInit(&NANDD1); - NANDD1.rxdata = NULL; - NANDD1.datalen = 0; - NANDD1.thread = NULL; - NANDD1.dma = STM32_DMA_STREAM(STM32_NAND_DMA_STREAM); - NANDD1.nand = FSMCD1.nand1; - NANDD1.map_data = (void *)FSMC_Bank2_MAP_COMMON_DATA; - NANDD1.map_cmd = (uint16_t *)FSMC_Bank2_MAP_COMMON_CMD; - NANDD1.map_addr = (uint16_t *)FSMC_Bank2_MAP_COMMON_ADDR; - NANDD1.bb_map = NULL; -#endif /* STM32_NAND_USE_FSMC_NAND1 */ - -#if STM32_NAND_USE_FSMC_NAND2 - /* Driver initialization.*/ - nandObjectInit(&NANDD2); - NANDD2.rxdata = NULL; - NANDD2.datalen = 0; - NANDD2.thread = NULL; - NANDD2.dma = STM32_DMA_STREAM(STM32_NAND_DMA_STREAM); - NANDD2.nand = FSMCD1.nand2; - NANDD2.map_data = (void *)FSMC_Bank3_MAP_COMMON_DATA; - NANDD2.map_cmd = (uint16_t *)FSMC_Bank3_MAP_COMMON_CMD; - NANDD2.map_addr = (uint16_t *)FSMC_Bank3_MAP_COMMON_ADDR; - NANDD2.bb_map = NULL; -#endif /* STM32_NAND_USE_FSMC_NAND2 */ -} - -/** - * @brief Configures and activates the NAND peripheral. - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @notapi - */ -void nand_lld_start(NANDDriver *nandp) { - - bool b; - uint32_t dmasize; - uint32_t pcr_bus_width; - - if (FSMCD1.state == FSMC_STOP) - fsmc_start(&FSMCD1); - - if (nandp->state == NAND_STOP) { - b = dmaStreamAlloc(nandp->dma, - STM32_EMC_FSMC1_IRQ_PRIORITY, - (stm32_dmaisr_t)nand_lld_serve_transfer_end_irq, - (void *)nandp); - osalDbgAssert(!b, "stream already allocated"); - -#if AHB_TRANSACTION_WIDTH == 4 - dmasize = STM32_DMA_CR_PSIZE_WORD | STM32_DMA_CR_MSIZE_WORD; -#elif AHB_TRANSACTION_WIDTH == 2 - dmasize = STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; -#elif AHB_TRANSACTION_WIDTH == 1 - dmasize = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE; -#else -#error "Incorrect AHB_TRANSACTION_WIDTH" -#endif - - nandp->dmamode = STM32_DMA_CR_CHSEL(NAND_DMA_CHANNEL) | - STM32_DMA_CR_PL(STM32_NAND_NAND1_DMA_PRIORITY) | - dmasize | - STM32_DMA_CR_DMEIE | - STM32_DMA_CR_TEIE | - STM32_DMA_CR_TCIE; - -#if STM32_NAND_BUS_WIDTH == 8 - pcr_bus_width = FSMC_PCR_PWID_8; -#elif STM32_NAND_BUS_WIDTH == 16 - pcr_bus_width = FSMC_PCR_PWID_16; -#else -#error "Bus width must be 8 or 16 bits" -#endif - nandp->nand->PCR = pcr_bus_width | calc_eccps(nandp) | - FSMC_PCR_PTYP_NAND | FSMC_PCR_PBKEN; - nandp->nand->PMEM = nandp->config->pmem; - nandp->nand->PATT = nandp->config->pmem; - nandp->isr_handler = nand_isr_handler; - nand_ready_isr_enable(nandp); - } -} - -/** - * @brief Deactivates the NAND peripheral. - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @notapi - */ -void nand_lld_stop(NANDDriver *nandp) { - - if (nandp->state == NAND_READY) { - dmaStreamFree(nandp->dma); - nandp->nand->PCR &= ~FSMC_PCR_PBKEN; - nand_ready_isr_disable(nandp); - nandp->isr_handler = NULL; - } -} - -/** - * @brief Read data from NAND. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[out] data pointer to data buffer - * @param[in] datalen size of data buffer in bytes - * @param[in] addr pointer to address buffer - * @param[in] addrlen length of address - * @param[out] ecc pointer to store computed ECC. Ignored when NULL. - * - * @notapi - */ -void nand_lld_read_data(NANDDriver *nandp, uint16_t *data, size_t datalen, - uint8_t *addr, size_t addrlen, uint32_t *ecc){ - - align_check(data, datalen); - - nandp->state = NAND_READ; - nandp->rxdata = data; - nandp->datalen = datalen; - - set_16bit_bus(nandp); - nand_lld_write_cmd(nandp, NAND_CMD_READ0); - nand_lld_write_addr(nandp, addr, addrlen); - osalSysLock(); - nand_lld_write_cmd(nandp, NAND_CMD_READ0_CONFIRM); - set_8bit_bus(nandp); - - /* Here NAND asserts busy signal and starts transferring from memory - array to page buffer. After the end of transmission ready_isr functions - starts DMA transfer from page buffer to MCU's RAM.*/ - osalDbgAssert((nandp->nand->PCR & FSMC_PCR_ECCEN) == 0, - "State machine broken. ECCEN must be previously disabled."); - - if (NULL != ecc){ - nandp->nand->PCR |= FSMC_PCR_ECCEN; - } - - nand_lld_suspend_thread(nandp); - osalSysUnlock(); - - /* thread was woken up from DMA ISR */ - if (NULL != ecc){ - while (! (nandp->nand->SR & FSMC_SR_FEMPT)) - ; - *ecc = nandp->nand->ECCR; - nandp->nand->PCR &= ~FSMC_PCR_ECCEN; - } -} - -/** - * @brief Write data to NAND. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] data buffer with data to be written - * @param[in] datalen size of data buffer in bytes - * @param[in] addr pointer to address buffer - * @param[in] addrlen length of address - * @param[out] ecc pointer to store computed ECC. Ignored when NULL. - * - * @return The operation status reported by NAND IC (0x70 command). - * - * @notapi - */ -uint8_t nand_lld_write_data(NANDDriver *nandp, const uint16_t *data, - size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc) { - - align_check(data, datalen); - - nandp->state = NAND_WRITE; - - set_16bit_bus(nandp); - nand_lld_write_cmd(nandp, NAND_CMD_WRITE); - osalSysLock(); - nand_lld_write_addr(nandp, addr, addrlen); - set_8bit_bus(nandp); - - /* Now start DMA transfer to NAND buffer and put thread in sleep state. - Tread will be woken up from ready ISR. */ - nandp->state = NAND_DMA_TX; - osalDbgAssert((nandp->nand->PCR & FSMC_PCR_ECCEN) == 0, - "State machine broken. ECCEN must be previously disabled."); - - if (NULL != ecc){ - nandp->nand->PCR |= FSMC_PCR_ECCEN; - } - - dmaStartMemCopy(nandp->dma, nandp->dmamode, data, nandp->map_data, - datalen/AHB_TRANSACTION_WIDTH); - - nand_lld_suspend_thread(nandp); - osalSysUnlock(); - - if (NULL != ecc){ - while (! (nandp->nand->SR & FSMC_SR_FEMPT)) - ; - *ecc = nandp->nand->ECCR; - nandp->nand->PCR &= ~FSMC_PCR_ECCEN; - } - - return nand_lld_read_status(nandp); -} - -/** - * @brief Soft reset NAND device. - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @notapi - */ -void nand_lld_reset(NANDDriver *nandp) { - - nandp->state = NAND_RESET; - - set_16bit_bus(nandp); - nand_lld_write_cmd(nandp, NAND_CMD_RESET); - set_8bit_bus(nandp); - - osalSysLock(); - nand_lld_suspend_thread(nandp); - osalSysUnlock(); -} - -/** - * @brief Erase block. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] addr pointer to address buffer - * @param[in] addrlen length of address - * - * @return The operation status reported by NAND IC (0x70 command). - * - * @notapi - */ -uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen) { - - nandp->state = NAND_ERASE; - - set_16bit_bus(nandp); - nand_lld_write_cmd(nandp, NAND_CMD_ERASE); - nand_lld_write_addr(nandp, addr, addrlen); - osalSysLock(); - nand_lld_write_cmd(nandp, NAND_CMD_ERASE_CONFIRM); - set_8bit_bus(nandp); - - nand_lld_suspend_thread(nandp); - osalSysUnlock(); - - return nand_lld_read_status(nandp); -} - -/** - * @brief Send addres to NAND. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] len length of address array - * @param[in] addr pointer to address array - * - * @notapi - */ -void nand_lld_write_addr(NANDDriver *nandp, const uint8_t *addr, size_t len) { - size_t i = 0; - - for (i=0; imap_addr[i] = addr[i]; -} - -/** - * @brief Send command to NAND. - * - * @param[in] nandp pointer to the @p NANDDriver object - * @param[in] cmd command value - * - * @notapi - */ -void nand_lld_write_cmd(NANDDriver *nandp, uint8_t cmd) { - nandp->map_cmd[0] = cmd; -} - -/** - * @brief Read status byte from NAND. - * - * @param[in] nandp pointer to the @p NANDDriver object - * - * @return Status byte. - * - * @notapi - */ -uint8_t nand_lld_read_status(NANDDriver *nandp) { - - uint16_t status; - - set_16bit_bus(nandp); - nand_lld_write_cmd(nandp, NAND_CMD_STATUS); - set_8bit_bus(nandp); - status = nandp->map_data[0]; - - return status & 0xFF; -} - -#endif /* HAL_USE_NAND */ - -/** @} */ - diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.h deleted file mode 100644 index f47ee75..0000000 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_nand_lld.h +++ /dev/null @@ -1,289 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_fsmc_nand_lld.h - * @brief FSMC NAND Driver subsystem low level driver header. - * - * @addtogroup NAND - * @{ - */ - -#ifndef HAL_FSMC_NAND_LLD_H_ -#define HAL_FSMC_NAND_LLD_H_ - -#include "bitmap.h" - -#if (HAL_USE_FSMC_NAND == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ -#define NAND_MIN_PAGE_SIZE 256 -#define NAND_MAX_PAGE_SIZE 8192 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief FSMC1 interrupt priority level setting. - */ -#if !defined(STM32_EMC_FSMC1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define STM32_EMC_FSMC1_IRQ_PRIORITY 10 -#endif - -/** - * @brief NAND driver enable switch. - * @details If set to @p TRUE the support for NAND1 is included. - */ -#if !defined(STM32_FSMC_USE_NAND1) || defined(__DOXYGEN__) -#define STM32_FSMC_USE_NAND1 FALSE -#endif - -/** - * @brief NAND driver enable switch. - * @details If set to @p TRUE the support for NAND2 is included. - */ -#if !defined(STM32_FSMC_USE_NAND2) || defined(__DOXYGEN__) -#define STM32_FSMC_USE_NAND2 FALSE -#endif - -/** - * @brief NAND DMA error hook. - * @note The default action for DMA errors is a system halt because DMA - * error can only happen because programming errors. - */ -#if !defined(STM32_FSMC_DMA_ERROR_HOOK) || defined(__DOXYGEN__) -#define STM32_FSMC_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure") -#endif - -/** - * @brief NAND interrupt enable switch. - * @details If set to @p TRUE the support for internal FSMC interrupt included. - */ -#if !defined(STM32_FSMC_NAND_USE_INT) || defined(__DOXYGEN__) -#define STM32_FSMC_NAND_USE_INT FALSE -#endif - -/** -* @brief NAND1 DMA priority (0..3|lowest..highest). -*/ -#if !defined(STM32_FSMC_NAND1_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_FSMC_NAND1_DMA_PRIORITY 0 -#endif - -/** -* @brief NAND2 DMA priority (0..3|lowest..highest). -*/ -#if !defined(STM32_FSMC_NAND2_DMA_PRIORITY) || defined(__DOXYGEN__) -#define STM32_FSMC_NAND2_DMA_PRIORITY 0 -#endif - -/** - * @brief DMA stream used for NAND operations. - * @note This option is only available on platforms with enhanced DMA. - */ -#if !defined(STM32_FSMC_DMA_STREAM) || defined(__DOXYGEN__) -#define STM32_FSMC_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) -#endif - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !STM32_FSMC_USE_NAND1 && !STM32_FSMC_USE_NAND2 -#error "NAND driver activated but no NAND peripheral assigned" -#endif - -#if (STM32_FSMC_USE_NAND1 || STM32_FSMC_USE_NAND2) && !STM32_HAS_FSMC -#error "FSMC not present in the selected device" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a structure representing an NAND driver. - */ -typedef struct NANDDriver NANDDriver; - -/** - * @brief Type of interrupt handler function. - */ -typedef void (*nandisrhandler_t)(NANDDriver *nandp); - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief Number of erase blocks in NAND device. - */ - uint32_t blocks; - /** - * @brief Number of data bytes in page. - */ - uint32_t page_data_size; - /** - * @brief Number of spare bytes in page. - */ - uint32_t page_spare_size; - /** - * @brief Number of pages in block. - */ - uint32_t pages_per_block; - /** - * @brief Number of write cycles for row addressing. - */ - uint8_t rowcycles; - /** - * @brief Number of write cycles for column addressing. - */ - uint8_t colcycles; - - /* End of the mandatory fields.*/ - /** - * @brief Number of wait cycles. This value will be used both for - * PMEM and PATTR registers - * - * @note For proper calculation procedure please look at AN2784 document - * from STMicroelectronics. - */ - uint32_t pmem; -} NANDConfig; - -/** - * @brief Structure representing an NAND driver. - */ -struct NANDDriver { - /** - * @brief Driver state. - */ - nandstate_t state; - /** - * @brief Current configuration data. - */ - const NANDConfig *config; - /** - * @brief Array to store bad block map. - */ -#if NAND_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) -#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the bus. - */ - mutex_t mutex; -#elif CH_CFG_USE_SEMAPHORES - semaphore_t semaphore; -#endif -#endif /* NAND_USE_MUTUAL_EXCLUSION */ - /* End of the mandatory fields.*/ - /** - * @brief Function enabling interrupts from FSMC. - */ - nandisrhandler_t isr_handler; - /** - * @brief Pointer to current transaction buffer. - */ - void *rxdata; - /** - * @brief Current transaction length in bytes. - */ - size_t datalen; - /** - * @brief DMA mode bit mask. - */ - uint32_t dmamode; - /** - * @brief DMA channel. - */ - const stm32_dma_stream_t *dma; - /** - * @brief Thread waiting for I/O completion. - */ - thread_t *thread; - /** - * @brief Pointer to the FSMC NAND registers block. - */ - FSMC_NAND_TypeDef *nand; - /** - * @brief Memory mapping for data. - */ - uint16_t *map_data; - /** - * @brief Memory mapping for commands. - */ - uint16_t *map_cmd; - /** - * @brief Memory mapping for addresses. - */ - uint16_t *map_addr; - /** - * @brief Pointer to bad block map. - * @details One bit per block. All memory allocation is user's responsibility. - */ - bitmap_t *bb_map; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_FSMC_USE_NAND1 && !defined(__DOXYGEN__) -extern NANDDriver NANDD1; -#endif - -#if STM32_FSMC_USE_NAND2 && !defined(__DOXYGEN__) -extern NANDDriver NANDD2; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void nand_lld_init(void); - void nand_lld_start(NANDDriver *nandp); - void nand_lld_stop(NANDDriver *nandp); - uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen); - void nand_lld_read_data(NANDDriver *nandp, uint16_t *data, - size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc); - void nand_lld_write_addr(NANDDriver *nandp, const uint8_t *addr, size_t len); - void nand_lld_write_cmd(NANDDriver *nandp, uint8_t cmd); - uint8_t nand_lld_write_data(NANDDriver *nandp, const uint16_t *data, - size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc); - uint8_t nand_lld_read_status(NANDDriver *nandp); - void nand_lld_reset(NANDDriver *nandp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_FSMC_NAND */ - -#endif /* HAL_FSMC_NAND_LLD_H_ */ - -/** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c deleted file mode 100644 index 1b0c0db..0000000 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.c +++ /dev/null @@ -1,172 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - SDRAM routines added by Nick Klimov aka progfin. - */ - -/** - * @file hal_fsmc_sdram.c - * @brief SDRAM Driver subsystem low level driver source. - * - * @addtogroup SDRAM - * @{ - */ - -#include "hal.h" - -#if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F745xx) || defined(STM32F746xx) || \ - defined(STM32F756xx) || defined(STM32F767xx) || \ - defined(STM32F769xx) || defined(STM32F777xx) || \ - defined(STM32F779xx)) - -#if (HAL_USE_FSMC_SDRAM == TRUE) || defined(__DOXYGEN__) - -#include "hal_fsmc_sdram_lld.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/** - * FMC_Command_Mode - */ -#define FMCCM_NORMAL ((uint32_t)0x00000000) -#define FMCCM_CLK_ENABLED ((uint32_t)0x00000001) -#define FMCCM_PALL ((uint32_t)0x00000002) -#define FMCCM_AUTO_REFRESH ((uint32_t)0x00000003) -#define FMCCM_LOAD_MODE ((uint32_t)0x00000004) -#define FMCCM_SELFREFRESH ((uint32_t)0x00000005) -#define FMCCM_POWER_DOWN ((uint32_t)0x00000006) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ -/** - * @brief SDRAM driver identifier. - */ -SDRAMDriver SDRAMD; - -/*===========================================================================*/ -/* Driver local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Wait until the SDRAM controller is ready. - * - * @notapi - */ -static void lld_sdram_wait_ready(void) { - /* Wait until the SDRAM controller is ready */ - while (SDRAMD.sdram->SDSR & FMC_SDSR_BUSY); -} - -/** - * @brief Executes the SDRAM memory initialization sequence. - * - * @param[in] cfgp pointer to the @p SDRAMConfig object - * - * @notapi - */ -static void lld_sdram_init_sequence(const SDRAMConfig *cfgp) { - - uint32_t command_target = 0; - -#if STM32_FSMC_USE_SDRAM1 - command_target |= FMC_SDCMR_CTB1; -#endif -#if STM32_FSMC_USE_SDRAM2 - command_target |= FMC_SDCMR_CTB2; -#endif - - /* Step 3: Configure a clock configuration enable command.*/ - lld_sdram_wait_ready(); - SDRAMD.sdram->SDCMR = FMCCM_CLK_ENABLED | command_target; - - /* Step 4: Insert delay (tipically 100uS).*/ - osalThreadSleepMilliseconds(1); - - /* Step 5: Configure a PALL (precharge all) command.*/ - lld_sdram_wait_ready(); - SDRAMD.sdram->SDCMR = FMCCM_PALL | command_target; - - /* Step 6.1: Configure a Auto-Refresh command: send the first command.*/ - lld_sdram_wait_ready(); - SDRAMD.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target | - (cfgp->sdcmr & FMC_SDCMR_NRFS); - - /* Step 6.2: Send the second command.*/ - lld_sdram_wait_ready(); - SDRAMD.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target | - (cfgp->sdcmr & FMC_SDCMR_NRFS); - - /* Step 7: Program the external memory mode register.*/ - lld_sdram_wait_ready(); - SDRAMD.sdram->SDCMR = FMCCM_LOAD_MODE | command_target | - (cfgp->sdcmr & FMC_SDCMR_MRD); - - /* Step 8: Set clock.*/ - lld_sdram_wait_ready(); - SDRAMD.sdram->SDRTR = cfgp->sdrtr & FMC_SDRTR_COUNT; - - lld_sdram_wait_ready(); -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -void lld_sdram_start(SDRAMDriver *sdramp, const SDRAMConfig *cfgp) -{ - sdramp->sdram->SDCR1 = cfgp->sdcr; - sdramp->sdram->SDTR1 = cfgp->sdtr; - sdramp->sdram->SDCR2 = cfgp->sdcr; - sdramp->sdram->SDTR2 = cfgp->sdtr; - - lld_sdram_init_sequence(cfgp); -} - -void lld_sdram_stop(SDRAMDriver *sdramp) { - uint32_t command_target = 0; - -#if STM32_FSMC_USE_SDRAM1 - command_target |= FMC_SDCMR_CTB1; -#endif -#if STM32_FSMC_USE_SDRAM2 - command_target |= FMC_SDCMR_CTB2; -#endif - - sdramp->sdram->SDCMR = FMCCM_POWER_DOWN | command_target; -} -#endif /* STM32_USE_FSMC_SDRAM */ - -#endif /* STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx */ - -/** @} */ - diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.h deleted file mode 100644 index 1fc7993..0000000 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram_lld.h +++ /dev/null @@ -1,117 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ -/* - SDRAM routines added by Nick Klimov aka progfin. - */ - -/** - * @file hal_fsmc_sdram.h - * @brief SDRAM Driver subsystem low level driver header. - * - * @addtogroup SDRAM - * @{ - */ - -#ifndef HAL_FMC_SDRAM_H_ -#define HAL_FMC_SDRAM_H_ - -#if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F745xx) || defined(STM32F746xx) || \ - defined(STM32F756xx) || defined(STM32F767xx) || \ - defined(STM32F769xx) || defined(STM32F777xx) || \ - defined(STM32F779xx)) - -#include "hal_fsmc.h" - -#if (HAL_USE_FSMC_SDRAM == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ -/** - * @name Configuration options - * @{ - */ - -/** - * @brief SDRAM driver enable switch. - * @details If set to @p TRUE the support for SDRAM1 is included. - */ -#if !defined(STM32_FSMC_USE_SDRAM1) || defined(__DOXYGEN__) -#define STM32_FSMC_USE_SDRAM1 FALSE -#else -#define STM32_SDRAM1_MAP_BASE FSMC_Bank5_MAP_BASE -#endif - -/** - * @brief SDRAM driver enable switch. - * @details If set to @p TRUE the support for SDRAM2 is included. - */ -#if !defined(STM32_FSMC_USE_SDRAM2) || defined(__DOXYGEN__) -#define STM32_FSMC_USE_SDRAM2 FALSE -#else -#define STM32_SDRAM2_MAP_BASE FSMC_Bank6_MAP_BASE -#endif - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !STM32_FSMC_USE_SDRAM1 && !STM32_FSMC_USE_SDRAM2 -#error "SDRAM driver activated but no SDRAM peripheral assigned" -#endif - -#if (STM32_FSMC_USE_SDRAM1 || STM32_FSMC_USE_SDRAM2) && !STM32_HAS_FSMC -#error "FMC not present in the selected device" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -extern SDRAMDriver SDRAMD; - -#ifdef __cplusplus -extern "C" { -#endif - void lld_sdram_start(SDRAMDriver *sdramp, const SDRAMConfig *cfgp); - void lld_sdram_stop(SDRAMDriver *sdramp); -#ifdef __cplusplus -} -#endif - -#endif /* STM32_FSMC_USE_SDRAM */ - -#endif /* STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx */ - -#endif /* HAL_FSMC_SDRAM_H_ */ - -/** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.c deleted file mode 100644 index 49b7826..0000000 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.c +++ /dev/null @@ -1,124 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_fsmc_sram.c - * @brief SRAM Driver subsystem low level driver source. - * - * @addtogroup SRAM - * @{ - */ -#include "hal.h" - -#if (HAL_USE_FSMC_SRAM == TRUE) || defined(__DOXYGEN__) - -#include "hal_fsmc_sram_lld.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ -/** - * @brief SRAM1 driver identifier. - */ -#if STM32_FSMC_USE_SRAM1 || defined(__DOXYGEN__) -SRAMDriver SRAMD1; -#endif - -/** - * @brief SRAM2 driver identifier. - */ -#if STM32_FSMC_USE_SRAM2 || defined(__DOXYGEN__) -SRAMDriver SRAMD2; -#endif - -/** - * @brief SRAM3 driver identifier. - */ -#if STM32_FSMC_USE_SRAM3 || defined(__DOXYGEN__) -SRAMDriver SRAMD3; -#endif - -/** - * @brief SRAM4 driver identifier. - */ -#if STM32_FSMC_USE_SRAM4 || defined(__DOXYGEN__) -SRAMDriver SRAMD4; -#endif - -/*===========================================================================*/ -/* Driver local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Configures and activates the SRAM peripheral. - * - * @param[in] sramp pointer to the @p SRAMDriver object - * @param[in] cfgp pointer to the @p SRAMConfig object - * - * @notapi - */ -void lld_sram_start(SRAMDriver *sramp, const SRAMConfig *cfgp) { - - sramp->sram->BTR = cfgp->btr; - sramp->sram->BWTR = cfgp->bwtr; - sramp->sram->BCR = cfgp->bcr | FSMC_BCR_MBKEN; -} - -/** - * @brief Deactivates the SRAM peripheral. - * - * @param[in] sramp pointer to the @p SRAMDriver object - * - * @notapi - */ -void lld_sram_stop(SRAMDriver *sramp) { - - uint32_t mask = FSMC_BCR_MBKEN; -#if (defined(STM32F427xx) || defined(STM32F437xx) || \ - defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F745xx) || defined(STM32F746xx) || \ - defined(STM32F756xx) || defined(STM32F767xx) || \ - defined(STM32F769xx) || defined(STM32F777xx) || \ - defined(STM32F779xx)) - mask |= FSMC_BCR_CCLKEN; -#endif - sramp->sram->BCR &= ~mask; -} - -#endif /* STM32_FSMC_USE_SRAM */ - -/** @} */ - diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.h deleted file mode 100644 index bfd878f..0000000 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram_lld.h +++ /dev/null @@ -1,91 +0,0 @@ -/* - ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file hal_fsmc_sram.h - * @brief SRAM Driver subsystem low level driver header. - * - * @addtogroup SRAM - * @{ - */ - -#ifndef HAL_FSMC_SRAM_H_ -#define HAL_FSMC_SRAM_H_ - -#include "hal_fsmc.h" - -#if (HAL_USE_FSMC_SRAM == TRUE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ -/** - * @name Configuration options - * @{ - */ - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if STM32_FSMC_USE_SRAM1 && !defined(__DOXYGEN__) -extern SRAMDriver SRAMD1; -#endif - -#if STM32_FSMC_USE_SRAM2 && !defined(__DOXYGEN__) -extern SRAMDriver SRAMD2; -#endif - -#if STM32_FSMC_USE_SRAM3 && !defined(__DOXYGEN__) -extern SRAMDriver SRAMD3; -#endif - -#if STM32_FSMC_USE_SRAM4 && !defined(__DOXYGEN__) -extern SRAMDriver SRAMD4; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void lld_sram_start(SRAMDriver *sramp, const SRAMConfig *cfgp); - void lld_sram_stop(SRAMDriver *sramp); -#ifdef __cplusplus -} -#endif - -#endif /* STM32_FSMC_USE_SRAM */ - -#endif /* HAL_FSMC_SRAM_H_ */ - -/** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c new file mode 100644 index 0000000..abd5aa3 --- /dev/null +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c @@ -0,0 +1,592 @@ +/* + ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_fsmc_nand_lld.c + * @brief FSMC NAND Driver subsystem low level driver source. + * + * @addtogroup NAND + * @{ + */ + +#include "hal.h" + +#if (HAL_USE_NAND == TRUE) || defined(__DOXYGEN__) + +#include "hal_nand_lld.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ +#define NAND_DMA_CHANNEL \ + STM32_DMA_GETCHANNEL(STM32_NAND_DMA_STREAM, \ + STM32_FSMC_DMA_CHN) + +/** + * @brief Bus width of NAND IC. + * @details Must be 8 or 16 + */ +#if ! defined(STM32_NAND_BUS_WIDTH) || defined(__DOXYGEN__) +#define STM32_NAND_BUS_WIDTH 8 +#endif + +/** + * @brief DMA transaction width on AHB bus in bytes + */ +#define AHB_TRANSACTION_WIDTH 2 + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief NAND1 driver identifier. + */ +#if STM32_NAND_USE_NAND1 || defined(__DOXYGEN__) +NANDDriver NANDD1; +#endif + +/** + * @brief NAND2 driver identifier. + */ +#if STM32_NAND_USE_NAND2 || defined(__DOXYGEN__) +NANDDriver NANDD2; +#endif + +/*===========================================================================*/ +/* Driver local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Helper function. + * + * @notapi + */ +static void align_check(const void *ptr, uint32_t len) { + osalDbgCheck((((uint32_t)ptr % AHB_TRANSACTION_WIDTH) == 0) && + ((len % AHB_TRANSACTION_WIDTH) == 0) && + (len >= AHB_TRANSACTION_WIDTH)); + (void)ptr; + (void)len; +} + +/** + * @brief Work around errata in STM32's FSMC core. + * @details Constant output clock (if enabled) disappears when CLKDIV value + * sets to 1 (FMC_CLK period = 2 × HCLK periods) AND 8-bit async + * transaction generated on AHB. This workaround eliminates 8-bit + * transactions on bus when you use 8-bit memory. It suitable only + * for 8-bit memory (i.e. PWID bits in PCR register must be set + * to 8-bit mode). + * + * @notapi + */ +static void set_16bit_bus(NANDDriver *nandp) { +#if STM32_NAND_BUS_WIDTH + nandp->nand->PCR |= FSMC_PCR_PWID_16; +#else + (void)nandp; +#endif +} + +static void set_8bit_bus(NANDDriver *nandp) { +#if STM32_NAND_BUS_WIDTH + nandp->nand->PCR &= ~FSMC_PCR_PWID_16; +#else + (void)nandp; +#endif +} + +/** + * @brief Wakes up the waiting thread. + * + * @param[in] nandp pointer to the @p NANDDriver object + * @param[in] msg wakeup message + * + * @notapi + */ +static void wakeup_isr(NANDDriver *nandp) { + + osalDbgCheck(nandp->thread != NULL); + osalThreadResumeI(&nandp->thread, MSG_OK); +} + +/** + * @brief Put calling thread in suspend and switch driver state + * + * @param[in] nandp pointer to the @p NANDDriver object + */ +static void nand_lld_suspend_thread(NANDDriver *nandp) { + + osalThreadSuspendS(&nandp->thread); +} + +/** + * @brief Caclulate ECCPS register value + * + * @param[in] nandp pointer to the @p NANDDriver object + */ +static uint32_t calc_eccps(NANDDriver *nandp) { + + uint32_t i = 0; + uint32_t eccps = nandp->config->page_data_size; + + eccps = eccps >> 9; + while (eccps > 0){ + i++; + eccps >>= 1; + } + + return i << 17; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief Enable interrupts from NAND + * + * @param[in] nandp pointer to the @p NANDDriver object + * + * @notapi + */ +static void nand_ready_isr_enable(NANDDriver *nandp) { + + nandp->nand->SR &= ~(FSMC_SR_IRS | FSMC_SR_ILS | FSMC_SR_IFS | + FSMC_SR_ILEN | FSMC_SR_IFEN); + nandp->nand->SR |= FSMC_SR_IREN; +} + +/** + * @brief Disable interrupts from NAND + * + * @param[in] nandp pointer to the @p NANDDriver object + * + * @notapi + */ +static void nand_ready_isr_disable(NANDDriver *nandp) { + + nandp->nand->SR &= ~FSMC_SR_IREN; +} + +/** + * @brief Ready interrupt handler + * + * @param[in] nandp pointer to the @p NANDDriver object + * + * @notapi + */ +static void nand_isr_handler(NANDDriver *nandp) { + + osalSysLockFromISR(); + + osalDbgCheck(nandp->nand->SR & FSMC_SR_IRS); /* spurious interrupt happened */ + nandp->nand->SR &= ~FSMC_SR_IRS; + + switch (nandp->state){ + case NAND_READ: + nandp->state = NAND_DMA_RX; + dmaStartMemCopy(nandp->dma, nandp->dmamode, nandp->map_data, nandp->rxdata, + nandp->datalen/AHB_TRANSACTION_WIDTH); + /* thread will be waked up from DMA ISR */ + break; + + case NAND_ERASE: /* NAND reports about erase finish */ + case NAND_PROGRAM: /* NAND reports about page programming finish */ + case NAND_RESET: /* NAND reports about finished reset recover */ + nandp->state = NAND_READY; + wakeup_isr(nandp); + break; + + default: + osalSysHalt("Unhandled case"); + break; + } + osalSysUnlockFromISR(); +} + +/** + * @brief DMA RX end IRQ handler. + * + * @param[in] nandp pointer to the @p NANDDriver object + * @param[in] flags pre-shifted content of the ISR register + * + * @notapi + */ +static void nand_lld_serve_transfer_end_irq(NANDDriver *nandp, uint32_t flags) { + /* DMA errors handling.*/ +#if defined(STM32_NAND_DMA_ERROR_HOOK) + if ((flags & (STM32_DMA_ISR_TEIF | STM32_DMA_ISR_DMEIF)) != 0) { + STM32_NAND_DMA_ERROR_HOOK(nandp); + } +#else + (void)flags; +#endif + + osalSysLockFromISR(); + + dmaStreamDisable(nandp->dma); + + switch (nandp->state){ + case NAND_DMA_TX: + nandp->state = NAND_PROGRAM; + nandp->map_cmd[0] = NAND_CMD_PAGEPROG; + /* thread will be woken up from ready_isr() */ + break; + + case NAND_DMA_RX: + nandp->state = NAND_READY; + nandp->rxdata = NULL; + nandp->datalen = 0; + wakeup_isr(nandp); + break; + + default: + osalSysHalt("Unhandled case"); + break; + } + + osalSysUnlockFromISR(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level NAND driver initialization. + * + * @notapi + */ +void nand_lld_init(void) { + + fsmcInit(); + +#if STM32_NAND_USE_NAND1 + /* Driver initialization.*/ + nandObjectInit(&NANDD1); + NANDD1.rxdata = NULL; + NANDD1.datalen = 0; + NANDD1.thread = NULL; + NANDD1.dma = STM32_DMA_STREAM(STM32_NAND_DMA_STREAM); + NANDD1.nand = FSMCD1.nand1; + NANDD1.map_data = (void *)FSMC_Bank2_MAP_COMMON_DATA; + NANDD1.map_cmd = (uint16_t *)FSMC_Bank2_MAP_COMMON_CMD; + NANDD1.map_addr = (uint16_t *)FSMC_Bank2_MAP_COMMON_ADDR; + NANDD1.bb_map = NULL; +#endif /* STM32_NAND_USE_NAND1 */ + +#if STM32_NAND_USE_NAND2 + /* Driver initialization.*/ + nandObjectInit(&NANDD2); + NANDD2.rxdata = NULL; + NANDD2.datalen = 0; + NANDD2.thread = NULL; + NANDD2.dma = STM32_DMA_STREAM(STM32_NAND_DMA_STREAM); + NANDD2.nand = FSMCD1.nand2; + NANDD2.map_data = (void *)FSMC_Bank3_MAP_COMMON_DATA; + NANDD2.map_cmd = (uint16_t *)FSMC_Bank3_MAP_COMMON_CMD; + NANDD2.map_addr = (uint16_t *)FSMC_Bank3_MAP_COMMON_ADDR; + NANDD2.bb_map = NULL; +#endif /* STM32_NAND_USE_NAND2 */ +} + +/** + * @brief Configures and activates the NAND peripheral. + * + * @param[in] nandp pointer to the @p NANDDriver object + * + * @notapi + */ +void nand_lld_start(NANDDriver *nandp) { + + bool b; + uint32_t dmasize; + uint32_t pcr_bus_width; + + if (FSMCD1.state == FSMC_STOP) + fsmcStart(&FSMCD1); + + if (nandp->state == NAND_STOP) { + b = dmaStreamAlloc(nandp->dma, + STM32_EMC_FSMC1_IRQ_PRIORITY, + (stm32_dmaisr_t)nand_lld_serve_transfer_end_irq, + (void *)nandp); + osalDbgAssert(!b, "stream already allocated"); + +#if AHB_TRANSACTION_WIDTH == 4 + dmasize = STM32_DMA_CR_PSIZE_WORD | STM32_DMA_CR_MSIZE_WORD; +#elif AHB_TRANSACTION_WIDTH == 2 + dmasize = STM32_DMA_CR_PSIZE_HWORD | STM32_DMA_CR_MSIZE_HWORD; +#elif AHB_TRANSACTION_WIDTH == 1 + dmasize = STM32_DMA_CR_PSIZE_BYTE | STM32_DMA_CR_MSIZE_BYTE; +#else +#error "Incorrect AHB_TRANSACTION_WIDTH" +#endif + + nandp->dmamode = STM32_DMA_CR_CHSEL(NAND_DMA_CHANNEL) | + STM32_DMA_CR_PL(STM32_NAND_DMA_PRIORITY) | + dmasize | + STM32_DMA_CR_DMEIE | + STM32_DMA_CR_TEIE | + STM32_DMA_CR_TCIE; + +#if STM32_NAND_BUS_WIDTH == 8 + pcr_bus_width = FSMC_PCR_PWID_8; +#elif STM32_NAND_BUS_WIDTH == 16 + pcr_bus_width = FSMC_PCR_PWID_16; +#else +#error "Bus width must be 8 or 16 bits" +#endif + nandp->nand->PCR = pcr_bus_width | calc_eccps(nandp) | + FSMC_PCR_PTYP_NAND | FSMC_PCR_PBKEN; + nandp->nand->PMEM = nandp->config->pmem; + nandp->nand->PATT = nandp->config->pmem; + nandp->isr_handler = nand_isr_handler; + nand_ready_isr_enable(nandp); + } +} + +/** + * @brief Deactivates the NAND peripheral. + * + * @param[in] nandp pointer to the @p NANDDriver object + * + * @notapi + */ +void nand_lld_stop(NANDDriver *nandp) { + + if (nandp->state == NAND_READY) { + dmaStreamFree(nandp->dma); + nandp->nand->PCR &= ~FSMC_PCR_PBKEN; + nand_ready_isr_disable(nandp); + nandp->isr_handler = NULL; + } +} + +/** + * @brief Read data from NAND. + * + * @param[in] nandp pointer to the @p NANDDriver object + * @param[out] data pointer to data buffer + * @param[in] datalen size of data buffer in bytes + * @param[in] addr pointer to address buffer + * @param[in] addrlen length of address + * @param[out] ecc pointer to store computed ECC. Ignored when NULL. + * + * @notapi + */ +void nand_lld_read_data(NANDDriver *nandp, uint16_t *data, size_t datalen, + uint8_t *addr, size_t addrlen, uint32_t *ecc){ + + align_check(data, datalen); + + nandp->state = NAND_READ; + nandp->rxdata = data; + nandp->datalen = datalen; + + set_16bit_bus(nandp); + nand_lld_write_cmd(nandp, NAND_CMD_READ0); + nand_lld_write_addr(nandp, addr, addrlen); + osalSysLock(); + nand_lld_write_cmd(nandp, NAND_CMD_READ0_CONFIRM); + set_8bit_bus(nandp); + + /* Here NAND asserts busy signal and starts transferring from memory + array to page buffer. After the end of transmission ready_isr functions + starts DMA transfer from page buffer to MCU's RAM.*/ + osalDbgAssert((nandp->nand->PCR & FSMC_PCR_ECCEN) == 0, + "State machine broken. ECCEN must be previously disabled."); + + if (NULL != ecc){ + nandp->nand->PCR |= FSMC_PCR_ECCEN; + } + + nand_lld_suspend_thread(nandp); + osalSysUnlock(); + + /* thread was woken up from DMA ISR */ + if (NULL != ecc){ + while (! (nandp->nand->SR & FSMC_SR_FEMPT)) + ; + *ecc = nandp->nand->ECCR; + nandp->nand->PCR &= ~FSMC_PCR_ECCEN; + } +} + +/** + * @brief Write data to NAND. + * + * @param[in] nandp pointer to the @p NANDDriver object + * @param[in] data buffer with data to be written + * @param[in] datalen size of data buffer in bytes + * @param[in] addr pointer to address buffer + * @param[in] addrlen length of address + * @param[out] ecc pointer to store computed ECC. Ignored when NULL. + * + * @return The operation status reported by NAND IC (0x70 command). + * + * @notapi + */ +uint8_t nand_lld_write_data(NANDDriver *nandp, const uint16_t *data, + size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc) { + + align_check(data, datalen); + + nandp->state = NAND_WRITE; + + set_16bit_bus(nandp); + nand_lld_write_cmd(nandp, NAND_CMD_WRITE); + osalSysLock(); + nand_lld_write_addr(nandp, addr, addrlen); + set_8bit_bus(nandp); + + /* Now start DMA transfer to NAND buffer and put thread in sleep state. + Tread will be woken up from ready ISR. */ + nandp->state = NAND_DMA_TX; + osalDbgAssert((nandp->nand->PCR & FSMC_PCR_ECCEN) == 0, + "State machine broken. ECCEN must be previously disabled."); + + if (NULL != ecc){ + nandp->nand->PCR |= FSMC_PCR_ECCEN; + } + + dmaStartMemCopy(nandp->dma, nandp->dmamode, data, nandp->map_data, + datalen/AHB_TRANSACTION_WIDTH); + + nand_lld_suspend_thread(nandp); + osalSysUnlock(); + + if (NULL != ecc){ + while (! (nandp->nand->SR & FSMC_SR_FEMPT)) + ; + *ecc = nandp->nand->ECCR; + nandp->nand->PCR &= ~FSMC_PCR_ECCEN; + } + + return nand_lld_read_status(nandp); +} + +/** + * @brief Soft reset NAND device. + * + * @param[in] nandp pointer to the @p NANDDriver object + * + * @notapi + */ +void nand_lld_reset(NANDDriver *nandp) { + + nandp->state = NAND_RESET; + + set_16bit_bus(nandp); + nand_lld_write_cmd(nandp, NAND_CMD_RESET); + set_8bit_bus(nandp); + + osalSysLock(); + nand_lld_suspend_thread(nandp); + osalSysUnlock(); +} + +/** + * @brief Erase block. + * + * @param[in] nandp pointer to the @p NANDDriver object + * @param[in] addr pointer to address buffer + * @param[in] addrlen length of address + * + * @return The operation status reported by NAND IC (0x70 command). + * + * @notapi + */ +uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen) { + + nandp->state = NAND_ERASE; + + set_16bit_bus(nandp); + nand_lld_write_cmd(nandp, NAND_CMD_ERASE); + nand_lld_write_addr(nandp, addr, addrlen); + osalSysLock(); + nand_lld_write_cmd(nandp, NAND_CMD_ERASE_CONFIRM); + set_8bit_bus(nandp); + + nand_lld_suspend_thread(nandp); + osalSysUnlock(); + + return nand_lld_read_status(nandp); +} + +/** + * @brief Send addres to NAND. + * + * @param[in] nandp pointer to the @p NANDDriver object + * @param[in] len length of address array + * @param[in] addr pointer to address array + * + * @notapi + */ +void nand_lld_write_addr(NANDDriver *nandp, const uint8_t *addr, size_t len) { + size_t i = 0; + + for (i=0; imap_addr[i] = addr[i]; +} + +/** + * @brief Send command to NAND. + * + * @param[in] nandp pointer to the @p NANDDriver object + * @param[in] cmd command value + * + * @notapi + */ +void nand_lld_write_cmd(NANDDriver *nandp, uint8_t cmd) { + nandp->map_cmd[0] = cmd; +} + +/** + * @brief Read status byte from NAND. + * + * @param[in] nandp pointer to the @p NANDDriver object + * + * @return Status byte. + * + * @notapi + */ +uint8_t nand_lld_read_status(NANDDriver *nandp) { + + uint16_t status; + + set_16bit_bus(nandp); + nand_lld_write_cmd(nandp, NAND_CMD_STATUS); + set_8bit_bus(nandp); + status = nandp->map_data[0]; + + return status & 0xFF; +} + +#endif /* HAL_USE_NAND */ + +/** @} */ + diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h new file mode 100644 index 0000000..c4f8595 --- /dev/null +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h @@ -0,0 +1,290 @@ +/* + ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_fsmc_nand_lld.h + * @brief FSMC NAND Driver subsystem low level driver header. + * + * @addtogroup NAND + * @{ + */ + +#ifndef HAL_NAND_LLD_H_ +#define HAL_NAND_LLD_H_ + +#include "bitmap.h" +#include "hal_fsmc.h" + +#if (HAL_USE_NAND == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ +#define NAND_MIN_PAGE_SIZE 256 +#define NAND_MAX_PAGE_SIZE 8192 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief FSMC1 interrupt priority level setting. + */ +#if !defined(STM32_EMC_FSMC1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define STM32_EMC_FSMC1_IRQ_PRIORITY 10 +#endif + +/** + * @brief NAND driver enable switch. + * @details If set to @p TRUE the support for NAND1 is included. + */ +#if !defined(STM32_NAND_USE_NAND1) || defined(__DOXYGEN__) +#define STM32_NAND_USE_NAND1 FALSE +#endif + +/** + * @brief NAND driver enable switch. + * @details If set to @p TRUE the support for NAND2 is included. + */ +#if !defined(STM32_NAND_USE_NAND2) || defined(__DOXYGEN__) +#define STM32_NAND_USE_NAND2 FALSE +#endif + +/** + * @brief NAND DMA error hook. + * @note The default action for DMA errors is a system halt because DMA + * error can only happen because programming errors. + */ +#if !defined(STM32_FSMC_DMA_ERROR_HOOK) || defined(__DOXYGEN__) +#define STM32_FSMC_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure") +#endif + +/** + * @brief NAND interrupt enable switch. + * @details If set to @p TRUE the support for internal FSMC interrupt included. + */ +#if !defined(STM32_FSMC_NAND_USE_INT) || defined(__DOXYGEN__) +#define STM32_FSMC_NAND_USE_INT FALSE +#endif + +/** +* @brief NAND1 DMA priority (0..3|lowest..highest). +*/ +#if !defined(STM32_FSMC_NAND1_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_FSMC_NAND1_DMA_PRIORITY 0 +#endif + +/** +* @brief NAND2 DMA priority (0..3|lowest..highest). +*/ +#if !defined(STM32_FSMC_NAND2_DMA_PRIORITY) || defined(__DOXYGEN__) +#define STM32_FSMC_NAND2_DMA_PRIORITY 0 +#endif + +/** + * @brief DMA stream used for NAND operations. + * @note This option is only available on platforms with enhanced DMA. + */ +#if !defined(STM32_FSMC_DMA_STREAM) || defined(__DOXYGEN__) +#define STM32_FSMC_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !STM32_NAND_USE_NAND1 && !STM32_NAND_USE_NAND2 +#error "NAND driver activated but no NAND peripheral assigned" +#endif + +#if (STM32_NAND_USE_NAND1 || STM32_NAND_USE_NAND2) && !STM32_HAS_FSMC +#error "FSMC not present in the selected device" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an NAND driver. + */ +typedef struct NANDDriver NANDDriver; + +/** + * @brief Type of interrupt handler function. + */ +typedef void (*nandisrhandler_t)(NANDDriver *nandp); + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Number of erase blocks in NAND device. + */ + uint32_t blocks; + /** + * @brief Number of data bytes in page. + */ + uint32_t page_data_size; + /** + * @brief Number of spare bytes in page. + */ + uint32_t page_spare_size; + /** + * @brief Number of pages in block. + */ + uint32_t pages_per_block; + /** + * @brief Number of write cycles for row addressing. + */ + uint8_t rowcycles; + /** + * @brief Number of write cycles for column addressing. + */ + uint8_t colcycles; + + /* End of the mandatory fields.*/ + /** + * @brief Number of wait cycles. This value will be used both for + * PMEM and PATTR registers + * + * @note For proper calculation procedure please look at AN2784 document + * from STMicroelectronics. + */ + uint32_t pmem; +} NANDConfig; + +/** + * @brief Structure representing an NAND driver. + */ +struct NANDDriver { + /** + * @brief Driver state. + */ + nandstate_t state; + /** + * @brief Current configuration data. + */ + const NANDConfig *config; + /** + * @brief Array to store bad block map. + */ +#if NAND_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) +#if CH_CFG_USE_MUTEXES || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + mutex_t mutex; +#elif CH_CFG_USE_SEMAPHORES + semaphore_t semaphore; +#endif +#endif /* NAND_USE_MUTUAL_EXCLUSION */ + /* End of the mandatory fields.*/ + /** + * @brief Function enabling interrupts from FSMC. + */ + nandisrhandler_t isr_handler; + /** + * @brief Pointer to current transaction buffer. + */ + void *rxdata; + /** + * @brief Current transaction length in bytes. + */ + size_t datalen; + /** + * @brief DMA mode bit mask. + */ + uint32_t dmamode; + /** + * @brief DMA channel. + */ + const stm32_dma_stream_t *dma; + /** + * @brief Thread waiting for I/O completion. + */ + thread_t *thread; + /** + * @brief Pointer to the FSMC NAND registers block. + */ + FSMC_NAND_TypeDef *nand; + /** + * @brief Memory mapping for data. + */ + uint16_t *map_data; + /** + * @brief Memory mapping for commands. + */ + uint16_t *map_cmd; + /** + * @brief Memory mapping for addresses. + */ + uint16_t *map_addr; + /** + * @brief Pointer to bad block map. + * @details One bit per block. All memory allocation is user's responsibility. + */ + bitmap_t *bb_map; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_NAND_USE_NAND1 && !defined(__DOXYGEN__) +extern NANDDriver NANDD1; +#endif + +#if STM32_NAND_USE_NAND2 && !defined(__DOXYGEN__) +extern NANDDriver NANDD2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void nand_lld_init(void); + void nand_lld_start(NANDDriver *nandp); + void nand_lld_stop(NANDDriver *nandp); + uint8_t nand_lld_erase(NANDDriver *nandp, uint8_t *addr, size_t addrlen); + void nand_lld_read_data(NANDDriver *nandp, uint16_t *data, + size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc); + void nand_lld_write_addr(NANDDriver *nandp, const uint8_t *addr, size_t len); + void nand_lld_write_cmd(NANDDriver *nandp, uint8_t cmd); + uint8_t nand_lld_write_data(NANDDriver *nandp, const uint16_t *data, + size_t datalen, uint8_t *addr, size_t addrlen, uint32_t *ecc); + uint8_t nand_lld_read_status(NANDDriver *nandp); + void nand_lld_reset(NANDDriver *nandp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_NAND */ + +#endif /* HAL_NAND_LLD_H_ */ + +/** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.c new file mode 100644 index 0000000..66f7b80 --- /dev/null +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.c @@ -0,0 +1,172 @@ +/* + ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + SDRAM routines added by Nick Klimov aka progfin. + */ + +/** + * @file hal_fsmc_sdram.c + * @brief SDRAM Driver subsystem low level driver source. + * + * @addtogroup SDRAM + * @{ + */ + +#include "hal.h" + +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F745xx) || defined(STM32F746xx) || \ + defined(STM32F756xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || \ + defined(STM32F779xx)) + +#if (HAL_USE_SDRAM == TRUE) || defined(__DOXYGEN__) + +#include "hal_sdram_lld.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/** + * FMC_Command_Mode + */ +#define FMCCM_NORMAL ((uint32_t)0x00000000) +#define FMCCM_CLK_ENABLED ((uint32_t)0x00000001) +#define FMCCM_PALL ((uint32_t)0x00000002) +#define FMCCM_AUTO_REFRESH ((uint32_t)0x00000003) +#define FMCCM_LOAD_MODE ((uint32_t)0x00000004) +#define FMCCM_SELFREFRESH ((uint32_t)0x00000005) +#define FMCCM_POWER_DOWN ((uint32_t)0x00000006) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ +/** + * @brief SDRAM driver identifier. + */ +SDRAMDriver SDRAMD1; + +/*===========================================================================*/ +/* Driver local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Wait until the SDRAM controller is ready. + * + * @notapi + */ +static void sdram_lld_wait_ready(void) { + /* Wait until the SDRAM controller is ready */ + while (SDRAMD1.sdram->SDSR & FMC_SDSR_BUSY); +} + +/** + * @brief Executes the SDRAM memory initialization sequence. + * + * @param[in] cfgp pointer to the @p SDRAMConfig object + * + * @notapi + */ +static void sdram_lld_init_sequence(const SDRAMConfig *cfgp) { + + uint32_t command_target = 0; + +#if STM32_SDRAM_USE_SDRAM1 + command_target |= FMC_SDCMR_CTB1; +#endif +#if STM32_SDRAM_USE_SDRAM2 + command_target |= FMC_SDCMR_CTB2; +#endif + + /* Step 3: Configure a clock configuration enable command.*/ + sdram_lld_wait_ready(); + SDRAMD1.sdram->SDCMR = FMCCM_CLK_ENABLED | command_target; + + /* Step 4: Insert delay (tipically 100uS).*/ + osalThreadSleepMilliseconds(1); + + /* Step 5: Configure a PALL (precharge all) command.*/ + sdram_lld_wait_ready(); + SDRAMD1.sdram->SDCMR = FMCCM_PALL | command_target; + + /* Step 6.1: Configure a Auto-Refresh command: send the first command.*/ + sdram_lld_wait_ready(); + SDRAMD1.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target | + (cfgp->sdcmr & FMC_SDCMR_NRFS); + + /* Step 6.2: Send the second command.*/ + sdram_lld_wait_ready(); + SDRAMD1.sdram->SDCMR = FMCCM_AUTO_REFRESH | command_target | + (cfgp->sdcmr & FMC_SDCMR_NRFS); + + /* Step 7: Program the external memory mode register.*/ + sdram_lld_wait_ready(); + SDRAMD1.sdram->SDCMR = FMCCM_LOAD_MODE | command_target | + (cfgp->sdcmr & FMC_SDCMR_MRD); + + /* Step 8: Set clock.*/ + sdram_lld_wait_ready(); + SDRAMD1.sdram->SDRTR = cfgp->sdrtr & FMC_SDRTR_COUNT; + + sdram_lld_wait_ready(); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +void sdram_lld_start(SDRAMDriver *sdramp, const SDRAMConfig *cfgp) +{ + sdramp->sdram->SDCR1 = cfgp->sdcr; + sdramp->sdram->SDTR1 = cfgp->sdtr; + sdramp->sdram->SDCR2 = cfgp->sdcr; + sdramp->sdram->SDTR2 = cfgp->sdtr; + + sdram_lld_init_sequence(cfgp); +} + +void sdram_lld_stop(SDRAMDriver *sdramp) { + uint32_t command_target = 0; + +#if STM32_SDRAM_USE_SDRAM1 + command_target |= FMC_SDCMR_CTB1; +#endif +#if STM32_SDRAM_USE_SDRAM2 + command_target |= FMC_SDCMR_CTB2; +#endif + + sdramp->sdram->SDCMR = FMCCM_POWER_DOWN | command_target; +} +#endif /* STM32_USE_FSMC_SDRAM */ + +#endif /* STM32F427xx / STM32F429xx / STM32F437xx / STM32F439xx */ + +/** @} */ + diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h new file mode 100644 index 0000000..6a19728 --- /dev/null +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h @@ -0,0 +1,118 @@ +/* + ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* + SDRAM routines added by Nick Klimov aka progfin. + */ + +/** + * @file hal_fsmc_sdram.h + * @brief SDRAM Driver subsystem low level driver header. + * + * @addtogroup SDRAM + * @{ + */ + +#ifndef HAL_FMC_SDRAM_H_ +#define HAL_FMC_SDRAM_H_ + +#include "hal_fsmc.h" + +#if (HAL_USE_SDRAM == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ + +/** + * @brief SDRAM driver enable switch. + * @details If set to @p TRUE the support for SDRAM1 is included. + */ +#if !defined(STM32_SDRAM_USE_SDRAM1) || defined(__DOXYGEN__) +#define STM32_SDRAM_USE_SDRAM1 FALSE +#else +#define STM32_SDRAM1_MAP_BASE FSMC_Bank5_MAP_BASE +#endif + +/** + * @brief SDRAM driver enable switch. + * @details If set to @p TRUE the support for SDRAM2 is included. + */ +#if !defined(STM32_SDRAM_USE_SDRAM2) || defined(__DOXYGEN__) +#define STM32_SDRAM_USE_SDRAM2 FALSE +#else +#define STM32_SDRAM2_MAP_BASE FSMC_Bank6_MAP_BASE +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !STM32_SDRAM_USE_SDRAM1 && !STM32_SDRAM_USE_SDRAM2 +#error "SDRAM driver activated but no SDRAM peripheral assigned" +#endif + +#if (STM32_SDRAM_USE_SDRAM1 || STM32_SDRAM_USE_SDRAM2) && !STM32_HAS_FSMC +#error "FMC not present in the selected device" +#endif + +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F745xx) || defined(STM32F746xx) || \ + defined(STM32F756xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || \ + defined(STM32F779xx)) +#else +#error "Device is not compatible with SDRAM" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +extern SDRAMDriver SDRAMD1; + +#ifdef __cplusplus +extern "C" { +#endif + void sdram_lld_start(SDRAMDriver *sdramp, const SDRAMConfig *cfgp); + void sdram_lld_stop(SDRAMDriver *sdramp); +#ifdef __cplusplus +} +#endif + +#endif /* STM32_SDRAM_USE_SDRAM */ + +#endif /* HAL_FSMC_SDRAM_H_ */ + +/** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.c new file mode 100644 index 0000000..71ecacd --- /dev/null +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.c @@ -0,0 +1,124 @@ +/* + ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_fsmc_sram.c + * @brief SRAM Driver subsystem low level driver source. + * + * @addtogroup SRAM + * @{ + */ +#include "hal.h" + +#if (HAL_USE_SRAM == TRUE) || defined(__DOXYGEN__) + +#include "hal_sram_lld.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ +/** + * @brief SRAM1 driver identifier. + */ +#if STM32_SRAM_USE_SRAM1 || defined(__DOXYGEN__) +SRAMDriver SRAMD1; +#endif + +/** + * @brief SRAM2 driver identifier. + */ +#if STM32_SRAM_USE_SRAM2 || defined(__DOXYGEN__) +SRAMDriver SRAMD2; +#endif + +/** + * @brief SRAM3 driver identifier. + */ +#if STM32_SRAM_USE_SRAM3 || defined(__DOXYGEN__) +SRAMDriver SRAMD3; +#endif + +/** + * @brief SRAM4 driver identifier. + */ +#if STM32_SRAM_USE_SRAM4 || defined(__DOXYGEN__) +SRAMDriver SRAMD4; +#endif + +/*===========================================================================*/ +/* Driver local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Configures and activates the SRAM peripheral. + * + * @param[in] sramp pointer to the @p SRAMDriver object + * @param[in] cfgp pointer to the @p SRAMConfig object + * + * @notapi + */ +void sram_lld_start(SRAMDriver *sramp, const SRAMConfig *cfgp) { + + sramp->sram->BTR = cfgp->btr; + sramp->sram->BWTR = cfgp->bwtr; + sramp->sram->BCR = cfgp->bcr | FSMC_BCR_MBKEN; +} + +/** + * @brief Deactivates the SRAM peripheral. + * + * @param[in] sramp pointer to the @p SRAMDriver object + * + * @notapi + */ +void sram_lld_stop(SRAMDriver *sramp) { + + uint32_t mask = FSMC_BCR_MBKEN; +#if (defined(STM32F427xx) || defined(STM32F437xx) || \ + defined(STM32F429xx) || defined(STM32F439xx) || \ + defined(STM32F745xx) || defined(STM32F746xx) || \ + defined(STM32F756xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || \ + defined(STM32F779xx)) + mask |= FSMC_BCR_CCLKEN; +#endif + sramp->sram->BCR &= ~mask; +} + +#endif /* STM32_SRAM_USE_SRAM */ + +/** @} */ + diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.h new file mode 100644 index 0000000..7af18c4 --- /dev/null +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.h @@ -0,0 +1,91 @@ +/* + ChibiOS/HAL - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_fsmc_sram.h + * @brief SRAM Driver subsystem low level driver header. + * + * @addtogroup SRAM + * @{ + */ + +#ifndef HAL_FSMC_SRAM_H_ +#define HAL_FSMC_SRAM_H_ + +#include "hal_fsmc.h" + +#if (HAL_USE_SRAM == TRUE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ +/** + * @name Configuration options + * @{ + */ + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if STM32_SRAM_USE_SRAM1 && !defined(__DOXYGEN__) +extern SRAMDriver SRAMD1; +#endif + +#if STM32_SRAM_USE_SRAM2 && !defined(__DOXYGEN__) +extern SRAMDriver SRAMD2; +#endif + +#if STM32_SRAM_USE_SRAM3 && !defined(__DOXYGEN__) +extern SRAMDriver SRAMD3; +#endif + +#if STM32_SRAM_USE_SRAM4 && !defined(__DOXYGEN__) +extern SRAMDriver SRAMD4; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sram_lld_start(SRAMDriver *sramp, const SRAMConfig *cfgp); + void sram_lld_stop(SRAMDriver *sramp); +#ifdef __cplusplus +} +#endif + +#endif /* STM32_SRAM_USE_SRAM */ + +#endif /* HAL_FSMC_SRAM_H_ */ + +/** @} */ diff --git a/os/hal/src/hal_fsmc.c b/os/hal/src/hal_fsmc.c index cdbb387..7d30720 100644 --- a/os/hal/src/hal_fsmc.c +++ b/os/hal/src/hal_fsmc.c @@ -23,7 +23,7 @@ */ #include "hal.h" -#if (HAL_USE_FSMC_SDRAM == TRUE) || (HAL_USE_FSMC_SRAM == TRUE) || (HAL_USE_FSMC_NAND == TRUE) || defined(__DOXYGEN__) +#if (HAL_USE_SDRAM == TRUE) || (HAL_USE_SRAM == TRUE) || (HAL_USE_NAND == TRUE) || defined(__DOXYGEN__) /*===========================================================================*/ /* Driver local definitions. */ @@ -72,27 +72,27 @@ void fsmcInit(void) { if (FSMCD1.state == FSMC_UNINIT) { FSMCD1.state = FSMC_STOP; -#if STM32_FSMC_USE_SRAM1 - FSMCD1.sram1 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE); +#if STM32_SRAM_USE_SRAM1 + FSMCD1.sram1 = (FSMC_SRAM_TypeDef *)(FSMC_Bank1_R_BASE); #endif -#if STM32_FSMC_USE_SRAM2 - FSMCD1.sram2 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8); +#if STM32_SRAM_USE_SRAM2 + FSMCD1.sram2 = (FSMC_SRAM_TypeDef *)(FSMC_Bank1_R_BASE + 8); #endif -#if STM32_FSMC_USE_SRAM3 - FSMCD1.sram3 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 2); +#if STM32_SRAM_USE_SRAM3 + FSMCD1.sram3 = (FSMC_SRAM_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 2); #endif -#if STM32_FSMC_USE_SRAM4 - FSMCD1.sram4 = (FSMC_SRAM_NOR_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 3); +#if STM32_SRAM_USE_SRAM4 + FSMCD1.sram4 = (FSMC_SRAM_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 3); #endif -#if STM32_FSMC_USE_NAND1 +#if STM32_NAND_USE_NAND1 FSMCD1.nand1 = (FSMC_NAND_TypeDef *)FSMC_Bank2_R_BASE; #endif -#if STM32_FSMC_USE_NAND2 +#if STM32_NAND_USE_NAND2 FSMCD1.nand2 = (FSMC_NAND_TypeDef *)FSMC_Bank3_R_BASE; #endif @@ -102,7 +102,7 @@ void fsmcInit(void) { defined(STM32F756xx) || defined(STM32F767xx) || \ defined(STM32F769xx) || defined(STM32F777xx) || \ defined(STM32F779xx)) - #if STM32_FSMC_USE_SDRAM1 || STM32_FSMC_USE_SDRAM2 + #if STM32_SDRAM_USE_SDRAM1 || STM32_SDRAM_USE_SDRAM2 FSMCD1.sdram = (FSMC_SDRAM_TypeDef *)FSMC_Bank5_6_R_BASE; #endif #endif @@ -176,12 +176,12 @@ void fsmcStop(FSMCDriver *fsmcp) { CH_IRQ_HANDLER(STM32_FSMC_HANDLER) { CH_IRQ_PROLOGUE(); -#if STM32_FSMC_USE_NAND1 +#if STM32_NAND_USE_NAND1 if (FSMCD1.nand1->SR & FSMC_SR_ISR_MASK) { NANDD1.isr_handler(&NANDD1); } #endif -#if STM32_FSMC_USE_NAND2 +#if STM32_NAND_USE_NAND2 if (FSMCD1.nand2->SR & FSMC_SR_ISR_MASK) { NANDD2.isr_handler(&NANDD2); } @@ -189,131 +189,6 @@ CH_IRQ_HANDLER(STM32_FSMC_HANDLER) { CH_IRQ_EPILOGUE(); } -#if (HAL_USE_FSMC_SDRAM == TRUE) - -#include "hal_fsmc_sdram_lld.h" -/** - * @brief FSMC SDRAM Driver init - */ -void fsmcSdramInit(void) { - - fsmcInit(); - SDRAMD.sdram = FSMCD1.sdram; - SDRAMD.state = SDRAM_STOP; -} - -/** - * @brief Configures and activates the SDRAM peripheral. - * - * @param[in] sdramp pointer to the @p SDRAMDriver object - * @param[in] cfgp pointer to the @p SDRAMConfig object - */ -void fsmcSdramStart(SDRAMDriver *sdramp, const SDRAMConfig *cfgp) { - - if (FSMCD1.state == FSMC_STOP) - fsmcStart(&FSMCD1); - - osalDbgAssert((sdramp->state == SDRAM_STOP) || (sdramp->state == SDRAM_READY), - "SDRAM. Invalid state."); - - if (sdramp->state == SDRAM_STOP) { - - lld_sdram_start(sdramp, cfgp); - - sdramp->state = SDRAM_READY; - } -} - -/** - * @brief Deactivates the SDRAM peripheral. - * - * @param[in] sdramp pointer to the @p SDRAMDriver object - * - * @notapi - */ -void fsmcSdramStop(SDRAMDriver *sdramp) { - - if (sdramp->state == SDRAM_READY) { - lld_sdram_stop(sdramp); - sdramp->state = SDRAM_STOP; - } -} -#endif /* HAL_USE_FSMC_SDRAM == TRUE */ - - -#if (HAL_USE_FSMC_SRAM == TRUE) - -#include "hal_fsmc_sram_lld.h" - -/** - * @brief Low level SRAM driver initialization. - * - * @notapi - */ -void fsmcSramInit(void) { - - fsmcInit(); - -#if STM32_FSMC_USE_SRAM1 - SRAMD1.sram = FSMCD1.sram1; - SRAMD1.state = SRAM_STOP; -#endif /* STM32_FSMC_USE_SRAM1 */ - -#if STM32_FSMC_USE_SRAM2 - SRAMD2.sram = FSMCD1.sram2; - SRAMD2.state = SRAM_STOP; -#endif /* STM32_FSMC_USE_SRAM2 */ - -#if STM32_FSMC_USE_SRAM3 - SRAMD3.sram = FSMCD1.sram3; - SRAMD3.state = SRAM_STOP; -#endif /* STM32_FSMC_USE_SRAM3 */ - -#if STM32_FSMC_USE_SRAM4 - SRAMD4.sram = FSMCD1.sram4; - SRAMD4.state = SRAM_STOP; -#endif /* STM32_FSMC_USE_SRAM4 */ -} - -/** - * @brief Configures and activates the SRAM peripheral. - * - * @param[in] sramp pointer to the @p SRAMDriver object - * @param[in] cfgp pointer to the @p SRAMConfig object - * - * @notapi - */ -void fsmcSramStart(SRAMDriver *sramp, const SRAMConfig *cfgp) { - - if (FSMCD1.state == FSMC_STOP) - fsmcStart(&FSMCD1); - - osalDbgAssert((sramp->state == SRAM_STOP) || (sramp->state == SRAM_READY), - "invalid state"); - - if (sramp->state == SRAM_STOP) { - lld_sram_start(sramp, cfgp); - sramp->state = SRAM_READY; - } -} - -/** - * @brief Deactivates the SRAM peripheral. - * - * @param[in] sramp pointer to the @p SRAMDriver object - * - * @notapi - */ -void fsmcSramStop(SRAMDriver *sramp) { - - if (sramp->state == SRAM_READY) { - lld_sram_stop(sramp); - sramp->state = SRAM_STOP; - } -} - -#endif /* HAL_USE_FSMC_SRAM == TRUE */ - #endif /* HAL_USE_FSMC */ /** @} */ diff --git a/os/hal/src/hal_sdram.c b/os/hal/src/hal_sdram.c new file mode 100644 index 0000000..efa876b --- /dev/null +++ b/os/hal/src/hal_sdram.c @@ -0,0 +1,122 @@ +/* + ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio + Copyright (C) 2017 Fabien Poussin (fabien.poussin (at) google's mail) + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in sdramliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_sdram.c + * @brief SDRAM Driver code. + * + * @addtogroup SDRAM + * @{ + */ + +#include "hal.h" + +#if HAL_USE_SDRAM || defined(__DOXYGEN__) + + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +#include "hal_sdram_lld.h" + +/** + * @brief SDRAM Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void sdramInit(void) { + fsmcInit(); + sdramObjectInit(&SDRAMD1); +} + +/** + * @brief Initializes the standard part of a @p SDRAMDriver structure. + * + * @param[out] sdramp pointer to the @p SDRAMDriver object + * + * @init + */ +void sdramObjectInit(SDRAMDriver *sdramp) { + + sdramp->sdram = FSMCD1.sdram; + sdramp->state = SDRAM_STOP; +} + +/** + * @brief Configures and activates the SDRAM peripheral. + * + * @param[in] sdramp pointer to the @p SDRAMDriver object + * @param[in] config pointer to the @p SDRAMConfig object + * + * @api + */ +void sdramStart(SDRAMDriver *sdramp, const SDRAMConfig *config) { + + osalDbgCheck((sdramp != NULL) && (config != NULL)); + + if (FSMCD1.state == FSMC_STOP) + fsmcStart(&FSMCD1); + + osalSysLock(); + osalDbgAssert((sdramp->state == SDRAM_STOP) || (sdramp->state == SDRAM_READY), + "invalid state"); + sdram_lld_start(sdramp, config); + sdramp->state = SDRAM_READY; + osalSysUnlock(); +} + +/** + * @brief Deactivates the SDRAM peripheral. + * + * @param[in] sdramp pointer to the @p SDRAMDriver object + * + * @api + */ +void sdramStop(SDRAMDriver *sdramp) { + + osalDbgCheck(sdramp != NULL); + + osalSysLock(); + osalDbgAssert((sdramp->state == SDRAM_STOP) || (sdramp->state == SDRAM_READY), + "invalid state"); + sdram_lld_stop(sdramp); + sdramp->state = SDRAM_STOP; + osalSysUnlock(); +} + +#endif /* HAL_USE_SDRAM */ + +/** @} */ diff --git a/os/hal/src/hal_sram.c b/os/hal/src/hal_sram.c new file mode 100644 index 0000000..892e9a2 --- /dev/null +++ b/os/hal/src/hal_sram.c @@ -0,0 +1,146 @@ +/* + ChibiOS - Copyright (C) 2006..2017 Giovanni Di Sirio + Copyright (C) 2017 Fabien Poussin (fabien.poussin (at) google's mail) + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in sramliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file hal_sram.c + * @brief SRAM Driver code. + * + * @addtogroup SRAM + * @{ + */ + +#include "hal.h" + +#if HAL_USE_SRAM || defined(__DOXYGEN__) + + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +#include "hal_sram_lld.h" + +/** + * @brief SRAM Driver initialization. + * @note This function is implicitly invoked by @p halInit(), there is + * no need to explicitly initialize the driver. + * + * @init + */ +void sramInit(void) { + + fsmcInit(); + +#if STM32_SRAM_USE_SRAM1 + SRAMD1.sram = FSMCD1.sram1; + SRAMD1.state = SRAM_STOP; + sramObjectInit(&SRAMD1); +#endif /* STM32_SRAM_USE_SRAM1 */ + +#if STM32_SRAM_USE_SRAM2 + SRAMD2.sram = FSMCD1.sram2; + SRAMD2.state = SRAM_STOP; + sramObjectInit(&SRAMD2); +#endif /* STM32_SRAM_USE_SRAM2 */ + +#if STM32_SRAM_USE_SRAM3 + SRAMD3.sram = FSMCD1.sram3; + SRAMD3.state = SRAM_STOP; + sramObjectInit(&SRAMD3); +#endif /* STM32_SRAM_USE_SRAM3 */ + +#if STM32_SRAM_USE_SRAM4 + SRAMD4.sram = FSMCD1.sram4; + SRAMD4.state = SRAM_STOP; + sramObjectInit(&SRAMD4); +#endif /* STM32_SRAM_USE_SRAM4 */ + +} + +/** + * @brief Initializes the standard part of a @p SRAMDriver structure. + * + * @param[out] sramp pointer to the @p SRAMDriver object + * + * @init + */ +void sramObjectInit(SRAMDriver *sramp) { + + sramp->state = SRAM_STOP; +} + +/** + * @brief Configures and activates the SRAM peripheral. + * + * @param[in] sramp pointer to the @p SRAMDriver object + * @param[in] config pointer to the @p SRAMConfig object + * + * @api + */ +void sramStart(SRAMDriver *sramp, const SRAMConfig *config) { + + osalDbgCheck((sramp != NULL) && (config != NULL)); + + if (FSMCD1.state == FSMC_STOP) + fsmcStart(&FSMCD1); + + osalSysLock(); + osalDbgAssert((sramp->state == SRAM_STOP) || (sramp->state == SRAM_READY), + "invalid state"); + sram_lld_start(sramp, config); + sramp->state = SRAM_READY; + osalSysUnlock(); +} + +/** + * @brief Deactivates the SRAM peripheral. + * + * @param[in] sramp pointer to the @p SRAMDriver object + * + * @api + */ +void sramStop(SRAMDriver *sramp) { + + osalDbgCheck(sramp != NULL); + + osalSysLock(); + osalDbgAssert((sramp->state == SRAM_STOP) || (sramp->state == SRAM_READY), + "invalid state"); + sram_lld_stop(sramp); + sramp->state = SRAM_STOP; + osalSysUnlock(); +} + +#endif /* HAL_USE_SRAM */ + +/** @} */ diff --git a/testhal/STM32/STM32F0xx/COMP/mcuconf_community.h b/testhal/STM32/STM32F0xx/COMP/mcuconf_community.h index 1be93a6..0af8b15 100644 --- a/testhal/STM32/STM32F0xx/COMP/mcuconf_community.h +++ b/testhal/STM32/STM32F0xx/COMP/mcuconf_community.h @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 diff --git a/testhal/STM32/STM32F0xx/crc/mcuconf_community.h b/testhal/STM32/STM32F0xx/crc/mcuconf_community.h index 1ebe24c..3b9709a 100644 --- a/testhal/STM32/STM32F0xx/crc/mcuconf_community.h +++ b/testhal/STM32/STM32F0xx/crc/mcuconf_community.h @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 diff --git a/testhal/STM32/STM32F0xx/onewire/mcuconf_community.h b/testhal/STM32/STM32F0xx/onewire/mcuconf_community.h index 1ebe24c..3b9709a 100644 --- a/testhal/STM32/STM32F0xx/onewire/mcuconf_community.h +++ b/testhal/STM32/STM32F0xx/onewire/mcuconf_community.h @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 diff --git a/testhal/STM32/STM32F0xx/qei/mcuconf_community.h b/testhal/STM32/STM32F0xx/qei/mcuconf_community.h index 1ebe24c..3b9709a 100644 --- a/testhal/STM32/STM32F0xx/qei/mcuconf_community.h +++ b/testhal/STM32/STM32F0xx/qei/mcuconf_community.h @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 diff --git a/testhal/STM32/STM32F1xx/onewire/mcuconf_community.h b/testhal/STM32/STM32F1xx/onewire/mcuconf_community.h index 1ebe24c..3b9709a 100644 --- a/testhal/STM32/STM32F1xx/onewire/mcuconf_community.h +++ b/testhal/STM32/STM32F1xx/onewire/mcuconf_community.h @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 diff --git a/testhal/STM32/STM32F1xx/qei/mcuconf_community.h b/testhal/STM32/STM32F1xx/qei/mcuconf_community.h index 1ebe24c..3b9709a 100644 --- a/testhal/STM32/STM32F1xx/qei/mcuconf_community.h +++ b/testhal/STM32/STM32F1xx/qei/mcuconf_community.h @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 diff --git a/testhal/STM32/STM32F3xx/COMP/mcuconf_community.h b/testhal/STM32/STM32F3xx/COMP/mcuconf_community.h index 1ebe24c..3b9709a 100644 --- a/testhal/STM32/STM32F3xx/COMP/mcuconf_community.h +++ b/testhal/STM32/STM32F3xx/COMP/mcuconf_community.h @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 diff --git a/testhal/STM32/STM32F3xx/EEProm/mcuconf_community.h b/testhal/STM32/STM32F3xx/EEProm/mcuconf_community.h index 1ebe24c..3b9709a 100644 --- a/testhal/STM32/STM32F3xx/EEProm/mcuconf_community.h +++ b/testhal/STM32/STM32F3xx/EEProm/mcuconf_community.h @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 diff --git a/testhal/STM32/STM32F3xx/OPAMP/mcuconf_community.h b/testhal/STM32/STM32F3xx/OPAMP/mcuconf_community.h index b862d6e..d62e390 100644 --- a/testhal/STM32/STM32F3xx/OPAMP/mcuconf_community.h +++ b/testhal/STM32/STM32F3xx/OPAMP/mcuconf_community.h @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 diff --git a/testhal/STM32/STM32F3xx/TIMCAP/mcuconf_community.h b/testhal/STM32/STM32F3xx/TIMCAP/mcuconf_community.h index a462bae..822b972 100644 --- a/testhal/STM32/STM32F3xx/TIMCAP/mcuconf_community.h +++ b/testhal/STM32/STM32F3xx/TIMCAP/mcuconf_community.h @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 diff --git a/testhal/STM32/STM32F4xx/EICU/mcuconf_community.h b/testhal/STM32/STM32F4xx/EICU/mcuconf_community.h index 36e182b..c6b0466 100644 --- a/testhal/STM32/STM32F4xx/EICU/mcuconf_community.h +++ b/testhal/STM32/STM32F4xx/EICU/mcuconf_community.h @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/halconf_community.h b/testhal/STM32/STM32F4xx/FSMC_NAND/halconf_community.h index 20fd46c..a72fba8 100644 --- a/testhal/STM32/STM32F4xx/FSMC_NAND/halconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_NAND/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC TRUE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/main.c b/testhal/STM32/STM32F4xx/FSMC_NAND/main.c index 73c9cb3..c4e2324 100644 --- a/testhal/STM32/STM32F4xx/FSMC_NAND/main.c +++ b/testhal/STM32/STM32F4xx/FSMC_NAND/main.c @@ -78,9 +78,9 @@ #define NAND_TEST_KILL_BLOCK 8000 #endif -#if STM32_NAND_USE_FSMC_NAND1 +#if STM32_NAND_USE_NAND1 #define NAND NANDD1 -#elif STM32_NAND_USE_FSMC_NAND2 +#elif STM32_NAND_USE_NAND2 #define NAND NANDD2 #else #error "You should enable at least one NAND interface" diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf_community.h b/testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf_community.h index 108d84c..bba7f08 100644 --- a/testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf_community.h @@ -24,8 +24,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 TRUE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 TRUE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 @@ -34,18 +34,16 @@ /* * FSMC SRAM driver system settings. */ -#define STM32_USE_FSMC_SRAM FALSE -#define STM32_SRAM_USE_FSMC_SRAM1 FALSE -#define STM32_SRAM_USE_FSMC_SRAM2 FALSE -#define STM32_SRAM_USE_FSMC_SRAM3 FALSE -#define STM32_SRAM_USE_FSMC_SRAM4 FALSE +#define STM32_SRAM_USE_SRAM1 FALSE +#define STM32_SRAM_USE_SRAM2 FALSE +#define STM32_SRAM_USE_SRAM3 FALSE +#define STM32_SRAM_USE_SRAM4 FALSE /* * FSMC SDRAM driver system settings. */ -#define STM32_USE_FSMC_SDRAM FALSE -#define STM32_SDRAM_USE_FSMC_SDRAM1 FALSE -#define STM32_SDRAM_USE_FSMC_SDRAM2 TRUE +#define STM32_SDRAM_USE_SDRAM1 FALSE +#define STM32_SDRAM_USE_SDRAM2 FALSE /* * TIMCAP driver system settings. diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h b/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h index 9ad41fd..91ad637 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h @@ -27,24 +27,30 @@ /** * @brief Enables the FSMC subsystem. */ -#if !defined(HAL_USE_FSMC_SDRAM) || defined(__DOXYGEN__) -#define HAL_USE_FSMC_SDRAM TRUE +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC TRUE #endif /** - * @brief Enables the FSMC subsystem. + * @brief Enables the SDRAM subsystem. */ -#if !defined(HAL_USE_FSMC_SRAM) || defined(__DOXYGEN__) -#define HAL_USE_FSMC_SRAM FALSE +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM TRUE #endif /** - * @brief Enables the FSMC subsystem. + * @brief Enables the SRAM subsystem. */ -#if !defined(HAL_USE_FSMC_NAND) || defined(__DOXYGEN__) -#define HAL_USE_FSMC_NAND FALSE +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE #endif +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif /** * @brief Enables the 1-wire subsystem. */ diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c b/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c index 1ff7740..0d3feee 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c +++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/main.c @@ -183,8 +183,8 @@ int main(void) { halInit(); chSysInit(); - fsmcSdramInit(); - fsmcSdramStart(&SDRAMD, &sdram_cfg); + sdramInit(); + sdramStart(&SDRAMD1, &sdram_cfg); membench(); memtest(); diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf_community.h b/testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf_community.h index 4494929..4e08dfe 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/mcuconf_community.h @@ -22,30 +22,30 @@ #define STM32_FSMC_USE_FSMC1 TRUE #define STM32_FSMC_FSMC1_IRQ_PRIORITY 10 #define STM32_FSMC_DMA_CHN 0x03010201 -#define STM32_FSMC_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_FSMC_DMA_PRIORITY 0 -#define STM32_FSMC_DMA_ERROR_HOOK(nandp) osalSysHalt("FSMC DMA failure") /* * FSMC NAND driver system settings. */ -#define STM32_FSMC_USE_NAND1 FALSE -#define STM32_FSMC_USE_NAND2 FALSE -#define STM32_FSMC_USE_NAND_EXT_INT FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE +#define STM32_NAND_USE_EXT_INT FALSE +#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_NAND_DMA_PRIORITY 0 +#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure") /* * FSMC SRAM driver system settings. */ -#define STM32_FSMC_USE_SRAM1 FALSE -#define STM32_FSMC_USE_SRAM2 FALSE -#define STM32_FSMC_USE_SRAM3 FALSE -#define STM32_FSMC_USE_SRAM4 FALSE +#define STM32_SRAM_USE_SRAM1 FALSE +#define STM32_SRAM_USE_SRAM2 FALSE +#define STM32_SRAM_USE_SRAM3 FALSE +#define STM32_SRAM_USE_SRAM4 FALSE /* * FSMC SDRAM driver system settings. */ -#define STM32_FSMC_USE_SDRAM1 FALSE -#define STM32_FSMC_USE_SDRAM2 TRUE +#define STM32_SDRAM_USE_SDRAM1 FALSE +#define STM32_SDRAM_USE_SDRAM2 TRUE /* * TIMCAP driver system settings. diff --git a/testhal/STM32/STM32F4xx/FSMC_SRAM/halconf_community.h b/testhal/STM32/STM32F4xx/FSMC_SRAM/halconf_community.h index f9cfcbe..a19553b 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SRAM/halconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_SRAM/halconf_community.h @@ -27,22 +27,29 @@ /** * @brief Enables the FSMC subsystem. */ -#if !defined(HAL_USE_FSMC_SDRAM) || defined(__DOXYGEN__) -#define HAL_USE_FSMC_SDRAM FALSE +#if !defined(HAL_USE_FSMC) || defined(__DOXYGEN__) +#define HAL_USE_FSMC TRUE #endif /** - * @brief Enables the FSMC subsystem. + * @brief Enables the SDRAM subsystem. */ -#if !defined(HAL_USE_FSMC_SRAM) || defined(__DOXYGEN__) -#define HAL_USE_FSMC_SRAM TRUE +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE #endif /** - * @brief Enables the FSMC subsystem. + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM TRUE +#endif + +/** + * @brief Enables the NAND subsystem. */ -#if !defined(HAL_USE_FSMC_NAND) || defined(__DOXYGEN__) -#define HAL_USE_FSMC_NAND FALSE +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE #endif /** diff --git a/testhal/STM32/STM32F4xx/FSMC_SRAM/main.c b/testhal/STM32/STM32F4xx/FSMC_SRAM/main.c index 6413835..4bd94f8 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SRAM/main.c +++ b/testhal/STM32/STM32F4xx/FSMC_SRAM/main.c @@ -172,8 +172,8 @@ int main(void) { halInit(); chSysInit(); - fsmcSramInit(); - fsmcSramStart(&SRAMD4, &sram_cfg); + sramInit(); + sramStart(&SRAMD4, &sram_cfg); membench(); memtest(); diff --git a/testhal/STM32/STM32F4xx/FSMC_SRAM/mcuconf_community.h b/testhal/STM32/STM32F4xx/FSMC_SRAM/mcuconf_community.h index 8abb48d..b601a5f 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SRAM/mcuconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_SRAM/mcuconf_community.h @@ -22,30 +22,30 @@ #define STM32_FSMC_USE_FSMC1 TRUE #define STM32_FSMC_FSMC1_IRQ_PRIORITY 10 #define STM32_FSMC_DMA_CHN 0x03010201 -#define STM32_FSMC_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) -#define STM32_FSMC_DMA_PRIORITY 0 -#define STM32_FSMC_DMA_ERROR_HOOK(nandp) osalSysHalt("FSMC DMA failure") /* * FSMC NAND driver system settings. */ -#define STM32_FSMC_USE_NAND1 FALSE -#define STM32_FSMC_USE_NAND2 FALSE -#define STM32_FSMC_USE_NAND_EXT_INT FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE +#define STM32_NAND_USE_EXT_INT FALSE +#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_NAND_DMA_PRIORITY 0 +#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure") /* * FSMC SRAM driver system settings. */ -#define STM32_FSMC_USE_SRAM1 FALSE -#define STM32_FSMC_USE_SRAM2 FALSE -#define STM32_FSMC_USE_SRAM3 FALSE -#define STM32_FSMC_USE_SRAM4 TRUE +#define STM32_SRAM_USE_SRAM1 FALSE +#define STM32_SRAM_USE_SRAM2 FALSE +#define STM32_SRAM_USE_SRAM3 FALSE +#define STM32_SRAM_USE_SRAM4 TRUE /* * FSMC SDRAM driver system settings. */ -#define STM32_FSMC_USE_SDRAM1 FALSE -#define STM32_FSMC_USE_SDRAM2 FALSE +#define STM32_SDRAM_USE_SDRAM1 FALSE +#define STM32_SDRAM_USE_SDRAM2 FALSE /* * TIMCAP driver system settings. diff --git a/testhal/STM32/STM32F4xx/USB_HOST/mcuconf_community.h b/testhal/STM32/STM32F4xx/USB_HOST/mcuconf_community.h index 1ebe24c..3b9709a 100644 --- a/testhal/STM32/STM32F4xx/USB_HOST/mcuconf_community.h +++ b/testhal/STM32/STM32F4xx/USB_HOST/mcuconf_community.h @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 diff --git a/testhal/STM32/STM32F4xx/onewire/mcuconf_community.h b/testhal/STM32/STM32F4xx/onewire/mcuconf_community.h index 1ebe24c..3b9709a 100644 --- a/testhal/STM32/STM32F4xx/onewire/mcuconf_community.h +++ b/testhal/STM32/STM32F4xx/onewire/mcuconf_community.h @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 diff --git a/testhal/STM32/STM32F7xx/USB_MSD/mcuconf_community.h b/testhal/STM32/STM32F7xx/USB_MSD/mcuconf_community.h index 1ebe24c..3b9709a 100644 --- a/testhal/STM32/STM32F7xx/USB_MSD/mcuconf_community.h +++ b/testhal/STM32/STM32F7xx/USB_MSD/mcuconf_community.h @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 diff --git a/testhal/STM32/STM32L0xx/COMP/mcuconf_community.h b/testhal/STM32/STM32L0xx/COMP/mcuconf_community.h index 142ed57..e771876 100644 --- a/testhal/STM32/STM32L0xx/COMP/mcuconf_community.h +++ b/testhal/STM32/STM32L0xx/COMP/mcuconf_community.h @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 diff --git a/tools/templates/mcuconf_community.h b/tools/templates/mcuconf_community.h index b862d6e..d62e390 100644 --- a/tools/templates/mcuconf_community.h +++ b/tools/templates/mcuconf_community.h @@ -23,8 +23,8 @@ /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_FSMC_NAND1 FALSE -#define STM32_NAND_USE_FSMC_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE #define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) #define STM32_NAND_DMA_PRIORITY 0 -- cgit v1.2.3 From 05913b8055080125374af839f0f6baba53792d1b Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Wed, 30 Oct 2019 13:03:32 +0100 Subject: Cleaning FSMC code --- os/hal/include/hal_community.h | 1 - os/hal/include/hal_sdram.h | 2 +- os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h | 2 +- os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h | 6 +++--- os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.h | 6 +++--- os/hal/src/hal_fsmc.c | 9 ++++++++- testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf_community.h | 13 ++++++------- 7 files changed, 22 insertions(+), 17 deletions(-) diff --git a/os/hal/include/hal_community.h b/os/hal/include/hal_community.h index 889da4f..d4924f5 100644 --- a/os/hal/include/hal_community.h +++ b/os/hal/include/hal_community.h @@ -96,7 +96,6 @@ /* Shared headers.*/ /* Normal drivers.*/ -#include "hal_nand.h" #include "hal_eicu.h" #include "hal_rng.h" #include "hal_usbh.h" diff --git a/os/hal/include/hal_sdram.h b/os/hal/include/hal_sdram.h index 297b715..af4a1ad 100644 --- a/os/hal/include/hal_sdram.h +++ b/os/hal/include/hal_sdram.h @@ -239,6 +239,6 @@ extern "C" { #endif /* HAL_USE_SDRAM */ -#endif /* SDRAM_H_ */ +#endif /* HAL_SDRAM_H_ */ /** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h index c4f8595..51f2b95 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.h @@ -15,7 +15,7 @@ */ /** - * @file hal_fsmc_nand_lld.h + * @file hal_nand_lld.h * @brief FSMC NAND Driver subsystem low level driver header. * * @addtogroup NAND diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h index 6a19728..3991695 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h @@ -25,8 +25,8 @@ * @{ */ -#ifndef HAL_FMC_SDRAM_H_ -#define HAL_FMC_SDRAM_H_ +#ifndef HAL_SDRAM_LLD_H_ +#define HAL_SDRAM_LLD_H_ #include "hal_fsmc.h" @@ -113,6 +113,6 @@ extern "C" { #endif /* STM32_SDRAM_USE_SDRAM */ -#endif /* HAL_FSMC_SDRAM_H_ */ +#endif /* HAL_SDRAM_LLD_H_ */ /** @} */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.h index 7af18c4..857a96e 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_sram_lld.h @@ -22,8 +22,8 @@ * @{ */ -#ifndef HAL_FSMC_SRAM_H_ -#define HAL_FSMC_SRAM_H_ +#ifndef HAL_SRAM_LLD_H_ +#define HAL_SRAM_LLD_H_ #include "hal_fsmc.h" @@ -86,6 +86,6 @@ extern "C" { #endif /* STM32_SRAM_USE_SRAM */ -#endif /* HAL_FSMC_SRAM_H_ */ +#endif /* HAL_SRAM_LLD_H_ */ /** @} */ diff --git a/os/hal/src/hal_fsmc.c b/os/hal/src/hal_fsmc.c index 7d30720..c3f2a99 100644 --- a/os/hal/src/hal_fsmc.c +++ b/os/hal/src/hal_fsmc.c @@ -71,7 +71,7 @@ void fsmcInit(void) { if (FSMCD1.state == FSMC_UNINIT) { FSMCD1.state = FSMC_STOP; - +#if HAL_USE_SRAM #if STM32_SRAM_USE_SRAM1 FSMCD1.sram1 = (FSMC_SRAM_TypeDef *)(FSMC_Bank1_R_BASE); #endif @@ -87,7 +87,9 @@ void fsmcInit(void) { #if STM32_SRAM_USE_SRAM4 FSMCD1.sram4 = (FSMC_SRAM_TypeDef *)(FSMC_Bank1_R_BASE + 8 * 3); #endif +#endif +#if HAL_USE_NAND #if STM32_NAND_USE_NAND1 FSMCD1.nand1 = (FSMC_NAND_TypeDef *)FSMC_Bank2_R_BASE; #endif @@ -95,7 +97,9 @@ void fsmcInit(void) { #if STM32_NAND_USE_NAND2 FSMCD1.nand2 = (FSMC_NAND_TypeDef *)FSMC_Bank3_R_BASE; #endif +#endif +#if HAL_USE_SDRAM #if (defined(STM32F427xx) || defined(STM32F437xx) || \ defined(STM32F429xx) || defined(STM32F439xx) || \ defined(STM32F745xx) || defined(STM32F746xx) || \ @@ -105,6 +109,7 @@ void fsmcInit(void) { #if STM32_SDRAM_USE_SDRAM1 || STM32_SDRAM_USE_SDRAM2 FSMCD1.sdram = (FSMC_SDRAM_TypeDef *)FSMC_Bank5_6_R_BASE; #endif +#endif #endif } } @@ -176,6 +181,7 @@ void fsmcStop(FSMCDriver *fsmcp) { CH_IRQ_HANDLER(STM32_FSMC_HANDLER) { CH_IRQ_PROLOGUE(); +#if HAL_USE_NAND #if STM32_NAND_USE_NAND1 if (FSMCD1.nand1->SR & FSMC_SR_ISR_MASK) { NANDD1.isr_handler(&NANDD1); @@ -185,6 +191,7 @@ CH_IRQ_HANDLER(STM32_FSMC_HANDLER) { if (FSMCD1.nand2->SR & FSMC_SR_ISR_MASK) { NANDD2.isr_handler(&NANDD2); } +#endif #endif CH_IRQ_EPILOGUE(); } diff --git a/testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf_community.h b/testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf_community.h index bba7f08..0a5db9b 100644 --- a/testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_NAND/mcuconf_community.h @@ -34,17 +34,16 @@ /* * FSMC SRAM driver system settings. */ -#define STM32_SRAM_USE_SRAM1 FALSE -#define STM32_SRAM_USE_SRAM2 FALSE -#define STM32_SRAM_USE_SRAM3 FALSE -#define STM32_SRAM_USE_SRAM4 FALSE +#define STM32_SRAM_USE_SRAM1 FALSE +#define STM32_SRAM_USE_SRAM2 FALSE +#define STM32_SRAM_USE_SRAM3 FALSE +#define STM32_SRAM_USE_SRAM4 FALSE /* * FSMC SDRAM driver system settings. */ -#define STM32_SDRAM_USE_SDRAM1 FALSE -#define STM32_SDRAM_USE_SDRAM2 FALSE - +#define STM32_SDRAM_USE_SDRAM1 FALSE +#define STM32_SDRAM_USE_SDRAM2 FALSE /* * TIMCAP driver system settings. */ -- cgit v1.2.3 From b15b68c1c4dd59a846c36e52ef4502eb8ad84a5a Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Wed, 30 Oct 2019 13:12:29 +0100 Subject: Fixed default hal defines --- os/hal/include/hal_community.h | 4 ++-- os/hal/include/hal_fsmc.h | 1 + os/hal/include/hal_nand.h | 1 + 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/os/hal/include/hal_community.h b/os/hal/include/hal_community.h index d4924f5..435115b 100644 --- a/os/hal/include/hal_community.h +++ b/os/hal/include/hal_community.h @@ -84,11 +84,11 @@ #endif #if !defined(HAL_USE_SDRAM) -#define HAL_USE_FSMC FALSE +#define HAL_USE_SDRAM FALSE #endif #if !defined(HAL_USE_SRAM) -#define HAL_USE_FSMC FALSE +#define HAL_USE_SRAM FALSE #endif /* Abstract interfaces.*/ diff --git a/os/hal/include/hal_fsmc.h b/os/hal/include/hal_fsmc.h index 3b27941..3c5d999 100644 --- a/os/hal/include/hal_fsmc.h +++ b/os/hal/include/hal_fsmc.h @@ -256,6 +256,7 @@ typedef struct { * @name Configuration options * @{ */ + /** * @brief FSMC driver enable switch. * @details If set to @p TRUE the support for FSMC is included. diff --git a/os/hal/include/hal_nand.h b/os/hal/include/hal_nand.h index f907152..0c95e89 100644 --- a/os/hal/include/hal_nand.h +++ b/os/hal/include/hal_nand.h @@ -51,6 +51,7 @@ /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ + /** * @brief Enables the mutual exclusion APIs on the NAND. */ -- cgit v1.2.3 From f6b1a12ecf14e4c703b18f3d13537e878215e91a Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Wed, 30 Oct 2019 13:19:08 +0100 Subject: Fixed DMA2D example --- .../halconf_community.h | 14 ++++++++++++ demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c | 3 +-- .../mcuconf_community.h | 26 ++++++++++++---------- os/hal/include/hal_sdram.h | 2 +- os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h | 2 +- .../STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h | 1 + 6 files changed, 32 insertions(+), 16 deletions(-) diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/halconf_community.h b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/halconf_community.h index c28b90b..8082fce 100644 --- a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/halconf_community.h +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC TRUE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM TRUE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c index 55a66a5..ce99e3b 100644 --- a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c @@ -23,7 +23,6 @@ #include "usbcfg.h" #endif -#include "hal_fsmc_sdram.h" #include "ili9341.h" #include "hal_stm32_ltdc.h" #include "hal_stm32_dma2d.h" @@ -557,7 +556,7 @@ int main(void) { * Initialise FSMC for SDRAM. */ sdramInit(); - sdramStart(&SDRAMD, &sdram_cfg); + sdramStart(&SDRAMD1, &sdram_cfg); sdram_bulk_erase(); /* diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf_community.h b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf_community.h index 6ecfe91..2528ef4 100644 --- a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf_community.h +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf_community.h @@ -19,29 +19,31 @@ */ #define STM32_FSMC_USE_FSMC1 TRUE #define STM32_FSMC_FSMC1_IRQ_PRIORITY 10 +#define STM32_FSMC_DMA_CHN 0x03010201 /* * FSMC NAND driver system settings. */ -#define STM32_NAND_USE_NAND1 FALSE -#define STM32_NAND_USE_NAND2 FALSE +#define STM32_NAND_USE_NAND1 FALSE +#define STM32_NAND_USE_NAND2 FALSE #define STM32_NAND_USE_EXT_INT FALSE +#define STM32_NAND_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_NAND_DMA_PRIORITY 0 +#define STM32_NAND_DMA_ERROR_HOOK(nandp) osalSysHalt("DMA failure") /* - * FSMC SDRAM driver system settings. + * FSMC SRAM driver system settings. */ -#define STM32_USE_FSMC_SDRAM TRUE -#define STM32_SDRAM_USE_FSMC_SDRAM1 FALSE -#define STM32_SDRAM_USE_FSMC_SDRAM2 TRUE +#define STM32_SRAM_USE_SRAM1 FALSE +#define STM32_SRAM_USE_SRAM2 FALSE +#define STM32_SRAM_USE_SRAM3 FALSE +#define STM32_SRAM_USE_SRAM4 FALSE /* - * FSMC SRAM driver system settings. + * FSMC SDRAM driver system settings. */ -#define STM32_USE_FSMC_SRAM FALSE -#define STM32_SRAM_USE_FSMC_SRAM1 FALSE -#define STM32_SRAM_USE_FSMC_SRAM2 FALSE -#define STM32_SRAM_USE_FSMC_SRAM3 FALSE -#define STM32_SRAM_USE_FSMC_SRAM4 FALSE +#define STM32_SDRAM_USE_SDRAM1 FALSE +#define STM32_SDRAM_USE_SDRAM2 TRUE /* * LTDC driver system settings. diff --git a/os/hal/include/hal_sdram.h b/os/hal/include/hal_sdram.h index af4a1ad..eaca0fb 100644 --- a/os/hal/include/hal_sdram.h +++ b/os/hal/include/hal_sdram.h @@ -18,7 +18,7 @@ */ /** - * @file hal_fsmc_sdram.h + * @file hal_sdram.h * @brief SDRAM Driver subsystem low level driver header. * * @addtogroup SDRAM diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h index 3991695..665c570 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_sdram_lld.h @@ -18,7 +18,7 @@ */ /** - * @file hal_fsmc_sdram.h + * @file hal_sdram.h * @brief SDRAM Driver subsystem low level driver header. * * @addtogroup SDRAM diff --git a/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h b/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h index 91ad637..51524e1 100644 --- a/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h +++ b/testhal/STM32/STM32F4xx/FSMC_SDRAM/halconf_community.h @@ -51,6 +51,7 @@ #if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) #define HAL_USE_NAND FALSE #endif + /** * @brief Enables the 1-wire subsystem. */ -- cgit v1.2.3 From cf7e66ddaed1f5f0e02b79a691a84a3dbae72348 Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Wed, 30 Oct 2019 13:35:59 +0100 Subject: Updating halconf_community.h for demos/testhal --- demos/STM32/RT-STM32F303-DISCOVERY-PID/halconf_community.h | 14 ++++++++++++++ .../RT-STM32F429-DISCOVERY-TRIBUF/halconf_community.h | 14 ++++++++++++++ testhal/STM32/STM32F0xx/COMP/halconf_community.h | 14 ++++++++++++++ testhal/STM32/STM32F0xx/crc/halconf_community.h | 14 ++++++++++++++ testhal/STM32/STM32F0xx/onewire/halconf_community.h | 14 ++++++++++++++ testhal/STM32/STM32F0xx/qei/halconf_community.h | 14 ++++++++++++++ testhal/STM32/STM32F1xx/onewire/halconf_community.h | 14 ++++++++++++++ testhal/STM32/STM32F1xx/qei/halconf_community.h | 14 ++++++++++++++ testhal/STM32/STM32F3xx/COMP/halconf_community.h | 14 ++++++++++++++ testhal/STM32/STM32F3xx/EEProm/halconf_community.h | 14 ++++++++++++++ testhal/STM32/STM32F3xx/OPAMP/halconf_community.h | 14 ++++++++++++++ testhal/STM32/STM32F3xx/TIMCAP/halconf_community.h | 14 ++++++++++++++ testhal/STM32/STM32F4xx/EICU/halconf_community.h | 14 ++++++++++++++ testhal/STM32/STM32F4xx/USB_HOST/halconf_community.h | 14 ++++++++++++++ testhal/STM32/STM32F4xx/onewire/halconf_community.h | 14 ++++++++++++++ testhal/STM32/STM32F7xx/USB_MSD/halconf_community.h | 14 ++++++++++++++ testhal/STM32/STM32L0xx/COMP/halconf_community.h | 14 ++++++++++++++ 17 files changed, 238 insertions(+) diff --git a/demos/STM32/RT-STM32F303-DISCOVERY-PID/halconf_community.h b/demos/STM32/RT-STM32F303-DISCOVERY-PID/halconf_community.h index 631bb9f..246e3cb 100644 --- a/demos/STM32/RT-STM32F303-DISCOVERY-PID/halconf_community.h +++ b/demos/STM32/RT-STM32F303-DISCOVERY-PID/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC FALSE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/halconf_community.h b/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/halconf_community.h index 2e8b241..2e6d633 100644 --- a/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/halconf_community.h +++ b/demos/STM32/RT-STM32F429-DISCOVERY-TRIBUF/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC FALSE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ diff --git a/testhal/STM32/STM32F0xx/COMP/halconf_community.h b/testhal/STM32/STM32F0xx/COMP/halconf_community.h index 76d4856..3279b50 100644 --- a/testhal/STM32/STM32F0xx/COMP/halconf_community.h +++ b/testhal/STM32/STM32F0xx/COMP/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC FALSE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ diff --git a/testhal/STM32/STM32F0xx/crc/halconf_community.h b/testhal/STM32/STM32F0xx/crc/halconf_community.h index 91233ed..ad52c4b 100644 --- a/testhal/STM32/STM32F0xx/crc/halconf_community.h +++ b/testhal/STM32/STM32F0xx/crc/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC FALSE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ diff --git a/testhal/STM32/STM32F0xx/onewire/halconf_community.h b/testhal/STM32/STM32F0xx/onewire/halconf_community.h index df56d7e..42bdd72 100644 --- a/testhal/STM32/STM32F0xx/onewire/halconf_community.h +++ b/testhal/STM32/STM32F0xx/onewire/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC FALSE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ diff --git a/testhal/STM32/STM32F0xx/qei/halconf_community.h b/testhal/STM32/STM32F0xx/qei/halconf_community.h index 14fb2ca..2017e79 100644 --- a/testhal/STM32/STM32F0xx/qei/halconf_community.h +++ b/testhal/STM32/STM32F0xx/qei/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC FALSE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ diff --git a/testhal/STM32/STM32F1xx/onewire/halconf_community.h b/testhal/STM32/STM32F1xx/onewire/halconf_community.h index df56d7e..42bdd72 100644 --- a/testhal/STM32/STM32F1xx/onewire/halconf_community.h +++ b/testhal/STM32/STM32F1xx/onewire/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC FALSE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ diff --git a/testhal/STM32/STM32F1xx/qei/halconf_community.h b/testhal/STM32/STM32F1xx/qei/halconf_community.h index 14fb2ca..2017e79 100644 --- a/testhal/STM32/STM32F1xx/qei/halconf_community.h +++ b/testhal/STM32/STM32F1xx/qei/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC FALSE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ diff --git a/testhal/STM32/STM32F3xx/COMP/halconf_community.h b/testhal/STM32/STM32F3xx/COMP/halconf_community.h index 76d4856..3279b50 100644 --- a/testhal/STM32/STM32F3xx/COMP/halconf_community.h +++ b/testhal/STM32/STM32F3xx/COMP/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC FALSE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ diff --git a/testhal/STM32/STM32F3xx/EEProm/halconf_community.h b/testhal/STM32/STM32F3xx/EEProm/halconf_community.h index 75035b3..2f4cf60 100644 --- a/testhal/STM32/STM32F3xx/EEProm/halconf_community.h +++ b/testhal/STM32/STM32F3xx/EEProm/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC FALSE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ diff --git a/testhal/STM32/STM32F3xx/OPAMP/halconf_community.h b/testhal/STM32/STM32F3xx/OPAMP/halconf_community.h index 41bc0df..d56022f 100644 --- a/testhal/STM32/STM32F3xx/OPAMP/halconf_community.h +++ b/testhal/STM32/STM32F3xx/OPAMP/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC FALSE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ diff --git a/testhal/STM32/STM32F3xx/TIMCAP/halconf_community.h b/testhal/STM32/STM32F3xx/TIMCAP/halconf_community.h index dbd6deb..2ef054b 100644 --- a/testhal/STM32/STM32F3xx/TIMCAP/halconf_community.h +++ b/testhal/STM32/STM32F3xx/TIMCAP/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC FALSE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ diff --git a/testhal/STM32/STM32F4xx/EICU/halconf_community.h b/testhal/STM32/STM32F4xx/EICU/halconf_community.h index f5cb75e..007550c 100644 --- a/testhal/STM32/STM32F4xx/EICU/halconf_community.h +++ b/testhal/STM32/STM32F4xx/EICU/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC FALSE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ diff --git a/testhal/STM32/STM32F4xx/USB_HOST/halconf_community.h b/testhal/STM32/STM32F4xx/USB_HOST/halconf_community.h index c76d1ef..60452b8 100644 --- a/testhal/STM32/STM32F4xx/USB_HOST/halconf_community.h +++ b/testhal/STM32/STM32F4xx/USB_HOST/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC FALSE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ diff --git a/testhal/STM32/STM32F4xx/onewire/halconf_community.h b/testhal/STM32/STM32F4xx/onewire/halconf_community.h index df56d7e..42bdd72 100644 --- a/testhal/STM32/STM32F4xx/onewire/halconf_community.h +++ b/testhal/STM32/STM32F4xx/onewire/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC FALSE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ diff --git a/testhal/STM32/STM32F7xx/USB_MSD/halconf_community.h b/testhal/STM32/STM32F7xx/USB_MSD/halconf_community.h index 32d0271..6e804ec 100644 --- a/testhal/STM32/STM32F7xx/USB_MSD/halconf_community.h +++ b/testhal/STM32/STM32F7xx/USB_MSD/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC FALSE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ diff --git a/testhal/STM32/STM32L0xx/COMP/halconf_community.h b/testhal/STM32/STM32L0xx/COMP/halconf_community.h index 76d4856..3279b50 100644 --- a/testhal/STM32/STM32L0xx/COMP/halconf_community.h +++ b/testhal/STM32/STM32L0xx/COMP/halconf_community.h @@ -31,6 +31,20 @@ #define HAL_USE_FSMC FALSE #endif +/** + * @brief Enables the SDRAM subsystem. + */ +#if !defined(HAL_USE_SDRAM) || defined(__DOXYGEN__) +#define HAL_USE_SDRAM FALSE +#endif + +/** + * @brief Enables the SRAM subsystem. + */ +#if !defined(HAL_USE_SRAM) || defined(__DOXYGEN__) +#define HAL_USE_SRAM FALSE +#endif + /** * @brief Enables the NAND subsystem. */ -- cgit v1.2.3 From c65efdcfa1d281a8f0a29bb864e86dd0c892c156 Mon Sep 17 00:00:00 2001 From: Fabien Poussin Date: Thu, 31 Oct 2019 14:45:33 +0100 Subject: Fixed unwanted rename --- os/common/ext/CMSIS/KINETIS/MK66F18.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/os/common/ext/CMSIS/KINETIS/MK66F18.h b/os/common/ext/CMSIS/KINETIS/MK66F18.h index 2fdfbbd..432944f 100644 --- a/os/common/ext/CMSIS/KINETIS/MK66F18.h +++ b/os/common/ext/CMSIS/KINETIS/MK66F18.h @@ -14379,7 +14379,7 @@ typedef struct { __IO uint32_t AC; /**< Address and Control Register, array offset: 0x48, array step: 0x8 */ __IO uint32_t CM; /**< Control Mask, array offset: 0x4C, array step: 0x8 */ } BLOCK[2]; -} FSMC_SDRAM_TypeDef; +} SDRAM_TypeDef; /* ---------------------------------------------------------------------------- -- SDRAM Register Masks @@ -14464,7 +14464,7 @@ typedef struct { /** Peripheral SDRAM base address */ #define SDRAM_BASE (0x4000F000u) /** Peripheral SDRAM base pointer */ -#define SDRAM ((FSMC_SDRAM_TypeDef *)SDRAM_BASE) +#define SDRAM ((SDRAM_TypeDef *)SDRAM_BASE) /** Array initializer of SDRAM peripheral base addresses */ #define SDRAM_BASE_ADDRS { SDRAM_BASE } /** Array initializer of SDRAM peripheral base pointers */ -- cgit v1.2.3