From 41f2f8462a2dc71c8194703fb879e6a667fb723b Mon Sep 17 00:00:00 2001 From: Diego Ismirlian Date: Wed, 2 Oct 2019 15:14:28 -0300 Subject: Add fault handlers to ease ARM-v7m (Cortex M3/M4(F)/M7 debugging --- .../.cproject | 67 ++ .../RT-STM32F407-DISCOVERY-fault_handlers/.project | 100 +++ .../.settings/org.eclipse.cdt.core.prefs | 6 + .../RT-STM32F407-DISCOVERY-fault_handlers/Makefile | 189 ++++++ .../cfg/chconf.h | 714 +++++++++++++++++++++ .../cfg/halconf.h | 525 +++++++++++++++ .../cfg/mcuconf.h | 342 ++++++++++ .../crash_test.c | 169 +++++ .../crash_test_asm.S | 273 ++++++++ ...2F407-DISCOVERY (OpenOCD, Flash and Run).launch | 52 ++ ...-STM32F407-DISCOVERY (OpenOCD, Just Run).launch | 52 ++ .../RT-STM32F407-DISCOVERY-fault_handlers/main.c | 69 ++ .../readme.txt | 25 + .../compilers/GCC/utils/fault_handlers_v7m.c | 215 +++++++ .../compilers/GCC/utils/fault_handlers_v7m.mk | 4 + .../compilers/GCC/utils/hardfault_handler_v7m.S | 113 ++++ .../compilers/GCC/utils/port_fault_handlers.h | 52 ++ os/various/fault_handlers/fault_handlers.h | 22 + 18 files changed, 2989 insertions(+) create mode 100644 demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/.cproject create mode 100644 demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/.project create mode 100644 demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/.settings/org.eclipse.cdt.core.prefs create mode 100644 demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/Makefile create mode 100644 demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/cfg/chconf.h create mode 100644 demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/cfg/halconf.h create mode 100644 demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/cfg/mcuconf.h create mode 100644 demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/crash_test.c create mode 100644 demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/crash_test_asm.S create mode 100644 demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/debug/RT-STM32F407-DISCOVERY (OpenOCD, Flash and Run).launch create mode 100644 demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/debug/RT-STM32F407-DISCOVERY (OpenOCD, Just Run).launch create mode 100644 demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/main.c create mode 100644 demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/readme.txt create mode 100644 os/common/ports/ARMCMx/compilers/GCC/utils/fault_handlers_v7m.c create mode 100644 os/common/ports/ARMCMx/compilers/GCC/utils/fault_handlers_v7m.mk create mode 100644 os/common/ports/ARMCMx/compilers/GCC/utils/hardfault_handler_v7m.S create mode 100644 os/common/ports/ARMCMx/compilers/GCC/utils/port_fault_handlers.h create mode 100644 os/various/fault_handlers/fault_handlers.h diff --git a/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/.cproject b/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/.cproject new file mode 100644 index 0000000..84bb22d --- /dev/null +++ b/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/.cproject @@ -0,0 +1,67 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/.project b/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/.project new file mode 100644 index 0000000..34d336b --- /dev/null +++ b/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/.project @@ -0,0 +1,100 @@ + + + RT-STM32F407-DISCOVERY-fault_handlers + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + ?name? + + + + org.eclipse.cdt.make.core.append_environment + true + + + org.eclipse.cdt.make.core.autoBuildTarget + all + + + org.eclipse.cdt.make.core.buildArguments + -j1 + + + org.eclipse.cdt.make.core.buildCommand + make + + + org.eclipse.cdt.make.core.cleanBuildTarget + clean + + + org.eclipse.cdt.make.core.contents + org.eclipse.cdt.make.core.activeConfigSettings + + + org.eclipse.cdt.make.core.enableAutoBuild + false + + + org.eclipse.cdt.make.core.enableCleanBuild + true + + + org.eclipse.cdt.make.core.enableFullBuild + true + + + org.eclipse.cdt.make.core.fullBuildTarget + all + + + org.eclipse.cdt.make.core.stopOnError + true + + + org.eclipse.cdt.make.core.useDefaultBuildCmd + true + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + board + 2 + $%7BPARENT-4-PROJECT_LOC%7D/ChibiOS/os/hal/boards/ST_STM32F4_DISCOVERY + + + contrib-os + 2 + $%7BPARENT-3-PROJECT_LOC%7D/os + + + os + 2 + $%7BPARENT-4-PROJECT_LOC%7D/ChibiOS/os + + + test + 2 + CHIBIOS/test + + + diff --git a/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/.settings/org.eclipse.cdt.core.prefs b/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/.settings/org.eclipse.cdt.core.prefs new file mode 100644 index 0000000..2862090 --- /dev/null +++ b/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/.settings/org.eclipse.cdt.core.prefs @@ -0,0 +1,6 @@ +eclipse.preferences.version=1 +environment/project/0.114656749/PATH/delimiter=; +environment/project/0.114656749/PATH/operation=replace +environment/project/0.114656749/PATH/value=${PATH};D\:\\toolchains\\gcc-arm-none-eabi-8-2018-q4-major-win32\\bin;${PATH};D\:\\toolchains\\gcc-arm-none-eabi-4_9-2014q4-20141203-win32\\bin;D\:\\toolchains\\msys64\\usr\\bin +environment/project/0.114656749/append=true +environment/project/0.114656749/appendContributed=true diff --git a/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/Makefile b/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/Makefile new file mode 100644 index 0000000..6127db4 --- /dev/null +++ b/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/Makefile @@ -0,0 +1,189 @@ +############################################################################## +# Build global options +# NOTE: Can be overridden externally. +# + +# Compiler options here. +ifeq ($(USE_OPT),) + USE_OPT = -Og -ggdb -fomit-frame-pointer -falign-functions=16 +endif + +# C specific options here (added to USE_OPT). +ifeq ($(USE_COPT),) + USE_COPT = +endif + +# C++ specific options here (added to USE_OPT). +ifeq ($(USE_CPPOPT),) + USE_CPPOPT = -fno-rtti +endif + +# Enable this if you want the linker to remove unused code and data. +ifeq ($(USE_LINK_GC),) + USE_LINK_GC = yes +endif + +# Linker extra options here. +ifeq ($(USE_LDOPT),) + USE_LDOPT = +endif + +# Enable this if you want link time optimizations (LTO). +ifeq ($(USE_LTO),) + USE_LTO = no +endif + +# Enable this if you want to see the full log while compiling. +ifeq ($(USE_VERBOSE_COMPILE),) + USE_VERBOSE_COMPILE = no +endif + +# If enabled, this option makes the build process faster by not compiling +# modules not used in the current configuration. +ifeq ($(USE_SMART_BUILD),) + USE_SMART_BUILD = yes +endif + +# +# Build global options +############################################################################## + +############################################################################## +# Architecture or project specific options +# + +# Stack size to be allocated to the Cortex-M process stack. This stack is +# the stack used by the main() thread. +ifeq ($(USE_PROCESS_STACKSIZE),) + USE_PROCESS_STACKSIZE = 0x400 +endif + +# Stack size to the allocated to the Cortex-M main/exceptions stack. This +# stack is used for processing interrupts and exceptions. +ifeq ($(USE_EXCEPTIONS_STACKSIZE),) + USE_EXCEPTIONS_STACKSIZE = 0x400 +endif + +# Enables the use of FPU (no, softfp, hard). +ifeq ($(USE_FPU),) + USE_FPU = hard +endif + +# FPU-related options. +ifeq ($(USE_FPU_OPT),) + USE_FPU_OPT = -mfloat-abi=$(USE_FPU) -mfpu=fpv4-sp-d16 +endif + +# +# Architecture or project specific options +############################################################################## + +############################################################################## +# Project, target, sources and paths +# + +# Define project name here +PROJECT = ch + +# Target settings. +MCU = cortex-m4 + +# Imported source files and paths. +CHIBIOS := ../../../../ChibiOS +CHIBIOS_CONTRIB := ../../../ +CONFDIR := ./cfg +BUILDDIR := ./build +DEPDIR := ./.dep + +# Licensing files. +include $(CHIBIOS)/os/license/license.mk +# Startup files. +include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/startup_stm32f4xx.mk +# HAL-OSAL files (optional). +include $(CHIBIOS)/os/hal/hal.mk +include $(CHIBIOS)/os/hal/ports/STM32/STM32F4xx/platform.mk +include $(CHIBIOS)/os/hal/boards/ST_STM32F4_DISCOVERY/board.mk +include $(CHIBIOS)/os/hal/osal/rt/osal.mk +# RTOS files (optional). +include $(CHIBIOS)/os/rt/rt.mk +include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk +# Auto-build files in ./source recursively. +include $(CHIBIOS)/tools/mk/autobuild.mk +# Other files (optional). +include $(CHIBIOS_CONTRIB)/os/common/ports/ARMCMx/compilers/GCC/utils/fault_handlers_v7m.mk +include $(CHIBIOS)/os/hal/lib/streams/streams.mk + +# Define linker script file here +LDSCRIPT= $(STARTUPLD)/STM32F407xG.ld + +# C sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CSRC = $(ALLCSRC) \ + $(TESTSRC) \ + main.c crash_test.c + +# C++ sources that can be compiled in ARM or THUMB mode depending on the global +# setting. +CPPSRC = $(ALLCPPSRC) + +# List ASM source files here. +ASMSRC = $(ALLASMSRC) + +# List ASM with preprocessor source files here. +ASMXSRC = $(ALLXASMSRC) crash_test_asm.S + +# Inclusion directories. +INCDIR = $(CONFDIR) $(ALLINC) $(TESTINC) + +# Define C warning options here. +CWARN = -Wall -Wextra -Wundef -Wstrict-prototypes + +# Define C++ warning options here. +CPPWARN = -Wall -Wextra -Wundef + +# +# Project, target, sources and paths +############################################################################## + +############################################################################## +# Start of user section +# + +# List all user C define here, like -D_DEBUG=1 +UDEFS = -DFAULT_INFO_HOOK=_fault_info_hook + +# Define ASM defines here +UADEFS = + +# List all user directories here +UINCDIR = + +# List the user directory to look for the libraries here +ULIBDIR = + +# List all user libraries here +ULIBS = + +# +# End of user section +############################################################################## + +############################################################################## +# Common rules +# + +RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk +include $(RULESPATH)/arm-none-eabi.mk +include $(RULESPATH)/rules.mk + +# +# Common rules +############################################################################## + +############################################################################## +# Custom rules +# + +# +# Custom rules +############################################################################## diff --git a/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/cfg/chconf.h b/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/cfg/chconf.h new file mode 100644 index 0000000..7dc4f84 --- /dev/null +++ b/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/cfg/chconf.h @@ -0,0 +1,714 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file rt/templates/chconf.h + * @brief Configuration file template. + * @details A copy of this file must be placed in each project directory, it + * contains the application specific kernel settings. + * + * @addtogroup config + * @details Kernel related settings and hooks. + * @{ + */ + +#ifndef CHCONF_H +#define CHCONF_H + +#define _CHIBIOS_RT_CONF_ +#define _CHIBIOS_RT_CONF_VER_6_0_ + +/*===========================================================================*/ +/** + * @name System timers settings + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System time counter resolution. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_ST_RESOLUTION) +#define CH_CFG_ST_RESOLUTION 32 +#endif + +/** + * @brief System tick frequency. + * @details Frequency of the system timer that drives the system ticks. This + * setting also defines the system tick time unit. + */ +#if !defined(CH_CFG_ST_FREQUENCY) +#define CH_CFG_ST_FREQUENCY 10000 +#endif + +/** + * @brief Time intervals data size. + * @note Allowed values are 16, 32 or 64 bits. + */ +#if !defined(CH_CFG_INTERVALS_SIZE) +#define CH_CFG_INTERVALS_SIZE 32 +#endif + +/** + * @brief Time types data size. + * @note Allowed values are 16 or 32 bits. + */ +#if !defined(CH_CFG_TIME_TYPES_SIZE) +#define CH_CFG_TIME_TYPES_SIZE 32 +#endif + +/** + * @brief Time delta constant for the tick-less mode. + * @note If this value is zero then the system uses the classic + * periodic tick. This value represents the minimum number + * of ticks that is safe to specify in a timeout directive. + * The value one is not valid, timeouts are rounded up to + * this value. + */ +#if !defined(CH_CFG_ST_TIMEDELTA) +#define CH_CFG_ST_TIMEDELTA 2 +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel parameters and options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Round robin interval. + * @details This constant is the number of system ticks allowed for the + * threads before preemption occurs. Setting this value to zero + * disables the preemption for threads with equal priority and the + * round robin becomes cooperative. Note that higher priority + * threads can still preempt, the kernel is always preemptive. + * @note Disabling the round robin preemption makes the kernel more compact + * and generally faster. + * @note The round robin preemption is not supported in tickless mode and + * must be set to zero in that case. + */ +#if !defined(CH_CFG_TIME_QUANTUM) +#define CH_CFG_TIME_QUANTUM 0 +#endif + +/** + * @brief Managed RAM size. + * @details Size of the RAM area to be managed by the OS. If set to zero + * then the whole available RAM is used. The core memory is made + * available to the heap allocator and/or can be used directly through + * the simplified core memory allocator. + * + * @note In order to let the OS manage the whole RAM the linker script must + * provide the @p __heap_base__ and @p __heap_end__ symbols. + * @note Requires @p CH_CFG_USE_MEMCORE. + */ +#if !defined(CH_CFG_MEMCORE_SIZE) +#define CH_CFG_MEMCORE_SIZE 0 +#endif + +/** + * @brief Idle thread automatic spawn suppression. + * @details When this option is activated the function @p chSysInit() + * does not spawn the idle thread. The application @p main() + * function becomes the idle thread and must implement an + * infinite loop. + */ +#if !defined(CH_CFG_NO_IDLE_THREAD) +#define CH_CFG_NO_IDLE_THREAD FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Performance options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief OS optimization. + * @details If enabled then time efficient rather than space efficient code + * is used when two possible implementations exist. + * + * @note This is not related to the compiler optimization options. + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_OPTIMIZE_SPEED) +#define CH_CFG_OPTIMIZE_SPEED TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Subsystem options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Time Measurement APIs. + * @details If enabled then the time measurement APIs are included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_TM) +#define CH_CFG_USE_TM TRUE +#endif + +/** + * @brief Threads registry APIs. + * @details If enabled then the registry APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_REGISTRY) +#define CH_CFG_USE_REGISTRY TRUE +#endif + +/** + * @brief Threads synchronization APIs. + * @details If enabled then the @p chThdWait() function is included in + * the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_WAITEXIT) +#define CH_CFG_USE_WAITEXIT TRUE +#endif + +/** + * @brief Semaphores APIs. + * @details If enabled then the Semaphores APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_SEMAPHORES) +#define CH_CFG_USE_SEMAPHORES TRUE +#endif + +/** + * @brief Semaphores queuing mode. + * @details If enabled then the threads are enqueued on semaphores by + * priority rather than in FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_SEMAPHORES_PRIORITY) +#define CH_CFG_USE_SEMAPHORES_PRIORITY FALSE +#endif + +/** + * @brief Mutexes APIs. + * @details If enabled then the mutexes APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MUTEXES) +#define CH_CFG_USE_MUTEXES TRUE +#endif + +/** + * @brief Enables recursive behavior on mutexes. + * @note Recursive mutexes are heavier and have an increased + * memory footprint. + * + * @note The default is @p FALSE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_MUTEXES_RECURSIVE) +#define CH_CFG_USE_MUTEXES_RECURSIVE FALSE +#endif + +/** + * @brief Conditional Variables APIs. + * @details If enabled then the conditional variables APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MUTEXES. + */ +#if !defined(CH_CFG_USE_CONDVARS) +#define CH_CFG_USE_CONDVARS TRUE +#endif + +/** + * @brief Conditional Variables APIs with timeout. + * @details If enabled then the conditional variables APIs with timeout + * specification are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_CONDVARS. + */ +#if !defined(CH_CFG_USE_CONDVARS_TIMEOUT) +#define CH_CFG_USE_CONDVARS_TIMEOUT TRUE +#endif + +/** + * @brief Events Flags APIs. + * @details If enabled then the event flags APIs are included in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_EVENTS) +#define CH_CFG_USE_EVENTS TRUE +#endif + +/** + * @brief Events Flags APIs with timeout. + * @details If enabled then the events APIs with timeout specification + * are included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_EVENTS. + */ +#if !defined(CH_CFG_USE_EVENTS_TIMEOUT) +#define CH_CFG_USE_EVENTS_TIMEOUT TRUE +#endif + +/** + * @brief Synchronous Messages APIs. + * @details If enabled then the synchronous messages APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MESSAGES) +#define CH_CFG_USE_MESSAGES TRUE +#endif + +/** + * @brief Synchronous Messages queuing mode. + * @details If enabled then messages are served by priority rather than in + * FIFO order. + * + * @note The default is @p FALSE. Enable this if you have special + * requirements. + * @note Requires @p CH_CFG_USE_MESSAGES. + */ +#if !defined(CH_CFG_USE_MESSAGES_PRIORITY) +#define CH_CFG_USE_MESSAGES_PRIORITY FALSE +#endif + +/** + * @brief Mailboxes APIs. + * @details If enabled then the asynchronous messages (mailboxes) APIs are + * included in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_SEMAPHORES. + */ +#if !defined(CH_CFG_USE_MAILBOXES) +#define CH_CFG_USE_MAILBOXES TRUE +#endif + +/** + * @brief Core Memory Manager APIs. + * @details If enabled then the core memory manager APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMCORE) +#define CH_CFG_USE_MEMCORE TRUE +#endif + +/** + * @brief Heap Allocator APIs. + * @details If enabled then the memory heap allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_MEMCORE and either @p CH_CFG_USE_MUTEXES or + * @p CH_CFG_USE_SEMAPHORES. + * @note Mutexes are recommended. + */ +#if !defined(CH_CFG_USE_HEAP) +#define CH_CFG_USE_HEAP TRUE +#endif + +/** + * @brief Memory Pools Allocator APIs. + * @details If enabled then the memory pools allocator APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_MEMPOOLS) +#define CH_CFG_USE_MEMPOOLS TRUE +#endif + +/** + * @brief Objects FIFOs APIs. + * @details If enabled then the objects FIFOs APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_OBJ_FIFOS) +#define CH_CFG_USE_OBJ_FIFOS TRUE +#endif + +/** + * @brief Pipes APIs. + * @details If enabled then the pipes APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + */ +#if !defined(CH_CFG_USE_PIPES) +#define CH_CFG_USE_PIPES TRUE +#endif + +/** + * @brief Dynamic Threads APIs. + * @details If enabled then the dynamic threads creation APIs are included + * in the kernel. + * + * @note The default is @p TRUE. + * @note Requires @p CH_CFG_USE_WAITEXIT. + * @note Requires @p CH_CFG_USE_HEAP and/or @p CH_CFG_USE_MEMPOOLS. + */ +#if !defined(CH_CFG_USE_DYNAMIC) +#define CH_CFG_USE_DYNAMIC TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Objects factory options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Objects Factory APIs. + * @details If enabled then the objects factory APIs are included in the + * kernel. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_CFG_USE_FACTORY) +#define CH_CFG_USE_FACTORY TRUE +#endif + +/** + * @brief Maximum length for object names. + * @details If the specified length is zero then the name is stored by + * pointer but this could have unintended side effects. + */ +#if !defined(CH_CFG_FACTORY_MAX_NAMES_LENGTH) +#define CH_CFG_FACTORY_MAX_NAMES_LENGTH 8 +#endif + +/** + * @brief Enables the registry of generic objects. + */ +#if !defined(CH_CFG_FACTORY_OBJECTS_REGISTRY) +#define CH_CFG_FACTORY_OBJECTS_REGISTRY TRUE +#endif + +/** + * @brief Enables factory for generic buffers. + */ +#if !defined(CH_CFG_FACTORY_GENERIC_BUFFERS) +#define CH_CFG_FACTORY_GENERIC_BUFFERS TRUE +#endif + +/** + * @brief Enables factory for semaphores. + */ +#if !defined(CH_CFG_FACTORY_SEMAPHORES) +#define CH_CFG_FACTORY_SEMAPHORES TRUE +#endif + +/** + * @brief Enables factory for mailboxes. + */ +#if !defined(CH_CFG_FACTORY_MAILBOXES) +#define CH_CFG_FACTORY_MAILBOXES TRUE +#endif + +/** + * @brief Enables factory for objects FIFOs. + */ +#if !defined(CH_CFG_FACTORY_OBJ_FIFOS) +#define CH_CFG_FACTORY_OBJ_FIFOS TRUE +#endif + +/** + * @brief Enables factory for Pipes. + */ +#if !defined(CH_CFG_FACTORY_PIPES) || defined(__DOXYGEN__) +#define CH_CFG_FACTORY_PIPES TRUE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Debug options + * @{ + */ +/*===========================================================================*/ + +/** + * @brief Debug option, kernel statistics. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_STATISTICS) +#define CH_DBG_STATISTICS FALSE +#endif + +/** + * @brief Debug option, system state check. + * @details If enabled the correct call protocol for system APIs is checked + * at runtime. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_SYSTEM_STATE_CHECK) +#define CH_DBG_SYSTEM_STATE_CHECK FALSE +#endif + +/** + * @brief Debug option, parameters checks. + * @details If enabled then the checks on the API functions input + * parameters are activated. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_CHECKS) +#define CH_DBG_ENABLE_CHECKS FALSE +#endif + +/** + * @brief Debug option, consistency checks. + * @details If enabled then all the assertions in the kernel code are + * activated. This includes consistency checks inside the kernel, + * runtime anomalies and port-defined checks. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_ENABLE_ASSERTS) +#define CH_DBG_ENABLE_ASSERTS FALSE +#endif + +/** + * @brief Debug option, trace buffer. + * @details If enabled then the trace buffer is activated. + * + * @note The default is @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_MASK) +#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED +#endif + +/** + * @brief Trace buffer entries. + * @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is + * different from @p CH_DBG_TRACE_MASK_DISABLED. + */ +#if !defined(CH_DBG_TRACE_BUFFER_SIZE) +#define CH_DBG_TRACE_BUFFER_SIZE 128 +#endif + +/** + * @brief Debug option, stack checks. + * @details If enabled then a runtime stack check is performed. + * + * @note The default is @p FALSE. + * @note The stack check is performed in a architecture/port dependent way. + * It may not be implemented or some ports. + * @note The default failure mode is to halt the system with the global + * @p panic_msg variable set to @p NULL. + */ +#if !defined(CH_DBG_ENABLE_STACK_CHECK) +#define CH_DBG_ENABLE_STACK_CHECK FALSE +#endif + +/** + * @brief Debug option, stacks initialization. + * @details If enabled then the threads working area is filled with a byte + * value when a thread is created. This can be useful for the + * runtime measurement of the used stack. + * + * @note The default is @p FALSE. + */ +#if !defined(CH_DBG_FILL_THREADS) +#define CH_DBG_FILL_THREADS FALSE +#endif + +/** + * @brief Debug option, threads profiling. + * @details If enabled then a field is added to the @p thread_t structure that + * counts the system ticks occurred while executing the thread. + * + * @note The default is @p FALSE. + * @note This debug option is not currently compatible with the + * tickless mode. + */ +#if !defined(CH_DBG_THREADS_PROFILING) +#define CH_DBG_THREADS_PROFILING FALSE +#endif + +/** @} */ + +/*===========================================================================*/ +/** + * @name Kernel hooks + * @{ + */ +/*===========================================================================*/ + +/** + * @brief System structure extension. + * @details User fields added to the end of the @p ch_system_t structure. + */ +#define CH_CFG_SYSTEM_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief System initialization hook. + * @details User initialization code added to the @p chSysInit() function + * just before interrupts are enabled globally. + */ +#define CH_CFG_SYSTEM_INIT_HOOK() { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads descriptor structure extension. + * @details User fields added to the end of the @p thread_t structure. + */ +#define CH_CFG_THREAD_EXTRA_FIELDS \ + /* Add threads custom fields here.*/ + +/** + * @brief Threads initialization hook. + * @details User initialization code added to the @p _thread_init() function. + * + * @note It is invoked from within @p _thread_init() and implicitly from all + * the threads creation APIs. + */ +#define CH_CFG_THREAD_INIT_HOOK(tp) { \ + /* Add threads initialization code here.*/ \ +} + +/** + * @brief Threads finalization hook. + * @details User finalization code added to the @p chThdExit() API. + */ +#define CH_CFG_THREAD_EXIT_HOOK(tp) { \ + /* Add threads finalization code here.*/ \ +} + +/** + * @brief Context switch hook. + * @details This hook is invoked just before switching between threads. + */ +#define CH_CFG_CONTEXT_SWITCH_HOOK(ntp, otp) { \ + /* Context switch code here.*/ \ +} + +/** + * @brief ISR enter hook. + */ +#define CH_CFG_IRQ_PROLOGUE_HOOK() { \ + /* IRQ prologue code here.*/ \ +} + +/** + * @brief ISR exit hook. + */ +#define CH_CFG_IRQ_EPILOGUE_HOOK() { \ + /* IRQ epilogue code here.*/ \ +} + +/** + * @brief Idle thread enter hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to activate a power saving mode. + */ +#define CH_CFG_IDLE_ENTER_HOOK() { \ + /* Idle-enter code here.*/ \ +} + +/** + * @brief Idle thread leave hook. + * @note This hook is invoked within a critical zone, no OS functions + * should be invoked from here. + * @note This macro can be used to deactivate a power saving mode. + */ +#define CH_CFG_IDLE_LEAVE_HOOK() { \ + /* Idle-leave code here.*/ \ +} + +/** + * @brief Idle Loop hook. + * @details This hook is continuously invoked by the idle thread loop. + */ +#define CH_CFG_IDLE_LOOP_HOOK() { \ + /* Idle loop code here.*/ \ +} + +/** + * @brief System tick event hook. + * @details This hook is invoked in the system tick handler immediately + * after processing the virtual timers queue. + */ +#define CH_CFG_SYSTEM_TICK_HOOK() { \ + /* System tick event code here.*/ \ +} + +/** + * @brief System halt hook. + * @details This hook is invoked in case to a system halting error before + * the system is halted. + */ +#define CH_CFG_SYSTEM_HALT_HOOK(reason) { \ + /* System halt code here.*/ \ +} + +/** + * @brief Trace hook. + * @details This hook is invoked each time a new record is written in the + * trace buffer. + */ +#define CH_CFG_TRACE_HOOK(tep) { \ + /* Trace code here.*/ \ +} + +/** @} */ + +/*===========================================================================*/ +/* Port-specific settings (override port settings defaulted in chcore.h). */ +/*===========================================================================*/ + +#endif /* CHCONF_H */ + +/** @} */ diff --git a/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/cfg/halconf.h b/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/cfg/halconf.h new file mode 100644 index 0000000..e6437cd --- /dev/null +++ b/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/cfg/halconf.h @@ -0,0 +1,525 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file templates/halconf.h + * @brief HAL configuration header. + * @details HAL configuration file, this file allows to enable or disable the + * various device drivers from your application. You may also use + * this file in order to override the device drivers default settings. + * + * @addtogroup HAL_CONF + * @{ + */ + +#ifndef HALCONF_H +#define HALCONF_H + +#define _CHIBIOS_HAL_CONF_ +#define _CHIBIOS_HAL_CONF_VER_7_0_ + +#include "mcuconf.h" + +/** + * @brief Enables the PAL subsystem. + */ +#if !defined(HAL_USE_PAL) || defined(__DOXYGEN__) +#define HAL_USE_PAL TRUE +#endif + +/** + * @brief Enables the ADC subsystem. + */ +#if !defined(HAL_USE_ADC) || defined(__DOXYGEN__) +#define HAL_USE_ADC FALSE +#endif + +/** + * @brief Enables the CAN subsystem. + */ +#if !defined(HAL_USE_CAN) || defined(__DOXYGEN__) +#define HAL_USE_CAN FALSE +#endif + +/** + * @brief Enables the cryptographic subsystem. + */ +#if !defined(HAL_USE_CRY) || defined(__DOXYGEN__) +#define HAL_USE_CRY FALSE +#endif + +/** + * @brief Enables the DAC subsystem. + */ +#if !defined(HAL_USE_DAC) || defined(__DOXYGEN__) +#define HAL_USE_DAC FALSE +#endif + +/** + * @brief Enables the GPT subsystem. + */ +#if !defined(HAL_USE_GPT) || defined(__DOXYGEN__) +#define HAL_USE_GPT FALSE +#endif + +/** + * @brief Enables the I2C subsystem. + */ +#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__) +#define HAL_USE_I2C FALSE +#endif + +/** + * @brief Enables the I2S subsystem. + */ +#if !defined(HAL_USE_I2S) || defined(__DOXYGEN__) +#define HAL_USE_I2S FALSE +#endif + +/** + * @brief Enables the ICU subsystem. + */ +#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__) +#define HAL_USE_ICU FALSE +#endif + +/** + * @brief Enables the MAC subsystem. + */ +#if !defined(HAL_USE_MAC) || defined(__DOXYGEN__) +#define HAL_USE_MAC FALSE +#endif + +/** + * @brief Enables the MMC_SPI subsystem. + */ +#if !defined(HAL_USE_MMC_SPI) || defined(__DOXYGEN__) +#define HAL_USE_MMC_SPI FALSE +#endif + +/** + * @brief Enables the PWM subsystem. + */ +#if !defined(HAL_USE_PWM) || defined(__DOXYGEN__) +#define HAL_USE_PWM FALSE +#endif + +/** + * @brief Enables the RTC subsystem. + */ +#if !defined(HAL_USE_RTC) || defined(__DOXYGEN__) +#define HAL_USE_RTC FALSE +#endif + +/** + * @brief Enables the SDC subsystem. + */ +#if !defined(HAL_USE_SDC) || defined(__DOXYGEN__) +#define HAL_USE_SDC FALSE +#endif + +/** + * @brief Enables the SERIAL subsystem. + */ +#if !defined(HAL_USE_SERIAL) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL TRUE +#endif + +/** + * @brief Enables the SERIAL over USB subsystem. + */ +#if !defined(HAL_USE_SERIAL_USB) || defined(__DOXYGEN__) +#define HAL_USE_SERIAL_USB FALSE +#endif + +/** + * @brief Enables the SIO subsystem. + */ +#if !defined(HAL_USE_SIO) || defined(__DOXYGEN__) +#define HAL_USE_SIO FALSE +#endif + +/** + * @brief Enables the SPI subsystem. + */ +#if !defined(HAL_USE_SPI) || defined(__DOXYGEN__) +#define HAL_USE_SPI FALSE +#endif + +/** + * @brief Enables the TRNG subsystem. + */ +#if !defined(HAL_USE_TRNG) || defined(__DOXYGEN__) +#define HAL_USE_TRNG FALSE +#endif + +/** + * @brief Enables the UART subsystem. + */ +#if !defined(HAL_USE_UART) || defined(__DOXYGEN__) +#define HAL_USE_UART FALSE +#endif + +/** + * @brief Enables the USB subsystem. + */ +#if !defined(HAL_USE_USB) || defined(__DOXYGEN__) +#define HAL_USE_USB FALSE +#endif + +/** + * @brief Enables the WDG subsystem. + */ +#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__) +#define HAL_USE_WDG FALSE +#endif + +/** + * @brief Enables the WSPI subsystem. + */ +#if !defined(HAL_USE_WSPI) || defined(__DOXYGEN__) +#define HAL_USE_WSPI FALSE +#endif + +/*===========================================================================*/ +/* PAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_CALLBACKS) || defined(__DOXYGEN__) +#define PAL_USE_CALLBACKS FALSE +#endif + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(PAL_USE_WAIT) || defined(__DOXYGEN__) +#define PAL_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* ADC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_WAIT) || defined(__DOXYGEN__) +#define ADC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p adcAcquireBus() and @p adcReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(ADC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define ADC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* CAN driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Sleep mode related APIs inclusion switch. + */ +#if !defined(CAN_USE_SLEEP_MODE) || defined(__DOXYGEN__) +#define CAN_USE_SLEEP_MODE TRUE +#endif + +/** + * @brief Enforces the driver to use direct callbacks rather than OSAL events. + */ +#if !defined(CAN_ENFORCE_USE_CALLBACKS) || defined(__DOXYGEN__) +#define CAN_ENFORCE_USE_CALLBACKS FALSE +#endif + +/*===========================================================================*/ +/* CRY driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the SW fall-back of the cryptographic driver. + * @details When enabled, this option, activates a fall-back software + * implementation for algorithms not supported by the underlying + * hardware. + * @note Fall-back implementations may not be present for all algorithms. + */ +#if !defined(HAL_CRY_USE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_USE_FALLBACK FALSE +#endif + +/** + * @brief Makes the driver forcibly use the fall-back implementations. + */ +#if !defined(HAL_CRY_ENFORCE_FALLBACK) || defined(__DOXYGEN__) +#define HAL_CRY_ENFORCE_FALLBACK FALSE +#endif + +/*===========================================================================*/ +/* DAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_WAIT) || defined(__DOXYGEN__) +#define DAC_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p dacAcquireBus() and @p dacReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(DAC_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define DAC_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* I2C driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the mutual exclusion APIs on the I2C bus. + */ +#if !defined(I2C_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define I2C_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* MAC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the zero-copy API. + */ +#if !defined(MAC_USE_ZERO_COPY) || defined(__DOXYGEN__) +#define MAC_USE_ZERO_COPY FALSE +#endif + +/** + * @brief Enables an event sources for incoming packets. + */ +#if !defined(MAC_USE_EVENTS) || defined(__DOXYGEN__) +#define MAC_USE_EVENTS TRUE +#endif + +/*===========================================================================*/ +/* MMC_SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + * This option is recommended also if the SPI driver does not + * use a DMA channel and heavily loads the CPU. + */ +#if !defined(MMC_NICE_WAITING) || defined(__DOXYGEN__) +#define MMC_NICE_WAITING TRUE +#endif + +/*===========================================================================*/ +/* SDC driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Number of initialization attempts before rejecting the card. + * @note Attempts are performed at 10mS intervals. + */ +#if !defined(SDC_INIT_RETRY) || defined(__DOXYGEN__) +#define SDC_INIT_RETRY 100 +#endif + +/** + * @brief Include support for MMC cards. + * @note MMC support is not yet implemented so this option must be kept + * at @p FALSE. + */ +#if !defined(SDC_MMC_SUPPORT) || defined(__DOXYGEN__) +#define SDC_MMC_SUPPORT FALSE +#endif + +/** + * @brief Delays insertions. + * @details If enabled this options inserts delays into the MMC waiting + * routines releasing some extra CPU time for the threads with + * lower priority, this may slow down the driver a bit however. + */ +#if !defined(SDC_NICE_WAITING) || defined(__DOXYGEN__) +#define SDC_NICE_WAITING TRUE +#endif + +/** + * @brief OCR initialization constant for V20 cards. + */ +#if !defined(SDC_INIT_OCR_V20) || defined(__DOXYGEN__) +#define SDC_INIT_OCR_V20 0x50FF8000U +#endif + +/** + * @brief OCR initialization constant for non-V20 cards. + */ +#if !defined(SDC_INIT_OCR) || defined(__DOXYGEN__) +#define SDC_INIT_OCR 0x80100000U +#endif + +/*===========================================================================*/ +/* SERIAL driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Default bit rate. + * @details Configuration parameter, this is the baud rate selected for the + * default configuration. + */ +#if !defined(SERIAL_DEFAULT_BITRATE) || defined(__DOXYGEN__) +#define SERIAL_DEFAULT_BITRATE 38400 +#endif + +/** + * @brief Serial buffers size. + * @details Configuration parameter, you can change the depth of the queue + * buffers depending on the requirements of your application. + * @note The default is 16 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_BUFFERS_SIZE 16 +#endif + +/*===========================================================================*/ +/* SERIAL_USB driver related setting. */ +/*===========================================================================*/ + +/** + * @brief Serial over USB buffers size. + * @details Configuration parameter, the buffer size must be a multiple of + * the USB data endpoint maximum packet size. + * @note The default is 256 bytes for both the transmission and receive + * buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_SIZE 256 +#endif + +/** + * @brief Serial over USB number of buffers. + * @note The default is 2 buffers. + */ +#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__) +#define SERIAL_USB_BUFFERS_NUMBER 2 +#endif + +/*===========================================================================*/ +/* SPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_WAIT) || defined(__DOXYGEN__) +#define SPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables circular transfers APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_CIRCULAR) || defined(__DOXYGEN__) +#define SPI_USE_CIRCULAR FALSE +#endif + + +/** + * @brief Enables the @p spiAcquireBus() and @p spiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define SPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +/** + * @brief Handling method for SPI CS line. + * @note Disabling this option saves both code and data space. + */ +#if !defined(SPI_SELECT_MODE) || defined(__DOXYGEN__) +#define SPI_SELECT_MODE SPI_SELECT_MODE_PAD +#endif + +/*===========================================================================*/ +/* UART driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__) +#define UART_USE_WAIT FALSE +#endif + +/** + * @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define UART_USE_MUTUAL_EXCLUSION FALSE +#endif + +/*===========================================================================*/ +/* USB driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__) +#define USB_USE_WAIT FALSE +#endif + +/*===========================================================================*/ +/* WSPI driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables synchronous APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_WAIT) || defined(__DOXYGEN__) +#define WSPI_USE_WAIT TRUE +#endif + +/** + * @brief Enables the @p wspiAcquireBus() and @p wspiReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(WSPI_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define WSPI_USE_MUTUAL_EXCLUSION TRUE +#endif + +#endif /* HALCONF_H */ + +/** @} */ diff --git a/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/cfg/mcuconf.h b/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/cfg/mcuconf.h new file mode 100644 index 0000000..9b16e42 --- /dev/null +++ b/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/cfg/mcuconf.h @@ -0,0 +1,342 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef MCUCONF_H +#define MCUCONF_H + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 8 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE + +/* + * IRQ system settings. + */ +#define STM32_IRQ_EXTI0_PRIORITY 6 +#define STM32_IRQ_EXTI1_PRIORITY 6 +#define STM32_IRQ_EXTI2_PRIORITY 6 +#define STM32_IRQ_EXTI3_PRIORITY 6 +#define STM32_IRQ_EXTI4_PRIORITY 6 +#define STM32_IRQ_EXTI5_9_PRIORITY 6 +#define STM32_IRQ_EXTI10_15_PRIORITY 6 +#define STM32_IRQ_EXTI16_PRIORITY 6 +#define STM32_IRQ_EXTI17_PRIORITY 15 +#define STM32_IRQ_EXTI18_PRIORITY 6 +#define STM32_IRQ_EXTI19_PRIORITY 6 +#define STM32_IRQ_EXTI20_PRIORITY 6 +#define STM32_IRQ_EXTI21_PRIORITY 15 +#define STM32_IRQ_EXTI22_PRIORITY 15 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 FALSE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#define STM32_CAN_USE_CAN1 FALSE +#define STM32_CAN_USE_CAN2 FALSE +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#define STM32_I2C_USE_I2C1 FALSE +#define STM32_I2C_USE_I2C2 FALSE +#define STM32_I2C_USE_I2C3 FALSE +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * I2S driver system settings. + */ +#define STM32_I2S_USE_SPI2 FALSE +#define STM32_I2S_USE_SPI3 FALSE +#define STM32_I2S_SPI2_IRQ_PRIORITY 10 +#define STM32_I2S_SPI3_IRQ_PRIORITY 10 +#define STM32_I2S_SPI2_DMA_PRIORITY 1 +#define STM32_I2S_SPI3_DMA_PRIORITY 1 +#define STM32_I2S_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_I2S_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2S_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2S_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2S_DMA_ERROR_HOOK(i2sp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 FALSE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 FALSE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SDC driver system settings. + */ +#define STM32_SDC_SDIO_DMA_PRIORITY 3 +#define STM32_SDC_SDIO_IRQ_PRIORITY 9 +#define STM32_SDC_WRITE_TIMEOUT_MS 1000 +#define STM32_SDC_READ_TIMEOUT_MS 1000 +#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define STM32_SDC_SDIO_UNALIGNED_SUPPORT TRUE +#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) + +/* + * SERIAL driver system settings. + */ +#define STM32_SERIAL_USE_USART1 FALSE +#define STM32_SERIAL_USE_USART2 TRUE +#define STM32_SERIAL_USE_USART3 FALSE +#define STM32_SERIAL_USE_UART4 FALSE +#define STM32_SERIAL_USE_UART5 FALSE +#define STM32_SERIAL_USE_USART6 FALSE +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#define STM32_SPI_USE_SPI1 FALSE +#define STM32_SPI_USE_SPI2 FALSE +#define STM32_SPI_USE_SPI3 FALSE +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 FALSE +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +#endif /* MCUCONF_H */ diff --git a/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/crash_test.c b/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/crash_test.c new file mode 100644 index 0000000..bf11436 --- /dev/null +++ b/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/crash_test.c @@ -0,0 +1,169 @@ +/* Copyright (C) 2018 Adam Green (https://github.com/adamgreen) + 2019 Diego Ismirlian (dismirlian(at)google's mail) + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + This code is heavily based on the work of Adam Green (https://github.com/adamgreen) +*/ + + +#include +#include + +// Assembly language routines defined in tests.S +void testMspMultipleOf8(void); +void testMspNotMultipleOf8(void); +void testPspMultipleOf8(void); +void testInitFPURegisters(void); +void testBreakpoints(void); + +static void enable8ByteStackAlignment(void); +static void crashWithFPUDisabled(void); +static void crashWithFPUAutoStackingDisabled(void); +static void crashWithFPUAutoStackEnabled(void); +static void crashWithFPULazyAutoStacking(void); + +#define CRASH_CATCHER_READ_FAULT() (*(volatile unsigned int*)0x55555550) +#define CRASH_CATCHER_WRITE_FAULT() (*(volatile unsigned int*)0x55555550 = 0x0) +#define CRASH_CATCHER_INVALID_INSTRUCTION() { __asm volatile (".word 0xDE00"); } + +/* Macro used to insert hardcoded breakpoint into user's code. */ +#define CRASH_CATCHER_BREAKPOINT() { __asm volatile ("bkpt #0"); } + +int crash(int option) { + + enable8ByteStackAlignment(); + + switch (option) { + case 1: + testMspMultipleOf8(); + break; + case 2: + testMspNotMultipleOf8(); + break; + case 3: + testPspMultipleOf8(); + break; + case 4: + CRASH_CATCHER_READ_FAULT(); + break; + case 5: + CRASH_CATCHER_WRITE_FAULT(); + break; + case 6: + crashWithFPUDisabled(); + break; + case 7: + crashWithFPUAutoStackingDisabled(); + break; + case 8: + crashWithFPUAutoStackEnabled(); + break; + case 9: + crashWithFPULazyAutoStacking(); + break; + case 10: + testBreakpoints(); + break; + default: + break; + } + + return 0; +} + +static void enable8ByteStackAlignment() +{ + SCB->CCR |= SCB_CCR_STKALIGN_Msk; +} + +#if CORTEX_HAS_FPU +static void disableFPU(void) +{ + static const uint32_t FPCA = 1 << 2; + SCB->CPACR &= ~(0xF << 20); + __set_CONTROL(__get_CONTROL() & ~FPCA); +} + +static void enableFPU(void) +{ + SCB->CPACR |= (0xF << 20); +} + +static void crashWithFPUDisabled(void) +{ + disableFPU(); + __disable_irq(); + testInitFPURegisters(); + CRASH_CATCHER_READ_FAULT(); +} + +static const uint32_t ASPEN = 1 << 31; +static const uint32_t LSPEN = 1 << 30; + +static void crashWithFPUAutoStackingDisabled(void) +{ + disableFPU(); + FPU->FPCCR &= ~(ASPEN | LSPEN); + enableFPU(); + __disable_irq(); + testInitFPURegisters(); + CRASH_CATCHER_READ_FAULT(); +} + +static void crashWithFPUAutoStackEnabled(void) +{ + disableFPU(); + FPU->FPCCR |= ASPEN; + FPU->FPCCR &= ~LSPEN; + enableFPU(); + __disable_irq(); + testInitFPURegisters(); + CRASH_CATCHER_READ_FAULT(); +} + +static void crashWithFPULazyAutoStacking(void) +{ + disableFPU(); + FPU->FPCCR |= (ASPEN | LSPEN); + enableFPU(); + __disable_irq(); + testInitFPURegisters(); + CRASH_CATCHER_READ_FAULT(); +} + +#else + +static void crashWithFPUDisabled(void) +{ + return; +} + +static void crashWithFPUAutoStackingDisabled(void) +{ + return; +} + +static void crashWithFPUAutoStackEnabled(void) +{ + return; +} + +static void crashWithFPULazyAutoStacking(void) +{ + return; +} + +#endif // !defined(CORTEX_M4) diff --git a/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/crash_test_asm.S b/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/crash_test_asm.S new file mode 100644 index 0000000..57a2f8a --- /dev/null +++ b/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/crash_test_asm.S @@ -0,0 +1,273 @@ +/* Copyright (C) 2018 Adam Green (https://github.com/adamgreen) + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +/* Implementation of code to generate various crash scenarios for testing. */ + .text + .syntax unified + + .global testMspMultipleOf8 + .type testMspMultipleOf8, %function + .thumb_func + /* extern "C" void testMspMultipleOf8(void); + Uses MSP and has it pointing to an even multiple of 8. + */ +testMspMultipleOf8: + // Make SP, an even multiple of 8. + mov r0, sp + movs r1, #4 + bics r0, r1 + mov sp, r0 + // Load 0xFFFFFFFF into LR + movs r1, #1 + rsbs r0, r1, #0 + mov lr, r0 + // Load known values into R0-R12 + movs r0, #0 + // r1 was already set correctly above when initializing LR. + movs r2, #2 + movs r3, #3 + movs r4, #4 + movs r5, #5 + movs r6, #6 + movs r7, #7 + mov r8, r7 + mov r9, r7 + mov r10, r7 + mov r11, r7 + mov r12, r7 + add r8, r1 + add r9, r2 + add r10, r3 + add r11, r4 + add r12, r5 + // Generate a hard fault by executing an undefined instruction. + .word 0xDE00 + // CrashCatcher_Entry() shouldn't return but if it does, just infinite loop here. + b . + // Let assembler know that we have hit the end of the function. + .pool + .size testMspMultipleOf8, .-testMspMultipleOf8 + + + .global testMspNotMultipleOf8 + .type testMspNotMultipleOf8, %function + .thumb_func + /* extern "C" void testMspNotMultipleOf8(void); + Uses MSP and has it not pointing to an even multiple of 8. + */ +testMspNotMultipleOf8: + // Make SP, not an even multiple of 8. + mov r0, sp + subs r0, #8 + movs r1, #4 + orrs r0, r1 + mov sp, r0 + // Load 0xFFFFFFFF into LR + movs r1, #1 + rsbs r0, r1, #0 + mov lr, r0 + // Load known values into R0-R12 + movs r0, #0 + // r1 was already set correctly above when initializing LR. + movs r2, #2 + movs r3, #3 + movs r4, #4 + movs r5, #5 + movs r6, #6 + movs r7, #7 + mov r8, r7 + mov r9, r7 + mov r10, r7 + mov r11, r7 + mov r12, r7 + add r8, r1 + add r9, r2 + add r10, r3 + add r11, r4 + add r12, r5 + // Generate a hard fault by executing an undefined instruction. + .word 0xDE00 + // CrashCatcher_Entry() shouldn't return but if it does, just infinite loop here. + b . + // Let assembler know that we have hit the end of the function. + .pool + .size testMspNotMultipleOf8, .-testMspNotMultipleOf8 + + + .global testPspMultipleOf8 + .type testPspMultipleOf8, %function + .thumb_func + /* extern "C" void testPspMultipleOf8(void); + Uses MSP and has it pointing to an even multiple of 8. + */ +testPspMultipleOf8: + // Make PSP, an even multiple of 8. + mov r0, sp + movs r1, #4 + bics r0, r1 + msr psp, r0 + // Switch to use of PSP. + movs r0, #3 + msr control,r0 + // Flush instructions so that control mods take effect. + isb + // Load 0xFFFFFFFF into LR + movs r1, #1 + rsbs r0, r1, #0 + mov lr, r0 + // Load known values into R0-R12 + movs r0, #0 + // r1 was already set correctly above when initializing LR. + movs r2, #2 + movs r3, #3 + movs r4, #4 + movs r5, #5 + movs r6, #6 + movs r7, #7 + mov r8, r7 + mov r9, r7 + mov r10, r7 + mov r11, r7 + mov r12, r7 + add r8, r1 + add r9, r2 + add r10, r3 + add r11, r4 + add r12, r5 + // Generate a hard fault by executing an undefined instruction. + .word 0xDE00 + // CrashCatcher_Entry() shouldn't return but if it does, just infinite loop here. + b . + // Let assembler know that we have hit the end of the function. + .pool + .size testPspMultipleOf8, .-testPspMultipleOf8 + + + .global testBreakpoints + .type testBreakpoints, %function + .thumb_func + /* extern "C" void testBreakpoints(void); + Set registers to known values, breakpoint, allow continuation, and breakpoint again to see if anything changed. + */ +testBreakpoints: + // Save away non-volatile registers that will be modified for testing. + mov r0, r8 + mov r1, r9 + mov r2, r10 + mov r3, r11 + push {r0-r7} + + // Load incrementing values into R0-R12 + movs r0, #0 + movs r1, #1 + movs r2, #2 + movs r3, #3 + movs r4, #4 + movs r5, #5 + movs r6, #6 + movs r7, #7 + mov r8, r7 + mov r9, r7 + mov r10, r7 + mov r11, r7 + mov r12, r7 + add r8, r1 + add r9, r2 + add r10, r3 + add r11, r4 + add r12, r5 + + // Issue one hard coded breakpoint. + bkpt #0 + + // Issue another hard coded breakpoint and see if dumps contain same values for all registers other than PC. + bkpt #255 + + // Restore non-volatile registers and return to caller. + pop {r0-r7} + mov r8, r0 + mov r9, r1 + mov r10, r2 + mov r11, r3 + bx lr + + // Let assembler know that we have hit the end of the function. + .pool + .size testBreakpoints, .-testBreakpoints + + +#if defined(TARGET_M4) + + .global testInitFPURegisters + .type testInitFPURegisters, %function + .thumb_func + /* extern "C" void testInitFPURegisters(void); + Initialize FPU registers to known values. + */ +testInitFPURegisters: + vmov.f32 s0, #-1.0 + vmov.f32 s1, #1.0 + vmov.f32 s2, #2.0 + vmov.f32 s3, #3.0 + vmov.f32 s4, #4.0 + vmov.f32 s5, #5.0 + vmov.f32 s6, #6.0 + vmov.f32 s7, #7.0 + vmov.f32 s8, #8.0 + vmov.f32 s9, #9.0 + vmov.f32 s10, #10.0 + vmov.f32 s11, #11.0 + vmov.f32 s12, #12.0 + vmov.f32 s13, #13.0 + vmov.f32 s14, #14.0 + vmov.f32 s15, #15.0 + vmov.f32 s16, #16.0 + vmov.f32 s17, #17.0 + vmov.f32 s18, #18.0 + vmov.f32 s19, #19.0 + vmov.f32 s20, #20.0 + vmov.f32 s21, #21.0 + vmov.f32 s22, #22.0 + vmov.f32 s23, #23.0 + vmov.f32 s24, #24.0 + vmov.f32 s25, #25.0 + vmov.f32 s26, #26.0 + vmov.f32 s27, #27.0 + vmov.f32 s28, #28.0 + vmov.f32 s29, #29.0 + vmov.f32 s30, #30.0 + vmov.f32 s31, #31.0 + ldr r0, =0xBAADFEED + vmsr fpscr, r0 + bx lr + .pool + .size testInitFPURegisters, .-testInitFPURegisters + +#else + + .global testInitFPURegisters + .type testInitFPURegisters, %function + .thumb_func + /* extern "C" void testInitFPURegisters(void); + Initialize FPU registers to known values. + */ +testInitFPURegisters: + bx lr + .pool + .size testInitFPURegisters, .-testInitFPURegisters + +#endif + + + .end diff --git a/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/debug/RT-STM32F407-DISCOVERY (OpenOCD, Flash and Run).launch b/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/debug/RT-STM32F407-DISCOVERY (OpenOCD, Flash and Run).launch new file mode 100644 index 0000000..3552b93 --- /dev/null +++ b/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/debug/RT-STM32F407-DISCOVERY (OpenOCD, Flash and Run).launch @@ -0,0 +1,52 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/debug/RT-STM32F407-DISCOVERY (OpenOCD, Just Run).launch b/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/debug/RT-STM32F407-DISCOVERY (OpenOCD, Just Run).launch new file mode 100644 index 0000000..b692aa6 --- /dev/null +++ b/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/debug/RT-STM32F407-DISCOVERY (OpenOCD, Just Run).launch @@ -0,0 +1,52 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/main.c b/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/main.c new file mode 100644 index 0000000..f5f6584 --- /dev/null +++ b/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/main.c @@ -0,0 +1,69 @@ +/* + ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "ch.h" +#include "hal.h" +#include "fault_handlers.h" + +int crash(int option); + +void _fault_info_hook(const struct fault_info *info) { + (void)info; + /* _print_message(info->decoded_info_string); */ +} + +int main(void) { + + /* + * System initializations. + * - HAL initialization, this also initializes the configured device drivers + * and performs the board-specific initializations. + * - Kernel initialization, the main() function becomes a thread and the + * RTOS is active. + */ + halInit(); + chSysInit(); + + /* + 1) MSP Rounded to multiple of 8 bytes. + 2) MSP Not Rounded to multiple of 8 bytes. + 3) PSP in use. + 4) Precise fault. + 5) Imprecise fault. + 6) Fault with FPU disabled. + 7) Fault with FPU auto-stacking disabled. + 8) Fault with FPU auto-stacking enabled. + 9) Fault with FPU lazy auto-stacking. + 10) Issue two breakpoints and return. + */ + crash(4); + + /* + * Activates the serial driver 2 using the driver default configuration. + * PA2(TX) and PA3(RX) are routed to USART2. + */ + sdStart(&SD2, NULL); + palSetPadMode(GPIOA, 2, PAL_MODE_ALTERNATE(7)); + palSetPadMode(GPIOA, 3, PAL_MODE_ALTERNATE(7)); + + /* + * Normal main() thread activity, in this demo it does nothing except + * sleeping in a loop and check the button state. + */ + while (true) { + chThdSleepMilliseconds(500); + } +} diff --git a/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/readme.txt b/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/readme.txt new file mode 100644 index 0000000..1e088b7 --- /dev/null +++ b/demos/STM32/RT-STM32F407-DISCOVERY-fault_handlers/readme.txt @@ -0,0 +1,25 @@ +***************************************************************************** +** ChibiOS/RT port for ARM-Cortex-M4 STM32F407. ** +***************************************************************************** + +** TARGET ** + +The demo runs on an ST STM32F4-Discovery board. + +** The Demo ** + + +** Build Procedure ** + +The demo has been tested by using the free Codesourcery GCC-based toolchain +and YAGARTO. just modify the TRGT line in the makefile in order to use +different GCC toolchains. + +** Notes ** + +Some files used by the demo are not part of ChibiOS/RT but are copyright of +ST Microelectronics and are licensed under a different license. +Also note that not all the files present in the ST library are distributed +with ChibiOS/RT, you can find the whole library on the ST web site: + + http://www.st.com diff --git a/os/common/ports/ARMCMx/compilers/GCC/utils/fault_handlers_v7m.c b/os/common/ports/ARMCMx/compilers/GCC/utils/fault_handlers_v7m.c new file mode 100644 index 0000000..37b7fc7 --- /dev/null +++ b/os/common/ports/ARMCMx/compilers/GCC/utils/fault_handlers_v7m.c @@ -0,0 +1,215 @@ +/* + ChibiOS - Copyright (C) 2019 Diego Ismirlian (dismirlian(at)google's mail) + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "fault_handlers.h" +#include +#include + +#ifndef FAULT_NO_PRINT +#include +#include + +#define fault_printf(f, ...) \ + chprintf((BaseSequentialStream *)(&ms), \ + f "\n", ##__VA_ARGS__) + +static MemoryStream ms; +#else +#define fault_printf(f, ...) do {} while(0) +#endif + +static struct fault_info fault_info; + +static void _mem_fault(void) { + fault_printf("== Mem faults follow =="); + + if (SCB->CFSR & SCB_CFSR_MSTKERR_Msk) { + fault_printf("Stacking error"); + fault_info.decoded_fault_registers.memfault.stacking_error = true; + } + if (SCB->CFSR & SCB_CFSR_MUNSTKERR_Msk) { + fault_printf("Unstacking error"); + fault_info.decoded_fault_registers.memfault.unstacking_error = true; + } + if (SCB->CFSR & SCB_CFSR_DACCVIOL_Msk) { + fault_printf("Data Access Violation"); + fault_info.decoded_fault_registers.memfault.data_access_violation = true; + } + if (SCB->CFSR & SCB_CFSR_MMARVALID_Msk) { + fault_printf("Address: 0x%08x", (uint32_t)SCB->MMFAR); + fault_info.decoded_fault_registers.memfault.data_access_violation_address = (uint32_t)SCB->MMFAR; + } else { + fault_printf("Address: unknown"); + fault_info.decoded_fault_registers.memfault.data_access_violation_address = 0xffffffff; + } + if (SCB->CFSR & SCB_CFSR_IACCVIOL_Msk) { + fault_printf("Instruction Access Violation"); + fault_info.decoded_fault_registers.memfault.instruction_access_violation = true; + } +} + +static void _bus_fault(void) { + fault_printf("== Bus faults follow =="); + + if (SCB->CFSR & SCB_CFSR_STKERR_Msk) { + fault_printf("Stacking error"); + fault_info.decoded_fault_registers.busfault.stacking_error = true; + } + if (SCB->CFSR & SCB_CFSR_UNSTKERR_Msk) { + fault_printf("Unstacking error"); + fault_info.decoded_fault_registers.busfault.unstacking_error = true; + } + if (SCB->CFSR & SCB_CFSR_PRECISERR_Msk) { + fault_printf("Precise data bus error"); + fault_info.decoded_fault_registers.busfault.precise_data_bus_error = true; + } + if (SCB->CFSR & SCB_CFSR_BFARVALID_Msk) { + fault_printf("Address: 0x%08x", (uint32_t)SCB->BFAR); + fault_info.decoded_fault_registers.busfault.precise_data_bus_error_address = (uint32_t)SCB->BFAR; + } else { + fault_printf("Address: unknown"); + fault_info.decoded_fault_registers.busfault.precise_data_bus_error_address = 0xffffffff; + } + if (SCB->CFSR & SCB_CFSR_IMPRECISERR_Msk) { + fault_printf("Imprecise data bus error"); + fault_info.decoded_fault_registers.busfault.imprecise_data_bus_error = true; + } + if (SCB->CFSR & SCB_CFSR_IBUSERR_Msk) { + fault_printf("Instruction bus error"); + fault_info.decoded_fault_registers.busfault.instruction_bus_error = true; + } +} + +static void _usage_fault(void) { + fault_printf("== Usage faults follow =="); + + if (SCB->CFSR & SCB_CFSR_DIVBYZERO_Msk) { + fault_printf("Division by zero"); + fault_info.decoded_fault_registers.usagefault.division_by_zero = true; + } + if (SCB->CFSR & SCB_CFSR_UNALIGNED_Msk) { + fault_printf("Unaligned memory access"); + fault_info.decoded_fault_registers.usagefault.unaligned_memory_access = true; + } + if (SCB->CFSR & SCB_CFSR_NOCP_Msk) { + fault_printf("No coprocessor instructions"); + fault_info.decoded_fault_registers.usagefault.no_coprocessor_instructions = true; + } + if (SCB->CFSR & SCB_CFSR_INVPC_Msk) { + fault_printf("Invalid load of PC"); + fault_info.decoded_fault_registers.usagefault.invalid_load_of_pc = true; + } + if (SCB->CFSR & SCB_CFSR_INVSTATE_Msk) { + fault_printf("Invalid state"); + fault_info.decoded_fault_registers.usagefault.invalid_state = true; + } + if (SCB->CFSR & SCB_CFSR_UNDEFINSTR_Msk) { + fault_printf("Undefined instruction"); + fault_info.decoded_fault_registers.usagefault.undefined_instruction = true; + } +} + +static void _init_fault_info(void) { +#ifndef FAULT_NO_PRINT + msObjectInit(&ms, + (uint8_t *)fault_info.decoded_info_string, + sizeof(fault_info.decoded_info_string) - 1, 0); +#endif +} + +static void _save_fault_info(void) { + memset(&fault_info.decoded_fault_registers, 0, sizeof(fault_info.decoded_fault_registers)); +#ifndef FAULT_NO_PRINT + memset(&fault_info.decoded_info_string, 0, sizeof(fault_info.decoded_info_string)); +#endif + + if (ch.rlist.current) { + fault_printf("Thread: 0x%08x, %s", + ch.rlist.current, ch.rlist.current->name); + + fault_info.decoded_fault_registers.general.current_thread_address = (uint32_t)ch.rlist.current; + fault_info.decoded_fault_registers.general.current_thread_name = ch.rlist.current->name; + } else { + fault_printf("Thread: unknown"); + } + + if (SCB->HFSR & SCB_HFSR_VECTTBL_Msk) { + fault_printf("Bus fault on vector table read"); + fault_info.decoded_fault_registers.general.bus_fault_on_ivt_read = true; + } + + if (SCB->HFSR & SCB_HFSR_FORCED_Msk) { + fault_info.decoded_fault_registers.general.escalation = true; + _mem_fault(); + _bus_fault(); + _usage_fault(); + } + if (!(SCB->HFSR & + (SCB_HFSR_VECTTBL_Msk | SCB_HFSR_FORCED_Msk))) { + fault_printf("No fault info"); + } +} + +#if defined(FAULT_INFO_HOOK) +void FAULT_INFO_HOOK(const struct fault_info *info); +#endif + +void _hardfault_info(void) { + _init_fault_info(); + fault_printf("HardFault Handler"); + _save_fault_info(); + +#if defined(FAULT_INFO_HOOK) + FAULT_INFO_HOOK(&fault_info); +#endif +} + +void _hardfault_epilogue(void) __attribute__((used, naked)); +void _hardfault_epilogue(void) { + + /* This is part of the HardFault handler + * + * You may inspect fault_info.decoded_fault_registers and + * fault_info.decoded_info_string to get a description of the fault that + * occurred. + * + * Also, the debugger should show an artificial call stack that led to the + * fault. This stack is reconstructed in assembly code, until GDB includes + * a way of automatically unwind an exception stack. + * + */ + __asm volatile( + "bkpt #0 \n" + "b _hardfault_exit \n" + ); +} + +void _unhandled_exception(void) { + /* This is an unhandled exception + * + * Once the breakpoint is hit, the debugger should show the ISR number + * in the vector_number variable. Don't trust the debugger's stack unwind; + * the _unhandled_exception ISR is shared among all undefined vectors. + */ + + volatile uint32_t vector_number = SCB->ICSR & SCB_ICSR_VECTACTIVE_Msk; + (void)vector_number; + + __asm volatile("bkpt #0"); + + /* we are here if there is no debugger attached */ + chSysHalt("unhandled exception"); +} diff --git a/os/common/ports/ARMCMx/compilers/GCC/utils/fault_handlers_v7m.mk b/os/common/ports/ARMCMx/compilers/GCC/utils/fault_handlers_v7m.mk new file mode 100644 index 0000000..8e04203 --- /dev/null +++ b/os/common/ports/ARMCMx/compilers/GCC/utils/fault_handlers_v7m.mk @@ -0,0 +1,4 @@ +ALLINC += $(CHIBIOS_CONTRIB)/os/various/fault_handlers \ + $(CHIBIOS_CONTRIB)/os/common/ports/ARMCMx/compilers/GCC/utils/ +ALLCSRC += $(CHIBIOS_CONTRIB)/os/common/ports/ARMCMx/compilers/GCC/utils/fault_handlers_v7m.c +ALLXASMSRC += $(CHIBIOS_CONTRIB)/os/common/ports/ARMCMx/compilers/GCC/utils/hardfault_handler_v7m.S diff --git a/os/common/ports/ARMCMx/compilers/GCC/utils/hardfault_handler_v7m.S b/os/common/ports/ARMCMx/compilers/GCC/utils/hardfault_handler_v7m.S new file mode 100644 index 0000000..9b4b96f --- /dev/null +++ b/os/common/ports/ARMCMx/compilers/GCC/utils/hardfault_handler_v7m.S @@ -0,0 +1,113 @@ +/* + ChibiOS - Copyright (C) 2019 Diego Ismirlian (dismirlian(at)google's mail) + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + + .syntax unified + .cpu cortex-m4 + + .section .data._fault_stack + .align 3 +_fault_stack: + .skip 256 +_fault_stack_end: + + .thumb + + .section .text.HardFault_Handler + .thumb_func + .globl HardFault_Handler +HardFault_Handler: + /* disable further interrupts */ + cpsid i + + /* preserve the ISR sp for later */ + mov r1, sp + + /* set the sp to a separate stack, in case of sp corruption */ + ldr sp, .L1 + + /* preserve the ISR lr and sp for later */ + push {r1, lr} + + /* print info */ + bl _hardfault_info + + /* restore the sp and the lr */ + pop {r1, lr} + mov sp, r1 + + /* Try to rebuild the stack for the debugger. + * The idea is that the debugger will unwind the stack, and + * show a call to the HardFault_Handler from the offending + * instruction */ + + /* check which stack was in use */ + tst lr, #4 //check bit 2 of EXC_RETURN + ite eq + mrseq r0, msp + mrsne r0, psp //r0 points to the stack that was in use + + /* try to rebuild the stack for the debugger */ + mov sp, r0 //sp points to the end of the IRQ stack + /* check if FPU registers were stacked */ + tst lr, #16 //check bit 4 of EXC_RETURN + ite eq + addeq sp, #104 //jump over the IRQ+FPU stack + addne sp, #32 //jump over the IRQ stack + + /* compensate padding */ + ldr r1, [sp, #28] //r1 = stacked xPSR + tst r1, #512 //check bit 9 of the stacked xPSR + ite eq + addeq sp, #0 //add 0 to sp if there was no padding + addne sp, #4 //add 4 to sp if there was padding + /* here, sp finally points to the stack before the IRQ was triggered */ + + /* set lr to the stacked PC address, so the debugger can show where the + fault was produced (may not be accurate, depending on the fault) */ + ldr lr, [r0, #24] + + /* restore used registers */ + ldr r0, [r0, #0] + ldr r1, [r0, #4] + + b _hardfault_epilogue + + .align 2 +.L1: .word _fault_stack_end + + + .section .text._hardfault_exit + .thumb_func + .globl _hardfault_exit +_hardfault_exit: + /* we are here if there is no debugger attached */ + + /* restore the sp to the separate stack */ + ldr sp, .L3 + + /* call chSysHalt */ + ldr r0, =.L2 + bl chSysHalt + + b . + + .align 2 +.L3: .word _fault_stack_end + + .align 2 +.L2: .asciz "hard fault" + + .align 2 diff --git a/os/common/ports/ARMCMx/compilers/GCC/utils/port_fault_handlers.h b/os/common/ports/ARMCMx/compilers/GCC/utils/port_fault_handlers.h new file mode 100644 index 0000000..ca98459 --- /dev/null +++ b/os/common/ports/ARMCMx/compilers/GCC/utils/port_fault_handlers.h @@ -0,0 +1,52 @@ +/* + ChibiOS - Copyright (C) 2019 Diego Ismirlian (dismirlian(at)google's mail) + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef FAULT_HANDLERS_v7m_H_ +#define FAULT_HANDLERS_v7m_H_ + +struct decoded_fault_registers { + struct general { + bool bus_fault_on_ivt_read; + bool escalation; + uint32_t current_thread_address; + const char *current_thread_name; + } general; + struct memfault { + bool stacking_error; + bool unstacking_error; + bool data_access_violation; + uint32_t data_access_violation_address; + bool instruction_access_violation; + } memfault; + struct busfault { + bool stacking_error; + bool unstacking_error; + bool precise_data_bus_error; + uint32_t precise_data_bus_error_address; + bool imprecise_data_bus_error; + bool instruction_bus_error; + } busfault; + struct usagefault { + bool division_by_zero; + bool unaligned_memory_access; + bool no_coprocessor_instructions; + bool invalid_load_of_pc; + bool invalid_state; + bool undefined_instruction; + } usagefault; +}; + +#endif /* FAULT_HANDLERS_v7m_H_ */ diff --git a/os/various/fault_handlers/fault_handlers.h b/os/various/fault_handlers/fault_handlers.h new file mode 100644 index 0000000..1fb210b --- /dev/null +++ b/os/various/fault_handlers/fault_handlers.h @@ -0,0 +1,22 @@ +#ifndef FAULT_HANDLERS_H_ +#define FAULT_HANDLERS_H_ + +#include +#include "port_fault_handlers.h" + +/* + * Notes: + * + * 1) #define FAULT_NO_PRINT to remove chprintf, etc + * 2) #define FAULT_INFO_HOOK(fault_info) to receive a struct fault_info when + * a fault is produced. + */ + +struct fault_info { + struct decoded_fault_registers decoded_fault_registers; +#ifndef FAULT_NO_PRINT + char decoded_info_string[300]; +#endif +}; + +#endif /* FAULT_HANDLERS_H_ */ -- cgit v1.2.3 From 1ca49e0b903954c1fd463d29e51faa22436fa33f Mon Sep 17 00:00:00 2001 From: Diego Ismirlian Date: Wed, 2 Oct 2019 15:18:08 -0300 Subject: Fault handlers: v7m: simplify --- os/common/ports/ARMCMx/compilers/GCC/utils/fault_handlers_v7m.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) diff --git a/os/common/ports/ARMCMx/compilers/GCC/utils/fault_handlers_v7m.c b/os/common/ports/ARMCMx/compilers/GCC/utils/fault_handlers_v7m.c index 37b7fc7..587fce3 100644 --- a/os/common/ports/ARMCMx/compilers/GCC/utils/fault_handlers_v7m.c +++ b/os/common/ports/ARMCMx/compilers/GCC/utils/fault_handlers_v7m.c @@ -131,10 +131,7 @@ static void _init_fault_info(void) { } static void _save_fault_info(void) { - memset(&fault_info.decoded_fault_registers, 0, sizeof(fault_info.decoded_fault_registers)); -#ifndef FAULT_NO_PRINT - memset(&fault_info.decoded_info_string, 0, sizeof(fault_info.decoded_info_string)); -#endif + memset(&fault_info, 0, sizeof(fault_info)); if (ch.rlist.current) { fault_printf("Thread: 0x%08x, %s", -- cgit v1.2.3