From 81c70f5ce6452f184e3cef46159ae2dc171bd51a Mon Sep 17 00:00:00 2001 From: marcoveeneman Date: Wed, 6 Jul 2016 20:12:03 +0200 Subject: Organized Tiva LLD folder. --- os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c | 981 ++++++++++++++++++++++++++++ os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.h | 523 +++++++++++++++ os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c | 445 +++++++++++++ os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h | 762 +++++++++++++++++++++ os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.c | 756 +++++++++++++++++++++ os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.h | 501 ++++++++++++++ os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c | 253 +++++++ os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.h | 276 ++++++++ os/hal/ports/TIVA/LLD/GPTM/tiva_gpt.h | 135 ++++ os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c | 894 +++++++++++++++++++++++++ os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.h | 527 +++++++++++++++ os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.c | 823 +++++++++++++++++++++++ os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.h | 438 +++++++++++++ os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.c | 585 +++++++++++++++++ os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.h | 372 +++++++++++ os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c | 685 +++++++++++++++++++ os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h | 388 +++++++++++ os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c | 664 +++++++++++++++++++ os/hal/ports/TIVA/LLD/UART/hal_serial_lld.h | 482 ++++++++++++++ os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.c | 244 +++++++ os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.h | 190 ++++++ os/hal/ports/TIVA/LLD/hal_ext_lld.c | 981 ---------------------------- os/hal/ports/TIVA/LLD/hal_ext_lld.h | 523 --------------- os/hal/ports/TIVA/LLD/hal_gpt_lld.c | 756 --------------------- os/hal/ports/TIVA/LLD/hal_gpt_lld.h | 501 -------------- os/hal/ports/TIVA/LLD/hal_i2c_lld.c | 894 ------------------------- os/hal/ports/TIVA/LLD/hal_i2c_lld.h | 527 --------------- os/hal/ports/TIVA/LLD/hal_mac_lld.c | 823 ----------------------- os/hal/ports/TIVA/LLD/hal_mac_lld.h | 438 ------------- os/hal/ports/TIVA/LLD/hal_pal_lld.c | 445 ------------- os/hal/ports/TIVA/LLD/hal_pal_lld.h | 762 --------------------- os/hal/ports/TIVA/LLD/hal_pwm_lld.c | 585 ----------------- os/hal/ports/TIVA/LLD/hal_pwm_lld.h | 372 ----------- os/hal/ports/TIVA/LLD/hal_serial_lld.c | 664 ------------------- os/hal/ports/TIVA/LLD/hal_serial_lld.h | 482 -------------- os/hal/ports/TIVA/LLD/hal_spi_lld.c | 685 ------------------- os/hal/ports/TIVA/LLD/hal_spi_lld.h | 388 ----------- os/hal/ports/TIVA/LLD/hal_st_lld.c | 253 ------- os/hal/ports/TIVA/LLD/hal_st_lld.h | 276 -------- os/hal/ports/TIVA/LLD/hal_wdg_lld.c | 244 ------- os/hal/ports/TIVA/LLD/hal_wdg_lld.h | 190 ------ os/hal/ports/TIVA/LLD/tiva_gpt.h | 135 ---- os/hal/ports/TIVA/LLD/tiva_udma.c | 141 ---- os/hal/ports/TIVA/LLD/tiva_udma.h | 195 ------ os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c | 141 ++++ os/hal/ports/TIVA/LLD/uDMA/tiva_udma.h | 195 ++++++ os/hal/ports/TIVA/TM4C123x/platform.mk | 29 +- os/hal/ports/TIVA/TM4C129x/platform.mk | 27 +- 48 files changed, 11298 insertions(+), 11278 deletions(-) create mode 100644 os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c create mode 100644 os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.h create mode 100644 os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c create mode 100644 os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h create mode 100644 os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.c create mode 100644 os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.h create mode 100644 os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c create mode 100644 os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.h create mode 100644 os/hal/ports/TIVA/LLD/GPTM/tiva_gpt.h create mode 100644 os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c create mode 100644 os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.h create mode 100644 os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.c create mode 100644 os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.h create mode 100644 os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.c create mode 100644 os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.h create mode 100644 os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c create mode 100644 os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h create mode 100644 os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c create mode 100644 os/hal/ports/TIVA/LLD/UART/hal_serial_lld.h create mode 100644 os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.c create mode 100644 os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.h delete mode 100644 os/hal/ports/TIVA/LLD/hal_ext_lld.c delete mode 100644 os/hal/ports/TIVA/LLD/hal_ext_lld.h delete mode 100644 os/hal/ports/TIVA/LLD/hal_gpt_lld.c delete mode 100644 os/hal/ports/TIVA/LLD/hal_gpt_lld.h delete mode 100644 os/hal/ports/TIVA/LLD/hal_i2c_lld.c delete mode 100644 os/hal/ports/TIVA/LLD/hal_i2c_lld.h delete mode 100644 os/hal/ports/TIVA/LLD/hal_mac_lld.c delete mode 100644 os/hal/ports/TIVA/LLD/hal_mac_lld.h delete mode 100644 os/hal/ports/TIVA/LLD/hal_pal_lld.c delete mode 100644 os/hal/ports/TIVA/LLD/hal_pal_lld.h delete mode 100644 os/hal/ports/TIVA/LLD/hal_pwm_lld.c delete mode 100644 os/hal/ports/TIVA/LLD/hal_pwm_lld.h delete mode 100644 os/hal/ports/TIVA/LLD/hal_serial_lld.c delete mode 100644 os/hal/ports/TIVA/LLD/hal_serial_lld.h delete mode 100644 os/hal/ports/TIVA/LLD/hal_spi_lld.c delete mode 100644 os/hal/ports/TIVA/LLD/hal_spi_lld.h delete mode 100644 os/hal/ports/TIVA/LLD/hal_st_lld.c delete mode 100644 os/hal/ports/TIVA/LLD/hal_st_lld.h delete mode 100644 os/hal/ports/TIVA/LLD/hal_wdg_lld.c delete mode 100644 os/hal/ports/TIVA/LLD/hal_wdg_lld.h delete mode 100644 os/hal/ports/TIVA/LLD/tiva_gpt.h delete mode 100644 os/hal/ports/TIVA/LLD/tiva_udma.c delete mode 100644 os/hal/ports/TIVA/LLD/tiva_udma.h create mode 100644 os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c create mode 100644 os/hal/ports/TIVA/LLD/uDMA/tiva_udma.h diff --git a/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c b/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c new file mode 100644 index 0000000..efe6421 --- /dev/null +++ b/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c @@ -0,0 +1,981 @@ +/* + Copyright (C) 2014..2016 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file Tiva/ext_lld.c + * @brief Tiva EXT subsystem low level driver source. + * + * @addtogroup EXT + * @{ + */ + +#include "hal.h" + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/** + * @brief Generic interrupt serving code for multiple pins per interrupt + * handler. + */ +#define ext_lld_serve_port_interrupt(gpiop, start) \ + do { \ + uint32_t mis = gpiop->MIS; \ + \ + gpiop->ICR = mis; \ + \ + if (mis & (1 << 0)) { \ + EXTD1.config->channels[start + 0].cb(&EXTD1, start + 0); \ + } \ + if (mis & (1 << 1)) { \ + EXTD1.config->channels[start + 1].cb(&EXTD1, start + 1); \ + } \ + if (mis & (1 << 2)) { \ + EXTD1.config->channels[start + 2].cb(&EXTD1, start + 2); \ + } \ + if (mis & (1 << 3)) { \ + EXTD1.config->channels[start + 3].cb(&EXTD1, start + 3); \ + } \ + if (mis & (1 << 4)) { \ + EXTD1.config->channels[start + 4].cb(&EXTD1, start + 4); \ + } \ + if (mis & (1 << 5)) { \ + EXTD1.config->channels[start + 5].cb(&EXTD1, start + 5); \ + } \ + if (mis & (1 << 6)) { \ + EXTD1.config->channels[start + 6].cb(&EXTD1, start + 6); \ + } \ + if (mis & (1 << 7)) { \ + EXTD1.config->channels[start + 7].cb(&EXTD1, start + 7); \ + } \ + } while (0); + +/** + * @brief Generic interrupt serving code for single pin per interrupt + * handler. + */ +#define ext_lld_serve_pin_interrupt(gpiop, start, pin) \ + do { \ + gpiop->ICR = (1 << pin); \ + EXTD1.config->channels[start].cb(&EXTD1, start); \ + } while (0); + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief EXTD1 driver identifier. + */ +EXTDriver EXTD1; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +const ioportid_t gpio[] = +{ +#if TIVA_HAS_GPIOA + GPIOA, +#endif +#if TIVA_HAS_GPIOB + GPIOB, +#endif +#if TIVA_HAS_GPIOC + GPIOC, +#endif +#if TIVA_HAS_GPIOD + GPIOD, +#endif +#if TIVA_HAS_GPIOE + GPIOE, +#endif +#if TIVA_HAS_GPIOF + GPIOF, +#endif +#if TIVA_HAS_GPIOG + GPIOG, +#endif +#if TIVA_HAS_GPIOH + GPIOH, +#endif +#if TIVA_HAS_GPIOJ + GPIOJ, +#endif +#if TIVA_HAS_GPIOK + GPIOK, +#endif +#if TIVA_HAS_GPIOL + GPIOL, +#endif +#if TIVA_HAS_GPIOM + GPIOM, +#endif +#if TIVA_HAS_GPION + GPION, +#endif +#if TIVA_HAS_GPIOP + GPIOP, +#endif +#if TIVA_HAS_GPIOQ + GPIOQ, +#endif +#if TIVA_HAS_GPIOR + GPIOR, +#endif +#if TIVA_HAS_GPIOS + GPIOS, +#endif +#if TIVA_HAS_GPIOT + GPIOT, +#endif +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Enables GPIO IRQ sources. + * + * @notapi + */ +static void ext_lld_irq_enable(void) +{ +#if TIVA_HAS_GPIOA + nvicEnableVector(TIVA_GPIOA_NUMBER, TIVA_EXT_GPIOA_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOB + nvicEnableVector(TIVA_GPIOB_NUMBER, TIVA_EXT_GPIOB_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOC + nvicEnableVector(TIVA_GPIOC_NUMBER, TIVA_EXT_GPIOC_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOD + nvicEnableVector(TIVA_GPIOD_NUMBER, TIVA_EXT_GPIOD_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOE + nvicEnableVector(TIVA_GPIOE_NUMBER, TIVA_EXT_GPIOE_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOF + nvicEnableVector(TIVA_GPIOF_NUMBER, TIVA_EXT_GPIOF_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOG + nvicEnableVector(TIVA_GPIOG_NUMBER, TIVA_EXT_GPIOG_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOH + nvicEnableVector(TIVA_GPIOH_NUMBER, TIVA_EXT_GPIOH_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOJ + nvicEnableVector(TIVA_GPIOJ_NUMBER, TIVA_EXT_GPIOJ_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOK + nvicEnableVector(TIVA_GPIOK_NUMBER, TIVA_EXT_GPIOK_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOL + nvicEnableVector(TIVA_GPIOL_NUMBER, TIVA_EXT_GPIOL_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOM + nvicEnableVector(TIVA_GPIOM_NUMBER, TIVA_EXT_GPIOM_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPION + nvicEnableVector(TIVA_GPION_NUMBER, TIVA_EXT_GPION_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOP + nvicEnableVector(TIVA_GPIOP0_NUMBER, TIVA_EXT_GPIOP0_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP1_NUMBER, TIVA_EXT_GPIOP1_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP2_NUMBER, TIVA_EXT_GPIOP2_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP3_NUMBER, TIVA_EXT_GPIOP3_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP4_NUMBER, TIVA_EXT_GPIOP4_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP5_NUMBER, TIVA_EXT_GPIOP5_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP6_NUMBER, TIVA_EXT_GPIOP6_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP7_NUMBER, TIVA_EXT_GPIOP7_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOQ + nvicEnableVector(TIVA_GPIOQ0_NUMBER, TIVA_EXT_GPIOQ0_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ1_NUMBER, TIVA_EXT_GPIOQ1_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ2_NUMBER, TIVA_EXT_GPIOQ2_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ3_NUMBER, TIVA_EXT_GPIOQ3_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ4_NUMBER, TIVA_EXT_GPIOQ4_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ5_NUMBER, TIVA_EXT_GPIOQ5_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ6_NUMBER, TIVA_EXT_GPIOQ6_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ7_NUMBER, TIVA_EXT_GPIOQ7_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOR + nvicEnableVector(TIVA_GPIOR_NUMBER, TIVA_EXT_GPIOR_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOS + nvicEnableVector(TIVA_GPIOS_NUMBER, TIVA_EXT_GPIOS_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOT + nvicEnableVector(TIVA_GPIOT_NUMBER, TIVA_EXT_GPIOT_IRQ_PRIORITY); +#endif +} + +/** + * @brief Disables GPIO IRQ sources. + * + * @notapi + */ +static void ext_lld_irq_disable(void) +{ +#if TIVA_HAS_GPIOA + nvicDisableVector(TIVA_GPIOA_NUMBER); +#endif +#if TIVA_HAS_GPIOB + nvicDisableVector(TIVA_GPIOB_NUMBER); +#endif +#if TIVA_HAS_GPIOC + nvicDisableVector(TIVA_GPIOC_NUMBER); +#endif +#if TIVA_HAS_GPIOD + nvicDisableVector(TIVA_GPIOD_NUMBER); +#endif +#if TIVA_HAS_GPIOE + nvicDisableVector(TIVA_GPIOE_NUMBER); +#endif +#if TIVA_HAS_GPIOF + nvicDisableVector(TIVA_GPIOF_NUMBER); +#endif +#if TIVA_HAS_GPIOG + nvicDisableVector(TIVA_GPIOG_NUMBER); +#endif +#if TIVA_HAS_GPIOH + nvicDisableVector(TIVA_GPIOH_NUMBER); +#endif +#if TIVA_HAS_GPIOJ + nvicDisableVector(TIVA_GPIOJ_NUMBER); +#endif +#if TIVA_HAS_GPIOK + nvicDisableVector(TIVA_GPIOK_NUMBER); +#endif +#if TIVA_HAS_GPIOL + nvicDisableVector(TIVA_GPIOL_NUMBER); +#endif +#if TIVA_HAS_GPIOM + nvicDisableVector(TIVA_GPIOM_NUMBER); +#endif +#if TIVA_HAS_GPION + nvicDisableVector(TIVA_GPION_NUMBER); +#endif +#if TIVA_HAS_GPIOP + nvicDisableVector(TIVA_GPIOP0_NUMBER); + nvicDisableVector(TIVA_GPIOP1_NUMBER); + nvicDisableVector(TIVA_GPIOP2_NUMBER); + nvicDisableVector(TIVA_GPIOP3_NUMBER); + nvicDisableVector(TIVA_GPIOP4_NUMBER); + nvicDisableVector(TIVA_GPIOP5_NUMBER); + nvicDisableVector(TIVA_GPIOP6_NUMBER); + nvicDisableVector(TIVA_GPIOP7_NUMBER); +#endif +#if TIVA_HAS_GPIOQ + nvicDisableVector(TIVA_GPIOQ0_NUMBER); + nvicDisableVector(TIVA_GPIOQ1_NUMBER); + nvicDisableVector(TIVA_GPIOQ2_NUMBER); + nvicDisableVector(TIVA_GPIOQ3_NUMBER); + nvicDisableVector(TIVA_GPIOQ4_NUMBER); + nvicDisableVector(TIVA_GPIOQ5_NUMBER); + nvicDisableVector(TIVA_GPIOQ6_NUMBER); + nvicDisableVector(TIVA_GPIOQ7_NUMBER); +#endif +#if TIVA_HAS_GPIOR + nvicDisableVector(TIVA_GPIOR_NUMBER); +#endif +#if TIVA_HAS_GPIOS + nvicDisableVector(TIVA_GPIOS_NUMBER); +#endif +#if TIVA_HAS_GPIOT + nvicDisableVector(TIVA_GPIOT_NUMBER); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if TIVA_HAS_GPIOA || defined(__DOXYGEN__) +/** + * @brief GPIOA interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOA_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOA, 0); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOB || defined(__DOXYGEN__) +/** + * @brief GPIOB interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOB_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOB, 8); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOC || defined(__DOXYGEN__) +/** + * @brief GPIOC interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOC_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOC, 16); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOD || defined(__DOXYGEN__) +/** + * @brief GPIOD interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOD_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOD, 24); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOE || defined(__DOXYGEN__) +/** + * @brief GPIOE interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOE_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOE, 32); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOF || defined(__DOXYGEN__) +/** + * @brief GPIOF interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOF_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOF, 40); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOG || defined(__DOXYGEN__) +/** + * @brief GPIOG interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOG_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(&GPIOG, 48); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOH || defined(__DOXYGEN__) +/** + * @brief GPIOH interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOH_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(&GPIOH, 56); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__) +/** + * @brief GPIOJ interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOJ_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(&GPIOJ, 64); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOK || defined(__DOXYGEN__) +/** + * @brief GPIOK interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOK_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(&GPIOK, 72); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOL || defined(__DOXYGEN__) +/** + * @brief GPIOL interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOL_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(&GPIOL, 80); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOM || defined(__DOXYGEN__) +/** + * @brief GPIOM interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOM_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(&GPIOM, 88); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPION || defined(__DOXYGEN__) +/** + * @brief GPION interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPION_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(&GPION, 96); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOP || defined(__DOXYGEN__) +/** + * @brief GPIOP0 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP0_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(&GPIOP, 104, 0); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP1 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP1_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(&GPIOP, 105, 1); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP2 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP2_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(&GPIOP, 106, 2); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP3 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP3_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(&GPIOP, 107, 3); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP4 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP4_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(&GPIOP, 108, 4); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP5 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP5_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(&GPIOP, 109, 5); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP6 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP6_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(&GPIOP, 110, 6); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP7 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP7_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(&GPIOP, 111, 7); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__) +/** + * @brief GPIOQ0 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ0_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(&GPIOQ, 112, 0); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ1 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ1_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(&GPIOQ, 113, 1); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ2 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ2_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(&GPIOQ, 114, 2); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ3 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ3_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(&GPIOQ, 115, 3); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ4 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ4_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(&GPIOQ, 116, 4); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ5 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ5_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(&GPIOQ, 117, 5); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ6 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ6_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(&GPIOQ, 118, 6); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ7 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ7_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(&GPIOQ, 119, 7); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOR || defined(__DOXYGEN__) +/** + * @brief GPIOR interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOR_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(&GPIOR, 120); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOS || defined(__DOXYGEN__) +/** + * @brief GPIOS interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOS_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(&GPIOS, 128); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOT || defined(__DOXYGEN__) +/** + * @brief GPIOT interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOT_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(&GPIOT, 132); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level EXT driver initialization. + * + * @notapi + */ +void ext_lld_init(void) +{ + extObjectInit(&EXTD1); +} + +/** + * @brief Configures and activates the EXT peripheral. + * + * @param[in] extp pointer to the @p EXTDriver object + * + * @notapi + */ +void ext_lld_start(EXTDriver *extp) +{ + uint8_t i; + + if (extp->state == EXT_STOP) { + ext_lld_irq_enable(); + } + + /* Configuration of automatic channels.*/ + for (i = 0; i < EXT_MAX_CHANNELS; i++) { + if (extp->config->channels[i].mode & EXT_CH_MODE_AUTOSTART) { + ext_lld_channel_enable(extp, i); + } + else { + ext_lld_channel_disable(extp, i); + } + } +} + +/** + * @brief Deactivates the EXT peripheral. + * + * @param[in] extp pointer to the @p EXTDriver object + * + * @notapi + */ +void ext_lld_stop(EXTDriver *extp) +{ + if (extp->state == EXT_ACTIVE) { + ext_lld_irq_disable(); + } + +#if TIVA_HAS_GPIOA + GPIOA->IM = 0; +#endif +#if TIVA_HAS_GPIOB + GPIOB->IM = 0; +#endif +#if TIVA_HAS_GPIOC + GPIOC->IM = 0; +#endif +#if TIVA_HAS_GPIOD + GPIOD->IM = 0; +#endif +#if TIVA_HAS_GPIOE + GPIOE->IM = 0; +#endif +#if TIVA_HAS_GPIOF + GPIOF->IM = 0; +#endif +#if TIVA_HAS_GPIOG + GPIOG->IM = 0; +#endif +#if TIVA_HAS_GPIOH + GPIOH->IM = 0; +#endif +#if TIVA_HAS_GPIOJ + GPIOJ->IM = 0; +#endif +#if TIVA_HAS_GPIOK + GPIOK->IM = 0; +#endif +#if TIVA_HAS_GPIOL + GPIOL->IM = 0; +#endif +#if TIVA_HAS_GPIOM + GPIOM->IM = 0; +#endif +#if TIVA_HAS_GPION + GPION->IM = 0; +#endif +#if TIVA_HAS_GPIOP + GPIOP->IM = 0; +#endif +#if TIVA_HAS_GPIOQ + GPIOQ->IM = 0; +#endif +#if TIVA_HAS_GPIOR + GPIOR->IM = 0; +#endif +#if TIVA_HAS_GPIOS + GPIOS->IM = 0; +#endif +#if TIVA_HAS_GPIOT + GPIOT->IM = 0; +#endif +} + +/** + * @brief Enables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be enabled + * + * @notapi + */ +void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) +{ + GPIO_TypeDef *gpiop; + uint8_t pin; + uint32_t im; + + pin = channel & 0x07; + gpiop = gpio[channel >> 3]; + + /* Disable interrupts */ + im = gpiop->IM; + gpiop->IM = 0; + + /* Configure pin to be edge-sensitive.*/ + gpiop->IS &= ~(1 << pin); + + /* Programming edge registers.*/ + if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) == + EXT_CH_MODE_BOTH_EDGES) { + gpiop->IBE |= (1 << pin); + } + else if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) == + EXT_CH_MODE_FALLING_EDGE) { + gpiop->IBE &= ~(1 << pin); + gpiop->IEV &= ~(1 << pin); + } + else if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) == + EXT_CH_MODE_RISING_EDGE) { + gpiop->IBE &= ~(1 << pin); + gpiop->IEV |= (1 << pin); + } + + /* Programming interrupt and event registers.*/ + if ((extp->config->channels[channel].cb != NULL) && + ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) != + EXT_CH_MODE_DISABLED)) { + im |= (1 << pin); + } + else { + im &= ~(1 << pin); + } + + /* Restore interrupts */ + gpiop->IM = im; +} + +/** + * @brief Disables an EXT channel. + * + * @param[in] extp pointer to the @p EXTDriver object + * @param[in] channel channel to be disabled + * + * @notapi + */ +void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) +{ + (void)extp; + GPIO_TypeDef *gpiop; + uint8_t pin; + + pin = channel & 0x07; + gpiop = gpio[channel >> 3]; + + gpiop->IM &= ~(1 << pin); +} + +#endif /* HAL_USE_EXT */ + +/** @} */ diff --git a/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.h b/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.h new file mode 100644 index 0000000..08accb2 --- /dev/null +++ b/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.h @@ -0,0 +1,523 @@ +/* + Copyright (C) 2014..2016 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file Tiva/ext_lld.h + * @brief Tiva EXT subsystem low level driver header. + * + * @addtogroup EXT + * @{ + */ + +#ifndef HAL_EXT_LLD_H +#define HAL_EXT_LLD_H + +#if HAL_USE_EXT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Number of EXT per port. + */ +#define EXT_MAX_CHANNELS TIVA_GPIO_PINS + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief GPIOA interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOA_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOA_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOB interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOB_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOB_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOC interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOC_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOC_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOD interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOD_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOD_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOE interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOE_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOE_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOF interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOF_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOF_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOG interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOG_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOG_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOH interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOH_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOH_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOJ interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOJ_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOJ_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOK interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOK_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOK_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOL interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOL_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOL_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOM interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOM_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOM_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPION interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPION_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPION_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOP0 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOP0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOP0_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOP1 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOP1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOP1_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOP2 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOP2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOP2_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOP3 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOP3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOP3_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOP4 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOP4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOP4_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOP5 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOP5_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOP5_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOP6 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOP6_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOP6_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOP7 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOP7_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOP7_IRQ_PRIORITY 3 +#endif +/** @} */ + +/** + * @brief GPIOQ0 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOQ0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOQ0_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ1 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOQ1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOQ1_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ2 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOQ2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOQ2_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ3 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOQ3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOQ3_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ4 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOQ4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOQ4_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ5 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOQ5_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOQ5_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ6 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOQ6_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOQ6_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ7 interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOQ7_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOQ7_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOR interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOR_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOR_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOS interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOS_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOS_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOT interrupt priority level setting. + */ +#if !defined(TIVA_EXT_GPIOT_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_EXT_GPIOT_IRQ_PRIORITY 3 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if TIVA_HAS_GPIOA && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOA_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOA" +#endif + +#if TIVA_HAS_GPIOB && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOB_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOB" +#endif + +#if TIVA_HAS_GPIOC && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOC_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOC" +#endif + +#if TIVA_HAS_GPIOD && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOD_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOD" +#endif + +#if TIVA_HAS_GPIOE && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOE_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOE" +#endif + +#if TIVA_HAS_GPIOF && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOF_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOF" +#endif + +#if TIVA_HAS_GPIOG && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOG_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOG" +#endif + +#if TIVA_HAS_GPIOH && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOH_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOH" +#endif + +#if TIVA_HAS_GPIOJ && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOJ_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOJ" +#endif + +#if TIVA_HAS_GPIOK && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOK_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOK" +#endif + +#if TIVA_HAS_GPIOL && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOL_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOL" +#endif + +#if TIVA_HAS_GPIOM && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOM_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOM" +#endif + +#if TIVA_HAS_GPION && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPION_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPION" +#endif + +#if TIVA_HAS_GPIOP0 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP0_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP0" +#endif + +#if TIVA_HAS_GPIOP1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP1" +#endif + +#if TIVA_HAS_GPIOP2 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP2" +#endif + +#if TIVA_HAS_GPIOP3 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP3" +#endif + +#if TIVA_HAS_GPIOP4 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP4_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP4" +#endif + +#if TIVA_HAS_GPIOP5 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP5_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP5" +#endif + +#if TIVA_HAS_GPIOP6 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP6_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP6" +#endif + +#if TIVA_HAS_GPIOP7 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP7_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP7" +#endif + +#if TIVA_HAS_GPIOQ0 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ0_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ0" +#endif + +#if TIVA_HAS_GPIOQ1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ1" +#endif + +#if TIVA_HAS_GPIOQ2 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ2" +#endif + +#if TIVA_HAS_GPIOQ3 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ3" +#endif + +#if TIVA_HAS_GPIOQ4 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ4_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ4" +#endif + +#if TIVA_HAS_GPIOQ5 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ5_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ5" +#endif + +#if TIVA_HAS_GPIOQ6 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ6_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ6" +#endif + +#if TIVA_HAS_GPIOQ7 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ7_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ7" +#endif + +#if TIVA_HAS_GPIOR && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOR_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOR" +#endif + +#if TIVA_HAS_GPIOS && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOS_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOS" +#endif + +#if TIVA_HAS_GPIOT && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOT_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOT" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief EXT channel identifier. + */ +typedef uint32_t expchannel_t; + +/** + * @brief Type of an EXT generic notification callback. + * + * @param[in] extp pointer to the @p EXPDriver object triggering the + * callback + */ +typedef void (*extcallback_t)(EXTDriver *extp, expchannel_t channel); + +/** + * @brief Channel configuration structure. + */ +typedef struct { + /** + * @brief Channel mode. + */ + uint32_t mode; + /** + * @brief Channel callback. + */ + extcallback_t cb; +} EXTChannelConfig; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Channel configurations. + */ + EXTChannelConfig channels[EXT_MAX_CHANNELS]; + /* End of the mandatory fields.*/ +} EXTConfig; + +/** + * @brief Structure representing an EXT driver. + */ +struct EXTDriver { + /** + * @brief Driver state. + */ + extstate_t state; + /** + * @brief Current configuration data. + */ + const EXTConfig *config; + /* End of the mandatory fields.*/ +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern EXTDriver EXTD1; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void ext_lld_init(void); + void ext_lld_start(EXTDriver *extp); + void ext_lld_stop(EXTDriver *extp); + void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel); + void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_EXT */ + +#endif /* HAL_EXT_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c new file mode 100644 index 0000000..5460fd4 --- /dev/null +++ b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c @@ -0,0 +1,445 @@ +/* + Copyright (C) 2014..2016 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file TIVA/LLD/pal_lld.c + * @brief TM4C123x/TM4C129x PAL subsystem low level driver. + * + * @addtogroup PAL + * @{ + */ + +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#if TIVA_HAS_GPIOA || defined(__DOXYGEN__) +#define GPIOA_BIT (1 << 0) +#if TIVA_GPIO_GPIOA_USE_AHB && defined(TM4C123x) +#define GPIOA_AHB_BIT (1 << 0) +#else +#define GPIOA_AHB_BIT 0 +#endif +#else +#define GPIOA_BIT 0 +#define GPIOA_AHB_BIT 0 +#endif + +#if TIVA_HAS_GPIOB || defined(__DOXYGEN__) +#define GPIOB_BIT (1 << 1) +#if TIVA_GPIO_GPIOB_USE_AHB && defined(TM4C123x) +#define GPIOB_AHB_BIT (1 << 1) +#else +#define GPIOB_AHB_BIT 0 +#endif +#else +#define GPIOB_BIT 0 +#define GPIOB_AHB_BIT 0 +#endif + +#if TIVA_HAS_GPIOC || defined(__DOXYGEN__) +#define GPIOC_BIT (1 << 2) +#if TIVA_GPIO_GPIOC_USE_AHB && defined(TM4C123x) +#define GPIOC_AHB_BIT (1 << 2) +#else +#define GPIOC_AHB_BIT 0 +#endif +#else +#define GPIOC_BIT 0 +#define GPIOC_AHB_BIT 0 +#endif + +#if TIVA_HAS_GPIOD || defined(__DOXYGEN__) +#define GPIOD_BIT (1 << 3) +#if TIVA_GPIO_GPIOD_USE_AHB && defined(TM4C123x) +#define GPIOD_AHB_BIT (1 << 3) +#else +#define GPIOD_AHB_BIT 0 +#endif +#else +#define GPIOD_BIT 0 +#define GPIOD_AHB_BIT 0 +#endif + +#if TIVA_HAS_GPIOE || defined(__DOXYGEN__) +#define GPIOE_BIT (1 << 4) +#if TIVA_GPIO_GPIOE_USE_AHB && defined(TM4C123x) +#define GPIOE_AHB_BIT (1 << 4) +#else +#define GPIOE_AHB_BIT 0 +#endif +#else +#define GPIOE_BIT 0 +#define GPIOE_AHB_BIT 0 +#endif + +#if TIVA_HAS_GPIOF || defined(__DOXYGEN__) +#define GPIOF_BIT (1 << 5) +#if TIVA_GPIO_GPIOF_USE_AHB && defined(TM4C123x) +#define GPIOF_AHB_BIT (1 << 5) +#else +#define GPIOF_AHB_BIT 0 +#endif +#else +#define GPIOF_BIT 0 +#define GPIOF_AHB_BIT 0 +#endif + +#if TIVA_HAS_GPIOG || defined(__DOXYGEN__) +#define GPIOG_BIT (1 << 6) +#if TIVA_GPIO_GPIOG_USE_AHB && defined(TM4C123x) +#define GPIOG_AHB_BIT (1 << 6) +#else +#define GPIOG_AHB_BIT 0 +#endif +#else +#define GPIOG_BIT 0 +#define GPIOG_AHB_BIT 0 +#endif + +#if TIVA_HAS_GPIOH || defined(__DOXYGEN__) +#define GPIOH_BIT (1 << 7) +#if TIVA_GPIO_GPIOH_USE_AHB && defined(TM4C123x) +#define GPIOH_AHB_BIT (1 << 7) +#else +#define GPIOH_AHB_BIT 0 +#endif +#else +#define GPIOH_BIT 0 +#define GPIOH_AHB_BIT 0 +#endif + +#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__) +#define GPIOJ_BIT (1 << 8) +#if TIVA_GPIO_GPIOJ_USE_AHB && defined(TM4C123x) +#define GPIOJ_AHB_BIT (1 << 8) +#else +#define GPIOJ_AHB_BIT 0 +#endif +#else +#define GPIOJ_BIT 0 +#define GPIOJ_AHB_BIT 0 +#endif + +#if TIVA_HAS_GPIOK || defined(__DOXYGEN__) +#define GPIOK_BIT (1 << 9) +#define GPIOK_AHB_BIT (1 << 9) +#else +#define GPIOK_BIT 0 +#define GPIOK_AHB_BIT 0 +#endif + +#if TIVA_HAS_GPIOL || defined(__DOXYGEN__) +#define GPIOL_BIT (1 << 10) +#define GPIOL_AHB_BIT (1 << 10) +#else +#define GPIOL_BIT 0 +#define GPIOL_AHB_BIT 0 +#endif + +#if TIVA_HAS_GPIOM || defined(__DOXYGEN__) +#define GPIOM_BIT (1 << 11) +#define GPIOM_AHB_BIT (1 << 11) +#else +#define GPIOM_BIT 0 +#define GPIOM_AHB_BIT 0 +#endif + +#if TIVA_HAS_GPION || defined(__DOXYGEN__) +#define GPION_BIT (1 << 12) +#define GPION_AHB_BIT (1 << 12) +#else +#define GPION_BIT 0 +#define GPION_AHB_BIT 0 +#endif + +#if TIVA_HAS_GPIOP || defined(__DOXYGEN__) +#define GPIOP_BIT (1 << 13) +#define GPIOP_AHB_BIT (1 << 13) +#else +#define GPIOP_BIT 0 +#define GPIOP_AHB_BIT 0 +#endif + +#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__) +#define GPIOQ_BIT (1 << 14) +#define GPIOQ_AHB_BIT (1 << 14) +#else +#define GPIOQ_BIT 0 +#define GPIOQ_AHB_BIT 0 +#endif + +#if TIVA_HAS_GPIOR || defined(__DOXYGEN__) +#define GPIOR_BIT (1 << 15) +#define GPIOR_AHB_BIT (1 << 15) +#else +#define GPIOR_BIT 0 +#define GPIOR_AHB_BIT 0 +#endif + +#if TIVA_HAS_GPIOS || defined(__DOXYGEN__) +#define GPIOS_BIT (1 << 16) +#define GPIOS_AHB_BIT (1 << 16) +#else +#define GPIOS_BIT 0 +#define GPIOS_AHB_BIT 0 +#endif + +#if TIVA_HAS_GPIOT || defined(__DOXYGEN__) +#define GPIOT_BIT (1 << 17) +#define GPIOT_AHB_BIT (1 << 17) +#else +#define GPIOT_BIT 0 +#define GPIOT_AHB_BIT 0 +#endif + +#define RCGCGPIO_MASK (GPIOA_BIT | GPIOB_BIT | GPIOC_BIT | GPIOD_BIT | \ + GPIOE_BIT | GPIOF_BIT | GPIOG_BIT | GPIOH_BIT | \ + GPIOJ_BIT | GPIOK_BIT | GPIOL_BIT | GPIOM_BIT | \ + GPION_BIT | GPIOP_BIT | GPIOQ_BIT | GPIOR_BIT | \ + GPIOS_BIT | GPIOR_BIT) + +#define GPIOHBCTL_MASK (GPIOA_AHB_BIT | GPIOB_AHB_BIT | GPIOC_AHB_BIT | \ + GPIOD_AHB_BIT | GPIOE_AHB_BIT | GPIOF_AHB_BIT | \ + GPIOG_AHB_BIT | GPIOH_AHB_BIT | GPIOJ_AHB_BIT | \ + GPIOK_AHB_BIT | GPIOL_AHB_BIT | GPIOM_AHB_BIT | \ + GPION_AHB_BIT | GPIOP_AHB_BIT | GPIOQ_AHB_BIT | \ + GPIOR_AHB_BIT | GPIOS_AHB_BIT | GPIOT_AHB_BIT) + +/* GPIO lock password.*/ +#define TIVA_GPIO_LOCK_PWD 0x4C4F434B + +#define GPIOC_JTAG_MASK (0x0F) +#define GPIOD_NMI_MASK (0x80) +#define GPIOF_NMI_MASK (0x01) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Initializes the port with the port configuration. + * + * @param[in] port the port identifier + * @param[in] config the port configuration + */ +static void gpio_init(ioportid_t port, const tiva_gpio_setup_t *config) +{ + port->DATA = config->data; + port->DIR = config->dir; + port->AFSEL = config->afsel; + port->DR2R = config->dr2r; + port->DR4R = config->dr4r; + port->DR8R = config->dr8r; + port->ODR = config->odr; + port->PUR = config->pur; + port->PDR = config->pdr; + port->SLR = config->slr; + port->DEN = config->den; + port->AMSEL = config->amsel; + port->PCTL = config->pctl; +} + +/** + * @brief Unlocks the masked pins of the GPIO peripheral. + * @note This function is only useful for PORTC0-3, PORTD7 and PORTF0. + * + * @param[in] port the port identifier + * @param[in] mask the pin mask + */ +static void gpio_unlock(ioportid_t port, ioportmask_t mask) +{ + port->LOCK = TIVA_GPIO_LOCK_PWD; + port->CR = mask; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Tiva I/O ports configuration. + * @details Ports A-F (G, H, J, K, L, M, N, P, Q, R, S, T) clocks enabled. + * + * @param[in] config the Tiva ports configuration + * + * @notapi + */ +void _pal_lld_init(const PALConfig *config) +{ + /* + * Enables all GPIO clocks. + */ + SYSCTL->RCGCGPIO = RCGCGPIO_MASK; +#if defined(TM4C123x) + SYSCTL->GPIOHBCTL = GPIOHBCTL_MASK; +#endif + + /* Wait until all GPIO modules are ready */ + while (!((SYSCTL->PRGPIO & RCGCGPIO_MASK) == RCGCGPIO_MASK)) + ; + +#if TIVA_HAS_GPIOA + gpio_init(GPIOA, &config->PAData); +#endif +#if TIVA_HAS_GPIOB + gpio_init(GPIOB, &config->PBData); +#endif +#if TIVA_HAS_GPIOC + /* Unlock JTAG pins.*/ + gpio_unlock(GPIOC, GPIOC_JTAG_MASK); + gpio_init(GPIOC, &config->PCData); +#endif +#if TIVA_HAS_GPIOD + /* Unlock NMI pin.*/ + gpio_unlock(GPIOD, GPIOD_NMI_MASK); + gpio_init(GPIOD, &config->PDData); +#endif +#if TIVA_HAS_GPIOE + gpio_init(GPIOE, &config->PEData); +#endif +#if TIVA_HAS_GPIOF + /* Unlock NMI pin.*/ + gpio_unlock(GPIOF, GPIOF_NMI_MASK); + gpio_init(GPIOF, &config->PFData); +#endif +#if TIVA_HAS_GPIOG || defined(__DOXYGEN__) + gpio_init(GPIOG, &config->PGData); +#endif +#if TIVA_HAS_GPIOH || defined(__DOXYGEN__) + gpio_init(GPIOH, &config->PHData); +#endif +#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__) + gpio_init(GPIOJ, &config->PJData); +#endif +#if TIVA_HAS_GPIOK || defined(__DOXYGEN__) + gpio_init(GPIOK, &config->PKData); +#endif +#if TIVA_HAS_GPIOL || defined(__DOXYGEN__) + gpio_init(GPIOL, &config->PLData); +#endif +#if TIVA_HAS_GPIOM || defined(__DOXYGEN__) + gpio_init(GPIOM, &config->PMData); +#endif +#if TIVA_HAS_GPION || defined(__DOXYGEN__) + gpio_init(GPION, &config->PNData); +#endif +#if TIVA_HAS_GPIOP || defined(__DOXYGEN__) + gpio_init(GPIOP, &config->PPData); +#endif +#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__) + gpio_init(GPIOQ, &config->PQData); +#endif +#if TIVA_HAS_GPIOR || defined(__DOXYGEN__) + gpio_init(GPIOR, &config->PRData); +#endif +#if TIVA_HAS_GPIOS || defined(__DOXYGEN__) + gpio_init(GPIOS, &config->PSData); +#endif +#if TIVA_HAS_GPIOT || defined(__DOXYGEN__) + gpio_init(GPIOT, &config->PTData); +#endif +} + +/** + * @brief Pads mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * + * @param[in] port the port identifier + * @param[in] mask the group mask + * @param[in] mode the mode + * + * @notapi + */ +void _pal_lld_setgroupmode(ioportid_t port, ioportmask_t mask, iomode_t mode) +{ + uint32_t dir = (mode & PAL_TIVA_DIR_MASK) >> 0; + uint32_t afsel = (mode & PAL_TIVA_AFSEL_MASK) >> 1; + uint32_t dr2r = (mode & PAL_TIVA_DR2R_MASK) >> 2; + uint32_t dr4r = (mode & PAL_TIVA_DR4R_MASK) >> 3; + uint32_t dr8r = (mode & PAL_TIVA_DR8R_MASK) >> 4; + uint32_t odr = (mode & PAL_TIVA_ODR_MASK) >> 5; + uint32_t pur = (mode & PAL_TIVA_PUR_MASK) >> 6; + uint32_t pdr = (mode & PAL_TIVA_PDR_MASK) >> 7; + uint32_t slr = (mode & PAL_TIVA_SLR_MASK) >> 8; + uint32_t den = (mode & PAL_TIVA_DEN_MASK) >> 9; + uint32_t amsel = (mode & PAL_TIVA_AMSEL_MASK) >> 10; + uint32_t pctl = (mode & PAL_TIVA_PCTL_MASK) >> 11; + uint32_t bit = 0; + + while(TRUE) { + uint32_t pctl_mask = (7 << (4 * bit)); + uint32_t bit_mask = (1 << bit); + + if ((mask & 1) != 0) { + port->DIR = (port->DIR & ~bit_mask) | dir; + port->AFSEL = (port->AFSEL & ~bit_mask) | afsel; + port->DR2R = (port->DR2R & ~bit_mask) | dr2r; + port->DR4R = (port->DR4R & ~bit_mask) | dr4r; + port->DR8R = (port->DR8R & ~bit_mask) | dr8r; + port->ODR = (port->ODR & ~bit_mask) | odr; + port->PUR = (port->PUR & ~bit_mask) | pur; + port->PDR = (port->PDR & ~bit_mask) | pdr; + port->SLR = (port->SLR & ~bit_mask) | slr; + port->DEN = (port->DEN & ~bit_mask) | den; + port->AMSEL = (port->AMSEL & ~bit_mask) | amsel; + port->PCTL = (port->PCTL & ~pctl_mask) | pctl; + } + + mask >>= 1; + if (!mask) { + return; + } + + dir <<= 1; + afsel <<= 1; + dr2r <<= 1; + dr4r <<= 1; + dr8r <<= 1; + odr <<= 1; + pur <<= 1; + pdr <<= 1; + slr <<= 1; + den <<= 1; + amsel <<= 1; + pctl <<= 4; + + bit++; + } +} + +#endif /* HAL_USE_PAL */ + +/** + * @} + */ diff --git a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h new file mode 100644 index 0000000..c0cd82b --- /dev/null +++ b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h @@ -0,0 +1,762 @@ +/* + Copyright (C) 2014..2016 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file TIVA/LLD/pal_lld.h + * @brief TM4C123x/TM4C129x PAL subsystem low level driver header. + * + * @addtogroup PAL + * @{ + */ + +#ifndef HAL_PAL_LLD_H +#define HAL_PAL_LLD_H + +#if HAL_USE_PAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#undef PAL_MODE_RESET +#undef PAL_MODE_UNCONNECTED +#undef PAL_MODE_INPUT +#undef PAL_MODE_INPUT_PULLUP +#undef PAL_MODE_INPUT_PULLDOWN +#undef PAL_MODE_INPUT_ANALOG +#undef PAL_MODE_OUTPUT_PUSHPULL +#undef PAL_MODE_OUTPUT_OPENDRAIN + +/** + * @name TIVA-specific I/O mode flags + * @{ + */ +#define PAL_TIVA_DIR_MASK (1 << 0) +#define PAL_TIVA_DIR_INPUT (0 << 0) +#define PAL_TIVA_DIR_OUTPUT (1 << 0) + +#define PAL_TIVA_AFSEL_MASK (1 << 1) +#define PAL_TIVA_AFSEL_GPIO (0 << 1) +#define PAL_TIVA_AFSEL_ALTERNATE (1 << 1) + +#define PAL_TIVA_DR2R_MASK (1 << 2) +#define PAL_TIVA_DR2R_DISABLE (0 << 2) +#define PAL_TIVA_DR2R_ENABLE (1 << 2) + +#define PAL_TIVA_DR4R_MASK (1 << 3) +#define PAL_TIVA_DR4R_DISABLE (0 << 3) +#define PAL_TIVA_DR4R_ENABLE (1 << 3) + +#define PAL_TIVA_DR8R_MASK (1 << 4) +#define PAL_TIVA_DR8R_DISABLE (0 << 4) +#define PAL_TIVA_DR8R_ENABLE (1 << 4) + +#define PAL_TIVA_ODR_MASK (1 << 5) +#define PAL_TIVA_ODR_PUSHPULL (0 << 5) +#define PAL_TIVA_ODR_OPENDRAIN (1 << 5) + +#define PAL_TIVA_PUR_MASK (1 << 6) +#define PAL_TIVA_PUR_DISABLE (0 << 6) +#define PAL_TIVA_PUR_ENABLE (1 << 6) + +#define PAL_TIVA_PDR_MASK (1 << 7) +#define PAL_TIVA_PDR_DISABLE (0 << 7) +#define PAL_TIVA_PDR_ENABLE (1 << 7) + +#define PAL_TIVA_SLR_MASK (1 << 8) +#define PAL_TIVA_SLR_DISABLE (0 << 8) +#define PAL_TIVA_SLR_ENABLE (1 << 8) + +#define PAL_TIVA_DEN_MASK (1 << 9) +#define PAL_TIVA_DEN_DISABLE (0 << 9) +#define PAL_TIVA_DEN_ENABLE (1 << 9) + +#define PAL_TIVA_AMSEL_MASK (1 << 10) +#define PAL_TIVA_AMSEL_DISABLE (0 << 10) +#define PAL_TIVA_AMSEL_ENABLE (1 << 10) + +#define PAL_TIVA_PCTL_MASK (7 << 11) +#define PAL_TIVA_PCTL(n) ((n) << 11) + +/** + * @brief Alternate function. + * + * @param[in] n alternate function selector + */ +#define PAL_MODE_ALTERNATE(n) (PAL_TIVA_AFSEL_ALTERNATE | \ + PAL_TIVA_PCTL(n)) +/** + * @} + */ + +/** + * @name Standard I/O mode flags + * @{ + */ +/** + * @brief This mode is implemented as input. + */ +#define PAL_MODE_RESET PAL_MODE_INPUT + +/** + * @brief This mode is implemented as input with pull-up. + */ +#define PAL_MODE_UNCONNECTED PAL_MODE_INPUT_PULLUP + +/** + * @brief Regular input high-Z pad. + */ +#define PAL_MODE_INPUT (PAL_TIVA_DEN_ENABLE | \ + PAL_TIVA_DIR_INPUT) + +/** + * @brief Input pad with weak pull up resistor. + */ +#define PAL_MODE_INPUT_PULLUP (PAL_TIVA_DIR_INPUT | \ + PAL_TIVA_PUR_ENABLE | \ + PAL_TIVA_DEN_ENABLE) + +/** + * @brief Input pad with weak pull down resistor. + */ +#define PAL_MODE_INPUT_PULLDOWN (PAL_TIVA_DIR_INPUT | \ + PAL_TIVA_PDR_ENABLE | \ + PAL_TIVA_DEN_ENABLE) + +/** + * @brief Analog input mode. + */ +#define PAL_MODE_INPUT_ANALOG (PAL_TIVA_DEN_DISABLE | \ + PAL_TIVA_AMSEL_ENABLE) + +/** + * @brief Push-pull output pad. + */ +#define PAL_MODE_OUTPUT_PUSHPULL (PAL_TIVA_DIR_OUTPUT | \ + PAL_TIVA_DR2R_ENABLE | \ + PAL_TIVA_ODR_PUSHPULL | \ + PAL_TIVA_DEN_ENABLE) + +/** + * @brief Open-drain output pad. + */ +#define PAL_MODE_OUTPUT_OPENDRAIN (PAL_TIVA_DIR_OUTPUT | \ + PAL_TIVA_DR2R_ENABLE | \ + PAL_TIVA_ODR_OPENDRAIN | \ + PAL_TIVA_DEN_ENABLE) +/** + * @} + */ + +/** @brief GPIOA port identifier.*/ +#define IOPORT1 GPIOA + +/** @brief GPIOB port identifier.*/ +#define IOPORT2 GPIOB + +/** @brief GPIOC port identifier.*/ +#define IOPORT3 GPIOC + +/** @brief GPIOD port identifier.*/ +#define IOPORT4 GPIOD + +/** @brief GPIOE port identifier.*/ +#define IOPORT5 GPIOE + +/** @brief GPIOF port identifier.*/ +#define IOPORT6 GPIOF + +#if TIVA_HAS_GPIOG || defined(__DOXYGEN__) +/** @brief Port G setup data.*/ +#define IOPORT7 GPIOG +#endif /* TIVA_HAS_GPIOG.*/ + +#if TIVA_HAS_GPIOH || defined(__DOXYGEN__) +/** @brief Port H setup data.*/ +#define IOPORT8 GPIOH +#endif /* TIVA_HAS_GPIOH.*/ + +#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__) +/** @brief Port J setup data.*/ +#define IOPORT9 GPIOJ +#endif /* TIVA_HAS_GPIOJ.*/ + +#if TIVA_HAS_GPIOK || defined(__DOXYGEN__) +/** @brief Port K setup data.*/ +#define IOPORT10 GPIOK +#endif /* TIVA_HAS_GPIOK.*/ + +#if TIVA_HAS_GPIOL || defined(__DOXYGEN__) +/** @brief Port L setup data.*/ +#define IOPORT11 GPIOL +#endif /* TIVA_HAS_GPIOL.*/ + +#if TIVA_HAS_GPIOM || defined(__DOXYGEN__) +/** @brief Port M setup data.*/ +#define IOPORT12 GPIOM +#endif /* TIVA_HAS_GPIOM.*/ + +#if TIVA_HAS_GPION || defined(__DOXYGEN__) +/** @brief Port N setup data.*/ +#define IOPORT13 GPION +#endif /* TIVA_HAS_GPION.*/ + +#if TIVA_HAS_GPIOP || defined(__DOXYGEN__) +/** @brief Port P setup data.*/ +#define IOPORT14 GPIOP +#endif /* TIVA_HAS_GPIOP.*/ + +#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__) +/** @brief Port Q setup data.*/ +#define IOPORT15 GPIOQ +#endif /* TIVA_HAS_GPIOQ.*/ + +#if TIVA_HAS_GPIOR || defined(__DOXYGEN__) +/** @brief Port R setup data.*/ +#define IOPORT16 GPIOR +#endif /* TIVA_HAS_GPIOR.*/ + +#if TIVA_HAS_GPIOS || defined(__DOXYGEN__) +/** @brief Port S setup data.*/ +#define IOPORT17 GPIOS +#endif /* TIVA_HAS_GPIOS.*/ + +#if TIVA_HAS_GPIOT || defined(__DOXYGEN__) +/** @brief Port T setup data.*/ +#define IOPORT18 GPIOT +#endif /* TIVA_HAS_GPIOT.*/ + +/** + * @brief Width, in bits, of an I/O port. + */ +#define PAL_IOPORTS_WIDTH 8 + +/** + * @brief Whole port mask. + * @brief This macro specifies all the valid bits into a port. + */ +#define PAL_WHOLE_PORT ((ioportmask_t)0xFF) + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +#if defined(TM4C123x) + +/** + * @brief GPIOA AHB enable switch. + * @details When set to @p TRUE the AHB bus is used to access GPIOA. When set + * to @p FALSE the APB bus is used to access GPIOA. + * @note The default is TRUE. + */ +#if !defined(TIVA_GPIO_GPIOA_USE_AHB) || defined(__DOXYGEN__) +#define TIVA_GPIO_GPIOA_USE_AHB TRUE +#endif + +/** + * @brief GPIOB AHB enable switch. + * @details When set to @p TRUE the AHB bus is used to access GPIOB. When set + * to @p FALSE the APB bus is used to access GPIOB. + * @note The default is TRUE. + */ +#if !defined(TIVA_GPIO_GPIOB_USE_AHB) || defined(__DOXYGEN__) +#define TIVA_GPIO_GPIOB_USE_AHB TRUE +#endif + +/** + * @brief GPIOC AHB enable switch. + * @details When set to @p TRUE the AHB bus is used to access GPIOC. When set + * to @p FALSE the APB bus is used to access GPIOC. + * @note The default is TRUE. + */ +#if !defined(TIVA_GPIO_GPIOC_USE_AHB) || defined(__DOXYGEN__) +#define TIVA_GPIO_GPIOC_USE_AHB TRUE +#endif + +/** + * @brief GPIOD AHB enable switch. + * @details When set to @p TRUE the AHB bus is used to access GPIOD. When set + * to @p FALSE the APB bus is used to access GPIOD. + * @note The default is TRUE. + */ +#if !defined(TIVA_GPIO_GPIOD_USE_AHB) || defined(__DOXYGEN__) +#define TIVA_GPIO_GPIOD_USE_AHB TRUE +#endif + +/** + * @brief GPIOE AHB enable switch. + * @details When set to @p TRUE the AHB bus is used to access GPIOE. When set + * to @p FALSE the APB bus is used to access GPIOE. + * @note The default is TRUE. + */ +#if !defined(TIVA_GPIO_GPIOE_USE_AHB) || defined(__DOXYGEN__) +#define TIVA_GPIO_GPIOE_USE_AHB TRUE +#endif + +/** + * @brief GPIOF AHB enable switch. + * @details When set to @p TRUE the AHB bus is used to access GPIOF. When set + * to @p FALSE the APB bus is used to access GPIOF. + * @note The default is TRUE. + */ +#if !defined(TIVA_GPIO_GPIOF_USE_AHB) || defined(__DOXYGEN__) +#define TIVA_GPIO_GPIOF_USE_AHB TRUE +#endif + +/** + * @brief GPIOG AHB enable switch. + * @details When set to @p TRUE the AHB bus is used to access GPIOG. When set + * to @p FALSE the APB bus is used to access GPIOG. + * @note The default is TRUE. + */ +#if !defined(TIVA_GPIO_GPIOG_USE_AHB) || defined(__DOXYGEN__) +#define TIVA_GPIO_GPIOG_USE_AHB TRUE +#endif + +/** + * @brief GPIOH AHB enable switch. + * @details When set to @p TRUE the AHB bus is used to access GPIOH. When set + * to @p FALSE the APB bus is used to access GPIOH. + * @note The default is TRUE. + */ +#if !defined(TIVA_GPIO_GPIOH_USE_AHB) || defined(__DOXYGEN__) +#define TIVA_GPIO_GPIOH_USE_AHB TRUE +#endif + +/** + * @brief GPIOJ AHB enable switch. + * @details When set to @p TRUE the AHB bus is used to access GPIOJ. When set + * to @p FALSE the APB bus is used to access GPIOJ. + * @note The default is TRUE. + */ +#if !defined(TIVA_GPIO_GPIOJ_USE_AHB) || defined(__DOXYGEN__) +#define TIVA_GPIO_GPIOJ_USE_AHB TRUE +#endif + +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if defined(TM4C123x) + +#if TIVA_GPIO_GPIOA_USE_AHB +#define GPIOA GPIOA_AHB +#else +#define GPIOA GPIOA_APB +#endif + +#if TIVA_GPIO_GPIOB_USE_AHB +#define GPIOB GPIOB_AHB +#else +#define GPIOB GPIOB_APB +#endif + +#if TIVA_GPIO_GPIOC_USE_AHB +#define GPIOC GPIOC_AHB +#else +#define GPIOC GPIOC_APB +#endif + +#if TIVA_GPIO_GPIOD_USE_AHB +#define GPIOD GPIOD_AHB +#else +#define GPIOD GPIOD_APB +#endif + +#if TIVA_GPIO_GPIOE_USE_AHB +#define GPIOE GPIOE_AHB +#else +#define GPIOE GPIOE_APB +#endif + +#if TIVA_GPIO_GPIOF_USE_AHB +#define GPIOF GPIOF_AHB +#else +#define GPIOF GPIOF_APB +#endif + +#if TIVA_GPIO_GPIOG_USE_AHB +#define GPIOG GPIOG_AHB +#else +#define GPIOG GPIOG_APB +#endif + +#if TIVA_GPIO_GPIOH_USE_AHB +#define GPIOH GPIOH_AHB +#else +#define GPIOH GPIOH_APB +#endif + +#if TIVA_GPIO_GPIOJ_USE_AHB +#define GPIOJ GPIOJ_AHB +#else +#define GPIOJ GPIOJ_APB +#endif + +#define GPIOK GPIOK_AHB +#define GPIOL GPIOL_AHB +#define GPIOM GPIOM_AHB +#define GPION GPION_AHB +#define GPIOP GPIOP_AHB +#define GPIOQ GPIOQ_AHB + +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief GPIO port setup info. + */ +typedef struct +{ + /** @brief Initial value for DATA register.*/ + uint32_t data; + /** @brief Initial value for DIR register.*/ + uint32_t dir; + /** @brief Initial value for AFSEL register.*/ + uint32_t afsel; + /** @brief Initial value for DR2R register.*/ + uint32_t dr2r; + /** @brief Initial value for DR4R register.*/ + uint32_t dr4r; + /** @brief Initial value for DR8R register.*/ + uint32_t dr8r; + /** @brief Initial value for ODR register.*/ + uint32_t odr; + /** @brief Initial value for PUR register.*/ + uint32_t pur; + /** @brief Initial value for PDR register.*/ + uint32_t pdr; + /** @brief Initial value for SLR register.*/ + uint32_t slr; + /** @brief Initial value for DEN register.*/ + uint32_t den; + /** @brief Initial value for AMSEL register.*/ + uint32_t amsel; + /** @brief Initial value for PCTL register.*/ + uint32_t pctl; +} tiva_gpio_setup_t; + +/** + * @brief Tiva GPIO static initializer. + * @details An instance of this structure must be passed to @p palInit() at + * system startup time in order to initialized the digital I/O + * subsystem. This represents only the initial setup, specific pads + * or whole ports can be reprogrammed at later time. + */ +typedef struct +{ + /** @brief Port A setup data.*/ + tiva_gpio_setup_t PAData; + /** @brief Port B setup data.*/ + tiva_gpio_setup_t PBData; + /** @brief Port C setup data.*/ + tiva_gpio_setup_t PCData; + /** @brief Port D setup data.*/ + tiva_gpio_setup_t PDData; + /** @brief Port E setup data.*/ + tiva_gpio_setup_t PEData; + /** @brief Port F setup data.*/ + tiva_gpio_setup_t PFData; + +#if TIVA_HAS_GPIOG || defined(__DOXYGEN__) + /** @brief Port G setup data.*/ + tiva_gpio_setup_t PGData; +#endif /* TIVA_HAS_GPIOG.*/ + +#if TIVA_HAS_GPIOH || defined(__DOXYGEN__) + /** @brief Port H setup data.*/ + tiva_gpio_setup_t PHData; +#endif /* TIVA_HAS_GPIOH.*/ + +#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__) + /** @brief Port J setup data.*/ + tiva_gpio_setup_t PJData; +#endif /* TIVA_HAS_GPIOJ.*/ + +#if TIVA_HAS_GPIOK || defined(__DOXYGEN__) + /** @brief Port K setup data.*/ + tiva_gpio_setup_t PKData; +#endif /* TIVA_HAS_GPIOK.*/ + +#if TIVA_HAS_GPIOL || defined(__DOXYGEN__) + /** @brief Port L setup data.*/ + tiva_gpio_setup_t PLData; +#endif /* TIVA_HAS_GPIOL.*/ + +#if TIVA_HAS_GPIOM || defined(__DOXYGEN__) + /** @brief Port M setup data.*/ + tiva_gpio_setup_t PMData; +#endif /* TIVA_HAS_GPIOM.*/ + +#if TIVA_HAS_GPION || defined(__DOXYGEN__) + /** @brief Port N setup data.*/ + tiva_gpio_setup_t PNData; +#endif /* TIVA_HAS_GPION.*/ + +#if TIVA_HAS_GPIOP || defined(__DOXYGEN__) + /** @brief Port P setup data.*/ + tiva_gpio_setup_t PPData; +#endif /* TIVA_HAS_GPIOP.*/ + +#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__) + /** @brief Port Q setup data.*/ + tiva_gpio_setup_t PQData; +#endif /* TIVA_HAS_GPIOQ.*/ + +#if TIVA_HAS_GPIOR || defined(__DOXYGEN__) + /** @brief Port R setup data.*/ + tiva_gpio_setup_t PRData; +#endif /* TIVA_HAS_GPIOR.*/ + +#if TIVA_HAS_GPIOS || defined(__DOXYGEN__) + /** @brief Port S setup data.*/ + tiva_gpio_setup_t PSData; +#endif /* TIVA_HAS_GPIOS.*/ + +#if TIVA_HAS_GPIOT || defined(__DOXYGEN__) + /** @brief Port T setup data.*/ + tiva_gpio_setup_t PTData; +#endif /* TIVA_HAS_GPIOT.*/ +} PALConfig; + +/** + * @brief Digital I/O port sized unsigned type. + */ +typedef uint32_t ioportmask_t; + +/** + * @brief Digital I/O modes. + */ +typedef uint32_t iomode_t; + +/** + * @brief Port Identifier. + */ +typedef GPIO_TypeDef *ioportid_t; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Low level PAL subsystem initialization. + * + * @param[in] config architecture-dependent ports configuration + * + * @notapi + */ +#define pal_lld_init(config) _pal_lld_init(config) + +/** + * @brief Reads the physical I/O port states. + * + * @param[in] port port identifier + * @return The port bits. + * + * @notapi + */ +#define pal_lld_readport(port) ((port)->DATA) + +/** + * @brief Reads the output latch. + * @details The purpose of this function is to read back the latched output + * value. + * + * @param[in] port port identifier + * @return The latched logical states. + * + * @notapi + */ +#define pal_lld_readlatch(port) ((port)->DATA) + +/** + * @brief Writes a bits mask on a I/O port. + * + * @param[in] port port identifier + * @param[in] bits bits to be written on the specified port + * + * @notapi + */ +#define pal_lld_writeport(port, bits) ((port)->DATA = (bits)) + +/** + * @brief Sets a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be ORed on the specified port + * + * @notapi + */ +#define pal_lld_setport(port, bits) ((port)->MASKED_ACCESS[bits] = 0xFF) + +/** + * @brief Clears a bits mask on a I/O port. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] bits bits to be cleared on the specified port + * + * @notapi + */ +#define pal_lld_clearport(port, bits) ((port)->MASKED_ACCESS[bits] = 0) + +/** + * @brief Reads a group of bits. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @return The group logical states. + * + * @notapi + */ +#define pal_lld_readgroup(port, mask, offset) \ + ((port)->MASKED_ACCESS[(mask) << (offset)]) + +/** + * @brief Writes a group of bits. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] bits bits to be written. Values exceeding the group width + * are masked. + * + * @notapi + */ +#define pal_lld_writegroup(port, mask, offset, bits) \ + ((port)->MASKED_ACCESS[(mask) << (offset)] = (bits)) + +/** + * @brief Pads group mode setup. + * @details This function programs a pads group belonging to the same port + * with the specified mode. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] mask group mask + * @param[in] offset group bit offset within the port + * @param[in] mode group mode + * + * @notapi + */ +#define pal_lld_setgroupmode(port, mask, offset, mode) \ + _pal_lld_setgroupmode(port, mask << offset, mode) + +/** + * @brief Reads a logical state from an I/O pad. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @return The logical state. + * @retval PAL_LOW low logical state. + * @retval PAL_HIGH high logical state. + * + * @notapi + */ +#define pal_lld_readpad(port, pad) ((port)->MASKED_ACCESS[1 << (pad)]) + +/** + * @brief Writes a logical state on an output pad. + * @note This function is not meant to be invoked directly by the + * application code. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] bit logical value, the value must be @p PAL_LOW or + * @p PAL_HIGH + * + * @notapi + */ +#define pal_lld_writepad(port, pad, bit) \ + ((port)->MASKED_ACCESS[1 << (pad)] = (bit)) + +/** + * @brief Sets a pad logical state to @p PAL_HIGH. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_setpad(port, pad) \ + ((port)->MASKED_ACCESS[1 << (pad)] = 1 << (pad)) + +/** + * @brief Clears a pad logical state to @p PAL_LOW. + * @note The @ref PAL provides a default software implementation of this + * functionality, implement this function if can optimize it by using + * special hardware functionalities or special coding. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_clearpad(port, pad) \ + ((port)->MASKED_ACCESS[1 << (pad)] = 0) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +extern const PALConfig pal_default_config; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void _pal_lld_init(const PALConfig *config); + void _pal_lld_setgroupmode(ioportid_t port, + ioportmask_t mask, + iomode_t mode); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PAL */ + +#endif /* HAL_PAL_LLD_H */ + +/** + * @} + */ diff --git a/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.c b/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.c new file mode 100644 index 0000000..870ba12 --- /dev/null +++ b/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.c @@ -0,0 +1,756 @@ +/* + Copyright (C) 2014..2016 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file TIVA/gpt_lld.c + * @brief TM4C123x/TM4C129x GPT subsystem low level driver source. + * + * @addtogroup GPT + * @{ + */ + +#include "hal.h" + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief GPTD1 driver identifier. + */ +#if TIVA_GPT_USE_GPT0 || defined(__DOXYGEN__) +GPTDriver GPTD1; +#endif + +/** + * @brief GPTD2 driver identifier. + */ +#if TIVA_GPT_USE_GPT1 || defined(__DOXYGEN__) +GPTDriver GPTD2; +#endif + +/** + * @brief GPTD3 driver identifier. + */ +#if TIVA_GPT_USE_GPT2 || defined(__DOXYGEN__) +GPTDriver GPTD3; +#endif + +/** + * @brief GPTD4 driver identifier. + */ +#if TIVA_GPT_USE_GPT3 || defined(__DOXYGEN__) +GPTDriver GPTD4; +#endif + +/** + * @brief GPTD5 driver identifier. + */ +#if TIVA_GPT_USE_GPT4 || defined(__DOXYGEN__) +GPTDriver GPTD5; +#endif + +/** + * @brief GPTD6 driver identifier. + */ +#if TIVA_GPT_USE_GPT5 || defined(__DOXYGEN__) +GPTDriver GPTD6; +#endif + +/** + * @brief GPTD7 driver identifier. + */ +#if TIVA_GPT_USE_WGPT0 || defined(__DOXYGEN__) +GPTDriver GPTD7; +#endif + +/** + * @brief GPTD8 driver identifier. + */ +#if TIVA_GPT_USE_WGPT1 || defined(__DOXYGEN__) +GPTDriver GPTD8; +#endif + +/** + * @brief GPTD9 driver identifier. + */ +#if TIVA_GPT_USE_WGPT2 || defined(__DOXYGEN__) +GPTDriver GPTD9; +#endif + +/** + * @brief GPTD10 driver identifier. + */ +#if TIVA_GPT_USE_WGPT3 || defined(__DOXYGEN__) +GPTDriver GPTD10; +#endif + +/** + * @brief GPTD11 driver identifier. + */ +#if TIVA_GPT_USE_WGPT4 || defined(__DOXYGEN__) +GPTDriver GPTD11; +#endif + +/** + * @brief GPTD12 driver identifier. + */ +#if TIVA_GPT_USE_WGPT5 || defined(__DOXYGEN__) +GPTDriver GPTD12; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Shared IRQ handler. + * + * @param[in] gptp pointer to @p GPTDriver object + */ +static void gpt_lld_serve_interrupt(GPTDriver *gptp) +{ + gptp->gpt->ICR = 0xffffffff; + + if (gptp->state == GPT_ONESHOT) { + gptp->state = GPT_READY; + gpt_lld_stop_timer(gptp); + } + + gptp->config->callback(gptp); +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if TIVA_GPT_USE_GPT0 +#if !defined(TIVA_GPT0A_HANDLER) +#error "TIVA_GPT0A_HANDLER not defined" +#endif +/** + * @brief GPT0 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPT0A_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD1); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_GPT_USE_GPT1 +#if !defined(TIVA_GPT1A_HANDLER) +#error "TIVA_GPT1A_HANDLER not defined" +#endif +/** + * @brief GPT1 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPT1A_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD2); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_GPT_USE_GPT2 +#if !defined(TIVA_GPT2A_HANDLER) +#error "TIVA_GPT2A_HANDLER not defined" +#endif +/** + * @brief GPT2 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPT2A_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD3); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_GPT_USE_GPT3 +#if !defined(TIVA_GPT3A_HANDLER) +#error "TIVA_GPT3A_HANDLER not defined" +#endif +/** + * @brief GPT3 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPT3A_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD4); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_GPT_USE_GPT4 +#if !defined(TIVA_GPT4A_HANDLER) +#error "TIVA_GPT4A_HANDLER not defined" +#endif +/** + * @brief GPT4 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPT4A_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD5); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_GPT_USE_GPT5 +#if !defined(TIVA_GPT5A_HANDLER) +#error "TIVA_GPT5A_HANDLER not defined" +#endif +/** + * @brief GPT5 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPT5A_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD6); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_GPT_USE_WGPT0 +#if !defined(TIVA_WGPT0A_HANDLER) +#error "TIVA_WGPT0A_HANDLER not defined" +#endif +/** + * @brief WGPT0 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_WGPT0A_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD7); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_GPT_USE_WGPT1 +#if !defined(TIVA_WGPT1A_HANDLER) +#error "TIVA_WGPT1A_HANDLER not defined" +#endif +/** + * @brief WGPT1 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_WGPT1A_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD8); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_GPT_USE_WGPT2 +#if !defined(TIVA_WGPT2A_HANDLER) +#error "TIVA_WGPT2A_HANDLER not defined" +#endif +/** + * @brief WGPT2 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_WGPT2A_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD9); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_GPT_USE_WGPT3 +#if !defined(TIVA_WGPT3A_HANDLER) +#error "TIVA_WGPT3A_HANDLER not defined" +#endif +/** + * @brief WGPT3 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_WGPT3A_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD10); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_GPT_USE_WGPT4 +#if !defined(TIVA_WGPT4A_HANDLER) +#error "TIVA_WGPT4A_HANDLER not defined" +#endif +/** + * @brief WGPT4 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_WGPT4A_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD11); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_GPT_USE_WGPT5 +#if !defined(TIVA_WGPT5A_HANDLER) +#error "TIVA_WGPT5A_HANDLER not defined" +#endif +/** + * @brief WGPT5 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_WGPT5A_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + gpt_lld_serve_interrupt(&GPTD12); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level GPT driver initialization. + * + * @notapi + */ +void gpt_lld_init(void) +{ + /* Driver initialization.*/ +#if TIVA_GPT_USE_GPT0 + GPTD1.gpt = GPT0; + gptObjectInit(&GPTD1); +#endif + +#if TIVA_GPT_USE_GPT1 + GPTD2.gpt = GPT1; + gptObjectInit(&GPTD2); +#endif + +#if TIVA_GPT_USE_GPT2 + GPTD3.gpt = GPT2; + gptObjectInit(&GPTD3); +#endif + +#if TIVA_GPT_USE_GPT3 + GPTD4.gpt = GPT3; + gptObjectInit(&GPTD4); +#endif + +#if TIVA_GPT_USE_GPT4 + GPTD5.gpt = GPT4; + gptObjectInit(&GPTD5); +#endif + +#if TIVA_GPT_USE_GPT5 + GPTD6.gpt = GPT5; + gptObjectInit(&GPTD6); +#endif + +#if TIVA_GPT_USE_WGPT0 + GPTD7.gpt = WGPT0; + gptObjectInit(&GPTD7); +#endif + +#if TIVA_GPT_USE_WGPT1 + GPTD8.gpt = WGPT1; + gptObjectInit(&GPTD8); +#endif + +#if TIVA_GPT_USE_WGPT2 + GPTD9.gpt = WGPT2; + gptObjectInit(&GPTD9); +#endif + +#if TIVA_GPT_USE_WGPT3 + GPTD10.gpt = WGPT3; + gptObjectInit(&GPTD10); +#endif + +#if TIVA_GPT_USE_WGPT4 + GPTD11.gpt = WGPT4; + gptObjectInit(&GPTD11); +#endif + +#if TIVA_GPT_USE_WGPT5 + GPTD12.gpt = WGPT5; + gptObjectInit(&GPTD12); +#endif +} + +/** + * @brief Configures and activates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_start(GPTDriver *gptp) +{ + if (gptp->state == GPT_STOP) { + /* Clock activation.*/ +#if TIVA_GPT_USE_GPT0 + if (&GPTD1 == gptp) { + SYSCTL->RCGCTIMER |= (1 << 0); + + while (!(SYSCTL->PRTIMER & (1 << 0))) + ; + + nvicEnableVector(TIVA_GPT0A_NUMBER, TIVA_GPT_GPT0A_IRQ_PRIORITY); + } +#endif + +#if TIVA_GPT_USE_GPT1 + if (&GPTD2 == gptp) { + SYSCTL->RCGCTIMER |= (1 << 1); + + while (!(SYSCTL->PRTIMER & (1 << 1))) + ; + + nvicEnableVector(TIVA_GPT1A_NUMBER, TIVA_GPT_GPT1A_IRQ_PRIORITY); + } +#endif + +#if TIVA_GPT_USE_GPT2 + if (&GPTD3 == gptp) { + SYSCTL->RCGCTIMER |= (1 << 2); + + while (!(SYSCTL->PRTIMER & (1 << 2))) + ; + + nvicEnableVector(TIVA_GPT2A_NUMBER, TIVA_GPT_GPT2A_IRQ_PRIORITY); + } +#endif + +#if TIVA_GPT_USE_GPT3 + if (&GPTD4 == gptp) { + SYSCTL->RCGCTIMER |= (1 << 3); + + while (!(SYSCTL->PRTIMER & (1 << 3))) + ; + + nvicEnableVector(TIVA_GPT3A_NUMBER, TIVA_GPT_GPT3A_IRQ_PRIORITY); + } +#endif + +#if TIVA_GPT_USE_GPT4 + if (&GPTD5 == gptp) { + SYSCTL->RCGCTIMER |= (1 << 4); + + while (!(SYSCTL->PRTIMER & (1 << 4))) + ; + + nvicEnableVector(TIVA_GPT4A_NUMBER, TIVA_GPT_GPT4A_IRQ_PRIORITY); + } +#endif + +#if TIVA_GPT_USE_GPT5 + if (&GPTD6 == gptp) { + SYSCTL->RCGCTIMER |= (1 << 5); + + while (!(SYSCTL->PRTIMER & (1 << 5))) + ; + + nvicEnableVector(TIVA_GPT5A_NUMBER, TIVA_GPT_GPT5A_IRQ_PRIORITY); + } +#endif + +#if TIVA_GPT_USE_WGPT0 + if (&GPTD7 == gptp) { + SYSCTL->RCGCWTIMER |= (1 << 0); + + while (!(SYSCTL->PRWTIMER & (1 << 0))) + ; + + nvicEnableVector(TIVA_WGPT0A_NUMBER, TIVA_GPT_WGPT0A_IRQ_PRIORITY); + } +#endif + +#if TIVA_GPT_USE_WGPT1 + if (&GPTD8 == gptp) { + SYSCTL->RCGCWTIMER |= (1 << 1); + + while (!(SYSCTL->PRWTIMER & (1 << 1))) + ; + + nvicEnableVector(TIVA_WGPT1A_NUMBER, TIVA_GPT_WGPT1A_IRQ_PRIORITY); + } +#endif + +#if TIVA_GPT_USE_WGPT2 + if (&GPTD9 == gptp) { + SYSCTL->RCGCWTIMER |= (1 << 2); + + while (!(SYSCTL->PRWTIMER & (1 << 2))) + ; + + nvicEnableVector(TIVA_WGPT2A_NUMBER, TIVA_GPT_WGPT2A_IRQ_PRIORITY); + } +#endif + +#if TIVA_GPT_USE_WGPT3 + if (&GPTD10 == gptp) { + SYSCTL->RCGCWTIMER |= (1 << 3); + + while (!(SYSCTL->PRWTIMER & (1 << 3))) + ; + + nvicEnableVector(TIVA_WGPT3A_NUMBER, TIVA_GPT_WGPT3A_IRQ_PRIORITY); + } +#endif + +#if TIVA_GPT_USE_WGPT4 + if (&GPTD11 == gptp) { + SYSCTL->RCGCWTIMER |= (1 << 4); + + while (!(SYSCTL->PRWTIMER & (1 << 4))) + ; + + nvicEnableVector(TIVA_WGPT4A_NUMBER, TIVA_GPT_WGPT4A_IRQ_PRIORITY); + } +#endif + +#if TIVA_GPT_USE_WGPT5 + if (&GPTD12 == gptp) { + SYSCTL->RCGCWTIMER |= (1 << 5); + + while (!(SYSCTL->PRWTIMER & (1 << 5))) + ; + + nvicEnableVector(TIVA_WGPT5A_NUMBER, TIVA_GPT_WGPT5A_IRQ_PRIORITY); + } +#endif + } + + /* Timer configuration.*/ + gptp->gpt->CTL = 0; + gptp->gpt->CFG = GPTM_CFG_CFG_SPLIT; + gptp->gpt->TAPR = ((TIVA_SYSCLK / gptp->config->frequency) - 1); +} + +/** + * @brief Deactivates the GPT peripheral. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop(GPTDriver *gptp) +{ + if (gptp->state == GPT_READY) { + gptp->gpt->IMR = 0; + gptp->gpt->TAILR = 0; + gptp->gpt->CTL = 0; + +#if TIVA_GPT_USE_GPT0 + if (&GPTD1 == gptp) { + nvicDisableVector(TIVA_GPT0A_NUMBER); + SYSCTL->RCGCTIMER &= ~(1 << 0); + } +#endif + +#if TIVA_GPT_USE_GPT1 + if (&GPTD2 == gptp) { + nvicDisableVector(TIVA_GPT1A_NUMBER); + SYSCTL->RCGCTIMER &= ~(1 << 1); + } +#endif + +#if TIVA_GPT_USE_GPT2 + if (&GPTD3 == gptp) { + nvicDisableVector(TIVA_GPT2A_NUMBER); + SYSCTL->RCGCTIMER &= ~(1 << 2); + } +#endif + +#if TIVA_GPT_USE_GPT3 + if (&GPTD4 == gptp) { + nvicDisableVector(TIVA_GPT3A_NUMBER); + SYSCTL->RCGCTIMER &= ~(1 << 3); + } +#endif + +#if TIVA_GPT_USE_GPT4 + if (&GPTD5 == gptp) { + nvicDisableVector(TIVA_GPT4A_NUMBER); + SYSCTL->RCGCTIMER &= ~(1 << 4); + } +#endif + +#if TIVA_GPT_USE_GPT5 + if (&GPTD6 == gptp) { + nvicDisableVector(TIVA_GPT5A_NUMBER); + SYSCTL->RCGCTIMER &= ~(1 << 5); + } +#endif + +#if TIVA_GPT_USE_WGPT0 + if (&GPTD7 == gptp) { + nvicDisableVector(TIVA_WGPT0A_NUMBER); + SYSCTL->RCGCWTIMER &= ~(1 << 0); + } +#endif + +#if TIVA_GPT_USE_WGPT1 + if (&GPTD8 == gptp) { + nvicDisableVector(TIVA_WGPT1A_NUMBER); + SYSCTL->RCGCWTIMER &= ~(1 << 1); + } +#endif + +#if TIVA_GPT_USE_WGPT2 + if (&GPTD9 == gptp) { + nvicDisableVector(TIVA_WGPT2A_NUMBER); + SYSCTL->RCGCWTIMER &= ~(1 << 2); + } +#endif + +#if TIVA_GPT_USE_WGPT3 + if (&GPTD10 == gptp) { + nvicDisableVector(TIVA_WGPT3A_NUMBER); + SYSCTL->RCGCWTIMER &= ~(1 << 3); + } +#endif + +#if TIVA_GPT_USE_WGPT4 + if (&GPTD11 == gptp) { + nvicDisableVector(TIVA_WGPT4A_NUMBER); + SYSCTL->RCGCWTIMER &= ~(1 << 4); + } +#endif + +#if TIVA_GPT_USE_WGPT5 + if (&GPTD12 == gptp) { + nvicDisableVector(TIVA_WGPT5A_NUMBER); + SYSCTL->RCGCWTIMER &= ~(1 << 5); + } +#endif + } +} + +/** + * @brief Starts the timer in continuous mode. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval period in ticks + * + * @notapi + */ +void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) +{ + gptp->gpt->TAILR = interval - 1; + gptp->gpt->ICR = 0xfffffff; + gptp->gpt->IMR = GPTM_IMR_TATOIM; + gptp->gpt->TAMR = GPTM_TAMR_TAMR_PERIODIC | GPTM_TAMR_TAILD | GPTM_TAMR_TASNAPS; + gptp->gpt->CTL = GPTM_CTL_TAEN | GPTM_CTL_TASTALL; +} + +/** + * @brief Stops the timer. + * + * @param[in] gptp pointer to the @p GPTDriver object + * + * @notapi + */ +void gpt_lld_stop_timer(GPTDriver *gptp) +{ + gptp->gpt->IMR = 0; + gptp->gpt->TAILR = 0; + gptp->gpt->CTL &= ~GPTM_CTL_TAEN; +} + +/** + * @brief Starts the timer in one shot mode and waits for completion. + * @details This function specifically polls the timer waiting for completion + * in order to not have extra delays caused by interrupt servicing, + * this function is only recommended for short delays. + * + * @param[in] gptp pointer to the @p GPTDriver object + * @param[in] interval time interval in ticks + * + * @notapi + */ +void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) +{ + gptp->gpt->TAMR = GPTM_TAMR_TAMR_ONESHOT | GPTM_TAMR_TAILD | GPTM_TAMR_TASNAPS; + gptp->gpt->TAILR = interval - 1; + gptp->gpt->ICR = 0xffffffff; + gptp->gpt->CTL = GPTM_CTL_TAEN | GPTM_CTL_TASTALL; + while (!(gptp->gpt->RIS & GPTM_IMR_TATOIM)) + ; + gptp->gpt->ICR = 0xffffffff; +} + +#endif /* HAL_USE_GPT */ + +/** @} */ diff --git a/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.h b/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.h new file mode 100644 index 0000000..e518e58 --- /dev/null +++ b/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.h @@ -0,0 +1,501 @@ +/* + Copyright (C) 2014..2016 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file TIVA/gpt_lld.h + * @brief TM4C123x/TM4C129x GPT subsystem low level driver header. + * + * @addtogroup GPT + * @{ + */ + +#ifndef HAL_GPT_LLD_H +#define HAL_GPT_LLD_H + +#if HAL_USE_GPT || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ + +/** + * @brief GPTD1 driver enable switch. + * @details If set to @p TRUE the support for GPTD1 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_GPT_USE_GPT0) || defined(__DOXYGEN__) +#define TIVA_GPT_USE_GPT0 FALSE +#endif + +/** + * @brief GPTD2 driver enable switch. + * @details If set to @p TRUE the support for GPTD2 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_GPT_USE_GPT1) || defined(__DOXYGEN__) +#define TIVA_GPT_USE_GPT1 FALSE +#endif + +/** + * @brief GPTD3 driver enable switch. + * @details If set to @p TRUE the support for GPTD3 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_GPT_USE_GPT2) || defined(__DOXYGEN__) +#define TIVA_GPT_USE_GPT2 FALSE +#endif + +/** + * @brief GPTD4 driver enable switch. + * @details If set to @p TRUE the support for GPTD4 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_GPT_USE_GPT3) || defined(__DOXYGEN__) +#define TIVA_GPT_USE_GPT3 FALSE +#endif + +/** + * @brief GPTD5 driver enable switch. + * @details If set to @p TRUE the support for GPTD5 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_GPT_USE_GPT4) || defined(__DOXYGEN__) +#define TIVA_GPT_USE_GPT4 FALSE +#endif + +/** + * @brief GPTD6 driver enable switch. + * @details If set to @p TRUE the support for GPTD6 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_GPT_USE_GPT5) || defined(__DOXYGEN__) +#define TIVA_GPT_USE_GPT5 FALSE +#endif + +/** + * @brief GPTD7 driver enable switch. + * @details If set to @p TRUE the support for GPTD1 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_GPT_USE_WGPT0) || defined(__DOXYGEN__) +#define TIVA_GPT_USE_WGPT0 FALSE +#endif + +/** + * @brief GPTD8 driver enable switch. + * @details If set to @p TRUE the support for GPTD2 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_GPT_USE_WGPT1) || defined(__DOXYGEN__) +#define TIVA_GPT_USE_WGPT1 FALSE +#endif + +/** + * @brief GPTD9 driver enable switch. + * @details If set to @p TRUE the support for GPTD3 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_GPT_USE_WGPT2) || defined(__DOXYGEN__) +#define TIVA_GPT_USE_WGPT2 FALSE +#endif + +/** + * @brief GPTD10 driver enable switch. + * @details If set to @p TRUE the support for GPTD4 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_GPT_USE_WGPT3) || defined(__DOXYGEN__) +#define TIVA_GPT_USE_WGPT3 FALSE +#endif + +/** + * @brief GPTD11 driver enable switch. + * @details If set to @p TRUE the support for GPTD5 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_GPT_USE_WGPT4) || defined(__DOXYGEN__) +#define TIVA_GPT_USE_WGPT4 FALSE +#endif + +/** + * @brief GPTD12 driver enable switch. + * @details If set to @p TRUE the support for GPTD6 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_GPT_USE_WGPT5) || defined(__DOXYGEN__) +#define TIVA_GPT_USE_WGPT5 FALSE +#endif + +/** + * @brief GPTD1 interrupt priority level setting. + */ +#if !defined(TIVA_GPT_GPT0A_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_GPT_GPT0A_IRQ_PRIORITY 7 +#endif + +/** + * @brief GPTD2 interrupt priority level setting. + */ +#if !defined(TIVA_GPT_GPT1A_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_GPT_GPT1A_IRQ_PRIORITY 7 +#endif + +/** + * @brief GPTD3 interrupt priority level setting. + */ +#if !defined(TIVA_GPT_GPT2A_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_GPT_GPT2A_IRQ_PRIORITY 7 +#endif + +/** + * @brief GPTD4 interrupt priority level setting. + */ +#if !defined(TIVA_GPT_GPT3A_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_GPT_GPT3A_IRQ_PRIORITY 7 +#endif + +/** + * @brief GPTD5 interrupt priority level setting. + */ +#if !defined(TIVA_GPT_GPT4A_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_GPT_GPT4A_IRQ_PRIORITY 7 +#endif + +/** + * @brief GPTD6 interrupt priority level setting. + */ +#if !defined(TIVA_GPT_GPT5A_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_GPT_GPT5A_IRQ_PRIORITY 7 +#endif + +/** + * @brief GPTD7 interrupt priority level setting. + */ +#if !defined(TIVA_GPT_WGPT0A_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_GPT_WGPT0A_IRQ_PRIORITY 7 +#endif + +/** + * @brief GPTD8 interrupt priority level setting. + */ +#if !defined(TIVA_GPT_WGPT1A_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_GPT_WGPT1A_IRQ_PRIORITY 7 +#endif + +/** + * @brief GPTD9 interrupt priority level setting. + */ +#if !defined(TIVA_GPT_WGPT2A_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_GPT_WGPT2A_IRQ_PRIORITY 7 +#endif + +/** + * @brief GPTD10 interrupt priority level setting. + */ +#if !defined(TIVA_GPT_WGPT3A_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_GPT_WGPT3A_IRQ_PRIORITY 7 +#endif + +/** + * @brief GPTD11 interrupt priority level setting. + */ +#if !defined(TIVA_GPT_WGPT4A_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_GPT_WGPT4A_IRQ_PRIORITY 7 +#endif + +/** + * @brief GPTD12 interrupt priority level setting. + */ +#if !defined(TIVA_GPT_WGPT5A_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_GPT_WGPT5A_IRQ_PRIORITY 7 +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if TIVA_GPT_USE_GPT0 && !TIVA_HAS_GPT0 +#error "GPT0 not present in the selected device" +#endif + +#if TIVA_GPT_USE_GPT1 && !TIVA_HAS_GPT1 +#error "GPT1 not present in the selected device" +#endif + +#if TIVA_GPT_USE_GPT2 && !TIVA_HAS_GPT2 +#error "GPT2 not present in the selected device" +#endif + +#if TIVA_GPT_USE_GPT3 && !TIVA_HAS_GPT3 +#error "GPT3 not present in the selected device" +#endif + +#if TIVA_GPT_USE_GPT4 && !TIVA_HAS_GPT4 +#error "GPT4 not present in the selected device" +#endif + +#if TIVA_GPT_USE_GPT5 && !TIVA_HAS_GPT5 +#error "GPT5 not present in the selected device" +#endif + +#if TIVA_GPT_USE_WGPT0 && !TIVA_HAS_WGPT0 +#error "WGPT0 not present in the selected device" +#endif + +#if TIVA_GPT_USE_WGPT1 && !TIVA_HAS_WGPT1 +#error "WGPT1 not present in the selected device" +#endif + +#if TIVA_GPT_USE_WGPT2 && !TIVA_HAS_WGPT2 +#error "WGPT2 not present in the selected device" +#endif + +#if TIVA_GPT_USE_WGPT3 && !TIVA_HAS_WGPT3 +#error "WGPT3 not present in the selected device" +#endif + +#if TIVA_GPT_USE_WGPT4 && !TIVA_HAS_WGPT4 +#error "WGPT4 not present in the selected device" +#endif + +#if TIVA_GPT_USE_WGPT5 && !TIVA_HAS_WGPT5 +#error "WGPT5 not present in the selected device" +#endif + +#if !TIVA_GPT_USE_GPT0 && !TIVA_GPT_USE_GPT1 && !TIVA_GPT_USE_GPT2 && \ + !TIVA_GPT_USE_GPT3 && !TIVA_GPT_USE_GPT4 && !TIVA_GPT_USE_GPT5 && \ + !TIVA_GPT_USE_WGPT0 && !TIVA_GPT_USE_WGPT1 && !TIVA_GPT_USE_WGPT2 && \ + !TIVA_GPT_USE_WGPT3 && !TIVA_GPT_USE_WGPT4 && !TIVA_GPT_USE_WGPT5 +#error "GPT driver activated but no (W)GPT peripheral assigned" +#endif + +#if TIVA_GPT_USE_GPT0 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_GPT0A_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPT0" +#endif + +#if TIVA_GPT_USE_GPT1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_GPT1A_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPT1" +#endif + +#if TIVA_GPT_USE_GPT2 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_GPT2A_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPT2" +#endif + +#if TIVA_GPT_USE_GPT3 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_GPT3A_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPT3" +#endif + +#if TIVA_GPT_USE_GPT4 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_GPT4A_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPT4" +#endif + +#if TIVA_GPT_USE_GPT5 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_GPT5A_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPT5" +#endif + +#if TIVA_GPT_USE_WGPT0 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_WGPT0A_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to WGPT0" +#endif + +#if TIVA_GPT_USE_WGPT1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_WGPT1A_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to WGPT1" +#endif + +#if TIVA_GPT_USE_WGPT2 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_WGPT2A_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to WGPT2" +#endif + +#if TIVA_GPT_USE_WGPT3 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_WGPT3A_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to WGPT3" +#endif + +#if TIVA_GPT_USE_WGPT4 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_WGPT4A_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to WGPT4" +#endif + +#if TIVA_GPT_USE_WGPT5 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_WGPT5A_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to WGPT5" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief GPT frequency type. + */ +typedef uint32_t gptfreq_t; + +/** + * @brief GPT counter type. + */ +typedef uint16_t gptcnt_t; + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct { + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + gptfreq_t frequency; + /** + * @brief Timer callback pointer. + * @note This callback is invoked on GPT counter events. + */ + gptcallback_t callback; + /* End of the mandatory fields.*/ +} GPTConfig; + +/** + * @brief Structure representing a GPT driver. + */ +struct GPTDriver { + /** + * @brief Driver state. + */ + gptstate_t state; + /** + * @brief Current configuration data. + */ + const GPTConfig *config; +#if defined(GPT_DRIVER_EXT_FIELDS) + GPT_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the GPT registers block. + */ + GPT_TypeDef *gpt; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Changes the interval of GPT peripheral. + * @details This function changes the interval of a running GPT unit. + * @pre The GPT unit must have been activated using @p gptStart(). + * @pre The GPT unit must have been running in continuous mode using + * @p gptStartContinuous(). + * @post The GPT unit interval is changed to the new value. + * @note The function has effect at the next cycle start. + * + * @param[in] gptp pointer to a @p GPTDriver object + * @param[in] interval new cycle time in timer ticks + * @notapi + */ +#define gpt_lld_change_interval(gptp, interval) { \ + gptp->gpt->TAILR = interval - 1; \ +} + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if TIVA_GPT_USE_GPT0 && !defined(__DOXYGEN__) +extern GPTDriver GPTD1; +#endif + +#if TIVA_GPT_USE_GPT1 && !defined(__DOXYGEN__) +extern GPTDriver GPTD2; +#endif + +#if TIVA_GPT_USE_GPT2 && !defined(__DOXYGEN__) +extern GPTDriver GPTD3; +#endif + +#if TIVA_GPT_USE_GPT3 && !defined(__DOXYGEN__) +extern GPTDriver GPTD4; +#endif + +#if TIVA_GPT_USE_GPT4 && !defined(__DOXYGEN__) +extern GPTDriver GPTD5; +#endif + +#if TIVA_GPT_USE_GPT5 && !defined(__DOXYGEN__) +extern GPTDriver GPTD6; +#endif + +#if TIVA_GPT_USE_WGPT0 && !defined(__DOXYGEN__) +extern GPTDriver GPTD7; +#endif + +#if TIVA_GPT_USE_WGPT1 && !defined(__DOXYGEN__) +extern GPTDriver GPTD8; +#endif + +#if TIVA_GPT_USE_WGPT2 && !defined(__DOXYGEN__) +extern GPTDriver GPTD9; +#endif + +#if TIVA_GPT_USE_WGPT3 && !defined(__DOXYGEN__) +extern GPTDriver GPTD10; +#endif + +#if TIVA_GPT_USE_WGPT4 && !defined(__DOXYGEN__) +extern GPTDriver GPTD11; +#endif + +#if TIVA_GPT_USE_WGPT5 && !defined(__DOXYGEN__) +extern GPTDriver GPTD12; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void gpt_lld_init(void); + void gpt_lld_start(GPTDriver *gptp); + void gpt_lld_stop(GPTDriver *gptp); + void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period); + void gpt_lld_stop_timer(GPTDriver *gptp); + void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_GPT */ + +#endif /* HAL_GPT_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c new file mode 100644 index 0000000..30fdb8a --- /dev/null +++ b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c @@ -0,0 +1,253 @@ +/* + Copyright (C) 2014..2016 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file Tiva/LLD/st_lld.c + * @brief ST Driver subsystem low level driver code. + * + * @addtogroup ST + * @{ + */ + +#include "hal.h" + +#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING + +#if (TIVA_ST_USE_WIDE_TIMER == TRUE) + +#if TIVA_ST_TIMER_NUMBER == 0 +#define ST_HANDLER TIVA_WGPT0A_HANDLER +#define ST_NUMBER TIVA_WGPT0A_NUMBER +#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 0)) +#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 0))) + +#elif TIVA_ST_TIMER_NUMBER == 1 +#define ST_HANDLER TIVA_WGPT1A_HANDLER +#define ST_NUMBER TIVA_WGPT1A_NUMBER +#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 1)) +#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 1))) + +#elif TIVA_ST_TIMER_NUMBER == 2 +#define ST_HANDLER TIVA_WGPT2A_HANDLER +#define ST_NUMBER TIVA_WGPT2A_NUMBER +#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 2)) +#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 2))) + +#elif TIVA_ST_TIMER_NUMBER == 3 +#define ST_HANDLER TIVA_WGPT3A_HANDLER +#define ST_NUMBER TIVA_WGPT3A_NUMBER +#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 3)) +#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 3))) + +#elif TIVA_ST_TIMER_NUMBER == 4 +#define ST_HANDLER TIVA_WGPT4A_HANDLER +#define ST_NUMBER TIVA_WGPT4A_NUMBER +#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 4)) +#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 4))) + +#elif TIVA_ST_TIMER_NUMBER == 5 +#define ST_HANDLER TIVA_WGPT5A_HANDLER +#define ST_NUMBER TIVA_WGPT5A_NUMBER +#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 5)) +#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 5))) + +#else +#error "TIVA_ST_USE_TIMER specifies an unsupported timer" +#endif + +#if (ST_CLOCK_SRC / OSAL_ST_FREQUENCY) - 1 > 0xFFFF +#error "the selected ST frequency is not obtainable because TIM timer prescaler limits" +#endif + +#elif (TIVA_ST_USE_WIDE_TIMER == FALSE) + +#if TIVA_ST_TIMER_NUMBER == 0 +#define ST_HANDLER TIVA_GPT0A_HANDLER +#define ST_NUMBER TIVA_GPT0A_NUMBER +#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 0)) +#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 0))) + +#elif TIVA_ST_TIMER_NUMBER == 1 +#define ST_HANDLER TIVA_GPT1A_HANDLER +#define ST_NUMBER TIVA_GPT1A_NUMBER +#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 1)) +#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 1))) + +#elif TIVA_ST_TIMER_NUMBER == 2 +#define ST_HANDLER TIVA_GPT2A_HANDLER +#define ST_NUMBER TIVA_GPT2A_NUMBER +#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 2)) +#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 2))) + +#elif TIVA_ST_TIMER_NUMBER == 3 +#define ST_HANDLER TIVA_GPT3A_HANDLER +#define ST_NUMBER TIVA_GPT3A_NUMBER +#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 3)) +#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 3))) + +#elif TIVA_ST_TIMER_NUMBER == 4 +#define ST_HANDLER TIVA_GPT4A_HANDLER +#define ST_NUMBER TIVA_GPT4A_NUMBER +#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 4)) +#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 4))) + +#elif TIVA_ST_TIMER_NUMBER == 5 +#define ST_HANDLER TIVA_GPT5A_HANDLER +#define ST_NUMBER TIVA_GPT5A_NUMBER +#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 5)) +#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 5))) + +#else +#error "TIVA_ST_USE_TIMER specifies an unsupported timer" +#endif + +#if (TIVA_SYSCLK / OSAL_ST_FREQUENCY) - 1 > 0xFF +#error "the selected ST frequency is not obtainable because TIM timer prescaler limits" +#endif + +#endif + +#if TIVA_SYSCLK % OSAL_ST_FREQUENCY != 0 +#error "the selected ST frequency is not obtainable because integer rounding" +#endif + +#endif + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if (OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) || defined(__DOXYGEN__) +/** + * @brief System Timer vector. + * @details This interrupt is used for system tick in periodic mode. + * + * @isr + */ +OSAL_IRQ_HANDLER(SysTick_Handler) +{ + OSAL_IRQ_PROLOGUE(); + + osalSysLockFromISR(); + osalOsTimerHandlerI(); + osalSysUnlockFromISR(); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */ + +#if (OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING) || defined(__DOXYGEN__) +/** + * @brief GPT interrupt handler. + * @details This interrupt is used for system tick in free running mode. + * + * @isr + */ +OSAL_IRQ_HANDLER(ST_HANDLER) +{ + uint32_t mis; + + OSAL_IRQ_PROLOGUE(); + + mis = TIVA_ST_TIM->MIS; + TIVA_ST_TIM->ICR = mis; + + if (mis & GPTM_IMR_TAMIM) { + osalSysLockFromISR(); + osalOsTimerHandlerI(); + osalSysUnlockFromISR(); + } + + OSAL_IRQ_EPILOGUE(); +} +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level ST driver initialization. + * + * @notapi + */ +void st_lld_init(void) +{ +#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING + /* Free running counter mode.*/ + + /* Enabling timer clock.*/ + ST_ENABLE_CLOCK(); + + /* Wait until timer peripheral is ready */ + ST_WAIT_CLOCK(); + + /* Initializing the counter in free running down mode.*/ + TIVA_ST_TIM->CTL = 0; + TIVA_ST_TIM->CFG = GPTM_CFG_CFG_SPLIT; /* Timer split mode */ + TIVA_ST_TIM->TAMR = (GPTM_TAMR_TAMR_PERIODIC |/* Periodic mode */ + GPTM_TAMR_TAMIE | /* Match interrupt enable */ + GPTM_TAMR_TASNAPS); /* Snapshot mode */ + + TIVA_ST_TIM->TAPR = (TIVA_SYSCLK / OSAL_ST_FREQUENCY) - 1; + TIVA_ST_TIM->CTL = (GPTM_CTL_TAEN | /* Timer A enable */ + GPTM_CTL_TASTALL); /* Timer A stall when paused */ + + /* IRQ enabled.*/ + nvicEnableVector(ST_NUMBER, TIVA_ST_IRQ_PRIORITY); +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */ + +#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC + /* Periodic systick mode, the Cortex-Mx internal systick timer is used + in this mode.*/ + SysTick->LOAD = (TIVA_SYSCLK / OSAL_ST_FREQUENCY) - 1; + SysTick->VAL = 0; + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_ENABLE_Msk | + SysTick_CTRL_TICKINT_Msk; + + /* IRQ enabled.*/ + nvicSetSystemHandlerPriority(HANDLER_SYSTICK, TIVA_ST_IRQ_PRIORITY); +#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */ +} + +#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */ + +/** + * @} + */ diff --git a/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.h b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.h new file mode 100644 index 0000000..35bf008 --- /dev/null +++ b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.h @@ -0,0 +1,276 @@ +/* + Copyright (C) 2014..2016 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file Tiva/LLD/st_lld.h + * @brief ST Driver subsystem low level driver header. + * @details This header is designed to be include-able without having to + * include other files from the HAL. + * + * @addtogroup ST + * @{ + */ + +#ifndef HAL_ST_LLD_H +#define HAL_ST_LLD_H + +#include "mcuconf.h" +#include "tiva_registry.h" +#include "tiva_gpt.h" + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ + +/** + * @brief SysTick timer IRQ priority. + */ +#if !defined(TIVA_ST_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_ST_IRQ_PRIORITY 2 +#endif + +/** + * @brief GPTx unit (by number) to be used for free running operations. + * @note You must select a 32 bits timer if a 32 bits @p systick_t type + * is required. + */ +#if !defined(TIVA_ST_TIMER_NUMBER) || defined(__DOXYGEN__) +#define TIVA_ST_TIMER_NUMBER 0 +#endif + +/** + * @brief When set to @p TRUE a wide timer is used. When set to @p FALSE a + * normal timer is used. + */ +#if !defined(TIVA_ST_USE_WIDE_TIMER) || defined(__DOXYGEN__) +#define TIVA_ST_USE_WIDE_TIMER TRUE +#endif + +/** + * @} + */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if (TIVA_ST_USE_WIDE_TIMER == TRUE) + +#if TIVA_ST_TIMER_NUMBER == 0 +#if !TIVA_HAS_WGPT0 +#error "WGPT0 not present" +#endif +#define TIVA_ST_TIM WGPT0 + +#elif TIVA_ST_TIMER_NUMBER == 1 +#if !TIVA_HAS_WGPT1 +#error "WGPT1 not present" +#endif +#define TIVA_ST_TIM WGPT1 + +#elif TIVA_ST_TIMER_NUMBER == 2 +#if !TIVA_HAS_WGPT2 +#error "WGPT2 not present" +#endif +#define TIVA_ST_TIM WGPT2 + +#elif TIVA_ST_TIMER_NUMBER == 3 +#if !TIVA_HAS_WGPT3 +#error "WGPT3 not present" +#endif +#define TIVA_ST_TIM WGPT3 + +#elif TIVA_ST_TIMER_NUMBER == 4 +#if !TIVA_HAS_WGPT4 +#error "WGPT4 not present" +#endif +#define TIVA_ST_TIM WGPT4 + +#elif TIVA_ST_TIMER_NUMBER == 5 +#if !TIVA_HAS_WGPT5 +#error "WGPT5 not present" +#endif +#define TIVA_ST_TIM WGPT5 + +#else +#error "TIVA_ST_USE_TIMER specifies an unsupported timer" +#endif + +#elif (TIVA_ST_USE_WIDE_TIMER == FALSE) + +#if TIVA_ST_TIMER_NUMBER == 0 +#if !TIVA_HAS_GPT0 +#error "GPT0 not present" +#endif +#define TIVA_ST_TIM GPT0 + +#elif TIVA_ST_TIMER_NUMBER == 1 +#if !TIVA_HAS_GPT1 +#error "GPT1 not present" +#endif +#define TIVA_ST_TIM GPT1 + +#elif TIVA_ST_TIMER_NUMBER == 2 +#if !TIVA_HAS_GPT2 +#error "GPT2 not present" +#endif +#define TIVA_ST_TIM GPT2 + +#elif TIVA_ST_TIMER_NUMBER == 3 +#if !TIVA_HAS_GPT3 +#error "GPT3 not present" +#endif +#define TIVA_ST_TIM GPT3 + +#elif TIVA_ST_TIMER_NUMBER == 4 +#if !TIVA_HAS_GPT4 +#error "GPT4 not present" +#endif +#define TIVA_ST_TIM GPT4 + +#elif TIVA_ST_TIMER_NUMBER == 5 +#if !TIVA_HAS_GPT5 +#error "GPT5 not present" +#endif +#define TIVA_ST_TIM GPT5 + +#else +#error "TIVA_ST_TIMER_NUMBER specifies an unsupported timer" +#endif + +#else +#error "wrong value defined for TIVA_ST_USE_WIDE_TIMER" +#endif + +#if OSAL_ST_MODE != OSAL_ST_MODE_NONE && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_ST_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to ST" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#ifdef __cplusplus +extern "C" { +#endif + void st_lld_init(void); +#ifdef __cplusplus +} +#endif + +/*===========================================================================*/ +/* Driver inline functions. */ +/*===========================================================================*/ + +/** + * @brief Returns the time counter value. + * + * @return The counter value. + * + * @notapi + */ +static inline systime_t st_lld_get_counter(void) +{ + return (systime_t) (((systime_t) 0xffffffff) - TIVA_ST_TIM->TAR); +} + +/** + * @brief Starts the alarm. + * @note Makes sure that no spurious alarms are triggered after + * this call. + * + * @param[in] time the time to be set for the first alarm + * + * @notapi + */ +static inline void st_lld_start_alarm(systime_t time) +{ + TIVA_ST_TIM->TAMATCHR = (systime_t) (((systime_t) 0xffffffff) - time); + TIVA_ST_TIM->ICR = TIVA_ST_TIM->MIS; + TIVA_ST_TIM->IMR = GPTM_IMR_TAMIM; +} + +/** + * @brief Stops the alarm interrupt. + * + * @notapi + */ +static inline void st_lld_stop_alarm(void) +{ + TIVA_ST_TIM->IMR = 0; +} + +/** + * @brief Sets the alarm time. + * + * @param[in] time the time to be set for the next alarm + * + * @notapi + */ +static inline void st_lld_set_alarm(systime_t time) +{ + TIVA_ST_TIM->TAMATCHR = (systime_t) (((systime_t) 0xffffffff) - time); +} + +/** + * @brief Returns the current alarm time. + * + * @return The currently set alarm time. + * + * @notapi + */ +static inline systime_t st_lld_get_alarm(void) +{ + return (systime_t) (((systime_t)0xffffffff) - TIVA_ST_TIM->TAMATCHR); +} + +/** + * @brief Determines if the alarm is active. + * + * @return The alarm status. + * @retval false if the alarm is not active. + * @retval true is the alarm is active + * + * @notapi + */ +static inline bool st_lld_is_alarm_active(void) +{ + return (bool) ((TIVA_ST_TIM->IMR & GPTM_IMR_TAMIM) !=0); +} + +#endif /* HAL_ST_LLD_H */ + +/** + * @} + */ diff --git a/os/hal/ports/TIVA/LLD/GPTM/tiva_gpt.h b/os/hal/ports/TIVA/LLD/GPTM/tiva_gpt.h new file mode 100644 index 0000000..114831b --- /dev/null +++ b/os/hal/ports/TIVA/LLD/GPTM/tiva_gpt.h @@ -0,0 +1,135 @@ +/* + Copyright (C) 2014..2016 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file tiva_gpt.h + * @brief TIVA GPT registers layout header. + * + * @addtogroup TIVA_GPT + * @{ + */ + +#ifndef TIVA_GPT_H_ +#define TIVA_GPT_H_ + +// cfg +#define GPTM_CFG_CFG_MASK (7 << 0) +#define GPTM_CFG_CFG_WHOLE (0 << 0) +#define GPTM_CFG_CFG_RTC (1 << 0) +#define GPTM_CFG_CFG_SPLIT (4 << 0) + +// tamr +#define GPTM_TAMR_TAMR_MASK (3 << 0) +#define GPTM_TAMR_TAMR_ONESHOT (1 << 0) +#define GPTM_TAMR_TAMR_PERIODIC (2 << 0) +#define GPTM_TAMR_TAMR_CAPTURE (3 << 0) + +#define GPTM_TAMR_TACMR (1 << 2) + +#define GPTM_TAMR_TAAMS (1 << 3) + +#define GPTM_TAMR_TACDIR (1 << 4) + +#define GPTM_TAMR_TAMIE (1 << 5) + +#define GPTM_TAMR_TAWOT (1 << 6) + +#define GPTM_TAMR_TASNAPS (1 << 7) + +#define GPTM_TAMR_TAILD (1 << 8) + +#define GPTM_TAMR_TAPWMIE (1 << 9) + +#define GPTM_TAMR_TAMRSU (1 << 10) + +#define GPTM_TAMR_TAPLO (1 << 11) + +// ctl +#define GPTM_CTL_TAEN (1 << 0) + +#define GPTM_CTL_TASTALL (1 << 1) + +#define GPTM_CTL_TAEVENT_MASK (3 << 2) +#define GPTM_CTL_TAEVENT_POS (0 << 2) +#define GPTM_CTL_TAEVENT_NEG (1 << 2) +#define GPTM_CTL_TAEVENT_BOTH (3 << 2) + +#define GPTM_CTL_RTCEN (1 << 4) + +#define GPTM_CTL_TAOTE (1 << 5) + +#define GPTM_CTL_TAPWML (1 << 6) + +#define GPTM_CTL_TBEN (1 << 8) + +#define GPTM_CTL_TBSTALL (1 << 9) + +#define GPTM_CTL_TBEVENT_MASK (3 << 10) +#define GPTM_CTL_TBEVENT_POS (0 << 10) +#define GPTM_CTL_TBEVENT_NEG (1 << 10) +#define GPTM_CTL_TBEVENT_BOTH (3 << 10) + +#define GPTM_CTL_TBOTE (1 << 13) + +#define GPTM_CTL_TBPWML (1 << 14) + +// imr +#define GPTM_IMR_TATOIM (1 << 0) + +#define GPTM_IMR_CAMIM (1 << 1) + +#define GPTM_IMR_CAEIM (1 << 2) + +#define GPTM_IMR_RTCIM (1 << 3) + +#define GPTM_IMR_TAMIM (1 << 4) + +#define GPTM_IMR_TBTOIM (1 << 8) + +#define GPTM_IMR_CBMIM (1 << 9) + +#define GPTM_IMR_CBEIM (1 << 10) + +#define GPTM_IMR_TBMIM (1 << 11) + +#define GPTM_IMR_WUEIM (1 << 16) + +// icr +#define GPTM_ICR_TATOCINT (1 << 0) + +#define GPTM_ICR_CAMCINT (1 << 1) + +#define GPTM_ICR_CAECINT (1 << 2) + +#define GPTM_ICR_RTCCINT (1 << 3) + +#define GPTM_ICR_TAMCINT (1 << 4) + +#define GPTM_ICR_TBTOCINT (1 << 8) + +#define GPTM_ICR_CBMCINT (1 << 9) + +#define GPTM_ICR_CBECINT (1 << 10) + +#define GPTM_ICR_TBMCINT (1 << 11) + +#define GPTM_ICR_WUECINT (1 << 16) + +#endif /* TIVA_GPT_H_ */ + +/* + * @} + */ diff --git a/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c new file mode 100644 index 0000000..cb69861 --- /dev/null +++ b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c @@ -0,0 +1,894 @@ +/* + Copyright (C) 2014..2016 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file TIVA/LLD/i2c_lld.c + * @brief TM4C123x/TM4C129x I2C subsystem low level driver source. + * + * @addtogroup I2C + * @{ + */ + +#include "hal.h" + +#if HAL_USE_I2C || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief I2C0 driver identifier. + */ +#if TIVA_I2C_USE_I2C0 || defined(__DOXYGEN__) +I2CDriver I2CD1; +#endif + +/** + * @brief I2C1 driver identifier. + */ +#if TIVA_I2C_USE_I2C1 || defined(__DOXYGEN__) +I2CDriver I2CD2; +#endif + +/** + * @brief I2C2 driver identifier. + */ +#if TIVA_I2C_USE_I2C2 || defined(__DOXYGEN__) +I2CDriver I2CD3; +#endif + +/** + * @brief I2C3 driver identifier. + */ +#if TIVA_I2C_USE_I2C3 || defined(__DOXYGEN__) +I2CDriver I2CD4; +#endif + +/** + * @brief I2C4 driver identifier. + */ +#if TIVA_I2C_USE_I2C4 || defined(__DOXYGEN__) +I2CDriver I2CD5; +#endif + +/** + * @brief I2C5 driver identifier. + */ +#if TIVA_I2C_USE_I2C5 || defined(__DOXYGEN__) +I2CDriver I2CD6; +#endif + +/** + * @brief I2C6 driver identifier. + */ +#if TIVA_I2C_USE_I2C6 || defined(__DOXYGEN__) +I2CDriver I2CD7; +#endif + +/** + * @brief I2C7 driver identifier. + */ +#if TIVA_I2C_USE_I2C7 || defined(__DOXYGEN__) +I2CDriver I2CD8; +#endif + +/** + * @brief I2C8 driver identifier. + */ +#if TIVA_I2C_USE_I2C8 || defined(__DOXYGEN__) +I2CDriver I2CD9; +#endif + +/** + * @brief I2C9 driver identifier. + */ +#if TIVA_I2C_USE_I2C9 || defined(__DOXYGEN__) +I2CDriver I2CD10; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief I2C shared ISR code. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +static void i2c_lld_serve_interrupt(I2CDriver *i2cp) +{ + I2C_TypeDef *dp = i2cp->i2c; + uint32_t status; + + // clear MIS bit in MICR by writing 1 + dp->MICR = 1; + + // read interrupt status + status = dp->MCS; + + if (status & TIVA_MCS_ERROR) { + i2cp->errors |= I2C_BUS_ERROR; + } + if (status & TIVA_MCS_ARBLST) { + i2cp->errors |= I2C_ARBITRATION_LOST; + } + + if (i2cp->errors == I2C_NO_ERROR) { + // no error detected + switch(i2cp->intstate) { + case STATE_IDLE: { + _i2c_wakeup_isr(i2cp); + break; + } + case STATE_WRITE_NEXT: { + if (i2cp->txbytes == 1) { + i2cp->intstate = STATE_WRITE_FINAL; + } + dp->MDR = *(i2cp->txbuf); + i2cp->txbuf++; + i2cp->txbytes--; + // start transmission + dp->MCS = TIVA_I2C_BURST_SEND_CONTINUE; + break; + } + case STATE_WRITE_FINAL: { + if (i2cp->rxbytes == 0) { + i2cp->intstate = STATE_IDLE; + } + else if (i2cp->rxbytes == 1) { + i2cp->intstate = STATE_READ_ONE; + } + else { + i2cp->intstate = STATE_READ_FIRST; + } + dp->MDR = *(i2cp->txbuf); + i2cp->txbuf++; + // txbytes - 1 + i2cp->txbytes--; + // start transmission + dp->MCS = TIVA_I2C_BURST_SEND_FINISH; + break; + } + case STATE_WAIT_ACK: { + break; + } + case STATE_SEND_ACK: { + break; + } + case STATE_READ_ONE: { + i2cp->intstate = STATE_READ_WAIT; + // Initializes driver fields, LSB = 1 -> read. + i2cp->addr |= 1; + + // set slave address + dp->MSA = i2cp->addr; + i2cp->rxbytes--; + //start receiving + dp->MCS = TIVA_I2C_SINGLE_RECEIVE; + + break; + } + case STATE_READ_FIRST: { + if (i2cp->rxbytes == 2) { + i2cp->intstate = STATE_READ_FINAL; + } + else { + i2cp->intstate = STATE_READ_NEXT; + } + + // Initializes driver fields, LSB = 1 -> read. + i2cp->addr |= 1; + + // set slave address + dp->MSA = i2cp->addr; + i2cp->rxbytes--; + //start receiving + dp->MCS = TIVA_I2C_BURST_RECEIVE_START; + + break; + } + case STATE_READ_NEXT: { + if(i2cp->rxbytes == 2) { + i2cp->intstate = STATE_READ_FINAL; + } + *(i2cp->rxbuf) = dp->MDR; + i2cp->rxbuf++; + i2cp->rxbytes--; + //start receiving + dp->MCS = TIVA_I2C_BURST_RECEIVE_CONTINUE; + + break; + } + case STATE_READ_FINAL: { + i2cp->intstate = STATE_READ_WAIT; + *(i2cp->rxbuf) = dp->MDR; + i2cp->rxbuf++; + i2cp->rxbytes--; + //start receiving + dp->MCS = TIVA_I2C_BURST_RECEIVE_FINISH; + + break; + } + case STATE_READ_WAIT: { + i2cp->intstate = STATE_IDLE; + *(i2cp->rxbuf) = dp->MDR; + i2cp->rxbuf++; + _i2c_wakeup_isr(i2cp); + break; + } + } + } + else { + // error detected + _i2c_wakeup_error_isr(i2cp); + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if TIVA_I2C_USE_I2C0 || defined(__DOXYGEN__) +/** + * @brief I2C0 interrupt handler. + * + * @notapi + */ +OSAL_IRQ_HANDLER(TIVA_I2C0_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + i2c_lld_serve_interrupt(&I2CD1); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* TIVA_I2C_USE_I2C0 */ + +#if TIVA_I2C_USE_I2C1 || defined(__DOXYGEN__) +/** + * @brief I2C1 interrupt handler. + * + * @notapi + */ +OSAL_IRQ_HANDLER(TIVA_I2C1_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + i2c_lld_serve_interrupt(&I2CD2); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* TIVA_I2C_USE_I2C1 */ + +#if TIVA_I2C_USE_I2C2 || defined(__DOXYGEN__) +/** + * @brief I2C2 interrupt handler. + * + * @notapi + */ +OSAL_IRQ_HANDLER(TIVA_I2C2_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + i2c_lld_serve_interrupt(&I2CD3); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* TIVA_I2C_USE_I2C2 */ + +#if TIVA_I2C_USE_I2C3 || defined(__DOXYGEN__) +/** + * @brief I2C3 interrupt handler. + * + * @notapi + */ +OSAL_IRQ_HANDLER(TIVA_I2C3_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + i2c_lld_serve_interrupt(&I2CD4); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* TIVA_I2C_USE_I2C3 */ + +#if TIVA_I2C_USE_I2C4 || defined(__DOXYGEN__) +/** + * @brief I2C4 interrupt handler. + * + * @notapi + */ +OSAL_IRQ_HANDLER(TIVA_I2C4_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + i2c_lld_serve_interrupt(&I2CD5); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* TIVA_I2C_USE_I2C4 */ + +#if TIVA_I2C_USE_I2C5 || defined(__DOXYGEN__) +/** + * @brief I2C5 interrupt handler. + * + * @notapi + */ +OSAL_IRQ_HANDLER(TIVA_I2C5_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + i2c_lld_serve_interrupt(&I2CD6); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* TIVA_I2C_USE_I2C5 */ + +#if TIVA_I2C_USE_I2C6 || defined(__DOXYGEN__) +/** + * @brief I2C6 interrupt handler. + * + * @notapi + */ +OSAL_IRQ_HANDLER(TIVA_I2C6_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + i2c_lld_serve_interrupt(&I2CD7); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* TIVA_I2C_USE_I2C6 */ + +#if TIVA_I2C_USE_I2C7 || defined(__DOXYGEN__) +/** + * @brief I2C7 interrupt handler. + * + * @notapi + */ +OSAL_IRQ_HANDLER(TIVA_I2C7_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + i2c_lld_serve_interrupt(&I2CD8); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* TIVA_I2C_USE_I2C7 */ + +#if TIVA_I2C_USE_I2C8 || defined(__DOXYGEN__) +/** + * @brief I2C8 interrupt handler. + * + * @notapi + */ +OSAL_IRQ_HANDLER(TIVA_I2C8_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + i2c_lld_serve_interrupt(&I2CD9); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* TIVA_I2C_USE_I2C8 */ + +#if TIVA_I2C_USE_I2C9 || defined(__DOXYGEN__) +/** + * @brief I2C9 interrupt handler. + * + * @notapi + */ +OSAL_IRQ_HANDLER(TIVA_I2C9_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + i2c_lld_serve_interrupt(&I2CD10); + + OSAL_IRQ_EPILOGUE(); +} +#endif /* TIVA_I2C_USE_I2C9 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level I2C driver initialization. + * + * @notapi + */ +void i2c_lld_init(void) { + +#if TIVA_I2C_USE_I2C0 + i2cObjectInit(&I2CD1); + I2CD1.thread = NULL; + I2CD1.i2c = I2C0; +#endif /* TIVA_I2C_USE_I2C0 */ + +#if TIVA_I2C_USE_I2C1 + i2cObjectInit(&I2CD2); + I2CD2.thread = NULL; + I2CD2.i2c = I2C1; +#endif /* TIVA_I2C_USE_I2C1 */ + +#if TIVA_I2C_USE_I2C2 + i2cObjectInit(&I2CD3); + I2CD3.thread = NULL; + I2CD3.i2c = I2C2; +#endif /* TIVA_I2C_USE_I2C2 */ + +#if TIVA_I2C_USE_I2C3 + i2cObjectInit(&I2CD4); + I2CD4.thread = NULL; + I2CD4.i2c = I2C3; +#endif /* TIVA_I2C_USE_I2C3 */ + +#if TIVA_I2C_USE_I2C4 + i2cObjectInit(&I2CD5); + I2CD5.thread = NULL; + I2CD5.i2c = I2C4; +#endif /* TIVA_I2C_USE_I2C4 */ + +#if TIVA_I2C_USE_I2C5 + i2cObjectInit(&I2CD6); + I2CD6.thread = NULL; + I2CD6.i2c = I2C5; +#endif /* TIVA_I2C_USE_I2C5 */ + +#if TIVA_I2C_USE_I2C6 + i2cObjectInit(&I2CD7); + I2CD7.thread = NULL; + I2CD7.i2c = I2C6; +#endif /* TIVA_I2C_USE_I2C6 */ + +#if TIVA_I2C_USE_I2C7 + i2cObjectInit(&I2CD8); + I2CD8.thread = NULL; + I2CD8.i2c = I2C7; +#endif /* TIVA_I2C_USE_I2C7 */ + +#if TIVA_I2C_USE_I2C8 + i2cObjectInit(&I2CD9); + I2CD9.thread = NULL; + I2CD9.i2c = I2C8; +#endif /* TIVA_I2C_USE_I2C8 */ + +#if TIVA_I2C_USE_I2C9 + i2cObjectInit(&I2CD10); + I2CD10.thread = NULL; + I2CD10.i2c = I2C9; +#endif /* TIVA_I2C_USE_I2C9 */ +} + +/** + * @brief Configures and activates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +void i2c_lld_start(I2CDriver *i2cp) +{ + I2C_TypeDef *dp = i2cp->i2c; + + /* If in stopped state then enables the I2C clocks.*/ + if (i2cp->state == I2C_STOP) { +#if TIVA_I2C_USE_I2C0 + if (&I2CD1 == i2cp) { + SYSCTL->RCGCI2C |= (1 << 0); + + while (!(SYSCTL->PRI2C & (1 << 0))) + ; + + nvicEnableVector(TIVA_I2C0_NUMBER, TIVA_I2C_I2C0_IRQ_PRIORITY); + } +#endif /* TIVA_I2C_USE_I2C0 */ + +#if TIVA_I2C_USE_I2C1 + if (&I2CD2 == i2cp) { + SYSCTL->RCGCI2C |= (1 << 1); + + while (!(SYSCTL->PRI2C & (1 << 1))) + ; + + nvicEnableVector(TIVA_I2C1_NUMBER, TIVA_I2C_I2C1_IRQ_PRIORITY); + } +#endif /* TIVA_I2C_USE_I2C1 */ + +#if TIVA_I2C_USE_I2C2 + if (&I2CD3 == i2cp) { + SYSCTL->RCGCI2C |= (1 << 2); + + while (!(SYSCTL->PRI2C & (1 << 2))) + ; + + nvicEnableVector(TIVA_I2C2_NUMBER, TIVA_I2C_I2C2_IRQ_PRIORITY); + } +#endif /* TIVA_I2C_USE_I2C2 */ + +#if TIVA_I2C_USE_I2C3 + if (&I2CD4 == i2cp) { + SYSCTL->RCGCI2C |= (1 << 3); + + while (!(SYSCTL->PRI2C & (1 << 3))) + ; + + nvicEnableVector(TIVA_I2C3_NUMBER, TIVA_I2C_I2C3_IRQ_PRIORITY); + } +#endif /* TIVA_I2C_USE_I2C3 */ + +#if TIVA_I2C_USE_I2C4 + if (&I2CD5 == i2cp) { + SYSCTL->RCGCI2C |= (1 << 4); + + while (!(SYSCTL->PRI2C & (1 << 4))) + ; + + nvicEnableVector(TIVA_I2C4_NUMBER, TIVA_I2C_I2C4_IRQ_PRIORITY); + } +#endif /* TIVA_I2C_USE_I2C4 */ + +#if TIVA_I2C_USE_I2C5 + if (&I2CD6 == i2cp) { + SYSCTL->RCGCI2C |= (1 << 5); + + while (!(SYSCTL->PRI2C & (1 << 5))) + ; + + nvicEnableVector(TIVA_I2C5_NUMBER, TIVA_I2C_I2C5_IRQ_PRIORITY); + } +#endif /* TIVA_I2C_USE_I2C5 */ + +#if TIVA_I2C_USE_I2C6 + if (&I2CD7 == i2cp) { + SYSCTL->RCGCI2C |= (1 << 6); + + while (!(SYSCTL->PRI2C & (1 << 6))) + ; + + nvicEnableVector(TIVA_I2C6_NUMBER, TIVA_I2C_I2C6_IRQ_PRIORITY); + } +#endif /* TIVA_I2C_USE_I2C6 */ + +#if TIVA_I2C_USE_I2C7 + if (&I2CD8 == i2cp) { + SYSCTL->RCGCI2C |= (1 << 7); + + while (!(SYSCTL->PRI2C & (1 << 7))) + ; + + nvicEnableVector(TIVA_I2C7_NUMBER, TIVA_I2C_I2C7_IRQ_PRIORITY); + } +#endif /* TIVA_I2C_USE_I2C7 */ + +#if TIVA_I2C_USE_I2C8 + if (&I2CD9 == i2cp) { + SYSCTL->RCGCI2C |= (1 << 8); + + while (!(SYSCTL->PRI2C & (1 << 8))) + ; + + nvicEnableVector(TIVA_I2C8_NUMBER, TIVA_I2C_I2C8_IRQ_PRIORITY); + } +#endif /* TIVA_I2C_USE_I2C7 */ + +#if TIVA_I2C_USE_I2C9 + if (&I2CD10 == i2cp) { + SYSCTL->RCGCI2C |= (1 << 9); + + while (!(SYSCTL->PRI2C & (1 << 9))) + ; + + nvicEnableVector(TIVA_I2C9_NUMBER, TIVA_I2C_I2C9_IRQ_PRIORITY); + } +#endif /* TIVA_I2C_USE_I2C7 */ + } + + dp->MCR = 0x10; + dp->MTPR = MTPR_VALUE; +} + +/** + * @brief Deactivates the I2C peripheral. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +void i2c_lld_stop(I2CDriver *i2cp) +{ + I2C_TypeDef *dp = i2cp->i2c; + /* If not in stopped state then disables the I2C clock.*/ + if (i2cp->state != I2C_STOP) { + + /* I2C disable.*/ + // TODO: abort i2c operation + //i2c_lld_abort_operation(i2cp); + +#if TIVA_I2C_USE_I2C0 + if (&I2CD1 == i2cp) { + SYSCTL->RCGCI2C &= ~(1 << 0); + nvicDisableVector(TIVA_I2C0_NUMBER); + } +#endif /* TIVA_I2C_USE_I2C0 */ + +#if TIVA_I2C_USE_I2C1 + if (&I2CD2 == i2cp) { + SYSCTL->RCGCI2C &= ~(1 << 1); + nvicDisableVector(TIVA_I2C1_NUMBER); + } +#endif /* TIVA_I2C_USE_I2C1 */ + +#if TIVA_I2C_USE_I2C2 + if (&I2CD3 == i2cp) { + SYSCTL->RCGCI2C &= ~(1 << 2); + nvicDisableVector(TIVA_I2C2_NUMBER); + } +#endif /* TIVA_I2C_USE_I2C2 */ + +#if TIVA_I2C_USE_I2C3 + if (&I2CD4 == i2cp) { + SYSCTL->RCGCI2C &= ~(1 << 3); + nvicDisableVector(TIVA_I2C3_NUMBER); + } +#endif /* TIVA_I2C_USE_I2C3 */ + +#if TIVA_I2C_USE_I2C4 + if (&I2CD5 == i2cp) { + SYSCTL->RCGCI2C &= ~(1 << 4); + nvicDisableVector(TIVA_I2C4_NUMBER); + } +#endif /* TIVA_I2C_USE_I2C4 */ + +#if TIVA_I2C_USE_I2C5 + if (&I2CD6 == i2cp) { + SYSCTL->RCGCI2C &= ~(1 << 5); + nvicDisableVector(TIVA_I2C5_NUMBER); + } +#endif /* TIVA_I2C_USE_I2C5 */ + +#if TIVA_I2C_USE_I2C6 + if (&I2CD7 == i2cp) { + SYSCTL->RCGCI2C &= ~(1 << 6); + nvicDisableVector(TIVA_I2C6_NUMBER); + } +#endif /* TIVA_I2C_USE_I2C6 */ + +#if TIVA_I2C_USE_I2C7 + if (&I2CD8 == i2cp) { + SYSCTL->RCGCI2C &= ~(1 << 7); + nvicDisableVector(TIVA_I2C7_NUMBER); + } +#endif /* TIVA_I2C_USE_I2C7 */ + +#if TIVA_I2C_USE_I2C8 + if (&I2CD9 == i2cp) { + SYSCTL->RCGCI2C &= ~(1 << 8); + nvicDisableVector(TIVA_I2C8_NUMBER); + } +#endif /* TIVA_I2C_USE_I2C8 */ + +#if TIVA_I2C_USE_I2C9 + if (&I2CD10 == i2cp) { + SYSCTL->RCGCI2C &= ~(1 << 9); + nvicDisableVector(TIVA_I2C9_NUMBER); + } +#endif /* TIVA_I2C_USE_I2C9 */ + + dp->MCR = 0; + dp->MTPR = 0; + } +} + +/** + * @brief Receives data via the I2C bus as master. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] addr slave device address + * @param[out] rxbuf pointer to the receive buffer + * @param[in] rxbytes number of bytes to be received + * @param[in] timeout the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK if the function succeeded. + * @retval RDY_RESET if one or more I2C errors occurred, the errors can + * be retrieved using @p i2cGetErrors(). + * @retval RDY_TIMEOUT if a timeout occurred before operation end. After a + * timeout the driver must be stopped and restarted + * because the bus is in an uncertain state. + * + * @notapi + */ +msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout) +{ + I2C_TypeDef *dp = i2cp->i2c; + systime_t start, end; + + i2cp->rxbuf = rxbuf; + i2cp->rxbytes = rxbytes; + + /* Resetting error flags for this transfer.*/ + i2cp->errors = I2C_NO_ERROR; + + /* Initializes driver fields, LSB = 1 -> receive.*/ + i2cp->addr = (addr << 1) | 0x01; + + /* Releases the lock from high level driver.*/ + osalSysUnlock(); + + /* Calculating the time window for the timeout on the busy bus condition.*/ + start = osalOsGetSystemTimeX(); + end = start + OSAL_MS2ST(TIVA_I2C_BUSY_TIMEOUT); + + /* Waits until BUSY flag is reset or, alternatively, for a timeout + condition.*/ + while (true) { + osalSysLock(); + + /* If the bus is not busy then the operation can continue, note, the + loop is exited in the locked state.*/ + if ((dp->MCS & TIVA_MCS_BUSY) == 0) + break; + + /* If the system time went outside the allowed window then a timeout + condition is returned.*/ + if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), start, end)) + return MSG_TIMEOUT; + + osalSysUnlock(); + } + + /* set slave address */ + dp->MSA = addr; + + /* Starts the operation.*/ + dp->MCS = TIVA_I2C_SINGLE_RECEIVE; + + /* Waits for the operation completion or a timeout.*/ + return osalThreadSuspendTimeoutS(&i2cp->thread, timeout); +} + +/** + * @brief Transmits data via the I2C bus as master. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * @param[in] addr slave device address + * @param[in] txbuf pointer to the transmit buffer + * @param[in] txbytes number of bytes to be transmitted + * @param[out] rxbuf pointer to the receive buffer + * @param[in] rxbytes number of bytes to be received + * @param[in] timeout the number of ticks before the operation timeouts, + * the following special values are allowed: + * - @a TIME_INFINITE no timeout. + * . + * @return The operation status. + * @retval RDY_OK if the function succeeded. + * @retval RDY_RESET if one or more I2C errors occurred, the errors can + * be retrieved using @p i2cGetErrors(). + * @retval RDY_TIMEOUT if a timeout occurred before operation end. After a + * timeout the driver must be stopped and restarted + * because the bus is in an uncertain state. + * + * @notapi + */ +msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, + const uint8_t *txbuf, size_t txbytes, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout) +{ + I2C_TypeDef *dp = i2cp->i2c; + systime_t start, end; + + i2cp->rxbuf = rxbuf; + i2cp->rxbytes = rxbytes; + i2cp->txbuf = txbuf; + i2cp->txbytes = txbytes; + + /* Resetting error flags for this transfer.*/ + i2cp->errors = I2C_NO_ERROR; + + /* Releases the lock from high level driver.*/ + osalSysUnlock(); + + /* Calculating the time window for the timeout on the busy bus condition.*/ + start = osalOsGetSystemTimeX(); + end = start + OSAL_MS2ST(TIVA_I2C_BUSY_TIMEOUT); + + /* Waits until BUSY flag is reset or, alternatively, for a timeout + condition.*/ + while (true) { + osalSysLock(); + + /* If the bus is not busy then the operation can continue, note, the + loop is exited in the locked state.*/ + if ((dp->MCS & TIVA_MCS_BUSY) == 0) + break; + + /* If the system time went outside the allowed window then a timeout + condition is returned.*/ + if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), start, end)) + return MSG_TIMEOUT; + + osalSysUnlock(); + } + + /* Initializes driver fields, LSB = 0 -> write.*/ + i2cp->addr = addr << 1 | 0; + + /* set slave address */ + dp->MSA = i2cp->addr; + + /* enable interrupts */ + dp->MIMR = TIVA_MIMR_IM; + + /* put data in register */ + dp->MDR = *(i2cp->txbuf); + + /* check if 1 or more bytes */ + if (i2cp->txbytes == 1) { + if (i2cp->rxbytes == 1) { + // one byte read + i2cp->intstate = STATE_READ_ONE; + } + else { + // multiple byte read + i2cp->intstate = STATE_READ_FIRST; + } + // single byte send + dp->MCS = TIVA_I2C_SIGNLE_SEND; + } + else { + if (i2cp->txbytes == 2) { + // 2 bytes + i2cp->intstate = STATE_WRITE_FINAL; + } + else { + // more then 2 bytes + i2cp->intstate = STATE_WRITE_NEXT; + } + // multiple bytes start send + dp->MCS = TIVA_I2C_BURST_SEND_START; + } + + i2cp->txbuf++; + i2cp->txbytes--; + + /* Waits for the operation completion or a timeout.*/ + return osalThreadSuspendTimeoutS(&i2cp->thread, timeout); +} + +#endif /* HAL_USE_I2C */ + +/** @} */ diff --git a/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.h b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.h new file mode 100644 index 0000000..460d231 --- /dev/null +++ b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.h @@ -0,0 +1,527 @@ +/* + Copyright (C) 2014..2016 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file TIVA/LLD/i2c_lld.h + * @brief TM4C123x/TM4C129x I2C subsystem low level driver header. + * + * @addtogroup I2C + * @{ + */ + +#ifndef HAL_I2C_LLD_H +#define HAL_I2C_LLD_H + +#if HAL_USE_I2C || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define MTPR_VALUE ((TIVA_SYSCLK/(2*(6+4)*i2cp->config->clock_speed))-1) + +#define TIVA_MSA_RS (1 << 0) +#define TIVA_MSA_SA (127 << 1) + +#define TIVA_MCS_BUSY (1 << 0) +#define TIVA_MCS_ERROR (1 << 1) +#define TIVA_MCS_ADRACK (1 << 2) +#define TIVA_MCS_DATACK (1 << 3) +#define TIVA_MCS_ARBLST (1 << 4) +#define TIVA_MCS_IDLE (1 << 5) +#define TIVA_MCS_BUSBSY (1 << 6) +#define TIVA_MCS_CLKTO (1 << 7) + +#define TIVA_MCS_RUN (1 << 0) +#define TIVA_MCS_START (1 << 1) +#define TIVA_MCS_STOP (1 << 2) +#define TIVA_MCS_ACK (1 << 3) +#define TIVA_MCS_HS (1 << 4) + +#define TIVA_I2C_SIGNLE_SEND (TIVA_MCS_RUN | TIVA_MCS_START | TIVA_MCS_STOP) +#define TIVA_I2C_BURST_SEND_START (TIVA_MCS_RUN | TIVA_MCS_START) +#define TIVA_I2C_BURST_SEND_CONTINUE (TIVA_MCS_RUN) +#define TIVA_I2C_BURST_SEND_FINISH (TIVA_MCS_RUN | TIVA_MCS_STOP) +#define TIVA_I2C_BURST_SEND_STOP (TIVA_MCS_STOP) +#define TIVA_I2C_BURST_SEND_ERROR_STOP (TIVA_MCS_STOP) + +#define TIVA_I2C_SINGLE_RECEIVE (TIVA_MCS_RUN | TIVA_MCS_START | TIVA_MCS_STOP) +#define TIVA_I2C_BURST_RECEIVE_START (TIVA_MCS_RUN | TIVA_MCS_START | TIVA_MCS_ACK) +#define TIVA_I2C_BURST_RECEIVE_CONTINUE (TIVA_MCS_RUN | TIVA_MCS_ACK) +#define TIVA_I2C_BURST_RECEIVE_FINISH (TIVA_MCS_RUN | TIVA_MCS_STOP) +#define TIVA_I2C_BURST_RECEIVE_ERROR_STOP (TIVA_MCS_STOP) + +#define TIVA_MDR_DATA (255 << 0) + +#define TIVA_MTPR_TPR (127 << 0) +#define TIVA_MTPR_HS (1 << 7) + +#define TIVA_MIMR_IM (1 << 0) +#define TIVA_MIMR_CLKIM (1 << 1) + +#define TIVA_MRIS_RIS (1 << 0) +#define TIVA_MRIS_CLKRIS (1 << 1) + +#define TIVA_MMIS_MIS (1 << 0) +#define TIVA_MMIS_CLKMIS (1 << 1) + +#define TIVA_MICR_IC (1 << 0) +#define TIVA_MICR_CLKIC (1 << 1) + +#define TIVA_MCR_LPBK (1 << 0) +#define TIVA_MCR_MFE (1 << 4) +#define TIVA_MCR_SFE (1 << 5) +#define TIVA_MCR_GFE (1 << 6) + +#define TIVA_MCLKOCNT_CNTL (255 << 0) + +#define TIVA_MBMON_SCL (1 << 0) +#define TIVA_MBMON_SDA (1 << 1) + +#define TIVA_MCR2_GFPW (7 << 4) + +// interrupt states +#define STATE_IDLE 0 +#define STATE_WRITE_NEXT 1 +#define STATE_WRITE_FINAL 2 +#define STATE_WAIT_ACK 3 +#define STATE_SEND_ACK 4 +#define STATE_READ_ONE 5 +#define STATE_READ_FIRST 6 +#define STATE_READ_NEXT 7 +#define STATE_READ_FINAL 8 +#define STATE_READ_WAIT 9 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ + +/** + * @brief I2C0 driver enable switch. + * @details If set to @p TRUE the support for I2C0 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_I2C_USE_I2C0) || defined(__DOXYGEN__) +#define TIVA_I2C_USE_I2C0 FALSE +#endif + +/** + * @brief I2C1 driver enable switch. + * @details If set to @p TRUE the support for I2C1 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_I2C_USE_I2C1) || defined(__DOXYGEN__) +#define TIVA_I2C_USE_I2C1 FALSE +#endif + +/** + * @brief I2C2 driver enable switch. + * @details If set to @p TRUE the support for I2C2 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_I2C_USE_I2C2) || defined(__DOXYGEN__) +#define TIVA_I2C_USE_I2C2 FALSE +#endif + +/** + * @brief I2C3 driver enable switch. + * @details If set to @p TRUE the support for I2C3 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_I2C_USE_I2C3) || defined(__DOXYGEN__) +#define TIVA_I2C_USE_I2C3 FALSE +#endif + +/** + * @brief I2C4 driver enable switch. + * @details If set to @p TRUE the support for I2C4 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_I2C_USE_I2C4) || defined(__DOXYGEN__) +#define TIVA_I2C_USE_I2C4 FALSE +#endif + +/** + * @brief I2C5 driver enable switch. + * @details If set to @p TRUE the support for I2C5 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_I2C_USE_I2C5) || defined(__DOXYGEN__) +#define TIVA_I2C_USE_I2C5 FALSE +#endif + +/** + * @brief I2C6 driver enable switch. + * @details If set to @p TRUE the support for I2C6 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_I2C_USE_I2C6) || defined(__DOXYGEN__) +#define TIVA_I2C_USE_I2C6 FALSE +#endif + +/** + * @brief I2C7 driver enable switch. + * @details If set to @p TRUE the support for I2C7 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_I2C_USE_I2C7) || defined(__DOXYGEN__) +#define TIVA_I2C_USE_I2C7 FALSE +#endif + +/** + * @brief I2C8 driver enable switch. + * @details If set to @p TRUE the support for I2C8 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_I2C_USE_I2C8) || defined(__DOXYGEN__) +#define TIVA_I2C_USE_I2C8 FALSE +#endif + +/** + * @brief I2C9 driver enable switch. + * @details If set to @p TRUE the support for I2C9 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_I2C_USE_I2C9) || defined(__DOXYGEN__) +#define TIVA_I2C_USE_I2C9 FALSE +#endif + +/** + * @brief I2C timeout on busy condition in milliseconds. + */ +#if !defined(TIVA_I2C_BUSY_TIMEOUT) || defined(__DOXYGEN__) +#define TIVA_I2C_BUSY_TIMEOUT 50 +#endif + +/** + * @brief I2C0 interrupt priority level setting. + */ +#if !defined(TIVA_I2C_I2C0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_I2C_I2C0_IRQ_PRIORITY 4 +#endif + +/** + * @brief I2C1 interrupt priority level setting. + */ +#if !defined(TIVA_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_I2C_I2C1_IRQ_PRIORITY 4 +#endif + +/** + * @brief I2C2 interrupt priority level setting. + */ +#if !defined(TIVA_I2C_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_I2C_I2C2_IRQ_PRIORITY 4 +#endif + +/** + * @brief I2C3 interrupt priority level setting. + */ +#if !defined(TIVA_I2C_I2C3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_I2C_I2C3_IRQ_PRIORITY 4 +#endif + +/** + * @brief I2C4 interrupt priority level setting. + */ +#if !defined(TIVA_I2C_I2C4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_I2C_I2C4_IRQ_PRIORITY 4 +#endif + +/** + * @brief I2C5 interrupt priority level setting. + */ +#if !defined(TIVA_I2C_I2C5_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_I2C_I2C5_IRQ_PRIORITY 4 +#endif + +/** + * @brief I2C6 interrupt priority level setting. + */ +#if !defined(TIVA_I2C_I2C6_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_I2C_I2C6_IRQ_PRIORITY 4 +#endif + +/** + * @brief I2C7 interrupt priority level setting. + */ +#if !defined(TIVA_I2C_I2C7_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_I2C_I2C7_IRQ_PRIORITY 4 +#endif + +/** + * @brief I2C8 interrupt priority level setting. + */ +#if !defined(TIVA_I2C_I2C8_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_I2C_I2C8_IRQ_PRIORITY 4 +#endif + +/** + * @brief I2C9 interrupt priority level setting. + */ +#if !defined(TIVA_I2C_I2C9_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_I2C_I2C9_IRQ_PRIORITY 4 +#endif + +/** + * @} + */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/** + * @brief error checks + */ +#if !TIVA_I2C_USE_I2C0 && !TIVA_I2C_USE_I2C1 && !TIVA_I2C_USE_I2C2 && \ + !TIVA_I2C_USE_I2C3 && !TIVA_I2C_USE_I2C4 && !TIVA_I2C_USE_I2C5 && \ + !TIVA_I2C_USE_I2C6 && !TIVA_I2C_USE_I2C7 && !TIVA_I2C_USE_I2C8 && \ + !TIVA_I2C_USE_I2C9 +#error "I2C driver activated but no I2C peripheral assigned" +#endif + +#if TIVA_I2C_USE_I2C0 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C0_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to I2C0" +#endif + +#if TIVA_I2C_USE_I2C1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to I2C1" +#endif + +#if TIVA_I2C_USE_I2C2 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to I2C2" +#endif + +#if TIVA_I2C_USE_I2C3 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to I2C3" +#endif + +#if TIVA_I2C_USE_I2C4 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C4_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to I2C4" +#endif + +#if TIVA_I2C_USE_I2C5 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C5_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to I2C5" +#endif + +#if TIVA_I2C_USE_I2C6 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C6_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to I2C6" +#endif + +#if TIVA_I2C_USE_I2C7 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C7_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to I2C7" +#endif + +#if TIVA_I2C_USE_I2C8 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C8_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to I2C8" +#endif + +#if TIVA_I2C_USE_I2C9 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C9_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to I2C9" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type representing I2C address. + */ +typedef uint16_t i2caddr_t; + +/** + * @brief I2C Driver condition flags type. + */ +typedef uint32_t i2cflags_t; + +/** + * @brief Driver configuration structure. + */ +typedef struct +{ + /** + * @brief Specifies the clock frequency. + * @note Must be set to a value lower than 3.33Mbps. + * TODO: high-speed mode: 3333 kHz. setup is 100-400-1000 kHz then switched to 3333 kHz + */ + uint32_t clock_speed; +} I2CConfig; + +/** + * @brief Type of a structure representing an I2C driver. + */ +typedef struct I2CDriver I2CDriver; + +/** + * @brief Structure representing an I2C driver. + */ +struct I2CDriver { + /** + * @brief Driver state. + */ + i2cstate_t state; + /** + * @brief Current configuration data. + */ + const I2CConfig *config; + /** + * @brief Error flags. + */ + i2cflags_t errors; +#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + mutex_t mutex; +#endif /* I2C_USE_MUTUAL_EXCLUSION */ +#if defined(I2C_DRIVER_EXT_FIELDS) + I2C_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Thread waiting for I/O completion. + */ + thread_reference_t thread; + /** + * @brief Current slave address without R/W bit. + */ + i2caddr_t addr; + /** + * @brief Pointer to the buffer with data to send. + */ + const uint8_t *txbuf; + /** + * @brief Number of bytes of data to send. + */ + size_t txbytes; + /** + * @brief Pointer to the buffer to put received data. + */ + uint8_t *rxbuf; + /** + * @brief Number of bytes of data to receive. + */ + size_t rxbytes; + /** + * @brief State of the interrupt state machine. + * + * TODO is it possible to remove the interrupt state? + */ + uint8_t intstate; + /** + * @brief Pointer to the I2Cx registers block. + */ + I2C_TypeDef *i2c; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Get errors from I2C driver. + * + * @param[in] i2cp pointer to the @p I2CDriver object + * + * @notapi + */ +#define i2c_lld_get_errors(i2cp) ((i2cp)->errors) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if !defined(__DOXYGEN__) +#if TIVA_I2C_USE_I2C0 +extern I2CDriver I2CD1; +#endif + +#if TIVA_I2C_USE_I2C1 +extern I2CDriver I2CD2; +#endif + +#if TIVA_I2C_USE_I2C2 +extern I2CDriver I2CD3; +#endif + +#if TIVA_I2C_USE_I2C3 +extern I2CDriver I2CD4; +#endif + +#if TIVA_I2C_USE_I2C4 +extern I2CDriver I2CD5; +#endif + +#if TIVA_I2C_USE_I2C5 +extern I2CDriver I2CD6; +#endif + +#if TIVA_I2C_USE_I2C6 +extern I2CDriver I2CD7; +#endif + +#if TIVA_I2C_USE_I2C7 +extern I2CDriver I2CD8; +#endif + +#if TIVA_I2C_USE_I2C8 +extern I2CDriver I2CD9; +#endif + +#if TIVA_I2C_USE_I2C9 +extern I2CDriver I2CD10; +#endif + +#endif /* !defined(__DOXYGEN__) */ + +#ifdef __cplusplus +extern "C" { +#endif + void i2c_lld_init(void); + void i2c_lld_start(I2CDriver *i2cp); + void i2c_lld_stop(I2CDriver *i2cp); + msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, + const uint8_t *txbuf, size_t txbytes, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout); + msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, + uint8_t *rxbuf, size_t rxbytes, + systime_t timeout); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_I2C */ + +#endif /* HAL_I2C_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.c b/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.c new file mode 100644 index 0000000..04177b6 --- /dev/null +++ b/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.c @@ -0,0 +1,823 @@ +/* + Copyright (C) 2014..2016 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file TIVA/mac_lld.c + * @brief MAC Driver subsystem low level driver source. + * + * @addtogroup MAC + * @{ + */ + +#include + +#include "hal.h" + +#if HAL_USE_MAC || defined(__DOXYGEN__) + +#include "hal_mii.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define BUFFER_SIZE ((((TIVA_MAC_BUFFERS_SIZE - 1) | 3) + 1) / 4) + +/* MII divider optimal value.*/ +#if (TIVA_SYSCLK >= 100000000) +#define MACMIIADDR_CR (0x01 << 2) +#elif (TIVA_SYSCLK >= 60000000) +#define MACMIIADDR_CR (0x00 << 2) +#elif (TIVA_SYSCLK >= 35000000) +#define MACMIIADDR_CR (0x03 << 2) +#elif (TIVA_SYSCLK >= 20000000) +#define MACMIIADDR_CR (0x02 << 2) +#else +#error "TIVA_SYSCLK below minimum frequency for ETH operations (20MHz)" +#endif + +#define EMAC_MIIADDR_MIIW 0x00000002 /* MII Write */ +#define EMAC_MIIADDR_MIIB 0x00000001 /* MII Busy */ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief Ethernet driver 1. + */ +MACDriver ETHD1; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +static const uint8_t default_mac_address[] = {0xAA, 0x55, 0x13, + 0x37, 0x01, 0x10}; + +static tiva_eth_rx_descriptor_t rd[TIVA_MAC_RECEIVE_BUFFERS]; +static tiva_eth_tx_descriptor_t td[TIVA_MAC_TRANSMIT_BUFFERS]; + +static uint32_t rb[TIVA_MAC_RECEIVE_BUFFERS][BUFFER_SIZE]; +static uint32_t tb[TIVA_MAC_TRANSMIT_BUFFERS][BUFFER_SIZE]; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Writes a PHY register. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[in] reg register number + * @param[in] value new register value + * + * @notapi + */ +static void mii_write(MACDriver *macp, uint32_t reg, uint32_t value) +{ + ETH->MIIDATA = value; + ETH->MIIADDR = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIW | EMAC_MIIADDR_MIIB; + + while ((ETH->MIIADDR & EMAC_MIIADDR_MIIB) != 0) + ; +} + +/** + * @brief Writes an extended PHY register. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[in] reg register number + * @param[in] value new register value + * + * @notapi + */ +static void mii_write_extended(MACDriver *macp, uint32_t reg, uint32_t value) +{ + mii_write(macp, TIVA_REGCTL, 0x001F); + mii_write(macp, TIVA_ADDAR, reg); + + mii_write(macp, TIVA_REGCTL, 0x401F); + mii_write(macp, TIVA_ADDAR, value); +} + +/** + * @brief Reads a PHY register. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[in] reg register number + * + * @return The PHY register content. + * + * @notapi + */ +static uint32_t mii_read(MACDriver *macp, uint32_t reg) +{ + ETH->MIIADDR = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIB; + + while ((ETH->MIIADDR & EMAC_MIIADDR_MIIB) != 0) + ; + + return ETH->MIIDATA; +} + +/** + * @brief Reads an extended PHY register. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[in] reg register number + * + * @return The extended PHY register content. + * + * @notapi + */ +static uint32_t mii_read_extended(MACDriver *macp, uint32_t reg) +{ + mii_write(macp, TIVA_REGCTL, 0x001F); + mii_write(macp, TIVA_ADDAR, reg); + + mii_write(macp, TIVA_REGCTL, 0x401F); + return mii_read(macp, TIVA_ADDAR); +} + +#if !defined(BOARD_PHY_ADDRESS) +/** + * @brief PHY address detection. + * + * @param[in] macp pointer to the @p MACDriver object + */ +static void mii_find_phy(MACDriver *macp) +{ + uint32_t i; + +#if TIVA_MAC_PHY_TIMEOUT > 0 + rtcnt_t start = chSysGetRealtimeCounterX(); + rtcnt_t timeout = start + MS2RTC(STM32_HCLK,STM32_MAC_PHY_TIMEOUT); + rtcnt_t time = start; + while (chSysIsCounterWithinX(time, start, timeout)) { +#endif + for (i = 0; i < 31; i++) { + macp->phyaddr = i << 11; + ETH->MIIDATA = (i << 6) | MACMIIADDR_CR; + if ((mii_read(macp, TIVA_ID1) == (BOARD_PHY_ID >> 16)) && + ((mii_read(macp, TIVA_ID2) & 0xFFF0) == (BOARD_PHY_ID & 0xFFF0))) { + return; + } + } +#if TIVA_MAC_PHY_TIMEOUT > 0 + time = chSysGetRealtimeCounterX(); + } +#endif + /* Wrong or defective board.*/ + osalSysHalt("MAC failure"); +} +#endif + +/** + * @brief MAC address setup. + * + * @param[in] p pointer to a six bytes buffer containing the MAC + * address + */ +static void mac_lld_set_address(const uint8_t *p) +{ + /* MAC address configuration, only a single address comparator is used, + hash table not used.*/ + ETH->ADDR0H = ((uint32_t)p[5] << 8) | + ((uint32_t)p[4] << 0); + ETH->ADDR0L = ((uint32_t)p[3] << 24) | + ((uint32_t)p[2] << 16) | + ((uint32_t)p[1] << 8) | + ((uint32_t)p[0] << 0); + ETH->ADDR1H = 0x0000FFFF; + ETH->ADDR1L = 0xFFFFFFFF; + ETH->ADDR2H = 0x0000FFFF; + ETH->ADDR2L = 0xFFFFFFFF; + ETH->ADDR3H = 0x0000FFFF; + ETH->ADDR3L = 0xFFFFFFFF; + ETH->HASHTBLH = 0; + ETH->HASHTBLL = 0; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +CH_IRQ_HANDLER(TIVA_MAC_HANDLER) +{ + uint32_t dmaris; + + CH_IRQ_PROLOGUE(); + + dmaris = ETH->DMARIS; + ETH->DMARIS = dmaris & 0x0001FFFF; /* Clear status bits.*/ + + if (dmaris & (1 << 6)) { + /* Data Received.*/ + osalSysLockFromISR(); + osalThreadDequeueAllI(ÐD1.rdqueue, MSG_RESET); +#if MAC_USE_EVENTS + osalEventBroadcastFlagsI(ÐD1.rdevent, 0); +#endif + osalSysUnlockFromISR(); + } + + if (dmaris & (1 << 0)) { + /* Data Transmitted.*/ + osalSysLockFromISR(); + osalThreadDequeueAllI(ÐD1.tdqueue, MSG_RESET); + osalSysUnlockFromISR(); + } + + CH_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level MAC initialization. + * + * @notapi + */ +void mac_lld_init(void) +{ + uint8_t i; + + macObjectInit(ÐD1); + ETHD1.link_up = false; + + /* Descriptor tables are initialized in chained mode, note that the first + word is not initialized here but in mac_lld_start().*/ + for (i = 0; i < TIVA_MAC_RECEIVE_BUFFERS; i++) { + rd[i].rdes1 = TIVA_RDES1_RCH | TIVA_RDES1_RBS1(TIVA_MAC_BUFFERS_SIZE); + rd[i].rdes2 = (uint32_t)rb[i]; + rd[i].rdes3 = (uint32_t)&rd[(i + 1) % TIVA_MAC_RECEIVE_BUFFERS]; + } + for (i = 0; i < TIVA_MAC_TRANSMIT_BUFFERS; i++) { + td[i].tdes1 = 0; + td[i].tdes2 = (uint32_t)tb[i]; + td[i].tdes3 = (uint32_t)&td[(i + 1) % TIVA_MAC_TRANSMIT_BUFFERS]; + } + + /* Enable MAC clock */ + SYSCTL->RCGCEMAC = 1; + while (SYSCTL->PREMAC != 0x01) + ; + + /* Set PHYHOLD bit */ + ETH->PC |= 1; + + /* Enable PHY clock */ + SYSCTL->RCGCEPHY = 1; + while (SYSCTL->PREPHY != 0x01) + ; + + /* Enable power to PHY */ + SYSCTL->PCEPHY |= 1; + while (SYSCTL->PREPHY != 0x01) + ; +#if BOARD_PHY_RMII + ETH->PC = EMAC_PHY_CONFIG | (0x04 << 28); +#else + ETH->PC = EMAC_PHY_CONFIG; +#endif + + /* + * Write OHY led configuration. + * 0: link ok + * 1: tx activity + * 2: link ok + * blink rate: 20Hz + */ + mii_write_extended(ÐD1, TIVA_LEDCFG, (0 << 8) | (2 << 4) | (0 << 0)); + mii_write(ÐD1, TIVA_LEDCR, (0 << 9)); + + /* Set done bit after writing EMACPC register */ + mii_write(ÐD1, TIVA_CFG1, (1 << 15) | mii_read(ÐD1, TIVA_CFG1)); + + while(ETH->DMABUSMOD & 1) + ; + + /* Reset MAC */ + ETH->DMABUSMOD |= 1; + while (ETH->DMABUSMOD & 1) + ; + + /* PHY address setup.*/ +#if defined(BOARD_PHY_ADDRESS) + ETHD1.phyaddr = BOARD_PHY_ADDRESS << 11; +#else + mii_find_phy(ÐD1); +#endif + +#if defined(BOARD_PHY_RESET) + /* PHY board-specific reset procedure.*/ + BOARD_PHY_RESET(); +#else + /* PHY soft reset procedure.*/ + mii_write(ÐD1, MII_BMCR, BMCR_RESET); +#if defined(BOARD_PHY_RESET_DELAY) + chSysPolledDelayX(BOARD_PHY_RESET_DELAY); +#endif + while (mii_read(ÐD1, MII_BMCR) & BMCR_RESET) + ; +#endif + +#if TIVA_MAC_CHANGE_PHY_STATE + /* PHY in power down mode until the driver will be started.*/ + mii_write(ÐD1, MII_BMCR, mii_read(ÐD1, MII_BMCR) | BMCR_PDOWN); +#endif + + /* Disable MAC clock */ + SYSCTL->RCGCEMAC = 0; + + /* Disable PHY clock */ + SYSCTL->RCGCEPHY = 0; +} + +/** + * @brief Configures and activates the MAC peripheral. + * + * @param[in] macp pointer to the @p MACDriver object + * + * @notapi + */ +void mac_lld_start(MACDriver *macp) +{ + uint8_t i; + + /* Resets the state of all descriptors.*/ + for (i = 0; i < TIVA_MAC_RECEIVE_BUFFERS; i++) { + rd[i].rdes0 = TIVA_RDES0_OWN; + } + macp->rxptr = (tiva_eth_rx_descriptor_t *)rd; + + for (i = 0; i < TIVA_MAC_TRANSMIT_BUFFERS; i++) { + td[i].tdes0 = TIVA_TDES0_TCH; + td[i].locked = 0; + } + macp->txptr = (tiva_eth_tx_descriptor_t *)td; + + /* Enable MAC clock */ + SYSCTL->RCGCEMAC = 1; + while (SYSCTL->PREMAC != 0x01) + ; + + /* Enable PHY clock */ + SYSCTL->RCGCEPHY = 1; + while (!SYSCTL->PREPHY) + ; + + /* ISR vector enabled.*/ + nvicEnableVector(TIVA_MAC_NUMBER, TIVA_MAC_IRQ_PRIORITY); + +#if TIVA_MAC_CHANGE_PHY_STATE + /* PHY in power up mode.*/ + mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) & ~BMCR_PDOWN); +#endif + + /* MAC configuration.*/ + ETH->FRAMEFLTR = 0; + ETH->FLOWCTL = 0; + ETH->VLANTG = 0; + + /* MAC address setup.*/ + if (macp->config->mac_address == NULL) + mac_lld_set_address(default_mac_address); + else + mac_lld_set_address(macp->config->mac_address); + + /* Transmitter and receiver enabled. + Note that the complete setup of the MAC is performed when the link + status is detected.*/ +#if TIVA_MAC_IP_CHECKSUM_OFFLOAD + ETH->CFG = (1 << 10) | (1 << 3) | (1 << 2); +#else + ETH->CFG = (1 << 3) | (1 << 2); +#endif + + /* DMA configuration: + Descriptor chains pointers.*/ + ETH->RXDLADDR = (uint32_t)rd; + ETH->TXDLADDR = (uint32_t)td; + + /* Enabling required interrupt sources.*/ + ETH->DMARIS &= 0xFFFF; + ETH->DMAIM = (1 << 16) | (1 << 6) | (1 << 0); + + /* DMA general settings.*/ + ETH->DMABUSMOD = (1 << 25) | (1 << 17) | (1 << 8); + + /* Transmit FIFO flush.*/ + ETH->DMAOPMODE = (1 << 20); + while (ETH->DMAOPMODE & (1 << 20)) + ; + + /* DMA final configuration and start.*/ + ETH->DMAOPMODE = (1 << 26) | (1 << 25) | (1 << 21) | + (1 << 13) | (1 << 1); +} + +/** + * @brief Deactivates the MAC peripheral. + * + * @param[in] macp pointer to the @p MACDriver object + * + * @notapi + */ +void mac_lld_stop(MACDriver *macp) +{ + if (macp->state != MAC_STOP) { +#if TIVA_MAC_CHANGE_PHY_STATE + /* PHY in power down mode until the driver will be restarted.*/ + mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) | BMCR_PDOWN); +#endif + + /* MAC and DMA stopped.*/ + ETH->CFG = 0; + ETH->DMAOPMODE = 0; + ETH->DMAIM = 0; + ETH->DMARIS &= 0xFFFF; + + /* MAC clocks stopped.*/ + SYSCTL->RCGCEMAC = 0; + + /* PHY clock stopped.*/ + SYSCTL->RCGCEPHY = 0; + + /* ISR vector disabled.*/ + nvicDisableVector(TIVA_MAC_NUMBER); + } +} + +/** + * @brief Returns a transmission descriptor. + * @details One of the available transmission descriptors is locked and + * returned. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[out] tdp pointer to a @p MACTransmitDescriptor structure + * @return The operation status. + * @retval RDY_OK the descriptor has been obtained. + * @retval RDY_TIMEOUT descriptor not available. + * + * @notapi + */ +msg_t mac_lld_get_transmit_descriptor(MACDriver *macp, + MACTransmitDescriptor *tdp) +{ + tiva_eth_tx_descriptor_t *tdes; + + if (!macp->link_up) + return MSG_TIMEOUT; + + osalSysLock(); + + /* Get Current TX descriptor.*/ + tdes = macp->txptr; + + /* Ensure that descriptor isn't owned by the Ethernet DMA or locked by + another thread.*/ + if (tdes->tdes0 & (TIVA_TDES0_OWN) || (tdes->locked)) { + osalSysUnlock(); + return MSG_TIMEOUT; + } + + /* Marks the current descriptor as locked.*/ + tdes->locked = 1; + + /* Next TX descriptor to use.*/ + macp->txptr = (tiva_eth_tx_descriptor_t *)tdes->tdes3; + + osalSysUnlock(); + + /* Set the buffer size and configuration.*/ + tdp->offset = 0; + tdp->size = TIVA_MAC_BUFFERS_SIZE; + tdp->physdesc = tdes; + + return MSG_OK; +} + +/** + * @brief Releases a transmit descriptor and starts the transmission of the + * enqueued data as a single frame. + * + * @param[in] tdp the pointer to the @p MACTransmitDescriptor structure + * + * @notapi + */ +void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) +{ + osalDbgAssert(!(tdp->physdesc->tdes0 & TIVA_TDES0_OWN), + "attempt to release descriptor already owned by DMA"); + + osalSysLock(); + + /* Unlocks the descriptor and returns it to the DMA engine.*/ + tdp->physdesc->tdes1 = tdp->offset; + tdp->physdesc->tdes0 = TIVA_TDES0_CIC(TIVA_MAC_IP_CHECKSUM_OFFLOAD) | + TIVA_TDES0_IC | TIVA_TDES0_LS | TIVA_TDES0_FS | + TIVA_TDES0_TCH | TIVA_TDES0_OWN; + tdp->physdesc->locked = 0; + + /* If the DMA engine is stalled then a restart request is issued.*/ + if ((ETH->DMARIS & (0x7 << 20)) == (6 << 20)) { + ETH->DMARIS = (1 << 2); + ETH->TXPOLLD = 1; /* Any value is OK.*/ + } + + osalSysUnlock(); +} + +/** + * @brief Returns a receive descriptor. + * + * @param[in] macp pointer to the @p MACDriver object + * @param[out] rdp pointer to a @p MACReceiveDescriptor structure + * @return The operation status. + * @retval RDY_OK the descriptor has been obtained. + * @retval RDY_TIMEOUT descriptor not available. + * + * @notapi + */ +msg_t mac_lld_get_receive_descriptor(MACDriver *macp, + MACReceiveDescriptor *rdp) +{ + tiva_eth_rx_descriptor_t *rdes; + + osalSysLock(); + + /* Get Current RX descriptor.*/ + rdes = macp->rxptr; + + /* Iterates through received frames until a valid one is found, invalid + frames are discarded.*/ + while (!(rdes->rdes0 & TIVA_RDES0_OWN)) { + if (!(rdes->rdes0 & (TIVA_RDES0_AFM | TIVA_RDES0_ES)) +#if TIVA_MAC_IP_CHECKSUM_OFFLOAD + && (rdes->rdes0 & TIVA_RDES0_FT) + && !(rdes->rdes0 & (TIVA_RDES0_IPHCE | TIVA_RDES0_PCE)) +#endif + && (rdes->rdes0 & TIVA_RDES0_FS) && (rdes->rdes0 & TIVA_RDES0_LS)) { + /* Found a valid one.*/ + rdp->offset = 0; + rdp->size = ((rdes->rdes0 & TIVA_RDES0_FL_MASK) >> 16) - 4; + rdp->physdesc = rdes; + macp->rxptr = (tiva_eth_rx_descriptor_t *)rdes->rdes3; + + osalSysUnlock(); + return MSG_OK; + } + /* Invalid frame found, purging.*/ + rdes->rdes0 = TIVA_RDES0_OWN; + rdes = (tiva_eth_rx_descriptor_t *)rdes->rdes3; + } + + /* Next descriptor to check.*/ + macp->rxptr = rdes; + + osalSysUnlock(); + return MSG_TIMEOUT; +} + +/** + * @brief Releases a receive descriptor. + * @details The descriptor and its buffer are made available for more incoming + * frames. + * + * @param[in] rdp the pointer to the @p MACReceiveDescriptor structure + * + * @notapi + */ +void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) +{ + osalDbgAssert(!(rdp->physdesc->rdes0 & TIVA_RDES0_OWN), + "attempt to release descriptor already owned by DMA"); + + osalSysLock(); + + /* Give buffer back to the Ethernet DMA.*/ + rdp->physdesc->rdes0 = TIVA_RDES0_OWN; + + /* If the DMA engine is stalled then a restart request is issued.*/ + if ((ETH->STATUS & (0xf << 17)) == (4 << 17)) { + ETH->DMARIS = (1 << 7); + ETH->TXPOLLD = 1; /* Any value is OK.*/ + } + + osalSysUnlock(); +} + +/** + * @brief Updates and returns the link status. + * + * @param[in] macp pointer to the @p MACDriver object + * @return The link status. + * @retval TRUE if the link is active. + * @retval FALSE if the link is down. + * + * @notapi + */ +bool mac_lld_poll_link_status(MACDriver *macp) +{ + uint32_t maccfg, bmsr, bmcr; + + maccfg = ETH->CFG; + + /* PHY CR and SR registers read.*/ + (void)mii_read(macp, MII_BMSR); + bmsr = mii_read(macp, MII_BMSR); + bmcr = mii_read(macp, MII_BMCR); + + /* Check on auto-negotiation mode.*/ + if (bmcr & BMCR_ANENABLE) { + uint32_t lpa; + + /* Auto-negotiation must be finished without faults and link established.*/ + if ((bmsr & (BMSR_LSTATUS | BMSR_RFAULT | BMSR_ANEGCOMPLETE)) != + (BMSR_LSTATUS | BMSR_ANEGCOMPLETE)) + return macp->link_up = false; + + /* Auto-negotiation enabled, checks the LPA register.*/ + lpa = mii_read(macp, MII_LPA); + + /* Check on link speed.*/ + if (lpa & (LPA_100HALF | LPA_100FULL | LPA_100BASE4)) + maccfg |= (1 << 14); + else + maccfg &= ~(1 << 14); + + /* Check on link mode.*/ + if (lpa & (LPA_10FULL | LPA_100FULL)) + maccfg |= (1 << 11); + else + maccfg &= ~(1 << 11); + } + else { + /* Link must be established.*/ + if (!(bmsr & BMSR_LSTATUS)) + return macp->link_up = false; + + /* Check on link speed.*/ + if (bmcr & BMCR_SPEED100) + maccfg |= (1 << 14); + else + maccfg &= ~(1 << 14); + + /* Check on link mode.*/ + if (bmcr & BMCR_FULLDPLX) + maccfg |= (1 << 11); + else + maccfg &= ~(1 << 11); + } + + /* Changes the mode in the MAC.*/ + ETH->CFG = maccfg; + + /* Returns the link status.*/ + return macp->link_up = true; +} + +/** + * @brief Writes to a transmit descriptor's stream. + * + * @param[in] tdp pointer to a @p MACTransmitDescriptor structure + * @param[in] buf pointer to the buffer containing the data to be + * written + * @param[in] size number of bytes to be written + * @return The number of bytes written into the descriptor's + * stream, this value can be less than the amount + * specified in the parameter @p size if the maximum + * frame size is reached. + * + * @notapi + */ +size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, + uint8_t *buf, + size_t size) +{ + osalDbgAssert(!(tdp->physdesc->tdes0 & TIVA_TDES0_OWN), + "attempt to write descriptor already owned by DMA"); + + if (size > tdp->size - tdp->offset) + size = tdp->size - tdp->offset; + + if (size > 0) { + memcpy((uint8_t *)(tdp->physdesc->tdes2) + tdp->offset, buf, size); + tdp->offset += size; + } + return size; +} + +/** + * @brief Reads from a receive descriptor's stream. + * + * @param[in] rdp pointer to a @p MACReceiveDescriptor structure + * @param[in] buf pointer to the buffer that will receive the read data + * @param[in] size number of bytes to be read + * @return The number of bytes read from the descriptor's + * stream, this value can be less than the amount + * specified in the parameter @p size if there are + * no more bytes to read. + * + * @notapi + */ +size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, + uint8_t *buf, + size_t size) +{ + osalDbgAssert(!(rdp->physdesc->rdes0 & TIVA_RDES0_OWN), + "attempt to read descriptor already owned by DMA"); + + if (size > rdp->size - rdp->offset) + size = rdp->size - rdp->offset; + + if (size > 0) { + memcpy(buf, (uint8_t *)(rdp->physdesc->rdes2) + rdp->offset, size); + rdp->offset += size; + } + return size; +} + +#if MAC_USE_ZERO_COPY || defined(__DOXYGEN__) +/** + * @brief Returns a pointer to the next transmit buffer in the descriptor + * chain. + * @note The API guarantees that enough buffers can be requested to fill + * a whole frame. + * + * @param[in] tdp pointer to a @p MACTransmitDescriptor structure + * @param[in] size size of the requested buffer. Specify the frame size + * on the first call then scale the value down subtracting + * the amount of data already copied into the previous + * buffers. + * @param[out] sizep pointer to variable receiving the buffer size, it is + * zero when the last buffer has already been returned. + * Note that a returned size lower than the amount + * requested means that more buffers must be requested + * in order to fill the frame data entirely. + * @return Pointer to the returned buffer. + * @retval NULL if the buffer chain has been entirely scanned. + * + * @notapi + */ +uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp, + size_t size, + size_t *sizep) +{ + if (tdp->offset == 0) { + *sizep = tdp->size; + tdp->offset = size; + return (uint8_t *)tdp->physdesc->tdes2; + } + *sizep = 0; + return NULL; +} + +/** + * @brief Returns a pointer to the next receive buffer in the descriptor + * chain. + * @note The API guarantees that the descriptor chain contains a whole + * frame. + * + * @param[in] rdp pointer to a @p MACReceiveDescriptor structure + * @param[out] sizep pointer to variable receiving the buffer size, it is + * zero when the last buffer has already been returned. + * @return Pointer to the returned buffer. + * @retval NULL if the buffer chain has been entirely scanned. + * + * @notapi + */ +const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp, + size_t *sizep) +{ + if (rdp->size > 0) { + *sizep = rdp->size; + rdp->offset = rdp->size; + rdp->size = 0; + return (uint8_t *)rdp->physdesc->rdes2; + } + *sizep = 0; + return NULL; +} +#endif /* MAC_USE_ZERO_COPY */ + +#endif /* HAL_USE_MAC */ + +/** @} */ diff --git a/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.h b/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.h new file mode 100644 index 0000000..98036bb --- /dev/null +++ b/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.h @@ -0,0 +1,438 @@ +/* + Copyright (C) 2014..2016 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file TIVA/mac_lld.h + * @brief MAC Driver subsystem low level driver header. + * + * @addtogroup MAC + * @{ + */ + +#ifndef HAL_MAC_LLD_H +#define HAL_MAC_LLD_H + +#if HAL_USE_MAC || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief This implementation supports the zero-copy mode API. + */ +#define MAC_SUPPORTS_ZERO_COPY TRUE + +/** + * @name RDES0 constants + * @{ + */ +#define TIVA_RDES0_OWN 0x80000000 +#define TIVA_RDES0_AFM 0x40000000 + +#define TIVA_RDES0_FL_MASK 0x3FFF0000 +#define TIVA_RDES0_FL(n) ((n) << 16) + +#define TIVA_RDES0_ES 0x00008000 +#define TIVA_RDES0_DESERR 0x00004000 +#define TIVA_RDES0_SAF 0x00002000 +#define TIVA_RDES0_LE 0x00001000 +#define TIVA_RDES0_OE 0x00000800 +#define TIVA_RDES0_VLAN 0x00000400 +#define TIVA_RDES0_FS 0x00000200 +#define TIVA_RDES0_LS 0x00000100 +#define TIVA_RDES0_TAGF 0x00000080 +#define TIVA_RDES0_LC 0x00000040 +#define TIVA_RDES0_FT 0x00000020 +#define TIVA_RDES0_RWT 0x00000010 +#define TIVA_RDES0_RE 0x00000008 +#define TIVA_RDES0_DE 0x00000004 +#define TIVA_RDES0_CE 0x00000002 +#define TIVA_RDES0_ESA 0x00000001 +/** @} */ + +/** + * @name RDES1 constants + * @{ + */ +#define TIVA_RDES1_DIC 0x80000000 + +#define TIVA_RDES1_RBS2_MASK 0x1FFF0000 +#define TIVA_RDES1_RBS2(n) ((n) << 16) + +#define TIVA_RDES1_RER 0x00008000 +#define TIVA_RDES1_RCH 0x00004000 + +#define TIVA_RDES1_RBS1_MASK 0x00001FFF +#define TIVA_RDES1_RBS1(n) ((n) << 0) + +/** @} */ + +/** + * @name TDES0 constants + * @{ + */ +#define TIVA_TDES0_OWN 0x80000000 +#define TIVA_TDES0_IC 0x40000000 +#define TIVA_TDES0_LS 0x20000000 +#define TIVA_TDES0_FS 0x10000000 +#define TIVA_TDES0_DC 0x08000000 +#define TIVA_TDES0_DP 0x04000000 +#define TIVA_TDES0_TTSE 0x02000000 +#define TIVA_TDES0_CRCR 0x01000000 + +#define TIVA_TDES0_CIC_MASK 0x00C00000 +#define TIVA_TDES0_CIC(n) ((n) << 22) + +#define TIVA_TDES0_TER 0x00200000 +#define TIVA_TDES0_TCH 0x00100000 +#define TIVA_TDES0_VLIC 0x000C0000 +#define TIVA_TDES0_TTSS 0x00020000 +#define TIVA_TDES0_IHE 0x00010000 +#define TIVA_TDES0_ES 0x00008000 +#define TIVA_TDES0_JT 0x00004000 +#define TIVA_TDES0_FF 0x00002000 +#define TIVA_TDES0_IPE 0x00001000 +#define TIVA_TDES0_LC 0x00000800 +#define TIVA_TDES0_NC 0x00000400 +#define TIVA_TDES0_LCO 0x00000200 +#define TIVA_TDES0_EC 0x00000100 +#define TIVA_TDES0_VF 0x00000080 + +#define TIVA_TDES0_CC_MASK 0x00000078 +#define TIVA_TDES0_CC(n) ((n) << 3) + +#define TIVA_TDES0_ED 0x00000004 +#define TIVA_TDES0_UF 0x00000002 +#define TIVA_TDES0_DB 0x00000001 +/** @} */ + +/** + * @name TDES1 constants + * @{ + */ +#define TIVA_TDES1_SAIC_MASK 0xE0000000 +#define TIVA_TDES1_SAIC(n) ((n) << 29) + +#define TIVA_TDES1_TBS2_MASK 0x1FFF0000 +#define TIVA_TDES1_TBS2(n) ((n) << 16) + +#define TIVA_TDES1_TBS1_MASK 0x00001FFF +#define TIVA_TDES1_TBS1(n) ((n) << 0) +/** @} */ + + + + +/** + * @name Ethernet PHY registers + */ +#define TIVA_BMCR 0x00000000 /* MR0 - Basic Mode Control */ +#define TIVA_BMSR 0x00000001 /* MR1 - Basic Mode Status */ +#define TIVA_ID1 0x00000002 /* MR2 - Identifier Register 1 */ +#define TIVA_ID2 0x00000003 /* MR3 - Identifier Register 2 */ +#define TIVA_ANA 0x00000004 /* MR4 - Auto-Negotiation Advertisement */ +#define TIVA_ANLPA 0x00000005 /* MR5 - Auto-Negotiation Link Partner Ability */ +#define TIVA_ANER 0x00000006 /* MR6 - Auto-Negotiation Expansion */ +#define TIVA_ANNPTR 0x00000007 /* MR7 - Auto-Negotiation Next Page TX */ +#define TIVA_ANLNPTR 0x00000008 /* MR8 - Auto-Negotiation Link Partner Ability Next Page */ +#define TIVA_CFG1 0x00000009 /* MR9 - Configuration 1 */ +#define TIVA_CFG2 0x0000000A /* MR10 - Configuration 2 */ +#define TIVA_CFG3 0x0000000B /* MR11 - Configuration 3 */ +#define TIVA_REGCTL 0x0000000D /* MR13 - Register Control */ +#define TIVA_ADDAR 0x0000000E /* MR14 - Address or Data */ +#define TIVA_STS 0x00000010 /* MR16 - Status */ +#define TIVA_SCR 0x00000011 /* MR17 - Specific Control */ +#define TIVA_MISR1 0x00000012 /* MR18 - MII Interrupt Status 1 */ +#define TIVA_MISR2 0x00000013 /* MR19 - MII Interrupt Status 2 */ +#define TIVA_FCSCR 0x00000014 /* MR20 - False Carrier Sense Counter */ +#define TIVA_RXERCNT 0x00000015 /* MR21 - Receive Error Count */ +#define TIVA_BISTCR 0x00000016 /* MR22 - BIST Control */ +#define TIVA_LEDCR 0x00000018 /* MR24 - LED Control */ +#define TIVA_CTL 0x00000019 /* MR25 - Control */ +#define TIVA_10BTSC 0x0000001A /* MR26 - 10Base-T Status/Control - MR26 */ +#define TIVA_BICSR1 0x0000001B /* MR27 - BIST Control and Status 1 */ +#define TIVA_BICSR2 0x0000001C /* MR28 - BIST Control and Status 2 */ +#define TIVA_CDCR 0x0000001E /* MR30 - Cable Diagnostic Control */ +#define TIVA_RCR 0x0000001F /* MR31 - Reset Control */ +#define TIVA_LEDCFG 0x00000025 /* MR37 - LED Configuration */ +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief Number of available transmit buffers. + */ +#if !defined(TIVA_MAC_TRANSMIT_BUFFERS) || defined(__DOXYGEN__) +#define TIVA_MAC_TRANSMIT_BUFFERS 2 +#endif + +/** + * @brief Number of available receive buffers. + */ +#if !defined(TIVA_MAC_RECEIVE_BUFFERS) || defined(__DOXYGEN__) +#define TIVA_MAC_RECEIVE_BUFFERS 4 +#endif + +/** + * @brief Maximum supported frame size. + */ +#if !defined(TIVA_MAC_BUFFERS_SIZE) || defined(__DOXYGEN__) +#define TIVA_MAC_BUFFERS_SIZE 1522 +#endif + +/** + * @brief PHY detection timeout. + * @details Timeout, in milliseconds, for PHY address detection, if a PHY + * is not detected within the timeout then the driver halts during + * initialization. This setting applies only if the PHY address is + * not explicitly set in the board header file using + * @p BOARD_PHY_ADDRESS. A zero value disables the timeout and a + * single search path is performed. + */ +#if !defined(TIVA_MAC_PHY_TIMEOUT) || defined(__DOXYGEN__) +#define TIVA_MAC_PHY_TIMEOUT 0 +#endif + +/** + * @brief Change the PHY power state inside the driver. + */ +#if !defined(TIVA_MAC_CHANGE_PHY_STATE) || defined(__DOXYGEN__) +#define TIVA_MAC_CHANGE_PHY_STATE TRUE +#endif + +/** + * @brief ETHD1 interrupt priority level setting. + */ +#if !defined(TIVA_MAC_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_MAC_IRQ_PRIORITY 5 +#endif + +/** + * @brief IP checksum offload. + * @details The following modes are available: + * - 0 Function disabled. + * - 1 Only IP header checksum calculation and insertion are enabled. + * - 2 IP header checksum and payload checksum calculation and + * insertion are enabled, but pseudo-header checksum is not + * calculated in hardware. + * - 3 IP Header checksum and payload checksum calculation and + * insertion are enabled, and pseudo-header checksum is + * calculated in hardware. + * . + */ +#if !defined(TIVA_MAC_IP_CHECKSUM_OFFLOAD) || defined(__DOXYGEN__) +#define TIVA_MAC_IP_CHECKSUM_OFFLOAD 0 +#endif +/** @} */ + +#ifndef EMAC_PHY_CONFIG +#define EMAC_PHY_CONFIG ((0 << 31) | \ + (1 << 23) | \ + (1 << 10) | \ + (1 << 3) | \ + (3 << 1) | \ + (1 << 0)) +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if (TIVA_MAC_PHY_TIMEOUT > 0) && !HAL_IMPLEMENTS_COUNTERS +#error "TIVA_MAC_PHY_TIMEOUT requires the realtime counter service" +#endif + +#if !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_MAC_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to MAC" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of an Tiva Ethernet receive descriptor. + */ +typedef struct +{ + volatile uint32_t rdes0; + volatile uint32_t rdes1; + volatile uint32_t rdes2; + volatile uint32_t rdes3; +} tiva_eth_rx_descriptor_t; + +/** + * @brief Type of an Tiva Ethernet transmit descriptor. + */ +typedef struct +{ + volatile uint32_t tdes0; + volatile uint32_t tdes1; + volatile uint32_t tdes2; + volatile uint32_t tdes3; + volatile uint32_t locked; +} tiva_eth_tx_descriptor_t; + +/** + * @brief Driver configuration structure. + */ +typedef struct +{ + /** + * @brief MAC address. + */ + uint8_t *mac_address; + /* End of the mandatory fields.*/ +} MACConfig; + +/** + * @brief Structure representing a MAC driver. + */ +struct MACDriver +{ + /** + * @brief Driver state. + */ + macstate_t state; + /** + * @brief Current configuration data. + */ + const MACConfig *config; + /** + * @brief Transmit semaphore. + */ + threads_queue_t tdqueue; + /** + * @brief Receive semaphore. + */ + threads_queue_t rdqueue; +#if MAC_USE_EVENTS || defined(__DOXYGEN__) + /** + * @brief Receive event. + */ + event_source_t rdevent; +#endif + /* End of the mandatory fields.*/ + /** + * @brief Link status flag. + */ + bool link_up; + /** + * @brief PHY address (pre shifted). + */ + uint32_t phyaddr; + /** + * @brief Receive next frame pointer. + */ + tiva_eth_rx_descriptor_t *rxptr; + /** + * @brief Transmit next frame pointer. + */ + tiva_eth_tx_descriptor_t *txptr; +}; + +/** + * @brief Structure representing a transmit descriptor. + */ +typedef struct +{ + /** + * @brief Current write offset. + */ + size_t offset; + /** + * @brief Available space size. + */ + size_t size; + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the physical descriptor. + */ + tiva_eth_tx_descriptor_t *physdesc; +} MACTransmitDescriptor; + +/** + * @brief Structure representing a receive descriptor. + */ +typedef struct +{ + /** + * @brief Current read offset. + */ + size_t offset; + /** + * @brief Available data size. + */ + size_t size; + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the physical descriptor. + */ + tiva_eth_rx_descriptor_t *physdesc; +} MACReceiveDescriptor; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +extern MACDriver ETHD1; + +#ifdef __cplusplus +extern "C" { +#endif + void mac_lld_init(void); + void mac_lld_start(MACDriver *macp); + void mac_lld_stop(MACDriver *macp); + msg_t mac_lld_get_transmit_descriptor(MACDriver *macp, + MACTransmitDescriptor *tdp); + void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp); + msg_t mac_lld_get_receive_descriptor(MACDriver *macp, + MACReceiveDescriptor *rdp); + void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp); + bool mac_lld_poll_link_status(MACDriver *macp); + size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, + uint8_t *buf, + size_t size); + size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, + uint8_t *buf, + size_t size); +#if MAC_USE_ZERO_COPY + uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp, + size_t size, + size_t *sizep); + const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp, + size_t *sizep); +#endif /* MAC_USE_ZERO_COPY */ +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_MAC */ + +#endif /* HAL_MAC_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.c b/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.c new file mode 100644 index 0000000..ad7c587 --- /dev/null +++ b/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.c @@ -0,0 +1,585 @@ +/* + Copyright (C) 2014..2016 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file TIVA/LLD/pwm_lld.c + * @brief TM4C123x/TM4C129x PWM subsystem low level driver. + * + * @addtogroup PWM + * @{ + */ + +#include "hal.h" + +#if HAL_USE_PWM || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +#define PWM_INT_CMPBD (1 << 5) +#define PWM_INT_CMPBU (1 << 4) +#define PWM_INT_CMPAD (1 << 3) +#define PWM_INT_CMPAU (1 << 2) +#define PWM_INT_CNTLOAD (1 << 1) +#define PWM_INT_CNTZERO (1 << 0) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief PWMD1 driver identifier. + */ +#if TIVA_PWM_USE_PWM0 || defined(__DOXYGEN__) +PWMDriver PWMD1; +#endif + +/** + * @brief PWMD2 driver identifier. + */ +#if TIVA_PWM_USE_PWM1 || defined(__DOXYGEN__) +PWMDriver PWMD2; +#endif + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Common PWM Generator IRQ handler. + * @note It is assumed that the various sources are only activated if the + * associated callback pointer is not equal to @p NULL in order to not + * perform an extra check in a potentially critical interrupt handler. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] i pwm generator number + */ +static void pwm_lld_serve_generator_interrupt (PWMDriver *pwmp, uint8_t i) +{ + uint32_t isc; + + isc = pwmp->pwm->PWM[i].ISC; + pwmp->pwm->PWM[i].ISC = isc; + + if (((isc & PWM_INT_CMPAD) != 0) && + (pwmp->config->channels[i * 2 + 0].callback != NULL)) { + pwmp->config->channels[i * 2 + 0].callback(pwmp); + } + + if (((isc & PWM_INT_CMPAU) != 0) && + (pwmp->config->channels[i * 2 + 0].callback != NULL)) { + pwmp->config->channels[i * 2 + 0].callback(pwmp); + } + + if (((isc & PWM_INT_CMPBD) != 0) && + (pwmp->config->channels[i * 2 + 1].callback != NULL)) { + pwmp->config->channels[i * 2 + 1].callback(pwmp); + } + + if (((isc & PWM_INT_CMPBU) != 0) && + (pwmp->config->channels[i * 2 + 1].callback != NULL)) { + pwmp->config->channels[i * 2 + 1].callback(pwmp); + } + + if (((isc & PWM_INT_CNTLOAD) != 0) && (pwmp->config->callback != NULL)) { + pwmp->config->callback(pwmp); + } + + if (((isc & PWM_INT_CNTZERO) != 0) && (pwmp->config->callback != NULL)) { + pwmp->config->callback(pwmp); + } +} + +/** + * @brief Common PWM fault IRQ handler. + * + * @param[in] pwmp pointer to a @p PWMDriver object + */ +static void pwm_lld_serve_fault_interrupt (PWMDriver *pwmp) +{ + (void) pwmp; +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if TIVA_PWM_USE_PWM0 +#if !defined(TIVA_PWM0FAULT_HANDLER) +#error "TIVA_PWM0FAULT_HANDLER not defined" +#endif +/* + * @brief PWM0 Fault handler + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_PWM0FAULT_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + pwm_lld_serve_fault_interrupt(&PWMD1); + + OSAL_IRQ_EPILOGUE(); +} + +#if !defined(TIVA_PWM0GEN0_HANDLER) +#error "TIVA_PWM0GEN0_HANDLER not defined" +#endif +/* + * @brief PWM0 Generator 0 handler + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_PWM0GEN0_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + pwm_lld_serve_generator_interrupt(&PWMD1, 0); + + OSAL_IRQ_EPILOGUE(); +} + +#if !defined(TIVA_PWM0GEN1_HANDLER) +#error "TIVA_PWM0GEN1_HANDLER not defined" +#endif +/* + * @brief PWM0 Generator 1 handler + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_PWM0GEN1_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + pwm_lld_serve_generator_interrupt(&PWMD1, 1); + + OSAL_IRQ_EPILOGUE(); +} + +#if !defined(TIVA_PWM0GEN2_HANDLER) +#error "TIVA_PWM0GEN2_HANDLER not defined" +#endif +/* + * @brief PWM0 Generator 2 handler + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_PWM0GEN2_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + pwm_lld_serve_generator_interrupt(&PWMD1, 2); + + OSAL_IRQ_EPILOGUE(); +} + +#if !defined(TIVA_PWM0GEN3_HANDLER) +#error "TIVA_PWM0GEN3_HANDLER not defined" +#endif +/* + * @brief PWM0 Generator 3 handler + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_PWM0GEN3_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + pwm_lld_serve_generator_interrupt(&PWMD1, 3); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_PWM_USE_PWM1 +#if !defined(TIVA_PWM1FAULT_HANDLER) +#error "TIVA_PWM1FAULT_HANDLER not defined" +#endif +/* + * @brief PWM1 Fault handler + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_PWM1FAULT_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + pwm_lld_serve_fault_interrupt(&PWMD2); + + OSAL_IRQ_EPILOGUE(); +} + +#if !defined(TIVA_PWM1GEN0_HANDLER) +#error "TIVA_PWM1GEN0_HANDLER not defined" +#endif +/* + * @brief PWM1 Generator 0 handler + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_PWM1GEN0_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + pwm_lld_serve_generator_interrupt(&PWMD2, 0); + + OSAL_IRQ_EPILOGUE(); +} + +#if !defined(TIVA_PWM1GEN1_HANDLER) +#error "TIVA_PWM1GEN1_HANDLER not defined" +#endif +/* + * @brief PWM1 Generator 1 handler + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_PWM1GEN1_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + pwm_lld_serve_generator_interrupt(&PWMD2, 1); + + OSAL_IRQ_EPILOGUE(); +} + +#if !defined(TIVA_PWM1GEN2_HANDLER) +#error "TIVA_PWM1GEN2_HANDLER not defined" +#endif +/* + * @brief PWM1 Generator 2 handler + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_PWM1GEN2_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + pwm_lld_serve_generator_interrupt(&PWMD2, 2); + + OSAL_IRQ_EPILOGUE(); +} + +#if !defined(TIVA_PWM1GEN3_HANDLER) +#error "TIVA_PWM1GEN3_HANDLER not defined" +#endif +/* + * @brief PWM1 Generator 3 handler + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_PWM1GEN3_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + pwm_lld_serve_generator_interrupt(&PWMD2, 3); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level PWM driver initialization. + * + * @notapi + */ +void pwm_lld_init(void) +{ + /* Driver initialization.*/ +#if TIVA_PWM_USE_PWM0 + pwmObjectInit(&PWMD1); + PWMD1.channels = PWM_CHANNELS; + PWMD1.pwm = PWM0; +#endif + +#if TIVA_PWM_USE_PWM1 + pwmObjectInit(&PWMD2); + PWMD2.channels = PWM_CHANNELS; + PWMD2.pwm = PWM1; +#endif +} + +/** + * @brief Configures and activates the PWM peripheral. + * @note Starting a driver that is already in the @p PWM_READY state + * disables all the active channels. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_start(PWMDriver *pwmp) +{ + uint8_t i; + uint32_t invert = 0; + uint32_t enable = 0; + + if (pwmp->state == PWM_STOP) { + /* Clock activation.*/ +#if TIVA_PWM_USE_PWM0 + if (&PWMD1 == pwmp) { + SYSCTL->RCGCPWM |= (1 << 0); + + while (!(SYSCTL->PRPWM & (1 << 0))) + ; + + nvicEnableVector(TIVA_PWM0FAULT_NUMBER, + TIVA_PWM_PWM0_FAULT_IRQ_PRIORITY); + nvicEnableVector(TIVA_PWM0GEN0_NUMBER, TIVA_PWM_PWM0_0_IRQ_PRIORITY); + nvicEnableVector(TIVA_PWM0GEN1_NUMBER, TIVA_PWM_PWM0_1_IRQ_PRIORITY); + nvicEnableVector(TIVA_PWM0GEN2_NUMBER, TIVA_PWM_PWM0_2_IRQ_PRIORITY); + nvicEnableVector(TIVA_PWM0GEN3_NUMBER, TIVA_PWM_PWM0_3_IRQ_PRIORITY); + } +#endif + +#if TIVA_PWM_USE_PWM1 + if (&PWMD2 == pwmp) { + SYSCTL->RCGCPWM |= (1 << 1); + + while (!(SYSCTL->PRPWM & (1 << 1))) + ; + + nvicEnableVector(TIVA_PWM1FAULT_NUMBER, + TIVA_PWM_PWM1_FAULT_IRQ_PRIORITY); + nvicEnableVector(TIVA_PWM1GEN0_NUMBER, TIVA_PWM_PWM1_0_IRQ_PRIORITY); + nvicEnableVector(TIVA_PWM1GEN1_NUMBER, TIVA_PWM_PWM1_1_IRQ_PRIORITY); + nvicEnableVector(TIVA_PWM1GEN2_NUMBER, TIVA_PWM_PWM1_2_IRQ_PRIORITY); + nvicEnableVector(TIVA_PWM1GEN3_NUMBER, TIVA_PWM_PWM1_3_IRQ_PRIORITY); + } +#endif + } + else { + /* Driver re-configuration scenario, it must be stopped first.*/ + pwmp->pwm->PWM[0].CTL = 0; + pwmp->pwm->PWM[1].CTL = 0; + pwmp->pwm->PWM[2].CTL = 0; + pwmp->pwm->PWM[3].CTL = 0; + } + + /* Timer configuration.*/ + for (i = 0; i < (PWM_CHANNELS >> 1); i++) { + pwmp->pwm->PWM[i].CTL = 0; + pwmp->pwm->PWM[i].GEN[0] = 0x08C; + pwmp->pwm->PWM[i].GEN[1] = 0x80C; + pwmp->pwm->PWM[i].LOAD = (uint16_t)(pwmp->config->frequency - 1); + pwmp->pwm->PWM[i].CMP[0] = (uint16_t)(pwmp->period - 1); + pwmp->pwm->PWM[i].CMP[1] = (uint16_t)(pwmp->period - 1); + } + + /* Output enables and polarities setup.*/ + for (i = 0; i < PWM_CHANNELS; i++) { + switch (pwmp->config->channels[i].mode & PWM_OUTPUT_MASK) { + case PWM_OUTPUT_DISABLED: + enable &= ~(1 << i); + break; + case PWM_OUTPUT_ACTIVE_LOW: + invert |= (1 << i); + enable |= (1 << i); + break; + case PWM_OUTPUT_ACTIVE_HIGH: + invert &= ~(1 << i); + enable |= (1 << i); + break; + default: + ; + } + } + + pwmp->pwm->INVERT = invert; + pwmp->pwm->ENABLE = enable; + pwmp->pwm->ISC = 0xFFFFFFFF; +} + +/** + * @brief Deactivates the PWM peripheral. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_stop(PWMDriver *pwmp) +{ + /* If in ready state then disables the PWM clock.*/ + if (pwmp->state == PWM_READY) { + pwmp->pwm->PWM[0].CTL = 0; + pwmp->pwm->PWM[1].CTL = 0; + pwmp->pwm->PWM[2].CTL = 0; + pwmp->pwm->PWM[3].CTL = 0; + +#if TIVA_PWM_USE_PWM0 + if (&PWMD1 == pwmp) { + nvicDisableVector(TIVA_PWM0FAULT_NUMBER); + nvicDisableVector(TIVA_PWM0GEN0_NUMBER); + nvicDisableVector(TIVA_PWM0GEN1_NUMBER); + nvicDisableVector(TIVA_PWM0GEN2_NUMBER); + nvicDisableVector(TIVA_PWM0GEN3_NUMBER); + SYSCTL->RCGCPWM &= ~(1 << 0); + } +#endif + +#if TIVA_PWM_USE_PWM1 + if (&PWMD2 == pwmp) { + nvicDisableVector(TIVA_PWM1FAULT_NUMBER); + nvicDisableVector(TIVA_PWM1GEN0_NUMBER); + nvicDisableVector(TIVA_PWM1GEN1_NUMBER); + nvicDisableVector(TIVA_PWM1GEN2_NUMBER); + nvicDisableVector(TIVA_PWM1GEN3_NUMBER); + SYSCTL->RCGCPWM &= ~(1 << 1); + } +#endif + } +} + +/** + * @brief Enables a PWM channel. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is active using the specified configuration. + * @note The function has effect at the next cycle start. + * @note Channel notification is not enabled. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...channels-1) + * @param[in] width PWM pulse width as clock pulses number + * + * @notapi + */ +void pwm_lld_enable_channel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width) +{ + /* Changing channel duty cycle on the fly.*/ + pwmp->pwm->PWM[channel >> 1].CMP[channel & 1] = width; + pwmp->pwm->PWM[channel >> 1].CTL |= (1 << 0); +} + +/** + * @brief Disables a PWM channel and its notification. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The channel is disabled and its output line returned to the + * idle state. + * @note The function has effect at the next cycle start. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...channels-1) + * + * @notapi + */ +void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) +{ + pwmp->pwm->PWM[channel >> 1].CMP[channel & 1] = 0; + pwmp->pwm->PWM[channel >> 1].CTL &= ~(1 << 0); +} + +/** + * @brief Enables the periodic activation edge notification. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @note If the notification is already enabled then the call has no effect. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) +{ + uint32_t inten; + uint8_t i; + + /* If the IRQ is not already enabled care must be taken to clear it, + it is probably already pending because the timer is running.*/ + for(i = 0; i < (PWM_CHANNELS >> 1); i++) { + inten = pwmp->pwm->PWM[i].INTEN; + if ((inten & 0x03) == 0) { + pwmp->pwm->PWM[i].INTEN |= 0x03; + pwmp->pwm->PWM[i].ISC = 0x03; + } + } + + pwmp->pwm->INTEN = 0x3f; +} + +/** + * @brief Disables the periodic activation edge notification. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @note If the notification is already disabled then the call has no effect. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * + * @notapi + */ +void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) +{ + pwmp->pwm->PWM[0].INTEN &= ~(0x03); + pwmp->pwm->PWM[1].INTEN &= ~(0x03); + pwmp->pwm->PWM[2].INTEN &= ~(0x03); + pwmp->pwm->PWM[3].INTEN &= ~(0x03); + pwmp->pwm->INTEN &= ~(0x3F); +} + +/** + * @brief Enables a channel de-activation edge notification. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @pre The channel must have been activated using @p pwmEnableChannel(). + * @note If the notification is already enabled then the call has no effect. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...channels-1) + * + * @notapi + */ +void pwm_lld_enable_channel_notification(PWMDriver *pwmp, + pwmchannel_t channel) +{ + uint32_t inten = pwmp->pwm->PWM[channel >> 1].INTEN; + + /* If the IRQ is not already enabled care must be taken to clear it, + it is probably already pending because the timer is running.*/ + if ((inten & (0x03 << (((channel & 1) * 2) + 2))) == 0) { + pwmp->pwm->PWM[channel >> 1].INTEN |= (0x03 << (((channel & 1) * 2) + 2)); + pwmp->pwm->PWM[channel >> 1].ISC = (0x03 << (((channel & 1) * 2) + 2)); + } +} + +/** + * @brief Disables a channel de-activation edge notification. + * @pre The PWM unit must have been activated using @p pwmStart(). + * @pre The channel must have been activated using @p pwmEnableChannel(). + * @note If the notification is already disabled then the call has no effect. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] channel PWM channel identifier (0...channels-1) + * + * @notapi + */ +void pwm_lld_disable_channel_notification(PWMDriver *pwmp, + pwmchannel_t channel) +{ + pwmp->pwm->PWM[channel >> 1].INTEN &= ~(0x03 << (((channel & 1) * 2) + 2)); +} + +#endif /* HAL_USE_PWM */ + +/** + * @} + */ diff --git a/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.h b/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.h new file mode 100644 index 0000000..ac64fe1 --- /dev/null +++ b/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.h @@ -0,0 +1,372 @@ +/* + Copyright (C) 2014..2016 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file TIVA/LLD/pwm_lld.c + * @brief TM4C123x/TM4C129x PWM subsystem low level driver header. + * + * @addtogroup PWM + * @{ + */ + +#ifndef HAL_PWM_LLD_H +#define HAL_PWM_LLD_H + +#if HAL_USE_PWM || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @brief Number of PWM channels per PWM driver. + */ +#define PWM_CHANNELS 8 + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ + +/** + * @brief PWMD1 driver enable switch. + * @details If set to @p TRUE the support for PWMD1 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_PWM_USE_PWM0) || defined(__DOXYGEN__) +#define TIVA_PWM_USE_PWM0 FALSE +#endif + +/** + * @brief PWMD2 driver enable switch. + * @details If set to @p TRUE the support for PWMD2 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_PWM_USE_PWM1) || defined(__DOXYGEN__) +#define TIVA_PWM_USE_PWM1 FALSE +#endif + +/** + * @brief PWMD1 fault interrupt priority level setting. + */ +#if !defined(TIVA_PWM_PWM0_FAULT_IRQ_PRIORITY) || defined (__DOXYGEN__) +#define TIVA_PWM_PWM0_FAULT_IRQ_PRIORITY +#endif + +/** + * @brief PWMD1 channel 0 & 1 interrupt priority level setting. + */ +#if !defined(TIVA_PWM_PWM0_0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PWM_PWM0_0_IRQ_PRIORITY 4 +#endif + +/** + * @brief PWMD1 channel 2 & 3 interrupt priority level setting. + */ +#if !defined(TIVA_PWM_PWM0_1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PWM_PWM0_1_IRQ_PRIORITY 4 +#endif + +/** + * @brief PWMD1 channel 4 & 5 interrupt priority level setting. + */ +#if !defined(TIVA_PWM_PWM0_2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PWM_PWM0_2_IRQ_PRIORITY 4 +#endif + +/** + * @brief PWMD1 channel 6 & 7 interrupt priority level setting. + */ +#if !defined(TIVA_PWM_PWM0_3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PWM_PWM0_3_IRQ_PRIORITY 4 +#endif + +/** + * @brief PWMD2 fault interrupt priority level setting. + */ +#if !defined(TIVA_PWM_PWM1_FAULT_IRQ_PRIORITY) || defined (__DOXYGEN__) +#define TIVA_PWM_PWM1_FAULT_IRQ_PRIORITY +#endif + +/** + * @brief PWMD2 channel 0 & 1 interrupt priority level setting. + */ +#if !defined(TIVA_PWM_PWM1_0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PWM_PWM1_0_IRQ_PRIORITY 4 +#endif + +/** + * @brief PWMD2 channel 2 & 3 interrupt priority level setting. + */ +#if !defined(TIVA_PWM_PWM1_1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PWM_PWM1_1_IRQ_PRIORITY 4 +#endif + +/** + * @brief PWMD2 channel 4 & 5 interrupt priority level setting. + */ +#if !defined(TIVA_PWM_PWM1_2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PWM_PWM1_2_IRQ_PRIORITY 4 +#endif + +/** + * @brief PWMD2 channel 6 & 7 interrupt priority level setting. + */ +#if !defined(TIVA_PWM_PWM1_3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PWM_PWM1_3_IRQ_PRIORITY 4 +#endif + +/** + * @} + */ + +/*===========================================================================*/ +/* Configuration checks. */ +/*===========================================================================*/ + +#if TIVA_PWM_USE_PWM0 && !TIVA_HAS_PWM0 +#error "PWM0 not present in the selected device" +#endif + +#if TIVA_PWM_USE_PWM1 && !TIVA_HAS_PWM1 +#error "PWM1 not present in the selected device" +#endif + +#if !TIVA_PWM_USE_PWM0 && !TIVA_PWM_USE_PWM1 +#error "PWM driver activated but no PWM peripheral assigned" +#endif + +#if TIVA_PWM_USE_PWM0 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM0_FAULT_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to PWM0 FAULT" +#endif + +#if TIVA_PWM_USE_PWM0 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM0_0_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to PWM0 GEN0" +#endif + +#if TIVA_PWM_USE_PWM0 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM0_1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to PWM0 GEN1" +#endif + +#if TIVA_PWM_USE_PWM0 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM0_2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to PWM0 GEN2" +#endif + +#if TIVA_PWM_USE_PWM0 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM0_3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to PWM0 GEN3" +#endif + +#if TIVA_PWM_USE_PWM1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM1_FAULT_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to PWM1 FAULT" +#endif + +#if TIVA_PWM_USE_PWM1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM1_0_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to PWM1 GEN0" +#endif + +#if TIVA_PWM_USE_PWM1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM1_1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to PWM1 GEN1" +#endif + +#if TIVA_PWM_USE_PWM1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM1_2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to PWM1 GEN2" +#endif + +#if TIVA_PWM_USE_PWM1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM1_3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to PWM1 GEN3" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a PWM mode. + */ +typedef uint32_t pwmmode_t; + +/** + * @brief Type of a PWM channel. + */ +typedef uint8_t pwmchannel_t; + +/** + * @brief Type of a channels mask. + */ +typedef uint32_t pwmchnmsk_t; + +/** + * @brief Type of a PWM counter. + */ +typedef uint16_t pwmcnt_t; + +/** + * @brief Type of a PWM driver channel configuration structure. + */ +typedef struct { + /** + * @brief Channel active logic level. + */ + pwmmode_t mode; + /** + * @brief Channel callback pointer. + * @note This callback is invoked on the channel compare event. If set to + * @p NULL then the callback is disabled. + */ + pwmcallback_t callback; + /* End of the mandatory fields.*/ +} PWMChannelConfig; + +/** + * @brief Type of a PWM driver configuration structure. + */ +typedef struct { + /** + * @brief Timer clock in Hz. + * @note The low level can use assertions in order to catch invalid + * frequency specifications. + */ + uint32_t frequency; + /** + * @brief PWM period in ticks. + * @note The low level can use assertions in order to catch invalid + * period specifications. + */ + pwmcnt_t period; + /** + * @brief Periodic callback pointer. + * @note This callback is invoked on PWM counter reset. If set to + * @p NULL then the callback is disabled. + */ + pwmcallback_t callback; + /** + * @brief Channels configurations. + */ + PWMChannelConfig channels[PWM_CHANNELS]; + /* End of the mandatory fields.*/ +} PWMConfig; + +/** + * @brief Structure representing a PWM driver. + */ +struct PWMDriver { + /** + * @brief Driver state. + */ + pwmstate_t state; + /** + * @brief Current driver configuration data. + */ + const PWMConfig *config; + /** + * @brief Current PWM period in ticks. + */ + pwmcnt_t period; + /** + * @brief Mask of the enabled channels. + */ + pwmchnmsk_t enabled; + /** + * @brief Number of channels in this instance. + */ + pwmchannel_t channels; +#if defined(PWM_DRIVER_EXT_FIELDS) + PWM_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the PWMx registers block. + */ + PWM_TypeDef *pwm; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/** + * @brief Changes the period the PWM peripheral. + * @details This function changes the period of a PWM unit that has already + * been activated using @p pwmStart(). + * @pre The PWM unit must have been activated using @p pwmStart(). + * @post The PWM unit period is changed to the new value. + * @note The function has effect at the next cycle start. + * @note If a period is specified that is shorter than the pulse width + * programmed in one of the channels then the behavior is not + * guaranteed. + * + * @param[in] pwmp pointer to a @p PWMDriver object + * @param[in] period new cycle time in ticks + * + * @notapi + */ +#define pwm_lld_change_period(pwmp, period) \ + ((pwmp)->pwm->PWM[0].LOAD = (uint16_t)((period) - 1)); \ + ((pwmp)->pwm->PWM[1].LOAD = (uint16_t)((period) - 1)); \ + ((pwmp)->pwm->PWM[2].LOAD = (uint16_t)((period) - 1)); \ + ((pwmp)->pwm->PWM[3].LOAD = (uint16_t)((period) - 1)) + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if TIVA_PWM_USE_PWM0 && !defined(__DOXYGEN__) +extern PWMDriver PWMD1; +#endif + +#if TIVA_PWM_USE_PWM1 && !defined(__DOXYGEN__) +extern PWMDriver PWMD2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void pwm_lld_init(void); + void pwm_lld_start(PWMDriver *pwmp); + void pwm_lld_stop(PWMDriver *pwmp); + void pwm_lld_enable_channel(PWMDriver *pwmp, + pwmchannel_t channel, + pwmcnt_t width); + void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel); + void pwm_lld_enable_periodic_notification(PWMDriver *pwmp); + void pwm_lld_disable_periodic_notification(PWMDriver *pwmp); + void pwm_lld_enable_channel_notification(PWMDriver *pwmp, + pwmchannel_t channel); + void pwm_lld_disable_channel_notification(PWMDriver *pwmp, + pwmchannel_t channel); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_PWM */ + +#endif /* HAL_PWM_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c new file mode 100644 index 0000000..ded2b99 --- /dev/null +++ b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c @@ -0,0 +1,685 @@ +/* + Copyright (C) 2014..2016 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file TIVA/LLD/spi_lld.c + * @brief TM4C123x/TM4C129x SPI subsystem low level driver. + * + * @addtogroup SPI + * @{ + */ + +#include "ch.h" +#include "hal.h" + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief SPI1 driver identifier. + */ +#if TIVA_SPI_USE_SSI0 || defined(__DOXYGEN__) +SPIDriver SPID1; +#endif + +/** + * @brief SPI2 driver identifier. + */ +#if TIVA_SPI_USE_SSI1 || defined(__DOXYGEN__) +SPIDriver SPID2; +#endif + +/** + * @brief SPI3 driver identifier. + */ +#if TIVA_SPI_USE_SSI2 || defined(__DOXYGEN__) +SPIDriver SPID3; +#endif + +/** + * @brief SPI4 driver identifier. + */ +#if TIVA_SPI_USE_SSI3 || defined(__DOXYGEN__) +SPIDriver SPID4; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +static uint16_t dummytx; +static uint16_t dummyrx; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Common IRQ handler. + * + * @param[in] spip pointer to the @p SPIDriver object + */ +static void spi_serve_interrupt(SPIDriver *spip) +{ + SSI_TypeDef *ssi = spip->ssi; + uint32_t mis = ssi->MIS; + uint32_t dmachis = UDMA->CHIS; + + /* SPI error handling.*/ + if ((mis & (TIVA_MIS_RORMIS | TIVA_MIS_RTMIS)) != 0) { + TIVA_SPI_SSI_ERROR_HOOK(spip); + } + + if ( (dmachis & ( (1 << spip->dmarxnr) | (1 << spip->dmatxnr) ) ) == + ( (1 << spip->dmarxnr) | (1 << spip->dmatxnr) ) ) { + /* Clear DMA Channel interrupts.*/ + UDMA->CHIS = (1 << spip->dmarxnr) | (1 << spip->dmatxnr); + + /* Portable SPI ISR code defined in the high level driver, note, it is a + macro.*/ + _spi_isr_code(spip); + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if TIVA_SPI_USE_SSI0 || defined(__DOXYGEN__) +/** + * @brief SSI0 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_SSI0_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + spi_serve_interrupt(&SPID1); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_SPI_USE_SSI1 || defined(__DOXYGEN__) +/** + * @brief SSI1 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_SSI1_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + spi_serve_interrupt(&SPID2); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_SPI_USE_SSI2 || defined(__DOXYGEN__) +/** + * @brief SSI2 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_SSI2_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + spi_serve_interrupt(&SPID3); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_SPI_USE_SSI3 || defined(__DOXYGEN__) +/** + * @brief SSI3 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_SSI3_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + spi_serve_interrupt(&SPID4); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level SPI driver initialization. + * + * @notapi + */ +void spi_lld_init(void) +{ + dummytx = 0xFFFF; + +#if TIVA_SPI_USE_SSI0 + spiObjectInit(&SPID1); + SPID1.ssi = SSI0; + SPID1.dmarxnr = TIVA_SPI_SSI0_RX_UDMA_CHANNEL; + SPID1.dmatxnr = TIVA_SPI_SSI0_TX_UDMA_CHANNEL; + SPID1.rxchnmap = TIVA_SPI_SSI0_RX_UDMA_MAPPING; + SPID1.txchnmap = TIVA_SPI_SSI0_TX_UDMA_MAPPING; +#endif + +#if TIVA_SPI_USE_SSI1 + spiObjectInit(&SPID2); + SPID2.ssi = SSI1; + SPID2.dmarxnr = TIVA_SPI_SSI1_RX_UDMA_CHANNEL; + SPID2.dmatxnr = TIVA_SPI_SSI1_TX_UDMA_CHANNEL; + SPID2.rxchnmap = TIVA_SPI_SSI1_RX_UDMA_MAPPING; + SPID2.txchnmap = TIVA_SPI_SSI1_TX_UDMA_MAPPING; +#endif + +#if TIVA_SPI_USE_SSI2 + spiObjectInit(&SPID3); + SPID3.ssi = SSI2; + SPID3.dmarxnr = TIVA_SPI_SSI2_RX_UDMA_CHANNEL; + SPID3.dmatxnr = TIVA_SPI_SSI2_TX_UDMA_CHANNEL; + SPID3.rxchnmap = TIVA_SPI_SSI2_RX_UDMA_MAPPING; + SPID3.txchnmap = TIVA_SPI_SSI2_TX_UDMA_MAPPING; +#endif + +#if TIVA_SPI_USE_SSI3 + spiObjectInit(&SPID4); + SPID4.ssi = SSI3; + SPID4.dmarxnr = TIVA_SPI_SSI3_RX_UDMA_CHANNEL; + SPID4.dmatxnr = TIVA_SPI_SSI3_TX_UDMA_CHANNEL; + SPID4.rxchnmap = TIVA_SPI_SSI3_RX_UDMA_MAPPING; + SPID4.txchnmap = TIVA_SPI_SSI3_TX_UDMA_MAPPING; +#endif +} + +/** + * @brief Configures and activates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_start(SPIDriver *spip) +{ + if (spip->state == SPI_STOP) { + /* Clock activation.*/ +#if TIVA_SPI_USE_SSI0 + if (&SPID1 == spip) { + bool b; + b = udmaChannelAllocate(spip->dmarxnr); + osalDbgAssert(!b, "channel already allocated"); + b = udmaChannelAllocate(spip->dmatxnr); + osalDbgAssert(!b, "channel already allocated"); + + /* Enable SSI0 module.*/ + SYSCTL->RCGCSSI |= (1 << 0); + while (!(SYSCTL->PRSSI & (1 << 0))) + ; + + nvicEnableVector(TIVA_SSI0_NUMBER, TIVA_SPI_SSI0_IRQ_PRIORITY); + } +#endif +#if TIVA_SPI_USE_SSI1 + if (&SPID2 == spip) { + bool b; + b = udmaChannelAllocate(spip->dmarxnr); + osalDbgAssert(!b, "channel already allocated"); + b = udmaChannelAllocate(spip->dmatxnr); + osalDbgAssert(!b, "channel already allocated"); + + /* Enable SSI0 module.*/ + SYSCTL->RCGCSSI |= (1 << 1); + while (!(SYSCTL->PRSSI & (1 << 1))) + ; + + nvicEnableVector(TIVA_SSI1_NUMBER, TIVA_SPI_SSI1_IRQ_PRIORITY); + } +#endif +#if TIVASPI_USE_SSI2 + if (&SPID2 == spip) { + bool b; + b = udmaChannelAllocate(spip->dmarxnr); + osalDbgAssert(!b, "channel already allocated"); + b = udmaChannelAllocate(spip->dmatxnr); + osalDbgAssert(!b, "channel already allocated"); + + /* Enable SSI0 module.*/ + SYSCTL->RCGCSSI |= (1 << 2); + while (!(SYSCTL->PRSSI & (1 << 2))) + ; + + nvicEnableVector(TIVA_SSI2_NUMBER, TIVA_SPI_SSI2_IRQ_PRIORITY); + } +#endif +#if TIVA_SPI_USE_SSI3 + if (&SPID2 == spip) { + bool b; + b = udmaChannelAllocate(spip->dmarxnr); + osalDbgAssert(!b, "channel already allocated"); + b = udmaChannelAllocate(spip->dmatxnr); + osalDbgAssert(!b, "channel already allocated"); + + /* Enable SSI0 module.*/ + SYSCTL->RCGCSSI |= (1 << 3); + while (!(SYSCTL->PRSSI & (1 << 3))) + ; + + nvicEnableVector(TIVA_SSI3_NUMBER, TIVA_SPI_SSI3_IRQ_PRIORITY); + } +#endif + + UDMA->CHMAP[spip->dmarxnr / 8] |= (spip->rxchnmap << (spip->dmarxnr % 8)); + UDMA->CHMAP[spip->dmatxnr / 8] |= (spip->txchnmap << (spip->dmatxnr % 8)); + } + /* Set master operation mode.*/ + spip->ssi->CR1 = 0; + + /* Clock configuration - System Clock.*/ + spip->ssi->CC = 0; + + /* Clear pending interrupts.*/ + spip->ssi->ICR = TIVA_ICR_RTIC | TIVA_ICR_RORIC; + + /* Enable Receive Time-Out and Receive Overrun Interrupts.*/ + spip->ssi->IM = TIVA_IM_RTIM | TIVA_IM_RORIM; + + /* Configure the clock prescale divisor.*/ + spip->ssi->CPSR = spip->config->cpsr; + + /* Serial clock rate, phase/polarity, data size, fixed SPI frame format.*/ + spip->ssi->CR0 = (spip->config->cr0 & ~TIVA_CR0_FRF_MASK) | TIVA_CR0_FRF(0); + + /* Enable SSI.*/ + spip->ssi->CR1 |= TIVA_CR1_SSE; + + /* Enable RX and TX DMA channels.*/ + spip->ssi->DMACTL = (TIVA_DMACTL_TXDMAE | TIVA_DMACTL_RXDMAE); +} + +/** + * @brief Deactivates the SPI peripheral. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_stop(SPIDriver *spip) +{ + if (spip->state != SPI_STOP) { + spip->ssi->CR1 = 0; + spip->ssi->CR0 = 0; + spip->ssi->CPSR = 0; + + udmaChannelRelease(spip->dmarxnr); + udmaChannelRelease(spip->dmatxnr); + +#if TIVA_SPI_USE_SSI0 + if (&SPID1 == spip) { + nvicDisableVector(TIVA_SSI0_NUMBER); + } +#endif +#if TIVA_SPI_USE_SSI1 + if (&SPID2 == spip) { + nvicDisableVector(TIVA_SSI1_NUMBER); + } +#endif +#if TIVA_SPI_USE_SSI2 + if (&SPID3 == spip) { + nvicDisableVector(TIVA_SSI2_NUMBER); + } +#endif +#if TIVA_SPI_USE_SSI3 + if (&SPID4 == spip) { + nvicDisableVector(TIVA_SSI3_NUMBER); + } +#endif + } +} + +/** + * @brief Asserts the slave select signal and prepares for transfers. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_select(SPIDriver *spip) +{ + palClearPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Deasserts the slave select signal. + * @details The previously selected peripheral is unselected. + * + * @param[in] spip pointer to the @p SPIDriver object + * + * @notapi + */ +void spi_lld_unselect(SPIDriver *spip) +{ + palSetPad(spip->config->ssport, spip->config->sspad); +} + +/** + * @brief Ignores data on the SPI bus. + * @details This function transmits a series of idle words on the SPI bus and + * ignores the received data. This function can be invoked even + * when a slave select signal has not been yet asserted. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be ignored + * + * @notapi + */ +void spi_lld_ignore(SPIDriver *spip, size_t n) +{ + tiva_udma_table_entry_t *primary = udmaControlTable.primary; + + if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) { + /* Configure for 8-bit transfers.*/ + primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx; + primary[spip->dmatxnr].dstendp = &spip->ssi->DR; + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | + UDMA_CHCTL_ARBSIZE_4 | + UDMA_CHCTL_XFERSIZE(n) | + UDMA_CHCTL_XFERMODE_BASIC; + + primary[spip->dmarxnr].srcendp = &spip->ssi->DR; + primary[spip->dmarxnr].dstendp = &dummyrx; + primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | + UDMA_CHCTL_ARBSIZE_4 | + UDMA_CHCTL_XFERSIZE(n) | + UDMA_CHCTL_XFERMODE_BASIC; + } + else { + /* Configure for 16-bit transfers.*/ + primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx; + primary[spip->dmatxnr].dstendp = &spip->ssi->DR; + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | + UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | + UDMA_CHCTL_ARBSIZE_4 | + UDMA_CHCTL_XFERSIZE(n) | + UDMA_CHCTL_XFERMODE_BASIC; + + primary[spip->dmarxnr].srcendp = &spip->ssi->DR; + primary[spip->dmarxnr].dstendp = &dummyrx; + primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | + UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | + UDMA_CHCTL_ARBSIZE_4 | + UDMA_CHCTL_XFERSIZE(n) | + UDMA_CHCTL_XFERMODE_BASIC; + } + + dmaChannelSingleBurst(spip->dmatxnr); + dmaChannelPrimary(spip->dmatxnr); + dmaChannelPriorityDefault(spip->dmatxnr); + dmaChannelEnableRequest(spip->dmatxnr); + + dmaChannelSingleBurst(spip->dmarxnr); + dmaChannelPrimary(spip->dmarxnr); + dmaChannelPriorityDefault(spip->dmarxnr); + dmaChannelEnableRequest(spip->dmarxnr); + + /* Enable DMA channels, when the TX channel is enabled the transfer starts.*/ + dmaChannelEnable(spip->dmarxnr); + dmaChannelEnable(spip->dmatxnr); +} + +/** + * @brief Exchanges data on the SPI bus. + * @details This asynchronous function starts a simultaneous transmit/receive + * operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to be exchanged + * @param[in] txbuf the pointer to the transmit buffer + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_exchange(SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf) +{ + tiva_udma_table_entry_t *primary = udmaControlTable.primary; + + if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) { + /* Configure for 8-bit transfers.*/ + primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+n-1; + primary[spip->dmatxnr].dstendp = &spip->ssi->DR; + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_8 | + UDMA_CHCTL_ARBSIZE_4 | + UDMA_CHCTL_XFERSIZE(n) | + UDMA_CHCTL_XFERMODE_BASIC; + + primary[spip->dmarxnr].srcendp = &spip->ssi->DR; + primary[spip->dmarxnr].dstendp = rxbuf+n-1; + primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_8 | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | + UDMA_CHCTL_ARBSIZE_4 | + UDMA_CHCTL_XFERSIZE(n) | + UDMA_CHCTL_XFERMODE_BASIC; + } + else { + /* Configure for 16-bit transfers.*/ + primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+(n*2)-1; + primary[spip->dmatxnr].dstendp = &spip->ssi->DR; + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | + UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_16 | + UDMA_CHCTL_ARBSIZE_4 | + UDMA_CHCTL_XFERSIZE(n) | + UDMA_CHCTL_XFERMODE_BASIC; + + primary[spip->dmarxnr].srcendp = &spip->ssi->DR; + primary[spip->dmarxnr].dstendp = rxbuf+(n*2)-1; + primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_16 | + UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | + UDMA_CHCTL_ARBSIZE_4 | + UDMA_CHCTL_XFERSIZE(n) | + UDMA_CHCTL_XFERMODE_BASIC; + } + + dmaChannelSingleBurst(spip->dmatxnr); + dmaChannelPrimary(spip->dmatxnr); + dmaChannelPriorityDefault(spip->dmatxnr); + dmaChannelEnableRequest(spip->dmatxnr); + + dmaChannelSingleBurst(spip->dmarxnr); + dmaChannelPrimary(spip->dmarxnr); + dmaChannelPriorityDefault(spip->dmarxnr); + dmaChannelEnableRequest(spip->dmarxnr); + + /* Enable DMA channels, when the TX channel is enabled the transfer starts.*/ + dmaChannelEnable(spip->dmarxnr); + dmaChannelEnable(spip->dmatxnr); +} + +/** + * @brief Sends data over the SPI bus. + * @details This asynchronous function starts a transmit operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to send + * @param[in] txbuf the pointer to the transmit buffer + * + * @notapi + */ +void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) +{ + tiva_udma_table_entry_t *primary = udmaControlTable.primary; + + if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) { + /* Configure for 8-bit transfers.*/ + primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+n-1; + primary[spip->dmatxnr].dstendp = &spip->ssi->DR; + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_8 | + UDMA_CHCTL_ARBSIZE_4 | + UDMA_CHCTL_XFERSIZE(n) | + UDMA_CHCTL_XFERMODE_BASIC; + + primary[spip->dmarxnr].dstendp = &spip->ssi->DR; + primary[spip->dmarxnr].srcendp = &dummyrx; + primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | + UDMA_CHCTL_ARBSIZE_4 | + UDMA_CHCTL_XFERSIZE(n) | + UDMA_CHCTL_XFERMODE_BASIC; + } + else { + /* Configure for 16-bit transfers.*/ + primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+(n*2)-1; + primary[spip->dmatxnr].dstendp = &spip->ssi->DR; + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | + UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_16 | + UDMA_CHCTL_ARBSIZE_4 | + UDMA_CHCTL_XFERSIZE(n) | + UDMA_CHCTL_XFERMODE_BASIC; + + primary[spip->dmarxnr].dstendp = &spip->ssi->DR; + primary[spip->dmarxnr].srcendp = &dummyrx; + primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | + UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | + UDMA_CHCTL_ARBSIZE_4 | + UDMA_CHCTL_XFERSIZE(n) | + UDMA_CHCTL_XFERMODE_BASIC; + } + + dmaChannelSingleBurst(spip->dmatxnr); + dmaChannelPrimary(spip->dmatxnr); + dmaChannelPriorityDefault(spip->dmatxnr); + dmaChannelEnableRequest(spip->dmatxnr); + + dmaChannelSingleBurst(spip->dmarxnr); + dmaChannelPrimary(spip->dmarxnr); + dmaChannelPriorityDefault(spip->dmarxnr); + dmaChannelEnableRequest(spip->dmarxnr); + + /* Enable DMA channels, when the TX channel is enabled the transfer starts.*/ + dmaChannelEnable(spip->dmarxnr); + dmaChannelEnable(spip->dmatxnr); +} + +/** + * @brief Receives data from the SPI bus. + * @details This asynchronous function starts a receive operation. + * @post At the end of the operation the configured callback is invoked. + * @note The buffers are organized as uint8_t arrays for data sizes below or + * equal to 8 bits else it is organized as uint16_t arrays. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] n number of words to receive + * @param[out] rxbuf the pointer to the receive buffer + * + * @notapi + */ +void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) +{ + tiva_udma_table_entry_t *primary = udmaControlTable.primary; + + if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) { + /* Configure for 8-bit transfers.*/ + primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx; + primary[spip->dmatxnr].dstendp = &spip->ssi->DR; + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | + UDMA_CHCTL_ARBSIZE_4 | + UDMA_CHCTL_XFERSIZE(n) | + UDMA_CHCTL_XFERMODE_BASIC; + + primary[spip->dmarxnr].srcendp = &spip->ssi->DR; + primary[spip->dmarxnr].dstendp = rxbuf+n-1; + primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_8 | + UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | + UDMA_CHCTL_ARBSIZE_4 | + UDMA_CHCTL_XFERSIZE(n) | + UDMA_CHCTL_XFERMODE_BASIC; + } + else { + /* Configure for 16-bit transfers.*/ + primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx; + primary[spip->dmatxnr].dstendp = &spip->ssi->DR; + primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | + UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | + UDMA_CHCTL_ARBSIZE_4 | + UDMA_CHCTL_XFERSIZE(n) | + UDMA_CHCTL_XFERMODE_BASIC; + + primary[spip->dmarxnr].srcendp = &spip->ssi->DR; + primary[spip->dmarxnr].dstendp = rxbuf+(n*2)-1; + primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_16 | + UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | + UDMA_CHCTL_ARBSIZE_4 | + UDMA_CHCTL_XFERSIZE(n) | + UDMA_CHCTL_XFERMODE_BASIC; + } + + dmaChannelSingleBurst(spip->dmatxnr); + dmaChannelPrimary(spip->dmatxnr); + dmaChannelPriorityDefault(spip->dmatxnr); + dmaChannelEnableRequest(spip->dmatxnr); + + dmaChannelSingleBurst(spip->dmarxnr); + dmaChannelPrimary(spip->dmarxnr); + dmaChannelPriorityDefault(spip->dmarxnr); + dmaChannelEnableRequest(spip->dmarxnr); + + /* Enable DMA channels, when the TX channel is enabled the transfer starts.*/ + dmaChannelEnable(spip->dmarxnr); + dmaChannelEnable(spip->dmatxnr); +} + +/** + * @brief Exchanges one frame using a polled wait. + * @details This synchronous function exchanges one frame using a polled + * synchronization method. This function is useful when exchanging + * small amount of data on high speed channels, usually in this + * situation is much more efficient just wait for completion using + * polling than suspending the thread waiting for an interrupt. + * + * @param[in] spip pointer to the @p SPIDriver object + * @param[in] frame the data frame to send over the SPI bus + * @return The received data frame from the SPI bus. + */ +uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) +{ + spip->ssi->DR = (uint32_t)frame; + while ((spip->ssi->SR & TIVA_SR_RNE) == 0) + ; + return (uint16_t)spip->ssi->DR; +} + +#endif /* HAL_USE_SPI */ + +/** @} */ diff --git a/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h new file mode 100644 index 0000000..2adc9ed --- /dev/null +++ b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h @@ -0,0 +1,388 @@ +/* + Copyright (C) 2014..2016 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file TIVA/LLD/spi_lld.h + * @brief TM4C123x/TM4C129x SPI subsystem low level driver. + * + * @addtogroup SPI + * @{ + */ + +#ifndef HAL_SPI_LLD_H +#define HAL_SPI_LLD_H + +#if HAL_USE_SPI || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name Control 0 + * @{ + */ +#define TIVA_CR0_DSS_MASK 0x0F +#define TIVA_CR0_DSS(n) ((n-1) << 0) + +#define TIVA_CR0_FRF_MASK (3 << 4) +#define TIVA_CR0_FRF(n) ((n) << 4) + +#define TIVA_CR0_SPO (1 << 6) +#define TIVA_CR0_SPH (1 << 7) + +#define TIVA_CR0_SRC_MASK (0xFF << 8) +#define TIVA_CR0_SRC(n) ((n) << 8) +/** @} */ + +/** + * @name Control 1 + * @{ + */ +#define TIVA_CR1_LBM (1 << 0) +#define TIVA_CR1_SSE (1 << 1) +#define TIVA_CR1_MS (1 << 2) +#define TIVA_CR1_SOD (1 << 3) +#define TIVA_CR1_EOT (1 << 4) +/** @} */ + +/** + * @name Status + * @{ + */ +#define TIVA_SR_TFE (1 << 0) +#define TIVA_SR_TNF (1 << 1) +#define TIVA_SR_RNE (1 << 2) +#define TIVA_SR_RFF (1 << 3) +#define TIVA_SR_BSY (1 << 4) +/** @} */ + +/** + * @name Interrupt Mask + * @{ + */ +#define TIVA_IM_RORIM (1 << 0) +#define TIVA_IM_RTIM (1 << 1) +#define TIVA_IM_RXIM (1 << 2) +#define TIVA_IM_TXIM (1 << 3) +/** @} */ + +/** + * @name Interrupt Status + * @{ + */ +#define TIVA_IS_RORIS (1 << 0) +#define TIVA_IS_RTIS (1 << 1) +#define TIVA_IS_RXIS (1 << 2) +#define TIVA_IS_TXIS (1 << 3) +/** @} */ + +/** + * @name Masked Interrupt Status + * @{ + */ +#define TIVA_MIS_RORMIS (1 << 0) +#define TIVA_MIS_RTMIS (1 << 1) +#define TIVA_MIS_RXMIS (1 << 2) +#define TIVA_MIS_TXMIS (1 << 3) +/** @} */ + +/** + * @name Interrupt Clear + * @{ + */ +#define TIVA_ICR_RORIC (1 << 0) +#define TIVA_ICR_RTIC (1 << 1) +/** @} */ + +/** + * @name DMA Control + * @{ + */ +#define TIVA_DMACTL_RXDMAE (1 << 0) +#define TIVA_DMACTL_TXDMAE (1 << 1) +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ + +/** + * @brief SSI0 driver enable switch. + * @details If set to @p TRUE the support for SSI0 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_SPI_USE_SSI0) || defined(__DOXYGEN__) +#define TIVA_SPI_USE_SSI0 FALSE +#endif + +/** + * @brief SSI1 driver enable switch. + * @details If set to @p TRUE the support for SSI1 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_SPI_USE_SSI1) || defined(__DOXYGEN__) +#define TIVA_SPI_USE_SSI1 FALSE +#endif + +/** + * @brief SSI2 driver enable switch. + * @details If set to @p TRUE the support for SSI2 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_SPI_USE_SSI2) || defined(__DOXYGEN__) +#define TIVA_SPI_USE_SSI2 FALSE +#endif + +/** + * @brief SSI3 driver enable switch. + * @details If set to @p TRUE the support for SSI3 is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_SPI_USE_SSI3) || defined(__DOXYGEN__) +#define TIVA_SPI_USE_SSI3 FALSE +#endif + +/** + * @brief SPID1 interrupt priority level setting. + */ +#if !defined(TIVA_SPI_SSI0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_SPI_SSI0_IRQ_PRIORITY 5 +#endif + +/** + * @brief SPID2 interrupt priority level setting. + */ +#if !defined(TIVA_SPI_SSI1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_SPI_SSI1_IRQ_PRIORITY 5 +#endif + +/** + * @brief SPID3 interrupt priority level setting. + */ +#if !defined(TIVA_SPI_SSI2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_SPI_SSI2_IRQ_PRIORITY 5 +#endif + +/** + * @brief SPID4 interrupt priority level setting. + */ +#if !defined(TIVA_SPI_SSI3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_SPI_SSI3_IRQ_PRIORITY 5 +#endif + +/** + * @brief SPI error hook. + */ +#if !defined(TIVA_SPI_SSI_ERROR_HOOK) || defined(__DOXYGEN__) +#define TIVA_SPI_SSI_ERROR_HOOK(spip) osalSysHalt("SSI failure") +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if TIVA_SPI_USE_SSI0 && !TIVA_HAS_SSI0 +#error "SSI0 not present in the selected device" +#endif + +#if TIVA_SPI_USE_SSI1 && !TIVA_HAS_SSI1 +#error "SSI1 not present in the selected device" +#endif + +#if TIVA_SPI_USE_SSI2 && !TIVA_HAS_SSI2 +#error "SSI2 not present in the selected device" +#endif + +#if TIVA_SPI_USE_SSI3 && !TIVA_HAS_SSI03 +#error "SSI3 not present in the selected device" +#endif + +#if !TIVA_SPI_USE_SSI0 && !TIVA_SPI_USE_SSI1 && !TIVA_SPI_USE_SSI2 && \ + !TIVA_SPI_USE_SSI3 +#error "SPI driver activated but no SSI peripheral assigned" +#endif + +#if TIVA_SPI_USE_SSI0 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SPI_SSI0_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to SSI0" +#endif + +#if TIVA_SPI_USE_SSI1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SPI_SSI1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to SSI1" +#endif + +#if TIVA_SPI_USE_SSI2 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SPI_SSI2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to SSI2" +#endif + +#if TM4C123x_SPI_USE_SSI3 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SPI_SSI3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to SSI3" +#endif + +#if !defined(TIVA_UDMA_REQUIRED) +#define TIVA_UDMA_REQUIRED +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an SPI driver. + */ +typedef struct SPIDriver SPIDriver; + +/** + * @brief SPI notification callback type. + * + * @param[in] spip pointer to the @p SPIDriver object triggering the + * callback + */ +typedef void (*spicallback_t)(SPIDriver *spip); + +/** + * @brief Driver configuration structure. + */ +typedef struct { + /** + * @brief Operation complete callback or @p NULL. + */ + spicallback_t end_cb; + /* End of the mandatory fields.*/ + /** + * @brief The chip select line port. + */ + ioportid_t ssport; + /** + * @brief The chip select line pad number. + */ + uint16_t sspad; + /** + * @brief SSI CR0 initialization data. + */ + uint16_t cr0; + /** + * @brief SSI CPSR initialization data. + */ + uint32_t cpsr; +} SPIConfig; + +/** + * @brief Structure representing a SPI driver. + */ +struct SPIDriver { + /** + * @brief Driver state. + */ + spistate_t state; + /** + * @brief Current configuration data. + */ + const SPIConfig *config; +#if SPI_USE_WAIT || defined(__DOXYGEN__) + /** + * @brief Waiting thread. + */ + thread_reference_t thread; +#endif /* SPI_USE_WAIT */ +#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) + /** + * @brief Mutex protecting the bus. + */ + mutex_t mutex; +#endif /* SPI_USE_MUTUAL_EXCLUSION */ +#if defined(SPI_DRIVER_EXT_FIELDS) + SPI_DRIVER_EXT_FIELDS +#endif + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the SSI registers block. + */ + SSI_TypeDef *ssi; + /** + * @brief Receive DMA channel number. + */ + uint8_t dmarxnr; + /** + * @brief Transmit DMA channel number. + */ + uint8_t dmatxnr; + /** + * @brief Receive DMA channel map. + */ + uint8_t rxchnmap; + /** + * @brief Transmit DMA channel map. + */ + uint8_t txchnmap; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if TIVA_SPI_USE_SSI0 && !defined(__DOXYGEN__) +extern SPIDriver SPID1; +#endif + +#if TIVA_SPI_USE_SSI1 && !defined(__DOXYGEN__) +extern SPIDriver SPID2; +#endif + +#if TIVA_SPI_USE_SSI2 && !defined(__DOXYGEN__) +extern SPIDriver SPID3; +#endif + +#if TIVA_SPI_USE_SSI3 && !defined(__DOXYGEN__) +extern SPIDriver SPID4; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void spi_lld_init(void); + void spi_lld_start(SPIDriver *spip); + void spi_lld_stop(SPIDriver *spip); + void spi_lld_select(SPIDriver *spip); + void spi_lld_unselect(SPIDriver *spip); + void spi_lld_ignore(SPIDriver *spip, size_t n); + void spi_lld_exchange(SPIDriver *spip, size_t n, + const void *txbuf, void *rxbuf); + void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); + void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); + uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SPI */ + +#endif /* HAL_SPI_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c b/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c new file mode 100644 index 0000000..89d29da --- /dev/null +++ b/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c @@ -0,0 +1,664 @@ +/* + Copyright (C) 2014..2016 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file TIVA/LLD/serial_lld.c + * @brief Tiva low level serial driver code. + * + * @addtogroup SERIAL + * @{ + */ + +#include "hal.h" + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/** + * @brief UART0 serial driver identifier. + */ +#if TIVA_SERIAL_USE_UART0 || defined(__DOXYGEN__) +SerialDriver SD1; +#endif + +/** + * @brief UART1 serial driver identifier. + */ +#if TIVA_SERIAL_USE_UART1 || defined(__DOXYGEN__) +SerialDriver SD2; +#endif + +/** + * @brief UART2 serial driver identifier. + */ +#if TIVA_SERIAL_USE_UART2 || defined(__DOXYGEN__) +SerialDriver SD3; +#endif + +/** + * @brief UART3 serial driver identifier. + */ +#if TIVA_SERIAL_USE_UART3 || defined(__DOXYGEN__) +SerialDriver SD4; +#endif + +/** + * @brief UART4 serial driver identifier. + */ +#if TIVA_SERIAL_USE_UART4 || defined(__DOXYGEN__) +SerialDriver SD5; +#endif + +/** + * @brief UART5 serial driver identifier. + */ +#if TIVA_SERIAL_USE_UART5 || defined(__DOXYGEN__) +SerialDriver SD6; +#endif + +/** + * @brief UART6 serial driver identifier. + */ +#if TIVA_SERIAL_USE_UART6 || defined(__DOXYGEN__) +SerialDriver SD7; +#endif + +/** + * @brief UART7 serial driver identifier. + */ +#if TIVA_SERIAL_USE_UART7 || defined(__DOXYGEN__) +SerialDriver SD8; +#endif + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/** + * @brief Driver default configuration. + */ +static const SerialConfig sd_default_config = +{ + SERIAL_DEFAULT_BITRATE, + TIVA_LCRH_FEN | TIVA_LCRH_WLEN_8, + TIVA_IFLS_TXIFLSEL_1_8_F | TIVA_IFLS_RXIFLSEL_1_8_E +}; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief UART initialization. + * + * @param[in] sdp communication channel associated to the UART + * @param[in] config the architecture-dependent serial driver configuration + */ +static void uart_init(SerialDriver *sdp, const SerialConfig *config) +{ + UART_TypeDef *u = sdp->uart; + uint32_t div; /* baud rate divisor */ + + /* disable the UART before any of the control registers are reprogrammed */ + u->CTL &= ~TIVA_CTL_UARTEN; + div = (((TIVA_SYSCLK * 8) / config->sc_speed) + 1) / 2; + u->IBRD = div / 64; /* integer portion of the baud rate divisor */ + u->FBRD = div % 64; /* fractional portion of the baud rate divisor */ + u->LCRH = config->sc_lcrh; /* set data format */ + u->IFLS = config->sc_ifls; + u->CTL |= TIVA_CTL_TXE | TIVA_CTL_RXE | TIVA_CTL_UARTEN; + u->IM |= TIVA_IM_RXIM | TIVA_IM_TXIM | TIVA_IM_RTIM; /* interrupts enable */ +} + +/** + * @brief UART de-initialization. + * + * @param[in] u pointer to an UART I/O block + */ +static void uart_deinit(UART_TypeDef *u) +{ + u->CTL &= ~TIVA_CTL_UARTEN; +} + +/** + * @brief Error handling routine. + * + * @param[in] sdp communication channel associated to the UART + * @param[in] err UART LSR register value + */ +static void set_error(SerialDriver *sdp, uint16_t err) +{ + eventflags_t sts = 0; + + if (err & TIVA_MIS_FEMIS) + sts |= SD_FRAMING_ERROR; + if (err & TIVA_MIS_PEMIS) + sts |= SD_PARITY_ERROR; + if (err & TIVA_MIS_BEMIS) + sts |= SD_BREAK_DETECTED; + if (err & TIVA_MIS_OEMIS) + sts |= SD_OVERRUN_ERROR; + osalSysLockFromISR(); + chnAddFlagsI(sdp, sts); + osalSysUnlockFromISR(); +} + +/** + * @brief Common IRQ handler. + * @note Tries hard to clear all the pending interrupt sources, we don't + * want to go through the whole ISR and have another interrupt soon + * after. + * + * @param[in] u pointer to an UART I/O block + * @param[in] sdp communication channel associated to the UART + */ +static void serial_serve_interrupt(SerialDriver *sdp) +{ + UART_TypeDef *u = sdp->uart; + uint16_t mis = u->MIS; + + u->ICR = mis; /* clear interrupts */ + + if (mis & (TIVA_MIS_FEMIS | TIVA_MIS_PEMIS | TIVA_MIS_BEMIS | TIVA_MIS_OEMIS)) { + set_error(sdp, mis); + } + + if ((mis & TIVA_MIS_RXMIS) || (mis & TIVA_MIS_RTMIS)) { + osalSysLockFromISR(); + if (iqIsEmptyI(&sdp->iqueue)) { + chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE); + } + osalSysUnlockFromISR(); + while ((u->FR & TIVA_FR_RXFE) == 0) { + osalSysLockFromISR(); + if (iqPutI(&sdp->iqueue, u->DR) < Q_OK) { + chnAddFlagsI(sdp, SD_OVERRUN_ERROR); + } + osalSysUnlockFromISR(); + } + } + + if (mis & TIVA_MIS_TXMIS) { + while ((u->FR & TIVA_FR_TXFF) == 0) { + msg_t b; + osalSysLockFromISR(); + b = oqGetI(&sdp->oqueue); + osalSysUnlockFromISR(); + if (b < Q_OK) { + u->IM &= ~TIVA_IM_TXIM; + osalSysLockFromISR(); + chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); + osalSysUnlockFromISR(); + break; + } + u->DR = b; + } + } +} + +/** + * @brief + */ +static void fifo_load(SerialDriver *sdp) +{ + UART_TypeDef *u = sdp->uart; + + while ((u->FR & TIVA_FR_TXFF) == 0) { + msg_t b = oqGetI(&sdp->oqueue); + if (b < Q_OK) { + chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); + return; + } + u->DR = b; + } + u->IM |= TIVA_IM_TXIM; /* transmit interrupt enable */ +} + +/** + * @brief Driver SD1 output notification. + */ +#if TIVA_SERIAL_USE_UART0 || defined(__DOXYGEN__) +static void notify1(io_queue_t *qp) +{ + (void)qp; + fifo_load(&SD1); +} +#endif + +/** + * @brief Driver SD2 output notification. + */ +#if TIVA_SERIAL_USE_UART1 || defined(__DOXYGEN__) +static void notify2(io_queue_t *qp) +{ + (void)qp; + fifo_load(&SD2); +} +#endif + +/** + * @brief Driver SD3 output notification. + */ +#if TIVA_SERIAL_USE_UART2 || defined(__DOXYGEN__) +static void notify3(io_queue_t *qp) +{ + (void)qp; + fifo_load(&SD3); +} +#endif + +/** + * @brief Driver SD4 output notification. + */ +#if TIVA_SERIAL_USE_UART3 || defined(__DOXYGEN__) +static void notify4(io_queue_t *qp) +{ + (void)qp; + fifo_load(&SD4); +} +#endif + +/** + * @brief Driver SD5 output notification. + */ +#if TIVA_SERIAL_USE_UART4 || defined(__DOXYGEN__) +static void notify5(io_queue_t *qp) +{ + (void)qp; + fifo_load(&SD5); +} +#endif + +/** + * @brief Driver SD6 output notification. + */ +#if TIVA_SERIAL_USE_UART5 || defined(__DOXYGEN__) +static void notify6(io_queue_t *qp) +{ + (void)qp; + fifo_load(&SD6); +} +#endif + +/** + * @brief Driver SD7 output notification. + */ +#if TIVA_SERIAL_USE_UART6 || defined(__DOXYGEN__) +static void notify7(io_queue_t *qp) +{ + (void)qp; + fifo_load(&SD7); +} +#endif + +/** + * @brief Driver SD8 output notification. + */ +#if TIVA_SERIAL_USE_UART7 || defined(__DOXYGEN__) +static void notify8(io_queue_t *qp) +{ + (void)qp; + fifo_load(&SD8); +} +#endif + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/** + * @brief UART0 IRQ handler. + */ +#if TIVA_SERIAL_USE_UART0 || defined(__DOXYGEN__) +#if !defined(TIVA_UART0_HANDLER) +#error "TIVA_UART0_HANDLER not defined" +#endif +CH_IRQ_HANDLER(TIVA_UART0_HANDLER) +{ + CH_IRQ_PROLOGUE(); + + serial_serve_interrupt(&SD1); + + CH_IRQ_EPILOGUE(); +} +#endif + +/** + * @brief UART1 IRQ handler. + */ +#if TIVA_SERIAL_USE_UART1 || defined(__DOXYGEN__) +CH_IRQ_HANDLER(TIVA_UART1_HANDLER) +{ + CH_IRQ_PROLOGUE(); + + serial_serve_interrupt(&SD2); + + CH_IRQ_EPILOGUE(); +} +#endif + +/** + * @brief UART2 IRQ handler. + */ +#if TIVA_SERIAL_USE_UART2 || defined(__DOXYGEN__) +CH_IRQ_HANDLER(TIVA_UART2_HANDLER) +{ + CH_IRQ_PROLOGUE(); + + serial_serve_interrupt(&SD3); + + CH_IRQ_EPILOGUE(); +} +#endif + +/** + * @brief UART3 IRQ handler. + */ +#if TIVA_SERIAL_USE_UART3 || defined(__DOXYGEN__) +CH_IRQ_HANDLER(TIVA_UART3_HANDLER) +{ + CH_IRQ_PROLOGUE(); + + serial_serve_interrupt(&SD4); + + CH_IRQ_EPILOGUE(); +} +#endif + +/** + * @brief UART4 IRQ handler. + */ +#if TIVA_SERIAL_USE_UART4 || defined(__DOXYGEN__) +CH_IRQ_HANDLER(TIVA_UART4_HANDLER) +{ + CH_IRQ_PROLOGUE(); + + serial_serve_interrupt(&SD5); + + CH_IRQ_EPILOGUE(); +} +#endif + +/** + * @brief UART5 IRQ handler. + */ +#if TIVA_SERIAL_USE_UART5 || defined(__DOXYGEN__) +CH_IRQ_HANDLER(TIVA_UART5_HANDLER) +{ + CH_IRQ_PROLOGUE(); + + serial_serve_interrupt(&SD6); + + CH_IRQ_EPILOGUE(); +} +#endif + +/** + * @brief UART6 IRQ handler. + */ +#if TIVA_SERIAL_USE_UART6 || defined(__DOXYGEN__) +CH_IRQ_HANDLER(TIVA_UART6_HANDLER) +{ + CH_IRQ_PROLOGUE(); + + serial_serve_interrupt(&SD7); + + CH_IRQ_EPILOGUE(); +} +#endif + +/** + * @brief UART7 IRQ handler. + */ +#if TIVA_SERIAL_USE_UART7 || defined(__DOXYGEN__) +CH_IRQ_HANDLER(TIVA_UART7_HANDLER) +{ + CH_IRQ_PROLOGUE(); + + serial_serve_interrupt(&SD8); + + CH_IRQ_EPILOGUE(); +} +#endif + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level serial driver initialization. + */ +void sd_lld_init(void) +{ +#if TIVA_SERIAL_USE_UART0 + sdObjectInit(&SD1, NULL, notify1); + SD1.uart = UART0; +#endif + +#if TIVA_SERIAL_USE_UART1 + sdObjectInit(&SD2, NULL, notify2); + SD2.uart = UART1; +#endif + +#if TIVA_SERIAL_USE_UART2 + sdObjectInit(&SD3, NULL, notify3); + SD3.uart = UART2; +#endif + +#if TIVA_SERIAL_USE_UART3 + sdObjectInit(&SD4, NULL, notify4); + SD4.uart = UART3; +#endif + +#if TIVA_SERIAL_USE_UART4 + sdObjectInit(&SD5, NULL, notify5); + SD5.uart = UART4; +#endif + +#if TIVA_SERIAL_USE_UART5 + sdObjectInit(&SD6, NULL, notify6); + SD6.uart = UART5; +#endif + +#if TIVA_SERIAL_USE_UART6 + sdObjectInit(&SD7, NULL, notify7); + SD7.uart = UART6; +#endif + +#if TIVA_SERIAL_USE_UART7 + sdObjectInit(&SD8, NULL, notify8); + SD8.uart = UART7; +#endif +} + +/** + * @brief Low level serial driver configuration and (re)start. + * + * @param[in] sdp pointer to a @p SerialDriver object + * @param[in] config the architecture-dependent serial driver configuration. + * If this parameter is set to @p NULL then a default + * configuration is used. + */ +void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) +{ + if (config == NULL) + config = &sd_default_config; + + if (sdp->state == SD_STOP) { +#if TIVA_SERIAL_USE_UART0 + if (&SD1 == sdp) { + SYSCTL->RCGCUART |= (1 << 0); + + while (!(SYSCTL->PRUART & (1 << 0))) + ; + + nvicEnableVector(TIVA_UART0_NUMBER, TIVA_SERIAL_UART0_PRIORITY); + } +#endif +#if TIVA_SERIAL_USE_UART1 + if (&SD2 == sdp) { + SYSCTL->RCGCUART |= (1 << 1); + + while (!(SYSCTL->PRUART & (1 << 1))) + ; + + nvicEnableVector(TIVA_UART1_NUMBER, TIVA_SERIAL_UART1_PRIORITY); + } +#endif +#if TIVA_SERIAL_USE_UART2 + if (&SD3 == sdp) { + SYSCTL->RCGCUART |= (1 << 2); + + while (!(SYSCTL->PRUART & (1 << 2))) + ; + + nvicEnableVector(TIVA_UART2_NUMBER, TIVA_SERIAL_UART2_PRIORITY); + } +#endif +#if TIVA_SERIAL_USE_UART3 + if (&SD4 == sdp) { + SYSCTL->RCGCUART |= (1 << 3); + + while (!(SYSCTL->PRUART & (1 << 3))) + ; + + nvicEnableVector(TIVA_UART3_NUMBER, TIVA_SERIAL_UART3_PRIORITY); + } +#endif +#if TIVA_SERIAL_USE_UART4 + if (&SD5 == sdp) { + SYSCTL->RCGCUART |= (1 << 4); + + while (!(SYSCTL->PRUART & (1 << 4))) + ; + + nvicEnableVector(TIVA_UART4_NUMBER, TIVA_SERIAL_UART4_PRIORITY); + } +#endif +#if TIVA_SERIAL_USE_UART5 + if (&SD6 == sdp) { + SYSCTL->RCGCUART |= (1 << 5); + + while (!(SYSCTL->PRUART & (1 << 5))) + ; + + nvicEnableVector(TIVA_UART5_NUMBER, TIVA_SERIAL_UART5_PRIORITY); + } +#endif +#if TIVA_SERIAL_USE_UART6 + if (&SD7 == sdp) { + SYSCTL->RCGCUART |= (1 << 6); + + while (!(SYSCTL->PRUART & (1 << 6))) + ; + + nvicEnableVector(TIVA_UART6_NUMBER, TIVA_SERIAL_UART6_PRIORITY); + } +#endif +#if TIVA_SERIAL_USE_UART7 + if (&SD8 == sdp) { + SYSCTL->RCGCUART |= (1 << 7); + + while (!(SYSCTL->PRUART & (1 << 7))) + ; + + nvicEnableVector(TIVA_UART7_NUMBER, TIVA_SERIAL_UART7_PRIORITY); + } +#endif + } + uart_init(sdp, config); +} + +/** + * @brief Low level serial driver stop. + * @details De-initializes the UART, stops the associated clock, resets the + * interrupt vector. + * + * @param[in] sdp pointer to a @p SerialDriver object + */ +void sd_lld_stop(SerialDriver *sdp) +{ + if (sdp->state == SD_READY) { + uart_deinit(sdp->uart); +#if TIVA_SERIAL_USE_UART0 + if (&SD1 == sdp) { + SYSCTL->RCGCUART &= ~(1 << 0); /* disable UART0 module */ + nvicDisableVector(TIVA_UART0_NUMBER); + return; + } +#endif +#if TIVA_SERIAL_USE_UART1 + if (&SD2 == sdp) { + SYSCTL->RCGCUART &= ~(1 << 1); /* disable UART1 module */ + nvicDisableVector(TIVA_UART1_NUMBER); + return; + } +#endif +#if TIVA_SERIAL_USE_UART2 + if (&SD3 == sdp) { + SYSCTL->RCGCUART &= ~(1 << 2); /* disable UART2 module */ + nvicDisableVector(TIVA_UART2_NUMBER); + return; + } +#endif +#if TIVA_SERIAL_USE_UART3 + if (&SD4 == sdp) { + SYSCTL->RCGCUART &= ~(1 << 3); /* disable UART3 module */ + nvicDisableVector(TIVA_UART3_NUMBER); + return; + } +#endif +#if TIVA_SERIAL_USE_UART4 + if (&SD5 == sdp) { + SYSCTL->RCGCUART &= ~(1 << 4); /* disable UART4 module */ + nvicDisableVector(TIVA_UART4_NUMBER); + return; + } +#endif +#if TIVA_SERIAL_USE_UART5 + if (&SD6 == sdp) { + SYSCTL->RCGCUART &= ~(1 << 5); /* disable UART5 module */ + nvicDisableVector(TIVA_UART5_NUMBER); + return; + } +#endif +#if TIVA_SERIAL_USE_UART6 + if (&SD7 == sdp) { + SYSCTL->RCGCUART &= ~(1 << 6); /* disable UART6 module */ + nvicDisableVector(TIVA_UART6_NUMBER); + return; + } +#endif +#if TIVA_SERIAL_USE_UART7 + if (&SD8 == sdp) { + SYSCTL->RCGCUART &= ~(1 << 7); /* disable UART7 module */ + nvicDisableVector(TIVA_UART7_NUMBER); + return; + } +#endif + } +} + +#endif /* CH_HAL_USE_SERIAL */ + +/** @} */ diff --git a/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.h b/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.h new file mode 100644 index 0000000..203ef6a --- /dev/null +++ b/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.h @@ -0,0 +1,482 @@ +/* + Copyright (C) 2014..2016 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/** + * @file TIVA/LLD/serial_lld.h + * @brief Tiva low level serial driver header. + * + * @addtogroup SERIAL + * @{ + */ + +#ifndef HAL_SERIAL_LLD_H +#define HAL_SERIAL_LLD_H + +#if HAL_USE_SERIAL || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name FR register bits definitions + * @{ + */ + +#define TIVA_FR_CTS (1 << 0) + +#define TIVA_FR_BUSY (1 << 3) + +#define TIVA_FR_RXFE (1 << 4) + +#define TIVA_FR_TXFF (1 << 5) + +#define TIVA_FR_RXFF (1 << 6) + +#define TIVA_FR_TXFE (1 << 7) + +/** + * @} + */ + +/** + * @name LCRH register bits definitions + * @{ + */ + +#define TIVA_LCRH_BRK (1 << 0) + +#define TIVA_LCRH_PEN (1 << 1) + +#define TIVA_LCRH_EPS (1 << 2) + +#define TIVA_LCRH_STP2 (1 << 3) + +#define TIVA_LCRH_FEN (1 << 4) + +#define TIVA_LCRH_WLEN_MASK (3 << 5) +#define TIVA_LCRH_WLEN_5 (0 << 5) +#define TIVA_LCRH_WLEN_6 (1 << 5) +#define TIVA_LCRH_WLEN_7 (2 << 5) +#define TIVA_LCRH_WLEN_8 (3 << 5) + +#define TIVA_LCRH_SPS (1 << 7) + +/** + * @} + */ + +/** + * @name CTL register bits definitions + * @{ + */ + +#define TIVA_CTL_UARTEN (1 << 0) + +#define TIVA_CTL_SIREN (1 << 1) + +#define TIVA_CTL_SIRLP (1 << 2) + +#define TIVA_CTL_SMART (1 << 3) + +#define TIVA_CTL_EOT (1 << 4) + +#define TIVA_CTL_HSE (1 << 5) + +#define TIVA_CTL_LBE (1 << 7) + +#define TIVA_CTL_TXE (1 << 8) + +#define TIVA_CTL_RXE (1 << 9) + +#define TIVA_CTL_RTS (1 << 11) + +#define TIVA_CTL_RTSEN (1 << 14) + +#define TIVA_CTL_CTSEN (1 << 15) + +/** + * @} + */ + +/** + * @name IFLS register bits definitions + * @{ + */ + +#define TIVA_IFLS_TXIFLSEL_MASK (7 << 0) +#define TIVA_IFLS_TXIFLSEL_1_8_F (0 << 0) +#define TIVA_IFLS_TXIFLSEL_1_4_F (1 << 0) +#define TIVA_IFLS_TXIFLSEL_1_2_F (2 << 0) +#define TIVA_IFLS_TXIFLSEL_3_4_F (3 << 0) +#define TIVA_IFLS_TXIFLSEL_7_8_F (4 << 0) + +#define TIVA_IFLS_RXIFLSEL_MASK (7 << 3) +#define TIVA_IFLS_RXIFLSEL_7_8_E (0 << 3) +#define TIVA_IFLS_RXIFLSEL_3_4_E (1 << 3) +#define TIVA_IFLS_RXIFLSEL_1_2_E (2 << 3) +#define TIVA_IFLS_RXIFLSEL_1_4_E (3 << 3) +#define TIVA_IFLS_RXIFLSEL_1_8_E (4 << 3) + +/** + * @} + */ + +/** + * @name MIS register bits definitions + * @{ + */ + +#define TIVA_MIS_CTSMIS (1 << 1) + +#define TIVA_MIS_RXMIS (1 << 4) + +#define TIVA_MIS_TXMIS (1 << 5) + +#define TIVA_MIS_RTMIS (1 << 6) + +#define TIVA_MIS_FEMIS (1 << 7) + +#define TIVA_MIS_PEMIS (1 << 8) + +#define TIVA_MIS_BEMIS (1 << 9) + +#define TIVA_MIS_OEMIS (1 << 10) + +#define TIVA_MIS_9BITMIS (1 << 12) + +/** + * @} + */ + +/** + * @name IM register bits definitions + * @{ + */ + +#define TIVA_IM_CTSIM (1 << 1) + +#define TIVA_IM_RXIM (1 << 4) + +#define TIVA_IM_TXIM (1 << 5) + +#define TIVA_IM_RTIM (1 << 6) + +#define TIVA_IM_FEIM (1 << 7) + +#define TIVA_IM_PEIM (1 << 8) + +#define TIVA_IM_BEIM (1 << 9) + +#define TIVA_IM_OEIM (1 << 10) + +#define TIVA_IM_9BITIM (1 << 12) + +/** + * @} + */ +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ + +/** + * @brief UART0 driver enable switch. + * @details If set to @p TRUE the support for UART0 is included. + * @note The default is @p TRUE. + */ +#if !defined(TIVA_SERIAL_USE_UART0) || defined(__DOXYGEN__) +#define TIVA_SERIAL_USE_UART0 FALSE +#endif + +/** + * @brief UART1 driver enable switch. + * @details If set to @p TRUE the support for UART1 is included. + * @note The default is @p FALSE . + */ +#if !defined(TIVA_SERIAL_USE_UART1) || defined(__DOXYGEN__) +#define TIVA_SERIAL_USE_UART1 FALSE +#endif + +/** + * @brief UART2 driver enable switch. + * @details If set to @p TRUE the support for UART2 is included. + * @note The default is @p FALSE . + */ +#if !defined(TIVA_SERIAL_USE_UART2) || defined(__DOXYGEN__) +#define TIVA_SERIAL_USE_UART2 FALSE +#endif + +/** + * @brief UART3 driver enable switch. + * @details If set to @p TRUE the support for UART3 is included. + * @note The default is @p FALSE . + */ +#if !defined(TIVA_SERIAL_USE_UART3) || defined(__DOXYGEN__) +#define TIVA_SERIAL_USE_UART3 FALSE +#endif + +/** + * @brief UART4 driver enable switch. + * @details If set to @p TRUE the support for UART4 is included. + * @note The default is @p FALSE . + */ +#if !defined(TIVA_SERIAL_USE_UART4) || defined(__DOXYGEN__) +#define TIVA_SERIAL_USE_UART4 FALSE +#endif + +/** + * @brief UART5 driver enable switch. + * @details If set to @p TRUE the support for UART5 is included. + * @note The default is @p FALSE . + */ +#if !defined(TIVA_SERIAL_USE_UART5) || defined(__DOXYGEN__) +#define TIVA_SERIAL_USE_UART5 FALSE +#endif + +/** + * @brief UART6 driver enable switch. + * @details If set to @p TRUE the support for UART6 is included. + * @note The default is @p FALSE . + */ +#if !defined(TIVA_SERIAL_USE_UART6) || defined(__DOXYGEN__) +#define TIVA_SERIAL_USE_UART6 FALSE +#endif + +/** + * @brief UART7 driver enable switch. + * @details If set to @p TRUE the support for UART7 is included. + * @note The default is @p FALSE . + */ +#if !defined(TIVA_SERIAL_USE_UART7) || defined(__DOXYGEN__) +#define TIVA_SERIAL_USE_UART7 FALSE +#endif + +/** + * @brief UART0 interrupt priority level setting. + */ +#if !defined(TIVA_SERIAL_UART0_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_SERIAL_UART0_PRIORITY 5 +#endif + +/** + * @brief UART1 interrupt priority level setting. + */ +#if !defined(TIVA_SERIAL_UART1_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_SERIAL_UART1_PRIORITY 5 +#endif + +/** + * @brief UART2 interrupt priority level setting. + */ +#if !defined(TIVA_SERIAL_UART2_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_SERIAL_UART2_PRIORITY 5 +#endif + +/** + * @brief UART3 interrupt priority level setting. + */ +#if !defined(TIVA_SERIAL_UART3_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_SERIAL_UART3_PRIORITY 5 +#endif + +/** + * @brief UART4 interrupt priority level setting. + */ +#if !defined(TIVA_SERIAL_UART4_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_SERIAL_UART4_PRIORITY 5 +#endif + +/** + * @brief UART5 interrupt priority level setting. + */ +#if !defined(TIVA_SERIAL_UART5_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_SERIAL_UART5_PRIORITY 5 +#endif + +/** + * @brief UART6 interrupt priority level setting. + */ +#if !defined(TIVA_SERIAL_UART6_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_SERIAL_UART6_PRIORITY 5 +#endif + +/** + * @brief UART7 interrupt priority level setting. + */ +#if !defined(TIVA_SERIAL_UART7_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_SERIAL_UART7_PRIORITY 5 +#endif + +/** + * @} + */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if !TIVA_SERIAL_USE_UART0 && !TIVA_SERIAL_USE_UART1 && \ + !TIVA_SERIAL_USE_UART2 && !TIVA_SERIAL_USE_UART3 && \ + !TIVA_SERIAL_USE_UART4 && !TIVA_SERIAL_USE_UART5 && \ + !TIVA_SERIAL_USE_UART6 && !TIVA_SERIAL_USE_UART7 +#error "SERIAL driver activated but no UART peripheral assigned" +#endif + +#if TIVA_SERIAL_USE_UART0 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART0_PRIORITY) +#error "Invalid IRQ priority assigned to UART0" +#endif + +#if TIVA_SERIAL_USE_UART1 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART1_PRIORITY) +#error "Invalid IRQ priority assigned to UART1" +#endif + +#if TIVA_SERIAL_USE_UART2 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART2_PRIORITY) +#error "Invalid IRQ priority assigned to UART2" +#endif + +#if TIVA_SERIAL_USE_UART3 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART3_PRIORITY) +#error "Invalid IRQ priority assigned to UART3" +#endif + +#if TIVA_SERIAL_USE_UART4 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART4_PRIORITY) +#error "Invalid IRQ priority assigned to UART4" +#endif + +#if TIVA_SERIAL_USE_UART5 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART5_PRIORITY) +#error "Invalid IRQ priority assigned to UART5" +#endif + +#if TIVA_SERIAL_USE_UART6 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART6_PRIORITY) +#error "Invalid IRQ priority assigned to UART6" +#endif + +#if TIVA_SERIAL_USE_UART7 && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART7_PRIORITY) +#error "Invalid IRQ priority assigned to UART7" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Tiva Serial Driver configuration structure. + * @details An instance of this structure must be passed to @p sdStart() + * in order to configure and start a serial driver operations. + */ +typedef struct { + /** + * @brief Bit rate. + */ + uint32_t sc_speed; + /* End of the mandatory fields. */ + /** + * @brief Initialization value for the LCRH (Line Control) register. + */ + uint32_t sc_lcrh; + /** + * @brief Initialization value for the IFLS (Interrupt FIFO Level Select) + * register. + */ + uint32_t sc_ifls; +} SerialConfig; + +/** + * @brief @p SerialDriver specific data. + */ +#define _serial_driver_data \ + _base_asynchronous_channel_data \ + /* Driver state.*/ \ + sdstate_t state; \ + /* Input queue.*/ \ + input_queue_t iqueue; \ + /* Output queue.*/ \ + output_queue_t oqueue; \ + /* Input circular buffer.*/ \ + uint8_t ib[SERIAL_BUFFERS_SIZE]; \ + /* Output circular buffer.*/ \ + uint8_t ob[SERIAL_BUFFERS_SIZE]; \ + /* End of the mandatory fields.*/ \ + /* Pointer to the USART registers block.*/ \ + UART_TypeDef *uart; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if TIVA_SERIAL_USE_UART0 && !defined(__DOXYGEN__) +extern SerialDriver SD1; +#endif + +#if TIVA_SERIAL_USE_UART1 && !defined(__DOXYGEN__) +extern SerialDriver SD2; +#endif + +#if TIVA_SERIAL_USE_UART2 && !defined(__DOXYGEN__) +extern SerialDriver SD3; +#endif + +#if TIVA_SERIAL_USE_UART3 && !defined(__DOXYGEN__) +extern SerialDriver SD4; +#endif + +#if TIVA_SERIAL_USE_UART4 && !defined(__DOXYGEN__) +extern SerialDriver SD5; +#endif + +#if TIVA_SERIAL_USE_UART5 && !defined(__DOXYGEN__) +extern SerialDriver SD6; +#endif + +#if TIVA_SERIAL_USE_UART6 && !defined(__DOXYGEN__) +extern SerialDriver SD7; +#endif + +#if TIVA_SERIAL_USE_UART7 && !defined(__DOXYGEN__) +extern SerialDriver SD8; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void sd_lld_init(void); + void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); + void sd_lld_stop(SerialDriver *sdp); +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_SERIAL */ + +#endif /* HAL_SERIAL_LLD_H */ + +/** @} */ diff --git a/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.c b/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.c new file mode 100644 index 0000000..38dcef0 --- /dev/null +++ b/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.c @@ -0,0 +1,244 @@ +/* + Copyright (C) 2014..2016 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + + +/** + * @file TIVA/wdg_lld.c + * @brief WDG Driver subsystem low level driver source. + * + * @addtogroup WDG + * @{ + */ + +#include "hal.h" + +#if HAL_USE_WDG || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +#if TIVA_WDG_USE_WDT0 || defined(__DOXYGEN__) +WDGDriver WDGD1; +#endif /* TIVA_WDG_USE_WDT0 */ + +#if TIVA_WDG_USE_WDT1 || defined(__DOXYGEN__) +WDGDriver WDGD2; +#endif /* TIVA_WDG_USE_WDT1 */ + +/*===========================================================================*/ +/* Driver local variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/** + * @brief Shared IRQ handler. + * + * @param[in] wdgp pointer to @p WDGDriver object. + */ +static void serve_interrupt(WDGDriver *wdgp) +{ + uint32_t mis; + + mis = wdgp->wdt->MIS; + + if (mis & MIS_WDTMIS) { + /* Invoke callback, if any */ + if (wdgp->config->callback) { + if (wdgp->config->callback(wdgp)) { + /* Clear interrupt */ + wdgp->wdt->ICR = 0; + wdgTivaSyncWrite(wdgp); + } + } + } +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if TIVA_WDG_USE_WDT0 || TIVA_WDG_USE_WDT1 +/** + * @brief WDT0/WDT1 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_WDT_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + +#if TIVA_WDG_USE_WDT0 + serve_interrupt(&WDGD1); +#endif + +#if TIVA_WDG_USE_WDT1 + serve_interrupt(&WDGD2); +#endif + + OSAL_IRQ_EPILOGUE(); +} +#endif /* TIVA_WDG_USE_WDT0 || TIVA_WDG_USE_WDT1 */ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Low level WDG driver initialization. + * + * @notapi + */ +void wdg_lld_init(void) +{ +#if TIVA_WDG_USE_WDT0 + WDGD1.state = WDG_STOP; + WDGD1.wdt = WDT0; +#endif /* TIVA_WDG_USE_WDT0 */ + +#if TIVA_WDG_USE_WDT1 + WDGD2.state = WDG_STOP; + WDGD2.wdt = WDT1; +#endif /* TIVA_WDG_USE_WDT1 */ + + /* The shared vector is initialized on driver initialization and never + disabled because it is shared between the Watchdog Timers.*/ + nvicEnableVector(TIVA_WDT_NUMBER, TIVA_WDG_WDT_IRQ_PRIORITY); +} + +/** + * @brief Configures and activates the WDG peripheral. + * + * @param[in] wdgp pointer to the @p WDGDriver object + * + * @notapi + */ +void wdg_lld_start(WDGDriver *wdgp) +{ +#if TIVA_WDG_USE_WDT0 + if (&WDGD1 == wdgp) { + SYSCTL->RCGCWD |= (1 << 0); + + while (!(SYSCTL->PRWD & (1 << 0))) + ; + } +#endif /* TIVA_WDG_USE_WDT0 */ + +#if TIVA_WDG_USE_WDT1 + if (&WDGD2 == wdgp) { + SYSCTL->RCGCWD |= (1 << 1); + + while (!(SYSCTL->PRWD & (1 << 1))) + ; + } +#endif /* TIVA_WDG_USE_WDT1 */ + + wdgp->wdt->LOAD = wdgp->config->load; + wdgTivaSyncWrite(wdgp); + + wdgp->wdt->TEST = wdgp->config->test; + wdgTivaSyncWrite(wdgp); + + wdgp->wdt->CTL |= CTL_RESEN; + wdgTivaSyncWrite(wdgp); + + wdgp->wdt->CTL |= CTL_INTEN; + wdgTivaSyncWrite(wdgp); +} + +/** + * @brief Deactivates the WDG peripheral. + * + * @param[in] wdgp pointer to the @p WDGDriver object + * + * @api + */ +void wdg_lld_stop(WDGDriver *wdgp) +{ +#if TIVA_WDG_USE_WDT0 + if (&WDGD1 == wdgp) { + SYSCTL->SRWD |= (1 << 0); + SYSCTL->SRWD &= ~(1 << 0); + } +#endif /* TIVA_WDG_USE_WDT0 */ + +#if TIVA_WDG_USE_WDT1 + if (&WDGD2 == wdgp) { + SYSCTL->SRWD |= (1 << 1); + SYSCTL->SRWD &= ~(1 << 1); + } +#endif /* TIVA_WDG_USE_WDT1 */ +} + +/** + * @brief Reloads WDG's counter. + * + * @param[in] wdgp pointer to the @p WDGDriver object + * + * @notapi + */ +void wdg_lld_reset(WDGDriver *wdgp) +{ +#if defined(TM4C123_USE_REVISION_6_FIX) || defined(TM4C123_USE_REVISION_7_FIX) + +#if TIVA_WDG_USE_WDT1 + if (&WDGD2 == wdgp) { + /* Number: WDT#02 + * Description: Periodically reloading the count value into the Watchdog + * Timer Load (WDTLOAD) register of the Watchdog Timer 1 + * module will not restart the count, as specified in the data + * sheet. + * Workaround: Disable the Watchdog Timer 1 module by setting the + * appropriate bit in the Watchdog Timer Software Reset (SRWD) + * register before reprogramming the counter.*/ + wdg_lld_stop(wdgp); + wdg_lld_start(wdgp); + return; + } +#endif /* TIVA_WDG_USE_WDT1 */ + +#endif /* defined(TM4C123_USE_REVISION_6_FIX) || + defined(TM4C123_USE_REVISION_7_FIX) */ + wdgp->wdt->LOAD = wdgp->config->load; + wdgTivaSyncWrite(wdgp); +} + +#endif /* HAL_USE_WDG */ + +#if TIVA_WDG_USE_WDT1 +/** + * @brief synchronize after a write to a watchdog register. + * + * @param[in] wdgp pointer to the @p WDGDriver object. + */ +void wdgTivaSyncWrite(WDGDriver *wdgp) +{ + if (&WDGD2 == wdgp) { + while (!(wdgp->wdt->CTL & CTL_WRC)) { + ; + } + } +} +#endif /* TIVA_WDG_USE_WDT1 */ + +/** @} */ diff --git a/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.h b/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.h new file mode 100644 index 0000000..f88fa26 --- /dev/null +++ b/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.h @@ -0,0 +1,190 @@ +/* + Copyright (C) 2014..2016 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + + +/** + * @file TIVA/wdg_lld.h + * @brief WDG Driver subsystem low level driver header. + * + * @addtogroup WDG + * @{ + */ + +#ifndef _WDG_LLD_H_ +#define _WDG_LLD_H_ + +#if HAL_USE_WDG || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +#define LOCK_UNLOCK 0x1ACCE551U +#define LOCK_LOCK 0x00000000U + +#define LOCK_IS_UNLOCKED 0U +#define LOCK_IS_LOCKED 1U + +#define TEST_STALL (1 << 8) + +#define MIS_WDTMIS (1 << 0) +#define RIS_WDTRIS (1 << 0) +#define ICR_WDTICR (1 << 0) + +#define CTL_INTEN (1 << 0) +#define CTL_RESEN (1 << 1) +#define CTL_INTTYPE (1 << 2) +#define CTL_WRC (1 << 31) + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @name Configuration options + * @{ + */ +/** + * @brief WDT driver enable switch. + * @details If set to @p TRUE the support for WDT is included. + * @note The default is @p FALSE. + */ +#if !defined(TIVA_WDG_USE_WDT) || defined(__DOXYGEN__) +#define TIVA_WDG_USE_WDT FALSE +#endif + +/** + * @brief WDT interrupt priority level setting. + */ +#if !defined(TIVA_WDG_WDT_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_WDG_WDT_IRQ_PRIORITY 5 +#endif + +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#if TIVA_WDG_USE_WDT0 && !TIVA_HAS_WDT0 +#error "WDT0 not present in the selected device" +#endif + +#if TIVA_WDG_USE_WDT1 && !TIVA_HAS_WDT1 +#error "WDT1 not present in the selected device" +#endif + +#if !TIVA_WDG_USE_WDT0 && !TIVA_WDG_USE_WDT1 +#error "WDG driver activated but no WDT peripheral assigned" +#endif + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief Type of a structure representing an WDG driver. + */ +typedef struct WDGDriver WDGDriver; + +/** + * @brief WDG timeout callback type. + * + * @param[in] wdgp pointer to the @p WDGDriver object triggering the callback. + */ +typedef bool (*wdgcallback_t)(WDGDriver *wdgp); + +/** + * @brief Driver configuration structure. + * @note It could be empty on some architectures. + */ +typedef struct +{ + /** + * @brief Interval value used by the WDT. + */ + uint32_t load; + /** + * @brief Timeout callback pointer. + * @note This callback is invoked on the first WDT timeout. If set to + * @p NULL then the callback is disabled. + */ + wdgcallback_t callback; + /** + * @brief Test register configuration value. + */ + uint16_t test; +} WDGConfig; + +/** + * @brief Structure representing an WDG driver. + */ +struct WDGDriver +{ + /** + * @brief Driver state. + */ + wdgstate_t state; + /** + * @brief Current configuration data. + */ + const WDGConfig *config; + /* End of the mandatory fields.*/ + /** + * @brief Pointer to the WDT registers block. + */ + WDT_TypeDef *wdt; +}; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +#if !TIVA_WDG_USE_WDT1 +#define wdgTivaSyncWrite(wdt) +#endif + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +#if TIVA_WDG_USE_WDT0 && !defined(__DOXYGEN__) +extern WDGDriver WDGD1; +#endif + +#if TIVA_WDG_USE_WDT1 && !defined(__DOXYGEN__) +extern WDGDriver WDGD2; +#endif + +#ifdef __cplusplus +extern "C" { +#endif + void wdg_lld_init(void); + void wdg_lld_start(WDGDriver *wdgp); + void wdg_lld_stop(WDGDriver *wdgp); + void wdg_lld_reset(WDGDriver *wdgp); +#if TIVA_WDG_USE_WDT1 + void wdgTivaSyncWrite(WDGDriver *wdgp); +#endif +#ifdef __cplusplus +} +#endif + +#endif /* HAL_USE_WDG */ + +#endif /* _WDG_LLD_H_ */ + +/** @} */ diff --git a/os/hal/ports/TIVA/LLD/hal_ext_lld.c b/os/hal/ports/TIVA/LLD/hal_ext_lld.c deleted file mode 100644 index efe6421..0000000 --- a/os/hal/ports/TIVA/LLD/hal_ext_lld.c +++ /dev/null @@ -1,981 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file Tiva/ext_lld.c - * @brief Tiva EXT subsystem low level driver source. - * - * @addtogroup EXT - * @{ - */ - -#include "hal.h" - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/** - * @brief Generic interrupt serving code for multiple pins per interrupt - * handler. - */ -#define ext_lld_serve_port_interrupt(gpiop, start) \ - do { \ - uint32_t mis = gpiop->MIS; \ - \ - gpiop->ICR = mis; \ - \ - if (mis & (1 << 0)) { \ - EXTD1.config->channels[start + 0].cb(&EXTD1, start + 0); \ - } \ - if (mis & (1 << 1)) { \ - EXTD1.config->channels[start + 1].cb(&EXTD1, start + 1); \ - } \ - if (mis & (1 << 2)) { \ - EXTD1.config->channels[start + 2].cb(&EXTD1, start + 2); \ - } \ - if (mis & (1 << 3)) { \ - EXTD1.config->channels[start + 3].cb(&EXTD1, start + 3); \ - } \ - if (mis & (1 << 4)) { \ - EXTD1.config->channels[start + 4].cb(&EXTD1, start + 4); \ - } \ - if (mis & (1 << 5)) { \ - EXTD1.config->channels[start + 5].cb(&EXTD1, start + 5); \ - } \ - if (mis & (1 << 6)) { \ - EXTD1.config->channels[start + 6].cb(&EXTD1, start + 6); \ - } \ - if (mis & (1 << 7)) { \ - EXTD1.config->channels[start + 7].cb(&EXTD1, start + 7); \ - } \ - } while (0); - -/** - * @brief Generic interrupt serving code for single pin per interrupt - * handler. - */ -#define ext_lld_serve_pin_interrupt(gpiop, start, pin) \ - do { \ - gpiop->ICR = (1 << pin); \ - EXTD1.config->channels[start].cb(&EXTD1, start); \ - } while (0); - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief EXTD1 driver identifier. - */ -EXTDriver EXTD1; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -const ioportid_t gpio[] = -{ -#if TIVA_HAS_GPIOA - GPIOA, -#endif -#if TIVA_HAS_GPIOB - GPIOB, -#endif -#if TIVA_HAS_GPIOC - GPIOC, -#endif -#if TIVA_HAS_GPIOD - GPIOD, -#endif -#if TIVA_HAS_GPIOE - GPIOE, -#endif -#if TIVA_HAS_GPIOF - GPIOF, -#endif -#if TIVA_HAS_GPIOG - GPIOG, -#endif -#if TIVA_HAS_GPIOH - GPIOH, -#endif -#if TIVA_HAS_GPIOJ - GPIOJ, -#endif -#if TIVA_HAS_GPIOK - GPIOK, -#endif -#if TIVA_HAS_GPIOL - GPIOL, -#endif -#if TIVA_HAS_GPIOM - GPIOM, -#endif -#if TIVA_HAS_GPION - GPION, -#endif -#if TIVA_HAS_GPIOP - GPIOP, -#endif -#if TIVA_HAS_GPIOQ - GPIOQ, -#endif -#if TIVA_HAS_GPIOR - GPIOR, -#endif -#if TIVA_HAS_GPIOS - GPIOS, -#endif -#if TIVA_HAS_GPIOT - GPIOT, -#endif -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Enables GPIO IRQ sources. - * - * @notapi - */ -static void ext_lld_irq_enable(void) -{ -#if TIVA_HAS_GPIOA - nvicEnableVector(TIVA_GPIOA_NUMBER, TIVA_EXT_GPIOA_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOB - nvicEnableVector(TIVA_GPIOB_NUMBER, TIVA_EXT_GPIOB_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOC - nvicEnableVector(TIVA_GPIOC_NUMBER, TIVA_EXT_GPIOC_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOD - nvicEnableVector(TIVA_GPIOD_NUMBER, TIVA_EXT_GPIOD_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOE - nvicEnableVector(TIVA_GPIOE_NUMBER, TIVA_EXT_GPIOE_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOF - nvicEnableVector(TIVA_GPIOF_NUMBER, TIVA_EXT_GPIOF_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOG - nvicEnableVector(TIVA_GPIOG_NUMBER, TIVA_EXT_GPIOG_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOH - nvicEnableVector(TIVA_GPIOH_NUMBER, TIVA_EXT_GPIOH_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOJ - nvicEnableVector(TIVA_GPIOJ_NUMBER, TIVA_EXT_GPIOJ_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOK - nvicEnableVector(TIVA_GPIOK_NUMBER, TIVA_EXT_GPIOK_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOL - nvicEnableVector(TIVA_GPIOL_NUMBER, TIVA_EXT_GPIOL_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOM - nvicEnableVector(TIVA_GPIOM_NUMBER, TIVA_EXT_GPIOM_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPION - nvicEnableVector(TIVA_GPION_NUMBER, TIVA_EXT_GPION_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOP - nvicEnableVector(TIVA_GPIOP0_NUMBER, TIVA_EXT_GPIOP0_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOP1_NUMBER, TIVA_EXT_GPIOP1_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOP2_NUMBER, TIVA_EXT_GPIOP2_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOP3_NUMBER, TIVA_EXT_GPIOP3_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOP4_NUMBER, TIVA_EXT_GPIOP4_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOP5_NUMBER, TIVA_EXT_GPIOP5_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOP6_NUMBER, TIVA_EXT_GPIOP6_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOP7_NUMBER, TIVA_EXT_GPIOP7_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOQ - nvicEnableVector(TIVA_GPIOQ0_NUMBER, TIVA_EXT_GPIOQ0_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOQ1_NUMBER, TIVA_EXT_GPIOQ1_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOQ2_NUMBER, TIVA_EXT_GPIOQ2_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOQ3_NUMBER, TIVA_EXT_GPIOQ3_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOQ4_NUMBER, TIVA_EXT_GPIOQ4_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOQ5_NUMBER, TIVA_EXT_GPIOQ5_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOQ6_NUMBER, TIVA_EXT_GPIOQ6_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOQ7_NUMBER, TIVA_EXT_GPIOQ7_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOR - nvicEnableVector(TIVA_GPIOR_NUMBER, TIVA_EXT_GPIOR_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOS - nvicEnableVector(TIVA_GPIOS_NUMBER, TIVA_EXT_GPIOS_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOT - nvicEnableVector(TIVA_GPIOT_NUMBER, TIVA_EXT_GPIOT_IRQ_PRIORITY); -#endif -} - -/** - * @brief Disables GPIO IRQ sources. - * - * @notapi - */ -static void ext_lld_irq_disable(void) -{ -#if TIVA_HAS_GPIOA - nvicDisableVector(TIVA_GPIOA_NUMBER); -#endif -#if TIVA_HAS_GPIOB - nvicDisableVector(TIVA_GPIOB_NUMBER); -#endif -#if TIVA_HAS_GPIOC - nvicDisableVector(TIVA_GPIOC_NUMBER); -#endif -#if TIVA_HAS_GPIOD - nvicDisableVector(TIVA_GPIOD_NUMBER); -#endif -#if TIVA_HAS_GPIOE - nvicDisableVector(TIVA_GPIOE_NUMBER); -#endif -#if TIVA_HAS_GPIOF - nvicDisableVector(TIVA_GPIOF_NUMBER); -#endif -#if TIVA_HAS_GPIOG - nvicDisableVector(TIVA_GPIOG_NUMBER); -#endif -#if TIVA_HAS_GPIOH - nvicDisableVector(TIVA_GPIOH_NUMBER); -#endif -#if TIVA_HAS_GPIOJ - nvicDisableVector(TIVA_GPIOJ_NUMBER); -#endif -#if TIVA_HAS_GPIOK - nvicDisableVector(TIVA_GPIOK_NUMBER); -#endif -#if TIVA_HAS_GPIOL - nvicDisableVector(TIVA_GPIOL_NUMBER); -#endif -#if TIVA_HAS_GPIOM - nvicDisableVector(TIVA_GPIOM_NUMBER); -#endif -#if TIVA_HAS_GPION - nvicDisableVector(TIVA_GPION_NUMBER); -#endif -#if TIVA_HAS_GPIOP - nvicDisableVector(TIVA_GPIOP0_NUMBER); - nvicDisableVector(TIVA_GPIOP1_NUMBER); - nvicDisableVector(TIVA_GPIOP2_NUMBER); - nvicDisableVector(TIVA_GPIOP3_NUMBER); - nvicDisableVector(TIVA_GPIOP4_NUMBER); - nvicDisableVector(TIVA_GPIOP5_NUMBER); - nvicDisableVector(TIVA_GPIOP6_NUMBER); - nvicDisableVector(TIVA_GPIOP7_NUMBER); -#endif -#if TIVA_HAS_GPIOQ - nvicDisableVector(TIVA_GPIOQ0_NUMBER); - nvicDisableVector(TIVA_GPIOQ1_NUMBER); - nvicDisableVector(TIVA_GPIOQ2_NUMBER); - nvicDisableVector(TIVA_GPIOQ3_NUMBER); - nvicDisableVector(TIVA_GPIOQ4_NUMBER); - nvicDisableVector(TIVA_GPIOQ5_NUMBER); - nvicDisableVector(TIVA_GPIOQ6_NUMBER); - nvicDisableVector(TIVA_GPIOQ7_NUMBER); -#endif -#if TIVA_HAS_GPIOR - nvicDisableVector(TIVA_GPIOR_NUMBER); -#endif -#if TIVA_HAS_GPIOS - nvicDisableVector(TIVA_GPIOS_NUMBER); -#endif -#if TIVA_HAS_GPIOT - nvicDisableVector(TIVA_GPIOT_NUMBER); -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if TIVA_HAS_GPIOA || defined(__DOXYGEN__) -/** - * @brief GPIOA interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOA_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(GPIOA, 0); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOB || defined(__DOXYGEN__) -/** - * @brief GPIOB interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOB_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(GPIOB, 8); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOC || defined(__DOXYGEN__) -/** - * @brief GPIOC interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOC_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(GPIOC, 16); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOD || defined(__DOXYGEN__) -/** - * @brief GPIOD interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOD_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(GPIOD, 24); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOE || defined(__DOXYGEN__) -/** - * @brief GPIOE interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOE_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(GPIOE, 32); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOF || defined(__DOXYGEN__) -/** - * @brief GPIOF interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOF_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(GPIOF, 40); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOG || defined(__DOXYGEN__) -/** - * @brief GPIOG interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOG_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOG, 48); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOH || defined(__DOXYGEN__) -/** - * @brief GPIOH interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOH_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOH, 56); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__) -/** - * @brief GPIOJ interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOJ_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOJ, 64); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOK || defined(__DOXYGEN__) -/** - * @brief GPIOK interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOK_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOK, 72); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOL || defined(__DOXYGEN__) -/** - * @brief GPIOL interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOL_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOL, 80); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOM || defined(__DOXYGEN__) -/** - * @brief GPIOM interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOM_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOM, 88); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPION || defined(__DOXYGEN__) -/** - * @brief GPION interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPION_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPION, 96); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOP || defined(__DOXYGEN__) -/** - * @brief GPIOP0 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP0_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 104, 0); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOP1 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP1_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 105, 1); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOP2 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP2_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 106, 2); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOP3 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP3_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 107, 3); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOP4 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP4_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 108, 4); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOP5 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP5_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 109, 5); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOP6 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP6_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 110, 6); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOP7 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP7_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 111, 7); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__) -/** - * @brief GPIOQ0 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ0_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 112, 0); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOQ1 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ1_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 113, 1); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOQ2 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ2_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 114, 2); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOQ3 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ3_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 115, 3); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOQ4 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ4_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 116, 4); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOQ5 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ5_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 117, 5); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOQ6 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ6_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 118, 6); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOQ7 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ7_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 119, 7); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOR || defined(__DOXYGEN__) -/** - * @brief GPIOR interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOR_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOR, 120); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOS || defined(__DOXYGEN__) -/** - * @brief GPIOS interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOS_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOS, 128); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOT || defined(__DOXYGEN__) -/** - * @brief GPIOT interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOT_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOT, 132); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level EXT driver initialization. - * - * @notapi - */ -void ext_lld_init(void) -{ - extObjectInit(&EXTD1); -} - -/** - * @brief Configures and activates the EXT peripheral. - * - * @param[in] extp pointer to the @p EXTDriver object - * - * @notapi - */ -void ext_lld_start(EXTDriver *extp) -{ - uint8_t i; - - if (extp->state == EXT_STOP) { - ext_lld_irq_enable(); - } - - /* Configuration of automatic channels.*/ - for (i = 0; i < EXT_MAX_CHANNELS; i++) { - if (extp->config->channels[i].mode & EXT_CH_MODE_AUTOSTART) { - ext_lld_channel_enable(extp, i); - } - else { - ext_lld_channel_disable(extp, i); - } - } -} - -/** - * @brief Deactivates the EXT peripheral. - * - * @param[in] extp pointer to the @p EXTDriver object - * - * @notapi - */ -void ext_lld_stop(EXTDriver *extp) -{ - if (extp->state == EXT_ACTIVE) { - ext_lld_irq_disable(); - } - -#if TIVA_HAS_GPIOA - GPIOA->IM = 0; -#endif -#if TIVA_HAS_GPIOB - GPIOB->IM = 0; -#endif -#if TIVA_HAS_GPIOC - GPIOC->IM = 0; -#endif -#if TIVA_HAS_GPIOD - GPIOD->IM = 0; -#endif -#if TIVA_HAS_GPIOE - GPIOE->IM = 0; -#endif -#if TIVA_HAS_GPIOF - GPIOF->IM = 0; -#endif -#if TIVA_HAS_GPIOG - GPIOG->IM = 0; -#endif -#if TIVA_HAS_GPIOH - GPIOH->IM = 0; -#endif -#if TIVA_HAS_GPIOJ - GPIOJ->IM = 0; -#endif -#if TIVA_HAS_GPIOK - GPIOK->IM = 0; -#endif -#if TIVA_HAS_GPIOL - GPIOL->IM = 0; -#endif -#if TIVA_HAS_GPIOM - GPIOM->IM = 0; -#endif -#if TIVA_HAS_GPION - GPION->IM = 0; -#endif -#if TIVA_HAS_GPIOP - GPIOP->IM = 0; -#endif -#if TIVA_HAS_GPIOQ - GPIOQ->IM = 0; -#endif -#if TIVA_HAS_GPIOR - GPIOR->IM = 0; -#endif -#if TIVA_HAS_GPIOS - GPIOS->IM = 0; -#endif -#if TIVA_HAS_GPIOT - GPIOT->IM = 0; -#endif -} - -/** - * @brief Enables an EXT channel. - * - * @param[in] extp pointer to the @p EXTDriver object - * @param[in] channel channel to be enabled - * - * @notapi - */ -void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) -{ - GPIO_TypeDef *gpiop; - uint8_t pin; - uint32_t im; - - pin = channel & 0x07; - gpiop = gpio[channel >> 3]; - - /* Disable interrupts */ - im = gpiop->IM; - gpiop->IM = 0; - - /* Configure pin to be edge-sensitive.*/ - gpiop->IS &= ~(1 << pin); - - /* Programming edge registers.*/ - if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) == - EXT_CH_MODE_BOTH_EDGES) { - gpiop->IBE |= (1 << pin); - } - else if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) == - EXT_CH_MODE_FALLING_EDGE) { - gpiop->IBE &= ~(1 << pin); - gpiop->IEV &= ~(1 << pin); - } - else if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) == - EXT_CH_MODE_RISING_EDGE) { - gpiop->IBE &= ~(1 << pin); - gpiop->IEV |= (1 << pin); - } - - /* Programming interrupt and event registers.*/ - if ((extp->config->channels[channel].cb != NULL) && - ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) != - EXT_CH_MODE_DISABLED)) { - im |= (1 << pin); - } - else { - im &= ~(1 << pin); - } - - /* Restore interrupts */ - gpiop->IM = im; -} - -/** - * @brief Disables an EXT channel. - * - * @param[in] extp pointer to the @p EXTDriver object - * @param[in] channel channel to be disabled - * - * @notapi - */ -void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) -{ - (void)extp; - GPIO_TypeDef *gpiop; - uint8_t pin; - - pin = channel & 0x07; - gpiop = gpio[channel >> 3]; - - gpiop->IM &= ~(1 << pin); -} - -#endif /* HAL_USE_EXT */ - -/** @} */ diff --git a/os/hal/ports/TIVA/LLD/hal_ext_lld.h b/os/hal/ports/TIVA/LLD/hal_ext_lld.h deleted file mode 100644 index 08accb2..0000000 --- a/os/hal/ports/TIVA/LLD/hal_ext_lld.h +++ /dev/null @@ -1,523 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file Tiva/ext_lld.h - * @brief Tiva EXT subsystem low level driver header. - * - * @addtogroup EXT - * @{ - */ - -#ifndef HAL_EXT_LLD_H -#define HAL_EXT_LLD_H - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Number of EXT per port. - */ -#define EXT_MAX_CHANNELS TIVA_GPIO_PINS - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief GPIOA interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOA_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOA_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOB interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOB_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOB_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOC interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOC_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOC_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOD interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOD_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOD_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOE interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOE_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOE_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOF interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOF_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOF_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOG interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOG_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOG_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOH interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOH_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOH_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOJ interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOJ_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOJ_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOK interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOK_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOK_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOL interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOL_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOL_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOM interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOM_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOM_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPION interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPION_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPION_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP0 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP0_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP0_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP1 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP1_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP2 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP2_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP3 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP3_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP4 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP4_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP5 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP5_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP5_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP6 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP6_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP6_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP7 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP7_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP7_IRQ_PRIORITY 3 -#endif -/** @} */ - -/** - * @brief GPIOQ0 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ0_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ0_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOQ1 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ1_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOQ2 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ2_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOQ3 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ3_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOQ4 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ4_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOQ5 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ5_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ5_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOQ6 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ6_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ6_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOQ7 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ7_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ7_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOR interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOR_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOR_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOS interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOS_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOS_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOT interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOT_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOT_IRQ_PRIORITY 3 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if TIVA_HAS_GPIOA && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOA_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOA" -#endif - -#if TIVA_HAS_GPIOB && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOB_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOB" -#endif - -#if TIVA_HAS_GPIOC && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOC_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOC" -#endif - -#if TIVA_HAS_GPIOD && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOD_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOD" -#endif - -#if TIVA_HAS_GPIOE && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOE_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOE" -#endif - -#if TIVA_HAS_GPIOF && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOF_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOF" -#endif - -#if TIVA_HAS_GPIOG && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOG_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOG" -#endif - -#if TIVA_HAS_GPIOH && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOH_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOH" -#endif - -#if TIVA_HAS_GPIOJ && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOJ_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOJ" -#endif - -#if TIVA_HAS_GPIOK && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOK_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOK" -#endif - -#if TIVA_HAS_GPIOL && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOL_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOL" -#endif - -#if TIVA_HAS_GPIOM && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOM_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOM" -#endif - -#if TIVA_HAS_GPION && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPION_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPION" -#endif - -#if TIVA_HAS_GPIOP0 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP0_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP0" -#endif - -#if TIVA_HAS_GPIOP1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP1" -#endif - -#if TIVA_HAS_GPIOP2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP2" -#endif - -#if TIVA_HAS_GPIOP3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP3" -#endif - -#if TIVA_HAS_GPIOP4 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP4_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP4" -#endif - -#if TIVA_HAS_GPIOP5 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP5_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP5" -#endif - -#if TIVA_HAS_GPIOP6 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP6_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP6" -#endif - -#if TIVA_HAS_GPIOP7 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP7_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP7" -#endif - -#if TIVA_HAS_GPIOQ0 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ0_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ0" -#endif - -#if TIVA_HAS_GPIOQ1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ1" -#endif - -#if TIVA_HAS_GPIOQ2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ2" -#endif - -#if TIVA_HAS_GPIOQ3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ3" -#endif - -#if TIVA_HAS_GPIOQ4 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ4_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ4" -#endif - -#if TIVA_HAS_GPIOQ5 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ5_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ5" -#endif - -#if TIVA_HAS_GPIOQ6 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ6_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ6" -#endif - -#if TIVA_HAS_GPIOQ7 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ7_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ7" -#endif - -#if TIVA_HAS_GPIOR && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOR_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOR" -#endif - -#if TIVA_HAS_GPIOS && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOS_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOS" -#endif - -#if TIVA_HAS_GPIOT && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOT_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOT" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief EXT channel identifier. - */ -typedef uint32_t expchannel_t; - -/** - * @brief Type of an EXT generic notification callback. - * - * @param[in] extp pointer to the @p EXPDriver object triggering the - * callback - */ -typedef void (*extcallback_t)(EXTDriver *extp, expchannel_t channel); - -/** - * @brief Channel configuration structure. - */ -typedef struct { - /** - * @brief Channel mode. - */ - uint32_t mode; - /** - * @brief Channel callback. - */ - extcallback_t cb; -} EXTChannelConfig; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief Channel configurations. - */ - EXTChannelConfig channels[EXT_MAX_CHANNELS]; - /* End of the mandatory fields.*/ -} EXTConfig; - -/** - * @brief Structure representing an EXT driver. - */ -struct EXTDriver { - /** - * @brief Driver state. - */ - extstate_t state; - /** - * @brief Current configuration data. - */ - const EXTConfig *config; - /* End of the mandatory fields.*/ -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern EXTDriver EXTD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void ext_lld_init(void); - void ext_lld_start(EXTDriver *extp); - void ext_lld_stop(EXTDriver *extp); - void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel); - void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_EXT */ - -#endif /* HAL_EXT_LLD_H */ - -/** @} */ diff --git a/os/hal/ports/TIVA/LLD/hal_gpt_lld.c b/os/hal/ports/TIVA/LLD/hal_gpt_lld.c deleted file mode 100644 index 870ba12..0000000 --- a/os/hal/ports/TIVA/LLD/hal_gpt_lld.c +++ /dev/null @@ -1,756 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TIVA/gpt_lld.c - * @brief TM4C123x/TM4C129x GPT subsystem low level driver source. - * - * @addtogroup GPT - * @{ - */ - -#include "hal.h" - -#if HAL_USE_GPT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief GPTD1 driver identifier. - */ -#if TIVA_GPT_USE_GPT0 || defined(__DOXYGEN__) -GPTDriver GPTD1; -#endif - -/** - * @brief GPTD2 driver identifier. - */ -#if TIVA_GPT_USE_GPT1 || defined(__DOXYGEN__) -GPTDriver GPTD2; -#endif - -/** - * @brief GPTD3 driver identifier. - */ -#if TIVA_GPT_USE_GPT2 || defined(__DOXYGEN__) -GPTDriver GPTD3; -#endif - -/** - * @brief GPTD4 driver identifier. - */ -#if TIVA_GPT_USE_GPT3 || defined(__DOXYGEN__) -GPTDriver GPTD4; -#endif - -/** - * @brief GPTD5 driver identifier. - */ -#if TIVA_GPT_USE_GPT4 || defined(__DOXYGEN__) -GPTDriver GPTD5; -#endif - -/** - * @brief GPTD6 driver identifier. - */ -#if TIVA_GPT_USE_GPT5 || defined(__DOXYGEN__) -GPTDriver GPTD6; -#endif - -/** - * @brief GPTD7 driver identifier. - */ -#if TIVA_GPT_USE_WGPT0 || defined(__DOXYGEN__) -GPTDriver GPTD7; -#endif - -/** - * @brief GPTD8 driver identifier. - */ -#if TIVA_GPT_USE_WGPT1 || defined(__DOXYGEN__) -GPTDriver GPTD8; -#endif - -/** - * @brief GPTD9 driver identifier. - */ -#if TIVA_GPT_USE_WGPT2 || defined(__DOXYGEN__) -GPTDriver GPTD9; -#endif - -/** - * @brief GPTD10 driver identifier. - */ -#if TIVA_GPT_USE_WGPT3 || defined(__DOXYGEN__) -GPTDriver GPTD10; -#endif - -/** - * @brief GPTD11 driver identifier. - */ -#if TIVA_GPT_USE_WGPT4 || defined(__DOXYGEN__) -GPTDriver GPTD11; -#endif - -/** - * @brief GPTD12 driver identifier. - */ -#if TIVA_GPT_USE_WGPT5 || defined(__DOXYGEN__) -GPTDriver GPTD12; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Shared IRQ handler. - * - * @param[in] gptp pointer to @p GPTDriver object - */ -static void gpt_lld_serve_interrupt(GPTDriver *gptp) -{ - gptp->gpt->ICR = 0xffffffff; - - if (gptp->state == GPT_ONESHOT) { - gptp->state = GPT_READY; - gpt_lld_stop_timer(gptp); - } - - gptp->config->callback(gptp); -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if TIVA_GPT_USE_GPT0 -#if !defined(TIVA_GPT0A_HANDLER) -#error "TIVA_GPT0A_HANDLER not defined" -#endif -/** - * @brief GPT0 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPT0A_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD1); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_GPT_USE_GPT1 -#if !defined(TIVA_GPT1A_HANDLER) -#error "TIVA_GPT1A_HANDLER not defined" -#endif -/** - * @brief GPT1 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPT1A_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD2); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_GPT_USE_GPT2 -#if !defined(TIVA_GPT2A_HANDLER) -#error "TIVA_GPT2A_HANDLER not defined" -#endif -/** - * @brief GPT2 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPT2A_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD3); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_GPT_USE_GPT3 -#if !defined(TIVA_GPT3A_HANDLER) -#error "TIVA_GPT3A_HANDLER not defined" -#endif -/** - * @brief GPT3 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPT3A_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD4); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_GPT_USE_GPT4 -#if !defined(TIVA_GPT4A_HANDLER) -#error "TIVA_GPT4A_HANDLER not defined" -#endif -/** - * @brief GPT4 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPT4A_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD5); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_GPT_USE_GPT5 -#if !defined(TIVA_GPT5A_HANDLER) -#error "TIVA_GPT5A_HANDLER not defined" -#endif -/** - * @brief GPT5 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPT5A_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD6); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_GPT_USE_WGPT0 -#if !defined(TIVA_WGPT0A_HANDLER) -#error "TIVA_WGPT0A_HANDLER not defined" -#endif -/** - * @brief WGPT0 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_WGPT0A_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD7); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_GPT_USE_WGPT1 -#if !defined(TIVA_WGPT1A_HANDLER) -#error "TIVA_WGPT1A_HANDLER not defined" -#endif -/** - * @brief WGPT1 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_WGPT1A_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD8); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_GPT_USE_WGPT2 -#if !defined(TIVA_WGPT2A_HANDLER) -#error "TIVA_WGPT2A_HANDLER not defined" -#endif -/** - * @brief WGPT2 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_WGPT2A_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD9); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_GPT_USE_WGPT3 -#if !defined(TIVA_WGPT3A_HANDLER) -#error "TIVA_WGPT3A_HANDLER not defined" -#endif -/** - * @brief WGPT3 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_WGPT3A_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD10); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_GPT_USE_WGPT4 -#if !defined(TIVA_WGPT4A_HANDLER) -#error "TIVA_WGPT4A_HANDLER not defined" -#endif -/** - * @brief WGPT4 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_WGPT4A_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD11); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_GPT_USE_WGPT5 -#if !defined(TIVA_WGPT5A_HANDLER) -#error "TIVA_WGPT5A_HANDLER not defined" -#endif -/** - * @brief WGPT5 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_WGPT5A_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - gpt_lld_serve_interrupt(&GPTD12); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level GPT driver initialization. - * - * @notapi - */ -void gpt_lld_init(void) -{ - /* Driver initialization.*/ -#if TIVA_GPT_USE_GPT0 - GPTD1.gpt = GPT0; - gptObjectInit(&GPTD1); -#endif - -#if TIVA_GPT_USE_GPT1 - GPTD2.gpt = GPT1; - gptObjectInit(&GPTD2); -#endif - -#if TIVA_GPT_USE_GPT2 - GPTD3.gpt = GPT2; - gptObjectInit(&GPTD3); -#endif - -#if TIVA_GPT_USE_GPT3 - GPTD4.gpt = GPT3; - gptObjectInit(&GPTD4); -#endif - -#if TIVA_GPT_USE_GPT4 - GPTD5.gpt = GPT4; - gptObjectInit(&GPTD5); -#endif - -#if TIVA_GPT_USE_GPT5 - GPTD6.gpt = GPT5; - gptObjectInit(&GPTD6); -#endif - -#if TIVA_GPT_USE_WGPT0 - GPTD7.gpt = WGPT0; - gptObjectInit(&GPTD7); -#endif - -#if TIVA_GPT_USE_WGPT1 - GPTD8.gpt = WGPT1; - gptObjectInit(&GPTD8); -#endif - -#if TIVA_GPT_USE_WGPT2 - GPTD9.gpt = WGPT2; - gptObjectInit(&GPTD9); -#endif - -#if TIVA_GPT_USE_WGPT3 - GPTD10.gpt = WGPT3; - gptObjectInit(&GPTD10); -#endif - -#if TIVA_GPT_USE_WGPT4 - GPTD11.gpt = WGPT4; - gptObjectInit(&GPTD11); -#endif - -#if TIVA_GPT_USE_WGPT5 - GPTD12.gpt = WGPT5; - gptObjectInit(&GPTD12); -#endif -} - -/** - * @brief Configures and activates the GPT peripheral. - * - * @param[in] gptp pointer to the @p GPTDriver object - * - * @notapi - */ -void gpt_lld_start(GPTDriver *gptp) -{ - if (gptp->state == GPT_STOP) { - /* Clock activation.*/ -#if TIVA_GPT_USE_GPT0 - if (&GPTD1 == gptp) { - SYSCTL->RCGCTIMER |= (1 << 0); - - while (!(SYSCTL->PRTIMER & (1 << 0))) - ; - - nvicEnableVector(TIVA_GPT0A_NUMBER, TIVA_GPT_GPT0A_IRQ_PRIORITY); - } -#endif - -#if TIVA_GPT_USE_GPT1 - if (&GPTD2 == gptp) { - SYSCTL->RCGCTIMER |= (1 << 1); - - while (!(SYSCTL->PRTIMER & (1 << 1))) - ; - - nvicEnableVector(TIVA_GPT1A_NUMBER, TIVA_GPT_GPT1A_IRQ_PRIORITY); - } -#endif - -#if TIVA_GPT_USE_GPT2 - if (&GPTD3 == gptp) { - SYSCTL->RCGCTIMER |= (1 << 2); - - while (!(SYSCTL->PRTIMER & (1 << 2))) - ; - - nvicEnableVector(TIVA_GPT2A_NUMBER, TIVA_GPT_GPT2A_IRQ_PRIORITY); - } -#endif - -#if TIVA_GPT_USE_GPT3 - if (&GPTD4 == gptp) { - SYSCTL->RCGCTIMER |= (1 << 3); - - while (!(SYSCTL->PRTIMER & (1 << 3))) - ; - - nvicEnableVector(TIVA_GPT3A_NUMBER, TIVA_GPT_GPT3A_IRQ_PRIORITY); - } -#endif - -#if TIVA_GPT_USE_GPT4 - if (&GPTD5 == gptp) { - SYSCTL->RCGCTIMER |= (1 << 4); - - while (!(SYSCTL->PRTIMER & (1 << 4))) - ; - - nvicEnableVector(TIVA_GPT4A_NUMBER, TIVA_GPT_GPT4A_IRQ_PRIORITY); - } -#endif - -#if TIVA_GPT_USE_GPT5 - if (&GPTD6 == gptp) { - SYSCTL->RCGCTIMER |= (1 << 5); - - while (!(SYSCTL->PRTIMER & (1 << 5))) - ; - - nvicEnableVector(TIVA_GPT5A_NUMBER, TIVA_GPT_GPT5A_IRQ_PRIORITY); - } -#endif - -#if TIVA_GPT_USE_WGPT0 - if (&GPTD7 == gptp) { - SYSCTL->RCGCWTIMER |= (1 << 0); - - while (!(SYSCTL->PRWTIMER & (1 << 0))) - ; - - nvicEnableVector(TIVA_WGPT0A_NUMBER, TIVA_GPT_WGPT0A_IRQ_PRIORITY); - } -#endif - -#if TIVA_GPT_USE_WGPT1 - if (&GPTD8 == gptp) { - SYSCTL->RCGCWTIMER |= (1 << 1); - - while (!(SYSCTL->PRWTIMER & (1 << 1))) - ; - - nvicEnableVector(TIVA_WGPT1A_NUMBER, TIVA_GPT_WGPT1A_IRQ_PRIORITY); - } -#endif - -#if TIVA_GPT_USE_WGPT2 - if (&GPTD9 == gptp) { - SYSCTL->RCGCWTIMER |= (1 << 2); - - while (!(SYSCTL->PRWTIMER & (1 << 2))) - ; - - nvicEnableVector(TIVA_WGPT2A_NUMBER, TIVA_GPT_WGPT2A_IRQ_PRIORITY); - } -#endif - -#if TIVA_GPT_USE_WGPT3 - if (&GPTD10 == gptp) { - SYSCTL->RCGCWTIMER |= (1 << 3); - - while (!(SYSCTL->PRWTIMER & (1 << 3))) - ; - - nvicEnableVector(TIVA_WGPT3A_NUMBER, TIVA_GPT_WGPT3A_IRQ_PRIORITY); - } -#endif - -#if TIVA_GPT_USE_WGPT4 - if (&GPTD11 == gptp) { - SYSCTL->RCGCWTIMER |= (1 << 4); - - while (!(SYSCTL->PRWTIMER & (1 << 4))) - ; - - nvicEnableVector(TIVA_WGPT4A_NUMBER, TIVA_GPT_WGPT4A_IRQ_PRIORITY); - } -#endif - -#if TIVA_GPT_USE_WGPT5 - if (&GPTD12 == gptp) { - SYSCTL->RCGCWTIMER |= (1 << 5); - - while (!(SYSCTL->PRWTIMER & (1 << 5))) - ; - - nvicEnableVector(TIVA_WGPT5A_NUMBER, TIVA_GPT_WGPT5A_IRQ_PRIORITY); - } -#endif - } - - /* Timer configuration.*/ - gptp->gpt->CTL = 0; - gptp->gpt->CFG = GPTM_CFG_CFG_SPLIT; - gptp->gpt->TAPR = ((TIVA_SYSCLK / gptp->config->frequency) - 1); -} - -/** - * @brief Deactivates the GPT peripheral. - * - * @param[in] gptp pointer to the @p GPTDriver object - * - * @notapi - */ -void gpt_lld_stop(GPTDriver *gptp) -{ - if (gptp->state == GPT_READY) { - gptp->gpt->IMR = 0; - gptp->gpt->TAILR = 0; - gptp->gpt->CTL = 0; - -#if TIVA_GPT_USE_GPT0 - if (&GPTD1 == gptp) { - nvicDisableVector(TIVA_GPT0A_NUMBER); - SYSCTL->RCGCTIMER &= ~(1 << 0); - } -#endif - -#if TIVA_GPT_USE_GPT1 - if (&GPTD2 == gptp) { - nvicDisableVector(TIVA_GPT1A_NUMBER); - SYSCTL->RCGCTIMER &= ~(1 << 1); - } -#endif - -#if TIVA_GPT_USE_GPT2 - if (&GPTD3 == gptp) { - nvicDisableVector(TIVA_GPT2A_NUMBER); - SYSCTL->RCGCTIMER &= ~(1 << 2); - } -#endif - -#if TIVA_GPT_USE_GPT3 - if (&GPTD4 == gptp) { - nvicDisableVector(TIVA_GPT3A_NUMBER); - SYSCTL->RCGCTIMER &= ~(1 << 3); - } -#endif - -#if TIVA_GPT_USE_GPT4 - if (&GPTD5 == gptp) { - nvicDisableVector(TIVA_GPT4A_NUMBER); - SYSCTL->RCGCTIMER &= ~(1 << 4); - } -#endif - -#if TIVA_GPT_USE_GPT5 - if (&GPTD6 == gptp) { - nvicDisableVector(TIVA_GPT5A_NUMBER); - SYSCTL->RCGCTIMER &= ~(1 << 5); - } -#endif - -#if TIVA_GPT_USE_WGPT0 - if (&GPTD7 == gptp) { - nvicDisableVector(TIVA_WGPT0A_NUMBER); - SYSCTL->RCGCWTIMER &= ~(1 << 0); - } -#endif - -#if TIVA_GPT_USE_WGPT1 - if (&GPTD8 == gptp) { - nvicDisableVector(TIVA_WGPT1A_NUMBER); - SYSCTL->RCGCWTIMER &= ~(1 << 1); - } -#endif - -#if TIVA_GPT_USE_WGPT2 - if (&GPTD9 == gptp) { - nvicDisableVector(TIVA_WGPT2A_NUMBER); - SYSCTL->RCGCWTIMER &= ~(1 << 2); - } -#endif - -#if TIVA_GPT_USE_WGPT3 - if (&GPTD10 == gptp) { - nvicDisableVector(TIVA_WGPT3A_NUMBER); - SYSCTL->RCGCWTIMER &= ~(1 << 3); - } -#endif - -#if TIVA_GPT_USE_WGPT4 - if (&GPTD11 == gptp) { - nvicDisableVector(TIVA_WGPT4A_NUMBER); - SYSCTL->RCGCWTIMER &= ~(1 << 4); - } -#endif - -#if TIVA_GPT_USE_WGPT5 - if (&GPTD12 == gptp) { - nvicDisableVector(TIVA_WGPT5A_NUMBER); - SYSCTL->RCGCWTIMER &= ~(1 << 5); - } -#endif - } -} - -/** - * @brief Starts the timer in continuous mode. - * - * @param[in] gptp pointer to the @p GPTDriver object - * @param[in] interval period in ticks - * - * @notapi - */ -void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t interval) -{ - gptp->gpt->TAILR = interval - 1; - gptp->gpt->ICR = 0xfffffff; - gptp->gpt->IMR = GPTM_IMR_TATOIM; - gptp->gpt->TAMR = GPTM_TAMR_TAMR_PERIODIC | GPTM_TAMR_TAILD | GPTM_TAMR_TASNAPS; - gptp->gpt->CTL = GPTM_CTL_TAEN | GPTM_CTL_TASTALL; -} - -/** - * @brief Stops the timer. - * - * @param[in] gptp pointer to the @p GPTDriver object - * - * @notapi - */ -void gpt_lld_stop_timer(GPTDriver *gptp) -{ - gptp->gpt->IMR = 0; - gptp->gpt->TAILR = 0; - gptp->gpt->CTL &= ~GPTM_CTL_TAEN; -} - -/** - * @brief Starts the timer in one shot mode and waits for completion. - * @details This function specifically polls the timer waiting for completion - * in order to not have extra delays caused by interrupt servicing, - * this function is only recommended for short delays. - * - * @param[in] gptp pointer to the @p GPTDriver object - * @param[in] interval time interval in ticks - * - * @notapi - */ -void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval) -{ - gptp->gpt->TAMR = GPTM_TAMR_TAMR_ONESHOT | GPTM_TAMR_TAILD | GPTM_TAMR_TASNAPS; - gptp->gpt->TAILR = interval - 1; - gptp->gpt->ICR = 0xffffffff; - gptp->gpt->CTL = GPTM_CTL_TAEN | GPTM_CTL_TASTALL; - while (!(gptp->gpt->RIS & GPTM_IMR_TATOIM)) - ; - gptp->gpt->ICR = 0xffffffff; -} - -#endif /* HAL_USE_GPT */ - -/** @} */ diff --git a/os/hal/ports/TIVA/LLD/hal_gpt_lld.h b/os/hal/ports/TIVA/LLD/hal_gpt_lld.h deleted file mode 100644 index e518e58..0000000 --- a/os/hal/ports/TIVA/LLD/hal_gpt_lld.h +++ /dev/null @@ -1,501 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TIVA/gpt_lld.h - * @brief TM4C123x/TM4C129x GPT subsystem low level driver header. - * - * @addtogroup GPT - * @{ - */ - -#ifndef HAL_GPT_LLD_H -#define HAL_GPT_LLD_H - -#if HAL_USE_GPT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ - -/** - * @brief GPTD1 driver enable switch. - * @details If set to @p TRUE the support for GPTD1 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_GPT_USE_GPT0) || defined(__DOXYGEN__) -#define TIVA_GPT_USE_GPT0 FALSE -#endif - -/** - * @brief GPTD2 driver enable switch. - * @details If set to @p TRUE the support for GPTD2 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_GPT_USE_GPT1) || defined(__DOXYGEN__) -#define TIVA_GPT_USE_GPT1 FALSE -#endif - -/** - * @brief GPTD3 driver enable switch. - * @details If set to @p TRUE the support for GPTD3 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_GPT_USE_GPT2) || defined(__DOXYGEN__) -#define TIVA_GPT_USE_GPT2 FALSE -#endif - -/** - * @brief GPTD4 driver enable switch. - * @details If set to @p TRUE the support for GPTD4 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_GPT_USE_GPT3) || defined(__DOXYGEN__) -#define TIVA_GPT_USE_GPT3 FALSE -#endif - -/** - * @brief GPTD5 driver enable switch. - * @details If set to @p TRUE the support for GPTD5 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_GPT_USE_GPT4) || defined(__DOXYGEN__) -#define TIVA_GPT_USE_GPT4 FALSE -#endif - -/** - * @brief GPTD6 driver enable switch. - * @details If set to @p TRUE the support for GPTD6 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_GPT_USE_GPT5) || defined(__DOXYGEN__) -#define TIVA_GPT_USE_GPT5 FALSE -#endif - -/** - * @brief GPTD7 driver enable switch. - * @details If set to @p TRUE the support for GPTD1 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_GPT_USE_WGPT0) || defined(__DOXYGEN__) -#define TIVA_GPT_USE_WGPT0 FALSE -#endif - -/** - * @brief GPTD8 driver enable switch. - * @details If set to @p TRUE the support for GPTD2 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_GPT_USE_WGPT1) || defined(__DOXYGEN__) -#define TIVA_GPT_USE_WGPT1 FALSE -#endif - -/** - * @brief GPTD9 driver enable switch. - * @details If set to @p TRUE the support for GPTD3 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_GPT_USE_WGPT2) || defined(__DOXYGEN__) -#define TIVA_GPT_USE_WGPT2 FALSE -#endif - -/** - * @brief GPTD10 driver enable switch. - * @details If set to @p TRUE the support for GPTD4 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_GPT_USE_WGPT3) || defined(__DOXYGEN__) -#define TIVA_GPT_USE_WGPT3 FALSE -#endif - -/** - * @brief GPTD11 driver enable switch. - * @details If set to @p TRUE the support for GPTD5 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_GPT_USE_WGPT4) || defined(__DOXYGEN__) -#define TIVA_GPT_USE_WGPT4 FALSE -#endif - -/** - * @brief GPTD12 driver enable switch. - * @details If set to @p TRUE the support for GPTD6 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_GPT_USE_WGPT5) || defined(__DOXYGEN__) -#define TIVA_GPT_USE_WGPT5 FALSE -#endif - -/** - * @brief GPTD1 interrupt priority level setting. - */ -#if !defined(TIVA_GPT_GPT0A_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_GPT_GPT0A_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD2 interrupt priority level setting. - */ -#if !defined(TIVA_GPT_GPT1A_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_GPT_GPT1A_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD3 interrupt priority level setting. - */ -#if !defined(TIVA_GPT_GPT2A_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_GPT_GPT2A_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD4 interrupt priority level setting. - */ -#if !defined(TIVA_GPT_GPT3A_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_GPT_GPT3A_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD5 interrupt priority level setting. - */ -#if !defined(TIVA_GPT_GPT4A_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_GPT_GPT4A_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD6 interrupt priority level setting. - */ -#if !defined(TIVA_GPT_GPT5A_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_GPT_GPT5A_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD7 interrupt priority level setting. - */ -#if !defined(TIVA_GPT_WGPT0A_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_GPT_WGPT0A_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD8 interrupt priority level setting. - */ -#if !defined(TIVA_GPT_WGPT1A_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_GPT_WGPT1A_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD9 interrupt priority level setting. - */ -#if !defined(TIVA_GPT_WGPT2A_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_GPT_WGPT2A_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD10 interrupt priority level setting. - */ -#if !defined(TIVA_GPT_WGPT3A_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_GPT_WGPT3A_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD11 interrupt priority level setting. - */ -#if !defined(TIVA_GPT_WGPT4A_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_GPT_WGPT4A_IRQ_PRIORITY 7 -#endif - -/** - * @brief GPTD12 interrupt priority level setting. - */ -#if !defined(TIVA_GPT_WGPT5A_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_GPT_WGPT5A_IRQ_PRIORITY 7 -#endif - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if TIVA_GPT_USE_GPT0 && !TIVA_HAS_GPT0 -#error "GPT0 not present in the selected device" -#endif - -#if TIVA_GPT_USE_GPT1 && !TIVA_HAS_GPT1 -#error "GPT1 not present in the selected device" -#endif - -#if TIVA_GPT_USE_GPT2 && !TIVA_HAS_GPT2 -#error "GPT2 not present in the selected device" -#endif - -#if TIVA_GPT_USE_GPT3 && !TIVA_HAS_GPT3 -#error "GPT3 not present in the selected device" -#endif - -#if TIVA_GPT_USE_GPT4 && !TIVA_HAS_GPT4 -#error "GPT4 not present in the selected device" -#endif - -#if TIVA_GPT_USE_GPT5 && !TIVA_HAS_GPT5 -#error "GPT5 not present in the selected device" -#endif - -#if TIVA_GPT_USE_WGPT0 && !TIVA_HAS_WGPT0 -#error "WGPT0 not present in the selected device" -#endif - -#if TIVA_GPT_USE_WGPT1 && !TIVA_HAS_WGPT1 -#error "WGPT1 not present in the selected device" -#endif - -#if TIVA_GPT_USE_WGPT2 && !TIVA_HAS_WGPT2 -#error "WGPT2 not present in the selected device" -#endif - -#if TIVA_GPT_USE_WGPT3 && !TIVA_HAS_WGPT3 -#error "WGPT3 not present in the selected device" -#endif - -#if TIVA_GPT_USE_WGPT4 && !TIVA_HAS_WGPT4 -#error "WGPT4 not present in the selected device" -#endif - -#if TIVA_GPT_USE_WGPT5 && !TIVA_HAS_WGPT5 -#error "WGPT5 not present in the selected device" -#endif - -#if !TIVA_GPT_USE_GPT0 && !TIVA_GPT_USE_GPT1 && !TIVA_GPT_USE_GPT2 && \ - !TIVA_GPT_USE_GPT3 && !TIVA_GPT_USE_GPT4 && !TIVA_GPT_USE_GPT5 && \ - !TIVA_GPT_USE_WGPT0 && !TIVA_GPT_USE_WGPT1 && !TIVA_GPT_USE_WGPT2 && \ - !TIVA_GPT_USE_WGPT3 && !TIVA_GPT_USE_WGPT4 && !TIVA_GPT_USE_WGPT5 -#error "GPT driver activated but no (W)GPT peripheral assigned" -#endif - -#if TIVA_GPT_USE_GPT0 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_GPT0A_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPT0" -#endif - -#if TIVA_GPT_USE_GPT1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_GPT1A_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPT1" -#endif - -#if TIVA_GPT_USE_GPT2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_GPT2A_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPT2" -#endif - -#if TIVA_GPT_USE_GPT3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_GPT3A_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPT3" -#endif - -#if TIVA_GPT_USE_GPT4 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_GPT4A_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPT4" -#endif - -#if TIVA_GPT_USE_GPT5 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_GPT5A_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPT5" -#endif - -#if TIVA_GPT_USE_WGPT0 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_WGPT0A_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to WGPT0" -#endif - -#if TIVA_GPT_USE_WGPT1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_WGPT1A_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to WGPT1" -#endif - -#if TIVA_GPT_USE_WGPT2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_WGPT2A_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to WGPT2" -#endif - -#if TIVA_GPT_USE_WGPT3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_WGPT3A_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to WGPT3" -#endif - -#if TIVA_GPT_USE_WGPT4 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_WGPT4A_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to WGPT4" -#endif - -#if TIVA_GPT_USE_WGPT5 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_GPT_WGPT5A_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to WGPT5" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief GPT frequency type. - */ -typedef uint32_t gptfreq_t; - -/** - * @brief GPT counter type. - */ -typedef uint16_t gptcnt_t; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief Timer clock in Hz. - * @note The low level can use assertions in order to catch invalid - * frequency specifications. - */ - gptfreq_t frequency; - /** - * @brief Timer callback pointer. - * @note This callback is invoked on GPT counter events. - */ - gptcallback_t callback; - /* End of the mandatory fields.*/ -} GPTConfig; - -/** - * @brief Structure representing a GPT driver. - */ -struct GPTDriver { - /** - * @brief Driver state. - */ - gptstate_t state; - /** - * @brief Current configuration data. - */ - const GPTConfig *config; -#if defined(GPT_DRIVER_EXT_FIELDS) - GPT_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the GPT registers block. - */ - GPT_TypeDef *gpt; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Changes the interval of GPT peripheral. - * @details This function changes the interval of a running GPT unit. - * @pre The GPT unit must have been activated using @p gptStart(). - * @pre The GPT unit must have been running in continuous mode using - * @p gptStartContinuous(). - * @post The GPT unit interval is changed to the new value. - * @note The function has effect at the next cycle start. - * - * @param[in] gptp pointer to a @p GPTDriver object - * @param[in] interval new cycle time in timer ticks - * @notapi - */ -#define gpt_lld_change_interval(gptp, interval) { \ - gptp->gpt->TAILR = interval - 1; \ -} - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if TIVA_GPT_USE_GPT0 && !defined(__DOXYGEN__) -extern GPTDriver GPTD1; -#endif - -#if TIVA_GPT_USE_GPT1 && !defined(__DOXYGEN__) -extern GPTDriver GPTD2; -#endif - -#if TIVA_GPT_USE_GPT2 && !defined(__DOXYGEN__) -extern GPTDriver GPTD3; -#endif - -#if TIVA_GPT_USE_GPT3 && !defined(__DOXYGEN__) -extern GPTDriver GPTD4; -#endif - -#if TIVA_GPT_USE_GPT4 && !defined(__DOXYGEN__) -extern GPTDriver GPTD5; -#endif - -#if TIVA_GPT_USE_GPT5 && !defined(__DOXYGEN__) -extern GPTDriver GPTD6; -#endif - -#if TIVA_GPT_USE_WGPT0 && !defined(__DOXYGEN__) -extern GPTDriver GPTD7; -#endif - -#if TIVA_GPT_USE_WGPT1 && !defined(__DOXYGEN__) -extern GPTDriver GPTD8; -#endif - -#if TIVA_GPT_USE_WGPT2 && !defined(__DOXYGEN__) -extern GPTDriver GPTD9; -#endif - -#if TIVA_GPT_USE_WGPT3 && !defined(__DOXYGEN__) -extern GPTDriver GPTD10; -#endif - -#if TIVA_GPT_USE_WGPT4 && !defined(__DOXYGEN__) -extern GPTDriver GPTD11; -#endif - -#if TIVA_GPT_USE_WGPT5 && !defined(__DOXYGEN__) -extern GPTDriver GPTD12; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void gpt_lld_init(void); - void gpt_lld_start(GPTDriver *gptp); - void gpt_lld_stop(GPTDriver *gptp); - void gpt_lld_start_timer(GPTDriver *gptp, gptcnt_t period); - void gpt_lld_stop_timer(GPTDriver *gptp); - void gpt_lld_polled_delay(GPTDriver *gptp, gptcnt_t interval); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_GPT */ - -#endif /* HAL_GPT_LLD_H */ - -/** @} */ diff --git a/os/hal/ports/TIVA/LLD/hal_i2c_lld.c b/os/hal/ports/TIVA/LLD/hal_i2c_lld.c deleted file mode 100644 index cb69861..0000000 --- a/os/hal/ports/TIVA/LLD/hal_i2c_lld.c +++ /dev/null @@ -1,894 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TIVA/LLD/i2c_lld.c - * @brief TM4C123x/TM4C129x I2C subsystem low level driver source. - * - * @addtogroup I2C - * @{ - */ - -#include "hal.h" - -#if HAL_USE_I2C || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief I2C0 driver identifier. - */ -#if TIVA_I2C_USE_I2C0 || defined(__DOXYGEN__) -I2CDriver I2CD1; -#endif - -/** - * @brief I2C1 driver identifier. - */ -#if TIVA_I2C_USE_I2C1 || defined(__DOXYGEN__) -I2CDriver I2CD2; -#endif - -/** - * @brief I2C2 driver identifier. - */ -#if TIVA_I2C_USE_I2C2 || defined(__DOXYGEN__) -I2CDriver I2CD3; -#endif - -/** - * @brief I2C3 driver identifier. - */ -#if TIVA_I2C_USE_I2C3 || defined(__DOXYGEN__) -I2CDriver I2CD4; -#endif - -/** - * @brief I2C4 driver identifier. - */ -#if TIVA_I2C_USE_I2C4 || defined(__DOXYGEN__) -I2CDriver I2CD5; -#endif - -/** - * @brief I2C5 driver identifier. - */ -#if TIVA_I2C_USE_I2C5 || defined(__DOXYGEN__) -I2CDriver I2CD6; -#endif - -/** - * @brief I2C6 driver identifier. - */ -#if TIVA_I2C_USE_I2C6 || defined(__DOXYGEN__) -I2CDriver I2CD7; -#endif - -/** - * @brief I2C7 driver identifier. - */ -#if TIVA_I2C_USE_I2C7 || defined(__DOXYGEN__) -I2CDriver I2CD8; -#endif - -/** - * @brief I2C8 driver identifier. - */ -#if TIVA_I2C_USE_I2C8 || defined(__DOXYGEN__) -I2CDriver I2CD9; -#endif - -/** - * @brief I2C9 driver identifier. - */ -#if TIVA_I2C_USE_I2C9 || defined(__DOXYGEN__) -I2CDriver I2CD10; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief I2C shared ISR code. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -static void i2c_lld_serve_interrupt(I2CDriver *i2cp) -{ - I2C_TypeDef *dp = i2cp->i2c; - uint32_t status; - - // clear MIS bit in MICR by writing 1 - dp->MICR = 1; - - // read interrupt status - status = dp->MCS; - - if (status & TIVA_MCS_ERROR) { - i2cp->errors |= I2C_BUS_ERROR; - } - if (status & TIVA_MCS_ARBLST) { - i2cp->errors |= I2C_ARBITRATION_LOST; - } - - if (i2cp->errors == I2C_NO_ERROR) { - // no error detected - switch(i2cp->intstate) { - case STATE_IDLE: { - _i2c_wakeup_isr(i2cp); - break; - } - case STATE_WRITE_NEXT: { - if (i2cp->txbytes == 1) { - i2cp->intstate = STATE_WRITE_FINAL; - } - dp->MDR = *(i2cp->txbuf); - i2cp->txbuf++; - i2cp->txbytes--; - // start transmission - dp->MCS = TIVA_I2C_BURST_SEND_CONTINUE; - break; - } - case STATE_WRITE_FINAL: { - if (i2cp->rxbytes == 0) { - i2cp->intstate = STATE_IDLE; - } - else if (i2cp->rxbytes == 1) { - i2cp->intstate = STATE_READ_ONE; - } - else { - i2cp->intstate = STATE_READ_FIRST; - } - dp->MDR = *(i2cp->txbuf); - i2cp->txbuf++; - // txbytes - 1 - i2cp->txbytes--; - // start transmission - dp->MCS = TIVA_I2C_BURST_SEND_FINISH; - break; - } - case STATE_WAIT_ACK: { - break; - } - case STATE_SEND_ACK: { - break; - } - case STATE_READ_ONE: { - i2cp->intstate = STATE_READ_WAIT; - // Initializes driver fields, LSB = 1 -> read. - i2cp->addr |= 1; - - // set slave address - dp->MSA = i2cp->addr; - i2cp->rxbytes--; - //start receiving - dp->MCS = TIVA_I2C_SINGLE_RECEIVE; - - break; - } - case STATE_READ_FIRST: { - if (i2cp->rxbytes == 2) { - i2cp->intstate = STATE_READ_FINAL; - } - else { - i2cp->intstate = STATE_READ_NEXT; - } - - // Initializes driver fields, LSB = 1 -> read. - i2cp->addr |= 1; - - // set slave address - dp->MSA = i2cp->addr; - i2cp->rxbytes--; - //start receiving - dp->MCS = TIVA_I2C_BURST_RECEIVE_START; - - break; - } - case STATE_READ_NEXT: { - if(i2cp->rxbytes == 2) { - i2cp->intstate = STATE_READ_FINAL; - } - *(i2cp->rxbuf) = dp->MDR; - i2cp->rxbuf++; - i2cp->rxbytes--; - //start receiving - dp->MCS = TIVA_I2C_BURST_RECEIVE_CONTINUE; - - break; - } - case STATE_READ_FINAL: { - i2cp->intstate = STATE_READ_WAIT; - *(i2cp->rxbuf) = dp->MDR; - i2cp->rxbuf++; - i2cp->rxbytes--; - //start receiving - dp->MCS = TIVA_I2C_BURST_RECEIVE_FINISH; - - break; - } - case STATE_READ_WAIT: { - i2cp->intstate = STATE_IDLE; - *(i2cp->rxbuf) = dp->MDR; - i2cp->rxbuf++; - _i2c_wakeup_isr(i2cp); - break; - } - } - } - else { - // error detected - _i2c_wakeup_error_isr(i2cp); - } -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if TIVA_I2C_USE_I2C0 || defined(__DOXYGEN__) -/** - * @brief I2C0 interrupt handler. - * - * @notapi - */ -OSAL_IRQ_HANDLER(TIVA_I2C0_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - i2c_lld_serve_interrupt(&I2CD1); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* TIVA_I2C_USE_I2C0 */ - -#if TIVA_I2C_USE_I2C1 || defined(__DOXYGEN__) -/** - * @brief I2C1 interrupt handler. - * - * @notapi - */ -OSAL_IRQ_HANDLER(TIVA_I2C1_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - i2c_lld_serve_interrupt(&I2CD2); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* TIVA_I2C_USE_I2C1 */ - -#if TIVA_I2C_USE_I2C2 || defined(__DOXYGEN__) -/** - * @brief I2C2 interrupt handler. - * - * @notapi - */ -OSAL_IRQ_HANDLER(TIVA_I2C2_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - i2c_lld_serve_interrupt(&I2CD3); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* TIVA_I2C_USE_I2C2 */ - -#if TIVA_I2C_USE_I2C3 || defined(__DOXYGEN__) -/** - * @brief I2C3 interrupt handler. - * - * @notapi - */ -OSAL_IRQ_HANDLER(TIVA_I2C3_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - i2c_lld_serve_interrupt(&I2CD4); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* TIVA_I2C_USE_I2C3 */ - -#if TIVA_I2C_USE_I2C4 || defined(__DOXYGEN__) -/** - * @brief I2C4 interrupt handler. - * - * @notapi - */ -OSAL_IRQ_HANDLER(TIVA_I2C4_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - i2c_lld_serve_interrupt(&I2CD5); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* TIVA_I2C_USE_I2C4 */ - -#if TIVA_I2C_USE_I2C5 || defined(__DOXYGEN__) -/** - * @brief I2C5 interrupt handler. - * - * @notapi - */ -OSAL_IRQ_HANDLER(TIVA_I2C5_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - i2c_lld_serve_interrupt(&I2CD6); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* TIVA_I2C_USE_I2C5 */ - -#if TIVA_I2C_USE_I2C6 || defined(__DOXYGEN__) -/** - * @brief I2C6 interrupt handler. - * - * @notapi - */ -OSAL_IRQ_HANDLER(TIVA_I2C6_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - i2c_lld_serve_interrupt(&I2CD7); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* TIVA_I2C_USE_I2C6 */ - -#if TIVA_I2C_USE_I2C7 || defined(__DOXYGEN__) -/** - * @brief I2C7 interrupt handler. - * - * @notapi - */ -OSAL_IRQ_HANDLER(TIVA_I2C7_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - i2c_lld_serve_interrupt(&I2CD8); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* TIVA_I2C_USE_I2C7 */ - -#if TIVA_I2C_USE_I2C8 || defined(__DOXYGEN__) -/** - * @brief I2C8 interrupt handler. - * - * @notapi - */ -OSAL_IRQ_HANDLER(TIVA_I2C8_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - i2c_lld_serve_interrupt(&I2CD9); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* TIVA_I2C_USE_I2C8 */ - -#if TIVA_I2C_USE_I2C9 || defined(__DOXYGEN__) -/** - * @brief I2C9 interrupt handler. - * - * @notapi - */ -OSAL_IRQ_HANDLER(TIVA_I2C9_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - i2c_lld_serve_interrupt(&I2CD10); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* TIVA_I2C_USE_I2C9 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level I2C driver initialization. - * - * @notapi - */ -void i2c_lld_init(void) { - -#if TIVA_I2C_USE_I2C0 - i2cObjectInit(&I2CD1); - I2CD1.thread = NULL; - I2CD1.i2c = I2C0; -#endif /* TIVA_I2C_USE_I2C0 */ - -#if TIVA_I2C_USE_I2C1 - i2cObjectInit(&I2CD2); - I2CD2.thread = NULL; - I2CD2.i2c = I2C1; -#endif /* TIVA_I2C_USE_I2C1 */ - -#if TIVA_I2C_USE_I2C2 - i2cObjectInit(&I2CD3); - I2CD3.thread = NULL; - I2CD3.i2c = I2C2; -#endif /* TIVA_I2C_USE_I2C2 */ - -#if TIVA_I2C_USE_I2C3 - i2cObjectInit(&I2CD4); - I2CD4.thread = NULL; - I2CD4.i2c = I2C3; -#endif /* TIVA_I2C_USE_I2C3 */ - -#if TIVA_I2C_USE_I2C4 - i2cObjectInit(&I2CD5); - I2CD5.thread = NULL; - I2CD5.i2c = I2C4; -#endif /* TIVA_I2C_USE_I2C4 */ - -#if TIVA_I2C_USE_I2C5 - i2cObjectInit(&I2CD6); - I2CD6.thread = NULL; - I2CD6.i2c = I2C5; -#endif /* TIVA_I2C_USE_I2C5 */ - -#if TIVA_I2C_USE_I2C6 - i2cObjectInit(&I2CD7); - I2CD7.thread = NULL; - I2CD7.i2c = I2C6; -#endif /* TIVA_I2C_USE_I2C6 */ - -#if TIVA_I2C_USE_I2C7 - i2cObjectInit(&I2CD8); - I2CD8.thread = NULL; - I2CD8.i2c = I2C7; -#endif /* TIVA_I2C_USE_I2C7 */ - -#if TIVA_I2C_USE_I2C8 - i2cObjectInit(&I2CD9); - I2CD9.thread = NULL; - I2CD9.i2c = I2C8; -#endif /* TIVA_I2C_USE_I2C8 */ - -#if TIVA_I2C_USE_I2C9 - i2cObjectInit(&I2CD10); - I2CD10.thread = NULL; - I2CD10.i2c = I2C9; -#endif /* TIVA_I2C_USE_I2C9 */ -} - -/** - * @brief Configures and activates the I2C peripheral. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -void i2c_lld_start(I2CDriver *i2cp) -{ - I2C_TypeDef *dp = i2cp->i2c; - - /* If in stopped state then enables the I2C clocks.*/ - if (i2cp->state == I2C_STOP) { -#if TIVA_I2C_USE_I2C0 - if (&I2CD1 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 0); - - while (!(SYSCTL->PRI2C & (1 << 0))) - ; - - nvicEnableVector(TIVA_I2C0_NUMBER, TIVA_I2C_I2C0_IRQ_PRIORITY); - } -#endif /* TIVA_I2C_USE_I2C0 */ - -#if TIVA_I2C_USE_I2C1 - if (&I2CD2 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 1); - - while (!(SYSCTL->PRI2C & (1 << 1))) - ; - - nvicEnableVector(TIVA_I2C1_NUMBER, TIVA_I2C_I2C1_IRQ_PRIORITY); - } -#endif /* TIVA_I2C_USE_I2C1 */ - -#if TIVA_I2C_USE_I2C2 - if (&I2CD3 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 2); - - while (!(SYSCTL->PRI2C & (1 << 2))) - ; - - nvicEnableVector(TIVA_I2C2_NUMBER, TIVA_I2C_I2C2_IRQ_PRIORITY); - } -#endif /* TIVA_I2C_USE_I2C2 */ - -#if TIVA_I2C_USE_I2C3 - if (&I2CD4 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 3); - - while (!(SYSCTL->PRI2C & (1 << 3))) - ; - - nvicEnableVector(TIVA_I2C3_NUMBER, TIVA_I2C_I2C3_IRQ_PRIORITY); - } -#endif /* TIVA_I2C_USE_I2C3 */ - -#if TIVA_I2C_USE_I2C4 - if (&I2CD5 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 4); - - while (!(SYSCTL->PRI2C & (1 << 4))) - ; - - nvicEnableVector(TIVA_I2C4_NUMBER, TIVA_I2C_I2C4_IRQ_PRIORITY); - } -#endif /* TIVA_I2C_USE_I2C4 */ - -#if TIVA_I2C_USE_I2C5 - if (&I2CD6 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 5); - - while (!(SYSCTL->PRI2C & (1 << 5))) - ; - - nvicEnableVector(TIVA_I2C5_NUMBER, TIVA_I2C_I2C5_IRQ_PRIORITY); - } -#endif /* TIVA_I2C_USE_I2C5 */ - -#if TIVA_I2C_USE_I2C6 - if (&I2CD7 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 6); - - while (!(SYSCTL->PRI2C & (1 << 6))) - ; - - nvicEnableVector(TIVA_I2C6_NUMBER, TIVA_I2C_I2C6_IRQ_PRIORITY); - } -#endif /* TIVA_I2C_USE_I2C6 */ - -#if TIVA_I2C_USE_I2C7 - if (&I2CD8 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 7); - - while (!(SYSCTL->PRI2C & (1 << 7))) - ; - - nvicEnableVector(TIVA_I2C7_NUMBER, TIVA_I2C_I2C7_IRQ_PRIORITY); - } -#endif /* TIVA_I2C_USE_I2C7 */ - -#if TIVA_I2C_USE_I2C8 - if (&I2CD9 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 8); - - while (!(SYSCTL->PRI2C & (1 << 8))) - ; - - nvicEnableVector(TIVA_I2C8_NUMBER, TIVA_I2C_I2C8_IRQ_PRIORITY); - } -#endif /* TIVA_I2C_USE_I2C7 */ - -#if TIVA_I2C_USE_I2C9 - if (&I2CD10 == i2cp) { - SYSCTL->RCGCI2C |= (1 << 9); - - while (!(SYSCTL->PRI2C & (1 << 9))) - ; - - nvicEnableVector(TIVA_I2C9_NUMBER, TIVA_I2C_I2C9_IRQ_PRIORITY); - } -#endif /* TIVA_I2C_USE_I2C7 */ - } - - dp->MCR = 0x10; - dp->MTPR = MTPR_VALUE; -} - -/** - * @brief Deactivates the I2C peripheral. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -void i2c_lld_stop(I2CDriver *i2cp) -{ - I2C_TypeDef *dp = i2cp->i2c; - /* If not in stopped state then disables the I2C clock.*/ - if (i2cp->state != I2C_STOP) { - - /* I2C disable.*/ - // TODO: abort i2c operation - //i2c_lld_abort_operation(i2cp); - -#if TIVA_I2C_USE_I2C0 - if (&I2CD1 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 0); - nvicDisableVector(TIVA_I2C0_NUMBER); - } -#endif /* TIVA_I2C_USE_I2C0 */ - -#if TIVA_I2C_USE_I2C1 - if (&I2CD2 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 1); - nvicDisableVector(TIVA_I2C1_NUMBER); - } -#endif /* TIVA_I2C_USE_I2C1 */ - -#if TIVA_I2C_USE_I2C2 - if (&I2CD3 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 2); - nvicDisableVector(TIVA_I2C2_NUMBER); - } -#endif /* TIVA_I2C_USE_I2C2 */ - -#if TIVA_I2C_USE_I2C3 - if (&I2CD4 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 3); - nvicDisableVector(TIVA_I2C3_NUMBER); - } -#endif /* TIVA_I2C_USE_I2C3 */ - -#if TIVA_I2C_USE_I2C4 - if (&I2CD5 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 4); - nvicDisableVector(TIVA_I2C4_NUMBER); - } -#endif /* TIVA_I2C_USE_I2C4 */ - -#if TIVA_I2C_USE_I2C5 - if (&I2CD6 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 5); - nvicDisableVector(TIVA_I2C5_NUMBER); - } -#endif /* TIVA_I2C_USE_I2C5 */ - -#if TIVA_I2C_USE_I2C6 - if (&I2CD7 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 6); - nvicDisableVector(TIVA_I2C6_NUMBER); - } -#endif /* TIVA_I2C_USE_I2C6 */ - -#if TIVA_I2C_USE_I2C7 - if (&I2CD8 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 7); - nvicDisableVector(TIVA_I2C7_NUMBER); - } -#endif /* TIVA_I2C_USE_I2C7 */ - -#if TIVA_I2C_USE_I2C8 - if (&I2CD9 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 8); - nvicDisableVector(TIVA_I2C8_NUMBER); - } -#endif /* TIVA_I2C_USE_I2C8 */ - -#if TIVA_I2C_USE_I2C9 - if (&I2CD10 == i2cp) { - SYSCTL->RCGCI2C &= ~(1 << 9); - nvicDisableVector(TIVA_I2C9_NUMBER); - } -#endif /* TIVA_I2C_USE_I2C9 */ - - dp->MCR = 0; - dp->MTPR = 0; - } -} - -/** - * @brief Receives data via the I2C bus as master. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] addr slave device address - * @param[out] rxbuf pointer to the receive buffer - * @param[in] rxbytes number of bytes to be received - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval RDY_OK if the function succeeded. - * @retval RDY_RESET if one or more I2C errors occurred, the errors can - * be retrieved using @p i2cGetErrors(). - * @retval RDY_TIMEOUT if a timeout occurred before operation end. After a - * timeout the driver must be stopped and restarted - * because the bus is in an uncertain state. - * - * @notapi - */ -msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, - uint8_t *rxbuf, size_t rxbytes, - systime_t timeout) -{ - I2C_TypeDef *dp = i2cp->i2c; - systime_t start, end; - - i2cp->rxbuf = rxbuf; - i2cp->rxbytes = rxbytes; - - /* Resetting error flags for this transfer.*/ - i2cp->errors = I2C_NO_ERROR; - - /* Initializes driver fields, LSB = 1 -> receive.*/ - i2cp->addr = (addr << 1) | 0x01; - - /* Releases the lock from high level driver.*/ - osalSysUnlock(); - - /* Calculating the time window for the timeout on the busy bus condition.*/ - start = osalOsGetSystemTimeX(); - end = start + OSAL_MS2ST(TIVA_I2C_BUSY_TIMEOUT); - - /* Waits until BUSY flag is reset or, alternatively, for a timeout - condition.*/ - while (true) { - osalSysLock(); - - /* If the bus is not busy then the operation can continue, note, the - loop is exited in the locked state.*/ - if ((dp->MCS & TIVA_MCS_BUSY) == 0) - break; - - /* If the system time went outside the allowed window then a timeout - condition is returned.*/ - if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), start, end)) - return MSG_TIMEOUT; - - osalSysUnlock(); - } - - /* set slave address */ - dp->MSA = addr; - - /* Starts the operation.*/ - dp->MCS = TIVA_I2C_SINGLE_RECEIVE; - - /* Waits for the operation completion or a timeout.*/ - return osalThreadSuspendTimeoutS(&i2cp->thread, timeout); -} - -/** - * @brief Transmits data via the I2C bus as master. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * @param[in] addr slave device address - * @param[in] txbuf pointer to the transmit buffer - * @param[in] txbytes number of bytes to be transmitted - * @param[out] rxbuf pointer to the receive buffer - * @param[in] rxbytes number of bytes to be received - * @param[in] timeout the number of ticks before the operation timeouts, - * the following special values are allowed: - * - @a TIME_INFINITE no timeout. - * . - * @return The operation status. - * @retval RDY_OK if the function succeeded. - * @retval RDY_RESET if one or more I2C errors occurred, the errors can - * be retrieved using @p i2cGetErrors(). - * @retval RDY_TIMEOUT if a timeout occurred before operation end. After a - * timeout the driver must be stopped and restarted - * because the bus is in an uncertain state. - * - * @notapi - */ -msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, - const uint8_t *txbuf, size_t txbytes, - uint8_t *rxbuf, size_t rxbytes, - systime_t timeout) -{ - I2C_TypeDef *dp = i2cp->i2c; - systime_t start, end; - - i2cp->rxbuf = rxbuf; - i2cp->rxbytes = rxbytes; - i2cp->txbuf = txbuf; - i2cp->txbytes = txbytes; - - /* Resetting error flags for this transfer.*/ - i2cp->errors = I2C_NO_ERROR; - - /* Releases the lock from high level driver.*/ - osalSysUnlock(); - - /* Calculating the time window for the timeout on the busy bus condition.*/ - start = osalOsGetSystemTimeX(); - end = start + OSAL_MS2ST(TIVA_I2C_BUSY_TIMEOUT); - - /* Waits until BUSY flag is reset or, alternatively, for a timeout - condition.*/ - while (true) { - osalSysLock(); - - /* If the bus is not busy then the operation can continue, note, the - loop is exited in the locked state.*/ - if ((dp->MCS & TIVA_MCS_BUSY) == 0) - break; - - /* If the system time went outside the allowed window then a timeout - condition is returned.*/ - if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), start, end)) - return MSG_TIMEOUT; - - osalSysUnlock(); - } - - /* Initializes driver fields, LSB = 0 -> write.*/ - i2cp->addr = addr << 1 | 0; - - /* set slave address */ - dp->MSA = i2cp->addr; - - /* enable interrupts */ - dp->MIMR = TIVA_MIMR_IM; - - /* put data in register */ - dp->MDR = *(i2cp->txbuf); - - /* check if 1 or more bytes */ - if (i2cp->txbytes == 1) { - if (i2cp->rxbytes == 1) { - // one byte read - i2cp->intstate = STATE_READ_ONE; - } - else { - // multiple byte read - i2cp->intstate = STATE_READ_FIRST; - } - // single byte send - dp->MCS = TIVA_I2C_SIGNLE_SEND; - } - else { - if (i2cp->txbytes == 2) { - // 2 bytes - i2cp->intstate = STATE_WRITE_FINAL; - } - else { - // more then 2 bytes - i2cp->intstate = STATE_WRITE_NEXT; - } - // multiple bytes start send - dp->MCS = TIVA_I2C_BURST_SEND_START; - } - - i2cp->txbuf++; - i2cp->txbytes--; - - /* Waits for the operation completion or a timeout.*/ - return osalThreadSuspendTimeoutS(&i2cp->thread, timeout); -} - -#endif /* HAL_USE_I2C */ - -/** @} */ diff --git a/os/hal/ports/TIVA/LLD/hal_i2c_lld.h b/os/hal/ports/TIVA/LLD/hal_i2c_lld.h deleted file mode 100644 index 460d231..0000000 --- a/os/hal/ports/TIVA/LLD/hal_i2c_lld.h +++ /dev/null @@ -1,527 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TIVA/LLD/i2c_lld.h - * @brief TM4C123x/TM4C129x I2C subsystem low level driver header. - * - * @addtogroup I2C - * @{ - */ - -#ifndef HAL_I2C_LLD_H -#define HAL_I2C_LLD_H - -#if HAL_USE_I2C || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define MTPR_VALUE ((TIVA_SYSCLK/(2*(6+4)*i2cp->config->clock_speed))-1) - -#define TIVA_MSA_RS (1 << 0) -#define TIVA_MSA_SA (127 << 1) - -#define TIVA_MCS_BUSY (1 << 0) -#define TIVA_MCS_ERROR (1 << 1) -#define TIVA_MCS_ADRACK (1 << 2) -#define TIVA_MCS_DATACK (1 << 3) -#define TIVA_MCS_ARBLST (1 << 4) -#define TIVA_MCS_IDLE (1 << 5) -#define TIVA_MCS_BUSBSY (1 << 6) -#define TIVA_MCS_CLKTO (1 << 7) - -#define TIVA_MCS_RUN (1 << 0) -#define TIVA_MCS_START (1 << 1) -#define TIVA_MCS_STOP (1 << 2) -#define TIVA_MCS_ACK (1 << 3) -#define TIVA_MCS_HS (1 << 4) - -#define TIVA_I2C_SIGNLE_SEND (TIVA_MCS_RUN | TIVA_MCS_START | TIVA_MCS_STOP) -#define TIVA_I2C_BURST_SEND_START (TIVA_MCS_RUN | TIVA_MCS_START) -#define TIVA_I2C_BURST_SEND_CONTINUE (TIVA_MCS_RUN) -#define TIVA_I2C_BURST_SEND_FINISH (TIVA_MCS_RUN | TIVA_MCS_STOP) -#define TIVA_I2C_BURST_SEND_STOP (TIVA_MCS_STOP) -#define TIVA_I2C_BURST_SEND_ERROR_STOP (TIVA_MCS_STOP) - -#define TIVA_I2C_SINGLE_RECEIVE (TIVA_MCS_RUN | TIVA_MCS_START | TIVA_MCS_STOP) -#define TIVA_I2C_BURST_RECEIVE_START (TIVA_MCS_RUN | TIVA_MCS_START | TIVA_MCS_ACK) -#define TIVA_I2C_BURST_RECEIVE_CONTINUE (TIVA_MCS_RUN | TIVA_MCS_ACK) -#define TIVA_I2C_BURST_RECEIVE_FINISH (TIVA_MCS_RUN | TIVA_MCS_STOP) -#define TIVA_I2C_BURST_RECEIVE_ERROR_STOP (TIVA_MCS_STOP) - -#define TIVA_MDR_DATA (255 << 0) - -#define TIVA_MTPR_TPR (127 << 0) -#define TIVA_MTPR_HS (1 << 7) - -#define TIVA_MIMR_IM (1 << 0) -#define TIVA_MIMR_CLKIM (1 << 1) - -#define TIVA_MRIS_RIS (1 << 0) -#define TIVA_MRIS_CLKRIS (1 << 1) - -#define TIVA_MMIS_MIS (1 << 0) -#define TIVA_MMIS_CLKMIS (1 << 1) - -#define TIVA_MICR_IC (1 << 0) -#define TIVA_MICR_CLKIC (1 << 1) - -#define TIVA_MCR_LPBK (1 << 0) -#define TIVA_MCR_MFE (1 << 4) -#define TIVA_MCR_SFE (1 << 5) -#define TIVA_MCR_GFE (1 << 6) - -#define TIVA_MCLKOCNT_CNTL (255 << 0) - -#define TIVA_MBMON_SCL (1 << 0) -#define TIVA_MBMON_SDA (1 << 1) - -#define TIVA_MCR2_GFPW (7 << 4) - -// interrupt states -#define STATE_IDLE 0 -#define STATE_WRITE_NEXT 1 -#define STATE_WRITE_FINAL 2 -#define STATE_WAIT_ACK 3 -#define STATE_SEND_ACK 4 -#define STATE_READ_ONE 5 -#define STATE_READ_FIRST 6 -#define STATE_READ_NEXT 7 -#define STATE_READ_FINAL 8 -#define STATE_READ_WAIT 9 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ - -/** - * @brief I2C0 driver enable switch. - * @details If set to @p TRUE the support for I2C0 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_I2C_USE_I2C0) || defined(__DOXYGEN__) -#define TIVA_I2C_USE_I2C0 FALSE -#endif - -/** - * @brief I2C1 driver enable switch. - * @details If set to @p TRUE the support for I2C1 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_I2C_USE_I2C1) || defined(__DOXYGEN__) -#define TIVA_I2C_USE_I2C1 FALSE -#endif - -/** - * @brief I2C2 driver enable switch. - * @details If set to @p TRUE the support for I2C2 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_I2C_USE_I2C2) || defined(__DOXYGEN__) -#define TIVA_I2C_USE_I2C2 FALSE -#endif - -/** - * @brief I2C3 driver enable switch. - * @details If set to @p TRUE the support for I2C3 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_I2C_USE_I2C3) || defined(__DOXYGEN__) -#define TIVA_I2C_USE_I2C3 FALSE -#endif - -/** - * @brief I2C4 driver enable switch. - * @details If set to @p TRUE the support for I2C4 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_I2C_USE_I2C4) || defined(__DOXYGEN__) -#define TIVA_I2C_USE_I2C4 FALSE -#endif - -/** - * @brief I2C5 driver enable switch. - * @details If set to @p TRUE the support for I2C5 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_I2C_USE_I2C5) || defined(__DOXYGEN__) -#define TIVA_I2C_USE_I2C5 FALSE -#endif - -/** - * @brief I2C6 driver enable switch. - * @details If set to @p TRUE the support for I2C6 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_I2C_USE_I2C6) || defined(__DOXYGEN__) -#define TIVA_I2C_USE_I2C6 FALSE -#endif - -/** - * @brief I2C7 driver enable switch. - * @details If set to @p TRUE the support for I2C7 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_I2C_USE_I2C7) || defined(__DOXYGEN__) -#define TIVA_I2C_USE_I2C7 FALSE -#endif - -/** - * @brief I2C8 driver enable switch. - * @details If set to @p TRUE the support for I2C8 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_I2C_USE_I2C8) || defined(__DOXYGEN__) -#define TIVA_I2C_USE_I2C8 FALSE -#endif - -/** - * @brief I2C9 driver enable switch. - * @details If set to @p TRUE the support for I2C9 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_I2C_USE_I2C9) || defined(__DOXYGEN__) -#define TIVA_I2C_USE_I2C9 FALSE -#endif - -/** - * @brief I2C timeout on busy condition in milliseconds. - */ -#if !defined(TIVA_I2C_BUSY_TIMEOUT) || defined(__DOXYGEN__) -#define TIVA_I2C_BUSY_TIMEOUT 50 -#endif - -/** - * @brief I2C0 interrupt priority level setting. - */ -#if !defined(TIVA_I2C_I2C0_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_I2C_I2C0_IRQ_PRIORITY 4 -#endif - -/** - * @brief I2C1 interrupt priority level setting. - */ -#if !defined(TIVA_I2C_I2C1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_I2C_I2C1_IRQ_PRIORITY 4 -#endif - -/** - * @brief I2C2 interrupt priority level setting. - */ -#if !defined(TIVA_I2C_I2C2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_I2C_I2C2_IRQ_PRIORITY 4 -#endif - -/** - * @brief I2C3 interrupt priority level setting. - */ -#if !defined(TIVA_I2C_I2C3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_I2C_I2C3_IRQ_PRIORITY 4 -#endif - -/** - * @brief I2C4 interrupt priority level setting. - */ -#if !defined(TIVA_I2C_I2C4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_I2C_I2C4_IRQ_PRIORITY 4 -#endif - -/** - * @brief I2C5 interrupt priority level setting. - */ -#if !defined(TIVA_I2C_I2C5_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_I2C_I2C5_IRQ_PRIORITY 4 -#endif - -/** - * @brief I2C6 interrupt priority level setting. - */ -#if !defined(TIVA_I2C_I2C6_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_I2C_I2C6_IRQ_PRIORITY 4 -#endif - -/** - * @brief I2C7 interrupt priority level setting. - */ -#if !defined(TIVA_I2C_I2C7_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_I2C_I2C7_IRQ_PRIORITY 4 -#endif - -/** - * @brief I2C8 interrupt priority level setting. - */ -#if !defined(TIVA_I2C_I2C8_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_I2C_I2C8_IRQ_PRIORITY 4 -#endif - -/** - * @brief I2C9 interrupt priority level setting. - */ -#if !defined(TIVA_I2C_I2C9_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_I2C_I2C9_IRQ_PRIORITY 4 -#endif - -/** - * @} - */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/** - * @brief error checks - */ -#if !TIVA_I2C_USE_I2C0 && !TIVA_I2C_USE_I2C1 && !TIVA_I2C_USE_I2C2 && \ - !TIVA_I2C_USE_I2C3 && !TIVA_I2C_USE_I2C4 && !TIVA_I2C_USE_I2C5 && \ - !TIVA_I2C_USE_I2C6 && !TIVA_I2C_USE_I2C7 && !TIVA_I2C_USE_I2C8 && \ - !TIVA_I2C_USE_I2C9 -#error "I2C driver activated but no I2C peripheral assigned" -#endif - -#if TIVA_I2C_USE_I2C0 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C0_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to I2C0" -#endif - -#if TIVA_I2C_USE_I2C1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to I2C1" -#endif - -#if TIVA_I2C_USE_I2C2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to I2C2" -#endif - -#if TIVA_I2C_USE_I2C3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to I2C3" -#endif - -#if TIVA_I2C_USE_I2C4 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C4_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to I2C4" -#endif - -#if TIVA_I2C_USE_I2C5 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C5_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to I2C5" -#endif - -#if TIVA_I2C_USE_I2C6 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C6_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to I2C6" -#endif - -#if TIVA_I2C_USE_I2C7 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C7_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to I2C7" -#endif - -#if TIVA_I2C_USE_I2C8 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C8_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to I2C8" -#endif - -#if TIVA_I2C_USE_I2C9 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_I2C_I2C9_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to I2C9" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type representing I2C address. - */ -typedef uint16_t i2caddr_t; - -/** - * @brief I2C Driver condition flags type. - */ -typedef uint32_t i2cflags_t; - -/** - * @brief Driver configuration structure. - */ -typedef struct -{ - /** - * @brief Specifies the clock frequency. - * @note Must be set to a value lower than 3.33Mbps. - * TODO: high-speed mode: 3333 kHz. setup is 100-400-1000 kHz then switched to 3333 kHz - */ - uint32_t clock_speed; -} I2CConfig; - -/** - * @brief Type of a structure representing an I2C driver. - */ -typedef struct I2CDriver I2CDriver; - -/** - * @brief Structure representing an I2C driver. - */ -struct I2CDriver { - /** - * @brief Driver state. - */ - i2cstate_t state; - /** - * @brief Current configuration data. - */ - const I2CConfig *config; - /** - * @brief Error flags. - */ - i2cflags_t errors; -#if I2C_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the bus. - */ - mutex_t mutex; -#endif /* I2C_USE_MUTUAL_EXCLUSION */ -#if defined(I2C_DRIVER_EXT_FIELDS) - I2C_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Thread waiting for I/O completion. - */ - thread_reference_t thread; - /** - * @brief Current slave address without R/W bit. - */ - i2caddr_t addr; - /** - * @brief Pointer to the buffer with data to send. - */ - const uint8_t *txbuf; - /** - * @brief Number of bytes of data to send. - */ - size_t txbytes; - /** - * @brief Pointer to the buffer to put received data. - */ - uint8_t *rxbuf; - /** - * @brief Number of bytes of data to receive. - */ - size_t rxbytes; - /** - * @brief State of the interrupt state machine. - * - * TODO is it possible to remove the interrupt state? - */ - uint8_t intstate; - /** - * @brief Pointer to the I2Cx registers block. - */ - I2C_TypeDef *i2c; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Get errors from I2C driver. - * - * @param[in] i2cp pointer to the @p I2CDriver object - * - * @notapi - */ -#define i2c_lld_get_errors(i2cp) ((i2cp)->errors) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -#if TIVA_I2C_USE_I2C0 -extern I2CDriver I2CD1; -#endif - -#if TIVA_I2C_USE_I2C1 -extern I2CDriver I2CD2; -#endif - -#if TIVA_I2C_USE_I2C2 -extern I2CDriver I2CD3; -#endif - -#if TIVA_I2C_USE_I2C3 -extern I2CDriver I2CD4; -#endif - -#if TIVA_I2C_USE_I2C4 -extern I2CDriver I2CD5; -#endif - -#if TIVA_I2C_USE_I2C5 -extern I2CDriver I2CD6; -#endif - -#if TIVA_I2C_USE_I2C6 -extern I2CDriver I2CD7; -#endif - -#if TIVA_I2C_USE_I2C7 -extern I2CDriver I2CD8; -#endif - -#if TIVA_I2C_USE_I2C8 -extern I2CDriver I2CD9; -#endif - -#if TIVA_I2C_USE_I2C9 -extern I2CDriver I2CD10; -#endif - -#endif /* !defined(__DOXYGEN__) */ - -#ifdef __cplusplus -extern "C" { -#endif - void i2c_lld_init(void); - void i2c_lld_start(I2CDriver *i2cp); - void i2c_lld_stop(I2CDriver *i2cp); - msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, - const uint8_t *txbuf, size_t txbytes, - uint8_t *rxbuf, size_t rxbytes, - systime_t timeout); - msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, - uint8_t *rxbuf, size_t rxbytes, - systime_t timeout); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_I2C */ - -#endif /* HAL_I2C_LLD_H */ - -/** @} */ diff --git a/os/hal/ports/TIVA/LLD/hal_mac_lld.c b/os/hal/ports/TIVA/LLD/hal_mac_lld.c deleted file mode 100644 index 04177b6..0000000 --- a/os/hal/ports/TIVA/LLD/hal_mac_lld.c +++ /dev/null @@ -1,823 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TIVA/mac_lld.c - * @brief MAC Driver subsystem low level driver source. - * - * @addtogroup MAC - * @{ - */ - -#include - -#include "hal.h" - -#if HAL_USE_MAC || defined(__DOXYGEN__) - -#include "hal_mii.h" - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define BUFFER_SIZE ((((TIVA_MAC_BUFFERS_SIZE - 1) | 3) + 1) / 4) - -/* MII divider optimal value.*/ -#if (TIVA_SYSCLK >= 100000000) -#define MACMIIADDR_CR (0x01 << 2) -#elif (TIVA_SYSCLK >= 60000000) -#define MACMIIADDR_CR (0x00 << 2) -#elif (TIVA_SYSCLK >= 35000000) -#define MACMIIADDR_CR (0x03 << 2) -#elif (TIVA_SYSCLK >= 20000000) -#define MACMIIADDR_CR (0x02 << 2) -#else -#error "TIVA_SYSCLK below minimum frequency for ETH operations (20MHz)" -#endif - -#define EMAC_MIIADDR_MIIW 0x00000002 /* MII Write */ -#define EMAC_MIIADDR_MIIB 0x00000001 /* MII Busy */ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief Ethernet driver 1. - */ -MACDriver ETHD1; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -static const uint8_t default_mac_address[] = {0xAA, 0x55, 0x13, - 0x37, 0x01, 0x10}; - -static tiva_eth_rx_descriptor_t rd[TIVA_MAC_RECEIVE_BUFFERS]; -static tiva_eth_tx_descriptor_t td[TIVA_MAC_TRANSMIT_BUFFERS]; - -static uint32_t rb[TIVA_MAC_RECEIVE_BUFFERS][BUFFER_SIZE]; -static uint32_t tb[TIVA_MAC_TRANSMIT_BUFFERS][BUFFER_SIZE]; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Writes a PHY register. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[in] reg register number - * @param[in] value new register value - * - * @notapi - */ -static void mii_write(MACDriver *macp, uint32_t reg, uint32_t value) -{ - ETH->MIIDATA = value; - ETH->MIIADDR = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIW | EMAC_MIIADDR_MIIB; - - while ((ETH->MIIADDR & EMAC_MIIADDR_MIIB) != 0) - ; -} - -/** - * @brief Writes an extended PHY register. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[in] reg register number - * @param[in] value new register value - * - * @notapi - */ -static void mii_write_extended(MACDriver *macp, uint32_t reg, uint32_t value) -{ - mii_write(macp, TIVA_REGCTL, 0x001F); - mii_write(macp, TIVA_ADDAR, reg); - - mii_write(macp, TIVA_REGCTL, 0x401F); - mii_write(macp, TIVA_ADDAR, value); -} - -/** - * @brief Reads a PHY register. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[in] reg register number - * - * @return The PHY register content. - * - * @notapi - */ -static uint32_t mii_read(MACDriver *macp, uint32_t reg) -{ - ETH->MIIADDR = macp->phyaddr | (reg << 6) | MACMIIADDR_CR | EMAC_MIIADDR_MIIB; - - while ((ETH->MIIADDR & EMAC_MIIADDR_MIIB) != 0) - ; - - return ETH->MIIDATA; -} - -/** - * @brief Reads an extended PHY register. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[in] reg register number - * - * @return The extended PHY register content. - * - * @notapi - */ -static uint32_t mii_read_extended(MACDriver *macp, uint32_t reg) -{ - mii_write(macp, TIVA_REGCTL, 0x001F); - mii_write(macp, TIVA_ADDAR, reg); - - mii_write(macp, TIVA_REGCTL, 0x401F); - return mii_read(macp, TIVA_ADDAR); -} - -#if !defined(BOARD_PHY_ADDRESS) -/** - * @brief PHY address detection. - * - * @param[in] macp pointer to the @p MACDriver object - */ -static void mii_find_phy(MACDriver *macp) -{ - uint32_t i; - -#if TIVA_MAC_PHY_TIMEOUT > 0 - rtcnt_t start = chSysGetRealtimeCounterX(); - rtcnt_t timeout = start + MS2RTC(STM32_HCLK,STM32_MAC_PHY_TIMEOUT); - rtcnt_t time = start; - while (chSysIsCounterWithinX(time, start, timeout)) { -#endif - for (i = 0; i < 31; i++) { - macp->phyaddr = i << 11; - ETH->MIIDATA = (i << 6) | MACMIIADDR_CR; - if ((mii_read(macp, TIVA_ID1) == (BOARD_PHY_ID >> 16)) && - ((mii_read(macp, TIVA_ID2) & 0xFFF0) == (BOARD_PHY_ID & 0xFFF0))) { - return; - } - } -#if TIVA_MAC_PHY_TIMEOUT > 0 - time = chSysGetRealtimeCounterX(); - } -#endif - /* Wrong or defective board.*/ - osalSysHalt("MAC failure"); -} -#endif - -/** - * @brief MAC address setup. - * - * @param[in] p pointer to a six bytes buffer containing the MAC - * address - */ -static void mac_lld_set_address(const uint8_t *p) -{ - /* MAC address configuration, only a single address comparator is used, - hash table not used.*/ - ETH->ADDR0H = ((uint32_t)p[5] << 8) | - ((uint32_t)p[4] << 0); - ETH->ADDR0L = ((uint32_t)p[3] << 24) | - ((uint32_t)p[2] << 16) | - ((uint32_t)p[1] << 8) | - ((uint32_t)p[0] << 0); - ETH->ADDR1H = 0x0000FFFF; - ETH->ADDR1L = 0xFFFFFFFF; - ETH->ADDR2H = 0x0000FFFF; - ETH->ADDR2L = 0xFFFFFFFF; - ETH->ADDR3H = 0x0000FFFF; - ETH->ADDR3L = 0xFFFFFFFF; - ETH->HASHTBLH = 0; - ETH->HASHTBLL = 0; -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -CH_IRQ_HANDLER(TIVA_MAC_HANDLER) -{ - uint32_t dmaris; - - CH_IRQ_PROLOGUE(); - - dmaris = ETH->DMARIS; - ETH->DMARIS = dmaris & 0x0001FFFF; /* Clear status bits.*/ - - if (dmaris & (1 << 6)) { - /* Data Received.*/ - osalSysLockFromISR(); - osalThreadDequeueAllI(ÐD1.rdqueue, MSG_RESET); -#if MAC_USE_EVENTS - osalEventBroadcastFlagsI(ÐD1.rdevent, 0); -#endif - osalSysUnlockFromISR(); - } - - if (dmaris & (1 << 0)) { - /* Data Transmitted.*/ - osalSysLockFromISR(); - osalThreadDequeueAllI(ÐD1.tdqueue, MSG_RESET); - osalSysUnlockFromISR(); - } - - CH_IRQ_EPILOGUE(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level MAC initialization. - * - * @notapi - */ -void mac_lld_init(void) -{ - uint8_t i; - - macObjectInit(ÐD1); - ETHD1.link_up = false; - - /* Descriptor tables are initialized in chained mode, note that the first - word is not initialized here but in mac_lld_start().*/ - for (i = 0; i < TIVA_MAC_RECEIVE_BUFFERS; i++) { - rd[i].rdes1 = TIVA_RDES1_RCH | TIVA_RDES1_RBS1(TIVA_MAC_BUFFERS_SIZE); - rd[i].rdes2 = (uint32_t)rb[i]; - rd[i].rdes3 = (uint32_t)&rd[(i + 1) % TIVA_MAC_RECEIVE_BUFFERS]; - } - for (i = 0; i < TIVA_MAC_TRANSMIT_BUFFERS; i++) { - td[i].tdes1 = 0; - td[i].tdes2 = (uint32_t)tb[i]; - td[i].tdes3 = (uint32_t)&td[(i + 1) % TIVA_MAC_TRANSMIT_BUFFERS]; - } - - /* Enable MAC clock */ - SYSCTL->RCGCEMAC = 1; - while (SYSCTL->PREMAC != 0x01) - ; - - /* Set PHYHOLD bit */ - ETH->PC |= 1; - - /* Enable PHY clock */ - SYSCTL->RCGCEPHY = 1; - while (SYSCTL->PREPHY != 0x01) - ; - - /* Enable power to PHY */ - SYSCTL->PCEPHY |= 1; - while (SYSCTL->PREPHY != 0x01) - ; -#if BOARD_PHY_RMII - ETH->PC = EMAC_PHY_CONFIG | (0x04 << 28); -#else - ETH->PC = EMAC_PHY_CONFIG; -#endif - - /* - * Write OHY led configuration. - * 0: link ok - * 1: tx activity - * 2: link ok - * blink rate: 20Hz - */ - mii_write_extended(ÐD1, TIVA_LEDCFG, (0 << 8) | (2 << 4) | (0 << 0)); - mii_write(ÐD1, TIVA_LEDCR, (0 << 9)); - - /* Set done bit after writing EMACPC register */ - mii_write(ÐD1, TIVA_CFG1, (1 << 15) | mii_read(ÐD1, TIVA_CFG1)); - - while(ETH->DMABUSMOD & 1) - ; - - /* Reset MAC */ - ETH->DMABUSMOD |= 1; - while (ETH->DMABUSMOD & 1) - ; - - /* PHY address setup.*/ -#if defined(BOARD_PHY_ADDRESS) - ETHD1.phyaddr = BOARD_PHY_ADDRESS << 11; -#else - mii_find_phy(ÐD1); -#endif - -#if defined(BOARD_PHY_RESET) - /* PHY board-specific reset procedure.*/ - BOARD_PHY_RESET(); -#else - /* PHY soft reset procedure.*/ - mii_write(ÐD1, MII_BMCR, BMCR_RESET); -#if defined(BOARD_PHY_RESET_DELAY) - chSysPolledDelayX(BOARD_PHY_RESET_DELAY); -#endif - while (mii_read(ÐD1, MII_BMCR) & BMCR_RESET) - ; -#endif - -#if TIVA_MAC_CHANGE_PHY_STATE - /* PHY in power down mode until the driver will be started.*/ - mii_write(ÐD1, MII_BMCR, mii_read(ÐD1, MII_BMCR) | BMCR_PDOWN); -#endif - - /* Disable MAC clock */ - SYSCTL->RCGCEMAC = 0; - - /* Disable PHY clock */ - SYSCTL->RCGCEPHY = 0; -} - -/** - * @brief Configures and activates the MAC peripheral. - * - * @param[in] macp pointer to the @p MACDriver object - * - * @notapi - */ -void mac_lld_start(MACDriver *macp) -{ - uint8_t i; - - /* Resets the state of all descriptors.*/ - for (i = 0; i < TIVA_MAC_RECEIVE_BUFFERS; i++) { - rd[i].rdes0 = TIVA_RDES0_OWN; - } - macp->rxptr = (tiva_eth_rx_descriptor_t *)rd; - - for (i = 0; i < TIVA_MAC_TRANSMIT_BUFFERS; i++) { - td[i].tdes0 = TIVA_TDES0_TCH; - td[i].locked = 0; - } - macp->txptr = (tiva_eth_tx_descriptor_t *)td; - - /* Enable MAC clock */ - SYSCTL->RCGCEMAC = 1; - while (SYSCTL->PREMAC != 0x01) - ; - - /* Enable PHY clock */ - SYSCTL->RCGCEPHY = 1; - while (!SYSCTL->PREPHY) - ; - - /* ISR vector enabled.*/ - nvicEnableVector(TIVA_MAC_NUMBER, TIVA_MAC_IRQ_PRIORITY); - -#if TIVA_MAC_CHANGE_PHY_STATE - /* PHY in power up mode.*/ - mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) & ~BMCR_PDOWN); -#endif - - /* MAC configuration.*/ - ETH->FRAMEFLTR = 0; - ETH->FLOWCTL = 0; - ETH->VLANTG = 0; - - /* MAC address setup.*/ - if (macp->config->mac_address == NULL) - mac_lld_set_address(default_mac_address); - else - mac_lld_set_address(macp->config->mac_address); - - /* Transmitter and receiver enabled. - Note that the complete setup of the MAC is performed when the link - status is detected.*/ -#if TIVA_MAC_IP_CHECKSUM_OFFLOAD - ETH->CFG = (1 << 10) | (1 << 3) | (1 << 2); -#else - ETH->CFG = (1 << 3) | (1 << 2); -#endif - - /* DMA configuration: - Descriptor chains pointers.*/ - ETH->RXDLADDR = (uint32_t)rd; - ETH->TXDLADDR = (uint32_t)td; - - /* Enabling required interrupt sources.*/ - ETH->DMARIS &= 0xFFFF; - ETH->DMAIM = (1 << 16) | (1 << 6) | (1 << 0); - - /* DMA general settings.*/ - ETH->DMABUSMOD = (1 << 25) | (1 << 17) | (1 << 8); - - /* Transmit FIFO flush.*/ - ETH->DMAOPMODE = (1 << 20); - while (ETH->DMAOPMODE & (1 << 20)) - ; - - /* DMA final configuration and start.*/ - ETH->DMAOPMODE = (1 << 26) | (1 << 25) | (1 << 21) | - (1 << 13) | (1 << 1); -} - -/** - * @brief Deactivates the MAC peripheral. - * - * @param[in] macp pointer to the @p MACDriver object - * - * @notapi - */ -void mac_lld_stop(MACDriver *macp) -{ - if (macp->state != MAC_STOP) { -#if TIVA_MAC_CHANGE_PHY_STATE - /* PHY in power down mode until the driver will be restarted.*/ - mii_write(macp, MII_BMCR, mii_read(macp, MII_BMCR) | BMCR_PDOWN); -#endif - - /* MAC and DMA stopped.*/ - ETH->CFG = 0; - ETH->DMAOPMODE = 0; - ETH->DMAIM = 0; - ETH->DMARIS &= 0xFFFF; - - /* MAC clocks stopped.*/ - SYSCTL->RCGCEMAC = 0; - - /* PHY clock stopped.*/ - SYSCTL->RCGCEPHY = 0; - - /* ISR vector disabled.*/ - nvicDisableVector(TIVA_MAC_NUMBER); - } -} - -/** - * @brief Returns a transmission descriptor. - * @details One of the available transmission descriptors is locked and - * returned. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[out] tdp pointer to a @p MACTransmitDescriptor structure - * @return The operation status. - * @retval RDY_OK the descriptor has been obtained. - * @retval RDY_TIMEOUT descriptor not available. - * - * @notapi - */ -msg_t mac_lld_get_transmit_descriptor(MACDriver *macp, - MACTransmitDescriptor *tdp) -{ - tiva_eth_tx_descriptor_t *tdes; - - if (!macp->link_up) - return MSG_TIMEOUT; - - osalSysLock(); - - /* Get Current TX descriptor.*/ - tdes = macp->txptr; - - /* Ensure that descriptor isn't owned by the Ethernet DMA or locked by - another thread.*/ - if (tdes->tdes0 & (TIVA_TDES0_OWN) || (tdes->locked)) { - osalSysUnlock(); - return MSG_TIMEOUT; - } - - /* Marks the current descriptor as locked.*/ - tdes->locked = 1; - - /* Next TX descriptor to use.*/ - macp->txptr = (tiva_eth_tx_descriptor_t *)tdes->tdes3; - - osalSysUnlock(); - - /* Set the buffer size and configuration.*/ - tdp->offset = 0; - tdp->size = TIVA_MAC_BUFFERS_SIZE; - tdp->physdesc = tdes; - - return MSG_OK; -} - -/** - * @brief Releases a transmit descriptor and starts the transmission of the - * enqueued data as a single frame. - * - * @param[in] tdp the pointer to the @p MACTransmitDescriptor structure - * - * @notapi - */ -void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp) -{ - osalDbgAssert(!(tdp->physdesc->tdes0 & TIVA_TDES0_OWN), - "attempt to release descriptor already owned by DMA"); - - osalSysLock(); - - /* Unlocks the descriptor and returns it to the DMA engine.*/ - tdp->physdesc->tdes1 = tdp->offset; - tdp->physdesc->tdes0 = TIVA_TDES0_CIC(TIVA_MAC_IP_CHECKSUM_OFFLOAD) | - TIVA_TDES0_IC | TIVA_TDES0_LS | TIVA_TDES0_FS | - TIVA_TDES0_TCH | TIVA_TDES0_OWN; - tdp->physdesc->locked = 0; - - /* If the DMA engine is stalled then a restart request is issued.*/ - if ((ETH->DMARIS & (0x7 << 20)) == (6 << 20)) { - ETH->DMARIS = (1 << 2); - ETH->TXPOLLD = 1; /* Any value is OK.*/ - } - - osalSysUnlock(); -} - -/** - * @brief Returns a receive descriptor. - * - * @param[in] macp pointer to the @p MACDriver object - * @param[out] rdp pointer to a @p MACReceiveDescriptor structure - * @return The operation status. - * @retval RDY_OK the descriptor has been obtained. - * @retval RDY_TIMEOUT descriptor not available. - * - * @notapi - */ -msg_t mac_lld_get_receive_descriptor(MACDriver *macp, - MACReceiveDescriptor *rdp) -{ - tiva_eth_rx_descriptor_t *rdes; - - osalSysLock(); - - /* Get Current RX descriptor.*/ - rdes = macp->rxptr; - - /* Iterates through received frames until a valid one is found, invalid - frames are discarded.*/ - while (!(rdes->rdes0 & TIVA_RDES0_OWN)) { - if (!(rdes->rdes0 & (TIVA_RDES0_AFM | TIVA_RDES0_ES)) -#if TIVA_MAC_IP_CHECKSUM_OFFLOAD - && (rdes->rdes0 & TIVA_RDES0_FT) - && !(rdes->rdes0 & (TIVA_RDES0_IPHCE | TIVA_RDES0_PCE)) -#endif - && (rdes->rdes0 & TIVA_RDES0_FS) && (rdes->rdes0 & TIVA_RDES0_LS)) { - /* Found a valid one.*/ - rdp->offset = 0; - rdp->size = ((rdes->rdes0 & TIVA_RDES0_FL_MASK) >> 16) - 4; - rdp->physdesc = rdes; - macp->rxptr = (tiva_eth_rx_descriptor_t *)rdes->rdes3; - - osalSysUnlock(); - return MSG_OK; - } - /* Invalid frame found, purging.*/ - rdes->rdes0 = TIVA_RDES0_OWN; - rdes = (tiva_eth_rx_descriptor_t *)rdes->rdes3; - } - - /* Next descriptor to check.*/ - macp->rxptr = rdes; - - osalSysUnlock(); - return MSG_TIMEOUT; -} - -/** - * @brief Releases a receive descriptor. - * @details The descriptor and its buffer are made available for more incoming - * frames. - * - * @param[in] rdp the pointer to the @p MACReceiveDescriptor structure - * - * @notapi - */ -void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp) -{ - osalDbgAssert(!(rdp->physdesc->rdes0 & TIVA_RDES0_OWN), - "attempt to release descriptor already owned by DMA"); - - osalSysLock(); - - /* Give buffer back to the Ethernet DMA.*/ - rdp->physdesc->rdes0 = TIVA_RDES0_OWN; - - /* If the DMA engine is stalled then a restart request is issued.*/ - if ((ETH->STATUS & (0xf << 17)) == (4 << 17)) { - ETH->DMARIS = (1 << 7); - ETH->TXPOLLD = 1; /* Any value is OK.*/ - } - - osalSysUnlock(); -} - -/** - * @brief Updates and returns the link status. - * - * @param[in] macp pointer to the @p MACDriver object - * @return The link status. - * @retval TRUE if the link is active. - * @retval FALSE if the link is down. - * - * @notapi - */ -bool mac_lld_poll_link_status(MACDriver *macp) -{ - uint32_t maccfg, bmsr, bmcr; - - maccfg = ETH->CFG; - - /* PHY CR and SR registers read.*/ - (void)mii_read(macp, MII_BMSR); - bmsr = mii_read(macp, MII_BMSR); - bmcr = mii_read(macp, MII_BMCR); - - /* Check on auto-negotiation mode.*/ - if (bmcr & BMCR_ANENABLE) { - uint32_t lpa; - - /* Auto-negotiation must be finished without faults and link established.*/ - if ((bmsr & (BMSR_LSTATUS | BMSR_RFAULT | BMSR_ANEGCOMPLETE)) != - (BMSR_LSTATUS | BMSR_ANEGCOMPLETE)) - return macp->link_up = false; - - /* Auto-negotiation enabled, checks the LPA register.*/ - lpa = mii_read(macp, MII_LPA); - - /* Check on link speed.*/ - if (lpa & (LPA_100HALF | LPA_100FULL | LPA_100BASE4)) - maccfg |= (1 << 14); - else - maccfg &= ~(1 << 14); - - /* Check on link mode.*/ - if (lpa & (LPA_10FULL | LPA_100FULL)) - maccfg |= (1 << 11); - else - maccfg &= ~(1 << 11); - } - else { - /* Link must be established.*/ - if (!(bmsr & BMSR_LSTATUS)) - return macp->link_up = false; - - /* Check on link speed.*/ - if (bmcr & BMCR_SPEED100) - maccfg |= (1 << 14); - else - maccfg &= ~(1 << 14); - - /* Check on link mode.*/ - if (bmcr & BMCR_FULLDPLX) - maccfg |= (1 << 11); - else - maccfg &= ~(1 << 11); - } - - /* Changes the mode in the MAC.*/ - ETH->CFG = maccfg; - - /* Returns the link status.*/ - return macp->link_up = true; -} - -/** - * @brief Writes to a transmit descriptor's stream. - * - * @param[in] tdp pointer to a @p MACTransmitDescriptor structure - * @param[in] buf pointer to the buffer containing the data to be - * written - * @param[in] size number of bytes to be written - * @return The number of bytes written into the descriptor's - * stream, this value can be less than the amount - * specified in the parameter @p size if the maximum - * frame size is reached. - * - * @notapi - */ -size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, - uint8_t *buf, - size_t size) -{ - osalDbgAssert(!(tdp->physdesc->tdes0 & TIVA_TDES0_OWN), - "attempt to write descriptor already owned by DMA"); - - if (size > tdp->size - tdp->offset) - size = tdp->size - tdp->offset; - - if (size > 0) { - memcpy((uint8_t *)(tdp->physdesc->tdes2) + tdp->offset, buf, size); - tdp->offset += size; - } - return size; -} - -/** - * @brief Reads from a receive descriptor's stream. - * - * @param[in] rdp pointer to a @p MACReceiveDescriptor structure - * @param[in] buf pointer to the buffer that will receive the read data - * @param[in] size number of bytes to be read - * @return The number of bytes read from the descriptor's - * stream, this value can be less than the amount - * specified in the parameter @p size if there are - * no more bytes to read. - * - * @notapi - */ -size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, - uint8_t *buf, - size_t size) -{ - osalDbgAssert(!(rdp->physdesc->rdes0 & TIVA_RDES0_OWN), - "attempt to read descriptor already owned by DMA"); - - if (size > rdp->size - rdp->offset) - size = rdp->size - rdp->offset; - - if (size > 0) { - memcpy(buf, (uint8_t *)(rdp->physdesc->rdes2) + rdp->offset, size); - rdp->offset += size; - } - return size; -} - -#if MAC_USE_ZERO_COPY || defined(__DOXYGEN__) -/** - * @brief Returns a pointer to the next transmit buffer in the descriptor - * chain. - * @note The API guarantees that enough buffers can be requested to fill - * a whole frame. - * - * @param[in] tdp pointer to a @p MACTransmitDescriptor structure - * @param[in] size size of the requested buffer. Specify the frame size - * on the first call then scale the value down subtracting - * the amount of data already copied into the previous - * buffers. - * @param[out] sizep pointer to variable receiving the buffer size, it is - * zero when the last buffer has already been returned. - * Note that a returned size lower than the amount - * requested means that more buffers must be requested - * in order to fill the frame data entirely. - * @return Pointer to the returned buffer. - * @retval NULL if the buffer chain has been entirely scanned. - * - * @notapi - */ -uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp, - size_t size, - size_t *sizep) -{ - if (tdp->offset == 0) { - *sizep = tdp->size; - tdp->offset = size; - return (uint8_t *)tdp->physdesc->tdes2; - } - *sizep = 0; - return NULL; -} - -/** - * @brief Returns a pointer to the next receive buffer in the descriptor - * chain. - * @note The API guarantees that the descriptor chain contains a whole - * frame. - * - * @param[in] rdp pointer to a @p MACReceiveDescriptor structure - * @param[out] sizep pointer to variable receiving the buffer size, it is - * zero when the last buffer has already been returned. - * @return Pointer to the returned buffer. - * @retval NULL if the buffer chain has been entirely scanned. - * - * @notapi - */ -const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp, - size_t *sizep) -{ - if (rdp->size > 0) { - *sizep = rdp->size; - rdp->offset = rdp->size; - rdp->size = 0; - return (uint8_t *)rdp->physdesc->rdes2; - } - *sizep = 0; - return NULL; -} -#endif /* MAC_USE_ZERO_COPY */ - -#endif /* HAL_USE_MAC */ - -/** @} */ diff --git a/os/hal/ports/TIVA/LLD/hal_mac_lld.h b/os/hal/ports/TIVA/LLD/hal_mac_lld.h deleted file mode 100644 index 98036bb..0000000 --- a/os/hal/ports/TIVA/LLD/hal_mac_lld.h +++ /dev/null @@ -1,438 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TIVA/mac_lld.h - * @brief MAC Driver subsystem low level driver header. - * - * @addtogroup MAC - * @{ - */ - -#ifndef HAL_MAC_LLD_H -#define HAL_MAC_LLD_H - -#if HAL_USE_MAC || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief This implementation supports the zero-copy mode API. - */ -#define MAC_SUPPORTS_ZERO_COPY TRUE - -/** - * @name RDES0 constants - * @{ - */ -#define TIVA_RDES0_OWN 0x80000000 -#define TIVA_RDES0_AFM 0x40000000 - -#define TIVA_RDES0_FL_MASK 0x3FFF0000 -#define TIVA_RDES0_FL(n) ((n) << 16) - -#define TIVA_RDES0_ES 0x00008000 -#define TIVA_RDES0_DESERR 0x00004000 -#define TIVA_RDES0_SAF 0x00002000 -#define TIVA_RDES0_LE 0x00001000 -#define TIVA_RDES0_OE 0x00000800 -#define TIVA_RDES0_VLAN 0x00000400 -#define TIVA_RDES0_FS 0x00000200 -#define TIVA_RDES0_LS 0x00000100 -#define TIVA_RDES0_TAGF 0x00000080 -#define TIVA_RDES0_LC 0x00000040 -#define TIVA_RDES0_FT 0x00000020 -#define TIVA_RDES0_RWT 0x00000010 -#define TIVA_RDES0_RE 0x00000008 -#define TIVA_RDES0_DE 0x00000004 -#define TIVA_RDES0_CE 0x00000002 -#define TIVA_RDES0_ESA 0x00000001 -/** @} */ - -/** - * @name RDES1 constants - * @{ - */ -#define TIVA_RDES1_DIC 0x80000000 - -#define TIVA_RDES1_RBS2_MASK 0x1FFF0000 -#define TIVA_RDES1_RBS2(n) ((n) << 16) - -#define TIVA_RDES1_RER 0x00008000 -#define TIVA_RDES1_RCH 0x00004000 - -#define TIVA_RDES1_RBS1_MASK 0x00001FFF -#define TIVA_RDES1_RBS1(n) ((n) << 0) - -/** @} */ - -/** - * @name TDES0 constants - * @{ - */ -#define TIVA_TDES0_OWN 0x80000000 -#define TIVA_TDES0_IC 0x40000000 -#define TIVA_TDES0_LS 0x20000000 -#define TIVA_TDES0_FS 0x10000000 -#define TIVA_TDES0_DC 0x08000000 -#define TIVA_TDES0_DP 0x04000000 -#define TIVA_TDES0_TTSE 0x02000000 -#define TIVA_TDES0_CRCR 0x01000000 - -#define TIVA_TDES0_CIC_MASK 0x00C00000 -#define TIVA_TDES0_CIC(n) ((n) << 22) - -#define TIVA_TDES0_TER 0x00200000 -#define TIVA_TDES0_TCH 0x00100000 -#define TIVA_TDES0_VLIC 0x000C0000 -#define TIVA_TDES0_TTSS 0x00020000 -#define TIVA_TDES0_IHE 0x00010000 -#define TIVA_TDES0_ES 0x00008000 -#define TIVA_TDES0_JT 0x00004000 -#define TIVA_TDES0_FF 0x00002000 -#define TIVA_TDES0_IPE 0x00001000 -#define TIVA_TDES0_LC 0x00000800 -#define TIVA_TDES0_NC 0x00000400 -#define TIVA_TDES0_LCO 0x00000200 -#define TIVA_TDES0_EC 0x00000100 -#define TIVA_TDES0_VF 0x00000080 - -#define TIVA_TDES0_CC_MASK 0x00000078 -#define TIVA_TDES0_CC(n) ((n) << 3) - -#define TIVA_TDES0_ED 0x00000004 -#define TIVA_TDES0_UF 0x00000002 -#define TIVA_TDES0_DB 0x00000001 -/** @} */ - -/** - * @name TDES1 constants - * @{ - */ -#define TIVA_TDES1_SAIC_MASK 0xE0000000 -#define TIVA_TDES1_SAIC(n) ((n) << 29) - -#define TIVA_TDES1_TBS2_MASK 0x1FFF0000 -#define TIVA_TDES1_TBS2(n) ((n) << 16) - -#define TIVA_TDES1_TBS1_MASK 0x00001FFF -#define TIVA_TDES1_TBS1(n) ((n) << 0) -/** @} */ - - - - -/** - * @name Ethernet PHY registers - */ -#define TIVA_BMCR 0x00000000 /* MR0 - Basic Mode Control */ -#define TIVA_BMSR 0x00000001 /* MR1 - Basic Mode Status */ -#define TIVA_ID1 0x00000002 /* MR2 - Identifier Register 1 */ -#define TIVA_ID2 0x00000003 /* MR3 - Identifier Register 2 */ -#define TIVA_ANA 0x00000004 /* MR4 - Auto-Negotiation Advertisement */ -#define TIVA_ANLPA 0x00000005 /* MR5 - Auto-Negotiation Link Partner Ability */ -#define TIVA_ANER 0x00000006 /* MR6 - Auto-Negotiation Expansion */ -#define TIVA_ANNPTR 0x00000007 /* MR7 - Auto-Negotiation Next Page TX */ -#define TIVA_ANLNPTR 0x00000008 /* MR8 - Auto-Negotiation Link Partner Ability Next Page */ -#define TIVA_CFG1 0x00000009 /* MR9 - Configuration 1 */ -#define TIVA_CFG2 0x0000000A /* MR10 - Configuration 2 */ -#define TIVA_CFG3 0x0000000B /* MR11 - Configuration 3 */ -#define TIVA_REGCTL 0x0000000D /* MR13 - Register Control */ -#define TIVA_ADDAR 0x0000000E /* MR14 - Address or Data */ -#define TIVA_STS 0x00000010 /* MR16 - Status */ -#define TIVA_SCR 0x00000011 /* MR17 - Specific Control */ -#define TIVA_MISR1 0x00000012 /* MR18 - MII Interrupt Status 1 */ -#define TIVA_MISR2 0x00000013 /* MR19 - MII Interrupt Status 2 */ -#define TIVA_FCSCR 0x00000014 /* MR20 - False Carrier Sense Counter */ -#define TIVA_RXERCNT 0x00000015 /* MR21 - Receive Error Count */ -#define TIVA_BISTCR 0x00000016 /* MR22 - BIST Control */ -#define TIVA_LEDCR 0x00000018 /* MR24 - LED Control */ -#define TIVA_CTL 0x00000019 /* MR25 - Control */ -#define TIVA_10BTSC 0x0000001A /* MR26 - 10Base-T Status/Control - MR26 */ -#define TIVA_BICSR1 0x0000001B /* MR27 - BIST Control and Status 1 */ -#define TIVA_BICSR2 0x0000001C /* MR28 - BIST Control and Status 2 */ -#define TIVA_CDCR 0x0000001E /* MR30 - Cable Diagnostic Control */ -#define TIVA_RCR 0x0000001F /* MR31 - Reset Control */ -#define TIVA_LEDCFG 0x00000025 /* MR37 - LED Configuration */ -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief Number of available transmit buffers. - */ -#if !defined(TIVA_MAC_TRANSMIT_BUFFERS) || defined(__DOXYGEN__) -#define TIVA_MAC_TRANSMIT_BUFFERS 2 -#endif - -/** - * @brief Number of available receive buffers. - */ -#if !defined(TIVA_MAC_RECEIVE_BUFFERS) || defined(__DOXYGEN__) -#define TIVA_MAC_RECEIVE_BUFFERS 4 -#endif - -/** - * @brief Maximum supported frame size. - */ -#if !defined(TIVA_MAC_BUFFERS_SIZE) || defined(__DOXYGEN__) -#define TIVA_MAC_BUFFERS_SIZE 1522 -#endif - -/** - * @brief PHY detection timeout. - * @details Timeout, in milliseconds, for PHY address detection, if a PHY - * is not detected within the timeout then the driver halts during - * initialization. This setting applies only if the PHY address is - * not explicitly set in the board header file using - * @p BOARD_PHY_ADDRESS. A zero value disables the timeout and a - * single search path is performed. - */ -#if !defined(TIVA_MAC_PHY_TIMEOUT) || defined(__DOXYGEN__) -#define TIVA_MAC_PHY_TIMEOUT 0 -#endif - -/** - * @brief Change the PHY power state inside the driver. - */ -#if !defined(TIVA_MAC_CHANGE_PHY_STATE) || defined(__DOXYGEN__) -#define TIVA_MAC_CHANGE_PHY_STATE TRUE -#endif - -/** - * @brief ETHD1 interrupt priority level setting. - */ -#if !defined(TIVA_MAC_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_MAC_IRQ_PRIORITY 5 -#endif - -/** - * @brief IP checksum offload. - * @details The following modes are available: - * - 0 Function disabled. - * - 1 Only IP header checksum calculation and insertion are enabled. - * - 2 IP header checksum and payload checksum calculation and - * insertion are enabled, but pseudo-header checksum is not - * calculated in hardware. - * - 3 IP Header checksum and payload checksum calculation and - * insertion are enabled, and pseudo-header checksum is - * calculated in hardware. - * . - */ -#if !defined(TIVA_MAC_IP_CHECKSUM_OFFLOAD) || defined(__DOXYGEN__) -#define TIVA_MAC_IP_CHECKSUM_OFFLOAD 0 -#endif -/** @} */ - -#ifndef EMAC_PHY_CONFIG -#define EMAC_PHY_CONFIG ((0 << 31) | \ - (1 << 23) | \ - (1 << 10) | \ - (1 << 3) | \ - (3 << 1) | \ - (1 << 0)) -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if (TIVA_MAC_PHY_TIMEOUT > 0) && !HAL_IMPLEMENTS_COUNTERS -#error "TIVA_MAC_PHY_TIMEOUT requires the realtime counter service" -#endif - -#if !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_MAC_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to MAC" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of an Tiva Ethernet receive descriptor. - */ -typedef struct -{ - volatile uint32_t rdes0; - volatile uint32_t rdes1; - volatile uint32_t rdes2; - volatile uint32_t rdes3; -} tiva_eth_rx_descriptor_t; - -/** - * @brief Type of an Tiva Ethernet transmit descriptor. - */ -typedef struct -{ - volatile uint32_t tdes0; - volatile uint32_t tdes1; - volatile uint32_t tdes2; - volatile uint32_t tdes3; - volatile uint32_t locked; -} tiva_eth_tx_descriptor_t; - -/** - * @brief Driver configuration structure. - */ -typedef struct -{ - /** - * @brief MAC address. - */ - uint8_t *mac_address; - /* End of the mandatory fields.*/ -} MACConfig; - -/** - * @brief Structure representing a MAC driver. - */ -struct MACDriver -{ - /** - * @brief Driver state. - */ - macstate_t state; - /** - * @brief Current configuration data. - */ - const MACConfig *config; - /** - * @brief Transmit semaphore. - */ - threads_queue_t tdqueue; - /** - * @brief Receive semaphore. - */ - threads_queue_t rdqueue; -#if MAC_USE_EVENTS || defined(__DOXYGEN__) - /** - * @brief Receive event. - */ - event_source_t rdevent; -#endif - /* End of the mandatory fields.*/ - /** - * @brief Link status flag. - */ - bool link_up; - /** - * @brief PHY address (pre shifted). - */ - uint32_t phyaddr; - /** - * @brief Receive next frame pointer. - */ - tiva_eth_rx_descriptor_t *rxptr; - /** - * @brief Transmit next frame pointer. - */ - tiva_eth_tx_descriptor_t *txptr; -}; - -/** - * @brief Structure representing a transmit descriptor. - */ -typedef struct -{ - /** - * @brief Current write offset. - */ - size_t offset; - /** - * @brief Available space size. - */ - size_t size; - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the physical descriptor. - */ - tiva_eth_tx_descriptor_t *physdesc; -} MACTransmitDescriptor; - -/** - * @brief Structure representing a receive descriptor. - */ -typedef struct -{ - /** - * @brief Current read offset. - */ - size_t offset; - /** - * @brief Available data size. - */ - size_t size; - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the physical descriptor. - */ - tiva_eth_rx_descriptor_t *physdesc; -} MACReceiveDescriptor; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -extern MACDriver ETHD1; - -#ifdef __cplusplus -extern "C" { -#endif - void mac_lld_init(void); - void mac_lld_start(MACDriver *macp); - void mac_lld_stop(MACDriver *macp); - msg_t mac_lld_get_transmit_descriptor(MACDriver *macp, - MACTransmitDescriptor *tdp); - void mac_lld_release_transmit_descriptor(MACTransmitDescriptor *tdp); - msg_t mac_lld_get_receive_descriptor(MACDriver *macp, - MACReceiveDescriptor *rdp); - void mac_lld_release_receive_descriptor(MACReceiveDescriptor *rdp); - bool mac_lld_poll_link_status(MACDriver *macp); - size_t mac_lld_write_transmit_descriptor(MACTransmitDescriptor *tdp, - uint8_t *buf, - size_t size); - size_t mac_lld_read_receive_descriptor(MACReceiveDescriptor *rdp, - uint8_t *buf, - size_t size); -#if MAC_USE_ZERO_COPY - uint8_t *mac_lld_get_next_transmit_buffer(MACTransmitDescriptor *tdp, - size_t size, - size_t *sizep); - const uint8_t *mac_lld_get_next_receive_buffer(MACReceiveDescriptor *rdp, - size_t *sizep); -#endif /* MAC_USE_ZERO_COPY */ -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_MAC */ - -#endif /* HAL_MAC_LLD_H */ - -/** @} */ diff --git a/os/hal/ports/TIVA/LLD/hal_pal_lld.c b/os/hal/ports/TIVA/LLD/hal_pal_lld.c deleted file mode 100644 index 5460fd4..0000000 --- a/os/hal/ports/TIVA/LLD/hal_pal_lld.c +++ /dev/null @@ -1,445 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TIVA/LLD/pal_lld.c - * @brief TM4C123x/TM4C129x PAL subsystem low level driver. - * - * @addtogroup PAL - * @{ - */ - -#include "hal.h" - -#if HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#if TIVA_HAS_GPIOA || defined(__DOXYGEN__) -#define GPIOA_BIT (1 << 0) -#if TIVA_GPIO_GPIOA_USE_AHB && defined(TM4C123x) -#define GPIOA_AHB_BIT (1 << 0) -#else -#define GPIOA_AHB_BIT 0 -#endif -#else -#define GPIOA_BIT 0 -#define GPIOA_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOB || defined(__DOXYGEN__) -#define GPIOB_BIT (1 << 1) -#if TIVA_GPIO_GPIOB_USE_AHB && defined(TM4C123x) -#define GPIOB_AHB_BIT (1 << 1) -#else -#define GPIOB_AHB_BIT 0 -#endif -#else -#define GPIOB_BIT 0 -#define GPIOB_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOC || defined(__DOXYGEN__) -#define GPIOC_BIT (1 << 2) -#if TIVA_GPIO_GPIOC_USE_AHB && defined(TM4C123x) -#define GPIOC_AHB_BIT (1 << 2) -#else -#define GPIOC_AHB_BIT 0 -#endif -#else -#define GPIOC_BIT 0 -#define GPIOC_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOD || defined(__DOXYGEN__) -#define GPIOD_BIT (1 << 3) -#if TIVA_GPIO_GPIOD_USE_AHB && defined(TM4C123x) -#define GPIOD_AHB_BIT (1 << 3) -#else -#define GPIOD_AHB_BIT 0 -#endif -#else -#define GPIOD_BIT 0 -#define GPIOD_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOE || defined(__DOXYGEN__) -#define GPIOE_BIT (1 << 4) -#if TIVA_GPIO_GPIOE_USE_AHB && defined(TM4C123x) -#define GPIOE_AHB_BIT (1 << 4) -#else -#define GPIOE_AHB_BIT 0 -#endif -#else -#define GPIOE_BIT 0 -#define GPIOE_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOF || defined(__DOXYGEN__) -#define GPIOF_BIT (1 << 5) -#if TIVA_GPIO_GPIOF_USE_AHB && defined(TM4C123x) -#define GPIOF_AHB_BIT (1 << 5) -#else -#define GPIOF_AHB_BIT 0 -#endif -#else -#define GPIOF_BIT 0 -#define GPIOF_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOG || defined(__DOXYGEN__) -#define GPIOG_BIT (1 << 6) -#if TIVA_GPIO_GPIOG_USE_AHB && defined(TM4C123x) -#define GPIOG_AHB_BIT (1 << 6) -#else -#define GPIOG_AHB_BIT 0 -#endif -#else -#define GPIOG_BIT 0 -#define GPIOG_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOH || defined(__DOXYGEN__) -#define GPIOH_BIT (1 << 7) -#if TIVA_GPIO_GPIOH_USE_AHB && defined(TM4C123x) -#define GPIOH_AHB_BIT (1 << 7) -#else -#define GPIOH_AHB_BIT 0 -#endif -#else -#define GPIOH_BIT 0 -#define GPIOH_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__) -#define GPIOJ_BIT (1 << 8) -#if TIVA_GPIO_GPIOJ_USE_AHB && defined(TM4C123x) -#define GPIOJ_AHB_BIT (1 << 8) -#else -#define GPIOJ_AHB_BIT 0 -#endif -#else -#define GPIOJ_BIT 0 -#define GPIOJ_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOK || defined(__DOXYGEN__) -#define GPIOK_BIT (1 << 9) -#define GPIOK_AHB_BIT (1 << 9) -#else -#define GPIOK_BIT 0 -#define GPIOK_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOL || defined(__DOXYGEN__) -#define GPIOL_BIT (1 << 10) -#define GPIOL_AHB_BIT (1 << 10) -#else -#define GPIOL_BIT 0 -#define GPIOL_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOM || defined(__DOXYGEN__) -#define GPIOM_BIT (1 << 11) -#define GPIOM_AHB_BIT (1 << 11) -#else -#define GPIOM_BIT 0 -#define GPIOM_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPION || defined(__DOXYGEN__) -#define GPION_BIT (1 << 12) -#define GPION_AHB_BIT (1 << 12) -#else -#define GPION_BIT 0 -#define GPION_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOP || defined(__DOXYGEN__) -#define GPIOP_BIT (1 << 13) -#define GPIOP_AHB_BIT (1 << 13) -#else -#define GPIOP_BIT 0 -#define GPIOP_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__) -#define GPIOQ_BIT (1 << 14) -#define GPIOQ_AHB_BIT (1 << 14) -#else -#define GPIOQ_BIT 0 -#define GPIOQ_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOR || defined(__DOXYGEN__) -#define GPIOR_BIT (1 << 15) -#define GPIOR_AHB_BIT (1 << 15) -#else -#define GPIOR_BIT 0 -#define GPIOR_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOS || defined(__DOXYGEN__) -#define GPIOS_BIT (1 << 16) -#define GPIOS_AHB_BIT (1 << 16) -#else -#define GPIOS_BIT 0 -#define GPIOS_AHB_BIT 0 -#endif - -#if TIVA_HAS_GPIOT || defined(__DOXYGEN__) -#define GPIOT_BIT (1 << 17) -#define GPIOT_AHB_BIT (1 << 17) -#else -#define GPIOT_BIT 0 -#define GPIOT_AHB_BIT 0 -#endif - -#define RCGCGPIO_MASK (GPIOA_BIT | GPIOB_BIT | GPIOC_BIT | GPIOD_BIT | \ - GPIOE_BIT | GPIOF_BIT | GPIOG_BIT | GPIOH_BIT | \ - GPIOJ_BIT | GPIOK_BIT | GPIOL_BIT | GPIOM_BIT | \ - GPION_BIT | GPIOP_BIT | GPIOQ_BIT | GPIOR_BIT | \ - GPIOS_BIT | GPIOR_BIT) - -#define GPIOHBCTL_MASK (GPIOA_AHB_BIT | GPIOB_AHB_BIT | GPIOC_AHB_BIT | \ - GPIOD_AHB_BIT | GPIOE_AHB_BIT | GPIOF_AHB_BIT | \ - GPIOG_AHB_BIT | GPIOH_AHB_BIT | GPIOJ_AHB_BIT | \ - GPIOK_AHB_BIT | GPIOL_AHB_BIT | GPIOM_AHB_BIT | \ - GPION_AHB_BIT | GPIOP_AHB_BIT | GPIOQ_AHB_BIT | \ - GPIOR_AHB_BIT | GPIOS_AHB_BIT | GPIOT_AHB_BIT) - -/* GPIO lock password.*/ -#define TIVA_GPIO_LOCK_PWD 0x4C4F434B - -#define GPIOC_JTAG_MASK (0x0F) -#define GPIOD_NMI_MASK (0x80) -#define GPIOF_NMI_MASK (0x01) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Initializes the port with the port configuration. - * - * @param[in] port the port identifier - * @param[in] config the port configuration - */ -static void gpio_init(ioportid_t port, const tiva_gpio_setup_t *config) -{ - port->DATA = config->data; - port->DIR = config->dir; - port->AFSEL = config->afsel; - port->DR2R = config->dr2r; - port->DR4R = config->dr4r; - port->DR8R = config->dr8r; - port->ODR = config->odr; - port->PUR = config->pur; - port->PDR = config->pdr; - port->SLR = config->slr; - port->DEN = config->den; - port->AMSEL = config->amsel; - port->PCTL = config->pctl; -} - -/** - * @brief Unlocks the masked pins of the GPIO peripheral. - * @note This function is only useful for PORTC0-3, PORTD7 and PORTF0. - * - * @param[in] port the port identifier - * @param[in] mask the pin mask - */ -static void gpio_unlock(ioportid_t port, ioportmask_t mask) -{ - port->LOCK = TIVA_GPIO_LOCK_PWD; - port->CR = mask; -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Tiva I/O ports configuration. - * @details Ports A-F (G, H, J, K, L, M, N, P, Q, R, S, T) clocks enabled. - * - * @param[in] config the Tiva ports configuration - * - * @notapi - */ -void _pal_lld_init(const PALConfig *config) -{ - /* - * Enables all GPIO clocks. - */ - SYSCTL->RCGCGPIO = RCGCGPIO_MASK; -#if defined(TM4C123x) - SYSCTL->GPIOHBCTL = GPIOHBCTL_MASK; -#endif - - /* Wait until all GPIO modules are ready */ - while (!((SYSCTL->PRGPIO & RCGCGPIO_MASK) == RCGCGPIO_MASK)) - ; - -#if TIVA_HAS_GPIOA - gpio_init(GPIOA, &config->PAData); -#endif -#if TIVA_HAS_GPIOB - gpio_init(GPIOB, &config->PBData); -#endif -#if TIVA_HAS_GPIOC - /* Unlock JTAG pins.*/ - gpio_unlock(GPIOC, GPIOC_JTAG_MASK); - gpio_init(GPIOC, &config->PCData); -#endif -#if TIVA_HAS_GPIOD - /* Unlock NMI pin.*/ - gpio_unlock(GPIOD, GPIOD_NMI_MASK); - gpio_init(GPIOD, &config->PDData); -#endif -#if TIVA_HAS_GPIOE - gpio_init(GPIOE, &config->PEData); -#endif -#if TIVA_HAS_GPIOF - /* Unlock NMI pin.*/ - gpio_unlock(GPIOF, GPIOF_NMI_MASK); - gpio_init(GPIOF, &config->PFData); -#endif -#if TIVA_HAS_GPIOG || defined(__DOXYGEN__) - gpio_init(GPIOG, &config->PGData); -#endif -#if TIVA_HAS_GPIOH || defined(__DOXYGEN__) - gpio_init(GPIOH, &config->PHData); -#endif -#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__) - gpio_init(GPIOJ, &config->PJData); -#endif -#if TIVA_HAS_GPIOK || defined(__DOXYGEN__) - gpio_init(GPIOK, &config->PKData); -#endif -#if TIVA_HAS_GPIOL || defined(__DOXYGEN__) - gpio_init(GPIOL, &config->PLData); -#endif -#if TIVA_HAS_GPIOM || defined(__DOXYGEN__) - gpio_init(GPIOM, &config->PMData); -#endif -#if TIVA_HAS_GPION || defined(__DOXYGEN__) - gpio_init(GPION, &config->PNData); -#endif -#if TIVA_HAS_GPIOP || defined(__DOXYGEN__) - gpio_init(GPIOP, &config->PPData); -#endif -#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__) - gpio_init(GPIOQ, &config->PQData); -#endif -#if TIVA_HAS_GPIOR || defined(__DOXYGEN__) - gpio_init(GPIOR, &config->PRData); -#endif -#if TIVA_HAS_GPIOS || defined(__DOXYGEN__) - gpio_init(GPIOS, &config->PSData); -#endif -#if TIVA_HAS_GPIOT || defined(__DOXYGEN__) - gpio_init(GPIOT, &config->PTData); -#endif -} - -/** - * @brief Pads mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * - * @param[in] port the port identifier - * @param[in] mask the group mask - * @param[in] mode the mode - * - * @notapi - */ -void _pal_lld_setgroupmode(ioportid_t port, ioportmask_t mask, iomode_t mode) -{ - uint32_t dir = (mode & PAL_TIVA_DIR_MASK) >> 0; - uint32_t afsel = (mode & PAL_TIVA_AFSEL_MASK) >> 1; - uint32_t dr2r = (mode & PAL_TIVA_DR2R_MASK) >> 2; - uint32_t dr4r = (mode & PAL_TIVA_DR4R_MASK) >> 3; - uint32_t dr8r = (mode & PAL_TIVA_DR8R_MASK) >> 4; - uint32_t odr = (mode & PAL_TIVA_ODR_MASK) >> 5; - uint32_t pur = (mode & PAL_TIVA_PUR_MASK) >> 6; - uint32_t pdr = (mode & PAL_TIVA_PDR_MASK) >> 7; - uint32_t slr = (mode & PAL_TIVA_SLR_MASK) >> 8; - uint32_t den = (mode & PAL_TIVA_DEN_MASK) >> 9; - uint32_t amsel = (mode & PAL_TIVA_AMSEL_MASK) >> 10; - uint32_t pctl = (mode & PAL_TIVA_PCTL_MASK) >> 11; - uint32_t bit = 0; - - while(TRUE) { - uint32_t pctl_mask = (7 << (4 * bit)); - uint32_t bit_mask = (1 << bit); - - if ((mask & 1) != 0) { - port->DIR = (port->DIR & ~bit_mask) | dir; - port->AFSEL = (port->AFSEL & ~bit_mask) | afsel; - port->DR2R = (port->DR2R & ~bit_mask) | dr2r; - port->DR4R = (port->DR4R & ~bit_mask) | dr4r; - port->DR8R = (port->DR8R & ~bit_mask) | dr8r; - port->ODR = (port->ODR & ~bit_mask) | odr; - port->PUR = (port->PUR & ~bit_mask) | pur; - port->PDR = (port->PDR & ~bit_mask) | pdr; - port->SLR = (port->SLR & ~bit_mask) | slr; - port->DEN = (port->DEN & ~bit_mask) | den; - port->AMSEL = (port->AMSEL & ~bit_mask) | amsel; - port->PCTL = (port->PCTL & ~pctl_mask) | pctl; - } - - mask >>= 1; - if (!mask) { - return; - } - - dir <<= 1; - afsel <<= 1; - dr2r <<= 1; - dr4r <<= 1; - dr8r <<= 1; - odr <<= 1; - pur <<= 1; - pdr <<= 1; - slr <<= 1; - den <<= 1; - amsel <<= 1; - pctl <<= 4; - - bit++; - } -} - -#endif /* HAL_USE_PAL */ - -/** - * @} - */ diff --git a/os/hal/ports/TIVA/LLD/hal_pal_lld.h b/os/hal/ports/TIVA/LLD/hal_pal_lld.h deleted file mode 100644 index c0cd82b..0000000 --- a/os/hal/ports/TIVA/LLD/hal_pal_lld.h +++ /dev/null @@ -1,762 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TIVA/LLD/pal_lld.h - * @brief TM4C123x/TM4C129x PAL subsystem low level driver header. - * - * @addtogroup PAL - * @{ - */ - -#ifndef HAL_PAL_LLD_H -#define HAL_PAL_LLD_H - -#if HAL_USE_PAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#undef PAL_MODE_RESET -#undef PAL_MODE_UNCONNECTED -#undef PAL_MODE_INPUT -#undef PAL_MODE_INPUT_PULLUP -#undef PAL_MODE_INPUT_PULLDOWN -#undef PAL_MODE_INPUT_ANALOG -#undef PAL_MODE_OUTPUT_PUSHPULL -#undef PAL_MODE_OUTPUT_OPENDRAIN - -/** - * @name TIVA-specific I/O mode flags - * @{ - */ -#define PAL_TIVA_DIR_MASK (1 << 0) -#define PAL_TIVA_DIR_INPUT (0 << 0) -#define PAL_TIVA_DIR_OUTPUT (1 << 0) - -#define PAL_TIVA_AFSEL_MASK (1 << 1) -#define PAL_TIVA_AFSEL_GPIO (0 << 1) -#define PAL_TIVA_AFSEL_ALTERNATE (1 << 1) - -#define PAL_TIVA_DR2R_MASK (1 << 2) -#define PAL_TIVA_DR2R_DISABLE (0 << 2) -#define PAL_TIVA_DR2R_ENABLE (1 << 2) - -#define PAL_TIVA_DR4R_MASK (1 << 3) -#define PAL_TIVA_DR4R_DISABLE (0 << 3) -#define PAL_TIVA_DR4R_ENABLE (1 << 3) - -#define PAL_TIVA_DR8R_MASK (1 << 4) -#define PAL_TIVA_DR8R_DISABLE (0 << 4) -#define PAL_TIVA_DR8R_ENABLE (1 << 4) - -#define PAL_TIVA_ODR_MASK (1 << 5) -#define PAL_TIVA_ODR_PUSHPULL (0 << 5) -#define PAL_TIVA_ODR_OPENDRAIN (1 << 5) - -#define PAL_TIVA_PUR_MASK (1 << 6) -#define PAL_TIVA_PUR_DISABLE (0 << 6) -#define PAL_TIVA_PUR_ENABLE (1 << 6) - -#define PAL_TIVA_PDR_MASK (1 << 7) -#define PAL_TIVA_PDR_DISABLE (0 << 7) -#define PAL_TIVA_PDR_ENABLE (1 << 7) - -#define PAL_TIVA_SLR_MASK (1 << 8) -#define PAL_TIVA_SLR_DISABLE (0 << 8) -#define PAL_TIVA_SLR_ENABLE (1 << 8) - -#define PAL_TIVA_DEN_MASK (1 << 9) -#define PAL_TIVA_DEN_DISABLE (0 << 9) -#define PAL_TIVA_DEN_ENABLE (1 << 9) - -#define PAL_TIVA_AMSEL_MASK (1 << 10) -#define PAL_TIVA_AMSEL_DISABLE (0 << 10) -#define PAL_TIVA_AMSEL_ENABLE (1 << 10) - -#define PAL_TIVA_PCTL_MASK (7 << 11) -#define PAL_TIVA_PCTL(n) ((n) << 11) - -/** - * @brief Alternate function. - * - * @param[in] n alternate function selector - */ -#define PAL_MODE_ALTERNATE(n) (PAL_TIVA_AFSEL_ALTERNATE | \ - PAL_TIVA_PCTL(n)) -/** - * @} - */ - -/** - * @name Standard I/O mode flags - * @{ - */ -/** - * @brief This mode is implemented as input. - */ -#define PAL_MODE_RESET PAL_MODE_INPUT - -/** - * @brief This mode is implemented as input with pull-up. - */ -#define PAL_MODE_UNCONNECTED PAL_MODE_INPUT_PULLUP - -/** - * @brief Regular input high-Z pad. - */ -#define PAL_MODE_INPUT (PAL_TIVA_DEN_ENABLE | \ - PAL_TIVA_DIR_INPUT) - -/** - * @brief Input pad with weak pull up resistor. - */ -#define PAL_MODE_INPUT_PULLUP (PAL_TIVA_DIR_INPUT | \ - PAL_TIVA_PUR_ENABLE | \ - PAL_TIVA_DEN_ENABLE) - -/** - * @brief Input pad with weak pull down resistor. - */ -#define PAL_MODE_INPUT_PULLDOWN (PAL_TIVA_DIR_INPUT | \ - PAL_TIVA_PDR_ENABLE | \ - PAL_TIVA_DEN_ENABLE) - -/** - * @brief Analog input mode. - */ -#define PAL_MODE_INPUT_ANALOG (PAL_TIVA_DEN_DISABLE | \ - PAL_TIVA_AMSEL_ENABLE) - -/** - * @brief Push-pull output pad. - */ -#define PAL_MODE_OUTPUT_PUSHPULL (PAL_TIVA_DIR_OUTPUT | \ - PAL_TIVA_DR2R_ENABLE | \ - PAL_TIVA_ODR_PUSHPULL | \ - PAL_TIVA_DEN_ENABLE) - -/** - * @brief Open-drain output pad. - */ -#define PAL_MODE_OUTPUT_OPENDRAIN (PAL_TIVA_DIR_OUTPUT | \ - PAL_TIVA_DR2R_ENABLE | \ - PAL_TIVA_ODR_OPENDRAIN | \ - PAL_TIVA_DEN_ENABLE) -/** - * @} - */ - -/** @brief GPIOA port identifier.*/ -#define IOPORT1 GPIOA - -/** @brief GPIOB port identifier.*/ -#define IOPORT2 GPIOB - -/** @brief GPIOC port identifier.*/ -#define IOPORT3 GPIOC - -/** @brief GPIOD port identifier.*/ -#define IOPORT4 GPIOD - -/** @brief GPIOE port identifier.*/ -#define IOPORT5 GPIOE - -/** @brief GPIOF port identifier.*/ -#define IOPORT6 GPIOF - -#if TIVA_HAS_GPIOG || defined(__DOXYGEN__) -/** @brief Port G setup data.*/ -#define IOPORT7 GPIOG -#endif /* TIVA_HAS_GPIOG.*/ - -#if TIVA_HAS_GPIOH || defined(__DOXYGEN__) -/** @brief Port H setup data.*/ -#define IOPORT8 GPIOH -#endif /* TIVA_HAS_GPIOH.*/ - -#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__) -/** @brief Port J setup data.*/ -#define IOPORT9 GPIOJ -#endif /* TIVA_HAS_GPIOJ.*/ - -#if TIVA_HAS_GPIOK || defined(__DOXYGEN__) -/** @brief Port K setup data.*/ -#define IOPORT10 GPIOK -#endif /* TIVA_HAS_GPIOK.*/ - -#if TIVA_HAS_GPIOL || defined(__DOXYGEN__) -/** @brief Port L setup data.*/ -#define IOPORT11 GPIOL -#endif /* TIVA_HAS_GPIOL.*/ - -#if TIVA_HAS_GPIOM || defined(__DOXYGEN__) -/** @brief Port M setup data.*/ -#define IOPORT12 GPIOM -#endif /* TIVA_HAS_GPIOM.*/ - -#if TIVA_HAS_GPION || defined(__DOXYGEN__) -/** @brief Port N setup data.*/ -#define IOPORT13 GPION -#endif /* TIVA_HAS_GPION.*/ - -#if TIVA_HAS_GPIOP || defined(__DOXYGEN__) -/** @brief Port P setup data.*/ -#define IOPORT14 GPIOP -#endif /* TIVA_HAS_GPIOP.*/ - -#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__) -/** @brief Port Q setup data.*/ -#define IOPORT15 GPIOQ -#endif /* TIVA_HAS_GPIOQ.*/ - -#if TIVA_HAS_GPIOR || defined(__DOXYGEN__) -/** @brief Port R setup data.*/ -#define IOPORT16 GPIOR -#endif /* TIVA_HAS_GPIOR.*/ - -#if TIVA_HAS_GPIOS || defined(__DOXYGEN__) -/** @brief Port S setup data.*/ -#define IOPORT17 GPIOS -#endif /* TIVA_HAS_GPIOS.*/ - -#if TIVA_HAS_GPIOT || defined(__DOXYGEN__) -/** @brief Port T setup data.*/ -#define IOPORT18 GPIOT -#endif /* TIVA_HAS_GPIOT.*/ - -/** - * @brief Width, in bits, of an I/O port. - */ -#define PAL_IOPORTS_WIDTH 8 - -/** - * @brief Whole port mask. - * @brief This macro specifies all the valid bits into a port. - */ -#define PAL_WHOLE_PORT ((ioportmask_t)0xFF) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -#if defined(TM4C123x) - -/** - * @brief GPIOA AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOA. When set - * to @p FALSE the APB bus is used to access GPIOA. - * @note The default is TRUE. - */ -#if !defined(TIVA_GPIO_GPIOA_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOA_USE_AHB TRUE -#endif - -/** - * @brief GPIOB AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOB. When set - * to @p FALSE the APB bus is used to access GPIOB. - * @note The default is TRUE. - */ -#if !defined(TIVA_GPIO_GPIOB_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOB_USE_AHB TRUE -#endif - -/** - * @brief GPIOC AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOC. When set - * to @p FALSE the APB bus is used to access GPIOC. - * @note The default is TRUE. - */ -#if !defined(TIVA_GPIO_GPIOC_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOC_USE_AHB TRUE -#endif - -/** - * @brief GPIOD AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOD. When set - * to @p FALSE the APB bus is used to access GPIOD. - * @note The default is TRUE. - */ -#if !defined(TIVA_GPIO_GPIOD_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOD_USE_AHB TRUE -#endif - -/** - * @brief GPIOE AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOE. When set - * to @p FALSE the APB bus is used to access GPIOE. - * @note The default is TRUE. - */ -#if !defined(TIVA_GPIO_GPIOE_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOE_USE_AHB TRUE -#endif - -/** - * @brief GPIOF AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOF. When set - * to @p FALSE the APB bus is used to access GPIOF. - * @note The default is TRUE. - */ -#if !defined(TIVA_GPIO_GPIOF_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOF_USE_AHB TRUE -#endif - -/** - * @brief GPIOG AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOG. When set - * to @p FALSE the APB bus is used to access GPIOG. - * @note The default is TRUE. - */ -#if !defined(TIVA_GPIO_GPIOG_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOG_USE_AHB TRUE -#endif - -/** - * @brief GPIOH AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOH. When set - * to @p FALSE the APB bus is used to access GPIOH. - * @note The default is TRUE. - */ -#if !defined(TIVA_GPIO_GPIOH_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOH_USE_AHB TRUE -#endif - -/** - * @brief GPIOJ AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOJ. When set - * to @p FALSE the APB bus is used to access GPIOJ. - * @note The default is TRUE. - */ -#if !defined(TIVA_GPIO_GPIOJ_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOJ_USE_AHB TRUE -#endif - -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if defined(TM4C123x) - -#if TIVA_GPIO_GPIOA_USE_AHB -#define GPIOA GPIOA_AHB -#else -#define GPIOA GPIOA_APB -#endif - -#if TIVA_GPIO_GPIOB_USE_AHB -#define GPIOB GPIOB_AHB -#else -#define GPIOB GPIOB_APB -#endif - -#if TIVA_GPIO_GPIOC_USE_AHB -#define GPIOC GPIOC_AHB -#else -#define GPIOC GPIOC_APB -#endif - -#if TIVA_GPIO_GPIOD_USE_AHB -#define GPIOD GPIOD_AHB -#else -#define GPIOD GPIOD_APB -#endif - -#if TIVA_GPIO_GPIOE_USE_AHB -#define GPIOE GPIOE_AHB -#else -#define GPIOE GPIOE_APB -#endif - -#if TIVA_GPIO_GPIOF_USE_AHB -#define GPIOF GPIOF_AHB -#else -#define GPIOF GPIOF_APB -#endif - -#if TIVA_GPIO_GPIOG_USE_AHB -#define GPIOG GPIOG_AHB -#else -#define GPIOG GPIOG_APB -#endif - -#if TIVA_GPIO_GPIOH_USE_AHB -#define GPIOH GPIOH_AHB -#else -#define GPIOH GPIOH_APB -#endif - -#if TIVA_GPIO_GPIOJ_USE_AHB -#define GPIOJ GPIOJ_AHB -#else -#define GPIOJ GPIOJ_APB -#endif - -#define GPIOK GPIOK_AHB -#define GPIOL GPIOL_AHB -#define GPIOM GPIOM_AHB -#define GPION GPION_AHB -#define GPIOP GPIOP_AHB -#define GPIOQ GPIOQ_AHB - -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief GPIO port setup info. - */ -typedef struct -{ - /** @brief Initial value for DATA register.*/ - uint32_t data; - /** @brief Initial value for DIR register.*/ - uint32_t dir; - /** @brief Initial value for AFSEL register.*/ - uint32_t afsel; - /** @brief Initial value for DR2R register.*/ - uint32_t dr2r; - /** @brief Initial value for DR4R register.*/ - uint32_t dr4r; - /** @brief Initial value for DR8R register.*/ - uint32_t dr8r; - /** @brief Initial value for ODR register.*/ - uint32_t odr; - /** @brief Initial value for PUR register.*/ - uint32_t pur; - /** @brief Initial value for PDR register.*/ - uint32_t pdr; - /** @brief Initial value for SLR register.*/ - uint32_t slr; - /** @brief Initial value for DEN register.*/ - uint32_t den; - /** @brief Initial value for AMSEL register.*/ - uint32_t amsel; - /** @brief Initial value for PCTL register.*/ - uint32_t pctl; -} tiva_gpio_setup_t; - -/** - * @brief Tiva GPIO static initializer. - * @details An instance of this structure must be passed to @p palInit() at - * system startup time in order to initialized the digital I/O - * subsystem. This represents only the initial setup, specific pads - * or whole ports can be reprogrammed at later time. - */ -typedef struct -{ - /** @brief Port A setup data.*/ - tiva_gpio_setup_t PAData; - /** @brief Port B setup data.*/ - tiva_gpio_setup_t PBData; - /** @brief Port C setup data.*/ - tiva_gpio_setup_t PCData; - /** @brief Port D setup data.*/ - tiva_gpio_setup_t PDData; - /** @brief Port E setup data.*/ - tiva_gpio_setup_t PEData; - /** @brief Port F setup data.*/ - tiva_gpio_setup_t PFData; - -#if TIVA_HAS_GPIOG || defined(__DOXYGEN__) - /** @brief Port G setup data.*/ - tiva_gpio_setup_t PGData; -#endif /* TIVA_HAS_GPIOG.*/ - -#if TIVA_HAS_GPIOH || defined(__DOXYGEN__) - /** @brief Port H setup data.*/ - tiva_gpio_setup_t PHData; -#endif /* TIVA_HAS_GPIOH.*/ - -#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__) - /** @brief Port J setup data.*/ - tiva_gpio_setup_t PJData; -#endif /* TIVA_HAS_GPIOJ.*/ - -#if TIVA_HAS_GPIOK || defined(__DOXYGEN__) - /** @brief Port K setup data.*/ - tiva_gpio_setup_t PKData; -#endif /* TIVA_HAS_GPIOK.*/ - -#if TIVA_HAS_GPIOL || defined(__DOXYGEN__) - /** @brief Port L setup data.*/ - tiva_gpio_setup_t PLData; -#endif /* TIVA_HAS_GPIOL.*/ - -#if TIVA_HAS_GPIOM || defined(__DOXYGEN__) - /** @brief Port M setup data.*/ - tiva_gpio_setup_t PMData; -#endif /* TIVA_HAS_GPIOM.*/ - -#if TIVA_HAS_GPION || defined(__DOXYGEN__) - /** @brief Port N setup data.*/ - tiva_gpio_setup_t PNData; -#endif /* TIVA_HAS_GPION.*/ - -#if TIVA_HAS_GPIOP || defined(__DOXYGEN__) - /** @brief Port P setup data.*/ - tiva_gpio_setup_t PPData; -#endif /* TIVA_HAS_GPIOP.*/ - -#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__) - /** @brief Port Q setup data.*/ - tiva_gpio_setup_t PQData; -#endif /* TIVA_HAS_GPIOQ.*/ - -#if TIVA_HAS_GPIOR || defined(__DOXYGEN__) - /** @brief Port R setup data.*/ - tiva_gpio_setup_t PRData; -#endif /* TIVA_HAS_GPIOR.*/ - -#if TIVA_HAS_GPIOS || defined(__DOXYGEN__) - /** @brief Port S setup data.*/ - tiva_gpio_setup_t PSData; -#endif /* TIVA_HAS_GPIOS.*/ - -#if TIVA_HAS_GPIOT || defined(__DOXYGEN__) - /** @brief Port T setup data.*/ - tiva_gpio_setup_t PTData; -#endif /* TIVA_HAS_GPIOT.*/ -} PALConfig; - -/** - * @brief Digital I/O port sized unsigned type. - */ -typedef uint32_t ioportmask_t; - -/** - * @brief Digital I/O modes. - */ -typedef uint32_t iomode_t; - -/** - * @brief Port Identifier. - */ -typedef GPIO_TypeDef *ioportid_t; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Low level PAL subsystem initialization. - * - * @param[in] config architecture-dependent ports configuration - * - * @notapi - */ -#define pal_lld_init(config) _pal_lld_init(config) - -/** - * @brief Reads the physical I/O port states. - * - * @param[in] port port identifier - * @return The port bits. - * - * @notapi - */ -#define pal_lld_readport(port) ((port)->DATA) - -/** - * @brief Reads the output latch. - * @details The purpose of this function is to read back the latched output - * value. - * - * @param[in] port port identifier - * @return The latched logical states. - * - * @notapi - */ -#define pal_lld_readlatch(port) ((port)->DATA) - -/** - * @brief Writes a bits mask on a I/O port. - * - * @param[in] port port identifier - * @param[in] bits bits to be written on the specified port - * - * @notapi - */ -#define pal_lld_writeport(port, bits) ((port)->DATA = (bits)) - -/** - * @brief Sets a bits mask on a I/O port. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] bits bits to be ORed on the specified port - * - * @notapi - */ -#define pal_lld_setport(port, bits) ((port)->MASKED_ACCESS[bits] = 0xFF) - -/** - * @brief Clears a bits mask on a I/O port. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] bits bits to be cleared on the specified port - * - * @notapi - */ -#define pal_lld_clearport(port, bits) ((port)->MASKED_ACCESS[bits] = 0) - -/** - * @brief Reads a group of bits. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset group bit offset within the port - * @return The group logical states. - * - * @notapi - */ -#define pal_lld_readgroup(port, mask, offset) \ - ((port)->MASKED_ACCESS[(mask) << (offset)]) - -/** - * @brief Writes a group of bits. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset group bit offset within the port - * @param[in] bits bits to be written. Values exceeding the group width - * are masked. - * - * @notapi - */ -#define pal_lld_writegroup(port, mask, offset, bits) \ - ((port)->MASKED_ACCESS[(mask) << (offset)] = (bits)) - -/** - * @brief Pads group mode setup. - * @details This function programs a pads group belonging to the same port - * with the specified mode. - * @note Programming an unknown or unsupported mode is silently ignored. - * - * @param[in] port port identifier - * @param[in] mask group mask - * @param[in] offset group bit offset within the port - * @param[in] mode group mode - * - * @notapi - */ -#define pal_lld_setgroupmode(port, mask, offset, mode) \ - _pal_lld_setgroupmode(port, mask << offset, mode) - -/** - * @brief Reads a logical state from an I/O pad. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * @return The logical state. - * @retval PAL_LOW low logical state. - * @retval PAL_HIGH high logical state. - * - * @notapi - */ -#define pal_lld_readpad(port, pad) ((port)->MASKED_ACCESS[1 << (pad)]) - -/** - * @brief Writes a logical state on an output pad. - * @note This function is not meant to be invoked directly by the - * application code. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * @param[in] bit logical value, the value must be @p PAL_LOW or - * @p PAL_HIGH - * - * @notapi - */ -#define pal_lld_writepad(port, pad, bit) \ - ((port)->MASKED_ACCESS[1 << (pad)] = (bit)) - -/** - * @brief Sets a pad logical state to @p PAL_HIGH. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * - * @notapi - */ -#define pal_lld_setpad(port, pad) \ - ((port)->MASKED_ACCESS[1 << (pad)] = 1 << (pad)) - -/** - * @brief Clears a pad logical state to @p PAL_LOW. - * @note The @ref PAL provides a default software implementation of this - * functionality, implement this function if can optimize it by using - * special hardware functionalities or special coding. - * - * @param[in] port port identifier - * @param[in] pad pad number within the port - * - * @notapi - */ -#define pal_lld_clearpad(port, pad) \ - ((port)->MASKED_ACCESS[1 << (pad)] = 0) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern const PALConfig pal_default_config; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void _pal_lld_init(const PALConfig *config); - void _pal_lld_setgroupmode(ioportid_t port, - ioportmask_t mask, - iomode_t mode); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_PAL */ - -#endif /* HAL_PAL_LLD_H */ - -/** - * @} - */ diff --git a/os/hal/ports/TIVA/LLD/hal_pwm_lld.c b/os/hal/ports/TIVA/LLD/hal_pwm_lld.c deleted file mode 100644 index ad7c587..0000000 --- a/os/hal/ports/TIVA/LLD/hal_pwm_lld.c +++ /dev/null @@ -1,585 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TIVA/LLD/pwm_lld.c - * @brief TM4C123x/TM4C129x PWM subsystem low level driver. - * - * @addtogroup PWM - * @{ - */ - -#include "hal.h" - -#if HAL_USE_PWM || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#define PWM_INT_CMPBD (1 << 5) -#define PWM_INT_CMPBU (1 << 4) -#define PWM_INT_CMPAD (1 << 3) -#define PWM_INT_CMPAU (1 << 2) -#define PWM_INT_CNTLOAD (1 << 1) -#define PWM_INT_CNTZERO (1 << 0) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief PWMD1 driver identifier. - */ -#if TIVA_PWM_USE_PWM0 || defined(__DOXYGEN__) -PWMDriver PWMD1; -#endif - -/** - * @brief PWMD2 driver identifier. - */ -#if TIVA_PWM_USE_PWM1 || defined(__DOXYGEN__) -PWMDriver PWMD2; -#endif - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Common PWM Generator IRQ handler. - * @note It is assumed that the various sources are only activated if the - * associated callback pointer is not equal to @p NULL in order to not - * perform an extra check in a potentially critical interrupt handler. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] i pwm generator number - */ -static void pwm_lld_serve_generator_interrupt (PWMDriver *pwmp, uint8_t i) -{ - uint32_t isc; - - isc = pwmp->pwm->PWM[i].ISC; - pwmp->pwm->PWM[i].ISC = isc; - - if (((isc & PWM_INT_CMPAD) != 0) && - (pwmp->config->channels[i * 2 + 0].callback != NULL)) { - pwmp->config->channels[i * 2 + 0].callback(pwmp); - } - - if (((isc & PWM_INT_CMPAU) != 0) && - (pwmp->config->channels[i * 2 + 0].callback != NULL)) { - pwmp->config->channels[i * 2 + 0].callback(pwmp); - } - - if (((isc & PWM_INT_CMPBD) != 0) && - (pwmp->config->channels[i * 2 + 1].callback != NULL)) { - pwmp->config->channels[i * 2 + 1].callback(pwmp); - } - - if (((isc & PWM_INT_CMPBU) != 0) && - (pwmp->config->channels[i * 2 + 1].callback != NULL)) { - pwmp->config->channels[i * 2 + 1].callback(pwmp); - } - - if (((isc & PWM_INT_CNTLOAD) != 0) && (pwmp->config->callback != NULL)) { - pwmp->config->callback(pwmp); - } - - if (((isc & PWM_INT_CNTZERO) != 0) && (pwmp->config->callback != NULL)) { - pwmp->config->callback(pwmp); - } -} - -/** - * @brief Common PWM fault IRQ handler. - * - * @param[in] pwmp pointer to a @p PWMDriver object - */ -static void pwm_lld_serve_fault_interrupt (PWMDriver *pwmp) -{ - (void) pwmp; -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if TIVA_PWM_USE_PWM0 -#if !defined(TIVA_PWM0FAULT_HANDLER) -#error "TIVA_PWM0FAULT_HANDLER not defined" -#endif -/* - * @brief PWM0 Fault handler - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_PWM0FAULT_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - pwm_lld_serve_fault_interrupt(&PWMD1); - - OSAL_IRQ_EPILOGUE(); -} - -#if !defined(TIVA_PWM0GEN0_HANDLER) -#error "TIVA_PWM0GEN0_HANDLER not defined" -#endif -/* - * @brief PWM0 Generator 0 handler - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_PWM0GEN0_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - pwm_lld_serve_generator_interrupt(&PWMD1, 0); - - OSAL_IRQ_EPILOGUE(); -} - -#if !defined(TIVA_PWM0GEN1_HANDLER) -#error "TIVA_PWM0GEN1_HANDLER not defined" -#endif -/* - * @brief PWM0 Generator 1 handler - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_PWM0GEN1_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - pwm_lld_serve_generator_interrupt(&PWMD1, 1); - - OSAL_IRQ_EPILOGUE(); -} - -#if !defined(TIVA_PWM0GEN2_HANDLER) -#error "TIVA_PWM0GEN2_HANDLER not defined" -#endif -/* - * @brief PWM0 Generator 2 handler - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_PWM0GEN2_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - pwm_lld_serve_generator_interrupt(&PWMD1, 2); - - OSAL_IRQ_EPILOGUE(); -} - -#if !defined(TIVA_PWM0GEN3_HANDLER) -#error "TIVA_PWM0GEN3_HANDLER not defined" -#endif -/* - * @brief PWM0 Generator 3 handler - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_PWM0GEN3_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - pwm_lld_serve_generator_interrupt(&PWMD1, 3); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_PWM_USE_PWM1 -#if !defined(TIVA_PWM1FAULT_HANDLER) -#error "TIVA_PWM1FAULT_HANDLER not defined" -#endif -/* - * @brief PWM1 Fault handler - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_PWM1FAULT_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - pwm_lld_serve_fault_interrupt(&PWMD2); - - OSAL_IRQ_EPILOGUE(); -} - -#if !defined(TIVA_PWM1GEN0_HANDLER) -#error "TIVA_PWM1GEN0_HANDLER not defined" -#endif -/* - * @brief PWM1 Generator 0 handler - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_PWM1GEN0_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - pwm_lld_serve_generator_interrupt(&PWMD2, 0); - - OSAL_IRQ_EPILOGUE(); -} - -#if !defined(TIVA_PWM1GEN1_HANDLER) -#error "TIVA_PWM1GEN1_HANDLER not defined" -#endif -/* - * @brief PWM1 Generator 1 handler - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_PWM1GEN1_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - pwm_lld_serve_generator_interrupt(&PWMD2, 1); - - OSAL_IRQ_EPILOGUE(); -} - -#if !defined(TIVA_PWM1GEN2_HANDLER) -#error "TIVA_PWM1GEN2_HANDLER not defined" -#endif -/* - * @brief PWM1 Generator 2 handler - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_PWM1GEN2_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - pwm_lld_serve_generator_interrupt(&PWMD2, 2); - - OSAL_IRQ_EPILOGUE(); -} - -#if !defined(TIVA_PWM1GEN3_HANDLER) -#error "TIVA_PWM1GEN3_HANDLER not defined" -#endif -/* - * @brief PWM1 Generator 3 handler - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_PWM1GEN3_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - pwm_lld_serve_generator_interrupt(&PWMD2, 3); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level PWM driver initialization. - * - * @notapi - */ -void pwm_lld_init(void) -{ - /* Driver initialization.*/ -#if TIVA_PWM_USE_PWM0 - pwmObjectInit(&PWMD1); - PWMD1.channels = PWM_CHANNELS; - PWMD1.pwm = PWM0; -#endif - -#if TIVA_PWM_USE_PWM1 - pwmObjectInit(&PWMD2); - PWMD2.channels = PWM_CHANNELS; - PWMD2.pwm = PWM1; -#endif -} - -/** - * @brief Configures and activates the PWM peripheral. - * @note Starting a driver that is already in the @p PWM_READY state - * disables all the active channels. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * - * @notapi - */ -void pwm_lld_start(PWMDriver *pwmp) -{ - uint8_t i; - uint32_t invert = 0; - uint32_t enable = 0; - - if (pwmp->state == PWM_STOP) { - /* Clock activation.*/ -#if TIVA_PWM_USE_PWM0 - if (&PWMD1 == pwmp) { - SYSCTL->RCGCPWM |= (1 << 0); - - while (!(SYSCTL->PRPWM & (1 << 0))) - ; - - nvicEnableVector(TIVA_PWM0FAULT_NUMBER, - TIVA_PWM_PWM0_FAULT_IRQ_PRIORITY); - nvicEnableVector(TIVA_PWM0GEN0_NUMBER, TIVA_PWM_PWM0_0_IRQ_PRIORITY); - nvicEnableVector(TIVA_PWM0GEN1_NUMBER, TIVA_PWM_PWM0_1_IRQ_PRIORITY); - nvicEnableVector(TIVA_PWM0GEN2_NUMBER, TIVA_PWM_PWM0_2_IRQ_PRIORITY); - nvicEnableVector(TIVA_PWM0GEN3_NUMBER, TIVA_PWM_PWM0_3_IRQ_PRIORITY); - } -#endif - -#if TIVA_PWM_USE_PWM1 - if (&PWMD2 == pwmp) { - SYSCTL->RCGCPWM |= (1 << 1); - - while (!(SYSCTL->PRPWM & (1 << 1))) - ; - - nvicEnableVector(TIVA_PWM1FAULT_NUMBER, - TIVA_PWM_PWM1_FAULT_IRQ_PRIORITY); - nvicEnableVector(TIVA_PWM1GEN0_NUMBER, TIVA_PWM_PWM1_0_IRQ_PRIORITY); - nvicEnableVector(TIVA_PWM1GEN1_NUMBER, TIVA_PWM_PWM1_1_IRQ_PRIORITY); - nvicEnableVector(TIVA_PWM1GEN2_NUMBER, TIVA_PWM_PWM1_2_IRQ_PRIORITY); - nvicEnableVector(TIVA_PWM1GEN3_NUMBER, TIVA_PWM_PWM1_3_IRQ_PRIORITY); - } -#endif - } - else { - /* Driver re-configuration scenario, it must be stopped first.*/ - pwmp->pwm->PWM[0].CTL = 0; - pwmp->pwm->PWM[1].CTL = 0; - pwmp->pwm->PWM[2].CTL = 0; - pwmp->pwm->PWM[3].CTL = 0; - } - - /* Timer configuration.*/ - for (i = 0; i < (PWM_CHANNELS >> 1); i++) { - pwmp->pwm->PWM[i].CTL = 0; - pwmp->pwm->PWM[i].GEN[0] = 0x08C; - pwmp->pwm->PWM[i].GEN[1] = 0x80C; - pwmp->pwm->PWM[i].LOAD = (uint16_t)(pwmp->config->frequency - 1); - pwmp->pwm->PWM[i].CMP[0] = (uint16_t)(pwmp->period - 1); - pwmp->pwm->PWM[i].CMP[1] = (uint16_t)(pwmp->period - 1); - } - - /* Output enables and polarities setup.*/ - for (i = 0; i < PWM_CHANNELS; i++) { - switch (pwmp->config->channels[i].mode & PWM_OUTPUT_MASK) { - case PWM_OUTPUT_DISABLED: - enable &= ~(1 << i); - break; - case PWM_OUTPUT_ACTIVE_LOW: - invert |= (1 << i); - enable |= (1 << i); - break; - case PWM_OUTPUT_ACTIVE_HIGH: - invert &= ~(1 << i); - enable |= (1 << i); - break; - default: - ; - } - } - - pwmp->pwm->INVERT = invert; - pwmp->pwm->ENABLE = enable; - pwmp->pwm->ISC = 0xFFFFFFFF; -} - -/** - * @brief Deactivates the PWM peripheral. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * - * @notapi - */ -void pwm_lld_stop(PWMDriver *pwmp) -{ - /* If in ready state then disables the PWM clock.*/ - if (pwmp->state == PWM_READY) { - pwmp->pwm->PWM[0].CTL = 0; - pwmp->pwm->PWM[1].CTL = 0; - pwmp->pwm->PWM[2].CTL = 0; - pwmp->pwm->PWM[3].CTL = 0; - -#if TIVA_PWM_USE_PWM0 - if (&PWMD1 == pwmp) { - nvicDisableVector(TIVA_PWM0FAULT_NUMBER); - nvicDisableVector(TIVA_PWM0GEN0_NUMBER); - nvicDisableVector(TIVA_PWM0GEN1_NUMBER); - nvicDisableVector(TIVA_PWM0GEN2_NUMBER); - nvicDisableVector(TIVA_PWM0GEN3_NUMBER); - SYSCTL->RCGCPWM &= ~(1 << 0); - } -#endif - -#if TIVA_PWM_USE_PWM1 - if (&PWMD2 == pwmp) { - nvicDisableVector(TIVA_PWM1FAULT_NUMBER); - nvicDisableVector(TIVA_PWM1GEN0_NUMBER); - nvicDisableVector(TIVA_PWM1GEN1_NUMBER); - nvicDisableVector(TIVA_PWM1GEN2_NUMBER); - nvicDisableVector(TIVA_PWM1GEN3_NUMBER); - SYSCTL->RCGCPWM &= ~(1 << 1); - } -#endif - } -} - -/** - * @brief Enables a PWM channel. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @post The channel is active using the specified configuration. - * @note The function has effect at the next cycle start. - * @note Channel notification is not enabled. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...channels-1) - * @param[in] width PWM pulse width as clock pulses number - * - * @notapi - */ -void pwm_lld_enable_channel(PWMDriver *pwmp, - pwmchannel_t channel, - pwmcnt_t width) -{ - /* Changing channel duty cycle on the fly.*/ - pwmp->pwm->PWM[channel >> 1].CMP[channel & 1] = width; - pwmp->pwm->PWM[channel >> 1].CTL |= (1 << 0); -} - -/** - * @brief Disables a PWM channel and its notification. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @post The channel is disabled and its output line returned to the - * idle state. - * @note The function has effect at the next cycle start. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...channels-1) - * - * @notapi - */ -void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel) -{ - pwmp->pwm->PWM[channel >> 1].CMP[channel & 1] = 0; - pwmp->pwm->PWM[channel >> 1].CTL &= ~(1 << 0); -} - -/** - * @brief Enables the periodic activation edge notification. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @note If the notification is already enabled then the call has no effect. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * - * @notapi - */ -void pwm_lld_enable_periodic_notification(PWMDriver *pwmp) -{ - uint32_t inten; - uint8_t i; - - /* If the IRQ is not already enabled care must be taken to clear it, - it is probably already pending because the timer is running.*/ - for(i = 0; i < (PWM_CHANNELS >> 1); i++) { - inten = pwmp->pwm->PWM[i].INTEN; - if ((inten & 0x03) == 0) { - pwmp->pwm->PWM[i].INTEN |= 0x03; - pwmp->pwm->PWM[i].ISC = 0x03; - } - } - - pwmp->pwm->INTEN = 0x3f; -} - -/** - * @brief Disables the periodic activation edge notification. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @note If the notification is already disabled then the call has no effect. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * - * @notapi - */ -void pwm_lld_disable_periodic_notification(PWMDriver *pwmp) -{ - pwmp->pwm->PWM[0].INTEN &= ~(0x03); - pwmp->pwm->PWM[1].INTEN &= ~(0x03); - pwmp->pwm->PWM[2].INTEN &= ~(0x03); - pwmp->pwm->PWM[3].INTEN &= ~(0x03); - pwmp->pwm->INTEN &= ~(0x3F); -} - -/** - * @brief Enables a channel de-activation edge notification. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @pre The channel must have been activated using @p pwmEnableChannel(). - * @note If the notification is already enabled then the call has no effect. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...channels-1) - * - * @notapi - */ -void pwm_lld_enable_channel_notification(PWMDriver *pwmp, - pwmchannel_t channel) -{ - uint32_t inten = pwmp->pwm->PWM[channel >> 1].INTEN; - - /* If the IRQ is not already enabled care must be taken to clear it, - it is probably already pending because the timer is running.*/ - if ((inten & (0x03 << (((channel & 1) * 2) + 2))) == 0) { - pwmp->pwm->PWM[channel >> 1].INTEN |= (0x03 << (((channel & 1) * 2) + 2)); - pwmp->pwm->PWM[channel >> 1].ISC = (0x03 << (((channel & 1) * 2) + 2)); - } -} - -/** - * @brief Disables a channel de-activation edge notification. - * @pre The PWM unit must have been activated using @p pwmStart(). - * @pre The channel must have been activated using @p pwmEnableChannel(). - * @note If the notification is already disabled then the call has no effect. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] channel PWM channel identifier (0...channels-1) - * - * @notapi - */ -void pwm_lld_disable_channel_notification(PWMDriver *pwmp, - pwmchannel_t channel) -{ - pwmp->pwm->PWM[channel >> 1].INTEN &= ~(0x03 << (((channel & 1) * 2) + 2)); -} - -#endif /* HAL_USE_PWM */ - -/** - * @} - */ diff --git a/os/hal/ports/TIVA/LLD/hal_pwm_lld.h b/os/hal/ports/TIVA/LLD/hal_pwm_lld.h deleted file mode 100644 index ac64fe1..0000000 --- a/os/hal/ports/TIVA/LLD/hal_pwm_lld.h +++ /dev/null @@ -1,372 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TIVA/LLD/pwm_lld.c - * @brief TM4C123x/TM4C129x PWM subsystem low level driver header. - * - * @addtogroup PWM - * @{ - */ - -#ifndef HAL_PWM_LLD_H -#define HAL_PWM_LLD_H - -#if HAL_USE_PWM || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Number of PWM channels per PWM driver. - */ -#define PWM_CHANNELS 8 - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ - -/** - * @brief PWMD1 driver enable switch. - * @details If set to @p TRUE the support for PWMD1 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_PWM_USE_PWM0) || defined(__DOXYGEN__) -#define TIVA_PWM_USE_PWM0 FALSE -#endif - -/** - * @brief PWMD2 driver enable switch. - * @details If set to @p TRUE the support for PWMD2 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_PWM_USE_PWM1) || defined(__DOXYGEN__) -#define TIVA_PWM_USE_PWM1 FALSE -#endif - -/** - * @brief PWMD1 fault interrupt priority level setting. - */ -#if !defined(TIVA_PWM_PWM0_FAULT_IRQ_PRIORITY) || defined (__DOXYGEN__) -#define TIVA_PWM_PWM0_FAULT_IRQ_PRIORITY -#endif - -/** - * @brief PWMD1 channel 0 & 1 interrupt priority level setting. - */ -#if !defined(TIVA_PWM_PWM0_0_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_PWM_PWM0_0_IRQ_PRIORITY 4 -#endif - -/** - * @brief PWMD1 channel 2 & 3 interrupt priority level setting. - */ -#if !defined(TIVA_PWM_PWM0_1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_PWM_PWM0_1_IRQ_PRIORITY 4 -#endif - -/** - * @brief PWMD1 channel 4 & 5 interrupt priority level setting. - */ -#if !defined(TIVA_PWM_PWM0_2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_PWM_PWM0_2_IRQ_PRIORITY 4 -#endif - -/** - * @brief PWMD1 channel 6 & 7 interrupt priority level setting. - */ -#if !defined(TIVA_PWM_PWM0_3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_PWM_PWM0_3_IRQ_PRIORITY 4 -#endif - -/** - * @brief PWMD2 fault interrupt priority level setting. - */ -#if !defined(TIVA_PWM_PWM1_FAULT_IRQ_PRIORITY) || defined (__DOXYGEN__) -#define TIVA_PWM_PWM1_FAULT_IRQ_PRIORITY -#endif - -/** - * @brief PWMD2 channel 0 & 1 interrupt priority level setting. - */ -#if !defined(TIVA_PWM_PWM1_0_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_PWM_PWM1_0_IRQ_PRIORITY 4 -#endif - -/** - * @brief PWMD2 channel 2 & 3 interrupt priority level setting. - */ -#if !defined(TIVA_PWM_PWM1_1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_PWM_PWM1_1_IRQ_PRIORITY 4 -#endif - -/** - * @brief PWMD2 channel 4 & 5 interrupt priority level setting. - */ -#if !defined(TIVA_PWM_PWM1_2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_PWM_PWM1_2_IRQ_PRIORITY 4 -#endif - -/** - * @brief PWMD2 channel 6 & 7 interrupt priority level setting. - */ -#if !defined(TIVA_PWM_PWM1_3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_PWM_PWM1_3_IRQ_PRIORITY 4 -#endif - -/** - * @} - */ - -/*===========================================================================*/ -/* Configuration checks. */ -/*===========================================================================*/ - -#if TIVA_PWM_USE_PWM0 && !TIVA_HAS_PWM0 -#error "PWM0 not present in the selected device" -#endif - -#if TIVA_PWM_USE_PWM1 && !TIVA_HAS_PWM1 -#error "PWM1 not present in the selected device" -#endif - -#if !TIVA_PWM_USE_PWM0 && !TIVA_PWM_USE_PWM1 -#error "PWM driver activated but no PWM peripheral assigned" -#endif - -#if TIVA_PWM_USE_PWM0 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM0_FAULT_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to PWM0 FAULT" -#endif - -#if TIVA_PWM_USE_PWM0 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM0_0_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to PWM0 GEN0" -#endif - -#if TIVA_PWM_USE_PWM0 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM0_1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to PWM0 GEN1" -#endif - -#if TIVA_PWM_USE_PWM0 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM0_2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to PWM0 GEN2" -#endif - -#if TIVA_PWM_USE_PWM0 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM0_3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to PWM0 GEN3" -#endif - -#if TIVA_PWM_USE_PWM1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM1_FAULT_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to PWM1 FAULT" -#endif - -#if TIVA_PWM_USE_PWM1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM1_0_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to PWM1 GEN0" -#endif - -#if TIVA_PWM_USE_PWM1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM1_1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to PWM1 GEN1" -#endif - -#if TIVA_PWM_USE_PWM1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM1_2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to PWM1 GEN2" -#endif - -#if TIVA_PWM_USE_PWM1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PWM_PWM1_3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to PWM1 GEN3" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a PWM mode. - */ -typedef uint32_t pwmmode_t; - -/** - * @brief Type of a PWM channel. - */ -typedef uint8_t pwmchannel_t; - -/** - * @brief Type of a channels mask. - */ -typedef uint32_t pwmchnmsk_t; - -/** - * @brief Type of a PWM counter. - */ -typedef uint16_t pwmcnt_t; - -/** - * @brief Type of a PWM driver channel configuration structure. - */ -typedef struct { - /** - * @brief Channel active logic level. - */ - pwmmode_t mode; - /** - * @brief Channel callback pointer. - * @note This callback is invoked on the channel compare event. If set to - * @p NULL then the callback is disabled. - */ - pwmcallback_t callback; - /* End of the mandatory fields.*/ -} PWMChannelConfig; - -/** - * @brief Type of a PWM driver configuration structure. - */ -typedef struct { - /** - * @brief Timer clock in Hz. - * @note The low level can use assertions in order to catch invalid - * frequency specifications. - */ - uint32_t frequency; - /** - * @brief PWM period in ticks. - * @note The low level can use assertions in order to catch invalid - * period specifications. - */ - pwmcnt_t period; - /** - * @brief Periodic callback pointer. - * @note This callback is invoked on PWM counter reset. If set to - * @p NULL then the callback is disabled. - */ - pwmcallback_t callback; - /** - * @brief Channels configurations. - */ - PWMChannelConfig channels[PWM_CHANNELS]; - /* End of the mandatory fields.*/ -} PWMConfig; - -/** - * @brief Structure representing a PWM driver. - */ -struct PWMDriver { - /** - * @brief Driver state. - */ - pwmstate_t state; - /** - * @brief Current driver configuration data. - */ - const PWMConfig *config; - /** - * @brief Current PWM period in ticks. - */ - pwmcnt_t period; - /** - * @brief Mask of the enabled channels. - */ - pwmchnmsk_t enabled; - /** - * @brief Number of channels in this instance. - */ - pwmchannel_t channels; -#if defined(PWM_DRIVER_EXT_FIELDS) - PWM_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the PWMx registers block. - */ - PWM_TypeDef *pwm; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/** - * @brief Changes the period the PWM peripheral. - * @details This function changes the period of a PWM unit that has already - * been activated using @p pwmStart(). - * @pre The PWM unit must have been activated using @p pwmStart(). - * @post The PWM unit period is changed to the new value. - * @note The function has effect at the next cycle start. - * @note If a period is specified that is shorter than the pulse width - * programmed in one of the channels then the behavior is not - * guaranteed. - * - * @param[in] pwmp pointer to a @p PWMDriver object - * @param[in] period new cycle time in ticks - * - * @notapi - */ -#define pwm_lld_change_period(pwmp, period) \ - ((pwmp)->pwm->PWM[0].LOAD = (uint16_t)((period) - 1)); \ - ((pwmp)->pwm->PWM[1].LOAD = (uint16_t)((period) - 1)); \ - ((pwmp)->pwm->PWM[2].LOAD = (uint16_t)((period) - 1)); \ - ((pwmp)->pwm->PWM[3].LOAD = (uint16_t)((period) - 1)) - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if TIVA_PWM_USE_PWM0 && !defined(__DOXYGEN__) -extern PWMDriver PWMD1; -#endif - -#if TIVA_PWM_USE_PWM1 && !defined(__DOXYGEN__) -extern PWMDriver PWMD2; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void pwm_lld_init(void); - void pwm_lld_start(PWMDriver *pwmp); - void pwm_lld_stop(PWMDriver *pwmp); - void pwm_lld_enable_channel(PWMDriver *pwmp, - pwmchannel_t channel, - pwmcnt_t width); - void pwm_lld_disable_channel(PWMDriver *pwmp, pwmchannel_t channel); - void pwm_lld_enable_periodic_notification(PWMDriver *pwmp); - void pwm_lld_disable_periodic_notification(PWMDriver *pwmp); - void pwm_lld_enable_channel_notification(PWMDriver *pwmp, - pwmchannel_t channel); - void pwm_lld_disable_channel_notification(PWMDriver *pwmp, - pwmchannel_t channel); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_PWM */ - -#endif /* HAL_PWM_LLD_H */ - -/** @} */ diff --git a/os/hal/ports/TIVA/LLD/hal_serial_lld.c b/os/hal/ports/TIVA/LLD/hal_serial_lld.c deleted file mode 100644 index 89d29da..0000000 --- a/os/hal/ports/TIVA/LLD/hal_serial_lld.c +++ /dev/null @@ -1,664 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TIVA/LLD/serial_lld.c - * @brief Tiva low level serial driver code. - * - * @addtogroup SERIAL - * @{ - */ - -#include "hal.h" - -#if HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief UART0 serial driver identifier. - */ -#if TIVA_SERIAL_USE_UART0 || defined(__DOXYGEN__) -SerialDriver SD1; -#endif - -/** - * @brief UART1 serial driver identifier. - */ -#if TIVA_SERIAL_USE_UART1 || defined(__DOXYGEN__) -SerialDriver SD2; -#endif - -/** - * @brief UART2 serial driver identifier. - */ -#if TIVA_SERIAL_USE_UART2 || defined(__DOXYGEN__) -SerialDriver SD3; -#endif - -/** - * @brief UART3 serial driver identifier. - */ -#if TIVA_SERIAL_USE_UART3 || defined(__DOXYGEN__) -SerialDriver SD4; -#endif - -/** - * @brief UART4 serial driver identifier. - */ -#if TIVA_SERIAL_USE_UART4 || defined(__DOXYGEN__) -SerialDriver SD5; -#endif - -/** - * @brief UART5 serial driver identifier. - */ -#if TIVA_SERIAL_USE_UART5 || defined(__DOXYGEN__) -SerialDriver SD6; -#endif - -/** - * @brief UART6 serial driver identifier. - */ -#if TIVA_SERIAL_USE_UART6 || defined(__DOXYGEN__) -SerialDriver SD7; -#endif - -/** - * @brief UART7 serial driver identifier. - */ -#if TIVA_SERIAL_USE_UART7 || defined(__DOXYGEN__) -SerialDriver SD8; -#endif - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/** - * @brief Driver default configuration. - */ -static const SerialConfig sd_default_config = -{ - SERIAL_DEFAULT_BITRATE, - TIVA_LCRH_FEN | TIVA_LCRH_WLEN_8, - TIVA_IFLS_TXIFLSEL_1_8_F | TIVA_IFLS_RXIFLSEL_1_8_E -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief UART initialization. - * - * @param[in] sdp communication channel associated to the UART - * @param[in] config the architecture-dependent serial driver configuration - */ -static void uart_init(SerialDriver *sdp, const SerialConfig *config) -{ - UART_TypeDef *u = sdp->uart; - uint32_t div; /* baud rate divisor */ - - /* disable the UART before any of the control registers are reprogrammed */ - u->CTL &= ~TIVA_CTL_UARTEN; - div = (((TIVA_SYSCLK * 8) / config->sc_speed) + 1) / 2; - u->IBRD = div / 64; /* integer portion of the baud rate divisor */ - u->FBRD = div % 64; /* fractional portion of the baud rate divisor */ - u->LCRH = config->sc_lcrh; /* set data format */ - u->IFLS = config->sc_ifls; - u->CTL |= TIVA_CTL_TXE | TIVA_CTL_RXE | TIVA_CTL_UARTEN; - u->IM |= TIVA_IM_RXIM | TIVA_IM_TXIM | TIVA_IM_RTIM; /* interrupts enable */ -} - -/** - * @brief UART de-initialization. - * - * @param[in] u pointer to an UART I/O block - */ -static void uart_deinit(UART_TypeDef *u) -{ - u->CTL &= ~TIVA_CTL_UARTEN; -} - -/** - * @brief Error handling routine. - * - * @param[in] sdp communication channel associated to the UART - * @param[in] err UART LSR register value - */ -static void set_error(SerialDriver *sdp, uint16_t err) -{ - eventflags_t sts = 0; - - if (err & TIVA_MIS_FEMIS) - sts |= SD_FRAMING_ERROR; - if (err & TIVA_MIS_PEMIS) - sts |= SD_PARITY_ERROR; - if (err & TIVA_MIS_BEMIS) - sts |= SD_BREAK_DETECTED; - if (err & TIVA_MIS_OEMIS) - sts |= SD_OVERRUN_ERROR; - osalSysLockFromISR(); - chnAddFlagsI(sdp, sts); - osalSysUnlockFromISR(); -} - -/** - * @brief Common IRQ handler. - * @note Tries hard to clear all the pending interrupt sources, we don't - * want to go through the whole ISR and have another interrupt soon - * after. - * - * @param[in] u pointer to an UART I/O block - * @param[in] sdp communication channel associated to the UART - */ -static void serial_serve_interrupt(SerialDriver *sdp) -{ - UART_TypeDef *u = sdp->uart; - uint16_t mis = u->MIS; - - u->ICR = mis; /* clear interrupts */ - - if (mis & (TIVA_MIS_FEMIS | TIVA_MIS_PEMIS | TIVA_MIS_BEMIS | TIVA_MIS_OEMIS)) { - set_error(sdp, mis); - } - - if ((mis & TIVA_MIS_RXMIS) || (mis & TIVA_MIS_RTMIS)) { - osalSysLockFromISR(); - if (iqIsEmptyI(&sdp->iqueue)) { - chnAddFlagsI(sdp, CHN_INPUT_AVAILABLE); - } - osalSysUnlockFromISR(); - while ((u->FR & TIVA_FR_RXFE) == 0) { - osalSysLockFromISR(); - if (iqPutI(&sdp->iqueue, u->DR) < Q_OK) { - chnAddFlagsI(sdp, SD_OVERRUN_ERROR); - } - osalSysUnlockFromISR(); - } - } - - if (mis & TIVA_MIS_TXMIS) { - while ((u->FR & TIVA_FR_TXFF) == 0) { - msg_t b; - osalSysLockFromISR(); - b = oqGetI(&sdp->oqueue); - osalSysUnlockFromISR(); - if (b < Q_OK) { - u->IM &= ~TIVA_IM_TXIM; - osalSysLockFromISR(); - chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); - osalSysUnlockFromISR(); - break; - } - u->DR = b; - } - } -} - -/** - * @brief - */ -static void fifo_load(SerialDriver *sdp) -{ - UART_TypeDef *u = sdp->uart; - - while ((u->FR & TIVA_FR_TXFF) == 0) { - msg_t b = oqGetI(&sdp->oqueue); - if (b < Q_OK) { - chnAddFlagsI(sdp, CHN_OUTPUT_EMPTY); - return; - } - u->DR = b; - } - u->IM |= TIVA_IM_TXIM; /* transmit interrupt enable */ -} - -/** - * @brief Driver SD1 output notification. - */ -#if TIVA_SERIAL_USE_UART0 || defined(__DOXYGEN__) -static void notify1(io_queue_t *qp) -{ - (void)qp; - fifo_load(&SD1); -} -#endif - -/** - * @brief Driver SD2 output notification. - */ -#if TIVA_SERIAL_USE_UART1 || defined(__DOXYGEN__) -static void notify2(io_queue_t *qp) -{ - (void)qp; - fifo_load(&SD2); -} -#endif - -/** - * @brief Driver SD3 output notification. - */ -#if TIVA_SERIAL_USE_UART2 || defined(__DOXYGEN__) -static void notify3(io_queue_t *qp) -{ - (void)qp; - fifo_load(&SD3); -} -#endif - -/** - * @brief Driver SD4 output notification. - */ -#if TIVA_SERIAL_USE_UART3 || defined(__DOXYGEN__) -static void notify4(io_queue_t *qp) -{ - (void)qp; - fifo_load(&SD4); -} -#endif - -/** - * @brief Driver SD5 output notification. - */ -#if TIVA_SERIAL_USE_UART4 || defined(__DOXYGEN__) -static void notify5(io_queue_t *qp) -{ - (void)qp; - fifo_load(&SD5); -} -#endif - -/** - * @brief Driver SD6 output notification. - */ -#if TIVA_SERIAL_USE_UART5 || defined(__DOXYGEN__) -static void notify6(io_queue_t *qp) -{ - (void)qp; - fifo_load(&SD6); -} -#endif - -/** - * @brief Driver SD7 output notification. - */ -#if TIVA_SERIAL_USE_UART6 || defined(__DOXYGEN__) -static void notify7(io_queue_t *qp) -{ - (void)qp; - fifo_load(&SD7); -} -#endif - -/** - * @brief Driver SD8 output notification. - */ -#if TIVA_SERIAL_USE_UART7 || defined(__DOXYGEN__) -static void notify8(io_queue_t *qp) -{ - (void)qp; - fifo_load(&SD8); -} -#endif - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -/** - * @brief UART0 IRQ handler. - */ -#if TIVA_SERIAL_USE_UART0 || defined(__DOXYGEN__) -#if !defined(TIVA_UART0_HANDLER) -#error "TIVA_UART0_HANDLER not defined" -#endif -CH_IRQ_HANDLER(TIVA_UART0_HANDLER) -{ - CH_IRQ_PROLOGUE(); - - serial_serve_interrupt(&SD1); - - CH_IRQ_EPILOGUE(); -} -#endif - -/** - * @brief UART1 IRQ handler. - */ -#if TIVA_SERIAL_USE_UART1 || defined(__DOXYGEN__) -CH_IRQ_HANDLER(TIVA_UART1_HANDLER) -{ - CH_IRQ_PROLOGUE(); - - serial_serve_interrupt(&SD2); - - CH_IRQ_EPILOGUE(); -} -#endif - -/** - * @brief UART2 IRQ handler. - */ -#if TIVA_SERIAL_USE_UART2 || defined(__DOXYGEN__) -CH_IRQ_HANDLER(TIVA_UART2_HANDLER) -{ - CH_IRQ_PROLOGUE(); - - serial_serve_interrupt(&SD3); - - CH_IRQ_EPILOGUE(); -} -#endif - -/** - * @brief UART3 IRQ handler. - */ -#if TIVA_SERIAL_USE_UART3 || defined(__DOXYGEN__) -CH_IRQ_HANDLER(TIVA_UART3_HANDLER) -{ - CH_IRQ_PROLOGUE(); - - serial_serve_interrupt(&SD4); - - CH_IRQ_EPILOGUE(); -} -#endif - -/** - * @brief UART4 IRQ handler. - */ -#if TIVA_SERIAL_USE_UART4 || defined(__DOXYGEN__) -CH_IRQ_HANDLER(TIVA_UART4_HANDLER) -{ - CH_IRQ_PROLOGUE(); - - serial_serve_interrupt(&SD5); - - CH_IRQ_EPILOGUE(); -} -#endif - -/** - * @brief UART5 IRQ handler. - */ -#if TIVA_SERIAL_USE_UART5 || defined(__DOXYGEN__) -CH_IRQ_HANDLER(TIVA_UART5_HANDLER) -{ - CH_IRQ_PROLOGUE(); - - serial_serve_interrupt(&SD6); - - CH_IRQ_EPILOGUE(); -} -#endif - -/** - * @brief UART6 IRQ handler. - */ -#if TIVA_SERIAL_USE_UART6 || defined(__DOXYGEN__) -CH_IRQ_HANDLER(TIVA_UART6_HANDLER) -{ - CH_IRQ_PROLOGUE(); - - serial_serve_interrupt(&SD7); - - CH_IRQ_EPILOGUE(); -} -#endif - -/** - * @brief UART7 IRQ handler. - */ -#if TIVA_SERIAL_USE_UART7 || defined(__DOXYGEN__) -CH_IRQ_HANDLER(TIVA_UART7_HANDLER) -{ - CH_IRQ_PROLOGUE(); - - serial_serve_interrupt(&SD8); - - CH_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level serial driver initialization. - */ -void sd_lld_init(void) -{ -#if TIVA_SERIAL_USE_UART0 - sdObjectInit(&SD1, NULL, notify1); - SD1.uart = UART0; -#endif - -#if TIVA_SERIAL_USE_UART1 - sdObjectInit(&SD2, NULL, notify2); - SD2.uart = UART1; -#endif - -#if TIVA_SERIAL_USE_UART2 - sdObjectInit(&SD3, NULL, notify3); - SD3.uart = UART2; -#endif - -#if TIVA_SERIAL_USE_UART3 - sdObjectInit(&SD4, NULL, notify4); - SD4.uart = UART3; -#endif - -#if TIVA_SERIAL_USE_UART4 - sdObjectInit(&SD5, NULL, notify5); - SD5.uart = UART4; -#endif - -#if TIVA_SERIAL_USE_UART5 - sdObjectInit(&SD6, NULL, notify6); - SD6.uart = UART5; -#endif - -#if TIVA_SERIAL_USE_UART6 - sdObjectInit(&SD7, NULL, notify7); - SD7.uart = UART6; -#endif - -#if TIVA_SERIAL_USE_UART7 - sdObjectInit(&SD8, NULL, notify8); - SD8.uart = UART7; -#endif -} - -/** - * @brief Low level serial driver configuration and (re)start. - * - * @param[in] sdp pointer to a @p SerialDriver object - * @param[in] config the architecture-dependent serial driver configuration. - * If this parameter is set to @p NULL then a default - * configuration is used. - */ -void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) -{ - if (config == NULL) - config = &sd_default_config; - - if (sdp->state == SD_STOP) { -#if TIVA_SERIAL_USE_UART0 - if (&SD1 == sdp) { - SYSCTL->RCGCUART |= (1 << 0); - - while (!(SYSCTL->PRUART & (1 << 0))) - ; - - nvicEnableVector(TIVA_UART0_NUMBER, TIVA_SERIAL_UART0_PRIORITY); - } -#endif -#if TIVA_SERIAL_USE_UART1 - if (&SD2 == sdp) { - SYSCTL->RCGCUART |= (1 << 1); - - while (!(SYSCTL->PRUART & (1 << 1))) - ; - - nvicEnableVector(TIVA_UART1_NUMBER, TIVA_SERIAL_UART1_PRIORITY); - } -#endif -#if TIVA_SERIAL_USE_UART2 - if (&SD3 == sdp) { - SYSCTL->RCGCUART |= (1 << 2); - - while (!(SYSCTL->PRUART & (1 << 2))) - ; - - nvicEnableVector(TIVA_UART2_NUMBER, TIVA_SERIAL_UART2_PRIORITY); - } -#endif -#if TIVA_SERIAL_USE_UART3 - if (&SD4 == sdp) { - SYSCTL->RCGCUART |= (1 << 3); - - while (!(SYSCTL->PRUART & (1 << 3))) - ; - - nvicEnableVector(TIVA_UART3_NUMBER, TIVA_SERIAL_UART3_PRIORITY); - } -#endif -#if TIVA_SERIAL_USE_UART4 - if (&SD5 == sdp) { - SYSCTL->RCGCUART |= (1 << 4); - - while (!(SYSCTL->PRUART & (1 << 4))) - ; - - nvicEnableVector(TIVA_UART4_NUMBER, TIVA_SERIAL_UART4_PRIORITY); - } -#endif -#if TIVA_SERIAL_USE_UART5 - if (&SD6 == sdp) { - SYSCTL->RCGCUART |= (1 << 5); - - while (!(SYSCTL->PRUART & (1 << 5))) - ; - - nvicEnableVector(TIVA_UART5_NUMBER, TIVA_SERIAL_UART5_PRIORITY); - } -#endif -#if TIVA_SERIAL_USE_UART6 - if (&SD7 == sdp) { - SYSCTL->RCGCUART |= (1 << 6); - - while (!(SYSCTL->PRUART & (1 << 6))) - ; - - nvicEnableVector(TIVA_UART6_NUMBER, TIVA_SERIAL_UART6_PRIORITY); - } -#endif -#if TIVA_SERIAL_USE_UART7 - if (&SD8 == sdp) { - SYSCTL->RCGCUART |= (1 << 7); - - while (!(SYSCTL->PRUART & (1 << 7))) - ; - - nvicEnableVector(TIVA_UART7_NUMBER, TIVA_SERIAL_UART7_PRIORITY); - } -#endif - } - uart_init(sdp, config); -} - -/** - * @brief Low level serial driver stop. - * @details De-initializes the UART, stops the associated clock, resets the - * interrupt vector. - * - * @param[in] sdp pointer to a @p SerialDriver object - */ -void sd_lld_stop(SerialDriver *sdp) -{ - if (sdp->state == SD_READY) { - uart_deinit(sdp->uart); -#if TIVA_SERIAL_USE_UART0 - if (&SD1 == sdp) { - SYSCTL->RCGCUART &= ~(1 << 0); /* disable UART0 module */ - nvicDisableVector(TIVA_UART0_NUMBER); - return; - } -#endif -#if TIVA_SERIAL_USE_UART1 - if (&SD2 == sdp) { - SYSCTL->RCGCUART &= ~(1 << 1); /* disable UART1 module */ - nvicDisableVector(TIVA_UART1_NUMBER); - return; - } -#endif -#if TIVA_SERIAL_USE_UART2 - if (&SD3 == sdp) { - SYSCTL->RCGCUART &= ~(1 << 2); /* disable UART2 module */ - nvicDisableVector(TIVA_UART2_NUMBER); - return; - } -#endif -#if TIVA_SERIAL_USE_UART3 - if (&SD4 == sdp) { - SYSCTL->RCGCUART &= ~(1 << 3); /* disable UART3 module */ - nvicDisableVector(TIVA_UART3_NUMBER); - return; - } -#endif -#if TIVA_SERIAL_USE_UART4 - if (&SD5 == sdp) { - SYSCTL->RCGCUART &= ~(1 << 4); /* disable UART4 module */ - nvicDisableVector(TIVA_UART4_NUMBER); - return; - } -#endif -#if TIVA_SERIAL_USE_UART5 - if (&SD6 == sdp) { - SYSCTL->RCGCUART &= ~(1 << 5); /* disable UART5 module */ - nvicDisableVector(TIVA_UART5_NUMBER); - return; - } -#endif -#if TIVA_SERIAL_USE_UART6 - if (&SD7 == sdp) { - SYSCTL->RCGCUART &= ~(1 << 6); /* disable UART6 module */ - nvicDisableVector(TIVA_UART6_NUMBER); - return; - } -#endif -#if TIVA_SERIAL_USE_UART7 - if (&SD8 == sdp) { - SYSCTL->RCGCUART &= ~(1 << 7); /* disable UART7 module */ - nvicDisableVector(TIVA_UART7_NUMBER); - return; - } -#endif - } -} - -#endif /* CH_HAL_USE_SERIAL */ - -/** @} */ diff --git a/os/hal/ports/TIVA/LLD/hal_serial_lld.h b/os/hal/ports/TIVA/LLD/hal_serial_lld.h deleted file mode 100644 index 203ef6a..0000000 --- a/os/hal/ports/TIVA/LLD/hal_serial_lld.h +++ /dev/null @@ -1,482 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TIVA/LLD/serial_lld.h - * @brief Tiva low level serial driver header. - * - * @addtogroup SERIAL - * @{ - */ - -#ifndef HAL_SERIAL_LLD_H -#define HAL_SERIAL_LLD_H - -#if HAL_USE_SERIAL || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name FR register bits definitions - * @{ - */ - -#define TIVA_FR_CTS (1 << 0) - -#define TIVA_FR_BUSY (1 << 3) - -#define TIVA_FR_RXFE (1 << 4) - -#define TIVA_FR_TXFF (1 << 5) - -#define TIVA_FR_RXFF (1 << 6) - -#define TIVA_FR_TXFE (1 << 7) - -/** - * @} - */ - -/** - * @name LCRH register bits definitions - * @{ - */ - -#define TIVA_LCRH_BRK (1 << 0) - -#define TIVA_LCRH_PEN (1 << 1) - -#define TIVA_LCRH_EPS (1 << 2) - -#define TIVA_LCRH_STP2 (1 << 3) - -#define TIVA_LCRH_FEN (1 << 4) - -#define TIVA_LCRH_WLEN_MASK (3 << 5) -#define TIVA_LCRH_WLEN_5 (0 << 5) -#define TIVA_LCRH_WLEN_6 (1 << 5) -#define TIVA_LCRH_WLEN_7 (2 << 5) -#define TIVA_LCRH_WLEN_8 (3 << 5) - -#define TIVA_LCRH_SPS (1 << 7) - -/** - * @} - */ - -/** - * @name CTL register bits definitions - * @{ - */ - -#define TIVA_CTL_UARTEN (1 << 0) - -#define TIVA_CTL_SIREN (1 << 1) - -#define TIVA_CTL_SIRLP (1 << 2) - -#define TIVA_CTL_SMART (1 << 3) - -#define TIVA_CTL_EOT (1 << 4) - -#define TIVA_CTL_HSE (1 << 5) - -#define TIVA_CTL_LBE (1 << 7) - -#define TIVA_CTL_TXE (1 << 8) - -#define TIVA_CTL_RXE (1 << 9) - -#define TIVA_CTL_RTS (1 << 11) - -#define TIVA_CTL_RTSEN (1 << 14) - -#define TIVA_CTL_CTSEN (1 << 15) - -/** - * @} - */ - -/** - * @name IFLS register bits definitions - * @{ - */ - -#define TIVA_IFLS_TXIFLSEL_MASK (7 << 0) -#define TIVA_IFLS_TXIFLSEL_1_8_F (0 << 0) -#define TIVA_IFLS_TXIFLSEL_1_4_F (1 << 0) -#define TIVA_IFLS_TXIFLSEL_1_2_F (2 << 0) -#define TIVA_IFLS_TXIFLSEL_3_4_F (3 << 0) -#define TIVA_IFLS_TXIFLSEL_7_8_F (4 << 0) - -#define TIVA_IFLS_RXIFLSEL_MASK (7 << 3) -#define TIVA_IFLS_RXIFLSEL_7_8_E (0 << 3) -#define TIVA_IFLS_RXIFLSEL_3_4_E (1 << 3) -#define TIVA_IFLS_RXIFLSEL_1_2_E (2 << 3) -#define TIVA_IFLS_RXIFLSEL_1_4_E (3 << 3) -#define TIVA_IFLS_RXIFLSEL_1_8_E (4 << 3) - -/** - * @} - */ - -/** - * @name MIS register bits definitions - * @{ - */ - -#define TIVA_MIS_CTSMIS (1 << 1) - -#define TIVA_MIS_RXMIS (1 << 4) - -#define TIVA_MIS_TXMIS (1 << 5) - -#define TIVA_MIS_RTMIS (1 << 6) - -#define TIVA_MIS_FEMIS (1 << 7) - -#define TIVA_MIS_PEMIS (1 << 8) - -#define TIVA_MIS_BEMIS (1 << 9) - -#define TIVA_MIS_OEMIS (1 << 10) - -#define TIVA_MIS_9BITMIS (1 << 12) - -/** - * @} - */ - -/** - * @name IM register bits definitions - * @{ - */ - -#define TIVA_IM_CTSIM (1 << 1) - -#define TIVA_IM_RXIM (1 << 4) - -#define TIVA_IM_TXIM (1 << 5) - -#define TIVA_IM_RTIM (1 << 6) - -#define TIVA_IM_FEIM (1 << 7) - -#define TIVA_IM_PEIM (1 << 8) - -#define TIVA_IM_BEIM (1 << 9) - -#define TIVA_IM_OEIM (1 << 10) - -#define TIVA_IM_9BITIM (1 << 12) - -/** - * @} - */ -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ - -/** - * @brief UART0 driver enable switch. - * @details If set to @p TRUE the support for UART0 is included. - * @note The default is @p TRUE. - */ -#if !defined(TIVA_SERIAL_USE_UART0) || defined(__DOXYGEN__) -#define TIVA_SERIAL_USE_UART0 FALSE -#endif - -/** - * @brief UART1 driver enable switch. - * @details If set to @p TRUE the support for UART1 is included. - * @note The default is @p FALSE . - */ -#if !defined(TIVA_SERIAL_USE_UART1) || defined(__DOXYGEN__) -#define TIVA_SERIAL_USE_UART1 FALSE -#endif - -/** - * @brief UART2 driver enable switch. - * @details If set to @p TRUE the support for UART2 is included. - * @note The default is @p FALSE . - */ -#if !defined(TIVA_SERIAL_USE_UART2) || defined(__DOXYGEN__) -#define TIVA_SERIAL_USE_UART2 FALSE -#endif - -/** - * @brief UART3 driver enable switch. - * @details If set to @p TRUE the support for UART3 is included. - * @note The default is @p FALSE . - */ -#if !defined(TIVA_SERIAL_USE_UART3) || defined(__DOXYGEN__) -#define TIVA_SERIAL_USE_UART3 FALSE -#endif - -/** - * @brief UART4 driver enable switch. - * @details If set to @p TRUE the support for UART4 is included. - * @note The default is @p FALSE . - */ -#if !defined(TIVA_SERIAL_USE_UART4) || defined(__DOXYGEN__) -#define TIVA_SERIAL_USE_UART4 FALSE -#endif - -/** - * @brief UART5 driver enable switch. - * @details If set to @p TRUE the support for UART5 is included. - * @note The default is @p FALSE . - */ -#if !defined(TIVA_SERIAL_USE_UART5) || defined(__DOXYGEN__) -#define TIVA_SERIAL_USE_UART5 FALSE -#endif - -/** - * @brief UART6 driver enable switch. - * @details If set to @p TRUE the support for UART6 is included. - * @note The default is @p FALSE . - */ -#if !defined(TIVA_SERIAL_USE_UART6) || defined(__DOXYGEN__) -#define TIVA_SERIAL_USE_UART6 FALSE -#endif - -/** - * @brief UART7 driver enable switch. - * @details If set to @p TRUE the support for UART7 is included. - * @note The default is @p FALSE . - */ -#if !defined(TIVA_SERIAL_USE_UART7) || defined(__DOXYGEN__) -#define TIVA_SERIAL_USE_UART7 FALSE -#endif - -/** - * @brief UART0 interrupt priority level setting. - */ -#if !defined(TIVA_SERIAL_UART0_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_SERIAL_UART0_PRIORITY 5 -#endif - -/** - * @brief UART1 interrupt priority level setting. - */ -#if !defined(TIVA_SERIAL_UART1_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_SERIAL_UART1_PRIORITY 5 -#endif - -/** - * @brief UART2 interrupt priority level setting. - */ -#if !defined(TIVA_SERIAL_UART2_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_SERIAL_UART2_PRIORITY 5 -#endif - -/** - * @brief UART3 interrupt priority level setting. - */ -#if !defined(TIVA_SERIAL_UART3_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_SERIAL_UART3_PRIORITY 5 -#endif - -/** - * @brief UART4 interrupt priority level setting. - */ -#if !defined(TIVA_SERIAL_UART4_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_SERIAL_UART4_PRIORITY 5 -#endif - -/** - * @brief UART5 interrupt priority level setting. - */ -#if !defined(TIVA_SERIAL_UART5_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_SERIAL_UART5_PRIORITY 5 -#endif - -/** - * @brief UART6 interrupt priority level setting. - */ -#if !defined(TIVA_SERIAL_UART6_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_SERIAL_UART6_PRIORITY 5 -#endif - -/** - * @brief UART7 interrupt priority level setting. - */ -#if !defined(TIVA_SERIAL_UART7_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_SERIAL_UART7_PRIORITY 5 -#endif - -/** - * @} - */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if !TIVA_SERIAL_USE_UART0 && !TIVA_SERIAL_USE_UART1 && \ - !TIVA_SERIAL_USE_UART2 && !TIVA_SERIAL_USE_UART3 && \ - !TIVA_SERIAL_USE_UART4 && !TIVA_SERIAL_USE_UART5 && \ - !TIVA_SERIAL_USE_UART6 && !TIVA_SERIAL_USE_UART7 -#error "SERIAL driver activated but no UART peripheral assigned" -#endif - -#if TIVA_SERIAL_USE_UART0 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART0_PRIORITY) -#error "Invalid IRQ priority assigned to UART0" -#endif - -#if TIVA_SERIAL_USE_UART1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART1_PRIORITY) -#error "Invalid IRQ priority assigned to UART1" -#endif - -#if TIVA_SERIAL_USE_UART2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART2_PRIORITY) -#error "Invalid IRQ priority assigned to UART2" -#endif - -#if TIVA_SERIAL_USE_UART3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART3_PRIORITY) -#error "Invalid IRQ priority assigned to UART3" -#endif - -#if TIVA_SERIAL_USE_UART4 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART4_PRIORITY) -#error "Invalid IRQ priority assigned to UART4" -#endif - -#if TIVA_SERIAL_USE_UART5 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART5_PRIORITY) -#error "Invalid IRQ priority assigned to UART5" -#endif - -#if TIVA_SERIAL_USE_UART6 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART6_PRIORITY) -#error "Invalid IRQ priority assigned to UART6" -#endif - -#if TIVA_SERIAL_USE_UART7 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SERIAL_UART7_PRIORITY) -#error "Invalid IRQ priority assigned to UART7" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Tiva Serial Driver configuration structure. - * @details An instance of this structure must be passed to @p sdStart() - * in order to configure and start a serial driver operations. - */ -typedef struct { - /** - * @brief Bit rate. - */ - uint32_t sc_speed; - /* End of the mandatory fields. */ - /** - * @brief Initialization value for the LCRH (Line Control) register. - */ - uint32_t sc_lcrh; - /** - * @brief Initialization value for the IFLS (Interrupt FIFO Level Select) - * register. - */ - uint32_t sc_ifls; -} SerialConfig; - -/** - * @brief @p SerialDriver specific data. - */ -#define _serial_driver_data \ - _base_asynchronous_channel_data \ - /* Driver state.*/ \ - sdstate_t state; \ - /* Input queue.*/ \ - input_queue_t iqueue; \ - /* Output queue.*/ \ - output_queue_t oqueue; \ - /* Input circular buffer.*/ \ - uint8_t ib[SERIAL_BUFFERS_SIZE]; \ - /* Output circular buffer.*/ \ - uint8_t ob[SERIAL_BUFFERS_SIZE]; \ - /* End of the mandatory fields.*/ \ - /* Pointer to the USART registers block.*/ \ - UART_TypeDef *uart; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if TIVA_SERIAL_USE_UART0 && !defined(__DOXYGEN__) -extern SerialDriver SD1; -#endif - -#if TIVA_SERIAL_USE_UART1 && !defined(__DOXYGEN__) -extern SerialDriver SD2; -#endif - -#if TIVA_SERIAL_USE_UART2 && !defined(__DOXYGEN__) -extern SerialDriver SD3; -#endif - -#if TIVA_SERIAL_USE_UART3 && !defined(__DOXYGEN__) -extern SerialDriver SD4; -#endif - -#if TIVA_SERIAL_USE_UART4 && !defined(__DOXYGEN__) -extern SerialDriver SD5; -#endif - -#if TIVA_SERIAL_USE_UART5 && !defined(__DOXYGEN__) -extern SerialDriver SD6; -#endif - -#if TIVA_SERIAL_USE_UART6 && !defined(__DOXYGEN__) -extern SerialDriver SD7; -#endif - -#if TIVA_SERIAL_USE_UART7 && !defined(__DOXYGEN__) -extern SerialDriver SD8; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void sd_lld_init(void); - void sd_lld_start(SerialDriver *sdp, const SerialConfig *config); - void sd_lld_stop(SerialDriver *sdp); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SERIAL */ - -#endif /* HAL_SERIAL_LLD_H */ - -/** @} */ diff --git a/os/hal/ports/TIVA/LLD/hal_spi_lld.c b/os/hal/ports/TIVA/LLD/hal_spi_lld.c deleted file mode 100644 index ded2b99..0000000 --- a/os/hal/ports/TIVA/LLD/hal_spi_lld.c +++ /dev/null @@ -1,685 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TIVA/LLD/spi_lld.c - * @brief TM4C123x/TM4C129x SPI subsystem low level driver. - * - * @addtogroup SPI - * @{ - */ - -#include "ch.h" -#include "hal.h" - -#if HAL_USE_SPI || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief SPI1 driver identifier. - */ -#if TIVA_SPI_USE_SSI0 || defined(__DOXYGEN__) -SPIDriver SPID1; -#endif - -/** - * @brief SPI2 driver identifier. - */ -#if TIVA_SPI_USE_SSI1 || defined(__DOXYGEN__) -SPIDriver SPID2; -#endif - -/** - * @brief SPI3 driver identifier. - */ -#if TIVA_SPI_USE_SSI2 || defined(__DOXYGEN__) -SPIDriver SPID3; -#endif - -/** - * @brief SPI4 driver identifier. - */ -#if TIVA_SPI_USE_SSI3 || defined(__DOXYGEN__) -SPIDriver SPID4; -#endif - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -static uint16_t dummytx; -static uint16_t dummyrx; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Common IRQ handler. - * - * @param[in] spip pointer to the @p SPIDriver object - */ -static void spi_serve_interrupt(SPIDriver *spip) -{ - SSI_TypeDef *ssi = spip->ssi; - uint32_t mis = ssi->MIS; - uint32_t dmachis = UDMA->CHIS; - - /* SPI error handling.*/ - if ((mis & (TIVA_MIS_RORMIS | TIVA_MIS_RTMIS)) != 0) { - TIVA_SPI_SSI_ERROR_HOOK(spip); - } - - if ( (dmachis & ( (1 << spip->dmarxnr) | (1 << spip->dmatxnr) ) ) == - ( (1 << spip->dmarxnr) | (1 << spip->dmatxnr) ) ) { - /* Clear DMA Channel interrupts.*/ - UDMA->CHIS = (1 << spip->dmarxnr) | (1 << spip->dmatxnr); - - /* Portable SPI ISR code defined in the high level driver, note, it is a - macro.*/ - _spi_isr_code(spip); - } -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if TIVA_SPI_USE_SSI0 || defined(__DOXYGEN__) -/** - * @brief SSI0 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_SSI0_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - spi_serve_interrupt(&SPID1); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_SPI_USE_SSI1 || defined(__DOXYGEN__) -/** - * @brief SSI1 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_SSI1_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - spi_serve_interrupt(&SPID2); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_SPI_USE_SSI2 || defined(__DOXYGEN__) -/** - * @brief SSI2 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_SSI2_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - spi_serve_interrupt(&SPID3); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_SPI_USE_SSI3 || defined(__DOXYGEN__) -/** - * @brief SSI3 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_SSI3_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - spi_serve_interrupt(&SPID4); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level SPI driver initialization. - * - * @notapi - */ -void spi_lld_init(void) -{ - dummytx = 0xFFFF; - -#if TIVA_SPI_USE_SSI0 - spiObjectInit(&SPID1); - SPID1.ssi = SSI0; - SPID1.dmarxnr = TIVA_SPI_SSI0_RX_UDMA_CHANNEL; - SPID1.dmatxnr = TIVA_SPI_SSI0_TX_UDMA_CHANNEL; - SPID1.rxchnmap = TIVA_SPI_SSI0_RX_UDMA_MAPPING; - SPID1.txchnmap = TIVA_SPI_SSI0_TX_UDMA_MAPPING; -#endif - -#if TIVA_SPI_USE_SSI1 - spiObjectInit(&SPID2); - SPID2.ssi = SSI1; - SPID2.dmarxnr = TIVA_SPI_SSI1_RX_UDMA_CHANNEL; - SPID2.dmatxnr = TIVA_SPI_SSI1_TX_UDMA_CHANNEL; - SPID2.rxchnmap = TIVA_SPI_SSI1_RX_UDMA_MAPPING; - SPID2.txchnmap = TIVA_SPI_SSI1_TX_UDMA_MAPPING; -#endif - -#if TIVA_SPI_USE_SSI2 - spiObjectInit(&SPID3); - SPID3.ssi = SSI2; - SPID3.dmarxnr = TIVA_SPI_SSI2_RX_UDMA_CHANNEL; - SPID3.dmatxnr = TIVA_SPI_SSI2_TX_UDMA_CHANNEL; - SPID3.rxchnmap = TIVA_SPI_SSI2_RX_UDMA_MAPPING; - SPID3.txchnmap = TIVA_SPI_SSI2_TX_UDMA_MAPPING; -#endif - -#if TIVA_SPI_USE_SSI3 - spiObjectInit(&SPID4); - SPID4.ssi = SSI3; - SPID4.dmarxnr = TIVA_SPI_SSI3_RX_UDMA_CHANNEL; - SPID4.dmatxnr = TIVA_SPI_SSI3_TX_UDMA_CHANNEL; - SPID4.rxchnmap = TIVA_SPI_SSI3_RX_UDMA_MAPPING; - SPID4.txchnmap = TIVA_SPI_SSI3_TX_UDMA_MAPPING; -#endif -} - -/** - * @brief Configures and activates the SPI peripheral. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_start(SPIDriver *spip) -{ - if (spip->state == SPI_STOP) { - /* Clock activation.*/ -#if TIVA_SPI_USE_SSI0 - if (&SPID1 == spip) { - bool b; - b = udmaChannelAllocate(spip->dmarxnr); - osalDbgAssert(!b, "channel already allocated"); - b = udmaChannelAllocate(spip->dmatxnr); - osalDbgAssert(!b, "channel already allocated"); - - /* Enable SSI0 module.*/ - SYSCTL->RCGCSSI |= (1 << 0); - while (!(SYSCTL->PRSSI & (1 << 0))) - ; - - nvicEnableVector(TIVA_SSI0_NUMBER, TIVA_SPI_SSI0_IRQ_PRIORITY); - } -#endif -#if TIVA_SPI_USE_SSI1 - if (&SPID2 == spip) { - bool b; - b = udmaChannelAllocate(spip->dmarxnr); - osalDbgAssert(!b, "channel already allocated"); - b = udmaChannelAllocate(spip->dmatxnr); - osalDbgAssert(!b, "channel already allocated"); - - /* Enable SSI0 module.*/ - SYSCTL->RCGCSSI |= (1 << 1); - while (!(SYSCTL->PRSSI & (1 << 1))) - ; - - nvicEnableVector(TIVA_SSI1_NUMBER, TIVA_SPI_SSI1_IRQ_PRIORITY); - } -#endif -#if TIVASPI_USE_SSI2 - if (&SPID2 == spip) { - bool b; - b = udmaChannelAllocate(spip->dmarxnr); - osalDbgAssert(!b, "channel already allocated"); - b = udmaChannelAllocate(spip->dmatxnr); - osalDbgAssert(!b, "channel already allocated"); - - /* Enable SSI0 module.*/ - SYSCTL->RCGCSSI |= (1 << 2); - while (!(SYSCTL->PRSSI & (1 << 2))) - ; - - nvicEnableVector(TIVA_SSI2_NUMBER, TIVA_SPI_SSI2_IRQ_PRIORITY); - } -#endif -#if TIVA_SPI_USE_SSI3 - if (&SPID2 == spip) { - bool b; - b = udmaChannelAllocate(spip->dmarxnr); - osalDbgAssert(!b, "channel already allocated"); - b = udmaChannelAllocate(spip->dmatxnr); - osalDbgAssert(!b, "channel already allocated"); - - /* Enable SSI0 module.*/ - SYSCTL->RCGCSSI |= (1 << 3); - while (!(SYSCTL->PRSSI & (1 << 3))) - ; - - nvicEnableVector(TIVA_SSI3_NUMBER, TIVA_SPI_SSI3_IRQ_PRIORITY); - } -#endif - - UDMA->CHMAP[spip->dmarxnr / 8] |= (spip->rxchnmap << (spip->dmarxnr % 8)); - UDMA->CHMAP[spip->dmatxnr / 8] |= (spip->txchnmap << (spip->dmatxnr % 8)); - } - /* Set master operation mode.*/ - spip->ssi->CR1 = 0; - - /* Clock configuration - System Clock.*/ - spip->ssi->CC = 0; - - /* Clear pending interrupts.*/ - spip->ssi->ICR = TIVA_ICR_RTIC | TIVA_ICR_RORIC; - - /* Enable Receive Time-Out and Receive Overrun Interrupts.*/ - spip->ssi->IM = TIVA_IM_RTIM | TIVA_IM_RORIM; - - /* Configure the clock prescale divisor.*/ - spip->ssi->CPSR = spip->config->cpsr; - - /* Serial clock rate, phase/polarity, data size, fixed SPI frame format.*/ - spip->ssi->CR0 = (spip->config->cr0 & ~TIVA_CR0_FRF_MASK) | TIVA_CR0_FRF(0); - - /* Enable SSI.*/ - spip->ssi->CR1 |= TIVA_CR1_SSE; - - /* Enable RX and TX DMA channels.*/ - spip->ssi->DMACTL = (TIVA_DMACTL_TXDMAE | TIVA_DMACTL_RXDMAE); -} - -/** - * @brief Deactivates the SPI peripheral. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_stop(SPIDriver *spip) -{ - if (spip->state != SPI_STOP) { - spip->ssi->CR1 = 0; - spip->ssi->CR0 = 0; - spip->ssi->CPSR = 0; - - udmaChannelRelease(spip->dmarxnr); - udmaChannelRelease(spip->dmatxnr); - -#if TIVA_SPI_USE_SSI0 - if (&SPID1 == spip) { - nvicDisableVector(TIVA_SSI0_NUMBER); - } -#endif -#if TIVA_SPI_USE_SSI1 - if (&SPID2 == spip) { - nvicDisableVector(TIVA_SSI1_NUMBER); - } -#endif -#if TIVA_SPI_USE_SSI2 - if (&SPID3 == spip) { - nvicDisableVector(TIVA_SSI2_NUMBER); - } -#endif -#if TIVA_SPI_USE_SSI3 - if (&SPID4 == spip) { - nvicDisableVector(TIVA_SSI3_NUMBER); - } -#endif - } -} - -/** - * @brief Asserts the slave select signal and prepares for transfers. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_select(SPIDriver *spip) -{ - palClearPad(spip->config->ssport, spip->config->sspad); -} - -/** - * @brief Deasserts the slave select signal. - * @details The previously selected peripheral is unselected. - * - * @param[in] spip pointer to the @p SPIDriver object - * - * @notapi - */ -void spi_lld_unselect(SPIDriver *spip) -{ - palSetPad(spip->config->ssport, spip->config->sspad); -} - -/** - * @brief Ignores data on the SPI bus. - * @details This function transmits a series of idle words on the SPI bus and - * ignores the received data. This function can be invoked even - * when a slave select signal has not been yet asserted. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be ignored - * - * @notapi - */ -void spi_lld_ignore(SPIDriver *spip, size_t n) -{ - tiva_udma_table_entry_t *primary = udmaControlTable.primary; - - if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) { - /* Configure for 8-bit transfers.*/ - primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | - UDMA_CHCTL_ARBSIZE_4 | - UDMA_CHCTL_XFERSIZE(n) | - UDMA_CHCTL_XFERMODE_BASIC; - - primary[spip->dmarxnr].srcendp = &spip->ssi->DR; - primary[spip->dmarxnr].dstendp = &dummyrx; - primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | - UDMA_CHCTL_ARBSIZE_4 | - UDMA_CHCTL_XFERSIZE(n) | - UDMA_CHCTL_XFERMODE_BASIC; - } - else { - /* Configure for 16-bit transfers.*/ - primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | - UDMA_CHCTL_ARBSIZE_4 | - UDMA_CHCTL_XFERSIZE(n) | - UDMA_CHCTL_XFERMODE_BASIC; - - primary[spip->dmarxnr].srcendp = &spip->ssi->DR; - primary[spip->dmarxnr].dstendp = &dummyrx; - primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | - UDMA_CHCTL_ARBSIZE_4 | - UDMA_CHCTL_XFERSIZE(n) | - UDMA_CHCTL_XFERMODE_BASIC; - } - - dmaChannelSingleBurst(spip->dmatxnr); - dmaChannelPrimary(spip->dmatxnr); - dmaChannelPriorityDefault(spip->dmatxnr); - dmaChannelEnableRequest(spip->dmatxnr); - - dmaChannelSingleBurst(spip->dmarxnr); - dmaChannelPrimary(spip->dmarxnr); - dmaChannelPriorityDefault(spip->dmarxnr); - dmaChannelEnableRequest(spip->dmarxnr); - - /* Enable DMA channels, when the TX channel is enabled the transfer starts.*/ - dmaChannelEnable(spip->dmarxnr); - dmaChannelEnable(spip->dmatxnr); -} - -/** - * @brief Exchanges data on the SPI bus. - * @details This asynchronous function starts a simultaneous transmit/receive - * operation. - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to be exchanged - * @param[in] txbuf the pointer to the transmit buffer - * @param[out] rxbuf the pointer to the receive buffer - * - * @notapi - */ -void spi_lld_exchange(SPIDriver *spip, size_t n, const void *txbuf, void *rxbuf) -{ - tiva_udma_table_entry_t *primary = udmaControlTable.primary; - - if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) { - /* Configure for 8-bit transfers.*/ - primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+n-1; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_8 | - UDMA_CHCTL_ARBSIZE_4 | - UDMA_CHCTL_XFERSIZE(n) | - UDMA_CHCTL_XFERMODE_BASIC; - - primary[spip->dmarxnr].srcendp = &spip->ssi->DR; - primary[spip->dmarxnr].dstendp = rxbuf+n-1; - primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_8 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | - UDMA_CHCTL_ARBSIZE_4 | - UDMA_CHCTL_XFERSIZE(n) | - UDMA_CHCTL_XFERMODE_BASIC; - } - else { - /* Configure for 16-bit transfers.*/ - primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+(n*2)-1; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_16 | - UDMA_CHCTL_ARBSIZE_4 | - UDMA_CHCTL_XFERSIZE(n) | - UDMA_CHCTL_XFERMODE_BASIC; - - primary[spip->dmarxnr].srcendp = &spip->ssi->DR; - primary[spip->dmarxnr].dstendp = rxbuf+(n*2)-1; - primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_16 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | - UDMA_CHCTL_ARBSIZE_4 | - UDMA_CHCTL_XFERSIZE(n) | - UDMA_CHCTL_XFERMODE_BASIC; - } - - dmaChannelSingleBurst(spip->dmatxnr); - dmaChannelPrimary(spip->dmatxnr); - dmaChannelPriorityDefault(spip->dmatxnr); - dmaChannelEnableRequest(spip->dmatxnr); - - dmaChannelSingleBurst(spip->dmarxnr); - dmaChannelPrimary(spip->dmarxnr); - dmaChannelPriorityDefault(spip->dmarxnr); - dmaChannelEnableRequest(spip->dmarxnr); - - /* Enable DMA channels, when the TX channel is enabled the transfer starts.*/ - dmaChannelEnable(spip->dmarxnr); - dmaChannelEnable(spip->dmatxnr); -} - -/** - * @brief Sends data over the SPI bus. - * @details This asynchronous function starts a transmit operation. - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to send - * @param[in] txbuf the pointer to the transmit buffer - * - * @notapi - */ -void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf) -{ - tiva_udma_table_entry_t *primary = udmaControlTable.primary; - - if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) { - /* Configure for 8-bit transfers.*/ - primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+n-1; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_8 | - UDMA_CHCTL_ARBSIZE_4 | - UDMA_CHCTL_XFERSIZE(n) | - UDMA_CHCTL_XFERMODE_BASIC; - - primary[spip->dmarxnr].dstendp = &spip->ssi->DR; - primary[spip->dmarxnr].srcendp = &dummyrx; - primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | - UDMA_CHCTL_ARBSIZE_4 | - UDMA_CHCTL_XFERSIZE(n) | - UDMA_CHCTL_XFERMODE_BASIC; - } - else { - /* Configure for 16-bit transfers.*/ - primary[spip->dmatxnr].srcendp = (volatile void *)txbuf+(n*2)-1; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_16 | - UDMA_CHCTL_ARBSIZE_4 | - UDMA_CHCTL_XFERSIZE(n) | - UDMA_CHCTL_XFERMODE_BASIC; - - primary[spip->dmarxnr].dstendp = &spip->ssi->DR; - primary[spip->dmarxnr].srcendp = &dummyrx; - primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | - UDMA_CHCTL_ARBSIZE_4 | - UDMA_CHCTL_XFERSIZE(n) | - UDMA_CHCTL_XFERMODE_BASIC; - } - - dmaChannelSingleBurst(spip->dmatxnr); - dmaChannelPrimary(spip->dmatxnr); - dmaChannelPriorityDefault(spip->dmatxnr); - dmaChannelEnableRequest(spip->dmatxnr); - - dmaChannelSingleBurst(spip->dmarxnr); - dmaChannelPrimary(spip->dmarxnr); - dmaChannelPriorityDefault(spip->dmarxnr); - dmaChannelEnableRequest(spip->dmarxnr); - - /* Enable DMA channels, when the TX channel is enabled the transfer starts.*/ - dmaChannelEnable(spip->dmarxnr); - dmaChannelEnable(spip->dmatxnr); -} - -/** - * @brief Receives data from the SPI bus. - * @details This asynchronous function starts a receive operation. - * @post At the end of the operation the configured callback is invoked. - * @note The buffers are organized as uint8_t arrays for data sizes below or - * equal to 8 bits else it is organized as uint16_t arrays. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] n number of words to receive - * @param[out] rxbuf the pointer to the receive buffer - * - * @notapi - */ -void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf) -{ - tiva_udma_table_entry_t *primary = udmaControlTable.primary; - - if ((spip->config->cr0 & TIVA_CR0_DSS_MASK) < 8) { - /* Configure for 8-bit transfers.*/ - primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | - UDMA_CHCTL_ARBSIZE_4 | - UDMA_CHCTL_XFERSIZE(n) | - UDMA_CHCTL_XFERMODE_BASIC; - - primary[spip->dmarxnr].srcendp = &spip->ssi->DR; - primary[spip->dmarxnr].dstendp = rxbuf+n-1; - primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_8 | UDMA_CHCTL_DSTINC_8 | - UDMA_CHCTL_SRCSIZE_8 | UDMA_CHCTL_SRCINC_0 | - UDMA_CHCTL_ARBSIZE_4 | - UDMA_CHCTL_XFERSIZE(n) | - UDMA_CHCTL_XFERMODE_BASIC; - } - else { - /* Configure for 16-bit transfers.*/ - primary[spip->dmatxnr].srcendp = (volatile void *)&dummytx; - primary[spip->dmatxnr].dstendp = &spip->ssi->DR; - primary[spip->dmatxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_0 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | - UDMA_CHCTL_ARBSIZE_4 | - UDMA_CHCTL_XFERSIZE(n) | - UDMA_CHCTL_XFERMODE_BASIC; - - primary[spip->dmarxnr].srcendp = &spip->ssi->DR; - primary[spip->dmarxnr].dstendp = rxbuf+(n*2)-1; - primary[spip->dmarxnr].chctl = UDMA_CHCTL_DSTSIZE_16 | UDMA_CHCTL_DSTINC_16 | - UDMA_CHCTL_SRCSIZE_16 | UDMA_CHCTL_SRCINC_0 | - UDMA_CHCTL_ARBSIZE_4 | - UDMA_CHCTL_XFERSIZE(n) | - UDMA_CHCTL_XFERMODE_BASIC; - } - - dmaChannelSingleBurst(spip->dmatxnr); - dmaChannelPrimary(spip->dmatxnr); - dmaChannelPriorityDefault(spip->dmatxnr); - dmaChannelEnableRequest(spip->dmatxnr); - - dmaChannelSingleBurst(spip->dmarxnr); - dmaChannelPrimary(spip->dmarxnr); - dmaChannelPriorityDefault(spip->dmarxnr); - dmaChannelEnableRequest(spip->dmarxnr); - - /* Enable DMA channels, when the TX channel is enabled the transfer starts.*/ - dmaChannelEnable(spip->dmarxnr); - dmaChannelEnable(spip->dmatxnr); -} - -/** - * @brief Exchanges one frame using a polled wait. - * @details This synchronous function exchanges one frame using a polled - * synchronization method. This function is useful when exchanging - * small amount of data on high speed channels, usually in this - * situation is much more efficient just wait for completion using - * polling than suspending the thread waiting for an interrupt. - * - * @param[in] spip pointer to the @p SPIDriver object - * @param[in] frame the data frame to send over the SPI bus - * @return The received data frame from the SPI bus. - */ -uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame) -{ - spip->ssi->DR = (uint32_t)frame; - while ((spip->ssi->SR & TIVA_SR_RNE) == 0) - ; - return (uint16_t)spip->ssi->DR; -} - -#endif /* HAL_USE_SPI */ - -/** @} */ diff --git a/os/hal/ports/TIVA/LLD/hal_spi_lld.h b/os/hal/ports/TIVA/LLD/hal_spi_lld.h deleted file mode 100644 index 2adc9ed..0000000 --- a/os/hal/ports/TIVA/LLD/hal_spi_lld.h +++ /dev/null @@ -1,388 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file TIVA/LLD/spi_lld.h - * @brief TM4C123x/TM4C129x SPI subsystem low level driver. - * - * @addtogroup SPI - * @{ - */ - -#ifndef HAL_SPI_LLD_H -#define HAL_SPI_LLD_H - -#if HAL_USE_SPI || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name Control 0 - * @{ - */ -#define TIVA_CR0_DSS_MASK 0x0F -#define TIVA_CR0_DSS(n) ((n-1) << 0) - -#define TIVA_CR0_FRF_MASK (3 << 4) -#define TIVA_CR0_FRF(n) ((n) << 4) - -#define TIVA_CR0_SPO (1 << 6) -#define TIVA_CR0_SPH (1 << 7) - -#define TIVA_CR0_SRC_MASK (0xFF << 8) -#define TIVA_CR0_SRC(n) ((n) << 8) -/** @} */ - -/** - * @name Control 1 - * @{ - */ -#define TIVA_CR1_LBM (1 << 0) -#define TIVA_CR1_SSE (1 << 1) -#define TIVA_CR1_MS (1 << 2) -#define TIVA_CR1_SOD (1 << 3) -#define TIVA_CR1_EOT (1 << 4) -/** @} */ - -/** - * @name Status - * @{ - */ -#define TIVA_SR_TFE (1 << 0) -#define TIVA_SR_TNF (1 << 1) -#define TIVA_SR_RNE (1 << 2) -#define TIVA_SR_RFF (1 << 3) -#define TIVA_SR_BSY (1 << 4) -/** @} */ - -/** - * @name Interrupt Mask - * @{ - */ -#define TIVA_IM_RORIM (1 << 0) -#define TIVA_IM_RTIM (1 << 1) -#define TIVA_IM_RXIM (1 << 2) -#define TIVA_IM_TXIM (1 << 3) -/** @} */ - -/** - * @name Interrupt Status - * @{ - */ -#define TIVA_IS_RORIS (1 << 0) -#define TIVA_IS_RTIS (1 << 1) -#define TIVA_IS_RXIS (1 << 2) -#define TIVA_IS_TXIS (1 << 3) -/** @} */ - -/** - * @name Masked Interrupt Status - * @{ - */ -#define TIVA_MIS_RORMIS (1 << 0) -#define TIVA_MIS_RTMIS (1 << 1) -#define TIVA_MIS_RXMIS (1 << 2) -#define TIVA_MIS_TXMIS (1 << 3) -/** @} */ - -/** - * @name Interrupt Clear - * @{ - */ -#define TIVA_ICR_RORIC (1 << 0) -#define TIVA_ICR_RTIC (1 << 1) -/** @} */ - -/** - * @name DMA Control - * @{ - */ -#define TIVA_DMACTL_RXDMAE (1 << 0) -#define TIVA_DMACTL_TXDMAE (1 << 1) -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ - -/** - * @brief SSI0 driver enable switch. - * @details If set to @p TRUE the support for SSI0 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_SPI_USE_SSI0) || defined(__DOXYGEN__) -#define TIVA_SPI_USE_SSI0 FALSE -#endif - -/** - * @brief SSI1 driver enable switch. - * @details If set to @p TRUE the support for SSI1 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_SPI_USE_SSI1) || defined(__DOXYGEN__) -#define TIVA_SPI_USE_SSI1 FALSE -#endif - -/** - * @brief SSI2 driver enable switch. - * @details If set to @p TRUE the support for SSI2 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_SPI_USE_SSI2) || defined(__DOXYGEN__) -#define TIVA_SPI_USE_SSI2 FALSE -#endif - -/** - * @brief SSI3 driver enable switch. - * @details If set to @p TRUE the support for SSI3 is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_SPI_USE_SSI3) || defined(__DOXYGEN__) -#define TIVA_SPI_USE_SSI3 FALSE -#endif - -/** - * @brief SPID1 interrupt priority level setting. - */ -#if !defined(TIVA_SPI_SSI0_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_SPI_SSI0_IRQ_PRIORITY 5 -#endif - -/** - * @brief SPID2 interrupt priority level setting. - */ -#if !defined(TIVA_SPI_SSI1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_SPI_SSI1_IRQ_PRIORITY 5 -#endif - -/** - * @brief SPID3 interrupt priority level setting. - */ -#if !defined(TIVA_SPI_SSI2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_SPI_SSI2_IRQ_PRIORITY 5 -#endif - -/** - * @brief SPID4 interrupt priority level setting. - */ -#if !defined(TIVA_SPI_SSI3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_SPI_SSI3_IRQ_PRIORITY 5 -#endif - -/** - * @brief SPI error hook. - */ -#if !defined(TIVA_SPI_SSI_ERROR_HOOK) || defined(__DOXYGEN__) -#define TIVA_SPI_SSI_ERROR_HOOK(spip) osalSysHalt("SSI failure") -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if TIVA_SPI_USE_SSI0 && !TIVA_HAS_SSI0 -#error "SSI0 not present in the selected device" -#endif - -#if TIVA_SPI_USE_SSI1 && !TIVA_HAS_SSI1 -#error "SSI1 not present in the selected device" -#endif - -#if TIVA_SPI_USE_SSI2 && !TIVA_HAS_SSI2 -#error "SSI2 not present in the selected device" -#endif - -#if TIVA_SPI_USE_SSI3 && !TIVA_HAS_SSI03 -#error "SSI3 not present in the selected device" -#endif - -#if !TIVA_SPI_USE_SSI0 && !TIVA_SPI_USE_SSI1 && !TIVA_SPI_USE_SSI2 && \ - !TIVA_SPI_USE_SSI3 -#error "SPI driver activated but no SSI peripheral assigned" -#endif - -#if TIVA_SPI_USE_SSI0 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SPI_SSI0_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SSI0" -#endif - -#if TIVA_SPI_USE_SSI1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SPI_SSI1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SSI1" -#endif - -#if TIVA_SPI_USE_SSI2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SPI_SSI2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SSI2" -#endif - -#if TM4C123x_SPI_USE_SSI3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SPI_SSI3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to SSI3" -#endif - -#if !defined(TIVA_UDMA_REQUIRED) -#define TIVA_UDMA_REQUIRED -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a structure representing an SPI driver. - */ -typedef struct SPIDriver SPIDriver; - -/** - * @brief SPI notification callback type. - * - * @param[in] spip pointer to the @p SPIDriver object triggering the - * callback - */ -typedef void (*spicallback_t)(SPIDriver *spip); - -/** - * @brief Driver configuration structure. - */ -typedef struct { - /** - * @brief Operation complete callback or @p NULL. - */ - spicallback_t end_cb; - /* End of the mandatory fields.*/ - /** - * @brief The chip select line port. - */ - ioportid_t ssport; - /** - * @brief The chip select line pad number. - */ - uint16_t sspad; - /** - * @brief SSI CR0 initialization data. - */ - uint16_t cr0; - /** - * @brief SSI CPSR initialization data. - */ - uint32_t cpsr; -} SPIConfig; - -/** - * @brief Structure representing a SPI driver. - */ -struct SPIDriver { - /** - * @brief Driver state. - */ - spistate_t state; - /** - * @brief Current configuration data. - */ - const SPIConfig *config; -#if SPI_USE_WAIT || defined(__DOXYGEN__) - /** - * @brief Waiting thread. - */ - thread_reference_t thread; -#endif /* SPI_USE_WAIT */ -#if SPI_USE_MUTUAL_EXCLUSION || defined(__DOXYGEN__) - /** - * @brief Mutex protecting the bus. - */ - mutex_t mutex; -#endif /* SPI_USE_MUTUAL_EXCLUSION */ -#if defined(SPI_DRIVER_EXT_FIELDS) - SPI_DRIVER_EXT_FIELDS -#endif - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the SSI registers block. - */ - SSI_TypeDef *ssi; - /** - * @brief Receive DMA channel number. - */ - uint8_t dmarxnr; - /** - * @brief Transmit DMA channel number. - */ - uint8_t dmatxnr; - /** - * @brief Receive DMA channel map. - */ - uint8_t rxchnmap; - /** - * @brief Transmit DMA channel map. - */ - uint8_t txchnmap; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if TIVA_SPI_USE_SSI0 && !defined(__DOXYGEN__) -extern SPIDriver SPID1; -#endif - -#if TIVA_SPI_USE_SSI1 && !defined(__DOXYGEN__) -extern SPIDriver SPID2; -#endif - -#if TIVA_SPI_USE_SSI2 && !defined(__DOXYGEN__) -extern SPIDriver SPID3; -#endif - -#if TIVA_SPI_USE_SSI3 && !defined(__DOXYGEN__) -extern SPIDriver SPID4; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void spi_lld_init(void); - void spi_lld_start(SPIDriver *spip); - void spi_lld_stop(SPIDriver *spip); - void spi_lld_select(SPIDriver *spip); - void spi_lld_unselect(SPIDriver *spip); - void spi_lld_ignore(SPIDriver *spip, size_t n); - void spi_lld_exchange(SPIDriver *spip, size_t n, - const void *txbuf, void *rxbuf); - void spi_lld_send(SPIDriver *spip, size_t n, const void *txbuf); - void spi_lld_receive(SPIDriver *spip, size_t n, void *rxbuf); - uint16_t spi_lld_polled_exchange(SPIDriver *spip, uint16_t frame); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_SPI */ - -#endif /* HAL_SPI_LLD_H */ - -/** @} */ diff --git a/os/hal/ports/TIVA/LLD/hal_st_lld.c b/os/hal/ports/TIVA/LLD/hal_st_lld.c deleted file mode 100644 index 30fdb8a..0000000 --- a/os/hal/ports/TIVA/LLD/hal_st_lld.c +++ /dev/null @@ -1,253 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file Tiva/LLD/st_lld.c - * @brief ST Driver subsystem low level driver code. - * - * @addtogroup ST - * @{ - */ - -#include "hal.h" - -#if (OSAL_ST_MODE != OSAL_ST_MODE_NONE) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING - -#if (TIVA_ST_USE_WIDE_TIMER == TRUE) - -#if TIVA_ST_TIMER_NUMBER == 0 -#define ST_HANDLER TIVA_WGPT0A_HANDLER -#define ST_NUMBER TIVA_WGPT0A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 0)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 0))) - -#elif TIVA_ST_TIMER_NUMBER == 1 -#define ST_HANDLER TIVA_WGPT1A_HANDLER -#define ST_NUMBER TIVA_WGPT1A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 1)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 1))) - -#elif TIVA_ST_TIMER_NUMBER == 2 -#define ST_HANDLER TIVA_WGPT2A_HANDLER -#define ST_NUMBER TIVA_WGPT2A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 2)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 2))) - -#elif TIVA_ST_TIMER_NUMBER == 3 -#define ST_HANDLER TIVA_WGPT3A_HANDLER -#define ST_NUMBER TIVA_WGPT3A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 3)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 3))) - -#elif TIVA_ST_TIMER_NUMBER == 4 -#define ST_HANDLER TIVA_WGPT4A_HANDLER -#define ST_NUMBER TIVA_WGPT4A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 4)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 4))) - -#elif TIVA_ST_TIMER_NUMBER == 5 -#define ST_HANDLER TIVA_WGPT5A_HANDLER -#define ST_NUMBER TIVA_WGPT5A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 5)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 5))) - -#else -#error "TIVA_ST_USE_TIMER specifies an unsupported timer" -#endif - -#if (ST_CLOCK_SRC / OSAL_ST_FREQUENCY) - 1 > 0xFFFF -#error "the selected ST frequency is not obtainable because TIM timer prescaler limits" -#endif - -#elif (TIVA_ST_USE_WIDE_TIMER == FALSE) - -#if TIVA_ST_TIMER_NUMBER == 0 -#define ST_HANDLER TIVA_GPT0A_HANDLER -#define ST_NUMBER TIVA_GPT0A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 0)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 0))) - -#elif TIVA_ST_TIMER_NUMBER == 1 -#define ST_HANDLER TIVA_GPT1A_HANDLER -#define ST_NUMBER TIVA_GPT1A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 1)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 1))) - -#elif TIVA_ST_TIMER_NUMBER == 2 -#define ST_HANDLER TIVA_GPT2A_HANDLER -#define ST_NUMBER TIVA_GPT2A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 2)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 2))) - -#elif TIVA_ST_TIMER_NUMBER == 3 -#define ST_HANDLER TIVA_GPT3A_HANDLER -#define ST_NUMBER TIVA_GPT3A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 3)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 3))) - -#elif TIVA_ST_TIMER_NUMBER == 4 -#define ST_HANDLER TIVA_GPT4A_HANDLER -#define ST_NUMBER TIVA_GPT4A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 4)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 4))) - -#elif TIVA_ST_TIMER_NUMBER == 5 -#define ST_HANDLER TIVA_GPT5A_HANDLER -#define ST_NUMBER TIVA_GPT5A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 5)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 5))) - -#else -#error "TIVA_ST_USE_TIMER specifies an unsupported timer" -#endif - -#if (TIVA_SYSCLK / OSAL_ST_FREQUENCY) - 1 > 0xFF -#error "the selected ST frequency is not obtainable because TIM timer prescaler limits" -#endif - -#endif - -#if TIVA_SYSCLK % OSAL_ST_FREQUENCY != 0 -#error "the selected ST frequency is not obtainable because integer rounding" -#endif - -#endif - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if (OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC) || defined(__DOXYGEN__) -/** - * @brief System Timer vector. - * @details This interrupt is used for system tick in periodic mode. - * - * @isr - */ -OSAL_IRQ_HANDLER(SysTick_Handler) -{ - OSAL_IRQ_PROLOGUE(); - - osalSysLockFromISR(); - osalOsTimerHandlerI(); - osalSysUnlockFromISR(); - - OSAL_IRQ_EPILOGUE(); -} -#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */ - -#if (OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING) || defined(__DOXYGEN__) -/** - * @brief GPT interrupt handler. - * @details This interrupt is used for system tick in free running mode. - * - * @isr - */ -OSAL_IRQ_HANDLER(ST_HANDLER) -{ - uint32_t mis; - - OSAL_IRQ_PROLOGUE(); - - mis = TIVA_ST_TIM->MIS; - TIVA_ST_TIM->ICR = mis; - - if (mis & GPTM_IMR_TAMIM) { - osalSysLockFromISR(); - osalOsTimerHandlerI(); - osalSysUnlockFromISR(); - } - - OSAL_IRQ_EPILOGUE(); -} -#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level ST driver initialization. - * - * @notapi - */ -void st_lld_init(void) -{ -#if OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING - /* Free running counter mode.*/ - - /* Enabling timer clock.*/ - ST_ENABLE_CLOCK(); - - /* Wait until timer peripheral is ready */ - ST_WAIT_CLOCK(); - - /* Initializing the counter in free running down mode.*/ - TIVA_ST_TIM->CTL = 0; - TIVA_ST_TIM->CFG = GPTM_CFG_CFG_SPLIT; /* Timer split mode */ - TIVA_ST_TIM->TAMR = (GPTM_TAMR_TAMR_PERIODIC |/* Periodic mode */ - GPTM_TAMR_TAMIE | /* Match interrupt enable */ - GPTM_TAMR_TASNAPS); /* Snapshot mode */ - - TIVA_ST_TIM->TAPR = (TIVA_SYSCLK / OSAL_ST_FREQUENCY) - 1; - TIVA_ST_TIM->CTL = (GPTM_CTL_TAEN | /* Timer A enable */ - GPTM_CTL_TASTALL); /* Timer A stall when paused */ - - /* IRQ enabled.*/ - nvicEnableVector(ST_NUMBER, TIVA_ST_IRQ_PRIORITY); -#endif /* OSAL_ST_MODE == OSAL_ST_MODE_FREERUNNING */ - -#if OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC - /* Periodic systick mode, the Cortex-Mx internal systick timer is used - in this mode.*/ - SysTick->LOAD = (TIVA_SYSCLK / OSAL_ST_FREQUENCY) - 1; - SysTick->VAL = 0; - SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | - SysTick_CTRL_ENABLE_Msk | - SysTick_CTRL_TICKINT_Msk; - - /* IRQ enabled.*/ - nvicSetSystemHandlerPriority(HANDLER_SYSTICK, TIVA_ST_IRQ_PRIORITY); -#endif /* OSAL_ST_MODE == OSAL_ST_MODE_PERIODIC */ -} - -#endif /* OSAL_ST_MODE != OSAL_ST_MODE_NONE */ - -/** - * @} - */ diff --git a/os/hal/ports/TIVA/LLD/hal_st_lld.h b/os/hal/ports/TIVA/LLD/hal_st_lld.h deleted file mode 100644 index 35bf008..0000000 --- a/os/hal/ports/TIVA/LLD/hal_st_lld.h +++ /dev/null @@ -1,276 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file Tiva/LLD/st_lld.h - * @brief ST Driver subsystem low level driver header. - * @details This header is designed to be include-able without having to - * include other files from the HAL. - * - * @addtogroup ST - * @{ - */ - -#ifndef HAL_ST_LLD_H -#define HAL_ST_LLD_H - -#include "mcuconf.h" -#include "tiva_registry.h" -#include "tiva_gpt.h" - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ - -/** - * @brief SysTick timer IRQ priority. - */ -#if !defined(TIVA_ST_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_ST_IRQ_PRIORITY 2 -#endif - -/** - * @brief GPTx unit (by number) to be used for free running operations. - * @note You must select a 32 bits timer if a 32 bits @p systick_t type - * is required. - */ -#if !defined(TIVA_ST_TIMER_NUMBER) || defined(__DOXYGEN__) -#define TIVA_ST_TIMER_NUMBER 0 -#endif - -/** - * @brief When set to @p TRUE a wide timer is used. When set to @p FALSE a - * normal timer is used. - */ -#if !defined(TIVA_ST_USE_WIDE_TIMER) || defined(__DOXYGEN__) -#define TIVA_ST_USE_WIDE_TIMER TRUE -#endif - -/** - * @} - */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if (TIVA_ST_USE_WIDE_TIMER == TRUE) - -#if TIVA_ST_TIMER_NUMBER == 0 -#if !TIVA_HAS_WGPT0 -#error "WGPT0 not present" -#endif -#define TIVA_ST_TIM WGPT0 - -#elif TIVA_ST_TIMER_NUMBER == 1 -#if !TIVA_HAS_WGPT1 -#error "WGPT1 not present" -#endif -#define TIVA_ST_TIM WGPT1 - -#elif TIVA_ST_TIMER_NUMBER == 2 -#if !TIVA_HAS_WGPT2 -#error "WGPT2 not present" -#endif -#define TIVA_ST_TIM WGPT2 - -#elif TIVA_ST_TIMER_NUMBER == 3 -#if !TIVA_HAS_WGPT3 -#error "WGPT3 not present" -#endif -#define TIVA_ST_TIM WGPT3 - -#elif TIVA_ST_TIMER_NUMBER == 4 -#if !TIVA_HAS_WGPT4 -#error "WGPT4 not present" -#endif -#define TIVA_ST_TIM WGPT4 - -#elif TIVA_ST_TIMER_NUMBER == 5 -#if !TIVA_HAS_WGPT5 -#error "WGPT5 not present" -#endif -#define TIVA_ST_TIM WGPT5 - -#else -#error "TIVA_ST_USE_TIMER specifies an unsupported timer" -#endif - -#elif (TIVA_ST_USE_WIDE_TIMER == FALSE) - -#if TIVA_ST_TIMER_NUMBER == 0 -#if !TIVA_HAS_GPT0 -#error "GPT0 not present" -#endif -#define TIVA_ST_TIM GPT0 - -#elif TIVA_ST_TIMER_NUMBER == 1 -#if !TIVA_HAS_GPT1 -#error "GPT1 not present" -#endif -#define TIVA_ST_TIM GPT1 - -#elif TIVA_ST_TIMER_NUMBER == 2 -#if !TIVA_HAS_GPT2 -#error "GPT2 not present" -#endif -#define TIVA_ST_TIM GPT2 - -#elif TIVA_ST_TIMER_NUMBER == 3 -#if !TIVA_HAS_GPT3 -#error "GPT3 not present" -#endif -#define TIVA_ST_TIM GPT3 - -#elif TIVA_ST_TIMER_NUMBER == 4 -#if !TIVA_HAS_GPT4 -#error "GPT4 not present" -#endif -#define TIVA_ST_TIM GPT4 - -#elif TIVA_ST_TIMER_NUMBER == 5 -#if !TIVA_HAS_GPT5 -#error "GPT5 not present" -#endif -#define TIVA_ST_TIM GPT5 - -#else -#error "TIVA_ST_TIMER_NUMBER specifies an unsupported timer" -#endif - -#else -#error "wrong value defined for TIVA_ST_USE_WIDE_TIMER" -#endif - -#if OSAL_ST_MODE != OSAL_ST_MODE_NONE && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_ST_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to ST" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#ifdef __cplusplus -extern "C" { -#endif - void st_lld_init(void); -#ifdef __cplusplus -} -#endif - -/*===========================================================================*/ -/* Driver inline functions. */ -/*===========================================================================*/ - -/** - * @brief Returns the time counter value. - * - * @return The counter value. - * - * @notapi - */ -static inline systime_t st_lld_get_counter(void) -{ - return (systime_t) (((systime_t) 0xffffffff) - TIVA_ST_TIM->TAR); -} - -/** - * @brief Starts the alarm. - * @note Makes sure that no spurious alarms are triggered after - * this call. - * - * @param[in] time the time to be set for the first alarm - * - * @notapi - */ -static inline void st_lld_start_alarm(systime_t time) -{ - TIVA_ST_TIM->TAMATCHR = (systime_t) (((systime_t) 0xffffffff) - time); - TIVA_ST_TIM->ICR = TIVA_ST_TIM->MIS; - TIVA_ST_TIM->IMR = GPTM_IMR_TAMIM; -} - -/** - * @brief Stops the alarm interrupt. - * - * @notapi - */ -static inline void st_lld_stop_alarm(void) -{ - TIVA_ST_TIM->IMR = 0; -} - -/** - * @brief Sets the alarm time. - * - * @param[in] time the time to be set for the next alarm - * - * @notapi - */ -static inline void st_lld_set_alarm(systime_t time) -{ - TIVA_ST_TIM->TAMATCHR = (systime_t) (((systime_t) 0xffffffff) - time); -} - -/** - * @brief Returns the current alarm time. - * - * @return The currently set alarm time. - * - * @notapi - */ -static inline systime_t st_lld_get_alarm(void) -{ - return (systime_t) (((systime_t)0xffffffff) - TIVA_ST_TIM->TAMATCHR); -} - -/** - * @brief Determines if the alarm is active. - * - * @return The alarm status. - * @retval false if the alarm is not active. - * @retval true is the alarm is active - * - * @notapi - */ -static inline bool st_lld_is_alarm_active(void) -{ - return (bool) ((TIVA_ST_TIM->IMR & GPTM_IMR_TAMIM) !=0); -} - -#endif /* HAL_ST_LLD_H */ - -/** - * @} - */ diff --git a/os/hal/ports/TIVA/LLD/hal_wdg_lld.c b/os/hal/ports/TIVA/LLD/hal_wdg_lld.c deleted file mode 100644 index 38dcef0..0000000 --- a/os/hal/ports/TIVA/LLD/hal_wdg_lld.c +++ /dev/null @@ -1,244 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - - -/** - * @file TIVA/wdg_lld.c - * @brief WDG Driver subsystem low level driver source. - * - * @addtogroup WDG - * @{ - */ - -#include "hal.h" - -#if HAL_USE_WDG || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -#if TIVA_WDG_USE_WDT0 || defined(__DOXYGEN__) -WDGDriver WDGD1; -#endif /* TIVA_WDG_USE_WDT0 */ - -#if TIVA_WDG_USE_WDT1 || defined(__DOXYGEN__) -WDGDriver WDGD2; -#endif /* TIVA_WDG_USE_WDT1 */ - -/*===========================================================================*/ -/* Driver local variables. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Shared IRQ handler. - * - * @param[in] wdgp pointer to @p WDGDriver object. - */ -static void serve_interrupt(WDGDriver *wdgp) -{ - uint32_t mis; - - mis = wdgp->wdt->MIS; - - if (mis & MIS_WDTMIS) { - /* Invoke callback, if any */ - if (wdgp->config->callback) { - if (wdgp->config->callback(wdgp)) { - /* Clear interrupt */ - wdgp->wdt->ICR = 0; - wdgTivaSyncWrite(wdgp); - } - } - } -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if TIVA_WDG_USE_WDT0 || TIVA_WDG_USE_WDT1 -/** - * @brief WDT0/WDT1 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_WDT_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - -#if TIVA_WDG_USE_WDT0 - serve_interrupt(&WDGD1); -#endif - -#if TIVA_WDG_USE_WDT1 - serve_interrupt(&WDGD2); -#endif - - OSAL_IRQ_EPILOGUE(); -} -#endif /* TIVA_WDG_USE_WDT0 || TIVA_WDG_USE_WDT1 */ - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level WDG driver initialization. - * - * @notapi - */ -void wdg_lld_init(void) -{ -#if TIVA_WDG_USE_WDT0 - WDGD1.state = WDG_STOP; - WDGD1.wdt = WDT0; -#endif /* TIVA_WDG_USE_WDT0 */ - -#if TIVA_WDG_USE_WDT1 - WDGD2.state = WDG_STOP; - WDGD2.wdt = WDT1; -#endif /* TIVA_WDG_USE_WDT1 */ - - /* The shared vector is initialized on driver initialization and never - disabled because it is shared between the Watchdog Timers.*/ - nvicEnableVector(TIVA_WDT_NUMBER, TIVA_WDG_WDT_IRQ_PRIORITY); -} - -/** - * @brief Configures and activates the WDG peripheral. - * - * @param[in] wdgp pointer to the @p WDGDriver object - * - * @notapi - */ -void wdg_lld_start(WDGDriver *wdgp) -{ -#if TIVA_WDG_USE_WDT0 - if (&WDGD1 == wdgp) { - SYSCTL->RCGCWD |= (1 << 0); - - while (!(SYSCTL->PRWD & (1 << 0))) - ; - } -#endif /* TIVA_WDG_USE_WDT0 */ - -#if TIVA_WDG_USE_WDT1 - if (&WDGD2 == wdgp) { - SYSCTL->RCGCWD |= (1 << 1); - - while (!(SYSCTL->PRWD & (1 << 1))) - ; - } -#endif /* TIVA_WDG_USE_WDT1 */ - - wdgp->wdt->LOAD = wdgp->config->load; - wdgTivaSyncWrite(wdgp); - - wdgp->wdt->TEST = wdgp->config->test; - wdgTivaSyncWrite(wdgp); - - wdgp->wdt->CTL |= CTL_RESEN; - wdgTivaSyncWrite(wdgp); - - wdgp->wdt->CTL |= CTL_INTEN; - wdgTivaSyncWrite(wdgp); -} - -/** - * @brief Deactivates the WDG peripheral. - * - * @param[in] wdgp pointer to the @p WDGDriver object - * - * @api - */ -void wdg_lld_stop(WDGDriver *wdgp) -{ -#if TIVA_WDG_USE_WDT0 - if (&WDGD1 == wdgp) { - SYSCTL->SRWD |= (1 << 0); - SYSCTL->SRWD &= ~(1 << 0); - } -#endif /* TIVA_WDG_USE_WDT0 */ - -#if TIVA_WDG_USE_WDT1 - if (&WDGD2 == wdgp) { - SYSCTL->SRWD |= (1 << 1); - SYSCTL->SRWD &= ~(1 << 1); - } -#endif /* TIVA_WDG_USE_WDT1 */ -} - -/** - * @brief Reloads WDG's counter. - * - * @param[in] wdgp pointer to the @p WDGDriver object - * - * @notapi - */ -void wdg_lld_reset(WDGDriver *wdgp) -{ -#if defined(TM4C123_USE_REVISION_6_FIX) || defined(TM4C123_USE_REVISION_7_FIX) - -#if TIVA_WDG_USE_WDT1 - if (&WDGD2 == wdgp) { - /* Number: WDT#02 - * Description: Periodically reloading the count value into the Watchdog - * Timer Load (WDTLOAD) register of the Watchdog Timer 1 - * module will not restart the count, as specified in the data - * sheet. - * Workaround: Disable the Watchdog Timer 1 module by setting the - * appropriate bit in the Watchdog Timer Software Reset (SRWD) - * register before reprogramming the counter.*/ - wdg_lld_stop(wdgp); - wdg_lld_start(wdgp); - return; - } -#endif /* TIVA_WDG_USE_WDT1 */ - -#endif /* defined(TM4C123_USE_REVISION_6_FIX) || - defined(TM4C123_USE_REVISION_7_FIX) */ - wdgp->wdt->LOAD = wdgp->config->load; - wdgTivaSyncWrite(wdgp); -} - -#endif /* HAL_USE_WDG */ - -#if TIVA_WDG_USE_WDT1 -/** - * @brief synchronize after a write to a watchdog register. - * - * @param[in] wdgp pointer to the @p WDGDriver object. - */ -void wdgTivaSyncWrite(WDGDriver *wdgp) -{ - if (&WDGD2 == wdgp) { - while (!(wdgp->wdt->CTL & CTL_WRC)) { - ; - } - } -} -#endif /* TIVA_WDG_USE_WDT1 */ - -/** @} */ diff --git a/os/hal/ports/TIVA/LLD/hal_wdg_lld.h b/os/hal/ports/TIVA/LLD/hal_wdg_lld.h deleted file mode 100644 index f88fa26..0000000 --- a/os/hal/ports/TIVA/LLD/hal_wdg_lld.h +++ /dev/null @@ -1,190 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - - -/** - * @file TIVA/wdg_lld.h - * @brief WDG Driver subsystem low level driver header. - * - * @addtogroup WDG - * @{ - */ - -#ifndef _WDG_LLD_H_ -#define _WDG_LLD_H_ - -#if HAL_USE_WDG || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -#define LOCK_UNLOCK 0x1ACCE551U -#define LOCK_LOCK 0x00000000U - -#define LOCK_IS_UNLOCKED 0U -#define LOCK_IS_LOCKED 1U - -#define TEST_STALL (1 << 8) - -#define MIS_WDTMIS (1 << 0) -#define RIS_WDTRIS (1 << 0) -#define ICR_WDTICR (1 << 0) - -#define CTL_INTEN (1 << 0) -#define CTL_RESEN (1 << 1) -#define CTL_INTTYPE (1 << 2) -#define CTL_WRC (1 << 31) - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief WDT driver enable switch. - * @details If set to @p TRUE the support for WDT is included. - * @note The default is @p FALSE. - */ -#if !defined(TIVA_WDG_USE_WDT) || defined(__DOXYGEN__) -#define TIVA_WDG_USE_WDT FALSE -#endif - -/** - * @brief WDT interrupt priority level setting. - */ -#if !defined(TIVA_WDG_WDT_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_WDG_WDT_IRQ_PRIORITY 5 -#endif - -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if TIVA_WDG_USE_WDT0 && !TIVA_HAS_WDT0 -#error "WDT0 not present in the selected device" -#endif - -#if TIVA_WDG_USE_WDT1 && !TIVA_HAS_WDT1 -#error "WDT1 not present in the selected device" -#endif - -#if !TIVA_WDG_USE_WDT0 && !TIVA_WDG_USE_WDT1 -#error "WDG driver activated but no WDT peripheral assigned" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief Type of a structure representing an WDG driver. - */ -typedef struct WDGDriver WDGDriver; - -/** - * @brief WDG timeout callback type. - * - * @param[in] wdgp pointer to the @p WDGDriver object triggering the callback. - */ -typedef bool (*wdgcallback_t)(WDGDriver *wdgp); - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct -{ - /** - * @brief Interval value used by the WDT. - */ - uint32_t load; - /** - * @brief Timeout callback pointer. - * @note This callback is invoked on the first WDT timeout. If set to - * @p NULL then the callback is disabled. - */ - wdgcallback_t callback; - /** - * @brief Test register configuration value. - */ - uint16_t test; -} WDGConfig; - -/** - * @brief Structure representing an WDG driver. - */ -struct WDGDriver -{ - /** - * @brief Driver state. - */ - wdgstate_t state; - /** - * @brief Current configuration data. - */ - const WDGConfig *config; - /* End of the mandatory fields.*/ - /** - * @brief Pointer to the WDT registers block. - */ - WDT_TypeDef *wdt; -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -#if !TIVA_WDG_USE_WDT1 -#define wdgTivaSyncWrite(wdt) -#endif - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if TIVA_WDG_USE_WDT0 && !defined(__DOXYGEN__) -extern WDGDriver WDGD1; -#endif - -#if TIVA_WDG_USE_WDT1 && !defined(__DOXYGEN__) -extern WDGDriver WDGD2; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void wdg_lld_init(void); - void wdg_lld_start(WDGDriver *wdgp); - void wdg_lld_stop(WDGDriver *wdgp); - void wdg_lld_reset(WDGDriver *wdgp); -#if TIVA_WDG_USE_WDT1 - void wdgTivaSyncWrite(WDGDriver *wdgp); -#endif -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_WDG */ - -#endif /* _WDG_LLD_H_ */ - -/** @} */ diff --git a/os/hal/ports/TIVA/LLD/tiva_gpt.h b/os/hal/ports/TIVA/LLD/tiva_gpt.h deleted file mode 100644 index 114831b..0000000 --- a/os/hal/ports/TIVA/LLD/tiva_gpt.h +++ /dev/null @@ -1,135 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file tiva_gpt.h - * @brief TIVA GPT registers layout header. - * - * @addtogroup TIVA_GPT - * @{ - */ - -#ifndef TIVA_GPT_H_ -#define TIVA_GPT_H_ - -// cfg -#define GPTM_CFG_CFG_MASK (7 << 0) -#define GPTM_CFG_CFG_WHOLE (0 << 0) -#define GPTM_CFG_CFG_RTC (1 << 0) -#define GPTM_CFG_CFG_SPLIT (4 << 0) - -// tamr -#define GPTM_TAMR_TAMR_MASK (3 << 0) -#define GPTM_TAMR_TAMR_ONESHOT (1 << 0) -#define GPTM_TAMR_TAMR_PERIODIC (2 << 0) -#define GPTM_TAMR_TAMR_CAPTURE (3 << 0) - -#define GPTM_TAMR_TACMR (1 << 2) - -#define GPTM_TAMR_TAAMS (1 << 3) - -#define GPTM_TAMR_TACDIR (1 << 4) - -#define GPTM_TAMR_TAMIE (1 << 5) - -#define GPTM_TAMR_TAWOT (1 << 6) - -#define GPTM_TAMR_TASNAPS (1 << 7) - -#define GPTM_TAMR_TAILD (1 << 8) - -#define GPTM_TAMR_TAPWMIE (1 << 9) - -#define GPTM_TAMR_TAMRSU (1 << 10) - -#define GPTM_TAMR_TAPLO (1 << 11) - -// ctl -#define GPTM_CTL_TAEN (1 << 0) - -#define GPTM_CTL_TASTALL (1 << 1) - -#define GPTM_CTL_TAEVENT_MASK (3 << 2) -#define GPTM_CTL_TAEVENT_POS (0 << 2) -#define GPTM_CTL_TAEVENT_NEG (1 << 2) -#define GPTM_CTL_TAEVENT_BOTH (3 << 2) - -#define GPTM_CTL_RTCEN (1 << 4) - -#define GPTM_CTL_TAOTE (1 << 5) - -#define GPTM_CTL_TAPWML (1 << 6) - -#define GPTM_CTL_TBEN (1 << 8) - -#define GPTM_CTL_TBSTALL (1 << 9) - -#define GPTM_CTL_TBEVENT_MASK (3 << 10) -#define GPTM_CTL_TBEVENT_POS (0 << 10) -#define GPTM_CTL_TBEVENT_NEG (1 << 10) -#define GPTM_CTL_TBEVENT_BOTH (3 << 10) - -#define GPTM_CTL_TBOTE (1 << 13) - -#define GPTM_CTL_TBPWML (1 << 14) - -// imr -#define GPTM_IMR_TATOIM (1 << 0) - -#define GPTM_IMR_CAMIM (1 << 1) - -#define GPTM_IMR_CAEIM (1 << 2) - -#define GPTM_IMR_RTCIM (1 << 3) - -#define GPTM_IMR_TAMIM (1 << 4) - -#define GPTM_IMR_TBTOIM (1 << 8) - -#define GPTM_IMR_CBMIM (1 << 9) - -#define GPTM_IMR_CBEIM (1 << 10) - -#define GPTM_IMR_TBMIM (1 << 11) - -#define GPTM_IMR_WUEIM (1 << 16) - -// icr -#define GPTM_ICR_TATOCINT (1 << 0) - -#define GPTM_ICR_CAMCINT (1 << 1) - -#define GPTM_ICR_CAECINT (1 << 2) - -#define GPTM_ICR_RTCCINT (1 << 3) - -#define GPTM_ICR_TAMCINT (1 << 4) - -#define GPTM_ICR_TBTOCINT (1 << 8) - -#define GPTM_ICR_CBMCINT (1 << 9) - -#define GPTM_ICR_CBECINT (1 << 10) - -#define GPTM_ICR_TBMCINT (1 << 11) - -#define GPTM_ICR_WUECINT (1 << 16) - -#endif /* TIVA_GPT_H_ */ - -/* - * @} - */ diff --git a/os/hal/ports/TIVA/LLD/tiva_udma.c b/os/hal/ports/TIVA/LLD/tiva_udma.c deleted file mode 100644 index 9f122b2..0000000 --- a/os/hal/ports/TIVA/LLD/tiva_udma.c +++ /dev/null @@ -1,141 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#include "hal.h" - -/* The following macro is only defined if some driver requiring DMA services - has been enabled.*/ -#if defined(TIVA_UDMA_REQUIRED) || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -udmaControlTable_t udmaControlTable; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -static uint32_t udma_channel_mask; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if !defined(TIVA_UDMA_SW_HANDLER) -#error "TIVA_UDMA_SW_HANDLER not defined" -#endif -/** - * @brief UDMA software interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_UDMA_SW_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - /* TODO Process software transfer interrupts.*/ - - OSAL_IRQ_EPILOGUE(); -} - -#if !defined(TIVA_UDMA_ERR_HANDLER) -#error "TIVA_UDMA_ERR_HANDLER not defined" -#endif -/** - * @brief UDMA error interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_UDMA_ERR_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - /* TODO Do we need to halt the system on a DMA error?*/ - - if (UDMA->ERRCLR) { - UDMA->ERRCLR = 1; - } - - OSAL_IRQ_EPILOGUE(); -} - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Initialize UDMA. - * - * @init - */ -void udmaInit(void) -{ - udma_channel_mask = 0; - - /* Enable UDMA module.*/ - SYSCTL->RCGCDMA = 1; - while (!(SYSCTL->PRDMA & (1 << 0))) - ; - - nvicEnableVector(TIVA_UDMA_ERR_NUMBER, TIVA_UDMA_ERR_IRQ_PRIORITY); - nvicEnableVector(TIVA_UDMA_SW_NUMBER, TIVA_UDMA_SW_IRQ_PRIORITY); - - /* Enable UDMA controller.*/ - UDMA->CFG = 1; - - /* Set address of control table.*/ - UDMA->CTLBASE = (uint32_t)udmaControlTable.primary; -} - -/** - * @brief Allocates a DMA channel. - * - * @special - */ -bool udmaChannelAllocate(uint8_t dmach) -{ - /* Checks if the channel is already taken.*/ - if ((udma_channel_mask & (1 << dmach)) != 0) - return TRUE; - - /* Mark channel as used */ - udma_channel_mask |= (1 << dmach); - - return FALSE; -} - -/** - * @brief Releases a DMA channel. - * - * @special - */ -void udmaChannelRelease(uint8_t dmach) -{ - /* Marks the channel as not used.*/ - udma_channel_mask &= ~(1 << dmach); -} - -#endif diff --git a/os/hal/ports/TIVA/LLD/tiva_udma.h b/os/hal/ports/TIVA/LLD/tiva_udma.h deleted file mode 100644 index 6479b08..0000000 --- a/os/hal/ports/TIVA/LLD/tiva_udma.h +++ /dev/null @@ -1,195 +0,0 @@ -/* - Copyright (C) 2014..2016 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -#ifndef TIVA_UDMA_H_ -#define TIVA_UDMA_H_ - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @name CHCTL register defines. - * @{ - */ -#define UDMA_CHCTL_DSTINC_MASK 0xC0000000 -#define UDMA_CHCTL_DSTINC_0 0xC0000000 -#define UDMA_CHCTL_DSTINC_8 0x00000000 -#define UDMA_CHCTL_DSTINC_16 0x40000000 -#define UDMA_CHCTL_DSTINC_32 0x80000000 -#define UDMA_CHCTL_DSTSIZE_MASK 0x30000000 -#define UDMA_CHCTL_DSTSIZE_8 0x00000000 -#define UDMA_CHCTL_DSTSIZE_16 0x10000000 -#define UDMA_CHCTL_DSTSIZE_32 0x20000000 -#define UDMA_CHCTL_SRCINC_MASK 0x0C000000 -#define UDMA_CHCTL_SRCINC_0 0x0C000000 -#define UDMA_CHCTL_SRCINC_8 0x00000000 -#define UDMA_CHCTL_SRCINC_16 0x04000000 -#define UDMA_CHCTL_SRCINC_32 0x08000000 -#define UDMA_CHCTL_SRCSIZE_MASK 0x03000000 -#define UDMA_CHCTL_SRCSIZE_8 0x00000000 -#define UDMA_CHCTL_SRCSIZE_16 0x01000000 -#define UDMA_CHCTL_SRCSIZE_32 0x02000000 -#define UDMA_CHCTL_ARBSIZE_MASK 0x0003C000 -#define UDMA_CHCTL_ARBSIZE_1 0x00000000 -#define UDMA_CHCTL_ARBSIZE_2 0x00004000 -#define UDMA_CHCTL_ARBSIZE_4 0x00008000 -#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 -#define UDMA_CHCTL_ARBSIZE_16 0x00010000 -#define UDMA_CHCTL_ARBSIZE_32 0x00014000 -#define UDMA_CHCTL_ARBSIZE_64 0x00018000 -#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 -#define UDMA_CHCTL_ARBSIZE_256 0x00020000 -#define UDMA_CHCTL_ARBSIZE_512 0x00024000 -#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 -#define UDMA_CHCTL_XFERSIZE_MASK 0x00003FF0 -#define UDMA_CHCTL_XFERSIZE(n) ((n-1) << 4) -#define UDMA_CHCTL_NXTUSEBURST 0x00000008 -#define UDMA_CHCTL_XFERMODE_MASK 0x00000007 -#define UDMA_CHCTL_XFERMODE_STOP 0x00000000 -#define UDMA_CHCTL_XFERMODE_BASIC 0x00000001 -#define UDMA_CHCTL_XFERMODE_AUTO 0x00000002 -#define UDMA_CHCTL_XFERMODE_PINGPONG 0x00000003 -#define UDMA_CHCTL_XFERMODE_MSG 0x00000004 -#define UDMA_CHCTL_XFERMODE_AMSG 0x00000005 -#define UDMA_CHCTL_XFERMODE_PSG 0x00000006 -#define UDMA_CHCTL_XFERMODE_APSG 0x00000007 -/** @} */ - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @brief UDMA software interrupt priority level setting. - */ -#if !defined(TIVA_UDMA_SW_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_UDMA_SW_IRQ_PRIORITY 5 -#endif - -/** - * @brief UDMA error interrupt priority level setting. - */ -#if !defined(TIVA_UDMA_ERR_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_UDMA_ERR_IRQ_PRIORITY 5 -#endif - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief A structure that defines an entry in the channel control table. - * @note These fields are used by the uDMA controller and normally it is not - * necessary for software to directly read or write fields in the - * table. - */ -typedef struct __attribute__((packed)) -{ - /** - * @brief The ending source address of the data transfer. - */ - volatile void *srcendp; - /** - * @brief The ending destination address of the data transfer. - */ - volatile void *dstendp; - /** - * @brief The channel control mode. - */ - volatile uint32_t chctl; - /** - * @brief An unused location. - */ - volatile uint32_t unused; -} tiva_udma_table_entry_t; - -typedef struct __attribute__((packed, aligned(1024))) -{ - union { - struct { - tiva_udma_table_entry_t primary[32]; - tiva_udma_table_entry_t alternate[32]; - }; - uint8_t raw[1024]; - }; -} udmaControlTable_t ; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -#define dmaChannelEnable(dmach) {\ - UDMA->ENASET = (1 << dmach);\ -} - -#define dmaChannelDisable(dmach) { \ - UDMA->ENACLR = (1 << dmach); \ -} - -#define dmaChannelPrimary(dmach) {\ - UDMA->ALTCLR = (1 << dmach); \ -} - -#define dmaChannelAlternate(dmach) { \ - UDMA->ALTSET = (1 << dmach); \ -} - -#define dmaChannelSingleBurst(dmach) { \ - UDMA->USEBURSTCLR = (1 << dmach); \ -} - -#define dmaChannelBurstOnly(dmach) { \ - UDMA->USEBURSTSET = (1 << dmach); \ -} - -#define dmaChannelPriorityHigh(dmach) { \ - UDMA->PRIOSET = (1 << dmach); \ -} - -#define dmaChannelPriorityDefault(dmach) { \ - UDMA->PRIOCLR = (1 << dmach); \ -} - -#define dmaChannelEnableRequest(dmach) {\ - UDMA->REQMASKCLR = (1 << dmach); \ -} - -#define dmaChannelDisableRequest(dmach) {\ - UDMA->REQMASKSET = (1 << dmach); \ -} - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -extern udmaControlTable_t udmaControlTable; - -#ifdef __cplusplus -extern "C" { -#endif - void udmaInit(void); - bool udmaChannelAllocate(uint8_t dmach); - void udmaChannelRelease(uint8_t dmach); -#ifdef __cplusplus -} -#endif - -#endif /* TIVA_UDMA_H_ */ diff --git a/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c b/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c new file mode 100644 index 0000000..9f122b2 --- /dev/null +++ b/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c @@ -0,0 +1,141 @@ +/* + Copyright (C) 2014..2016 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" + +/* The following macro is only defined if some driver requiring DMA services + has been enabled.*/ +#if defined(TIVA_UDMA_REQUIRED) || defined(__DOXYGEN__) + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +udmaControlTable_t udmaControlTable; + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +static uint32_t udma_channel_mask; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +#if !defined(TIVA_UDMA_SW_HANDLER) +#error "TIVA_UDMA_SW_HANDLER not defined" +#endif +/** + * @brief UDMA software interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_UDMA_SW_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + /* TODO Process software transfer interrupts.*/ + + OSAL_IRQ_EPILOGUE(); +} + +#if !defined(TIVA_UDMA_ERR_HANDLER) +#error "TIVA_UDMA_ERR_HANDLER not defined" +#endif +/** + * @brief UDMA error interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_UDMA_ERR_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + /* TODO Do we need to halt the system on a DMA error?*/ + + if (UDMA->ERRCLR) { + UDMA->ERRCLR = 1; + } + + OSAL_IRQ_EPILOGUE(); +} + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ + +/** + * @brief Initialize UDMA. + * + * @init + */ +void udmaInit(void) +{ + udma_channel_mask = 0; + + /* Enable UDMA module.*/ + SYSCTL->RCGCDMA = 1; + while (!(SYSCTL->PRDMA & (1 << 0))) + ; + + nvicEnableVector(TIVA_UDMA_ERR_NUMBER, TIVA_UDMA_ERR_IRQ_PRIORITY); + nvicEnableVector(TIVA_UDMA_SW_NUMBER, TIVA_UDMA_SW_IRQ_PRIORITY); + + /* Enable UDMA controller.*/ + UDMA->CFG = 1; + + /* Set address of control table.*/ + UDMA->CTLBASE = (uint32_t)udmaControlTable.primary; +} + +/** + * @brief Allocates a DMA channel. + * + * @special + */ +bool udmaChannelAllocate(uint8_t dmach) +{ + /* Checks if the channel is already taken.*/ + if ((udma_channel_mask & (1 << dmach)) != 0) + return TRUE; + + /* Mark channel as used */ + udma_channel_mask |= (1 << dmach); + + return FALSE; +} + +/** + * @brief Releases a DMA channel. + * + * @special + */ +void udmaChannelRelease(uint8_t dmach) +{ + /* Marks the channel as not used.*/ + udma_channel_mask &= ~(1 << dmach); +} + +#endif diff --git a/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.h b/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.h new file mode 100644 index 0000000..6479b08 --- /dev/null +++ b/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.h @@ -0,0 +1,195 @@ +/* + Copyright (C) 2014..2016 Marco Veeneman + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef TIVA_UDMA_H_ +#define TIVA_UDMA_H_ + +/*===========================================================================*/ +/* Driver constants. */ +/*===========================================================================*/ + +/** + * @name CHCTL register defines. + * @{ + */ +#define UDMA_CHCTL_DSTINC_MASK 0xC0000000 +#define UDMA_CHCTL_DSTINC_0 0xC0000000 +#define UDMA_CHCTL_DSTINC_8 0x00000000 +#define UDMA_CHCTL_DSTINC_16 0x40000000 +#define UDMA_CHCTL_DSTINC_32 0x80000000 +#define UDMA_CHCTL_DSTSIZE_MASK 0x30000000 +#define UDMA_CHCTL_DSTSIZE_8 0x00000000 +#define UDMA_CHCTL_DSTSIZE_16 0x10000000 +#define UDMA_CHCTL_DSTSIZE_32 0x20000000 +#define UDMA_CHCTL_SRCINC_MASK 0x0C000000 +#define UDMA_CHCTL_SRCINC_0 0x0C000000 +#define UDMA_CHCTL_SRCINC_8 0x00000000 +#define UDMA_CHCTL_SRCINC_16 0x04000000 +#define UDMA_CHCTL_SRCINC_32 0x08000000 +#define UDMA_CHCTL_SRCSIZE_MASK 0x03000000 +#define UDMA_CHCTL_SRCSIZE_8 0x00000000 +#define UDMA_CHCTL_SRCSIZE_16 0x01000000 +#define UDMA_CHCTL_SRCSIZE_32 0x02000000 +#define UDMA_CHCTL_ARBSIZE_MASK 0x0003C000 +#define UDMA_CHCTL_ARBSIZE_1 0x00000000 +#define UDMA_CHCTL_ARBSIZE_2 0x00004000 +#define UDMA_CHCTL_ARBSIZE_4 0x00008000 +#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 +#define UDMA_CHCTL_ARBSIZE_16 0x00010000 +#define UDMA_CHCTL_ARBSIZE_32 0x00014000 +#define UDMA_CHCTL_ARBSIZE_64 0x00018000 +#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 +#define UDMA_CHCTL_ARBSIZE_256 0x00020000 +#define UDMA_CHCTL_ARBSIZE_512 0x00024000 +#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 +#define UDMA_CHCTL_XFERSIZE_MASK 0x00003FF0 +#define UDMA_CHCTL_XFERSIZE(n) ((n-1) << 4) +#define UDMA_CHCTL_NXTUSEBURST 0x00000008 +#define UDMA_CHCTL_XFERMODE_MASK 0x00000007 +#define UDMA_CHCTL_XFERMODE_STOP 0x00000000 +#define UDMA_CHCTL_XFERMODE_BASIC 0x00000001 +#define UDMA_CHCTL_XFERMODE_AUTO 0x00000002 +#define UDMA_CHCTL_XFERMODE_PINGPONG 0x00000003 +#define UDMA_CHCTL_XFERMODE_MSG 0x00000004 +#define UDMA_CHCTL_XFERMODE_AMSG 0x00000005 +#define UDMA_CHCTL_XFERMODE_PSG 0x00000006 +#define UDMA_CHCTL_XFERMODE_APSG 0x00000007 +/** @} */ + +/*===========================================================================*/ +/* Driver pre-compile time settings. */ +/*===========================================================================*/ + +/** + * @brief UDMA software interrupt priority level setting. + */ +#if !defined(TIVA_UDMA_SW_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_UDMA_SW_IRQ_PRIORITY 5 +#endif + +/** + * @brief UDMA error interrupt priority level setting. + */ +#if !defined(TIVA_UDMA_ERR_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_UDMA_ERR_IRQ_PRIORITY 5 +#endif + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver data structures and types. */ +/*===========================================================================*/ + +/** + * @brief A structure that defines an entry in the channel control table. + * @note These fields are used by the uDMA controller and normally it is not + * necessary for software to directly read or write fields in the + * table. + */ +typedef struct __attribute__((packed)) +{ + /** + * @brief The ending source address of the data transfer. + */ + volatile void *srcendp; + /** + * @brief The ending destination address of the data transfer. + */ + volatile void *dstendp; + /** + * @brief The channel control mode. + */ + volatile uint32_t chctl; + /** + * @brief An unused location. + */ + volatile uint32_t unused; +} tiva_udma_table_entry_t; + +typedef struct __attribute__((packed, aligned(1024))) +{ + union { + struct { + tiva_udma_table_entry_t primary[32]; + tiva_udma_table_entry_t alternate[32]; + }; + uint8_t raw[1024]; + }; +} udmaControlTable_t ; + +/*===========================================================================*/ +/* Driver macros. */ +/*===========================================================================*/ + +#define dmaChannelEnable(dmach) {\ + UDMA->ENASET = (1 << dmach);\ +} + +#define dmaChannelDisable(dmach) { \ + UDMA->ENACLR = (1 << dmach); \ +} + +#define dmaChannelPrimary(dmach) {\ + UDMA->ALTCLR = (1 << dmach); \ +} + +#define dmaChannelAlternate(dmach) { \ + UDMA->ALTSET = (1 << dmach); \ +} + +#define dmaChannelSingleBurst(dmach) { \ + UDMA->USEBURSTCLR = (1 << dmach); \ +} + +#define dmaChannelBurstOnly(dmach) { \ + UDMA->USEBURSTSET = (1 << dmach); \ +} + +#define dmaChannelPriorityHigh(dmach) { \ + UDMA->PRIOSET = (1 << dmach); \ +} + +#define dmaChannelPriorityDefault(dmach) { \ + UDMA->PRIOCLR = (1 << dmach); \ +} + +#define dmaChannelEnableRequest(dmach) {\ + UDMA->REQMASKCLR = (1 << dmach); \ +} + +#define dmaChannelDisableRequest(dmach) {\ + UDMA->REQMASKSET = (1 << dmach); \ +} + +/*===========================================================================*/ +/* External declarations. */ +/*===========================================================================*/ + +extern udmaControlTable_t udmaControlTable; + +#ifdef __cplusplus +extern "C" { +#endif + void udmaInit(void); + bool udmaChannelAllocate(uint8_t dmach); + void udmaChannelRelease(uint8_t dmach); +#ifdef __cplusplus +} +#endif + +#endif /* TIVA_UDMA_H_ */ diff --git a/os/hal/ports/TIVA/TM4C123x/platform.mk b/os/hal/ports/TIVA/TM4C123x/platform.mk index 0abafcc..809172c 100644 --- a/os/hal/ports/TIVA/TM4C123x/platform.mk +++ b/os/hal/ports/TIVA/TM4C123x/platform.mk @@ -1,18 +1,25 @@ # List of all the TM4C123x platform files. PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \ ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C123x/hal_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_st_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_pal_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_serial_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_i2c_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_gpt_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_pwm_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_spi_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/tiva_udma.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_ext_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_wdg_lld.c + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.c # Required include directories PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \ ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C123x \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPIO \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPTM \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/I2C \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/PWM \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/SSI \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/UART \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/uDMA \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/WDT diff --git a/os/hal/ports/TIVA/TM4C129x/platform.mk b/os/hal/ports/TIVA/TM4C129x/platform.mk index b8363f3..dd70cde 100644 --- a/os/hal/ports/TIVA/TM4C129x/platform.mk +++ b/os/hal/ports/TIVA/TM4C129x/platform.mk @@ -1,14 +1,27 @@ # List of all the TM4C129x platform files. PLATFORMSRC = ${CHIBIOS}/os/hal/ports/common/ARMCMx/nvic.c \ ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C129x/hal_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_st_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_pal_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_serial_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_mac_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_ext_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/hal_wdg_lld.c + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPTM/hal_gpt_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/MAC/hal_mac_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/PWM/hal_pwm_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/UART/hal_serial_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/uDMA/tiva_udma.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/WDT/hal_wdg_lld.c # Required include directories PLATFORMINC = ${CHIBIOS}/os/hal/ports/common/ARMCMx \ ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C129x \ - ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPIO \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/GPTM \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/I2C \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/MAC \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/PWM \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/SSI \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/UART \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/uDMA \ + ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/LLD/WDT -- cgit v1.2.3