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* 1-wire. Fixed possible deadlock situation.barthess2016-03-281-13/+10
| | | | | In old code thread could be suspended *after* the callback was called. New code protected with more wide critical section.
* QUEUES flags deleted from chconf.h filesbarthess2016-03-281-1/+1
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* Merge branch 'master' into rngStephane D'Alu2016-02-2112-0/+5264
|\ | | | | | | | | | | | | | | | | Added haltest Conflicts: os/hal/hal.mk os/hal/include/hal_community.h os/hal/src/hal_community.c
| * TIMCAP: Initial commitFabien Poussin2016-02-162-0/+163
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| * EEPROM: Initial commitFabien Poussin2016-02-163-0/+954
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| * USB-Host: Initial commitFabien Poussin2016-02-158-0/+4147
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* | cleanupStephane D'Alu2016-02-091-11/+8
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* | Random Number Generator driverStephane D'Alu2016-02-082-0/+189
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* Merge branch 'master' of github.com:ChibiOS/ChibiOS-Contribbarthess2016-01-245-5/+5
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| * Fixed typobarthess2015-10-141-1/+1
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| * FSMC code cleanupbarthess2015-10-145-5/+5
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* | 1-wire driver improvements.barthess2016-01-241-47/+45
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* Update code from code feedbackMichael Spradling2015-08-161-5/+6
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* Add CRC DriverMichael Spradling2015-08-162-0/+267
| | | | | | | | | | | | | | | | | | | | | | This patch includes a high level and two low level drivers. The high level driver is enabled with flag HAL_USE_CRC The low level drivers include: * Hardware CRC for the STM32 cortex processor lines.(when supported) * Enabled with flag STM32_CRC_USE_CRC1 * DMA is enabled with CRC_USE_DMA * SYNC api will use DMA, but put calling thread to sleep * ASYNC api enabled. * DMA Disabled * SYNC api spin while calculating CRC * ASYNC api disabled * Software CRC (3 modes) * CRCSW_CRC32_TABLE - Enables crc32 with lookup table. * CRCSW_CRC16_TABLE - Enables crc16 with lookup tables. * CRCSW_PROGRAMMBLE - Enables any crc done with computation. * Can calculate any crc configuration. * CRC_USE_DMA obviously not support with software CRC
* NAND. Minor improvementsbarthess2015-05-081-19/+16
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* Fixed copyright notesbarthess2015-05-022-30/+20
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* NAND code changed to use bitmap classbarthess2015-05-021-82/+59
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* EICU. Updated authors.barthess2015-03-131-0/+4
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* EICU. Fixed handlign of 32-bit timers. General code cleanup. PWM mode still ↵barthess2015-03-011-2/+2
| | | | untested.
* EICU. Fixed another portion of typos.barthess2015-03-011-1/+1
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* Added EICU driver in HAL. Added STM32 backend for EICU.barthess2015-02-282-0/+153
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* [1-wire] Cosmetical cleanupsbarthess2014-12-271-30/+29
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* 1-wire. STM32F1xx code testedbarthess2014-12-181-63/+105
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* 1-wire. Added workaround form F1xx MCUsbarthess2014-12-141-6/+17
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* 1-wire. Fixed incorrect debug checkbarthess2014-12-141-1/+1
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* Onewire. Deleted unneded time measurement unigbarthess2014-12-081-12/+1
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* 1-wire. Search ROM feature now optionalbarthess2014-12-061-0/+8
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* 1-wire. Improved commentsbarthess2014-12-061-14/+12
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* Added onewire driverbarthess2014-12-061-0/+848
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* Fixed copyrightsbarthess2014-12-061-2/+1
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* Added hooks for community sourcebarthess2014-11-161-0/+66
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* Added fsmc codebarthess2014-10-181-0/+601