diff options
Diffstat (limited to 'os')
51 files changed, 3481 insertions, 1921 deletions
diff --git a/os/common/ext/CMSIS/KINETIS/k20xx.h b/os/common/ext/CMSIS/KINETIS/k20xx.h index 38855aa..8218b3c 100644 --- a/os/common/ext/CMSIS/KINETIS/k20xx.h +++ b/os/common/ext/CMSIS/KINETIS/k20xx.h @@ -2242,7 +2242,7 @@ typedef struct /******** Bits definition for USBx_CTL register *****************/ #define USBx_CTL_JSTATE ((uint8_t)0x80) /*!< Live USB differential receiver JSTATE signal */ #define USBx_CTL_SE0 ((uint8_t)0x40) /*!< Live USB single ended zero signal */ -#define USBx_CTL_TXSUSPENDTOKENBUS ((uint8_t)0x20) /*!< */ +#define USBx_CTL_TXSUSPENDTOKENBUSY ((uint8_t)0x20) /*!< */ #define USBx_CTL_RESET ((uint8_t)0x10) /*!< Generates an USB reset signal (host mode) */ #define USBx_CTL_HOSTMODEEN ((uint8_t)0x08) /*!< Operate in Host mode */ #define USBx_CTL_RESUME ((uint8_t)0x04) /*!< Executes resume signaling */ diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk index 263338a..835faca 100644 --- a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk +++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c123x.mk @@ -1,12 +1,18 @@ # List of the ChibiOS generic TM4C123x startup and CMSIS files. -STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \ - $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.c +STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c -STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S +STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S -STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \ +STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \ $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/TM4C123x \ - $(CHIBIOS)/os/common/ext/CMSIS/include \ + $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \ $(CHIBIOS_CONTRIB)/os/common/ext/TivaWare STARTUPLD = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld + +# Shared variables +ALLXASMSRC += $(STARTUPASM) +ALLCSRC += $(STARTUPSRC) +ALLINC += $(STARTUPINC) diff --git a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk index 6cf42f7..ac4f76e 100644 --- a/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk +++ b/os/common/startup/ARMCMx/compilers/GCC/mk/startup_tm4c129x.mk @@ -1,12 +1,18 @@ # List of the ChibiOS generic TM4C129x startup and CMSIS files. -STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c \ - $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.c +STARTUPSRC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt1.c -STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S +STARTUPASM = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/crt0_v7m.S \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/vectors.S -STARTUPINC = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \ +STARTUPINC = $(CHIBIOS)/os/common/portability/GCC \ + $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC \ $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/devices/TM4C129x \ - $(CHIBIOS)/os/common/ext/CMSIS/include \ + $(CHIBIOS)/os/common/ext/ARM/CMSIS/Core/Include \ $(CHIBIOS_CONTRIB)/os/common/ext/TivaWare STARTUPLD = $(CHIBIOS_CONTRIB)/os/common/startup/ARMCMx/compilers/GCC/ld + +# Shared variables +ALLXASMSRC += $(STARTUPASM) +ALLCSRC += $(STARTUPSRC) +ALLINC += $(STARTUPINC) diff --git a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c index e6c6080..09b44f7 100644 --- a/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c +++ b/os/hal/boards/NONSTANDARD_STM32F4_BARTHESS2/board.c @@ -14,45 +14,197 @@ limitations under the License. */ -#include "ch.h" #include "hal.h" +#include "stm32_gpio.h" + +/*===========================================================================*/ +/* Driver local definitions. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported variables. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver local variables and types. */ +/*===========================================================================*/ + +/** + * @brief Type of STM32 GPIO port setup. + */ +typedef struct { + uint32_t moder; + uint32_t otyper; + uint32_t ospeedr; + uint32_t pupdr; + uint32_t odr; + uint32_t afrl; + uint32_t afrh; +} gpio_setup_t; + +/** + * @brief Type of STM32 GPIO initialization data. + */ +typedef struct { +#if STM32_HAS_GPIOA || defined(__DOXYGEN__) + gpio_setup_t PAData; +#endif +#if STM32_HAS_GPIOB || defined(__DOXYGEN__) + gpio_setup_t PBData; +#endif +#if STM32_HAS_GPIOC || defined(__DOXYGEN__) + gpio_setup_t PCData; +#endif +#if STM32_HAS_GPIOD || defined(__DOXYGEN__) + gpio_setup_t PDData; +#endif +#if STM32_HAS_GPIOE || defined(__DOXYGEN__) + gpio_setup_t PEData; +#endif +#if STM32_HAS_GPIOF || defined(__DOXYGEN__) + gpio_setup_t PFData; +#endif +#if STM32_HAS_GPIOG || defined(__DOXYGEN__) + gpio_setup_t PGData; +#endif +#if STM32_HAS_GPIOH || defined(__DOXYGEN__) + gpio_setup_t PHData; +#endif +#if STM32_HAS_GPIOI || defined(__DOXYGEN__) + gpio_setup_t PIData; +#endif +#if STM32_HAS_GPIOJ || defined(__DOXYGEN__) + gpio_setup_t PJData; +#endif +#if STM32_HAS_GPIOK || defined(__DOXYGEN__) + gpio_setup_t PKData; +#endif +} gpio_config_t; -#if HAL_USE_PAL || defined(__DOXYGEN__) /** - * @brief PAL setup. - * @details Digital I/O ports static configuration as defined in @p board.h. - * This variable is used by the HAL when initializing the PAL driver. + * @brief STM32 GPIO static initialization data. */ -const PALConfig pal_default_config = -{ +static const gpio_config_t gpio_default_config = { +#if STM32_HAS_GPIOA {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, +#endif +#if STM32_HAS_GPIOB {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, +#endif +#if STM32_HAS_GPIOC {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, +#endif +#if STM32_HAS_GPIOD {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, +#endif +#if STM32_HAS_GPIOE {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, +#endif +#if STM32_HAS_GPIOF {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, +#endif +#if STM32_HAS_GPIOG {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, +#endif +#if STM32_HAS_GPIOH {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, +#endif +#if STM32_HAS_GPIOI {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, - VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH} + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}, +#endif +#if STM32_HAS_GPIOJ + {VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR, + VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH}, +#endif +#if STM32_HAS_GPIOK + {VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR, + VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH} +#endif }; + +/*===========================================================================*/ +/* Driver local functions. */ +/*===========================================================================*/ + +static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) { + + gpiop->OTYPER = config->otyper; + gpiop->OSPEEDR = config->ospeedr; + gpiop->PUPDR = config->pupdr; + gpiop->ODR = config->odr; + gpiop->AFRL = config->afrl; + gpiop->AFRH = config->afrh; + gpiop->MODER = config->moder; +} + +static void stm32_gpio_init(void) { + + /* Enabling GPIO-related clocks, the mask comes from the + registry header file.*/ + rccResetAHB1(STM32_GPIO_EN_MASK); + rccEnableAHB1(STM32_GPIO_EN_MASK, true); + + /* Initializing all the defined GPIO ports.*/ +#if STM32_HAS_GPIOA + gpio_init(GPIOA, &gpio_default_config.PAData); +#endif +#if STM32_HAS_GPIOB + gpio_init(GPIOB, &gpio_default_config.PBData); #endif +#if STM32_HAS_GPIOC + gpio_init(GPIOC, &gpio_default_config.PCData); +#endif +#if STM32_HAS_GPIOD + gpio_init(GPIOD, &gpio_default_config.PDData); +#endif +#if STM32_HAS_GPIOE + gpio_init(GPIOE, &gpio_default_config.PEData); +#endif +#if STM32_HAS_GPIOF + gpio_init(GPIOF, &gpio_default_config.PFData); +#endif +#if STM32_HAS_GPIOG + gpio_init(GPIOG, &gpio_default_config.PGData); +#endif +#if STM32_HAS_GPIOH + gpio_init(GPIOH, &gpio_default_config.PHData); +#endif +#if STM32_HAS_GPIOI + gpio_init(GPIOI, &gpio_default_config.PIData); +#endif +#if STM32_HAS_GPIOJ + gpio_init(GPIOJ, &gpio_default_config.PJData); +#endif +#if STM32_HAS_GPIOK + gpio_init(GPIOK, &gpio_default_config.PKData); +#endif +} + +/*===========================================================================*/ +/* Driver interrupt handlers. */ +/*===========================================================================*/ + +/*===========================================================================*/ +/* Driver exported functions. */ +/*===========================================================================*/ /** * @brief Early initialization code. - * @details This initialization must be performed just after stack setup - * and before any other initialization. + * @details GPIO ports and system clocks are initialized before everything + * else. */ void __early_init(void) { + stm32_gpio_init(); stm32_clock_init(); } @@ -60,21 +212,21 @@ void __early_init(void) { /** * @brief SDC card detection. */ -bool_t sdc_lld_is_card_inserted(SDCDriver *sdcp) { +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { (void)sdcp; /* TODO: Fill the implementation.*/ - return TRUE; + return true; } /** * @brief SDC card write protection detection. */ -bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) { +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { (void)sdcp; /* TODO: Fill the implementation.*/ - return FALSE; + return false; } #endif /* HAL_USE_SDC */ @@ -82,21 +234,21 @@ bool_t sdc_lld_is_write_protected(SDCDriver *sdcp) { /** * @brief MMC_SPI card detection. */ -bool_t mmc_lld_is_card_inserted(MMCDriver *mmcp) { +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { (void)mmcp; /* TODO: Fill the implementation.*/ - return TRUE; + return true; } /** * @brief MMC_SPI card write protection detection. */ -bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) { +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { (void)mmcp; /* TODO: Fill the implementation.*/ - return FALSE; + return false; } #endif @@ -105,4 +257,5 @@ bool_t mmc_lld_is_write_protected(MMCDriver *mmcp) { * @todo Add your board-specific code, if any. */ void boardInit(void) { + } diff --git a/os/hal/boards/ST_STM32F0308_DISCOVERY/board.c b/os/hal/boards/ST_STM32F0308_DISCOVERY/board.c index dc058f6..3412452 100644 --- a/os/hal/boards/ST_STM32F0308_DISCOVERY/board.c +++ b/os/hal/boards/ST_STM32F0308_DISCOVERY/board.c @@ -1,5 +1,5 @@ /*
- ChibiOS - Copyright (C) 2006-2014 Giovanni Di Sirio
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -14,15 +14,76 @@ limitations under the License.
*/
+/*
+ * This file has been automatically generated using ChibiStudio board
+ * generator plugin. Do not edit manually.
+ */
+
#include "hal.h"
+#include "stm32_gpio.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of STM32 GPIO port setup.
+ */
+typedef struct {
+ uint32_t moder;
+ uint32_t otyper;
+ uint32_t ospeedr;
+ uint32_t pupdr;
+ uint32_t odr;
+ uint32_t afrl;
+ uint32_t afrh;
+} gpio_setup_t;
+
+/**
+ * @brief Type of STM32 GPIO initialization data.
+ */
+typedef struct {
+#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
+ gpio_setup_t PAData;
+#endif
+#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
+ gpio_setup_t PBData;
+#endif
+#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
+ gpio_setup_t PCData;
+#endif
+#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
+ gpio_setup_t PDData;
+#endif
+#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
+ gpio_setup_t PEData;
+#endif
+#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
+ gpio_setup_t PFData;
+#endif
+#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
+ gpio_setup_t PGData;
+#endif
+#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
+ gpio_setup_t PHData;
+#endif
+#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
+ gpio_setup_t PIData;
+#endif
+} gpio_config_t;
-#if HAL_USE_PAL || defined(__DOXYGEN__)
/**
- * @brief PAL setup.
- * @details Digital I/O ports static configuration as defined in @p board.h.
- * This variable is used by the HAL when initializing the PAL driver.
+ * @brief STM32 GPIO static initialization data.
*/
-const PALConfig pal_default_config = {
+static const gpio_config_t gpio_default_config = {
#if STM32_HAS_GPIOA
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
@@ -57,21 +118,103 @@ const PALConfig pal_default_config = { #endif
#if STM32_HAS_GPIOI
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
- VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH}
+ VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
#endif
};
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
+
+ gpiop->OTYPER = config->otyper;
+ gpiop->OSPEEDR = config->ospeedr;
+ gpiop->PUPDR = config->pupdr;
+ gpiop->ODR = config->odr;
+ gpiop->AFRL = config->afrl;
+ gpiop->AFRH = config->afrh;
+ gpiop->MODER = config->moder;
+}
+
+static void stm32_gpio_init(void) {
+
+ /* Enabling GPIO-related clocks, the mask comes from the
+ registry header file.*/
+ rccResetAHB(STM32_GPIO_EN_MASK);
+ rccEnableAHB(STM32_GPIO_EN_MASK, true);
+
+ /* Initializing all the defined GPIO ports.*/
+#if STM32_HAS_GPIOA
+ gpio_init(GPIOA, &gpio_default_config.PAData);
+#endif
+#if STM32_HAS_GPIOB
+ gpio_init(GPIOB, &gpio_default_config.PBData);
#endif
+#if STM32_HAS_GPIOC
+ gpio_init(GPIOC, &gpio_default_config.PCData);
+#endif
+#if STM32_HAS_GPIOD
+ gpio_init(GPIOD, &gpio_default_config.PDData);
+#endif
+#if STM32_HAS_GPIOE
+ gpio_init(GPIOE, &gpio_default_config.PEData);
+#endif
+#if STM32_HAS_GPIOF
+ gpio_init(GPIOF, &gpio_default_config.PFData);
+#endif
+#if STM32_HAS_GPIOG
+ gpio_init(GPIOG, &gpio_default_config.PGData);
+#endif
+#if STM32_HAS_GPIOH
+ gpio_init(GPIOH, &gpio_default_config.PHData);
+#endif
+#if STM32_HAS_GPIOI
+ gpio_init(GPIOI, &gpio_default_config.PIData);
+#endif
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
/**
* @brief Early initialization code.
- * @details This initialization must be performed just after stack setup
- * and before any other initialization.
+ * @details GPIO ports and system clocks are initialized before everything
+ * else.
*/
void __early_init(void) {
+ stm32_gpio_init();
stm32_clock_init();
}
+#if HAL_USE_SDC || defined(__DOXYGEN__)
+/**
+ * @brief SDC card detection.
+ */
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* TODO: Fill the implementation.*/
+ return true;
+}
+
+/**
+ * @brief SDC card write protection detection.
+ */
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+
+ (void)sdcp;
+ /* TODO: Fill the implementation.*/
+ return false;
+}
+#endif /* HAL_USE_SDC */
+
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
/**
* @brief MMC_SPI card detection.
@@ -99,4 +242,5 @@ bool mmc_lld_is_write_protected(MMCDriver *mmcp) { * @todo Add your board-specific code, if any.
*/
void boardInit(void) {
+
}
diff --git a/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk b/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk index 8232a30..22b5467 100644 --- a/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk +++ b/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.mk @@ -3,3 +3,7 @@ BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/TI_TM4C123G_LAUNCHPAD/board.c # Required include directories BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/TI_TM4C123G_LAUNCHPAD + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) diff --git a/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk b/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk index 56298eb..e95de0b 100644 --- a/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk +++ b/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.mk @@ -3,3 +3,7 @@ BOARDSRC = ${CHIBIOS_CONTRIB}/os/hal/boards/TI_TM4C1294_LAUNCHPAD/board.c # Required include directories BOARDINC = ${CHIBIOS_CONTRIB}/os/hal/boards/TI_TM4C1294_LAUNCHPAD + +# Shared variables +ALLCSRC += $(BOARDSRC) +ALLINC += $(BOARDINC) diff --git a/os/hal/include/hal_community.h b/os/hal/include/hal_community.h index cdedad6..83b1f02 100644 --- a/os/hal/include/hal_community.h +++ b/os/hal/include/hal_community.h @@ -48,7 +48,7 @@ #endif
#if !defined(HAL_USE_QEI)
-#define HAL_USE_QEI FALSE
+#define HAL_USE_QEI FALSE
#endif
#if !defined(HAL_USE_RNG)
diff --git a/os/hal/include/usbh/dev/uvc.h b/os/hal/include/usbh/dev/uvc.h index 817d465..0477312 100644 --- a/os/hal/include/usbh/dev/uvc.h +++ b/os/hal/include/usbh/dev/uvc.h @@ -430,7 +430,7 @@ extern "C" { static inline msg_t usbhuvcLockAndFetchS(USBHUVCDriver *uvcdp, msg_t *msg, systime_t timeout) { chMtxLockS(&uvcdp->mtx); - msg_t ret = chMBFetchS(&uvcdp->mb, msg, timeout); + msg_t ret = chMBFetchTimeoutS(&uvcdp->mb, msg, timeout); if (ret != MSG_OK) chMtxUnlockS(&uvcdp->mtx); return ret; diff --git a/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c b/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c index c6b3d11..a005c32 100644 --- a/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c +++ b/os/hal/ports/KINETIS/LLD/hal_i2c_lld.c @@ -442,7 +442,7 @@ static inline msg_t _i2c_txrx_timeout(I2CDriver *i2cp, i2caddr_t addr, /* wait until the bus is released */
/* Calculating the time window for the timeout on the busy bus condition.*/
start = osalOsGetSystemTimeX();
- end = start + OSAL_MS2ST(KINETIS_I2C_BUSY_TIMEOUT);
+ end = start + OSAL_TIME_MS2I(KINETIS_I2C_BUSY_TIMEOUT);
while(true) {
osalSysLock();
diff --git a/os/hal/ports/KINETIS/LLD/hal_sdc_lld.c b/os/hal/ports/KINETIS/LLD/hal_sdc_lld.c new file mode 100644 index 0000000..1b19a90 --- /dev/null +++ b/os/hal/ports/KINETIS/LLD/hal_sdc_lld.c @@ -0,0 +1,977 @@ +/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+ Copyright (C) 2017..2018 Wim Lewis
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_sdc_lld.c
+ * @brief Kinetis SDC subsystem low level driver.
+ *
+ * This driver provides a single SDC driver based on the Kinetis
+ * "Secured Digital Host Controller (SDHC)" peripheral.
+ *
+ * In order to use this driver, other peripherals must also be configured:
+ *
+ * The MPU must either be disabled (CESR=0), or it must be configured
+ * to allow the SDHC peripheral DMA access to any data buffers (read
+ * or write).
+ *
+ * The SDHC signals must be routed to the desired pins, and pullups/pulldowns
+ * configured. + *
+ * @addtogroup SDC
+ * @{
+ */
+
+#include "hal.h"
+
+#if (HAL_USE_SDC == TRUE) || defined(__DOXYGEN__)
+
+#include "hal_mmcsd.h"
+
+/*===========================================================================*/
+/* Driver local definitions. */
+/*===========================================================================*/
+
+/* We configure the SDHC block to use the system clock */
+#define KINETIS_SDHC_PERIPHERAL_FREQUENCY KINETIS_SYSCLK_FREQUENCY
+
+#ifndef KINETIS_SDHC_PRIORITY
+#define KINETIS_SDHC_PRIORITY 12 /* TODO? Default IRQ priority for SDHC */
+#endif
+
+/* The DTOC value (data timeout counter) controls how long the SDHC
+ will wait for a data transfer before indicating a timeout to
+ us. The card can tell us how long that should be, but various SDHC
+ documentation suggests that we should always allow around 500 msec
+ even if the card says it will finish sooner. This only comes into
+ play if there's a malfunction or something, so it's not critical to
+ get it exactly right.
+
+ It controls the ratio between the SDCLK frequency and the
+ timeout, so we have a different DTOCV for each bus clock
+ frequency.
+*/
+#define DTOCV_300ms_400kHz 4 /* 4 -> 2^17 -> 328 msec */
+#define DTOCV_700ms_25MHz 11 /* 11 -> 2^24 -> 671 msec */
+#define DTOCV_700ms_50MHz 12 /* 12 -> 2^25 -> 671 msec */
+
+#if 0
+#define TRACE(t, val) chDbgWriteTrace ((void *)t, (void *)(uintptr_t)(val))
+#define TRACEI(t, val) chDbgWriteTraceI((void *)t, (void *)(uintptr_t)(val))
+#else
+#define TRACE(t, val)
+#define TRACEI(t, val)
+#endif
+
+#define DIV_RND_UP(a, b) ( ((a)+(b)-1) / (b) )
+
+/* Error bits from the SD / MMC Card Status response word. */
+/* TODO: These really belong in a HLD, not here. */
+#define MMC_ERR_OUT_OF_RANGE (1U << 31)
+#define MMC_ERR_ADDRESS (1U << 30)
+#define MMC_ERR_BLOCK_LEN (1U << 29)
+#define MMC_ERR_ERASE_SEQ (1U << 28)
+#define MMC_ERR_ERASE_PARAM (1U << 27)
+#define MMC_ERR_WP (1U << 26)
+#define MMC_ERR_CARD_IS_LOCKED (1U << 25)
+#define MMC_ERR_LOCK_UNLOCK_FAILED (1U << 24)
+#define MMC_ERR_COM_CRC_ERROR (1U << 23)
+#define MMC_ERR_ILLEGAL_COMMAND (1U << 22)
+#define MMC_ERR_CARD_ECC_FAILED (1U << 21)
+#define MMC_ERR_CARD_CONTROLLER (1U << 20)
+#define MMC_ERR_ERROR (1U << 19)
+#define MMC_ERR_CSD_OVERWRITE (1U << 16)
+#define MMC_ERR_AKE_SEQ (1U << 3)
+
+/*===========================================================================*/
+/* Driver exported variables. */
+/*===========================================================================*/
+
+/**
+ * @brief SDCD1 driver identifier.
+ */
+#if (PLATFORM_SDC_USE_SDC1 == TRUE) || defined(__DOXYGEN__)
+SDCDriver SDCD1;
+#else
+#error HAL_USE_SDC is true but PLATFORM_SDC_USE_SDC1 is false
+#endif
+
+/*===========================================================================*/
+/* Driver local variables and types. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver local functions. */
+/*===========================================================================*/
+
+static void recover_after_botched_transfer(SDCDriver *);
+static msg_t wait_interrupt(SDCDriver *, uint32_t);
+static bool sdc_lld_transfer(SDCDriver *, uint32_t, uintptr_t, uint32_t, uint32_t);
+
+/**
+ * Compute the SDCLKFS and DVS values for a given SDCLK divisor.
+ *
+ * Note that in the current code, this function is always called with
+ * a constant argument (there are only a handful of valid SDCLK
+ * frequencies), and so GCC computes the results at compile time and
+ * does not actually emit this function into the output at all unless
+ * you're compiling with optimizations turned off.
+ *
+ * However if someone compiles with a KINETIS_SDHC_PERIPHERAL_FREQUENCY
+ * that is not a compile-time constant, this function would get emitted.
+ */
+static uint32_t divisor_settings(unsigned divisor)
+{
+ /* First, handle all the special cases */
+ if (divisor <= 1) {
+ /* Pass through */
+ return SDHC_SYSCTL_SDCLKFS(0) | SDHC_SYSCTL_DVS(0);
+ }
+ if (divisor <= 16 && (divisor & 0x01)) {
+ /* Disable the prescaler, just use the divider. */
+ return SDHC_SYSCTL_SDCLKFS(0) | SDHC_SYSCTL_DVS(divisor - 1);
+ }
+ if (divisor <= 32 && !(divisor & 0x01)) {
+ /* Prescale by 2, but do the rest with the divider */
+ return SDHC_SYSCTL_SDCLKFS(0x01) | SDHC_SYSCTL_DVS((divisor >> 1) - 1);
+ }
+ if (divisor >= 0x1000) {
+ /* It's not possible to divide by more than 2^12. If we're asked to,
+ just do the best we can. */
+ return SDHC_SYSCTL_SDCLKFS(0x80) | SDHC_SYSCTL_DVS(0xF);
+ }
+
+ /* The bit position in SDCLKFS provides a power-of-two prescale
+ factor, and the four bits in DVS allow division by up to 16
+ (division by DVS+1). We want to approximate `divisor` using these
+ terms, but we want to round up --- it's OK to run the card a
+ little bit too slow, but not OK to run it a little bit too
+ fast. */
+
+ unsigned shift = (8 * sizeof(unsigned int) - 4) - __builtin_clz(divisor);
+
+ /* Shift the divisor value right so that it only occupies the four
+ lowest bits. Subtract one because that's how the DVS circuit
+ works. Add one if we shifted any 1-bits off the bottom, so that
+ we always round up. */
+ unsigned dvs = (divisor >> shift) - ((divisor & ((1 << shift)-1))? 0 : 1);
+
+ return SDHC_SYSCTL_SDCLKFS(1 << (shift-1)) | SDHC_SYSCTL_DVS(dvs);
+}
+
+/**
+ * @brief Enable the SDHC clock when stable.
+ *
+ * Waits for the clock divider in the SDHC block to stabilize, then
+ * enables the SD clock.
+ */
+static void enable_clock_when_stable(uint32_t new_sysctl)
+{
+ SDHC->SYSCTL = new_sysctl;
+
+ /* Wait for clock divider to stabilize */
+ while(!(SDHC->PRSSTAT & SDHC_PRSSTAT_SDSTB)) {
+ osalThreadSleepMilliseconds(1);
+ }
+
+ /* Restart the clock */
+ SDHC->SYSCTL = new_sysctl | SDHC_SYSCTL_SDCLKEN;
+}
+
+/**
+ * Translate error bits from a CMD transaction to the HAL's error flag set.
+ */
+static sdcflags_t translate_cmd_error(uint32_t status) {
+ /* Translate the failure into the flags understood by the top half */
+
+ sdcflags_t errors = 0;
+
+ if (status & SDHC_IRQSTAT_CTOE || !(status & SDHC_IRQSTAT_CC)) {
+ errors |= SDC_COMMAND_TIMEOUT;
+ }
+ if (status & SDHC_IRQSTAT_CCE) {
+ errors |= SDC_CMD_CRC_ERROR;
+ }
+
+ /* If CTOE and CCE are both set, this indicates that the Kinetis
+ SDHC peripheral has detected a CMD line conflict in a
+ multi-master scenario. There's no specific code for that, so just
+ pass it through as a combined timeout+CRC failure. */
+
+ /* Translate any other framing and protocol errors into CRC errors. */
+ if (status & ~(SDHC_IRQSTAT_CCE|SDHC_IRQSTAT_CTOE|SDHC_IRQSTAT_CC)) {
+ errors |= SDC_CMD_CRC_ERROR;
+ }
+
+ return errors;
+}
+
+/**
+ * Translate error bits from a card's R1 response word into the HAL's
+ * error flag set.
+ *
+ * This function should probably be in the HLD, not here.
+ */
+static sdcflags_t translate_mmcsd_error(uint32_t cardstatus) {
+ sdcflags_t errors = 0;
+
+ cardstatus &= MMCSD_R1_ERROR_MASK;
+
+ if (cardstatus & MMC_ERR_COM_CRC_ERROR)
+ errors |= SDC_CMD_CRC_ERROR;
+
+ if (cardstatus & MMC_ERR_CARD_ECC_FAILED)
+ errors |= SDC_DATA_CRC_ERROR;
+
+ /* TODO: Extend the HLD error codes at least enough to distinguish
+ between invalid command/parameter errors (card is OK, but
+ retrying w/o change won't help) and other errors */
+ if (cardstatus & ~(MMC_ERR_COM_CRC_ERROR|MMC_ERR_CARD_ECC_FAILED))
+ errors |= SDC_UNHANDLED_ERROR;
+
+ return errors;
+}
+
+/**
+ * @brief Perform one CMD transaction on the SD bus.
+ */
+static bool send_and_wait_cmd(SDCDriver *sdcp, uint32_t cmd) {
+ /* SDCLKEN (CMD clock enabled) should be true;
+ * SDSTB (clock stable) should be true;
+ * CIHB (command inhibit / busy) should be false */
+ osalDbgAssert((SDHC->PRSSTAT & (SDHC_PRSSTAT_SDSTB|SDHC_PRSSTAT_CIHB)) == SDHC_PRSSTAT_SDSTB, "Not in expected state");
+ osalDbgAssert(SDHC->SYSCTL & SDHC_SYSCTL_SDCLKEN, "Clock disabled");
+ osalDbgCheck((cmd & SDHC_XFERTYP_DPSEL) == 0);
+ osalDbgCheck((SDHC->IRQSTAT & (SDHC_IRQSTAT_CIE | SDHC_IRQSTAT_CEBE | SDHC_IRQSTAT_CCE |
+ SDHC_IRQSTAT_CTOE | SDHC_IRQSTAT_CC)) == 0);
+
+ /* This initiates the CMD transaction */
+ TRACE(1, cmd);
+ SDHC->XFERTYP = cmd;
+
+ uint32_t events =
+ SDHC_IRQSTAT_CIE | SDHC_IRQSTAT_CEBE | SDHC_IRQSTAT_CCE |
+ SDHC_IRQSTAT_CTOE | /* SDHC_IRQSTAT_CRM | */ SDHC_IRQSTAT_CC;
+ wait_interrupt(sdcp, SDHC_IRQSTAT_CTOE | SDHC_IRQSTAT_CC);
+ uint32_t status = SDHC->IRQSTAT & events;
+
+ /* These bits are write-1-to-clear (w1c) */
+ SDHC->IRQSTAT = status;
+
+ /* In the normal case, the CC (command complete) bit is set but none
+ of the others are */
+ if (status == SDHC_IRQSTAT_CC)
+ return HAL_SUCCESS;
+
+ /* Translate the failure into the flags understood by the top half */
+ sdcp->errors |= translate_cmd_error(status);
+
+ TRACE(9, SDHC->PRSSTAT);
+
+ /* Issue a reset to the CMD portion of the SDHC peripheral to clear the
+ error bits and enable subsequent commands */
+ SDHC->SYSCTL |= SDHC_SYSCTL_RSTC;
+
+ return HAL_FAILED;
+}
+
+/**
+ * @brief Perform one data transaction on the SD bus.
+ */
+static bool send_and_wait_transfer(SDCDriver *sdcp, uint32_t cmd) {
+
+ osalDbgCheck(cmd & SDHC_XFERTYP_DPSEL);
+ osalDbgCheck(cmd & SDHC_XFERTYP_DMAEN);
+
+ const uint32_t cmd_end_bits =
+ SDHC_IRQSTAT_CIE | SDHC_IRQSTAT_CEBE | SDHC_IRQSTAT_CCE |
+ SDHC_IRQSTAT_CTOE | /* SDHC_IRQSTAT_CRM | */ SDHC_IRQSTAT_CC;
+
+ const uint32_t transfer_end_bits =
+ SDHC_IRQSTAT_DMAE | SDHC_IRQSTAT_AC12E | SDHC_IRQSTAT_DEBE |
+ SDHC_IRQSTAT_DCE | SDHC_IRQSTAT_DTOE | SDHC_IRQSTAT_TC;
+
+ TRACE(3, cmd);
+
+ osalSysLock();
+ osalDbgCheck(sdcp->thread == NULL);
+
+ /* Clear anything pending from an earlier transfer */
+ SDHC->IRQSTAT = cmd_end_bits | transfer_end_bits | SDHC_IRQSTAT_DINT;
+
+ /* Enable interrupts on completions or failures */
+ uint32_t old_staten = SDHC->IRQSTATEN;
+ SDHC->IRQSTATEN = (old_staten & ~(SDHC_IRQSTAT_BRR|SDHC_IRQSTAT_BWR)) | (cmd_end_bits | transfer_end_bits | SDHC_IRQSTAT_DINT);
+ SDHC->IRQSIGEN = SDHC_IRQSTAT_CTOE | SDHC_IRQSTAT_CC;
+
+ /* Start the transfer */
+ SDHC->XFERTYP = cmd;
+
+ /* Await an interrupt */
+ osalThreadSuspendS(&sdcp->thread);
+ osalSysUnlock();
+
+ /* Retrieve the flags and clear them */
+ uint32_t cmdstat = SDHC->IRQSTAT & cmd_end_bits;
+ SDHC->IRQSTAT = cmdstat;
+ TRACE(2, cmdstat);
+
+ /* If the command failed, the transfer won't happen */
+ if (cmdstat != SDHC_IRQSTAT_CC) {
+ /* The command couldn't be sent, or wasn't acknowledged */
+ sdcp->errors |= translate_cmd_error(cmdstat);
+
+ /* Clear the error status */
+ SDHC->SYSCTL |= SDHC_SYSCTL_RSTC;
+
+ if (cmdstat == (SDHC_IRQSTAT_CCE|SDHC_IRQSTAT_CTOE)) {
+ /* A CMD-line conflict is unlikely, but doesn't require further recovery */
+ } else {
+ /* For most error situations, we don't know whether the command
+ failed to send or we got line noise while receiving. Make sure
+ we're in a sane state by resetting the connection. */
+ recover_after_botched_transfer(sdcp);
+ }
+
+ return HAL_FAILED;
+ }
+
+ uint32_t cmdresp = SDHC->CMDRSP[0];
+ TRACE(11, cmdresp);
+ if (cmdresp & MMCSD_R1_ERROR_MASK) {
+ /* The command was sent, and the card responded with an error indication */
+ sdcp->errors |= translate_mmcsd_error(cmdresp);
+ return HAL_FAILED;
+ }
+
+ /* Check for end of data transfer phase */
+ uint32_t datastat;
+ for (;;) {
+ datastat = SDHC->IRQSTAT & (transfer_end_bits | SDHC_IRQSTAT_DINT);
+ if (datastat & transfer_end_bits)
+ break;
+ wait_interrupt(sdcp, transfer_end_bits);
+ }
+ TRACE(6, datastat);
+ SDHC->IRQSTAT = datastat;
+
+ /* Handle data transfer errors */
+ if ((datastat & ~(SDHC_IRQSTAT_DINT)) != SDHC_IRQSTAT_TC) {
+ bool should_cancel = false;
+
+ /* Data phase errors */
+ if (datastat & (SDHC_IRQSTAT_DCE|SDHC_IRQSTAT_DEBE)) {
+ sdcp->errors |= SDC_DATA_CRC_ERROR;
+ should_cancel = true;
+ }
+ if (datastat & SDHC_IRQSTAT_DTOE) {
+ sdcp->errors |= SDC_DATA_TIMEOUT;
+ should_cancel = true;
+ }
+
+ /* Internal DMA error */
+ if (datastat & SDHC_IRQSTAT_DMAE) {
+ sdcp->errors |= SDC_UNHANDLED_ERROR;
+ if (!(datastat & SDHC_IRQSTAT_TC))
+ should_cancel = true;
+ }
+
+ if (datastat & SDHC_IRQSTAT_AC12E) {
+ uint32_t cmd12error = SDHC->AC12ERR;
+
+ /* We don't know if CMD12 was successfully executed */
+ should_cancel = true;
+
+ if (cmd12error & SDHC_AC12ERR_AC12NE) {
+ sdcp->errors |= SDC_UNHANDLED_ERROR;
+ } else {
+ if (cmd12error & SDHC_AC12ERR_AC12TOE)
+ sdcp->errors |= SDC_COMMAND_TIMEOUT;
+ if (cmd12error & (SDHC_AC12ERR_AC12CE|SDHC_AC12ERR_AC12EBE))
+ sdcp->errors |= SDC_CMD_CRC_ERROR;
+ }
+ }
+
+ if (should_cancel) {
+ recover_after_botched_transfer(sdcp);
+ }
+
+ return HAL_FAILED;
+ }
+
+ /* For a read transfer, make sure the DMA has finished transferring
+ * to host memory. (For a write transfer, the DMA necessarily finishes
+ * before the transfer does, so we don't need to wait for it
+ * specially.) */
+ if (!(datastat & SDHC_IRQSTAT_DINT)) {
+ for(;;) {
+ datastat = SDHC->IRQSTAT & (SDHC_IRQSTAT_DINT|SDHC_IRQSTAT_DMAE);
+ if (datastat) {
+ SDHC->IRQSTAT = datastat;
+ TRACE(7, datastat);
+ break;
+ }
+ /* ...?? */
+ }
+ }
+
+ SDHC->IRQSTATEN = old_staten;
+
+ return HAL_SUCCESS;
+}
+
+/**
+ * @brief Wait for an interrupt from the SDHC peripheral.
+ *
+ * @param[in] mask Bits to enable in IRQSIGEN.
+ *
+ * @return MSG_OK
+ */
+static msg_t wait_interrupt(SDCDriver *sdcp, uint32_t mask) {
+ osalSysLock();
+ SDHC->IRQSIGEN = mask;
+ msg_t wakeup = osalThreadSuspendS(&sdcp->thread);
+ osalSysUnlock();
+ return wakeup;
+}
+
+static void recover_after_botched_transfer(SDCDriver *sdcp) {
+
+ /* Query the card state */
+ uint32_t cardstatus;
+ if (sdc_lld_send_cmd_short_crc(sdcp,
+ MMCSD_CMD_SEND_STATUS,
+ sdcp->rca, &cardstatus) == HAL_SUCCESS) {
+ sdcp->errors |= translate_mmcsd_error(cardstatus);
+ uint32_t state = MMCSD_R1_STS(cardstatus);
+ if (state == MMCSD_STS_DATA) {
+
+ /* Send a CMD12 to make sure the card isn't still transferring anything */
+ SDHC->CMDARG = 0;
+ send_and_wait_cmd(sdcp,
+ SDHC_XFERTYP_CMDINX(MMCSD_CMD_STOP_TRANSMISSION) |
+ SDHC_XFERTYP_CMDTYP_ABORT |
+ /* TODO: Should we set CICEN and CCCEN here? */
+ SDHC_XFERTYP_CICEN | SDHC_XFERTYP_CCCEN |
+ SDHC_XFERTYP_RSPTYP_48b);
+ }
+ }
+
+ /* And reset the data block of the SDHC peripheral */
+ SDHC->SYSCTL |= SDHC_SYSCTL_RSTD;
+}
+
+/**
+ * @brief Perform one data transfer command
+ *
+ * Sends a command to the card and waits for the corresponding data transfer
+ * (either a read or write) to complete.
+ */
+static bool sdc_lld_transfer(SDCDriver *sdcp, uint32_t startblk,
+ uintptr_t buf, uint32_t n,
+ uint32_t cmdx) {
+
+ osalDbgCheck(n > 0);
+ osalDbgCheck((buf & 0x03) == 0); /* Must be 32-bit aligned */
+
+ osalDbgAssert((SDHC->PRSSTAT & (SDHC_PRSSTAT_DLA|SDHC_PRSSTAT_CDIHB|SDHC_PRSSTAT_CIHB)) == 0,
+ "SDHC interface not ready");
+
+ /* We always operate in terms of 512-byte blocks; the upper-layer
+ driver doesn't change the block size. The SDHC spec suggests that
+ only low-capacity cards support block sizes other than 512 bytes
+ anyway (SDHC "Physical Layer Simplified Specification" ver 6.0) */
+
+ if (sdcp->cardmode & SDC_MODE_HIGH_CAPACITY) {
+ SDHC->CMDARG = startblk;
+ } else {
+ SDHC->CMDARG = startblk * MMCSD_BLOCK_SIZE;
+ }
+
+ /* Store the DMA start address */
+ SDHC->DSADDR = buf;
+
+ uint32_t xfer;
+ /* For data transfers, we need to set some extra bits in XFERTYP according to the
+ transfer we're starting:
+ DPSEL -> enable data transfer
+ DTDSEL -> 1 for a read (card-to-host) transfer
+ MSBSEL, BCEN -> multiple block transfer using BLKATTR_BLKCNT
+ AC12EN -> Automatically issue MMCSD_CMD_STOP_TRANSMISSION at end of transfer
+
+ Setting BLKCOUNT to 1 seems to be necessary even if MSBSEL+BCEN
+ is not set, despite the datasheet suggesting otherwise. I'm not
+ sure if this is a silicon bug or if I'm misunderstanding the
+ datasheet.
+ */
+ SDHC->BLKATTR =
+ SDHC_BLKATTR_BLKCNT(n) |
+ SDHC_BLKATTR_BLKSIZE(MMCSD_BLOCK_SIZE);
+ if (n == 1) {
+ xfer =
+ cmdx |
+ SDHC_XFERTYP_CMDTYP_NORMAL |
+ SDHC_XFERTYP_CICEN | SDHC_XFERTYP_CCCEN |
+ SDHC_XFERTYP_RSPTYP_48b |
+ SDHC_XFERTYP_DPSEL | SDHC_XFERTYP_DMAEN;
+ } else {
+ xfer =
+ cmdx |
+ SDHC_XFERTYP_CMDTYP_NORMAL |
+ SDHC_XFERTYP_CICEN | SDHC_XFERTYP_CCCEN |
+ SDHC_XFERTYP_RSPTYP_48b |
+ SDHC_XFERTYP_MSBSEL | SDHC_XFERTYP_BCEN | SDHC_XFERTYP_AC12EN |
+ SDHC_XFERTYP_DPSEL | SDHC_XFERTYP_DMAEN;
+ }
+
+ return send_and_wait_transfer(sdcp, xfer);
+}
+
+/*===========================================================================*/
+/* Driver interrupt handlers. */
+/*===========================================================================*/
+
+#if (PLATFORM_SDC_USE_SDC1 == TRUE) || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SDHC_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ osalSysLockFromISR();
+
+ TRACEI(4, SDHC->IRQSTAT);
+
+ /* We disable the interrupts, and wake up the usermode task to read
+ * the flags from IRQSTAT.
+ */
+ SDHC->IRQSIGEN = 0;
+
+ osalThreadResumeI(&SDCD1.thread, MSG_OK);
+
+ osalSysUnlockFromISR();
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+/*===========================================================================*/
+/* Driver exported functions. */
+/*===========================================================================*/
+
+/**
+ * @brief Low level SDC driver initialization.
+ *
+ * @notapi
+ */
+void sdc_lld_init(void) {
+#if PLATFORM_SDC_USE_SDC1 == TRUE
+ sdcObjectInit(&SDCD1);
+#endif
+}
+
+
+/**
+ * @brief Configures and activates the SDC peripheral.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ *
+ * @notapi
+ */
+void sdc_lld_start(SDCDriver *sdcp) {
+
+ if (sdcp->state == BLK_STOP) {
+ SIM->SOPT2 =
+ (SIM->SOPT2 & ~SIM_SOPT2_SDHCSRC_MASK) |
+ SIM_SOPT2_SDHCSRC(0); /* SDHC clock source 0: Core/system clock. */
+ SIM->SCGC3 |= SIM_SCGC3_SDHC; /* Enable clock to SDHC peripheral */
+
+ /* Reset the SDHC block */
+ SDHC->SYSCTL |= SDHC_SYSCTL_RSTA;
+ while(SDHC->SYSCTL & SDHC_SYSCTL_RSTA) {
+ osalThreadSleepMilliseconds(1);
+ }
+
+ SDHC->IRQSIGEN = 0;
+ nvicEnableVector(SDHC_IRQn, KINETIS_SDHC_PRIORITY);
+ }
+}
+
+/**
+ * @brief Deactivates the SDC peripheral.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ *
+ * @notapi
+ */
+void sdc_lld_stop(SDCDriver *sdcp) {
+
+ if (sdcp->state != BLK_STOP) {
+ /* TODO: Should we perform a reset (RSTA) before putting the
+ peripheral to sleep? */
+
+ /* Disable the card clock */
+ SDHC->SYSCTL &= ~( SDHC_SYSCTL_SDCLKEN );
+
+ /* Turn off interrupts */
+ nvicDisableVector(SDHC_IRQn);
+ SDHC->IRQSIGEN = 0;
+ SDHC->IRQSTATEN &= ~( SDHC_IRQSTATEN_CINTSEN |
+ SDHC_IRQSTATEN_CINSEN |
+ SDHC_IRQSTATEN_CRMSEN );
+
+ /* Disable the clock to the SDHC peripheral block */
+ SIM->SCGC3 &= ~( SIM_SCGC3_SDHC );
+ }
+}
+
+/**
+ * @brief Starts the SDIO clock and sets it to init mode (400kHz or less).
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ *
+ * @notapi
+ */
+void sdc_lld_start_clk(SDCDriver *sdcp) {
+
+ (void)sdcp;
+
+ /* Stop the card clock (it should already be stopped) */
+ SDHC->SYSCTL &= ~( SDHC_SYSCTL_SDCLKEN );
+
+ /* Change the divisor and DTOCV for a 400kHz card closk */
+ uint32_t sysctl =
+ SDHC_SYSCTL_DTOCV(DTOCV_300ms_400kHz) |
+ divisor_settings(DIV_RND_UP(KINETIS_SDHC_PERIPHERAL_FREQUENCY, 400000));
+
+ /* Restart the clock */
+ enable_clock_when_stable(sysctl);
+
+ /* Reset any protocol machinery; this also runs the clock for 80
+ cycles without any data bits to help initalize the card's state
+ (the Kinetis peripheral docs say that this is required after card
+ insertion or power-on, but the abridged SDHC specifications I
+ have don't seem to mention it) */
+ SDHC->SYSCTL |= SDHC_SYSCTL_INITA;
+
+ TRACE(9, SDHC->PRSSTAT);
+}
+
+/**
+ * @brief Sets the SDIO clock to data mode (25MHz or less).
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] clk the clock mode
+ *
+ * @notapi
+ */
+void sdc_lld_set_data_clk(SDCDriver *sdcp, sdcbusclk_t clk) {
+
+ (void)sdcp;
+
+ /* Stop the card clock */
+ SDHC->SYSCTL &= ~( SDHC_SYSCTL_SDCLKEN );
+
+ /* Change the divisor */
+ uint32_t ctl;
+ switch (clk) {
+ default:
+ case SDC_CLK_25MHz:
+ ctl =
+ SDHC_SYSCTL_DTOCV(DTOCV_700ms_25MHz) |
+ divisor_settings(DIV_RND_UP(KINETIS_SDHC_PERIPHERAL_FREQUENCY, 25000000));
+ break;
+ case SDC_CLK_50MHz:
+ ctl =
+ SDHC_SYSCTL_DTOCV(DTOCV_700ms_50MHz) |
+ divisor_settings(DIV_RND_UP(KINETIS_SDHC_PERIPHERAL_FREQUENCY, 50000000));
+ break;
+ }
+
+ /* Restart the clock */
+ enable_clock_when_stable(ctl);
+}
+
+/**
+ * @brief Stops the SDIO clock.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ *
+ * @notapi
+ */
+void sdc_lld_stop_clk(SDCDriver *sdcp) {
+ (void)sdcp;
+ SDHC->SYSCTL &= ~( SDHC_SYSCTL_SDCLKEN );
+}
+
+/**
+ * @brief Switches the bus to 4 bit or 8 bit mode.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] mode bus mode
+ *
+ * @notapi
+ */
+void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode) {
+ (void)sdcp;
+ uint32_t proctl = SDHC->PROCTL & ~( SDHC_PROCTL_DTW_MASK );
+
+ switch (mode) {
+ case SDC_MODE_1BIT:
+ proctl |= SDHC_PROCTL_DTW_1BIT;
+ break;
+ case SDC_MODE_4BIT:
+ proctl |= SDHC_PROCTL_DTW_4BIT;
+ break;
+ case SDC_MODE_8BIT:
+ proctl |= SDHC_PROCTL_DTW_8BIT;
+ break;
+ default:
+ osalDbgAssert(false, "invalid bus mode");
+ break;
+ }
+
+ SDHC->PROCTL = proctl;
+}
+
+/**
+ * @brief Sends an SDIO command with no response expected.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] cmd card command
+ * @param[in] arg command argument
+ *
+ * @notapi
+ */
+void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg) {
+ SDHC->CMDARG = arg;
+ uint32_t xfer =
+ SDHC_XFERTYP_CMDINX(cmd) |
+ SDHC_XFERTYP_CMDTYP_NORMAL |
+ /* DPSEL=0, CICEN=0, CCCEN=0 */
+ SDHC_XFERTYP_RSPTYP_NONE;
+
+ send_and_wait_cmd(sdcp, xfer);
+}
+
+/**
+ * @brief Sends an SDIO command with a short response expected.
+ * @note The CRC is not verified.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] cmd card command
+ * @param[in] arg command argument
+ * @param[out] resp pointer to the response buffer (one word)
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+bool sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+ uint32_t *resp) {
+ SDHC->CMDARG = arg;
+ uint32_t xfer =
+ SDHC_XFERTYP_CMDINX(cmd) |
+ SDHC_XFERTYP_CMDTYP_NORMAL |
+ /* DPSEL=0, CICEN=0, CCCEN=0 */
+ SDHC_XFERTYP_RSPTYP_48;
+
+ bool waited = send_and_wait_cmd(sdcp, xfer);
+
+ *resp = SDHC->CMDRSP[0];
+
+ return waited;
+}
+
+/**
+ * @brief Sends an SDIO command with a short response expected and CRC.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] cmd card command
+ * @param[in] arg command argument
+ * @param[out] resp pointer to the response buffer (one word)
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+bool sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+ uint32_t *resp) {
+ SDHC->CMDARG = arg;
+ uint32_t xfer =
+ SDHC_XFERTYP_CMDINX(cmd) |
+ SDHC_XFERTYP_CMDTYP_NORMAL |
+ /* DPSEL=0, CICEN=1, CCCEN=1 */
+ SDHC_XFERTYP_CICEN | SDHC_XFERTYP_CCCEN |
+ SDHC_XFERTYP_RSPTYP_48;
+
+ bool waited = send_and_wait_cmd(sdcp, xfer);
+
+ *resp = SDHC->CMDRSP[0];
+ TRACE(11, *resp);
+
+ return waited;
+}
+
+/**
+ * @brief Sends an SDIO command with a long response expected and CRC.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] cmd card command
+ * @param[in] arg command argument
+ * @param[out] resp pointer to the response buffer (four words)
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+bool sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+ uint32_t *resp) {
+
+ /* In response format R2 (the 136-bit or "long" response) the CRC7
+ field is valid, but the command index field is set to all 1s, so
+ we need to disable the command index check function (CICEN=0). */
+
+ SDHC->CMDARG = arg;
+ uint32_t xfer =
+ SDHC_XFERTYP_CMDINX(cmd) |
+ SDHC_XFERTYP_CMDTYP_NORMAL |
+ /* DPSEL=0, CICEN=0, CCCEN=1 */
+ SDHC_XFERTYP_CCCEN |
+ SDHC_XFERTYP_RSPTYP_136;
+
+ bool waited = send_and_wait_cmd(sdcp, xfer);
+
+ resp[0] = SDHC->CMDRSP[0];
+ resp[1] = SDHC->CMDRSP[1];
+ resp[2] = SDHC->CMDRSP[2];
+ resp[3] = SDHC->CMDRSP[3];
+
+ return waited;
+}
+
+/**
+ * @brief Reads one or more blocks.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] startblk first block to read
+ * @param[out] buf pointer to the read buffer
+ * @param[in] n number of blocks to read
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+
+bool sdc_lld_read(SDCDriver *sdcp, uint32_t startblk,
+ uint8_t *buf, uint32_t n) {
+ uint32_t cmdx = (n == 1)?
+ SDHC_XFERTYP_CMDINX(MMCSD_CMD_READ_SINGLE_BLOCK) :
+ SDHC_XFERTYP_CMDINX(MMCSD_CMD_READ_MULTIPLE_BLOCK);
+ cmdx |= SDHC_XFERTYP_DTDSEL;
+
+ return sdc_lld_transfer(sdcp, startblk, (uintptr_t)buf, n, cmdx);
+}
+
+/**
+ * @brief Writes one or more blocks.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ * @param[in] startblk first block to write
+ * @param[out] buf pointer to the write buffer
+ * @param[in] n number of blocks to write
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS operation succeeded.
+ * @retval HAL_FAILED operation failed.
+ *
+ * @notapi
+ */
+bool sdc_lld_write(SDCDriver *sdcp, uint32_t startblk,
+ const uint8_t *buf, uint32_t n) {
+ uint32_t cmdx = (n == 1)?
+ SDHC_XFERTYP_CMDINX(MMCSD_CMD_WRITE_BLOCK) :
+ SDHC_XFERTYP_CMDINX(MMCSD_CMD_WRITE_MULTIPLE_BLOCK);
+
+ return sdc_lld_transfer(sdcp, startblk, (uintptr_t)buf, n, cmdx);
+}
+
+/**
+ * @brief Waits for card idle condition.
+ *
+ * @param[in] sdcp pointer to the @p SDCDriver object
+ *
+ * @return The operation status.
+ * @retval HAL_SUCCESS the operation succeeded.
+ * @retval HAL_FAILED the operation failed.
+ *
+ * @api
+ */
+bool sdc_lld_sync(SDCDriver *sdcp) {
+
+ (void)sdcp;
+
+ return HAL_SUCCESS;
+}
+
+bool sdc_lld_read_special(SDCDriver *sdcp, uint8_t *buf, size_t bytes,
+ uint8_t cmd, uint32_t argument) {
+ uintptr_t bufaddr = (uintptr_t)buf;
+
+ osalDbgCheck((bufaddr & 0x03) == 0); /* Must be 32-bit aligned */
+ osalDbgCheck(bytes > 0);
+ osalDbgCheck(bytes < 4096);
+
+ osalDbgAssert((SDHC->PRSSTAT & (SDHC_PRSSTAT_DLA|SDHC_PRSSTAT_CDIHB|SDHC_PRSSTAT_CIHB)) == 0,
+ "SDHC interface not ready");
+
+ TRACE(5, argument);
+
+ /* Store the cmd argument and DMA start address */
+ SDHC->CMDARG = argument;
+ SDHC->DSADDR = bufaddr;
+
+ /* We're reading one block, of a (possibly) nonstandard size */
+ SDHC->BLKATTR = SDHC_BLKATTR_BLKSIZE(bytes);
+
+ uint32_t xfer =
+ SDHC_XFERTYP_CMDINX(cmd) | /* the command */
+ SDHC_XFERTYP_DTDSEL | /* read transfer (card -> host) */
+ SDHC_XFERTYP_CMDTYP_NORMAL |
+ SDHC_XFERTYP_CICEN | SDHC_XFERTYP_CCCEN |
+ SDHC_XFERTYP_RSPTYP_48 |
+ SDHC_XFERTYP_DPSEL | SDHC_XFERTYP_DMAEN; /* DMA-assisted data transfer */
+
+ return send_and_wait_transfer(sdcp, xfer);
+}
+
+bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
+ (void)sdcp;
+
+ return ( SDHC->PRSSTAT & SDHC_PRSSTAT_CLSL )? true : false;
+}
+
+bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
+ (void)sdcp;
+ return false;
+}
+
+#endif /* HAL_USE_SDC == TRUE */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/LLD/hal_sdc_lld.h b/os/hal/ports/KINETIS/LLD/hal_sdc_lld.h new file mode 100644 index 0000000..9f77bf6 --- /dev/null +++ b/os/hal/ports/KINETIS/LLD/hal_sdc_lld.h @@ -0,0 +1,202 @@ +/*
+ ChibiOS - Copyright (C) 2006..2016 Giovanni Di Sirio
+ Copyright (C) 2017 Wim Lewis
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+/**
+ * @file hal_sdc_lld.h
+ * @brief PLATFORM SDC subsystem low level driver header.
+ *
+ * @addtogroup SDC
+ * @{
+ */
+
+#ifndef HAL_SDC_LLD_H
+#define HAL_SDC_LLD_H
+
+#if (HAL_USE_SDC == TRUE) || defined(__DOXYGEN__)
+
+/*===========================================================================*/
+/* Driver constants. */
+/*===========================================================================*/
+
+#define SDHC_XFERTYP_CMDTYP_NORMAL SDHC_XFERTYP_CMDTYP(0)
+#define SDHC_XFERTYP_CMDTYP_SUSPEND SDHC_XFERTYP_CMDTYP(1)
+#define SDHC_XFERTYP_CMDTYP_RESUME SDHC_XFERTYP_CMDTYP(2)
+#define SDHC_XFERTYP_CMDTYP_ABORT SDHC_XFERTYP_CMDTYP(3)
+
+#define SDHC_XFERTYP_RSPTYP_NONE SDHC_XFERTYP_RSPTYP(0) /* no response */
+#define SDHC_XFERTYP_RSPTYP_136 SDHC_XFERTYP_RSPTYP(1) /* 136-bit response */
+#define SDHC_XFERTYP_RSPTYP_48 SDHC_XFERTYP_RSPTYP(2) /* 48-bit response */
+#define SDHC_XFERTYP_RSPTYP_48b SDHC_XFERTYP_RSPTYP(3) /* 48-bit plus busy */
+
+#define SDHC_PROCTL_DTW_1BIT SDHC_PROCTL_DTW(0)
+#define SDHC_PROCTL_DTW_4BIT SDHC_PROCTL_DTW(1)
+#define SDHC_PROCTL_DTW_8BIT SDHC_PROCTL_DTW(2)
+
+/*===========================================================================*/
+/* Driver pre-compile time settings. */
+/*===========================================================================*/
+
+/**
+ * @name PLATFORM configuration options
+ * @{
+ */
+/**
+ * @brief SDC1 driver enable switch.
+ * @details If set to @p TRUE the support for SDC1 is included.
+ * @note The default is @p TRUE if HAL_USE_SDC is set.
+ */
+#if !defined(PLATFORM_SDC_USE_SDC1) || defined(__DOXYGEN__)
+#define PLATFORM_SDC_USE_SDC1 TRUE
+#endif
+/** @} */
+
+/*===========================================================================*/
+/* Derived constants and error checks. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* Driver data structures and types. */
+/*===========================================================================*/
+
+/**
+ * @brief Type of card flags.
+ */
+typedef uint32_t sdcmode_t;
+
+/**
+ * @brief SDC Driver condition flags type.
+ */
+typedef uint32_t sdcflags_t;
+
+/**
+ * @brief Type of a structure representing an SDC driver.
+ */
+typedef struct SDCDriver SDCDriver;
+
+/**
+ * @brief Driver configuration structure.
+ * @note It could be empty on some architectures.
+ */
+typedef struct {
+ /**
+ * @brief Working area for memory consuming operations.
+ * @note It is mandatory for detecting MMC cards bigger than 2GB else it
+ * can be @p NULL.
+ * @note Memory pointed by this buffer is only used by @p sdcConnect(),
+ * afterward it can be reused for other purposes.
+ */
+ uint8_t *scratchpad;
+ /**
+ * @brief Bus width.
+ */
+ sdcbusmode_t bus_width;
+ /* End of the mandatory fields.*/
+} SDCConfig;
+
+/**
+ * @brief @p SDCDriver specific methods.
+ */
+#define _sdc_driver_methods \
+ _mmcsd_block_device_methods
+
+/**
+ * @extends MMCSDBlockDeviceVMT
+ *
+ * @brief @p SDCDriver virtual methods table.
+ */
+struct SDCDriverVMT {
+ _sdc_driver_methods
+};
+
+/**
+ * @brief Structure representing an SDC driver.
+ */
+struct SDCDriver {
+ /**
+ * @brief Virtual Methods Table.
+ */
+ const struct SDCDriverVMT *vmt;
+ _mmcsd_block_device_data
+ /**
+ * @brief Current configuration data.
+ */
+ const SDCConfig *config;
+ /**
+ * @brief Various flags regarding the mounted card.
+ */
+ sdcmode_t cardmode;
+ /**
+ * @brief Errors flags.
+ */
+ sdcflags_t errors;
+ /**
+ * @brief Card RCA.
+ */
+ uint32_t rca;
+ /* End of the mandatory fields.*/
+
+ /* Platform specific fields */
+ thread_reference_t thread;
+};
+
+/*===========================================================================*/
+/* Driver macros. */
+/*===========================================================================*/
+
+/*===========================================================================*/
+/* External declarations. */
+/*===========================================================================*/
+
+#if (PLATFORM_SDC_USE_SDC1 == TRUE) && !defined(__DOXYGEN__)
+extern SDCDriver SDCD1;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void sdc_lld_init(void);
+ void sdc_lld_start(SDCDriver *sdcp);
+ void sdc_lld_stop(SDCDriver *sdcp);
+ void sdc_lld_start_clk(SDCDriver *sdcp);
+ void sdc_lld_set_data_clk(SDCDriver *sdcp, sdcbusclk_t clk);
+ void sdc_lld_stop_clk(SDCDriver *sdcp);
+ void sdc_lld_set_bus_mode(SDCDriver *sdcp, sdcbusmode_t mode);
+ void sdc_lld_send_cmd_none(SDCDriver *sdcp, uint8_t cmd, uint32_t arg);
+ bool sdc_lld_send_cmd_short(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+ uint32_t *resp);
+ bool sdc_lld_send_cmd_short_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+ uint32_t *resp);
+ bool sdc_lld_send_cmd_long_crc(SDCDriver *sdcp, uint8_t cmd, uint32_t arg,
+ uint32_t *resp);
+ bool sdc_lld_read_special(SDCDriver *sdcp, uint8_t *buf, size_t bytes,
+ uint8_t cmd, uint32_t argument);
+ bool sdc_lld_read(SDCDriver *sdcp, uint32_t startblk,
+ uint8_t *buf, uint32_t n);
+ bool sdc_lld_write(SDCDriver *sdcp, uint32_t startblk,
+ const uint8_t *buf, uint32_t n);
+ bool sdc_lld_sync(SDCDriver *sdcp);
+ bool sdc_lld_is_card_inserted(SDCDriver *sdcp);
+ bool sdc_lld_is_write_protected(SDCDriver *sdcp);
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* HAL_USE_SDC == TRUE */
+
+#endif /* HAL_SDC_LLD_H */
+
+/** @} */
diff --git a/os/hal/ports/KINETIS/LLD/hal_serial_lld.c b/os/hal/ports/KINETIS/LLD/hal_serial_lld.c index c80cf22..c92fa5c 100644 --- a/os/hal/ports/KINETIS/LLD/hal_serial_lld.c +++ b/os/hal/ports/KINETIS/LLD/hal_serial_lld.c @@ -1,5 +1,6 @@ /*
ChibiOS - Copyright (C) 2013-2015 Fabio Utzig
+ Copyright (C) 2017 Wim Lewis
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
@@ -50,6 +51,18 @@ SerialDriver SD2; SerialDriver SD3;
#endif
+#if KINETIS_SERIAL_USE_UART3 || defined(__DOXYGEN__)
+SerialDriver SD4;
+#endif
+
+#if KINETIS_SERIAL_USE_UART4 || defined(__DOXYGEN__)
+SerialDriver SD5;
+#endif
+
+#if KINETIS_SERIAL_USE_UART5 || defined(__DOXYGEN__)
+SerialDriver SD6;
+#endif
+
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
@@ -95,33 +108,37 @@ static void serve_error_interrupt(SerialDriver *sdp) { UART_w_TypeDef *u = &(sdp->uart);
uint8_t s1 = *(u->s1_p);
- /* S1 bits are write-1-to-clear for UART0 on KL2x. */
- /* Clearing on K20x and KL2x/UART>0 is done by reading S1 and
+ /* Clearing on K20x, K60x, and KL2x/UART>0 is done by reading S1 and
* then reading D.*/
-#if defined(KL2x) && KINETIS_SERIAL_USE_UART0
- if(sdp == &SD1) {
- if(s1 & UARTx_S1_IDLE) {
- *(u->s1_p) |= UARTx_S1_IDLE;
- }
+ if(s1 & UARTx_S1_IDLE) {
+ (void)*(u->d_p);
+ }
- if(s1 & (UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF)) {
- set_error(sdp, s1);
- *(u->s1_p) |= UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF;
- }
- return;
+ if(s1 & (UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF)) {
+ set_error(sdp, s1);
+ (void)*(u->d_p);
}
-#endif /* KL2x && KINETIS_SERIAL_USE_UART0 */
+}
+
+#if defined(KL2x) && KINETIS_SERIAL_USE_UART0
+static void serve_error_interrupt_uart0(void) {
+ SerialDriver *sdp = &SD1;
+ UART_w_TypeDef *u = &(sdp->uart);
+ uint8_t s1 = *(u->s1_p);
+
+ /* S1 bits are write-1-to-clear for UART0 on KL2x. */
if(s1 & UARTx_S1_IDLE) {
- (void)*(u->d_p);
+ *(u->s1_p) |= UARTx_S1_IDLE;
}
if(s1 & (UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF)) {
set_error(sdp, s1);
- (void)*(u->d_p);
+ *(u->s1_p) |= UARTx_S1_OR | UARTx_S1_NF | UARTx_S1_FE | UARTx_S1_PF;
}
}
+#endif /* KL2x && KINETIS_SERIAL_USE_UART0 */
/**
* @brief Common IRQ handler.
@@ -161,6 +178,12 @@ static void serve_interrupt(SerialDriver *sdp) { }
}
+#if defined(KL2x) && KINETIS_SERIAL_USE_UART0
+ if (sdp == &SD1) {
+ serve_error_interrupt_uart0();
+ return;
+ }
+#endif
serve_error_interrupt(sdp);
}
@@ -184,29 +207,28 @@ static void preload(SerialDriver *sdp) { /**
* @brief Driver output notification.
*/
-#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
-static void notify1(io_queue_t *qp)
+static void notify(io_queue_t *qp)
{
- (void)qp;
- preload(&SD1);
+ preload(qp->q_link);
}
-#endif
-#if KINETIS_SERIAL_USE_UART1 || defined(__DOXYGEN__)
-static void notify2(io_queue_t *qp)
-{
- (void)qp;
- preload(&SD2);
-}
-#endif
-
-#if KINETIS_SERIAL_USE_UART2 || defined(__DOXYGEN__)
-static void notify3(io_queue_t *qp)
-{
- (void)qp;
- preload(&SD3);
+/**
+ * @brief Common driver initialization, except LP.
+ */
+static void sd_lld_init_driver(SerialDriver *SDn, UART_TypeDef *UARTn) {
+ /* Driver initialization.*/
+ sdObjectInit(SDn, NULL, notify);
+ SDn->uart.bdh_p = &(UARTn->BDH);
+ SDn->uart.bdl_p = &(UARTn->BDL);
+ SDn->uart.c1_p = &(UARTn->C1);
+ SDn->uart.c2_p = &(UARTn->C2);
+ SDn->uart.c3_p = &(UARTn->C3);
+ SDn->uart.c4_p = &(UARTn->C4);
+ SDn->uart.s1_p = (volatile uint8_t *)&(UARTn->S1);
+ SDn->uart.s2_p = &(UARTn->S2);
+ SDn->uart.d_p = &(UARTn->D);
+ SDn->uart.uart_p = UARTn;
}
-#endif
/**
* @brief Common UART configuration.
@@ -240,9 +262,9 @@ static void configure_uart(SerialDriver *sdp, const SerialConfig *config) { }
#endif /* KINETIS_SERIAL_USE_UART0 */
-#elif defined(K20x) /* KL2x */
+#elif defined(K20x) || defined(K60x) /* KL2x */
- /* UARTs 0 and 1 are clocked from SYSCLK, others from BUSCLK on K20x. */
+ /* UARTs 0 and 1 are clocked from SYSCLK, others from BUSCLK on K20x and K60x. */
#if KINETIS_SERIAL_USE_UART0
if(sdp == &SD1)
divisor = KINETIS_SYSCLK_FREQUENCY;
@@ -260,9 +282,9 @@ static void configure_uart(SerialDriver *sdp, const SerialConfig *config) { *(uart->bdh_p) = UARTx_BDH_SBR(divisor >> 13) | (*(uart->bdh_p) & ~UARTx_BDH_SBR_MASK);
*(uart->bdl_p) = UARTx_BDL_SBR(divisor >> 5);
-#if defined(K20x)
+#if defined(K20x) || defined(K60x)
*(uart->c4_p) = UARTx_C4_BRFA(divisor) | (*(uart->c4_p) & ~UARTx_C4_BRFA_MASK);
-#endif /* K20x */
+#endif /* K20x, K60x */
/* Line settings. */
*(uart->c1_p) = 0;
@@ -300,12 +322,40 @@ OSAL_IRQ_HANDLER(KINETIS_SERIAL2_IRQ_VECTOR) { }
#endif
+#if KINETIS_SERIAL_USE_UART3 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL3_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ serve_interrupt(&SD4);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART4 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL4_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ serve_interrupt(&SD5);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART5 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL5_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ serve_interrupt(&SD6);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
#if KINETIS_HAS_SERIAL_ERROR_IRQ
#if KINETIS_SERIAL_USE_UART0 || defined(__DOXYGEN__)
OSAL_IRQ_HANDLER(KINETIS_SERIAL0_ERROR_IRQ_VECTOR) {
OSAL_IRQ_PROLOGUE();
+#if defined(KL2x)
+ serve_error_interrupt_uart0();
+#else
serve_error_interrupt(&SD1);
+#endif
OSAL_IRQ_EPILOGUE();
}
#endif
@@ -326,6 +376,30 @@ OSAL_IRQ_HANDLER(KINETIS_SERIAL2_ERROR_IRQ_VECTOR) { }
#endif
+#if KINETIS_SERIAL_USE_UART3 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL3_ERROR_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ serve_error_interrupt(&SD4);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART4 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL4_ERROR_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ serve_error_interrupt(&SD5);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
+#if KINETIS_SERIAL_USE_UART5 || defined(__DOXYGEN__)
+OSAL_IRQ_HANDLER(KINETIS_SERIAL5_ERROR_IRQ_VECTOR) {
+ OSAL_IRQ_PROLOGUE();
+ serve_error_interrupt(&SD6);
+ OSAL_IRQ_EPILOGUE();
+}
+#endif
+
#endif /* KINETIS_HAS_SERIAL_ERROR_IRQ */
/*===========================================================================*/
@@ -341,19 +415,11 @@ void sd_lld_init(void) { #if KINETIS_SERIAL_USE_UART0
/* Driver initialization.*/
- sdObjectInit(&SD1, NULL, notify1);
#if ! KINETIS_SERIAL0_IS_LPUART
- SD1.uart.bdh_p = &(UART0->BDH);
- SD1.uart.bdl_p = &(UART0->BDL);
- SD1.uart.c1_p = &(UART0->C1);
- SD1.uart.c2_p = &(UART0->C2);
- SD1.uart.c3_p = &(UART0->C3);
- SD1.uart.c4_p = &(UART0->C4);
- SD1.uart.s1_p = (volatile uint8_t *)&(UART0->S1);
- SD1.uart.s2_p = &(UART0->S2);
- SD1.uart.d_p = &(UART0->D);
+ sd_lld_init_driver(&SD1, UART0);
#else /* ! KINETIS_SERIAL0_IS_LPUART */
/* little endian! */
+ sdObjectInit(&SD1, NULL, notify);
SD1.uart.bdh_p = ((uint8_t *)&(LPUART0->BAUD)) + 1; /* BDH: BAUD, byte 3 */
SD1.uart.bdl_p = ((uint8_t *)&(LPUART0->BAUD)) + 0; /* BDL: BAUD, byte 4 */
SD1.uart.c1_p = ((uint8_t *)&(LPUART0->CTRL)) + 0; /* C1: CTRL, byte 4 */
@@ -377,20 +443,11 @@ void sd_lld_init(void) { #if KINETIS_SERIAL_USE_UART1
/* Driver initialization.*/
- sdObjectInit(&SD2, NULL, notify2);
#if ! KINETIS_SERIAL1_IS_LPUART
- SD2.uart.bdh_p = &(UART1->BDH);
- SD2.uart.bdl_p = &(UART1->BDL);
- SD2.uart.c1_p = &(UART1->C1);
- SD2.uart.c2_p = &(UART1->C2);
- SD2.uart.c3_p = &(UART1->C3);
- SD2.uart.c4_p = &(UART1->C4);
- SD2.uart.s1_p = (volatile uint8_t *)&(UART1->S1);
- SD2.uart.s2_p = &(UART1->S2);
- SD2.uart.d_p = &(UART1->D);
- SD2.uart.uart_p = UART1;
+ sd_lld_init_driver(&SD2, UART1);
#else /* ! KINETIS_SERIAL1_IS_LPUART */
/* little endian! */
+ sdObjectInit(&SD2, NULL, notify);
SD2.uart.bdh_p = ((uint8_t *)&(LPUART1->BAUD)) + 1; /* BDH: BAUD, byte 3 */
SD2.uart.bdl_p = ((uint8_t *)&(LPUART1->BAUD)) + 0; /* BDL: BAUD, byte 4 */
SD2.uart.c1_p = ((uint8_t *)&(LPUART1->CTRL)) + 0; /* C1: CTRL, byte 4 */
@@ -406,19 +463,20 @@ void sd_lld_init(void) { #endif /* KINETIS_SERIAL_USE_UART1 */
#if KINETIS_SERIAL_USE_UART2
- /* Driver initialization.*/
- sdObjectInit(&SD3, NULL, notify3);
- SD3.uart.bdh_p = &(UART2->BDH);
- SD3.uart.bdl_p = &(UART2->BDL);
- SD3.uart.c1_p = &(UART2->C1);
- SD3.uart.c2_p = &(UART2->C2);
- SD3.uart.c3_p = &(UART2->C3);
- SD3.uart.c4_p = &(UART2->C4);
- SD3.uart.s1_p = (volatile uint8_t *)&(UART2->S1);
- SD3.uart.s2_p = &(UART2->S2);
- SD3.uart.d_p = &(UART2->D);
- SD3.uart.uart_p = UART2;
+ sd_lld_init_driver(&SD3, UART2);
#endif /* KINETIS_SERIAL_USE_UART2 */
+
+#if KINETIS_SERIAL_USE_UART3
+ sd_lld_init_driver(&SD4, UART3);
+#endif /* KINETIS_SERIAL_USE_UART3 */
+
+#if KINETIS_SERIAL_USE_UART4
+ sd_lld_init_driver(&SD5, UART4);
+#endif /* KINETIS_SERIAL_USE_UART4 */
+
+#if KINETIS_SERIAL_USE_UART5
+ sd_lld_init_driver(&SD6, UART5);
+#endif /* KINETIS_SERIAL_USE_UART5 */
}
/**
@@ -505,6 +563,33 @@ void sd_lld_start(SerialDriver *sdp, const SerialConfig *config) { }
#endif /* KINETIS_SERIAL_USE_UART2 */
+#if KINETIS_SERIAL_USE_UART3
+ if (sdp == &SD4) {
+ SIM->SCGC4 |= SIM_SCGC4_UART3;
+ configure_uart(sdp, config);
+ nvicEnableVector(UART3Status_IRQn, KINETIS_SERIAL_UART3_PRIORITY);
+ nvicEnableVector(UART3Error_IRQn, KINETIS_SERIAL_UART3_PRIORITY);
+ }
+#endif /* KINETIS_SERIAL_USE_UART3 */
+
+#if KINETIS_SERIAL_USE_UART4
+ if (sdp == &SD5) {
+ SIM->SCGC1 |= SIM_SCGC1_UART4;
+ configure_uart(sdp, config);
+ nvicEnableVector(UART4Status_IRQn, KINETIS_SERIAL_UART4_PRIORITY);
+ nvicEnableVector(UART4Error_IRQn, KINETIS_SERIAL_UART4_PRIORITY);
+ }
+#endif /* KINETIS_SERIAL_USE_UART4 */
+
+#if KINETIS_SERIAL_USE_UART5
+ if (sdp == &SD6) {
+ SIM->SCGC1 |= SIM_SCGC1_UART5;
+ configure_uart(sdp, config);
+ nvicEnableVector(UART5Status_IRQn, KINETIS_SERIAL_UART5_PRIORITY);
+ nvicEnableVector(UART5Error_IRQn, KINETIS_SERIAL_UART5_PRIORITY);
+ }
+#endif /* KINETIS_SERIAL_USE_UART5 */
+
}
/* Configures the peripheral.*/
@@ -575,6 +660,30 @@ void sd_lld_stop(SerialDriver *sdp) { SIM->SCGC4 &= ~SIM_SCGC4_UART2;
}
#endif
+
+#if KINETIS_SERIAL_USE_UART3
+ if (sdp == &SD4) {
+ nvicDisableVector(UART3Status_IRQn);
+ nvicDisableVector(UART3Error_IRQn);
+ SIM->SCGC4 &= ~SIM_SCGC4_UART3;
+ }
+#endif
+
+#if KINETIS_SERIAL_USE_UART4
+ if (sdp == &SD5) {
+ nvicDisableVector(UART4Status_IRQn);
+ nvicDisableVector(UART4Error_IRQn);
+ SIM->SCGC1 &= ~SIM_SCGC1_UART4;
+ }
+#endif
+
+#if KINETIS_SERIAL_USE_UART5
+ if (sdp == &SD6) {
+ nvicDisableVector(UART5Status_IRQn);
+ nvicDisableVector(UART5Error_IRQn);
+ SIM->SCGC1 &= ~SIM_SCGC1_UART5;
+ }
+#endif
}
}
diff --git a/os/hal/ports/KINETIS/LLD/hal_serial_lld.h b/os/hal/ports/KINETIS/LLD/hal_serial_lld.h index f11c063..3cb6d2b 100644 --- a/os/hal/ports/KINETIS/LLD/hal_serial_lld.h +++ b/os/hal/ports/KINETIS/LLD/hal_serial_lld.h @@ -60,6 +60,27 @@ #if !defined(KINETIS_SERIAL_USE_UART2) || defined(__DOXYGEN__)
#define KINETIS_SERIAL_USE_UART2 FALSE
#endif
+/**
+ * @brief SD4 driver enable switch.
+ * @details If set to @p TRUE the support for SD4 is included.
+ */
+#if !defined(KINETIS_SERIAL_USE_UART3) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_USE_UART3 FALSE
+#endif
+/**
+ * @brief SD5 driver enable switch.
+ * @details If set to @p TRUE the support for SD5 is included.
+ */
+#if !defined(KINETIS_SERIAL_USE_UART4) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_USE_UART4 FALSE
+#endif
+/**
+ * @brief SD6 driver enable switch.
+ * @details If set to @p TRUE the support for SD6 is included.
+ */
+#if !defined(KINETIS_SERIAL_USE_UART5) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_USE_UART5 FALSE
+#endif
/**
* @brief UART0 interrupt priority level setting.
@@ -83,6 +104,27 @@ #endif
/**
+ * @brief UART3 interrupt priority level setting.
+ */
+#if !defined(KINETIS_SERIAL_UART3_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_UART3_PRIORITY 12
+#endif
+
+/**
+ * @brief UART4 interrupt priority level setting.
+ */
+#if !defined(KINETIS_SERIAL_UART4_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_UART4_PRIORITY 12
+#endif
+
+/**
+ * @brief UART5 interrupt priority level setting.
+ */
+#if !defined(KINETIS_SERIAL_UART5_PRIORITY) || defined(__DOXYGEN__)
+#define KINETIS_SERIAL_UART5_PRIORITY 12
+#endif
+
+/**
* @brief UART0 clock source.
*/
#if !defined(KINETIS_UART0_CLOCK_SRC) || defined(__DOXYGEN__)
@@ -115,8 +157,21 @@ #error "UART2 not present in the selected device"
#endif
+#if KINETIS_SERIAL_USE_UART3 && !KINETIS_HAS_SERIAL3
+#error "UART3 not present in the selected device"
+#endif
+
+#if KINETIS_SERIAL_USE_UART4 && !KINETIS_HAS_SERIAL4
+#error "UART4 not present in the selected device"
+#endif
+
+#if KINETIS_SERIAL_USE_UART5 && !KINETIS_HAS_SERIAL5
+#error "UART5 not present in the selected device"
+#endif
+
#if !(KINETIS_SERIAL_USE_UART0 || KINETIS_SERIAL_USE_UART1 || \
- KINETIS_SERIAL_USE_UART2)
+ KINETIS_SERIAL_USE_UART2 || KINETIS_SERIAL_USE_UART3 || \
+ KINETIS_SERIAL_USE_UART4 || KINETIS_SERIAL_USE_UART5)
#error "Serial driver activated but no UART peripheral assigned"
#endif
@@ -203,6 +258,18 @@ extern SerialDriver SD2; extern SerialDriver SD3;
#endif
+#if KINETIS_SERIAL_USE_UART3 && !defined(__DOXYGEN__)
+extern SerialDriver SD4;
+#endif
+
+#if KINETIS_SERIAL_USE_UART4 && !defined(__DOXYGEN__)
+extern SerialDriver SD5;
+#endif
+
+#if KINETIS_SERIAL_USE_UART5 && !defined(__DOXYGEN__)
+extern SerialDriver SD6;
+#endif
+
#ifdef __cplusplus
extern "C" {
#endif
diff --git a/os/hal/ports/KINETIS/LLD/hal_usb_lld.c b/os/hal/ports/KINETIS/LLD/hal_usb_lld.c index e8d9778..ba91d24 100644 --- a/os/hal/ports/KINETIS/LLD/hal_usb_lld.c +++ b/os/hal/ports/KINETIS/LLD/hal_usb_lld.c @@ -158,7 +158,7 @@ void usb_packet_transmit(USBDriver *usbp, usbep_t ep, size_t n) USBInEndpointState *isp = epc->in_state;
bd_t *bd = (bd_t *)&_bdt[BDT_INDEX(ep, TX, isp->odd_even)];
-
+
if (n > (size_t)epc->in_maxsize)
n = (size_t)epc->in_maxsize;
@@ -244,19 +244,16 @@ OSAL_IRQ_HANDLER(KINETIS_USB_IRQ_VECTOR) { {
case BDT_PID_SETUP: // SETUP
{
- /* Clear any pending IN stuff */
- _bdt[BDT_INDEX(ep, TX, EVEN)].desc = 0;
- _bdt[BDT_INDEX(ep, TX, ODD)].desc = 0;
- /* Also in the chibios state machine */
+ /* Clear receiving in the chibios state machine */
(usbp)->receiving &= ~1;
- /* After a SETUP, IN is always DATA1 */
- usbp->epc[ep]->in_state->data_bank = DATA1;
-
- /* Call SETUP function (ChibiOS core), which sends back stuff */
+ /* Call SETUP function (ChibiOS core), which prepares
+ * for send or receive and releases the buffer
+ */
_usb_isr_invoke_setup_cb(usbp, ep);
- /* Buffer is released by the above callback. */
- /* from Paul: "unfreeze the USB, now that we're ready" */
- USB0->CTL = USBx_CTL_USBENSOFEN;
+ /* When a setup packet is received, tx is suspended,
+ * so it needs to be resumed here.
+ */
+ USB0->CTL &= ~USBx_CTL_TXSUSPENDTOKENBUSY;
} break;
case BDT_PID_IN: // IN
{
@@ -728,9 +725,23 @@ void usb_lld_read_setup(USBDriver *usbp, usbep_t ep, uint8_t *buf) { }
/* Release the buffer
* Setup packet is always DATA0
- * Initialize buffers so current expects DATA0 & opposite DATA1 */
+ * Release the current DATA0 buffer
+ */
bd->desc = BDT_DESC(usbp->epc[ep]->out_maxsize,DATA0);
- _bdt[BDT_INDEX(ep, RX, os->odd_even^ODD)].desc = BDT_DESC(usbp->epc[ep]->out_maxsize,DATA1);
+ /* If DATA1 was expected, then the states are out of sync.
+ * So reset the other buffer too, and set it as DATA1.
+ * This should not happen in normal cases, but is possible in
+ * error situations. NOTE: it's possible that this is too late
+ * and the next packet has already been received and dropped, but
+ * there's nothing that we can do about that anymore at this point.
+ */
+ if (os->data_bank == DATA1)
+ {
+ bd_t *bd_next = (bd_t*)&_bdt[BDT_INDEX(ep, RX, os->odd_even^ODD)];
+ bd_next->desc = BDT_DESC(usbp->epc[ep]->out_maxsize,DATA1);
+ }
+ /* After a SETUP, both in and out are always DATA1 */
+ usbp->epc[ep]->in_state->data_bank = DATA1;
os->data_bank = DATA1;
}
@@ -762,8 +773,22 @@ void usb_lld_start_out(USBDriver *usbp, usbep_t ep) { * @notapi
*/
void usb_lld_start_in(USBDriver *usbp, usbep_t ep) {
- (void)usbp;
- (void)ep;
+ if (ep == 0 && usbp->ep0state == USB_EP0_IN_SENDING_STS) {
+ /* When a status packet is about to be sent on endpoint 0 the
+ * next packet will be a setup packet, which means that the
+ * buffer we expect after this should be DATA0, and the following
+ * DATA1. Since no out packets should be in flight at this time
+ * it's safe to initialize the buffers according to the expectations
+ * here.
+ */
+ const USBEndpointConfig* epc = usbp->epc[ep];
+ bd_t * bd = (bd_t*)&_bdt[BDT_INDEX(ep, RX, epc->out_state->odd_even)];
+ bd_t *bd_next = (bd_t*)&_bdt[BDT_INDEX(ep, RX, epc->out_state->odd_even^ODD)];
+
+ bd->desc = BDT_DESC(usbp->epc[ep]->out_maxsize,DATA1);
+ bd_next->desc = BDT_DESC(usbp->epc[ep]->out_maxsize,DATA0);
+ epc->out_state->data_bank = DATA0;
+ }
usb_packet_transmit(usbp,ep,usbp->epc[ep]->in_state->txsize);
}
diff --git a/os/hal/ports/KINETIS/LLD/hal_usb_lld.h b/os/hal/ports/KINETIS/LLD/hal_usb_lld.h index 961490e..bd4eb39 100644 --- a/os/hal/ports/KINETIS/LLD/hal_usb_lld.h +++ b/os/hal/ports/KINETIS/LLD/hal_usb_lld.h @@ -76,6 +76,13 @@ #define KINETIS_USB_ENDPOINTS USB_MAX_ENDPOINTS+1
#endif
+/**
+ * @brief Host wake-up procedure duration.
+ */
+#if !defined(USB_HOST_WAKEUP_DURATION) || defined(__DOXYGEN__)
+#define USB_HOST_WAKEUP_DURATION 2
+#endif
+
/*===========================================================================*/
/* Derived constants and error checks. */
/*===========================================================================*/
@@ -97,6 +104,10 @@ #error "KINETIS_USB_IRQ_VECTOR not defined"
#endif
+#if (USB_HOST_WAKEUP_DURATION < 2) || (USB_HOST_WAKEUP_DURATION > 15)
+#error "invalid USB_HOST_WAKEUP_DURATION setting, it must be between 2 and 15"
+#endif
+
/*===========================================================================*/
/* Driver data structures and types. */
/*===========================================================================*/
@@ -394,6 +405,18 @@ struct USBDriver { #endif /* KINETIS_USB0_IS_USBOTG */
#endif
+/**
+ * @brief Start of host wake-up procedure.
+ *
+ * @notapi
+ */
+#define usb_lld_wakeup_host(usbp) \
+ do{ \
+ USB0->CTL |= USBx_CTL_RESUME; \
+ osalThreadSleepMilliseconds(USB_HOST_WAKEUP_DURATION); \
+ USB0->CTL &= ~USBx_CTL_RESUME; \
+ } while (false)
+
/*===========================================================================*/
/* External declarations. */
/*===========================================================================*/
diff --git a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c index a2cf026..701b87d 100755 --- a/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c +++ b/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c @@ -155,7 +155,7 @@ void crc_lld_start(CRCDriver *crcp) { if (crcp->config == NULL) crcp->config = &default_config; - rccEnableCRC(FALSE); + rccEnableCRC(); #if STM32_CRC_PROGRAMMABLE == TRUE crcp->crc->INIT = crcp->config->initial_val; @@ -234,7 +234,7 @@ void crc_lld_stop(CRCDriver *crcp) { #else (void)crcp; #endif - rccDisableCRC(FALSE); + rccDisableCRC(); } /** diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c index b4c2938..71c6ada 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c @@ -97,7 +97,10 @@ void fsmc_init(void) { #if (defined(STM32F427xx) || defined(STM32F437xx) || \ defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F7)) + defined(STM32F745xx) || defined(STM32F746xx) || \ + defined(STM32F756xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || \ + defined(STM32F779xx)) #if STM32_USE_FSMC_SDRAM FSMCD1.sdram = (FSMC_SDRAM_TypeDef *)FSMC_Bank5_6_R_BASE; #endif @@ -156,7 +159,7 @@ void fsmc_stop(FSMCDriver *fsmcp) { #if HAL_USE_NAND nvicDisableVector(STM32_FSMC_NUMBER); #endif - rccDisableFSMC(FALSE); + rccDisableFSMC(); } #endif /* STM32_FSMC_USE_FSMC1 */ diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h index 2bc267f..80c5d26 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.h @@ -36,7 +36,10 @@ */ #if (defined(STM32F427xx) || defined(STM32F437xx) || \ defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F769xx)) + defined(STM32F745xx) || defined(STM32F746xx) || \ + defined(STM32F756xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || \ + defined(STM32F779xx)) #if !defined(FSMC_Bank1_R_BASE) #define FSMC_Bank1_R_BASE (FMC_R_BASE + 0x0000) #endif diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c index ea1be4c..6d727c8 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.c @@ -29,7 +29,10 @@ #if (defined(STM32F427xx) || defined(STM32F437xx) || \ defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F769xx)) + defined(STM32F745xx) || defined(STM32F746xx) || \ + defined(STM32F756xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || \ + defined(STM32F779xx)) #if (STM32_USE_FSMC_SDRAM == TRUE) || defined(__DOXYGEN__) diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h index fdf3268..c9f9de0 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sdram.h @@ -30,7 +30,10 @@ #if (defined(STM32F427xx) || defined(STM32F437xx) || \ defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F769xx)) + defined(STM32F745xx) || defined(STM32F746xx) || \ + defined(STM32F756xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || \ + defined(STM32F779xx)) #include "hal_fsmc.h" diff --git a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c index fbd6f56..da13ca5 100644 --- a/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c +++ b/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c @@ -148,7 +148,10 @@ void fsmcSramStop(SRAMDriver *sramp) { uint32_t mask = FSMC_BCR_MBKEN; #if (defined(STM32F427xx) || defined(STM32F437xx) || \ defined(STM32F429xx) || defined(STM32F439xx) || \ - defined(STM32F7)) + defined(STM32F745xx) || defined(STM32F746xx) || \ + defined(STM32F756xx) || defined(STM32F767xx) || \ + defined(STM32F769xx) || defined(STM32F777xx) || \ + defined(STM32F779xx)) mask |= FSMC_BCR_CCLKEN; #endif sramp->sram->BCR &= ~mask; diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c index c04278e..ed4c5b8 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c +++ b/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c @@ -1057,75 +1057,75 @@ void eicu_lld_stop(EICUDriver *eicup) { if (&EICUD1 == eicup) { nvicDisableVector(STM32_TIM1_UP_NUMBER); nvicDisableVector(STM32_TIM1_CC_NUMBER); - rccDisableTIM1(FALSE); + rccDisableTIM1(); } #endif #if STM32_EICU_USE_TIM2 if (&EICUD2 == eicup) { nvicDisableVector(STM32_TIM2_NUMBER); - rccDisableTIM2(FALSE); + rccDisableTIM2(); } #endif #if STM32_EICU_USE_TIM3 if (&EICUD3 == eicup) { nvicDisableVector(STM32_TIM3_NUMBER); - rccDisableTIM3(FALSE); + rccDisableTIM3(); } #endif #if STM32_EICU_USE_TIM4 if (&EICUD4 == eicup) { nvicDisableVector(STM32_TIM4_NUMBER); - rccDisableTIM4(FALSE); + rccDisableTIM4(); } #endif #if STM32_EICU_USE_TIM5 if (&EICUD5 == eicup) { nvicDisableVector(STM32_TIM5_NUMBER); - rccDisableTIM5(FALSE); + rccDisableTIM5(); } #endif #if STM32_EICU_USE_TIM8 if (&EICUD8 == eicup) { nvicDisableVector(STM32_TIM8_UP_NUMBER); nvicDisableVector(STM32_TIM8_CC_NUMBER); - rccDisableTIM8(FALSE); + rccDisableTIM8(); } #endif #if STM32_EICU_USE_TIM9 if (&EICUD9 == eicup) { nvicDisableVector(STM32_TIM9_NUMBER); - rccDisableTIM9(FALSE); + rccDisableTIM9(); } #endif #if STM32_EICU_USE_TIM12 if (&EICUD12 == eicup) { nvicDisableVector(STM32_TIM12_NUMBER); - rccDisableTIM12(FALSE); + rccDisableTIM12(); } #endif } #if STM32_EICU_USE_TIM10 if (&EICUD10 == eicup) { nvicDisableVector(STM32_TIM10_NUMBER); - rccDisableTIM10(FALSE); + rccDisableTIM10(); } #endif #if STM32_EICU_USE_TIM11 if (&EICUD11 == eicup) { nvicDisableVector(STM32_TIM11_NUMBER); - rccDisableTIM11(FALSE); + rccDisableTIM11(); } #endif #if STM32_EICU_USE_TIM13 if (&EICUD13 == eicup) { nvicDisableVector(STM32_TIM13_NUMBER); - rccDisableTIM13(FALSE); + rccDisableTIM13(); } #endif #if STM32_EICU_USE_TIM14 if (&EICUD14 == eicup) { nvicDisableVector(STM32_TIM14_NUMBER); - rccDisableTIM14(FALSE); + rccDisableTIM14(); } #endif } diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c index 6138481..e07b946 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c +++ b/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c @@ -235,33 +235,33 @@ void qei_lld_stop(QEIDriver *qeip) { /* Clock deactivation.*/
#if STM32_QEI_USE_TIM1
if (&QEID1 == qeip) {
- rccDisableTIM1(FALSE);
+ rccDisableTIM1();
}
#endif
#if STM32_QEI_USE_TIM2
if (&QEID2 == qeip) {
- rccDisableTIM2(FALSE);
+ rccDisableTIM2();
}
#endif
#if STM32_QEI_USE_TIM3
if (&QEID3 == qeip) {
- rccDisableTIM3(FALSE);
+ rccDisableTIM3();
}
#endif
#if STM32_QEI_USE_TIM4
if (&QEID4 == qeip) {
- rccDisableTIM4(FALSE);
+ rccDisableTIM4();
}
#endif
#if STM32_QEI_USE_TIM5
if (&QEID5 == qeip) {
- rccDisableTIM5(FALSE);
+ rccDisableTIM5();
}
#endif
}
#if STM32_QEI_USE_TIM8
if (&QEID8 == qeip) {
- rccDisableTIM8(FALSE);
+ rccDisableTIM8();
}
#endif
}
diff --git a/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c b/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c index 37a48fd..d95c6a3 100644 --- a/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c +++ b/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c @@ -713,44 +713,44 @@ void timcap_lld_stop(TIMCAPDriver *timcapp) { if (&TIMCAPD1 == timcapp) { nvicDisableVector(STM32_TIM1_UP_NUMBER); nvicDisableVector(STM32_TIM1_CC_NUMBER); - rccDisableTIM1(FALSE); + rccDisableTIM1(); } #endif #if STM32_TIMCAP_USE_TIM2 if (&TIMCAPD2 == timcapp) { nvicDisableVector(STM32_TIM2_NUMBER); - rccDisableTIM2(FALSE); + rccDisableTIM2(); } #endif #if STM32_TIMCAP_USE_TIM3 if (&TIMCAPD3 == timcapp) { nvicDisableVector(STM32_TIM3_NUMBER); - rccDisableTIM3(FALSE); + rccDisableTIM3(); } #endif #if STM32_TIMCAP_USE_TIM4 if (&TIMCAPD4 == timcapp) { nvicDisableVector(STM32_TIM4_NUMBER); - rccDisableTIM4(FALSE); + rccDisableTIM4(); } #endif #if STM32_TIMCAP_USE_TIM5 if (&TIMCAPD5 == timcapp) { nvicDisableVector(STM32_TIM5_NUMBER); - rccDisableTIM5(FALSE); + rccDisableTIM5(); } #endif #if STM32_TIMCAP_USE_TIM8 if (&TIMCAPD8 == timcapp) { nvicDisableVector(STM32_TIM8_UP_NUMBER); nvicDisableVector(STM32_TIM8_CC_NUMBER); - rccDisableTIM8(FALSE); + rccDisableTIM8(); } #endif #if STM32_TIMCAP_USE_TIM9 if (&TIMCAPD9 == timcapp) { nvicDisableVector(STM32_TIM9_NUMBER); - rccDisableTIM9(FALSE); + rccDisableTIM9(); } #endif } diff --git a/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c b/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c index 4723508..2894907 100644 --- a/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c +++ b/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c @@ -1665,9 +1665,9 @@ usbh_urbstatus_t usbh_lld_root_hub_request(USBHDriver *usbh, uint8_t bmRequestTy * despite reporting a successful por enable. */ uerr("Detected enabled port; resetting OTG core"); otg->GAHBCFG = 0; - osalThreadSleepS(MS2ST(20)); + osalThreadSleepS(OSAL_MS2I(20)); _usbh_start(usbh); /* this effectively resets the core */ - osalThreadSleepS(MS2ST(100)); /* during this delay, the core generates connect ISR */ + osalThreadSleepS(OSAL_MS2I(100)); /* during this delay, the core generates connect ISR */ uinfo("OTG reset ended"); if (otg->HPRT & HPRT_PCSTS) { /* if the device is still connected, don't report a C_CONNECTION flag, which would cause @@ -1680,9 +1680,9 @@ usbh_urbstatus_t usbh_lld_root_hub_request(USBHDriver *usbh, uint8_t bmRequestTy hprt &= ~(HPRT_PSUSP | HPRT_PENA | HPRT_PCDET | HPRT_PENCHNG | HPRT_POCCHNG); while ((otg->GRSTCTL & GRSTCTL_AHBIDL) == 0); otg->HPRT = hprt | HPRT_PRST; - osalThreadSleepS(MS2ST(15)); + osalThreadSleepS(OSAL_MS2I(15)); otg->HPRT = hprt; - osalThreadSleepS(MS2ST(10)); + osalThreadSleepS(OSAL_MS2I(10)); usbh->rootport.lld_c_status |= USBH_PORTSTATUS_C_RESET; osalSysUnlock(); } break; diff --git a/os/hal/ports/STM32/STM32F0xx/platform.mk b/os/hal/ports/STM32/STM32F0xx/platform.mk index 377acdf..0102162 100644 --- a/os/hal/ports/STM32/STM32F0xx/platform.mk +++ b/os/hal/ports/STM32/STM32F0xx/platform.mk @@ -2,7 +2,7 @@ include ${CHIBIOS}/os/hal/ports/STM32/STM32F0xx/platform.mk PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c \ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c \ - ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c \ + ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1 \ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1 \ diff --git a/os/hal/ports/STM32/STM32L4xx/platform.mk b/os/hal/ports/STM32/STM32L4xx/platform.mk new file mode 100644 index 0000000..b9bbfea --- /dev/null +++ b/os/hal/ports/STM32/STM32L4xx/platform.mk @@ -0,0 +1,21 @@ +include ${CHIBIOS}/os/hal/ports/STM32/STM32L4xx/platform.mk
+
+PLATFORMSRC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1/hal_crc_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/DMA2Dv1/hal_stm32_dma2d.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_nand_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1/hal_fsmc_sram.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/LTDCv1/hal_stm32_ltdc.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_eicu_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_timcap_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1/hal_qei_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/USBHv1/hal_usbh_lld.c \
+ ${CHIBIOS_CONTRIB}/os/hal/src/hal_fsmc_sdram.c
+
+PLATFORMINC += ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/CRCv1 \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/DMA2Dv1 \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/FSMCv1 \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/LTDCv1 \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/TIMv1 \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD/USBHv1 \
+ ${CHIBIOS_CONTRIB}/os/hal/ports/STM32/LLD
diff --git a/os/hal/ports/TIVA/LLD/GPIO/driver.mk b/os/hal/ports/TIVA/LLD/GPIO/driver.mk index 121ef57..486fe73 100644 --- a/os/hal/ports/TIVA/LLD/GPIO/driver.mk +++ b/os/hal/ports/TIVA/LLD/GPIO/driver.mk @@ -2,12 +2,8 @@ ifeq ($(USE_SMART_BUILD),yes) ifneq ($(findstring HAL_USE_PAL TRUE,$(HALCONF)),) PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c endif -ifneq ($(findstring HAL_USE_EXT TRUE,$(HALCONF)),) -PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c -endif else PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c -PLATFORMSRC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c endif PLATFORMINC += $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/GPIO diff --git a/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c b/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c deleted file mode 100644 index 40f06f9..0000000 --- a/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.c +++ /dev/null @@ -1,981 +0,0 @@ -/* - Copyright (C) 2014..2017 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file GPIO/hal_ext_lld.c - * @brief Tiva EXT subsystem low level driver source. - * - * @addtogroup EXT - * @{ - */ - -#include "hal.h" - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver local definitions. */ -/*===========================================================================*/ - -/** - * @brief Generic interrupt serving code for multiple pins per interrupt - * handler. - */ -#define ext_lld_serve_port_interrupt(gpio, start) \ - do { \ - uint32_t mis = HWREG(gpio + GPIO_O_MIS); \ - \ - HWREG(gpio + GPIO_O_ICR) = mis; \ - \ - if (mis & (1 << 0)) { \ - EXTD1.config->channels[start + 0].cb(&EXTD1, start + 0); \ - } \ - if (mis & (1 << 1)) { \ - EXTD1.config->channels[start + 1].cb(&EXTD1, start + 1); \ - } \ - if (mis & (1 << 2)) { \ - EXTD1.config->channels[start + 2].cb(&EXTD1, start + 2); \ - } \ - if (mis & (1 << 3)) { \ - EXTD1.config->channels[start + 3].cb(&EXTD1, start + 3); \ - } \ - if (mis & (1 << 4)) { \ - EXTD1.config->channels[start + 4].cb(&EXTD1, start + 4); \ - } \ - if (mis & (1 << 5)) { \ - EXTD1.config->channels[start + 5].cb(&EXTD1, start + 5); \ - } \ - if (mis & (1 << 6)) { \ - EXTD1.config->channels[start + 6].cb(&EXTD1, start + 6); \ - } \ - if (mis & (1 << 7)) { \ - EXTD1.config->channels[start + 7].cb(&EXTD1, start + 7); \ - } \ - } while (0); - -/** - * @brief Generic interrupt serving code for single pin per interrupt - * handler. - */ -#define ext_lld_serve_pin_interrupt(gpiop, start, pin) \ - do { \ - gpiop->ICR = (1 << pin); \ - EXTD1.config->channels[start].cb(&EXTD1, start); \ - } while (0); - -/*===========================================================================*/ -/* Driver exported variables. */ -/*===========================================================================*/ - -/** - * @brief EXTD1 driver identifier. - */ -EXTDriver EXTD1; - -/*===========================================================================*/ -/* Driver local variables and types. */ -/*===========================================================================*/ - -const ioportid_t gpio_table[] = -{ -#if TIVA_HAS_GPIOA - GPIOA, -#endif -#if TIVA_HAS_GPIOB - GPIOB, -#endif -#if TIVA_HAS_GPIOC - GPIOC, -#endif -#if TIVA_HAS_GPIOD - GPIOD, -#endif -#if TIVA_HAS_GPIOE - GPIOE, -#endif -#if TIVA_HAS_GPIOF - GPIOF, -#endif -#if TIVA_HAS_GPIOG - GPIOG, -#endif -#if TIVA_HAS_GPIOH - GPIOH, -#endif -#if TIVA_HAS_GPIOJ - GPIOJ, -#endif -#if TIVA_HAS_GPIOK - GPIOK, -#endif -#if TIVA_HAS_GPIOL - GPIOL, -#endif -#if TIVA_HAS_GPIOM - GPIOM, -#endif -#if TIVA_HAS_GPION - GPION, -#endif -#if TIVA_HAS_GPIOP - GPIOP, -#endif -#if TIVA_HAS_GPIOQ - GPIOQ, -#endif -#if TIVA_HAS_GPIOR - GPIOR, -#endif -#if TIVA_HAS_GPIOS - GPIOS, -#endif -#if TIVA_HAS_GPIOT - GPIOT, -#endif -}; - -/*===========================================================================*/ -/* Driver local functions. */ -/*===========================================================================*/ - -/** - * @brief Enables GPIO IRQ sources. - * - * @notapi - */ -static void ext_lld_irq_enable(void) -{ -#if TIVA_HAS_GPIOA - nvicEnableVector(TIVA_GPIOA_NUMBER, TIVA_EXT_GPIOA_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOB - nvicEnableVector(TIVA_GPIOB_NUMBER, TIVA_EXT_GPIOB_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOC - nvicEnableVector(TIVA_GPIOC_NUMBER, TIVA_EXT_GPIOC_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOD - nvicEnableVector(TIVA_GPIOD_NUMBER, TIVA_EXT_GPIOD_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOE - nvicEnableVector(TIVA_GPIOE_NUMBER, TIVA_EXT_GPIOE_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOF - nvicEnableVector(TIVA_GPIOF_NUMBER, TIVA_EXT_GPIOF_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOG - nvicEnableVector(TIVA_GPIOG_NUMBER, TIVA_EXT_GPIOG_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOH - nvicEnableVector(TIVA_GPIOH_NUMBER, TIVA_EXT_GPIOH_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOJ - nvicEnableVector(TIVA_GPIOJ_NUMBER, TIVA_EXT_GPIOJ_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOK - nvicEnableVector(TIVA_GPIOK_NUMBER, TIVA_EXT_GPIOK_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOL - nvicEnableVector(TIVA_GPIOL_NUMBER, TIVA_EXT_GPIOL_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOM - nvicEnableVector(TIVA_GPIOM_NUMBER, TIVA_EXT_GPIOM_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPION - nvicEnableVector(TIVA_GPION_NUMBER, TIVA_EXT_GPION_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOP - nvicEnableVector(TIVA_GPIOP0_NUMBER, TIVA_EXT_GPIOP0_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOP1_NUMBER, TIVA_EXT_GPIOP1_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOP2_NUMBER, TIVA_EXT_GPIOP2_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOP3_NUMBER, TIVA_EXT_GPIOP3_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOP4_NUMBER, TIVA_EXT_GPIOP4_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOP5_NUMBER, TIVA_EXT_GPIOP5_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOP6_NUMBER, TIVA_EXT_GPIOP6_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOP7_NUMBER, TIVA_EXT_GPIOP7_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOQ - nvicEnableVector(TIVA_GPIOQ0_NUMBER, TIVA_EXT_GPIOQ0_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOQ1_NUMBER, TIVA_EXT_GPIOQ1_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOQ2_NUMBER, TIVA_EXT_GPIOQ2_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOQ3_NUMBER, TIVA_EXT_GPIOQ3_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOQ4_NUMBER, TIVA_EXT_GPIOQ4_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOQ5_NUMBER, TIVA_EXT_GPIOQ5_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOQ6_NUMBER, TIVA_EXT_GPIOQ6_IRQ_PRIORITY); - nvicEnableVector(TIVA_GPIOQ7_NUMBER, TIVA_EXT_GPIOQ7_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOR - nvicEnableVector(TIVA_GPIOR_NUMBER, TIVA_EXT_GPIOR_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOS - nvicEnableVector(TIVA_GPIOS_NUMBER, TIVA_EXT_GPIOS_IRQ_PRIORITY); -#endif -#if TIVA_HAS_GPIOT - nvicEnableVector(TIVA_GPIOT_NUMBER, TIVA_EXT_GPIOT_IRQ_PRIORITY); -#endif -} - -/** - * @brief Disables GPIO IRQ sources. - * - * @notapi - */ -static void ext_lld_irq_disable(void) -{ -#if TIVA_HAS_GPIOA - nvicDisableVector(TIVA_GPIOA_NUMBER); -#endif -#if TIVA_HAS_GPIOB - nvicDisableVector(TIVA_GPIOB_NUMBER); -#endif -#if TIVA_HAS_GPIOC - nvicDisableVector(TIVA_GPIOC_NUMBER); -#endif -#if TIVA_HAS_GPIOD - nvicDisableVector(TIVA_GPIOD_NUMBER); -#endif -#if TIVA_HAS_GPIOE - nvicDisableVector(TIVA_GPIOE_NUMBER); -#endif -#if TIVA_HAS_GPIOF - nvicDisableVector(TIVA_GPIOF_NUMBER); -#endif -#if TIVA_HAS_GPIOG - nvicDisableVector(TIVA_GPIOG_NUMBER); -#endif -#if TIVA_HAS_GPIOH - nvicDisableVector(TIVA_GPIOH_NUMBER); -#endif -#if TIVA_HAS_GPIOJ - nvicDisableVector(TIVA_GPIOJ_NUMBER); -#endif -#if TIVA_HAS_GPIOK - nvicDisableVector(TIVA_GPIOK_NUMBER); -#endif -#if TIVA_HAS_GPIOL - nvicDisableVector(TIVA_GPIOL_NUMBER); -#endif -#if TIVA_HAS_GPIOM - nvicDisableVector(TIVA_GPIOM_NUMBER); -#endif -#if TIVA_HAS_GPION - nvicDisableVector(TIVA_GPION_NUMBER); -#endif -#if TIVA_HAS_GPIOP - nvicDisableVector(TIVA_GPIOP0_NUMBER); - nvicDisableVector(TIVA_GPIOP1_NUMBER); - nvicDisableVector(TIVA_GPIOP2_NUMBER); - nvicDisableVector(TIVA_GPIOP3_NUMBER); - nvicDisableVector(TIVA_GPIOP4_NUMBER); - nvicDisableVector(TIVA_GPIOP5_NUMBER); - nvicDisableVector(TIVA_GPIOP6_NUMBER); - nvicDisableVector(TIVA_GPIOP7_NUMBER); -#endif -#if TIVA_HAS_GPIOQ - nvicDisableVector(TIVA_GPIOQ0_NUMBER); - nvicDisableVector(TIVA_GPIOQ1_NUMBER); - nvicDisableVector(TIVA_GPIOQ2_NUMBER); - nvicDisableVector(TIVA_GPIOQ3_NUMBER); - nvicDisableVector(TIVA_GPIOQ4_NUMBER); - nvicDisableVector(TIVA_GPIOQ5_NUMBER); - nvicDisableVector(TIVA_GPIOQ6_NUMBER); - nvicDisableVector(TIVA_GPIOQ7_NUMBER); -#endif -#if TIVA_HAS_GPIOR - nvicDisableVector(TIVA_GPIOR_NUMBER); -#endif -#if TIVA_HAS_GPIOS - nvicDisableVector(TIVA_GPIOS_NUMBER); -#endif -#if TIVA_HAS_GPIOT - nvicDisableVector(TIVA_GPIOT_NUMBER); -#endif -} - -/*===========================================================================*/ -/* Driver interrupt handlers. */ -/*===========================================================================*/ - -#if TIVA_HAS_GPIOA || defined(__DOXYGEN__) -/** - * @brief GPIOA interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOA_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(GPIOA, 0); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOB || defined(__DOXYGEN__) -/** - * @brief GPIOB interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOB_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(GPIOB, 8); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOC || defined(__DOXYGEN__) -/** - * @brief GPIOC interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOC_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(GPIOC, 16); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOD || defined(__DOXYGEN__) -/** - * @brief GPIOD interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOD_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(GPIOD, 24); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOE || defined(__DOXYGEN__) -/** - * @brief GPIOE interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOE_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(GPIOE, 32); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOF || defined(__DOXYGEN__) -/** - * @brief GPIOF interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOF_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(GPIOF, 40); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOG || defined(__DOXYGEN__) -/** - * @brief GPIOG interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOG_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOG, 48); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOH || defined(__DOXYGEN__) -/** - * @brief GPIOH interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOH_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOH, 56); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__) -/** - * @brief GPIOJ interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOJ_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOJ, 64); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOK || defined(__DOXYGEN__) -/** - * @brief GPIOK interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOK_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOK, 72); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOL || defined(__DOXYGEN__) -/** - * @brief GPIOL interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOL_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOL, 80); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOM || defined(__DOXYGEN__) -/** - * @brief GPIOM interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOM_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOM, 88); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPION || defined(__DOXYGEN__) -/** - * @brief GPION interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPION_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPION, 96); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOP || defined(__DOXYGEN__) -/** - * @brief GPIOP0 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP0_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 104, 0); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOP1 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP1_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 105, 1); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOP2 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP2_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 106, 2); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOP3 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP3_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 107, 3); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOP4 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP4_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 108, 4); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOP5 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP5_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 109, 5); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOP6 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP6_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 110, 6); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOP7 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOP7_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOP, 111, 7); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__) -/** - * @brief GPIOQ0 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ0_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 112, 0); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOQ1 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ1_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 113, 1); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOQ2 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ2_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 114, 2); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOQ3 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ3_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 115, 3); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOQ4 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ4_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 116, 4); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOQ5 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ5_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 117, 5); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOQ6 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ6_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 118, 6); - - OSAL_IRQ_EPILOGUE(); -} - -/** - * @brief GPIOQ7 interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOQ7_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_pin_interrupt(&GPIOQ, 119, 7); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOR || defined(__DOXYGEN__) -/** - * @brief GPIOR interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOR_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOR, 120); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOS || defined(__DOXYGEN__) -/** - * @brief GPIOS interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOS_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOS, 128); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -#if TIVA_HAS_GPIOT || defined(__DOXYGEN__) -/** - * @brief GPIOT interrupt handler. - * - * @isr - */ -OSAL_IRQ_HANDLER(TIVA_GPIOT_HANDLER) -{ - OSAL_IRQ_PROLOGUE(); - - ext_lld_serve_port_interrupt(&GPIOT, 132); - - OSAL_IRQ_EPILOGUE(); -} -#endif - -/*===========================================================================*/ -/* Driver exported functions. */ -/*===========================================================================*/ - -/** - * @brief Low level EXT driver initialization. - * - * @notapi - */ -void ext_lld_init(void) -{ - extObjectInit(&EXTD1); -} - -/** - * @brief Configures and activates the EXT peripheral. - * - * @param[in] extp pointer to the @p EXTDriver object - * - * @notapi - */ -void ext_lld_start(EXTDriver *extp) -{ - uint8_t i; - - if (extp->state == EXT_STOP) { - ext_lld_irq_enable(); - } - - /* Configuration of automatic channels.*/ - for (i = 0; i < EXT_MAX_CHANNELS; i++) { - if (extp->config->channels[i].mode & EXT_CH_MODE_AUTOSTART) { - ext_lld_channel_enable(extp, i); - } - else { - ext_lld_channel_disable(extp, i); - } - } -} - -/** - * @brief Deactivates the EXT peripheral. - * - * @param[in] extp pointer to the @p EXTDriver object - * - * @notapi - */ -void ext_lld_stop(EXTDriver *extp) -{ - if (extp->state == EXT_ACTIVE) { - ext_lld_irq_disable(); - } - -#if TIVA_HAS_GPIOA - HWREG(GPIOA + GPIO_O_IM) = 0; -#endif -#if TIVA_HAS_GPIOB - HWREG(GPIOB + GPIO_O_IM) = 0; -#endif -#if TIVA_HAS_GPIOC - HWREG(GPIOC + GPIO_O_IM) = 0; -#endif -#if TIVA_HAS_GPIOD - HWREG(GPIOD + GPIO_O_IM) = 0; -#endif -#if TIVA_HAS_GPIOE - HWREG(GPIOE + GPIO_O_IM) = 0; -#endif -#if TIVA_HAS_GPIOF - HWREG(GPIOF + GPIO_O_IM) = 0; -#endif -#if TIVA_HAS_GPIOG - HWREG(GPIOG + GPIO_O_IM) = 0; -#endif -#if TIVA_HAS_GPIOH - HWREG(GPIOH + GPIO_O_IM) = 0; -#endif -#if TIVA_HAS_GPIOJ - HWREG(GPIOJ + GPIO_O_IM) = 0; -#endif -#if TIVA_HAS_GPIOK - HWREG(GPIOK + GPIO_O_IM) = 0; -#endif -#if TIVA_HAS_GPIOL - HWREG(GPIOL + GPIO_O_IM) = 0; -#endif -#if TIVA_HAS_GPIOM - HWREG(GPIOM + GPIO_O_IM) = 0; -#endif -#if TIVA_HAS_GPION - HWREG(GPION + GPIO_O_IM) = 0; -#endif -#if TIVA_HAS_GPIOP - HWREG(GPIOP + GPIO_O_IM) = 0; -#endif -#if TIVA_HAS_GPIOQ - HWREG(GPIOQ + GPIO_O_IM) = 0; -#endif -#if TIVA_HAS_GPIOR - HWREG(GPIOR + GPIO_O_IM) = 0; -#endif -#if TIVA_HAS_GPIOS - HWREG(GPIOS + GPIO_O_IM) = 0; -#endif -#if TIVA_HAS_GPIOT - HWREG(GPIOT + GPIO_O_IM) = 0; -#endif -} - -/** - * @brief Enables an EXT channel. - * - * @param[in] extp pointer to the @p EXTDriver object - * @param[in] channel channel to be enabled - * - * @notapi - */ -void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel) -{ - uint32_t gpio; - uint8_t pin; - uint32_t im; - - pin = channel & 0x07; - gpio = gpio_table[channel >> 3]; - - /* Disable interrupts */ - im = HWREG(gpio + GPIO_O_IM); - HWREG(gpio + GPIO_O_IM) = 0; - - /* Configure pin to be edge-sensitive.*/ - HWREG(gpio + GPIO_O_IS) &= ~(1 << pin); - - /* Programming edge registers.*/ - if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) == - EXT_CH_MODE_BOTH_EDGES) { - HWREG(gpio + GPIO_O_IBE) |= (1 << pin); - } - else if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) == - EXT_CH_MODE_FALLING_EDGE) { - HWREG(gpio + GPIO_O_IBE) &= ~(1 << pin); - HWREG(gpio + GPIO_O_IEV) &= ~(1 << pin); - } - else if ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) == - EXT_CH_MODE_RISING_EDGE) { - HWREG(gpio + GPIO_O_IBE) &= ~(1 << pin); - HWREG(gpio + GPIO_O_IEV) |= (1 << pin); - } - - /* Programming interrupt and event registers.*/ - if ((extp->config->channels[channel].cb != NULL) && - ((extp->config->channels[channel].mode & EXT_CH_MODE_EDGES_MASK) != - EXT_CH_MODE_DISABLED)) { - im |= (1 << pin); - } - else { - im &= ~(1 << pin); - } - - /* Restore interrupts */ - HWREG(gpio + GPIO_O_IM) = im; -} - -/** - * @brief Disables an EXT channel. - * - * @param[in] extp pointer to the @p EXTDriver object - * @param[in] channel channel to be disabled - * - * @notapi - */ -void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel) -{ - (void)extp; - uint32_t gpio; - uint8_t pin; - - pin = channel & 0x07; - gpio = gpio_table[channel >> 3]; - - HWREG(gpio + GPIO_O_IM) &= ~(1 << pin); -} - -#endif /* HAL_USE_EXT */ - -/** @} */ diff --git a/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.h b/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.h deleted file mode 100644 index 731f455..0000000 --- a/os/hal/ports/TIVA/LLD/GPIO/hal_ext_lld.h +++ /dev/null @@ -1,523 +0,0 @@ -/* - Copyright (C) 2014..2017 Marco Veeneman - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/** - * @file GPIO/hal_ext_lld.h - * @brief Tiva EXT subsystem low level driver header. - * - * @addtogroup EXT - * @{ - */ - -#ifndef HAL_EXT_LLD_H -#define HAL_EXT_LLD_H - -#if HAL_USE_EXT || defined(__DOXYGEN__) - -/*===========================================================================*/ -/* Driver constants. */ -/*===========================================================================*/ - -/** - * @brief Number of EXT per port. - */ -#define EXT_MAX_CHANNELS TIVA_GPIO_PINS - -/*===========================================================================*/ -/* Driver pre-compile time settings. */ -/*===========================================================================*/ - -/** - * @name Configuration options - * @{ - */ -/** - * @brief GPIOA interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOA_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOA_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOB interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOB_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOB_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOC interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOC_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOC_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOD interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOD_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOD_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOE interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOE_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOE_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOF interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOF_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOF_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOG interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOG_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOG_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOH interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOH_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOH_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOJ interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOJ_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOJ_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOK interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOK_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOK_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOL interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOL_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOL_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOM interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOM_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOM_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPION interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPION_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPION_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP0 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP0_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP0_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP1 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP1_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP2 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP2_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP3 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP3_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP4 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP4_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP5 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP5_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP5_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP6 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP6_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP6_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOP7 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOP7_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOP7_IRQ_PRIORITY 3 -#endif -/** @} */ - -/** - * @brief GPIOQ0 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ0_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ0_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOQ1 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ1_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ1_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOQ2 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ2_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ2_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOQ3 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ3_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ3_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOQ4 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ4_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ4_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOQ5 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ5_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ5_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOQ6 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ6_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ6_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOQ7 interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOQ7_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOQ7_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOR interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOR_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOR_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOS interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOS_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOS_IRQ_PRIORITY 3 -#endif - -/** - * @brief GPIOT interrupt priority level setting. - */ -#if !defined(TIVA_EXT_GPIOT_IRQ_PRIORITY) || defined(__DOXYGEN__) -#define TIVA_EXT_GPIOT_IRQ_PRIORITY 3 -#endif -/** @} */ - -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ - -#if TIVA_HAS_GPIOA && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOA_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOA" -#endif - -#if TIVA_HAS_GPIOB && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOB_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOB" -#endif - -#if TIVA_HAS_GPIOC && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOC_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOC" -#endif - -#if TIVA_HAS_GPIOD && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOD_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOD" -#endif - -#if TIVA_HAS_GPIOE && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOE_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOE" -#endif - -#if TIVA_HAS_GPIOF && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOF_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOF" -#endif - -#if TIVA_HAS_GPIOG && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOG_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOG" -#endif - -#if TIVA_HAS_GPIOH && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOH_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOH" -#endif - -#if TIVA_HAS_GPIOJ && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOJ_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOJ" -#endif - -#if TIVA_HAS_GPIOK && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOK_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOK" -#endif - -#if TIVA_HAS_GPIOL && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOL_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOL" -#endif - -#if TIVA_HAS_GPIOM && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOM_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOM" -#endif - -#if TIVA_HAS_GPION && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPION_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPION" -#endif - -#if TIVA_HAS_GPIOP0 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP0_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP0" -#endif - -#if TIVA_HAS_GPIOP1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP1" -#endif - -#if TIVA_HAS_GPIOP2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP2" -#endif - -#if TIVA_HAS_GPIOP3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP3" -#endif - -#if TIVA_HAS_GPIOP4 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP4_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP4" -#endif - -#if TIVA_HAS_GPIOP5 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP5_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP5" -#endif - -#if TIVA_HAS_GPIOP6 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP6_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP6" -#endif - -#if TIVA_HAS_GPIOP7 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOP7_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOP7" -#endif - -#if TIVA_HAS_GPIOQ0 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ0_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ0" -#endif - -#if TIVA_HAS_GPIOQ1 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ1_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ1" -#endif - -#if TIVA_HAS_GPIOQ2 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ2_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ2" -#endif - -#if TIVA_HAS_GPIOQ3 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ3_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ3" -#endif - -#if TIVA_HAS_GPIOQ4 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ4_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ4" -#endif - -#if TIVA_HAS_GPIOQ5 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ5_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ5" -#endif - -#if TIVA_HAS_GPIOQ6 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ6_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ6" -#endif - -#if TIVA_HAS_GPIOQ7 && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOQ7_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOQ7" -#endif - -#if TIVA_HAS_GPIOR && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOR_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOR" -#endif - -#if TIVA_HAS_GPIOS && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOS_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOS" -#endif - -#if TIVA_HAS_GPIOT && \ - !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_EXT_GPIOT_IRQ_PRIORITY) -#error "Invalid IRQ priority assigned to GPIOT" -#endif - -/*===========================================================================*/ -/* Driver data structures and types. */ -/*===========================================================================*/ - -/** - * @brief EXT channel identifier. - */ -typedef uint32_t expchannel_t; - -/** - * @brief Type of an EXT generic notification callback. - * - * @param[in] extp pointer to the @p EXPDriver object triggering the - * callback - */ -typedef void (*extcallback_t)(EXTDriver *extp, expchannel_t channel); - -/** - * @brief Channel configuration structure. - */ -typedef struct { - /** - * @brief Channel mode. - */ - uint32_t mode; - /** - * @brief Channel callback. - */ - extcallback_t cb; -} EXTChannelConfig; - -/** - * @brief Driver configuration structure. - * @note It could be empty on some architectures. - */ -typedef struct { - /** - * @brief Channel configurations. - */ - EXTChannelConfig channels[EXT_MAX_CHANNELS]; - /* End of the mandatory fields.*/ -} EXTConfig; - -/** - * @brief Structure representing an EXT driver. - */ -struct EXTDriver { - /** - * @brief Driver state. - */ - extstate_t state; - /** - * @brief Current configuration data. - */ - const EXTConfig *config; - /* End of the mandatory fields.*/ -}; - -/*===========================================================================*/ -/* Driver macros. */ -/*===========================================================================*/ - -/*===========================================================================*/ -/* External declarations. */ -/*===========================================================================*/ - -#if !defined(__DOXYGEN__) -extern EXTDriver EXTD1; -#endif - -#ifdef __cplusplus -extern "C" { -#endif - void ext_lld_init(void); - void ext_lld_start(EXTDriver *extp); - void ext_lld_stop(EXTDriver *extp); - void ext_lld_channel_enable(EXTDriver *extp, expchannel_t channel); - void ext_lld_channel_disable(EXTDriver *extp, expchannel_t channel); -#ifdef __cplusplus -} -#endif - -#endif /* HAL_USE_EXT */ - -#endif /* HAL_EXT_LLD_H */ - -/** @} */ diff --git a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c index 41fb3cd..7a222e4 100644 --- a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c +++ b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.c @@ -32,196 +32,121 @@ #if TIVA_HAS_GPIOA || defined(__DOXYGEN__) #define GPIOA_BIT (1 << 0) -#if TIVA_GPIO_GPIOA_USE_AHB && defined(TM4C123x) -#define GPIOA_AHB_BIT (1 << 0) -#else -#define GPIOA_AHB_BIT 0 -#endif #else #define GPIOA_BIT 0 -#define GPIOA_AHB_BIT 0 #endif #if TIVA_HAS_GPIOB || defined(__DOXYGEN__) #define GPIOB_BIT (1 << 1) -#if TIVA_GPIO_GPIOB_USE_AHB && defined(TM4C123x) -#define GPIOB_AHB_BIT (1 << 1) -#else -#define GPIOB_AHB_BIT 0 -#endif #else #define GPIOB_BIT 0 -#define GPIOB_AHB_BIT 0 #endif #if TIVA_HAS_GPIOC || defined(__DOXYGEN__) #define GPIOC_BIT (1 << 2) -#if TIVA_GPIO_GPIOC_USE_AHB && defined(TM4C123x) -#define GPIOC_AHB_BIT (1 << 2) -#else -#define GPIOC_AHB_BIT 0 -#endif #else #define GPIOC_BIT 0 -#define GPIOC_AHB_BIT 0 #endif #if TIVA_HAS_GPIOD || defined(__DOXYGEN__) #define GPIOD_BIT (1 << 3) -#if TIVA_GPIO_GPIOD_USE_AHB && defined(TM4C123x) -#define GPIOD_AHB_BIT (1 << 3) -#else -#define GPIOD_AHB_BIT 0 -#endif #else #define GPIOD_BIT 0 -#define GPIOD_AHB_BIT 0 #endif #if TIVA_HAS_GPIOE || defined(__DOXYGEN__) #define GPIOE_BIT (1 << 4) -#if TIVA_GPIO_GPIOE_USE_AHB && defined(TM4C123x) -#define GPIOE_AHB_BIT (1 << 4) -#else -#define GPIOE_AHB_BIT 0 -#endif #else #define GPIOE_BIT 0 -#define GPIOE_AHB_BIT 0 #endif #if TIVA_HAS_GPIOF || defined(__DOXYGEN__) #define GPIOF_BIT (1 << 5) -#if TIVA_GPIO_GPIOF_USE_AHB && defined(TM4C123x) -#define GPIOF_AHB_BIT (1 << 5) -#else -#define GPIOF_AHB_BIT 0 -#endif #else #define GPIOF_BIT 0 -#define GPIOF_AHB_BIT 0 #endif #if TIVA_HAS_GPIOG || defined(__DOXYGEN__) #define GPIOG_BIT (1 << 6) -#if TIVA_GPIO_GPIOG_USE_AHB && defined(TM4C123x) -#define GPIOG_AHB_BIT (1 << 6) -#else -#define GPIOG_AHB_BIT 0 -#endif #else #define GPIOG_BIT 0 -#define GPIOG_AHB_BIT 0 #endif #if TIVA_HAS_GPIOH || defined(__DOXYGEN__) #define GPIOH_BIT (1 << 7) -#if TIVA_GPIO_GPIOH_USE_AHB && defined(TM4C123x) -#define GPIOH_AHB_BIT (1 << 7) -#else -#define GPIOH_AHB_BIT 0 -#endif #else #define GPIOH_BIT 0 -#define GPIOH_AHB_BIT 0 #endif #if TIVA_HAS_GPIOJ || defined(__DOXYGEN__) #define GPIOJ_BIT (1 << 8) -#if TIVA_GPIO_GPIOJ_USE_AHB && defined(TM4C123x) -#define GPIOJ_AHB_BIT (1 << 8) -#else -#define GPIOJ_AHB_BIT 0 -#endif #else #define GPIOJ_BIT 0 -#define GPIOJ_AHB_BIT 0 #endif #if TIVA_HAS_GPIOK || defined(__DOXYGEN__) #define GPIOK_BIT (1 << 9) -#define GPIOK_AHB_BIT (1 << 9) #else #define GPIOK_BIT 0 -#define GPIOK_AHB_BIT 0 #endif #if TIVA_HAS_GPIOL || defined(__DOXYGEN__) #define GPIOL_BIT (1 << 10) -#define GPIOL_AHB_BIT (1 << 10) #else #define GPIOL_BIT 0 -#define GPIOL_AHB_BIT 0 #endif #if TIVA_HAS_GPIOM || defined(__DOXYGEN__) #define GPIOM_BIT (1 << 11) -#define GPIOM_AHB_BIT (1 << 11) #else #define GPIOM_BIT 0 -#define GPIOM_AHB_BIT 0 #endif #if TIVA_HAS_GPION || defined(__DOXYGEN__) #define GPION_BIT (1 << 12) -#define GPION_AHB_BIT (1 << 12) #else #define GPION_BIT 0 -#define GPION_AHB_BIT 0 #endif #if TIVA_HAS_GPIOP || defined(__DOXYGEN__) #define GPIOP_BIT (1 << 13) -#define GPIOP_AHB_BIT (1 << 13) #else #define GPIOP_BIT 0 -#define GPIOP_AHB_BIT 0 #endif #if TIVA_HAS_GPIOQ || defined(__DOXYGEN__) #define GPIOQ_BIT (1 << 14) -#define GPIOQ_AHB_BIT (1 << 14) #else #define GPIOQ_BIT 0 -#define GPIOQ_AHB_BIT 0 #endif #if TIVA_HAS_GPIOR || defined(__DOXYGEN__) #define GPIOR_BIT (1 << 15) -#define GPIOR_AHB_BIT (1 << 15) #else #define GPIOR_BIT 0 -#define GPIOR_AHB_BIT 0 #endif #if TIVA_HAS_GPIOS || defined(__DOXYGEN__) #define GPIOS_BIT (1 << 16) -#define GPIOS_AHB_BIT (1 << 16) #else #define GPIOS_BIT 0 -#define GPIOS_AHB_BIT 0 #endif #if TIVA_HAS_GPIOT || defined(__DOXYGEN__) #define GPIOT_BIT (1 << 17) -#define GPIOT_AHB_BIT (1 << 17) #else #define GPIOT_BIT 0 -#define GPIOT_AHB_BIT 0 #endif #define RCGCGPIO_MASK (GPIOA_BIT | GPIOB_BIT | GPIOC_BIT | GPIOD_BIT | \ GPIOE_BIT | GPIOF_BIT | GPIOG_BIT | GPIOH_BIT | \ GPIOJ_BIT | GPIOK_BIT | GPIOL_BIT | GPIOM_BIT | \ GPION_BIT | GPIOP_BIT | GPIOQ_BIT | GPIOR_BIT | \ - GPIOS_BIT | GPIOR_BIT) + GPIOS_BIT | GPIOT_BIT) -#define GPIOHBCTL_MASK (GPIOA_AHB_BIT | GPIOB_AHB_BIT | GPIOC_AHB_BIT | \ - GPIOD_AHB_BIT | GPIOE_AHB_BIT | GPIOF_AHB_BIT | \ - GPIOG_AHB_BIT | GPIOH_AHB_BIT | GPIOJ_AHB_BIT | \ - GPIOK_AHB_BIT | GPIOL_AHB_BIT | GPIOM_AHB_BIT | \ - GPION_AHB_BIT | GPIOP_AHB_BIT | GPIOQ_AHB_BIT | \ - GPIOR_AHB_BIT | GPIOS_AHB_BIT | GPIOT_AHB_BIT) +#define GPIOHBCTL_MASK (GPIOA_BIT | GPIOB_BIT | GPIOC_BIT | GPIOD_BIT | \ + GPIOE_BIT | GPIOF_BIT | GPIOG_BIT | GPIOH_BIT | \ + GPIOJ_BIT) #define GPIOC_JTAG_MASK (0x0F) #define GPIOD_NMI_MASK (0x80) @@ -231,6 +156,11 @@ /* Driver exported variables. */ /*===========================================================================*/ +/** + * @brief Event records for all GPIO channels. + */ +palevent_t _pal_events[TIVA_GPIO_PINS]; + /*===========================================================================*/ /* Driver local variables and types. */ /*===========================================================================*/ @@ -276,10 +206,608 @@ static void gpio_unlock(ioportid_t port, ioportmask_t mask) HWREG(port + GPIO_O_CR) = mask; } +#if PAL_USE_CALLBACKS || PAL_USE_WAIT +/** + * @brief Enables GPIO IRQ sources. + */ +static void gpio_irq_enable(void) +{ +#if TIVA_HAS_GPIOA + nvicEnableVector(TIVA_GPIOA_NUMBER, TIVA_PAL_GPIOA_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOB + nvicEnableVector(TIVA_GPIOB_NUMBER, TIVA_PAL_GPIOB_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOC + nvicEnableVector(TIVA_GPIOC_NUMBER, TIVA_PAL_GPIOC_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOD + nvicEnableVector(TIVA_GPIOD_NUMBER, TIVA_PAL_GPIOD_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOE + nvicEnableVector(TIVA_GPIOE_NUMBER, TIVA_PAL_GPIOE_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOF + nvicEnableVector(TIVA_GPIOF_NUMBER, TIVA_PAL_GPIOF_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOG + nvicEnableVector(TIVA_GPIOG_NUMBER, TIVA_PAL_GPIOG_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOH + nvicEnableVector(TIVA_GPIOH_NUMBER, TIVA_PAL_GPIOH_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOJ + nvicEnableVector(TIVA_GPIOJ_NUMBER, TIVA_PAL_GPIOJ_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOK + nvicEnableVector(TIVA_GPIOK_NUMBER, TIVA_PAL_GPIOK_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOL + nvicEnableVector(TIVA_GPIOL_NUMBER, TIVA_PAL_GPIOL_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOM + nvicEnableVector(TIVA_GPIOM_NUMBER, TIVA_PAL_GPIOM_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPION + nvicEnableVector(TIVA_GPION_NUMBER, TIVA_PAL_GPION_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOP + nvicEnableVector(TIVA_GPIOP0_NUMBER, TIVA_PAL_GPIOP0_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP1_NUMBER, TIVA_PAL_GPIOP1_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP2_NUMBER, TIVA_PAL_GPIOP2_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP3_NUMBER, TIVA_PAL_GPIOP3_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP4_NUMBER, TIVA_PAL_GPIOP4_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP5_NUMBER, TIVA_PAL_GPIOP5_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP6_NUMBER, TIVA_PAL_GPIOP6_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOP7_NUMBER, TIVA_PAL_GPIOP7_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOQ + nvicEnableVector(TIVA_GPIOQ0_NUMBER, TIVA_PAL_GPIOQ0_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ1_NUMBER, TIVA_PAL_GPIOQ1_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ2_NUMBER, TIVA_PAL_GPIOQ2_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ3_NUMBER, TIVA_PAL_GPIOQ3_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ4_NUMBER, TIVA_PAL_GPIOQ4_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ5_NUMBER, TIVA_PAL_GPIOQ5_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ6_NUMBER, TIVA_PAL_GPIOQ6_IRQ_PRIORITY); + nvicEnableVector(TIVA_GPIOQ7_NUMBER, TIVA_PAL_GPIOQ7_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOR + nvicEnableVector(TIVA_GPIOR_NUMBER, TIVA_PAL_GPIOR_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOS + nvicEnableVector(TIVA_GPIOS_NUMBER, TIVA_PAL_GPIOS_IRQ_PRIORITY); +#endif +#if TIVA_HAS_GPIOT + nvicEnableVector(TIVA_GPIOT_NUMBER, TIVA_PAL_GPIOT_IRQ_PRIORITY); +#endif +} +#endif + +#define gpio_serve_irq(mask, pin, channel) { \ + \ + if ((mask) & (1U << (pin))) { \ + _pal_isr_code(channel); \ + } \ +} + +/** + * @brief Generic interrupt serving code for multiple pins per interrupt + * handler. + */ +#define ext_lld_serve_port_interrupt(gpio, start) \ + do { \ + uint32_t mis = HWREG(gpio + GPIO_O_MIS); \ + \ + HWREG(gpio + GPIO_O_ICR) = mis; \ + \ + gpio_serve_irq(mis, 0, start + 0); \ + gpio_serve_irq(mis, 1, start + 1); \ + gpio_serve_irq(mis, 2, start + 2); \ + gpio_serve_irq(mis, 3, start + 3); \ + gpio_serve_irq(mis, 4, start + 4); \ + gpio_serve_irq(mis, 5, start + 5); \ + gpio_serve_irq(mis, 6, start + 6); \ + gpio_serve_irq(mis, 7, start + 7); \ + } while (0); + +/** + * @brief Generic interrupt serving code for single pin per interrupt + * handler. + */ +#define ext_lld_serve_pin_interrupt(gpio, start, pin) \ + do { \ + HWREG(gpio + GPIO_O_ICR) = (1 << pin); \ + gpio_serve_irq((1 << pin), pin, start) \ + } while (0); + /*===========================================================================*/ /* Driver interrupt handlers. */ /*===========================================================================*/ +#if TIVA_HAS_GPIOA || defined(__DOXYGEN__) +/** + * @brief GPIOA interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOA_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOA, 0); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOB || defined(__DOXYGEN__) +/** + * @brief GPIOB interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOB_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOB, 8); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOC || defined(__DOXYGEN__) +/** + * @brief GPIOC interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOC_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOC, 16); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOD || defined(__DOXYGEN__) +/** + * @brief GPIOD interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOD_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOD, 24); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOE || defined(__DOXYGEN__) +/** + * @brief GPIOE interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOE_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOE, 32); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOF || defined(__DOXYGEN__) +/** + * @brief GPIOF interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOF_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOF, 40); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOG || defined(__DOXYGEN__) +/** + * @brief GPIOG interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOG_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOG, 48); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOH || defined(__DOXYGEN__) +/** + * @brief GPIOH interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOH_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOH, 56); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOJ || defined(__DOXYGEN__) +/** + * @brief GPIOJ interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOJ_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOJ, 64); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOK || defined(__DOXYGEN__) +/** + * @brief GPIOK interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOK_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOK, 72); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOL || defined(__DOXYGEN__) +/** + * @brief GPIOL interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOL_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOL, 80); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOM || defined(__DOXYGEN__) +/** + * @brief GPIOM interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOM_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOM, 88); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPION || defined(__DOXYGEN__) +/** + * @brief GPION interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPION_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPION, 96); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOP || defined(__DOXYGEN__) +/** + * @brief GPIOP0 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP0_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOP, 104, 0); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP1 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP1_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOP, 105, 1); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP2 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP2_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOP, 106, 2); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP3 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP3_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOP, 107, 3); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP4 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP4_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOP, 108, 4); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP5 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP5_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOP, 109, 5); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP6 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP6_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOP, 110, 6); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOP7 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOP7_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOP, 111, 7); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOQ || defined(__DOXYGEN__) +/** + * @brief GPIOQ0 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ0_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOQ, 112, 0); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ1 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ1_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOQ, 113, 1); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ2 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ2_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOQ, 114, 2); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ3 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ3_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOQ, 115, 3); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ4 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ4_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOQ, 116, 4); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ5 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ5_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOQ, 117, 5); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ6 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ6_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOQ, 118, 6); + + OSAL_IRQ_EPILOGUE(); +} + +/** + * @brief GPIOQ7 interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOQ7_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_pin_interrupt(GPIOQ, 119, 7); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOR || defined(__DOXYGEN__) +/** + * @brief GPIOR interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOR_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOR, 120); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOS || defined(__DOXYGEN__) +/** + * @brief GPIOS interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOS_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOS, 128); + + OSAL_IRQ_EPILOGUE(); +} +#endif + +#if TIVA_HAS_GPIOT || defined(__DOXYGEN__) +/** + * @brief GPIOT interrupt handler. + * + * @isr + */ +OSAL_IRQ_HANDLER(TIVA_GPIOT_HANDLER) +{ + OSAL_IRQ_PROLOGUE(); + + ext_lld_serve_port_interrupt(GPIOT, 132); + + OSAL_IRQ_EPILOGUE(); +} +#endif + /*===========================================================================*/ /* Driver exported functions. */ /*===========================================================================*/ @@ -294,6 +822,14 @@ static void gpio_unlock(ioportid_t port, ioportmask_t mask) */ void _pal_lld_init(const PALConfig *config) { +#if PAL_USE_CALLBACKS || PAL_USE_WAIT || defined(__DOXYGEN__) + unsigned i; + + for (i = 0; i < TIVA_GPIO_PINS; i++) { + _pal_init_event(i); + } +#endif + /* * Enables all GPIO clocks. */ @@ -366,6 +902,9 @@ void _pal_lld_init(const PALConfig *config) #if TIVA_HAS_GPIOT || defined(__DOXYGEN__) gpio_init(GPIOT, &config->PTData); #endif +#if PAL_USE_CALLBACKS || PAL_USE_WAIT + gpio_irq_enable(); +#endif } /** @@ -436,6 +975,159 @@ void _pal_lld_setgroupmode(ioportid_t port, ioportmask_t mask, iomode_t mode) } } +#if PAL_USE_CALLBACKS || PAL_USE_WAIT || defined(__DOXYGEN__) +/** + * @brief Pad event enable. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] mode pad event mode + * + * @notapi + */ +void _pal_lld_enablepadevent(ioportid_t port, + iopadid_t pad, + ioeventmode_t mode) +{ + //uint8_t portidx; + uint32_t padmask; + + //portidx = (((uint32_t)port - (uint32_t)GPIOA) >> 12) & 0x1FU; + padmask = (1 << pad); + + /* Disable interrupt before changing edge configuration.*/ + HWREG(port + GPIO_O_IM) &= ~padmask; + + /* Configure pin to be edge-sensitive.*/ + HWREG(port + GPIO_O_IS) &= ~(1 << pad); + + /* Configure edges */ + switch(mode & PAL_EVENT_MODE_EDGES_MASK) { + case PAL_EVENT_MODE_BOTH_EDGES: + HWREG(port + GPIO_O_IBE) |= padmask; + break; + case PAL_EVENT_MODE_RISING_EDGE: + HWREG(port + GPIO_O_IBE) &= ~padmask; + HWREG(port + GPIO_O_IEV) &= ~padmask; + break; + case PAL_EVENT_MODE_FALLING_EDGE: + HWREG(port + GPIO_O_IBE) &= ~padmask; + HWREG(port + GPIO_O_IEV) |= padmask; + break; + default: + /* Interrupt is already disabled */ + break; + } + + if (mode & PAL_EVENT_MODE_EDGES_MASK) { + /* Enable interrupt for this pad */ + HWREG(port + GPIO_O_IM) |= padmask; + } +} + +/** + * @brief Pad event disable. + * @details This function disables previously programmed event callbacks. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad) +{ + uint8_t portidx; + uint8_t eventidx; + + portidx = (((uint32_t)port - (uint32_t)GPIOA) >> 12) & 0x1FU; + + eventidx = portidx * 8 + pad; + + HWREG(port + GPIO_O_IM) &= ~(1 << pad); + +#if PAL_USE_CALLBACKS || PAL_USE_WAIT + /* Callback cleared and/or thread reset.*/ + _pal_clear_event(eventidx); +#endif +} + +/** + * @brief Disables GPIO IRQ sources. + */ +void pal_lld_disable_irqs(void) +{ +#if TIVA_HAS_GPIOA + nvicDisableVector(TIVA_GPIOA_NUMBER); +#endif +#if TIVA_HAS_GPIOB + nvicDisableVector(TIVA_GPIOB_NUMBER); +#endif +#if TIVA_HAS_GPIOC + nvicDisableVector(TIVA_GPIOC_NUMBER); +#endif +#if TIVA_HAS_GPIOD + nvicDisableVector(TIVA_GPIOD_NUMBER); +#endif +#if TIVA_HAS_GPIOE + nvicDisableVector(TIVA_GPIOE_NUMBER); +#endif +#if TIVA_HAS_GPIOF + nvicDisableVector(TIVA_GPIOF_NUMBER); +#endif +#if TIVA_HAS_GPIOG + nvicDisableVector(TIVA_GPIOG_NUMBER); +#endif +#if TIVA_HAS_GPIOH + nvicDisableVector(TIVA_GPIOH_NUMBER); +#endif +#if TIVA_HAS_GPIOJ + nvicDisableVector(TIVA_GPIOJ_NUMBER); +#endif +#if TIVA_HAS_GPIOK + nvicDisableVector(TIVA_GPIOK_NUMBER); +#endif +#if TIVA_HAS_GPIOL + nvicDisableVector(TIVA_GPIOL_NUMBER); +#endif +#if TIVA_HAS_GPIOM + nvicDisableVector(TIVA_GPIOM_NUMBER); +#endif +#if TIVA_HAS_GPION + nvicDisableVector(TIVA_GPION_NUMBER); +#endif +#if TIVA_HAS_GPIOP + nvicDisableVector(TIVA_GPIOP0_NUMBER); + nvicDisableVector(TIVA_GPIOP1_NUMBER); + nvicDisableVector(TIVA_GPIOP2_NUMBER); + nvicDisableVector(TIVA_GPIOP3_NUMBER); + nvicDisableVector(TIVA_GPIOP4_NUMBER); + nvicDisableVector(TIVA_GPIOP5_NUMBER); + nvicDisableVector(TIVA_GPIOP6_NUMBER); + nvicDisableVector(TIVA_GPIOP7_NUMBER); +#endif +#if TIVA_HAS_GPIOQ + nvicDisableVector(TIVA_GPIOQ0_NUMBER); + nvicDisableVector(TIVA_GPIOQ1_NUMBER); + nvicDisableVector(TIVA_GPIOQ2_NUMBER); + nvicDisableVector(TIVA_GPIOQ3_NUMBER); + nvicDisableVector(TIVA_GPIOQ4_NUMBER); + nvicDisableVector(TIVA_GPIOQ5_NUMBER); + nvicDisableVector(TIVA_GPIOQ6_NUMBER); + nvicDisableVector(TIVA_GPIOQ7_NUMBER); +#endif +#if TIVA_HAS_GPIOR + nvicDisableVector(TIVA_GPIOR_NUMBER); +#endif +#if TIVA_HAS_GPIOS + nvicDisableVector(TIVA_GPIOS_NUMBER); +#endif +#if TIVA_HAS_GPIOT + nvicDisableVector(TIVA_GPIOT_NUMBER); +#endif +} +#endif /* PAL_USE_CALLBACKS || PAL_USE_WAIT */ + #endif /* HAL_USE_PAL */ /** diff --git a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h index cf14bfb..e884a92 100644 --- a/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h +++ b/os/hal/ports/TIVA/LLD/GPIO/hal_pal_lld.h @@ -329,157 +329,267 @@ typedef uint32_t iomode_t; typedef uint32_t ioline_t; /** + * @brief Type of an event mode. + */ +typedef uint32_t ioeventmode_t; + +/** * @brief Port Identifier. */ typedef uint32_t ioportid_t; +/** + * @brief Type of an pad identifier. + */ +typedef uint32_t iopadid_t; + /*===========================================================================*/ /* Driver pre-compile time settings. */ /*===========================================================================*/ -#if defined(TM4C123x) +/** + * @name Configuration options + * @{ + */ +/** + * @brief GPIOA interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOA_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOA_IRQ_PRIORITY 3 +#endif /** - * @brief GPIOA AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOA. When set - * to @p FALSE the APB bus is used to access GPIOA. + * @brief GPIOB interrupt priority level setting. */ -#if !defined(TIVA_GPIO_GPIOA_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOA_USE_AHB TRUE +#if !defined(TIVA_PAL_GPIOB_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOB_IRQ_PRIORITY 3 #endif /** - * @brief GPIOB AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOB. When set - * to @p FALSE the APB bus is used to access GPIOB. + * @brief GPIOC interrupt priority level setting. */ -#if !defined(TIVA_GPIO_GPIOB_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOB_USE_AHB TRUE +#if !defined(TIVA_PAL_GPIOC_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOC_IRQ_PRIORITY 3 #endif /** - * @brief GPIOC AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOC. When set - * to @p FALSE the APB bus is used to access GPIOC. + * @brief GPIOD interrupt priority level setting. */ -#if !defined(TIVA_GPIO_GPIOC_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOC_USE_AHB TRUE +#if !defined(TIVA_PAL_GPIOD_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOD_IRQ_PRIORITY 3 #endif /** - * @brief GPIOD AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOD. When set - * to @p FALSE the APB bus is used to access GPIOD. + * @brief GPIOE interrupt priority level setting. */ -#if !defined(TIVA_GPIO_GPIOD_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOD_USE_AHB TRUE +#if !defined(TIVA_PAL_GPIOE_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOE_IRQ_PRIORITY 3 #endif /** - * @brief GPIOE AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOE. When set - * to @p FALSE the APB bus is used to access GPIOE. + * @brief GPIOF interrupt priority level setting. */ -#if !defined(TIVA_GPIO_GPIOE_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOE_USE_AHB TRUE +#if !defined(TIVA_PAL_GPIOF_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOF_IRQ_PRIORITY 3 #endif /** - * @brief GPIOF AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOF. When set - * to @p FALSE the APB bus is used to access GPIOF. + * @brief GPIOG interrupt priority level setting. */ -#if !defined(TIVA_GPIO_GPIOF_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOF_USE_AHB TRUE +#if !defined(TIVA_PAL_GPIOG_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOG_IRQ_PRIORITY 3 #endif /** - * @brief GPIOG AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOG. When set - * to @p FALSE the APB bus is used to access GPIOG. + * @brief GPIOH interrupt priority level setting. */ -#if !defined(TIVA_GPIO_GPIOG_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOG_USE_AHB TRUE +#if !defined(TIVA_PAL_GPIOH_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOH_IRQ_PRIORITY 3 #endif /** - * @brief GPIOH AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOH. When set - * to @p FALSE the APB bus is used to access GPIOH. + * @brief GPIOJ interrupt priority level setting. */ -#if !defined(TIVA_GPIO_GPIOH_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOH_USE_AHB TRUE +#if !defined(TIVA_PAL_GPIOJ_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOJ_IRQ_PRIORITY 3 #endif /** - * @brief GPIOJ AHB enable switch. - * @details When set to @p TRUE the AHB bus is used to access GPIOJ. When set - * to @p FALSE the APB bus is used to access GPIOJ. + * @brief GPIOK interrupt priority level setting. */ -#if !defined(TIVA_GPIO_GPIOJ_USE_AHB) || defined(__DOXYGEN__) -#define TIVA_GPIO_GPIOJ_USE_AHB TRUE +#if !defined(TIVA_PAL_GPIOK_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOK_IRQ_PRIORITY 3 #endif +/** + * @brief GPIOL interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOL_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOL_IRQ_PRIORITY 3 #endif -/*===========================================================================*/ -/* Derived constants and error checks. */ -/*===========================================================================*/ +/** + * @brief GPIOM interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOM_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOM_IRQ_PRIORITY 3 +#endif -#if TIVA_GPIO_GPIOA_USE_AHB && defined(TM4C123x) -#define GPIOA GPIO_PORTA_AHB_BASE -#else -#define GPIOA GPIO_PORTA_BASE +/** + * @brief GPION interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPION_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPION_IRQ_PRIORITY 3 #endif -#if TIVA_GPIO_GPIOB_USE_AHB && defined(TM4C123x) -#define GPIOB GPIO_PORTB_AHB_BASE -#else -#define GPIOB GPIO_PORTB_BASE +/** + * @brief GPIOP0 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOP0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOP0_IRQ_PRIORITY 3 #endif -#if TIVA_GPIO_GPIOC_USE_AHB && defined(TM4C123x) -#define GPIOC GPIO_PORTC_AHB_BASE -#else -#define GPIOC GPIO_PORTC_BASE +/** + * @brief GPIOP1 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOP1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOP1_IRQ_PRIORITY 3 #endif -#if TIVA_GPIO_GPIOD_USE_AHB && defined(TM4C123x) -#define GPIOD GPIO_PORTD_AHB_BASE -#else -#define GPIOD GPIO_PORTD_BASE +/** + * @brief GPIOP2 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOP2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOP2_IRQ_PRIORITY 3 #endif -#if TIVA_GPIO_GPIOE_USE_AHB && defined(TM4C123x) -#define GPIOE GPIO_PORTE_AHB_BASE -#else -#define GPIOE GPIO_PORTE_BASE +/** + * @brief GPIOP3 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOP3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOP3_IRQ_PRIORITY 3 #endif -#if TIVA_GPIO_GPIOF_USE_AHB && defined(TM4C123x) -#define GPIOF GPIO_PORTF_AHB_BASE -#else -#define GPIOF GPIO_PORTF_BASE +/** + * @brief GPIOP4 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOP4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOP4_IRQ_PRIORITY 3 #endif -#if TIVA_GPIO_GPIOG_USE_AHB && defined(TM4C123x) -#define GPIOG GPIO_PORTG_AHB_BASE -#else -#define GPIOG GPIO_PORTG_BASE +/** + * @brief GPIOP5 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOP5_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOP5_IRQ_PRIORITY 3 #endif -#if TIVA_GPIO_GPIOH_USE_AHB && defined(TM4C123x) -#define GPIOH GPIO_PORTH_AHB_BASE -#else -#define GPIOH GPIO_PORTH_BASE +/** + * @brief GPIOP6 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOP6_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOP6_IRQ_PRIORITY 3 #endif -#if TIVA_GPIO_GPIOJ_USE_AHB && defined(TM4C123x) -#define GPIOJ GPIO_PORTJ_AHB_BASE -#else -#define GPIOJ GPIO_PORTJ_BASE +/** + * @brief GPIOP7 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOP7_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOP7_IRQ_PRIORITY 3 #endif +/** @} */ +/** + * @brief GPIOQ0 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOQ0_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOQ0_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ1 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOQ1_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOQ1_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ2 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOQ2_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOQ2_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ3 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOQ3_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOQ3_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ4 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOQ4_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOQ4_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ5 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOQ5_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOQ5_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ6 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOQ6_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOQ6_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOQ7 interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOQ7_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOQ7_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOR interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOR_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOR_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOS interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOS_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOS_IRQ_PRIORITY 3 +#endif + +/** + * @brief GPIOT interrupt priority level setting. + */ +#if !defined(TIVA_PAL_GPIOT_IRQ_PRIORITY) || defined(__DOXYGEN__) +#define TIVA_PAL_GPIOT_IRQ_PRIORITY 3 +#endif +/** @} */ + +/*===========================================================================*/ +/* Derived constants and error checks. */ +/*===========================================================================*/ + +#define GPIOA GPIO_PORTA_AHB_BASE +#define GPIOB GPIO_PORTB_AHB_BASE +#define GPIOC GPIO_PORTC_AHB_BASE +#define GPIOD GPIO_PORTD_AHB_BASE +#define GPIOE GPIO_PORTE_AHB_BASE +#define GPIOF GPIO_PORTF_AHB_BASE +#define GPIOG GPIO_PORTG_AHB_BASE +#define GPIOH GPIO_PORTH_AHB_BASE +#define GPIOJ GPIO_PORTJ_AHB_BASE #define GPIOK GPIO_PORTK_BASE #define GPIOL GPIO_PORTL_BASE #define GPIOM GPIO_PORTM_BASE @@ -490,6 +600,166 @@ typedef uint32_t ioportid_t; #define GPIOS GPIO_PORTS_BASE #define GPIOT GPIO_PORTT_BASE +#if TIVA_HAS_GPIOA && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOA_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOA" +#endif + +#if TIVA_HAS_GPIOB && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOB_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOB" +#endif + +#if TIVA_HAS_GPIOC && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOC_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOC" +#endif + +#if TIVA_HAS_GPIOD && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOD_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOD" +#endif + +#if TIVA_HAS_GPIOE && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOE_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOE" +#endif + +#if TIVA_HAS_GPIOF && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOF_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOF" +#endif + +#if TIVA_HAS_GPIOG && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOG_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOG" +#endif + +#if TIVA_HAS_GPIOH && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOH_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOH" +#endif + +#if TIVA_HAS_GPIOJ && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOJ_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOJ" +#endif + +#if TIVA_HAS_GPIOK && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOK_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOK" +#endif + +#if TIVA_HAS_GPIOL && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOL_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOL" +#endif + +#if TIVA_HAS_GPIOM && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOM_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOM" +#endif + +#if TIVA_HAS_GPION && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPION_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPION" +#endif + +#if TIVA_HAS_GPIOP && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP0_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP0" +#endif + +#if TIVA_HAS_GPIOP && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP1" +#endif + +#if TIVA_HAS_GPIOP && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP2" +#endif + +#if TIVA_HAS_GPIOP && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP3" +#endif + +#if TIVA_HAS_GPIOP && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP4_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP4" +#endif + +#if TIVA_HAS_GPIOP && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP5_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP5" +#endif + +#if TIVA_HAS_GPIOP && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP6_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP6" +#endif + +#if TIVA_HAS_GPIOP && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOP7_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOP7" +#endif + +#if TIVA_HAS_GPIOQ && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ0_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ0" +#endif + +#if TIVA_HAS_GPIOQ && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ1_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ1" +#endif + +#if TIVA_HAS_GPIOQ && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ2_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ2" +#endif + +#if TIVA_HAS_GPIOQ && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ3_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ3" +#endif + +#if TIVA_HAS_GPIOQ && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ4_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ4" +#endif + +#if TIVA_HAS_GPIOQ && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ5_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ5" +#endif + +#if TIVA_HAS_GPIOQ && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ6_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ6" +#endif + +#if TIVA_HAS_GPIOQ && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOQ7_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOQ7" +#endif + +#if TIVA_HAS_GPIOR && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOR_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOR" +#endif + +#if TIVA_HAS_GPIOS && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOS_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOS" +#endif + +#if TIVA_HAS_GPIOT && \ + !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_PAL_GPIOT_IRQ_PRIORITY) +#error "Invalid IRQ priority assigned to GPIOT" +#endif + /*===========================================================================*/ /* I/O Ports Identifiers. */ /*===========================================================================*/ @@ -761,7 +1031,7 @@ typedef uint32_t ioportid_t; * @notapi */ #define pal_lld_writepad(port, pad, bit) \ - (HWREG((port) + (GPIO_O_DATA + ((1 << (pad)) << 2))) = (bit)) + (HWREG((port) + (GPIO_O_DATA + ((1 << (pad)) << 2))) = 1 << (bit)) /** * @brief Sets a pad logical state to @p PAL_HIGH. @@ -791,12 +1061,59 @@ typedef uint32_t ioportid_t; #define pal_lld_clearpad(port, pad) \ (HWREG((port) + (GPIO_O_DATA + ((1 << (pad)) << 2))) = 0) +/** + * @brief Pad event enable. + * @note Programming an unknown or unsupported mode is silently ignored. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * @param[in] mode pad event mode + * + * @notapi + */ +#define pal_lld_enablepadevent(port, pad, mode) \ + _pal_lld_enablepadevent(port, pad, mode) + +/** + * @brief Pad event disable. + * @details This function disables previously programmed event callbacks. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_disablepadevent(port, pad) \ + _pal_lld_disablepadevent(port, pad) + +/** + * @brief Returns a PAL event structure associated to a pad. + * + * @param[in] port port identifier + * @param[in] pad pad number within the port + * + * @notapi + */ +#define pal_lld_get_pad_event(port, pad) \ + &_pal_events[((((((uint32_t)port - (uint32_t)GPIOA) >> 12) & 0x1FU) * 8) + pad)]; + +/** + * @brief Returns a PAL event structure associated to a line. + * + * @param[in] line line identifier + * + * @notapi + */ +#define pal_lld_get_line_event(line) \ + &_pal_events[((((((uint32_t)PAL_PORT(line) - (uint32_t)GPIOA) >> 12) & 0x1FU) * 8) + PAL_PAD(line))] + /*===========================================================================*/ /* External declarations. */ /*===========================================================================*/ #if !defined(__DOXYGEN__) extern const PALConfig pal_default_config; +extern palevent_t _pal_events[TIVA_GPIO_PINS]; #endif #ifdef __cplusplus @@ -806,6 +1123,13 @@ extern "C" { void _pal_lld_setgroupmode(ioportid_t port, ioportmask_t mask, iomode_t mode); +#if PAL_USE_CALLBACKS || PAL_USE_WAIT + void _pal_lld_enablepadevent(ioportid_t port, + iopadid_t pad, + ioeventmode_t mode); + void _pal_lld_disablepadevent(ioportid_t port, iopadid_t pad); + void pal_lld_disable_irqs(void); +#endif #ifdef __cplusplus } #endif diff --git a/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c index baa7112..0f9576a 100644 --- a/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c +++ b/os/hal/ports/TIVA/LLD/GPTM/hal_st_lld.c @@ -37,32 +37,32 @@ #if TIVA_ST_TIMER_NUMBER == 0 #define ST_HANDLER TIVA_WGPT0A_HANDLER #define ST_NUMBER TIVA_WGPT0A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 0)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 0))) +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCWTIMER) |= (1 << 0)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 0))) #elif TIVA_ST_TIMER_NUMBER == 1 #define ST_HANDLER TIVA_WGPT1A_HANDLER #define ST_NUMBER TIVA_WGPT1A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 1)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 1))) +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCWTIMER) |= (1 << 1)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 1))) #elif TIVA_ST_TIMER_NUMBER == 2 #define ST_HANDLER TIVA_WGPT2A_HANDLER #define ST_NUMBER TIVA_WGPT2A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 2)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 2))) +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCWTIMER) |= (1 << 2)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 2))) #elif TIVA_ST_TIMER_NUMBER == 3 #define ST_HANDLER TIVA_WGPT3A_HANDLER #define ST_NUMBER TIVA_WGPT3A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 3)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 3))) +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCWTIMER) |= (1 << 3)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 3))) #elif TIVA_ST_TIMER_NUMBER == 4 #define ST_HANDLER TIVA_WGPT4A_HANDLER #define ST_NUMBER TIVA_WGPT4A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCWTIMER |= (1 << 4)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRWTIMER & (1 << 4))) +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCWTIMER) |= (1 << 4)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRWTIMER) & (1 << 4))) #elif TIVA_ST_TIMER_NUMBER == 5 #define ST_HANDLER TIVA_WGPT5A_HANDLER @@ -74,7 +74,7 @@ #error "TIVA_ST_USE_TIMER specifies an unsupported timer" #endif -#if (ST_CLOCK_SRC / OSAL_ST_FREQUENCY) - 1 > 0xFFFF +#if (TIVA_SYSCLK / OSAL_ST_FREQUENCY) - 1 > 0xFFFF #error "the selected ST frequency is not obtainable because TIM timer prescaler limits" #endif @@ -83,38 +83,38 @@ #if TIVA_ST_TIMER_NUMBER == 0 #define ST_HANDLER TIVA_GPT0A_HANDLER #define ST_NUMBER TIVA_GPT0A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 0)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 0))) +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCTIMER) |= (1 << 0)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRTIMER) & (1 << 0))) #elif TIVA_ST_TIMER_NUMBER == 1 #define ST_HANDLER TIVA_GPT1A_HANDLER #define ST_NUMBER TIVA_GPT1A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 1)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 1))) +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCTIMER) |= (1 << 1)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRTIMER) & (1 << 1))) #elif TIVA_ST_TIMER_NUMBER == 2 #define ST_HANDLER TIVA_GPT2A_HANDLER #define ST_NUMBER TIVA_GPT2A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 2)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 2))) +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCTIMER) |= (1 << 2)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRTIMER) & (1 << 2))) #elif TIVA_ST_TIMER_NUMBER == 3 #define ST_HANDLER TIVA_GPT3A_HANDLER #define ST_NUMBER TIVA_GPT3A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 3)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 3))) +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCTIMER) |= (1 << 3)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRTIMER) & (1 << 3))) #elif TIVA_ST_TIMER_NUMBER == 4 #define ST_HANDLER TIVA_GPT4A_HANDLER #define ST_NUMBER TIVA_GPT4A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 4)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 4))) +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCTIMER) |= (1 << 4)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRTIMER) & (1 << 4))) #elif TIVA_ST_TIMER_NUMBER == 5 #define ST_HANDLER TIVA_GPT5A_HANDLER #define ST_NUMBER TIVA_GPT5A_NUMBER -#define ST_ENABLE_CLOCK() (SYSCTL->RCGCTIMER |= (1 << 5)) -#define ST_WAIT_CLOCK() while (!(SYSCTL->PRTIMER & (1 << 5))) +#define ST_ENABLE_CLOCK() (HWREG(SYSCTL_RCGCTIMER) |= (1 << 5)) +#define ST_WAIT_CLOCK() while (!(HWREG(SYSCTL_PRTIMER) & (1 << 5))) #else #error "TIVA_ST_USE_TIMER specifies an unsupported timer" diff --git a/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c index fd7395f..7ba7bad 100644 --- a/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c +++ b/os/hal/ports/TIVA/LLD/I2C/hal_i2c_lld.c @@ -778,7 +778,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, /* Calculating the time window for the timeout on the busy bus condition.*/ start = osalOsGetSystemTimeX(); - end = start + OSAL_MS2ST(TIVA_I2C_BUSY_TIMEOUT); + end = start + OSAL_MS2I(TIVA_I2C_BUSY_TIMEOUT); /* Waits until BUSY flag is reset or, alternatively, for a timeout condition.*/ @@ -792,7 +792,7 @@ msg_t i2c_lld_master_receive_timeout(I2CDriver *i2cp, i2caddr_t addr, /* If the system time went outside the allowed window then a timeout condition is returned.*/ - if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), start, end)) + if (!osalTimeIsInRangeX(osalOsGetSystemTimeX(), start, end)) return MSG_TIMEOUT; osalSysUnlock(); @@ -852,7 +852,7 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, /* Calculating the time window for the timeout on the busy bus condition.*/ start = osalOsGetSystemTimeX(); - end = start + OSAL_MS2ST(TIVA_I2C_BUSY_TIMEOUT); + end = start + OSAL_MS2I(TIVA_I2C_BUSY_TIMEOUT); /* Waits until BUSY flag is reset or, alternatively, for a timeout condition.*/ @@ -866,7 +866,8 @@ msg_t i2c_lld_master_transmit_timeout(I2CDriver *i2cp, i2caddr_t addr, /* If the system time went outside the allowed window then a timeout condition is returned.*/ - if (!osalOsIsTimeWithinX(osalOsGetSystemTimeX(), start, end)) + if (!osalTimeIsInRangeX(osalOsGetSystemTimeX(), start, end)) + return MSG_TIMEOUT; osalSysUnlock(); diff --git a/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c index 126959f..2255110 100644 --- a/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c +++ b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.c @@ -258,7 +258,7 @@ void spi_lld_start(SPIDriver *spip) nvicEnableVector(TIVA_SSI1_NUMBER, TIVA_SPI_SSI1_IRQ_PRIORITY); } #endif -#if TIVASPI_USE_SSI2 +#if TIVA_SPI_USE_SSI2 if (&SPID2 == spip) { bool b; b = udmaChannelAllocate(spip->dmarxnr); diff --git a/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h index 4dcf6db..c93c189 100644 --- a/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h +++ b/os/hal/ports/TIVA/LLD/SSI/hal_spi_lld.h @@ -156,7 +156,7 @@ #error "Invalid IRQ priority assigned to SSI2" #endif -#if TM4C123x_SPI_USE_SSI3 && \ +#if TIVA_SPI_USE_SSI3 && \ !OSAL_IRQ_IS_VALID_PRIORITY(TIVA_SPI_SSI3_IRQ_PRIORITY) #error "Invalid IRQ priority assigned to SSI3" #endif diff --git a/os/hal/ports/TIVA/TM4C123x/hal_lld.h b/os/hal/ports/TIVA/TM4C123x/hal_lld.h index 5937b88..5d38a67 100644 --- a/os/hal/ports/TIVA/TM4C123x/hal_lld.h +++ b/os/hal/ports/TIVA/TM4C123x/hal_lld.h @@ -203,7 +203,7 @@ #error "Invalid value for TIVA_BYPASS_VALUE defined" #endif -#if (TIVA_OSCSRC == TIVA_RCC_OSCSRC_MOSC) && (TIVA_MOSC_ENABLE == FALSE) +#if (TIVA_OSCSRC == SYSCTL_RCC2_OSCSRC2_MO) && (TIVA_MOSC_ENABLE == FALSE) #error "Main Oscillator selected but not enabled" #endif diff --git a/os/hal/ports/TIVA/TM4C123x/platform.mk b/os/hal/ports/TIVA/TM4C123x/platform.mk index de482d0..8e447ec 100644 --- a/os/hal/ports/TIVA/TM4C123x/platform.mk +++ b/os/hal/ports/TIVA/TM4C123x/platform.mk @@ -7,7 +7,14 @@ PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \ ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C123x ifeq ($(USE_SMART_BUILD),yes) -HALCONF := $(strip $(shell cat halconf.h | egrep -e "\#define")) + +# Configuration files directory +ifeq ($(CONFDIR),) + CONFDIR = . +endif + +HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h | egrep -e "\#define")) +else endif # Drivers compatible with the platform. @@ -20,3 +27,7 @@ include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/SSI/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/uDMA/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/WDT/driver.mk + +# Shared variables +ALLCSRC += $(PLATFORMSRC) +ALLINC += $(PLATFORMINC) diff --git a/os/hal/ports/TIVA/TM4C129x/platform.mk b/os/hal/ports/TIVA/TM4C129x/platform.mk index 8e4c9fa..9702796 100644 --- a/os/hal/ports/TIVA/TM4C129x/platform.mk +++ b/os/hal/ports/TIVA/TM4C129x/platform.mk @@ -7,7 +7,14 @@ PLATFORMINC := $(CHIBIOS)/os/hal/ports/common/ARMCMx \ ${CHIBIOS_CONTRIB}/os/hal/ports/TIVA/TM4C129x ifeq ($(USE_SMART_BUILD),yes) -HALCONF := $(strip $(shell cat halconf.h | egrep -e "\#define")) + +# Configuration files directory +ifeq ($(CONFDIR),) + CONFDIR = . +endif + +HALCONF := $(strip $(shell cat $(CONFDIR)/halconf.h | egrep -e "\#define")) +else endif # Drivers compatible with the platform. @@ -21,3 +28,7 @@ include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/SSI/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/UART/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/uDMA/driver.mk include $(CHIBIOS_CONTRIB)/os/hal/ports/TIVA/LLD/WDT/driver.mk + +# Shared variables +ALLCSRC += $(PLATFORMSRC) +ALLINC += $(PLATFORMINC) diff --git a/os/hal/ports/TIVA/TM4C129x/tiva_registry.h b/os/hal/ports/TIVA/TM4C129x/tiva_registry.h index 163d59c..cd8344d 100644 --- a/os/hal/ports/TIVA/TM4C129x/tiva_registry.h +++ b/os/hal/ports/TIVA/TM4C129x/tiva_registry.h @@ -77,6 +77,7 @@ #define TIVA_HAS_GPIOR FALSE #define TIVA_HAS_GPIOS FALSE #define TIVA_HAS_GPIOT FALSE +#define TIVA_GPIO_PINS 120 #endif #if defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294NCZAD)\ || defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD) || defined(PART_TM4C1299NCZAD)\ @@ -100,6 +101,7 @@ #define TIVA_HAS_GPIOR TRUE #define TIVA_HAS_GPIOS TRUE #define TIVA_HAS_GPIOT TRUE +#define TIVA_GPIO_PINS 144 #endif /* EPI attributes.*/ diff --git a/os/hal/src/hal_ee24xx.c b/os/hal/src/hal_ee24xx.c index 632ffbb..725258c 100644 --- a/os/hal/src/hal_ee24xx.c +++ b/os/hal/src/hal_ee24xx.c @@ -105,7 +105,7 @@ static systime_t calc_timeout(I2CDriver *i2cp, size_t txbytes, size_t rxbytes) { tmo = ((txbytes + rxbytes + 1) * bitsinbyte * 1000); tmo /= EEPROM_I2C_CLOCK; tmo += 10; /* some additional milliseconds to be safer */ - return MS2ST(tmo); + return TIME_MS2I(tmo); } /** @@ -202,7 +202,7 @@ static void __fitted_write(void *ip, const uint8_t *data, size_t len, uint32_t * msg_t status = MSG_RESET; - osalDbgAssert(len != 0, "something broken in hi level part"); + osalDbgAssert(len > 0, "len must be greater than 0"); status = eeprom_write(((I2CEepromFileStream *)ip)->cfg, eepfs_getposition(ip), data, len); @@ -214,15 +214,15 @@ static void __fitted_write(void *ip, const uint8_t *data, size_t len, uint32_t * /** * @brief Write data to EEPROM. - * @details Only one EEPROM page can be written at once. So fucntion + * @details Only one EEPROM page can be written at once. So function * splits large data chunks in small EEPROM transactions if needed. - * @note To achieve the maximum effectivity use write operations + * @note To achieve the maximum efficiency use write operations * aligned to EEPROM page boundaries. */ static size_t write(void *ip, const uint8_t *bp, size_t n) { - size_t len = 0; /* bytes to be written at one trasaction */ - uint32_t written; /* total bytes successfully written */ + size_t len = 0; /* bytes to be written per transaction */ + uint32_t written = 0; /* total bytes successfully written */ uint16_t pagesize; uint32_t firstpage; uint32_t lastpage; @@ -242,12 +242,10 @@ static size_t write(void *ip, const uint8_t *bp, size_t n) { lastpage = (((EepromFileStream *)ip)->cfg->barrier_low + eepfs_getposition(ip) + n - 1) / pagesize; - written = 0; - /* data fitted in single page */ + /* data fits in single page */ if (firstpage == lastpage) { len = n; __fitted_write(ip, bp, len, &written); - bp += len; return written; } @@ -255,17 +253,19 @@ static size_t write(void *ip, const uint8_t *bp, size_t n) { /* write first piece of data to first page boundary */ len = ((firstpage + 1) * pagesize) - eepfs_getposition(ip); len -= ((EepromFileStream *)ip)->cfg->barrier_low; - __fitted_write(ip, bp, len, &written); + if (__fitted_write(ip, bp, len, &written) != MSG_OK) + return written; bp += len; - /* now writes blocks at a size of pages (may be no one) */ + /* now write page sized blocks (zero or more) */ while ((n - written) > pagesize) { len = pagesize; - __fitted_write(ip, bp, len, &written); + if (__fitted_write(ip, bp, len, &written) != MSG_OK) + return written; bp += len; } - /* wrtie tail */ + /* write tail */ len = n - written; if (len == 0) return written; diff --git a/os/hal/src/hal_ee25xx.c b/os/hal/src/hal_ee25xx.c index 102aef8..8c35976 100644 --- a/os/hal/src/hal_ee25xx.c +++ b/os/hal/src/hal_ee25xx.c @@ -277,7 +277,7 @@ static msg_t __fitted_write(void *ip, const uint8_t *data, size_t len, uint32_t msg_t status = MSG_RESET; - osalDbgAssert(len != 0, "something broken in hi level part"); + osalDbgAssert(len > 0, "len must be greater than 0"); status = ll_eeprom_write(((SPIEepromFileStream *)ip)->cfg, eepfs_getposition(ip), data, len); @@ -290,15 +290,15 @@ static msg_t __fitted_write(void *ip, const uint8_t *data, size_t len, uint32_t /** * @brief Write data to EEPROM. - * @details Only one EEPROM page can be written at once. So fucntion + * @details Only one EEPROM page can be written at once. So function * splits large data chunks in small EEPROM transactions if needed. - * @note To achieve the maximum effectivity use write operations + * @note To achieve the maximum efficiency use write operations * aligned to EEPROM page boundaries. */ static size_t write(void *ip, const uint8_t *bp, size_t n) { - size_t len = 0; /* bytes to be written at one trasaction */ - uint32_t written; /* total bytes successfully written */ + size_t len = 0; /* bytes to be written per transaction */ + uint32_t written = 0; /* total bytes successfully written */ uint16_t pagesize; uint32_t firstpage; uint32_t lastpage; @@ -318,32 +318,30 @@ static size_t write(void *ip, const uint8_t *bp, size_t n) { firstpage = (cfg->barrier_low + eepfs_getposition(ip)) / pagesize; lastpage = ((cfg->barrier_low + eepfs_getposition(ip) + n) - 1) / pagesize; - written = 0; - /* data fitted in single page */ + /* data fits in single page */ if (firstpage == lastpage) { len = n; __fitted_write(ip, bp, len, &written); - bp += len; return written; } + else { /* write first piece of data to first page boundary */ len = ((firstpage + 1) * pagesize) - eepfs_getposition(ip); len -= cfg->barrier_low; - __fitted_write(ip, bp, len, &written); + if (__fitted_write(ip, bp, len, &written) != MSG_OK) + return written; bp += len; - /* now writes blocks at a size of pages (may be no one) */ + /* now write page sized blocks (zero or more) */ while ((n - written) > pagesize) { len = pagesize; - if (__fitted_write(ip, bp, len, &written) != MSG_OK) // Fixed: Would increase bp forever and crash in case of timeouts... + if (__fitted_write(ip, bp, len, &written) != MSG_OK) return written; - bp += len; } - - /* wrtie tail */ + /* write tail */ len = n - written; if (len == 0) return written; diff --git a/os/hal/src/usbh/hal_usbh_aoa.c b/os/hal/src/usbh/hal_usbh_aoa.c index 85c3130..d565595 100644 --- a/os/hal/src/usbh/hal_usbh_aoa.c +++ b/os/hal/src/usbh/hal_usbh_aoa.c @@ -533,7 +533,7 @@ static void _vt(void *p) { if ((aoacp->iq_counter == 0) && !usbhURBIsBusy(&aoacp->iq_urb)) { _submitInI(aoacp); } - chVTSetI(&aoacp->vt, MS2ST(16), _vt, aoacp); + chVTSetI(&aoacp->vt, OSAL_MS2I(16), _vt, aoacp); osalSysUnlockFromISR(); } @@ -565,7 +565,7 @@ void usbhaoaChannelStart(USBHAOADriver *aoap) { usbhURBSubmit(&aoacp->iq_urb); chVTObjectInit(&aoacp->vt); - chVTSet(&aoacp->vt, MS2ST(16), _vt, aoacp); + chVTSet(&aoacp->vt, OSAL_MS2I(16), _vt, aoacp); aoacp->state = USBHAOA_CHANNEL_STATE_READY; diff --git a/os/hal/src/usbh/hal_usbh_ftdi.c b/os/hal/src/usbh/hal_usbh_ftdi.c index 6fb556d..6966028 100644 --- a/os/hal/src/usbh/hal_usbh_ftdi.c +++ b/os/hal/src/usbh/hal_usbh_ftdi.c @@ -332,7 +332,7 @@ static usbh_urbstatus_t _ftdi_port_control(USBHFTDIPortDriver *ftdipp, wLength }; - return usbhControlRequestExtended(ftdipp->ftdip->dev, &req, buff, NULL, MS2ST(1000)); + return usbhControlRequestExtended(ftdipp->ftdip->dev, &req, buff, NULL, OSAL_MS2I(1000)); } static uint32_t _get_divisor(uint32_t baud, usbhftdi_type_t type) { @@ -394,7 +394,7 @@ static usbh_urbstatus_t _set_baudrate(USBHFTDIPortDriver *ftdipp, uint32_t baudr wIndex, 0 }; - return usbhControlRequestExtended(ftdipp->ftdip->dev, &req, NULL, NULL, MS2ST(1000)); + return usbhControlRequestExtended(ftdipp->ftdip->dev, &req, NULL, NULL, OSAL_MS2I(1000)); } @@ -610,7 +610,7 @@ static void _vt(void *p) { if ((ftdipp->iq_counter == 0) && !usbhURBIsBusy(&ftdipp->iq_urb)) { _submitInI(ftdipp); } - chVTSetI(&ftdipp->vt, MS2ST(16), _vt, ftdipp); + chVTSetI(&ftdipp->vt, OSAL_MS2I(16), _vt, ftdipp); osalSysUnlockFromISR(); } @@ -690,7 +690,7 @@ void usbhftdipStart(USBHFTDIPortDriver *ftdipp, const USBHFTDIPortConfig *config usbhURBSubmit(&ftdipp->iq_urb); chVTObjectInit(&ftdipp->vt); - chVTSet(&ftdipp->vt, MS2ST(16), _vt, ftdipp); + chVTSet(&ftdipp->vt, OSAL_MS2I(16), _vt, ftdipp); ftdipp->state = USBHFTDIP_STATE_READY; osalMutexUnlock(&ftdipp->ftdip->mtx); diff --git a/os/hal/src/usbh/hal_usbh_msd.c b/os/hal/src/usbh/hal_usbh_msd.c index 069c47b..7233a0b 100644 --- a/os/hal/src/usbh/hal_usbh_msd.c +++ b/os/hal/src/usbh/hal_usbh_msd.c @@ -304,7 +304,7 @@ static msd_bot_result_t _msd_bot_transaction(msd_transaction_t *tran, USBHMassSt /* control phase */ status = usbhBulkTransfer(&lunp->msdp->epout, tran->cbw, - sizeof(*tran->cbw), &actual_len, MS2ST(1000)); + sizeof(*tran->cbw), &actual_len, OSAL_MS2I(1000)); if (status == USBH_URBSTATUS_CANCELLED) { uerr("\tMSD: Control phase: USBH_URBSTATUS_CANCELLED"); @@ -327,7 +327,7 @@ static msd_bot_result_t _msd_bot_transaction(msd_transaction_t *tran, USBHMassSt ep, data, tran->cbw->dCBWDataTransferLength, - &data_actual_len, MS2ST(20000)); + &data_actual_len, OSAL_MS2I(20000)); if (status == USBH_URBSTATUS_CANCELLED) { uerr("\tMSD: Data phase: USBH_URBSTATUS_CANCELLED"); @@ -349,7 +349,7 @@ static msd_bot_result_t _msd_bot_transaction(msd_transaction_t *tran, USBHMassSt /* status phase */ status = usbhBulkTransfer(&lunp->msdp->epin, &csw, - sizeof(csw), &actual_len, MS2ST(1000)); + sizeof(csw), &actual_len, OSAL_MS2I(1000)); if (status == USBH_URBSTATUS_STALL) { uwarn("\tMSD: Status phase: USBH_URBSTATUS_STALL, clear halt and retry"); @@ -358,7 +358,7 @@ static msd_bot_result_t _msd_bot_transaction(msd_transaction_t *tran, USBHMassSt if (status == USBH_URBSTATUS_OK) { status = usbhBulkTransfer(&lunp->msdp->epin, &csw, - sizeof(csw), &actual_len, MS2ST(1000)); + sizeof(csw), &actual_len, OSAL_MS2I(1000)); } } diff --git a/os/various/fatfs_bindings/fatfs.mk b/os/various/fatfs_bindings/fatfs.mk index 238037e..f2feeb5 100644 --- a/os/various/fatfs_bindings/fatfs.mk +++ b/os/various/fatfs_bindings/fatfs.mk @@ -2,6 +2,6 @@ FATFSSRC = ${CHIBIOS_CONTRIB}/os/various/fatfs_bindings/fatfs_diskio.c \ ${CHIBIOS}/os/various/fatfs_bindings/fatfs_syscall.c \ ${CHIBIOS}/ext/fatfs/src/ff.c \ - ${CHIBIOS}/ext/fatfs/src/option/unicode.c + $(CHIBIOS)/ext/fatfs/src/ffunicode.c FATFSINC = ${CHIBIOS}/ext/fatfs/src diff --git a/os/various/fatfs_bindings/fatfs_diskio.c b/os/various/fatfs_bindings/fatfs_diskio.c index 9fa41e2..80d1502 100644 --- a/os/various/fatfs_bindings/fatfs_diskio.c +++ b/os/various/fatfs_bindings/fatfs_diskio.c @@ -89,7 +89,7 @@ DSTATUS disk_initialize ( /* Return Disk Status */ DSTATUS disk_status ( - BYTE pdrv /* Physical drive nmuber (0..) */ + BYTE pdrv /* Physical drive number (0..) */ ) { DSTATUS stat; @@ -132,9 +132,9 @@ DSTATUS disk_status ( /* Read Sector(s) */ DRESULT disk_read ( - BYTE pdrv, /* Physical drive nmuber (0..) */ - BYTE *buff, /* Data buffer to store read data */ - DWORD sector, /* Sector address (LBA) */ + BYTE pdrv, /* Physical drive number (0..) */ + BYTE *buff, /* Data buffer to store read data */ + DWORD sector, /* Sector address (LBA) */ UINT count /* Number of sectors to read (1..255) */ ) { @@ -181,10 +181,10 @@ DRESULT disk_read ( /* Write Sector(s) */ DRESULT disk_write ( - BYTE pdrv, /* Physical drive nmuber (0..) */ - const BYTE *buff, /* Data to be written */ - DWORD sector, /* Sector address (LBA) */ - UINT count /* Number of sectors to write (1..255) */ + BYTE pdrv, /* Physical drive number (0..) */ + const BYTE *buff, /* Data to be written */ + DWORD sector, /* Sector address (LBA) */ + UINT count /* Number of sectors to write (1..255) */ ) { switch (pdrv) { @@ -232,8 +232,8 @@ DRESULT disk_write ( /* Miscellaneous Functions */ DRESULT disk_ioctl ( - BYTE pdrv, /* Physical drive nmuber (0..) */ - BYTE cmd, /* Control code */ + BYTE pdrv, /* Physical drive number (0..) */ + BYTE cmd, /* Control code */ void *buff /* Buffer to send/receive control data */ ) { diff --git a/os/various/lib_scsi.c b/os/various/lib_scsi.c index ea2adda..720a90f 100644 --- a/os/various/lib_scsi.c +++ b/os/various/lib_scsi.c @@ -364,7 +364,8 @@ static bool data_read_write10(SCSITarget *scsip, const uint8_t *cmd) { size_t bs = bdi.blk_size; uint8_t *buf = scsip->config->blkbuf; - for (size_t i=0; i<req.blk_cnt; i++) { + size_t i = 0; + for (i=0; i<req.blk_cnt; i++) { if (cmd[0] == SCSI_CMD_READ_10) { // TODO: block error handling blkRead(blkdev, req.first_lba + i, buf, 1); diff --git a/os/various/pid.c b/os/various/pid.c new file mode 100644 index 0000000..fee9608 --- /dev/null +++ b/os/various/pid.c @@ -0,0 +1,194 @@ +/********************************************************************************************** +* Arduino PID Library - Version 1.2.1 +* by Brett Beauregard <br3ttb@gmail.com> brettbeauregard.com +* Modified by Fabien Poussin <fabien.poussin@gmail.com> for ChibiOS. +* +* This Library is licensed under the MIT License +**********************************************************************************************/ + +#include "pid.h" +#include "osal.h" + +#define TIME_MS ((osalOsGetSystemTimeX() * 1000) / OSAL_ST_FREQUENCY ) + +/*Constructor (...)********************************************************* +* The parameters specified here are those for for which we can't set up +* reliable defaults, so we need to have the user set them. +***************************************************************************/ +void pid_create(pidc_t* p, float* Input, float* Output, float* Setpoint, + float Kp, float Ki, float Kd, int POn, int Direction) +{ + p->output = Output; + p->input = Input; + p->setPoint = Setpoint; + p->inAuto = false; + + pid_setOutputLimits(p, 0, 4095); // default output limit corresponds to + // the 12 bit dac limit + + p->sampleTime = 100; // default Controller Sample Time is 100ms + + pid_setDirection(p, Direction); + pid_setTunings(p, Kp, Ki, Kd, POn); + pid_initialize(p); + + p->lastTime = TIME_MS - p->sampleTime; +} + + +/* Compute() ********************************************************************** +* This, as they say, is where the magic happens. this function should be called +* every time "void loop()" executes. the function will decide for itself whether a new +* pid Output needs to be computed. returns true when the output is computed, +* false when nothing has been done. +**********************************************************************************/ +bool pid_compute(pidc_t* p) +{ + if(!p->inAuto) return false; + unsigned long now = TIME_MS; + unsigned long timeChange = (now - p->lastTime); + if(timeChange >= p->sampleTime) + { + /* Compute all the working error variables */ + float input = *p->input; + float error = *p->setPoint - input; + float dInput = (input - p->lastInput); + p->outputSum += (p->ki * error); + + /* Add Proportional on Measurement, if PID_ON_M is specified */ + if(!p->pOnE) p->outputSum -= p->kp * dInput; + + if(p->outputSum > p->outMax) p->outputSum = p->outMax; + else if(p->outputSum < p->outMin) p->outputSum = p->outMin; + + /* Add Proportional on Error, if P_ON_E is specified */ + float output; + if(p->pOnE) output = p->kp * error; + else output = 0; + + /* Compute Rest of PID Output */ + output += p->outputSum - p->kd * dInput; + + if(output > p->outMax) output = p->outMax; + else if(output < p->outMin) output = p->outMin; + *p->output = output; + + /* Remember some variables for next time */ + p->lastInput = input; + p->lastTime = now; + return true; + } + else return false; +} + +/* SetTunings(...)************************************************************* +* This function allows the controller's dynamic performance to be adjusted. +* it's called automatically from the constructor, but tunings can also +* be adjusted on the fly during normal operation +******************************************************************************/ +void pid_setTunings(pidc_t* p, float Kp, float Ki, float Kd, int POn) +{ + if (Kp < 0 || Ki < 0 || Kd < 0) return; + + p->pOn = POn; + p->pOnE = POn == PID_ON_E; + + p->dispKp = Kp; + p->dispKi = Ki; + p->dispKd = Kd; + + float SampleTimeInSec = ((float)p->sampleTime) / 1000.0; + p->kp = Kp; + p->ki = Ki * SampleTimeInSec; + p->kd = Kd / SampleTimeInSec; + + if(p->direction == PID_REVERSE) + { + p->kp = (0 - p->kp); + p->ki = (0 - p->ki); + p->kd = (0 - p->kd); + } +} + +/* SetSampleTime(...) ********************************************************* +* sets the period, in Milliseconds, at which the calculation is performed +******************************************************************************/ +void pid_setSampleTime(pidc_t* p, int NewSampleTime) +{ + if (NewSampleTime > 0) + { + float ratio = (float)NewSampleTime / (float)p->sampleTime; + p->ki *= ratio; + p->kd /= ratio; + p->sampleTime = (unsigned long)NewSampleTime; + } +} + +/* SetOutputLimits(...)**************************************************** +* This function will be used far more often than SetInputLimits. while +* the input to the controller will generally be in the 0-1023 range (which is +* the default already,) the output will be a little different. maybe they'll +* be doing a time window and will need 0-8000 or something. or maybe they'll +* want to clamp it from 0-125. who knows. at any rate, that can all be done +* here. +**************************************************************************/ +void pid_setOutputLimits(pidc_t* p, float Min, float Max) +{ + if(Min >= Max) return; + p->outMin = Min; + p->outMax = Max; + + if(p->inAuto) + { + if(*p->output > p->outMax) *p->output = p->outMax; + else if(*p->output < p->outMin) *p->output = p->outMin; + + if(p->outputSum > p->outMax) p->outputSum = p->outMax; + else if(p->outputSum < p->outMin) p->outputSum = p->outMin; + } +} + +/* SetMode(...)**************************************************************** +* Allows the controller Mode to be set to manual (0) or Automatic (non-zero) +* when the transition from manual to auto occurs, the controller is +* automatically initialized +******************************************************************************/ +void pid_setMode(pidc_t* p, int Mode) +{ + bool newAuto = (Mode == PID_AUTOMATIC); + if(newAuto && !p->inAuto) + { /* we just went from manual to auto */ + pid_initialize(p); + } + p->inAuto = newAuto; +} + +/* Initialize()**************************************************************** +* does all the things that need to happen to ensure a bumpless transfer +* from manual to automatic mode. +******************************************************************************/ +void pid_initialize(pidc_t* p) +{ + p->outputSum = *p->output; + p->lastInput = *p->input; + if(p->outputSum > p->outMax) p->outputSum = p->outMax; + else if(p->outputSum < p->outMin) p->outputSum = p->outMin; +} + +/* SetControllerDirection(...)************************************************* +* The PID will either be connected to a DIRECT acting process (+Output leads +* to +Input) or a REVERSE acting process(+Output leads to -Input.) we need to +* know which one, because otherwise we may increase the output when we should +* be decreasing. This is called from the constructor. +******************************************************************************/ +void pid_setDirection(pidc_t* p, int Direction) +{ + if(p->inAuto && Direction != p->direction) + { + p->kp = (0 - p->kp); + p->ki = (0 - p->ki); + p->kd = (0 - p->kd); + } + p->direction = Direction; +} + diff --git a/os/various/pid.h b/os/various/pid.h new file mode 100644 index 0000000..49ccd6f --- /dev/null +++ b/os/various/pid.h @@ -0,0 +1,78 @@ +#ifndef PID_h +#define PID_h + +#include "chtypes.h" + +//Constants used in some of the functions below +#define PID_AUTOMATIC 1 +#define PID_MANUAL 0 +#define PID_DIRECT 0 +#define PID_REVERSE 1 +#define PID_ON_M 0 +#define PID_ON_E 1 + + +typedef struct { + + float kp; // * (P)roportional Tuning Parameter + float ki; // * (I)ntegral Tuning Parameter + float kd; // * (D)erivative Tuning Parameter + + float dispKp; // * we'll hold on to the tuning parameters in user-entered + float dispKi; // format for display purposes + float dispKd; // + + int direction; + int pOn; + + float *input; // * Pointers to the Input, Output, and Setpoint variables + float *output; // This creates a hard link between the variables and the + float *setPoint; // PID, freeing the user from having to constantly tell us + // what these values are. with pointers we'll just know. + unsigned long lastTime; + float outputSum; + float lastInput; + + unsigned long sampleTime; + float outMin; + float outMax; + + bool inAuto; + bool pOnE; + +} pidc_t; + + +//commonly used functions ************************************************************************** +void pid_create(pidc_t* p, float* Input, float* Output, float* Setpoint, // * constructor. links the PID to the Input, Output, and + float Kp, float Ki, float Kd, int POn, int Direction); // Setpoint. Initial tuning parameters are also set here. + // (overload for specifying proportional mode) + +void pid_setMode(pidc_t* p, int mode); // * sets PID to either Manual (0) or Auto (non-0) + +bool pid_compute(pidc_t* p); // * performs the PID calculation. it should be + // called every time loop() cycles. ON/OFF and + // calculation frequency can be set using SetMode + // SetsampleTime respectively + +void pid_setOutputLimits(pidc_t* p, float Min, float Max); // * clamps the output to a specific range. 0-255 by default, but + // it's likely the user will want to change this depending on + // the application + + + +//available but not commonly used functions ******************************************************** +void pid_setTunings(pidc_t* p, float Kp, float Ki, float Kd, int POn); // * While most users will set the tunings once in the + // constructor, this function gives the user the option + // of changing tunings during runtime for Adaptive control + +void pid_setDirection(pidc_t* p, int Direction); // * Sets the Direction, or "Action" of the controller. DIRECT + // means the output will increase when error is positive. REVERSE + // means the opposite. it's very unlikely that this will be needed + // once it is set in the constructor. +void pid_setSampleTime(pidc_t* p, int NewSampleTime); // * sets the frequency, in Milliseconds, with which + // the PID calculation is performed. default is 100 + +void pid_initialize(pidc_t* p); + +#endif |