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-rw-r--r--os/common/ext/CMSIS/KINETIS/k20xx.h2
-rw-r--r--os/common/ext/MSP430/inc/in430.h343
-rw-r--r--os/common/ext/MSP430/inc/iomacros.h85
-rwxr-xr-xos/common/ext/MSP430/inc/msp430.h1847
-rwxr-xr-xos/common/ext/MSP430/inc/msp430fr5969.h4509
-rw-r--r--os/common/ext/MSP430/inc/msp430fr6989.h6315
-rw-r--r--os/common/ext/TivaWare/inc/asmdefs.h227
-rw-r--r--os/common/ext/TivaWare/inc/hw_adc.h1306
-rw-r--r--os/common/ext/TivaWare/inc/hw_aes.h545
-rw-r--r--os/common/ext/TivaWare/inc/hw_can.h462
-rw-r--r--os/common/ext/TivaWare/inc/hw_ccm.h115
-rw-r--r--os/common/ext/TivaWare/inc/hw_comp.h211
-rw-r--r--os/common/ext/TivaWare/inc/hw_des.h310
-rw-r--r--os/common/ext/TivaWare/inc/hw_eeprom.h251
-rw-r--r--os/common/ext/TivaWare/inc/hw_emac.h1839
-rw-r--r--os/common/ext/TivaWare/inc/hw_epi.h933
-rw-r--r--os/common/ext/TivaWare/inc/hw_fan.h49
-rw-r--r--os/common/ext/TivaWare/inc/hw_flash.h625
-rw-r--r--os/common/ext/TivaWare/inc/hw_gpio.h213
-rw-r--r--os/common/ext/TivaWare/inc/hw_hibernate.h483
-rw-r--r--os/common/ext/TivaWare/inc/hw_i2c.h470
-rw-r--r--os/common/ext/TivaWare/inc/hw_ints.h491
-rw-r--r--os/common/ext/TivaWare/inc/hw_lcd.h575
-rw-r--r--os/common/ext/TivaWare/inc/hw_memmap.h151
-rw-r--r--os/common/ext/TivaWare/inc/hw_nvic.h1414
-rw-r--r--os/common/ext/TivaWare/inc/hw_onewire.h223
-rw-r--r--os/common/ext/TivaWare/inc/hw_pwm.h1885
-rw-r--r--os/common/ext/TivaWare/inc/hw_qei.h178
-rw-r--r--os/common/ext/TivaWare/inc/hw_shamd5.h548
-rw-r--r--os/common/ext/TivaWare/inc/hw_ssi.h237
-rw-r--r--os/common/ext/TivaWare/inc/hw_sysctl.h3749
-rw-r--r--os/common/ext/TivaWare/inc/hw_sysexc.h132
-rw-r--r--os/common/ext/TivaWare/inc/hw_timer.h700
-rw-r--r--os/common/ext/TivaWare/inc/hw_types.h147
-rw-r--r--os/common/ext/TivaWare/inc/hw_uart.h367
-rw-r--r--os/common/ext/TivaWare/inc/hw_udma.h414
-rw-r--r--os/common/ext/TivaWare/inc/hw_usb.h3032
-rw-r--r--os/common/ext/TivaWare/inc/hw_watchdog.h122
38 files changed, 35504 insertions, 1 deletions
diff --git a/os/common/ext/CMSIS/KINETIS/k20xx.h b/os/common/ext/CMSIS/KINETIS/k20xx.h
index 38855aa..8218b3c 100644
--- a/os/common/ext/CMSIS/KINETIS/k20xx.h
+++ b/os/common/ext/CMSIS/KINETIS/k20xx.h
@@ -2242,7 +2242,7 @@ typedef struct
/******** Bits definition for USBx_CTL register *****************/
#define USBx_CTL_JSTATE ((uint8_t)0x80) /*!< Live USB differential receiver JSTATE signal */
#define USBx_CTL_SE0 ((uint8_t)0x40) /*!< Live USB single ended zero signal */
-#define USBx_CTL_TXSUSPENDTOKENBUS ((uint8_t)0x20) /*!< */
+#define USBx_CTL_TXSUSPENDTOKENBUSY ((uint8_t)0x20) /*!< */
#define USBx_CTL_RESET ((uint8_t)0x10) /*!< Generates an USB reset signal (host mode) */
#define USBx_CTL_HOSTMODEEN ((uint8_t)0x08) /*!< Operate in Host mode */
#define USBx_CTL_RESUME ((uint8_t)0x04) /*!< Executes resume signaling */
diff --git a/os/common/ext/MSP430/inc/in430.h b/os/common/ext/MSP430/inc/in430.h
new file mode 100644
index 0000000..f907209
--- /dev/null
+++ b/os/common/ext/MSP430/inc/in430.h
@@ -0,0 +1,343 @@
+/*******************************************************************************
+ * in430.h -
+ *
+ * Copyright (C) 2003-2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************/
+
+#ifndef __IN430_H__
+#define __IN430_H__
+
+/* Definitions for projects using the GNU C/C++ compiler */
+#if !defined(__ASSEMBLER__)
+
+/* Definitions of things which are intrinsics with IAR and CCS, but which don't
+ appear to be intrinsics with the RedHat GCC compiler */
+
+/* The data type used to hold interrupt state */
+typedef unsigned int __istate_t;
+
+#define _no_operation() __asm__ __volatile__ ("nop")
+
+#define _get_interrupt_state() \
+({ \
+ unsigned int __x; \
+ __asm__ __volatile__( \
+ "mov SR, %0" \
+ : "=r" ((unsigned int) __x) \
+ :); \
+ __x; \
+})
+
+#if defined(__MSP430_HAS_MSP430XV2_CPU__) || defined(__MSP430_HAS_MSP430X_CPU__)
+#define _set_interrupt_state(x) \
+({ \
+ __asm__ __volatile__ ("mov %0, SR { nop" \
+ : : "ri"((unsigned int) x) \
+ );\
+})
+
+#define _enable_interrupts() __asm__ __volatile__ ("nop { eint { nop")
+
+#define _bis_SR_register(x) \
+ __asm__ __volatile__ ("bis.w %0, SR { nop" \
+ : : "ri"((unsigned int) x) \
+ )
+#else
+
+#define _set_interrupt_state(x) \
+({ \
+ __asm__ __volatile__ ("mov %0, SR" \
+ : : "ri"((unsigned int) x) \
+ );\
+})
+
+#define _enable_interrupts() __asm__ __volatile__ ("eint { nop")
+
+#define _bis_SR_register(x) \
+ __asm__ __volatile__ ("bis.w %0, SR" \
+ : : "ri"((unsigned int) x) \
+ )
+
+#endif
+
+#define _disable_interrupts() __asm__ __volatile__ ("dint { nop")
+
+#define _bic_SR_register(x) \
+ __asm__ __volatile__ ("bic.w %0, SR { nop" \
+ : : "ri"((unsigned int) x) \
+ )
+
+#define _get_SR_register() \
+({ \
+ unsigned int __x; \
+ __asm__ __volatile__( \
+ "mov SR, %0" \
+ : "=r" ((unsigned int) __x) \
+ :); \
+ __x; \
+})
+
+#define _swap_bytes(x) \
+({ \
+ unsigned int __dst = x; \
+ __asm__ __volatile__( \
+ "swpb %0" \
+ : "+r" ((unsigned int) __dst) \
+ :); \
+ __dst; \
+})
+
+/* Alternative names for GCC built-ins */
+#define _bic_SR_register_on_exit(x) __bic_SR_register_on_exit(x)
+#define _bis_SR_register_on_exit(x) __bis_SR_register_on_exit(x)
+
+/* Additional intrinsics provided for IAR/CCS compatibility */
+#define _bcd_add_short(x,y) \
+({ \
+ unsigned short __z = ((unsigned short) y); \
+ __asm__ __volatile__( \
+ "clrc \n\t" \
+ "dadd.w %1, %0" \
+ : "+r" ((unsigned short) __z) \
+ : "ri" ((unsigned short) x) \
+ ); \
+ __z; \
+})
+
+#define __bcd_add_short(x,y) _bcd_add_short(x,y)
+
+#define _bcd_add_long(x,y) \
+({ \
+ unsigned long __z = ((unsigned long) y); \
+ __asm__ __volatile__( \
+ "clrc \n\t" \
+ "dadd.w %L1, %L0 \n\t" \
+ "dadd.w %H1, %H0" \
+ : "+r" ((unsigned long) __z) \
+ : "ri" ((unsigned long) x) \
+ ); \
+ __z; \
+ })
+
+#define __bcd_add_long(x,y) _bcd_add_long(x,y)
+
+#define _get_SP_register() \
+({ \
+ unsigned int __x; \
+ __asm__ __volatile__( \
+ "mov SP, %0" \
+ : "=r" ((unsigned int) __x) \
+ :); \
+ __x; \
+})
+
+#define __get_SP_register() _get_SP_register()
+
+#define _set_SP_register(x) \
+({ \
+ __asm__ __volatile__ ("mov %0, SP" \
+ : : "ri"((unsigned int) x) \
+ );\
+})
+
+#define __set_SP_register(x) _set_SP_register(x)
+
+#define _data16_write_addr(addr,src) \
+({ \
+ unsigned long __src = src; \
+ __asm__ __volatile__ ( \
+ "movx.a %1, 0(%0)" \
+ : : "r"((unsigned int) addr), "m"((unsigned long) __src) \
+ ); \
+})
+
+#define __data16_write_addr(addr,src) _data16_write_addr(addr,src)
+
+#define _data16_read_addr(addr) \
+({ \
+ unsigned long __dst; \
+ __asm__ __volatile__ ( \
+ "movx.a @%1, %0" \
+ : "=m"((unsigned long) __dst) \
+ : "r"((unsigned int) addr) \
+ ); \
+ __dst; \
+})
+
+#define __data16_read_addr(addr) _data16_read_addr(addr)
+
+#define _data20_write_char(addr,src) \
+({ \
+ unsigned int __tmp; \
+ unsigned long __addr = addr; \
+ __asm__ __volatile__ ( \
+ "movx.a %1, %0 \n\t" \
+ "mov.b %2, 0(%0)" \
+ : "=&r"((unsigned int) __tmp) \
+ : "m"((unsigned long) __addr), "ri"((char) src) \
+ ); \
+})
+
+#define __data20_write_char(addr,src) _data20_write_char(addr,src)
+
+#define _data20_read_char(addr) \
+({ \
+ char __dst; \
+ unsigned int __tmp; \
+ unsigned long __addr = addr; \
+ __asm__ __volatile__ ( \
+ "movx.a %2, %1 \n\t" \
+ "mov.b 0(%1), %0" \
+ : "=r"((char) __dst), "=&r"((unsigned int) __tmp) \
+ : "m"((unsigned long) __addr) \
+ ); \
+ __dst ; \
+})
+
+#define __data20_read_char(addr) _data20_read_char(addr)
+
+#define _data20_write_short(addr,src) \
+({ \
+ unsigned int __tmp; \
+ unsigned long __addr = addr; \
+ __asm__ __volatile__ ( \
+ "movx.a %1, %0 \n\t" \
+ "mov.w %2, 0(%0)" \
+ : "=&r"((unsigned int) __tmp) \
+ : "m"((unsigned long) __addr), "ri"((short) src) \
+ ); \
+})
+
+#define __data20_write_short(addr,src) _data20_write_short(addr,src)
+
+#define _data20_read_short(addr) \
+({ \
+ short __dst; \
+ unsigned int __tmp; \
+ unsigned long __addr = addr; \
+ __asm__ __volatile__ ( \
+ "movx.a %2, %1 \n\t" \
+ "mov.w 0(%1), %0" \
+ : "=r"((short) __dst), "=&r"((unsigned int) __tmp) \
+ : "m"((unsigned long) __addr) \
+ ); \
+ __dst ; \
+})
+
+#define __data20_read_short(addr) _data20_read_short(addr)
+
+#define _data20_write_long(addr,src) \
+({ \
+ unsigned int __tmp; \
+ unsigned long __addr = addr; \
+ __asm__ __volatile__ ( \
+ "movx.a %1, %0 \n\t" \
+ "mov.w %L2, 0(%0) \n\t" \
+ "mov.w %H2, 2(%0)" \
+ : "=&r"((unsigned int) __tmp) \
+ : "m"((unsigned long) __addr), "ri"((long) src) \
+ ); \
+})
+
+#define __data20_write_long(addr,src) _data20_write_long(addr,src)
+
+#define _data20_read_long(addr) \
+({ \
+ long __dst; \
+ unsigned int __tmp; \
+ unsigned long __addr = addr; \
+ __asm__ __volatile__ ( \
+ "movx.a %2, %1 \n\t" \
+ "mov.w 0(%1), %L0 \n\t" \
+ "mov.w 2(%1), %H0" \
+ : "=r"((long) __dst), "=&r"((unsigned int) __tmp) \
+ : "m"((unsigned long) __addr) \
+ ); \
+ __dst ; \
+})
+
+#define __data20_read_long(addr) _data20_read_long(addr)
+
+#define _low_power_mode_0() _bis_SR_register(0x18)
+#define _low_power_mode_1() _bis_SR_register(0x58)
+#define _low_power_mode_2() _bis_SR_register(0x98)
+#define _low_power_mode_3() _bis_SR_register(0xD8)
+#define _low_power_mode_4() _bis_SR_register(0xF8)
+#define _low_power_mode_off_on_exit() _bic_SR_register_on_exit(0xF0)
+
+#define __low_power_mode_0() _low_power_mode_0()
+#define __low_power_mode_1() _low_power_mode_1()
+#define __low_power_mode_2() _low_power_mode_2()
+#define __low_power_mode_3() _low_power_mode_3()
+#define __low_power_mode_4() _low_power_mode_4()
+#define __low_power_mode_off_on_exit() _low_power_mode_off_on_exit()
+
+#define _even_in_range(x,y) (x)
+#define __even_in_range(x,y) _even_in_range(x,y)
+
+/* Define some alternative names for the intrinsics, which have been used
+ in the various versions of IAR and GCC */
+#define __no_operation() _no_operation()
+
+#define __get_interrupt_state() _get_interrupt_state()
+#define __set_interrupt_state(x) _set_interrupt_state(x)
+#define __enable_interrupt() _enable_interrupts()
+#define __disable_interrupt() _disable_interrupts()
+
+#define __bic_SR_register(x) _bic_SR_register(x)
+#define __bis_SR_register(x) _bis_SR_register(x)
+#define __get_SR_register() _get_SR_register()
+
+#define __swap_bytes(x) _swap_bytes(x)
+
+#define __nop() _no_operation()
+
+#define __eint() _enable_interrupts()
+#define __dint() _disable_interrupts()
+
+#define _NOP() _no_operation()
+#define _EINT() _enable_interrupts()
+#define _DINT() _disable_interrupts()
+
+#define _BIC_SR(x) _bic_SR_register(x)
+#define _BIC_SR_IRQ(x) _bic_SR_register_on_exit(x)
+#define _BIS_SR(x) _bis_SR_register(x)
+#define _BIS_SR_IRQ(x) _bis_SR_register_on_exit(x)
+#define _BIS_NMI_IE1(x) _bis_nmi_ie1(x)
+
+#define _SWAP_BYTES(x) _swap_bytes(x)
+
+#define __no_init __attribute__ ((section (".noinit")))
+
+#endif /* !defined _GNU_ASSEMBLER_ */
+
+#endif /* __IN430_H__ */
diff --git a/os/common/ext/MSP430/inc/iomacros.h b/os/common/ext/MSP430/inc/iomacros.h
new file mode 100644
index 0000000..fc0e76d
--- /dev/null
+++ b/os/common/ext/MSP430/inc/iomacros.h
@@ -0,0 +1,85 @@
+/*******************************************************************************
+ * iomacros.h -
+ *
+ * Copyright (C) 2003-2016 Texas Instruments Incorporated - http://www.ti.com/
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * Redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer.
+ *
+ * Redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the
+ * distribution.
+ *
+ * Neither the name of Texas Instruments Incorporated nor the names of
+ * its contributors may be used to endorse or promote products derived
+ * from this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************/
+
+#if !defined(_IOMACROS_H_)
+#define _IOMACROS_H_
+
+
+#if defined(__ASSEMBLER__)
+
+/* Definitions for assembly compilation using the GNU assembler */
+#define sfrb(x,x_) x=x_
+#define sfrw(x,x_) x=x_
+#define sfra(x,x_) x=x_
+#define sfrl(x,x_) x=x_
+
+#define const_sfrb(x,x_) x=x_
+#define const_sfrw(x,x_) x=x_
+#define const_sfra(x,x_) x=x_
+#define const_sfrl(x,x_) x=x_
+
+#define sfr_b(x)
+#define sfr_w(x)
+#define sfr_a(x)
+#define sfr_l(x)
+
+#else
+
+#define sfr_b(x) extern volatile unsigned char x
+#define sfr_w(x) extern volatile unsigned int x
+#define sfr_a(x) extern volatile unsigned long int x
+#define sfr_l(x) extern volatile unsigned long int x
+
+#define sfrb_(x,x_) extern volatile unsigned char x __asm__(#x_)
+#define sfrw_(x,x_) extern volatile unsigned int x __asm__(#x_)
+#define sfra_(x,x_) extern volatile unsigned long int x __asm__(#x_)
+#define sfrl_(x,x_) extern volatile unsigned long int x __asm__(#x_)
+
+#define sfrb(x,x_) sfrb_(x,x_)
+#define sfrw(x,x_) sfrw_(x,x_)
+#define sfra(x,x_) sfra_(x,x_)
+#define sfrl(x,x_) sfrl_(x,x_)
+
+#define const_sfrb(x,x_) const sfrb_(x,x_)
+#define const_sfrw(x,x_) const sfrw_(x,x_)
+#define const_sfra(x,x_) const sfra_(x,x_)
+#define const_sfrl(x,x_) const sfrl_(x,x_)
+
+#define __interrupt __attribute__((__interrupt__))
+#define __interrupt_vec(vec) __attribute__((interrupt(vec)))
+
+#endif /* defined(__ASSEMBLER__) */
+
+#endif /* _IOMACROS_H_ */
diff --git a/os/common/ext/MSP430/inc/msp430.h b/os/common/ext/MSP430/inc/msp430.h
new file mode 100755
index 0000000..40f8759
--- /dev/null
+++ b/os/common/ext/MSP430/inc/msp430.h
@@ -0,0 +1,1847 @@
+/*******************************************************************
+* *
+* This file is a generic include file controlled by *
+* compiler/assembler IDE generated defines *
+* *
+*******************************************************************/
+
+#ifndef __msp430
+#define __msp430
+
+
+#if defined (__MSP430C111__)
+#include "msp430c111.h"
+
+#elif defined (__MSP430C1111__)
+#include "msp430c1111.h"
+
+#elif defined (__MSP430C112__)
+#include "msp430c112.h"
+
+#elif defined (__MSP430C1121__)
+#include "msp430c1121.h"
+
+#elif defined (__MSP430C1331__)
+#include "msp430c1331.h"
+
+#elif defined (__MSP430C1351__)
+#include "msp430c1351.h"
+
+#elif defined (__MSP430C311S__)
+#include "msp430c311s.h"
+
+#elif defined (__MSP430C312__)
+#include "msp430c312.h"
+
+#elif defined (__MSP430C313__)
+#include "msp430c313.h"
+
+#elif defined (__MSP430C314__)
+#include "msp430c314.h"
+
+#elif defined (__MSP430C315__)
+#include "msp430c315.h"
+
+#elif defined (__MSP430C323__)
+#include "msp430c323.h"
+
+#elif defined (__MSP430C325__)
+#include "msp430c325.h"
+
+#elif defined (__MSP430C336__)
+#include "msp430c336.h"
+
+#elif defined (__MSP430C337__)
+#include "msp430c337.h"
+
+#elif defined (__MSP430C412__)
+#include "msp430c412.h"
+
+#elif defined (__MSP430C413__)
+#include "msp430c413.h"
+
+#elif defined (__MSP430CG4616__)
+#include "msp430cg4616.h"
+
+#elif defined (__MSP430CG4617__)
+#include "msp430cg4617.h"
+
+#elif defined (__MSP430CG4618__)
+#include "msp430cg4618.h"
+
+#elif defined (__MSP430CG4619__)
+#include "msp430cg4619.h"
+
+#elif defined (__MSP430E112__)
+#include "msp430e112.h"
+
+#elif defined (__MSP430E313__)
+#include "msp430e313.h"
+
+#elif defined (__MSP430E315__)
+#include "msp430e315.h"
+
+#elif defined (__MSP430E325__)
+#include "msp430e325.h"
+
+#elif defined (__MSP430E337__)
+#include "msp430e337.h"
+
+#elif defined (__MSP430F110__)
+#include "msp430f110.h"
+
+#elif defined (__MSP430F1101__)
+#include "msp430f1101.h"
+
+#elif defined (__MSP430F1101A__)
+#include "msp430f1101a.h"
+
+#elif defined (__MSP430F1111__)
+#include "msp430f1111.h"
+
+#elif defined (__MSP430F1111A__)
+#include "msp430f1111a.h"
+
+#elif defined (__MSP430F112__)
+#include "msp430f112.h"
+
+#elif defined (__MSP430F1121__)
+#include "msp430f1121.h"
+
+#elif defined (__MSP430F1121A__)
+#include "msp430f1121a.h"
+
+#elif defined (__MSP430F1122__)
+#include "msp430f1122.h"
+
+#elif defined (__MSP430F1132__)
+#include "msp430f1132.h"
+
+#elif defined (__MSP430F122__)
+#include "msp430f122.h"
+
+#elif defined (__MSP430F1222__)
+#include "msp430f1222.h"
+
+#elif defined (__MSP430F123__)
+#include "msp430f123.h"
+
+#elif defined (__MSP430F1232__)
+#include "msp430f1232.h"
+
+#elif defined (__MSP430F133__)
+#include "msp430f133.h"
+
+#elif defined (__MSP430F135__)
+#include "msp430f135.h"
+
+#elif defined (__MSP430F147__)
+#include "msp430f147.h"
+
+#elif defined (__MSP430F148__)
+#include "msp430f148.h"
+
+#elif defined (__MSP430F149__)
+#include "msp430f149.h"
+
+#elif defined (__MSP430F1471__)
+#include "msp430f1471.h"
+
+#elif defined (__MSP430F1481__)
+#include "msp430f1481.h"
+
+#elif defined (__MSP430F1491__)
+#include "msp430f1491.h"
+
+#elif defined (__MSP430F155__)
+#include "msp430f155.h"
+
+#elif defined (__MSP430F156__)
+#include "msp430f156.h"
+
+#elif defined (__MSP430F157__)
+#include "msp430f157.h"
+
+#elif defined (__MSP430F167__)
+#include "msp430f167.h"
+
+#elif defined (__MSP430F168__)
+#include "msp430f168.h"
+
+#elif defined (__MSP430F169__)
+#include "msp430f169.h"
+
+#elif defined (__MSP430F1610__)
+#include "msp430f1610.h"
+
+#elif defined (__MSP430F1611__)
+#include "msp430f1611.h"
+
+#elif defined (__MSP430F1612__)
+#include "msp430f1612.h"
+
+#elif defined (__MSP430F2001__)
+#include "msp430f2001.h"
+
+#elif defined (__MSP430F2011__)
+#include "msp430f2011.h"
+
+#elif defined (__MSP430F2002__)
+#include "msp430f2002.h"
+
+#elif defined (__MSP430F2012__)
+#include "msp430f2012.h"
+
+#elif defined (__MSP430F2003__)
+#include "msp430f2003.h"
+
+#elif defined (__MSP430F2013__)
+#include "msp430f2013.h"
+
+#elif defined (__MSP430F2101__)
+#include "msp430f2101.h"
+
+#elif defined (__MSP430F2111__)
+#include "msp430f2111.h"
+
+#elif defined (__MSP430F2121__)
+#include "msp430f2121.h"
+
+#elif defined (__MSP430F2131__)
+#include "msp430f2131.h"
+
+#elif defined (__MSP430F2112__)
+#include "msp430f2112.h"
+
+#elif defined (__MSP430F2122__)
+#include "msp430f2122.h"
+
+#elif defined (__MSP430F2132__)
+#include "msp430f2132.h"
+
+#elif defined (__MSP430F2232__)
+#include "msp430f2232.h"
+
+#elif defined (__MSP430F2252__)
+#include "msp430f2252.h"
+
+#elif defined (__MSP430F2272__)
+#include "msp430f2272.h"
+
+#elif defined (__MSP430F2234__)
+#include "msp430f2234.h"
+
+#elif defined (__MSP430F2254__)
+#include "msp430f2254.h"
+
+#elif defined (__MSP430F2274__)
+#include "msp430f2274.h"
+
+#elif defined (__MSP430F2330__)
+#include "msp430f2330.h"
+
+#elif defined (__MSP430F2350__)
+#include "msp430f2350.h"
+
+#elif defined (__MSP430F2370__)
+#include "msp430f2370.h"
+
+#elif defined (__MSP430F233__)
+#include "msp430f233.h"
+
+#elif defined (__MSP430F235__)
+#include "msp430f235.h"
+
+#elif defined (__MSP430F247__)
+#include "msp430f247.h"
+
+#elif defined (__MSP430F248__)
+#include "msp430f248.h"
+
+#elif defined (__MSP430F249__)
+#include "msp430f249.h"
+
+#elif defined (__MSP430F2410__)
+#include "msp430f2410.h"
+
+#elif defined (__MSP430F2471__)
+#include "msp430f2471.h"
+
+#elif defined (__MSP430F2481__)
+#include "msp430f2481.h"
+
+#elif defined (__MSP430F2491__)
+#include "msp430f2491.h"
+
+#elif defined (__MSP430F2416__)
+#include "msp430f2416.h"
+
+#elif defined (__MSP430F2417__)
+#include "msp430f2417.h"
+
+#elif defined (__MSP430F2418__)
+#include "msp430f2418.h"
+
+#elif defined (__MSP430F2419__)
+#include "msp430f2419.h"
+
+#elif defined (__MSP430F2616__)
+#include "msp430f2616.h"
+
+#elif defined (__MSP430F2617__)
+#include "msp430f2617.h"
+
+#elif defined (__MSP430F2618__)
+#include "msp430f2618.h"
+
+#elif defined (__MSP430F2619__)
+#include "msp430f2619.h"
+
+#elif defined (__MSP430F412__)
+#include "msp430f412.h"
+
+#elif defined (__MSP430F413__)
+#include "msp430f413.h"
+
+#elif defined (__MSP430F415__)
+#include "msp430f415.h"
+
+#elif defined (__MSP430F417__)
+#include "msp430f417.h"
+
+#elif defined (__MSP430F4132__)
+#include "msp430f4132.h"
+
+#elif defined (__MSP430F4152__)
+#include "msp430f4152.h"
+
+#elif defined (__MSP430F423__)
+#include "msp430f423.h"
+
+#elif defined (__MSP430F425__)
+#include "msp430f425.h"
+
+#elif defined (__MSP430F427__)
+#include "msp430f427.h"
+
+#elif defined (__MSP430F423A__)
+#include "msp430f423a.h"
+
+#elif defined (__MSP430F425A__)
+#include "msp430f425a.h"
+
+#elif defined (__MSP430F427A__)
+#include "msp430f427a.h"
+
+#elif defined (__MSP430F435__)
+#include "msp430f435.h"
+
+#elif defined (__MSP430F436__)
+#include "msp430f436.h"
+
+#elif defined (__MSP430F437__)
+#include "msp430f437.h"
+
+#elif defined (__MSP430F4351__)
+#include "msp430f4351.h"
+
+#elif defined (__MSP430F4361__)
+#include "msp430f4361.h"
+
+#elif defined (__MSP430F4371__)
+#include "msp430f4371.h"
+
+#elif defined (__MSP430F4481__)
+#include "msp430f4481.h"
+
+#elif defined (__MSP430F4491__)
+#include "msp430f4491.h"
+
+#elif defined (__MSP430F447__)
+#include "msp430f447.h"
+
+#elif defined (__MSP430F448__)
+#include "msp430f448.h"
+
+#elif defined (__MSP430F449__)
+#include "msp430f449.h"
+
+#elif defined (__MSP430FE423__)
+#include "msp430fe423.h"
+
+#elif defined (__MSP430FE425__)
+#include "msp430fe425.h"
+
+#elif defined (__MSP430FE427__)
+#include "msp430fe427.h"
+
+#elif defined (__MSP430FE423A__)
+#include "msp430fe423a.h"
+
+#elif defined (__MSP430FE425A__)
+#include "msp430fe425a.h"
+
+#elif defined (__MSP430FE427A__)
+#include "msp430fe427a.h"
+
+#elif defined (__MSP430FE4232__)
+#include "msp430fe4232.h"
+
+#elif defined (__MSP430FE4242__)
+#include "msp430fe4242.h"
+
+#elif defined (__MSP430FE4252__)
+#include "msp430fe4252.h"
+
+#elif defined (__MSP430FE4272__)
+#include "msp430fe4272.h"
+
+#elif defined (__MSP430F4783__)
+#include "msp430f4783.h"
+
+#elif defined (__MSP430F4793__)
+#include "msp430f4793.h"
+
+#elif defined (__MSP430F4784__)
+#include "msp430f4784.h"
+
+#elif defined (__MSP430F4794__)
+#include "msp430f4794.h"
+
+#elif defined (__MSP430F47126__)
+#include "msp430f47126.h"
+
+#elif defined (__MSP430F47127__)
+#include "msp430f47127.h"
+
+#elif defined (__MSP430F47163__)
+#include "msp430f47163.h"
+
+#elif defined (__MSP430F47173__)
+#include "msp430f47173.h"
+
+#elif defined (__MSP430F47183__)
+#include "msp430f47183.h"
+
+#elif defined (__MSP430F47193__)
+#include "msp430f47193.h"
+
+#elif defined (__MSP430F47166__)
+#include "msp430f47166.h"
+
+#elif defined (__MSP430F47176__)
+#include "msp430f47176.h"
+
+#elif defined (__MSP430F47186__)
+#include "msp430f47186.h"
+
+#elif defined (__MSP430F47196__)
+#include "msp430f47196.h"
+
+#elif defined (__MSP430F47167__)
+#include "msp430f47167.h"
+
+#elif defined (__MSP430F47177__)
+#include "msp430f47177.h"
+
+#elif defined (__MSP430F47187__)
+#include "msp430f47187.h"
+
+#elif defined (__MSP430F47197__)
+#include "msp430f47197.h"
+
+#elif defined (__MSP430F4250__)
+#include "msp430f4250.h"
+
+#elif defined (__MSP430F4260__)
+#include "msp430f4260.h"
+
+#elif defined (__MSP430F4270__)
+#include "msp430f4270.h"
+
+#elif defined (__MSP430FG4250__)
+#include "msp430fg4250.h"
+
+#elif defined (__MSP430FG4260__)
+#include "msp430fg4260.h"
+
+#elif defined (__MSP430FG4270__)
+#include "msp430fg4270.h"
+
+#elif defined (__MSP430FW423__)
+#include "msp430fw423.h"
+
+#elif defined (__MSP430FW425__)
+#include "msp430fw425.h"
+
+#elif defined (__MSP430FW427__)
+#include "msp430fw427.h"
+
+#elif defined (__MSP430FW428__)
+#include "msp430fw428.h"
+
+#elif defined (__MSP430FW429__)
+#include "msp430fw429.h"
+
+#elif defined (__MSP430FG437__)
+#include "msp430fg437.h"
+
+#elif defined (__MSP430FG438__)
+#include "msp430fg438.h"
+
+#elif defined (__MSP430FG439__)
+#include "msp430fg439.h"
+
+#elif defined (__MSP430F438__)
+#include "msp430f438.h"
+
+#elif defined (__MSP430F439__)
+#include "msp430f439.h"
+
+#elif defined (__MSP430F477__)
+#include "msp430f477.h"
+
+#elif defined (__MSP430F478__)
+#include "msp430f478.h"
+
+#elif defined (__MSP430F479__)
+#include "msp430f479.h"
+
+#elif defined (__MSP430FG477__)
+#include "msp430fg477.h"
+
+#elif defined (__MSP430FG478__)
+#include "msp430fg478.h"
+
+#elif defined (__MSP430FG479__)
+#include "msp430fg479.h"
+
+#elif defined (__MSP430F46161__)
+#include "msp430f46161.h"
+
+#elif defined (__MSP430F46171__)
+#include "msp430f46171.h"
+
+#elif defined (__MSP430F46181__)
+#include "msp430f46181.h"
+
+#elif defined (__MSP430F46191__)
+#include "msp430f46191.h"
+
+#elif defined (__MSP430F4616__)
+#include "msp430f4616.h"
+
+#elif defined (__MSP430F4617__)
+#include "msp430f4617.h"
+
+#elif defined (__MSP430F4618__)
+#include "msp430f4618.h"
+
+#elif defined (__MSP430F4619__)
+#include "msp430f4619.h"
+
+#elif defined (__MSP430FG4616__)
+#include "msp430fg4616.h"
+
+#elif defined (__MSP430FG4617__)
+#include "msp430fg4617.h"
+
+#elif defined (__MSP430FG4618__)
+#include "msp430fg4618.h"
+
+#elif defined (__MSP430FG4619__)
+#include "msp430fg4619.h"
+
+#elif defined (__MSP430F5418__)
+#include "msp430f5418.h"
+
+#elif defined (__MSP430F5419__)
+#include "msp430f5419.h"
+
+#elif defined (__MSP430F5435__)
+#include "msp430f5435.h"
+
+#elif defined (__MSP430F5436__)
+#include "msp430f5436.h"
+
+#elif defined (__MSP430F5437__)
+#include "msp430f5437.h"
+
+#elif defined (__MSP430F5438__)
+#include "msp430f5438.h"
+
+#elif defined (__MSP430F5418A__)
+#include "msp430f5418a.h"
+
+#elif defined (__MSP430F5419A__)
+#include "msp430f5419a.h"
+
+#elif defined (__MSP430F5435A__)
+#include "msp430f5435a.h"
+
+#elif defined (__MSP430F5436A__)
+#include "msp430f5436a.h"
+
+#elif defined (__MSP430F5437A__)
+#include "msp430f5437a.h"
+
+#elif defined (__MSP430F5438A__)
+#include "msp430f5438a.h"
+
+#elif defined (__MSP430F5212__)
+#include "msp430f5212.h"
+
+#elif defined (__MSP430F5213__)
+#include "msp430f5213.h"
+
+#elif defined (__MSP430F5214__)
+#include "msp430f5214.h"
+
+#elif defined (__MSP430F5217__)
+#include "msp430f5217.h"
+
+#elif defined (__MSP430F5218__)
+#include "msp430f5218.h"
+
+#elif defined (__MSP430F5219__)
+#include "msp430f5219.h"
+
+#elif defined (__MSP430F5222__)
+#include "msp430f5222.h"
+
+#elif defined (__MSP430F5223__)
+#include "msp430f5223.h"
+
+#elif defined (__MSP430F5224__)
+#include "msp430f5224.h"
+
+#elif defined (__MSP430F5227__)
+#include "msp430f5227.h"
+
+#elif defined (__MSP430F5228__)
+#include "msp430f5228.h"
+
+#elif defined (__MSP430F5229__)
+#include "msp430f5229.h"
+
+#elif defined (__MSP430F5232__)
+#include "msp430f5232.h"
+
+#elif defined (__MSP430F5234__)
+#include "msp430f5234.h"
+
+#elif defined (__MSP430F5237__)
+#include "msp430f5237.h"
+
+#elif defined (__MSP430F5239__)
+#include "msp430f5239.h"
+
+#elif defined (__MSP430F5242__)
+#include "msp430f5242.h"
+
+#elif defined (__MSP430F5244__)
+#include "msp430f5244.h"
+
+#elif defined (__MSP430F5247__)
+#include "msp430f5247.h"
+
+#elif defined (__MSP430F5249__)
+#include "msp430f5249.h"
+
+#elif defined (__MSP430F5304__)
+#include "msp430f5304.h"
+
+#elif defined (__MSP430F5308__)
+#include "msp430f5308.h"
+
+#elif defined (__MSP430F5309__)
+#include "msp430f5309.h"
+
+#elif defined (__MSP430F5310__)
+#include "msp430f5310.h"
+
+#elif defined (__MSP430F5340__)
+#include "msp430f5340.h"
+
+#elif defined (__MSP430F5341__)
+#include "msp430f5341.h"
+
+#elif defined (__MSP430F5342__)
+#include "msp430f5342.h"
+
+#elif defined (__MSP430F5324__)
+#include "msp430f5324.h"
+
+#elif defined (__MSP430F5325__)
+#include "msp430f5325.h"
+
+#elif defined (__MSP430F5326__)
+#include "msp430f5326.h"
+
+#elif defined (__MSP430F5327__)
+#include "msp430f5327.h"
+
+#elif defined (__MSP430F5328__)
+#include "msp430f5328.h"
+
+#elif defined (__MSP430F5329__)
+#include "msp430f5329.h"
+
+#elif defined (__MSP430F5500__)
+#include "msp430f5500.h"
+
+#elif defined (__MSP430F5501__)
+#include "msp430f5501.h"
+
+#elif defined (__MSP430F5502__)
+#include "msp430f5502.h"
+
+#elif defined (__MSP430F5503__)
+#include "msp430f5503.h"
+
+#elif defined (__MSP430F5504__)
+#include "msp430f5504.h"
+
+#elif defined (__MSP430F5505__)
+#include "msp430f5505.h"
+
+#elif defined (__MSP430F5506__)
+#include "msp430f5506.h"
+
+#elif defined (__MSP430F5507__)
+#include "msp430f5507.h"
+
+#elif defined (__MSP430F5508__)
+#include "msp430f5508.h"
+
+#elif defined (__MSP430F5509__)
+#include "msp430f5509.h"
+
+#elif defined (__MSP430F5510__)
+#include "msp430f5510.h"
+
+#elif defined (__MSP430F5513__)
+#include "msp430f5513.h"
+
+#elif defined (__MSP430F5514__)
+#include "msp430f5514.h"
+
+#elif defined (__MSP430F5515__)
+#include "msp430f5515.h"
+
+#elif defined (__MSP430F5517__)
+#include "msp430f5517.h"
+
+#elif defined (__MSP430F5519__)
+#include "msp430f5519.h"
+
+#elif defined (__MSP430F5521__)
+#include "msp430f5521.h"
+
+#elif defined (__MSP430F5522__)
+#include "msp430f5522.h"
+
+#elif defined (__MSP430F5524__)
+#include "msp430f5524.h"
+
+#elif defined (__MSP430F5525__)
+#include "msp430f5525.h"
+
+#elif defined (__MSP430F5526__)
+#include "msp430f5526.h"
+
+#elif defined (__MSP430F5527__)
+#include "msp430f5527.h"
+
+#elif defined (__MSP430F5528__)
+#include "msp430f5528.h"
+
+#elif defined (__MSP430F5529__)
+#include "msp430f5529.h"
+
+#elif defined (__MSP430P112__)
+#include "msp430p112.h"
+
+#elif defined (__MSP430P313__)
+#include "msp430p313.h"
+
+#elif defined (__MSP430P315__)
+#include "msp430p315.h"
+
+#elif defined (__MSP430P315S__)
+#include "msp430p315s.h"
+
+#elif defined (__MSP430P325__)
+#include "msp430p325.h"
+
+#elif defined (__MSP430P337__)
+#include "msp430p337.h"
+
+#elif defined (__CC430F5133__)
+#include "cc430f5133.h"
+
+#elif defined (__CC430F5135__)
+#include "cc430f5135.h"
+
+#elif defined (__CC430F5137__)
+#include "cc430f5137.h"
+
+#elif defined (__CC430F6125__)
+#include "cc430f6125.h"
+
+#elif defined (__CC430F6126__)
+#include "cc430f6126.h"
+
+#elif defined (__CC430F6127__)
+#include "cc430f6127.h"
+
+#elif defined (__CC430F6135__)
+#include "cc430f6135.h"
+
+#elif defined (__CC430F6137__)
+#include "cc430f6137.h"
+
+#elif defined (__CC430F5123__)
+#include "cc430f5123.h"
+
+#elif defined (__CC430F5125__)
+#include "cc430f5125.h"
+
+#elif defined (__CC430F5143__)
+#include "cc430f5143.h"
+
+#elif defined (__CC430F5145__)
+#include "cc430f5145.h"
+
+#elif defined (__CC430F5147__)
+#include "cc430f5147.h"
+
+#elif defined (__CC430F6143__)
+#include "cc430f6143.h"
+
+#elif defined (__CC430F6145__)
+#include "cc430f6145.h"
+
+#elif defined (__CC430F6147__)
+#include "cc430f6147.h"
+
+#elif defined (__MSP430F5333__)
+#include "msp430f5333.h"
+
+#elif defined (__MSP430F5335__)
+#include "msp430f5335.h"
+
+#elif defined (__MSP430F5336__)
+#include "msp430f5336.h"
+
+#elif defined (__MSP430F5338__)
+#include "msp430f5338.h"
+
+#elif defined (__MSP430F5630__)
+#include "msp430f5630.h"
+
+#elif defined (__MSP430F5631__)
+#include "msp430f5631.h"
+
+#elif defined (__MSP430F5632__)
+#include "msp430f5632.h"
+
+#elif defined (__MSP430F5633__)
+#include "msp430f5633.h"
+
+#elif defined (__MSP430F5634__)
+#include "msp430f5634.h"
+
+#elif defined (__MSP430F5635__)
+#include "msp430f5635.h"
+
+#elif defined (__MSP430F5636__)
+#include "msp430f5636.h"
+
+#elif defined (__MSP430F5637__)
+#include "msp430f5637.h"
+
+#elif defined (__MSP430F5638__)
+#include "msp430f5638.h"
+
+#elif defined (__MSP430F6433__)
+#include "msp430f6433.h"
+
+#elif defined (__MSP430F6435__)
+#include "msp430f6435.h"
+
+#elif defined (__MSP430F6436__)
+#include "msp430f6436.h"
+
+#elif defined (__MSP430F6438__)
+#include "msp430f6438.h"
+
+#elif defined (__MSP430F6630__)
+#include "msp430f6630.h"
+
+#elif defined (__MSP430F6631__)
+#include "msp430f6631.h"
+
+#elif defined (__MSP430F6632__)
+#include "msp430f6632.h"
+
+#elif defined (__MSP430F6633__)
+#include "msp430f6633.h"
+
+#elif defined (__MSP430F6634__)
+#include "msp430f6634.h"
+
+#elif defined (__MSP430F6635__)
+#include "msp430f6635.h"
+
+#elif defined (__MSP430F6636__)
+#include "msp430f6636.h"
+
+#elif defined (__MSP430F6637__)
+#include "msp430f6637.h"
+
+#elif defined (__MSP430F6638__)
+#include "msp430f6638.h"
+
+#elif defined (__MSP430F5358__)
+#include "msp430f5358.h"
+
+#elif defined (__MSP430F5359__)
+#include "msp430f5359.h"
+
+#elif defined (__MSP430F5658__)
+#include "msp430f5658.h"
+
+#elif defined (__MSP430F5659__)
+#include "msp430f5659.h"
+
+#elif defined (__MSP430F6458__)
+#include "msp430f6458.h"
+
+#elif defined (__MSP430F6459__)
+#include "msp430f6459.h"
+
+#elif defined (__MSP430F6658__)
+#include "msp430f6658.h"
+
+#elif defined (__MSP430F6659__)
+#include "msp430f6659.h"
+
+#elif defined (__MSP430FG6425__)
+#include "msp430fg6425.h"
+
+#elif defined (__MSP430FG6426__)
+#include "msp430fg6426.h"
+
+#elif defined (__MSP430FG6625__)
+#include "msp430fg6625.h"
+
+#elif defined (__MSP430FG6626__)
+#include "msp430fg6626.h"
+
+#elif defined (__MSP430L092__)
+#include "msp430l092.h"
+
+#elif defined (__MSP430C091__)
+#include "msp430c091.h"
+
+#elif defined (__MSP430C092__)
+#include "msp430c092.h"
+
+#elif defined (__MSP430F5131__)
+#include "msp430f5131.h"
+
+#elif defined (__MSP430F5151__)
+#include "msp430f5151.h"
+
+#elif defined (__MSP430F5171__)
+#include "msp430f5171.h"
+
+#elif defined (__MSP430F5132__)
+#include "msp430f5132.h"
+
+#elif defined (__MSP430F5152__)
+#include "msp430f5152.h"
+
+#elif defined (__MSP430F5172__)
+#include "msp430f5172.h"
+
+#elif defined (__MSP430F6720__)
+#include "msp430f6720.h"
+
+#elif defined (__MSP430F6721__)
+#include "msp430f6721.h"
+
+#elif defined (__MSP430F6723__)
+#include "msp430f6723.h"
+
+#elif defined (__MSP430F6724__)
+#include "msp430f6724.h"
+
+#elif defined (__MSP430F6725__)
+#include "msp430f6725.h"
+
+#elif defined (__MSP430F6726__)
+#include "msp430f6726.h"
+
+#elif defined (__MSP430F6730__)
+#include "msp430f6730.h"
+
+#elif defined (__MSP430F6731__)
+#include "msp430f6731.h"
+
+#elif defined (__MSP430F6733__)
+#include "msp430f6733.h"
+
+#elif defined (__MSP430F6734__)
+#include "msp430f6734.h"
+
+#elif defined (__MSP430F6735__)
+#include "msp430f6735.h"
+
+#elif defined (__MSP430F6736__)
+#include "msp430f6736.h"
+
+#elif defined (__MSP430F67621__)
+#include "msp430f67621.h"
+
+#elif defined (__MSP430F67641__)
+#include "msp430f67641.h"
+
+#elif defined (__MSP430F6720A__)
+#include "msp430f6720a.h"
+
+#elif defined (__MSP430F6721A__)
+#include "msp430f6721a.h"
+
+#elif defined (__MSP430F6723A__)
+#include "msp430f6723a.h"
+
+#elif defined (__MSP430F6724A__)
+#include "msp430f6724a.h"
+
+#elif defined (__MSP430F6725A__)
+#include "msp430f6725a.h"
+
+#elif defined (__MSP430F6726A__)
+#include "msp430f6726a.h"
+
+#elif defined (__MSP430F6730A__)
+#include "msp430f6730a.h"
+
+#elif defined (__MSP430F6731A__)
+#include "msp430f6731a.h"
+
+#elif defined (__MSP430F6733A__)
+#include "msp430f6733a.h"
+
+#elif defined (__MSP430F6734A__)
+#include "msp430f6734a.h"
+
+#elif defined (__MSP430F6735A__)
+#include "msp430f6735a.h"
+
+#elif defined (__MSP430F6736A__)
+#include "msp430f6736a.h"
+
+#elif defined (__MSP430F67621A__)
+#include "msp430f67621a.h"
+
+#elif defined (__MSP430F67641A__)
+#include "msp430f67641a.h"
+
+#elif defined (__MSP430F67451__)
+#include "msp430f67451.h"
+
+#elif defined (__MSP430F67651__)
+#include "msp430f67651.h"
+
+#elif defined (__MSP430F67751__)
+#include "msp430f67751.h"
+
+#elif defined (__MSP430F67461__)
+#include "msp430f67461.h"
+
+#elif defined (__MSP430F67661__)
+#include "msp430f67661.h"
+
+#elif defined (__MSP430F67761__)
+#include "msp430f67761.h"
+
+#elif defined (__MSP430F67471__)
+#include "msp430f67471.h"
+
+#elif defined (__MSP430F67671__)
+#include "msp430f67671.h"
+
+#elif defined (__MSP430F67771__)
+#include "msp430f67771.h"
+
+#elif defined (__MSP430F67481__)
+#include "msp430f67481.h"
+
+#elif defined (__MSP430F67681__)
+#include "msp430f67681.h"
+
+#elif defined (__MSP430F67781__)
+#include "msp430f67781.h"
+
+#elif defined (__MSP430F67491__)
+#include "msp430f67491.h"
+
+#elif defined (__MSP430F67691__)
+#include "msp430f67691.h"
+
+#elif defined (__MSP430F67791__)
+#include "msp430f67791.h"
+
+#elif defined (__MSP430F6745__)
+#include "msp430f6745.h"
+
+#elif defined (__MSP430F6765__)
+#include "msp430f6765.h"
+
+#elif defined (__MSP430F6775__)
+#include "msp430f6775.h"
+
+#elif defined (__MSP430F6746__)
+#include "msp430f6746.h"
+
+#elif defined (__MSP430F6766__)
+#include "msp430f6766.h"
+
+#elif defined (__MSP430F6776__)
+#include "msp430f6776.h"
+
+#elif defined (__MSP430F6747__)
+#include "msp430f6747.h"
+
+#elif defined (__MSP430F6767__)
+#include "msp430f6767.h"
+
+#elif defined (__MSP430F6777__)
+#include "msp430f6777.h"
+
+#elif defined (__MSP430F6748__)
+#include "msp430f6748.h"
+
+#elif defined (__MSP430F6768__)
+#include "msp430f6768.h"
+
+#elif defined (__MSP430F6778__)
+#include "msp430f6778.h"
+
+#elif defined (__MSP430F6749__)
+#include "msp430f6749.h"
+
+#elif defined (__MSP430F6769__)
+#include "msp430f6769.h"
+
+#elif defined (__MSP430F6779__)
+#include "msp430f6779.h"
+
+#elif defined (__MSP430F67451A__)
+#include "msp430f67451a.h"
+
+#elif defined (__MSP430F67651A__)
+#include "msp430f67651a.h"
+
+#elif defined (__MSP430F67751A__)
+#include "msp430f67751a.h"
+
+#elif defined (__MSP430F67461A__)
+#include "msp430f67461a.h"
+
+#elif defined (__MSP430F67661A__)
+#include "msp430f67661a.h"
+
+#elif defined (__MSP430F67761A__)
+#include "msp430f67761a.h"
+
+#elif defined (__MSP430F67471A__)
+#include "msp430f67471a.h"
+
+#elif defined (__MSP430F67671A__)
+#include "msp430f67671a.h"
+
+#elif defined (__MSP430F67771A__)
+#include "msp430f67771a.h"
+
+#elif defined (__MSP430F67481A__)
+#include "msp430f67481a.h"
+
+#elif defined (__MSP430F67681A__)
+#include "msp430f67681a.h"
+
+#elif defined (__MSP430F67781A__)
+#include "msp430f67781a.h"
+
+#elif defined (__MSP430F67491A__)
+#include "msp430f67491a.h"
+
+#elif defined (__MSP430F67691A__)
+#include "msp430f67691a.h"
+
+#elif defined (__MSP430F67791A__)
+#include "msp430f67791a.h"
+
+#elif defined (__MSP430F6745A__)
+#include "msp430f6745a.h"
+
+#elif defined (__MSP430F6765A__)
+#include "msp430f6765a.h"
+
+#elif defined (__MSP430F6775A__)
+#include "msp430f6775a.h"
+
+#elif defined (__MSP430F6746A__)
+#include "msp430f6746a.h"
+
+#elif defined (__MSP430F6766A__)
+#include "msp430f6766a.h"
+
+#elif defined (__MSP430F6776A__)
+#include "msp430f6776a.h"
+
+#elif defined (__MSP430F6747A__)
+#include "msp430f6747a.h"
+
+#elif defined (__MSP430F6767A__)
+#include "msp430f6767a.h"
+
+#elif defined (__MSP430F6777A__)
+#include "msp430f6777a.h"
+
+#elif defined (__MSP430F6748A__)
+#include "msp430f6748a.h"
+
+#elif defined (__MSP430F6768A__)
+#include "msp430f6768a.h"
+
+#elif defined (__MSP430F6778A__)
+#include "msp430f6778a.h"
+
+#elif defined (__MSP430F6749A__)
+#include "msp430f6749a.h"
+
+#elif defined (__MSP430F6769A__)
+#include "msp430f6769a.h"
+
+#elif defined (__MSP430F6779A__)
+#include "msp430f6779a.h"
+
+#elif defined (__MSP430FR5720__)
+#include "msp430fr5720.h"
+
+#elif defined (__MSP430FR5721__)
+#include "msp430fr5721.h"
+
+#elif defined (__MSP430FR5722__)
+#include "msp430fr5722.h"
+
+#elif defined (__MSP430FR5723__)
+#include "msp430fr5723.h"
+
+#elif defined (__MSP430FR5724__)
+#include "msp430fr5724.h"
+
+#elif defined (__MSP430FR5725__)
+#include "msp430fr5725.h"
+
+#elif defined (__MSP430FR5726__)
+#include "msp430fr5726.h"
+
+#elif defined (__MSP430FR5727__)
+#include "msp430fr5727.h"
+
+#elif defined (__MSP430FR5728__)
+#include "msp430fr5728.h"
+
+#elif defined (__MSP430FR5729__)
+#include "msp430fr5729.h"
+
+#elif defined (__MSP430FR5730__)
+#include "msp430fr5730.h"
+
+#elif defined (__MSP430FR5731__)
+#include "msp430fr5731.h"
+
+#elif defined (__MSP430FR5732__)
+#include "msp430fr5732.h"
+
+#elif defined (__MSP430FR5733__)
+#include "msp430fr5733.h"
+
+#elif defined (__MSP430FR5734__)
+#include "msp430fr5734.h"
+
+#elif defined (__MSP430FR5735__)
+#include "msp430fr5735.h"
+
+#elif defined (__MSP430FR5736__)
+#include "msp430fr5736.h"
+
+#elif defined (__MSP430FR5737__)
+#include "msp430fr5737.h"
+
+#elif defined (__MSP430FR5738__)
+#include "msp430fr5738.h"
+
+#elif defined (__MSP430FR5739__)
+#include "msp430fr5739.h"
+
+#elif defined (__MSP430G2211__)
+#include "msp430g2211.h"
+
+#elif defined (__MSP430G2201__)
+#include "msp430g2201.h"
+
+#elif defined (__MSP430G2111__)
+#include "msp430g2111.h"
+
+#elif defined (__MSP430G2101__)
+#include "msp430g2101.h"
+
+#elif defined (__MSP430G2001__)
+#include "msp430g2001.h"
+
+#elif defined (__MSP430G2231__)
+#include "msp430g2231.h"
+
+#elif defined (__MSP430G2221__)
+#include "msp430g2221.h"
+
+#elif defined (__MSP430G2131__)
+#include "msp430g2131.h"
+
+#elif defined (__MSP430G2121__)
+#include "msp430g2121.h"
+
+#elif defined (__MSP430AFE221__)
+#include "msp430afe221.h"
+
+#elif defined (__MSP430AFE231__)
+#include "msp430afe231.h"
+
+#elif defined (__MSP430AFE251__)
+#include "msp430afe251.h"
+
+#elif defined (__MSP430AFE222__)
+#include "msp430afe222.h"
+
+#elif defined (__MSP430AFE232__)
+#include "msp430afe232.h"
+
+#elif defined (__MSP430AFE252__)
+#include "msp430afe252.h"
+
+#elif defined (__MSP430AFE223__)
+#include "msp430afe223.h"
+
+#elif defined (__MSP430AFE233__)
+#include "msp430afe233.h"
+
+#elif defined (__MSP430AFE253__)
+#include "msp430afe253.h"
+
+#elif defined (__MSP430G2102__)
+#include "msp430g2102.h"
+
+#elif defined (__MSP430G2202__)
+#include "msp430g2202.h"
+
+#elif defined (__MSP430G2302__)
+#include "msp430g2302.h"
+
+#elif defined (__MSP430G2402__)
+#include "msp430g2402.h"
+
+#elif defined (__MSP430G2132__)
+#include "msp430g2132.h"
+
+#elif defined (__MSP430G2232__)
+#include "msp430g2232.h"
+
+#elif defined (__MSP430G2332__)
+#include "msp430g2332.h"
+
+#elif defined (__MSP430G2432__)
+#include "msp430g2432.h"
+
+#elif defined (__MSP430G2112__)
+#include "msp430g2112.h"
+
+#elif defined (__MSP430G2212__)
+#include "msp430g2212.h"
+
+#elif defined (__MSP430G2312__)
+#include "msp430g2312.h"
+
+#elif defined (__MSP430G2412__)
+#include "msp430g2412.h"
+
+#elif defined (__MSP430G2152__)
+#include "msp430g2152.h"
+
+#elif defined (__MSP430G2252__)
+#include "msp430g2252.h"
+
+#elif defined (__MSP430G2352__)
+#include "msp430g2352.h"
+
+#elif defined (__MSP430G2452__)
+#include "msp430g2452.h"
+
+#elif defined (__MSP430G2113__)
+#include "msp430g2113.h"
+
+#elif defined (__MSP430G2213__)
+#include "msp430g2213.h"
+
+#elif defined (__MSP430G2313__)
+#include "msp430g2313.h"
+
+#elif defined (__MSP430G2413__)
+#include "msp430g2413.h"
+
+#elif defined (__MSP430G2513__)
+#include "msp430g2513.h"
+
+#elif defined (__MSP430G2153__)
+#include "msp430g2153.h"
+
+#elif defined (__MSP430G2253__)
+#include "msp430g2253.h"
+
+#elif defined (__MSP430G2353__)
+#include "msp430g2353.h"
+
+#elif defined (__MSP430G2453__)
+#include "msp430g2453.h"
+
+#elif defined (__MSP430G2553__)
+#include "msp430g2553.h"
+
+#elif defined (__MSP430G2203__)
+#include "msp430g2203.h"
+
+#elif defined (__MSP430G2303__)
+#include "msp430g2303.h"
+
+#elif defined (__MSP430G2403__)
+#include "msp430g2403.h"
+
+#elif defined (__MSP430G2233__)
+#include "msp430g2233.h"
+
+#elif defined (__MSP430G2333__)
+#include "msp430g2333.h"
+
+#elif defined (__MSP430G2433__)
+#include "msp430g2433.h"
+
+#elif defined (__MSP430G2533__)
+#include "msp430g2533.h"
+
+#elif defined (__MSP430TCH5E__)
+#include "msp430tch5e.h"
+
+#elif defined (__MSP430G2444__)
+#include "msp430g2444.h"
+
+#elif defined (__MSP430G2544__)
+#include "msp430g2544.h"
+
+#elif defined (__MSP430G2744__)
+#include "msp430g2744.h"
+
+#elif defined (__MSP430G2755__)
+#include "msp430g2755.h"
+
+#elif defined (__MSP430G2855__)
+#include "msp430g2855.h"
+
+#elif defined (__MSP430G2955__)
+#include "msp430g2955.h"
+
+#elif defined (__MSP430G2230__)
+#include "msp430g2230.h"
+
+#elif defined (__MSP430G2210__)
+#include "msp430g2210.h"
+
+#elif defined (__MSP430BT5190__)
+#include "msp430bt5190.h"
+
+#elif defined (__MSP430FR5857__)
+#include "msp430fr5857.h"
+
+#elif defined (__MSP430FR5858__)
+#include "msp430fr5858.h"
+
+#elif defined (__MSP430FR5859__)
+#include "msp430fr5859.h"
+
+#elif defined (__MSP430FR5847__)
+#include "msp430fr5847.h"
+
+#elif defined (__MSP430FR58471__)
+#include "msp430fr58471.h"
+
+#elif defined (__MSP430FR5848__)
+#include "msp430fr5848.h"
+
+#elif defined (__MSP430FR5849__)
+#include "msp430fr5849.h"
+
+#elif defined (__MSP430FR5867__)
+#include "msp430fr5867.h"
+
+#elif defined (__MSP430FR58671__)
+#include "msp430fr58671.h"
+
+#elif defined (__MSP430FR5868__)
+#include "msp430fr5868.h"
+
+#elif defined (__MSP430FR5869__)
+#include "msp430fr5869.h"
+
+#elif defined (__MSP430FR5957__)
+#include "msp430fr5957.h"
+
+#elif defined (__MSP430FR5958__)
+#include "msp430fr5958.h"
+
+#elif defined (__MSP430FR5959__)
+#include "msp430fr5959.h"
+
+#elif defined (__MSP430FR5947__)
+#include "msp430fr5947.h"
+
+#elif defined (__MSP430FR59471__)
+#include "msp430fr59471.h"
+
+#elif defined (__MSP430FR5948__)
+#include "msp430fr5948.h"
+
+#elif defined (__MSP430FR5949__)
+#include "msp430fr5949.h"
+
+#elif defined (__MSP430FR5967__)
+#include "msp430fr5967.h"
+
+#elif defined (__MSP430FR5968__)
+#include "msp430fr5968.h"
+
+#elif defined (__MSP430FR5969__)
+#include "msp430fr5969.h"
+
+#elif defined (__MSP430FR59691__)
+#include "msp430fr59691.h"
+
+#elif defined (__MSP430FR5962__)
+#include "msp430fr5962.h"
+
+#elif defined (__MSP430FR5964__)
+#include "msp430fr5964.h"
+
+#elif defined (__MSP430FR5992__)
+#include "msp430fr5992.h"
+
+#elif defined (__MSP430FR5994__)
+#include "msp430fr5994.h"
+
+#elif defined (__MSP430FR59941__)
+#include "msp430fr59941.h"
+
+#elif defined (__MSP430i2020__)
+#include "msp430i2020.h"
+
+#elif defined (__MSP430i2021__)
+#include "msp430i2021.h"
+
+#elif defined (__MSP430i2030__)
+#include "msp430i2030.h"
+
+#elif defined (__MSP430i2031__)
+#include "msp430i2031.h"
+
+#elif defined (__MSP430i2040__)
+#include "msp430i2040.h"
+
+#elif defined (__MSP430i2041__)
+#include "msp430i2041.h"
+
+#elif defined (__RF430FRL152H__)
+#include "rf430frl152h.h"
+
+#elif defined (__RF430FRL153H__)
+#include "rf430frl153h.h"
+
+#elif defined (__RF430FRL154H__)
+#include "rf430frl154h.h"
+
+#elif defined (__RF430FRL152H_ROM__)
+#include "rf430frl152h_rom.h"
+
+#elif defined (__RF430FRL153H_ROM__)
+#include "rf430frl153h_rom.h"
+
+#elif defined (__RF430FRL154H_ROM__)
+#include "rf430frl154h_rom.h"
+
+#elif defined (__RF430F5175__)
+#include "rf430f5175.h"
+
+#elif defined (__RF430F5155__)
+#include "rf430f5155.h"
+
+#elif defined (__RF430F5144__)
+#include "rf430f5144.h"
+
+#elif defined (__MSP430FR69271__)
+#include "msp430fr69271.h"
+
+#elif defined (__MSP430FR68791__)
+#include "msp430fr68791.h"
+
+#elif defined (__MSP430FR69791__)
+#include "msp430fr69791.h"
+
+#elif defined (__MSP430FR6927__)
+#include "msp430fr6927.h"
+
+#elif defined (__MSP430FR6928__)
+#include "msp430fr6928.h"
+
+#elif defined (__MSP430FR6877__)
+#include "msp430fr6877.h"
+
+#elif defined (__MSP430FR6977__)
+#include "msp430fr6977.h"
+
+#elif defined (__MSP430FR6879__)
+#include "msp430fr6879.h"
+
+#elif defined (__MSP430FR6979__)
+#include "msp430fr6979.h"
+
+#elif defined (__MSP430FR58891__)
+#include "msp430fr58891.h"
+
+#elif defined (__MSP430FR68891__)
+#include "msp430fr68891.h"
+
+#elif defined (__MSP430FR59891__)
+#include "msp430fr59891.h"
+
+#elif defined (__MSP430FR69891__)
+#include "msp430fr69891.h"
+
+#elif defined (__MSP430FR5887__)
+#include "msp430fr5887.h"
+
+#elif defined (__MSP430FR5888__)
+#include "msp430fr5888.h"
+
+#elif defined (__MSP430FR5889__)
+#include "msp430fr5889.h"
+
+#elif defined (__MSP430FR6887__)
+#include "msp430fr6887.h"
+
+#elif defined (__MSP430FR6888__)
+#include "msp430fr6888.h"
+
+#elif defined (__MSP430FR6889__)
+#include "msp430fr6889.h"
+
+#elif defined (__MSP430FR5986__)
+#include "msp430fr5986.h"
+
+#elif defined (__MSP430FR5987__)
+#include "msp430fr5987.h"
+
+#elif defined (__MSP430FR5988__)
+#include "msp430fr5988.h"
+
+#elif defined (__MSP430FR5989__)
+#include "msp430fr5989.h"
+
+#elif defined (__MSP430FR6987__)
+#include "msp430fr6987.h"
+
+#elif defined (__MSP430FR6988__)
+#include "msp430fr6988.h"
+
+#elif defined (__MSP430FR6989__)
+#include "msp430fr6989.h"
+
+#elif defined (__MSP430FR5922__)
+#include "msp430fr5922.h"
+
+#elif defined (__MSP430FR5870__)
+#include "msp430fr5870.h"
+
+#elif defined (__MSP430FR5970__)
+#include "msp430fr5970.h"
+
+#elif defined (__MSP430FR5872__)
+#include "msp430fr5872.h"
+
+#elif defined (__MSP430FR5972__)
+#include "msp430fr5972.h"
+
+#elif defined (__MSP430FR6820__)
+#include "msp430fr6820.h"
+
+#elif defined (__MSP430FR6920__)
+#include "msp430fr6920.h"
+
+#elif defined (__MSP430FR6822__)
+#include "msp430fr6822.h"
+
+#elif defined (__MSP430FR6922__)
+#include "msp430fr6922.h"
+
+#elif defined (__MSP430FR6870__)
+#include "msp430fr6870.h"
+
+#elif defined (__MSP430FR6970__)
+#include "msp430fr6970.h"
+
+#elif defined (__MSP430FR6872__)
+#include "msp430fr6872.h"
+
+#elif defined (__MSP430FR6972__)
+#include "msp430fr6972.h"
+
+#elif defined (__MSP430FR59221__)
+#include "msp430fr59221.h"
+
+#elif defined (__MSP430FR58721__)
+#include "msp430fr58721.h"
+
+#elif defined (__MSP430FR59721__)
+#include "msp430fr59721.h"
+
+#elif defined (__MSP430FR68221__)
+#include "msp430fr68221.h"
+
+#elif defined (__MSP430FR69221__)
+#include "msp430fr69221.h"
+
+#elif defined (__MSP430FR68721__)
+#include "msp430fr68721.h"
+
+#elif defined (__MSP430FR69721__)
+#include "msp430fr69721.h"
+
+#elif defined (__MSP430SL5438A__)
+#include "msp430sl5438a.h"
+
+#elif defined (__MSP430FR4131__)
+#include "msp430fr4131.h"
+
+#elif defined (__MSP430FR4132__)
+#include "msp430fr4132.h"
+
+#elif defined (__MSP430FR4133__)
+#include "msp430fr4133.h"
+
+#elif defined (__MSP430FR2032__)
+#include "msp430fr2032.h"
+
+#elif defined (__MSP430FR2033__)
+#include "msp430fr2033.h"
+
+#elif defined (__MSP430FR2110__)
+#include "msp430fr2110.h"
+
+#elif defined (__MSP430FR2111__)
+#include "msp430fr2111.h"
+
+#elif defined (__MSP430FR2310__)
+#include "msp430fr2310.h"
+
+#elif defined (__MSP430FR2311__)
+#include "msp430fr2311.h"
+
+#elif defined (__MSP430FR2433__)
+#include "msp430fr2433.h"
+
+#elif defined (__MSP430FR2532__)
+#include "msp430fr2532.h"
+
+#elif defined (__MSP430FR2533__)
+#include "msp430fr2533.h"
+
+#elif defined (__MSP430FR2632__)
+#include "msp430fr2632.h"
+
+#elif defined (__MSP430FR2633__)
+#include "msp430fr2633.h"
+
+#elif defined (__MSP430F5252__)
+#include "msp430f5252.h"
+
+#elif defined (__MSP430F5253__)
+#include "msp430f5253.h"
+
+#elif defined (__MSP430F5254__)
+#include "msp430f5254.h"
+
+#elif defined (__MSP430F5255__)
+#include "msp430f5255.h"
+
+#elif defined (__MSP430F5256__)
+#include "msp430f5256.h"
+
+#elif defined (__MSP430F5257__)
+#include "msp430f5257.h"
+
+#elif defined (__MSP430F5258__)
+#include "msp430f5258.h"
+
+#elif defined (__MSP430F5259__)
+#include "msp430f5259.h"
+
+
+#elif defined (__MSP430XGENERIC__)
+#include "msp430xgeneric.h"
+
+#elif defined (__MSP430F5XX_6XXGENERIC__)
+#include "msp430f5xx_6xxgeneric.h"
+
+#elif defined (__MSP430FR5XX_6XXGENERIC__)
+#include "msp430fr5xx_6xxgeneric.h"
+
+#elif defined (__MSP430FR2XX_4XXGENERIC__)
+#include "msp430fr2xx_4xxgeneric.h"
+
+#elif defined (__MSP430FR57XXGENERIC__)
+#include "msp430fr57xxgeneric.h"
+
+#elif defined (__MSP430I2XXGENERIC__)
+#include "msp430i2xxgeneric.h"
+
+/********************************************************************
+ * msp430 generic
+ ********************************************************************/
+#elif defined (__MSP430GENERIC__)
+#error "msp430 generic device does not have a default include file"
+
+#elif defined (__MSP430XGENERIC__)
+#error "msp430X generic device does not have a default include file"
+
+
+/********************************************************************
+ *
+ ********************************************************************/
+#else
+#error "Failed to match a default include file"
+#endif
+
+#endif /* #ifndef __msp430 */
+
+
diff --git a/os/common/ext/MSP430/inc/msp430fr5969.h b/os/common/ext/MSP430/inc/msp430fr5969.h
new file mode 100755
index 0000000..54b14f1
--- /dev/null
+++ b/os/common/ext/MSP430/inc/msp430fr5969.h
@@ -0,0 +1,4509 @@
+/* ============================================================================ */
+/* Copyright (c) 2016, Texas Instruments Incorporated */
+/* All rights reserved. */
+/* */
+/* Redistribution and use in source and binary forms, with or without */
+/* modification, are permitted provided that the following conditions */
+/* are met: */
+/* */
+/* * Redistributions of source code must retain the above copyright */
+/* notice, this list of conditions and the following disclaimer. */
+/* */
+/* * Redistributions in binary form must reproduce the above copyright */
+/* notice, this list of conditions and the following disclaimer in the */
+/* documentation and/or other materials provided with the distribution. */
+/* */
+/* * Neither the name of Texas Instruments Incorporated nor the names of */
+/* its contributors may be used to endorse or promote products derived */
+/* from this software without specific prior written permission. */
+/* */
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */
+/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */
+/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */
+/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */
+/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */
+/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */
+/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */
+/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */
+/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */
+/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/* ============================================================================ */
+
+/********************************************************************
+*
+* Standard register and bit definitions for the Texas Instruments
+* MSP430 microcontroller.
+*
+* This file supports assembler and C development for
+* MSP430FR5969 devices.
+*
+* Texas Instruments, Version 1.4
+*
+* Rev. 1.0, Setup
+* Rev. 1.1 updated PxSELC register address to offset 0x16 (instead of 0x10)
+* replaced Comperator B with Comperator E
+* Rev. 1.2 fixed typo in SYSRSTIV_MPUSEG defintions
+* replaced COMP_B with COMP_E
+* Rev. 1.3 removed not available PxDS Register definitions
+* Rev. 1.4 replaced NACCESSx with NWAITSx
+*
+********************************************************************/
+
+#ifndef __MSP430FR5969
+#define __MSP430FR5969
+
+#define __MSP430_HAS_MSP430XV2_CPU__ /* Definition to show that it has MSP430XV2 CPU */
+#define __MSP430FR5XX_6XX_FAMILY__
+
+#define __MSP430_HEADER_VERSION__ 1198
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*----------------------------------------------------------------------------*/
+/* PERIPHERAL FILE MAP */
+/*----------------------------------------------------------------------------*/
+
+#define __MSP430_TI_HEADERS__
+
+#include <iomacros.h>
+
+
+/************************************************************
+* STANDARD BITS
+************************************************************/
+
+#define BIT0 (0x0001)
+#define BIT1 (0x0002)
+#define BIT2 (0x0004)
+#define BIT3 (0x0008)
+#define BIT4 (0x0010)
+#define BIT5 (0x0020)
+#define BIT6 (0x0040)
+#define BIT7 (0x0080)
+#define BIT8 (0x0100)
+#define BIT9 (0x0200)
+#define BITA (0x0400)
+#define BITB (0x0800)
+#define BITC (0x1000)
+#define BITD (0x2000)
+#define BITE (0x4000)
+#define BITF (0x8000)
+
+/************************************************************
+* STATUS REGISTER BITS
+************************************************************/
+
+#define C (0x0001)
+#define Z (0x0002)
+#define N (0x0004)
+#define V (0x0100)
+#define GIE (0x0008)
+#define CPUOFF (0x0010)
+#define OSCOFF (0x0020)
+#define SCG0 (0x0040)
+#define SCG1 (0x0080)
+
+/* Low Power Modes coded with Bits 4-7 in SR */
+
+#ifndef __STDC__ /* Begin #defines for assembler */
+#define LPM0 (CPUOFF)
+#define LPM1 (SCG0+CPUOFF)
+#define LPM2 (SCG1+CPUOFF)
+#define LPM3 (SCG1+SCG0+CPUOFF)
+#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)
+/* End #defines for assembler */
+
+#else /* Begin #defines for C */
+#define LPM0_bits (CPUOFF)
+#define LPM1_bits (SCG0+CPUOFF)
+#define LPM2_bits (SCG1+CPUOFF)
+#define LPM3_bits (SCG1+SCG0+CPUOFF)
+#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)
+
+#include "in430.h"
+
+#define LPM0 __bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */
+#define LPM0_EXIT __bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */
+#define LPM1 __bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */
+#define LPM1_EXIT __bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */
+#define LPM2 __bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */
+#define LPM2_EXIT __bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */
+#define LPM3 __bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */
+#define LPM3_EXIT __bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */
+#define LPM4 __bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */
+#define LPM4_EXIT __bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */
+#endif /* End #defines for C */
+
+/************************************************************
+* PERIPHERAL FILE MAP
+************************************************************/
+
+/************************************************************
+* ADC12_B
+************************************************************/
+#define __MSP430_HAS_ADC12_B__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_ADC12_B__ 0x0800
+#define ADC12_B_BASE __MSP430_BASEADDRESS_ADC12_B__
+
+sfr_w(ADC12CTL0); /* ADC12 B Control 0 */
+sfr_b(ADC12CTL0_L); /* ADC12 B Control 0 */
+sfr_b(ADC12CTL0_H); /* ADC12 B Control 0 */
+sfr_w(ADC12CTL1); /* ADC12 B Control 1 */
+sfr_b(ADC12CTL1_L); /* ADC12 B Control 1 */
+sfr_b(ADC12CTL1_H); /* ADC12 B Control 1 */
+sfr_w(ADC12CTL2); /* ADC12 B Control 2 */
+sfr_b(ADC12CTL2_L); /* ADC12 B Control 2 */
+sfr_b(ADC12CTL2_H); /* ADC12 B Control 2 */
+sfr_w(ADC12CTL3); /* ADC12 B Control 3 */
+sfr_b(ADC12CTL3_L); /* ADC12 B Control 3 */
+sfr_b(ADC12CTL3_H); /* ADC12 B Control 3 */
+sfr_w(ADC12LO); /* ADC12 B Window Comparator High Threshold */
+sfr_b(ADC12LO_L); /* ADC12 B Window Comparator High Threshold */
+sfr_b(ADC12LO_H); /* ADC12 B Window Comparator High Threshold */
+sfr_w(ADC12HI); /* ADC12 B Window Comparator High Threshold */
+sfr_b(ADC12HI_L); /* ADC12 B Window Comparator High Threshold */
+sfr_b(ADC12HI_H); /* ADC12 B Window Comparator High Threshold */
+sfr_w(ADC12IFGR0); /* ADC12 B Interrupt Flag 0 */
+sfr_b(ADC12IFGR0_L); /* ADC12 B Interrupt Flag 0 */
+sfr_b(ADC12IFGR0_H); /* ADC12 B Interrupt Flag 0 */
+sfr_w(ADC12IFGR1); /* ADC12 B Interrupt Flag 1 */
+sfr_b(ADC12IFGR1_L); /* ADC12 B Interrupt Flag 1 */
+sfr_b(ADC12IFGR1_H); /* ADC12 B Interrupt Flag 1 */
+sfr_w(ADC12IFGR2); /* ADC12 B Interrupt Flag 2 */
+sfr_b(ADC12IFGR2_L); /* ADC12 B Interrupt Flag 2 */
+sfr_b(ADC12IFGR2_H); /* ADC12 B Interrupt Flag 2 */
+sfr_w(ADC12IER0); /* ADC12 B Interrupt Enable 0 */
+sfr_b(ADC12IER0_L); /* ADC12 B Interrupt Enable 0 */
+sfr_b(ADC12IER0_H); /* ADC12 B Interrupt Enable 0 */
+sfr_w(ADC12IER1); /* ADC12 B Interrupt Enable 1 */
+sfr_b(ADC12IER1_L); /* ADC12 B Interrupt Enable 1 */
+sfr_b(ADC12IER1_H); /* ADC12 B Interrupt Enable 1 */
+sfr_w(ADC12IER2); /* ADC12 B Interrupt Enable 2 */
+sfr_b(ADC12IER2_L); /* ADC12 B Interrupt Enable 2 */
+sfr_b(ADC12IER2_H); /* ADC12 B Interrupt Enable 2 */
+sfr_w(ADC12IV); /* ADC12 B Interrupt Vector Word */
+sfr_b(ADC12IV_L); /* ADC12 B Interrupt Vector Word */
+sfr_b(ADC12IV_H); /* ADC12 B Interrupt Vector Word */
+
+sfr_w(ADC12MCTL0); /* ADC12 Memory Control 0 */
+sfr_b(ADC12MCTL0_L); /* ADC12 Memory Control 0 */
+sfr_b(ADC12MCTL0_H); /* ADC12 Memory Control 0 */
+sfr_w(ADC12MCTL1); /* ADC12 Memory Control 1 */
+sfr_b(ADC12MCTL1_L); /* ADC12 Memory Control 1 */
+sfr_b(ADC12MCTL1_H); /* ADC12 Memory Control 1 */
+sfr_w(ADC12MCTL2); /* ADC12 Memory Control 2 */
+sfr_b(ADC12MCTL2_L); /* ADC12 Memory Control 2 */
+sfr_b(ADC12MCTL2_H); /* ADC12 Memory Control 2 */
+sfr_w(ADC12MCTL3); /* ADC12 Memory Control 3 */
+sfr_b(ADC12MCTL3_L); /* ADC12 Memory Control 3 */
+sfr_b(ADC12MCTL3_H); /* ADC12 Memory Control 3 */
+sfr_w(ADC12MCTL4); /* ADC12 Memory Control 4 */
+sfr_b(ADC12MCTL4_L); /* ADC12 Memory Control 4 */
+sfr_b(ADC12MCTL4_H); /* ADC12 Memory Control 4 */
+sfr_w(ADC12MCTL5); /* ADC12 Memory Control 5 */
+sfr_b(ADC12MCTL5_L); /* ADC12 Memory Control 5 */
+sfr_b(ADC12MCTL5_H); /* ADC12 Memory Control 5 */
+sfr_w(ADC12MCTL6); /* ADC12 Memory Control 6 */
+sfr_b(ADC12MCTL6_L); /* ADC12 Memory Control 6 */
+sfr_b(ADC12MCTL6_H); /* ADC12 Memory Control 6 */
+sfr_w(ADC12MCTL7); /* ADC12 Memory Control 7 */
+sfr_b(ADC12MCTL7_L); /* ADC12 Memory Control 7 */
+sfr_b(ADC12MCTL7_H); /* ADC12 Memory Control 7 */
+sfr_w(ADC12MCTL8); /* ADC12 Memory Control 8 */
+sfr_b(ADC12MCTL8_L); /* ADC12 Memory Control 8 */
+sfr_b(ADC12MCTL8_H); /* ADC12 Memory Control 8 */
+sfr_w(ADC12MCTL9); /* ADC12 Memory Control 9 */
+sfr_b(ADC12MCTL9_L); /* ADC12 Memory Control 9 */
+sfr_b(ADC12MCTL9_H); /* ADC12 Memory Control 9 */
+sfr_w(ADC12MCTL10); /* ADC12 Memory Control 10 */
+sfr_b(ADC12MCTL10_L); /* ADC12 Memory Control 10 */
+sfr_b(ADC12MCTL10_H); /* ADC12 Memory Control 10 */
+sfr_w(ADC12MCTL11); /* ADC12 Memory Control 11 */
+sfr_b(ADC12MCTL11_L); /* ADC12 Memory Control 11 */
+sfr_b(ADC12MCTL11_H); /* ADC12 Memory Control 11 */
+sfr_w(ADC12MCTL12); /* ADC12 Memory Control 12 */
+sfr_b(ADC12MCTL12_L); /* ADC12 Memory Control 12 */
+sfr_b(ADC12MCTL12_H); /* ADC12 Memory Control 12 */
+sfr_w(ADC12MCTL13); /* ADC12 Memory Control 13 */
+sfr_b(ADC12MCTL13_L); /* ADC12 Memory Control 13 */
+sfr_b(ADC12MCTL13_H); /* ADC12 Memory Control 13 */
+sfr_w(ADC12MCTL14); /* ADC12 Memory Control 14 */
+sfr_b(ADC12MCTL14_L); /* ADC12 Memory Control 14 */
+sfr_b(ADC12MCTL14_H); /* ADC12 Memory Control 14 */
+sfr_w(ADC12MCTL15); /* ADC12 Memory Control 15 */
+sfr_b(ADC12MCTL15_L); /* ADC12 Memory Control 15 */
+sfr_b(ADC12MCTL15_H); /* ADC12 Memory Control 15 */
+sfr_w(ADC12MCTL16); /* ADC12 Memory Control 16 */
+sfr_b(ADC12MCTL16_L); /* ADC12 Memory Control 16 */
+sfr_b(ADC12MCTL16_H); /* ADC12 Memory Control 16 */
+sfr_w(ADC12MCTL17); /* ADC12 Memory Control 17 */
+sfr_b(ADC12MCTL17_L); /* ADC12 Memory Control 17 */
+sfr_b(ADC12MCTL17_H); /* ADC12 Memory Control 17 */
+sfr_w(ADC12MCTL18); /* ADC12 Memory Control 18 */
+sfr_b(ADC12MCTL18_L); /* ADC12 Memory Control 18 */
+sfr_b(ADC12MCTL18_H); /* ADC12 Memory Control 18 */
+sfr_w(ADC12MCTL19); /* ADC12 Memory Control 19 */
+sfr_b(ADC12MCTL19_L); /* ADC12 Memory Control 19 */
+sfr_b(ADC12MCTL19_H); /* ADC12 Memory Control 19 */
+sfr_w(ADC12MCTL20); /* ADC12 Memory Control 20 */
+sfr_b(ADC12MCTL20_L); /* ADC12 Memory Control 20 */
+sfr_b(ADC12MCTL20_H); /* ADC12 Memory Control 20 */
+sfr_w(ADC12MCTL21); /* ADC12 Memory Control 21 */
+sfr_b(ADC12MCTL21_L); /* ADC12 Memory Control 21 */
+sfr_b(ADC12MCTL21_H); /* ADC12 Memory Control 21 */
+sfr_w(ADC12MCTL22); /* ADC12 Memory Control 22 */
+sfr_b(ADC12MCTL22_L); /* ADC12 Memory Control 22 */
+sfr_b(ADC12MCTL22_H); /* ADC12 Memory Control 22 */
+sfr_w(ADC12MCTL23); /* ADC12 Memory Control 23 */
+sfr_b(ADC12MCTL23_L); /* ADC12 Memory Control 23 */
+sfr_b(ADC12MCTL23_H); /* ADC12 Memory Control 23 */
+sfr_w(ADC12MCTL24); /* ADC12 Memory Control 24 */
+sfr_b(ADC12MCTL24_L); /* ADC12 Memory Control 24 */
+sfr_b(ADC12MCTL24_H); /* ADC12 Memory Control 24 */
+sfr_w(ADC12MCTL25); /* ADC12 Memory Control 25 */
+sfr_b(ADC12MCTL25_L); /* ADC12 Memory Control 25 */
+sfr_b(ADC12MCTL25_H); /* ADC12 Memory Control 25 */
+sfr_w(ADC12MCTL26); /* ADC12 Memory Control 26 */
+sfr_b(ADC12MCTL26_L); /* ADC12 Memory Control 26 */
+sfr_b(ADC12MCTL26_H); /* ADC12 Memory Control 26 */
+sfr_w(ADC12MCTL27); /* ADC12 Memory Control 27 */
+sfr_b(ADC12MCTL27_L); /* ADC12 Memory Control 27 */
+sfr_b(ADC12MCTL27_H); /* ADC12 Memory Control 27 */
+sfr_w(ADC12MCTL28); /* ADC12 Memory Control 28 */
+sfr_b(ADC12MCTL28_L); /* ADC12 Memory Control 28 */
+sfr_b(ADC12MCTL28_H); /* ADC12 Memory Control 28 */
+sfr_w(ADC12MCTL29); /* ADC12 Memory Control 29 */
+sfr_b(ADC12MCTL29_L); /* ADC12 Memory Control 29 */
+sfr_b(ADC12MCTL29_H); /* ADC12 Memory Control 29 */
+sfr_w(ADC12MCTL30); /* ADC12 Memory Control 30 */
+sfr_b(ADC12MCTL30_L); /* ADC12 Memory Control 30 */
+sfr_b(ADC12MCTL30_H); /* ADC12 Memory Control 30 */
+sfr_w(ADC12MCTL31); /* ADC12 Memory Control 31 */
+sfr_b(ADC12MCTL31_L); /* ADC12 Memory Control 31 */
+sfr_b(ADC12MCTL31_H); /* ADC12 Memory Control 31 */
+#define ADC12MCTL_ ADC12MCTL /* ADC12 Memory Control */
+#ifndef __STDC__
+#define ADC12MCTL ADC12MCTL0 /* ADC12 Memory Control (for assembler) */
+#else
+#define ADC12MCTL ((volatile char*) &ADC12MCTL0) /* ADC12 Memory Control (for C) */
+#endif
+
+sfr_w(ADC12MEM0); /* ADC12 Conversion Memory 0 */
+sfr_b(ADC12MEM0_L); /* ADC12 Conversion Memory 0 */
+sfr_b(ADC12MEM0_H); /* ADC12 Conversion Memory 0 */
+sfr_w(ADC12MEM1); /* ADC12 Conversion Memory 1 */
+sfr_b(ADC12MEM1_L); /* ADC12 Conversion Memory 1 */
+sfr_b(ADC12MEM1_H); /* ADC12 Conversion Memory 1 */
+sfr_w(ADC12MEM2); /* ADC12 Conversion Memory 2 */
+sfr_b(ADC12MEM2_L); /* ADC12 Conversion Memory 2 */
+sfr_b(ADC12MEM2_H); /* ADC12 Conversion Memory 2 */
+sfr_w(ADC12MEM3); /* ADC12 Conversion Memory 3 */
+sfr_b(ADC12MEM3_L); /* ADC12 Conversion Memory 3 */
+sfr_b(ADC12MEM3_H); /* ADC12 Conversion Memory 3 */
+sfr_w(ADC12MEM4); /* ADC12 Conversion Memory 4 */
+sfr_b(ADC12MEM4_L); /* ADC12 Conversion Memory 4 */
+sfr_b(ADC12MEM4_H); /* ADC12 Conversion Memory 4 */
+sfr_w(ADC12MEM5); /* ADC12 Conversion Memory 5 */
+sfr_b(ADC12MEM5_L); /* ADC12 Conversion Memory 5 */
+sfr_b(ADC12MEM5_H); /* ADC12 Conversion Memory 5 */
+sfr_w(ADC12MEM6); /* ADC12 Conversion Memory 6 */
+sfr_b(ADC12MEM6_L); /* ADC12 Conversion Memory 6 */
+sfr_b(ADC12MEM6_H); /* ADC12 Conversion Memory 6 */
+sfr_w(ADC12MEM7); /* ADC12 Conversion Memory 7 */
+sfr_b(ADC12MEM7_L); /* ADC12 Conversion Memory 7 */
+sfr_b(ADC12MEM7_H); /* ADC12 Conversion Memory 7 */
+sfr_w(ADC12MEM8); /* ADC12 Conversion Memory 8 */
+sfr_b(ADC12MEM8_L); /* ADC12 Conversion Memory 8 */
+sfr_b(ADC12MEM8_H); /* ADC12 Conversion Memory 8 */
+sfr_w(ADC12MEM9); /* ADC12 Conversion Memory 9 */
+sfr_b(ADC12MEM9_L); /* ADC12 Conversion Memory 9 */
+sfr_b(ADC12MEM9_H); /* ADC12 Conversion Memory 9 */
+sfr_w(ADC12MEM10); /* ADC12 Conversion Memory 10 */
+sfr_b(ADC12MEM10_L); /* ADC12 Conversion Memory 10 */
+sfr_b(ADC12MEM10_H); /* ADC12 Conversion Memory 10 */
+sfr_w(ADC12MEM11); /* ADC12 Conversion Memory 11 */
+sfr_b(ADC12MEM11_L); /* ADC12 Conversion Memory 11 */
+sfr_b(ADC12MEM11_H); /* ADC12 Conversion Memory 11 */
+sfr_w(ADC12MEM12); /* ADC12 Conversion Memory 12 */
+sfr_b(ADC12MEM12_L); /* ADC12 Conversion Memory 12 */
+sfr_b(ADC12MEM12_H); /* ADC12 Conversion Memory 12 */
+sfr_w(ADC12MEM13); /* ADC12 Conversion Memory 13 */
+sfr_b(ADC12MEM13_L); /* ADC12 Conversion Memory 13 */
+sfr_b(ADC12MEM13_H); /* ADC12 Conversion Memory 13 */
+sfr_w(ADC12MEM14); /* ADC12 Conversion Memory 14 */
+sfr_b(ADC12MEM14_L); /* ADC12 Conversion Memory 14 */
+sfr_b(ADC12MEM14_H); /* ADC12 Conversion Memory 14 */
+sfr_w(ADC12MEM15); /* ADC12 Conversion Memory 15 */
+sfr_b(ADC12MEM15_L); /* ADC12 Conversion Memory 15 */
+sfr_b(ADC12MEM15_H); /* ADC12 Conversion Memory 15 */
+sfr_w(ADC12MEM16); /* ADC12 Conversion Memory 16 */
+sfr_b(ADC12MEM16_L); /* ADC12 Conversion Memory 16 */
+sfr_b(ADC12MEM16_H); /* ADC12 Conversion Memory 16 */
+sfr_w(ADC12MEM17); /* ADC12 Conversion Memory 17 */
+sfr_b(ADC12MEM17_L); /* ADC12 Conversion Memory 17 */
+sfr_b(ADC12MEM17_H); /* ADC12 Conversion Memory 17 */
+sfr_w(ADC12MEM18); /* ADC12 Conversion Memory 18 */
+sfr_b(ADC12MEM18_L); /* ADC12 Conversion Memory 18 */
+sfr_b(ADC12MEM18_H); /* ADC12 Conversion Memory 18 */
+sfr_w(ADC12MEM19); /* ADC12 Conversion Memory 19 */
+sfr_b(ADC12MEM19_L); /* ADC12 Conversion Memory 19 */
+sfr_b(ADC12MEM19_H); /* ADC12 Conversion Memory 19 */
+sfr_w(ADC12MEM20); /* ADC12 Conversion Memory 20 */
+sfr_b(ADC12MEM20_L); /* ADC12 Conversion Memory 20 */
+sfr_b(ADC12MEM20_H); /* ADC12 Conversion Memory 20 */
+sfr_w(ADC12MEM21); /* ADC12 Conversion Memory 21 */
+sfr_b(ADC12MEM21_L); /* ADC12 Conversion Memory 21 */
+sfr_b(ADC12MEM21_H); /* ADC12 Conversion Memory 21 */
+sfr_w(ADC12MEM22); /* ADC12 Conversion Memory 22 */
+sfr_b(ADC12MEM22_L); /* ADC12 Conversion Memory 22 */
+sfr_b(ADC12MEM22_H); /* ADC12 Conversion Memory 22 */
+sfr_w(ADC12MEM23); /* ADC12 Conversion Memory 23 */
+sfr_b(ADC12MEM23_L); /* ADC12 Conversion Memory 23 */
+sfr_b(ADC12MEM23_H); /* ADC12 Conversion Memory 23 */
+sfr_w(ADC12MEM24); /* ADC12 Conversion Memory 24 */
+sfr_b(ADC12MEM24_L); /* ADC12 Conversion Memory 24 */
+sfr_b(ADC12MEM24_H); /* ADC12 Conversion Memory 24 */
+sfr_w(ADC12MEM25); /* ADC12 Conversion Memory 25 */
+sfr_b(ADC12MEM25_L); /* ADC12 Conversion Memory 25 */
+sfr_b(ADC12MEM25_H); /* ADC12 Conversion Memory 25 */
+sfr_w(ADC12MEM26); /* ADC12 Conversion Memory 26 */
+sfr_b(ADC12MEM26_L); /* ADC12 Conversion Memory 26 */
+sfr_b(ADC12MEM26_H); /* ADC12 Conversion Memory 26 */
+sfr_w(ADC12MEM27); /* ADC12 Conversion Memory 27 */
+sfr_b(ADC12MEM27_L); /* ADC12 Conversion Memory 27 */
+sfr_b(ADC12MEM27_H); /* ADC12 Conversion Memory 27 */
+sfr_w(ADC12MEM28); /* ADC12 Conversion Memory 28 */
+sfr_b(ADC12MEM28_L); /* ADC12 Conversion Memory 28 */
+sfr_b(ADC12MEM28_H); /* ADC12 Conversion Memory 28 */
+sfr_w(ADC12MEM29); /* ADC12 Conversion Memory 29 */
+sfr_b(ADC12MEM29_L); /* ADC12 Conversion Memory 29 */
+sfr_b(ADC12MEM29_H); /* ADC12 Conversion Memory 29 */
+sfr_w(ADC12MEM30); /* ADC12 Conversion Memory 30 */
+sfr_b(ADC12MEM30_L); /* ADC12 Conversion Memory 30 */
+sfr_b(ADC12MEM30_H); /* ADC12 Conversion Memory 30 */
+sfr_w(ADC12MEM31); /* ADC12 Conversion Memory 31 */
+sfr_b(ADC12MEM31_L); /* ADC12 Conversion Memory 31 */
+sfr_b(ADC12MEM31_H); /* ADC12 Conversion Memory 31 */
+#define ADC12MEM_ ADC12MEM /* ADC12 Conversion Memory */
+#ifndef __STDC__
+#define ADC12MEM ADC12MEM0 /* ADC12 Conversion Memory (for assembler) */
+#else
+#define ADC12MEM ((volatile int*) &ADC12MEM0) /* ADC12 Conversion Memory (for C) */
+#endif
+
+/* ADC12CTL0 Control Bits */
+#define ADC12SC (0x0001) /* ADC12 Start Conversion */
+#define ADC12ENC (0x0002) /* ADC12 Enable Conversion */
+#define ADC12ON (0x0010) /* ADC12 On/enable */
+#define ADC12MSC (0x0080) /* ADC12 Multiple SampleConversion */
+#define ADC12SHT00 (0x0100) /* ADC12 Sample Hold 0 Select Bit: 0 */
+#define ADC12SHT01 (0x0200) /* ADC12 Sample Hold 0 Select Bit: 1 */
+#define ADC12SHT02 (0x0400) /* ADC12 Sample Hold 0 Select Bit: 2 */
+#define ADC12SHT03 (0x0800) /* ADC12 Sample Hold 0 Select Bit: 3 */
+#define ADC12SHT10 (0x1000) /* ADC12 Sample Hold 1 Select Bit: 0 */
+#define ADC12SHT11 (0x2000) /* ADC12 Sample Hold 1 Select Bit: 1 */
+#define ADC12SHT12 (0x4000) /* ADC12 Sample Hold 1 Select Bit: 2 */
+#define ADC12SHT13 (0x8000) /* ADC12 Sample Hold 1 Select Bit: 3 */
+
+/* ADC12CTL0 Control Bits */
+#define ADC12SC_L (0x0001) /* ADC12 Start Conversion */
+#define ADC12ENC_L (0x0002) /* ADC12 Enable Conversion */
+#define ADC12ON_L (0x0010) /* ADC12 On/enable */
+#define ADC12MSC_L (0x0080) /* ADC12 Multiple SampleConversion */
+
+/* ADC12CTL0 Control Bits */
+#define ADC12SHT00_H (0x0001) /* ADC12 Sample Hold 0 Select Bit: 0 */
+#define ADC12SHT01_H (0x0002) /* ADC12 Sample Hold 0 Select Bit: 1 */
+#define ADC12SHT02_H (0x0004) /* ADC12 Sample Hold 0 Select Bit: 2 */
+#define ADC12SHT03_H (0x0008) /* ADC12 Sample Hold 0 Select Bit: 3 */
+#define ADC12SHT10_H (0x0010) /* ADC12 Sample Hold 1 Select Bit: 0 */
+#define ADC12SHT11_H (0x0020) /* ADC12 Sample Hold 1 Select Bit: 1 */
+#define ADC12SHT12_H (0x0040) /* ADC12 Sample Hold 1 Select Bit: 2 */
+#define ADC12SHT13_H (0x0080) /* ADC12 Sample Hold 1 Select Bit: 3 */
+
+#define ADC12SHT0_0 (0x0000) /* ADC12 Sample Hold 0 Select Bit: 0 */
+#define ADC12SHT0_1 (0x0100) /* ADC12 Sample Hold 0 Select Bit: 1 */
+#define ADC12SHT0_2 (0x0200) /* ADC12 Sample Hold 0 Select Bit: 2 */
+#define ADC12SHT0_3 (0x0300) /* ADC12 Sample Hold 0 Select Bit: 3 */
+#define ADC12SHT0_4 (0x0400) /* ADC12 Sample Hold 0 Select Bit: 4 */
+#define ADC12SHT0_5 (0x0500) /* ADC12 Sample Hold 0 Select Bit: 5 */
+#define ADC12SHT0_6 (0x0600) /* ADC12 Sample Hold 0 Select Bit: 6 */
+#define ADC12SHT0_7 (0x0700) /* ADC12 Sample Hold 0 Select Bit: 7 */
+#define ADC12SHT0_8 (0x0800) /* ADC12 Sample Hold 0 Select Bit: 8 */
+#define ADC12SHT0_9 (0x0900) /* ADC12 Sample Hold 0 Select Bit: 9 */
+#define ADC12SHT0_10 (0x0A00) /* ADC12 Sample Hold 0 Select Bit: 10 */
+#define ADC12SHT0_11 (0x0B00) /* ADC12 Sample Hold 0 Select Bit: 11 */
+#define ADC12SHT0_12 (0x0C00) /* ADC12 Sample Hold 0 Select Bit: 12 */
+#define ADC12SHT0_13 (0x0D00) /* ADC12 Sample Hold 0 Select Bit: 13 */
+#define ADC12SHT0_14 (0x0E00) /* ADC12 Sample Hold 0 Select Bit: 14 */
+#define ADC12SHT0_15 (0x0F00) /* ADC12 Sample Hold 0 Select Bit: 15 */
+
+#define ADC12SHT1_0 (0x0000) /* ADC12 Sample Hold 1 Select Bit: 0 */
+#define ADC12SHT1_1 (0x1000) /* ADC12 Sample Hold 1 Select Bit: 1 */
+#define ADC12SHT1_2 (0x2000) /* ADC12 Sample Hold 1 Select Bit: 2 */
+#define ADC12SHT1_3 (0x3000) /* ADC12 Sample Hold 1 Select Bit: 3 */
+#define ADC12SHT1_4 (0x4000) /* ADC12 Sample Hold 1 Select Bit: 4 */
+#define ADC12SHT1_5 (0x5000) /* ADC12 Sample Hold 1 Select Bit: 5 */
+#define ADC12SHT1_6 (0x6000) /* ADC12 Sample Hold 1 Select Bit: 6 */
+#define ADC12SHT1_7 (0x7000) /* ADC12 Sample Hold 1 Select Bit: 7 */
+#define ADC12SHT1_8 (0x8000) /* ADC12 Sample Hold 1 Select Bit: 8 */
+#define ADC12SHT1_9 (0x9000) /* ADC12 Sample Hold 1 Select Bit: 9 */
+#define ADC12SHT1_10 (0xA000) /* ADC12 Sample Hold 1 Select Bit: 10 */
+#define ADC12SHT1_11 (0xB000) /* ADC12 Sample Hold 1 Select Bit: 11 */
+#define ADC12SHT1_12 (0xC000) /* ADC12 Sample Hold 1 Select Bit: 12 */
+#define ADC12SHT1_13 (0xD000) /* ADC12 Sample Hold 1 Select Bit: 13 */
+#define ADC12SHT1_14 (0xE000) /* ADC12 Sample Hold 1 Select Bit: 14 */
+#define ADC12SHT1_15 (0xF000) /* ADC12 Sample Hold 1 Select Bit: 15 */
+
+/* ADC12CTL1 Control Bits */
+#define ADC12BUSY (0x0001) /* ADC12 Busy */
+#define ADC12CONSEQ0 (0x0002) /* ADC12 Conversion Sequence Select Bit: 0 */
+#define ADC12CONSEQ1 (0x0004) /* ADC12 Conversion Sequence Select Bit: 1 */
+#define ADC12SSEL0 (0x0008) /* ADC12 Clock Source Select Bit: 0 */
+#define ADC12SSEL1 (0x0010) /* ADC12 Clock Source Select Bit: 1 */
+#define ADC12DIV0 (0x0020) /* ADC12 Clock Divider Select Bit: 0 */
+#define ADC12DIV1 (0x0040) /* ADC12 Clock Divider Select Bit: 1 */
+#define ADC12DIV2 (0x0080) /* ADC12 Clock Divider Select Bit: 2 */
+#define ADC12ISSH (0x0100) /* ADC12 Invert Sample Hold Signal */
+#define ADC12SHP (0x0200) /* ADC12 Sample/Hold Pulse Mode */
+#define ADC12SHS0 (0x0400) /* ADC12 Sample/Hold Source Bit: 0 */
+#define ADC12SHS1 (0x0800) /* ADC12 Sample/Hold Source Bit: 1 */
+#define ADC12SHS2 (0x1000) /* ADC12 Sample/Hold Source Bit: 2 */
+#define ADC12PDIV0 (0x2000) /* ADC12 Predivider Bit: 0 */
+#define ADC12PDIV1 (0x4000) /* ADC12 Predivider Bit: 1 */
+
+/* ADC12CTL1 Control Bits */
+#define ADC12BUSY_L (0x0001) /* ADC12 Busy */
+#define ADC12CONSEQ0_L (0x0002) /* ADC12 Conversion Sequence Select Bit: 0 */
+#define ADC12CONSEQ1_L (0x0004) /* ADC12 Conversion Sequence Select Bit: 1 */
+#define ADC12SSEL0_L (0x0008) /* ADC12 Clock Source Select Bit: 0 */
+#define ADC12SSEL1_L (0x0010) /* ADC12 Clock Source Select Bit: 1 */
+#define ADC12DIV0_L (0x0020) /* ADC12 Clock Divider Select Bit: 0 */
+#define ADC12DIV1_L (0x0040) /* ADC12 Clock Divider Select Bit: 1 */
+#define ADC12DIV2_L (0x0080) /* ADC12 Clock Divider Select Bit: 2 */
+
+/* ADC12CTL1 Control Bits */
+#define ADC12ISSH_H (0x0001) /* ADC12 Invert Sample Hold Signal */
+#define ADC12SHP_H (0x0002) /* ADC12 Sample/Hold Pulse Mode */
+#define ADC12SHS0_H (0x0004) /* ADC12 Sample/Hold Source Bit: 0 */
+#define ADC12SHS1_H (0x0008) /* ADC12 Sample/Hold Source Bit: 1 */
+#define ADC12SHS2_H (0x0010) /* ADC12 Sample/Hold Source Bit: 2 */
+#define ADC12PDIV0_H (0x0020) /* ADC12 Predivider Bit: 0 */
+#define ADC12PDIV1_H (0x0040) /* ADC12 Predivider Bit: 1 */
+
+#define ADC12CONSEQ_0 (0x0000) /* ADC12 Conversion Sequence Select: 0 */
+#define ADC12CONSEQ_1 (0x0002) /* ADC12 Conversion Sequence Select: 1 */
+#define ADC12CONSEQ_2 (0x0004) /* ADC12 Conversion Sequence Select: 2 */
+#define ADC12CONSEQ_3 (0x0006) /* ADC12 Conversion Sequence Select: 3 */
+
+#define ADC12SSEL_0 (0x0000) /* ADC12 Clock Source Select: 0 */
+#define ADC12SSEL_1 (0x0008) /* ADC12 Clock Source Select: 1 */
+#define ADC12SSEL_2 (0x0010) /* ADC12 Clock Source Select: 2 */
+#define ADC12SSEL_3 (0x0018) /* ADC12 Clock Source Select: 3 */
+
+#define ADC12DIV_0 (0x0000) /* ADC12 Clock Divider Select: 0 */
+#define ADC12DIV_1 (0x0020) /* ADC12 Clock Divider Select: 1 */
+#define ADC12DIV_2 (0x0040) /* ADC12 Clock Divider Select: 2 */
+#define ADC12DIV_3 (0x0060) /* ADC12 Clock Divider Select: 3 */
+#define ADC12DIV_4 (0x0080) /* ADC12 Clock Divider Select: 4 */
+#define ADC12DIV_5 (0x00A0) /* ADC12 Clock Divider Select: 5 */
+#define ADC12DIV_6 (0x00C0) /* ADC12 Clock Divider Select: 6 */
+#define ADC12DIV_7 (0x00E0) /* ADC12 Clock Divider Select: 7 */
+
+#define ADC12SHS_0 (0x0000) /* ADC12 Sample/Hold Source: 0 */
+#define ADC12SHS_1 (0x0400) /* ADC12 Sample/Hold Source: 1 */
+#define ADC12SHS_2 (0x0800) /* ADC12 Sample/Hold Source: 2 */
+#define ADC12SHS_3 (0x0C00) /* ADC12 Sample/Hold Source: 3 */
+#define ADC12SHS_4 (0x1000) /* ADC12 Sample/Hold Source: 4 */
+#define ADC12SHS_5 (0x1400) /* ADC12 Sample/Hold Source: 5 */
+#define ADC12SHS_6 (0x1800) /* ADC12 Sample/Hold Source: 6 */
+#define ADC12SHS_7 (0x1C00) /* ADC12 Sample/Hold Source: 7 */
+
+#define ADC12PDIV_0 (0x0000) /* ADC12 Clock predivider Select 0 */
+#define ADC12PDIV_1 (0x2000) /* ADC12 Clock predivider Select 1 */
+#define ADC12PDIV_2 (0x4000) /* ADC12 Clock predivider Select 2 */
+#define ADC12PDIV_3 (0x6000) /* ADC12 Clock predivider Select 3 */
+#define ADC12PDIV__1 (0x0000) /* ADC12 Clock predivider Select: /1 */
+#define ADC12PDIV__4 (0x2000) /* ADC12 Clock predivider Select: /4 */
+#define ADC12PDIV__32 (0x4000) /* ADC12 Clock predivider Select: /32 */
+#define ADC12PDIV__64 (0x6000) /* ADC12 Clock predivider Select: /64 */
+
+/* ADC12CTL2 Control Bits */
+#define ADC12PWRMD (0x0001) /* ADC12 Power Mode */
+#define ADC12DF (0x0008) /* ADC12 Data Format */
+#define ADC12RES0 (0x0010) /* ADC12 Resolution Bit: 0 */
+#define ADC12RES1 (0x0020) /* ADC12 Resolution Bit: 1 */
+
+/* ADC12CTL2 Control Bits */
+#define ADC12PWRMD_L (0x0001) /* ADC12 Power Mode */
+#define ADC12DF_L (0x0008) /* ADC12 Data Format */
+#define ADC12RES0_L (0x0010) /* ADC12 Resolution Bit: 0 */
+#define ADC12RES1_L (0x0020) /* ADC12 Resolution Bit: 1 */
+
+#define ADC12RES_0 (0x0000) /* ADC12+ Resolution : 8 Bit */
+#define ADC12RES_1 (0x0010) /* ADC12+ Resolution : 10 Bit */
+#define ADC12RES_2 (0x0020) /* ADC12+ Resolution : 12 Bit */
+#define ADC12RES_3 (0x0030) /* ADC12+ Resolution : reserved */
+
+#define ADC12RES__8BIT (0x0000) /* ADC12+ Resolution : 8 Bit */
+#define ADC12RES__10BIT (0x0010) /* ADC12+ Resolution : 10 Bit */
+#define ADC12RES__12BIT (0x0020) /* ADC12+ Resolution : 12 Bit */
+
+/* ADC12CTL3 Control Bits */
+#define ADC12CSTARTADD0 (0x0001) /* ADC12 Conversion Start Address Bit: 0 */
+#define ADC12CSTARTADD1 (0x0002) /* ADC12 Conversion Start Address Bit: 1 */
+#define ADC12CSTARTADD2 (0x0004) /* ADC12 Conversion Start Address Bit: 2 */
+#define ADC12CSTARTADD3 (0x0008) /* ADC12 Conversion Start Address Bit: 3 */
+#define ADC12CSTARTADD4 (0x0010) /* ADC12 Conversion Start Address Bit: 4 */
+#define ADC12BATMAP (0x0040) /* ADC12 Internal AVCC/2 select */
+#define ADC12TCMAP (0x0080) /* ADC12 Internal TempSensor select */
+#define ADC12ICH0MAP (0x0100) /* ADC12 Internal Channel 0 select */
+#define ADC12ICH1MAP (0x0200) /* ADC12 Internal Channel 1 select */
+#define ADC12ICH2MAP (0x0400) /* ADC12 Internal Channel 2 select */
+#define ADC12ICH3MAP (0x0800) /* ADC12 Internal Channel 3 select */
+
+/* ADC12CTL3 Control Bits */
+#define ADC12CSTARTADD0_L (0x0001) /* ADC12 Conversion Start Address Bit: 0 */
+#define ADC12CSTARTADD1_L (0x0002) /* ADC12 Conversion Start Address Bit: 1 */
+#define ADC12CSTARTADD2_L (0x0004) /* ADC12 Conversion Start Address Bit: 2 */
+#define ADC12CSTARTADD3_L (0x0008) /* ADC12 Conversion Start Address Bit: 3 */
+#define ADC12CSTARTADD4_L (0x0010) /* ADC12 Conversion Start Address Bit: 4 */
+#define ADC12BATMAP_L (0x0040) /* ADC12 Internal AVCC/2 select */
+#define ADC12TCMAP_L (0x0080) /* ADC12 Internal TempSensor select */
+
+/* ADC12CTL3 Control Bits */
+#define ADC12ICH0MAP_H (0x0001) /* ADC12 Internal Channel 0 select */
+#define ADC12ICH1MAP_H (0x0002) /* ADC12 Internal Channel 1 select */
+#define ADC12ICH2MAP_H (0x0004) /* ADC12 Internal Channel 2 select */
+#define ADC12ICH3MAP_H (0x0008) /* ADC12 Internal Channel 3 select */
+
+#define ADC12CSTARTADD_0 (0x0000) /* ADC12 Conversion Start Address: 0 */
+#define ADC12CSTARTADD_1 (0x0001) /* ADC12 Conversion Start Address: 1 */
+#define ADC12CSTARTADD_2 (0x0002) /* ADC12 Conversion Start Address: 2 */
+#define ADC12CSTARTADD_3 (0x0003) /* ADC12 Conversion Start Address: 3 */
+#define ADC12CSTARTADD_4 (0x0004) /* ADC12 Conversion Start Address: 4 */
+#define ADC12CSTARTADD_5 (0x0005) /* ADC12 Conversion Start Address: 5 */
+#define ADC12CSTARTADD_6 (0x0006) /* ADC12 Conversion Start Address: 6 */
+#define ADC12CSTARTADD_7 (0x0007) /* ADC12 Conversion Start Address: 7 */
+#define ADC12CSTARTADD_8 (0x0008) /* ADC12 Conversion Start Address: 8 */
+#define ADC12CSTARTADD_9 (0x0009) /* ADC12 Conversion Start Address: 9 */
+#define ADC12CSTARTADD_10 (0x000A) /* ADC12 Conversion Start Address: 10 */
+#define ADC12CSTARTADD_11 (0x000B) /* ADC12 Conversion Start Address: 11 */
+#define ADC12CSTARTADD_12 (0x000C) /* ADC12 Conversion Start Address: 12 */
+#define ADC12CSTARTADD_13 (0x000D) /* ADC12 Conversion Start Address: 13 */
+#define ADC12CSTARTADD_14 (0x000E) /* ADC12 Conversion Start Address: 14 */
+#define ADC12CSTARTADD_15 (0x000F) /* ADC12 Conversion Start Address: 15 */
+#define ADC12CSTARTADD_16 (0x0010) /* ADC12 Conversion Start Address: 16 */
+#define ADC12CSTARTADD_17 (0x0011) /* ADC12 Conversion Start Address: 17 */
+#define ADC12CSTARTADD_18 (0x0012) /* ADC12 Conversion Start Address: 18 */
+#define ADC12CSTARTADD_19 (0x0013) /* ADC12 Conversion Start Address: 19 */
+#define ADC12CSTARTADD_20 (0x0014) /* ADC12 Conversion Start Address: 20 */
+#define ADC12CSTARTADD_21 (0x0015) /* ADC12 Conversion Start Address: 21 */
+#define ADC12CSTARTADD_22 (0x0016) /* ADC12 Conversion Start Address: 22 */
+#define ADC12CSTARTADD_23 (0x0017) /* ADC12 Conversion Start Address: 23 */
+#define ADC12CSTARTADD_24 (0x0018) /* ADC12 Conversion Start Address: 24 */
+#define ADC12CSTARTADD_25 (0x0019) /* ADC12 Conversion Start Address: 25 */
+#define ADC12CSTARTADD_26 (0x001A) /* ADC12 Conversion Start Address: 26 */
+#define ADC12CSTARTADD_27 (0x001B) /* ADC12 Conversion Start Address: 27 */
+#define ADC12CSTARTADD_28 (0x001C) /* ADC12 Conversion Start Address: 28 */
+#define ADC12CSTARTADD_29 (0x001D) /* ADC12 Conversion Start Address: 29 */
+#define ADC12CSTARTADD_30 (0x001E) /* ADC12 Conversion Start Address: 30 */
+#define ADC12CSTARTADD_31 (0x001F) /* ADC12 Conversion Start Address: 31 */
+
+/* ADC12MCTLx Control Bits */
+#define ADC12INCH0 (0x0001) /* ADC12 Input Channel Select Bit 0 */
+#define ADC12INCH1 (0x0002) /* ADC12 Input Channel Select Bit 1 */
+#define ADC12INCH2 (0x0004) /* ADC12 Input Channel Select Bit 2 */
+#define ADC12INCH3 (0x0008) /* ADC12 Input Channel Select Bit 3 */
+#define ADC12INCH4 (0x0010) /* ADC12 Input Channel Select Bit 4 */
+#define ADC12EOS (0x0080) /* ADC12 End of Sequence */
+#define ADC12VRSEL0 (0x0100) /* ADC12 VR Select Bit 0 */
+#define ADC12VRSEL1 (0x0200) /* ADC12 VR Select Bit 1 */
+#define ADC12VRSEL2 (0x0400) /* ADC12 VR Select Bit 2 */
+#define ADC12VRSEL3 (0x0800) /* ADC12 VR Select Bit 3 */
+#define ADC12DIF (0x2000) /* ADC12 Differential mode (only for even Registers) */
+#define ADC12WINC (0x4000) /* ADC12 Comparator window enable */
+
+/* ADC12MCTLx Control Bits */
+#define ADC12INCH0_L (0x0001) /* ADC12 Input Channel Select Bit 0 */
+#define ADC12INCH1_L (0x0002) /* ADC12 Input Channel Select Bit 1 */
+#define ADC12INCH2_L (0x0004) /* ADC12 Input Channel Select Bit 2 */
+#define ADC12INCH3_L (0x0008) /* ADC12 Input Channel Select Bit 3 */
+#define ADC12INCH4_L (0x0010) /* ADC12 Input Channel Select Bit 4 */
+#define ADC12EOS_L (0x0080) /* ADC12 End of Sequence */
+
+/* ADC12MCTLx Control Bits */
+#define ADC12VRSEL0_H (0x0001) /* ADC12 VR Select Bit 0 */
+#define ADC12VRSEL1_H (0x0002) /* ADC12 VR Select Bit 1 */
+#define ADC12VRSEL2_H (0x0004) /* ADC12 VR Select Bit 2 */
+#define ADC12VRSEL3_H (0x0008) /* ADC12 VR Select Bit 3 */
+#define ADC12DIF_H (0x0020) /* ADC12 Differential mode (only for even Registers) */
+#define ADC12WINC_H (0x0040) /* ADC12 Comparator window enable */
+
+#define ADC12INCH_0 (0x0000) /* ADC12 Input Channel 0 */
+#define ADC12INCH_1 (0x0001) /* ADC12 Input Channel 1 */
+#define ADC12INCH_2 (0x0002) /* ADC12 Input Channel 2 */
+#define ADC12INCH_3 (0x0003) /* ADC12 Input Channel 3 */
+#define ADC12INCH_4 (0x0004) /* ADC12 Input Channel 4 */
+#define ADC12INCH_5 (0x0005) /* ADC12 Input Channel 5 */
+#define ADC12INCH_6 (0x0006) /* ADC12 Input Channel 6 */
+#define ADC12INCH_7 (0x0007) /* ADC12 Input Channel 7 */
+#define ADC12INCH_8 (0x0008) /* ADC12 Input Channel 8 */
+#define ADC12INCH_9 (0x0009) /* ADC12 Input Channel 9 */
+#define ADC12INCH_10 (0x000A) /* ADC12 Input Channel 10 */
+#define ADC12INCH_11 (0x000B) /* ADC12 Input Channel 11 */
+#define ADC12INCH_12 (0x000C) /* ADC12 Input Channel 12 */
+#define ADC12INCH_13 (0x000D) /* ADC12 Input Channel 13 */
+#define ADC12INCH_14 (0x000E) /* ADC12 Input Channel 14 */
+#define ADC12INCH_15 (0x000F) /* ADC12 Input Channel 15 */
+#define ADC12INCH_16 (0x0010) /* ADC12 Input Channel 16 */
+#define ADC12INCH_17 (0x0011) /* ADC12 Input Channel 17 */
+#define ADC12INCH_18 (0x0012) /* ADC12 Input Channel 18 */
+#define ADC12INCH_19 (0x0013) /* ADC12 Input Channel 19 */
+#define ADC12INCH_20 (0x0014) /* ADC12 Input Channel 20 */
+#define ADC12INCH_21 (0x0015) /* ADC12 Input Channel 21 */
+#define ADC12INCH_22 (0x0016) /* ADC12 Input Channel 22 */
+#define ADC12INCH_23 (0x0017) /* ADC12 Input Channel 23 */
+#define ADC12INCH_24 (0x0018) /* ADC12 Input Channel 24 */
+#define ADC12INCH_25 (0x0019) /* ADC12 Input Channel 25 */
+#define ADC12INCH_26 (0x001A) /* ADC12 Input Channel 26 */
+#define ADC12INCH_27 (0x001B) /* ADC12 Input Channel 27 */
+#define ADC12INCH_28 (0x001C) /* ADC12 Input Channel 28 */
+#define ADC12INCH_29 (0x001D) /* ADC12 Input Channel 29 */
+#define ADC12INCH_30 (0x001E) /* ADC12 Input Channel 30 */
+#define ADC12INCH_31 (0x001F) /* ADC12 Input Channel 31 */
+
+#define ADC12VRSEL_0 (0x0000) /* ADC12 Select Reference 0 */
+#define ADC12VRSEL_1 (0x0100) /* ADC12 Select Reference 1 */
+#define ADC12VRSEL_2 (0x0200) /* ADC12 Select Reference 2 */
+#define ADC12VRSEL_3 (0x0300) /* ADC12 Select Reference 3 */
+#define ADC12VRSEL_4 (0x0400) /* ADC12 Select Reference 4 */
+#define ADC12VRSEL_5 (0x0500) /* ADC12 Select Reference 5 */
+#define ADC12VRSEL_6 (0x0600) /* ADC12 Select Reference 6 */
+#define ADC12VRSEL_7 (0x0700) /* ADC12 Select Reference 7 */
+#define ADC12VRSEL_8 (0x0800) /* ADC12 Select Reference 8 */
+#define ADC12VRSEL_9 (0x0900) /* ADC12 Select Reference 9 */
+#define ADC12VRSEL_10 (0x0A00) /* ADC12 Select Reference 10 */
+#define ADC12VRSEL_11 (0x0B00) /* ADC12 Select Reference 11 */
+#define ADC12VRSEL_12 (0x0C00) /* ADC12 Select Reference 12 */
+#define ADC12VRSEL_13 (0x0D00) /* ADC12 Select Reference 13 */
+#define ADC12VRSEL_14 (0x0E00) /* ADC12 Select Reference 14 */
+#define ADC12VRSEL_15 (0x0F00) /* ADC12 Select Reference 15 */
+
+/* ADC12HI Control Bits */
+
+/* ADC12LO Control Bits */
+
+/* ADC12IER0 Control Bits */
+#define ADC12IE0 (0x0001) /* ADC12 Memory 0 Interrupt Enable */
+#define ADC12IE1 (0x0002) /* ADC12 Memory 1 Interrupt Enable */
+#define ADC12IE2 (0x0004) /* ADC12 Memory 2 Interrupt Enable */
+#define ADC12IE3 (0x0008) /* ADC12 Memory 3 Interrupt Enable */
+#define ADC12IE4 (0x0010) /* ADC12 Memory 4 Interrupt Enable */
+#define ADC12IE5 (0x0020) /* ADC12 Memory 5 Interrupt Enable */
+#define ADC12IE6 (0x0040) /* ADC12 Memory 6 Interrupt Enable */
+#define ADC12IE7 (0x0080) /* ADC12 Memory 7 Interrupt Enable */
+#define ADC12IE8 (0x0100) /* ADC12 Memory 8 Interrupt Enable */
+#define ADC12IE9 (0x0200) /* ADC12 Memory 9 Interrupt Enable */
+#define ADC12IE10 (0x0400) /* ADC12 Memory 10 Interrupt Enable */
+#define ADC12IE11 (0x0800) /* ADC12 Memory 11 Interrupt Enable */
+#define ADC12IE12 (0x1000) /* ADC12 Memory 12 Interrupt Enable */
+#define ADC12IE13 (0x2000) /* ADC12 Memory 13 Interrupt Enable */
+#define ADC12IE14 (0x4000) /* ADC12 Memory 14 Interrupt Enable */
+#define ADC12IE15 (0x8000) /* ADC12 Memory 15 Interrupt Enable */
+
+/* ADC12IER0 Control Bits */
+#define ADC12IE0_L (0x0001) /* ADC12 Memory 0 Interrupt Enable */
+#define ADC12IE1_L (0x0002) /* ADC12 Memory 1 Interrupt Enable */
+#define ADC12IE2_L (0x0004) /* ADC12 Memory 2 Interrupt Enable */
+#define ADC12IE3_L (0x0008) /* ADC12 Memory 3 Interrupt Enable */
+#define ADC12IE4_L (0x0010) /* ADC12 Memory 4 Interrupt Enable */
+#define ADC12IE5_L (0x0020) /* ADC12 Memory 5 Interrupt Enable */
+#define ADC12IE6_L (0x0040) /* ADC12 Memory 6 Interrupt Enable */
+#define ADC12IE7_L (0x0080) /* ADC12 Memory 7 Interrupt Enable */
+
+/* ADC12IER0 Control Bits */
+#define ADC12IE8_H (0x0001) /* ADC12 Memory 8 Interrupt Enable */
+#define ADC12IE9_H (0x0002) /* ADC12 Memory 9 Interrupt Enable */
+#define ADC12IE10_H (0x0004) /* ADC12 Memory 10 Interrupt Enable */
+#define ADC12IE11_H (0x0008) /* ADC12 Memory 11 Interrupt Enable */
+#define ADC12IE12_H (0x0010) /* ADC12 Memory 12 Interrupt Enable */
+#define ADC12IE13_H (0x0020) /* ADC12 Memory 13 Interrupt Enable */
+#define ADC12IE14_H (0x0040) /* ADC12 Memory 14 Interrupt Enable */
+#define ADC12IE15_H (0x0080) /* ADC12 Memory 15 Interrupt Enable */
+
+/* ADC12IER1 Control Bits */
+#define ADC12IE16 (0x0001) /* ADC12 Memory 16 Interrupt Enable */
+#define ADC12IE17 (0x0002) /* ADC12 Memory 17 Interrupt Enable */
+#define ADC12IE18 (0x0004) /* ADC12 Memory 18 Interrupt Enable */
+#define ADC12IE19 (0x0008) /* ADC12 Memory 19 Interrupt Enable */
+#define ADC12IE20 (0x0010) /* ADC12 Memory 20 Interrupt Enable */
+#define ADC12IE21 (0x0020) /* ADC12 Memory 21 Interrupt Enable */
+#define ADC12IE22 (0x0040) /* ADC12 Memory 22 Interrupt Enable */
+#define ADC12IE23 (0x0080) /* ADC12 Memory 23 Interrupt Enable */
+#define ADC12IE24 (0x0100) /* ADC12 Memory 24 Interrupt Enable */
+#define ADC12IE25 (0x0200) /* ADC12 Memory 25 Interrupt Enable */
+#define ADC12IE26 (0x0400) /* ADC12 Memory 26 Interrupt Enable */
+#define ADC12IE27 (0x0800) /* ADC12 Memory 27 Interrupt Enable */
+#define ADC12IE28 (0x1000) /* ADC12 Memory 28 Interrupt Enable */
+#define ADC12IE29 (0x2000) /* ADC12 Memory 29 Interrupt Enable */
+#define ADC12IE30 (0x4000) /* ADC12 Memory 30 Interrupt Enable */
+#define ADC12IE31 (0x8000) /* ADC12 Memory 31 Interrupt Enable */
+
+/* ADC12IER1 Control Bits */
+#define ADC12IE16_L (0x0001) /* ADC12 Memory 16 Interrupt Enable */
+#define ADC12IE17_L (0x0002) /* ADC12 Memory 17 Interrupt Enable */
+#define ADC12IE18_L (0x0004) /* ADC12 Memory 18 Interrupt Enable */
+#define ADC12IE19_L (0x0008) /* ADC12 Memory 19 Interrupt Enable */
+#define ADC12IE20_L (0x0010) /* ADC12 Memory 20 Interrupt Enable */
+#define ADC12IE21_L (0x0020) /* ADC12 Memory 21 Interrupt Enable */
+#define ADC12IE22_L (0x0040) /* ADC12 Memory 22 Interrupt Enable */
+#define ADC12IE23_L (0x0080) /* ADC12 Memory 23 Interrupt Enable */
+
+/* ADC12IER1 Control Bits */
+#define ADC12IE24_H (0x0001) /* ADC12 Memory 24 Interrupt Enable */
+#define ADC12IE25_H (0x0002) /* ADC12 Memory 25 Interrupt Enable */
+#define ADC12IE26_H (0x0004) /* ADC12 Memory 26 Interrupt Enable */
+#define ADC12IE27_H (0x0008) /* ADC12 Memory 27 Interrupt Enable */
+#define ADC12IE28_H (0x0010) /* ADC12 Memory 28 Interrupt Enable */
+#define ADC12IE29_H (0x0020) /* ADC12 Memory 29 Interrupt Enable */
+#define ADC12IE30_H (0x0040) /* ADC12 Memory 30 Interrupt Enable */
+#define ADC12IE31_H (0x0080) /* ADC12 Memory 31 Interrupt Enable */
+
+/* ADC12IER2 Control Bits */
+#define ADC12INIE (0x0002) /* ADC12 Interrupt enable for the inside of window of the Window comparator */
+#define ADC12LOIE (0x0004) /* ADC12 Interrupt enable for lower threshold of the Window comparator */
+#define ADC12HIIE (0x0008) /* ADC12 Interrupt enable for upper threshold of the Window comparator */
+#define ADC12OVIE (0x0010) /* ADC12 ADC12MEMx Overflow interrupt enable */
+#define ADC12TOVIE (0x0020) /* ADC12 Timer Overflow interrupt enable */
+#define ADC12RDYIE (0x0040) /* ADC12 local buffered reference ready interrupt enable */
+
+/* ADC12IER2 Control Bits */
+#define ADC12INIE_L (0x0002) /* ADC12 Interrupt enable for the inside of window of the Window comparator */
+#define ADC12LOIE_L (0x0004) /* ADC12 Interrupt enable for lower threshold of the Window comparator */
+#define ADC12HIIE_L (0x0008) /* ADC12 Interrupt enable for upper threshold of the Window comparator */
+#define ADC12OVIE_L (0x0010) /* ADC12 ADC12MEMx Overflow interrupt enable */
+#define ADC12TOVIE_L (0x0020) /* ADC12 Timer Overflow interrupt enable */
+#define ADC12RDYIE_L (0x0040) /* ADC12 local buffered reference ready interrupt enable */
+
+/* ADC12IFGR0 Control Bits */
+#define ADC12IFG0 (0x0001) /* ADC12 Memory 0 Interrupt Flag */
+#define ADC12IFG1 (0x0002) /* ADC12 Memory 1 Interrupt Flag */
+#define ADC12IFG2 (0x0004) /* ADC12 Memory 2 Interrupt Flag */
+#define ADC12IFG3 (0x0008) /* ADC12 Memory 3 Interrupt Flag */
+#define ADC12IFG4 (0x0010) /* ADC12 Memory 4 Interrupt Flag */
+#define ADC12IFG5 (0x0020) /* ADC12 Memory 5 Interrupt Flag */
+#define ADC12IFG6 (0x0040) /* ADC12 Memory 6 Interrupt Flag */
+#define ADC12IFG7 (0x0080) /* ADC12 Memory 7 Interrupt Flag */
+#define ADC12IFG8 (0x0100) /* ADC12 Memory 8 Interrupt Flag */
+#define ADC12IFG9 (0x0200) /* ADC12 Memory 9 Interrupt Flag */
+#define ADC12IFG10 (0x0400) /* ADC12 Memory 10 Interrupt Flag */
+#define ADC12IFG11 (0x0800) /* ADC12 Memory 11 Interrupt Flag */
+#define ADC12IFG12 (0x1000) /* ADC12 Memory 12 Interrupt Flag */
+#define ADC12IFG13 (0x2000) /* ADC12 Memory 13 Interrupt Flag */
+#define ADC12IFG14 (0x4000) /* ADC12 Memory 14 Interrupt Flag */
+#define ADC12IFG15 (0x8000) /* ADC12 Memory 15 Interrupt Flag */
+
+/* ADC12IFGR0 Control Bits */
+#define ADC12IFG0_L (0x0001) /* ADC12 Memory 0 Interrupt Flag */
+#define ADC12IFG1_L (0x0002) /* ADC12 Memory 1 Interrupt Flag */
+#define ADC12IFG2_L (0x0004) /* ADC12 Memory 2 Interrupt Flag */
+#define ADC12IFG3_L (0x0008) /* ADC12 Memory 3 Interrupt Flag */
+#define ADC12IFG4_L (0x0010) /* ADC12 Memory 4 Interrupt Flag */
+#define ADC12IFG5_L (0x0020) /* ADC12 Memory 5 Interrupt Flag */
+#define ADC12IFG6_L (0x0040) /* ADC12 Memory 6 Interrupt Flag */
+#define ADC12IFG7_L (0x0080) /* ADC12 Memory 7 Interrupt Flag */
+
+/* ADC12IFGR0 Control Bits */
+#define ADC12IFG8_H (0x0001) /* ADC12 Memory 8 Interrupt Flag */
+#define ADC12IFG9_H (0x0002) /* ADC12 Memory 9 Interrupt Flag */
+#define ADC12IFG10_H (0x0004) /* ADC12 Memory 10 Interrupt Flag */
+#define ADC12IFG11_H (0x0008) /* ADC12 Memory 11 Interrupt Flag */
+#define ADC12IFG12_H (0x0010) /* ADC12 Memory 12 Interrupt Flag */
+#define ADC12IFG13_H (0x0020) /* ADC12 Memory 13 Interrupt Flag */
+#define ADC12IFG14_H (0x0040) /* ADC12 Memory 14 Interrupt Flag */
+#define ADC12IFG15_H (0x0080) /* ADC12 Memory 15 Interrupt Flag */
+
+/* ADC12IFGR1 Control Bits */
+#define ADC12IFG16 (0x0001) /* ADC12 Memory 16 Interrupt Flag */
+#define ADC12IFG17 (0x0002) /* ADC12 Memory 17 Interrupt Flag */
+#define ADC12IFG18 (0x0004) /* ADC12 Memory 18 Interrupt Flag */
+#define ADC12IFG19 (0x0008) /* ADC12 Memory 19 Interrupt Flag */
+#define ADC12IFG20 (0x0010) /* ADC12 Memory 20 Interrupt Flag */
+#define ADC12IFG21 (0x0020) /* ADC12 Memory 21 Interrupt Flag */
+#define ADC12IFG22 (0x0040) /* ADC12 Memory 22 Interrupt Flag */
+#define ADC12IFG23 (0x0080) /* ADC12 Memory 23 Interrupt Flag */
+#define ADC12IFG24 (0x0100) /* ADC12 Memory 24 Interrupt Flag */
+#define ADC12IFG25 (0x0200) /* ADC12 Memory 25 Interrupt Flag */
+#define ADC12IFG26 (0x0400) /* ADC12 Memory 26 Interrupt Flag */
+#define ADC12IFG27 (0x0800) /* ADC12 Memory 27 Interrupt Flag */
+#define ADC12IFG28 (0x1000) /* ADC12 Memory 28 Interrupt Flag */
+#define ADC12IFG29 (0x2000) /* ADC12 Memory 29 Interrupt Flag */
+#define ADC12IFG30 (0x4000) /* ADC12 Memory 30 Interrupt Flag */
+#define ADC12IFG31 (0x8000) /* ADC12 Memory 31 Interrupt Flag */
+
+/* ADC12IFGR1 Control Bits */
+#define ADC12IFG16_L (0x0001) /* ADC12 Memory 16 Interrupt Flag */
+#define ADC12IFG17_L (0x0002) /* ADC12 Memory 17 Interrupt Flag */
+#define ADC12IFG18_L (0x0004) /* ADC12 Memory 18 Interrupt Flag */
+#define ADC12IFG19_L (0x0008) /* ADC12 Memory 19 Interrupt Flag */
+#define ADC12IFG20_L (0x0010) /* ADC12 Memory 20 Interrupt Flag */
+#define ADC12IFG21_L (0x0020) /* ADC12 Memory 21 Interrupt Flag */
+#define ADC12IFG22_L (0x0040) /* ADC12 Memory 22 Interrupt Flag */
+#define ADC12IFG23_L (0x0080) /* ADC12 Memory 23 Interrupt Flag */
+
+/* ADC12IFGR1 Control Bits */
+#define ADC12IFG24_H (0x0001) /* ADC12 Memory 24 Interrupt Flag */
+#define ADC12IFG25_H (0x0002) /* ADC12 Memory 25 Interrupt Flag */
+#define ADC12IFG26_H (0x0004) /* ADC12 Memory 26 Interrupt Flag */
+#define ADC12IFG27_H (0x0008) /* ADC12 Memory 27 Interrupt Flag */
+#define ADC12IFG28_H (0x0010) /* ADC12 Memory 28 Interrupt Flag */
+#define ADC12IFG29_H (0x0020) /* ADC12 Memory 29 Interrupt Flag */
+#define ADC12IFG30_H (0x0040) /* ADC12 Memory 30 Interrupt Flag */
+#define ADC12IFG31_H (0x0080) /* ADC12 Memory 31 Interrupt Flag */
+
+/* ADC12IFGR2 Control Bits */
+#define ADC12INIFG (0x0002) /* ADC12 Interrupt Flag for the inside of window of the Window comparator */
+#define ADC12LOIFG (0x0004) /* ADC12 Interrupt Flag for lower threshold of the Window comparator */
+#define ADC12HIIFG (0x0008) /* ADC12 Interrupt Flag for upper threshold of the Window comparator */
+#define ADC12OVIFG (0x0010) /* ADC12 ADC12MEMx Overflow interrupt Flag */
+#define ADC12TOVIFG (0x0020) /* ADC12 Timer Overflow interrupt Flag */
+#define ADC12RDYIFG (0x0040) /* ADC12 local buffered reference ready interrupt Flag */
+
+/* ADC12IFGR2 Control Bits */
+#define ADC12INIFG_L (0x0002) /* ADC12 Interrupt Flag for the inside of window of the Window comparator */
+#define ADC12LOIFG_L (0x0004) /* ADC12 Interrupt Flag for lower threshold of the Window comparator */
+#define ADC12HIIFG_L (0x0008) /* ADC12 Interrupt Flag for upper threshold of the Window comparator */
+#define ADC12OVIFG_L (0x0010) /* ADC12 ADC12MEMx Overflow interrupt Flag */
+#define ADC12TOVIFG_L (0x0020) /* ADC12 Timer Overflow interrupt Flag */
+#define ADC12RDYIFG_L (0x0040) /* ADC12 local buffered reference ready interrupt Flag */
+
+/* ADC12IV Definitions */
+#define ADC12IV_NONE (0x0000) /* No Interrupt pending */
+#define ADC12IV_ADC12OVIFG (0x0002) /* ADC12OVIFG */
+#define ADC12IV_ADC12TOVIFG (0x0004) /* ADC12TOVIFG */
+#define ADC12IV_ADC12HIIFG (0x0006) /* ADC12HIIFG */
+#define ADC12IV_ADC12LOIFG (0x0008) /* ADC12LOIFG */
+#define ADC12IV_ADC12INIFG (0x000A) /* ADC12INIFG */
+#define ADC12IV_ADC12IFG0 (0x000C) /* ADC12IFG0 */
+#define ADC12IV_ADC12IFG1 (0x000E) /* ADC12IFG1 */
+#define ADC12IV_ADC12IFG2 (0x0010) /* ADC12IFG2 */
+#define ADC12IV_ADC12IFG3 (0x0012) /* ADC12IFG3 */
+#define ADC12IV_ADC12IFG4 (0x0014) /* ADC12IFG4 */
+#define ADC12IV_ADC12IFG5 (0x0016) /* ADC12IFG5 */
+#define ADC12IV_ADC12IFG6 (0x0018) /* ADC12IFG6 */
+#define ADC12IV_ADC12IFG7 (0x001A) /* ADC12IFG7 */
+#define ADC12IV_ADC12IFG8 (0x001C) /* ADC12IFG8 */
+#define ADC12IV_ADC12IFG9 (0x001E) /* ADC12IFG9 */
+#define ADC12IV_ADC12IFG10 (0x0020) /* ADC12IFG10 */
+#define ADC12IV_ADC12IFG11 (0x0022) /* ADC12IFG11 */
+#define ADC12IV_ADC12IFG12 (0x0024) /* ADC12IFG12 */
+#define ADC12IV_ADC12IFG13 (0x0026) /* ADC12IFG13 */
+#define ADC12IV_ADC12IFG14 (0x0028) /* ADC12IFG14 */
+#define ADC12IV_ADC12IFG15 (0x002A) /* ADC12IFG15 */
+#define ADC12IV_ADC12IFG16 (0x002C) /* ADC12IFG16 */
+#define ADC12IV_ADC12IFG17 (0x002E) /* ADC12IFG17 */
+#define ADC12IV_ADC12IFG18 (0x0030) /* ADC12IFG18 */
+#define ADC12IV_ADC12IFG19 (0x0032) /* ADC12IFG19 */
+#define ADC12IV_ADC12IFG20 (0x0034) /* ADC12IFG20 */
+#define ADC12IV_ADC12IFG21 (0x0036) /* ADC12IFG21 */
+#define ADC12IV_ADC12IFG22 (0x0038) /* ADC12IFG22 */
+#define ADC12IV_ADC12IFG23 (0x003A) /* ADC12IFG23 */
+#define ADC12IV_ADC12IFG24 (0x003C) /* ADC12IFG24 */
+#define ADC12IV_ADC12IFG25 (0x003E) /* ADC12IFG25 */
+#define ADC12IV_ADC12IFG26 (0x0040) /* ADC12IFG26 */
+#define ADC12IV_ADC12IFG27 (0x0042) /* ADC12IFG27 */
+#define ADC12IV_ADC12IFG28 (0x0044) /* ADC12IFG28 */
+#define ADC12IV_ADC12IFG29 (0x0046) /* ADC12IFG29 */
+#define ADC12IV_ADC12IFG30 (0x0048) /* ADC12IFG30 */
+#define ADC12IV_ADC12IFG31 (0x004A) /* ADC12IFG31 */
+#define ADC12IV_ADC12RDYIFG (0x004C) /* ADC12RDYIFG */
+
+
+/************************************************************
+* AES256 Accelerator
+************************************************************/
+#define __MSP430_HAS_AES256__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_AES256__ 0x09C0
+#define AES256_BASE __MSP430_BASEADDRESS_AES256__
+
+sfr_w(AESACTL0); /* AES accelerator control register 0 */
+sfr_b(AESACTL0_L); /* AES accelerator control register 0 */
+sfr_b(AESACTL0_H); /* AES accelerator control register 0 */
+sfr_w(AESACTL1); /* AES accelerator control register 1 */
+sfr_b(AESACTL1_L); /* AES accelerator control register 1 */
+sfr_b(AESACTL1_H); /* AES accelerator control register 1 */
+sfr_w(AESASTAT); /* AES accelerator status register */
+sfr_b(AESASTAT_L); /* AES accelerator status register */
+sfr_b(AESASTAT_H); /* AES accelerator status register */
+sfr_w(AESAKEY); /* AES accelerator key register */
+sfr_b(AESAKEY_L); /* AES accelerator key register */
+sfr_b(AESAKEY_H); /* AES accelerator key register */
+sfr_w(AESADIN); /* AES accelerator data in register */
+sfr_b(AESADIN_L); /* AES accelerator data in register */
+sfr_b(AESADIN_H); /* AES accelerator data in register */
+sfr_w(AESADOUT); /* AES accelerator data out register */
+sfr_b(AESADOUT_L); /* AES accelerator data out register */
+sfr_b(AESADOUT_H); /* AES accelerator data out register */
+sfr_w(AESAXDIN); /* AES accelerator XORed data in register */
+sfr_b(AESAXDIN_L); /* AES accelerator XORed data in register */
+sfr_b(AESAXDIN_H); /* AES accelerator XORed data in register */
+sfr_w(AESAXIN); /* AES accelerator XORed data in register (no trigger) */
+sfr_b(AESAXIN_L); /* AES accelerator XORed data in register (no trigger) */
+sfr_b(AESAXIN_H); /* AES accelerator XORed data in register (no trigger) */
+
+/* AESACTL0 Control Bits */
+#define AESOP0 (0x0001) /* AES Operation Bit: 0 */
+#define AESOP1 (0x0002) /* AES Operation Bit: 1 */
+#define AESKL0 (0x0004) /* AES Key length Bit: 0 */
+#define AESKL1 (0x0008) /* AES Key length Bit: 1 */
+#define AESTRIG (0x0010) /* AES Trigger Select */
+#define AESCM0 (0x0020) /* AES Cipher mode select Bit: 0 */
+#define AESCM1 (0x0040) /* AES Cipher mode select Bit: 1 */
+#define AESSWRST (0x0080) /* AES Software Reset */
+#define AESRDYIFG (0x0100) /* AES ready interrupt flag */
+#define AESERRFG (0x0800) /* AES Error Flag */
+#define AESRDYIE (0x1000) /* AES ready interrupt enable*/
+#define AESCMEN (0x8000) /* AES DMA cipher mode enable*/
+
+/* AESACTL0 Control Bits */
+#define AESOP0_L (0x0001) /* AES Operation Bit: 0 */
+#define AESOP1_L (0x0002) /* AES Operation Bit: 1 */
+#define AESKL0_L (0x0004) /* AES Key length Bit: 0 */
+#define AESKL1_L (0x0008) /* AES Key length Bit: 1 */
+#define AESTRIG_L (0x0010) /* AES Trigger Select */
+#define AESCM0_L (0x0020) /* AES Cipher mode select Bit: 0 */
+#define AESCM1_L (0x0040) /* AES Cipher mode select Bit: 1 */
+#define AESSWRST_L (0x0080) /* AES Software Reset */
+
+/* AESACTL0 Control Bits */
+#define AESRDYIFG_H (0x0001) /* AES ready interrupt flag */
+#define AESERRFG_H (0x0008) /* AES Error Flag */
+#define AESRDYIE_H (0x0010) /* AES ready interrupt enable*/
+#define AESCMEN_H (0x0080) /* AES DMA cipher mode enable*/
+
+#define AESOP_0 (0x0000) /* AES Operation: Encrypt */
+#define AESOP_1 (0x0001) /* AES Operation: Decrypt (same Key) */
+#define AESOP_2 (0x0002) /* AES Operation: Generate first round Key */
+#define AESOP_3 (0x0003) /* AES Operation: Decrypt (first round Key) */
+
+#define AESKL_0 (0x0000) /* AES Key length: AES128 */
+#define AESKL_1 (0x0004) /* AES Key length: AES192 */
+#define AESKL_2 (0x0008) /* AES Key length: AES256 */
+#define AESKL__128 (0x0000) /* AES Key length: AES128 */
+#define AESKL__192 (0x0004) /* AES Key length: AES192 */
+#define AESKL__256 (0x0008) /* AES Key length: AES256 */
+
+#define AESCM_0 (0x0000) /* AES Cipher mode select: ECB */
+#define AESCM_1 (0x0020) /* AES Cipher mode select: CBC */
+#define AESCM_2 (0x0040) /* AES Cipher mode select: OFB */
+#define AESCM_3 (0x0060) /* AES Cipher mode select: CFB */
+#define AESCM__ECB (0x0000) /* AES Cipher mode select: ECB */
+#define AESCM__CBC (0x0020) /* AES Cipher mode select: CBC */
+#define AESCM__OFB (0x0040) /* AES Cipher mode select: OFB */
+#define AESCM__CFB (0x0060) /* AES Cipher mode select: CFB */
+
+/* AESACTL1 Control Bits */
+#define AESBLKCNT0 (0x0001) /* AES Cipher Block Counter Bit: 0 */
+#define AESBLKCNT1 (0x0002) /* AES Cipher Block Counter Bit: 1 */
+#define AESBLKCNT2 (0x0004) /* AES Cipher Block Counter Bit: 2 */
+#define AESBLKCNT3 (0x0008) /* AES Cipher Block Counter Bit: 3 */
+#define AESBLKCNT4 (0x0010) /* AES Cipher Block Counter Bit: 4 */
+#define AESBLKCNT5 (0x0020) /* AES Cipher Block Counter Bit: 5 */
+#define AESBLKCNT6 (0x0040) /* AES Cipher Block Counter Bit: 6 */
+#define AESBLKCNT7 (0x0080) /* AES Cipher Block Counter Bit: 7 */
+
+/* AESACTL1 Control Bits */
+#define AESBLKCNT0_L (0x0001) /* AES Cipher Block Counter Bit: 0 */
+#define AESBLKCNT1_L (0x0002) /* AES Cipher Block Counter Bit: 1 */
+#define AESBLKCNT2_L (0x0004) /* AES Cipher Block Counter Bit: 2 */
+#define AESBLKCNT3_L (0x0008) /* AES Cipher Block Counter Bit: 3 */
+#define AESBLKCNT4_L (0x0010) /* AES Cipher Block Counter Bit: 4 */
+#define AESBLKCNT5_L (0x0020) /* AES Cipher Block Counter Bit: 5 */
+#define AESBLKCNT6_L (0x0040) /* AES Cipher Block Counter Bit: 6 */
+#define AESBLKCNT7_L (0x0080) /* AES Cipher Block Counter Bit: 7 */
+
+/* AESASTAT Control Bits */
+#define AESBUSY (0x0001) /* AES Busy */
+#define AESKEYWR (0x0002) /* AES All 16 bytes written to AESAKEY */
+#define AESDINWR (0x0004) /* AES All 16 bytes written to AESADIN */
+#define AESDOUTRD (0x0008) /* AES All 16 bytes read from AESADOUT */
+#define AESKEYCNT0 (0x0010) /* AES Bytes written via AESAKEY Bit: 0 */
+#define AESKEYCNT1 (0x0020) /* AES Bytes written via AESAKEY Bit: 1 */
+#define AESKEYCNT2 (0x0040) /* AES Bytes written via AESAKEY Bit: 2 */
+#define AESKEYCNT3 (0x0080) /* AES Bytes written via AESAKEY Bit: 3 */
+#define AESDINCNT0 (0x0100) /* AES Bytes written via AESADIN Bit: 0 */
+#define AESDINCNT1 (0x0200) /* AES Bytes written via AESADIN Bit: 1 */
+#define AESDINCNT2 (0x0400) /* AES Bytes written via AESADIN Bit: 2 */
+#define AESDINCNT3 (0x0800) /* AES Bytes written via AESADIN Bit: 3 */
+#define AESDOUTCNT0 (0x1000) /* AES Bytes read via AESADOUT Bit: 0 */
+#define AESDOUTCNT1 (0x2000) /* AES Bytes read via AESADOUT Bit: 1 */
+#define AESDOUTCNT2 (0x4000) /* AES Bytes read via AESADOUT Bit: 2 */
+#define AESDOUTCNT3 (0x8000) /* AES Bytes read via AESADOUT Bit: 3 */
+
+/* AESASTAT Control Bits */
+#define AESBUSY_L (0x0001) /* AES Busy */
+#define AESKEYWR_L (0x0002) /* AES All 16 bytes written to AESAKEY */
+#define AESDINWR_L (0x0004) /* AES All 16 bytes written to AESADIN */
+#define AESDOUTRD_L (0x0008) /* AES All 16 bytes read from AESADOUT */
+#define AESKEYCNT0_L (0x0010) /* AES Bytes written via AESAKEY Bit: 0 */
+#define AESKEYCNT1_L (0x0020) /* AES Bytes written via AESAKEY Bit: 1 */
+#define AESKEYCNT2_L (0x0040) /* AES Bytes written via AESAKEY Bit: 2 */
+#define AESKEYCNT3_L (0x0080) /* AES Bytes written via AESAKEY Bit: 3 */
+
+/* AESASTAT Control Bits */
+#define AESDINCNT0_H (0x0001) /* AES Bytes written via AESADIN Bit: 0 */
+#define AESDINCNT1_H (0x0002) /* AES Bytes written via AESADIN Bit: 1 */
+#define AESDINCNT2_H (0x0004) /* AES Bytes written via AESADIN Bit: 2 */
+#define AESDINCNT3_H (0x0008) /* AES Bytes written via AESADIN Bit: 3 */
+#define AESDOUTCNT0_H (0x0010) /* AES Bytes read via AESADOUT Bit: 0 */
+#define AESDOUTCNT1_H (0x0020) /* AES Bytes read via AESADOUT Bit: 1 */
+#define AESDOUTCNT2_H (0x0040) /* AES Bytes read via AESADOUT Bit: 2 */
+#define AESDOUTCNT3_H (0x0080) /* AES Bytes read via AESADOUT Bit: 3 */
+
+/************************************************************
+* Capacitive_Touch_IO 0
+************************************************************/
+#define __MSP430_HAS_CAP_TOUCH_IO_0__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_CAP_TOUCH_IO_0__ 0x0430
+#define CAP_TOUCH_0_BASE __MSP430_BASEADDRESS_CAP_TOUCH_IO_0__
+
+sfr_w(CAPTIO0CTL); /* Capacitive_Touch_IO 0 control register */
+sfr_b(CAPTIO0CTL_L); /* Capacitive_Touch_IO 0 control register */
+sfr_b(CAPTIO0CTL_H); /* Capacitive_Touch_IO 0 control register */
+
+#define CAPSIO0CTL CAPTIO0CTL /* legacy define */
+
+/************************************************************
+* Capacitive_Touch_IO 1
+************************************************************/
+#define __MSP430_HAS_CAP_TOUCH_IO_1__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_CAP_TOUCH_IO_1__ 0x0470
+#define CAP_TOUCH_1_BASE __MSP430_BASEADDRESS_CAP_TOUCH_IO_1__
+
+sfr_w(CAPTIO1CTL); /* Capacitive_Touch_IO 1 control register */
+sfr_b(CAPTIO1CTL_L); /* Capacitive_Touch_IO 1 control register */
+sfr_b(CAPTIO1CTL_H); /* Capacitive_Touch_IO 1 control register */
+
+#define CAPSIO1CTL CAPTIO1CTL /* legacy define */
+
+/* CAPTIOxCTL Control Bits */
+#define CAPTIOPISEL0 (0x0002) /* CapTouchIO Pin Select Bit: 0 */
+#define CAPTIOPISEL1 (0x0004) /* CapTouchIO Pin Select Bit: 1 */
+#define CAPTIOPISEL2 (0x0008) /* CapTouchIO Pin Select Bit: 2 */
+#define CAPTIOPOSEL0 (0x0010) /* CapTouchIO Port Select Bit: 0 */
+#define CAPTIOPOSEL1 (0x0020) /* CapTouchIO Port Select Bit: 1 */
+#define CAPTIOPOSEL2 (0x0040) /* CapTouchIO Port Select Bit: 2 */
+#define CAPTIOPOSEL3 (0x0080) /* CapTouchIO Port Select Bit: 3 */
+#define CAPTIOEN (0x0100) /* CapTouchIO Enable */
+#define CAPTIO (0x0200) /* CapTouchIO state */
+
+/* CAPTIOxCTL Control Bits */
+#define CAPTIOPISEL0_L (0x0002) /* CapTouchIO Pin Select Bit: 0 */
+#define CAPTIOPISEL1_L (0x0004) /* CapTouchIO Pin Select Bit: 1 */
+#define CAPTIOPISEL2_L (0x0008) /* CapTouchIO Pin Select Bit: 2 */
+#define CAPTIOPOSEL0_L (0x0010) /* CapTouchIO Port Select Bit: 0 */
+#define CAPTIOPOSEL1_L (0x0020) /* CapTouchIO Port Select Bit: 1 */
+#define CAPTIOPOSEL2_L (0x0040) /* CapTouchIO Port Select Bit: 2 */
+#define CAPTIOPOSEL3_L (0x0080) /* CapTouchIO Port Select Bit: 3 */
+
+/* CAPTIOxCTL Control Bits */
+#define CAPTIOEN_H (0x0001) /* CapTouchIO Enable */
+#define CAPTIO_H (0x0002) /* CapTouchIO state */
+
+/* Legacy defines */
+#define CAPSIOPISEL0 (0x0002) /* CapTouchIO Pin Select Bit: 0 */
+#define CAPSIOPISEL1 (0x0004) /* CapTouchIO Pin Select Bit: 1 */
+#define CAPSIOPISEL2 (0x0008) /* CapTouchIO Pin Select Bit: 2 */
+#define CAPSIOPOSEL0 (0x0010) /* CapTouchIO Port Select Bit: 0 */
+#define CAPSIOPOSEL1 (0x0020) /* CapTouchIO Port Select Bit: 1 */
+#define CAPSIOPOSEL2 (0x0040) /* CapTouchIO Port Select Bit: 2 */
+#define CAPSIOPOSEL3 (0x0080) /* CapTouchIO Port Select Bit: 3 */
+#define CAPSIOEN (0x0100) /* CapTouchIO Enable */
+#define CAPSIO (0x0200) /* CapTouchIO state */
+
+/************************************************************
+* Comparator E
+************************************************************/
+#define __MSP430_HAS_COMP_E__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_COMP_E__ 0x08C0
+#define COMP_E_BASE __MSP430_BASEADDRESS_COMP_E__
+
+sfr_w(CECTL0); /* Comparator E Control Register 0 */
+sfr_b(CECTL0_L); /* Comparator E Control Register 0 */
+sfr_b(CECTL0_H); /* Comparator E Control Register 0 */
+sfr_w(CECTL1); /* Comparator E Control Register 1 */
+sfr_b(CECTL1_L); /* Comparator E Control Register 1 */
+sfr_b(CECTL1_H); /* Comparator E Control Register 1 */
+sfr_w(CECTL2); /* Comparator E Control Register 2 */
+sfr_b(CECTL2_L); /* Comparator E Control Register 2 */
+sfr_b(CECTL2_H); /* Comparator E Control Register 2 */
+sfr_w(CECTL3); /* Comparator E Control Register 3 */
+sfr_b(CECTL3_L); /* Comparator E Control Register 3 */
+sfr_b(CECTL3_H); /* Comparator E Control Register 3 */
+sfr_w(CEINT); /* Comparator E Interrupt Register */
+sfr_b(CEINT_L); /* Comparator E Interrupt Register */
+sfr_b(CEINT_H); /* Comparator E Interrupt Register */
+sfr_w(CEIV); /* Comparator E Interrupt Vector Word */
+sfr_b(CEIV_L); /* Comparator E Interrupt Vector Word */
+sfr_b(CEIV_H); /* Comparator E Interrupt Vector Word */
+
+/* CECTL0 Control Bits */
+#define CEIPSEL0 (0x0001) /* Comp. E Pos. Channel Input Select 0 */
+#define CEIPSEL1 (0x0002) /* Comp. E Pos. Channel Input Select 1 */
+#define CEIPSEL2 (0x0004) /* Comp. E Pos. Channel Input Select 2 */
+#define CEIPSEL3 (0x0008) /* Comp. E Pos. Channel Input Select 3 */
+//#define RESERVED (0x0010) /* Comp. E */
+//#define RESERVED (0x0020) /* Comp. E */
+//#define RESERVED (0x0040) /* Comp. E */
+#define CEIPEN (0x0080) /* Comp. E Pos. Channel Input Enable */
+#define CEIMSEL0 (0x0100) /* Comp. E Neg. Channel Input Select 0 */
+#define CEIMSEL1 (0x0200) /* Comp. E Neg. Channel Input Select 1 */
+#define CEIMSEL2 (0x0400) /* Comp. E Neg. Channel Input Select 2 */
+#define CEIMSEL3 (0x0800) /* Comp. E Neg. Channel Input Select 3 */
+//#define RESERVED (0x1000) /* Comp. E */
+//#define RESERVED (0x2000) /* Comp. E */
+//#define RESERVED (0x4000) /* Comp. E */
+#define CEIMEN (0x8000) /* Comp. E Neg. Channel Input Enable */
+
+/* CECTL0 Control Bits */
+#define CEIPSEL0_L (0x0001) /* Comp. E Pos. Channel Input Select 0 */
+#define CEIPSEL1_L (0x0002) /* Comp. E Pos. Channel Input Select 1 */
+#define CEIPSEL2_L (0x0004) /* Comp. E Pos. Channel Input Select 2 */
+#define CEIPSEL3_L (0x0008) /* Comp. E Pos. Channel Input Select 3 */
+//#define RESERVED (0x0010) /* Comp. E */
+//#define RESERVED (0x0020) /* Comp. E */
+//#define RESERVED (0x0040) /* Comp. E */
+#define CEIPEN_L (0x0080) /* Comp. E Pos. Channel Input Enable */
+//#define RESERVED (0x1000) /* Comp. E */
+//#define RESERVED (0x2000) /* Comp. E */
+//#define RESERVED (0x4000) /* Comp. E */
+
+/* CECTL0 Control Bits */
+//#define RESERVED (0x0010) /* Comp. E */
+//#define RESERVED (0x0020) /* Comp. E */
+//#define RESERVED (0x0040) /* Comp. E */
+#define CEIMSEL0_H (0x0001) /* Comp. E Neg. Channel Input Select 0 */
+#define CEIMSEL1_H (0x0002) /* Comp. E Neg. Channel Input Select 1 */
+#define CEIMSEL2_H (0x0004) /* Comp. E Neg. Channel Input Select 2 */
+#define CEIMSEL3_H (0x0008) /* Comp. E Neg. Channel Input Select 3 */
+//#define RESERVED (0x1000) /* Comp. E */
+//#define RESERVED (0x2000) /* Comp. E */
+//#define RESERVED (0x4000) /* Comp. E */
+#define CEIMEN_H (0x0080) /* Comp. E Neg. Channel Input Enable */
+
+#define CEIPSEL_0 (0x0000) /* Comp. E V+ terminal Input Select: Channel 0 */
+#define CEIPSEL_1 (0x0001) /* Comp. E V+ terminal Input Select: Channel 1 */
+#define CEIPSEL_2 (0x0002) /* Comp. E V+ terminal Input Select: Channel 2 */
+#define CEIPSEL_3 (0x0003) /* Comp. E V+ terminal Input Select: Channel 3 */
+#define CEIPSEL_4 (0x0004) /* Comp. E V+ terminal Input Select: Channel 4 */
+#define CEIPSEL_5 (0x0005) /* Comp. E V+ terminal Input Select: Channel 5 */
+#define CEIPSEL_6 (0x0006) /* Comp. E V+ terminal Input Select: Channel 6 */
+#define CEIPSEL_7 (0x0007) /* Comp. E V+ terminal Input Select: Channel 7 */
+#define CEIPSEL_8 (0x0008) /* Comp. E V+ terminal Input Select: Channel 8 */
+#define CEIPSEL_9 (0x0009) /* Comp. E V+ terminal Input Select: Channel 9 */
+#define CEIPSEL_10 (0x000A) /* Comp. E V+ terminal Input Select: Channel 10 */
+#define CEIPSEL_11 (0x000B) /* Comp. E V+ terminal Input Select: Channel 11 */
+#define CEIPSEL_12 (0x000C) /* Comp. E V+ terminal Input Select: Channel 12 */
+#define CEIPSEL_13 (0x000D) /* Comp. E V+ terminal Input Select: Channel 13 */
+#define CEIPSEL_14 (0x000E) /* Comp. E V+ terminal Input Select: Channel 14 */
+#define CEIPSEL_15 (0x000F) /* Comp. E V+ terminal Input Select: Channel 15 */
+
+#define CEIMSEL_0 (0x0000) /* Comp. E V- Terminal Input Select: Channel 0 */
+#define CEIMSEL_1 (0x0100) /* Comp. E V- Terminal Input Select: Channel 1 */
+#define CEIMSEL_2 (0x0200) /* Comp. E V- Terminal Input Select: Channel 2 */
+#define CEIMSEL_3 (0x0300) /* Comp. E V- Terminal Input Select: Channel 3 */
+#define CEIMSEL_4 (0x0400) /* Comp. E V- Terminal Input Select: Channel 4 */
+#define CEIMSEL_5 (0x0500) /* Comp. E V- Terminal Input Select: Channel 5 */
+#define CEIMSEL_6 (0x0600) /* Comp. E V- Terminal Input Select: Channel 6 */
+#define CEIMSEL_7 (0x0700) /* Comp. E V- Terminal Input Select: Channel 7 */
+#define CEIMSEL_8 (0x0800) /* Comp. E V- terminal Input Select: Channel 8 */
+#define CEIMSEL_9 (0x0900) /* Comp. E V- terminal Input Select: Channel 9 */
+#define CEIMSEL_10 (0x0A00) /* Comp. E V- terminal Input Select: Channel 10 */
+#define CEIMSEL_11 (0x0B00) /* Comp. E V- terminal Input Select: Channel 11 */
+#define CEIMSEL_12 (0x0C00) /* Comp. E V- terminal Input Select: Channel 12 */
+#define CEIMSEL_13 (0x0D00) /* Comp. E V- terminal Input Select: Channel 13 */
+#define CEIMSEL_14 (0x0E00) /* Comp. E V- terminal Input Select: Channel 14 */
+#define CEIMSEL_15 (0x0F00) /* Comp. E V- terminal Input Select: Channel 15 */
+
+/* CECTL1 Control Bits */
+#define CEOUT (0x0001) /* Comp. E Output */
+#define CEOUTPOL (0x0002) /* Comp. E Output Polarity */
+#define CEF (0x0004) /* Comp. E Enable Output Filter */
+#define CEIES (0x0008) /* Comp. E Interrupt Edge Select */
+#define CESHORT (0x0010) /* Comp. E Input Short */
+#define CEEX (0x0020) /* Comp. E Exchange Inputs */
+#define CEFDLY0 (0x0040) /* Comp. E Filter delay Bit 0 */
+#define CEFDLY1 (0x0080) /* Comp. E Filter delay Bit 1 */
+#define CEPWRMD0 (0x0100) /* Comp. E Power mode Bit 0 */
+#define CEPWRMD1 (0x0200) /* Comp. E Power mode Bit 1 */
+#define CEON (0x0400) /* Comp. E enable */
+#define CEMRVL (0x0800) /* Comp. E CEMRV Level */
+#define CEMRVS (0x1000) /* Comp. E Output selects between VREF0 or VREF1*/
+//#define RESERVED (0x2000) /* Comp. E */
+//#define RESERVED (0x4000) /* Comp. E */
+//#define RESERVED (0x8000) /* Comp. E */
+
+/* CECTL1 Control Bits */
+#define CEOUT_L (0x0001) /* Comp. E Output */
+#define CEOUTPOL_L (0x0002) /* Comp. E Output Polarity */
+#define CEF_L (0x0004) /* Comp. E Enable Output Filter */
+#define CEIES_L (0x0008) /* Comp. E Interrupt Edge Select */
+#define CESHORT_L (0x0010) /* Comp. E Input Short */
+#define CEEX_L (0x0020) /* Comp. E Exchange Inputs */
+#define CEFDLY0_L (0x0040) /* Comp. E Filter delay Bit 0 */
+#define CEFDLY1_L (0x0080) /* Comp. E Filter delay Bit 1 */
+//#define RESERVED (0x2000) /* Comp. E */
+//#define RESERVED (0x4000) /* Comp. E */
+//#define RESERVED (0x8000) /* Comp. E */
+
+/* CECTL1 Control Bits */
+#define CEPWRMD0_H (0x0001) /* Comp. E Power mode Bit 0 */
+#define CEPWRMD1_H (0x0002) /* Comp. E Power mode Bit 1 */
+#define CEON_H (0x0004) /* Comp. E enable */
+#define CEMRVL_H (0x0008) /* Comp. E CEMRV Level */
+#define CEMRVS_H (0x0010) /* Comp. E Output selects between VREF0 or VREF1*/
+//#define RESERVED (0x2000) /* Comp. E */
+//#define RESERVED (0x4000) /* Comp. E */
+//#define RESERVED (0x8000) /* Comp. E */
+
+#define CEPWRMD_0 (0x0000) /* Comp. E Power mode 0 */
+#define CEPWRMD_1 (0x0100) /* Comp. E Power mode 1 */
+#define CEPWRMD_2 (0x0200) /* Comp. E Power mode 2 */
+#define CEPWRMD_3 (0x0300) /* Comp. E Power mode 3*/
+
+#define CEFDLY_0 (0x0000) /* Comp. E Filter delay 0 : 450ns */
+#define CEFDLY_1 (0x0040) /* Comp. E Filter delay 1 : 900ns */
+#define CEFDLY_2 (0x0080) /* Comp. E Filter delay 2 : 1800ns */
+#define CEFDLY_3 (0x00C0) /* Comp. E Filter delay 3 : 3600ns */
+
+/* CECTL2 Control Bits */
+#define CEREF00 (0x0001) /* Comp. E Reference 0 Resistor Select Bit : 0 */
+#define CEREF01 (0x0002) /* Comp. E Reference 0 Resistor Select Bit : 1 */
+#define CEREF02 (0x0004) /* Comp. E Reference 0 Resistor Select Bit : 2 */
+#define CEREF03 (0x0008) /* Comp. E Reference 0 Resistor Select Bit : 3 */
+#define CEREF04 (0x0010) /* Comp. E Reference 0 Resistor Select Bit : 4 */
+#define CERSEL (0x0020) /* Comp. E Reference select */
+#define CERS0 (0x0040) /* Comp. E Reference Source Bit : 0 */
+#define CERS1 (0x0080) /* Comp. E Reference Source Bit : 1 */
+#define CEREF10 (0x0100) /* Comp. E Reference 1 Resistor Select Bit : 0 */
+#define CEREF11 (0x0200) /* Comp. E Reference 1 Resistor Select Bit : 1 */
+#define CEREF12 (0x0400) /* Comp. E Reference 1 Resistor Select Bit : 2 */
+#define CEREF13 (0x0800) /* Comp. E Reference 1 Resistor Select Bit : 3 */
+#define CEREF14 (0x1000) /* Comp. E Reference 1 Resistor Select Bit : 4 */
+#define CEREFL0 (0x2000) /* Comp. E Reference voltage level Bit : 0 */
+#define CEREFL1 (0x4000) /* Comp. E Reference voltage level Bit : 1 */
+#define CEREFACC (0x8000) /* Comp. E Reference Accuracy */
+
+/* CECTL2 Control Bits */
+#define CEREF00_L (0x0001) /* Comp. E Reference 0 Resistor Select Bit : 0 */
+#define CEREF01_L (0x0002) /* Comp. E Reference 0 Resistor Select Bit : 1 */
+#define CEREF02_L (0x0004) /* Comp. E Reference 0 Resistor Select Bit : 2 */
+#define CEREF03_L (0x0008) /* Comp. E Reference 0 Resistor Select Bit : 3 */
+#define CEREF04_L (0x0010) /* Comp. E Reference 0 Resistor Select Bit : 4 */
+#define CERSEL_L (0x0020) /* Comp. E Reference select */
+#define CERS0_L (0x0040) /* Comp. E Reference Source Bit : 0 */
+#define CERS1_L (0x0080) /* Comp. E Reference Source Bit : 1 */
+
+/* CECTL2 Control Bits */
+#define CEREF10_H (0x0001) /* Comp. E Reference 1 Resistor Select Bit : 0 */
+#define CEREF11_H (0x0002) /* Comp. E Reference 1 Resistor Select Bit : 1 */
+#define CEREF12_H (0x0004) /* Comp. E Reference 1 Resistor Select Bit : 2 */
+#define CEREF13_H (0x0008) /* Comp. E Reference 1 Resistor Select Bit : 3 */
+#define CEREF14_H (0x0010) /* Comp. E Reference 1 Resistor Select Bit : 4 */
+#define CEREFL0_H (0x0020) /* Comp. E Reference voltage level Bit : 0 */
+#define CEREFL1_H (0x0040) /* Comp. E Reference voltage level Bit : 1 */
+#define CEREFACC_H (0x0080) /* Comp. E Reference Accuracy */
+
+#define CEREF0_0 (0x0000) /* Comp. E Int. Ref.0 Select 0 : 1/32 */
+#define CEREF0_1 (0x0001) /* Comp. E Int. Ref.0 Select 1 : 2/32 */
+#define CEREF0_2 (0x0002) /* Comp. E Int. Ref.0 Select 2 : 3/32 */
+#define CEREF0_3 (0x0003) /* Comp. E Int. Ref.0 Select 3 : 4/32 */
+#define CEREF0_4 (0x0004) /* Comp. E Int. Ref.0 Select 4 : 5/32 */
+#define CEREF0_5 (0x0005) /* Comp. E Int. Ref.0 Select 5 : 6/32 */
+#define CEREF0_6 (0x0006) /* Comp. E Int. Ref.0 Select 6 : 7/32 */
+#define CEREF0_7 (0x0007) /* Comp. E Int. Ref.0 Select 7 : 8/32 */
+#define CEREF0_8 (0x0008) /* Comp. E Int. Ref.0 Select 0 : 9/32 */
+#define CEREF0_9 (0x0009) /* Comp. E Int. Ref.0 Select 1 : 10/32 */
+#define CEREF0_10 (0x000A) /* Comp. E Int. Ref.0 Select 2 : 11/32 */
+#define CEREF0_11 (0x000B) /* Comp. E Int. Ref.0 Select 3 : 12/32 */
+#define CEREF0_12 (0x000C) /* Comp. E Int. Ref.0 Select 4 : 13/32 */
+#define CEREF0_13 (0x000D) /* Comp. E Int. Ref.0 Select 5 : 14/32 */
+#define CEREF0_14 (0x000E) /* Comp. E Int. Ref.0 Select 6 : 15/32 */
+#define CEREF0_15 (0x000F) /* Comp. E Int. Ref.0 Select 7 : 16/32 */
+#define CEREF0_16 (0x0010) /* Comp. E Int. Ref.0 Select 0 : 17/32 */
+#define CEREF0_17 (0x0011) /* Comp. E Int. Ref.0 Select 1 : 18/32 */
+#define CEREF0_18 (0x0012) /* Comp. E Int. Ref.0 Select 2 : 19/32 */
+#define CEREF0_19 (0x0013) /* Comp. E Int. Ref.0 Select 3 : 20/32 */
+#define CEREF0_20 (0x0014) /* Comp. E Int. Ref.0 Select 4 : 21/32 */
+#define CEREF0_21 (0x0015) /* Comp. E Int. Ref.0 Select 5 : 22/32 */
+#define CEREF0_22 (0x0016) /* Comp. E Int. Ref.0 Select 6 : 23/32 */
+#define CEREF0_23 (0x0017) /* Comp. E Int. Ref.0 Select 7 : 24/32 */
+#define CEREF0_24 (0x0018) /* Comp. E Int. Ref.0 Select 0 : 25/32 */
+#define CEREF0_25 (0x0019) /* Comp. E Int. Ref.0 Select 1 : 26/32 */
+#define CEREF0_26 (0x001A) /* Comp. E Int. Ref.0 Select 2 : 27/32 */
+#define CEREF0_27 (0x001B) /* Comp. E Int. Ref.0 Select 3 : 28/32 */
+#define CEREF0_28 (0x001C) /* Comp. E Int. Ref.0 Select 4 : 29/32 */
+#define CEREF0_29 (0x001D) /* Comp. E Int. Ref.0 Select 5 : 30/32 */
+#define CEREF0_30 (0x001E) /* Comp. E Int. Ref.0 Select 6 : 31/32 */
+#define CEREF0_31 (0x001F) /* Comp. E Int. Ref.0 Select 7 : 32/32 */
+
+#define CERS_0 (0x0000) /* Comp. E Reference Source 0 : Off */
+#define CERS_1 (0x0040) /* Comp. E Reference Source 1 : Vcc */
+#define CERS_2 (0x0080) /* Comp. E Reference Source 2 : Shared Ref. */
+#define CERS_3 (0x00C0) /* Comp. E Reference Source 3 : Shared Ref. / Off */
+
+#define CEREF1_0 (0x0000) /* Comp. E Int. Ref.1 Select 0 : 1/32 */
+#define CEREF1_1 (0x0100) /* Comp. E Int. Ref.1 Select 1 : 2/32 */
+#define CEREF1_2 (0x0200) /* Comp. E Int. Ref.1 Select 2 : 3/32 */
+#define CEREF1_3 (0x0300) /* Comp. E Int. Ref.1 Select 3 : 4/32 */
+#define CEREF1_4 (0x0400) /* Comp. E Int. Ref.1 Select 4 : 5/32 */
+#define CEREF1_5 (0x0500) /* Comp. E Int. Ref.1 Select 5 : 6/32 */
+#define CEREF1_6 (0x0600) /* Comp. E Int. Ref.1 Select 6 : 7/32 */
+#define CEREF1_7 (0x0700) /* Comp. E Int. Ref.1 Select 7 : 8/32 */
+#define CEREF1_8 (0x0800) /* Comp. E Int. Ref.1 Select 0 : 9/32 */
+#define CEREF1_9 (0x0900) /* Comp. E Int. Ref.1 Select 1 : 10/32 */
+#define CEREF1_10 (0x0A00) /* Comp. E Int. Ref.1 Select 2 : 11/32 */
+#define CEREF1_11 (0x0B00) /* Comp. E Int. Ref.1 Select 3 : 12/32 */
+#define CEREF1_12 (0x0C00) /* Comp. E Int. Ref.1 Select 4 : 13/32 */
+#define CEREF1_13 (0x0D00) /* Comp. E Int. Ref.1 Select 5 : 14/32 */
+#define CEREF1_14 (0x0E00) /* Comp. E Int. Ref.1 Select 6 : 15/32 */
+#define CEREF1_15 (0x0F00) /* Comp. E Int. Ref.1 Select 7 : 16/32 */
+#define CEREF1_16 (0x1000) /* Comp. E Int. Ref.1 Select 0 : 17/32 */
+#define CEREF1_17 (0x1100) /* Comp. E Int. Ref.1 Select 1 : 18/32 */
+#define CEREF1_18 (0x1200) /* Comp. E Int. Ref.1 Select 2 : 19/32 */
+#define CEREF1_19 (0x1300) /* Comp. E Int. Ref.1 Select 3 : 20/32 */
+#define CEREF1_20 (0x1400) /* Comp. E Int. Ref.1 Select 4 : 21/32 */
+#define CEREF1_21 (0x1500) /* Comp. E Int. Ref.1 Select 5 : 22/32 */
+#define CEREF1_22 (0x1600) /* Comp. E Int. Ref.1 Select 6 : 23/32 */
+#define CEREF1_23 (0x1700) /* Comp. E Int. Ref.1 Select 7 : 24/32 */
+#define CEREF1_24 (0x1800) /* Comp. E Int. Ref.1 Select 0 : 25/32 */
+#define CEREF1_25 (0x1900) /* Comp. E Int. Ref.1 Select 1 : 26/32 */
+#define CEREF1_26 (0x1A00) /* Comp. E Int. Ref.1 Select 2 : 27/32 */
+#define CEREF1_27 (0x1B00) /* Comp. E Int. Ref.1 Select 3 : 28/32 */
+#define CEREF1_28 (0x1C00) /* Comp. E Int. Ref.1 Select 4 : 29/32 */
+#define CEREF1_29 (0x1D00) /* Comp. E Int. Ref.1 Select 5 : 30/32 */
+#define CEREF1_30 (0x1E00) /* Comp. E Int. Ref.1 Select 6 : 31/32 */
+#define CEREF1_31 (0x1F00) /* Comp. E Int. Ref.1 Select 7 : 32/32 */
+
+#define CEREFL_0 (0x0000) /* Comp. E Reference voltage level 0 : None */
+#define CEREFL_1 (0x2000) /* Comp. E Reference voltage level 1 : 1.2V */
+#define CEREFL_2 (0x4000) /* Comp. E Reference voltage level 2 : 2.0V */
+#define CEREFL_3 (0x6000) /* Comp. E Reference voltage level 3 : 2.5V */
+
+#define CEPD0 (0x0001) /* Comp. E Disable Input Buffer of Port Register .0 */
+#define CEPD1 (0x0002) /* Comp. E Disable Input Buffer of Port Register .1 */
+#define CEPD2 (0x0004) /* Comp. E Disable Input Buffer of Port Register .2 */
+#define CEPD3 (0x0008) /* Comp. E Disable Input Buffer of Port Register .3 */
+#define CEPD4 (0x0010) /* Comp. E Disable Input Buffer of Port Register .4 */
+#define CEPD5 (0x0020) /* Comp. E Disable Input Buffer of Port Register .5 */
+#define CEPD6 (0x0040) /* Comp. E Disable Input Buffer of Port Register .6 */
+#define CEPD7 (0x0080) /* Comp. E Disable Input Buffer of Port Register .7 */
+#define CEPD8 (0x0100) /* Comp. E Disable Input Buffer of Port Register .8 */
+#define CEPD9 (0x0200) /* Comp. E Disable Input Buffer of Port Register .9 */
+#define CEPD10 (0x0400) /* Comp. E Disable Input Buffer of Port Register .10 */
+#define CEPD11 (0x0800) /* Comp. E Disable Input Buffer of Port Register .11 */
+#define CEPD12 (0x1000) /* Comp. E Disable Input Buffer of Port Register .12 */
+#define CEPD13 (0x2000) /* Comp. E Disable Input Buffer of Port Register .13 */
+#define CEPD14 (0x4000) /* Comp. E Disable Input Buffer of Port Register .14 */
+#define CEPD15 (0x8000) /* Comp. E Disable Input Buffer of Port Register .15 */
+
+#define CEPD0_L (0x0001) /* Comp. E Disable Input Buffer of Port Register .0 */
+#define CEPD1_L (0x0002) /* Comp. E Disable Input Buffer of Port Register .1 */
+#define CEPD2_L (0x0004) /* Comp. E Disable Input Buffer of Port Register .2 */
+#define CEPD3_L (0x0008) /* Comp. E Disable Input Buffer of Port Register .3 */
+#define CEPD4_L (0x0010) /* Comp. E Disable Input Buffer of Port Register .4 */
+#define CEPD5_L (0x0020) /* Comp. E Disable Input Buffer of Port Register .5 */
+#define CEPD6_L (0x0040) /* Comp. E Disable Input Buffer of Port Register .6 */
+#define CEPD7_L (0x0080) /* Comp. E Disable Input Buffer of Port Register .7 */
+
+#define CEPD8_H (0x0001) /* Comp. E Disable Input Buffer of Port Register .8 */
+#define CEPD9_H (0x0002) /* Comp. E Disable Input Buffer of Port Register .9 */
+#define CEPD10_H (0x0004) /* Comp. E Disable Input Buffer of Port Register .10 */
+#define CEPD11_H (0x0008) /* Comp. E Disable Input Buffer of Port Register .11 */
+#define CEPD12_H (0x0010) /* Comp. E Disable Input Buffer of Port Register .12 */
+#define CEPD13_H (0x0020) /* Comp. E Disable Input Buffer of Port Register .13 */
+#define CEPD14_H (0x0040) /* Comp. E Disable Input Buffer of Port Register .14 */
+#define CEPD15_H (0x0080) /* Comp. E Disable Input Buffer of Port Register .15 */
+
+/* CEINT Control Bits */
+#define CEIFG (0x0001) /* Comp. E Interrupt Flag */
+#define CEIIFG (0x0002) /* Comp. E Interrupt Flag Inverted Polarity */
+//#define RESERVED (0x0004) /* Comp. E */
+//#define RESERVED (0x0008) /* Comp. E */
+#define CERDYIFG (0x0010) /* Comp. E Comparator_E ready interrupt flag */
+//#define RESERVED (0x0020) /* Comp. E */
+//#define RESERVED (0x0040) /* Comp. E */
+//#define RESERVED (0x0080) /* Comp. E */
+#define CEIE (0x0100) /* Comp. E Interrupt Enable */
+#define CEIIE (0x0200) /* Comp. E Interrupt Enable Inverted Polarity */
+//#define RESERVED (0x0400) /* Comp. E */
+//#define RESERVED (0x0800) /* Comp. E */
+#define CERDYIE (0x1000) /* Comp. E Comparator_E ready interrupt enable */
+//#define RESERVED (0x2000) /* Comp. E */
+//#define RESERVED (0x4000) /* Comp. E */
+//#define RESERVED (0x8000) /* Comp. E */
+
+/* CEINT Control Bits */
+#define CEIFG_L (0x0001) /* Comp. E Interrupt Flag */
+#define CEIIFG_L (0x0002) /* Comp. E Interrupt Flag Inverted Polarity */
+//#define RESERVED (0x0004) /* Comp. E */
+//#define RESERVED (0x0008) /* Comp. E */
+#define CERDYIFG_L (0x0010) /* Comp. E Comparator_E ready interrupt flag */
+//#define RESERVED (0x0020) /* Comp. E */
+//#define RESERVED (0x0040) /* Comp. E */
+//#define RESERVED (0x0080) /* Comp. E */
+//#define RESERVED (0x0400) /* Comp. E */
+//#define RESERVED (0x0800) /* Comp. E */
+//#define RESERVED (0x2000) /* Comp. E */
+//#define RESERVED (0x4000) /* Comp. E */
+//#define RESERVED (0x8000) /* Comp. E */
+
+/* CEINT Control Bits */
+//#define RESERVED (0x0004) /* Comp. E */
+//#define RESERVED (0x0008) /* Comp. E */
+//#define RESERVED (0x0020) /* Comp. E */
+//#define RESERVED (0x0040) /* Comp. E */
+//#define RESERVED (0x0080) /* Comp. E */
+#define CEIE_H (0x0001) /* Comp. E Interrupt Enable */
+#define CEIIE_H (0x0002) /* Comp. E Interrupt Enable Inverted Polarity */
+//#define RESERVED (0x0400) /* Comp. E */
+//#define RESERVED (0x0800) /* Comp. E */
+#define CERDYIE_H (0x0010) /* Comp. E Comparator_E ready interrupt enable */
+//#define RESERVED (0x2000) /* Comp. E */
+//#define RESERVED (0x4000) /* Comp. E */
+//#define RESERVED (0x8000) /* Comp. E */
+
+/* CEIV Definitions */
+#define CEIV_NONE (0x0000) /* No Interrupt pending */
+#define CEIV_CEIFG (0x0002) /* CEIFG */
+#define CEIV_CEIIFG (0x0004) /* CEIIFG */
+#define CEIV_CERDYIFG (0x000A) /* CERDYIFG */
+
+/*************************************************************
+* CRC Module
+*************************************************************/
+#define __MSP430_HAS_CRC__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_CRC__ 0x0150
+#define CRC_BASE __MSP430_BASEADDRESS_CRC__
+
+sfr_w(CRCDI); /* CRC Data In Register */
+sfr_b(CRCDI_L); /* CRC Data In Register */
+sfr_b(CRCDI_H); /* CRC Data In Register */
+sfr_w(CRCDIRB); /* CRC data in reverse byte Register */
+sfr_b(CRCDIRB_L); /* CRC data in reverse byte Register */
+sfr_b(CRCDIRB_H); /* CRC data in reverse byte Register */
+sfr_w(CRCINIRES); /* CRC Initialisation Register and Result Register */
+sfr_b(CRCINIRES_L); /* CRC Initialisation Register and Result Register */
+sfr_b(CRCINIRES_H); /* CRC Initialisation Register and Result Register */
+sfr_w(CRCRESR); /* CRC reverse result Register */
+sfr_b(CRCRESR_L); /* CRC reverse result Register */
+sfr_b(CRCRESR_H); /* CRC reverse result Register */
+
+/************************************************************
+* CLOCK SYSTEM
+************************************************************/
+#define __MSP430_HAS_CS__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_CS__ 0x0160
+#define CS_BASE __MSP430_BASEADDRESS_CS__
+
+sfr_w(CSCTL0); /* CS Control Register 0 */
+sfr_b(CSCTL0_L); /* CS Control Register 0 */
+sfr_b(CSCTL0_H); /* CS Control Register 0 */
+sfr_w(CSCTL1); /* CS Control Register 1 */
+sfr_b(CSCTL1_L); /* CS Control Register 1 */
+sfr_b(CSCTL1_H); /* CS Control Register 1 */
+sfr_w(CSCTL2); /* CS Control Register 2 */
+sfr_b(CSCTL2_L); /* CS Control Register 2 */
+sfr_b(CSCTL2_H); /* CS Control Register 2 */
+sfr_w(CSCTL3); /* CS Control Register 3 */
+sfr_b(CSCTL3_L); /* CS Control Register 3 */
+sfr_b(CSCTL3_H); /* CS Control Register 3 */
+sfr_w(CSCTL4); /* CS Control Register 4 */
+sfr_b(CSCTL4_L); /* CS Control Register 4 */
+sfr_b(CSCTL4_H); /* CS Control Register 4 */
+sfr_w(CSCTL5); /* CS Control Register 5 */
+sfr_b(CSCTL5_L); /* CS Control Register 5 */
+sfr_b(CSCTL5_H); /* CS Control Register 5 */
+sfr_w(CSCTL6); /* CS Control Register 6 */
+sfr_b(CSCTL6_L); /* CS Control Register 6 */
+sfr_b(CSCTL6_H); /* CS Control Register 6 */
+
+/* CSCTL0 Control Bits */
+
+#define CSKEY (0xA500) /* CS Password */
+#define CSKEY_H (0xA5) /* CS Password for high byte access */
+
+/* CSCTL1 Control Bits */
+#define DCOFSEL0 (0x0002) /* DCO frequency select Bit: 0 */
+#define DCOFSEL1 (0x0004) /* DCO frequency select Bit: 1 */
+#define DCOFSEL2 (0x0008) /* DCO frequency select Bit: 2 */
+#define DCORSEL (0x0040) /* DCO range select. */
+
+/* CSCTL1 Control Bits */
+#define DCOFSEL0_L (0x0002) /* DCO frequency select Bit: 0 */
+#define DCOFSEL1_L (0x0004) /* DCO frequency select Bit: 1 */
+#define DCOFSEL2_L (0x0008) /* DCO frequency select Bit: 2 */
+#define DCORSEL_L (0x0040) /* DCO range select. */
+
+#define DCOFSEL_0 (0x0000) /* DCO frequency select: 0 */
+#define DCOFSEL_1 (0x0002) /* DCO frequency select: 1 */
+#define DCOFSEL_2 (0x0004) /* DCO frequency select: 2 */
+#define DCOFSEL_3 (0x0006) /* DCO frequency select: 3 */
+#define DCOFSEL_4 (0x0008) /* DCO frequency select: 4 */
+#define DCOFSEL_5 (0x000A) /* DCO frequency select: 5 */
+#define DCOFSEL_6 (0x000C) /* DCO frequency select: 6 */
+#define DCOFSEL_7 (0x000E) /* DCO frequency select: 7 */
+
+/* CSCTL2 Control Bits */
+#define SELM0 (0x0001) /* MCLK Source Select Bit: 0 */
+#define SELM1 (0x0002) /* MCLK Source Select Bit: 1 */
+#define SELM2 (0x0004) /* MCLK Source Select Bit: 2 */
+//#define RESERVED (0x0004) /* RESERVED */
+//#define RESERVED (0x0008) /* RESERVED */
+#define SELS0 (0x0010) /* SMCLK Source Select Bit: 0 */
+#define SELS1 (0x0020) /* SMCLK Source Select Bit: 1 */
+#define SELS2 (0x0040) /* SMCLK Source Select Bit: 2 */
+//#define RESERVED (0x0040) /* RESERVED */
+//#define RESERVED (0x0080) /* RESERVED */
+#define SELA0 (0x0100) /* ACLK Source Select Bit: 0 */
+#define SELA1 (0x0200) /* ACLK Source Select Bit: 1 */
+#define SELA2 (0x0400) /* ACLK Source Select Bit: 2 */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x1000) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* CSCTL2 Control Bits */
+#define SELM0_L (0x0001) /* MCLK Source Select Bit: 0 */
+#define SELM1_L (0x0002) /* MCLK Source Select Bit: 1 */
+#define SELM2_L (0x0004) /* MCLK Source Select Bit: 2 */
+//#define RESERVED (0x0004) /* RESERVED */
+//#define RESERVED (0x0008) /* RESERVED */
+#define SELS0_L (0x0010) /* SMCLK Source Select Bit: 0 */
+#define SELS1_L (0x0020) /* SMCLK Source Select Bit: 1 */
+#define SELS2_L (0x0040) /* SMCLK Source Select Bit: 2 */
+//#define RESERVED (0x0040) /* RESERVED */
+//#define RESERVED (0x0080) /* RESERVED */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x1000) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* CSCTL2 Control Bits */
+//#define RESERVED (0x0004) /* RESERVED */
+//#define RESERVED (0x0008) /* RESERVED */
+//#define RESERVED (0x0040) /* RESERVED */
+//#define RESERVED (0x0080) /* RESERVED */
+#define SELA0_H (0x0001) /* ACLK Source Select Bit: 0 */
+#define SELA1_H (0x0002) /* ACLK Source Select Bit: 1 */
+#define SELA2_H (0x0004) /* ACLK Source Select Bit: 2 */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x1000) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+#define SELM_0 (0x0000) /* MCLK Source Select 0 */
+#define SELM_1 (0x0001) /* MCLK Source Select 1 */
+#define SELM_2 (0x0002) /* MCLK Source Select 2 */
+#define SELM_3 (0x0003) /* MCLK Source Select 3 */
+#define SELM_4 (0x0004) /* MCLK Source Select 4 */
+#define SELM_5 (0x0005) /* MCLK Source Select 5 */
+#define SELM_6 (0x0006) /* MCLK Source Select 6 */
+#define SELM_7 (0x0007) /* MCLK Source Select 7 */
+#define SELM__LFXTCLK (0x0000) /* MCLK Source Select LFXTCLK */
+#define SELM__VLOCLK (0x0001) /* MCLK Source Select VLOCLK */
+#define SELM__LFMODCLK (0x0002) /* MCLK Source Select LFMODOSC */
+#define SELM__LFMODOSC (0x0002) /* MCLK Source Select LFMODOSC (legacy) */
+#define SELM__DCOCLK (0x0003) /* MCLK Source Select DCOCLK */
+#define SELM__MODCLK (0x0004) /* MCLK Source Select MODOSC */
+#define SELM__MODOSC (0x0004) /* MCLK Source Select MODOSC (legacy) */
+#define SELM__HFXTCLK (0x0005) /* MCLK Source Select HFXTCLK */
+
+#define SELS_0 (0x0000) /* SMCLK Source Select 0 */
+#define SELS_1 (0x0010) /* SMCLK Source Select 1 */
+#define SELS_2 (0x0020) /* SMCLK Source Select 2 */
+#define SELS_3 (0x0030) /* SMCLK Source Select 3 */
+#define SELS_4 (0x0040) /* SMCLK Source Select 4 */
+#define SELS_5 (0x0050) /* SMCLK Source Select 5 */
+#define SELS_6 (0x0060) /* SMCLK Source Select 6 */
+#define SELS_7 (0x0070) /* SMCLK Source Select 7 */
+#define SELS__LFXTCLK (0x0000) /* SMCLK Source Select LFXTCLK */
+#define SELS__VLOCLK (0x0010) /* SMCLK Source Select VLOCLK */
+#define SELS__LFMODCLK (0x0020) /* SMCLK Source Select LFMODOSC */
+#define SELS__LFMODOSC (0x0020) /* SMCLK Source Select LFMODOSC (legacy) */
+#define SELS__DCOCLK (0x0030) /* SMCLK Source Select DCOCLK */
+#define SELS__MODCLK (0x0040) /* SMCLK Source Select MODOSC */
+#define SELS__MODOSC (0x0040) /* SMCLK Source Select MODOSC (legacy) */
+#define SELS__HFXTCLK (0x0050) /* SMCLK Source Select HFXTCLK */
+
+#define SELA_0 (0x0000) /* ACLK Source Select 0 */
+#define SELA_1 (0x0100) /* ACLK Source Select 1 */
+#define SELA_2 (0x0200) /* ACLK Source Select 2 */
+#define SELA_3 (0x0300) /* ACLK Source Select 3 */
+#define SELA_4 (0x0400) /* ACLK Source Select 4 */
+#define SELA_5 (0x0500) /* ACLK Source Select 5 */
+#define SELA_6 (0x0600) /* ACLK Source Select 6 */
+#define SELA_7 (0x0700) /* ACLK Source Select 7 */
+#define SELA__LFXTCLK (0x0000) /* ACLK Source Select LFXTCLK */
+#define SELA__VLOCLK (0x0100) /* ACLK Source Select VLOCLK */
+#define SELA__LFMODCLK (0x0200) /* ACLK Source Select LFMODOSC */
+#define SELA__LFMODOSC (0x0200) /* ACLK Source Select LFMODOSC (legacy) */
+
+/* CSCTL3 Control Bits */
+#define DIVM0 (0x0001) /* MCLK Divider Bit: 0 */
+#define DIVM1 (0x0002) /* MCLK Divider Bit: 1 */
+#define DIVM2 (0x0004) /* MCLK Divider Bit: 2 */
+//#define RESERVED (0x0004) /* RESERVED */
+//#define RESERVED (0x0008) /* RESERVED */
+#define DIVS0 (0x0010) /* SMCLK Divider Bit: 0 */
+#define DIVS1 (0x0020) /* SMCLK Divider Bit: 1 */
+#define DIVS2 (0x0040) /* SMCLK Divider Bit: 2 */
+//#define RESERVED (0x0040) /* RESERVED */
+//#define RESERVED (0x0080) /* RESERVED */
+#define DIVA0 (0x0100) /* ACLK Divider Bit: 0 */
+#define DIVA1 (0x0200) /* ACLK Divider Bit: 1 */
+#define DIVA2 (0x0400) /* ACLK Divider Bit: 2 */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x1000) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* CSCTL3 Control Bits */
+#define DIVM0_L (0x0001) /* MCLK Divider Bit: 0 */
+#define DIVM1_L (0x0002) /* MCLK Divider Bit: 1 */
+#define DIVM2_L (0x0004) /* MCLK Divider Bit: 2 */
+//#define RESERVED (0x0004) /* RESERVED */
+//#define RESERVED (0x0008) /* RESERVED */
+#define DIVS0_L (0x0010) /* SMCLK Divider Bit: 0 */
+#define DIVS1_L (0x0020) /* SMCLK Divider Bit: 1 */
+#define DIVS2_L (0x0040) /* SMCLK Divider Bit: 2 */
+//#define RESERVED (0x0040) /* RESERVED */
+//#define RESERVED (0x0080) /* RESERVED */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x1000) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* CSCTL3 Control Bits */
+//#define RESERVED (0x0004) /* RESERVED */
+//#define RESERVED (0x0008) /* RESERVED */
+//#define RESERVED (0x0040) /* RESERVED */
+//#define RESERVED (0x0080) /* RESERVED */
+#define DIVA0_H (0x0001) /* ACLK Divider Bit: 0 */
+#define DIVA1_H (0x0002) /* ACLK Divider Bit: 1 */
+#define DIVA2_H (0x0004) /* ACLK Divider Bit: 2 */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x1000) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+#define DIVM_0 (0x0000) /* MCLK Source Divider 0 */
+#define DIVM_1 (0x0001) /* MCLK Source Divider 1 */
+#define DIVM_2 (0x0002) /* MCLK Source Divider 2 */
+#define DIVM_3 (0x0003) /* MCLK Source Divider 3 */
+#define DIVM_4 (0x0004) /* MCLK Source Divider 4 */
+#define DIVM_5 (0x0005) /* MCLK Source Divider 5 */
+#define DIVM__1 (0x0000) /* MCLK Source Divider f(MCLK)/1 */
+#define DIVM__2 (0x0001) /* MCLK Source Divider f(MCLK)/2 */
+#define DIVM__4 (0x0002) /* MCLK Source Divider f(MCLK)/4 */
+#define DIVM__8 (0x0003) /* MCLK Source Divider f(MCLK)/8 */
+#define DIVM__16 (0x0004) /* MCLK Source Divider f(MCLK)/16 */
+#define DIVM__32 (0x0005) /* MCLK Source Divider f(MCLK)/32 */
+
+#define DIVS_0 (0x0000) /* SMCLK Source Divider 0 */
+#define DIVS_1 (0x0010) /* SMCLK Source Divider 1 */
+#define DIVS_2 (0x0020) /* SMCLK Source Divider 2 */
+#define DIVS_3 (0x0030) /* SMCLK Source Divider 3 */
+#define DIVS_4 (0x0040) /* SMCLK Source Divider 4 */
+#define DIVS_5 (0x0050) /* SMCLK Source Divider 5 */
+#define DIVS__1 (0x0000) /* SMCLK Source Divider f(SMCLK)/1 */
+#define DIVS__2 (0x0010) /* SMCLK Source Divider f(SMCLK)/2 */
+#define DIVS__4 (0x0020) /* SMCLK Source Divider f(SMCLK)/4 */
+#define DIVS__8 (0x0030) /* SMCLK Source Divider f(SMCLK)/8 */
+#define DIVS__16 (0x0040) /* SMCLK Source Divider f(SMCLK)/16 */
+#define DIVS__32 (0x0050) /* SMCLK Source Divider f(SMCLK)/32 */
+
+#define DIVA_0 (0x0000) /* ACLK Source Divider 0 */
+#define DIVA_1 (0x0100) /* ACLK Source Divider 1 */
+#define DIVA_2 (0x0200) /* ACLK Source Divider 2 */
+#define DIVA_3 (0x0300) /* ACLK Source Divider 3 */
+#define DIVA_4 (0x0400) /* ACLK Source Divider 4 */
+#define DIVA_5 (0x0500) /* ACLK Source Divider 5 */
+#define DIVA__1 (0x0000) /* ACLK Source Divider f(ACLK)/1 */
+#define DIVA__2 (0x0100) /* ACLK Source Divider f(ACLK)/2 */
+#define DIVA__4 (0x0200) /* ACLK Source Divider f(ACLK)/4 */
+#define DIVA__8 (0x0300) /* ACLK Source Divider f(ACLK)/8 */
+#define DIVA__16 (0x0400) /* ACLK Source Divider f(ACLK)/16 */
+#define DIVA__32 (0x0500) /* ACLK Source Divider f(ACLK)/32 */
+
+/* CSCTL4 Control Bits */
+#define LFXTOFF (0x0001) /* Low Frequency Oscillator (LFXT) disable */
+#define SMCLKOFF (0x0002) /* SMCLK Off */
+#define VLOOFF (0x0008) /* VLO Off */
+#define LFXTBYPASS (0x0010) /* LFXT bypass mode : 0: internal 1:sourced from external pin */
+#define LFXTDRIVE0 (0x0040) /* LFXT Drive Level mode Bit 0 */
+#define LFXTDRIVE1 (0x0080) /* LFXT Drive Level mode Bit 1 */
+#define HFXTOFF (0x0100) /* High Frequency Oscillator disable */
+#define HFFREQ0 (0x0400) /* HFXT frequency selection Bit 1 */
+#define HFFREQ1 (0x0800) /* HFXT frequency selection Bit 0 */
+#define HFXTBYPASS (0x1000) /* HFXT bypass mode : 0: internal 1:sourced from external pin */
+#define HFXTDRIVE0 (0x4000) /* HFXT Drive Level mode Bit 0 */
+#define HFXTDRIVE1 (0x8000) /* HFXT Drive Level mode Bit 1 */
+
+/* CSCTL4 Control Bits */
+#define LFXTOFF_L (0x0001) /* Low Frequency Oscillator (LFXT) disable */
+#define SMCLKOFF_L (0x0002) /* SMCLK Off */
+#define VLOOFF_L (0x0008) /* VLO Off */
+#define LFXTBYPASS_L (0x0010) /* LFXT bypass mode : 0: internal 1:sourced from external pin */
+#define LFXTDRIVE0_L (0x0040) /* LFXT Drive Level mode Bit 0 */
+#define LFXTDRIVE1_L (0x0080) /* LFXT Drive Level mode Bit 1 */
+
+/* CSCTL4 Control Bits */
+#define HFXTOFF_H (0x0001) /* High Frequency Oscillator disable */
+#define HFFREQ0_H (0x0004) /* HFXT frequency selection Bit 1 */
+#define HFFREQ1_H (0x0008) /* HFXT frequency selection Bit 0 */
+#define HFXTBYPASS_H (0x0010) /* HFXT bypass mode : 0: internal 1:sourced from external pin */
+#define HFXTDRIVE0_H (0x0040) /* HFXT Drive Level mode Bit 0 */
+#define HFXTDRIVE1_H (0x0080) /* HFXT Drive Level mode Bit 1 */
+
+#define LFXTDRIVE_0 (0x0000) /* LFXT Drive Level mode: 0 */
+#define LFXTDRIVE_1 (0x0040) /* LFXT Drive Level mode: 1 */
+#define LFXTDRIVE_2 (0x0080) /* LFXT Drive Level mode: 2 */
+#define LFXTDRIVE_3 (0x00C0) /* LFXT Drive Level mode: 3 */
+
+#define HFFREQ_0 (0x0000) /* HFXT frequency selection: 0 */
+#define HFFREQ_1 (0x0400) /* HFXT frequency selection: 1 */
+#define HFFREQ_2 (0x0800) /* HFXT frequency selection: 2 */
+#define HFFREQ_3 (0x0C00) /* HFXT frequency selection: 3 */
+
+#define HFXTDRIVE_0 (0x0000) /* HFXT Drive Level mode: 0 */
+#define HFXTDRIVE_1 (0x4000) /* HFXT Drive Level mode: 1 */
+#define HFXTDRIVE_2 (0x8000) /* HFXT Drive Level mode: 2 */
+#define HFXTDRIVE_3 (0xC000) /* HFXT Drive Level mode: 3 */
+
+/* CSCTL5 Control Bits */
+#define LFXTOFFG (0x0001) /* LFXT Low Frequency Oscillator Fault Flag */
+#define HFXTOFFG (0x0002) /* HFXT High Frequency Oscillator Fault Flag */
+#define ENSTFCNT1 (0x0040) /* Enable start counter for XT1 */
+#define ENSTFCNT2 (0x0080) /* Enable start counter for XT2 */
+
+/* CSCTL5 Control Bits */
+#define LFXTOFFG_L (0x0001) /* LFXT Low Frequency Oscillator Fault Flag */
+#define HFXTOFFG_L (0x0002) /* HFXT High Frequency Oscillator Fault Flag */
+#define ENSTFCNT1_L (0x0040) /* Enable start counter for XT1 */
+#define ENSTFCNT2_L (0x0080) /* Enable start counter for XT2 */
+
+/* CSCTL6 Control Bits */
+#define ACLKREQEN (0x0001) /* ACLK Clock Request Enable */
+#define MCLKREQEN (0x0002) /* MCLK Clock Request Enable */
+#define SMCLKREQEN (0x0004) /* SMCLK Clock Request Enable */
+#define MODCLKREQEN (0x0008) /* MODOSC Clock Request Enable */
+
+/* CSCTL6 Control Bits */
+#define ACLKREQEN_L (0x0001) /* ACLK Clock Request Enable */
+#define MCLKREQEN_L (0x0002) /* MCLK Clock Request Enable */
+#define SMCLKREQEN_L (0x0004) /* SMCLK Clock Request Enable */
+#define MODCLKREQEN_L (0x0008) /* MODOSC Clock Request Enable */
+
+/************************************************************
+* DMA_X
+************************************************************/
+#define __MSP430_HAS_DMAX_3__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_DMAX_3__ 0x0500
+#define DMA_BASE __MSP430_BASEADDRESS_DMAX_3__
+
+sfr_w(DMACTL0); /* DMA Module Control 0 */
+sfr_b(DMACTL0_L); /* DMA Module Control 0 */
+sfr_b(DMACTL0_H); /* DMA Module Control 0 */
+sfr_w(DMACTL1); /* DMA Module Control 1 */
+sfr_b(DMACTL1_L); /* DMA Module Control 1 */
+sfr_b(DMACTL1_H); /* DMA Module Control 1 */
+sfr_w(DMACTL2); /* DMA Module Control 2 */
+sfr_b(DMACTL2_L); /* DMA Module Control 2 */
+sfr_b(DMACTL2_H); /* DMA Module Control 2 */
+sfr_w(DMACTL3); /* DMA Module Control 3 */
+sfr_b(DMACTL3_L); /* DMA Module Control 3 */
+sfr_b(DMACTL3_H); /* DMA Module Control 3 */
+sfr_w(DMACTL4); /* DMA Module Control 4 */
+sfr_b(DMACTL4_L); /* DMA Module Control 4 */
+sfr_b(DMACTL4_H); /* DMA Module Control 4 */
+sfr_w(DMAIV); /* DMA Interrupt Vector Word */
+sfr_b(DMAIV_L); /* DMA Interrupt Vector Word */
+sfr_b(DMAIV_H); /* DMA Interrupt Vector Word */
+
+sfr_w(DMA0CTL); /* DMA Channel 0 Control */
+sfr_b(DMA0CTL_L); /* DMA Channel 0 Control */
+sfr_b(DMA0CTL_H); /* DMA Channel 0 Control */
+sfr_l(DMA0SA); /* DMA Channel 0 Source Address */
+sfr_w(DMA0SAL); /* DMA Channel 0 Source Address */
+sfr_w(DMA0SAH); /* DMA Channel 0 Source Address */
+sfr_l(DMA0DA); /* DMA Channel 0 Destination Address */
+sfr_w(DMA0DAL); /* DMA Channel 0 Destination Address */
+sfr_w(DMA0DAH); /* DMA Channel 0 Destination Address */
+sfr_w(DMA0SZ); /* DMA Channel 0 Transfer Size */
+
+sfr_w(DMA1CTL); /* DMA Channel 1 Control */
+sfr_b(DMA1CTL_L); /* DMA Channel 1 Control */
+sfr_b(DMA1CTL_H); /* DMA Channel 1 Control */
+sfr_l(DMA1SA); /* DMA Channel 1 Source Address */
+sfr_w(DMA1SAL); /* DMA Channel 1 Source Address */
+sfr_w(DMA1SAH); /* DMA Channel 1 Source Address */
+sfr_l(DMA1DA); /* DMA Channel 1 Destination Address */
+sfr_w(DMA1DAL); /* DMA Channel 1 Destination Address */
+sfr_w(DMA1DAH); /* DMA Channel 1 Destination Address */
+sfr_w(DMA1SZ); /* DMA Channel 1 Transfer Size */
+
+sfr_w(DMA2CTL); /* DMA Channel 2 Control */
+sfr_b(DMA2CTL_L); /* DMA Channel 2 Control */
+sfr_b(DMA2CTL_H); /* DMA Channel 2 Control */
+sfr_l(DMA2SA); /* DMA Channel 2 Source Address */
+sfr_w(DMA2SAL); /* DMA Channel 2 Source Address */
+sfr_w(DMA2SAH); /* DMA Channel 2 Source Address */
+sfr_l(DMA2DA); /* DMA Channel 2 Destination Address */
+sfr_w(DMA2DAL); /* DMA Channel 2 Destination Address */
+sfr_w(DMA2DAH); /* DMA Channel 2 Destination Address */
+sfr_w(DMA2SZ); /* DMA Channel 2 Transfer Size */
+
+/* DMACTL0 Control Bits */
+#define DMA0TSEL0 (0x0001) /* DMA channel 0 transfer select bit 0 */
+#define DMA0TSEL1 (0x0002) /* DMA channel 0 transfer select bit 1 */
+#define DMA0TSEL2 (0x0004) /* DMA channel 0 transfer select bit 2 */
+#define DMA0TSEL3 (0x0008) /* DMA channel 0 transfer select bit 3 */
+#define DMA0TSEL4 (0x0010) /* DMA channel 0 transfer select bit 4 */
+#define DMA1TSEL0 (0x0100) /* DMA channel 1 transfer select bit 0 */
+#define DMA1TSEL1 (0x0200) /* DMA channel 1 transfer select bit 1 */
+#define DMA1TSEL2 (0x0400) /* DMA channel 1 transfer select bit 2 */
+#define DMA1TSEL3 (0x0800) /* DMA channel 1 transfer select bit 3 */
+#define DMA1TSEL4 (0x1000) /* DMA channel 1 transfer select bit 4 */
+
+/* DMACTL0 Control Bits */
+#define DMA0TSEL0_L (0x0001) /* DMA channel 0 transfer select bit 0 */
+#define DMA0TSEL1_L (0x0002) /* DMA channel 0 transfer select bit 1 */
+#define DMA0TSEL2_L (0x0004) /* DMA channel 0 transfer select bit 2 */
+#define DMA0TSEL3_L (0x0008) /* DMA channel 0 transfer select bit 3 */
+#define DMA0TSEL4_L (0x0010) /* DMA channel 0 transfer select bit 4 */
+
+/* DMACTL0 Control Bits */
+#define DMA1TSEL0_H (0x0001) /* DMA channel 1 transfer select bit 0 */
+#define DMA1TSEL1_H (0x0002) /* DMA channel 1 transfer select bit 1 */
+#define DMA1TSEL2_H (0x0004) /* DMA channel 1 transfer select bit 2 */
+#define DMA1TSEL3_H (0x0008) /* DMA channel 1 transfer select bit 3 */
+#define DMA1TSEL4_H (0x0010) /* DMA channel 1 transfer select bit 4 */
+
+/* DMACTL01 Control Bits */
+#define DMA2TSEL0 (0x0001) /* DMA channel 2 transfer select bit 0 */
+#define DMA2TSEL1 (0x0002) /* DMA channel 2 transfer select bit 1 */
+#define DMA2TSEL2 (0x0004) /* DMA channel 2 transfer select bit 2 */
+#define DMA2TSEL3 (0x0008) /* DMA channel 2 transfer select bit 3 */
+#define DMA2TSEL4 (0x0010) /* DMA channel 2 transfer select bit 4 */
+
+/* DMACTL01 Control Bits */
+#define DMA2TSEL0_L (0x0001) /* DMA channel 2 transfer select bit 0 */
+#define DMA2TSEL1_L (0x0002) /* DMA channel 2 transfer select bit 1 */
+#define DMA2TSEL2_L (0x0004) /* DMA channel 2 transfer select bit 2 */
+#define DMA2TSEL3_L (0x0008) /* DMA channel 2 transfer select bit 3 */
+#define DMA2TSEL4_L (0x0010) /* DMA channel 2 transfer select bit 4 */
+
+/* DMACTL4 Control Bits */
+#define ENNMI (0x0001) /* Enable NMI interruption of DMA */
+#define ROUNDROBIN (0x0002) /* Round-Robin DMA channel priorities */
+#define DMARMWDIS (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */
+
+/* DMACTL4 Control Bits */
+#define ENNMI_L (0x0001) /* Enable NMI interruption of DMA */
+#define ROUNDROBIN_L (0x0002) /* Round-Robin DMA channel priorities */
+#define DMARMWDIS_L (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */
+
+/* DMAxCTL Control Bits */
+#define DMAREQ (0x0001) /* Initiate DMA transfer with DMATSEL */
+#define DMAABORT (0x0002) /* DMA transfer aborted by NMI */
+#define DMAIE (0x0004) /* DMA interrupt enable */
+#define DMAIFG (0x0008) /* DMA interrupt flag */
+#define DMAEN (0x0010) /* DMA enable */
+#define DMALEVEL (0x0020) /* DMA level sensitive trigger select */
+#define DMASRCBYTE (0x0040) /* DMA source byte */
+#define DMADSTBYTE (0x0080) /* DMA destination byte */
+#define DMASRCINCR0 (0x0100) /* DMA source increment bit 0 */
+#define DMASRCINCR1 (0x0200) /* DMA source increment bit 1 */
+#define DMADSTINCR0 (0x0400) /* DMA destination increment bit 0 */
+#define DMADSTINCR1 (0x0800) /* DMA destination increment bit 1 */
+#define DMADT0 (0x1000) /* DMA transfer mode bit 0 */
+#define DMADT1 (0x2000) /* DMA transfer mode bit 1 */
+#define DMADT2 (0x4000) /* DMA transfer mode bit 2 */
+
+/* DMAxCTL Control Bits */
+#define DMAREQ_L (0x0001) /* Initiate DMA transfer with DMATSEL */
+#define DMAABORT_L (0x0002) /* DMA transfer aborted by NMI */
+#define DMAIE_L (0x0004) /* DMA interrupt enable */
+#define DMAIFG_L (0x0008) /* DMA interrupt flag */
+#define DMAEN_L (0x0010) /* DMA enable */
+#define DMALEVEL_L (0x0020) /* DMA level sensitive trigger select */
+#define DMASRCBYTE_L (0x0040) /* DMA source byte */
+#define DMADSTBYTE_L (0x0080) /* DMA destination byte */
+
+/* DMAxCTL Control Bits */
+#define DMASRCINCR0_H (0x0001) /* DMA source increment bit 0 */
+#define DMASRCINCR1_H (0x0002) /* DMA source increment bit 1 */
+#define DMADSTINCR0_H (0x0004) /* DMA destination increment bit 0 */
+#define DMADSTINCR1_H (0x0008) /* DMA destination increment bit 1 */
+#define DMADT0_H (0x0010) /* DMA transfer mode bit 0 */
+#define DMADT1_H (0x0020) /* DMA transfer mode bit 1 */
+#define DMADT2_H (0x0040) /* DMA transfer mode bit 2 */
+
+#define DMASWDW (0x0000) /* DMA transfer: source word to destination word */
+#define DMASBDW (0x0040) /* DMA transfer: source byte to destination word */
+#define DMASWDB (0x0080) /* DMA transfer: source word to destination byte */
+#define DMASBDB (0x00C0) /* DMA transfer: source byte to destination byte */
+
+#define DMASRCINCR_0 (0x0000) /* DMA source increment 0: source address unchanged */
+#define DMASRCINCR_1 (0x0100) /* DMA source increment 1: source address unchanged */
+#define DMASRCINCR_2 (0x0200) /* DMA source increment 2: source address decremented */
+#define DMASRCINCR_3 (0x0300) /* DMA source increment 3: source address incremented */
+
+#define DMADSTINCR_0 (0x0000) /* DMA destination increment 0: destination address unchanged */
+#define DMADSTINCR_1 (0x0400) /* DMA destination increment 1: destination address unchanged */
+#define DMADSTINCR_2 (0x0800) /* DMA destination increment 2: destination address decremented */
+#define DMADSTINCR_3 (0x0C00) /* DMA destination increment 3: destination address incremented */
+
+#define DMADT_0 (0x0000) /* DMA transfer mode 0: Single transfer */
+#define DMADT_1 (0x1000) /* DMA transfer mode 1: Block transfer */
+#define DMADT_2 (0x2000) /* DMA transfer mode 2: Burst-Block transfer */
+#define DMADT_3 (0x3000) /* DMA transfer mode 3: Burst-Block transfer */
+#define DMADT_4 (0x4000) /* DMA transfer mode 4: Repeated Single transfer */
+#define DMADT_5 (0x5000) /* DMA transfer mode 5: Repeated Block transfer */
+#define DMADT_6 (0x6000) /* DMA transfer mode 6: Repeated Burst-Block transfer */
+#define DMADT_7 (0x7000) /* DMA transfer mode 7: Repeated Burst-Block transfer */
+
+/* DMAIV Definitions */
+#define DMAIV_NONE (0x0000) /* No Interrupt pending */
+#define DMAIV_DMA0IFG (0x0002) /* DMA0IFG*/
+#define DMAIV_DMA1IFG (0x0004) /* DMA1IFG*/
+#define DMAIV_DMA2IFG (0x0006) /* DMA2IFG*/
+
+#define DMA0TSEL_0 (0x0000) /* DMA channel 0 transfer select 0: DMA_REQ (sw) */
+#define DMA0TSEL_1 (0x0001) /* DMA channel 0 transfer select 1: */
+#define DMA0TSEL_2 (0x0002) /* DMA channel 0 transfer select 2: */
+#define DMA0TSEL_3 (0x0003) /* DMA channel 0 transfer select 3: */
+#define DMA0TSEL_4 (0x0004) /* DMA channel 0 transfer select 4: */
+#define DMA0TSEL_5 (0x0005) /* DMA channel 0 transfer select 5: */
+#define DMA0TSEL_6 (0x0006) /* DMA channel 0 transfer select 6: */
+#define DMA0TSEL_7 (0x0007) /* DMA channel 0 transfer select 7: */
+#define DMA0TSEL_8 (0x0008) /* DMA channel 0 transfer select 8: */
+#define DMA0TSEL_9 (0x0009) /* DMA channel 0 transfer select 9: */
+#define DMA0TSEL_10 (0x000A) /* DMA channel 0 transfer select 10: */
+#define DMA0TSEL_11 (0x000B) /* DMA channel 0 transfer select 11: */
+#define DMA0TSEL_12 (0x000C) /* DMA channel 0 transfer select 12: */
+#define DMA0TSEL_13 (0x000D) /* DMA channel 0 transfer select 13: */
+#define DMA0TSEL_14 (0x000E) /* DMA channel 0 transfer select 14: */
+#define DMA0TSEL_15 (0x000F) /* DMA channel 0 transfer select 15: */
+#define DMA0TSEL_16 (0x0010) /* DMA channel 0 transfer select 16: */
+#define DMA0TSEL_17 (0x0011) /* DMA channel 0 transfer select 17: */
+#define DMA0TSEL_18 (0x0012) /* DMA channel 0 transfer select 18: */
+#define DMA0TSEL_19 (0x0013) /* DMA channel 0 transfer select 19: */
+#define DMA0TSEL_20 (0x0014) /* DMA channel 0 transfer select 20: */
+#define DMA0TSEL_21 (0x0015) /* DMA channel 0 transfer select 21: */
+#define DMA0TSEL_22 (0x0016) /* DMA channel 0 transfer select 22: */
+#define DMA0TSEL_23 (0x0017) /* DMA channel 0 transfer select 23: */
+#define DMA0TSEL_24 (0x0018) /* DMA channel 0 transfer select 24: */
+#define DMA0TSEL_25 (0x0019) /* DMA channel 0 transfer select 25: */
+#define DMA0TSEL_26 (0x001A) /* DMA channel 0 transfer select 26: */
+#define DMA0TSEL_27 (0x001B) /* DMA channel 0 transfer select 27: */
+#define DMA0TSEL_28 (0x001C) /* DMA channel 0 transfer select 28: */
+#define DMA0TSEL_29 (0x001D) /* DMA channel 0 transfer select 29: */
+#define DMA0TSEL_30 (0x001E) /* DMA channel 0 transfer select 30: previous DMA channel DMA2IFG */
+#define DMA0TSEL_31 (0x001F) /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */
+
+#define DMA1TSEL_0 (0x0000) /* DMA channel 1 transfer select 0: DMA_REQ (sw) */
+#define DMA1TSEL_1 (0x0100) /* DMA channel 1 transfer select 1: */
+#define DMA1TSEL_2 (0x0200) /* DMA channel 1 transfer select 2: */
+#define DMA1TSEL_3 (0x0300) /* DMA channel 1 transfer select 3: */
+#define DMA1TSEL_4 (0x0400) /* DMA channel 1 transfer select 4: */
+#define DMA1TSEL_5 (0x0500) /* DMA channel 1 transfer select 5: */
+#define DMA1TSEL_6 (0x0600) /* DMA channel 1 transfer select 6: */
+#define DMA1TSEL_7 (0x0700) /* DMA channel 1 transfer select 7: */
+#define DMA1TSEL_8 (0x0800) /* DMA channel 1 transfer select 8: */
+#define DMA1TSEL_9 (0x0900) /* DMA channel 1 transfer select 9: */
+#define DMA1TSEL_10 (0x0A00) /* DMA channel 1 transfer select 10: */
+#define DMA1TSEL_11 (0x0B00) /* DMA channel 1 transfer select 11: */
+#define DMA1TSEL_12 (0x0C00) /* DMA channel 1 transfer select 12: */
+#define DMA1TSEL_13 (0x0D00) /* DMA channel 1 transfer select 13: */
+#define DMA1TSEL_14 (0x0E00) /* DMA channel 1 transfer select 14: */
+#define DMA1TSEL_15 (0x0F00) /* DMA channel 1 transfer select 15: */
+#define DMA1TSEL_16 (0x1000) /* DMA channel 1 transfer select 16: */
+#define DMA1TSEL_17 (0x1100) /* DMA channel 1 transfer select 17: */
+#define DMA1TSEL_18 (0x1200) /* DMA channel 1 transfer select 18: */
+#define DMA1TSEL_19 (0x1300) /* DMA channel 1 transfer select 19: */
+#define DMA1TSEL_20 (0x1400) /* DMA channel 1 transfer select 20: */
+#define DMA1TSEL_21 (0x1500) /* DMA channel 1 transfer select 21: */
+#define DMA1TSEL_22 (0x1600) /* DMA channel 1 transfer select 22: */
+#define DMA1TSEL_23 (0x1700) /* DMA channel 1 transfer select 23: */
+#define DMA1TSEL_24 (0x1800) /* DMA channel 1 transfer select 24: */
+#define DMA1TSEL_25 (0x1900) /* DMA channel 1 transfer select 25: */
+#define DMA1TSEL_26 (0x1A00) /* DMA channel 1 transfer select 26: */
+#define DMA1TSEL_27 (0x1B00) /* DMA channel 1 transfer select 27: */
+#define DMA1TSEL_28 (0x1C00) /* DMA channel 1 transfer select 28: */
+#define DMA1TSEL_29 (0x1D00) /* DMA channel 1 transfer select 29: */
+#define DMA1TSEL_30 (0x1E00) /* DMA channel 1 transfer select 30: previous DMA channel DMA0IFG */
+#define DMA1TSEL_31 (0x1F00) /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */
+
+#define DMA2TSEL_0 (0x0000) /* DMA channel 2 transfer select 0: DMA_REQ (sw) */
+#define DMA2TSEL_1 (0x0001) /* DMA channel 2 transfer select 1: */
+#define DMA2TSEL_2 (0x0002) /* DMA channel 2 transfer select 2: */
+#define DMA2TSEL_3 (0x0003) /* DMA channel 2 transfer select 3: */
+#define DMA2TSEL_4 (0x0004) /* DMA channel 2 transfer select 4: */
+#define DMA2TSEL_5 (0x0005) /* DMA channel 2 transfer select 5: */
+#define DMA2TSEL_6 (0x0006) /* DMA channel 2 transfer select 6: */
+#define DMA2TSEL_7 (0x0007) /* DMA channel 2 transfer select 7: */
+#define DMA2TSEL_8 (0x0008) /* DMA channel 2 transfer select 8: */
+#define DMA2TSEL_9 (0x0009) /* DMA channel 2 transfer select 9: */
+#define DMA2TSEL_10 (0x000A) /* DMA channel 2 transfer select 10: */
+#define DMA2TSEL_11 (0x000B) /* DMA channel 2 transfer select 11: */
+#define DMA2TSEL_12 (0x000C) /* DMA channel 2 transfer select 12: */
+#define DMA2TSEL_13 (0x000D) /* DMA channel 2 transfer select 13: */
+#define DMA2TSEL_14 (0x000E) /* DMA channel 2 transfer select 14: */
+#define DMA2TSEL_15 (0x000F) /* DMA channel 2 transfer select 15: */
+#define DMA2TSEL_16 (0x0010) /* DMA channel 2 transfer select 16: */
+#define DMA2TSEL_17 (0x0011) /* DMA channel 2 transfer select 17: */
+#define DMA2TSEL_18 (0x0012) /* DMA channel 2 transfer select 18: */
+#define DMA2TSEL_19 (0x0013) /* DMA channel 2 transfer select 19: */
+#define DMA2TSEL_20 (0x0014) /* DMA channel 2 transfer select 20: */
+#define DMA2TSEL_21 (0x0015) /* DMA channel 2 transfer select 21: */
+#define DMA2TSEL_22 (0x0016) /* DMA channel 2 transfer select 22: */
+#define DMA2TSEL_23 (0x0017) /* DMA channel 2 transfer select 23: */
+#define DMA2TSEL_24 (0x0018) /* DMA channel 2 transfer select 24: */
+#define DMA2TSEL_25 (0x0019) /* DMA channel 2 transfer select 25: */
+#define DMA2TSEL_26 (0x001A) /* DMA channel 2 transfer select 26: */
+#define DMA2TSEL_27 (0x001B) /* DMA channel 2 transfer select 27: */
+#define DMA2TSEL_28 (0x001C) /* DMA channel 2 transfer select 28: */
+#define DMA2TSEL_29 (0x001D) /* DMA channel 2 transfer select 29: */
+#define DMA2TSEL_30 (0x001E) /* DMA channel 2 transfer select 30: previous DMA channel DMA1IFG */
+#define DMA2TSEL_31 (0x001F) /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */
+
+#define DMA0TSEL__DMAREQ (0x0000) /* DMA channel 0 transfer select 0: DMA_REQ (sw) */
+#define DMA0TSEL__TA0CCR0 (0x0001) /* DMA channel 0 transfer select 1: TA0CCR0 */
+#define DMA0TSEL__TA0CCR2 (0x0002) /* DMA channel 0 transfer select 2: TA0CCR2 */
+#define DMA0TSEL__TA1CCR0 (0x0003) /* DMA channel 0 transfer select 3: TA1CCR0 */
+#define DMA0TSEL__TA1CCR2 (0x0004) /* DMA channel 0 transfer select 4: TA1CCR2 */
+#define DMA0TSEL__TA2CCR0 (0x0005) /* DMA channel 0 transfer select 3: TA2CCR0 */
+#define DMA0TSEL__TA3CCR0 (0x0006) /* DMA channel 0 transfer select 4: TA3CCR0 */
+#define DMA0TSEL__TB0CCR0 (0x0007) /* DMA channel 0 transfer select 7: TB0CCR0 */
+#define DMA0TSEL__TB0CCR2 (0x0008) /* DMA channel 0 transfer select 8: TB0CCR2 */
+#define DMA0TSEL__RES9 (0x0009) /* DMA channel 0 transfer select 9: RES9 */
+#define DMA0TSEL__RES10 (0x000A) /* DMA channel 0 transfer select 10: RES10 */
+#define DMA0TSEL__RES11 (0x000B) /* DMA channel 0 transfer select 11: RES11 */
+#define DMA0TSEL__RES12 (0x000C) /* DMA channel 0 transfer select 12: RES12 */
+#define DMA0TSEL__RES13 (0x000D) /* DMA channel 0 transfer select 13: RES13 */
+#define DMA0TSEL__UCA0RXIFG (0x000E) /* DMA channel 0 transfer select 14: UCA0RXIFG */
+#define DMA0TSEL__UCA0TXIFG (0x000F) /* DMA channel 0 transfer select 15: UCA0TXIFG */
+#define DMA0TSEL__UCA1RXIFG (0x0010) /* DMA channel 0 transfer select 16: UCA1RXIFG */
+#define DMA0TSEL__UCA1TXIFG (0x0011) /* DMA channel 0 transfer select 17: UCA1TXIFG */
+#define DMA0TSEL__UCB0RXIFG0 (0x0012) /* DMA channel 0 transfer select 18: UCB0RXIFG0 */
+#define DMA0TSEL__UCB0TXIFG0 (0x0013) /* DMA channel 0 transfer select 19: UCB0TXIFG0 */
+#define DMA0TSEL__UCB0RXIFG1 (0x0014) /* DMA channel 0 transfer select 20: UCB0RXIFG1 */
+#define DMA0TSEL__UCB0TXIFG1 (0x0015) /* DMA channel 0 transfer select 21: UCB0TXIFG1 */
+#define DMA0TSEL__UCB0RXIFG2 (0x0016) /* DMA channel 0 transfer select 22: UCB0RXIFG2 */
+#define DMA0TSEL__UCB0TXIFG2 (0x0017) /* DMA channel 0 transfer select 23: UCB0TXIFG2 */
+#define DMA0TSEL__UCB0RXIFG3 (0x0018) /* DMA channel 0 transfer select 24: UCB0RXIFG3 */
+#define DMA0TSEL__UCB0TXIFG3 (0x0019) /* DMA channel 0 transfer select 25: UCB0TXIFG3 */
+#define DMA0TSEL__ADC12IFG (0x001A) /* DMA channel 0 transfer select 26: ADC12IFG */
+#define DMA0TSEL__RES27 (0x001B) /* DMA channel 0 transfer select 27: RES27 */
+#define DMA0TSEL__RES28 (0x001C) /* DMA channel 0 transfer select 28: RES28 */
+#define DMA0TSEL__MPY (0x001D) /* DMA channel 0 transfer select 29: MPY */
+#define DMA0TSEL__DMA2IFG (0x001E) /* DMA channel 0 transfer select 30: previous DMA channel DMA2IFG */
+#define DMA0TSEL__DMAE0 (0x001F) /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */
+
+#define DMA1TSEL__DMAREQ (0x0000) /* DMA channel 1 transfer select 0: DMA_REQ (sw) */
+#define DMA1TSEL__TA0CCR0 (0x0100) /* DMA channel 1 transfer select 1: TA0CCR0 */
+#define DMA1TSEL__TA0CCR2 (0x0200) /* DMA channel 1 transfer select 2: TA0CCR2 */
+#define DMA1TSEL__TA1CCR0 (0x0300) /* DMA channel 1 transfer select 3: TA1CCR0 */
+#define DMA1TSEL__TA1CCR2 (0x0400) /* DMA channel 1 transfer select 4: TA1CCR2 */
+#define DMA1TSEL__TA2CCR0 (0x0500) /* DMA channel 1 transfer select 5: TA2CCR0 */
+#define DMA1TSEL__TA3CCR0 (0x0600) /* DMA channel 1 transfer select 6: TA3CCR0 */
+#define DMA1TSEL__TB0CCR0 (0x0700) /* DMA channel 1 transfer select 7: TB0CCR0 */
+#define DMA1TSEL__TB0CCR2 (0x0800) /* DMA channel 1 transfer select 8: TB0CCR2 */
+#define DMA1TSEL__RES9 (0x0900) /* DMA channel 1 transfer select 9: RES9 */
+#define DMA1TSEL__RES10 (0x0A00) /* DMA channel 1 transfer select 10: RES10 */
+#define DMA1TSEL__RES11 (0x0B00) /* DMA channel 1 transfer select 11: RES11 */
+#define DMA1TSEL__RES12 (0x0C00) /* DMA channel 1 transfer select 12: RES12 */
+#define DMA1TSEL__RES13 (0x0D00) /* DMA channel 1 transfer select 13: RES13 */
+#define DMA1TSEL__UCA0RXIFG (0x0E00) /* DMA channel 1 transfer select 14: UCA0RXIFG */
+#define DMA1TSEL__UCA0TXIFG (0x0F00) /* DMA channel 1 transfer select 15: UCA0TXIFG */
+#define DMA1TSEL__UCA1RXIFG (0x1000) /* DMA channel 1 transfer select 16: UCA1RXIFG */
+#define DMA1TSEL__UCA1TXIFG (0x1100) /* DMA channel 1 transfer select 17: UCA1TXIFG */
+#define DMA1TSEL__UCB0RXIFG0 (0x1200) /* DMA channel 1 transfer select 18: UCB0RXIFG0 */
+#define DMA1TSEL__UCB0TXIFG0 (0x1300) /* DMA channel 1 transfer select 19: UCB0TXIFG0 */
+#define DMA1TSEL__UCB0RXIFG1 (0x1400) /* DMA channel 1 transfer select 20: UCB0RXIFG1 */
+#define DMA1TSEL__UCB0TXIFG1 (0x1500) /* DMA channel 1 transfer select 21: UCB0TXIFG1 */
+#define DMA1TSEL__UCB0RXIFG2 (0x1600) /* DMA channel 1 transfer select 22: UCB0RXIFG2 */
+#define DMA1TSEL__UCB0TXIFG2 (0x1700) /* DMA channel 1 transfer select 23: UCB0TXIFG2 */
+#define DMA1TSEL__UCB0RXIFG3 (0x1800) /* DMA channel 1 transfer select 24: UCB0RXIFG3 */
+#define DMA1TSEL__UCB0TXIFG3 (0x1900) /* DMA channel 1 transfer select 25: UCB0TXIFG3 */
+#define DMA1TSEL__ADC12IFG (0x1A00) /* DMA channel 1 transfer select 26: ADC12IFG */
+#define DMA1TSEL__RES27 (0x1B00) /* DMA channel 1 transfer select 27: RES27 */
+#define DMA1TSEL__RES28 (0x1C00) /* DMA channel 1 transfer select 28: RES28 */
+#define DMA1TSEL__MPY (0x1D00) /* DMA channel 1 transfer select 29: MPY */
+#define DMA1TSEL__DMA2IFG (0x1E00) /* DMA channel 1 transfer select 30: previous DMA channel DMA2IFG */
+#define DMA1TSEL__DMAE0 (0x1F00) /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */
+
+#define DMA2TSEL__DMAREQ (0x0000) /* DMA channel 2 transfer select 0: DMA_REQ (sw) */
+#define DMA2TSEL__TA0CCR0 (0x0001) /* DMA channel 2 transfer select 1: TA0CCR0 */
+#define DMA2TSEL__TA0CCR2 (0x0002) /* DMA channel 2 transfer select 2: TA0CCR2 */
+#define DMA2TSEL__TA1CCR0 (0x0003) /* DMA channel 2 transfer select 3: TA1CCR0 */
+#define DMA2TSEL__TA1CCR2 (0x0004) /* DMA channel 2 transfer select 4: TA1CCR2 */
+#define DMA2TSEL__TA2CCR0 (0x0005) /* DMA channel 2 transfer select 5: TA2CCR0 */
+#define DMA2TSEL__TA3CCR0 (0x0006) /* DMA channel 2 transfer select 6: TA3CCR0 */
+#define DMA2TSEL__TB0CCR0 (0x0007) /* DMA channel 2 transfer select 7: TB0CCR0 */
+#define DMA2TSEL__TB0CCR2 (0x0008) /* DMA channel 2 transfer select 8: TB0CCR2 */
+#define DMA2TSEL__RES9 (0x0009) /* DMA channel 2 transfer select 9: RES9 */
+#define DMA2TSEL__RES10 (0x000A) /* DMA channel 2 transfer select 10: RES10 */
+#define DMA2TSEL__RES11 (0x000B) /* DMA channel 2 transfer select 11: RES11 */
+#define DMA2TSEL__RES12 (0x000C) /* DMA channel 2 transfer select 12: RES12 */
+#define DMA2TSEL__RES13 (0x000D) /* DMA channel 2 transfer select 13: RES13 */
+#define DMA2TSEL__UCA0RXIFG (0x000E) /* DMA channel 2 transfer select 14: UCA0RXIFG */
+#define DMA2TSEL__UCA0TXIFG (0x000F) /* DMA channel 2 transfer select 15: UCA0TXIFG */
+#define DMA2TSEL__UCA1RXIFG (0x0010) /* DMA channel 2 transfer select 16: UCA1RXIFG */
+#define DMA2TSEL__UCA1TXIFG (0x0011) /* DMA channel 2 transfer select 17: UCA1TXIFG */
+#define DMA2TSEL__UCB0RXIFG0 (0x0012) /* DMA channel 2 transfer select 18: UCB0RXIFG0 */
+#define DMA2TSEL__UCB0TXIFG0 (0x0013) /* DMA channel 2 transfer select 19: UCB0TXIFG0 */
+#define DMA2TSEL__UCB0RXIFG1 (0x0014) /* DMA channel 2 transfer select 20: UCB0RXIFG1 */
+#define DMA2TSEL__UCB0TXIFG1 (0x0015) /* DMA channel 2 transfer select 21: UCB0TXIFG1 */
+#define DMA2TSEL__UCB0RXIFG2 (0x0016) /* DMA channel 2 transfer select 22: UCB0RXIFG2 */
+#define DMA2TSEL__UCB0TXIFG2 (0x0017) /* DMA channel 2 transfer select 23: UCB0TXIFG2 */
+#define DMA2TSEL__UCB0RXIFG3 (0x0018) /* DMA channel 2 transfer select 24: UCB0RXIFG3 */
+#define DMA2TSEL__UCB0TXIFG3 (0x0019) /* DMA channel 2 transfer select 25: UCB0TXIFG3 */
+#define DMA2TSEL__ADC12IFG (0x001A) /* DMA channel 2 transfer select 26: ADC12IFG */
+#define DMA2TSEL__RES27 (0x001B) /* DMA channel 2 transfer select 27: RES27 */
+#define DMA2TSEL__RES28 (0x001C) /* DMA channel 2 transfer select 28: RES28 */
+#define DMA2TSEL__MPY (0x001D) /* DMA channel 2 transfer select 29: MPY */
+#define DMA2TSEL__DMA2IFG (0x001E) /* DMA channel 2 transfer select 30: previous DMA channel DMA2IFG */
+#define DMA2TSEL__DMAE0 (0x001F) /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */
+
+/*************************************************************
+* FRAM Memory
+*************************************************************/
+#define __MSP430_HAS_FRAM__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_FRAM__ 0x0140
+#define FRAM_BASE __MSP430_BASEADDRESS_FRAM__
+#define __MSP430_HAS_GC__ /* Definition to show that Module is available */
+
+sfr_w(FRCTL0); /* FRAM Controller Control 0 */
+sfr_b(FRCTL0_L); /* FRAM Controller Control 0 */
+sfr_b(FRCTL0_H); /* FRAM Controller Control 0 */
+sfr_w(GCCTL0); /* General Control 0 */
+sfr_b(GCCTL0_L); /* General Control 0 */
+sfr_b(GCCTL0_H); /* General Control 0 */
+sfr_w(GCCTL1); /* General Control 1 */
+sfr_b(GCCTL1_L); /* General Control 1 */
+sfr_b(GCCTL1_H); /* General Control 1 */
+
+#define FRCTLPW (0xA500) /* FRAM password for write */
+#define FRPW (0x9600) /* FRAM password returned by read */
+#define FWPW (0xA500) /* FRAM password for write */
+#define FXPW (0x3300) /* for use with XOR instruction */
+
+/* FRCTL0 Control Bits */
+//#define RESERVED (0x0001) /* RESERVED */
+//#define RESERVED (0x0002) /* RESERVED */
+//#define RESERVED (0x0004) /* RESERVED */
+#define NWAITS0 (0x0010) /* FRAM Wait state control Bit: 0 */
+#define NWAITS1 (0x0020) /* FRAM Wait state control Bit: 1 */
+#define NWAITS2 (0x0040) /* FRAM Wait state control Bit: 2 */
+//#define RESERVED (0x0080) /* RESERVED */
+
+/* FRCTL0 Control Bits */
+//#define RESERVED (0x0001) /* RESERVED */
+//#define RESERVED (0x0002) /* RESERVED */
+//#define RESERVED (0x0004) /* RESERVED */
+#define NWAITS0_L (0x0010) /* FRAM Wait state control Bit: 0 */
+#define NWAITS1_L (0x0020) /* FRAM Wait state control Bit: 1 */
+#define NWAITS2_L (0x0040) /* FRAM Wait state control Bit: 2 */
+//#define RESERVED (0x0080) /* RESERVED */
+
+#define NWAITS_0 (0x0000) /* FRAM Wait state control: 0 */
+#define NWAITS_1 (0x0010) /* FRAM Wait state control: 1 */
+#define NWAITS_2 (0x0020) /* FRAM Wait state control: 2 */
+#define NWAITS_3 (0x0030) /* FRAM Wait state control: 3 */
+#define NWAITS_4 (0x0040) /* FRAM Wait state control: 4 */
+#define NWAITS_5 (0x0050) /* FRAM Wait state control: 5 */
+#define NWAITS_6 (0x0060) /* FRAM Wait state control: 6 */
+#define NWAITS_7 (0x0070) /* FRAM Wait state control: 7 */
+
+/* Legacy Defines */
+#define NACCESS0 (0x0010) /* FRAM Wait state Generator Access Time control Bit: 0 */
+#define NACCESS1 (0x0020) /* FRAM Wait state Generator Access Time control Bit: 1 */
+#define NACCESS2 (0x0040) /* FRAM Wait state Generator Access Time control Bit: 2 */
+#define NACCESS_0 (0x0000) /* FRAM Wait state Generator Access Time control: 0 */
+#define NACCESS_1 (0x0010) /* FRAM Wait state Generator Access Time control: 1 */
+#define NACCESS_2 (0x0020) /* FRAM Wait state Generator Access Time control: 2 */
+#define NACCESS_3 (0x0030) /* FRAM Wait state Generator Access Time control: 3 */
+#define NACCESS_4 (0x0040) /* FRAM Wait state Generator Access Time control: 4 */
+#define NACCESS_5 (0x0050) /* FRAM Wait state Generator Access Time control: 5 */
+#define NACCESS_6 (0x0060) /* FRAM Wait state Generator Access Time control: 6 */
+#define NACCESS_7 (0x0070) /* FRAM Wait state Generator Access Time control: 7 */
+
+/* GCCTL0 Control Bits */
+//#define RESERVED (0x0001) /* RESERVED */
+#define FRLPMPWR (0x0002) /* FRAM Enable FRAM auto power up after LPM */
+#define FRPWR (0x0004) /* FRAM Power Control */
+#define ACCTEIE (0x0008) /* RESERVED */
+//#define RESERVED (0x0010) /* RESERVED */
+#define CBDIE (0x0020) /* Enable NMI event if correctable bit error detected */
+#define UBDIE (0x0040) /* Enable NMI event if uncorrectable bit error detected */
+#define UBDRSTEN (0x0080) /* Enable Power Up Clear (PUC) reset if FRAM uncorrectable bit error detected */
+
+/* GCCTL0 Control Bits */
+//#define RESERVED (0x0001) /* RESERVED */
+#define FRLPMPWR_L (0x0002) /* FRAM Enable FRAM auto power up after LPM */
+#define FRPWR_L (0x0004) /* FRAM Power Control */
+#define ACCTEIE_L (0x0008) /* RESERVED */
+//#define RESERVED (0x0010) /* RESERVED */
+#define CBDIE_L (0x0020) /* Enable NMI event if correctable bit error detected */
+#define UBDIE_L (0x0040) /* Enable NMI event if uncorrectable bit error detected */
+#define UBDRSTEN_L (0x0080) /* Enable Power Up Clear (PUC) reset if FRAM uncorrectable bit error detected */
+
+/* GCCTL1 Control Bits */
+//#define RESERVED (0x0001) /* RESERVED */
+#define CBDIFG (0x0002) /* FRAM correctable bit error flag */
+#define UBDIFG (0x0004) /* FRAM uncorrectable bit error flag */
+#define ACCTEIFG (0x0008) /* Access time error flag */
+
+/* GCCTL1 Control Bits */
+//#define RESERVED (0x0001) /* RESERVED */
+#define CBDIFG_L (0x0002) /* FRAM correctable bit error flag */
+#define UBDIFG_L (0x0004) /* FRAM uncorrectable bit error flag */
+#define ACCTEIFG_L (0x0008) /* Access time error flag */
+
+/************************************************************
+* Memory Protection Unit
+************************************************************/
+#define __MSP430_HAS_MPU__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_MPU__ 0x05A0
+#define MPU_BASE __MSP430_BASEADDRESS_MPU__
+
+sfr_w(MPUCTL0); /* MPU Control Register 0 */
+sfr_b(MPUCTL0_L); /* MPU Control Register 0 */
+sfr_b(MPUCTL0_H); /* MPU Control Register 0 */
+sfr_w(MPUCTL1); /* MPU Control Register 1 */
+sfr_b(MPUCTL1_L); /* MPU Control Register 1 */
+sfr_b(MPUCTL1_H); /* MPU Control Register 1 */
+sfr_w(MPUSEGB2); /* MPU Segmentation Border 2 Register */
+sfr_b(MPUSEGB2_L); /* MPU Segmentation Border 2 Register */
+sfr_b(MPUSEGB2_H); /* MPU Segmentation Border 2 Register */
+sfr_w(MPUSEGB1); /* MPU Segmentation Border 1 Register */
+sfr_b(MPUSEGB1_L); /* MPU Segmentation Border 1 Register */
+sfr_b(MPUSEGB1_H); /* MPU Segmentation Border 1 Register */
+sfr_w(MPUSAM); /* MPU Access Management Register */
+sfr_b(MPUSAM_L); /* MPU Access Management Register */
+sfr_b(MPUSAM_H); /* MPU Access Management Register */
+sfr_w(MPUIPC0); /* MPU IP Control 0 Register */
+sfr_b(MPUIPC0_L); /* MPU IP Control 0 Register */
+sfr_b(MPUIPC0_H); /* MPU IP Control 0 Register */
+sfr_w(MPUIPSEGB2); /* MPU IP Segment Border 2 Register */
+sfr_b(MPUIPSEGB2_L); /* MPU IP Segment Border 2 Register */
+sfr_b(MPUIPSEGB2_H); /* MPU IP Segment Border 2 Register */
+sfr_w(MPUIPSEGB1); /* MPU IP Segment Border 1 Register */
+sfr_b(MPUIPSEGB1_L); /* MPU IP Segment Border 1 Register */
+sfr_b(MPUIPSEGB1_H); /* MPU IP Segment Border 1 Register */
+
+/* MPUCTL0 Control Bits */
+#define MPUENA (0x0001) /* MPU Enable */
+#define MPULOCK (0x0002) /* MPU Lock */
+#define MPUSEGIE (0x0010) /* MPU Enable NMI on Segment violation */
+
+/* MPUCTL0 Control Bits */
+#define MPUENA_L (0x0001) /* MPU Enable */
+#define MPULOCK_L (0x0002) /* MPU Lock */
+#define MPUSEGIE_L (0x0010) /* MPU Enable NMI on Segment violation */
+
+#define MPUPW (0xA500) /* MPU Access Password */
+#define MPUPW_H (0xA5) /* MPU Access Password */
+
+/* MPUCTL1 Control Bits */
+#define MPUSEG1IFG (0x0001) /* MPU Main Memory Segment 1 violation interupt flag */
+#define MPUSEG2IFG (0x0002) /* MPU Main Memory Segment 2 violation interupt flag */
+#define MPUSEG3IFG (0x0004) /* MPU Main Memory Segment 3 violation interupt flag */
+#define MPUSEGIIFG (0x0008) /* MPU Info Memory Segment violation interupt flag */
+#define MPUSEGIPIFG (0x0010) /* MPU IP Memory Segment violation interupt flag */
+
+/* MPUCTL1 Control Bits */
+#define MPUSEG1IFG_L (0x0001) /* MPU Main Memory Segment 1 violation interupt flag */
+#define MPUSEG2IFG_L (0x0002) /* MPU Main Memory Segment 2 violation interupt flag */
+#define MPUSEG3IFG_L (0x0004) /* MPU Main Memory Segment 3 violation interupt flag */
+#define MPUSEGIIFG_L (0x0008) /* MPU Info Memory Segment violation interupt flag */
+#define MPUSEGIPIFG_L (0x0010) /* MPU IP Memory Segment violation interupt flag */
+
+/* MPUSEGB2 Control Bits */
+
+/* MPUSEGB2 Control Bits */
+
+/* MPUSEGB2 Control Bits */
+
+/* MPUSEGB1 Control Bits */
+
+/* MPUSEGB1 Control Bits */
+
+/* MPUSEGB1 Control Bits */
+
+/* MPUSAM Control Bits */
+#define MPUSEG1RE (0x0001) /* MPU Main memory Segment 1 Read enable */
+#define MPUSEG1WE (0x0002) /* MPU Main memory Segment 1 Write enable */
+#define MPUSEG1XE (0x0004) /* MPU Main memory Segment 1 Execute enable */
+#define MPUSEG1VS (0x0008) /* MPU Main memory Segment 1 Violation select */
+#define MPUSEG2RE (0x0010) /* MPU Main memory Segment 2 Read enable */
+#define MPUSEG2WE (0x0020) /* MPU Main memory Segment 2 Write enable */
+#define MPUSEG2XE (0x0040) /* MPU Main memory Segment 2 Execute enable */
+#define MPUSEG2VS (0x0080) /* MPU Main memory Segment 2 Violation select */
+#define MPUSEG3RE (0x0100) /* MPU Main memory Segment 3 Read enable */
+#define MPUSEG3WE (0x0200) /* MPU Main memory Segment 3 Write enable */
+#define MPUSEG3XE (0x0400) /* MPU Main memory Segment 3 Execute enable */
+#define MPUSEG3VS (0x0800) /* MPU Main memory Segment 3 Violation select */
+#define MPUSEGIRE (0x1000) /* MPU Info memory Segment Read enable */
+#define MPUSEGIWE (0x2000) /* MPU Info memory Segment Write enable */
+#define MPUSEGIXE (0x4000) /* MPU Info memory Segment Execute enable */
+#define MPUSEGIVS (0x8000) /* MPU Info memory Segment Violation select */
+
+/* MPUSAM Control Bits */
+#define MPUSEG1RE_L (0x0001) /* MPU Main memory Segment 1 Read enable */
+#define MPUSEG1WE_L (0x0002) /* MPU Main memory Segment 1 Write enable */
+#define MPUSEG1XE_L (0x0004) /* MPU Main memory Segment 1 Execute enable */
+#define MPUSEG1VS_L (0x0008) /* MPU Main memory Segment 1 Violation select */
+#define MPUSEG2RE_L (0x0010) /* MPU Main memory Segment 2 Read enable */
+#define MPUSEG2WE_L (0x0020) /* MPU Main memory Segment 2 Write enable */
+#define MPUSEG2XE_L (0x0040) /* MPU Main memory Segment 2 Execute enable */
+#define MPUSEG2VS_L (0x0080) /* MPU Main memory Segment 2 Violation select */
+
+/* MPUSAM Control Bits */
+#define MPUSEG3RE_H (0x0001) /* MPU Main memory Segment 3 Read enable */
+#define MPUSEG3WE_H (0x0002) /* MPU Main memory Segment 3 Write enable */
+#define MPUSEG3XE_H (0x0004) /* MPU Main memory Segment 3 Execute enable */
+#define MPUSEG3VS_H (0x0008) /* MPU Main memory Segment 3 Violation select */
+#define MPUSEGIRE_H (0x0010) /* MPU Info memory Segment Read enable */
+#define MPUSEGIWE_H (0x0020) /* MPU Info memory Segment Write enable */
+#define MPUSEGIXE_H (0x0040) /* MPU Info memory Segment Execute enable */
+#define MPUSEGIVS_H (0x0080) /* MPU Info memory Segment Violation select */
+
+/* MPUIPC0 Control Bits */
+#define MPUIPVS (0x0020) /* MPU MPU IP protection segment Violation Select */
+#define MPUIPENA (0x0040) /* MPU MPU IP Protection Enable */
+#define MPUIPLOCK (0x0080) /* MPU IP Protection Lock */
+
+/* MPUIPC0 Control Bits */
+#define MPUIPVS_L (0x0020) /* MPU MPU IP protection segment Violation Select */
+#define MPUIPENA_L (0x0040) /* MPU MPU IP Protection Enable */
+#define MPUIPLOCK_L (0x0080) /* MPU IP Protection Lock */
+
+/* MPUIPSEGB2 Control Bits */
+
+/* MPUIPSEGB2 Control Bits */
+
+/* MPUIPSEGB2 Control Bits */
+
+/* MPUIPSEGB1 Control Bits */
+
+/* MPUIPSEGB1 Control Bits */
+
+/* MPUIPSEGB1 Control Bits */
+
+/************************************************************
+* HARDWARE MULTIPLIER 32Bit
+************************************************************/
+#define __MSP430_HAS_MPY32__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_MPY32__ 0x04C0
+#define MPY32_BASE __MSP430_BASEADDRESS_MPY32__
+
+sfr_w(MPY); /* Multiply Unsigned/Operand 1 */
+sfr_b(MPY_L); /* Multiply Unsigned/Operand 1 */
+sfr_b(MPY_H); /* Multiply Unsigned/Operand 1 */
+sfr_w(MPYS); /* Multiply Signed/Operand 1 */
+sfr_b(MPYS_L); /* Multiply Signed/Operand 1 */
+sfr_b(MPYS_H); /* Multiply Signed/Operand 1 */
+sfr_w(MAC); /* Multiply Unsigned and Accumulate/Operand 1 */
+sfr_b(MAC_L); /* Multiply Unsigned and Accumulate/Operand 1 */
+sfr_b(MAC_H); /* Multiply Unsigned and Accumulate/Operand 1 */
+sfr_w(MACS); /* Multiply Signed and Accumulate/Operand 1 */
+sfr_b(MACS_L); /* Multiply Signed and Accumulate/Operand 1 */
+sfr_b(MACS_H); /* Multiply Signed and Accumulate/Operand 1 */
+sfr_w(OP2); /* Operand 2 */
+sfr_b(OP2_L); /* Operand 2 */
+sfr_b(OP2_H); /* Operand 2 */
+sfr_w(RESLO); /* Result Low Word */
+sfr_b(RESLO_L); /* Result Low Word */
+sfr_b(RESLO_H); /* Result Low Word */
+sfr_w(RESHI); /* Result High Word */
+sfr_b(RESHI_L); /* Result High Word */
+sfr_b(RESHI_H); /* Result High Word */
+sfr_w(SUMEXT); /* Sum Extend */
+sfr_b(SUMEXT_L); /* Sum Extend */
+sfr_b(SUMEXT_H); /* Sum Extend */
+
+sfr_w(MPY32L); /* 32-bit operand 1 - multiply - low word */
+sfr_b(MPY32L_L); /* 32-bit operand 1 - multiply - low word */
+sfr_b(MPY32L_H); /* 32-bit operand 1 - multiply - low word */
+sfr_w(MPY32H); /* 32-bit operand 1 - multiply - high word */
+sfr_b(MPY32H_L); /* 32-bit operand 1 - multiply - high word */
+sfr_b(MPY32H_H); /* 32-bit operand 1 - multiply - high word */
+sfr_w(MPYS32L); /* 32-bit operand 1 - signed multiply - low word */
+sfr_b(MPYS32L_L); /* 32-bit operand 1 - signed multiply - low word */
+sfr_b(MPYS32L_H); /* 32-bit operand 1 - signed multiply - low word */
+sfr_w(MPYS32H); /* 32-bit operand 1 - signed multiply - high word */
+sfr_b(MPYS32H_L); /* 32-bit operand 1 - signed multiply - high word */
+sfr_b(MPYS32H_H); /* 32-bit operand 1 - signed multiply - high word */
+sfr_w(MAC32L); /* 32-bit operand 1 - multiply accumulate - low word */
+sfr_b(MAC32L_L); /* 32-bit operand 1 - multiply accumulate - low word */
+sfr_b(MAC32L_H); /* 32-bit operand 1 - multiply accumulate - low word */
+sfr_w(MAC32H); /* 32-bit operand 1 - multiply accumulate - high word */
+sfr_b(MAC32H_L); /* 32-bit operand 1 - multiply accumulate - high word */
+sfr_b(MAC32H_H); /* 32-bit operand 1 - multiply accumulate - high word */
+sfr_w(MACS32L); /* 32-bit operand 1 - signed multiply accumulate - low word */
+sfr_b(MACS32L_L); /* 32-bit operand 1 - signed multiply accumulate - low word */
+sfr_b(MACS32L_H); /* 32-bit operand 1 - signed multiply accumulate - low word */
+sfr_w(MACS32H); /* 32-bit operand 1 - signed multiply accumulate - high word */
+sfr_b(MACS32H_L); /* 32-bit operand 1 - signed multiply accumulate - high word */
+sfr_b(MACS32H_H); /* 32-bit operand 1 - signed multiply accumulate - high word */
+sfr_w(OP2L); /* 32-bit operand 2 - low word */
+sfr_b(OP2L_L); /* 32-bit operand 2 - low word */
+sfr_b(OP2L_H); /* 32-bit operand 2 - low word */
+sfr_w(OP2H); /* 32-bit operand 2 - high word */
+sfr_b(OP2H_L); /* 32-bit operand 2 - high word */
+sfr_b(OP2H_H); /* 32-bit operand 2 - high word */
+sfr_w(RES0); /* 32x32-bit result 0 - least significant word */
+sfr_b(RES0_L); /* 32x32-bit result 0 - least significant word */
+sfr_b(RES0_H); /* 32x32-bit result 0 - least significant word */
+sfr_w(RES1); /* 32x32-bit result 1 */
+sfr_b(RES1_L); /* 32x32-bit result 1 */
+sfr_b(RES1_H); /* 32x32-bit result 1 */
+sfr_w(RES2); /* 32x32-bit result 2 */
+sfr_b(RES2_L); /* 32x32-bit result 2 */
+sfr_b(RES2_H); /* 32x32-bit result 2 */
+sfr_w(RES3); /* 32x32-bit result 3 - most significant word */
+sfr_b(RES3_L); /* 32x32-bit result 3 - most significant word */
+sfr_b(RES3_H); /* 32x32-bit result 3 - most significant word */
+sfr_w(MPY32CTL0); /* MPY32 Control Register 0 */
+sfr_b(MPY32CTL0_L); /* MPY32 Control Register 0 */
+sfr_b(MPY32CTL0_H); /* MPY32 Control Register 0 */
+
+#define MPY_B MPY_L /* Multiply Unsigned/Operand 1 (Byte Access) */
+#define MPYS_B MPYS_L /* Multiply Signed/Operand 1 (Byte Access) */
+#define MAC_B MAC_L /* Multiply Unsigned and Accumulate/Operand 1 (Byte Access) */
+#define MACS_B MACS_L /* Multiply Signed and Accumulate/Operand 1 (Byte Access) */
+#define OP2_B OP2_L /* Operand 2 (Byte Access) */
+#define MPY32L_B MPY32L_L /* 32-bit operand 1 - multiply - low word (Byte Access) */
+#define MPY32H_B MPY32H_L /* 32-bit operand 1 - multiply - high word (Byte Access) */
+#define MPYS32L_B MPYS32L_L /* 32-bit operand 1 - signed multiply - low word (Byte Access) */
+#define MPYS32H_B MPYS32H_L /* 32-bit operand 1 - signed multiply - high word (Byte Access) */
+#define MAC32L_B MAC32L_L /* 32-bit operand 1 - multiply accumulate - low word (Byte Access) */
+#define MAC32H_B MAC32H_L /* 32-bit operand 1 - multiply accumulate - high word (Byte Access) */
+#define MACS32L_B MACS32L_L /* 32-bit operand 1 - signed multiply accumulate - low word (Byte Access) */
+#define MACS32H_B MACS32H_L /* 32-bit operand 1 - signed multiply accumulate - high word (Byte Access) */
+#define OP2L_B OP2L_L /* 32-bit operand 2 - low word (Byte Access) */
+#define OP2H_B OP2H_L /* 32-bit operand 2 - high word (Byte Access) */
+
+/* MPY32CTL0 Control Bits */
+#define MPYC (0x0001) /* Carry of the multiplier */
+//#define RESERVED (0x0002) /* Reserved */
+#define MPYFRAC (0x0004) /* Fractional mode */
+#define MPYSAT (0x0008) /* Saturation mode */
+#define MPYM0 (0x0010) /* Multiplier mode Bit:0 */
+#define MPYM1 (0x0020) /* Multiplier mode Bit:1 */
+#define OP1_32 (0x0040) /* Bit-width of operand 1 0:16Bit / 1:32Bit */
+#define OP2_32 (0x0080) /* Bit-width of operand 2 0:16Bit / 1:32Bit */
+#define MPYDLYWRTEN (0x0100) /* Delayed write enable */
+#define MPYDLY32 (0x0200) /* Delayed write mode */
+
+/* MPY32CTL0 Control Bits */
+#define MPYC_L (0x0001) /* Carry of the multiplier */
+//#define RESERVED (0x0002) /* Reserved */
+#define MPYFRAC_L (0x0004) /* Fractional mode */
+#define MPYSAT_L (0x0008) /* Saturation mode */
+#define MPYM0_L (0x0010) /* Multiplier mode Bit:0 */
+#define MPYM1_L (0x0020) /* Multiplier mode Bit:1 */
+#define OP1_32_L (0x0040) /* Bit-width of operand 1 0:16Bit / 1:32Bit */
+#define OP2_32_L (0x0080) /* Bit-width of operand 2 0:16Bit / 1:32Bit */
+
+/* MPY32CTL0 Control Bits */
+//#define RESERVED (0x0002) /* Reserved */
+#define MPYDLYWRTEN_H (0x0001) /* Delayed write enable */
+#define MPYDLY32_H (0x0002) /* Delayed write mode */
+
+#define MPYM_0 (0x0000) /* Multiplier mode: MPY */
+#define MPYM_1 (0x0010) /* Multiplier mode: MPYS */
+#define MPYM_2 (0x0020) /* Multiplier mode: MAC */
+#define MPYM_3 (0x0030) /* Multiplier mode: MACS */
+#define MPYM__MPY (0x0000) /* Multiplier mode: MPY */
+#define MPYM__MPYS (0x0010) /* Multiplier mode: MPYS */
+#define MPYM__MAC (0x0020) /* Multiplier mode: MAC */
+#define MPYM__MACS (0x0030) /* Multiplier mode: MACS */
+
+/************************************************************
+* PMM - Power Management System for FRAM
+************************************************************/
+#define __MSP430_HAS_PMM_FRAM__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PMM_FRAM__ 0x0120
+#define PMM_BASE __MSP430_BASEADDRESS_PMM_FRAM__
+
+sfr_w(PMMCTL0); /* PMM Control 0 */
+sfr_b(PMMCTL0_L); /* PMM Control 0 */
+sfr_b(PMMCTL0_H); /* PMM Control 0 */
+sfr_w(PMMIFG); /* PMM Interrupt Flag */
+sfr_b(PMMIFG_L); /* PMM Interrupt Flag */
+sfr_b(PMMIFG_H); /* PMM Interrupt Flag */
+sfr_w(PM5CTL0); /* PMM Power Mode 5 Control Register 0 */
+sfr_b(PM5CTL0_L); /* PMM Power Mode 5 Control Register 0 */
+sfr_b(PM5CTL0_H); /* PMM Power Mode 5 Control Register 0 */
+
+#define PMMPW (0xA500) /* PMM Register Write Password */
+#define PMMPW_H (0xA5) /* PMM Register Write Password for high word access */
+
+/* PMMCTL0 Control Bits */
+#define PMMSWBOR (0x0004) /* PMM Software BOR */
+#define PMMSWPOR (0x0008) /* PMM Software POR */
+#define PMMREGOFF (0x0010) /* PMM Turn Regulator off */
+#define SVSHE (0x0040) /* SVS high side enable */
+#define PMMLPRST (0x0080) /* PMM Low-Power Reset Enable */
+
+/* PMMCTL0 Control Bits */
+#define PMMSWBOR_L (0x0004) /* PMM Software BOR */
+#define PMMSWPOR_L (0x0008) /* PMM Software POR */
+#define PMMREGOFF_L (0x0010) /* PMM Turn Regulator off */
+#define SVSHE_L (0x0040) /* SVS high side enable */
+#define PMMLPRST_L (0x0080) /* PMM Low-Power Reset Enable */
+
+/* PMMIFG Control Bits */
+#define PMMBORIFG (0x0100) /* PMM Software BOR interrupt flag */
+#define PMMRSTIFG (0x0200) /* PMM RESET pin interrupt flag */
+#define PMMPORIFG (0x0400) /* PMM Software POR interrupt flag */
+#define SVSHIFG (0x2000) /* SVS low side interrupt flag */
+#define PMMLPM5IFG (0x8000) /* LPM5 indication Flag */
+
+/* PMMIFG Control Bits */
+#define PMMBORIFG_H (0x0001) /* PMM Software BOR interrupt flag */
+#define PMMRSTIFG_H (0x0002) /* PMM RESET pin interrupt flag */
+#define PMMPORIFG_H (0x0004) /* PMM Software POR interrupt flag */
+#define SVSHIFG_H (0x0020) /* SVS low side interrupt flag */
+#define PMMLPM5IFG_H (0x0080) /* LPM5 indication Flag */
+
+/* PM5CTL0 Power Mode 5 Control Bits */
+#define LOCKLPM5 (0x0001) /* Lock I/O pin configuration upon entry/exit to/from LPM5 */
+
+/* PM5CTL0 Power Mode 5 Control Bits */
+#define LOCKLPM5_L (0x0001) /* Lock I/O pin configuration upon entry/exit to/from LPM5 */
+
+
+/************************************************************
+* DIGITAL I/O Port1/2 Pull up / Pull down Resistors
+************************************************************/
+#define __MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORT1_R__ 0x0200
+#define P1_BASE __MSP430_BASEADDRESS_PORT1_R__
+#define __MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORT2_R__ 0x0200
+#define P2_BASE __MSP430_BASEADDRESS_PORT2_R__
+#define __MSP430_HAS_PORTA_R__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORTA_R__ 0x0200
+#define PA_BASE __MSP430_BASEADDRESS_PORTA_R__
+#define __MSP430_HAS_P1SEL0__ /* Define for DriverLib */
+#define __MSP430_HAS_P2SEL0__ /* Define for DriverLib */
+#define __MSP430_HAS_PASEL0__ /* Define for DriverLib */
+#define __MSP430_HAS_P1SEL1__ /* Define for DriverLib */
+#define __MSP430_HAS_P2SEL1__ /* Define for DriverLib */
+#define __MSP430_HAS_PASEL1__ /* Define for DriverLib */
+
+sfr_w(PAIN); /* Port A Input */
+sfr_b(PAIN_L); /* Port A Input */
+sfr_b(PAIN_H); /* Port A Input */
+sfr_w(PAOUT); /* Port A Output */
+sfr_b(PAOUT_L); /* Port A Output */
+sfr_b(PAOUT_H); /* Port A Output */
+sfr_w(PADIR); /* Port A Direction */
+sfr_b(PADIR_L); /* Port A Direction */
+sfr_b(PADIR_H); /* Port A Direction */
+sfr_w(PAREN); /* Port A Resistor Enable */
+sfr_b(PAREN_L); /* Port A Resistor Enable */
+sfr_b(PAREN_H); /* Port A Resistor Enable */
+sfr_w(PASEL0); /* Port A Selection 0 */
+sfr_b(PASEL0_L); /* Port A Selection 0 */
+sfr_b(PASEL0_H); /* Port A Selection 0 */
+sfr_w(PASEL1); /* Port A Selection 1 */
+sfr_b(PASEL1_L); /* Port A Selection 1 */
+sfr_b(PASEL1_H); /* Port A Selection 1 */
+sfr_w(PASELC); /* Port A Complement Selection */
+sfr_b(PASELC_L); /* Port A Complement Selection */
+sfr_b(PASELC_H); /* Port A Complement Selection */
+sfr_w(PAIES); /* Port A Interrupt Edge Select */
+sfr_b(PAIES_L); /* Port A Interrupt Edge Select */
+sfr_b(PAIES_H); /* Port A Interrupt Edge Select */
+sfr_w(PAIE); /* Port A Interrupt Enable */
+sfr_b(PAIE_L); /* Port A Interrupt Enable */
+sfr_b(PAIE_H); /* Port A Interrupt Enable */
+sfr_w(PAIFG); /* Port A Interrupt Flag */
+sfr_b(PAIFG_L); /* Port A Interrupt Flag */
+sfr_b(PAIFG_H); /* Port A Interrupt Flag */
+
+
+sfr_w(P1IV); /* Port 1 Interrupt Vector Word */
+sfr_w(P2IV); /* Port 2 Interrupt Vector Word */
+#define P1IN (PAIN_L) /* Port 1 Input */
+#define P1OUT (PAOUT_L) /* Port 1 Output */
+#define P1DIR (PADIR_L) /* Port 1 Direction */
+#define P1REN (PAREN_L) /* Port 1 Resistor Enable */
+#define P1SEL0 (PASEL0_L) /* Port 1 Selection 0 */
+#define P1SEL1 (PASEL1_L) /* Port 1 Selection 1 */
+#define P1SELC (PASELC_L) /* Port 1 Complement Selection */
+#define P1IES (PAIES_L) /* Port 1 Interrupt Edge Select */
+#define P1IE (PAIE_L) /* Port 1 Interrupt Enable */
+#define P1IFG (PAIFG_L) /* Port 1 Interrupt Flag */
+
+//Definitions for P1IV
+#define P1IV_NONE (0x0000) /* No Interrupt pending */
+#define P1IV_P1IFG0 (0x0002) /* P1IV P1IFG.0 */
+#define P1IV_P1IFG1 (0x0004) /* P1IV P1IFG.1 */
+#define P1IV_P1IFG2 (0x0006) /* P1IV P1IFG.2 */
+#define P1IV_P1IFG3 (0x0008) /* P1IV P1IFG.3 */
+#define P1IV_P1IFG4 (0x000A) /* P1IV P1IFG.4 */
+#define P1IV_P1IFG5 (0x000C) /* P1IV P1IFG.5 */
+#define P1IV_P1IFG6 (0x000E) /* P1IV P1IFG.6 */
+#define P1IV_P1IFG7 (0x0010) /* P1IV P1IFG.7 */
+
+#define P2IN (PAIN_H) /* Port 2 Input */
+#define P2OUT (PAOUT_H) /* Port 2 Output */
+#define P2DIR (PADIR_H) /* Port 2 Direction */
+#define P2REN (PAREN_H) /* Port 2 Resistor Enable */
+#define P2SEL0 (PASEL0_H) /* Port 2 Selection 0 */
+#define P2SEL1 (PASEL1_H) /* Port 2 Selection 1 */
+#define P2SELC (PASELC_H) /* Port 2 Complement Selection */
+#define P2IES (PAIES_H) /* Port 2 Interrupt Edge Select */
+#define P2IE (PAIE_H) /* Port 2 Interrupt Enable */
+#define P2IFG (PAIFG_H) /* Port 2 Interrupt Flag */
+
+//Definitions for P2IV
+#define P2IV_NONE (0x0000) /* No Interrupt pending */
+#define P2IV_P2IFG0 (0x0002) /* P2IV P2IFG.0 */
+#define P2IV_P2IFG1 (0x0004) /* P2IV P2IFG.1 */
+#define P2IV_P2IFG2 (0x0006) /* P2IV P2IFG.2 */
+#define P2IV_P2IFG3 (0x0008) /* P2IV P2IFG.3 */
+#define P2IV_P2IFG4 (0x000A) /* P2IV P2IFG.4 */
+#define P2IV_P2IFG5 (0x000C) /* P2IV P2IFG.5 */
+#define P2IV_P2IFG6 (0x000E) /* P2IV P2IFG.6 */
+#define P2IV_P2IFG7 (0x0010) /* P2IV P2IFG.7 */
+
+
+/************************************************************
+* DIGITAL I/O Port3/4 Pull up / Pull down Resistors
+************************************************************/
+#define __MSP430_HAS_PORT3_R__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORT3_R__ 0x0220
+#define P3_BASE __MSP430_BASEADDRESS_PORT3_R__
+#define __MSP430_HAS_PORT4_R__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORT4_R__ 0x0220
+#define P4_BASE __MSP430_BASEADDRESS_PORT4_R__
+#define __MSP430_HAS_PORTB_R__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORTB_R__ 0x0220
+#define PB_BASE __MSP430_BASEADDRESS_PORTB_R__
+#define __MSP430_HAS_P3SEL0__ /* Define for DriverLib */
+#define __MSP430_HAS_P4SEL0__ /* Define for DriverLib */
+#define __MSP430_HAS_PBSEL0__ /* Define for DriverLib */
+#define __MSP430_HAS_P3SEL1__ /* Define for DriverLib */
+#define __MSP430_HAS_P4SEL1__ /* Define for DriverLib */
+#define __MSP430_HAS_PBSEL1__ /* Define for DriverLib */
+
+sfr_w(PBIN); /* Port B Input */
+sfr_b(PBIN_L); /* Port B Input */
+sfr_b(PBIN_H); /* Port B Input */
+sfr_w(PBOUT); /* Port B Output */
+sfr_b(PBOUT_L); /* Port B Output */
+sfr_b(PBOUT_H); /* Port B Output */
+sfr_w(PBDIR); /* Port B Direction */
+sfr_b(PBDIR_L); /* Port B Direction */
+sfr_b(PBDIR_H); /* Port B Direction */
+sfr_w(PBREN); /* Port B Resistor Enable */
+sfr_b(PBREN_L); /* Port B Resistor Enable */
+sfr_b(PBREN_H); /* Port B Resistor Enable */
+sfr_w(PBSEL0); /* Port B Selection 0 */
+sfr_b(PBSEL0_L); /* Port B Selection 0 */
+sfr_b(PBSEL0_H); /* Port B Selection 0 */
+sfr_w(PBSEL1); /* Port B Selection 1 */
+sfr_b(PBSEL1_L); /* Port B Selection 1 */
+sfr_b(PBSEL1_H); /* Port B Selection 1 */
+sfr_w(PBSELC); /* Port B Complement Selection */
+sfr_b(PBSELC_L); /* Port B Complement Selection */
+sfr_b(PBSELC_H); /* Port B Complement Selection */
+sfr_w(PBIES); /* Port B Interrupt Edge Select */
+sfr_b(PBIES_L); /* Port B Interrupt Edge Select */
+sfr_b(PBIES_H); /* Port B Interrupt Edge Select */
+sfr_w(PBIE); /* Port B Interrupt Enable */
+sfr_b(PBIE_L); /* Port B Interrupt Enable */
+sfr_b(PBIE_H); /* Port B Interrupt Enable */
+sfr_w(PBIFG); /* Port B Interrupt Flag */
+sfr_b(PBIFG_L); /* Port B Interrupt Flag */
+sfr_b(PBIFG_H); /* Port B Interrupt Flag */
+
+
+sfr_w(P3IV); /* Port 3 Interrupt Vector Word */
+sfr_w(P4IV); /* Port 4 Interrupt Vector Word */
+#define P3IN (PBIN_L) /* Port 3 Input */
+#define P3OUT (PBOUT_L) /* Port 3 Output */
+#define P3DIR (PBDIR_L) /* Port 3 Direction */
+#define P3REN (PBREN_L) /* Port 3 Resistor Enable */
+#define P3SEL0 (PBSEL0_L) /* Port 3 Selection 0 */
+#define P3SEL1 (PBSEL1_L) /* Port 3 Selection 1 */
+#define P3SELC (PBSELC_L) /* Port 3 Complement Selection */
+#define P3IES (PBIES_L) /* Port 3 Interrupt Edge Select */
+#define P3IE (PBIE_L) /* Port 3 Interrupt Enable */
+#define P3IFG (PBIFG_L) /* Port 3 Interrupt Flag */
+
+//Definitions for P3IV
+#define P3IV_NONE (0x0000) /* No Interrupt pending */
+#define P3IV_P3IFG0 (0x0002) /* P3IV P3IFG.0 */
+#define P3IV_P3IFG1 (0x0004) /* P3IV P3IFG.1 */
+#define P3IV_P3IFG2 (0x0006) /* P3IV P3IFG.2 */
+#define P3IV_P3IFG3 (0x0008) /* P3IV P3IFG.3 */
+#define P3IV_P3IFG4 (0x000A) /* P3IV P3IFG.4 */
+#define P3IV_P3IFG5 (0x000C) /* P3IV P3IFG.5 */
+#define P3IV_P3IFG6 (0x000E) /* P3IV P3IFG.6 */
+#define P3IV_P3IFG7 (0x0010) /* P3IV P3IFG.7 */
+
+#define P4IN (PBIN_H) /* Port 4 Input */
+#define P4OUT (PBOUT_H) /* Port 4 Output */
+#define P4DIR (PBDIR_H) /* Port 4 Direction */
+#define P4REN (PBREN_H) /* Port 4 Resistor Enable */
+#define P4SEL0 (PBSEL0_H) /* Port 4 Selection 0 */
+#define P4SEL1 (PBSEL1_H) /* Port 4 Selection 1 */
+#define P4SELC (PBSELC_H) /* Port 4 Complement Selection */
+#define P4IES (PBIES_H) /* Port 4 Interrupt Edge Select */
+#define P4IE (PBIE_H) /* Port 4 Interrupt Enable */
+#define P4IFG (PBIFG_H) /* Port 4 Interrupt Flag */
+
+//Definitions for P4IV
+#define P4IV_NONE (0x0000) /* No Interrupt pending */
+#define P4IV_P4IFG0 (0x0002) /* P4IV P4IFG.0 */
+#define P4IV_P4IFG1 (0x0004) /* P4IV P4IFG.1 */
+#define P4IV_P4IFG2 (0x0006) /* P4IV P4IFG.2 */
+#define P4IV_P4IFG3 (0x0008) /* P4IV P4IFG.3 */
+#define P4IV_P4IFG4 (0x000A) /* P4IV P4IFG.4 */
+#define P4IV_P4IFG5 (0x000C) /* P4IV P4IFG.5 */
+#define P4IV_P4IFG6 (0x000E) /* P4IV P4IFG.6 */
+#define P4IV_P4IFG7 (0x0010) /* P4IV P4IFG.7 */
+
+
+/************************************************************
+* DIGITAL I/O PortJ Pull up / Pull down Resistors
+************************************************************/
+#define __MSP430_HAS_PORTJ_R__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORTJ_R__ 0x0320
+#define PJ_BASE __MSP430_BASEADDRESS_PORTJ_R__
+#define __MSP430_HAS_PJSEL0__ /* Define for DriverLib */
+#define __MSP430_HAS_PJSEL1__ /* Define for DriverLib */
+
+sfr_w(PJIN); /* Port J Input */
+sfr_b(PJIN_L); /* Port J Input */
+sfr_b(PJIN_H); /* Port J Input */
+sfr_w(PJOUT); /* Port J Output */
+sfr_b(PJOUT_L); /* Port J Output */
+sfr_b(PJOUT_H); /* Port J Output */
+sfr_w(PJDIR); /* Port J Direction */
+sfr_b(PJDIR_L); /* Port J Direction */
+sfr_b(PJDIR_H); /* Port J Direction */
+sfr_w(PJREN); /* Port J Resistor Enable */
+sfr_b(PJREN_L); /* Port J Resistor Enable */
+sfr_b(PJREN_H); /* Port J Resistor Enable */
+sfr_w(PJSEL0); /* Port J Selection 0 */
+sfr_b(PJSEL0_L); /* Port J Selection 0 */
+sfr_b(PJSEL0_H); /* Port J Selection 0 */
+sfr_w(PJSEL1); /* Port J Selection 1 */
+sfr_b(PJSEL1_L); /* Port J Selection 1 */
+sfr_b(PJSEL1_H); /* Port J Selection 1 */
+sfr_w(PJSELC); /* Port J Complement Selection */
+sfr_b(PJSELC_L); /* Port J Complement Selection */
+sfr_b(PJSELC_H); /* Port J Complement Selection */
+
+/************************************************************
+* Shared Reference
+************************************************************/
+#define __MSP430_HAS_REF_A__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_REF_A__ 0x01B0
+#define REF_A_BASE __MSP430_BASEADDRESS_REF_A__
+
+sfr_w(REFCTL0); /* REF Shared Reference control register 0 */
+sfr_b(REFCTL0_L); /* REF Shared Reference control register 0 */
+sfr_b(REFCTL0_H); /* REF Shared Reference control register 0 */
+
+/* REFCTL0 Control Bits */
+#define REFON (0x0001) /* REF Reference On */
+#define REFOUT (0x0002) /* REF Reference output Buffer On */
+//#define RESERVED (0x0004) /* Reserved */
+#define REFTCOFF (0x0008) /* REF Temp.Sensor off */
+#define REFVSEL0 (0x0010) /* REF Reference Voltage Level Select Bit:0 */
+#define REFVSEL1 (0x0020) /* REF Reference Voltage Level Select Bit:1 */
+#define REFGENOT (0x0040) /* REF Reference generator one-time trigger */
+#define REFBGOT (0x0080) /* REF Bandgap and bandgap buffer one-time trigger */
+#define REFGENACT (0x0100) /* REF Reference generator active */
+#define REFBGACT (0x0200) /* REF Reference bandgap active */
+#define REFGENBUSY (0x0400) /* REF Reference generator busy */
+#define BGMODE (0x0800) /* REF Bandgap mode */
+#define REFGENRDY (0x1000) /* REF Reference generator ready */
+#define REFBGRDY (0x2000) /* REF Reference bandgap ready */
+//#define RESERVED (0x4000) /* Reserved */
+//#define RESERVED (0x8000) /* Reserved */
+
+/* REFCTL0 Control Bits */
+#define REFON_L (0x0001) /* REF Reference On */
+#define REFOUT_L (0x0002) /* REF Reference output Buffer On */
+//#define RESERVED (0x0004) /* Reserved */
+#define REFTCOFF_L (0x0008) /* REF Temp.Sensor off */
+#define REFVSEL0_L (0x0010) /* REF Reference Voltage Level Select Bit:0 */
+#define REFVSEL1_L (0x0020) /* REF Reference Voltage Level Select Bit:1 */
+#define REFGENOT_L (0x0040) /* REF Reference generator one-time trigger */
+#define REFBGOT_L (0x0080) /* REF Bandgap and bandgap buffer one-time trigger */
+//#define RESERVED (0x4000) /* Reserved */
+//#define RESERVED (0x8000) /* Reserved */
+
+/* REFCTL0 Control Bits */
+//#define RESERVED (0x0004) /* Reserved */
+#define REFGENACT_H (0x0001) /* REF Reference generator active */
+#define REFBGACT_H (0x0002) /* REF Reference bandgap active */
+#define REFGENBUSY_H (0x0004) /* REF Reference generator busy */
+#define BGMODE_H (0x0008) /* REF Bandgap mode */
+#define REFGENRDY_H (0x0010) /* REF Reference generator ready */
+#define REFBGRDY_H (0x0020) /* REF Reference bandgap ready */
+//#define RESERVED (0x4000) /* Reserved */
+//#define RESERVED (0x8000) /* Reserved */
+
+#define REFVSEL_0 (0x0000) /* REF Reference Voltage Level Select 1.2V */
+#define REFVSEL_1 (0x0010) /* REF Reference Voltage Level Select 2.0V */
+#define REFVSEL_2 (0x0020) /* REF Reference Voltage Level Select 2.5V */
+#define REFVSEL_3 (0x0030) /* REF Reference Voltage Level Select 2.5V */
+
+/************************************************************
+* Real Time Clock
+************************************************************/
+#define __MSP430_HAS_RTC_B__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_RTC_B__ 0x04A0
+#define RTC_B_BASE __MSP430_BASEADDRESS_RTC_B__
+
+sfr_w(RTCCTL01); /* Real Timer Control 0/1 */
+sfr_b(RTCCTL01_L); /* Real Timer Control 0/1 */
+sfr_b(RTCCTL01_H); /* Real Timer Control 0/1 */
+sfr_w(RTCCTL23); /* Real Timer Control 2/3 */
+sfr_b(RTCCTL23_L); /* Real Timer Control 2/3 */
+sfr_b(RTCCTL23_H); /* Real Timer Control 2/3 */
+sfr_w(RTCPS0CTL); /* Real Timer Prescale Timer 0 Control */
+sfr_b(RTCPS0CTL_L); /* Real Timer Prescale Timer 0 Control */
+sfr_b(RTCPS0CTL_H); /* Real Timer Prescale Timer 0 Control */
+sfr_w(RTCPS1CTL); /* Real Timer Prescale Timer 1 Control */
+sfr_b(RTCPS1CTL_L); /* Real Timer Prescale Timer 1 Control */
+sfr_b(RTCPS1CTL_H); /* Real Timer Prescale Timer 1 Control */
+sfr_w(RTCPS); /* Real Timer Prescale Timer Control */
+sfr_b(RTCPS_L); /* Real Timer Prescale Timer Control */
+sfr_b(RTCPS_H); /* Real Timer Prescale Timer Control */
+sfr_w(RTCIV); /* Real Time Clock Interrupt Vector */
+sfr_w(RTCTIM0); /* Real Time Clock Time 0 */
+sfr_b(RTCTIM0_L); /* Real Time Clock Time 0 */
+sfr_b(RTCTIM0_H); /* Real Time Clock Time 0 */
+sfr_w(RTCTIM1); /* Real Time Clock Time 1 */
+sfr_b(RTCTIM1_L); /* Real Time Clock Time 1 */
+sfr_b(RTCTIM1_H); /* Real Time Clock Time 1 */
+sfr_w(RTCDATE); /* Real Time Clock Date */
+sfr_b(RTCDATE_L); /* Real Time Clock Date */
+sfr_b(RTCDATE_H); /* Real Time Clock Date */
+sfr_w(RTCYEAR); /* Real Time Clock Year */
+sfr_b(RTCYEAR_L); /* Real Time Clock Year */
+sfr_b(RTCYEAR_H); /* Real Time Clock Year */
+sfr_w(RTCAMINHR); /* Real Time Clock Alarm Min/Hour */
+sfr_b(RTCAMINHR_L); /* Real Time Clock Alarm Min/Hour */
+sfr_b(RTCAMINHR_H); /* Real Time Clock Alarm Min/Hour */
+sfr_w(RTCADOWDAY); /* Real Time Clock Alarm day of week/day */
+sfr_b(RTCADOWDAY_L); /* Real Time Clock Alarm day of week/day */
+sfr_b(RTCADOWDAY_H); /* Real Time Clock Alarm day of week/day */
+sfr_w(BIN2BCD); /* Real Time Binary-to-BCD conversion register */
+sfr_w(BCD2BIN); /* Real Time BCD-to-binary conversion register */
+
+#define RTCCTL0 RTCCTL01_L /* Real Time Clock Control 0 */
+#define RTCCTL1 RTCCTL01_H /* Real Time Clock Control 1 */
+#define RTCCTL2 RTCCTL23_L /* Real Time Clock Control 2 */
+#define RTCCTL3 RTCCTL23_H /* Real Time Clock Control 3 */
+#define RTCNT12 RTCTIM0
+#define RTCNT34 RTCTIM1
+#define RTCNT1 RTCTIM0_L
+#define RTCNT2 RTCTIM0_H
+#define RTCNT3 RTCTIM1_L
+#define RTCNT4 RTCTIM1_H
+#define RTCSEC RTCTIM0_L
+#define RTCMIN RTCTIM0_H
+#define RTCHOUR RTCTIM1_L
+#define RTCDOW RTCTIM1_H
+#define RTCDAY RTCDATE_L
+#define RTCMON RTCDATE_H
+#define RTCYEARL RTCYEAR_L
+#define RTCYEARH RTCYEAR_H
+#define RT0PS RTCPS_L
+#define RT1PS RTCPS_H
+#define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */
+#define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */
+#define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */
+#define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */
+
+/* RTCCTL01 Control Bits */
+#define RTCBCD (0x8000) /* RTC BCD 0:Binary / 1:BCD */
+#define RTCHOLD (0x4000) /* RTC Hold */
+//#define RESERVED (0x2000) /* RESERVED */
+#define RTCRDY (0x1000) /* RTC Ready */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x0400) /* RESERVED */
+#define RTCTEV1 (0x0200) /* RTC Time Event 1 */
+#define RTCTEV0 (0x0100) /* RTC Time Event 0 */
+#define RTCOFIE (0x0080) /* RTC 32kHz cyrstal oscillator fault interrupt enable */
+#define RTCTEVIE (0x0040) /* RTC Time Event Interrupt Enable Flag */
+#define RTCAIE (0x0020) /* RTC Alarm Interrupt Enable Flag */
+#define RTCRDYIE (0x0010) /* RTC Ready Interrupt Enable Flag */
+#define RTCOFIFG (0x0008) /* RTC 32kHz cyrstal oscillator fault interrupt flag */
+#define RTCTEVIFG (0x0004) /* RTC Time Event Interrupt Flag */
+#define RTCAIFG (0x0002) /* RTC Alarm Interrupt Flag */
+#define RTCRDYIFG (0x0001) /* RTC Ready Interrupt Flag */
+
+/* RTCCTL01 Control Bits */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x0400) /* RESERVED */
+#define RTCOFIE_L (0x0080) /* RTC 32kHz cyrstal oscillator fault interrupt enable */
+#define RTCTEVIE_L (0x0040) /* RTC Time Event Interrupt Enable Flag */
+#define RTCAIE_L (0x0020) /* RTC Alarm Interrupt Enable Flag */
+#define RTCRDYIE_L (0x0010) /* RTC Ready Interrupt Enable Flag */
+#define RTCOFIFG_L (0x0008) /* RTC 32kHz cyrstal oscillator fault interrupt flag */
+#define RTCTEVIFG_L (0x0004) /* RTC Time Event Interrupt Flag */
+#define RTCAIFG_L (0x0002) /* RTC Alarm Interrupt Flag */
+#define RTCRDYIFG_L (0x0001) /* RTC Ready Interrupt Flag */
+
+/* RTCCTL01 Control Bits */
+#define RTCBCD_H (0x0080) /* RTC BCD 0:Binary / 1:BCD */
+#define RTCHOLD_H (0x0040) /* RTC Hold */
+//#define RESERVED (0x2000) /* RESERVED */
+#define RTCRDY_H (0x0010) /* RTC Ready */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x0400) /* RESERVED */
+#define RTCTEV1_H (0x0002) /* RTC Time Event 1 */
+#define RTCTEV0_H (0x0001) /* RTC Time Event 0 */
+
+#define RTCTEV_0 (0x0000) /* RTC Time Event: 0 (Min. changed) */
+#define RTCTEV_1 (0x0100) /* RTC Time Event: 1 (Hour changed) */
+#define RTCTEV_2 (0x0200) /* RTC Time Event: 2 (12:00 changed) */
+#define RTCTEV_3 (0x0300) /* RTC Time Event: 3 (00:00 changed) */
+#define RTCTEV__MIN (0x0000) /* RTC Time Event: 0 (Min. changed) */
+#define RTCTEV__HOUR (0x0100) /* RTC Time Event: 1 (Hour changed) */
+#define RTCTEV__0000 (0x0200) /* RTC Time Event: 2 (00:00 changed) */
+#define RTCTEV__1200 (0x0300) /* RTC Time Event: 3 (12:00 changed) */
+
+/* RTCCTL23 Control Bits */
+#define RTCCALF1 (0x0200) /* RTC Calibration Frequency Bit 1 */
+#define RTCCALF0 (0x0100) /* RTC Calibration Frequency Bit 0 */
+#define RTCCALS (0x0080) /* RTC Calibration Sign */
+//#define Reserved (0x0040)
+#define RTCCAL5 (0x0020) /* RTC Calibration Bit 5 */
+#define RTCCAL4 (0x0010) /* RTC Calibration Bit 4 */
+#define RTCCAL3 (0x0008) /* RTC Calibration Bit 3 */
+#define RTCCAL2 (0x0004) /* RTC Calibration Bit 2 */
+#define RTCCAL1 (0x0002) /* RTC Calibration Bit 1 */
+#define RTCCAL0 (0x0001) /* RTC Calibration Bit 0 */
+
+/* RTCCTL23 Control Bits */
+#define RTCCALS_L (0x0080) /* RTC Calibration Sign */
+//#define Reserved (0x0040)
+#define RTCCAL5_L (0x0020) /* RTC Calibration Bit 5 */
+#define RTCCAL4_L (0x0010) /* RTC Calibration Bit 4 */
+#define RTCCAL3_L (0x0008) /* RTC Calibration Bit 3 */
+#define RTCCAL2_L (0x0004) /* RTC Calibration Bit 2 */
+#define RTCCAL1_L (0x0002) /* RTC Calibration Bit 1 */
+#define RTCCAL0_L (0x0001) /* RTC Calibration Bit 0 */
+
+/* RTCCTL23 Control Bits */
+#define RTCCALF1_H (0x0002) /* RTC Calibration Frequency Bit 1 */
+#define RTCCALF0_H (0x0001) /* RTC Calibration Frequency Bit 0 */
+//#define Reserved (0x0040)
+
+#define RTCCALF_0 (0x0000) /* RTC Calibration Frequency: No Output */
+#define RTCCALF_1 (0x0100) /* RTC Calibration Frequency: 512 Hz */
+#define RTCCALF_2 (0x0200) /* RTC Calibration Frequency: 256 Hz */
+#define RTCCALF_3 (0x0300) /* RTC Calibration Frequency: 1 Hz */
+
+#define RTCAE (0x80) /* Real Time Clock Alarm enable */
+
+/* RTCPS0CTL Control Bits */
+//#define Reserved (0x0080)
+//#define Reserved (0x0040)
+//#define Reserved (0x0020)
+#define RT0IP2 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
+#define RT0IP1 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
+#define RT0IP0 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
+#define RT0PSIE (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */
+#define RT0PSIFG (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */
+
+/* RTCPS0CTL Control Bits */
+//#define Reserved (0x0080)
+//#define Reserved (0x0040)
+//#define Reserved (0x0020)
+#define RT0IP2_L (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
+#define RT0IP1_L (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
+#define RT0IP0_L (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
+#define RT0PSIE_L (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */
+#define RT0PSIFG_L (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */
+
+#define RT0IP_0 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */
+#define RT0IP_1 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */
+#define RT0IP_2 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */
+#define RT0IP_3 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */
+#define RT0IP_4 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */
+#define RT0IP_5 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */
+#define RT0IP_6 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */
+#define RT0IP_7 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */
+
+#define RT0IP__2 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */
+#define RT0IP__4 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */
+#define RT0IP__8 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */
+#define RT0IP__16 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */
+#define RT0IP__32 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */
+#define RT0IP__64 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */
+#define RT0IP__128 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */
+#define RT0IP__256 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */
+
+/* RTCPS1CTL Control Bits */
+//#define Reserved (0x0080)
+//#define Reserved (0x0040)
+//#define Reserved (0x0020)
+#define RT1IP2 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
+#define RT1IP1 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
+#define RT1IP0 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
+#define RT1PSIE (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */
+#define RT1PSIFG (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */
+
+/* RTCPS1CTL Control Bits */
+//#define Reserved (0x0080)
+//#define Reserved (0x0040)
+//#define Reserved (0x0020)
+#define RT1IP2_L (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
+#define RT1IP1_L (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
+#define RT1IP0_L (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
+#define RT1PSIE_L (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */
+#define RT1PSIFG_L (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */
+
+#define RT1IP_0 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */
+#define RT1IP_1 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */
+#define RT1IP_2 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */
+#define RT1IP_3 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */
+#define RT1IP_4 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */
+#define RT1IP_5 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */
+#define RT1IP_6 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */
+#define RT1IP_7 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */
+
+#define RT1IP__2 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */
+#define RT1IP__4 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */
+#define RT1IP__8 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */
+#define RT1IP__16 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */
+#define RT1IP__32 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */
+#define RT1IP__64 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */
+#define RT1IP__128 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */
+#define RT1IP__256 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */
+
+/* RTC Definitions */
+#define RTCIV_NONE (0x0000) /* No Interrupt pending */
+#define RTCIV_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */
+#define RTCIV_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */
+#define RTCIV_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */
+#define RTCIV_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */
+#define RTCIV_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */
+#define RTCIV_RTCOFIFG (0x000C) /* RTC Oscillator fault */
+
+/* Legacy Definitions */
+#define RTC_NONE (0x0000) /* No Interrupt pending */
+#define RTC_RTCRDYIFG (0x0002) /* RTC ready: RTCRDYIFG */
+#define RTC_RTCTEVIFG (0x0004) /* RTC interval timer: RTCTEVIFG */
+#define RTC_RTCAIFG (0x0006) /* RTC user alarm: RTCAIFG */
+#define RTC_RT0PSIFG (0x0008) /* RTC prescaler 0: RT0PSIFG */
+#define RTC_RT1PSIFG (0x000A) /* RTC prescaler 1: RT1PSIFG */
+#define RTC_RTCOFIFG (0x000C) /* RTC Oscillator fault */
+
+/************************************************************
+* SFR - Special Function Register Module
+************************************************************/
+#define __MSP430_HAS_SFR__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_SFR__ 0x0100
+#define SFR_BASE __MSP430_BASEADDRESS_SFR__
+
+sfr_w(SFRIE1); /* Interrupt Enable 1 */
+sfr_b(SFRIE1_L); /* Interrupt Enable 1 */
+sfr_b(SFRIE1_H); /* Interrupt Enable 1 */
+
+/* SFRIE1 Control Bits */
+#define WDTIE (0x0001) /* WDT Interrupt Enable */
+#define OFIE (0x0002) /* Osc Fault Enable */
+//#define Reserved (0x0004)
+#define VMAIE (0x0008) /* Vacant Memory Interrupt Enable */
+#define NMIIE (0x0010) /* NMI Interrupt Enable */
+#define JMBINIE (0x0040) /* JTAG Mail Box input Interrupt Enable */
+#define JMBOUTIE (0x0080) /* JTAG Mail Box output Interrupt Enable */
+
+#define WDTIE_L (0x0001) /* WDT Interrupt Enable */
+#define OFIE_L (0x0002) /* Osc Fault Enable */
+//#define Reserved (0x0004)
+#define VMAIE_L (0x0008) /* Vacant Memory Interrupt Enable */
+#define NMIIE_L (0x0010) /* NMI Interrupt Enable */
+#define JMBINIE_L (0x0040) /* JTAG Mail Box input Interrupt Enable */
+#define JMBOUTIE_L (0x0080) /* JTAG Mail Box output Interrupt Enable */
+
+sfr_w(SFRIFG1); /* Interrupt Flag 1 */
+sfr_b(SFRIFG1_L); /* Interrupt Flag 1 */
+sfr_b(SFRIFG1_H); /* Interrupt Flag 1 */
+/* SFRIFG1 Control Bits */
+#define WDTIFG (0x0001) /* WDT Interrupt Flag */
+#define OFIFG (0x0002) /* Osc Fault Flag */
+//#define Reserved (0x0004)
+#define VMAIFG (0x0008) /* Vacant Memory Interrupt Flag */
+#define NMIIFG (0x0010) /* NMI Interrupt Flag */
+//#define Reserved (0x0020)
+#define JMBINIFG (0x0040) /* JTAG Mail Box input Interrupt Flag */
+#define JMBOUTIFG (0x0080) /* JTAG Mail Box output Interrupt Flag */
+
+#define WDTIFG_L (0x0001) /* WDT Interrupt Flag */
+#define OFIFG_L (0x0002) /* Osc Fault Flag */
+//#define Reserved (0x0004)
+#define VMAIFG_L (0x0008) /* Vacant Memory Interrupt Flag */
+#define NMIIFG_L (0x0010) /* NMI Interrupt Flag */
+//#define Reserved (0x0020)
+#define JMBINIFG_L (0x0040) /* JTAG Mail Box input Interrupt Flag */
+#define JMBOUTIFG_L (0x0080) /* JTAG Mail Box output Interrupt Flag */
+
+sfr_w(SFRRPCR); /* RESET Pin Control Register */
+sfr_b(SFRRPCR_L); /* RESET Pin Control Register */
+sfr_b(SFRRPCR_H); /* RESET Pin Control Register */
+/* SFRRPCR Control Bits */
+#define SYSNMI (0x0001) /* NMI select */
+#define SYSNMIIES (0x0002) /* NMI edge select */
+#define SYSRSTUP (0x0004) /* RESET Pin pull down/up select */
+#define SYSRSTRE (0x0008) /* RESET Pin Resistor enable */
+
+#define SYSNMI_L (0x0001) /* NMI select */
+#define SYSNMIIES_L (0x0002) /* NMI edge select */
+#define SYSRSTUP_L (0x0004) /* RESET Pin pull down/up select */
+#define SYSRSTRE_L (0x0008) /* RESET Pin Resistor enable */
+
+/************************************************************
+* SYS - System Module
+************************************************************/
+#define __MSP430_HAS_SYS__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_SYS__ 0x0180
+#define SYS_BASE __MSP430_BASEADDRESS_SYS__
+
+sfr_w(SYSCTL); /* System control */
+sfr_b(SYSCTL_L); /* System control */
+sfr_b(SYSCTL_H); /* System control */
+sfr_w(SYSJMBC); /* JTAG mailbox control */
+sfr_b(SYSJMBC_L); /* JTAG mailbox control */
+sfr_b(SYSJMBC_H); /* JTAG mailbox control */
+sfr_w(SYSJMBI0); /* JTAG mailbox input 0 */
+sfr_b(SYSJMBI0_L); /* JTAG mailbox input 0 */
+sfr_b(SYSJMBI0_H); /* JTAG mailbox input 0 */
+sfr_w(SYSJMBI1); /* JTAG mailbox input 1 */
+sfr_b(SYSJMBI1_L); /* JTAG mailbox input 1 */
+sfr_b(SYSJMBI1_H); /* JTAG mailbox input 1 */
+sfr_w(SYSJMBO0); /* JTAG mailbox output 0 */
+sfr_b(SYSJMBO0_L); /* JTAG mailbox output 0 */
+sfr_b(SYSJMBO0_H); /* JTAG mailbox output 0 */
+sfr_w(SYSJMBO1); /* JTAG mailbox output 1 */
+sfr_b(SYSJMBO1_L); /* JTAG mailbox output 1 */
+sfr_b(SYSJMBO1_H); /* JTAG mailbox output 1 */
+
+sfr_w(SYSUNIV); /* User NMI vector generator */
+sfr_b(SYSUNIV_L); /* User NMI vector generator */
+sfr_b(SYSUNIV_H); /* User NMI vector generator */
+sfr_w(SYSSNIV); /* System NMI vector generator */
+sfr_b(SYSSNIV_L); /* System NMI vector generator */
+sfr_b(SYSSNIV_H); /* System NMI vector generator */
+sfr_w(SYSRSTIV); /* Reset vector generator */
+sfr_b(SYSRSTIV_L); /* Reset vector generator */
+sfr_b(SYSRSTIV_H); /* Reset vector generator */
+
+/* SYSCTL Control Bits */
+#define SYSRIVECT (0x0001) /* SYS - RAM based interrupt vectors */
+//#define RESERVED (0x0002) /* SYS - Reserved */
+#define SYSPMMPE (0x0004) /* SYS - PMM access protect */
+//#define RESERVED (0x0008) /* SYS - Reserved */
+#define SYSBSLIND (0x0010) /* SYS - TCK/RST indication detected */
+#define SYSJTAGPIN (0x0020) /* SYS - Dedicated JTAG pins enabled */
+//#define RESERVED (0x0040) /* SYS - Reserved */
+//#define RESERVED (0x0080) /* SYS - Reserved */
+//#define RESERVED (0x0100) /* SYS - Reserved */
+//#define RESERVED (0x0200) /* SYS - Reserved */
+//#define RESERVED (0x0400) /* SYS - Reserved */
+//#define RESERVED (0x0800) /* SYS - Reserved */
+//#define RESERVED (0x1000) /* SYS - Reserved */
+//#define RESERVED (0x2000) /* SYS - Reserved */
+//#define RESERVED (0x4000) /* SYS - Reserved */
+//#define RESERVED (0x8000) /* SYS - Reserved */
+
+/* SYSCTL Control Bits */
+#define SYSRIVECT_L (0x0001) /* SYS - RAM based interrupt vectors */
+//#define RESERVED (0x0002) /* SYS - Reserved */
+#define SYSPMMPE_L (0x0004) /* SYS - PMM access protect */
+//#define RESERVED (0x0008) /* SYS - Reserved */
+#define SYSBSLIND_L (0x0010) /* SYS - TCK/RST indication detected */
+#define SYSJTAGPIN_L (0x0020) /* SYS - Dedicated JTAG pins enabled */
+//#define RESERVED (0x0040) /* SYS - Reserved */
+//#define RESERVED (0x0080) /* SYS - Reserved */
+//#define RESERVED (0x0100) /* SYS - Reserved */
+//#define RESERVED (0x0200) /* SYS - Reserved */
+//#define RESERVED (0x0400) /* SYS - Reserved */
+//#define RESERVED (0x0800) /* SYS - Reserved */
+//#define RESERVED (0x1000) /* SYS - Reserved */
+//#define RESERVED (0x2000) /* SYS - Reserved */
+//#define RESERVED (0x4000) /* SYS - Reserved */
+//#define RESERVED (0x8000) /* SYS - Reserved */
+
+/* SYSJMBC Control Bits */
+#define JMBIN0FG (0x0001) /* SYS - Incoming JTAG Mailbox 0 Flag */
+#define JMBIN1FG (0x0002) /* SYS - Incoming JTAG Mailbox 1 Flag */
+#define JMBOUT0FG (0x0004) /* SYS - Outgoing JTAG Mailbox 0 Flag */
+#define JMBOUT1FG (0x0008) /* SYS - Outgoing JTAG Mailbox 1 Flag */
+#define JMBMODE (0x0010) /* SYS - JMB 16/32 Bit Mode */
+//#define RESERVED (0x0020) /* SYS - Reserved */
+#define JMBCLR0OFF (0x0040) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */
+#define JMBCLR1OFF (0x0080) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */
+//#define RESERVED (0x0100) /* SYS - Reserved */
+//#define RESERVED (0x0200) /* SYS - Reserved */
+//#define RESERVED (0x0400) /* SYS - Reserved */
+//#define RESERVED (0x0800) /* SYS - Reserved */
+//#define RESERVED (0x1000) /* SYS - Reserved */
+//#define RESERVED (0x2000) /* SYS - Reserved */
+//#define RESERVED (0x4000) /* SYS - Reserved */
+//#define RESERVED (0x8000) /* SYS - Reserved */
+
+/* SYSJMBC Control Bits */
+#define JMBIN0FG_L (0x0001) /* SYS - Incoming JTAG Mailbox 0 Flag */
+#define JMBIN1FG_L (0x0002) /* SYS - Incoming JTAG Mailbox 1 Flag */
+#define JMBOUT0FG_L (0x0004) /* SYS - Outgoing JTAG Mailbox 0 Flag */
+#define JMBOUT1FG_L (0x0008) /* SYS - Outgoing JTAG Mailbox 1 Flag */
+#define JMBMODE_L (0x0010) /* SYS - JMB 16/32 Bit Mode */
+//#define RESERVED (0x0020) /* SYS - Reserved */
+#define JMBCLR0OFF_L (0x0040) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */
+#define JMBCLR1OFF_L (0x0080) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */
+//#define RESERVED (0x0100) /* SYS - Reserved */
+//#define RESERVED (0x0200) /* SYS - Reserved */
+//#define RESERVED (0x0400) /* SYS - Reserved */
+//#define RESERVED (0x0800) /* SYS - Reserved */
+//#define RESERVED (0x1000) /* SYS - Reserved */
+//#define RESERVED (0x2000) /* SYS - Reserved */
+//#define RESERVED (0x4000) /* SYS - Reserved */
+//#define RESERVED (0x8000) /* SYS - Reserved */
+
+
+/* SYSUNIV Definitions */
+#define SYSUNIV_NONE (0x0000) /* No Interrupt pending */
+#define SYSUNIV_NMIIFG (0x0002) /* SYSUNIV : NMIIFG */
+#define SYSUNIV_OFIFG (0x0004) /* SYSUNIV : Osc. Fail - OFIFG */
+
+/* SYSSNIV Definitions */
+#define SYSSNIV_NONE (0x0000) /* No Interrupt pending */
+#define SYSSNIV_RES02 (0x0002) /* SYSSNIV : Reserved */
+#define SYSSNIV_UBDIFG (0x0004) /* SYSSNIV : FRAM Uncorrectable bit Error */
+#define SYSSNIV_RES06 (0x0006) /* SYSSNIV : Reserved */
+#define SYSSNIV_MPUSEGPIFG (0x0008) /* SYSSNIV : MPUSEGPIFG violation */
+#define SYSSNIV_MPUSEGIIFG (0x000A) /* SYSSNIV : MPUSEGIIFG violation */
+#define SYSSNIV_MPUSEG1IFG (0x000C) /* SYSSNIV : MPUSEG1IFG violation */
+#define SYSSNIV_MPUSEG2IFG (0x000E) /* SYSSNIV : MPUSEG2IFG violation */
+#define SYSSNIV_MPUSEG3IFG (0x0010) /* SYSSNIV : MPUSEG3IFG violation */
+#define SYSSNIV_VMAIFG (0x0012) /* SYSSNIV : VMAIFG */
+#define SYSSNIV_JMBINIFG (0x0014) /* SYSSNIV : JMBINIFG */
+#define SYSSNIV_JMBOUTIFG (0x0016) /* SYSSNIV : JMBOUTIFG */
+#define SYSSNIV_CBDIFG (0x0018) /* SYSSNIV : FRAM Correctable Bit error */
+
+/* SYSRSTIV Definitions */
+#define SYSRSTIV_NONE (0x0000) /* No Interrupt pending */
+#define SYSRSTIV_BOR (0x0002) /* SYSRSTIV : BOR */
+#define SYSRSTIV_RSTNMI (0x0004) /* SYSRSTIV : RST/NMI */
+#define SYSRSTIV_DOBOR (0x0006) /* SYSRSTIV : Do BOR */
+#define SYSRSTIV_LPM5WU (0x0008) /* SYSRSTIV : Port LPM5 Wake Up */
+#define SYSRSTIV_SECYV (0x000A) /* SYSRSTIV : Security violation */
+#define SYSRSTIV_RES0C (0x000C) /* SYSRSTIV : Reserved */
+#define SYSRSTIV_SVSHIFG (0x000E) /* SYSRSTIV : SVSHIFG */
+#define SYSRSTIV_RES10 (0x0010) /* SYSRSTIV : Reserved */
+#define SYSRSTIV_RES12 (0x0012) /* SYSRSTIV : Reserved */
+#define SYSRSTIV_DOPOR (0x0014) /* SYSRSTIV : Do POR */
+#define SYSRSTIV_WDTTO (0x0016) /* SYSRSTIV : WDT Time out */
+#define SYSRSTIV_WDTKEY (0x0018) /* SYSRSTIV : WDTKEY violation */
+#define SYSRSTIV_FRCTLPW (0x001A) /* SYSRSTIV : FRAM Key violation */
+#define SYSRSTIV_UBDIFG (0x001C) /* SYSRSTIV : FRAM Uncorrectable bit Error */
+#define SYSRSTIV_PERF (0x001E) /* SYSRSTIV : peripheral/config area fetch */
+#define SYSRSTIV_PMMPW (0x0020) /* SYSRSTIV : PMM Password violation */
+#define SYSRSTIV_MPUPW (0x0022) /* SYSRSTIV : MPU Password violation */
+#define SYSRSTIV_CSPW (0x0024) /* SYSRSTIV : CS Password violation */
+#define SYSRSTIV_MPUSEGPIFG (0x0026) /* SYSRSTIV : MPUSEGPIFG violation */
+#define SYSRSTIV_MPUSEGIIFG (0x0028) /* SYSRSTIV : MPUSEGIIFG violation */
+#define SYSRSTIV_MPUSEG1IFG (0x002A) /* SYSRSTIV : MPUSEG1IFG violation */
+#define SYSRSTIV_MPUSEG2IFG (0x002C) /* SYSRSTIV : MPUSEG2IFG violation */
+#define SYSRSTIV_MPUSEG3IFG (0x002E) /* SYSRSTIV : MPUSEG3IFG violation */
+#define SYSRSTIV_ACCTEIFG (0x0030) /* SYSRSTIV : ACCTEIFG access time error */
+
+/************************************************************
+* Timer0_A3
+************************************************************/
+#define __MSP430_HAS_T0A3__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_T0A3__ 0x0340
+#define TIMER_A0_BASE __MSP430_BASEADDRESS_T0A3__
+
+sfr_w(TA0CTL); /* Timer0_A3 Control */
+sfr_w(TA0CCTL0); /* Timer0_A3 Capture/Compare Control 0 */
+sfr_w(TA0CCTL1); /* Timer0_A3 Capture/Compare Control 1 */
+sfr_w(TA0CCTL2); /* Timer0_A3 Capture/Compare Control 2 */
+sfr_w(TA0R); /* Timer0_A3 */
+sfr_w(TA0CCR0); /* Timer0_A3 Capture/Compare 0 */
+sfr_w(TA0CCR1); /* Timer0_A3 Capture/Compare 1 */
+sfr_w(TA0CCR2); /* Timer0_A3 Capture/Compare 2 */
+sfr_w(TA0IV); /* Timer0_A3 Interrupt Vector Word */
+sfr_w(TA0EX0); /* Timer0_A3 Expansion Register 0 */
+
+/* TAxCTL Control Bits */
+#define TASSEL1 (0x0200) /* Timer A clock source select 1 */
+#define TASSEL0 (0x0100) /* Timer A clock source select 0 */
+#define ID1 (0x0080) /* Timer A clock input divider 1 */
+#define ID0 (0x0040) /* Timer A clock input divider 0 */
+#define MC1 (0x0020) /* Timer A mode control 1 */
+#define MC0 (0x0010) /* Timer A mode control 0 */
+#define TACLR (0x0004) /* Timer A counter clear */
+#define TAIE (0x0002) /* Timer A counter interrupt enable */
+#define TAIFG (0x0001) /* Timer A counter interrupt flag */
+
+#define MC_0 (0x0000) /* Timer A mode control: 0 - Stop */
+#define MC_1 (0x0010) /* Timer A mode control: 1 - Up to CCR0 */
+#define MC_2 (0x0020) /* Timer A mode control: 2 - Continuous up */
+#define MC_3 (0x0030) /* Timer A mode control: 3 - Up/Down */
+#define ID_0 (0x0000) /* Timer A input divider: 0 - /1 */
+#define ID_1 (0x0040) /* Timer A input divider: 1 - /2 */
+#define ID_2 (0x0080) /* Timer A input divider: 2 - /4 */
+#define ID_3 (0x00C0) /* Timer A input divider: 3 - /8 */
+#define TASSEL_0 (0x0000) /* Timer A clock source select: 0 - TACLK */
+#define TASSEL_1 (0x0100) /* Timer A clock source select: 1 - ACLK */
+#define TASSEL_2 (0x0200) /* Timer A clock source select: 2 - SMCLK */
+#define TASSEL_3 (0x0300) /* Timer A clock source select: 3 - INCLK */
+#define MC__STOP (0x0000) /* Timer A mode control: 0 - Stop */
+#define MC__UP (0x0010) /* Timer A mode control: 1 - Up to CCR0 */
+#define MC__CONTINUOUS (0x0020) /* Timer A mode control: 2 - Continuous up */
+#define MC__CONTINOUS (0x0020) /* Legacy define */
+#define MC__UPDOWN (0x0030) /* Timer A mode control: 3 - Up/Down */
+#define ID__1 (0x0000) /* Timer A input divider: 0 - /1 */
+#define ID__2 (0x0040) /* Timer A input divider: 1 - /2 */
+#define ID__4 (0x0080) /* Timer A input divider: 2 - /4 */
+#define ID__8 (0x00C0) /* Timer A input divider: 3 - /8 */
+#define TASSEL__TACLK (0x0000) /* Timer A clock source select: 0 - TACLK */
+#define TASSEL__ACLK (0x0100) /* Timer A clock source select: 1 - ACLK */
+#define TASSEL__SMCLK (0x0200) /* Timer A clock source select: 2 - SMCLK */
+#define TASSEL__INCLK (0x0300) /* Timer A clock source select: 3 - INCLK */
+
+/* TAxCCTLx Control Bits */
+#define CM1 (0x8000) /* Capture mode 1 */
+#define CM0 (0x4000) /* Capture mode 0 */
+#define CCIS1 (0x2000) /* Capture input select 1 */
+#define CCIS0 (0x1000) /* Capture input select 0 */
+#define SCS (0x0800) /* Capture sychronize */
+#define SCCI (0x0400) /* Latched capture signal (read) */
+#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */
+#define OUTMOD2 (0x0080) /* Output mode 2 */
+#define OUTMOD1 (0x0040) /* Output mode 1 */
+#define OUTMOD0 (0x0020) /* Output mode 0 */
+#define CCIE (0x0010) /* Capture/compare interrupt enable */
+#define CCI (0x0008) /* Capture input signal (read) */
+#define OUT (0x0004) /* PWM Output signal if output mode 0 */
+#define COV (0x0002) /* Capture/compare overflow flag */
+#define CCIFG (0x0001) /* Capture/compare interrupt flag */
+
+#define OUTMOD_0 (0x0000) /* PWM output mode: 0 - output only */
+#define OUTMOD_1 (0x0020) /* PWM output mode: 1 - set */
+#define OUTMOD_2 (0x0040) /* PWM output mode: 2 - PWM toggle/reset */
+#define OUTMOD_3 (0x0060) /* PWM output mode: 3 - PWM set/reset */
+#define OUTMOD_4 (0x0080) /* PWM output mode: 4 - toggle */
+#define OUTMOD_5 (0x00A0) /* PWM output mode: 5 - Reset */
+#define OUTMOD_6 (0x00C0) /* PWM output mode: 6 - PWM toggle/set */
+#define OUTMOD_7 (0x00E0) /* PWM output mode: 7 - PWM reset/set */
+#define CCIS_0 (0x0000) /* Capture input select: 0 - CCIxA */
+#define CCIS_1 (0x1000) /* Capture input select: 1 - CCIxB */
+#define CCIS_2 (0x2000) /* Capture input select: 2 - GND */
+#define CCIS_3 (0x3000) /* Capture input select: 3 - Vcc */
+#define CM_0 (0x0000) /* Capture mode: 0 - disabled */
+#define CM_1 (0x4000) /* Capture mode: 1 - pos. edge */
+#define CM_2 (0x8000) /* Capture mode: 1 - neg. edge */
+#define CM_3 (0xC000) /* Capture mode: 1 - both edges */
+
+/* TAxEX0 Control Bits */
+#define TAIDEX0 (0x0001) /* Timer A Input divider expansion Bit: 0 */
+#define TAIDEX1 (0x0002) /* Timer A Input divider expansion Bit: 1 */
+#define TAIDEX2 (0x0004) /* Timer A Input divider expansion Bit: 2 */
+
+#define TAIDEX_0 (0x0000) /* Timer A Input divider expansion : /1 */
+#define TAIDEX_1 (0x0001) /* Timer A Input divider expansion : /2 */
+#define TAIDEX_2 (0x0002) /* Timer A Input divider expansion : /3 */
+#define TAIDEX_3 (0x0003) /* Timer A Input divider expansion : /4 */
+#define TAIDEX_4 (0x0004) /* Timer A Input divider expansion : /5 */
+#define TAIDEX_5 (0x0005) /* Timer A Input divider expansion : /6 */
+#define TAIDEX_6 (0x0006) /* Timer A Input divider expansion : /7 */
+#define TAIDEX_7 (0x0007) /* Timer A Input divider expansion : /8 */
+
+/* T0A3IV Definitions */
+#define TA0IV_NONE (0x0000) /* No Interrupt pending */
+#define TA0IV_TACCR1 (0x0002) /* TA0CCR1_CCIFG */
+#define TA0IV_TACCR2 (0x0004) /* TA0CCR2_CCIFG */
+#define TA0IV_3 (0x0006) /* Reserved */
+#define TA0IV_4 (0x0008) /* Reserved */
+#define TA0IV_5 (0x000A) /* Reserved */
+#define TA0IV_6 (0x000C) /* Reserved */
+#define TA0IV_TAIFG (0x000E) /* TA0IFG */
+
+/* Legacy Defines */
+#define TA0IV_TA0CCR1 (0x0002) /* TA0CCR1_CCIFG */
+#define TA0IV_TA0CCR2 (0x0004) /* TA0CCR2_CCIFG */
+#define TA0IV_TA0IFG (0x000E) /* TA0IFG */
+
+/************************************************************
+* Timer1_A3
+************************************************************/
+#define __MSP430_HAS_T1A3__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_T1A3__ 0x0380
+#define TIMER_A1_BASE __MSP430_BASEADDRESS_T1A3__
+
+sfr_w(TA1CTL); /* Timer1_A3 Control */
+sfr_w(TA1CCTL0); /* Timer1_A3 Capture/Compare Control 0 */
+sfr_w(TA1CCTL1); /* Timer1_A3 Capture/Compare Control 1 */
+sfr_w(TA1CCTL2); /* Timer1_A3 Capture/Compare Control 2 */
+sfr_w(TA1R); /* Timer1_A3 */
+sfr_w(TA1CCR0); /* Timer1_A3 Capture/Compare 0 */
+sfr_w(TA1CCR1); /* Timer1_A3 Capture/Compare 1 */
+sfr_w(TA1CCR2); /* Timer1_A3 Capture/Compare 2 */
+sfr_w(TA1IV); /* Timer1_A3 Interrupt Vector Word */
+sfr_w(TA1EX0); /* Timer1_A3 Expansion Register 0 */
+
+/* Bits are already defined within the Timer0_Ax */
+
+/* TA1IV Definitions */
+#define TA1IV_NONE (0x0000) /* No Interrupt pending */
+#define TA1IV_TACCR1 (0x0002) /* TA1CCR1_CCIFG */
+#define TA1IV_TACCR2 (0x0004) /* TA1CCR2_CCIFG */
+#define TA1IV_3 (0x0006) /* Reserved */
+#define TA1IV_4 (0x0008) /* Reserved */
+#define TA1IV_5 (0x000A) /* Reserved */
+#define TA1IV_6 (0x000C) /* Reserved */
+#define TA1IV_TAIFG (0x000E) /* TA1IFG */
+
+/* Legacy Defines */
+#define TA1IV_TA1CCR1 (0x0002) /* TA1CCR1_CCIFG */
+#define TA1IV_TA1CCR2 (0x0004) /* TA1CCR2_CCIFG */
+#define TA1IV_TA1IFG (0x000E) /* TA1IFG */
+
+/************************************************************
+* Timer2_A2
+************************************************************/
+#define __MSP430_HAS_T2A2__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_T2A2__ 0x0400
+#define TIMER_A2_BASE __MSP430_BASEADDRESS_T2A2__
+
+sfr_w(TA2CTL); /* Timer2_A2 Control */
+sfr_w(TA2CCTL0); /* Timer2_A2 Capture/Compare Control 0 */
+sfr_w(TA2CCTL1); /* Timer2_A2 Capture/Compare Control 1 */
+sfr_w(TA2R); /* Timer2_A2 */
+sfr_w(TA2CCR0); /* Timer2_A2 Capture/Compare 0 */
+sfr_w(TA2CCR1); /* Timer2_A2 Capture/Compare 1 */
+sfr_w(TA2IV); /* Timer2_A2 Interrupt Vector Word */
+sfr_w(TA2EX0); /* Timer2_A2 Expansion Register 0 */
+
+/* Bits are already defined within the Timer0_Ax */
+
+/* TA2IV Definitions */
+#define TA2IV_NONE (0x0000) /* No Interrupt pending */
+#define TA2IV_TACCR1 (0x0002) /* TA2CCR1_CCIFG */
+#define TA2IV_3 (0x0006) /* Reserved */
+#define TA2IV_4 (0x0008) /* Reserved */
+#define TA2IV_5 (0x000A) /* Reserved */
+#define TA2IV_6 (0x000C) /* Reserved */
+#define TA2IV_TAIFG (0x000E) /* TA2IFG */
+
+/* Legacy Defines */
+#define TA2IV_TA2CCR1 (0x0002) /* TA2CCR1_CCIFG */
+#define TA2IV_TA2IFG (0x000E) /* TA2IFG */
+
+/************************************************************
+* Timer3_A2
+************************************************************/
+#define __MSP430_HAS_T3A2__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_T3A2__ 0x0440
+#define TIMER_A3_BASE __MSP430_BASEADDRESS_T3A2__
+
+sfr_w(TA3CTL); /* Timer3_A2 Control */
+sfr_w(TA3CCTL0); /* Timer3_A2 Capture/Compare Control 0 */
+sfr_w(TA3CCTL1); /* Timer3_A2 Capture/Compare Control 1 */
+sfr_w(TA3R); /* Timer3_A2 */
+sfr_w(TA3CCR0); /* Timer3_A2 Capture/Compare 0 */
+sfr_w(TA3CCR1); /* Timer3_A2 Capture/Compare 1 */
+sfr_w(TA3IV); /* Timer3_A2 Interrupt Vector Word */
+sfr_w(TA3EX0); /* Timer3_A2 Expansion Register 0 */
+
+/* Bits are already defined within the Timer0_Ax */
+
+/* TA3IV Definitions */
+#define TA3IV_NONE (0x0000) /* No Interrupt pending */
+#define TA3IV_TACCR1 (0x0002) /* TA3CCR1_CCIFG */
+#define TA3IV_3 (0x0006) /* Reserved */
+#define TA3IV_4 (0x0008) /* Reserved */
+#define TA3IV_5 (0x000A) /* Reserved */
+#define TA3IV_6 (0x000C) /* Reserved */
+#define TA3IV_TAIFG (0x000E) /* TA3IFG */
+
+/* Legacy Defines */
+#define TA3IV_TA3CCR1 (0x0002) /* TA3CCR1_CCIFG */
+#define TA3IV_TA3IFG (0x000E) /* TA3IFG */
+
+/************************************************************
+* Timer0_B7
+************************************************************/
+#define __MSP430_HAS_T0B7__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_T0B7__ 0x03C0
+#define TIMER_B0_BASE __MSP430_BASEADDRESS_T0B7__
+
+sfr_w(TB0CTL); /* Timer0_B7 Control */
+sfr_w(TB0CCTL0); /* Timer0_B7 Capture/Compare Control 0 */
+sfr_w(TB0CCTL1); /* Timer0_B7 Capture/Compare Control 1 */
+sfr_w(TB0CCTL2); /* Timer0_B7 Capture/Compare Control 2 */
+sfr_w(TB0CCTL3); /* Timer0_B7 Capture/Compare Control 3 */
+sfr_w(TB0CCTL4); /* Timer0_B7 Capture/Compare Control 4 */
+sfr_w(TB0CCTL5); /* Timer0_B7 Capture/Compare Control 5 */
+sfr_w(TB0CCTL6); /* Timer0_B7 Capture/Compare Control 6 */
+sfr_w(TB0R); /* Timer0_B7 */
+sfr_w(TB0CCR0); /* Timer0_B7 Capture/Compare 0 */
+sfr_w(TB0CCR1); /* Timer0_B7 Capture/Compare 1 */
+sfr_w(TB0CCR2); /* Timer0_B7 Capture/Compare 2 */
+sfr_w(TB0CCR3); /* Timer0_B7 Capture/Compare 3 */
+sfr_w(TB0CCR4); /* Timer0_B7 Capture/Compare 4 */
+sfr_w(TB0CCR5); /* Timer0_B7 Capture/Compare 5 */
+sfr_w(TB0CCR6); /* Timer0_B7 Capture/Compare 6 */
+sfr_w(TB0EX0); /* Timer0_B7 Expansion Register 0 */
+sfr_w(TB0IV); /* Timer0_B7 Interrupt Vector Word */
+
+/* Legacy Type Definitions for TimerB */
+#define TBCTL TB0CTL /* Timer0_B7 Control */
+#define TBCCTL0 TB0CCTL0 /* Timer0_B7 Capture/Compare Control 0 */
+#define TBCCTL1 TB0CCTL1 /* Timer0_B7 Capture/Compare Control 1 */
+#define TBCCTL2 TB0CCTL2 /* Timer0_B7 Capture/Compare Control 2 */
+#define TBCCTL3 TB0CCTL3 /* Timer0_B7 Capture/Compare Control 3 */
+#define TBCCTL4 TB0CCTL4 /* Timer0_B7 Capture/Compare Control 4 */
+#define TBCCTL5 TB0CCTL5 /* Timer0_B7 Capture/Compare Control 5 */
+#define TBCCTL6 TB0CCTL6 /* Timer0_B7 Capture/Compare Control 6 */
+#define TBR TB0R /* Timer0_B7 */
+#define TBCCR0 TB0CCR0 /* Timer0_B7 Capture/Compare 0 */
+#define TBCCR1 TB0CCR1 /* Timer0_B7 Capture/Compare 1 */
+#define TBCCR2 TB0CCR2 /* Timer0_B7 Capture/Compare 2 */
+#define TBCCR3 TB0CCR3 /* Timer0_B7 Capture/Compare 3 */
+#define TBCCR4 TB0CCR4 /* Timer0_B7 Capture/Compare 4 */
+#define TBCCR5 TB0CCR5 /* Timer0_B7 Capture/Compare 5 */
+#define TBCCR6 TB0CCR6 /* Timer0_B7 Capture/Compare 6 */
+#define TBEX0 TB0EX0 /* Timer0_B7 Expansion Register 0 */
+#define TBIV TB0IV /* Timer0_B7 Interrupt Vector Word */
+#define TIMERB1_VECTOR TIMER0_B1_VECTOR /* Timer0_B7 CC1-6, TB */
+#define TIMERB0_VECTOR TIMER0_B0_VECTOR /* Timer0_B7 CC0 */
+
+/* TBxCTL Control Bits */
+#define TBCLGRP1 (0x4000) /* Timer0_B7 Compare latch load group 1 */
+#define TBCLGRP0 (0x2000) /* Timer0_B7 Compare latch load group 0 */
+#define CNTL1 (0x1000) /* Counter lenght 1 */
+#define CNTL0 (0x0800) /* Counter lenght 0 */
+#define TBSSEL1 (0x0200) /* Clock source 1 */
+#define TBSSEL0 (0x0100) /* Clock source 0 */
+#define TBCLR (0x0004) /* Timer0_B7 counter clear */
+#define TBIE (0x0002) /* Timer0_B7 interrupt enable */
+#define TBIFG (0x0001) /* Timer0_B7 interrupt flag */
+
+#define SHR1 (0x4000) /* Timer0_B7 Compare latch load group 1 */
+#define SHR0 (0x2000) /* Timer0_B7 Compare latch load group 0 */
+
+#define TBSSEL_0 (0x0000) /* Clock Source: TBCLK */
+#define TBSSEL_1 (0x0100) /* Clock Source: ACLK */
+#define TBSSEL_2 (0x0200) /* Clock Source: SMCLK */
+#define TBSSEL_3 (0x0300) /* Clock Source: INCLK */
+#define CNTL_0 (0x0000) /* Counter lenght: 16 bit */
+#define CNTL_1 (0x0800) /* Counter lenght: 12 bit */
+#define CNTL_2 (0x1000) /* Counter lenght: 10 bit */
+#define CNTL_3 (0x1800) /* Counter lenght: 8 bit */
+#define SHR_0 (0x0000) /* Timer0_B7 Group: 0 - individually */
+#define SHR_1 (0x2000) /* Timer0_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
+#define SHR_2 (0x4000) /* Timer0_B7 Group: 2 - 2 groups (1-3, 4-6)*/
+#define SHR_3 (0x6000) /* Timer0_B7 Group: 3 - 1 group (all) */
+#define TBCLGRP_0 (0x0000) /* Timer0_B7 Group: 0 - individually */
+#define TBCLGRP_1 (0x2000) /* Timer0_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
+#define TBCLGRP_2 (0x4000) /* Timer0_B7 Group: 2 - 2 groups (1-3, 4-6)*/
+#define TBCLGRP_3 (0x6000) /* Timer0_B7 Group: 3 - 1 group (all) */
+#define TBSSEL__TBCLK (0x0000) /* Timer0_B7 clock source select: 0 - TBCLK */
+#define TBSSEL__TACLK (0x0000) /* Timer0_B7 clock source select: 0 - TBCLK (legacy) */
+#define TBSSEL__ACLK (0x0100) /* Timer0_B7 clock source select: 1 - ACLK */
+#define TBSSEL__SMCLK (0x0200) /* Timer0_B7 clock source select: 2 - SMCLK */
+#define TBSSEL__INCLK (0x0300) /* Timer0_B7 clock source select: 3 - INCLK */
+#define CNTL__16 (0x0000) /* Counter lenght: 16 bit */
+#define CNTL__12 (0x0800) /* Counter lenght: 12 bit */
+#define CNTL__10 (0x1000) /* Counter lenght: 10 bit */
+#define CNTL__8 (0x1800) /* Counter lenght: 8 bit */
+
+/* Additional Timer B Control Register bits are defined in Timer A */
+/* TBxCCTLx Control Bits */
+#define CLLD1 (0x0400) /* Compare latch load source 1 */
+#define CLLD0 (0x0200) /* Compare latch load source 0 */
+
+#define SLSHR1 (0x0400) /* Compare latch load source 1 */
+#define SLSHR0 (0x0200) /* Compare latch load source 0 */
+
+#define SLSHR_0 (0x0000) /* Compare latch load sourec : 0 - immediate */
+#define SLSHR_1 (0x0200) /* Compare latch load sourec : 1 - TBR counts to 0 */
+#define SLSHR_2 (0x0400) /* Compare latch load sourec : 2 - up/down */
+#define SLSHR_3 (0x0600) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
+
+#define CLLD_0 (0x0000) /* Compare latch load sourec : 0 - immediate */
+#define CLLD_1 (0x0200) /* Compare latch load sourec : 1 - TBR counts to 0 */
+#define CLLD_2 (0x0400) /* Compare latch load sourec : 2 - up/down */
+#define CLLD_3 (0x0600) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
+
+/* TBxEX0 Control Bits */
+#define TBIDEX0 (0x0001) /* Timer0_B7 Input divider expansion Bit: 0 */
+#define TBIDEX1 (0x0002) /* Timer0_B7 Input divider expansion Bit: 1 */
+#define TBIDEX2 (0x0004) /* Timer0_B7 Input divider expansion Bit: 2 */
+
+#define TBIDEX_0 (0x0000) /* Timer0_B7 Input divider expansion : /1 */
+#define TBIDEX_1 (0x0001) /* Timer0_B7 Input divider expansion : /2 */
+#define TBIDEX_2 (0x0002) /* Timer0_B7 Input divider expansion : /3 */
+#define TBIDEX_3 (0x0003) /* Timer0_B7 Input divider expansion : /4 */
+#define TBIDEX_4 (0x0004) /* Timer0_B7 Input divider expansion : /5 */
+#define TBIDEX_5 (0x0005) /* Timer0_B7 Input divider expansion : /6 */
+#define TBIDEX_6 (0x0006) /* Timer0_B7 Input divider expansion : /7 */
+#define TBIDEX_7 (0x0007) /* Timer0_B7 Input divider expansion : /8 */
+#define TBIDEX__1 (0x0000) /* Timer0_B7 Input divider expansion : /1 */
+#define TBIDEX__2 (0x0001) /* Timer0_B7 Input divider expansion : /2 */
+#define TBIDEX__3 (0x0002) /* Timer0_B7 Input divider expansion : /3 */
+#define TBIDEX__4 (0x0003) /* Timer0_B7 Input divider expansion : /4 */
+#define TBIDEX__5 (0x0004) /* Timer0_B7 Input divider expansion : /5 */
+#define TBIDEX__6 (0x0005) /* Timer0_B7 Input divider expansion : /6 */
+#define TBIDEX__7 (0x0006) /* Timer0_B7 Input divider expansion : /7 */
+#define TBIDEX__8 (0x0007) /* Timer0_B7 Input divider expansion : /8 */
+
+/* TB0IV Definitions */
+#define TB0IV_NONE (0x0000) /* No Interrupt pending */
+#define TB0IV_TBCCR1 (0x0002) /* TB0CCR1_CCIFG */
+#define TB0IV_TBCCR2 (0x0004) /* TB0CCR2_CCIFG */
+#define TB0IV_TBCCR3 (0x0006) /* TB0CCR3_CCIFG */
+#define TB0IV_TBCCR4 (0x0008) /* TB0CCR4_CCIFG */
+#define TB0IV_TBCCR5 (0x000A) /* TB0CCR5_CCIFG */
+#define TB0IV_TBCCR6 (0x000C) /* TB0CCR6_CCIFG */
+#define TB0IV_TBIFG (0x000E) /* TB0IFG */
+
+/* Legacy Defines */
+#define TB0IV_TB0CCR1 (0x0002) /* TB0CCR1_CCIFG */
+#define TB0IV_TB0CCR2 (0x0004) /* TB0CCR2_CCIFG */
+#define TB0IV_TB0CCR3 (0x0006) /* TB0CCR3_CCIFG */
+#define TB0IV_TB0CCR4 (0x0008) /* TB0CCR4_CCIFG */
+#define TB0IV_TB0CCR5 (0x000A) /* TB0CCR5_CCIFG */
+#define TB0IV_TB0CCR6 (0x000C) /* TB0CCR6_CCIFG */
+#define TB0IV_TB0IFG (0x000E) /* TB0IFG */
+
+
+/************************************************************
+* USCI A0
+************************************************************/
+#define __MSP430_HAS_EUSCI_A0__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_EUSCI_A0__ 0x05C0
+#define EUSCI_A0_BASE __MSP430_BASEADDRESS_EUSCI_A0__
+
+sfr_w(UCA0CTLW0); /* USCI A0 Control Word Register 0 */
+sfr_b(UCA0CTLW0_L); /* USCI A0 Control Word Register 0 */
+sfr_b(UCA0CTLW0_H); /* USCI A0 Control Word Register 0 */
+#define UCA0CTL1 UCA0CTLW0_L /* USCI A0 Control Register 1 */
+#define UCA0CTL0 UCA0CTLW0_H /* USCI A0 Control Register 0 */
+sfr_w(UCA0CTLW1); /* USCI A0 Control Word Register 1 */
+sfr_b(UCA0CTLW1_L); /* USCI A0 Control Word Register 1 */
+sfr_b(UCA0CTLW1_H); /* USCI A0 Control Word Register 1 */
+sfr_w(UCA0BRW); /* USCI A0 Baud Word Rate 0 */
+sfr_b(UCA0BRW_L); /* USCI A0 Baud Word Rate 0 */
+sfr_b(UCA0BRW_H); /* USCI A0 Baud Word Rate 0 */
+#define UCA0BR0 UCA0BRW_L /* USCI A0 Baud Rate 0 */
+#define UCA0BR1 UCA0BRW_H /* USCI A0 Baud Rate 1 */
+sfr_w(UCA0MCTLW); /* USCI A0 Modulation Control */
+sfr_b(UCA0MCTLW_L); /* USCI A0 Modulation Control */
+sfr_b(UCA0MCTLW_H); /* USCI A0 Modulation Control */
+sfr_b(UCA0STATW); /* USCI A0 Status Register */
+sfr_w(UCA0RXBUF); /* USCI A0 Receive Buffer */
+sfr_b(UCA0RXBUF_L); /* USCI A0 Receive Buffer */
+sfr_b(UCA0RXBUF_H); /* USCI A0 Receive Buffer */
+sfr_w(UCA0TXBUF); /* USCI A0 Transmit Buffer */
+sfr_b(UCA0TXBUF_L); /* USCI A0 Transmit Buffer */
+sfr_b(UCA0TXBUF_H); /* USCI A0 Transmit Buffer */
+sfr_b(UCA0ABCTL); /* USCI A0 LIN Control */
+sfr_w(UCA0IRCTL); /* USCI A0 IrDA Transmit Control */
+sfr_b(UCA0IRCTL_L); /* USCI A0 IrDA Transmit Control */
+sfr_b(UCA0IRCTL_H); /* USCI A0 IrDA Transmit Control */
+#define UCA0IRTCTL UCA0IRCTL_L /* USCI A0 IrDA Transmit Control */
+#define UCA0IRRCTL UCA0IRCTL_H /* USCI A0 IrDA Receive Control */
+sfr_w(UCA0IE); /* USCI A0 Interrupt Enable Register */
+sfr_b(UCA0IE_L); /* USCI A0 Interrupt Enable Register */
+sfr_b(UCA0IE_H); /* USCI A0 Interrupt Enable Register */
+sfr_w(UCA0IFG); /* USCI A0 Interrupt Flags Register */
+sfr_b(UCA0IFG_L); /* USCI A0 Interrupt Flags Register */
+sfr_b(UCA0IFG_H); /* USCI A0 Interrupt Flags Register */
+sfr_w(UCA0IV); /* USCI A0 Interrupt Vector Register */
+
+
+/************************************************************
+* USCI A1
+************************************************************/
+#define __MSP430_HAS_EUSCI_A1__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_EUSCI_A1__ 0x05E0
+#define EUSCI_A1_BASE __MSP430_BASEADDRESS_EUSCI_A1__
+
+sfr_w(UCA1CTLW0); /* USCI A1 Control Word Register 0 */
+sfr_b(UCA1CTLW0_L); /* USCI A1 Control Word Register 0 */
+sfr_b(UCA1CTLW0_H); /* USCI A1 Control Word Register 0 */
+#define UCA1CTL1 UCA1CTLW0_L /* USCI A1 Control Register 1 */
+#define UCA1CTL0 UCA1CTLW0_H /* USCI A1 Control Register 0 */
+sfr_w(UCA1CTLW1); /* USCI A1 Control Word Register 1 */
+sfr_b(UCA1CTLW1_L); /* USCI A1 Control Word Register 1 */
+sfr_b(UCA1CTLW1_H); /* USCI A1 Control Word Register 1 */
+sfr_w(UCA1BRW); /* USCI A1 Baud Word Rate 0 */
+sfr_b(UCA1BRW_L); /* USCI A1 Baud Word Rate 0 */
+sfr_b(UCA1BRW_H); /* USCI A1 Baud Word Rate 0 */
+#define UCA1BR0 UCA1BRW_L /* USCI A1 Baud Rate 0 */
+#define UCA1BR1 UCA1BRW_H /* USCI A1 Baud Rate 1 */
+sfr_w(UCA1MCTLW); /* USCI A1 Modulation Control */
+sfr_b(UCA1MCTLW_L); /* USCI A1 Modulation Control */
+sfr_b(UCA1MCTLW_H); /* USCI A1 Modulation Control */
+sfr_b(UCA1STATW); /* USCI A1 Status Register */
+sfr_w(UCA1RXBUF); /* USCI A1 Receive Buffer */
+sfr_b(UCA1RXBUF_L); /* USCI A1 Receive Buffer */
+sfr_b(UCA1RXBUF_H); /* USCI A1 Receive Buffer */
+sfr_w(UCA1TXBUF); /* USCI A1 Transmit Buffer */
+sfr_b(UCA1TXBUF_L); /* USCI A1 Transmit Buffer */
+sfr_b(UCA1TXBUF_H); /* USCI A1 Transmit Buffer */
+sfr_b(UCA1ABCTL); /* USCI A1 LIN Control */
+sfr_w(UCA1IRCTL); /* USCI A1 IrDA Transmit Control */
+sfr_b(UCA1IRCTL_L); /* USCI A1 IrDA Transmit Control */
+sfr_b(UCA1IRCTL_H); /* USCI A1 IrDA Transmit Control */
+#define UCA1IRTCTL UCA1IRCTL_L /* USCI A1 IrDA Transmit Control */
+#define UCA1IRRCTL UCA1IRCTL_H /* USCI A1 IrDA Receive Control */
+sfr_w(UCA1IE); /* USCI A1 Interrupt Enable Register */
+sfr_b(UCA1IE_L); /* USCI A1 Interrupt Enable Register */
+sfr_b(UCA1IE_H); /* USCI A1 Interrupt Enable Register */
+sfr_w(UCA1IFG); /* USCI A1 Interrupt Flags Register */
+sfr_b(UCA1IFG_L); /* USCI A1 Interrupt Flags Register */
+sfr_b(UCA1IFG_H); /* USCI A1 Interrupt Flags Register */
+sfr_w(UCA1IV); /* USCI A1 Interrupt Vector Register */
+
+
+/************************************************************
+* USCI B0
+************************************************************/
+#define __MSP430_HAS_EUSCI_B0__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_EUSCI_B0__ 0x0640
+#define EUSCI_B0_BASE __MSP430_BASEADDRESS_EUSCI_B0__
+
+
+sfr_w(UCB0CTLW0); /* USCI B0 Control Word Register 0 */
+sfr_b(UCB0CTLW0_L); /* USCI B0 Control Word Register 0 */
+sfr_b(UCB0CTLW0_H); /* USCI B0 Control Word Register 0 */
+#define UCB0CTL1 UCB0CTLW0_L /* USCI B0 Control Register 1 */
+#define UCB0CTL0 UCB0CTLW0_H /* USCI B0 Control Register 0 */
+sfr_w(UCB0CTLW1); /* USCI B0 Control Word Register 1 */
+sfr_b(UCB0CTLW1_L); /* USCI B0 Control Word Register 1 */
+sfr_b(UCB0CTLW1_H); /* USCI B0 Control Word Register 1 */
+sfr_w(UCB0BRW); /* USCI B0 Baud Word Rate 0 */
+sfr_b(UCB0BRW_L); /* USCI B0 Baud Word Rate 0 */
+sfr_b(UCB0BRW_H); /* USCI B0 Baud Word Rate 0 */
+#define UCB0BR0 UCB0BRW_L /* USCI B0 Baud Rate 0 */
+#define UCB0BR1 UCB0BRW_H /* USCI B0 Baud Rate 1 */
+sfr_w(UCB0STATW); /* USCI B0 Status Word Register */
+sfr_b(UCB0STATW_L); /* USCI B0 Status Word Register */
+sfr_b(UCB0STATW_H); /* USCI B0 Status Word Register */
+#define UCB0STAT UCB0STATW_L /* USCI B0 Status Register */
+#define UCB0BCNT UCB0STATW_H /* USCI B0 Byte Counter Register */
+sfr_w(UCB0TBCNT); /* USCI B0 Byte Counter Threshold Register */
+sfr_b(UCB0TBCNT_L); /* USCI B0 Byte Counter Threshold Register */
+sfr_b(UCB0TBCNT_H); /* USCI B0 Byte Counter Threshold Register */
+sfr_w(UCB0RXBUF); /* USCI B0 Receive Buffer */
+sfr_b(UCB0RXBUF_L); /* USCI B0 Receive Buffer */
+sfr_b(UCB0RXBUF_H); /* USCI B0 Receive Buffer */
+sfr_w(UCB0TXBUF); /* USCI B0 Transmit Buffer */
+sfr_b(UCB0TXBUF_L); /* USCI B0 Transmit Buffer */
+sfr_b(UCB0TXBUF_H); /* USCI B0 Transmit Buffer */
+sfr_w(UCB0I2COA0); /* USCI B0 I2C Own Address 0 */
+sfr_b(UCB0I2COA0_L); /* USCI B0 I2C Own Address 0 */
+sfr_b(UCB0I2COA0_H); /* USCI B0 I2C Own Address 0 */
+sfr_w(UCB0I2COA1); /* USCI B0 I2C Own Address 1 */
+sfr_b(UCB0I2COA1_L); /* USCI B0 I2C Own Address 1 */
+sfr_b(UCB0I2COA1_H); /* USCI B0 I2C Own Address 1 */
+sfr_w(UCB0I2COA2); /* USCI B0 I2C Own Address 2 */
+sfr_b(UCB0I2COA2_L); /* USCI B0 I2C Own Address 2 */
+sfr_b(UCB0I2COA2_H); /* USCI B0 I2C Own Address 2 */
+sfr_w(UCB0I2COA3); /* USCI B0 I2C Own Address 3 */
+sfr_b(UCB0I2COA3_L); /* USCI B0 I2C Own Address 3 */
+sfr_b(UCB0I2COA3_H); /* USCI B0 I2C Own Address 3 */
+sfr_w(UCB0ADDRX); /* USCI B0 Received Address Register */
+sfr_b(UCB0ADDRX_L); /* USCI B0 Received Address Register */
+sfr_b(UCB0ADDRX_H); /* USCI B0 Received Address Register */
+sfr_w(UCB0ADDMASK); /* USCI B0 Address Mask Register */
+sfr_b(UCB0ADDMASK_L); /* USCI B0 Address Mask Register */
+sfr_b(UCB0ADDMASK_H); /* USCI B0 Address Mask Register */
+sfr_w(UCB0I2CSA); /* USCI B0 I2C Slave Address */
+sfr_b(UCB0I2CSA_L); /* USCI B0 I2C Slave Address */
+sfr_b(UCB0I2CSA_H); /* USCI B0 I2C Slave Address */
+sfr_w(UCB0IE); /* USCI B0 Interrupt Enable Register */
+sfr_b(UCB0IE_L); /* USCI B0 Interrupt Enable Register */
+sfr_b(UCB0IE_H); /* USCI B0 Interrupt Enable Register */
+sfr_w(UCB0IFG); /* USCI B0 Interrupt Flags Register */
+sfr_b(UCB0IFG_L); /* USCI B0 Interrupt Flags Register */
+sfr_b(UCB0IFG_H); /* USCI B0 Interrupt Flags Register */
+sfr_w(UCB0IV); /* USCI B0 Interrupt Vector Register */
+
+// UCAxCTLW0 UART-Mode Control Bits
+#define UCPEN (0x8000) /* Async. Mode: Parity enable */
+#define UCPAR (0x4000) /* Async. Mode: Parity 0:odd / 1:even */
+#define UCMSB (0x2000) /* Async. Mode: MSB first 0:LSB / 1:MSB */
+#define UC7BIT (0x1000) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */
+#define UCSPB (0x0800) /* Async. Mode: Stop Bits 0:one / 1: two */
+#define UCMODE1 (0x0400) /* Async. Mode: USCI Mode 1 */
+#define UCMODE0 (0x0200) /* Async. Mode: USCI Mode 0 */
+#define UCSYNC (0x0100) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */
+#define UCSSEL1 (0x0080) /* USCI 0 Clock Source Select 1 */
+#define UCSSEL0 (0x0040) /* USCI 0 Clock Source Select 0 */
+#define UCRXEIE (0x0020) /* RX Error interrupt enable */
+#define UCBRKIE (0x0010) /* Break interrupt enable */
+#define UCDORM (0x0008) /* Dormant (Sleep) Mode */
+#define UCTXADDR (0x0004) /* Send next Data as Address */
+#define UCTXBRK (0x0002) /* Send next Data as Break */
+#define UCSWRST (0x0001) /* USCI Software Reset */
+
+// UCAxCTLW0 UART-Mode Control Bits
+#define UCSSEL1_L (0x0080) /* USCI 0 Clock Source Select 1 */
+#define UCSSEL0_L (0x0040) /* USCI 0 Clock Source Select 0 */
+#define UCRXEIE_L (0x0020) /* RX Error interrupt enable */
+#define UCBRKIE_L (0x0010) /* Break interrupt enable */
+#define UCDORM_L (0x0008) /* Dormant (Sleep) Mode */
+#define UCTXADDR_L (0x0004) /* Send next Data as Address */
+#define UCTXBRK_L (0x0002) /* Send next Data as Break */
+#define UCSWRST_L (0x0001) /* USCI Software Reset */
+
+// UCAxCTLW0 UART-Mode Control Bits
+#define UCPEN_H (0x0080) /* Async. Mode: Parity enable */
+#define UCPAR_H (0x0040) /* Async. Mode: Parity 0:odd / 1:even */
+#define UCMSB_H (0x0020) /* Async. Mode: MSB first 0:LSB / 1:MSB */
+#define UC7BIT_H (0x0010) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */
+#define UCSPB_H (0x0008) /* Async. Mode: Stop Bits 0:one / 1: two */
+#define UCMODE1_H (0x0004) /* Async. Mode: USCI Mode 1 */
+#define UCMODE0_H (0x0002) /* Async. Mode: USCI Mode 0 */
+#define UCSYNC_H (0x0001) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */
+
+// UCxxCTLW0 SPI-Mode Control Bits
+#define UCCKPH (0x8000) /* Sync. Mode: Clock Phase */
+#define UCCKPL (0x4000) /* Sync. Mode: Clock Polarity */
+#define UCMST (0x0800) /* Sync. Mode: Master Select */
+//#define res (0x0020) /* reserved */
+//#define res (0x0010) /* reserved */
+//#define res (0x0008) /* reserved */
+//#define res (0x0004) /* reserved */
+#define UCSTEM (0x0002) /* USCI STE Mode */
+
+// UCBxCTLW0 I2C-Mode Control Bits
+#define UCA10 (0x8000) /* 10-bit Address Mode */
+#define UCSLA10 (0x4000) /* 10-bit Slave Address Mode */
+#define UCMM (0x2000) /* Multi-Master Environment */
+//#define res (0x1000) /* reserved */
+//#define res (0x0100) /* reserved */
+#define UCTXACK (0x0020) /* Transmit ACK */
+#define UCTR (0x0010) /* Transmit/Receive Select/Flag */
+#define UCTXNACK (0x0008) /* Transmit NACK */
+#define UCTXSTP (0x0004) /* Transmit STOP */
+#define UCTXSTT (0x0002) /* Transmit START */
+
+// UCBxCTLW0 I2C-Mode Control Bits
+//#define res (0x1000) /* reserved */
+//#define res (0x0100) /* reserved */
+#define UCTXACK_L (0x0020) /* Transmit ACK */
+#define UCTR_L (0x0010) /* Transmit/Receive Select/Flag */
+#define UCTXNACK_L (0x0008) /* Transmit NACK */
+#define UCTXSTP_L (0x0004) /* Transmit STOP */
+#define UCTXSTT_L (0x0002) /* Transmit START */
+
+// UCBxCTLW0 I2C-Mode Control Bits
+#define UCA10_H (0x0080) /* 10-bit Address Mode */
+#define UCSLA10_H (0x0040) /* 10-bit Slave Address Mode */
+#define UCMM_H (0x0020) /* Multi-Master Environment */
+//#define res (0x1000) /* reserved */
+//#define res (0x0100) /* reserved */
+
+#define UCMODE_0 (0x0000) /* Sync. Mode: USCI Mode: 0 */
+#define UCMODE_1 (0x0200) /* Sync. Mode: USCI Mode: 1 */
+#define UCMODE_2 (0x0400) /* Sync. Mode: USCI Mode: 2 */
+#define UCMODE_3 (0x0600) /* Sync. Mode: USCI Mode: 3 */
+
+#define UCSSEL_0 (0x0000) /* USCI 0 Clock Source: 0 */
+#define UCSSEL_1 (0x0040) /* USCI 0 Clock Source: 1 */
+#define UCSSEL_2 (0x0080) /* USCI 0 Clock Source: 2 */
+#define UCSSEL_3 (0x00C0) /* USCI 0 Clock Source: 3 */
+#define UCSSEL__UCLK (0x0000) /* USCI 0 Clock Source: UCLK */
+#define UCSSEL__ACLK (0x0040) /* USCI 0 Clock Source: ACLK */
+#define UCSSEL__SMCLK (0x0080) /* USCI 0 Clock Source: SMCLK */
+
+// UCAxCTLW1 UART-Mode Control Bits
+#define UCGLIT1 (0x0002) /* USCI Deglitch Time Bit 1 */
+#define UCGLIT0 (0x0001) /* USCI Deglitch Time Bit 0 */
+
+// UCAxCTLW1 UART-Mode Control Bits
+#define UCGLIT1_L (0x0002) /* USCI Deglitch Time Bit 1 */
+#define UCGLIT0_L (0x0001) /* USCI Deglitch Time Bit 0 */
+
+// UCBxCTLW1 I2C-Mode Control Bits
+#define UCETXINT (0x0100) /* USCI Early UCTXIFG0 */
+#define UCCLTO1 (0x0080) /* USCI Clock low timeout Bit: 1 */
+#define UCCLTO0 (0x0040) /* USCI Clock low timeout Bit: 0 */
+#define UCSTPNACK (0x0020) /* USCI Acknowledge Stop last byte */
+#define UCSWACK (0x0010) /* USCI Software controlled ACK */
+#define UCASTP1 (0x0008) /* USCI Automatic Stop condition generation Bit: 1 */
+#define UCASTP0 (0x0004) /* USCI Automatic Stop condition generation Bit: 0 */
+#define UCGLIT1 (0x0002) /* USCI Deglitch time Bit: 1 */
+#define UCGLIT0 (0x0001) /* USCI Deglitch time Bit: 0 */
+
+// UCBxCTLW1 I2C-Mode Control Bits
+#define UCCLTO1_L (0x0080) /* USCI Clock low timeout Bit: 1 */
+#define UCCLTO0_L (0x0040) /* USCI Clock low timeout Bit: 0 */
+#define UCSTPNACK_L (0x0020) /* USCI Acknowledge Stop last byte */
+#define UCSWACK_L (0x0010) /* USCI Software controlled ACK */
+#define UCASTP1_L (0x0008) /* USCI Automatic Stop condition generation Bit: 1 */
+#define UCASTP0_L (0x0004) /* USCI Automatic Stop condition generation Bit: 0 */
+#define UCGLIT1_L (0x0002) /* USCI Deglitch time Bit: 1 */
+#define UCGLIT0_L (0x0001) /* USCI Deglitch time Bit: 0 */
+
+// UCBxCTLW1 I2C-Mode Control Bits
+#define UCETXINT_H (0x0001) /* USCI Early UCTXIFG0 */
+
+#define UCGLIT_0 (0x0000) /* USCI Deglitch time: 0 */
+#define UCGLIT_1 (0x0001) /* USCI Deglitch time: 1 */
+#define UCGLIT_2 (0x0002) /* USCI Deglitch time: 2 */
+#define UCGLIT_3 (0x0003) /* USCI Deglitch time: 3 */
+
+#define UCASTP_0 (0x0000) /* USCI Automatic Stop condition generation: 0 */
+#define UCASTP_1 (0x0004) /* USCI Automatic Stop condition generation: 1 */
+#define UCASTP_2 (0x0008) /* USCI Automatic Stop condition generation: 2 */
+#define UCASTP_3 (0x000C) /* USCI Automatic Stop condition generation: 3 */
+
+#define UCCLTO_0 (0x0000) /* USCI Clock low timeout: 0 */
+#define UCCLTO_1 (0x0040) /* USCI Clock low timeout: 1 */
+#define UCCLTO_2 (0x0080) /* USCI Clock low timeout: 2 */
+#define UCCLTO_3 (0x00C0) /* USCI Clock low timeout: 3 */
+
+/* UCAxMCTLW Control Bits */
+#define UCBRS7 (0x8000) /* USCI Second Stage Modulation Select 7 */
+#define UCBRS6 (0x4000) /* USCI Second Stage Modulation Select 6 */
+#define UCBRS5 (0x2000) /* USCI Second Stage Modulation Select 5 */
+#define UCBRS4 (0x1000) /* USCI Second Stage Modulation Select 4 */
+#define UCBRS3 (0x0800) /* USCI Second Stage Modulation Select 3 */
+#define UCBRS2 (0x0400) /* USCI Second Stage Modulation Select 2 */
+#define UCBRS1 (0x0200) /* USCI Second Stage Modulation Select 1 */
+#define UCBRS0 (0x0100) /* USCI Second Stage Modulation Select 0 */
+#define UCBRF3 (0x0080) /* USCI First Stage Modulation Select 3 */
+#define UCBRF2 (0x0040) /* USCI First Stage Modulation Select 2 */
+#define UCBRF1 (0x0020) /* USCI First Stage Modulation Select 1 */
+#define UCBRF0 (0x0010) /* USCI First Stage Modulation Select 0 */
+#define UCOS16 (0x0001) /* USCI 16-times Oversampling enable */
+
+/* UCAxMCTLW Control Bits */
+#define UCBRF3_L (0x0080) /* USCI First Stage Modulation Select 3 */
+#define UCBRF2_L (0x0040) /* USCI First Stage Modulation Select 2 */
+#define UCBRF1_L (0x0020) /* USCI First Stage Modulation Select 1 */
+#define UCBRF0_L (0x0010) /* USCI First Stage Modulation Select 0 */
+#define UCOS16_L (0x0001) /* USCI 16-times Oversampling enable */
+
+/* UCAxMCTLW Control Bits */
+#define UCBRS7_H (0x0080) /* USCI Second Stage Modulation Select 7 */
+#define UCBRS6_H (0x0040) /* USCI Second Stage Modulation Select 6 */
+#define UCBRS5_H (0x0020) /* USCI Second Stage Modulation Select 5 */
+#define UCBRS4_H (0x0010) /* USCI Second Stage Modulation Select 4 */
+#define UCBRS3_H (0x0008) /* USCI Second Stage Modulation Select 3 */
+#define UCBRS2_H (0x0004) /* USCI Second Stage Modulation Select 2 */
+#define UCBRS1_H (0x0002) /* USCI Second Stage Modulation Select 1 */
+#define UCBRS0_H (0x0001) /* USCI Second Stage Modulation Select 0 */
+
+#define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */
+#define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */
+#define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */
+#define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */
+#define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */
+#define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */
+#define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */
+#define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */
+#define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */
+#define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */
+#define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */
+#define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */
+#define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */
+#define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */
+#define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */
+#define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */
+
+/* UCAxSTATW Control Bits */
+#define UCLISTEN (0x0080) /* USCI Listen mode */
+#define UCFE (0x0040) /* USCI Frame Error Flag */
+#define UCOE (0x0020) /* USCI Overrun Error Flag */
+#define UCPE (0x0010) /* USCI Parity Error Flag */
+#define UCBRK (0x0008) /* USCI Break received */
+#define UCRXERR (0x0004) /* USCI RX Error Flag */
+#define UCADDR (0x0002) /* USCI Address received Flag */
+#define UCBUSY (0x0001) /* USCI Busy Flag */
+#define UCIDLE (0x0002) /* USCI Idle line detected Flag */
+
+/* UCBxSTATW I2C Control Bits */
+#define UCBCNT7 (0x8000) /* USCI Byte Counter Bit 7 */
+#define UCBCNT6 (0x4000) /* USCI Byte Counter Bit 6 */
+#define UCBCNT5 (0x2000) /* USCI Byte Counter Bit 5 */
+#define UCBCNT4 (0x1000) /* USCI Byte Counter Bit 4 */
+#define UCBCNT3 (0x0800) /* USCI Byte Counter Bit 3 */
+#define UCBCNT2 (0x0400) /* USCI Byte Counter Bit 2 */
+#define UCBCNT1 (0x0200) /* USCI Byte Counter Bit 1 */
+#define UCBCNT0 (0x0100) /* USCI Byte Counter Bit 0 */
+#define UCSCLLOW (0x0040) /* SCL low */
+#define UCGC (0x0020) /* General Call address received Flag */
+#define UCBBUSY (0x0010) /* Bus Busy Flag */
+
+/* UCBxTBCNT I2C Control Bits */
+#define UCTBCNT7 (0x0080) /* USCI Byte Counter Bit 7 */
+#define UCTBCNT6 (0x0040) /* USCI Byte Counter Bit 6 */
+#define UCTBCNT5 (0x0020) /* USCI Byte Counter Bit 5 */
+#define UCTBCNT4 (0x0010) /* USCI Byte Counter Bit 4 */
+#define UCTBCNT3 (0x0008) /* USCI Byte Counter Bit 3 */
+#define UCTBCNT2 (0x0004) /* USCI Byte Counter Bit 2 */
+#define UCTBCNT1 (0x0002) /* USCI Byte Counter Bit 1 */
+#define UCTBCNT0 (0x0001) /* USCI Byte Counter Bit 0 */
+
+/* UCAxIRCTL Control Bits */
+#define UCIRRXFL5 (0x8000) /* IRDA Receive Filter Length 5 */
+#define UCIRRXFL4 (0x4000) /* IRDA Receive Filter Length 4 */
+#define UCIRRXFL3 (0x2000) /* IRDA Receive Filter Length 3 */
+#define UCIRRXFL2 (0x1000) /* IRDA Receive Filter Length 2 */
+#define UCIRRXFL1 (0x0800) /* IRDA Receive Filter Length 1 */
+#define UCIRRXFL0 (0x0400) /* IRDA Receive Filter Length 0 */
+#define UCIRRXPL (0x0200) /* IRDA Receive Input Polarity */
+#define UCIRRXFE (0x0100) /* IRDA Receive Filter enable */
+#define UCIRTXPL5 (0x0080) /* IRDA Transmit Pulse Length 5 */
+#define UCIRTXPL4 (0x0040) /* IRDA Transmit Pulse Length 4 */
+#define UCIRTXPL3 (0x0020) /* IRDA Transmit Pulse Length 3 */
+#define UCIRTXPL2 (0x0010) /* IRDA Transmit Pulse Length 2 */
+#define UCIRTXPL1 (0x0008) /* IRDA Transmit Pulse Length 1 */
+#define UCIRTXPL0 (0x0004) /* IRDA Transmit Pulse Length 0 */
+#define UCIRTXCLK (0x0002) /* IRDA Transmit Pulse Clock Select */
+#define UCIREN (0x0001) /* IRDA Encoder/Decoder enable */
+
+/* UCAxIRCTL Control Bits */
+#define UCIRTXPL5_L (0x0080) /* IRDA Transmit Pulse Length 5 */
+#define UCIRTXPL4_L (0x0040) /* IRDA Transmit Pulse Length 4 */
+#define UCIRTXPL3_L (0x0020) /* IRDA Transmit Pulse Length 3 */
+#define UCIRTXPL2_L (0x0010) /* IRDA Transmit Pulse Length 2 */
+#define UCIRTXPL1_L (0x0008) /* IRDA Transmit Pulse Length 1 */
+#define UCIRTXPL0_L (0x0004) /* IRDA Transmit Pulse Length 0 */
+#define UCIRTXCLK_L (0x0002) /* IRDA Transmit Pulse Clock Select */
+#define UCIREN_L (0x0001) /* IRDA Encoder/Decoder enable */
+
+/* UCAxIRCTL Control Bits */
+#define UCIRRXFL5_H (0x0080) /* IRDA Receive Filter Length 5 */
+#define UCIRRXFL4_H (0x0040) /* IRDA Receive Filter Length 4 */
+#define UCIRRXFL3_H (0x0020) /* IRDA Receive Filter Length 3 */
+#define UCIRRXFL2_H (0x0010) /* IRDA Receive Filter Length 2 */
+#define UCIRRXFL1_H (0x0008) /* IRDA Receive Filter Length 1 */
+#define UCIRRXFL0_H (0x0004) /* IRDA Receive Filter Length 0 */
+#define UCIRRXPL_H (0x0002) /* IRDA Receive Input Polarity */
+#define UCIRRXFE_H (0x0001) /* IRDA Receive Filter enable */
+
+/* UCAxABCTL Control Bits */
+//#define res (0x80) /* reserved */
+//#define res (0x40) /* reserved */
+#define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */
+#define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */
+#define UCSTOE (0x08) /* Sync-Field Timeout error */
+#define UCBTOE (0x04) /* Break Timeout error */
+//#define res (0x02) /* reserved */
+#define UCABDEN (0x01) /* Auto Baud Rate detect enable */
+
+/* UCBxI2COA0 Control Bits */
+#define UCGCEN (0x8000) /* I2C General Call enable */
+#define UCOAEN (0x0400) /* I2C Own Address enable */
+#define UCOA9 (0x0200) /* I2C Own Address Bit 9 */
+#define UCOA8 (0x0100) /* I2C Own Address Bit 8 */
+#define UCOA7 (0x0080) /* I2C Own Address Bit 7 */
+#define UCOA6 (0x0040) /* I2C Own Address Bit 6 */
+#define UCOA5 (0x0020) /* I2C Own Address Bit 5 */
+#define UCOA4 (0x0010) /* I2C Own Address Bit 4 */
+#define UCOA3 (0x0008) /* I2C Own Address Bit 3 */
+#define UCOA2 (0x0004) /* I2C Own Address Bit 2 */
+#define UCOA1 (0x0002) /* I2C Own Address Bit 1 */
+#define UCOA0 (0x0001) /* I2C Own Address Bit 0 */
+
+/* UCBxI2COA0 Control Bits */
+#define UCOA7_L (0x0080) /* I2C Own Address Bit 7 */
+#define UCOA6_L (0x0040) /* I2C Own Address Bit 6 */
+#define UCOA5_L (0x0020) /* I2C Own Address Bit 5 */
+#define UCOA4_L (0x0010) /* I2C Own Address Bit 4 */
+#define UCOA3_L (0x0008) /* I2C Own Address Bit 3 */
+#define UCOA2_L (0x0004) /* I2C Own Address Bit 2 */
+#define UCOA1_L (0x0002) /* I2C Own Address Bit 1 */
+#define UCOA0_L (0x0001) /* I2C Own Address Bit 0 */
+
+/* UCBxI2COA0 Control Bits */
+#define UCGCEN_H (0x0080) /* I2C General Call enable */
+#define UCOAEN_H (0x0004) /* I2C Own Address enable */
+#define UCOA9_H (0x0002) /* I2C Own Address Bit 9 */
+#define UCOA8_H (0x0001) /* I2C Own Address Bit 8 */
+
+/* UCBxI2COAx Control Bits */
+#define UCOAEN (0x0400) /* I2C Own Address enable */
+#define UCOA9 (0x0200) /* I2C Own Address Bit 9 */
+#define UCOA8 (0x0100) /* I2C Own Address Bit 8 */
+#define UCOA7 (0x0080) /* I2C Own Address Bit 7 */
+#define UCOA6 (0x0040) /* I2C Own Address Bit 6 */
+#define UCOA5 (0x0020) /* I2C Own Address Bit 5 */
+#define UCOA4 (0x0010) /* I2C Own Address Bit 4 */
+#define UCOA3 (0x0008) /* I2C Own Address Bit 3 */
+#define UCOA2 (0x0004) /* I2C Own Address Bit 2 */
+#define UCOA1 (0x0002) /* I2C Own Address Bit 1 */
+#define UCOA0 (0x0001) /* I2C Own Address Bit 0 */
+
+/* UCBxI2COAx Control Bits */
+#define UCOA7_L (0x0080) /* I2C Own Address Bit 7 */
+#define UCOA6_L (0x0040) /* I2C Own Address Bit 6 */
+#define UCOA5_L (0x0020) /* I2C Own Address Bit 5 */
+#define UCOA4_L (0x0010) /* I2C Own Address Bit 4 */
+#define UCOA3_L (0x0008) /* I2C Own Address Bit 3 */
+#define UCOA2_L (0x0004) /* I2C Own Address Bit 2 */
+#define UCOA1_L (0x0002) /* I2C Own Address Bit 1 */
+#define UCOA0_L (0x0001) /* I2C Own Address Bit 0 */
+
+/* UCBxI2COAx Control Bits */
+#define UCOAEN_H (0x0004) /* I2C Own Address enable */
+#define UCOA9_H (0x0002) /* I2C Own Address Bit 9 */
+#define UCOA8_H (0x0001) /* I2C Own Address Bit 8 */
+
+/* UCBxADDRX Control Bits */
+#define UCADDRX9 (0x0200) /* I2C Receive Address Bit 9 */
+#define UCADDRX8 (0x0100) /* I2C Receive Address Bit 8 */
+#define UCADDRX7 (0x0080) /* I2C Receive Address Bit 7 */
+#define UCADDRX6 (0x0040) /* I2C Receive Address Bit 6 */
+#define UCADDRX5 (0x0020) /* I2C Receive Address Bit 5 */
+#define UCADDRX4 (0x0010) /* I2C Receive Address Bit 4 */
+#define UCADDRX3 (0x0008) /* I2C Receive Address Bit 3 */
+#define UCADDRX2 (0x0004) /* I2C Receive Address Bit 2 */
+#define UCADDRX1 (0x0002) /* I2C Receive Address Bit 1 */
+#define UCADDRX0 (0x0001) /* I2C Receive Address Bit 0 */
+
+/* UCBxADDRX Control Bits */
+#define UCADDRX7_L (0x0080) /* I2C Receive Address Bit 7 */
+#define UCADDRX6_L (0x0040) /* I2C Receive Address Bit 6 */
+#define UCADDRX5_L (0x0020) /* I2C Receive Address Bit 5 */
+#define UCADDRX4_L (0x0010) /* I2C Receive Address Bit 4 */
+#define UCADDRX3_L (0x0008) /* I2C Receive Address Bit 3 */
+#define UCADDRX2_L (0x0004) /* I2C Receive Address Bit 2 */
+#define UCADDRX1_L (0x0002) /* I2C Receive Address Bit 1 */
+#define UCADDRX0_L (0x0001) /* I2C Receive Address Bit 0 */
+
+/* UCBxADDRX Control Bits */
+#define UCADDRX9_H (0x0002) /* I2C Receive Address Bit 9 */
+#define UCADDRX8_H (0x0001) /* I2C Receive Address Bit 8 */
+
+/* UCBxADDMASK Control Bits */
+#define UCADDMASK9 (0x0200) /* I2C Address Mask Bit 9 */
+#define UCADDMASK8 (0x0100) /* I2C Address Mask Bit 8 */
+#define UCADDMASK7 (0x0080) /* I2C Address Mask Bit 7 */
+#define UCADDMASK6 (0x0040) /* I2C Address Mask Bit 6 */
+#define UCADDMASK5 (0x0020) /* I2C Address Mask Bit 5 */
+#define UCADDMASK4 (0x0010) /* I2C Address Mask Bit 4 */
+#define UCADDMASK3 (0x0008) /* I2C Address Mask Bit 3 */
+#define UCADDMASK2 (0x0004) /* I2C Address Mask Bit 2 */
+#define UCADDMASK1 (0x0002) /* I2C Address Mask Bit 1 */
+#define UCADDMASK0 (0x0001) /* I2C Address Mask Bit 0 */
+
+/* UCBxADDMASK Control Bits */
+#define UCADDMASK7_L (0x0080) /* I2C Address Mask Bit 7 */
+#define UCADDMASK6_L (0x0040) /* I2C Address Mask Bit 6 */
+#define UCADDMASK5_L (0x0020) /* I2C Address Mask Bit 5 */
+#define UCADDMASK4_L (0x0010) /* I2C Address Mask Bit 4 */
+#define UCADDMASK3_L (0x0008) /* I2C Address Mask Bit 3 */
+#define UCADDMASK2_L (0x0004) /* I2C Address Mask Bit 2 */
+#define UCADDMASK1_L (0x0002) /* I2C Address Mask Bit 1 */
+#define UCADDMASK0_L (0x0001) /* I2C Address Mask Bit 0 */
+
+/* UCBxADDMASK Control Bits */
+#define UCADDMASK9_H (0x0002) /* I2C Address Mask Bit 9 */
+#define UCADDMASK8_H (0x0001) /* I2C Address Mask Bit 8 */
+
+/* UCBxI2CSA Control Bits */
+#define UCSA9 (0x0200) /* I2C Slave Address Bit 9 */
+#define UCSA8 (0x0100) /* I2C Slave Address Bit 8 */
+#define UCSA7 (0x0080) /* I2C Slave Address Bit 7 */
+#define UCSA6 (0x0040) /* I2C Slave Address Bit 6 */
+#define UCSA5 (0x0020) /* I2C Slave Address Bit 5 */
+#define UCSA4 (0x0010) /* I2C Slave Address Bit 4 */
+#define UCSA3 (0x0008) /* I2C Slave Address Bit 3 */
+#define UCSA2 (0x0004) /* I2C Slave Address Bit 2 */
+#define UCSA1 (0x0002) /* I2C Slave Address Bit 1 */
+#define UCSA0 (0x0001) /* I2C Slave Address Bit 0 */
+
+/* UCBxI2CSA Control Bits */
+#define UCSA7_L (0x0080) /* I2C Slave Address Bit 7 */
+#define UCSA6_L (0x0040) /* I2C Slave Address Bit 6 */
+#define UCSA5_L (0x0020) /* I2C Slave Address Bit 5 */
+#define UCSA4_L (0x0010) /* I2C Slave Address Bit 4 */
+#define UCSA3_L (0x0008) /* I2C Slave Address Bit 3 */
+#define UCSA2_L (0x0004) /* I2C Slave Address Bit 2 */
+#define UCSA1_L (0x0002) /* I2C Slave Address Bit 1 */
+#define UCSA0_L (0x0001) /* I2C Slave Address Bit 0 */
+
+/* UCBxI2CSA Control Bits */
+#define UCSA9_H (0x0002) /* I2C Slave Address Bit 9 */
+#define UCSA8_H (0x0001) /* I2C Slave Address Bit 8 */
+
+/* UCAxIE UART Control Bits */
+#define UCTXCPTIE (0x0008) /* UART Transmit Complete Interrupt Enable */
+#define UCSTTIE (0x0004) /* UART Start Bit Interrupt Enalble */
+#define UCTXIE (0x0002) /* UART Transmit Interrupt Enable */
+#define UCRXIE (0x0001) /* UART Receive Interrupt Enable */
+
+/* UCAxIE/UCBxIE SPI Control Bits */
+
+/* UCBxIE I2C Control Bits */
+#define UCBIT9IE (0x4000) /* I2C Bit 9 Position Interrupt Enable 3 */
+#define UCTXIE3 (0x2000) /* I2C Transmit Interrupt Enable 3 */
+#define UCRXIE3 (0x1000) /* I2C Receive Interrupt Enable 3 */
+#define UCTXIE2 (0x0800) /* I2C Transmit Interrupt Enable 2 */
+#define UCRXIE2 (0x0400) /* I2C Receive Interrupt Enable 2 */
+#define UCTXIE1 (0x0200) /* I2C Transmit Interrupt Enable 1 */
+#define UCRXIE1 (0x0100) /* I2C Receive Interrupt Enable 1 */
+#define UCCLTOIE (0x0080) /* I2C Clock Low Timeout interrupt enable */
+#define UCBCNTIE (0x0040) /* I2C Automatic stop assertion interrupt enable */
+#define UCNACKIE (0x0020) /* I2C NACK Condition interrupt enable */
+#define UCALIE (0x0010) /* I2C Arbitration Lost interrupt enable */
+#define UCSTPIE (0x0008) /* I2C STOP Condition interrupt enable */
+#define UCSTTIE (0x0004) /* I2C START Condition interrupt enable */
+#define UCTXIE0 (0x0002) /* I2C Transmit Interrupt Enable 0 */
+#define UCRXIE0 (0x0001) /* I2C Receive Interrupt Enable 0 */
+
+/* UCAxIFG UART Control Bits */
+#define UCTXCPTIFG (0x0008) /* UART Transmit Complete Interrupt Flag */
+#define UCSTTIFG (0x0004) /* UART Start Bit Interrupt Flag */
+#define UCTXIFG (0x0002) /* UART Transmit Interrupt Flag */
+#define UCRXIFG (0x0001) /* UART Receive Interrupt Flag */
+
+/* UCAxIFG/UCBxIFG SPI Control Bits */
+#define UCTXIFG (0x0002) /* SPI Transmit Interrupt Flag */
+#define UCRXIFG (0x0001) /* SPI Receive Interrupt Flag */
+
+/* UCBxIFG Control Bits */
+#define UCBIT9IFG (0x4000) /* I2C Bit 9 Possition Interrupt Flag 3 */
+#define UCTXIFG3 (0x2000) /* I2C Transmit Interrupt Flag 3 */
+#define UCRXIFG3 (0x1000) /* I2C Receive Interrupt Flag 3 */
+#define UCTXIFG2 (0x0800) /* I2C Transmit Interrupt Flag 2 */
+#define UCRXIFG2 (0x0400) /* I2C Receive Interrupt Flag 2 */
+#define UCTXIFG1 (0x0200) /* I2C Transmit Interrupt Flag 1 */
+#define UCRXIFG1 (0x0100) /* I2C Receive Interrupt Flag 1 */
+#define UCCLTOIFG (0x0080) /* I2C Clock low Timeout interrupt Flag */
+#define UCBCNTIFG (0x0040) /* I2C Byte counter interrupt flag */
+#define UCNACKIFG (0x0020) /* I2C NACK Condition interrupt Flag */
+#define UCALIFG (0x0010) /* I2C Arbitration Lost interrupt Flag */
+#define UCSTPIFG (0x0008) /* I2C STOP Condition interrupt Flag */
+#define UCSTTIFG (0x0004) /* I2C START Condition interrupt Flag */
+#define UCTXIFG0 (0x0002) /* I2C Transmit Interrupt Flag 0 */
+#define UCRXIFG0 (0x0001) /* I2C Receive Interrupt Flag 0 */
+
+/* USCI Interrupt Vector UART Definitions */
+#define USCI_NONE (0x0000) /* No Interrupt pending */
+#define USCI_UART_UCRXIFG (0x0002) /* Interrupt Vector: UCRXIFG */
+#define USCI_UART_UCTXIFG (0x0004) /* Interrupt Vector: UCTXIFG */
+#define USCI_UART_UCSTTIFG (0x0006) /* Interrupt Vector: UCSTTIFG */
+#define USCI_UART_UCTXCPTIFG (0x0008) /* Interrupt Vector: UCTXCPTIFG */
+
+/* USCI Interrupt Vector SPI Definitions */
+#define USCI_SPI_UCRXIFG (0x0002) /* Interrupt Vector: UCRXIFG */
+#define USCI_SPI_UCTXIFG (0x0004) /* Interrupt Vector: UCTXIFG */
+
+/* USCI Interrupt Vector I2C Definitions */
+#define USCI_I2C_UCALIFG (0x0002) /* Interrupt Vector: I2C Mode: UCALIFG */
+#define USCI_I2C_UCNACKIFG (0x0004) /* Interrupt Vector: I2C Mode: UCNACKIFG */
+#define USCI_I2C_UCSTTIFG (0x0006) /* Interrupt Vector: I2C Mode: UCSTTIFG*/
+#define USCI_I2C_UCSTPIFG (0x0008) /* Interrupt Vector: I2C Mode: UCSTPIFG*/
+#define USCI_I2C_UCRXIFG3 (0x000A) /* Interrupt Vector: I2C Mode: UCRXIFG3 */
+#define USCI_I2C_UCTXIFG3 (0x000C) /* Interrupt Vector: I2C Mode: UCTXIFG3 */
+#define USCI_I2C_UCRXIFG2 (0x000E) /* Interrupt Vector: I2C Mode: UCRXIFG2 */
+#define USCI_I2C_UCTXIFG2 (0x0010) /* Interrupt Vector: I2C Mode: UCTXIFG2 */
+#define USCI_I2C_UCRXIFG1 (0x0012) /* Interrupt Vector: I2C Mode: UCRXIFG1 */
+#define USCI_I2C_UCTXIFG1 (0x0014) /* Interrupt Vector: I2C Mode: UCTXIFG1 */
+#define USCI_I2C_UCRXIFG0 (0x0016) /* Interrupt Vector: I2C Mode: UCRXIFG0 */
+#define USCI_I2C_UCTXIFG0 (0x0018) /* Interrupt Vector: I2C Mode: UCTXIFG0 */
+#define USCI_I2C_UCBCNTIFG (0x001A) /* Interrupt Vector: I2C Mode: UCBCNTIFG */
+#define USCI_I2C_UCCLTOIFG (0x001C) /* Interrupt Vector: I2C Mode: UCCLTOIFG */
+#define USCI_I2C_UCBIT9IFG (0x001E) /* Interrupt Vector: I2C Mode: UCBIT9IFG */
+
+/************************************************************
+* WATCHDOG TIMER A
+************************************************************/
+#define __MSP430_HAS_WDT_A__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_WDT_A__ 0x0150
+#define WDT_A_BASE __MSP430_BASEADDRESS_WDT_A__
+
+sfr_w(WDTCTL); /* Watchdog Timer Control */
+sfr_b(WDTCTL_L); /* Watchdog Timer Control */
+sfr_b(WDTCTL_H); /* Watchdog Timer Control */
+/* The bit names have been prefixed with "WDT" */
+/* WDTCTL Control Bits */
+#define WDTIS0 (0x0001) /* WDT - Timer Interval Select 0 */
+#define WDTIS1 (0x0002) /* WDT - Timer Interval Select 1 */
+#define WDTIS2 (0x0004) /* WDT - Timer Interval Select 2 */
+#define WDTCNTCL (0x0008) /* WDT - Timer Clear */
+#define WDTTMSEL (0x0010) /* WDT - Timer Mode Select */
+#define WDTSSEL0 (0x0020) /* WDT - Timer Clock Source Select 0 */
+#define WDTSSEL1 (0x0040) /* WDT - Timer Clock Source Select 1 */
+#define WDTHOLD (0x0080) /* WDT - Timer hold */
+
+/* WDTCTL Control Bits */
+#define WDTIS0_L (0x0001) /* WDT - Timer Interval Select 0 */
+#define WDTIS1_L (0x0002) /* WDT - Timer Interval Select 1 */
+#define WDTIS2_L (0x0004) /* WDT - Timer Interval Select 2 */
+#define WDTCNTCL_L (0x0008) /* WDT - Timer Clear */
+#define WDTTMSEL_L (0x0010) /* WDT - Timer Mode Select */
+#define WDTSSEL0_L (0x0020) /* WDT - Timer Clock Source Select 0 */
+#define WDTSSEL1_L (0x0040) /* WDT - Timer Clock Source Select 1 */
+#define WDTHOLD_L (0x0080) /* WDT - Timer hold */
+
+#define WDTPW (0x5A00)
+
+#define WDTIS_0 (0x0000) /* WDT - Timer Interval Select: /2G */
+#define WDTIS_1 (0x0001) /* WDT - Timer Interval Select: /128M */
+#define WDTIS_2 (0x0002) /* WDT - Timer Interval Select: /8192k */
+#define WDTIS_3 (0x0003) /* WDT - Timer Interval Select: /512k */
+#define WDTIS_4 (0x0004) /* WDT - Timer Interval Select: /32k */
+#define WDTIS_5 (0x0005) /* WDT - Timer Interval Select: /8192 */
+#define WDTIS_6 (0x0006) /* WDT - Timer Interval Select: /512 */
+#define WDTIS_7 (0x0007) /* WDT - Timer Interval Select: /64 */
+#define WDTIS__2G (0x0000) /* WDT - Timer Interval Select: /2G */
+#define WDTIS__128M (0x0001) /* WDT - Timer Interval Select: /128M */
+#define WDTIS__8192K (0x0002) /* WDT - Timer Interval Select: /8192k */
+#define WDTIS__512K (0x0003) /* WDT - Timer Interval Select: /512k */
+#define WDTIS__32K (0x0004) /* WDT - Timer Interval Select: /32k */
+#define WDTIS__8192 (0x0005) /* WDT - Timer Interval Select: /8192 */
+#define WDTIS__512 (0x0006) /* WDT - Timer Interval Select: /512 */
+#define WDTIS__64 (0x0007) /* WDT - Timer Interval Select: /64 */
+
+#define WDTSSEL_0 (0x0000) /* WDT - Timer Clock Source Select: SMCLK */
+#define WDTSSEL_1 (0x0020) /* WDT - Timer Clock Source Select: ACLK */
+#define WDTSSEL_2 (0x0040) /* WDT - Timer Clock Source Select: VLO_CLK */
+#define WDTSSEL_3 (0x0060) /* WDT - Timer Clock Source Select: reserved */
+#define WDTSSEL__SMCLK (0x0000) /* WDT - Timer Clock Source Select: SMCLK */
+#define WDTSSEL__ACLK (0x0020) /* WDT - Timer Clock Source Select: ACLK */
+#define WDTSSEL__VLO (0x0040) /* WDT - Timer Clock Source Select: VLO_CLK */
+
+/* WDT-interval times [1ms] coded with Bits 0-2 */
+/* WDT is clocked by fSMCLK (assumed 1MHz) */
+#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2) /* 32ms interval (default) */
+#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */
+#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */
+#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */
+/* WDT is clocked by fACLK (assumed 32KHz) */
+#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0) /* 1000ms " */
+#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS0) /* 250ms " */
+#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1) /* 16ms " */
+#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1+WDTIS0) /* 1.9ms " */
+/* Watchdog mode -> reset after expired time */
+/* WDT is clocked by fSMCLK (assumed 1MHz) */
+#define WDT_MRST_32 (WDTPW+WDTCNTCL+WDTIS2) /* 32ms interval (default) */
+#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */
+#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */
+#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */
+/* WDT is clocked by fACLK (assumed 32KHz) */
+#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2) /* 1000ms " */
+#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS0) /* 250ms " */
+#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1) /* 16ms " */
+#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1+WDTIS0) /* 1.9ms " */
+
+
+/************************************************************
+* TLV Descriptors
+************************************************************/
+#define __MSP430_HAS_TLV__ /* Definition to show that Module is available */
+#define TLV_BASE __MSP430_BASEADDRESS_TLV__
+
+#define TLV_CRC_LENGTH (0x1A01) /* CRC length of the TLV structure */
+#define TLV_CRC_VALUE (0x1A02) /* CRC value of the TLV structure */
+#define TLV_START (0x1A08) /* Start Address of the TLV structure */
+#define TLV_END (0x1AFF) /* End Address of the TLV structure */
+
+#define TLV_LDTAG (0x01) /* Legacy descriptor (1xx, 2xx, 4xx families) */
+#define TLV_PDTAG (0x02) /* Peripheral discovery descriptor */
+#define TLV_Reserved3 (0x03) /* Future usage */
+#define TLV_Reserved4 (0x04) /* Future usage */
+#define TLV_BLANK (0x05) /* Blank descriptor */
+#define TLV_Reserved6 (0x06) /* Future usage */
+#define TLV_Reserved7 (0x07) /* Serial Number */
+#define TLV_DIERECORD (0x08) /* Die Record */
+#define TLV_ADCCAL (0x11) /* ADC12 calibration */
+#define TLV_ADC12CAL (0x11) /* ADC12 calibration */
+#define TLV_ADC10CAL (0x13) /* ADC10 calibration */
+#define TLV_REFCAL (0x12) /* REF calibration */
+#define TLV_TAGEXT (0xFE) /* Tag extender */
+#define TLV_TAGEND (0xFF) // Tag End of Table
+
+/************************************************************
+* Interrupt Vectors (offset from 0xFF80 + 0x10 for Password)
+************************************************************/
+
+
+#define AES256_VECTOR (31) /* 0xFFCC AES256 */
+#define RTC_VECTOR (32) /* 0xFFCE RTC */
+#define PORT4_VECTOR (33) /* 0xFFD0 Port 4 */
+#define PORT3_VECTOR (34) /* 0xFFD2 Port 3 */
+#define TIMER3_A1_VECTOR (35) /* 0xFFD4 Timer3_A2 CC1, TA */
+#define TIMER3_A0_VECTOR (36) /* 0xFFD6 Timer3_A2 CC0 */
+#define PORT2_VECTOR (37) /* 0xFFD8 Port 2 */
+#define TIMER2_A1_VECTOR (38) /* 0xFFDA Timer2_A2 CC1, TA */
+#define TIMER2_A0_VECTOR (39) /* 0xFFDC Timer2_A2 CC0 */
+#define PORT1_VECTOR (40) /* 0xFFDE Port 1 */
+#define TIMER1_A1_VECTOR (41) /* 0xFFE0 Timer1_A3 CC1-2, TA */
+#define TIMER1_A0_VECTOR (42) /* 0xFFE2 Timer1_A3 CC0 */
+#define DMA_VECTOR (43) /* 0xFFE4 DMA */
+#define USCI_A1_VECTOR (44) /* 0xFFE6 USCI A1 Receive/Transmit */
+#define TIMER0_A1_VECTOR (45) /* 0xFFE8 Timer0_A3 CC1-2, TA */
+#define TIMER0_A0_VECTOR (46) /* 0xFFEA Timer0_A3 CC0 */
+#define ADC12_VECTOR (47) /* 0xFFEC ADC */
+#define USCI_B0_VECTOR (48) /* 0xFFEE USCI B0 Receive/Transmit */
+#define USCI_A0_VECTOR (49) /* 0xFFF0 USCI A0 Receive/Transmit */
+#define WDT_VECTOR (50) /* 0xFFF2 Watchdog Timer */
+#define TIMER0_B1_VECTOR (51) /* 0xFFF4 Timer0_B7 CC1-6, TB */
+#define TIMER0_B0_VECTOR (52) /* 0xFFF6 Timer0_B7 CC0 */
+#define COMP_E_VECTOR (53) /* 0xFFF8 Comparator E */
+#define UNMI_VECTOR (54) /* 0xFFFA User Non-maskable */
+#define SYSNMI_VECTOR (55) /* 0xFFFC System Non-maskable */
+#define RESET_VECTOR ("reset") /* 0xFFFE Reset [Highest Priority] */
+
+/************************************************************
+* End of Modules
+************************************************************/
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif /* #ifndef __MSP430FR5969 */
+
diff --git a/os/common/ext/MSP430/inc/msp430fr6989.h b/os/common/ext/MSP430/inc/msp430fr6989.h
new file mode 100644
index 0000000..1b25e9d
--- /dev/null
+++ b/os/common/ext/MSP430/inc/msp430fr6989.h
@@ -0,0 +1,6315 @@
+/* ============================================================================ */
+/* Copyright (c) 2016, Texas Instruments Incorporated */
+/* All rights reserved. */
+/* */
+/* Redistribution and use in source and binary forms, with or without */
+/* modification, are permitted provided that the following conditions */
+/* are met: */
+/* */
+/* * Redistributions of source code must retain the above copyright */
+/* notice, this list of conditions and the following disclaimer. */
+/* */
+/* * Redistributions in binary form must reproduce the above copyright */
+/* notice, this list of conditions and the following disclaimer in the */
+/* documentation and/or other materials provided with the distribution. */
+/* */
+/* * Neither the name of Texas Instruments Incorporated nor the names of */
+/* its contributors may be used to endorse or promote products derived */
+/* from this software without specific prior written permission. */
+/* */
+/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" */
+/* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, */
+/* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR */
+/* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR */
+/* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, */
+/* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, */
+/* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; */
+/* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, */
+/* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR */
+/* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, */
+/* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */
+/* ============================================================================ */
+
+/********************************************************************
+*
+* Standard register and bit definitions for the Texas Instruments
+* MSP430 microcontroller.
+*
+* This file supports assembler and C development for
+* MSP430FR6989 devices.
+*
+* Texas Instruments, Version 1.1
+*
+* Rev. 1.0, Setup
+* Rev. 1.1, ESI: Renamed bit ESIVCC2 to ESIVMIDEN, renamed bit ESIVSS to ESISHTSM
+*
+*
+********************************************************************/
+
+#ifndef __MSP430FR6989
+#define __MSP430FR6989
+
+#define __MSP430_HAS_MSP430XV2_CPU__ /* Definition to show that it has MSP430XV2 CPU */
+#define __MSP430FR5XX_6XX_FAMILY__
+
+#define __MSP430_HEADER_VERSION__ 1198
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/*----------------------------------------------------------------------------*/
+/* PERIPHERAL FILE MAP */
+/*----------------------------------------------------------------------------*/
+
+#define __MSP430_TI_HEADERS__
+
+#include <iomacros.h>
+
+
+/************************************************************
+* STANDARD BITS
+************************************************************/
+
+#define BIT0 (0x0001)
+#define BIT1 (0x0002)
+#define BIT2 (0x0004)
+#define BIT3 (0x0008)
+#define BIT4 (0x0010)
+#define BIT5 (0x0020)
+#define BIT6 (0x0040)
+#define BIT7 (0x0080)
+#define BIT8 (0x0100)
+#define BIT9 (0x0200)
+#define BITA (0x0400)
+#define BITB (0x0800)
+#define BITC (0x1000)
+#define BITD (0x2000)
+#define BITE (0x4000)
+#define BITF (0x8000)
+
+/************************************************************
+* STATUS REGISTER BITS
+************************************************************/
+
+#define C (0x0001)
+#define Z (0x0002)
+#define N (0x0004)
+#define V (0x0100)
+#define GIE (0x0008)
+#define CPUOFF (0x0010)
+#define OSCOFF (0x0020)
+#define SCG0 (0x0040)
+#define SCG1 (0x0080)
+
+/* Low Power Modes coded with Bits 4-7 in SR */
+
+#ifndef __STDC__ /* Begin #defines for assembler */
+#define LPM0 (CPUOFF)
+#define LPM1 (SCG0+CPUOFF)
+#define LPM2 (SCG1+CPUOFF)
+#define LPM3 (SCG1+SCG0+CPUOFF)
+#define LPM4 (SCG1+SCG0+OSCOFF+CPUOFF)
+/* End #defines for assembler */
+
+#else /* Begin #defines for C */
+#define LPM0_bits (CPUOFF)
+#define LPM1_bits (SCG0+CPUOFF)
+#define LPM2_bits (SCG1+CPUOFF)
+#define LPM3_bits (SCG1+SCG0+CPUOFF)
+#define LPM4_bits (SCG1+SCG0+OSCOFF+CPUOFF)
+
+#include "in430.h"
+
+#define LPM0 __bis_SR_register(LPM0_bits) /* Enter Low Power Mode 0 */
+#define LPM0_EXIT __bic_SR_register_on_exit(LPM0_bits) /* Exit Low Power Mode 0 */
+#define LPM1 __bis_SR_register(LPM1_bits) /* Enter Low Power Mode 1 */
+#define LPM1_EXIT __bic_SR_register_on_exit(LPM1_bits) /* Exit Low Power Mode 1 */
+#define LPM2 __bis_SR_register(LPM2_bits) /* Enter Low Power Mode 2 */
+#define LPM2_EXIT __bic_SR_register_on_exit(LPM2_bits) /* Exit Low Power Mode 2 */
+#define LPM3 __bis_SR_register(LPM3_bits) /* Enter Low Power Mode 3 */
+#define LPM3_EXIT __bic_SR_register_on_exit(LPM3_bits) /* Exit Low Power Mode 3 */
+#define LPM4 __bis_SR_register(LPM4_bits) /* Enter Low Power Mode 4 */
+#define LPM4_EXIT __bic_SR_register_on_exit(LPM4_bits) /* Exit Low Power Mode 4 */
+#endif /* End #defines for C */
+
+/************************************************************
+* PERIPHERAL FILE MAP
+************************************************************/
+
+/************************************************************
+* ADC12_B
+************************************************************/
+#define __MSP430_HAS_ADC12_B__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_ADC12_B__ 0x0800
+#define ADC12_B_BASE __MSP430_BASEADDRESS_ADC12_B__
+
+sfr_w(ADC12CTL0); /* ADC12 B Control 0 */
+sfr_b(ADC12CTL0_L); /* ADC12 B Control 0 */
+sfr_b(ADC12CTL0_H); /* ADC12 B Control 0 */
+sfr_w(ADC12CTL1); /* ADC12 B Control 1 */
+sfr_b(ADC12CTL1_L); /* ADC12 B Control 1 */
+sfr_b(ADC12CTL1_H); /* ADC12 B Control 1 */
+sfr_w(ADC12CTL2); /* ADC12 B Control 2 */
+sfr_b(ADC12CTL2_L); /* ADC12 B Control 2 */
+sfr_b(ADC12CTL2_H); /* ADC12 B Control 2 */
+sfr_w(ADC12CTL3); /* ADC12 B Control 3 */
+sfr_b(ADC12CTL3_L); /* ADC12 B Control 3 */
+sfr_b(ADC12CTL3_H); /* ADC12 B Control 3 */
+sfr_w(ADC12LO); /* ADC12 B Window Comparator High Threshold */
+sfr_b(ADC12LO_L); /* ADC12 B Window Comparator High Threshold */
+sfr_b(ADC12LO_H); /* ADC12 B Window Comparator High Threshold */
+sfr_w(ADC12HI); /* ADC12 B Window Comparator High Threshold */
+sfr_b(ADC12HI_L); /* ADC12 B Window Comparator High Threshold */
+sfr_b(ADC12HI_H); /* ADC12 B Window Comparator High Threshold */
+sfr_w(ADC12IFGR0); /* ADC12 B Interrupt Flag 0 */
+sfr_b(ADC12IFGR0_L); /* ADC12 B Interrupt Flag 0 */
+sfr_b(ADC12IFGR0_H); /* ADC12 B Interrupt Flag 0 */
+sfr_w(ADC12IFGR1); /* ADC12 B Interrupt Flag 1 */
+sfr_b(ADC12IFGR1_L); /* ADC12 B Interrupt Flag 1 */
+sfr_b(ADC12IFGR1_H); /* ADC12 B Interrupt Flag 1 */
+sfr_w(ADC12IFGR2); /* ADC12 B Interrupt Flag 2 */
+sfr_b(ADC12IFGR2_L); /* ADC12 B Interrupt Flag 2 */
+sfr_b(ADC12IFGR2_H); /* ADC12 B Interrupt Flag 2 */
+sfr_w(ADC12IER0); /* ADC12 B Interrupt Enable 0 */
+sfr_b(ADC12IER0_L); /* ADC12 B Interrupt Enable 0 */
+sfr_b(ADC12IER0_H); /* ADC12 B Interrupt Enable 0 */
+sfr_w(ADC12IER1); /* ADC12 B Interrupt Enable 1 */
+sfr_b(ADC12IER1_L); /* ADC12 B Interrupt Enable 1 */
+sfr_b(ADC12IER1_H); /* ADC12 B Interrupt Enable 1 */
+sfr_w(ADC12IER2); /* ADC12 B Interrupt Enable 2 */
+sfr_b(ADC12IER2_L); /* ADC12 B Interrupt Enable 2 */
+sfr_b(ADC12IER2_H); /* ADC12 B Interrupt Enable 2 */
+sfr_w(ADC12IV); /* ADC12 B Interrupt Vector Word */
+sfr_b(ADC12IV_L); /* ADC12 B Interrupt Vector Word */
+sfr_b(ADC12IV_H); /* ADC12 B Interrupt Vector Word */
+
+sfr_w(ADC12MCTL0); /* ADC12 Memory Control 0 */
+sfr_b(ADC12MCTL0_L); /* ADC12 Memory Control 0 */
+sfr_b(ADC12MCTL0_H); /* ADC12 Memory Control 0 */
+sfr_w(ADC12MCTL1); /* ADC12 Memory Control 1 */
+sfr_b(ADC12MCTL1_L); /* ADC12 Memory Control 1 */
+sfr_b(ADC12MCTL1_H); /* ADC12 Memory Control 1 */
+sfr_w(ADC12MCTL2); /* ADC12 Memory Control 2 */
+sfr_b(ADC12MCTL2_L); /* ADC12 Memory Control 2 */
+sfr_b(ADC12MCTL2_H); /* ADC12 Memory Control 2 */
+sfr_w(ADC12MCTL3); /* ADC12 Memory Control 3 */
+sfr_b(ADC12MCTL3_L); /* ADC12 Memory Control 3 */
+sfr_b(ADC12MCTL3_H); /* ADC12 Memory Control 3 */
+sfr_w(ADC12MCTL4); /* ADC12 Memory Control 4 */
+sfr_b(ADC12MCTL4_L); /* ADC12 Memory Control 4 */
+sfr_b(ADC12MCTL4_H); /* ADC12 Memory Control 4 */
+sfr_w(ADC12MCTL5); /* ADC12 Memory Control 5 */
+sfr_b(ADC12MCTL5_L); /* ADC12 Memory Control 5 */
+sfr_b(ADC12MCTL5_H); /* ADC12 Memory Control 5 */
+sfr_w(ADC12MCTL6); /* ADC12 Memory Control 6 */
+sfr_b(ADC12MCTL6_L); /* ADC12 Memory Control 6 */
+sfr_b(ADC12MCTL6_H); /* ADC12 Memory Control 6 */
+sfr_w(ADC12MCTL7); /* ADC12 Memory Control 7 */
+sfr_b(ADC12MCTL7_L); /* ADC12 Memory Control 7 */
+sfr_b(ADC12MCTL7_H); /* ADC12 Memory Control 7 */
+sfr_w(ADC12MCTL8); /* ADC12 Memory Control 8 */
+sfr_b(ADC12MCTL8_L); /* ADC12 Memory Control 8 */
+sfr_b(ADC12MCTL8_H); /* ADC12 Memory Control 8 */
+sfr_w(ADC12MCTL9); /* ADC12 Memory Control 9 */
+sfr_b(ADC12MCTL9_L); /* ADC12 Memory Control 9 */
+sfr_b(ADC12MCTL9_H); /* ADC12 Memory Control 9 */
+sfr_w(ADC12MCTL10); /* ADC12 Memory Control 10 */
+sfr_b(ADC12MCTL10_L); /* ADC12 Memory Control 10 */
+sfr_b(ADC12MCTL10_H); /* ADC12 Memory Control 10 */
+sfr_w(ADC12MCTL11); /* ADC12 Memory Control 11 */
+sfr_b(ADC12MCTL11_L); /* ADC12 Memory Control 11 */
+sfr_b(ADC12MCTL11_H); /* ADC12 Memory Control 11 */
+sfr_w(ADC12MCTL12); /* ADC12 Memory Control 12 */
+sfr_b(ADC12MCTL12_L); /* ADC12 Memory Control 12 */
+sfr_b(ADC12MCTL12_H); /* ADC12 Memory Control 12 */
+sfr_w(ADC12MCTL13); /* ADC12 Memory Control 13 */
+sfr_b(ADC12MCTL13_L); /* ADC12 Memory Control 13 */
+sfr_b(ADC12MCTL13_H); /* ADC12 Memory Control 13 */
+sfr_w(ADC12MCTL14); /* ADC12 Memory Control 14 */
+sfr_b(ADC12MCTL14_L); /* ADC12 Memory Control 14 */
+sfr_b(ADC12MCTL14_H); /* ADC12 Memory Control 14 */
+sfr_w(ADC12MCTL15); /* ADC12 Memory Control 15 */
+sfr_b(ADC12MCTL15_L); /* ADC12 Memory Control 15 */
+sfr_b(ADC12MCTL15_H); /* ADC12 Memory Control 15 */
+sfr_w(ADC12MCTL16); /* ADC12 Memory Control 16 */
+sfr_b(ADC12MCTL16_L); /* ADC12 Memory Control 16 */
+sfr_b(ADC12MCTL16_H); /* ADC12 Memory Control 16 */
+sfr_w(ADC12MCTL17); /* ADC12 Memory Control 17 */
+sfr_b(ADC12MCTL17_L); /* ADC12 Memory Control 17 */
+sfr_b(ADC12MCTL17_H); /* ADC12 Memory Control 17 */
+sfr_w(ADC12MCTL18); /* ADC12 Memory Control 18 */
+sfr_b(ADC12MCTL18_L); /* ADC12 Memory Control 18 */
+sfr_b(ADC12MCTL18_H); /* ADC12 Memory Control 18 */
+sfr_w(ADC12MCTL19); /* ADC12 Memory Control 19 */
+sfr_b(ADC12MCTL19_L); /* ADC12 Memory Control 19 */
+sfr_b(ADC12MCTL19_H); /* ADC12 Memory Control 19 */
+sfr_w(ADC12MCTL20); /* ADC12 Memory Control 20 */
+sfr_b(ADC12MCTL20_L); /* ADC12 Memory Control 20 */
+sfr_b(ADC12MCTL20_H); /* ADC12 Memory Control 20 */
+sfr_w(ADC12MCTL21); /* ADC12 Memory Control 21 */
+sfr_b(ADC12MCTL21_L); /* ADC12 Memory Control 21 */
+sfr_b(ADC12MCTL21_H); /* ADC12 Memory Control 21 */
+sfr_w(ADC12MCTL22); /* ADC12 Memory Control 22 */
+sfr_b(ADC12MCTL22_L); /* ADC12 Memory Control 22 */
+sfr_b(ADC12MCTL22_H); /* ADC12 Memory Control 22 */
+sfr_w(ADC12MCTL23); /* ADC12 Memory Control 23 */
+sfr_b(ADC12MCTL23_L); /* ADC12 Memory Control 23 */
+sfr_b(ADC12MCTL23_H); /* ADC12 Memory Control 23 */
+sfr_w(ADC12MCTL24); /* ADC12 Memory Control 24 */
+sfr_b(ADC12MCTL24_L); /* ADC12 Memory Control 24 */
+sfr_b(ADC12MCTL24_H); /* ADC12 Memory Control 24 */
+sfr_w(ADC12MCTL25); /* ADC12 Memory Control 25 */
+sfr_b(ADC12MCTL25_L); /* ADC12 Memory Control 25 */
+sfr_b(ADC12MCTL25_H); /* ADC12 Memory Control 25 */
+sfr_w(ADC12MCTL26); /* ADC12 Memory Control 26 */
+sfr_b(ADC12MCTL26_L); /* ADC12 Memory Control 26 */
+sfr_b(ADC12MCTL26_H); /* ADC12 Memory Control 26 */
+sfr_w(ADC12MCTL27); /* ADC12 Memory Control 27 */
+sfr_b(ADC12MCTL27_L); /* ADC12 Memory Control 27 */
+sfr_b(ADC12MCTL27_H); /* ADC12 Memory Control 27 */
+sfr_w(ADC12MCTL28); /* ADC12 Memory Control 28 */
+sfr_b(ADC12MCTL28_L); /* ADC12 Memory Control 28 */
+sfr_b(ADC12MCTL28_H); /* ADC12 Memory Control 28 */
+sfr_w(ADC12MCTL29); /* ADC12 Memory Control 29 */
+sfr_b(ADC12MCTL29_L); /* ADC12 Memory Control 29 */
+sfr_b(ADC12MCTL29_H); /* ADC12 Memory Control 29 */
+sfr_w(ADC12MCTL30); /* ADC12 Memory Control 30 */
+sfr_b(ADC12MCTL30_L); /* ADC12 Memory Control 30 */
+sfr_b(ADC12MCTL30_H); /* ADC12 Memory Control 30 */
+sfr_w(ADC12MCTL31); /* ADC12 Memory Control 31 */
+sfr_b(ADC12MCTL31_L); /* ADC12 Memory Control 31 */
+sfr_b(ADC12MCTL31_H); /* ADC12 Memory Control 31 */
+#define ADC12MCTL_ ADC12MCTL /* ADC12 Memory Control */
+#ifndef __STDC__
+#define ADC12MCTL ADC12MCTL0 /* ADC12 Memory Control (for assembler) */
+#else
+#define ADC12MCTL ((volatile char*) &ADC12MCTL0) /* ADC12 Memory Control (for C) */
+#endif
+
+sfr_w(ADC12MEM0); /* ADC12 Conversion Memory 0 */
+sfr_b(ADC12MEM0_L); /* ADC12 Conversion Memory 0 */
+sfr_b(ADC12MEM0_H); /* ADC12 Conversion Memory 0 */
+sfr_w(ADC12MEM1); /* ADC12 Conversion Memory 1 */
+sfr_b(ADC12MEM1_L); /* ADC12 Conversion Memory 1 */
+sfr_b(ADC12MEM1_H); /* ADC12 Conversion Memory 1 */
+sfr_w(ADC12MEM2); /* ADC12 Conversion Memory 2 */
+sfr_b(ADC12MEM2_L); /* ADC12 Conversion Memory 2 */
+sfr_b(ADC12MEM2_H); /* ADC12 Conversion Memory 2 */
+sfr_w(ADC12MEM3); /* ADC12 Conversion Memory 3 */
+sfr_b(ADC12MEM3_L); /* ADC12 Conversion Memory 3 */
+sfr_b(ADC12MEM3_H); /* ADC12 Conversion Memory 3 */
+sfr_w(ADC12MEM4); /* ADC12 Conversion Memory 4 */
+sfr_b(ADC12MEM4_L); /* ADC12 Conversion Memory 4 */
+sfr_b(ADC12MEM4_H); /* ADC12 Conversion Memory 4 */
+sfr_w(ADC12MEM5); /* ADC12 Conversion Memory 5 */
+sfr_b(ADC12MEM5_L); /* ADC12 Conversion Memory 5 */
+sfr_b(ADC12MEM5_H); /* ADC12 Conversion Memory 5 */
+sfr_w(ADC12MEM6); /* ADC12 Conversion Memory 6 */
+sfr_b(ADC12MEM6_L); /* ADC12 Conversion Memory 6 */
+sfr_b(ADC12MEM6_H); /* ADC12 Conversion Memory 6 */
+sfr_w(ADC12MEM7); /* ADC12 Conversion Memory 7 */
+sfr_b(ADC12MEM7_L); /* ADC12 Conversion Memory 7 */
+sfr_b(ADC12MEM7_H); /* ADC12 Conversion Memory 7 */
+sfr_w(ADC12MEM8); /* ADC12 Conversion Memory 8 */
+sfr_b(ADC12MEM8_L); /* ADC12 Conversion Memory 8 */
+sfr_b(ADC12MEM8_H); /* ADC12 Conversion Memory 8 */
+sfr_w(ADC12MEM9); /* ADC12 Conversion Memory 9 */
+sfr_b(ADC12MEM9_L); /* ADC12 Conversion Memory 9 */
+sfr_b(ADC12MEM9_H); /* ADC12 Conversion Memory 9 */
+sfr_w(ADC12MEM10); /* ADC12 Conversion Memory 10 */
+sfr_b(ADC12MEM10_L); /* ADC12 Conversion Memory 10 */
+sfr_b(ADC12MEM10_H); /* ADC12 Conversion Memory 10 */
+sfr_w(ADC12MEM11); /* ADC12 Conversion Memory 11 */
+sfr_b(ADC12MEM11_L); /* ADC12 Conversion Memory 11 */
+sfr_b(ADC12MEM11_H); /* ADC12 Conversion Memory 11 */
+sfr_w(ADC12MEM12); /* ADC12 Conversion Memory 12 */
+sfr_b(ADC12MEM12_L); /* ADC12 Conversion Memory 12 */
+sfr_b(ADC12MEM12_H); /* ADC12 Conversion Memory 12 */
+sfr_w(ADC12MEM13); /* ADC12 Conversion Memory 13 */
+sfr_b(ADC12MEM13_L); /* ADC12 Conversion Memory 13 */
+sfr_b(ADC12MEM13_H); /* ADC12 Conversion Memory 13 */
+sfr_w(ADC12MEM14); /* ADC12 Conversion Memory 14 */
+sfr_b(ADC12MEM14_L); /* ADC12 Conversion Memory 14 */
+sfr_b(ADC12MEM14_H); /* ADC12 Conversion Memory 14 */
+sfr_w(ADC12MEM15); /* ADC12 Conversion Memory 15 */
+sfr_b(ADC12MEM15_L); /* ADC12 Conversion Memory 15 */
+sfr_b(ADC12MEM15_H); /* ADC12 Conversion Memory 15 */
+sfr_w(ADC12MEM16); /* ADC12 Conversion Memory 16 */
+sfr_b(ADC12MEM16_L); /* ADC12 Conversion Memory 16 */
+sfr_b(ADC12MEM16_H); /* ADC12 Conversion Memory 16 */
+sfr_w(ADC12MEM17); /* ADC12 Conversion Memory 17 */
+sfr_b(ADC12MEM17_L); /* ADC12 Conversion Memory 17 */
+sfr_b(ADC12MEM17_H); /* ADC12 Conversion Memory 17 */
+sfr_w(ADC12MEM18); /* ADC12 Conversion Memory 18 */
+sfr_b(ADC12MEM18_L); /* ADC12 Conversion Memory 18 */
+sfr_b(ADC12MEM18_H); /* ADC12 Conversion Memory 18 */
+sfr_w(ADC12MEM19); /* ADC12 Conversion Memory 19 */
+sfr_b(ADC12MEM19_L); /* ADC12 Conversion Memory 19 */
+sfr_b(ADC12MEM19_H); /* ADC12 Conversion Memory 19 */
+sfr_w(ADC12MEM20); /* ADC12 Conversion Memory 20 */
+sfr_b(ADC12MEM20_L); /* ADC12 Conversion Memory 20 */
+sfr_b(ADC12MEM20_H); /* ADC12 Conversion Memory 20 */
+sfr_w(ADC12MEM21); /* ADC12 Conversion Memory 21 */
+sfr_b(ADC12MEM21_L); /* ADC12 Conversion Memory 21 */
+sfr_b(ADC12MEM21_H); /* ADC12 Conversion Memory 21 */
+sfr_w(ADC12MEM22); /* ADC12 Conversion Memory 22 */
+sfr_b(ADC12MEM22_L); /* ADC12 Conversion Memory 22 */
+sfr_b(ADC12MEM22_H); /* ADC12 Conversion Memory 22 */
+sfr_w(ADC12MEM23); /* ADC12 Conversion Memory 23 */
+sfr_b(ADC12MEM23_L); /* ADC12 Conversion Memory 23 */
+sfr_b(ADC12MEM23_H); /* ADC12 Conversion Memory 23 */
+sfr_w(ADC12MEM24); /* ADC12 Conversion Memory 24 */
+sfr_b(ADC12MEM24_L); /* ADC12 Conversion Memory 24 */
+sfr_b(ADC12MEM24_H); /* ADC12 Conversion Memory 24 */
+sfr_w(ADC12MEM25); /* ADC12 Conversion Memory 25 */
+sfr_b(ADC12MEM25_L); /* ADC12 Conversion Memory 25 */
+sfr_b(ADC12MEM25_H); /* ADC12 Conversion Memory 25 */
+sfr_w(ADC12MEM26); /* ADC12 Conversion Memory 26 */
+sfr_b(ADC12MEM26_L); /* ADC12 Conversion Memory 26 */
+sfr_b(ADC12MEM26_H); /* ADC12 Conversion Memory 26 */
+sfr_w(ADC12MEM27); /* ADC12 Conversion Memory 27 */
+sfr_b(ADC12MEM27_L); /* ADC12 Conversion Memory 27 */
+sfr_b(ADC12MEM27_H); /* ADC12 Conversion Memory 27 */
+sfr_w(ADC12MEM28); /* ADC12 Conversion Memory 28 */
+sfr_b(ADC12MEM28_L); /* ADC12 Conversion Memory 28 */
+sfr_b(ADC12MEM28_H); /* ADC12 Conversion Memory 28 */
+sfr_w(ADC12MEM29); /* ADC12 Conversion Memory 29 */
+sfr_b(ADC12MEM29_L); /* ADC12 Conversion Memory 29 */
+sfr_b(ADC12MEM29_H); /* ADC12 Conversion Memory 29 */
+sfr_w(ADC12MEM30); /* ADC12 Conversion Memory 30 */
+sfr_b(ADC12MEM30_L); /* ADC12 Conversion Memory 30 */
+sfr_b(ADC12MEM30_H); /* ADC12 Conversion Memory 30 */
+sfr_w(ADC12MEM31); /* ADC12 Conversion Memory 31 */
+sfr_b(ADC12MEM31_L); /* ADC12 Conversion Memory 31 */
+sfr_b(ADC12MEM31_H); /* ADC12 Conversion Memory 31 */
+#define ADC12MEM_ ADC12MEM /* ADC12 Conversion Memory */
+#ifndef __STDC__
+#define ADC12MEM ADC12MEM0 /* ADC12 Conversion Memory (for assembler) */
+#else
+#define ADC12MEM ((volatile int*) &ADC12MEM0) /* ADC12 Conversion Memory (for C) */
+#endif
+
+/* ADC12CTL0 Control Bits */
+#define ADC12SC (0x0001) /* ADC12 Start Conversion */
+#define ADC12ENC (0x0002) /* ADC12 Enable Conversion */
+#define ADC12ON (0x0010) /* ADC12 On/enable */
+#define ADC12MSC (0x0080) /* ADC12 Multiple SampleConversion */
+#define ADC12SHT00 (0x0100) /* ADC12 Sample Hold 0 Select Bit: 0 */
+#define ADC12SHT01 (0x0200) /* ADC12 Sample Hold 0 Select Bit: 1 */
+#define ADC12SHT02 (0x0400) /* ADC12 Sample Hold 0 Select Bit: 2 */
+#define ADC12SHT03 (0x0800) /* ADC12 Sample Hold 0 Select Bit: 3 */
+#define ADC12SHT10 (0x1000) /* ADC12 Sample Hold 1 Select Bit: 0 */
+#define ADC12SHT11 (0x2000) /* ADC12 Sample Hold 1 Select Bit: 1 */
+#define ADC12SHT12 (0x4000) /* ADC12 Sample Hold 1 Select Bit: 2 */
+#define ADC12SHT13 (0x8000) /* ADC12 Sample Hold 1 Select Bit: 3 */
+
+/* ADC12CTL0 Control Bits */
+#define ADC12SC_L (0x0001) /* ADC12 Start Conversion */
+#define ADC12ENC_L (0x0002) /* ADC12 Enable Conversion */
+#define ADC12ON_L (0x0010) /* ADC12 On/enable */
+#define ADC12MSC_L (0x0080) /* ADC12 Multiple SampleConversion */
+
+/* ADC12CTL0 Control Bits */
+#define ADC12SHT00_H (0x0001) /* ADC12 Sample Hold 0 Select Bit: 0 */
+#define ADC12SHT01_H (0x0002) /* ADC12 Sample Hold 0 Select Bit: 1 */
+#define ADC12SHT02_H (0x0004) /* ADC12 Sample Hold 0 Select Bit: 2 */
+#define ADC12SHT03_H (0x0008) /* ADC12 Sample Hold 0 Select Bit: 3 */
+#define ADC12SHT10_H (0x0010) /* ADC12 Sample Hold 1 Select Bit: 0 */
+#define ADC12SHT11_H (0x0020) /* ADC12 Sample Hold 1 Select Bit: 1 */
+#define ADC12SHT12_H (0x0040) /* ADC12 Sample Hold 1 Select Bit: 2 */
+#define ADC12SHT13_H (0x0080) /* ADC12 Sample Hold 1 Select Bit: 3 */
+
+#define ADC12SHT0_0 (0x0000) /* ADC12 Sample Hold 0 Select Bit: 0 */
+#define ADC12SHT0_1 (0x0100) /* ADC12 Sample Hold 0 Select Bit: 1 */
+#define ADC12SHT0_2 (0x0200) /* ADC12 Sample Hold 0 Select Bit: 2 */
+#define ADC12SHT0_3 (0x0300) /* ADC12 Sample Hold 0 Select Bit: 3 */
+#define ADC12SHT0_4 (0x0400) /* ADC12 Sample Hold 0 Select Bit: 4 */
+#define ADC12SHT0_5 (0x0500) /* ADC12 Sample Hold 0 Select Bit: 5 */
+#define ADC12SHT0_6 (0x0600) /* ADC12 Sample Hold 0 Select Bit: 6 */
+#define ADC12SHT0_7 (0x0700) /* ADC12 Sample Hold 0 Select Bit: 7 */
+#define ADC12SHT0_8 (0x0800) /* ADC12 Sample Hold 0 Select Bit: 8 */
+#define ADC12SHT0_9 (0x0900) /* ADC12 Sample Hold 0 Select Bit: 9 */
+#define ADC12SHT0_10 (0x0A00) /* ADC12 Sample Hold 0 Select Bit: 10 */
+#define ADC12SHT0_11 (0x0B00) /* ADC12 Sample Hold 0 Select Bit: 11 */
+#define ADC12SHT0_12 (0x0C00) /* ADC12 Sample Hold 0 Select Bit: 12 */
+#define ADC12SHT0_13 (0x0D00) /* ADC12 Sample Hold 0 Select Bit: 13 */
+#define ADC12SHT0_14 (0x0E00) /* ADC12 Sample Hold 0 Select Bit: 14 */
+#define ADC12SHT0_15 (0x0F00) /* ADC12 Sample Hold 0 Select Bit: 15 */
+
+#define ADC12SHT1_0 (0x0000) /* ADC12 Sample Hold 1 Select Bit: 0 */
+#define ADC12SHT1_1 (0x1000) /* ADC12 Sample Hold 1 Select Bit: 1 */
+#define ADC12SHT1_2 (0x2000) /* ADC12 Sample Hold 1 Select Bit: 2 */
+#define ADC12SHT1_3 (0x3000) /* ADC12 Sample Hold 1 Select Bit: 3 */
+#define ADC12SHT1_4 (0x4000) /* ADC12 Sample Hold 1 Select Bit: 4 */
+#define ADC12SHT1_5 (0x5000) /* ADC12 Sample Hold 1 Select Bit: 5 */
+#define ADC12SHT1_6 (0x6000) /* ADC12 Sample Hold 1 Select Bit: 6 */
+#define ADC12SHT1_7 (0x7000) /* ADC12 Sample Hold 1 Select Bit: 7 */
+#define ADC12SHT1_8 (0x8000) /* ADC12 Sample Hold 1 Select Bit: 8 */
+#define ADC12SHT1_9 (0x9000) /* ADC12 Sample Hold 1 Select Bit: 9 */
+#define ADC12SHT1_10 (0xA000) /* ADC12 Sample Hold 1 Select Bit: 10 */
+#define ADC12SHT1_11 (0xB000) /* ADC12 Sample Hold 1 Select Bit: 11 */
+#define ADC12SHT1_12 (0xC000) /* ADC12 Sample Hold 1 Select Bit: 12 */
+#define ADC12SHT1_13 (0xD000) /* ADC12 Sample Hold 1 Select Bit: 13 */
+#define ADC12SHT1_14 (0xE000) /* ADC12 Sample Hold 1 Select Bit: 14 */
+#define ADC12SHT1_15 (0xF000) /* ADC12 Sample Hold 1 Select Bit: 15 */
+
+/* ADC12CTL1 Control Bits */
+#define ADC12BUSY (0x0001) /* ADC12 Busy */
+#define ADC12CONSEQ0 (0x0002) /* ADC12 Conversion Sequence Select Bit: 0 */
+#define ADC12CONSEQ1 (0x0004) /* ADC12 Conversion Sequence Select Bit: 1 */
+#define ADC12SSEL0 (0x0008) /* ADC12 Clock Source Select Bit: 0 */
+#define ADC12SSEL1 (0x0010) /* ADC12 Clock Source Select Bit: 1 */
+#define ADC12DIV0 (0x0020) /* ADC12 Clock Divider Select Bit: 0 */
+#define ADC12DIV1 (0x0040) /* ADC12 Clock Divider Select Bit: 1 */
+#define ADC12DIV2 (0x0080) /* ADC12 Clock Divider Select Bit: 2 */
+#define ADC12ISSH (0x0100) /* ADC12 Invert Sample Hold Signal */
+#define ADC12SHP (0x0200) /* ADC12 Sample/Hold Pulse Mode */
+#define ADC12SHS0 (0x0400) /* ADC12 Sample/Hold Source Bit: 0 */
+#define ADC12SHS1 (0x0800) /* ADC12 Sample/Hold Source Bit: 1 */
+#define ADC12SHS2 (0x1000) /* ADC12 Sample/Hold Source Bit: 2 */
+#define ADC12PDIV0 (0x2000) /* ADC12 Predivider Bit: 0 */
+#define ADC12PDIV1 (0x4000) /* ADC12 Predivider Bit: 1 */
+
+/* ADC12CTL1 Control Bits */
+#define ADC12BUSY_L (0x0001) /* ADC12 Busy */
+#define ADC12CONSEQ0_L (0x0002) /* ADC12 Conversion Sequence Select Bit: 0 */
+#define ADC12CONSEQ1_L (0x0004) /* ADC12 Conversion Sequence Select Bit: 1 */
+#define ADC12SSEL0_L (0x0008) /* ADC12 Clock Source Select Bit: 0 */
+#define ADC12SSEL1_L (0x0010) /* ADC12 Clock Source Select Bit: 1 */
+#define ADC12DIV0_L (0x0020) /* ADC12 Clock Divider Select Bit: 0 */
+#define ADC12DIV1_L (0x0040) /* ADC12 Clock Divider Select Bit: 1 */
+#define ADC12DIV2_L (0x0080) /* ADC12 Clock Divider Select Bit: 2 */
+
+/* ADC12CTL1 Control Bits */
+#define ADC12ISSH_H (0x0001) /* ADC12 Invert Sample Hold Signal */
+#define ADC12SHP_H (0x0002) /* ADC12 Sample/Hold Pulse Mode */
+#define ADC12SHS0_H (0x0004) /* ADC12 Sample/Hold Source Bit: 0 */
+#define ADC12SHS1_H (0x0008) /* ADC12 Sample/Hold Source Bit: 1 */
+#define ADC12SHS2_H (0x0010) /* ADC12 Sample/Hold Source Bit: 2 */
+#define ADC12PDIV0_H (0x0020) /* ADC12 Predivider Bit: 0 */
+#define ADC12PDIV1_H (0x0040) /* ADC12 Predivider Bit: 1 */
+
+#define ADC12CONSEQ_0 (0x0000) /* ADC12 Conversion Sequence Select: 0 */
+#define ADC12CONSEQ_1 (0x0002) /* ADC12 Conversion Sequence Select: 1 */
+#define ADC12CONSEQ_2 (0x0004) /* ADC12 Conversion Sequence Select: 2 */
+#define ADC12CONSEQ_3 (0x0006) /* ADC12 Conversion Sequence Select: 3 */
+
+#define ADC12SSEL_0 (0x0000) /* ADC12 Clock Source Select: 0 */
+#define ADC12SSEL_1 (0x0008) /* ADC12 Clock Source Select: 1 */
+#define ADC12SSEL_2 (0x0010) /* ADC12 Clock Source Select: 2 */
+#define ADC12SSEL_3 (0x0018) /* ADC12 Clock Source Select: 3 */
+
+#define ADC12DIV_0 (0x0000) /* ADC12 Clock Divider Select: 0 */
+#define ADC12DIV_1 (0x0020) /* ADC12 Clock Divider Select: 1 */
+#define ADC12DIV_2 (0x0040) /* ADC12 Clock Divider Select: 2 */
+#define ADC12DIV_3 (0x0060) /* ADC12 Clock Divider Select: 3 */
+#define ADC12DIV_4 (0x0080) /* ADC12 Clock Divider Select: 4 */
+#define ADC12DIV_5 (0x00A0) /* ADC12 Clock Divider Select: 5 */
+#define ADC12DIV_6 (0x00C0) /* ADC12 Clock Divider Select: 6 */
+#define ADC12DIV_7 (0x00E0) /* ADC12 Clock Divider Select: 7 */
+
+#define ADC12SHS_0 (0x0000) /* ADC12 Sample/Hold Source: 0 */
+#define ADC12SHS_1 (0x0400) /* ADC12 Sample/Hold Source: 1 */
+#define ADC12SHS_2 (0x0800) /* ADC12 Sample/Hold Source: 2 */
+#define ADC12SHS_3 (0x0C00) /* ADC12 Sample/Hold Source: 3 */
+#define ADC12SHS_4 (0x1000) /* ADC12 Sample/Hold Source: 4 */
+#define ADC12SHS_5 (0x1400) /* ADC12 Sample/Hold Source: 5 */
+#define ADC12SHS_6 (0x1800) /* ADC12 Sample/Hold Source: 6 */
+#define ADC12SHS_7 (0x1C00) /* ADC12 Sample/Hold Source: 7 */
+
+#define ADC12PDIV_0 (0x0000) /* ADC12 Clock predivider Select 0 */
+#define ADC12PDIV_1 (0x2000) /* ADC12 Clock predivider Select 1 */
+#define ADC12PDIV_2 (0x4000) /* ADC12 Clock predivider Select 2 */
+#define ADC12PDIV_3 (0x6000) /* ADC12 Clock predivider Select 3 */
+#define ADC12PDIV__1 (0x0000) /* ADC12 Clock predivider Select: /1 */
+#define ADC12PDIV__4 (0x2000) /* ADC12 Clock predivider Select: /4 */
+#define ADC12PDIV__32 (0x4000) /* ADC12 Clock predivider Select: /32 */
+#define ADC12PDIV__64 (0x6000) /* ADC12 Clock predivider Select: /64 */
+
+/* ADC12CTL2 Control Bits */
+#define ADC12PWRMD (0x0001) /* ADC12 Power Mode */
+#define ADC12DF (0x0008) /* ADC12 Data Format */
+#define ADC12RES0 (0x0010) /* ADC12 Resolution Bit: 0 */
+#define ADC12RES1 (0x0020) /* ADC12 Resolution Bit: 1 */
+
+/* ADC12CTL2 Control Bits */
+#define ADC12PWRMD_L (0x0001) /* ADC12 Power Mode */
+#define ADC12DF_L (0x0008) /* ADC12 Data Format */
+#define ADC12RES0_L (0x0010) /* ADC12 Resolution Bit: 0 */
+#define ADC12RES1_L (0x0020) /* ADC12 Resolution Bit: 1 */
+
+#define ADC12RES_0 (0x0000) /* ADC12+ Resolution : 8 Bit */
+#define ADC12RES_1 (0x0010) /* ADC12+ Resolution : 10 Bit */
+#define ADC12RES_2 (0x0020) /* ADC12+ Resolution : 12 Bit */
+#define ADC12RES_3 (0x0030) /* ADC12+ Resolution : reserved */
+
+#define ADC12RES__8BIT (0x0000) /* ADC12+ Resolution : 8 Bit */
+#define ADC12RES__10BIT (0x0010) /* ADC12+ Resolution : 10 Bit */
+#define ADC12RES__12BIT (0x0020) /* ADC12+ Resolution : 12 Bit */
+
+/* ADC12CTL3 Control Bits */
+#define ADC12CSTARTADD0 (0x0001) /* ADC12 Conversion Start Address Bit: 0 */
+#define ADC12CSTARTADD1 (0x0002) /* ADC12 Conversion Start Address Bit: 1 */
+#define ADC12CSTARTADD2 (0x0004) /* ADC12 Conversion Start Address Bit: 2 */
+#define ADC12CSTARTADD3 (0x0008) /* ADC12 Conversion Start Address Bit: 3 */
+#define ADC12CSTARTADD4 (0x0010) /* ADC12 Conversion Start Address Bit: 4 */
+#define ADC12BATMAP (0x0040) /* ADC12 Internal AVCC/2 select */
+#define ADC12TCMAP (0x0080) /* ADC12 Internal TempSensor select */
+#define ADC12ICH0MAP (0x0100) /* ADC12 Internal Channel 0 select */
+#define ADC12ICH1MAP (0x0200) /* ADC12 Internal Channel 1 select */
+#define ADC12ICH2MAP (0x0400) /* ADC12 Internal Channel 2 select */
+#define ADC12ICH3MAP (0x0800) /* ADC12 Internal Channel 3 select */
+
+/* ADC12CTL3 Control Bits */
+#define ADC12CSTARTADD0_L (0x0001) /* ADC12 Conversion Start Address Bit: 0 */
+#define ADC12CSTARTADD1_L (0x0002) /* ADC12 Conversion Start Address Bit: 1 */
+#define ADC12CSTARTADD2_L (0x0004) /* ADC12 Conversion Start Address Bit: 2 */
+#define ADC12CSTARTADD3_L (0x0008) /* ADC12 Conversion Start Address Bit: 3 */
+#define ADC12CSTARTADD4_L (0x0010) /* ADC12 Conversion Start Address Bit: 4 */
+#define ADC12BATMAP_L (0x0040) /* ADC12 Internal AVCC/2 select */
+#define ADC12TCMAP_L (0x0080) /* ADC12 Internal TempSensor select */
+
+/* ADC12CTL3 Control Bits */
+#define ADC12ICH0MAP_H (0x0001) /* ADC12 Internal Channel 0 select */
+#define ADC12ICH1MAP_H (0x0002) /* ADC12 Internal Channel 1 select */
+#define ADC12ICH2MAP_H (0x0004) /* ADC12 Internal Channel 2 select */
+#define ADC12ICH3MAP_H (0x0008) /* ADC12 Internal Channel 3 select */
+
+#define ADC12CSTARTADD_0 (0x0000) /* ADC12 Conversion Start Address: 0 */
+#define ADC12CSTARTADD_1 (0x0001) /* ADC12 Conversion Start Address: 1 */
+#define ADC12CSTARTADD_2 (0x0002) /* ADC12 Conversion Start Address: 2 */
+#define ADC12CSTARTADD_3 (0x0003) /* ADC12 Conversion Start Address: 3 */
+#define ADC12CSTARTADD_4 (0x0004) /* ADC12 Conversion Start Address: 4 */
+#define ADC12CSTARTADD_5 (0x0005) /* ADC12 Conversion Start Address: 5 */
+#define ADC12CSTARTADD_6 (0x0006) /* ADC12 Conversion Start Address: 6 */
+#define ADC12CSTARTADD_7 (0x0007) /* ADC12 Conversion Start Address: 7 */
+#define ADC12CSTARTADD_8 (0x0008) /* ADC12 Conversion Start Address: 8 */
+#define ADC12CSTARTADD_9 (0x0009) /* ADC12 Conversion Start Address: 9 */
+#define ADC12CSTARTADD_10 (0x000A) /* ADC12 Conversion Start Address: 10 */
+#define ADC12CSTARTADD_11 (0x000B) /* ADC12 Conversion Start Address: 11 */
+#define ADC12CSTARTADD_12 (0x000C) /* ADC12 Conversion Start Address: 12 */
+#define ADC12CSTARTADD_13 (0x000D) /* ADC12 Conversion Start Address: 13 */
+#define ADC12CSTARTADD_14 (0x000E) /* ADC12 Conversion Start Address: 14 */
+#define ADC12CSTARTADD_15 (0x000F) /* ADC12 Conversion Start Address: 15 */
+#define ADC12CSTARTADD_16 (0x0010) /* ADC12 Conversion Start Address: 16 */
+#define ADC12CSTARTADD_17 (0x0011) /* ADC12 Conversion Start Address: 17 */
+#define ADC12CSTARTADD_18 (0x0012) /* ADC12 Conversion Start Address: 18 */
+#define ADC12CSTARTADD_19 (0x0013) /* ADC12 Conversion Start Address: 19 */
+#define ADC12CSTARTADD_20 (0x0014) /* ADC12 Conversion Start Address: 20 */
+#define ADC12CSTARTADD_21 (0x0015) /* ADC12 Conversion Start Address: 21 */
+#define ADC12CSTARTADD_22 (0x0016) /* ADC12 Conversion Start Address: 22 */
+#define ADC12CSTARTADD_23 (0x0017) /* ADC12 Conversion Start Address: 23 */
+#define ADC12CSTARTADD_24 (0x0018) /* ADC12 Conversion Start Address: 24 */
+#define ADC12CSTARTADD_25 (0x0019) /* ADC12 Conversion Start Address: 25 */
+#define ADC12CSTARTADD_26 (0x001A) /* ADC12 Conversion Start Address: 26 */
+#define ADC12CSTARTADD_27 (0x001B) /* ADC12 Conversion Start Address: 27 */
+#define ADC12CSTARTADD_28 (0x001C) /* ADC12 Conversion Start Address: 28 */
+#define ADC12CSTARTADD_29 (0x001D) /* ADC12 Conversion Start Address: 29 */
+#define ADC12CSTARTADD_30 (0x001E) /* ADC12 Conversion Start Address: 30 */
+#define ADC12CSTARTADD_31 (0x001F) /* ADC12 Conversion Start Address: 31 */
+
+/* ADC12MCTLx Control Bits */
+#define ADC12INCH0 (0x0001) /* ADC12 Input Channel Select Bit 0 */
+#define ADC12INCH1 (0x0002) /* ADC12 Input Channel Select Bit 1 */
+#define ADC12INCH2 (0x0004) /* ADC12 Input Channel Select Bit 2 */
+#define ADC12INCH3 (0x0008) /* ADC12 Input Channel Select Bit 3 */
+#define ADC12INCH4 (0x0010) /* ADC12 Input Channel Select Bit 4 */
+#define ADC12EOS (0x0080) /* ADC12 End of Sequence */
+#define ADC12VRSEL0 (0x0100) /* ADC12 VR Select Bit 0 */
+#define ADC12VRSEL1 (0x0200) /* ADC12 VR Select Bit 1 */
+#define ADC12VRSEL2 (0x0400) /* ADC12 VR Select Bit 2 */
+#define ADC12VRSEL3 (0x0800) /* ADC12 VR Select Bit 3 */
+#define ADC12DIF (0x2000) /* ADC12 Differential mode (only for even Registers) */
+#define ADC12WINC (0x4000) /* ADC12 Comparator window enable */
+
+/* ADC12MCTLx Control Bits */
+#define ADC12INCH0_L (0x0001) /* ADC12 Input Channel Select Bit 0 */
+#define ADC12INCH1_L (0x0002) /* ADC12 Input Channel Select Bit 1 */
+#define ADC12INCH2_L (0x0004) /* ADC12 Input Channel Select Bit 2 */
+#define ADC12INCH3_L (0x0008) /* ADC12 Input Channel Select Bit 3 */
+#define ADC12INCH4_L (0x0010) /* ADC12 Input Channel Select Bit 4 */
+#define ADC12EOS_L (0x0080) /* ADC12 End of Sequence */
+
+/* ADC12MCTLx Control Bits */
+#define ADC12VRSEL0_H (0x0001) /* ADC12 VR Select Bit 0 */
+#define ADC12VRSEL1_H (0x0002) /* ADC12 VR Select Bit 1 */
+#define ADC12VRSEL2_H (0x0004) /* ADC12 VR Select Bit 2 */
+#define ADC12VRSEL3_H (0x0008) /* ADC12 VR Select Bit 3 */
+#define ADC12DIF_H (0x0020) /* ADC12 Differential mode (only for even Registers) */
+#define ADC12WINC_H (0x0040) /* ADC12 Comparator window enable */
+
+#define ADC12INCH_0 (0x0000) /* ADC12 Input Channel 0 */
+#define ADC12INCH_1 (0x0001) /* ADC12 Input Channel 1 */
+#define ADC12INCH_2 (0x0002) /* ADC12 Input Channel 2 */
+#define ADC12INCH_3 (0x0003) /* ADC12 Input Channel 3 */
+#define ADC12INCH_4 (0x0004) /* ADC12 Input Channel 4 */
+#define ADC12INCH_5 (0x0005) /* ADC12 Input Channel 5 */
+#define ADC12INCH_6 (0x0006) /* ADC12 Input Channel 6 */
+#define ADC12INCH_7 (0x0007) /* ADC12 Input Channel 7 */
+#define ADC12INCH_8 (0x0008) /* ADC12 Input Channel 8 */
+#define ADC12INCH_9 (0x0009) /* ADC12 Input Channel 9 */
+#define ADC12INCH_10 (0x000A) /* ADC12 Input Channel 10 */
+#define ADC12INCH_11 (0x000B) /* ADC12 Input Channel 11 */
+#define ADC12INCH_12 (0x000C) /* ADC12 Input Channel 12 */
+#define ADC12INCH_13 (0x000D) /* ADC12 Input Channel 13 */
+#define ADC12INCH_14 (0x000E) /* ADC12 Input Channel 14 */
+#define ADC12INCH_15 (0x000F) /* ADC12 Input Channel 15 */
+#define ADC12INCH_16 (0x0010) /* ADC12 Input Channel 16 */
+#define ADC12INCH_17 (0x0011) /* ADC12 Input Channel 17 */
+#define ADC12INCH_18 (0x0012) /* ADC12 Input Channel 18 */
+#define ADC12INCH_19 (0x0013) /* ADC12 Input Channel 19 */
+#define ADC12INCH_20 (0x0014) /* ADC12 Input Channel 20 */
+#define ADC12INCH_21 (0x0015) /* ADC12 Input Channel 21 */
+#define ADC12INCH_22 (0x0016) /* ADC12 Input Channel 22 */
+#define ADC12INCH_23 (0x0017) /* ADC12 Input Channel 23 */
+#define ADC12INCH_24 (0x0018) /* ADC12 Input Channel 24 */
+#define ADC12INCH_25 (0x0019) /* ADC12 Input Channel 25 */
+#define ADC12INCH_26 (0x001A) /* ADC12 Input Channel 26 */
+#define ADC12INCH_27 (0x001B) /* ADC12 Input Channel 27 */
+#define ADC12INCH_28 (0x001C) /* ADC12 Input Channel 28 */
+#define ADC12INCH_29 (0x001D) /* ADC12 Input Channel 29 */
+#define ADC12INCH_30 (0x001E) /* ADC12 Input Channel 30 */
+#define ADC12INCH_31 (0x001F) /* ADC12 Input Channel 31 */
+
+#define ADC12VRSEL_0 (0x0000) /* ADC12 Select Reference 0 */
+#define ADC12VRSEL_1 (0x0100) /* ADC12 Select Reference 1 */
+#define ADC12VRSEL_2 (0x0200) /* ADC12 Select Reference 2 */
+#define ADC12VRSEL_3 (0x0300) /* ADC12 Select Reference 3 */
+#define ADC12VRSEL_4 (0x0400) /* ADC12 Select Reference 4 */
+#define ADC12VRSEL_5 (0x0500) /* ADC12 Select Reference 5 */
+#define ADC12VRSEL_6 (0x0600) /* ADC12 Select Reference 6 */
+#define ADC12VRSEL_7 (0x0700) /* ADC12 Select Reference 7 */
+#define ADC12VRSEL_8 (0x0800) /* ADC12 Select Reference 8 */
+#define ADC12VRSEL_9 (0x0900) /* ADC12 Select Reference 9 */
+#define ADC12VRSEL_10 (0x0A00) /* ADC12 Select Reference 10 */
+#define ADC12VRSEL_11 (0x0B00) /* ADC12 Select Reference 11 */
+#define ADC12VRSEL_12 (0x0C00) /* ADC12 Select Reference 12 */
+#define ADC12VRSEL_13 (0x0D00) /* ADC12 Select Reference 13 */
+#define ADC12VRSEL_14 (0x0E00) /* ADC12 Select Reference 14 */
+#define ADC12VRSEL_15 (0x0F00) /* ADC12 Select Reference 15 */
+
+/* ADC12HI Control Bits */
+
+/* ADC12LO Control Bits */
+
+/* ADC12IER0 Control Bits */
+#define ADC12IE0 (0x0001) /* ADC12 Memory 0 Interrupt Enable */
+#define ADC12IE1 (0x0002) /* ADC12 Memory 1 Interrupt Enable */
+#define ADC12IE2 (0x0004) /* ADC12 Memory 2 Interrupt Enable */
+#define ADC12IE3 (0x0008) /* ADC12 Memory 3 Interrupt Enable */
+#define ADC12IE4 (0x0010) /* ADC12 Memory 4 Interrupt Enable */
+#define ADC12IE5 (0x0020) /* ADC12 Memory 5 Interrupt Enable */
+#define ADC12IE6 (0x0040) /* ADC12 Memory 6 Interrupt Enable */
+#define ADC12IE7 (0x0080) /* ADC12 Memory 7 Interrupt Enable */
+#define ADC12IE8 (0x0100) /* ADC12 Memory 8 Interrupt Enable */
+#define ADC12IE9 (0x0200) /* ADC12 Memory 9 Interrupt Enable */
+#define ADC12IE10 (0x0400) /* ADC12 Memory 10 Interrupt Enable */
+#define ADC12IE11 (0x0800) /* ADC12 Memory 11 Interrupt Enable */
+#define ADC12IE12 (0x1000) /* ADC12 Memory 12 Interrupt Enable */
+#define ADC12IE13 (0x2000) /* ADC12 Memory 13 Interrupt Enable */
+#define ADC12IE14 (0x4000) /* ADC12 Memory 14 Interrupt Enable */
+#define ADC12IE15 (0x8000) /* ADC12 Memory 15 Interrupt Enable */
+
+/* ADC12IER0 Control Bits */
+#define ADC12IE0_L (0x0001) /* ADC12 Memory 0 Interrupt Enable */
+#define ADC12IE1_L (0x0002) /* ADC12 Memory 1 Interrupt Enable */
+#define ADC12IE2_L (0x0004) /* ADC12 Memory 2 Interrupt Enable */
+#define ADC12IE3_L (0x0008) /* ADC12 Memory 3 Interrupt Enable */
+#define ADC12IE4_L (0x0010) /* ADC12 Memory 4 Interrupt Enable */
+#define ADC12IE5_L (0x0020) /* ADC12 Memory 5 Interrupt Enable */
+#define ADC12IE6_L (0x0040) /* ADC12 Memory 6 Interrupt Enable */
+#define ADC12IE7_L (0x0080) /* ADC12 Memory 7 Interrupt Enable */
+
+/* ADC12IER0 Control Bits */
+#define ADC12IE8_H (0x0001) /* ADC12 Memory 8 Interrupt Enable */
+#define ADC12IE9_H (0x0002) /* ADC12 Memory 9 Interrupt Enable */
+#define ADC12IE10_H (0x0004) /* ADC12 Memory 10 Interrupt Enable */
+#define ADC12IE11_H (0x0008) /* ADC12 Memory 11 Interrupt Enable */
+#define ADC12IE12_H (0x0010) /* ADC12 Memory 12 Interrupt Enable */
+#define ADC12IE13_H (0x0020) /* ADC12 Memory 13 Interrupt Enable */
+#define ADC12IE14_H (0x0040) /* ADC12 Memory 14 Interrupt Enable */
+#define ADC12IE15_H (0x0080) /* ADC12 Memory 15 Interrupt Enable */
+
+/* ADC12IER1 Control Bits */
+#define ADC12IE16 (0x0001) /* ADC12 Memory 16 Interrupt Enable */
+#define ADC12IE17 (0x0002) /* ADC12 Memory 17 Interrupt Enable */
+#define ADC12IE18 (0x0004) /* ADC12 Memory 18 Interrupt Enable */
+#define ADC12IE19 (0x0008) /* ADC12 Memory 19 Interrupt Enable */
+#define ADC12IE20 (0x0010) /* ADC12 Memory 20 Interrupt Enable */
+#define ADC12IE21 (0x0020) /* ADC12 Memory 21 Interrupt Enable */
+#define ADC12IE22 (0x0040) /* ADC12 Memory 22 Interrupt Enable */
+#define ADC12IE23 (0x0080) /* ADC12 Memory 23 Interrupt Enable */
+#define ADC12IE24 (0x0100) /* ADC12 Memory 24 Interrupt Enable */
+#define ADC12IE25 (0x0200) /* ADC12 Memory 25 Interrupt Enable */
+#define ADC12IE26 (0x0400) /* ADC12 Memory 26 Interrupt Enable */
+#define ADC12IE27 (0x0800) /* ADC12 Memory 27 Interrupt Enable */
+#define ADC12IE28 (0x1000) /* ADC12 Memory 28 Interrupt Enable */
+#define ADC12IE29 (0x2000) /* ADC12 Memory 29 Interrupt Enable */
+#define ADC12IE30 (0x4000) /* ADC12 Memory 30 Interrupt Enable */
+#define ADC12IE31 (0x8000) /* ADC12 Memory 31 Interrupt Enable */
+
+/* ADC12IER1 Control Bits */
+#define ADC12IE16_L (0x0001) /* ADC12 Memory 16 Interrupt Enable */
+#define ADC12IE17_L (0x0002) /* ADC12 Memory 17 Interrupt Enable */
+#define ADC12IE18_L (0x0004) /* ADC12 Memory 18 Interrupt Enable */
+#define ADC12IE19_L (0x0008) /* ADC12 Memory 19 Interrupt Enable */
+#define ADC12IE20_L (0x0010) /* ADC12 Memory 20 Interrupt Enable */
+#define ADC12IE21_L (0x0020) /* ADC12 Memory 21 Interrupt Enable */
+#define ADC12IE22_L (0x0040) /* ADC12 Memory 22 Interrupt Enable */
+#define ADC12IE23_L (0x0080) /* ADC12 Memory 23 Interrupt Enable */
+
+/* ADC12IER1 Control Bits */
+#define ADC12IE24_H (0x0001) /* ADC12 Memory 24 Interrupt Enable */
+#define ADC12IE25_H (0x0002) /* ADC12 Memory 25 Interrupt Enable */
+#define ADC12IE26_H (0x0004) /* ADC12 Memory 26 Interrupt Enable */
+#define ADC12IE27_H (0x0008) /* ADC12 Memory 27 Interrupt Enable */
+#define ADC12IE28_H (0x0010) /* ADC12 Memory 28 Interrupt Enable */
+#define ADC12IE29_H (0x0020) /* ADC12 Memory 29 Interrupt Enable */
+#define ADC12IE30_H (0x0040) /* ADC12 Memory 30 Interrupt Enable */
+#define ADC12IE31_H (0x0080) /* ADC12 Memory 31 Interrupt Enable */
+
+/* ADC12IER2 Control Bits */
+#define ADC12INIE (0x0002) /* ADC12 Interrupt enable for the inside of window of the Window comparator */
+#define ADC12LOIE (0x0004) /* ADC12 Interrupt enable for lower threshold of the Window comparator */
+#define ADC12HIIE (0x0008) /* ADC12 Interrupt enable for upper threshold of the Window comparator */
+#define ADC12OVIE (0x0010) /* ADC12 ADC12MEMx Overflow interrupt enable */
+#define ADC12TOVIE (0x0020) /* ADC12 Timer Overflow interrupt enable */
+#define ADC12RDYIE (0x0040) /* ADC12 local buffered reference ready interrupt enable */
+
+/* ADC12IER2 Control Bits */
+#define ADC12INIE_L (0x0002) /* ADC12 Interrupt enable for the inside of window of the Window comparator */
+#define ADC12LOIE_L (0x0004) /* ADC12 Interrupt enable for lower threshold of the Window comparator */
+#define ADC12HIIE_L (0x0008) /* ADC12 Interrupt enable for upper threshold of the Window comparator */
+#define ADC12OVIE_L (0x0010) /* ADC12 ADC12MEMx Overflow interrupt enable */
+#define ADC12TOVIE_L (0x0020) /* ADC12 Timer Overflow interrupt enable */
+#define ADC12RDYIE_L (0x0040) /* ADC12 local buffered reference ready interrupt enable */
+
+/* ADC12IFGR0 Control Bits */
+#define ADC12IFG0 (0x0001) /* ADC12 Memory 0 Interrupt Flag */
+#define ADC12IFG1 (0x0002) /* ADC12 Memory 1 Interrupt Flag */
+#define ADC12IFG2 (0x0004) /* ADC12 Memory 2 Interrupt Flag */
+#define ADC12IFG3 (0x0008) /* ADC12 Memory 3 Interrupt Flag */
+#define ADC12IFG4 (0x0010) /* ADC12 Memory 4 Interrupt Flag */
+#define ADC12IFG5 (0x0020) /* ADC12 Memory 5 Interrupt Flag */
+#define ADC12IFG6 (0x0040) /* ADC12 Memory 6 Interrupt Flag */
+#define ADC12IFG7 (0x0080) /* ADC12 Memory 7 Interrupt Flag */
+#define ADC12IFG8 (0x0100) /* ADC12 Memory 8 Interrupt Flag */
+#define ADC12IFG9 (0x0200) /* ADC12 Memory 9 Interrupt Flag */
+#define ADC12IFG10 (0x0400) /* ADC12 Memory 10 Interrupt Flag */
+#define ADC12IFG11 (0x0800) /* ADC12 Memory 11 Interrupt Flag */
+#define ADC12IFG12 (0x1000) /* ADC12 Memory 12 Interrupt Flag */
+#define ADC12IFG13 (0x2000) /* ADC12 Memory 13 Interrupt Flag */
+#define ADC12IFG14 (0x4000) /* ADC12 Memory 14 Interrupt Flag */
+#define ADC12IFG15 (0x8000) /* ADC12 Memory 15 Interrupt Flag */
+
+/* ADC12IFGR0 Control Bits */
+#define ADC12IFG0_L (0x0001) /* ADC12 Memory 0 Interrupt Flag */
+#define ADC12IFG1_L (0x0002) /* ADC12 Memory 1 Interrupt Flag */
+#define ADC12IFG2_L (0x0004) /* ADC12 Memory 2 Interrupt Flag */
+#define ADC12IFG3_L (0x0008) /* ADC12 Memory 3 Interrupt Flag */
+#define ADC12IFG4_L (0x0010) /* ADC12 Memory 4 Interrupt Flag */
+#define ADC12IFG5_L (0x0020) /* ADC12 Memory 5 Interrupt Flag */
+#define ADC12IFG6_L (0x0040) /* ADC12 Memory 6 Interrupt Flag */
+#define ADC12IFG7_L (0x0080) /* ADC12 Memory 7 Interrupt Flag */
+
+/* ADC12IFGR0 Control Bits */
+#define ADC12IFG8_H (0x0001) /* ADC12 Memory 8 Interrupt Flag */
+#define ADC12IFG9_H (0x0002) /* ADC12 Memory 9 Interrupt Flag */
+#define ADC12IFG10_H (0x0004) /* ADC12 Memory 10 Interrupt Flag */
+#define ADC12IFG11_H (0x0008) /* ADC12 Memory 11 Interrupt Flag */
+#define ADC12IFG12_H (0x0010) /* ADC12 Memory 12 Interrupt Flag */
+#define ADC12IFG13_H (0x0020) /* ADC12 Memory 13 Interrupt Flag */
+#define ADC12IFG14_H (0x0040) /* ADC12 Memory 14 Interrupt Flag */
+#define ADC12IFG15_H (0x0080) /* ADC12 Memory 15 Interrupt Flag */
+
+/* ADC12IFGR1 Control Bits */
+#define ADC12IFG16 (0x0001) /* ADC12 Memory 16 Interrupt Flag */
+#define ADC12IFG17 (0x0002) /* ADC12 Memory 17 Interrupt Flag */
+#define ADC12IFG18 (0x0004) /* ADC12 Memory 18 Interrupt Flag */
+#define ADC12IFG19 (0x0008) /* ADC12 Memory 19 Interrupt Flag */
+#define ADC12IFG20 (0x0010) /* ADC12 Memory 20 Interrupt Flag */
+#define ADC12IFG21 (0x0020) /* ADC12 Memory 21 Interrupt Flag */
+#define ADC12IFG22 (0x0040) /* ADC12 Memory 22 Interrupt Flag */
+#define ADC12IFG23 (0x0080) /* ADC12 Memory 23 Interrupt Flag */
+#define ADC12IFG24 (0x0100) /* ADC12 Memory 24 Interrupt Flag */
+#define ADC12IFG25 (0x0200) /* ADC12 Memory 25 Interrupt Flag */
+#define ADC12IFG26 (0x0400) /* ADC12 Memory 26 Interrupt Flag */
+#define ADC12IFG27 (0x0800) /* ADC12 Memory 27 Interrupt Flag */
+#define ADC12IFG28 (0x1000) /* ADC12 Memory 28 Interrupt Flag */
+#define ADC12IFG29 (0x2000) /* ADC12 Memory 29 Interrupt Flag */
+#define ADC12IFG30 (0x4000) /* ADC12 Memory 30 Interrupt Flag */
+#define ADC12IFG31 (0x8000) /* ADC12 Memory 31 Interrupt Flag */
+
+/* ADC12IFGR1 Control Bits */
+#define ADC12IFG16_L (0x0001) /* ADC12 Memory 16 Interrupt Flag */
+#define ADC12IFG17_L (0x0002) /* ADC12 Memory 17 Interrupt Flag */
+#define ADC12IFG18_L (0x0004) /* ADC12 Memory 18 Interrupt Flag */
+#define ADC12IFG19_L (0x0008) /* ADC12 Memory 19 Interrupt Flag */
+#define ADC12IFG20_L (0x0010) /* ADC12 Memory 20 Interrupt Flag */
+#define ADC12IFG21_L (0x0020) /* ADC12 Memory 21 Interrupt Flag */
+#define ADC12IFG22_L (0x0040) /* ADC12 Memory 22 Interrupt Flag */
+#define ADC12IFG23_L (0x0080) /* ADC12 Memory 23 Interrupt Flag */
+
+/* ADC12IFGR1 Control Bits */
+#define ADC12IFG24_H (0x0001) /* ADC12 Memory 24 Interrupt Flag */
+#define ADC12IFG25_H (0x0002) /* ADC12 Memory 25 Interrupt Flag */
+#define ADC12IFG26_H (0x0004) /* ADC12 Memory 26 Interrupt Flag */
+#define ADC12IFG27_H (0x0008) /* ADC12 Memory 27 Interrupt Flag */
+#define ADC12IFG28_H (0x0010) /* ADC12 Memory 28 Interrupt Flag */
+#define ADC12IFG29_H (0x0020) /* ADC12 Memory 29 Interrupt Flag */
+#define ADC12IFG30_H (0x0040) /* ADC12 Memory 30 Interrupt Flag */
+#define ADC12IFG31_H (0x0080) /* ADC12 Memory 31 Interrupt Flag */
+
+/* ADC12IFGR2 Control Bits */
+#define ADC12INIFG (0x0002) /* ADC12 Interrupt Flag for the inside of window of the Window comparator */
+#define ADC12LOIFG (0x0004) /* ADC12 Interrupt Flag for lower threshold of the Window comparator */
+#define ADC12HIIFG (0x0008) /* ADC12 Interrupt Flag for upper threshold of the Window comparator */
+#define ADC12OVIFG (0x0010) /* ADC12 ADC12MEMx Overflow interrupt Flag */
+#define ADC12TOVIFG (0x0020) /* ADC12 Timer Overflow interrupt Flag */
+#define ADC12RDYIFG (0x0040) /* ADC12 local buffered reference ready interrupt Flag */
+
+/* ADC12IFGR2 Control Bits */
+#define ADC12INIFG_L (0x0002) /* ADC12 Interrupt Flag for the inside of window of the Window comparator */
+#define ADC12LOIFG_L (0x0004) /* ADC12 Interrupt Flag for lower threshold of the Window comparator */
+#define ADC12HIIFG_L (0x0008) /* ADC12 Interrupt Flag for upper threshold of the Window comparator */
+#define ADC12OVIFG_L (0x0010) /* ADC12 ADC12MEMx Overflow interrupt Flag */
+#define ADC12TOVIFG_L (0x0020) /* ADC12 Timer Overflow interrupt Flag */
+#define ADC12RDYIFG_L (0x0040) /* ADC12 local buffered reference ready interrupt Flag */
+
+/* ADC12IV Definitions */
+#define ADC12IV_NONE (0x0000) /* No Interrupt pending */
+#define ADC12IV_ADC12OVIFG (0x0002) /* ADC12OVIFG */
+#define ADC12IV_ADC12TOVIFG (0x0004) /* ADC12TOVIFG */
+#define ADC12IV_ADC12HIIFG (0x0006) /* ADC12HIIFG */
+#define ADC12IV_ADC12LOIFG (0x0008) /* ADC12LOIFG */
+#define ADC12IV_ADC12INIFG (0x000A) /* ADC12INIFG */
+#define ADC12IV_ADC12IFG0 (0x000C) /* ADC12IFG0 */
+#define ADC12IV_ADC12IFG1 (0x000E) /* ADC12IFG1 */
+#define ADC12IV_ADC12IFG2 (0x0010) /* ADC12IFG2 */
+#define ADC12IV_ADC12IFG3 (0x0012) /* ADC12IFG3 */
+#define ADC12IV_ADC12IFG4 (0x0014) /* ADC12IFG4 */
+#define ADC12IV_ADC12IFG5 (0x0016) /* ADC12IFG5 */
+#define ADC12IV_ADC12IFG6 (0x0018) /* ADC12IFG6 */
+#define ADC12IV_ADC12IFG7 (0x001A) /* ADC12IFG7 */
+#define ADC12IV_ADC12IFG8 (0x001C) /* ADC12IFG8 */
+#define ADC12IV_ADC12IFG9 (0x001E) /* ADC12IFG9 */
+#define ADC12IV_ADC12IFG10 (0x0020) /* ADC12IFG10 */
+#define ADC12IV_ADC12IFG11 (0x0022) /* ADC12IFG11 */
+#define ADC12IV_ADC12IFG12 (0x0024) /* ADC12IFG12 */
+#define ADC12IV_ADC12IFG13 (0x0026) /* ADC12IFG13 */
+#define ADC12IV_ADC12IFG14 (0x0028) /* ADC12IFG14 */
+#define ADC12IV_ADC12IFG15 (0x002A) /* ADC12IFG15 */
+#define ADC12IV_ADC12IFG16 (0x002C) /* ADC12IFG16 */
+#define ADC12IV_ADC12IFG17 (0x002E) /* ADC12IFG17 */
+#define ADC12IV_ADC12IFG18 (0x0030) /* ADC12IFG18 */
+#define ADC12IV_ADC12IFG19 (0x0032) /* ADC12IFG19 */
+#define ADC12IV_ADC12IFG20 (0x0034) /* ADC12IFG20 */
+#define ADC12IV_ADC12IFG21 (0x0036) /* ADC12IFG21 */
+#define ADC12IV_ADC12IFG22 (0x0038) /* ADC12IFG22 */
+#define ADC12IV_ADC12IFG23 (0x003A) /* ADC12IFG23 */
+#define ADC12IV_ADC12IFG24 (0x003C) /* ADC12IFG24 */
+#define ADC12IV_ADC12IFG25 (0x003E) /* ADC12IFG25 */
+#define ADC12IV_ADC12IFG26 (0x0040) /* ADC12IFG26 */
+#define ADC12IV_ADC12IFG27 (0x0042) /* ADC12IFG27 */
+#define ADC12IV_ADC12IFG28 (0x0044) /* ADC12IFG28 */
+#define ADC12IV_ADC12IFG29 (0x0046) /* ADC12IFG29 */
+#define ADC12IV_ADC12IFG30 (0x0048) /* ADC12IFG30 */
+#define ADC12IV_ADC12IFG31 (0x004A) /* ADC12IFG31 */
+#define ADC12IV_ADC12RDYIFG (0x004C) /* ADC12RDYIFG */
+
+
+/************************************************************
+* AES256 Accelerator
+************************************************************/
+#define __MSP430_HAS_AES256__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_AES256__ 0x09C0
+#define AES256_BASE __MSP430_BASEADDRESS_AES256__
+
+sfr_w(AESACTL0); /* AES accelerator control register 0 */
+sfr_b(AESACTL0_L); /* AES accelerator control register 0 */
+sfr_b(AESACTL0_H); /* AES accelerator control register 0 */
+sfr_w(AESACTL1); /* AES accelerator control register 1 */
+sfr_b(AESACTL1_L); /* AES accelerator control register 1 */
+sfr_b(AESACTL1_H); /* AES accelerator control register 1 */
+sfr_w(AESASTAT); /* AES accelerator status register */
+sfr_b(AESASTAT_L); /* AES accelerator status register */
+sfr_b(AESASTAT_H); /* AES accelerator status register */
+sfr_w(AESAKEY); /* AES accelerator key register */
+sfr_b(AESAKEY_L); /* AES accelerator key register */
+sfr_b(AESAKEY_H); /* AES accelerator key register */
+sfr_w(AESADIN); /* AES accelerator data in register */
+sfr_b(AESADIN_L); /* AES accelerator data in register */
+sfr_b(AESADIN_H); /* AES accelerator data in register */
+sfr_w(AESADOUT); /* AES accelerator data out register */
+sfr_b(AESADOUT_L); /* AES accelerator data out register */
+sfr_b(AESADOUT_H); /* AES accelerator data out register */
+sfr_w(AESAXDIN); /* AES accelerator XORed data in register */
+sfr_b(AESAXDIN_L); /* AES accelerator XORed data in register */
+sfr_b(AESAXDIN_H); /* AES accelerator XORed data in register */
+sfr_w(AESAXIN); /* AES accelerator XORed data in register (no trigger) */
+sfr_b(AESAXIN_L); /* AES accelerator XORed data in register (no trigger) */
+sfr_b(AESAXIN_H); /* AES accelerator XORed data in register (no trigger) */
+
+/* AESACTL0 Control Bits */
+#define AESOP0 (0x0001) /* AES Operation Bit: 0 */
+#define AESOP1 (0x0002) /* AES Operation Bit: 1 */
+#define AESKL0 (0x0004) /* AES Key length Bit: 0 */
+#define AESKL1 (0x0008) /* AES Key length Bit: 1 */
+#define AESTRIG (0x0010) /* AES Trigger Select */
+#define AESCM0 (0x0020) /* AES Cipher mode select Bit: 0 */
+#define AESCM1 (0x0040) /* AES Cipher mode select Bit: 1 */
+#define AESSWRST (0x0080) /* AES Software Reset */
+#define AESRDYIFG (0x0100) /* AES ready interrupt flag */
+#define AESERRFG (0x0800) /* AES Error Flag */
+#define AESRDYIE (0x1000) /* AES ready interrupt enable*/
+#define AESCMEN (0x8000) /* AES DMA cipher mode enable*/
+
+/* AESACTL0 Control Bits */
+#define AESOP0_L (0x0001) /* AES Operation Bit: 0 */
+#define AESOP1_L (0x0002) /* AES Operation Bit: 1 */
+#define AESKL0_L (0x0004) /* AES Key length Bit: 0 */
+#define AESKL1_L (0x0008) /* AES Key length Bit: 1 */
+#define AESTRIG_L (0x0010) /* AES Trigger Select */
+#define AESCM0_L (0x0020) /* AES Cipher mode select Bit: 0 */
+#define AESCM1_L (0x0040) /* AES Cipher mode select Bit: 1 */
+#define AESSWRST_L (0x0080) /* AES Software Reset */
+
+/* AESACTL0 Control Bits */
+#define AESRDYIFG_H (0x0001) /* AES ready interrupt flag */
+#define AESERRFG_H (0x0008) /* AES Error Flag */
+#define AESRDYIE_H (0x0010) /* AES ready interrupt enable*/
+#define AESCMEN_H (0x0080) /* AES DMA cipher mode enable*/
+
+#define AESOP_0 (0x0000) /* AES Operation: Encrypt */
+#define AESOP_1 (0x0001) /* AES Operation: Decrypt (same Key) */
+#define AESOP_2 (0x0002) /* AES Operation: Generate first round Key */
+#define AESOP_3 (0x0003) /* AES Operation: Decrypt (first round Key) */
+
+#define AESKL_0 (0x0000) /* AES Key length: AES128 */
+#define AESKL_1 (0x0004) /* AES Key length: AES192 */
+#define AESKL_2 (0x0008) /* AES Key length: AES256 */
+#define AESKL__128 (0x0000) /* AES Key length: AES128 */
+#define AESKL__192 (0x0004) /* AES Key length: AES192 */
+#define AESKL__256 (0x0008) /* AES Key length: AES256 */
+
+#define AESCM_0 (0x0000) /* AES Cipher mode select: ECB */
+#define AESCM_1 (0x0020) /* AES Cipher mode select: CBC */
+#define AESCM_2 (0x0040) /* AES Cipher mode select: OFB */
+#define AESCM_3 (0x0060) /* AES Cipher mode select: CFB */
+#define AESCM__ECB (0x0000) /* AES Cipher mode select: ECB */
+#define AESCM__CBC (0x0020) /* AES Cipher mode select: CBC */
+#define AESCM__OFB (0x0040) /* AES Cipher mode select: OFB */
+#define AESCM__CFB (0x0060) /* AES Cipher mode select: CFB */
+
+/* AESACTL1 Control Bits */
+#define AESBLKCNT0 (0x0001) /* AES Cipher Block Counter Bit: 0 */
+#define AESBLKCNT1 (0x0002) /* AES Cipher Block Counter Bit: 1 */
+#define AESBLKCNT2 (0x0004) /* AES Cipher Block Counter Bit: 2 */
+#define AESBLKCNT3 (0x0008) /* AES Cipher Block Counter Bit: 3 */
+#define AESBLKCNT4 (0x0010) /* AES Cipher Block Counter Bit: 4 */
+#define AESBLKCNT5 (0x0020) /* AES Cipher Block Counter Bit: 5 */
+#define AESBLKCNT6 (0x0040) /* AES Cipher Block Counter Bit: 6 */
+#define AESBLKCNT7 (0x0080) /* AES Cipher Block Counter Bit: 7 */
+
+/* AESACTL1 Control Bits */
+#define AESBLKCNT0_L (0x0001) /* AES Cipher Block Counter Bit: 0 */
+#define AESBLKCNT1_L (0x0002) /* AES Cipher Block Counter Bit: 1 */
+#define AESBLKCNT2_L (0x0004) /* AES Cipher Block Counter Bit: 2 */
+#define AESBLKCNT3_L (0x0008) /* AES Cipher Block Counter Bit: 3 */
+#define AESBLKCNT4_L (0x0010) /* AES Cipher Block Counter Bit: 4 */
+#define AESBLKCNT5_L (0x0020) /* AES Cipher Block Counter Bit: 5 */
+#define AESBLKCNT6_L (0x0040) /* AES Cipher Block Counter Bit: 6 */
+#define AESBLKCNT7_L (0x0080) /* AES Cipher Block Counter Bit: 7 */
+
+/* AESASTAT Control Bits */
+#define AESBUSY (0x0001) /* AES Busy */
+#define AESKEYWR (0x0002) /* AES All 16 bytes written to AESAKEY */
+#define AESDINWR (0x0004) /* AES All 16 bytes written to AESADIN */
+#define AESDOUTRD (0x0008) /* AES All 16 bytes read from AESADOUT */
+#define AESKEYCNT0 (0x0010) /* AES Bytes written via AESAKEY Bit: 0 */
+#define AESKEYCNT1 (0x0020) /* AES Bytes written via AESAKEY Bit: 1 */
+#define AESKEYCNT2 (0x0040) /* AES Bytes written via AESAKEY Bit: 2 */
+#define AESKEYCNT3 (0x0080) /* AES Bytes written via AESAKEY Bit: 3 */
+#define AESDINCNT0 (0x0100) /* AES Bytes written via AESADIN Bit: 0 */
+#define AESDINCNT1 (0x0200) /* AES Bytes written via AESADIN Bit: 1 */
+#define AESDINCNT2 (0x0400) /* AES Bytes written via AESADIN Bit: 2 */
+#define AESDINCNT3 (0x0800) /* AES Bytes written via AESADIN Bit: 3 */
+#define AESDOUTCNT0 (0x1000) /* AES Bytes read via AESADOUT Bit: 0 */
+#define AESDOUTCNT1 (0x2000) /* AES Bytes read via AESADOUT Bit: 1 */
+#define AESDOUTCNT2 (0x4000) /* AES Bytes read via AESADOUT Bit: 2 */
+#define AESDOUTCNT3 (0x8000) /* AES Bytes read via AESADOUT Bit: 3 */
+
+/* AESASTAT Control Bits */
+#define AESBUSY_L (0x0001) /* AES Busy */
+#define AESKEYWR_L (0x0002) /* AES All 16 bytes written to AESAKEY */
+#define AESDINWR_L (0x0004) /* AES All 16 bytes written to AESADIN */
+#define AESDOUTRD_L (0x0008) /* AES All 16 bytes read from AESADOUT */
+#define AESKEYCNT0_L (0x0010) /* AES Bytes written via AESAKEY Bit: 0 */
+#define AESKEYCNT1_L (0x0020) /* AES Bytes written via AESAKEY Bit: 1 */
+#define AESKEYCNT2_L (0x0040) /* AES Bytes written via AESAKEY Bit: 2 */
+#define AESKEYCNT3_L (0x0080) /* AES Bytes written via AESAKEY Bit: 3 */
+
+/* AESASTAT Control Bits */
+#define AESDINCNT0_H (0x0001) /* AES Bytes written via AESADIN Bit: 0 */
+#define AESDINCNT1_H (0x0002) /* AES Bytes written via AESADIN Bit: 1 */
+#define AESDINCNT2_H (0x0004) /* AES Bytes written via AESADIN Bit: 2 */
+#define AESDINCNT3_H (0x0008) /* AES Bytes written via AESADIN Bit: 3 */
+#define AESDOUTCNT0_H (0x0010) /* AES Bytes read via AESADOUT Bit: 0 */
+#define AESDOUTCNT1_H (0x0020) /* AES Bytes read via AESADOUT Bit: 1 */
+#define AESDOUTCNT2_H (0x0040) /* AES Bytes read via AESADOUT Bit: 2 */
+#define AESDOUTCNT3_H (0x0080) /* AES Bytes read via AESADOUT Bit: 3 */
+
+/************************************************************
+* Capacitive_Touch_IO 0
+************************************************************/
+#define __MSP430_HAS_CAP_TOUCH_IO_0__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_CAP_TOUCH_IO_0__ 0x0430
+#define CAP_TOUCH_0_BASE __MSP430_BASEADDRESS_CAP_TOUCH_IO_0__
+
+sfr_w(CAPTIO0CTL); /* Capacitive_Touch_IO 0 control register */
+sfr_b(CAPTIO0CTL_L); /* Capacitive_Touch_IO 0 control register */
+sfr_b(CAPTIO0CTL_H); /* Capacitive_Touch_IO 0 control register */
+
+#define CAPSIO0CTL CAPTIO0CTL /* legacy define */
+
+/************************************************************
+* Capacitive_Touch_IO 1
+************************************************************/
+#define __MSP430_HAS_CAP_TOUCH_IO_1__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_CAP_TOUCH_IO_1__ 0x0470
+#define CAP_TOUCH_1_BASE __MSP430_BASEADDRESS_CAP_TOUCH_IO_1__
+
+sfr_w(CAPTIO1CTL); /* Capacitive_Touch_IO 1 control register */
+sfr_b(CAPTIO1CTL_L); /* Capacitive_Touch_IO 1 control register */
+sfr_b(CAPTIO1CTL_H); /* Capacitive_Touch_IO 1 control register */
+
+#define CAPSIO1CTL CAPTIO1CTL /* legacy define */
+
+/* CAPTIOxCTL Control Bits */
+#define CAPTIOPISEL0 (0x0002) /* CapTouchIO Pin Select Bit: 0 */
+#define CAPTIOPISEL1 (0x0004) /* CapTouchIO Pin Select Bit: 1 */
+#define CAPTIOPISEL2 (0x0008) /* CapTouchIO Pin Select Bit: 2 */
+#define CAPTIOPOSEL0 (0x0010) /* CapTouchIO Port Select Bit: 0 */
+#define CAPTIOPOSEL1 (0x0020) /* CapTouchIO Port Select Bit: 1 */
+#define CAPTIOPOSEL2 (0x0040) /* CapTouchIO Port Select Bit: 2 */
+#define CAPTIOPOSEL3 (0x0080) /* CapTouchIO Port Select Bit: 3 */
+#define CAPTIOEN (0x0100) /* CapTouchIO Enable */
+#define CAPTIO (0x0200) /* CapTouchIO state */
+
+/* CAPTIOxCTL Control Bits */
+#define CAPTIOPISEL0_L (0x0002) /* CapTouchIO Pin Select Bit: 0 */
+#define CAPTIOPISEL1_L (0x0004) /* CapTouchIO Pin Select Bit: 1 */
+#define CAPTIOPISEL2_L (0x0008) /* CapTouchIO Pin Select Bit: 2 */
+#define CAPTIOPOSEL0_L (0x0010) /* CapTouchIO Port Select Bit: 0 */
+#define CAPTIOPOSEL1_L (0x0020) /* CapTouchIO Port Select Bit: 1 */
+#define CAPTIOPOSEL2_L (0x0040) /* CapTouchIO Port Select Bit: 2 */
+#define CAPTIOPOSEL3_L (0x0080) /* CapTouchIO Port Select Bit: 3 */
+
+/* CAPTIOxCTL Control Bits */
+#define CAPTIOEN_H (0x0001) /* CapTouchIO Enable */
+#define CAPTIO_H (0x0002) /* CapTouchIO state */
+
+/* Legacy defines */
+#define CAPSIOPISEL0 (0x0002) /* CapTouchIO Pin Select Bit: 0 */
+#define CAPSIOPISEL1 (0x0004) /* CapTouchIO Pin Select Bit: 1 */
+#define CAPSIOPISEL2 (0x0008) /* CapTouchIO Pin Select Bit: 2 */
+#define CAPSIOPOSEL0 (0x0010) /* CapTouchIO Port Select Bit: 0 */
+#define CAPSIOPOSEL1 (0x0020) /* CapTouchIO Port Select Bit: 1 */
+#define CAPSIOPOSEL2 (0x0040) /* CapTouchIO Port Select Bit: 2 */
+#define CAPSIOPOSEL3 (0x0080) /* CapTouchIO Port Select Bit: 3 */
+#define CAPSIOEN (0x0100) /* CapTouchIO Enable */
+#define CAPSIO (0x0200) /* CapTouchIO state */
+
+/************************************************************
+* Comparator E
+************************************************************/
+#define __MSP430_HAS_COMP_E__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_COMP_E__ 0x08C0
+#define COMP_E_BASE __MSP430_BASEADDRESS_COMP_E__
+
+sfr_w(CECTL0); /* Comparator E Control Register 0 */
+sfr_b(CECTL0_L); /* Comparator E Control Register 0 */
+sfr_b(CECTL0_H); /* Comparator E Control Register 0 */
+sfr_w(CECTL1); /* Comparator E Control Register 1 */
+sfr_b(CECTL1_L); /* Comparator E Control Register 1 */
+sfr_b(CECTL1_H); /* Comparator E Control Register 1 */
+sfr_w(CECTL2); /* Comparator E Control Register 2 */
+sfr_b(CECTL2_L); /* Comparator E Control Register 2 */
+sfr_b(CECTL2_H); /* Comparator E Control Register 2 */
+sfr_w(CECTL3); /* Comparator E Control Register 3 */
+sfr_b(CECTL3_L); /* Comparator E Control Register 3 */
+sfr_b(CECTL3_H); /* Comparator E Control Register 3 */
+sfr_w(CEINT); /* Comparator E Interrupt Register */
+sfr_b(CEINT_L); /* Comparator E Interrupt Register */
+sfr_b(CEINT_H); /* Comparator E Interrupt Register */
+sfr_w(CEIV); /* Comparator E Interrupt Vector Word */
+sfr_b(CEIV_L); /* Comparator E Interrupt Vector Word */
+sfr_b(CEIV_H); /* Comparator E Interrupt Vector Word */
+
+/* CECTL0 Control Bits */
+#define CEIPSEL0 (0x0001) /* Comp. E Pos. Channel Input Select 0 */
+#define CEIPSEL1 (0x0002) /* Comp. E Pos. Channel Input Select 1 */
+#define CEIPSEL2 (0x0004) /* Comp. E Pos. Channel Input Select 2 */
+#define CEIPSEL3 (0x0008) /* Comp. E Pos. Channel Input Select 3 */
+//#define RESERVED (0x0010) /* Comp. E */
+//#define RESERVED (0x0020) /* Comp. E */
+//#define RESERVED (0x0040) /* Comp. E */
+#define CEIPEN (0x0080) /* Comp. E Pos. Channel Input Enable */
+#define CEIMSEL0 (0x0100) /* Comp. E Neg. Channel Input Select 0 */
+#define CEIMSEL1 (0x0200) /* Comp. E Neg. Channel Input Select 1 */
+#define CEIMSEL2 (0x0400) /* Comp. E Neg. Channel Input Select 2 */
+#define CEIMSEL3 (0x0800) /* Comp. E Neg. Channel Input Select 3 */
+//#define RESERVED (0x1000) /* Comp. E */
+//#define RESERVED (0x2000) /* Comp. E */
+//#define RESERVED (0x4000) /* Comp. E */
+#define CEIMEN (0x8000) /* Comp. E Neg. Channel Input Enable */
+
+/* CECTL0 Control Bits */
+#define CEIPSEL0_L (0x0001) /* Comp. E Pos. Channel Input Select 0 */
+#define CEIPSEL1_L (0x0002) /* Comp. E Pos. Channel Input Select 1 */
+#define CEIPSEL2_L (0x0004) /* Comp. E Pos. Channel Input Select 2 */
+#define CEIPSEL3_L (0x0008) /* Comp. E Pos. Channel Input Select 3 */
+//#define RESERVED (0x0010) /* Comp. E */
+//#define RESERVED (0x0020) /* Comp. E */
+//#define RESERVED (0x0040) /* Comp. E */
+#define CEIPEN_L (0x0080) /* Comp. E Pos. Channel Input Enable */
+//#define RESERVED (0x1000) /* Comp. E */
+//#define RESERVED (0x2000) /* Comp. E */
+//#define RESERVED (0x4000) /* Comp. E */
+
+/* CECTL0 Control Bits */
+//#define RESERVED (0x0010) /* Comp. E */
+//#define RESERVED (0x0020) /* Comp. E */
+//#define RESERVED (0x0040) /* Comp. E */
+#define CEIMSEL0_H (0x0001) /* Comp. E Neg. Channel Input Select 0 */
+#define CEIMSEL1_H (0x0002) /* Comp. E Neg. Channel Input Select 1 */
+#define CEIMSEL2_H (0x0004) /* Comp. E Neg. Channel Input Select 2 */
+#define CEIMSEL3_H (0x0008) /* Comp. E Neg. Channel Input Select 3 */
+//#define RESERVED (0x1000) /* Comp. E */
+//#define RESERVED (0x2000) /* Comp. E */
+//#define RESERVED (0x4000) /* Comp. E */
+#define CEIMEN_H (0x0080) /* Comp. E Neg. Channel Input Enable */
+
+#define CEIPSEL_0 (0x0000) /* Comp. E V+ terminal Input Select: Channel 0 */
+#define CEIPSEL_1 (0x0001) /* Comp. E V+ terminal Input Select: Channel 1 */
+#define CEIPSEL_2 (0x0002) /* Comp. E V+ terminal Input Select: Channel 2 */
+#define CEIPSEL_3 (0x0003) /* Comp. E V+ terminal Input Select: Channel 3 */
+#define CEIPSEL_4 (0x0004) /* Comp. E V+ terminal Input Select: Channel 4 */
+#define CEIPSEL_5 (0x0005) /* Comp. E V+ terminal Input Select: Channel 5 */
+#define CEIPSEL_6 (0x0006) /* Comp. E V+ terminal Input Select: Channel 6 */
+#define CEIPSEL_7 (0x0007) /* Comp. E V+ terminal Input Select: Channel 7 */
+#define CEIPSEL_8 (0x0008) /* Comp. E V+ terminal Input Select: Channel 8 */
+#define CEIPSEL_9 (0x0009) /* Comp. E V+ terminal Input Select: Channel 9 */
+#define CEIPSEL_10 (0x000A) /* Comp. E V+ terminal Input Select: Channel 10 */
+#define CEIPSEL_11 (0x000B) /* Comp. E V+ terminal Input Select: Channel 11 */
+#define CEIPSEL_12 (0x000C) /* Comp. E V+ terminal Input Select: Channel 12 */
+#define CEIPSEL_13 (0x000D) /* Comp. E V+ terminal Input Select: Channel 13 */
+#define CEIPSEL_14 (0x000E) /* Comp. E V+ terminal Input Select: Channel 14 */
+#define CEIPSEL_15 (0x000F) /* Comp. E V+ terminal Input Select: Channel 15 */
+
+#define CEIMSEL_0 (0x0000) /* Comp. E V- Terminal Input Select: Channel 0 */
+#define CEIMSEL_1 (0x0100) /* Comp. E V- Terminal Input Select: Channel 1 */
+#define CEIMSEL_2 (0x0200) /* Comp. E V- Terminal Input Select: Channel 2 */
+#define CEIMSEL_3 (0x0300) /* Comp. E V- Terminal Input Select: Channel 3 */
+#define CEIMSEL_4 (0x0400) /* Comp. E V- Terminal Input Select: Channel 4 */
+#define CEIMSEL_5 (0x0500) /* Comp. E V- Terminal Input Select: Channel 5 */
+#define CEIMSEL_6 (0x0600) /* Comp. E V- Terminal Input Select: Channel 6 */
+#define CEIMSEL_7 (0x0700) /* Comp. E V- Terminal Input Select: Channel 7 */
+#define CEIMSEL_8 (0x0800) /* Comp. E V- terminal Input Select: Channel 8 */
+#define CEIMSEL_9 (0x0900) /* Comp. E V- terminal Input Select: Channel 9 */
+#define CEIMSEL_10 (0x0A00) /* Comp. E V- terminal Input Select: Channel 10 */
+#define CEIMSEL_11 (0x0B00) /* Comp. E V- terminal Input Select: Channel 11 */
+#define CEIMSEL_12 (0x0C00) /* Comp. E V- terminal Input Select: Channel 12 */
+#define CEIMSEL_13 (0x0D00) /* Comp. E V- terminal Input Select: Channel 13 */
+#define CEIMSEL_14 (0x0E00) /* Comp. E V- terminal Input Select: Channel 14 */
+#define CEIMSEL_15 (0x0F00) /* Comp. E V- terminal Input Select: Channel 15 */
+
+/* CECTL1 Control Bits */
+#define CEOUT (0x0001) /* Comp. E Output */
+#define CEOUTPOL (0x0002) /* Comp. E Output Polarity */
+#define CEF (0x0004) /* Comp. E Enable Output Filter */
+#define CEIES (0x0008) /* Comp. E Interrupt Edge Select */
+#define CESHORT (0x0010) /* Comp. E Input Short */
+#define CEEX (0x0020) /* Comp. E Exchange Inputs */
+#define CEFDLY0 (0x0040) /* Comp. E Filter delay Bit 0 */
+#define CEFDLY1 (0x0080) /* Comp. E Filter delay Bit 1 */
+#define CEPWRMD0 (0x0100) /* Comp. E Power mode Bit 0 */
+#define CEPWRMD1 (0x0200) /* Comp. E Power mode Bit 1 */
+#define CEON (0x0400) /* Comp. E enable */
+#define CEMRVL (0x0800) /* Comp. E CEMRV Level */
+#define CEMRVS (0x1000) /* Comp. E Output selects between VREF0 or VREF1*/
+//#define RESERVED (0x2000) /* Comp. E */
+//#define RESERVED (0x4000) /* Comp. E */
+//#define RESERVED (0x8000) /* Comp. E */
+
+/* CECTL1 Control Bits */
+#define CEOUT_L (0x0001) /* Comp. E Output */
+#define CEOUTPOL_L (0x0002) /* Comp. E Output Polarity */
+#define CEF_L (0x0004) /* Comp. E Enable Output Filter */
+#define CEIES_L (0x0008) /* Comp. E Interrupt Edge Select */
+#define CESHORT_L (0x0010) /* Comp. E Input Short */
+#define CEEX_L (0x0020) /* Comp. E Exchange Inputs */
+#define CEFDLY0_L (0x0040) /* Comp. E Filter delay Bit 0 */
+#define CEFDLY1_L (0x0080) /* Comp. E Filter delay Bit 1 */
+//#define RESERVED (0x2000) /* Comp. E */
+//#define RESERVED (0x4000) /* Comp. E */
+//#define RESERVED (0x8000) /* Comp. E */
+
+/* CECTL1 Control Bits */
+#define CEPWRMD0_H (0x0001) /* Comp. E Power mode Bit 0 */
+#define CEPWRMD1_H (0x0002) /* Comp. E Power mode Bit 1 */
+#define CEON_H (0x0004) /* Comp. E enable */
+#define CEMRVL_H (0x0008) /* Comp. E CEMRV Level */
+#define CEMRVS_H (0x0010) /* Comp. E Output selects between VREF0 or VREF1*/
+//#define RESERVED (0x2000) /* Comp. E */
+//#define RESERVED (0x4000) /* Comp. E */
+//#define RESERVED (0x8000) /* Comp. E */
+
+#define CEPWRMD_0 (0x0000) /* Comp. E Power mode 0 */
+#define CEPWRMD_1 (0x0100) /* Comp. E Power mode 1 */
+#define CEPWRMD_2 (0x0200) /* Comp. E Power mode 2 */
+#define CEPWRMD_3 (0x0300) /* Comp. E Power mode 3*/
+
+#define CEFDLY_0 (0x0000) /* Comp. E Filter delay 0 : 450ns */
+#define CEFDLY_1 (0x0040) /* Comp. E Filter delay 1 : 900ns */
+#define CEFDLY_2 (0x0080) /* Comp. E Filter delay 2 : 1800ns */
+#define CEFDLY_3 (0x00C0) /* Comp. E Filter delay 3 : 3600ns */
+
+/* CECTL2 Control Bits */
+#define CEREF00 (0x0001) /* Comp. E Reference 0 Resistor Select Bit : 0 */
+#define CEREF01 (0x0002) /* Comp. E Reference 0 Resistor Select Bit : 1 */
+#define CEREF02 (0x0004) /* Comp. E Reference 0 Resistor Select Bit : 2 */
+#define CEREF03 (0x0008) /* Comp. E Reference 0 Resistor Select Bit : 3 */
+#define CEREF04 (0x0010) /* Comp. E Reference 0 Resistor Select Bit : 4 */
+#define CERSEL (0x0020) /* Comp. E Reference select */
+#define CERS0 (0x0040) /* Comp. E Reference Source Bit : 0 */
+#define CERS1 (0x0080) /* Comp. E Reference Source Bit : 1 */
+#define CEREF10 (0x0100) /* Comp. E Reference 1 Resistor Select Bit : 0 */
+#define CEREF11 (0x0200) /* Comp. E Reference 1 Resistor Select Bit : 1 */
+#define CEREF12 (0x0400) /* Comp. E Reference 1 Resistor Select Bit : 2 */
+#define CEREF13 (0x0800) /* Comp. E Reference 1 Resistor Select Bit : 3 */
+#define CEREF14 (0x1000) /* Comp. E Reference 1 Resistor Select Bit : 4 */
+#define CEREFL0 (0x2000) /* Comp. E Reference voltage level Bit : 0 */
+#define CEREFL1 (0x4000) /* Comp. E Reference voltage level Bit : 1 */
+#define CEREFACC (0x8000) /* Comp. E Reference Accuracy */
+
+/* CECTL2 Control Bits */
+#define CEREF00_L (0x0001) /* Comp. E Reference 0 Resistor Select Bit : 0 */
+#define CEREF01_L (0x0002) /* Comp. E Reference 0 Resistor Select Bit : 1 */
+#define CEREF02_L (0x0004) /* Comp. E Reference 0 Resistor Select Bit : 2 */
+#define CEREF03_L (0x0008) /* Comp. E Reference 0 Resistor Select Bit : 3 */
+#define CEREF04_L (0x0010) /* Comp. E Reference 0 Resistor Select Bit : 4 */
+#define CERSEL_L (0x0020) /* Comp. E Reference select */
+#define CERS0_L (0x0040) /* Comp. E Reference Source Bit : 0 */
+#define CERS1_L (0x0080) /* Comp. E Reference Source Bit : 1 */
+
+/* CECTL2 Control Bits */
+#define CEREF10_H (0x0001) /* Comp. E Reference 1 Resistor Select Bit : 0 */
+#define CEREF11_H (0x0002) /* Comp. E Reference 1 Resistor Select Bit : 1 */
+#define CEREF12_H (0x0004) /* Comp. E Reference 1 Resistor Select Bit : 2 */
+#define CEREF13_H (0x0008) /* Comp. E Reference 1 Resistor Select Bit : 3 */
+#define CEREF14_H (0x0010) /* Comp. E Reference 1 Resistor Select Bit : 4 */
+#define CEREFL0_H (0x0020) /* Comp. E Reference voltage level Bit : 0 */
+#define CEREFL1_H (0x0040) /* Comp. E Reference voltage level Bit : 1 */
+#define CEREFACC_H (0x0080) /* Comp. E Reference Accuracy */
+
+#define CEREF0_0 (0x0000) /* Comp. E Int. Ref.0 Select 0 : 1/32 */
+#define CEREF0_1 (0x0001) /* Comp. E Int. Ref.0 Select 1 : 2/32 */
+#define CEREF0_2 (0x0002) /* Comp. E Int. Ref.0 Select 2 : 3/32 */
+#define CEREF0_3 (0x0003) /* Comp. E Int. Ref.0 Select 3 : 4/32 */
+#define CEREF0_4 (0x0004) /* Comp. E Int. Ref.0 Select 4 : 5/32 */
+#define CEREF0_5 (0x0005) /* Comp. E Int. Ref.0 Select 5 : 6/32 */
+#define CEREF0_6 (0x0006) /* Comp. E Int. Ref.0 Select 6 : 7/32 */
+#define CEREF0_7 (0x0007) /* Comp. E Int. Ref.0 Select 7 : 8/32 */
+#define CEREF0_8 (0x0008) /* Comp. E Int. Ref.0 Select 0 : 9/32 */
+#define CEREF0_9 (0x0009) /* Comp. E Int. Ref.0 Select 1 : 10/32 */
+#define CEREF0_10 (0x000A) /* Comp. E Int. Ref.0 Select 2 : 11/32 */
+#define CEREF0_11 (0x000B) /* Comp. E Int. Ref.0 Select 3 : 12/32 */
+#define CEREF0_12 (0x000C) /* Comp. E Int. Ref.0 Select 4 : 13/32 */
+#define CEREF0_13 (0x000D) /* Comp. E Int. Ref.0 Select 5 : 14/32 */
+#define CEREF0_14 (0x000E) /* Comp. E Int. Ref.0 Select 6 : 15/32 */
+#define CEREF0_15 (0x000F) /* Comp. E Int. Ref.0 Select 7 : 16/32 */
+#define CEREF0_16 (0x0010) /* Comp. E Int. Ref.0 Select 0 : 17/32 */
+#define CEREF0_17 (0x0011) /* Comp. E Int. Ref.0 Select 1 : 18/32 */
+#define CEREF0_18 (0x0012) /* Comp. E Int. Ref.0 Select 2 : 19/32 */
+#define CEREF0_19 (0x0013) /* Comp. E Int. Ref.0 Select 3 : 20/32 */
+#define CEREF0_20 (0x0014) /* Comp. E Int. Ref.0 Select 4 : 21/32 */
+#define CEREF0_21 (0x0015) /* Comp. E Int. Ref.0 Select 5 : 22/32 */
+#define CEREF0_22 (0x0016) /* Comp. E Int. Ref.0 Select 6 : 23/32 */
+#define CEREF0_23 (0x0017) /* Comp. E Int. Ref.0 Select 7 : 24/32 */
+#define CEREF0_24 (0x0018) /* Comp. E Int. Ref.0 Select 0 : 25/32 */
+#define CEREF0_25 (0x0019) /* Comp. E Int. Ref.0 Select 1 : 26/32 */
+#define CEREF0_26 (0x001A) /* Comp. E Int. Ref.0 Select 2 : 27/32 */
+#define CEREF0_27 (0x001B) /* Comp. E Int. Ref.0 Select 3 : 28/32 */
+#define CEREF0_28 (0x001C) /* Comp. E Int. Ref.0 Select 4 : 29/32 */
+#define CEREF0_29 (0x001D) /* Comp. E Int. Ref.0 Select 5 : 30/32 */
+#define CEREF0_30 (0x001E) /* Comp. E Int. Ref.0 Select 6 : 31/32 */
+#define CEREF0_31 (0x001F) /* Comp. E Int. Ref.0 Select 7 : 32/32 */
+
+#define CERS_0 (0x0000) /* Comp. E Reference Source 0 : Off */
+#define CERS_1 (0x0040) /* Comp. E Reference Source 1 : Vcc */
+#define CERS_2 (0x0080) /* Comp. E Reference Source 2 : Shared Ref. */
+#define CERS_3 (0x00C0) /* Comp. E Reference Source 3 : Shared Ref. / Off */
+
+#define CEREF1_0 (0x0000) /* Comp. E Int. Ref.1 Select 0 : 1/32 */
+#define CEREF1_1 (0x0100) /* Comp. E Int. Ref.1 Select 1 : 2/32 */
+#define CEREF1_2 (0x0200) /* Comp. E Int. Ref.1 Select 2 : 3/32 */
+#define CEREF1_3 (0x0300) /* Comp. E Int. Ref.1 Select 3 : 4/32 */
+#define CEREF1_4 (0x0400) /* Comp. E Int. Ref.1 Select 4 : 5/32 */
+#define CEREF1_5 (0x0500) /* Comp. E Int. Ref.1 Select 5 : 6/32 */
+#define CEREF1_6 (0x0600) /* Comp. E Int. Ref.1 Select 6 : 7/32 */
+#define CEREF1_7 (0x0700) /* Comp. E Int. Ref.1 Select 7 : 8/32 */
+#define CEREF1_8 (0x0800) /* Comp. E Int. Ref.1 Select 0 : 9/32 */
+#define CEREF1_9 (0x0900) /* Comp. E Int. Ref.1 Select 1 : 10/32 */
+#define CEREF1_10 (0x0A00) /* Comp. E Int. Ref.1 Select 2 : 11/32 */
+#define CEREF1_11 (0x0B00) /* Comp. E Int. Ref.1 Select 3 : 12/32 */
+#define CEREF1_12 (0x0C00) /* Comp. E Int. Ref.1 Select 4 : 13/32 */
+#define CEREF1_13 (0x0D00) /* Comp. E Int. Ref.1 Select 5 : 14/32 */
+#define CEREF1_14 (0x0E00) /* Comp. E Int. Ref.1 Select 6 : 15/32 */
+#define CEREF1_15 (0x0F00) /* Comp. E Int. Ref.1 Select 7 : 16/32 */
+#define CEREF1_16 (0x1000) /* Comp. E Int. Ref.1 Select 0 : 17/32 */
+#define CEREF1_17 (0x1100) /* Comp. E Int. Ref.1 Select 1 : 18/32 */
+#define CEREF1_18 (0x1200) /* Comp. E Int. Ref.1 Select 2 : 19/32 */
+#define CEREF1_19 (0x1300) /* Comp. E Int. Ref.1 Select 3 : 20/32 */
+#define CEREF1_20 (0x1400) /* Comp. E Int. Ref.1 Select 4 : 21/32 */
+#define CEREF1_21 (0x1500) /* Comp. E Int. Ref.1 Select 5 : 22/32 */
+#define CEREF1_22 (0x1600) /* Comp. E Int. Ref.1 Select 6 : 23/32 */
+#define CEREF1_23 (0x1700) /* Comp. E Int. Ref.1 Select 7 : 24/32 */
+#define CEREF1_24 (0x1800) /* Comp. E Int. Ref.1 Select 0 : 25/32 */
+#define CEREF1_25 (0x1900) /* Comp. E Int. Ref.1 Select 1 : 26/32 */
+#define CEREF1_26 (0x1A00) /* Comp. E Int. Ref.1 Select 2 : 27/32 */
+#define CEREF1_27 (0x1B00) /* Comp. E Int. Ref.1 Select 3 : 28/32 */
+#define CEREF1_28 (0x1C00) /* Comp. E Int. Ref.1 Select 4 : 29/32 */
+#define CEREF1_29 (0x1D00) /* Comp. E Int. Ref.1 Select 5 : 30/32 */
+#define CEREF1_30 (0x1E00) /* Comp. E Int. Ref.1 Select 6 : 31/32 */
+#define CEREF1_31 (0x1F00) /* Comp. E Int. Ref.1 Select 7 : 32/32 */
+
+#define CEREFL_0 (0x0000) /* Comp. E Reference voltage level 0 : None */
+#define CEREFL_1 (0x2000) /* Comp. E Reference voltage level 1 : 1.2V */
+#define CEREFL_2 (0x4000) /* Comp. E Reference voltage level 2 : 2.0V */
+#define CEREFL_3 (0x6000) /* Comp. E Reference voltage level 3 : 2.5V */
+
+#define CEPD0 (0x0001) /* Comp. E Disable Input Buffer of Port Register .0 */
+#define CEPD1 (0x0002) /* Comp. E Disable Input Buffer of Port Register .1 */
+#define CEPD2 (0x0004) /* Comp. E Disable Input Buffer of Port Register .2 */
+#define CEPD3 (0x0008) /* Comp. E Disable Input Buffer of Port Register .3 */
+#define CEPD4 (0x0010) /* Comp. E Disable Input Buffer of Port Register .4 */
+#define CEPD5 (0x0020) /* Comp. E Disable Input Buffer of Port Register .5 */
+#define CEPD6 (0x0040) /* Comp. E Disable Input Buffer of Port Register .6 */
+#define CEPD7 (0x0080) /* Comp. E Disable Input Buffer of Port Register .7 */
+#define CEPD8 (0x0100) /* Comp. E Disable Input Buffer of Port Register .8 */
+#define CEPD9 (0x0200) /* Comp. E Disable Input Buffer of Port Register .9 */
+#define CEPD10 (0x0400) /* Comp. E Disable Input Buffer of Port Register .10 */
+#define CEPD11 (0x0800) /* Comp. E Disable Input Buffer of Port Register .11 */
+#define CEPD12 (0x1000) /* Comp. E Disable Input Buffer of Port Register .12 */
+#define CEPD13 (0x2000) /* Comp. E Disable Input Buffer of Port Register .13 */
+#define CEPD14 (0x4000) /* Comp. E Disable Input Buffer of Port Register .14 */
+#define CEPD15 (0x8000) /* Comp. E Disable Input Buffer of Port Register .15 */
+
+#define CEPD0_L (0x0001) /* Comp. E Disable Input Buffer of Port Register .0 */
+#define CEPD1_L (0x0002) /* Comp. E Disable Input Buffer of Port Register .1 */
+#define CEPD2_L (0x0004) /* Comp. E Disable Input Buffer of Port Register .2 */
+#define CEPD3_L (0x0008) /* Comp. E Disable Input Buffer of Port Register .3 */
+#define CEPD4_L (0x0010) /* Comp. E Disable Input Buffer of Port Register .4 */
+#define CEPD5_L (0x0020) /* Comp. E Disable Input Buffer of Port Register .5 */
+#define CEPD6_L (0x0040) /* Comp. E Disable Input Buffer of Port Register .6 */
+#define CEPD7_L (0x0080) /* Comp. E Disable Input Buffer of Port Register .7 */
+
+#define CEPD8_H (0x0001) /* Comp. E Disable Input Buffer of Port Register .8 */
+#define CEPD9_H (0x0002) /* Comp. E Disable Input Buffer of Port Register .9 */
+#define CEPD10_H (0x0004) /* Comp. E Disable Input Buffer of Port Register .10 */
+#define CEPD11_H (0x0008) /* Comp. E Disable Input Buffer of Port Register .11 */
+#define CEPD12_H (0x0010) /* Comp. E Disable Input Buffer of Port Register .12 */
+#define CEPD13_H (0x0020) /* Comp. E Disable Input Buffer of Port Register .13 */
+#define CEPD14_H (0x0040) /* Comp. E Disable Input Buffer of Port Register .14 */
+#define CEPD15_H (0x0080) /* Comp. E Disable Input Buffer of Port Register .15 */
+
+/* CEINT Control Bits */
+#define CEIFG (0x0001) /* Comp. E Interrupt Flag */
+#define CEIIFG (0x0002) /* Comp. E Interrupt Flag Inverted Polarity */
+//#define RESERVED (0x0004) /* Comp. E */
+//#define RESERVED (0x0008) /* Comp. E */
+#define CERDYIFG (0x0010) /* Comp. E Comparator_E ready interrupt flag */
+//#define RESERVED (0x0020) /* Comp. E */
+//#define RESERVED (0x0040) /* Comp. E */
+//#define RESERVED (0x0080) /* Comp. E */
+#define CEIE (0x0100) /* Comp. E Interrupt Enable */
+#define CEIIE (0x0200) /* Comp. E Interrupt Enable Inverted Polarity */
+//#define RESERVED (0x0400) /* Comp. E */
+//#define RESERVED (0x0800) /* Comp. E */
+#define CERDYIE (0x1000) /* Comp. E Comparator_E ready interrupt enable */
+//#define RESERVED (0x2000) /* Comp. E */
+//#define RESERVED (0x4000) /* Comp. E */
+//#define RESERVED (0x8000) /* Comp. E */
+
+/* CEINT Control Bits */
+#define CEIFG_L (0x0001) /* Comp. E Interrupt Flag */
+#define CEIIFG_L (0x0002) /* Comp. E Interrupt Flag Inverted Polarity */
+//#define RESERVED (0x0004) /* Comp. E */
+//#define RESERVED (0x0008) /* Comp. E */
+#define CERDYIFG_L (0x0010) /* Comp. E Comparator_E ready interrupt flag */
+//#define RESERVED (0x0020) /* Comp. E */
+//#define RESERVED (0x0040) /* Comp. E */
+//#define RESERVED (0x0080) /* Comp. E */
+//#define RESERVED (0x0400) /* Comp. E */
+//#define RESERVED (0x0800) /* Comp. E */
+//#define RESERVED (0x2000) /* Comp. E */
+//#define RESERVED (0x4000) /* Comp. E */
+//#define RESERVED (0x8000) /* Comp. E */
+
+/* CEINT Control Bits */
+//#define RESERVED (0x0004) /* Comp. E */
+//#define RESERVED (0x0008) /* Comp. E */
+//#define RESERVED (0x0020) /* Comp. E */
+//#define RESERVED (0x0040) /* Comp. E */
+//#define RESERVED (0x0080) /* Comp. E */
+#define CEIE_H (0x0001) /* Comp. E Interrupt Enable */
+#define CEIIE_H (0x0002) /* Comp. E Interrupt Enable Inverted Polarity */
+//#define RESERVED (0x0400) /* Comp. E */
+//#define RESERVED (0x0800) /* Comp. E */
+#define CERDYIE_H (0x0010) /* Comp. E Comparator_E ready interrupt enable */
+//#define RESERVED (0x2000) /* Comp. E */
+//#define RESERVED (0x4000) /* Comp. E */
+//#define RESERVED (0x8000) /* Comp. E */
+
+/* CEIV Definitions */
+#define CEIV_NONE (0x0000) /* No Interrupt pending */
+#define CEIV_CEIFG (0x0002) /* CEIFG */
+#define CEIV_CEIIFG (0x0004) /* CEIIFG */
+#define CEIV_CERDYIFG (0x000A) /* CERDYIFG */
+
+/*************************************************************
+* CRC Module
+*************************************************************/
+#define __MSP430_HAS_CRC__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_CRC__ 0x0150
+#define CRC_BASE __MSP430_BASEADDRESS_CRC__
+
+sfr_w(CRCDI); /* CRC Data In Register */
+sfr_b(CRCDI_L); /* CRC Data In Register */
+sfr_b(CRCDI_H); /* CRC Data In Register */
+sfr_w(CRCDIRB); /* CRC data in reverse byte Register */
+sfr_b(CRCDIRB_L); /* CRC data in reverse byte Register */
+sfr_b(CRCDIRB_H); /* CRC data in reverse byte Register */
+sfr_w(CRCINIRES); /* CRC Initialisation Register and Result Register */
+sfr_b(CRCINIRES_L); /* CRC Initialisation Register and Result Register */
+sfr_b(CRCINIRES_H); /* CRC Initialisation Register and Result Register */
+sfr_w(CRCRESR); /* CRC reverse result Register */
+sfr_b(CRCRESR_L); /* CRC reverse result Register */
+sfr_b(CRCRESR_H); /* CRC reverse result Register */
+
+/*************************************************************
+* CRC Module
+*************************************************************/
+#define __MSP430_HAS_CRC32__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_CRC32__ 0x0980
+#define CRC32_BASE __MSP430_BASEADDRESS_CRC32__
+
+
+//sfrl CRC32DIL0 (0x0980) /* CRC32 Data In */
+sfr_w(CRC32DIW0); /* CRC32 Data In */
+sfr_b(CRC32DIW0_L); /* CRC32 Data In */
+sfr_b(CRC32DIW0_H); /* CRC32 Data In */
+sfr_w(CRC32DIW1); /* CRC32 Data In */
+sfr_b(CRC32DIW1_L); /* CRC32 Data In */
+sfr_b(CRC32DIW1_H); /* CRC32 Data In */
+#define CRC32DIB0 CRC32DIW0_L
+
+//sfrl CRC32DIRBL0 (0x0984) /* CRC32 Data In Reversed Bit */
+sfr_w(CRC32DIRBW1); /* CRC32 Data In Reversed Bit */
+sfr_b(CRC32DIRBW1_L); /* CRC32 Data In Reversed Bit */
+sfr_b(CRC32DIRBW1_H); /* CRC32 Data In Reversed Bit */
+sfr_w(CRC32DIRBW0); /* CRC32 Data In Reversed Bit */
+sfr_b(CRC32DIRBW0_L); /* CRC32 Data In Reversed Bit */
+sfr_b(CRC32DIRBW0_H); /* CRC32 Data In Reversed Bit */
+#define CRC32DIRBB0 CRC32DIRBW0_H
+
+//sfrl CRC32INIRESL0 (0x0988) /* CRC32 Initialization and Result */
+sfr_w(CRC32INIRESW0); /* CRC32 Initialization and Result */
+sfr_b(CRC32INIRESW0_L); /* CRC32 Initialization and Result */
+sfr_b(CRC32INIRESW0_H); /* CRC32 Initialization and Result */
+sfr_w(CRC32INIRESW1); /* CRC32 Initialization and Result */
+sfr_b(CRC32INIRESW1_L); /* CRC32 Initialization and Result */
+sfr_b(CRC32INIRESW1_H); /* CRC32 Initialization and Result */
+#define CRC32RESB0 CRC32INIRESW0_L
+#define CRC32RESB1 CRC32INIRESW0_H
+#define CRC32RESB2 CRC32INIRESW1_L
+#define CRC32RESB3 CRC32INIRESW1_H
+
+//sfrl CRC32RESRL0 (0x098C) /* CRC32 Result Reverse */
+sfr_w(CRC32RESRW1); /* CRC32 Result Reverse */
+sfr_b(CRC32RESRW1_L); /* CRC32 Result Reverse */
+sfr_b(CRC32RESRW1_H); /* CRC32 Result Reverse */
+sfr_w(CRC32RESRW0); /* CRC32 Result Reverse */
+sfr_b(CRC32RESRW0_L); /* CRC32 Result Reverse */
+sfr_b(CRC32RESRW0_H); /* CRC32 Result Reverse */
+#define CRC32RESRB3 CRC32RESRW1_L
+#define CRC32RESRB2 CRC32RESRW1_H
+#define CRC32RESRB1 CRC32RESRW0_L
+#define CRC32RESRB0 CRC32RESRW0_H
+
+//sfrl CRC16DIL0 (0x0990) /* CRC16 Data Input */
+sfr_w(CRC16DIW0); /* CRC16 Data Input */
+sfr_b(CRC16DIW0_L); /* CRC16 Data Input */
+sfr_b(CRC16DIW0_H); /* CRC16 Data Input */
+sfr_w(CRC16DIW1); /* CRC16 Data Input */
+sfr_b(CRC16DIW1_L); /* CRC16 Data Input */
+sfr_b(CRC16DIW1_H); /* CRC16 Data Input */
+#define CRC16DIB0 CRC16DIW0_L
+//sfrl CRC16DIRBL0 (0x0994) /* CRC16 Data In Reverse */
+sfr_w(CRC16DIRBW1); /* CRC16 Data In Reverse */
+sfr_b(CRC16DIRBW1_L); /* CRC16 Data In Reverse */
+sfr_b(CRC16DIRBW1_H); /* CRC16 Data In Reverse */
+sfr_w(CRC16DIRBW0); /* CRC16 Data In Reverse */
+sfr_b(CRC16DIRBW0_L); /* CRC16 Data In Reverse */
+sfr_b(CRC16DIRBW0_H); /* CRC16 Data In Reverse */
+#define CRC16DIRBB0 CRC16DIRBW0_L
+
+//sfrl CRC16INIRESL0 (0x0998) /* CRC16 Init and Result */
+sfr_w(CRC16INIRESW0); /* CRC16 Init and Result */
+sfr_b(CRC16INIRESW0_L); /* CRC16 Init and Result */
+sfr_b(CRC16INIRESW0_H); /* CRC16 Init and Result */
+#define CRC16INIRESB1 CRC16INIRESW0_H
+#define CRC16INIRESB0 CRC16INIRESW0_L
+
+//sfrl CRC16RESRL0 (0x099E) /* CRC16 Result Reverse */
+sfr_w(CRC16RESRW0); /* CRC16 Result Reverse */
+sfr_b(CRC16RESRW0_L); /* CRC16 Result Reverse */
+sfr_b(CRC16RESRW0_H); /* CRC16 Result Reverse */
+sfr_w(CRC16RESRW1); /* CRC16 Result Reverse */
+sfr_b(CRC16RESRW1_L); /* CRC16 Result Reverse */
+sfr_b(CRC16RESRW1_H); /* CRC16 Result Reverse */
+#define CRC16RESRB1 CRC16RESRW0_L
+#define CRC16RESRB0 CRC16RESRW0_H
+
+/************************************************************
+* CLOCK SYSTEM
+************************************************************/
+#define __MSP430_HAS_CS__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_CS__ 0x0160
+#define CS_BASE __MSP430_BASEADDRESS_CS__
+
+sfr_w(CSCTL0); /* CS Control Register 0 */
+sfr_b(CSCTL0_L); /* CS Control Register 0 */
+sfr_b(CSCTL0_H); /* CS Control Register 0 */
+sfr_w(CSCTL1); /* CS Control Register 1 */
+sfr_b(CSCTL1_L); /* CS Control Register 1 */
+sfr_b(CSCTL1_H); /* CS Control Register 1 */
+sfr_w(CSCTL2); /* CS Control Register 2 */
+sfr_b(CSCTL2_L); /* CS Control Register 2 */
+sfr_b(CSCTL2_H); /* CS Control Register 2 */
+sfr_w(CSCTL3); /* CS Control Register 3 */
+sfr_b(CSCTL3_L); /* CS Control Register 3 */
+sfr_b(CSCTL3_H); /* CS Control Register 3 */
+sfr_w(CSCTL4); /* CS Control Register 4 */
+sfr_b(CSCTL4_L); /* CS Control Register 4 */
+sfr_b(CSCTL4_H); /* CS Control Register 4 */
+sfr_w(CSCTL5); /* CS Control Register 5 */
+sfr_b(CSCTL5_L); /* CS Control Register 5 */
+sfr_b(CSCTL5_H); /* CS Control Register 5 */
+sfr_w(CSCTL6); /* CS Control Register 6 */
+sfr_b(CSCTL6_L); /* CS Control Register 6 */
+sfr_b(CSCTL6_H); /* CS Control Register 6 */
+
+/* CSCTL0 Control Bits */
+
+#define CSKEY (0xA500) /* CS Password */
+#define CSKEY_H (0xA5) /* CS Password for high byte access */
+
+/* CSCTL1 Control Bits */
+#define DCOFSEL0 (0x0002) /* DCO frequency select Bit: 0 */
+#define DCOFSEL1 (0x0004) /* DCO frequency select Bit: 1 */
+#define DCOFSEL2 (0x0008) /* DCO frequency select Bit: 2 */
+#define DCORSEL (0x0040) /* DCO range select. */
+
+/* CSCTL1 Control Bits */
+#define DCOFSEL0_L (0x0002) /* DCO frequency select Bit: 0 */
+#define DCOFSEL1_L (0x0004) /* DCO frequency select Bit: 1 */
+#define DCOFSEL2_L (0x0008) /* DCO frequency select Bit: 2 */
+#define DCORSEL_L (0x0040) /* DCO range select. */
+
+#define DCOFSEL_0 (0x0000) /* DCO frequency select: 0 */
+#define DCOFSEL_1 (0x0002) /* DCO frequency select: 1 */
+#define DCOFSEL_2 (0x0004) /* DCO frequency select: 2 */
+#define DCOFSEL_3 (0x0006) /* DCO frequency select: 3 */
+#define DCOFSEL_4 (0x0008) /* DCO frequency select: 4 */
+#define DCOFSEL_5 (0x000A) /* DCO frequency select: 5 */
+#define DCOFSEL_6 (0x000C) /* DCO frequency select: 6 */
+#define DCOFSEL_7 (0x000E) /* DCO frequency select: 7 */
+
+/* CSCTL2 Control Bits */
+#define SELM0 (0x0001) /* MCLK Source Select Bit: 0 */
+#define SELM1 (0x0002) /* MCLK Source Select Bit: 1 */
+#define SELM2 (0x0004) /* MCLK Source Select Bit: 2 */
+//#define RESERVED (0x0004) /* RESERVED */
+//#define RESERVED (0x0008) /* RESERVED */
+#define SELS0 (0x0010) /* SMCLK Source Select Bit: 0 */
+#define SELS1 (0x0020) /* SMCLK Source Select Bit: 1 */
+#define SELS2 (0x0040) /* SMCLK Source Select Bit: 2 */
+//#define RESERVED (0x0040) /* RESERVED */
+//#define RESERVED (0x0080) /* RESERVED */
+#define SELA0 (0x0100) /* ACLK Source Select Bit: 0 */
+#define SELA1 (0x0200) /* ACLK Source Select Bit: 1 */
+#define SELA2 (0x0400) /* ACLK Source Select Bit: 2 */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x1000) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* CSCTL2 Control Bits */
+#define SELM0_L (0x0001) /* MCLK Source Select Bit: 0 */
+#define SELM1_L (0x0002) /* MCLK Source Select Bit: 1 */
+#define SELM2_L (0x0004) /* MCLK Source Select Bit: 2 */
+//#define RESERVED (0x0004) /* RESERVED */
+//#define RESERVED (0x0008) /* RESERVED */
+#define SELS0_L (0x0010) /* SMCLK Source Select Bit: 0 */
+#define SELS1_L (0x0020) /* SMCLK Source Select Bit: 1 */
+#define SELS2_L (0x0040) /* SMCLK Source Select Bit: 2 */
+//#define RESERVED (0x0040) /* RESERVED */
+//#define RESERVED (0x0080) /* RESERVED */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x1000) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* CSCTL2 Control Bits */
+//#define RESERVED (0x0004) /* RESERVED */
+//#define RESERVED (0x0008) /* RESERVED */
+//#define RESERVED (0x0040) /* RESERVED */
+//#define RESERVED (0x0080) /* RESERVED */
+#define SELA0_H (0x0001) /* ACLK Source Select Bit: 0 */
+#define SELA1_H (0x0002) /* ACLK Source Select Bit: 1 */
+#define SELA2_H (0x0004) /* ACLK Source Select Bit: 2 */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x1000) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+#define SELM_0 (0x0000) /* MCLK Source Select 0 */
+#define SELM_1 (0x0001) /* MCLK Source Select 1 */
+#define SELM_2 (0x0002) /* MCLK Source Select 2 */
+#define SELM_3 (0x0003) /* MCLK Source Select 3 */
+#define SELM_4 (0x0004) /* MCLK Source Select 4 */
+#define SELM_5 (0x0005) /* MCLK Source Select 5 */
+#define SELM_6 (0x0006) /* MCLK Source Select 6 */
+#define SELM_7 (0x0007) /* MCLK Source Select 7 */
+#define SELM__LFXTCLK (0x0000) /* MCLK Source Select LFXTCLK */
+#define SELM__VLOCLK (0x0001) /* MCLK Source Select VLOCLK */
+#define SELM__LFMODCLK (0x0002) /* MCLK Source Select LFMODOSC */
+#define SELM__LFMODOSC (0x0002) /* MCLK Source Select LFMODOSC (legacy) */
+#define SELM__DCOCLK (0x0003) /* MCLK Source Select DCOCLK */
+#define SELM__MODCLK (0x0004) /* MCLK Source Select MODOSC */
+#define SELM__MODOSC (0x0004) /* MCLK Source Select MODOSC (legacy) */
+#define SELM__HFXTCLK (0x0005) /* MCLK Source Select HFXTCLK */
+
+#define SELS_0 (0x0000) /* SMCLK Source Select 0 */
+#define SELS_1 (0x0010) /* SMCLK Source Select 1 */
+#define SELS_2 (0x0020) /* SMCLK Source Select 2 */
+#define SELS_3 (0x0030) /* SMCLK Source Select 3 */
+#define SELS_4 (0x0040) /* SMCLK Source Select 4 */
+#define SELS_5 (0x0050) /* SMCLK Source Select 5 */
+#define SELS_6 (0x0060) /* SMCLK Source Select 6 */
+#define SELS_7 (0x0070) /* SMCLK Source Select 7 */
+#define SELS__LFXTCLK (0x0000) /* SMCLK Source Select LFXTCLK */
+#define SELS__VLOCLK (0x0010) /* SMCLK Source Select VLOCLK */
+#define SELS__LFMODCLK (0x0020) /* SMCLK Source Select LFMODOSC */
+#define SELS__LFMODOSC (0x0020) /* SMCLK Source Select LFMODOSC (legacy) */
+#define SELS__DCOCLK (0x0030) /* SMCLK Source Select DCOCLK */
+#define SELS__MODCLK (0x0040) /* SMCLK Source Select MODOSC */
+#define SELS__MODOSC (0x0040) /* SMCLK Source Select MODOSC (legacy) */
+#define SELS__HFXTCLK (0x0050) /* SMCLK Source Select HFXTCLK */
+
+#define SELA_0 (0x0000) /* ACLK Source Select 0 */
+#define SELA_1 (0x0100) /* ACLK Source Select 1 */
+#define SELA_2 (0x0200) /* ACLK Source Select 2 */
+#define SELA_3 (0x0300) /* ACLK Source Select 3 */
+#define SELA_4 (0x0400) /* ACLK Source Select 4 */
+#define SELA_5 (0x0500) /* ACLK Source Select 5 */
+#define SELA_6 (0x0600) /* ACLK Source Select 6 */
+#define SELA_7 (0x0700) /* ACLK Source Select 7 */
+#define SELA__LFXTCLK (0x0000) /* ACLK Source Select LFXTCLK */
+#define SELA__VLOCLK (0x0100) /* ACLK Source Select VLOCLK */
+#define SELA__LFMODCLK (0x0200) /* ACLK Source Select LFMODOSC */
+#define SELA__LFMODOSC (0x0200) /* ACLK Source Select LFMODOSC (legacy) */
+
+/* CSCTL3 Control Bits */
+#define DIVM0 (0x0001) /* MCLK Divider Bit: 0 */
+#define DIVM1 (0x0002) /* MCLK Divider Bit: 1 */
+#define DIVM2 (0x0004) /* MCLK Divider Bit: 2 */
+//#define RESERVED (0x0004) /* RESERVED */
+//#define RESERVED (0x0008) /* RESERVED */
+#define DIVS0 (0x0010) /* SMCLK Divider Bit: 0 */
+#define DIVS1 (0x0020) /* SMCLK Divider Bit: 1 */
+#define DIVS2 (0x0040) /* SMCLK Divider Bit: 2 */
+//#define RESERVED (0x0040) /* RESERVED */
+//#define RESERVED (0x0080) /* RESERVED */
+#define DIVA0 (0x0100) /* ACLK Divider Bit: 0 */
+#define DIVA1 (0x0200) /* ACLK Divider Bit: 1 */
+#define DIVA2 (0x0400) /* ACLK Divider Bit: 2 */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x1000) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* CSCTL3 Control Bits */
+#define DIVM0_L (0x0001) /* MCLK Divider Bit: 0 */
+#define DIVM1_L (0x0002) /* MCLK Divider Bit: 1 */
+#define DIVM2_L (0x0004) /* MCLK Divider Bit: 2 */
+//#define RESERVED (0x0004) /* RESERVED */
+//#define RESERVED (0x0008) /* RESERVED */
+#define DIVS0_L (0x0010) /* SMCLK Divider Bit: 0 */
+#define DIVS1_L (0x0020) /* SMCLK Divider Bit: 1 */
+#define DIVS2_L (0x0040) /* SMCLK Divider Bit: 2 */
+//#define RESERVED (0x0040) /* RESERVED */
+//#define RESERVED (0x0080) /* RESERVED */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x1000) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+/* CSCTL3 Control Bits */
+//#define RESERVED (0x0004) /* RESERVED */
+//#define RESERVED (0x0008) /* RESERVED */
+//#define RESERVED (0x0040) /* RESERVED */
+//#define RESERVED (0x0080) /* RESERVED */
+#define DIVA0_H (0x0001) /* ACLK Divider Bit: 0 */
+#define DIVA1_H (0x0002) /* ACLK Divider Bit: 1 */
+#define DIVA2_H (0x0004) /* ACLK Divider Bit: 2 */
+//#define RESERVED (0x0400) /* RESERVED */
+//#define RESERVED (0x0800) /* RESERVED */
+//#define RESERVED (0x1000) /* RESERVED */
+//#define RESERVED (0x2000) /* RESERVED */
+//#define RESERVED (0x4000) /* RESERVED */
+//#define RESERVED (0x8000) /* RESERVED */
+
+#define DIVM_0 (0x0000) /* MCLK Source Divider 0 */
+#define DIVM_1 (0x0001) /* MCLK Source Divider 1 */
+#define DIVM_2 (0x0002) /* MCLK Source Divider 2 */
+#define DIVM_3 (0x0003) /* MCLK Source Divider 3 */
+#define DIVM_4 (0x0004) /* MCLK Source Divider 4 */
+#define DIVM_5 (0x0005) /* MCLK Source Divider 5 */
+#define DIVM__1 (0x0000) /* MCLK Source Divider f(MCLK)/1 */
+#define DIVM__2 (0x0001) /* MCLK Source Divider f(MCLK)/2 */
+#define DIVM__4 (0x0002) /* MCLK Source Divider f(MCLK)/4 */
+#define DIVM__8 (0x0003) /* MCLK Source Divider f(MCLK)/8 */
+#define DIVM__16 (0x0004) /* MCLK Source Divider f(MCLK)/16 */
+#define DIVM__32 (0x0005) /* MCLK Source Divider f(MCLK)/32 */
+
+#define DIVS_0 (0x0000) /* SMCLK Source Divider 0 */
+#define DIVS_1 (0x0010) /* SMCLK Source Divider 1 */
+#define DIVS_2 (0x0020) /* SMCLK Source Divider 2 */
+#define DIVS_3 (0x0030) /* SMCLK Source Divider 3 */
+#define DIVS_4 (0x0040) /* SMCLK Source Divider 4 */
+#define DIVS_5 (0x0050) /* SMCLK Source Divider 5 */
+#define DIVS__1 (0x0000) /* SMCLK Source Divider f(SMCLK)/1 */
+#define DIVS__2 (0x0010) /* SMCLK Source Divider f(SMCLK)/2 */
+#define DIVS__4 (0x0020) /* SMCLK Source Divider f(SMCLK)/4 */
+#define DIVS__8 (0x0030) /* SMCLK Source Divider f(SMCLK)/8 */
+#define DIVS__16 (0x0040) /* SMCLK Source Divider f(SMCLK)/16 */
+#define DIVS__32 (0x0050) /* SMCLK Source Divider f(SMCLK)/32 */
+
+#define DIVA_0 (0x0000) /* ACLK Source Divider 0 */
+#define DIVA_1 (0x0100) /* ACLK Source Divider 1 */
+#define DIVA_2 (0x0200) /* ACLK Source Divider 2 */
+#define DIVA_3 (0x0300) /* ACLK Source Divider 3 */
+#define DIVA_4 (0x0400) /* ACLK Source Divider 4 */
+#define DIVA_5 (0x0500) /* ACLK Source Divider 5 */
+#define DIVA__1 (0x0000) /* ACLK Source Divider f(ACLK)/1 */
+#define DIVA__2 (0x0100) /* ACLK Source Divider f(ACLK)/2 */
+#define DIVA__4 (0x0200) /* ACLK Source Divider f(ACLK)/4 */
+#define DIVA__8 (0x0300) /* ACLK Source Divider f(ACLK)/8 */
+#define DIVA__16 (0x0400) /* ACLK Source Divider f(ACLK)/16 */
+#define DIVA__32 (0x0500) /* ACLK Source Divider f(ACLK)/32 */
+
+/* CSCTL4 Control Bits */
+#define LFXTOFF (0x0001) /* Low Frequency Oscillator (LFXT) disable */
+#define SMCLKOFF (0x0002) /* SMCLK Off */
+#define VLOOFF (0x0008) /* VLO Off */
+#define LFXTBYPASS (0x0010) /* LFXT bypass mode : 0: internal 1:sourced from external pin */
+#define LFXTDRIVE0 (0x0040) /* LFXT Drive Level mode Bit 0 */
+#define LFXTDRIVE1 (0x0080) /* LFXT Drive Level mode Bit 1 */
+#define HFXTOFF (0x0100) /* High Frequency Oscillator disable */
+#define HFFREQ0 (0x0400) /* HFXT frequency selection Bit 1 */
+#define HFFREQ1 (0x0800) /* HFXT frequency selection Bit 0 */
+#define HFXTBYPASS (0x1000) /* HFXT bypass mode : 0: internal 1:sourced from external pin */
+#define HFXTDRIVE0 (0x4000) /* HFXT Drive Level mode Bit 0 */
+#define HFXTDRIVE1 (0x8000) /* HFXT Drive Level mode Bit 1 */
+
+/* CSCTL4 Control Bits */
+#define LFXTOFF_L (0x0001) /* Low Frequency Oscillator (LFXT) disable */
+#define SMCLKOFF_L (0x0002) /* SMCLK Off */
+#define VLOOFF_L (0x0008) /* VLO Off */
+#define LFXTBYPASS_L (0x0010) /* LFXT bypass mode : 0: internal 1:sourced from external pin */
+#define LFXTDRIVE0_L (0x0040) /* LFXT Drive Level mode Bit 0 */
+#define LFXTDRIVE1_L (0x0080) /* LFXT Drive Level mode Bit 1 */
+
+/* CSCTL4 Control Bits */
+#define HFXTOFF_H (0x0001) /* High Frequency Oscillator disable */
+#define HFFREQ0_H (0x0004) /* HFXT frequency selection Bit 1 */
+#define HFFREQ1_H (0x0008) /* HFXT frequency selection Bit 0 */
+#define HFXTBYPASS_H (0x0010) /* HFXT bypass mode : 0: internal 1:sourced from external pin */
+#define HFXTDRIVE0_H (0x0040) /* HFXT Drive Level mode Bit 0 */
+#define HFXTDRIVE1_H (0x0080) /* HFXT Drive Level mode Bit 1 */
+
+#define LFXTDRIVE_0 (0x0000) /* LFXT Drive Level mode: 0 */
+#define LFXTDRIVE_1 (0x0040) /* LFXT Drive Level mode: 1 */
+#define LFXTDRIVE_2 (0x0080) /* LFXT Drive Level mode: 2 */
+#define LFXTDRIVE_3 (0x00C0) /* LFXT Drive Level mode: 3 */
+
+#define HFFREQ_0 (0x0000) /* HFXT frequency selection: 0 */
+#define HFFREQ_1 (0x0400) /* HFXT frequency selection: 1 */
+#define HFFREQ_2 (0x0800) /* HFXT frequency selection: 2 */
+#define HFFREQ_3 (0x0C00) /* HFXT frequency selection: 3 */
+
+#define HFXTDRIVE_0 (0x0000) /* HFXT Drive Level mode: 0 */
+#define HFXTDRIVE_1 (0x4000) /* HFXT Drive Level mode: 1 */
+#define HFXTDRIVE_2 (0x8000) /* HFXT Drive Level mode: 2 */
+#define HFXTDRIVE_3 (0xC000) /* HFXT Drive Level mode: 3 */
+
+/* CSCTL5 Control Bits */
+#define LFXTOFFG (0x0001) /* LFXT Low Frequency Oscillator Fault Flag */
+#define HFXTOFFG (0x0002) /* HFXT High Frequency Oscillator Fault Flag */
+#define ENSTFCNT1 (0x0040) /* Enable start counter for XT1 */
+#define ENSTFCNT2 (0x0080) /* Enable start counter for XT2 */
+
+/* CSCTL5 Control Bits */
+#define LFXTOFFG_L (0x0001) /* LFXT Low Frequency Oscillator Fault Flag */
+#define HFXTOFFG_L (0x0002) /* HFXT High Frequency Oscillator Fault Flag */
+#define ENSTFCNT1_L (0x0040) /* Enable start counter for XT1 */
+#define ENSTFCNT2_L (0x0080) /* Enable start counter for XT2 */
+
+/* CSCTL6 Control Bits */
+#define ACLKREQEN (0x0001) /* ACLK Clock Request Enable */
+#define MCLKREQEN (0x0002) /* MCLK Clock Request Enable */
+#define SMCLKREQEN (0x0004) /* SMCLK Clock Request Enable */
+#define MODCLKREQEN (0x0008) /* MODOSC Clock Request Enable */
+
+/* CSCTL6 Control Bits */
+#define ACLKREQEN_L (0x0001) /* ACLK Clock Request Enable */
+#define MCLKREQEN_L (0x0002) /* MCLK Clock Request Enable */
+#define SMCLKREQEN_L (0x0004) /* SMCLK Clock Request Enable */
+#define MODCLKREQEN_L (0x0008) /* MODOSC Clock Request Enable */
+
+/************************************************************
+* DMA_X
+************************************************************/
+#define __MSP430_HAS_DMAX_3__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_DMAX_3__ 0x0500
+#define DMA_BASE __MSP430_BASEADDRESS_DMAX_3__
+
+sfr_w(DMACTL0); /* DMA Module Control 0 */
+sfr_b(DMACTL0_L); /* DMA Module Control 0 */
+sfr_b(DMACTL0_H); /* DMA Module Control 0 */
+sfr_w(DMACTL1); /* DMA Module Control 1 */
+sfr_b(DMACTL1_L); /* DMA Module Control 1 */
+sfr_b(DMACTL1_H); /* DMA Module Control 1 */
+sfr_w(DMACTL2); /* DMA Module Control 2 */
+sfr_b(DMACTL2_L); /* DMA Module Control 2 */
+sfr_b(DMACTL2_H); /* DMA Module Control 2 */
+sfr_w(DMACTL3); /* DMA Module Control 3 */
+sfr_b(DMACTL3_L); /* DMA Module Control 3 */
+sfr_b(DMACTL3_H); /* DMA Module Control 3 */
+sfr_w(DMACTL4); /* DMA Module Control 4 */
+sfr_b(DMACTL4_L); /* DMA Module Control 4 */
+sfr_b(DMACTL4_H); /* DMA Module Control 4 */
+sfr_w(DMAIV); /* DMA Interrupt Vector Word */
+sfr_b(DMAIV_L); /* DMA Interrupt Vector Word */
+sfr_b(DMAIV_H); /* DMA Interrupt Vector Word */
+
+sfr_w(DMA0CTL); /* DMA Channel 0 Control */
+sfr_b(DMA0CTL_L); /* DMA Channel 0 Control */
+sfr_b(DMA0CTL_H); /* DMA Channel 0 Control */
+sfr_l(DMA0SA); /* DMA Channel 0 Source Address */
+sfr_w(DMA0SAL); /* DMA Channel 0 Source Address */
+sfr_w(DMA0SAH); /* DMA Channel 0 Source Address */
+sfr_l(DMA0DA); /* DMA Channel 0 Destination Address */
+sfr_w(DMA0DAL); /* DMA Channel 0 Destination Address */
+sfr_w(DMA0DAH); /* DMA Channel 0 Destination Address */
+sfr_w(DMA0SZ); /* DMA Channel 0 Transfer Size */
+
+sfr_w(DMA1CTL); /* DMA Channel 1 Control */
+sfr_b(DMA1CTL_L); /* DMA Channel 1 Control */
+sfr_b(DMA1CTL_H); /* DMA Channel 1 Control */
+sfr_l(DMA1SA); /* DMA Channel 1 Source Address */
+sfr_w(DMA1SAL); /* DMA Channel 1 Source Address */
+sfr_w(DMA1SAH); /* DMA Channel 1 Source Address */
+sfr_l(DMA1DA); /* DMA Channel 1 Destination Address */
+sfr_w(DMA1DAL); /* DMA Channel 1 Destination Address */
+sfr_w(DMA1DAH); /* DMA Channel 1 Destination Address */
+sfr_w(DMA1SZ); /* DMA Channel 1 Transfer Size */
+
+sfr_w(DMA2CTL); /* DMA Channel 2 Control */
+sfr_b(DMA2CTL_L); /* DMA Channel 2 Control */
+sfr_b(DMA2CTL_H); /* DMA Channel 2 Control */
+sfr_l(DMA2SA); /* DMA Channel 2 Source Address */
+sfr_w(DMA2SAL); /* DMA Channel 2 Source Address */
+sfr_w(DMA2SAH); /* DMA Channel 2 Source Address */
+sfr_l(DMA2DA); /* DMA Channel 2 Destination Address */
+sfr_w(DMA2DAL); /* DMA Channel 2 Destination Address */
+sfr_w(DMA2DAH); /* DMA Channel 2 Destination Address */
+sfr_w(DMA2SZ); /* DMA Channel 2 Transfer Size */
+
+/* DMACTL0 Control Bits */
+#define DMA0TSEL0 (0x0001) /* DMA channel 0 transfer select bit 0 */
+#define DMA0TSEL1 (0x0002) /* DMA channel 0 transfer select bit 1 */
+#define DMA0TSEL2 (0x0004) /* DMA channel 0 transfer select bit 2 */
+#define DMA0TSEL3 (0x0008) /* DMA channel 0 transfer select bit 3 */
+#define DMA0TSEL4 (0x0010) /* DMA channel 0 transfer select bit 4 */
+#define DMA1TSEL0 (0x0100) /* DMA channel 1 transfer select bit 0 */
+#define DMA1TSEL1 (0x0200) /* DMA channel 1 transfer select bit 1 */
+#define DMA1TSEL2 (0x0400) /* DMA channel 1 transfer select bit 2 */
+#define DMA1TSEL3 (0x0800) /* DMA channel 1 transfer select bit 3 */
+#define DMA1TSEL4 (0x1000) /* DMA channel 1 transfer select bit 4 */
+
+/* DMACTL0 Control Bits */
+#define DMA0TSEL0_L (0x0001) /* DMA channel 0 transfer select bit 0 */
+#define DMA0TSEL1_L (0x0002) /* DMA channel 0 transfer select bit 1 */
+#define DMA0TSEL2_L (0x0004) /* DMA channel 0 transfer select bit 2 */
+#define DMA0TSEL3_L (0x0008) /* DMA channel 0 transfer select bit 3 */
+#define DMA0TSEL4_L (0x0010) /* DMA channel 0 transfer select bit 4 */
+
+/* DMACTL0 Control Bits */
+#define DMA1TSEL0_H (0x0001) /* DMA channel 1 transfer select bit 0 */
+#define DMA1TSEL1_H (0x0002) /* DMA channel 1 transfer select bit 1 */
+#define DMA1TSEL2_H (0x0004) /* DMA channel 1 transfer select bit 2 */
+#define DMA1TSEL3_H (0x0008) /* DMA channel 1 transfer select bit 3 */
+#define DMA1TSEL4_H (0x0010) /* DMA channel 1 transfer select bit 4 */
+
+/* DMACTL01 Control Bits */
+#define DMA2TSEL0 (0x0001) /* DMA channel 2 transfer select bit 0 */
+#define DMA2TSEL1 (0x0002) /* DMA channel 2 transfer select bit 1 */
+#define DMA2TSEL2 (0x0004) /* DMA channel 2 transfer select bit 2 */
+#define DMA2TSEL3 (0x0008) /* DMA channel 2 transfer select bit 3 */
+#define DMA2TSEL4 (0x0010) /* DMA channel 2 transfer select bit 4 */
+
+/* DMACTL01 Control Bits */
+#define DMA2TSEL0_L (0x0001) /* DMA channel 2 transfer select bit 0 */
+#define DMA2TSEL1_L (0x0002) /* DMA channel 2 transfer select bit 1 */
+#define DMA2TSEL2_L (0x0004) /* DMA channel 2 transfer select bit 2 */
+#define DMA2TSEL3_L (0x0008) /* DMA channel 2 transfer select bit 3 */
+#define DMA2TSEL4_L (0x0010) /* DMA channel 2 transfer select bit 4 */
+
+/* DMACTL4 Control Bits */
+#define ENNMI (0x0001) /* Enable NMI interruption of DMA */
+#define ROUNDROBIN (0x0002) /* Round-Robin DMA channel priorities */
+#define DMARMWDIS (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */
+
+/* DMACTL4 Control Bits */
+#define ENNMI_L (0x0001) /* Enable NMI interruption of DMA */
+#define ROUNDROBIN_L (0x0002) /* Round-Robin DMA channel priorities */
+#define DMARMWDIS_L (0x0004) /* Inhibited DMA transfers during read-modify-write CPU operations */
+
+/* DMAxCTL Control Bits */
+#define DMAREQ (0x0001) /* Initiate DMA transfer with DMATSEL */
+#define DMAABORT (0x0002) /* DMA transfer aborted by NMI */
+#define DMAIE (0x0004) /* DMA interrupt enable */
+#define DMAIFG (0x0008) /* DMA interrupt flag */
+#define DMAEN (0x0010) /* DMA enable */
+#define DMALEVEL (0x0020) /* DMA level sensitive trigger select */
+#define DMASRCBYTE (0x0040) /* DMA source byte */
+#define DMADSTBYTE (0x0080) /* DMA destination byte */
+#define DMASRCINCR0 (0x0100) /* DMA source increment bit 0 */
+#define DMASRCINCR1 (0x0200) /* DMA source increment bit 1 */
+#define DMADSTINCR0 (0x0400) /* DMA destination increment bit 0 */
+#define DMADSTINCR1 (0x0800) /* DMA destination increment bit 1 */
+#define DMADT0 (0x1000) /* DMA transfer mode bit 0 */
+#define DMADT1 (0x2000) /* DMA transfer mode bit 1 */
+#define DMADT2 (0x4000) /* DMA transfer mode bit 2 */
+
+/* DMAxCTL Control Bits */
+#define DMAREQ_L (0x0001) /* Initiate DMA transfer with DMATSEL */
+#define DMAABORT_L (0x0002) /* DMA transfer aborted by NMI */
+#define DMAIE_L (0x0004) /* DMA interrupt enable */
+#define DMAIFG_L (0x0008) /* DMA interrupt flag */
+#define DMAEN_L (0x0010) /* DMA enable */
+#define DMALEVEL_L (0x0020) /* DMA level sensitive trigger select */
+#define DMASRCBYTE_L (0x0040) /* DMA source byte */
+#define DMADSTBYTE_L (0x0080) /* DMA destination byte */
+
+/* DMAxCTL Control Bits */
+#define DMASRCINCR0_H (0x0001) /* DMA source increment bit 0 */
+#define DMASRCINCR1_H (0x0002) /* DMA source increment bit 1 */
+#define DMADSTINCR0_H (0x0004) /* DMA destination increment bit 0 */
+#define DMADSTINCR1_H (0x0008) /* DMA destination increment bit 1 */
+#define DMADT0_H (0x0010) /* DMA transfer mode bit 0 */
+#define DMADT1_H (0x0020) /* DMA transfer mode bit 1 */
+#define DMADT2_H (0x0040) /* DMA transfer mode bit 2 */
+
+#define DMASWDW (0x0000) /* DMA transfer: source word to destination word */
+#define DMASBDW (0x0040) /* DMA transfer: source byte to destination word */
+#define DMASWDB (0x0080) /* DMA transfer: source word to destination byte */
+#define DMASBDB (0x00C0) /* DMA transfer: source byte to destination byte */
+
+#define DMASRCINCR_0 (0x0000) /* DMA source increment 0: source address unchanged */
+#define DMASRCINCR_1 (0x0100) /* DMA source increment 1: source address unchanged */
+#define DMASRCINCR_2 (0x0200) /* DMA source increment 2: source address decremented */
+#define DMASRCINCR_3 (0x0300) /* DMA source increment 3: source address incremented */
+
+#define DMADSTINCR_0 (0x0000) /* DMA destination increment 0: destination address unchanged */
+#define DMADSTINCR_1 (0x0400) /* DMA destination increment 1: destination address unchanged */
+#define DMADSTINCR_2 (0x0800) /* DMA destination increment 2: destination address decremented */
+#define DMADSTINCR_3 (0x0C00) /* DMA destination increment 3: destination address incremented */
+
+#define DMADT_0 (0x0000) /* DMA transfer mode 0: Single transfer */
+#define DMADT_1 (0x1000) /* DMA transfer mode 1: Block transfer */
+#define DMADT_2 (0x2000) /* DMA transfer mode 2: Burst-Block transfer */
+#define DMADT_3 (0x3000) /* DMA transfer mode 3: Burst-Block transfer */
+#define DMADT_4 (0x4000) /* DMA transfer mode 4: Repeated Single transfer */
+#define DMADT_5 (0x5000) /* DMA transfer mode 5: Repeated Block transfer */
+#define DMADT_6 (0x6000) /* DMA transfer mode 6: Repeated Burst-Block transfer */
+#define DMADT_7 (0x7000) /* DMA transfer mode 7: Repeated Burst-Block transfer */
+
+/* DMAIV Definitions */
+#define DMAIV_NONE (0x0000) /* No Interrupt pending */
+#define DMAIV_DMA0IFG (0x0002) /* DMA0IFG*/
+#define DMAIV_DMA1IFG (0x0004) /* DMA1IFG*/
+#define DMAIV_DMA2IFG (0x0006) /* DMA2IFG*/
+
+#define DMA0TSEL_0 (0x0000) /* DMA channel 0 transfer select 0: DMA_REQ (sw) */
+#define DMA0TSEL_1 (0x0001) /* DMA channel 0 transfer select 1: */
+#define DMA0TSEL_2 (0x0002) /* DMA channel 0 transfer select 2: */
+#define DMA0TSEL_3 (0x0003) /* DMA channel 0 transfer select 3: */
+#define DMA0TSEL_4 (0x0004) /* DMA channel 0 transfer select 4: */
+#define DMA0TSEL_5 (0x0005) /* DMA channel 0 transfer select 5: */
+#define DMA0TSEL_6 (0x0006) /* DMA channel 0 transfer select 6: */
+#define DMA0TSEL_7 (0x0007) /* DMA channel 0 transfer select 7: */
+#define DMA0TSEL_8 (0x0008) /* DMA channel 0 transfer select 8: */
+#define DMA0TSEL_9 (0x0009) /* DMA channel 0 transfer select 9: */
+#define DMA0TSEL_10 (0x000A) /* DMA channel 0 transfer select 10: */
+#define DMA0TSEL_11 (0x000B) /* DMA channel 0 transfer select 11: */
+#define DMA0TSEL_12 (0x000C) /* DMA channel 0 transfer select 12: */
+#define DMA0TSEL_13 (0x000D) /* DMA channel 0 transfer select 13: */
+#define DMA0TSEL_14 (0x000E) /* DMA channel 0 transfer select 14: */
+#define DMA0TSEL_15 (0x000F) /* DMA channel 0 transfer select 15: */
+#define DMA0TSEL_16 (0x0010) /* DMA channel 0 transfer select 16: */
+#define DMA0TSEL_17 (0x0011) /* DMA channel 0 transfer select 17: */
+#define DMA0TSEL_18 (0x0012) /* DMA channel 0 transfer select 18: */
+#define DMA0TSEL_19 (0x0013) /* DMA channel 0 transfer select 19: */
+#define DMA0TSEL_20 (0x0014) /* DMA channel 0 transfer select 20: */
+#define DMA0TSEL_21 (0x0015) /* DMA channel 0 transfer select 21: */
+#define DMA0TSEL_22 (0x0016) /* DMA channel 0 transfer select 22: */
+#define DMA0TSEL_23 (0x0017) /* DMA channel 0 transfer select 23: */
+#define DMA0TSEL_24 (0x0018) /* DMA channel 0 transfer select 24: */
+#define DMA0TSEL_25 (0x0019) /* DMA channel 0 transfer select 25: */
+#define DMA0TSEL_26 (0x001A) /* DMA channel 0 transfer select 26: */
+#define DMA0TSEL_27 (0x001B) /* DMA channel 0 transfer select 27: */
+#define DMA0TSEL_28 (0x001C) /* DMA channel 0 transfer select 28: */
+#define DMA0TSEL_29 (0x001D) /* DMA channel 0 transfer select 29: */
+#define DMA0TSEL_30 (0x001E) /* DMA channel 0 transfer select 30: previous DMA channel DMA2IFG */
+#define DMA0TSEL_31 (0x001F) /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */
+
+#define DMA1TSEL_0 (0x0000) /* DMA channel 1 transfer select 0: DMA_REQ (sw) */
+#define DMA1TSEL_1 (0x0100) /* DMA channel 1 transfer select 1: */
+#define DMA1TSEL_2 (0x0200) /* DMA channel 1 transfer select 2: */
+#define DMA1TSEL_3 (0x0300) /* DMA channel 1 transfer select 3: */
+#define DMA1TSEL_4 (0x0400) /* DMA channel 1 transfer select 4: */
+#define DMA1TSEL_5 (0x0500) /* DMA channel 1 transfer select 5: */
+#define DMA1TSEL_6 (0x0600) /* DMA channel 1 transfer select 6: */
+#define DMA1TSEL_7 (0x0700) /* DMA channel 1 transfer select 7: */
+#define DMA1TSEL_8 (0x0800) /* DMA channel 1 transfer select 8: */
+#define DMA1TSEL_9 (0x0900) /* DMA channel 1 transfer select 9: */
+#define DMA1TSEL_10 (0x0A00) /* DMA channel 1 transfer select 10: */
+#define DMA1TSEL_11 (0x0B00) /* DMA channel 1 transfer select 11: */
+#define DMA1TSEL_12 (0x0C00) /* DMA channel 1 transfer select 12: */
+#define DMA1TSEL_13 (0x0D00) /* DMA channel 1 transfer select 13: */
+#define DMA1TSEL_14 (0x0E00) /* DMA channel 1 transfer select 14: */
+#define DMA1TSEL_15 (0x0F00) /* DMA channel 1 transfer select 15: */
+#define DMA1TSEL_16 (0x1000) /* DMA channel 1 transfer select 16: */
+#define DMA1TSEL_17 (0x1100) /* DMA channel 1 transfer select 17: */
+#define DMA1TSEL_18 (0x1200) /* DMA channel 1 transfer select 18: */
+#define DMA1TSEL_19 (0x1300) /* DMA channel 1 transfer select 19: */
+#define DMA1TSEL_20 (0x1400) /* DMA channel 1 transfer select 20: */
+#define DMA1TSEL_21 (0x1500) /* DMA channel 1 transfer select 21: */
+#define DMA1TSEL_22 (0x1600) /* DMA channel 1 transfer select 22: */
+#define DMA1TSEL_23 (0x1700) /* DMA channel 1 transfer select 23: */
+#define DMA1TSEL_24 (0x1800) /* DMA channel 1 transfer select 24: */
+#define DMA1TSEL_25 (0x1900) /* DMA channel 1 transfer select 25: */
+#define DMA1TSEL_26 (0x1A00) /* DMA channel 1 transfer select 26: */
+#define DMA1TSEL_27 (0x1B00) /* DMA channel 1 transfer select 27: */
+#define DMA1TSEL_28 (0x1C00) /* DMA channel 1 transfer select 28: */
+#define DMA1TSEL_29 (0x1D00) /* DMA channel 1 transfer select 29: */
+#define DMA1TSEL_30 (0x1E00) /* DMA channel 1 transfer select 30: previous DMA channel DMA0IFG */
+#define DMA1TSEL_31 (0x1F00) /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */
+
+#define DMA2TSEL_0 (0x0000) /* DMA channel 2 transfer select 0: DMA_REQ (sw) */
+#define DMA2TSEL_1 (0x0001) /* DMA channel 2 transfer select 1: */
+#define DMA2TSEL_2 (0x0002) /* DMA channel 2 transfer select 2: */
+#define DMA2TSEL_3 (0x0003) /* DMA channel 2 transfer select 3: */
+#define DMA2TSEL_4 (0x0004) /* DMA channel 2 transfer select 4: */
+#define DMA2TSEL_5 (0x0005) /* DMA channel 2 transfer select 5: */
+#define DMA2TSEL_6 (0x0006) /* DMA channel 2 transfer select 6: */
+#define DMA2TSEL_7 (0x0007) /* DMA channel 2 transfer select 7: */
+#define DMA2TSEL_8 (0x0008) /* DMA channel 2 transfer select 8: */
+#define DMA2TSEL_9 (0x0009) /* DMA channel 2 transfer select 9: */
+#define DMA2TSEL_10 (0x000A) /* DMA channel 2 transfer select 10: */
+#define DMA2TSEL_11 (0x000B) /* DMA channel 2 transfer select 11: */
+#define DMA2TSEL_12 (0x000C) /* DMA channel 2 transfer select 12: */
+#define DMA2TSEL_13 (0x000D) /* DMA channel 2 transfer select 13: */
+#define DMA2TSEL_14 (0x000E) /* DMA channel 2 transfer select 14: */
+#define DMA2TSEL_15 (0x000F) /* DMA channel 2 transfer select 15: */
+#define DMA2TSEL_16 (0x0010) /* DMA channel 2 transfer select 16: */
+#define DMA2TSEL_17 (0x0011) /* DMA channel 2 transfer select 17: */
+#define DMA2TSEL_18 (0x0012) /* DMA channel 2 transfer select 18: */
+#define DMA2TSEL_19 (0x0013) /* DMA channel 2 transfer select 19: */
+#define DMA2TSEL_20 (0x0014) /* DMA channel 2 transfer select 20: */
+#define DMA2TSEL_21 (0x0015) /* DMA channel 2 transfer select 21: */
+#define DMA2TSEL_22 (0x0016) /* DMA channel 2 transfer select 22: */
+#define DMA2TSEL_23 (0x0017) /* DMA channel 2 transfer select 23: */
+#define DMA2TSEL_24 (0x0018) /* DMA channel 2 transfer select 24: */
+#define DMA2TSEL_25 (0x0019) /* DMA channel 2 transfer select 25: */
+#define DMA2TSEL_26 (0x001A) /* DMA channel 2 transfer select 26: */
+#define DMA2TSEL_27 (0x001B) /* DMA channel 2 transfer select 27: */
+#define DMA2TSEL_28 (0x001C) /* DMA channel 2 transfer select 28: */
+#define DMA2TSEL_29 (0x001D) /* DMA channel 2 transfer select 29: */
+#define DMA2TSEL_30 (0x001E) /* DMA channel 2 transfer select 30: previous DMA channel DMA1IFG */
+#define DMA2TSEL_31 (0x001F) /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */
+
+#define DMA0TSEL__DMAREQ (0x0000) /* DMA channel 0 transfer select 0: DMA_REQ (sw) */
+#define DMA0TSEL__TA0CCR0 (0x0001) /* DMA channel 0 transfer select 1: TA0CCR0 */
+#define DMA0TSEL__TA0CCR2 (0x0002) /* DMA channel 0 transfer select 2: TA0CCR2 */
+#define DMA0TSEL__TA1CCR0 (0x0003) /* DMA channel 0 transfer select 3: TA1CCR0 */
+#define DMA0TSEL__TA1CCR2 (0x0004) /* DMA channel 0 transfer select 4: TA1CCR2 */
+#define DMA0TSEL__TA2CCR0 (0x0005) /* DMA channel 0 transfer select 3: TA2CCR0 */
+#define DMA0TSEL__TA3CCR0 (0x0006) /* DMA channel 0 transfer select 4: TA3CCR0 */
+#define DMA0TSEL__TB0CCR0 (0x0007) /* DMA channel 0 transfer select 7: TB0CCR0 */
+#define DMA0TSEL__TB0CCR2 (0x0008) /* DMA channel 0 transfer select 8: TB0CCR2 */
+#define DMA0TSEL__RES9 (0x0009) /* DMA channel 0 transfer select 9: RES9 */
+#define DMA0TSEL__RES10 (0x000A) /* DMA channel 0 transfer select 10: RES10 */
+#define DMA0TSEL__AES_Trigger_0 (0x000B) /* DMA channel 0 transfer select 11: AES Trigger 0 */
+#define DMA0TSEL__AES_Trigger_1 (0x000C) /* DMA channel 0 transfer select 12: AES Trigger 1 */
+#define DMA0TSEL__AES_Trigger_2 (0x000D) /* DMA channel 0 transfer select 13: AES Trigger 2 */
+#define DMA0TSEL__UCA0RXIFG (0x000E) /* DMA channel 0 transfer select 14: UCA0RXIFG */
+#define DMA0TSEL__UCA0TXIFG (0x000F) /* DMA channel 0 transfer select 15: UCA0TXIFG */
+#define DMA0TSEL__UCA1RXIFG (0x0010) /* DMA channel 0 transfer select 16: UCA1RXIFG */
+#define DMA0TSEL__UCA1TXIFG (0x0011) /* DMA channel 0 transfer select 17: UCA1TXIFG */
+#define DMA0TSEL__UCB0RXIFG0 (0x0012) /* DMA channel 0 transfer select 18: UCB0RXIFG0 */
+#define DMA0TSEL__UCB0TXIFG0 (0x0013) /* DMA channel 0 transfer select 19: UCB0TXIFG0 */
+#define DMA0TSEL__UCB0RXIFG1 (0x0014) /* DMA channel 0 transfer select 20: UCB0RXIFG1 */
+#define DMA0TSEL__UCB0TXIFG1 (0x0015) /* DMA channel 0 transfer select 21: UCB0TXIFG1 */
+#define DMA0TSEL__UCB0RXIFG2 (0x0016) /* DMA channel 0 transfer select 22: UCB0RXIFG2 */
+#define DMA0TSEL__UCB0TXIFG2 (0x0017) /* DMA channel 0 transfer select 23: UCB0TXIFG2 */
+#define DMA0TSEL__UCB1RXIFG0 (0x0018) /* DMA channel 0 transfer select 24: UCB1RXIFG0 */
+#define DMA0TSEL__UCB1TXIFG0 (0x0019) /* DMA channel 0 transfer select 25: UCB1TXIFG0 */
+#define DMA0TSEL__ADC12IFG (0x001A) /* DMA channel 0 transfer select 26: ADC12IFG */
+#define DMA0TSEL__RES27 (0x001B) /* DMA channel 0 transfer select 27: RES27 */
+//#define DMA0TSEL__RES28 (0x001C) /* DMA channel 0 transfer select 28: RES28 */
+#define DMA0TSEL__ESI (0x001C) /* DMA channel 0 transfer select 28: ESI */
+#define DMA0TSEL__MPY (0x001D) /* DMA channel 0 transfer select 29: MPY */
+#define DMA0TSEL__DMA2IFG (0x001E) /* DMA channel 0 transfer select 30: previous DMA channel DMA2IFG */
+#define DMA0TSEL__DMAE0 (0x001F) /* DMA channel 0 transfer select 31: ext. Trigger (DMAE0) */
+
+#define DMA1TSEL__DMAREQ (0x0000) /* DMA channel 1 transfer select 0: DMA_REQ (sw) */
+#define DMA1TSEL__TA0CCR0 (0x0100) /* DMA channel 1 transfer select 1: TA0CCR0 */
+#define DMA1TSEL__TA0CCR2 (0x0200) /* DMA channel 1 transfer select 2: TA0CCR2 */
+#define DMA1TSEL__TA1CCR0 (0x0300) /* DMA channel 1 transfer select 3: TA1CCR0 */
+#define DMA1TSEL__TA1CCR2 (0x0400) /* DMA channel 1 transfer select 4: TA1CCR2 */
+#define DMA1TSEL__TA2CCR0 (0x0500) /* DMA channel 1 transfer select 5: TA2CCR0 */
+#define DMA1TSEL__TA3CCR0 (0x0600) /* DMA channel 1 transfer select 6: TA3CCR0 */
+#define DMA1TSEL__TB0CCR0 (0x0700) /* DMA channel 1 transfer select 7: TB0CCR0 */
+#define DMA1TSEL__TB0CCR2 (0x0800) /* DMA channel 1 transfer select 8: TB0CCR2 */
+#define DMA1TSEL__RES9 (0x0900) /* DMA channel 1 transfer select 9: RES9 */
+#define DMA1TSEL__RES10 (0x0A00) /* DMA channel 1 transfer select 10: RES10 */
+#define DMA1TSEL__AES_Trigger_0 (0x0B00) /* DMA channel 1 transfer select 11: AES Trigger 0 */
+#define DMA1TSEL__AES_Trigger_1 (0x0C00) /* DMA channel 1 transfer select 12: AES Trigger 1 */
+#define DMA1TSEL__AES_Trigger_2 (0x0D00) /* DMA channel 1 transfer select 13: AES Trigger 2 */
+#define DMA1TSEL__UCA0RXIFG (0x0E00) /* DMA channel 1 transfer select 14: UCA0RXIFG */
+#define DMA1TSEL__UCA0TXIFG (0x0F00) /* DMA channel 1 transfer select 15: UCA0TXIFG */
+#define DMA1TSEL__UCA1RXIFG (0x1000) /* DMA channel 1 transfer select 16: UCA1RXIFG */
+#define DMA1TSEL__UCA1TXIFG (0x1100) /* DMA channel 1 transfer select 17: UCA1TXIFG */
+#define DMA1TSEL__UCB0RXIFG0 (0x1200) /* DMA channel 1 transfer select 18: UCB0RXIFG0 */
+#define DMA1TSEL__UCB0TXIFG0 (0x1300) /* DMA channel 1 transfer select 19: UCB0TXIFG0 */
+#define DMA1TSEL__UCB0RXIFG1 (0x1400) /* DMA channel 1 transfer select 20: UCB0RXIFG1 */
+#define DMA1TSEL__UCB0TXIFG1 (0x1500) /* DMA channel 1 transfer select 21: UCB0TXIFG1 */
+#define DMA1TSEL__UCB0RXIFG2 (0x1600) /* DMA channel 1 transfer select 22: UCB0RXIFG2 */
+#define DMA1TSEL__UCB0TXIFG2 (0x1700) /* DMA channel 1 transfer select 23: UCB0TXIFG2 */
+#define DMA1TSEL__UCB1RXIFG0 (0x1800) /* DMA channel 1 transfer select 24: UCB1RXIFG0 */
+#define DMA1TSEL__UCB1TXIFG0 (0x1900) /* DMA channel 1 transfer select 25: UCB1TXIFG0 */
+#define DMA1TSEL__ADC12IFG (0x1A00) /* DMA channel 1 transfer select 26: ADC12IFG */
+#define DMA1TSEL__RES27 (0x1B00) /* DMA channel 1 transfer select 27: RES27 */
+#define DMA1TSEL__ESI (0x1C00) /* DMA channel 1 transfer select 28: ESI */
+#define DMA1TSEL__MPY (0x1D00) /* DMA channel 1 transfer select 29: MPY */
+#define DMA1TSEL__DMA0IFG (0x1E00) /* DMA channel 1 transfer select 30: previous DMA channel DMA0IFG */
+#define DMA1TSEL__DMAE0 (0x1F00) /* DMA channel 1 transfer select 31: ext. Trigger (DMAE0) */
+
+#define DMA2TSEL__DMAREQ (0x0000) /* DMA channel 2 transfer select 0: DMA_REQ (sw) */
+#define DMA2TSEL__TA0CCR0 (0x0001) /* DMA channel 2 transfer select 1: TA0CCR0 */
+#define DMA2TSEL__TA0CCR2 (0x0002) /* DMA channel 2 transfer select 2: TA0CCR2 */
+#define DMA2TSEL__TA1CCR0 (0x0003) /* DMA channel 2 transfer select 3: TA1CCR0 */
+#define DMA2TSEL__TA1CCR2 (0x0004) /* DMA channel 2 transfer select 4: TA1CCR2 */
+#define DMA2TSEL__TA2CCR0 (0x0005) /* DMA channel 2 transfer select 5: TA2CCR0 */
+#define DMA2TSEL__TA3CCR0 (0x0006) /* DMA channel 2 transfer select 6: TA3CCR0 */
+#define DMA2TSEL__TB0CCR0 (0x0007) /* DMA channel 2 transfer select 7: TB0CCR0 */
+#define DMA2TSEL__TB0CCR2 (0x0008) /* DMA channel 2 transfer select 8: TB0CCR2 */
+#define DMA2TSEL__RES9 (0x0009) /* DMA channel 2 transfer select 9: RES9 */
+#define DMA2TSEL__RES10 (0x000A) /* DMA channel 2 transfer select 10: RES10 */
+#define DMA2TSEL__AES_Trigger_0 (0x000B) /* DMA channel 2 transfer select 11: AES Trigger 0 */
+#define DMA2TSEL__AES_Trigger_1 (0x000C) /* DMA channel 2 transfer select 12: AES Trigger 1 */
+#define DMA2TSEL__AES_Trigger_2 (0x000D) /* DMA channel 2 transfer select 13: AES Trigger 2 */
+#define DMA2TSEL__UCA0RXIFG (0x000E) /* DMA channel 2 transfer select 14: UCA0RXIFG */
+#define DMA2TSEL__UCA0TXIFG (0x000F) /* DMA channel 2 transfer select 15: UCA0TXIFG */
+#define DMA2TSEL__UCA1RXIFG (0x0010) /* DMA channel 2 transfer select 16: UCA1RXIFG */
+#define DMA2TSEL__UCA1TXIFG (0x0011) /* DMA channel 2 transfer select 17: UCA1TXIFG */
+#define DMA2TSEL__UCB0RXIFG0 (0x0012) /* DMA channel 2 transfer select 18: UCB0RXIFG0 */
+#define DMA2TSEL__UCB0TXIFG0 (0x0013) /* DMA channel 2 transfer select 19: UCB0TXIFG0 */
+#define DMA2TSEL__UCB0RXIFG1 (0x0014) /* DMA channel 2 transfer select 20: UCB0RXIFG1 */
+#define DMA2TSEL__UCB0TXIFG1 (0x0015) /* DMA channel 2 transfer select 21: UCB0TXIFG1 */
+#define DMA2TSEL__UCB0RXIFG2 (0x0016) /* DMA channel 2 transfer select 22: UCB0RXIFG2 */
+#define DMA2TSEL__UCB0TXIFG2 (0x0017) /* DMA channel 2 transfer select 23: UCB0TXIFG2 */
+#define DMA2TSEL__UCB1RXIFG0 (0x0018) /* DMA channel 2 transfer select 24: UCB1RXIFG0 */
+#define DMA2TSEL__UCB1TXIFG0 (0x0019) /* DMA channel 2 transfer select 25: UCB1TXIFG0 */
+#define DMA2TSEL__ADC12IFG (0x001A) /* DMA channel 2 transfer select 26: ADC12IFG */
+#define DMA2TSEL__RES27 (0x001B) /* DMA channel 2 transfer select 27: RES27 */
+#define DMA2TSEL__ESI (0x001C) /* DMA channel 2 transfer select 28: ESI */
+#define DMA2TSEL__MPY (0x001D) /* DMA channel 2 transfer select 29: MPY */
+#define DMA2TSEL__DMA1IFG (0x001E) /* DMA channel 2 transfer select 30: previous DMA channel DMA1IFG */
+#define DMA2TSEL__DMAE0 (0x001F) /* DMA channel 2 transfer select 31: ext. Trigger (DMAE0) */
+
+/************************************************************
+* EXTENDED SCAN INTERFACE
+************************************************************/
+#define __MSP430_HAS_ESI__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_ESI__ 0x0D00
+#define ESI_BASE __MSP430_BASEADDRESS_ESI__
+
+sfr_w(ESIDEBUG1); /* ESI debug register 1 */
+sfr_b(ESIDEBUG1_L); /* ESI debug register 1 */
+sfr_b(ESIDEBUG1_H); /* ESI debug register 1 */
+sfr_w(ESIDEBUG2); /* ESI debug register 2 */
+sfr_b(ESIDEBUG2_L); /* ESI debug register 2 */
+sfr_b(ESIDEBUG2_H); /* ESI debug register 2 */
+sfr_w(ESIDEBUG3); /* ESI debug register 3 */
+sfr_b(ESIDEBUG3_L); /* ESI debug register 3 */
+sfr_b(ESIDEBUG3_H); /* ESI debug register 3 */
+sfr_w(ESIDEBUG4); /* ESI debug register 4 */
+sfr_b(ESIDEBUG4_L); /* ESI debug register 4 */
+sfr_b(ESIDEBUG4_H); /* ESI debug register 4 */
+sfr_w(ESIDEBUG5); /* ESI debug register 5 */
+sfr_b(ESIDEBUG5_L); /* ESI debug register 5 */
+sfr_b(ESIDEBUG5_H); /* ESI debug register 5 */
+sfr_w(ESICNT0); /* ESI PSM counter 0 */
+sfr_b(ESICNT0_L); /* ESI PSM counter 0 */
+sfr_b(ESICNT0_H); /* ESI PSM counter 0 */
+sfr_w(ESICNT1); /* ESI PSM counter 1 */
+sfr_b(ESICNT1_L); /* ESI PSM counter 1 */
+sfr_b(ESICNT1_H); /* ESI PSM counter 1 */
+sfr_w(ESICNT2); /* ESI PSM counter 2 */
+sfr_b(ESICNT2_L); /* ESI PSM counter 2 */
+sfr_b(ESICNT2_H); /* ESI PSM counter 2 */
+sfr_w(ESICNT3); /* ESI oscillator counter register */
+sfr_b(ESICNT3_L); /* ESI oscillator counter register */
+sfr_b(ESICNT3_H); /* ESI oscillator counter register */
+sfr_w(ESIIV); /* ESI interrupt vector */
+sfr_b(ESIIV_L); /* ESI interrupt vector */
+sfr_b(ESIIV_H); /* ESI interrupt vector */
+sfr_w(ESIINT1); /* ESI interrupt register 1 */
+sfr_b(ESIINT1_L); /* ESI interrupt register 1 */
+sfr_b(ESIINT1_H); /* ESI interrupt register 1 */
+sfr_w(ESIINT2); /* ESI interrupt register 2 */
+sfr_b(ESIINT2_L); /* ESI interrupt register 2 */
+sfr_b(ESIINT2_H); /* ESI interrupt register 2 */
+sfr_w(ESIAFE); /* ESI AFE control register */
+sfr_b(ESIAFE_L); /* ESI AFE control register */
+sfr_b(ESIAFE_H); /* ESI AFE control register */
+sfr_w(ESIPPU); /* ESI PPU control register */
+sfr_b(ESIPPU_L); /* ESI PPU control register */
+sfr_b(ESIPPU_H); /* ESI PPU control register */
+sfr_w(ESITSM); /* ESI TSM control register */
+sfr_b(ESITSM_L); /* ESI TSM control register */
+sfr_b(ESITSM_H); /* ESI TSM control register */
+sfr_w(ESIPSM); /* ESI PSM control register */
+sfr_b(ESIPSM_L); /* ESI PSM control register */
+sfr_b(ESIPSM_H); /* ESI PSM control register */
+sfr_w(ESIOSC); /* ESI oscillator control register*/
+sfr_b(ESIOSC_L); /* ESI oscillator control register*/
+sfr_b(ESIOSC_H); /* ESI oscillator control register*/
+sfr_w(ESICTL); /* ESI control register */
+sfr_b(ESICTL_L); /* ESI control register */
+sfr_b(ESICTL_H); /* ESI control register */
+sfr_w(ESITHR1); /* ESI PSM Counter Threshold 1 register */
+sfr_b(ESITHR1_L); /* ESI PSM Counter Threshold 1 register */
+sfr_b(ESITHR1_H); /* ESI PSM Counter Threshold 1 register */
+sfr_w(ESITHR2); /* ESI PSM Counter Threshold 2 register */
+sfr_b(ESITHR2_L); /* ESI PSM Counter Threshold 2 register */
+sfr_b(ESITHR2_H); /* ESI PSM Counter Threshold 2 register */
+sfr_w(ESIDAC1R0); /* ESI DAC1 register 0 */
+sfr_b(ESIDAC1R0_L); /* ESI DAC1 register 0 */
+sfr_b(ESIDAC1R0_H); /* ESI DAC1 register 0 */
+sfr_w(ESIDAC1R1); /* ESI DAC1 register 1 */
+sfr_b(ESIDAC1R1_L); /* ESI DAC1 register 1 */
+sfr_b(ESIDAC1R1_H); /* ESI DAC1 register 1 */
+sfr_w(ESIDAC1R2); /* ESI DAC1 register 2 */
+sfr_b(ESIDAC1R2_L); /* ESI DAC1 register 2 */
+sfr_b(ESIDAC1R2_H); /* ESI DAC1 register 2 */
+sfr_w(ESIDAC1R3); /* ESI DAC1 register 3 */
+sfr_b(ESIDAC1R3_L); /* ESI DAC1 register 3 */
+sfr_b(ESIDAC1R3_H); /* ESI DAC1 register 3 */
+sfr_w(ESIDAC1R4); /* ESI DAC1 register 4 */
+sfr_b(ESIDAC1R4_L); /* ESI DAC1 register 4 */
+sfr_b(ESIDAC1R4_H); /* ESI DAC1 register 4 */
+sfr_w(ESIDAC1R5); /* ESI DAC1 register 5 */
+sfr_b(ESIDAC1R5_L); /* ESI DAC1 register 5 */
+sfr_b(ESIDAC1R5_H); /* ESI DAC1 register 5 */
+sfr_w(ESIDAC1R6); /* ESI DAC1 register 6 */
+sfr_b(ESIDAC1R6_L); /* ESI DAC1 register 6 */
+sfr_b(ESIDAC1R6_H); /* ESI DAC1 register 6 */
+sfr_w(ESIDAC1R7); /* ESI DAC1 register 7 */
+sfr_b(ESIDAC1R7_L); /* ESI DAC1 register 7 */
+sfr_b(ESIDAC1R7_H); /* ESI DAC1 register 7 */
+sfr_w(ESIDAC2R0); /* ESI DAC2 register 0 */
+sfr_b(ESIDAC2R0_L); /* ESI DAC2 register 0 */
+sfr_b(ESIDAC2R0_H); /* ESI DAC2 register 0 */
+sfr_w(ESIDAC2R1); /* ESI DAC2 register 1 */
+sfr_b(ESIDAC2R1_L); /* ESI DAC2 register 1 */
+sfr_b(ESIDAC2R1_H); /* ESI DAC2 register 1 */
+sfr_w(ESIDAC2R2); /* ESI DAC2 register 2 */
+sfr_b(ESIDAC2R2_L); /* ESI DAC2 register 2 */
+sfr_b(ESIDAC2R2_H); /* ESI DAC2 register 2 */
+sfr_w(ESIDAC2R3); /* ESI DAC2 register 3 */
+sfr_b(ESIDAC2R3_L); /* ESI DAC2 register 3 */
+sfr_b(ESIDAC2R3_H); /* ESI DAC2 register 3 */
+sfr_w(ESIDAC2R4); /* ESI DAC2 register 4 */
+sfr_b(ESIDAC2R4_L); /* ESI DAC2 register 4 */
+sfr_b(ESIDAC2R4_H); /* ESI DAC2 register 4 */
+sfr_w(ESIDAC2R5); /* ESI DAC2 register 5 */
+sfr_b(ESIDAC2R5_L); /* ESI DAC2 register 5 */
+sfr_b(ESIDAC2R5_H); /* ESI DAC2 register 5 */
+sfr_w(ESIDAC2R6); /* ESI DAC2 register 6 */
+sfr_b(ESIDAC2R6_L); /* ESI DAC2 register 6 */
+sfr_b(ESIDAC2R6_H); /* ESI DAC2 register 6 */
+sfr_w(ESIDAC2R7); /* ESI DAC2 register 7 */
+sfr_b(ESIDAC2R7_L); /* ESI DAC2 register 7 */
+sfr_b(ESIDAC2R7_H); /* ESI DAC2 register 7 */
+sfr_w(ESITSM0); /* ESI TSM 0 */
+sfr_b(ESITSM0_L); /* ESI TSM 0 */
+sfr_b(ESITSM0_H); /* ESI TSM 0 */
+sfr_w(ESITSM1); /* ESI TSM 1 */
+sfr_b(ESITSM1_L); /* ESI TSM 1 */
+sfr_b(ESITSM1_H); /* ESI TSM 1 */
+sfr_w(ESITSM2); /* ESI TSM 2 */
+sfr_b(ESITSM2_L); /* ESI TSM 2 */
+sfr_b(ESITSM2_H); /* ESI TSM 2 */
+sfr_w(ESITSM3); /* ESI TSM 3 */
+sfr_b(ESITSM3_L); /* ESI TSM 3 */
+sfr_b(ESITSM3_H); /* ESI TSM 3 */
+sfr_w(ESITSM4); /* ESI TSM 4 */
+sfr_b(ESITSM4_L); /* ESI TSM 4 */
+sfr_b(ESITSM4_H); /* ESI TSM 4 */
+sfr_w(ESITSM5); /* ESI TSM 5 */
+sfr_b(ESITSM5_L); /* ESI TSM 5 */
+sfr_b(ESITSM5_H); /* ESI TSM 5 */
+sfr_w(ESITSM6); /* ESI TSM 6 */
+sfr_b(ESITSM6_L); /* ESI TSM 6 */
+sfr_b(ESITSM6_H); /* ESI TSM 6 */
+sfr_w(ESITSM7); /* ESI TSM 7 */
+sfr_b(ESITSM7_L); /* ESI TSM 7 */
+sfr_b(ESITSM7_H); /* ESI TSM 7 */
+sfr_w(ESITSM8); /* ESI TSM 8 */
+sfr_b(ESITSM8_L); /* ESI TSM 8 */
+sfr_b(ESITSM8_H); /* ESI TSM 8 */
+sfr_w(ESITSM9); /* ESI TSM 9 */
+sfr_b(ESITSM9_L); /* ESI TSM 9 */
+sfr_b(ESITSM9_H); /* ESI TSM 9 */
+sfr_w(ESITSM10); /* ESI TSM 10 */
+sfr_b(ESITSM10_L); /* ESI TSM 10 */
+sfr_b(ESITSM10_H); /* ESI TSM 10 */
+sfr_w(ESITSM11); /* ESI TSM 11 */
+sfr_b(ESITSM11_L); /* ESI TSM 11 */
+sfr_b(ESITSM11_H); /* ESI TSM 11 */
+sfr_w(ESITSM12); /* ESI TSM 12 */
+sfr_b(ESITSM12_L); /* ESI TSM 12 */
+sfr_b(ESITSM12_H); /* ESI TSM 12 */
+sfr_w(ESITSM13); /* ESI TSM 13 */
+sfr_b(ESITSM13_L); /* ESI TSM 13 */
+sfr_b(ESITSM13_H); /* ESI TSM 13 */
+sfr_w(ESITSM14); /* ESI TSM 14 */
+sfr_b(ESITSM14_L); /* ESI TSM 14 */
+sfr_b(ESITSM14_H); /* ESI TSM 14 */
+sfr_w(ESITSM15); /* ESI TSM 15 */
+sfr_b(ESITSM15_L); /* ESI TSM 15 */
+sfr_b(ESITSM15_H); /* ESI TSM 15 */
+sfr_w(ESITSM16); /* ESI TSM 16 */
+sfr_b(ESITSM16_L); /* ESI TSM 16 */
+sfr_b(ESITSM16_H); /* ESI TSM 16 */
+sfr_w(ESITSM17); /* ESI TSM 17 */
+sfr_b(ESITSM17_L); /* ESI TSM 17 */
+sfr_b(ESITSM17_H); /* ESI TSM 17 */
+sfr_w(ESITSM18); /* ESI TSM 18 */
+sfr_b(ESITSM18_L); /* ESI TSM 18 */
+sfr_b(ESITSM18_H); /* ESI TSM 18 */
+sfr_w(ESITSM19); /* ESI TSM 19 */
+sfr_b(ESITSM19_L); /* ESI TSM 19 */
+sfr_b(ESITSM19_H); /* ESI TSM 19 */
+sfr_w(ESITSM20); /* ESI TSM 20 */
+sfr_b(ESITSM20_L); /* ESI TSM 20 */
+sfr_b(ESITSM20_H); /* ESI TSM 20 */
+sfr_w(ESITSM21); /* ESI TSM 21 */
+sfr_b(ESITSM21_L); /* ESI TSM 21 */
+sfr_b(ESITSM21_H); /* ESI TSM 21 */
+sfr_w(ESITSM22); /* ESI TSM 22 */
+sfr_b(ESITSM22_L); /* ESI TSM 22 */
+sfr_b(ESITSM22_H); /* ESI TSM 22 */
+sfr_w(ESITSM23); /* ESI TSM 23 */
+sfr_b(ESITSM23_L); /* ESI TSM 23 */
+sfr_b(ESITSM23_H); /* ESI TSM 23 */
+sfr_w(ESITSM24); /* ESI TSM 24 */
+sfr_b(ESITSM24_L); /* ESI TSM 24 */
+sfr_b(ESITSM24_H); /* ESI TSM 24 */
+sfr_w(ESITSM25); /* ESI TSM 25 */
+sfr_b(ESITSM25_L); /* ESI TSM 25 */
+sfr_b(ESITSM25_H); /* ESI TSM 25 */
+sfr_w(ESITSM26); /* ESI TSM 26 */
+sfr_b(ESITSM26_L); /* ESI TSM 26 */
+sfr_b(ESITSM26_H); /* ESI TSM 26 */
+sfr_w(ESITSM27); /* ESI TSM 27 */
+sfr_b(ESITSM27_L); /* ESI TSM 27 */
+sfr_b(ESITSM27_H); /* ESI TSM 27 */
+sfr_w(ESITSM28); /* ESI TSM 28 */
+sfr_b(ESITSM28_L); /* ESI TSM 28 */
+sfr_b(ESITSM28_H); /* ESI TSM 28 */
+sfr_w(ESITSM29); /* ESI TSM 29 */
+sfr_b(ESITSM29_L); /* ESI TSM 29 */
+sfr_b(ESITSM29_H); /* ESI TSM 29 */
+sfr_w(ESITSM30); /* ESI TSM 30 */
+sfr_b(ESITSM30_L); /* ESI TSM 30 */
+sfr_b(ESITSM30_H); /* ESI TSM 30 */
+sfr_w(ESITSM31); /* ESI TSM 31 */
+sfr_b(ESITSM31_L); /* ESI TSM 31 */
+sfr_b(ESITSM31_H); /* ESI TSM 31 */
+
+/* ESIIV Control Bits */
+
+#define ESIIV_NONE (0x0000) /* No ESI Interrupt Pending */
+#define ESIIV_ESIIFG1 (0x0002) /* rising edge of the ESISTOP(tsm) */
+#define ESIIV_ESIIFG0 (0x0004) /* ESIOUT0 to ESIOUT3 conditions selected by ESIIFGSETx bits */
+#define ESIIV_ESIIFG8 (0x0006) /* ESIOUT4 to ESIOUT7 conditions selected by ESIIFGSET2x bits */
+#define ESIIV_ESIIFG3 (0x0008) /* ESICNT1 counter conditions selected with the ESITHR1 and ESITHR2 registers */
+#define ESIIV_ESIIFG6 (0x000A) /* PSM transitions to a state with a Q7 bit */
+#define ESIIV_ESIIFG5 (0x000C) /* PSM transitions to a state with a Q6 bit */
+#define ESIIV_ESIIFG4 (0x000E) /* ESICNT2 counter conditions selected with the ESIIS2x bits */
+#define ESIIV_ESIIFG7 (0x0010) /* ESICNT0 counter conditions selected with the ESIIS0x bits */
+#define ESIIV_ESIIFG2 (0x0012) /* start of a TSM sequence */
+
+/* ESIINT1 Control Bits */
+#define ESIIFGSET22 (0x8000) /* ESIIFG8 interrupt flag source */
+#define ESIIFGSET21 (0x4000) /* ESIIFG8 interrupt flag source */
+#define ESIIFGSET20 (0x2000) /* ESIIFG8 interrupt flag source */
+#define ESIIFGSET12 (0x1000) /* ESIIFG0 interrupt flag source */
+#define ESIIFGSET11 (0x0800) /* ESIIFG0 interrupt flag source */
+#define ESIIFGSET10 (0x0400) /* ESIIFG0 interrupt flag source */
+#define ESIIE8 (0x0100) /* Interrupt enable */
+#define ESIIE7 (0x0080) /* Interrupt enable */
+#define ESIIE6 (0x0040) /* Interrupt enable */
+#define ESIIE5 (0x0020) /* Interrupt enable */
+#define ESIIE4 (0x0010) /* Interrupt enable */
+#define ESIIE3 (0x0008) /* Interrupt enable */
+#define ESIIE2 (0x0004) /* Interrupt enable */
+#define ESIIE1 (0x0002) /* Interrupt enable */
+#define ESIIE0 (0x0001) /* Interrupt enable */
+
+/* ESIINT1 Control Bits */
+#define ESIIE7_L (0x0080) /* Interrupt enable */
+#define ESIIE6_L (0x0040) /* Interrupt enable */
+#define ESIIE5_L (0x0020) /* Interrupt enable */
+#define ESIIE4_L (0x0010) /* Interrupt enable */
+#define ESIIE3_L (0x0008) /* Interrupt enable */
+#define ESIIE2_L (0x0004) /* Interrupt enable */
+#define ESIIE1_L (0x0002) /* Interrupt enable */
+#define ESIIE0_L (0x0001) /* Interrupt enable */
+
+/* ESIINT1 Control Bits */
+#define ESIIFGSET22_H (0x0080) /* ESIIFG8 interrupt flag source */
+#define ESIIFGSET21_H (0x0040) /* ESIIFG8 interrupt flag source */
+#define ESIIFGSET20_H (0x0020) /* ESIIFG8 interrupt flag source */
+#define ESIIFGSET12_H (0x0010) /* ESIIFG0 interrupt flag source */
+#define ESIIFGSET11_H (0x0008) /* ESIIFG0 interrupt flag source */
+#define ESIIFGSET10_H (0x0004) /* ESIIFG0 interrupt flag source */
+#define ESIIE8_H (0x0001) /* Interrupt enable */
+
+#define ESIIFGSET2_0 (0x0000) /* ESIIFG8 is set when ESIOUT4 is set */
+#define ESIIFGSET2_1 (0x2000) /* ESIIFG8 is set when ESIOUT4 is reset */
+#define ESIIFGSET2_2 (0x4000) /* ESIIFG8 is set when ESIOUT5 is set */
+#define ESIIFGSET2_3 (0x6000) /* ESIIFG8 is set when ESIOUT5 is reset */
+#define ESIIFGSET2_4 (0x8000) /* ESIIFG8 is set when ESIOUT6 is set */
+#define ESIIFGSET2_5 (0xA000) /* ESIIFG8 is set when ESIOUT6 is reset */
+#define ESIIFGSET2_6 (0xC000) /* ESIIFG8 is set when ESIOUT7 is set */
+#define ESIIFGSET2_7 (0xE000) /* ESIIFG8 is set when ESIOUT7 is reset */
+#define ESIIFGSET1_0 (0x0000) /* ESIIFG0 is set when ESIOUT0 is set */
+#define ESIIFGSET1_1 (0x0400) /* ESIIFG0 is set when ESIOUT0 is reset */
+#define ESIIFGSET1_2 (0x0800) /* ESIIFG0 is set when ESIOUT1 is set */
+#define ESIIFGSET1_3 (0x0C00) /* ESIIFG0 is set when ESIOUT1 is reset */
+#define ESIIFGSET1_4 (0x1000) /* ESIIFG0 is set when ESIOUT2 is set */
+#define ESIIFGSET1_5 (0x1400) /* ESIIFG0 is set when ESIOUT2 is reset */
+#define ESIIFGSET1_6 (0x1800) /* ESIIFG0 is set when ESIOUT3 is set */
+#define ESIIFGSET1_7 (0x1C00) /* ESIIFG0 is set when ESIOUT3 is reset */
+
+/* ESIINT2 Control Bits */
+#define ESIIS21 (0x4000) /* SIFIFG4 interrupt flag source */
+#define ESIIS20 (0x2000) /* SIFIFG4 interrupt flag source */
+#define ESIIS01 (0x0800) /* SIFIFG7 interrupt flag source */
+#define ESIIS00 (0x0400) /* SIFIFG7 interrupt flag source */
+#define ESIIFG8 (0x0100) /* ESIIFG8 interrupt pending */
+#define ESIIFG7 (0x0080) /* ESIIFG7 interrupt pending */
+#define ESIIFG6 (0x0040) /* ESIIFG6 interrupt pending */
+#define ESIIFG5 (0x0020) /* ESIIFG5 interrupt pending */
+#define ESIIFG4 (0x0010) /* ESIIFG4 interrupt pending */
+#define ESIIFG3 (0x0008) /* ESIIFG3 interrupt pending */
+#define ESIIFG2 (0x0004) /* ESIIFG2 interrupt pending */
+#define ESIIFG1 (0x0002) /* ESIIFG1 interrupt pending */
+#define ESIIFG0 (0x0001) /* ESIIFG0 interrupt pending */
+
+/* ESIINT2 Control Bits */
+#define ESIIFG7_L (0x0080) /* ESIIFG7 interrupt pending */
+#define ESIIFG6_L (0x0040) /* ESIIFG6 interrupt pending */
+#define ESIIFG5_L (0x0020) /* ESIIFG5 interrupt pending */
+#define ESIIFG4_L (0x0010) /* ESIIFG4 interrupt pending */
+#define ESIIFG3_L (0x0008) /* ESIIFG3 interrupt pending */
+#define ESIIFG2_L (0x0004) /* ESIIFG2 interrupt pending */
+#define ESIIFG1_L (0x0002) /* ESIIFG1 interrupt pending */
+#define ESIIFG0_L (0x0001) /* ESIIFG0 interrupt pending */
+
+/* ESIINT2 Control Bits */
+#define ESIIS21_H (0x0040) /* SIFIFG4 interrupt flag source */
+#define ESIIS20_H (0x0020) /* SIFIFG4 interrupt flag source */
+#define ESIIS01_H (0x0008) /* SIFIFG7 interrupt flag source */
+#define ESIIS00_H (0x0004) /* SIFIFG7 interrupt flag source */
+#define ESIIFG8_H (0x0001) /* ESIIFG8 interrupt pending */
+
+#define ESIIS2_0 (0x0000) /* SIFIFG4 interrupt flag source: SIFCNT2 */
+#define ESIIS2_1 (0x2000) /* SIFIFG4 interrupt flag source: SIFCNT2 MOD 4 */
+#define ESIIS2_2 (0x4000) /* SIFIFG4 interrupt flag source: SIFCNT2 MOD 256 */
+#define ESIIS2_3 (0x6000) /* SIFIFG4 interrupt flag source: SIFCNT2 decrements from 01h to 00h */
+#define ESIIS0_0 (0x0000) /* SIFIFG7 interrupt flag source: SIFCNT0 */
+#define ESIIS0_1 (0x0400) /* SIFIFG7 interrupt flag source: SIFCNT0 MOD 4 */
+#define ESIIS0_2 (0x0800) /* SIFIFG7 interrupt flag source: SIFCNT0 MOD 256 */
+#define ESIIS0_3 (0x0C00) /* SIFIFG7 interrupt flag source: SIFCNT0 increments from FFFFh to 00h */
+
+/* ESIAFE Control Bits */
+#define ESIDAC2EN (0x0800) /* Enable ESIDAC(tsm) control for DAC in AFE2 */
+#define ESICA2EN (0x0400) /* Enable ESICA(tsm) control for comparator in AFE2 */
+#define ESICA2INV (0x0200) /* Invert AFE2's comparator output */
+#define ESICA1INV (0x0100) /* Invert AFE1's comparator output */
+#define ESICA2X (0x0080) /* AFE2's comparator input select */
+#define ESICA1X (0x0040) /* AFE1's comparator input select */
+#define ESICISEL (0x0020) /* Comparator input select for AFE1 only */
+#define ESICACI3 (0x0010) /* Comparator input select for AFE1 only */
+#define ESISHTSM (0x0008) /* Sample-and-hold ESIVSS select */
+#define ESIVMIDEN (0x0004) /* Mid-voltage generator */
+#define ESISH (0x0002) /* Sample-and-hold enable */
+#define ESITEN (0x0001) /* Excitation enable */
+
+/* ESIAFE Control Bits */
+#define ESICA2X_L (0x0080) /* AFE2's comparator input select */
+#define ESICA1X_L (0x0040) /* AFE1's comparator input select */
+#define ESICISEL_L (0x0020) /* Comparator input select for AFE1 only */
+#define ESICACI3_L (0x0010) /* Comparator input select for AFE1 only */
+#define ESISHTSM_L (0x0008) /* Sample-and-hold ESIVSS select */
+#define ESIVMIDEN_L (0x0004) /* Mid-voltage generator */
+#define ESISH_L (0x0002) /* Sample-and-hold enable */
+#define ESITEN_L (0x0001) /* Excitation enable */
+
+/* ESIAFE Control Bits */
+#define ESIDAC2EN_H (0x0008) /* Enable ESIDAC(tsm) control for DAC in AFE2 */
+#define ESICA2EN_H (0x0004) /* Enable ESICA(tsm) control for comparator in AFE2 */
+#define ESICA2INV_H (0x0002) /* Invert AFE2's comparator output */
+#define ESICA1INV_H (0x0001) /* Invert AFE1's comparator output */
+
+#define ESIVSS (0x0008) /* legacy define: Sample-and-hold ESIVSS select */
+#define ESIVCC2 (0x0004) /* legacy define: Mid-voltage generator */
+
+/* ESIPPU Control Bits */
+#define ESITCHOUT1 (0x0200) /* Latched AFE1 comparator output for test channel 1 */
+#define ESITCHOUT0 (0x0100) /* Lachted AFE1 comparator output for test channel 0 */
+#define ESIOUT7 (0x0080) /* Latched AFE2 comparator output when ESICH3 input is selected */
+#define ESIOUT6 (0x0040) /* Latched AFE2 comparator output when ESICH2 input is selected */
+#define ESIOUT5 (0x0020) /* Latched AFE2 comparator output when ESICH1 input is selected */
+#define ESIOUT4 (0x0010) /* Latched AFE2 comparator output when ESICH0 input is selected */
+#define ESIOUT3 (0x0008) /* Latched AFE1 comparator output when ESICH3 input is selected */
+#define ESIOUT2 (0x0004) /* Latched AFE1 comparator output when ESICH2 input is selected */
+#define ESIOUT1 (0x0002) /* Latched AFE1 comparator output when ESICH1 input is selected */
+#define ESIOUT0 (0x0001) /* Latched AFE1 comparator output when ESICH0 input is selected */
+
+/* ESIPPU Control Bits */
+#define ESIOUT7_L (0x0080) /* Latched AFE2 comparator output when ESICH3 input is selected */
+#define ESIOUT6_L (0x0040) /* Latched AFE2 comparator output when ESICH2 input is selected */
+#define ESIOUT5_L (0x0020) /* Latched AFE2 comparator output when ESICH1 input is selected */
+#define ESIOUT4_L (0x0010) /* Latched AFE2 comparator output when ESICH0 input is selected */
+#define ESIOUT3_L (0x0008) /* Latched AFE1 comparator output when ESICH3 input is selected */
+#define ESIOUT2_L (0x0004) /* Latched AFE1 comparator output when ESICH2 input is selected */
+#define ESIOUT1_L (0x0002) /* Latched AFE1 comparator output when ESICH1 input is selected */
+#define ESIOUT0_L (0x0001) /* Latched AFE1 comparator output when ESICH0 input is selected */
+
+/* ESIPPU Control Bits */
+#define ESITCHOUT1_H (0x0002) /* Latched AFE1 comparator output for test channel 1 */
+#define ESITCHOUT0_H (0x0001) /* Lachted AFE1 comparator output for test channel 0 */
+
+/* ESITSM Control Bits */
+#define ESICLKAZSEL (0x4000) /* Functionality selection of ESITSMx bit5 */
+#define ESITSMTRG1 (0x2000) /* TSM start trigger selection */
+#define ESITSMTRG0 (0x1000) /* TSM start trigger selection */
+#define ESISTART (0x0800) /* TSM software start trigger */
+#define ESITSMRP (0x0400) /* TSM repeat modee */
+#define ESIDIV3B2 (0x0200) /* TSM start trigger ACLK divider */
+#define ESIDIV3B1 (0x0100) /* TSM start trigger ACLK divider */
+#define ESIDIV3B0 (0x0080) /* TSM start trigger ACLK divider */
+#define ESIDIV3A2 (0x0040) /* TSM start trigger ACLK divider */
+#define ESIDIV3A1 (0x0020) /* TSM start trigger ACLK divider */
+#define ESIDIV3A0 (0x0010) /* TSM start trigger ACLK divider */
+#define ESIDIV21 (0x0008) /* ACLK divider */
+#define ESIDIV20 (0x0004) /* ACLK divider */
+#define ESIDIV11 (0x0002) /* TSM SMCLK divider */
+#define ESIDIV10 (0x0001) /* TSM SMCLK divider */
+
+/* ESITSM Control Bits */
+#define ESIDIV3B0_L (0x0080) /* TSM start trigger ACLK divider */
+#define ESIDIV3A2_L (0x0040) /* TSM start trigger ACLK divider */
+#define ESIDIV3A1_L (0x0020) /* TSM start trigger ACLK divider */
+#define ESIDIV3A0_L (0x0010) /* TSM start trigger ACLK divider */
+#define ESIDIV21_L (0x0008) /* ACLK divider */
+#define ESIDIV20_L (0x0004) /* ACLK divider */
+#define ESIDIV11_L (0x0002) /* TSM SMCLK divider */
+#define ESIDIV10_L (0x0001) /* TSM SMCLK divider */
+
+/* ESITSM Control Bits */
+#define ESICLKAZSEL_H (0x0040) /* Functionality selection of ESITSMx bit5 */
+#define ESITSMTRG1_H (0x0020) /* TSM start trigger selection */
+#define ESITSMTRG0_H (0x0010) /* TSM start trigger selection */
+#define ESISTART_H (0x0008) /* TSM software start trigger */
+#define ESITSMRP_H (0x0004) /* TSM repeat modee */
+#define ESIDIV3B2_H (0x0002) /* TSM start trigger ACLK divider */
+#define ESIDIV3B1_H (0x0001) /* TSM start trigger ACLK divider */
+
+#define ESITSMTRG_0 (0x0000) /* Halt mode */
+#define ESITSMTRG_1 (0x1000) /* TSM start trigger ACLK divider */
+#define ESITSMTRG_2 (0x2000) /* Software trigger for TSM */
+#define ESITSMTRG_3 (0x3000) /* Either the ACLK divider or the ESISTART biT */
+#define ESIDIV3B_0 (0x0000) /* TSM start trigger ACLK divider */
+#define ESIDIV3B_1 (0x0080) /* TSM start trigger ACLK divider */
+#define ESIDIV3B_2 (0x0100) /* TSM start trigger ACLK divider */
+#define ESIDIV3B_3 (0x0180) /* TSM start trigger ACLK divider */
+#define ESIDIV3B_4 (0x0200) /* TSM start trigger ACLK divider */
+#define ESIDIV3B_5 (0x0280) /* TSM start trigger ACLK divider */
+#define ESIDIV3B_6 (0x0300) /* TSM start trigger ACLK divider */
+#define ESIDIV3B_7 (0x0380) /* TSM start trigger ACLK divider */
+#define ESIDIV3A_0 (0x0000) /* TSM start trigger ACLK divider */
+#define ESIDIV3A_1 (0x0010) /* TSM start trigger ACLK divider */
+#define ESIDIV3A_2 (0x0020) /* TSM start trigger ACLK divider */
+#define ESIDIV3A_3 (0x0030) /* TSM start trigger ACLK divider */
+#define ESIDIV3A_4 (0x0040) /* TSM start trigger ACLK divider */
+#define ESIDIV3A_5 (0x0050) /* TSM start trigger ACLK divider */
+#define ESIDIV3A_6 (0x0060) /* TSM start trigger ACLK divider */
+#define ESIDIV3A_7 (0x0070) /* TSM start trigger ACLK divider */
+#define ESIDIV2_0 (0x0000) /* ACLK divider mode: 0 */
+#define ESIDIV2_1 (0x0004) /* ACLK divider mode: 1 */
+#define ESIDIV2_2 (0x0008) /* ACLK divider mode: 2 */
+#define ESIDIV2_3 (0x000C) /* ACLK divider mode: 3 */
+#define ESIDIV2__1 (0x0000) /* ACLK divider = /1 */
+#define ESIDIV2__2 (0x0004) /* ACLK divider = /2 */
+#define ESIDIV2__4 (0x0008) /* ACLK divider = /4 */
+#define ESIDIV2__8 (0x000C) /* ACLK divider = /8 */
+#define ESIDIV1_0 (0x0000) /* TSM SMCLK/ESIOSC divider mode: 0 */
+#define ESIDIV1_1 (0x0001) /* TSM SMCLK/ESIOSC divider mode: 1 */
+#define ESIDIV1_2 (0x0002) /* TSM SMCLK/ESIOSC divider mode: 2 */
+#define ESIDIV1_3 (0x0003) /* TSM SMCLK/ESIOSC divider mode: 3 */
+#define ESIDIV1__1 (0x0000) /* TSM SMCLK/ESIOSC divider = /1 */
+#define ESIDIV1__2 (0x0001) /* TSM SMCLK/ESIOSC divider = /2 */
+#define ESIDIV1__4 (0x0002) /* TSM SMCLK/ESIOSC divider = /4 */
+#define ESIDIV1__8 (0x0003) /* TSM SMCLK/ESIOSC divider = /8 */
+
+/* ESIPSM Control Bits */
+#define ESICNT2RST (0x8000) /* ESI Counter 2 reset */
+#define ESICNT1RST (0x4000) /* ESI Counter 1 reset */
+#define ESICNT0RST (0x2000) /* ESI Counter 0 reset */
+#define ESITEST4SEL1 (0x0200) /* Output signal selection for SIFTEST4 pin */
+#define ESITEST4SEL0 (0x0100) /* Output signal selection for SIFTEST4 pin */
+#define ESIV2SEL (0x0080) /* Source Selection for V2 bit*/
+#define ESICNT2EN (0x0020) /* ESICNT2 enable (down counter) */
+#define ESICNT1EN (0x0010) /* ESICNT1 enable (up/down counter) */
+#define ESICNT0EN (0x0008) /* ESICNT0 enable (up counter) */
+#define ESIQ7TRG (0x0004) /* Enabling to use Q7 as trigger for a TSM sequence */
+#define ESIQ6EN (0x0001) /* Q6 enable */
+
+/* ESIPSM Control Bits */
+#define ESIV2SEL_L (0x0080) /* Source Selection for V2 bit*/
+#define ESICNT2EN_L (0x0020) /* ESICNT2 enable (down counter) */
+#define ESICNT1EN_L (0x0010) /* ESICNT1 enable (up/down counter) */
+#define ESICNT0EN_L (0x0008) /* ESICNT0 enable (up counter) */
+#define ESIQ7TRG_L (0x0004) /* Enabling to use Q7 as trigger for a TSM sequence */
+#define ESIQ6EN_L (0x0001) /* Q6 enable */
+
+/* ESIPSM Control Bits */
+#define ESICNT2RST_H (0x0080) /* ESI Counter 2 reset */
+#define ESICNT1RST_H (0x0040) /* ESI Counter 1 reset */
+#define ESICNT0RST_H (0x0020) /* ESI Counter 0 reset */
+#define ESITEST4SEL1_H (0x0002) /* Output signal selection for SIFTEST4 pin */
+#define ESITEST4SEL0_H (0x0001) /* Output signal selection for SIFTEST4 pin */
+
+#define ESITEST4SEL_0 (0x0000) /* Q1 signal from PSM table */
+#define ESITEST4SEL_1 (0x0100) /* Q2 signal from PSM table */
+#define ESITEST4SEL_2 (0x0200) /* TSM clock signal from Timing State Machine */
+#define ESITEST4SEL_3 (0x0300) /* AFE1's comparator output signal Comp1Out */
+
+/* ESIOSC Control Bits */
+#define ESICLKFQ5 (0x2000) /* Internal oscillator frequency adjust */
+#define ESICLKFQ4 (0x1000) /* Internal oscillator frequency adjust */
+#define ESICLKFQ3 (0x0800) /* Internal oscillator frequency adjust */
+#define ESICLKFQ2 (0x0400) /* Internal oscillator frequency adjust */
+#define ESICLKFQ1 (0x0200) /* Internal oscillator frequency adjust */
+#define ESICLKFQ0 (0x0100) /* Internal oscillator frequency adjust */
+#define ESICLKGON (0x0002) /* Internal oscillator control */
+#define ESIHFSEL (0x0001) /* Internal oscillator enable */
+
+/* ESIOSC Control Bits */
+#define ESICLKGON_L (0x0002) /* Internal oscillator control */
+#define ESIHFSEL_L (0x0001) /* Internal oscillator enable */
+
+/* ESIOSC Control Bits */
+#define ESICLKFQ5_H (0x0020) /* Internal oscillator frequency adjust */
+#define ESICLKFQ4_H (0x0010) /* Internal oscillator frequency adjust */
+#define ESICLKFQ3_H (0x0008) /* Internal oscillator frequency adjust */
+#define ESICLKFQ2_H (0x0004) /* Internal oscillator frequency adjust */
+#define ESICLKFQ1_H (0x0002) /* Internal oscillator frequency adjust */
+#define ESICLKFQ0_H (0x0001) /* Internal oscillator frequency adjust */
+
+/* ESICTL Control Bits */
+#define ESIS3SEL2 (0x8000) /* PPUS3 source select */
+#define ESIS3SEL1 (0x4000) /* PPUS3 source select */
+#define ESIS3SEL0 (0x2000) /* PPUS3 source select */
+#define ESIS2SEL2 (0x1000) /* PPUS2 source select */
+#define ESIS2SEL1 (0x0800) /* PPUS2 source select */
+#define ESIS2SEL0 (0x0400) /* PPUS2 source select */
+#define ESIS1SEL2 (0x0200) /* PPUS1 source select */
+#define ESIS1SEL1 (0x0100) /* PPUS1 source select */
+#define ESIS1SEL0 (0x0080) /* PPUS1 source select */
+#define ESITCH11 (0x0040) /* select the comparator input for test channel 1 */
+#define ESITCH10 (0x0020) /* select the comparator input for test channel 1 */
+#define ESITCH01 (0x0010) /* select the comparator input for test channel 0 */
+#define ESITCH00 (0x0008) /* select the comparator input for test channel 0 */
+#define ESICS (0x0004) /* Comparator output/Timer_A input selection */
+#define ESITESTD (0x0002) /* Test cycle insertion */
+#define ESIEN (0x0001) /* Extended Scan interface enable */
+
+/* ESICTL Control Bits */
+#define ESIS1SEL0_L (0x0080) /* PPUS1 source select */
+#define ESITCH11_L (0x0040) /* select the comparator input for test channel 1 */
+#define ESITCH10_L (0x0020) /* select the comparator input for test channel 1 */
+#define ESITCH01_L (0x0010) /* select the comparator input for test channel 0 */
+#define ESITCH00_L (0x0008) /* select the comparator input for test channel 0 */
+#define ESICS_L (0x0004) /* Comparator output/Timer_A input selection */
+#define ESITESTD_L (0x0002) /* Test cycle insertion */
+#define ESIEN_L (0x0001) /* Extended Scan interface enable */
+
+/* ESICTL Control Bits */
+#define ESIS3SEL2_H (0x0080) /* PPUS3 source select */
+#define ESIS3SEL1_H (0x0040) /* PPUS3 source select */
+#define ESIS3SEL0_H (0x0020) /* PPUS3 source select */
+#define ESIS2SEL2_H (0x0010) /* PPUS2 source select */
+#define ESIS2SEL1_H (0x0008) /* PPUS2 source select */
+#define ESIS2SEL0_H (0x0004) /* PPUS2 source select */
+#define ESIS1SEL2_H (0x0002) /* PPUS1 source select */
+#define ESIS1SEL1_H (0x0001) /* PPUS1 source select */
+
+#define ESIS3SEL_0 (0x0000) /* ESIOUT0 is the PPUS3 source */
+#define ESIS3SEL_1 (0x2000) /* ESIOUT1 is the PPUS3 source */
+#define ESIS3SEL_2 (0x4000) /* ESIOUT2 is the PPUS3 source */
+#define ESIS3SEL_3 (0x6000) /* ESIOUT3 is the PPUS3 source */
+#define ESIS3SEL_4 (0x8000) /* ESIOUT4 is the PPUS3 source */
+#define ESIS3SEL_5 (0xA000) /* ESIOUT5 is the PPUS3 source */
+#define ESIS3SEL_6 (0xC000) /* ESIOUT6 is the PPUS3 source */
+#define ESIS3SEL_7 (0xE000) /* ESIOUT7 is the PPUS3 source */
+#define ESIS2SEL_0 (0x0000) /* ESIOUT0 is the PPUS2 source */
+#define ESIS2SEL_1 (0x0400) /* ESIOUT1 is the PPUS2 source */
+#define ESIS2SEL_2 (0x0800) /* ESIOUT2 is the PPUS2 source */
+#define ESIS2SEL_3 (0x0C00) /* ESIOUT3 is the PPUS2 source */
+#define ESIS2SEL_4 (0x1000) /* ESIOUT4 is the PPUS2 source */
+#define ESIS2SEL_5 (0x1400) /* ESIOUT5 is the PPUS2 source */
+#define ESIS2SEL_6 (0x1800) /* ESIOUT6 is the PPUS2 source */
+#define ESIS2SEL_7 (0x1C00) /* ESIOUT7 is the PPUS2 source */
+#define ESIS1SEL_0 (0x0000) /* ESIOUT0 is the PPUS1 source */
+#define ESIS1SEL_1 (0x0080) /* ESIOUT1 is the PPUS1 source */
+#define ESIS1SEL_2 (0x0100) /* ESIOUT2 is the PPUS1 source */
+#define ESIS1SEL_3 (0x0180) /* ESIOUT3 is the PPUS1 source */
+#define ESIS1SEL_4 (0x0200) /* ESIOUT4 is the PPUS1 source */
+#define ESIS1SEL_5 (0x0280) /* ESIOUT5 is the PPUS1 source */
+#define ESIS1SEL_6 (0x0300) /* ESIOUT6 is the PPUS1 source */
+#define ESIS1SEL_7 (0x0380) /* ESIOUT7 is the PPUS1 source */
+#define ESITCH1_0 (0x0000) /* Comparator input is ESICH0 when ESICAX = 0; Comparator input is ESICI0 when ESICAX = 1 */
+#define ESITCH1_1 (0x0400) /* Comparator input is ESICH1 when ESICAX = 0; Comparator input is ESICI1 when ESICAX = 1 */
+#define ESITCH1_2 (0x0800) /* Comparator input is ESICH2 when ESICAX = 0; Comparator input is ESICI2 when ESICAX = 1 */
+#define ESITCH1_3 (0x0C00) /* Comparator input is ESICH3 when ESICAX = 0; Comparator input is ESICI3 when ESICAX = 1 */
+#define ESITCH0_0 (0x0000) /* Comparator input is ESICH0 when ESICAX = 0; Comparator input is ESICI0 when ESICAX = 1 */
+#define ESITCH0_1 (0x0008) /* Comparator input is ESICH1 when ESICAX = 0; Comparator input is ESICI1 when ESICAX = 1 */
+#define ESITCH0_2 (0x0010) /* Comparator input is ESICH2 when ESICAX = 0; Comparator input is ESICI2 when ESICAX = 1 */
+#define ESITCH0_3 (0x0018) /* Comparator input is ESICH3 when ESICAX = 0; Comparator input is ESICI3 when ESICAX = 1 */
+
+/* Timing State Machine Control Bits */
+#define ESIREPEAT4 (0x8000) /* These bits together with the ESICLK bit configure the duration of this state */
+#define ESIREPEAT3 (0x4000) /* ESIREPEATx selects the number of clock cycles for this state. The number of clock cycles = ESIREPEATx + 1 */
+#define ESIREPEAT2 (0x2000) /* */
+#define ESIREPEAT1 (0x1000) /* */
+#define ESIREPEAT0 (0x0800) /* */
+#define ESICLK (0x0400) /* This bit selects the clock source for the TSM */
+#define ESISTOP (0x0200) /* This bit indicates the end of the TSM sequence */
+#define ESIDAC (0x0100) /* TSM DAC on */
+#define ESITESTS1 (0x0080) /* TSM test cycle control */
+#define ESIRSON (0x0040) /* Internal output latches enabled */
+#define ESICLKON (0x0020) /* High-frequency clock on */
+#define ESICA (0x0010) /* TSM comparator on */
+#define ESIEX (0x0008) /* Excitation and sample-and-hold */
+#define ESILCEN (0x0004) /* LC enable */
+#define ESICH1 (0x0002) /* Input channel select */
+#define ESICH0 (0x0001) /* Input channel select */
+
+/* Timing State Machine Control Bits */
+#define ESITESTS1_L (0x0080) /* TSM test cycle control */
+#define ESIRSON_L (0x0040) /* Internal output latches enabled */
+#define ESICLKON_L (0x0020) /* High-frequency clock on */
+#define ESICA_L (0x0010) /* TSM comparator on */
+#define ESIEX_L (0x0008) /* Excitation and sample-and-hold */
+#define ESILCEN_L (0x0004) /* LC enable */
+#define ESICH1_L (0x0002) /* Input channel select */
+#define ESICH0_L (0x0001) /* Input channel select */
+
+/* Timing State Machine Control Bits */
+#define ESIREPEAT4_H (0x0080) /* These bits together with the ESICLK bit configure the duration of this state */
+#define ESIREPEAT3_H (0x0040) /* ESIREPEATx selects the number of clock cycles for this state. The number of clock cycles = ESIREPEATx + 1 */
+#define ESIREPEAT2_H (0x0020) /* */
+#define ESIREPEAT1_H (0x0010) /* */
+#define ESIREPEAT0_H (0x0008) /* */
+#define ESICLK_H (0x0004) /* This bit selects the clock source for the TSM */
+#define ESISTOP_H (0x0002) /* This bit indicates the end of the TSM sequence */
+#define ESIDAC_H (0x0001) /* TSM DAC on */
+
+#define ESICAAZ (0x0020) /* Comparator Offset calibration annulation */
+
+#define ESIREPEAT_0 (0x0000) /* These bits configure the duration of this state */
+#define ESIREPEAT_1 (0x0800) /* ESIREPEATx selects the number of clock cycles for this state. The number of clock cycles = ESIREPEATx + 1 */
+#define ESIREPEAT_2 (0x1000)
+#define ESIREPEAT_3 (0x1800)
+#define ESIREPEAT_4 (0x2000)
+#define ESIREPEAT_5 (0x2800)
+#define ESIREPEAT_6 (0x3000)
+#define ESIREPEAT_7 (0x3800)
+#define ESIREPEAT_8 (0x4000)
+#define ESIREPEAT_9 (0x4800)
+#define ESIREPEAT_10 (0x5000)
+#define ESIREPEAT_11 (0x5800)
+#define ESIREPEAT_12 (0x6000)
+#define ESIREPEAT_13 (0x6800)
+#define ESIREPEAT_14 (0x7000)
+#define ESIREPEAT_15 (0x7800)
+#define ESIREPEAT_16 (0x8000)
+#define ESIREPEAT_17 (0x8800)
+#define ESIREPEAT_18 (0x9000)
+#define ESIREPEAT_19 (0x9800)
+#define ESIREPEAT_20 (0xA000)
+#define ESIREPEAT_21 (0xA800)
+#define ESIREPEAT_22 (0xB000)
+#define ESIREPEAT_23 (0xB800)
+#define ESIREPEAT_24 (0xC000)
+#define ESIREPEAT_25 (0xC800)
+#define ESIREPEAT_26 (0xD000)
+#define ESIREPEAT_27 (0xD800)
+#define ESIREPEAT_28 (0xE000)
+#define ESIREPEAT_29 (0xE800)
+#define ESIREPEAT_30 (0xF000)
+#define ESIREPEAT_31 (0xF800)
+#define ESICH_0 (0x0000) /* Input channel select: ESICH0 */
+#define ESICH_1 (0x0001) /* Input channel select: ESICH1 */
+#define ESICH_2 (0x0002) /* Input channel select: ESICH2 */
+#define ESICH_3 (0x0003) /* Input channel select: ESICH3 */
+/************************************************************
+* EXTENDED SCAN INTERFACE RAM
+************************************************************/
+#define __MSP430_HAS_ESI_RAM__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_ESI_RAM__ 0x0E00
+#define ESI_RAM_BASE __MSP430_BASEADDRESS_ESI_RAM__
+
+sfr_b(ESIRAM0); /* ESI RAM 0 */
+sfr_b(ESIRAM1); /* ESI RAM 1 */
+sfr_b(ESIRAM2); /* ESI RAM 2 */
+sfr_b(ESIRAM3); /* ESI RAM 3 */
+sfr_b(ESIRAM4); /* ESI RAM 4 */
+sfr_b(ESIRAM5); /* ESI RAM 5 */
+sfr_b(ESIRAM6); /* ESI RAM 6 */
+sfr_b(ESIRAM7); /* ESI RAM 7 */
+sfr_b(ESIRAM8); /* ESI RAM 8 */
+sfr_b(ESIRAM9); /* ESI RAM 9 */
+sfr_b(ESIRAM10); /* ESI RAM 10 */
+sfr_b(ESIRAM11); /* ESI RAM 11 */
+sfr_b(ESIRAM12); /* ESI RAM 12 */
+sfr_b(ESIRAM13); /* ESI RAM 13 */
+sfr_b(ESIRAM14); /* ESI RAM 14 */
+sfr_b(ESIRAM15); /* ESI RAM 15 */
+sfr_b(ESIRAM16); /* ESI RAM 16 */
+sfr_b(ESIRAM17); /* ESI RAM 17 */
+sfr_b(ESIRAM18); /* ESI RAM 18 */
+sfr_b(ESIRAM19); /* ESI RAM 19 */
+sfr_b(ESIRAM20); /* ESI RAM 20 */
+sfr_b(ESIRAM21); /* ESI RAM 21 */
+sfr_b(ESIRAM22); /* ESI RAM 22 */
+sfr_b(ESIRAM23); /* ESI RAM 23 */
+sfr_b(ESIRAM24); /* ESI RAM 24 */
+sfr_b(ESIRAM25); /* ESI RAM 25 */
+sfr_b(ESIRAM26); /* ESI RAM 26 */
+sfr_b(ESIRAM27); /* ESI RAM 27 */
+sfr_b(ESIRAM28); /* ESI RAM 28 */
+sfr_b(ESIRAM29); /* ESI RAM 29 */
+sfr_b(ESIRAM30); /* ESI RAM 30 */
+sfr_b(ESIRAM31); /* ESI RAM 31 */
+sfr_b(ESIRAM32); /* ESI RAM 32 */
+sfr_b(ESIRAM33); /* ESI RAM 33 */
+sfr_b(ESIRAM34); /* ESI RAM 34 */
+sfr_b(ESIRAM35); /* ESI RAM 35 */
+sfr_b(ESIRAM36); /* ESI RAM 36 */
+sfr_b(ESIRAM37); /* ESI RAM 37 */
+sfr_b(ESIRAM38); /* ESI RAM 38 */
+sfr_b(ESIRAM39); /* ESI RAM 39 */
+sfr_b(ESIRAM40); /* ESI RAM 40 */
+sfr_b(ESIRAM41); /* ESI RAM 41 */
+sfr_b(ESIRAM42); /* ESI RAM 42 */
+sfr_b(ESIRAM43); /* ESI RAM 43 */
+sfr_b(ESIRAM44); /* ESI RAM 44 */
+sfr_b(ESIRAM45); /* ESI RAM 45 */
+sfr_b(ESIRAM46); /* ESI RAM 46 */
+sfr_b(ESIRAM47); /* ESI RAM 47 */
+sfr_b(ESIRAM48); /* ESI RAM 48 */
+sfr_b(ESIRAM49); /* ESI RAM 49 */
+sfr_b(ESIRAM50); /* ESI RAM 50 */
+sfr_b(ESIRAM51); /* ESI RAM 51 */
+sfr_b(ESIRAM52); /* ESI RAM 52 */
+sfr_b(ESIRAM53); /* ESI RAM 53 */
+sfr_b(ESIRAM54); /* ESI RAM 54 */
+sfr_b(ESIRAM55); /* ESI RAM 55 */
+sfr_b(ESIRAM56); /* ESI RAM 56 */
+sfr_b(ESIRAM57); /* ESI RAM 57 */
+sfr_b(ESIRAM58); /* ESI RAM 58 */
+sfr_b(ESIRAM59); /* ESI RAM 59 */
+sfr_b(ESIRAM60); /* ESI RAM 60 */
+sfr_b(ESIRAM61); /* ESI RAM 61 */
+sfr_b(ESIRAM62); /* ESI RAM 62 */
+sfr_b(ESIRAM63); /* ESI RAM 63 */
+sfr_b(ESIRAM64); /* ESI RAM 64 */
+sfr_b(ESIRAM65); /* ESI RAM 65 */
+sfr_b(ESIRAM66); /* ESI RAM 66 */
+sfr_b(ESIRAM67); /* ESI RAM 67 */
+sfr_b(ESIRAM68); /* ESI RAM 68 */
+sfr_b(ESIRAM69); /* ESI RAM 69 */
+sfr_b(ESIRAM70); /* ESI RAM 70 */
+sfr_b(ESIRAM71); /* ESI RAM 71 */
+sfr_b(ESIRAM72); /* ESI RAM 72 */
+sfr_b(ESIRAM73); /* ESI RAM 73 */
+sfr_b(ESIRAM74); /* ESI RAM 74 */
+sfr_b(ESIRAM75); /* ESI RAM 75 */
+sfr_b(ESIRAM76); /* ESI RAM 76 */
+sfr_b(ESIRAM77); /* ESI RAM 77 */
+sfr_b(ESIRAM78); /* ESI RAM 78 */
+sfr_b(ESIRAM79); /* ESI RAM 79 */
+sfr_b(ESIRAM80); /* ESI RAM 80 */
+sfr_b(ESIRAM81); /* ESI RAM 81 */
+sfr_b(ESIRAM82); /* ESI RAM 82 */
+sfr_b(ESIRAM83); /* ESI RAM 83 */
+sfr_b(ESIRAM84); /* ESI RAM 84 */
+sfr_b(ESIRAM85); /* ESI RAM 85 */
+sfr_b(ESIRAM86); /* ESI RAM 86 */
+sfr_b(ESIRAM87); /* ESI RAM 87 */
+sfr_b(ESIRAM88); /* ESI RAM 88 */
+sfr_b(ESIRAM89); /* ESI RAM 89 */
+sfr_b(ESIRAM90); /* ESI RAM 90 */
+sfr_b(ESIRAM91); /* ESI RAM 91 */
+sfr_b(ESIRAM92); /* ESI RAM 92 */
+sfr_b(ESIRAM93); /* ESI RAM 93 */
+sfr_b(ESIRAM94); /* ESI RAM 94 */
+sfr_b(ESIRAM95); /* ESI RAM 95 */
+sfr_b(ESIRAM96); /* ESI RAM 96 */
+sfr_b(ESIRAM97); /* ESI RAM 97 */
+sfr_b(ESIRAM98); /* ESI RAM 98 */
+sfr_b(ESIRAM99); /* ESI RAM 99 */
+sfr_b(ESIRAM100); /* ESI RAM 100 */
+sfr_b(ESIRAM101); /* ESI RAM 101 */
+sfr_b(ESIRAM102); /* ESI RAM 102 */
+sfr_b(ESIRAM103); /* ESI RAM 103 */
+sfr_b(ESIRAM104); /* ESI RAM 104 */
+sfr_b(ESIRAM105); /* ESI RAM 105 */
+sfr_b(ESIRAM106); /* ESI RAM 106 */
+sfr_b(ESIRAM107); /* ESI RAM 107 */
+sfr_b(ESIRAM108); /* ESI RAM 108 */
+sfr_b(ESIRAM109); /* ESI RAM 109 */
+sfr_b(ESIRAM110); /* ESI RAM 110 */
+sfr_b(ESIRAM111); /* ESI RAM 111 */
+sfr_b(ESIRAM112); /* ESI RAM 112 */
+sfr_b(ESIRAM113); /* ESI RAM 113 */
+sfr_b(ESIRAM114); /* ESI RAM 114 */
+sfr_b(ESIRAM115); /* ESI RAM 115 */
+sfr_b(ESIRAM116); /* ESI RAM 116 */
+sfr_b(ESIRAM117); /* ESI RAM 117 */
+sfr_b(ESIRAM118); /* ESI RAM 118 */
+sfr_b(ESIRAM119); /* ESI RAM 119 */
+sfr_b(ESIRAM120); /* ESI RAM 120 */
+sfr_b(ESIRAM121); /* ESI RAM 121 */
+sfr_b(ESIRAM122); /* ESI RAM 122 */
+sfr_b(ESIRAM123); /* ESI RAM 123 */
+sfr_b(ESIRAM124); /* ESI RAM 124 */
+sfr_b(ESIRAM125); /* ESI RAM 125 */
+sfr_b(ESIRAM126); /* ESI RAM 126 */
+sfr_b(ESIRAM127); /* ESI RAM 127 */
+/*************************************************************
+* FRAM Memory
+*************************************************************/
+#define __MSP430_HAS_FRAM__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_FRAM__ 0x0140
+#define FRAM_BASE __MSP430_BASEADDRESS_FRAM__
+#define __MSP430_HAS_GC__ /* Definition to show that Module is available */
+
+sfr_w(FRCTL0); /* FRAM Controller Control 0 */
+sfr_b(FRCTL0_L); /* FRAM Controller Control 0 */
+sfr_b(FRCTL0_H); /* FRAM Controller Control 0 */
+sfr_w(GCCTL0); /* General Control 0 */
+sfr_b(GCCTL0_L); /* General Control 0 */
+sfr_b(GCCTL0_H); /* General Control 0 */
+sfr_w(GCCTL1); /* General Control 1 */
+sfr_b(GCCTL1_L); /* General Control 1 */
+sfr_b(GCCTL1_H); /* General Control 1 */
+
+#define FRCTLPW (0xA500) /* FRAM password for write */
+#define FRPW (0x9600) /* FRAM password returned by read */
+#define FWPW (0xA500) /* FRAM password for write */
+#define FXPW (0x3300) /* for use with XOR instruction */
+
+/* FRCTL0 Control Bits */
+//#define RESERVED (0x0001) /* RESERVED */
+//#define RESERVED (0x0002) /* RESERVED */
+//#define RESERVED (0x0004) /* RESERVED */
+#define NWAITS0 (0x0010) /* FRAM Wait state control Bit: 0 */
+#define NWAITS1 (0x0020) /* FRAM Wait state control Bit: 1 */
+#define NWAITS2 (0x0040) /* FRAM Wait state control Bit: 2 */
+//#define RESERVED (0x0080) /* RESERVED */
+
+/* FRCTL0 Control Bits */
+//#define RESERVED (0x0001) /* RESERVED */
+//#define RESERVED (0x0002) /* RESERVED */
+//#define RESERVED (0x0004) /* RESERVED */
+#define NWAITS0_L (0x0010) /* FRAM Wait state control Bit: 0 */
+#define NWAITS1_L (0x0020) /* FRAM Wait state control Bit: 1 */
+#define NWAITS2_L (0x0040) /* FRAM Wait state control Bit: 2 */
+//#define RESERVED (0x0080) /* RESERVED */
+
+#define NWAITS_0 (0x0000) /* FRAM Wait state control: 0 */
+#define NWAITS_1 (0x0010) /* FRAM Wait state control: 1 */
+#define NWAITS_2 (0x0020) /* FRAM Wait state control: 2 */
+#define NWAITS_3 (0x0030) /* FRAM Wait state control: 3 */
+#define NWAITS_4 (0x0040) /* FRAM Wait state control: 4 */
+#define NWAITS_5 (0x0050) /* FRAM Wait state control: 5 */
+#define NWAITS_6 (0x0060) /* FRAM Wait state control: 6 */
+#define NWAITS_7 (0x0070) /* FRAM Wait state control: 7 */
+
+/* GCCTL0 Control Bits */
+//#define RESERVED (0x0001) /* RESERVED */
+#define FRLPMPWR (0x0002) /* FRAM Enable FRAM auto power up after LPM */
+#define FRPWR (0x0004) /* FRAM Power Control */
+#define ACCTEIE (0x0008) /* RESERVED */
+//#define RESERVED (0x0010) /* RESERVED */
+#define CBDIE (0x0020) /* Enable NMI event if correctable bit error detected */
+#define UBDIE (0x0040) /* Enable NMI event if uncorrectable bit error detected */
+#define UBDRSTEN (0x0080) /* Enable Power Up Clear (PUC) reset if FRAM uncorrectable bit error detected */
+
+/* GCCTL0 Control Bits */
+//#define RESERVED (0x0001) /* RESERVED */
+#define FRLPMPWR_L (0x0002) /* FRAM Enable FRAM auto power up after LPM */
+#define FRPWR_L (0x0004) /* FRAM Power Control */
+#define ACCTEIE_L (0x0008) /* RESERVED */
+//#define RESERVED (0x0010) /* RESERVED */
+#define CBDIE_L (0x0020) /* Enable NMI event if correctable bit error detected */
+#define UBDIE_L (0x0040) /* Enable NMI event if uncorrectable bit error detected */
+#define UBDRSTEN_L (0x0080) /* Enable Power Up Clear (PUC) reset if FRAM uncorrectable bit error detected */
+
+/* GCCTL1 Control Bits */
+//#define RESERVED (0x0001) /* RESERVED */
+#define CBDIFG (0x0002) /* FRAM correctable bit error flag */
+#define UBDIFG (0x0004) /* FRAM uncorrectable bit error flag */
+#define ACCTEIFG (0x0008) /* Access time error flag */
+
+/* GCCTL1 Control Bits */
+//#define RESERVED (0x0001) /* RESERVED */
+#define CBDIFG_L (0x0002) /* FRAM correctable bit error flag */
+#define UBDIFG_L (0x0004) /* FRAM uncorrectable bit error flag */
+#define ACCTEIFG_L (0x0008) /* Access time error flag */
+
+/************************************************************
+* LCD_C
+************************************************************/
+#define __MSP430_HAS_LCD_C__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_LCD_C__ 0x0A00
+#define LCD_C_BASE __MSP430_BASEADDRESS_LCD_C__
+
+sfr_w(LCDCCTL0); /* LCD_C Control Register 0 */
+sfr_b(LCDCCTL0_L); /* LCD_C Control Register 0 */
+sfr_b(LCDCCTL0_H); /* LCD_C Control Register 0 */
+sfr_w(LCDCCTL1); /* LCD_C Control Register 1 */
+sfr_b(LCDCCTL1_L); /* LCD_C Control Register 1 */
+sfr_b(LCDCCTL1_H); /* LCD_C Control Register 1 */
+sfr_w(LCDCBLKCTL); /* LCD_C blinking control register */
+sfr_b(LCDCBLKCTL_L); /* LCD_C blinking control register */
+sfr_b(LCDCBLKCTL_H); /* LCD_C blinking control register */
+sfr_w(LCDCMEMCTL); /* LCD_C memory control register */
+sfr_b(LCDCMEMCTL_L); /* LCD_C memory control register */
+sfr_b(LCDCMEMCTL_H); /* LCD_C memory control register */
+sfr_w(LCDCVCTL); /* LCD_C Voltage Control Register */
+sfr_b(LCDCVCTL_L); /* LCD_C Voltage Control Register */
+sfr_b(LCDCVCTL_H); /* LCD_C Voltage Control Register */
+sfr_w(LCDCPCTL0); /* LCD_C Port Control Register 0 */
+sfr_b(LCDCPCTL0_L); /* LCD_C Port Control Register 0 */
+sfr_b(LCDCPCTL0_H); /* LCD_C Port Control Register 0 */
+sfr_w(LCDCPCTL1); /* LCD_C Port Control Register 1 */
+sfr_b(LCDCPCTL1_L); /* LCD_C Port Control Register 1 */
+sfr_b(LCDCPCTL1_H); /* LCD_C Port Control Register 1 */
+sfr_w(LCDCPCTL2); /* LCD_C Port Control Register 2 */
+sfr_b(LCDCPCTL2_L); /* LCD_C Port Control Register 2 */
+sfr_b(LCDCPCTL2_H); /* LCD_C Port Control Register 2 */
+sfr_w(LCDCCPCTL); /* LCD_C Charge Pump Control Register 3 */
+sfr_b(LCDCCPCTL_L); /* LCD_C Charge Pump Control Register 3 */
+sfr_b(LCDCCPCTL_H); /* LCD_C Charge Pump Control Register 3 */
+sfr_w(LCDCIV); /* LCD_C Interrupt Vector Register */
+
+// LCDCCTL0
+#define LCDON (0x0001) /* LCD_C LCD On */
+#define LCDLP (0x0002) /* LCD_C Low Power Waveform */
+#define LCDSON (0x0004) /* LCD_C LCD Segments On */
+#define LCDMX0 (0x0008) /* LCD_C Mux Rate Bit: 0 */
+#define LCDMX1 (0x0010) /* LCD_C Mux Rate Bit: 1 */
+#define LCDMX2 (0x0020) /* LCD_C Mux Rate Bit: 2 */
+//#define RESERVED (0x0040) /* LCD_C RESERVED */
+#define LCDSSEL (0x0080) /* LCD_C Clock Select */
+#define LCDPRE0 (0x0100) /* LCD_C LCD frequency pre-scaler Bit: 0 */
+#define LCDPRE1 (0x0200) /* LCD_C LCD frequency pre-scaler Bit: 1 */
+#define LCDPRE2 (0x0400) /* LCD_C LCD frequency pre-scaler Bit: 2 */
+#define LCDDIV0 (0x0800) /* LCD_C LCD frequency divider Bit: 0 */
+#define LCDDIV1 (0x1000) /* LCD_C LCD frequency divider Bit: 1 */
+#define LCDDIV2 (0x2000) /* LCD_C LCD frequency divider Bit: 2 */
+#define LCDDIV3 (0x4000) /* LCD_C LCD frequency divider Bit: 3 */
+#define LCDDIV4 (0x8000) /* LCD_C LCD frequency divider Bit: 4 */
+
+// LCDCCTL0
+#define LCDON_L (0x0001) /* LCD_C LCD On */
+#define LCDLP_L (0x0002) /* LCD_C Low Power Waveform */
+#define LCDSON_L (0x0004) /* LCD_C LCD Segments On */
+#define LCDMX0_L (0x0008) /* LCD_C Mux Rate Bit: 0 */
+#define LCDMX1_L (0x0010) /* LCD_C Mux Rate Bit: 1 */
+#define LCDMX2_L (0x0020) /* LCD_C Mux Rate Bit: 2 */
+//#define RESERVED (0x0040) /* LCD_C RESERVED */
+#define LCDSSEL_L (0x0080) /* LCD_C Clock Select */
+
+// LCDCCTL0
+//#define RESERVED (0x0040) /* LCD_C RESERVED */
+#define LCDPRE0_H (0x0001) /* LCD_C LCD frequency pre-scaler Bit: 0 */
+#define LCDPRE1_H (0x0002) /* LCD_C LCD frequency pre-scaler Bit: 1 */
+#define LCDPRE2_H (0x0004) /* LCD_C LCD frequency pre-scaler Bit: 2 */
+#define LCDDIV0_H (0x0008) /* LCD_C LCD frequency divider Bit: 0 */
+#define LCDDIV1_H (0x0010) /* LCD_C LCD frequency divider Bit: 1 */
+#define LCDDIV2_H (0x0020) /* LCD_C LCD frequency divider Bit: 2 */
+#define LCDDIV3_H (0x0040) /* LCD_C LCD frequency divider Bit: 3 */
+#define LCDDIV4_H (0x0080) /* LCD_C LCD frequency divider Bit: 4 */
+
+#define LCDPRE_0 (0x0000) /* LCD_C LCD frequency pre-scaler: /1 */
+#define LCDPRE_1 (0x0100) /* LCD_C LCD frequency pre-scaler: /2 */
+#define LCDPRE_2 (0x0200) /* LCD_C LCD frequency pre-scaler: /4 */
+#define LCDPRE_3 (0x0300) /* LCD_C LCD frequency pre-scaler: /8 */
+#define LCDPRE_4 (0x0400) /* LCD_C LCD frequency pre-scaler: /16 */
+#define LCDPRE_5 (0x0500) /* LCD_C LCD frequency pre-scaler: /32 */
+#define LCDPRE__1 (0x0000) /* LCD_C LCD frequency pre-scaler: /1 */
+#define LCDPRE__2 (0x0100) /* LCD_C LCD frequency pre-scaler: /2 */
+#define LCDPRE__4 (0x0200) /* LCD_C LCD frequency pre-scaler: /4 */
+#define LCDPRE__8 (0x0300) /* LCD_C LCD frequency pre-scaler: /8 */
+#define LCDPRE__16 (0x0400) /* LCD_C LCD frequency pre-scaler: /16 */
+#define LCDPRE__32 (0x0500) /* LCD_C LCD frequency pre-scaler: /32 */
+
+#define LCDDIV_0 (0x0000) /* LCD_C LCD frequency divider: /1 */
+#define LCDDIV_1 (0x0800) /* LCD_C LCD frequency divider: /2 */
+#define LCDDIV_2 (0x1000) /* LCD_C LCD frequency divider: /3 */
+#define LCDDIV_3 (0x1800) /* LCD_C LCD frequency divider: /4 */
+#define LCDDIV_4 (0x2000) /* LCD_C LCD frequency divider: /5 */
+#define LCDDIV_5 (0x2800) /* LCD_C LCD frequency divider: /6 */
+#define LCDDIV_6 (0x3000) /* LCD_C LCD frequency divider: /7 */
+#define LCDDIV_7 (0x3800) /* LCD_C LCD frequency divider: /8 */
+#define LCDDIV_8 (0x4000) /* LCD_C LCD frequency divider: /9 */
+#define LCDDIV_9 (0x4800) /* LCD_C LCD frequency divider: /10 */
+#define LCDDIV_10 (0x5000) /* LCD_C LCD frequency divider: /11 */
+#define LCDDIV_11 (0x5800) /* LCD_C LCD frequency divider: /12 */
+#define LCDDIV_12 (0x6000) /* LCD_C LCD frequency divider: /13 */
+#define LCDDIV_13 (0x6800) /* LCD_C LCD frequency divider: /14 */
+#define LCDDIV_14 (0x7000) /* LCD_C LCD frequency divider: /15 */
+#define LCDDIV_15 (0x7800) /* LCD_C LCD frequency divider: /16 */
+#define LCDDIV_16 (0x8000) /* LCD_C LCD frequency divider: /17 */
+#define LCDDIV_17 (0x8800) /* LCD_C LCD frequency divider: /18 */
+#define LCDDIV_18 (0x9000) /* LCD_C LCD frequency divider: /19 */
+#define LCDDIV_19 (0x9800) /* LCD_C LCD frequency divider: /20 */
+#define LCDDIV_20 (0xA000) /* LCD_C LCD frequency divider: /21 */
+#define LCDDIV_21 (0xA800) /* LCD_C LCD frequency divider: /22 */
+#define LCDDIV_22 (0xB000) /* LCD_C LCD frequency divider: /23 */
+#define LCDDIV_23 (0xB800) /* LCD_C LCD frequency divider: /24 */
+#define LCDDIV_24 (0xC000) /* LCD_C LCD frequency divider: /25 */
+#define LCDDIV_25 (0xC800) /* LCD_C LCD frequency divider: /26 */
+#define LCDDIV_26 (0xD000) /* LCD_C LCD frequency divider: /27 */
+#define LCDDIV_27 (0xD800) /* LCD_C LCD frequency divider: /28 */
+#define LCDDIV_28 (0xE000) /* LCD_C LCD frequency divider: /29 */
+#define LCDDIV_29 (0xE800) /* LCD_C LCD frequency divider: /30 */
+#define LCDDIV_30 (0xF000) /* LCD_C LCD frequency divider: /31 */
+#define LCDDIV_31 (0xF800) /* LCD_C LCD frequency divider: /32 */
+#define LCDDIV__1 (0x0000) /* LCD_C LCD frequency divider: /1 */
+#define LCDDIV__2 (0x0800) /* LCD_C LCD frequency divider: /2 */
+#define LCDDIV__3 (0x1000) /* LCD_C LCD frequency divider: /3 */
+#define LCDDIV__4 (0x1800) /* LCD_C LCD frequency divider: /4 */
+#define LCDDIV__5 (0x2000) /* LCD_C LCD frequency divider: /5 */
+#define LCDDIV__6 (0x2800) /* LCD_C LCD frequency divider: /6 */
+#define LCDDIV__7 (0x3000) /* LCD_C LCD frequency divider: /7 */
+#define LCDDIV__8 (0x3800) /* LCD_C LCD frequency divider: /8 */
+#define LCDDIV__9 (0x4000) /* LCD_C LCD frequency divider: /9 */
+#define LCDDIV__10 (0x4800) /* LCD_C LCD frequency divider: /10 */
+#define LCDDIV__11 (0x5000) /* LCD_C LCD frequency divider: /11 */
+#define LCDDIV__12 (0x5800) /* LCD_C LCD frequency divider: /12 */
+#define LCDDIV__13 (0x6000) /* LCD_C LCD frequency divider: /13 */
+#define LCDDIV__14 (0x6800) /* LCD_C LCD frequency divider: /14 */
+#define LCDDIV__15 (0x7000) /* LCD_C LCD frequency divider: /15 */
+#define LCDDIV__16 (0x7800) /* LCD_C LCD frequency divider: /16 */
+#define LCDDIV__17 (0x8000) /* LCD_C LCD frequency divider: /17 */
+#define LCDDIV__18 (0x8800) /* LCD_C LCD frequency divider: /18 */
+#define LCDDIV__19 (0x9000) /* LCD_C LCD frequency divider: /19 */
+#define LCDDIV__20 (0x9800) /* LCD_C LCD frequency divider: /20 */
+#define LCDDIV__21 (0xA000) /* LCD_C LCD frequency divider: /21 */
+#define LCDDIV__22 (0xA800) /* LCD_C LCD frequency divider: /22 */
+#define LCDDIV__23 (0xB000) /* LCD_C LCD frequency divider: /23 */
+#define LCDDIV__24 (0xB800) /* LCD_C LCD frequency divider: /24 */
+#define LCDDIV__25 (0xC000) /* LCD_C LCD frequency divider: /25 */
+#define LCDDIV__26 (0xC800) /* LCD_C LCD frequency divider: /26 */
+#define LCDDIV__27 (0xD000) /* LCD_C LCD frequency divider: /27 */
+#define LCDDIV__28 (0xD800) /* LCD_C LCD frequency divider: /28 */
+#define LCDDIV__29 (0xE000) /* LCD_C LCD frequency divider: /29 */
+#define LCDDIV__30 (0xE800) /* LCD_C LCD frequency divider: /30 */
+#define LCDDIV__31 (0xF000) /* LCD_C LCD frequency divider: /31 */
+#define LCDDIV__32 (0xF800) /* LCD_C LCD frequency divider: /32 */
+
+/* Display modes coded with Bits 2-4 */
+#define LCDSTATIC (LCDSON)
+#define LCD2MUX (LCDMX0+LCDSON)
+#define LCD3MUX (LCDMX1+LCDSON)
+#define LCD4MUX (LCDMX1+LCDMX0+LCDSON)
+#define LCD5MUX (LCDMX2+LCDSON)
+#define LCD6MUX (LCDMX2+LCDMX0+LCDSON)
+#define LCD7MUX (LCDMX2+LCDMX1+LCDSON)
+#define LCD8MUX (LCDMX2+LCDMX1+LCDMX0+LCDSON)
+
+// LCDCCTL1
+#define LCDFRMIFG (0x0001) /* LCD_C LCD frame interrupt flag */
+#define LCDBLKOFFIFG (0x0002) /* LCD_C LCD blinking off interrupt flag, */
+#define LCDBLKONIFG (0x0004) /* LCD_C LCD blinking on interrupt flag, */
+#define LCDNOCAPIFG (0x0008) /* LCD_C No cpacitance connected interrupt flag */
+#define LCDFRMIE (0x0100) /* LCD_C LCD frame interrupt enable */
+#define LCDBLKOFFIE (0x0200) /* LCD_C LCD blinking off interrupt flag, */
+#define LCDBLKONIE (0x0400) /* LCD_C LCD blinking on interrupt flag, */
+#define LCDNOCAPIE (0x0800) /* LCD_C No cpacitance connected interrupt enable */
+
+// LCDCCTL1
+#define LCDFRMIFG_L (0x0001) /* LCD_C LCD frame interrupt flag */
+#define LCDBLKOFFIFG_L (0x0002) /* LCD_C LCD blinking off interrupt flag, */
+#define LCDBLKONIFG_L (0x0004) /* LCD_C LCD blinking on interrupt flag, */
+#define LCDNOCAPIFG_L (0x0008) /* LCD_C No cpacitance connected interrupt flag */
+
+// LCDCCTL1
+#define LCDFRMIE_H (0x0001) /* LCD_C LCD frame interrupt enable */
+#define LCDBLKOFFIE_H (0x0002) /* LCD_C LCD blinking off interrupt flag, */
+#define LCDBLKONIE_H (0x0004) /* LCD_C LCD blinking on interrupt flag, */
+#define LCDNOCAPIE_H (0x0008) /* LCD_C No cpacitance connected interrupt enable */
+
+// LCDCBLKCTL
+#define LCDBLKMOD0 (0x0001) /* LCD_C Blinking mode Bit: 0 */
+#define LCDBLKMOD1 (0x0002) /* LCD_C Blinking mode Bit: 1 */
+#define LCDBLKPRE0 (0x0004) /* LCD_C Clock pre-scaler for blinking frequency Bit: 0 */
+#define LCDBLKPRE1 (0x0008) /* LCD_C Clock pre-scaler for blinking frequency Bit: 1 */
+#define LCDBLKPRE2 (0x0010) /* LCD_C Clock pre-scaler for blinking frequency Bit: 2 */
+#define LCDBLKDIV0 (0x0020) /* LCD_C Clock divider for blinking frequency Bit: 0 */
+#define LCDBLKDIV1 (0x0040) /* LCD_C Clock divider for blinking frequency Bit: 1 */
+#define LCDBLKDIV2 (0x0080) /* LCD_C Clock divider for blinking frequency Bit: 2 */
+
+// LCDCBLKCTL
+#define LCDBLKMOD0_L (0x0001) /* LCD_C Blinking mode Bit: 0 */
+#define LCDBLKMOD1_L (0x0002) /* LCD_C Blinking mode Bit: 1 */
+#define LCDBLKPRE0_L (0x0004) /* LCD_C Clock pre-scaler for blinking frequency Bit: 0 */
+#define LCDBLKPRE1_L (0x0008) /* LCD_C Clock pre-scaler for blinking frequency Bit: 1 */
+#define LCDBLKPRE2_L (0x0010) /* LCD_C Clock pre-scaler for blinking frequency Bit: 2 */
+#define LCDBLKDIV0_L (0x0020) /* LCD_C Clock divider for blinking frequency Bit: 0 */
+#define LCDBLKDIV1_L (0x0040) /* LCD_C Clock divider for blinking frequency Bit: 1 */
+#define LCDBLKDIV2_L (0x0080) /* LCD_C Clock divider for blinking frequency Bit: 2 */
+
+#define LCDBLKMOD_0 (0x0000) /* LCD_C Blinking mode: Off */
+#define LCDBLKMOD_1 (0x0001) /* LCD_C Blinking mode: Individual */
+#define LCDBLKMOD_2 (0x0002) /* LCD_C Blinking mode: All */
+#define LCDBLKMOD_3 (0x0003) /* LCD_C Blinking mode: Switching */
+
+#define LCDBLKPRE_0 (0x0000) /* LCD_C Clock pre-scaler for blinking frequency: 0 */
+#define LCDBLKPRE_1 (0x0004) /* LCD_C Clock pre-scaler for blinking frequency: 1 */
+#define LCDBLKPRE_2 (0x0008) /* LCD_C Clock pre-scaler for blinking frequency: 2 */
+#define LCDBLKPRE_3 (0x000C) /* LCD_C Clock pre-scaler for blinking frequency: 3 */
+#define LCDBLKPRE_4 (0x0010) /* LCD_C Clock pre-scaler for blinking frequency: 4 */
+#define LCDBLKPRE_5 (0x0014) /* LCD_C Clock pre-scaler for blinking frequency: 5 */
+#define LCDBLKPRE_6 (0x0018) /* LCD_C Clock pre-scaler for blinking frequency: 6 */
+#define LCDBLKPRE_7 (0x001C) /* LCD_C Clock pre-scaler for blinking frequency: 7 */
+
+#define LCDBLKPRE__512 (0x0000) /* LCD_C Clock pre-scaler for blinking frequency: 512 */
+#define LCDBLKPRE__1024 (0x0004) /* LCD_C Clock pre-scaler for blinking frequency: 1024 */
+#define LCDBLKPRE__2048 (0x0008) /* LCD_C Clock pre-scaler for blinking frequency: 2048 */
+#define LCDBLKPRE__4096 (0x000C) /* LCD_C Clock pre-scaler for blinking frequency: 4096 */
+#define LCDBLKPRE__8192 (0x0010) /* LCD_C Clock pre-scaler for blinking frequency: 8192 */
+#define LCDBLKPRE__16384 (0x0014) /* LCD_C Clock pre-scaler for blinking frequency: 16384 */
+#define LCDBLKPRE__32768 (0x0018) /* LCD_C Clock pre-scaler for blinking frequency: 32768 */
+#define LCDBLKPRE__65536 (0x001C) /* LCD_C Clock pre-scaler for blinking frequency: 65536 */
+
+#define LCDBLKDIV_0 (0x0000) /* LCD_C Clock divider for blinking frequency: 0 */
+#define LCDBLKDIV_1 (0x0020) /* LCD_C Clock divider for blinking frequency: 1 */
+#define LCDBLKDIV_2 (0x0040) /* LCD_C Clock divider for blinking frequency: 2 */
+#define LCDBLKDIV_3 (0x0060) /* LCD_C Clock divider for blinking frequency: 3 */
+#define LCDBLKDIV_4 (0x0080) /* LCD_C Clock divider for blinking frequency: 4 */
+#define LCDBLKDIV_5 (0x00A0) /* LCD_C Clock divider for blinking frequency: 5 */
+#define LCDBLKDIV_6 (0x00C0) /* LCD_C Clock divider for blinking frequency: 6 */
+#define LCDBLKDIV_7 (0x00E0) /* LCD_C Clock divider for blinking frequency: 7 */
+
+#define LCDBLKDIV__1 (0x0000) /* LCD_C Clock divider for blinking frequency: /1 */
+#define LCDBLKDIV__2 (0x0020) /* LCD_C Clock divider for blinking frequency: /2 */
+#define LCDBLKDIV__3 (0x0040) /* LCD_C Clock divider for blinking frequency: /3 */
+#define LCDBLKDIV__4 (0x0060) /* LCD_C Clock divider for blinking frequency: /4 */
+#define LCDBLKDIV__5 (0x0080) /* LCD_C Clock divider for blinking frequency: /5 */
+#define LCDBLKDIV__6 (0x00A0) /* LCD_C Clock divider for blinking frequency: /6 */
+#define LCDBLKDIV__7 (0x00C0) /* LCD_C Clock divider for blinking frequency: /7 */
+#define LCDBLKDIV__8 (0x00E0) /* LCD_C Clock divider for blinking frequency: /8 */
+
+// LCDCMEMCTL
+#define LCDDISP (0x0001) /* LCD_C LCD memory registers for display */
+#define LCDCLRM (0x0002) /* LCD_C Clear LCD memory */
+#define LCDCLRBM (0x0004) /* LCD_C Clear LCD blinking memory */
+
+// LCDCMEMCTL
+#define LCDDISP_L (0x0001) /* LCD_C LCD memory registers for display */
+#define LCDCLRM_L (0x0002) /* LCD_C Clear LCD memory */
+#define LCDCLRBM_L (0x0004) /* LCD_C Clear LCD blinking memory */
+
+// LCDCVCTL
+#define LCD2B (0x0001) /* Selects 1/2 bias. */
+#define VLCDREF0 (0x0002) /* Selects reference voltage for regulated charge pump: 0 */
+#define VLCDREF1 (0x0004) /* Selects reference voltage for regulated charge pump: 1 */
+#define LCDCPEN (0x0008) /* LCD Voltage Charge Pump Enable. */
+#define VLCDEXT (0x0010) /* Select external source for VLCD. */
+#define LCDEXTBIAS (0x0020) /* V2 - V4 voltage select. */
+#define R03EXT (0x0040) /* Selects external connections for LCD mid voltages. */
+#define LCDREXT (0x0080) /* Selects external connection for lowest LCD voltage. */
+#define VLCD0 (0x0200) /* VLCD select: 0 */
+#define VLCD1 (0x0400) /* VLCD select: 1 */
+#define VLCD2 (0x0800) /* VLCD select: 2 */
+#define VLCD3 (0x1000) /* VLCD select: 3 */
+#define VLCD4 (0x2000) /* VLCD select: 4 */
+#define VLCD5 (0x4000) /* VLCD select: 5 */
+
+// LCDCVCTL
+#define LCD2B_L (0x0001) /* Selects 1/2 bias. */
+#define VLCDREF0_L (0x0002) /* Selects reference voltage for regulated charge pump: 0 */
+#define VLCDREF1_L (0x0004) /* Selects reference voltage for regulated charge pump: 1 */
+#define LCDCPEN_L (0x0008) /* LCD Voltage Charge Pump Enable. */
+#define VLCDEXT_L (0x0010) /* Select external source for VLCD. */
+#define LCDEXTBIAS_L (0x0020) /* V2 - V4 voltage select. */
+#define R03EXT_L (0x0040) /* Selects external connections for LCD mid voltages. */
+#define LCDREXT_L (0x0080) /* Selects external connection for lowest LCD voltage. */
+
+// LCDCVCTL
+#define VLCD0_H (0x0002) /* VLCD select: 0 */
+#define VLCD1_H (0x0004) /* VLCD select: 1 */
+#define VLCD2_H (0x0008) /* VLCD select: 2 */
+#define VLCD3_H (0x0010) /* VLCD select: 3 */
+#define VLCD4_H (0x0020) /* VLCD select: 4 */
+#define VLCD5_H (0x0040) /* VLCD select: 5 */
+
+/* Reference voltage source select for the regulated charge pump */
+#define VLCDREF_0 (0x0000) /* Internal */
+#define VLCDREF_1 (0x0002) /* External */
+#define VLCDREF_2 (0x0004) /* Reserved */
+#define VLCDREF_3 (0x0006) /* Reserved */
+
+/* Charge pump voltage selections */
+#define VLCD_0 (0x0000) /* Charge pump disabled */
+#define VLCD_1 (0x0200) /* VLCD = 2.60V */
+#define VLCD_2 (0x0400) /* VLCD = 2.66V */
+#define VLCD_3 (0x0600) /* VLCD = 2.72V */
+#define VLCD_4 (0x0800) /* VLCD = 2.78V */
+#define VLCD_5 (0x0A00) /* VLCD = 2.84V */
+#define VLCD_6 (0x0C00) /* VLCD = 2.90V */
+#define VLCD_7 (0x0E00) /* VLCD = 2.96V */
+#define VLCD_8 (0x1000) /* VLCD = 3.02V */
+#define VLCD_9 (0x1200) /* VLCD = 3.08V */
+#define VLCD_10 (0x1400) /* VLCD = 3.14V */
+#define VLCD_11 (0x1600) /* VLCD = 3.20V */
+#define VLCD_12 (0x1800) /* VLCD = 3.26V */
+#define VLCD_13 (0x1A00) /* VLCD = 3.32V */
+#define VLCD_14 (0x1C00) /* VLCD = 3.38V */
+#define VLCD_15 (0x1E00) /* VLCD = 3.44V */
+
+#define VLCD_DISABLED (0x0000) /* Charge pump disabled */
+#define VLCD_2_60 (0x0200) /* VLCD = 2.60V */
+#define VLCD_2_66 (0x0400) /* VLCD = 2.66V */
+#define VLCD_2_72 (0x0600) /* VLCD = 2.72V */
+#define VLCD_2_78 (0x0800) /* VLCD = 2.78V */
+#define VLCD_2_84 (0x0A00) /* VLCD = 2.84V */
+#define VLCD_2_90 (0x0C00) /* VLCD = 2.90V */
+#define VLCD_2_96 (0x0E00) /* VLCD = 2.96V */
+#define VLCD_3_02 (0x1000) /* VLCD = 3.02V */
+#define VLCD_3_08 (0x1200) /* VLCD = 3.08V */
+#define VLCD_3_14 (0x1400) /* VLCD = 3.14V */
+#define VLCD_3_20 (0x1600) /* VLCD = 3.20V */
+#define VLCD_3_26 (0x1800) /* VLCD = 3.26V */
+#define VLCD_3_32 (0x1A00) /* VLCD = 3.32V */
+#define VLCD_3_38 (0x1C00) /* VLCD = 3.38V */
+#define VLCD_3_44 (0x1E00) /* VLCD = 3.44V */
+
+// LCDCPCTL0
+#define LCDS0 (0x0001) /* LCD Segment 0 enable. */
+#define LCDS1 (0x0002) /* LCD Segment 1 enable. */
+#define LCDS2 (0x0004) /* LCD Segment 2 enable. */
+#define LCDS3 (0x0008) /* LCD Segment 3 enable. */
+#define LCDS4 (0x0010) /* LCD Segment 4 enable. */
+#define LCDS5 (0x0020) /* LCD Segment 5 enable. */
+#define LCDS6 (0x0040) /* LCD Segment 6 enable. */
+#define LCDS7 (0x0080) /* LCD Segment 7 enable. */
+#define LCDS8 (0x0100) /* LCD Segment 8 enable. */
+#define LCDS9 (0x0200) /* LCD Segment 9 enable. */
+#define LCDS10 (0x0400) /* LCD Segment 10 enable. */
+#define LCDS11 (0x0800) /* LCD Segment 11 enable. */
+#define LCDS12 (0x1000) /* LCD Segment 12 enable. */
+#define LCDS13 (0x2000) /* LCD Segment 13 enable. */
+#define LCDS14 (0x4000) /* LCD Segment 14 enable. */
+#define LCDS15 (0x8000) /* LCD Segment 15 enable. */
+
+// LCDCPCTL0
+#define LCDS0_L (0x0001) /* LCD Segment 0 enable. */
+#define LCDS1_L (0x0002) /* LCD Segment 1 enable. */
+#define LCDS2_L (0x0004) /* LCD Segment 2 enable. */
+#define LCDS3_L (0x0008) /* LCD Segment 3 enable. */
+#define LCDS4_L (0x0010) /* LCD Segment 4 enable. */
+#define LCDS5_L (0x0020) /* LCD Segment 5 enable. */
+#define LCDS6_L (0x0040) /* LCD Segment 6 enable. */
+#define LCDS7_L (0x0080) /* LCD Segment 7 enable. */
+
+// LCDCPCTL0
+#define LCDS8_H (0x0001) /* LCD Segment 8 enable. */
+#define LCDS9_H (0x0002) /* LCD Segment 9 enable. */
+#define LCDS10_H (0x0004) /* LCD Segment 10 enable. */
+#define LCDS11_H (0x0008) /* LCD Segment 11 enable. */
+#define LCDS12_H (0x0010) /* LCD Segment 12 enable. */
+#define LCDS13_H (0x0020) /* LCD Segment 13 enable. */
+#define LCDS14_H (0x0040) /* LCD Segment 14 enable. */
+#define LCDS15_H (0x0080) /* LCD Segment 15 enable. */
+
+// LCDCPCTL1
+#define LCDS16 (0x0001) /* LCD Segment 16 enable. */
+#define LCDS17 (0x0002) /* LCD Segment 17 enable. */
+#define LCDS18 (0x0004) /* LCD Segment 18 enable. */
+#define LCDS19 (0x0008) /* LCD Segment 19 enable. */
+#define LCDS20 (0x0010) /* LCD Segment 20 enable. */
+#define LCDS21 (0x0020) /* LCD Segment 21 enable. */
+#define LCDS22 (0x0040) /* LCD Segment 22 enable. */
+#define LCDS23 (0x0080) /* LCD Segment 23 enable. */
+#define LCDS24 (0x0100) /* LCD Segment 24 enable. */
+#define LCDS25 (0x0200) /* LCD Segment 25 enable. */
+#define LCDS26 (0x0400) /* LCD Segment 26 enable. */
+#define LCDS27 (0x0800) /* LCD Segment 27 enable. */
+#define LCDS28 (0x1000) /* LCD Segment 28 enable. */
+#define LCDS29 (0x2000) /* LCD Segment 29 enable. */
+#define LCDS30 (0x4000) /* LCD Segment 30 enable. */
+#define LCDS31 (0x8000) /* LCD Segment 31 enable. */
+
+// LCDCPCTL1
+#define LCDS16_L (0x0001) /* LCD Segment 16 enable. */
+#define LCDS17_L (0x0002) /* LCD Segment 17 enable. */
+#define LCDS18_L (0x0004) /* LCD Segment 18 enable. */
+#define LCDS19_L (0x0008) /* LCD Segment 19 enable. */
+#define LCDS20_L (0x0010) /* LCD Segment 20 enable. */
+#define LCDS21_L (0x0020) /* LCD Segment 21 enable. */
+#define LCDS22_L (0x0040) /* LCD Segment 22 enable. */
+#define LCDS23_L (0x0080) /* LCD Segment 23 enable. */
+
+// LCDCPCTL1
+#define LCDS24_H (0x0001) /* LCD Segment 24 enable. */
+#define LCDS25_H (0x0002) /* LCD Segment 25 enable. */
+#define LCDS26_H (0x0004) /* LCD Segment 26 enable. */
+#define LCDS27_H (0x0008) /* LCD Segment 27 enable. */
+#define LCDS28_H (0x0010) /* LCD Segment 28 enable. */
+#define LCDS29_H (0x0020) /* LCD Segment 29 enable. */
+#define LCDS30_H (0x0040) /* LCD Segment 30 enable. */
+#define LCDS31_H (0x0080) /* LCD Segment 31 enable. */
+
+// LCDCPCTL2
+#define LCDS32 (0x0001) /* LCD Segment 32 enable. */
+#define LCDS33 (0x0002) /* LCD Segment 33 enable. */
+#define LCDS34 (0x0004) /* LCD Segment 34 enable. */
+#define LCDS35 (0x0008) /* LCD Segment 35 enable. */
+#define LCDS36 (0x0010) /* LCD Segment 36 enable. */
+#define LCDS37 (0x0020) /* LCD Segment 37 enable. */
+#define LCDS38 (0x0040) /* LCD Segment 38 enable. */
+#define LCDS39 (0x0080) /* LCD Segment 39 enable. */
+#define LCDS40 (0x0100) /* LCD Segment 40 enable. */
+#define LCDS41 (0x0200) /* LCD Segment 41 enable. */
+#define LCDS42 (0x0400) /* LCD Segment 42 enable. */
+#define LCDS43 (0x0800) /* LCD Segment 43 enable. */
+#define LCDS44 (0x1000) /* LCD Segment 44 enable. */
+#define LCDS45 (0x2000) /* LCD Segment 45 enable. */
+#define LCDS46 (0x4000) /* LCD Segment 46 enable. */
+#define LCDS47 (0x8000) /* LCD Segment 47 enable. */
+
+// LCDCPCTL2
+#define LCDS32_L (0x0001) /* LCD Segment 32 enable. */
+#define LCDS33_L (0x0002) /* LCD Segment 33 enable. */
+#define LCDS34_L (0x0004) /* LCD Segment 34 enable. */
+#define LCDS35_L (0x0008) /* LCD Segment 35 enable. */
+#define LCDS36_L (0x0010) /* LCD Segment 36 enable. */
+#define LCDS37_L (0x0020) /* LCD Segment 37 enable. */
+#define LCDS38_L (0x0040) /* LCD Segment 38 enable. */
+#define LCDS39_L (0x0080) /* LCD Segment 39 enable. */
+
+// LCDCPCTL2
+#define LCDS40_H (0x0001) /* LCD Segment 40 enable. */
+#define LCDS41_H (0x0002) /* LCD Segment 41 enable. */
+#define LCDS42_H (0x0004) /* LCD Segment 42 enable. */
+#define LCDS43_H (0x0008) /* LCD Segment 43 enable. */
+#define LCDS44_H (0x0010) /* LCD Segment 44 enable. */
+#define LCDS45_H (0x0020) /* LCD Segment 45 enable. */
+#define LCDS46_H (0x0040) /* LCD Segment 46 enable. */
+#define LCDS47_H (0x0080) /* LCD Segment 47 enable. */
+
+// LCDCCPCTL
+#define LCDCPDIS0 (0x0001) /* LCD charge pump disable */
+#define LCDCPDIS1 (0x0002) /* LCD charge pump disable */
+#define LCDCPDIS2 (0x0004) /* LCD charge pump disable */
+#define LCDCPDIS3 (0x0008) /* LCD charge pump disable */
+#define LCDCPDIS4 (0x0010) /* LCD charge pump disable */
+#define LCDCPDIS5 (0x0020) /* LCD charge pump disable */
+#define LCDCPDIS6 (0x0040) /* LCD charge pump disable */
+#define LCDCPDIS7 (0x0080) /* LCD charge pump disable */
+#define LCDCPCLKSYNC (0x8000) /* LCD charge pump clock synchronization */
+
+// LCDCCPCTL
+#define LCDCPDIS0_L (0x0001) /* LCD charge pump disable */
+#define LCDCPDIS1_L (0x0002) /* LCD charge pump disable */
+#define LCDCPDIS2_L (0x0004) /* LCD charge pump disable */
+#define LCDCPDIS3_L (0x0008) /* LCD charge pump disable */
+#define LCDCPDIS4_L (0x0010) /* LCD charge pump disable */
+#define LCDCPDIS5_L (0x0020) /* LCD charge pump disable */
+#define LCDCPDIS6_L (0x0040) /* LCD charge pump disable */
+#define LCDCPDIS7_L (0x0080) /* LCD charge pump disable */
+
+// LCDCCPCTL
+#define LCDCPCLKSYNC_H (0x0080) /* LCD charge pump clock synchronization */
+
+sfr_b(LCDM1); /* LCD Memory 1 */
+#define LCDMEM_ LCDM1 /* LCD Memory */
+#ifndef __STDC__
+#define LCDMEM LCDM1 /* LCD Memory (for assembler) */
+#else
+#define LCDMEM ((volatile char*) &LCDM1) /* LCD Memory (for C) */
+#endif
+sfr_b(LCDM2); /* LCD Memory 2 */
+sfr_b(LCDM3); /* LCD Memory 3 */
+sfr_b(LCDM4); /* LCD Memory 4 */
+sfr_b(LCDM5); /* LCD Memory 5 */
+sfr_b(LCDM6); /* LCD Memory 6 */
+sfr_b(LCDM7); /* LCD Memory 7 */
+sfr_b(LCDM8); /* LCD Memory 8 */
+sfr_b(LCDM9); /* LCD Memory 9 */
+sfr_b(LCDM10); /* LCD Memory 10 */
+sfr_b(LCDM11); /* LCD Memory 11 */
+sfr_b(LCDM12); /* LCD Memory 12 */
+sfr_b(LCDM13); /* LCD Memory 13 */
+sfr_b(LCDM14); /* LCD Memory 14 */
+sfr_b(LCDM15); /* LCD Memory 15 */
+sfr_b(LCDM16); /* LCD Memory 16 */
+sfr_b(LCDM17); /* LCD Memory 17 */
+sfr_b(LCDM18); /* LCD Memory 18 */
+sfr_b(LCDM19); /* LCD Memory 19 */
+sfr_b(LCDM20); /* LCD Memory 20 */
+sfr_b(LCDM21); /* LCD Memory 21 */
+sfr_b(LCDM22); /* LCD Memory 22 */
+sfr_b(LCDM23); /* LCD Memory 23 */
+sfr_b(LCDM24); /* LCD Memory 24 */
+sfr_b(LCDM25); /* LCD Memory 25 */
+sfr_b(LCDM26); /* LCD Memory 26 */
+sfr_b(LCDM27); /* LCD Memory 27 */
+sfr_b(LCDM28); /* LCD Memory 28 */
+sfr_b(LCDM29); /* LCD Memory 29 */
+sfr_b(LCDM30); /* LCD Memory 30 */
+sfr_b(LCDM31); /* LCD Memory 31 */
+sfr_b(LCDM32); /* LCD Memory 32 */
+sfr_b(LCDM33); /* LCD Memory 33 */
+sfr_b(LCDM34); /* LCD Memory 34 */
+sfr_b(LCDM35); /* LCD Memory 35 */
+sfr_b(LCDM36); /* LCD Memory 36 */
+sfr_b(LCDM37); /* LCD Memory 37 */
+sfr_b(LCDM38); /* LCD Memory 38 */
+sfr_b(LCDM39); /* LCD Memory 39 */
+sfr_b(LCDM40); /* LCD Memory 40 */
+sfr_b(LCDM41); /* LCD Memory 41 */
+sfr_b(LCDM42); /* LCD Memory 42 */
+sfr_b(LCDM43); /* LCD Memory 43 */
+
+sfr_b(LCDBM1); /* LCD Blinking Memory 1 */
+#define LCDBMEM_ LCDBM1 /* LCD Blinking Memory */
+#ifndef __STDC__
+#define LCDBMEM (LCDBM1) /* LCD Blinking Memory (for assembler) */
+#else
+#define LCDBMEM ((volatile char*) &LCDBM1) /* LCD Blinking Memory (for C) */
+#endif
+sfr_b(LCDBM2); /* LCD Blinking Memory 2 */
+sfr_b(LCDBM3); /* LCD Blinking Memory 3 */
+sfr_b(LCDBM4); /* LCD Blinking Memory 4 */
+sfr_b(LCDBM5); /* LCD Blinking Memory 5 */
+sfr_b(LCDBM6); /* LCD Blinking Memory 6 */
+sfr_b(LCDBM7); /* LCD Blinking Memory 7 */
+sfr_b(LCDBM8); /* LCD Blinking Memory 8 */
+sfr_b(LCDBM9); /* LCD Blinking Memory 9 */
+sfr_b(LCDBM10); /* LCD Blinking Memory 10 */
+sfr_b(LCDBM11); /* LCD Blinking Memory 11 */
+sfr_b(LCDBM12); /* LCD Blinking Memory 12 */
+sfr_b(LCDBM13); /* LCD Blinking Memory 13 */
+sfr_b(LCDBM14); /* LCD Blinking Memory 14 */
+sfr_b(LCDBM15); /* LCD Blinking Memory 15 */
+sfr_b(LCDBM16); /* LCD Blinking Memory 16 */
+sfr_b(LCDBM17); /* LCD Blinking Memory 17 */
+sfr_b(LCDBM18); /* LCD Blinking Memory 18 */
+sfr_b(LCDBM19); /* LCD Blinking Memory 19 */
+sfr_b(LCDBM20); /* LCD Blinking Memory 20 */
+sfr_b(LCDBM21); /* LCD Blinking Memory 21 */
+sfr_b(LCDBM22); /* LCD Blinking Memory 22 */
+
+/* LCDCIV Definitions */
+#define LCDCIV_NONE (0x0000) /* No Interrupt pending */
+#define LCDCIV_LCDNOCAPIFG (0x0002) /* No capacitor connected */
+#define LCDCIV_LCDCLKOFFIFG (0x0004) /* Blink, segments off */
+#define LCDCIV_LCDCLKONIFG (0x0006) /* Blink, segments on */
+#define LCDCIV_LCDFRMIFG (0x0008) /* Frame interrupt */
+
+/************************************************************
+* Memory Protection Unit
+************************************************************/
+#define __MSP430_HAS_MPU__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_MPU__ 0x05A0
+#define MPU_BASE __MSP430_BASEADDRESS_MPU__
+
+sfr_w(MPUCTL0); /* MPU Control Register 0 */
+sfr_b(MPUCTL0_L); /* MPU Control Register 0 */
+sfr_b(MPUCTL0_H); /* MPU Control Register 0 */
+sfr_w(MPUCTL1); /* MPU Control Register 1 */
+sfr_b(MPUCTL1_L); /* MPU Control Register 1 */
+sfr_b(MPUCTL1_H); /* MPU Control Register 1 */
+sfr_w(MPUSEGB2); /* MPU Segmentation Border 2 Register */
+sfr_b(MPUSEGB2_L); /* MPU Segmentation Border 2 Register */
+sfr_b(MPUSEGB2_H); /* MPU Segmentation Border 2 Register */
+sfr_w(MPUSEGB1); /* MPU Segmentation Border 1 Register */
+sfr_b(MPUSEGB1_L); /* MPU Segmentation Border 1 Register */
+sfr_b(MPUSEGB1_H); /* MPU Segmentation Border 1 Register */
+sfr_w(MPUSAM); /* MPU Access Management Register */
+sfr_b(MPUSAM_L); /* MPU Access Management Register */
+sfr_b(MPUSAM_H); /* MPU Access Management Register */
+sfr_w(MPUIPC0); /* MPU IP Control 0 Register */
+sfr_b(MPUIPC0_L); /* MPU IP Control 0 Register */
+sfr_b(MPUIPC0_H); /* MPU IP Control 0 Register */
+sfr_w(MPUIPSEGB2); /* MPU IP Segment Border 2 Register */
+sfr_b(MPUIPSEGB2_L); /* MPU IP Segment Border 2 Register */
+sfr_b(MPUIPSEGB2_H); /* MPU IP Segment Border 2 Register */
+sfr_w(MPUIPSEGB1); /* MPU IP Segment Border 1 Register */
+sfr_b(MPUIPSEGB1_L); /* MPU IP Segment Border 1 Register */
+sfr_b(MPUIPSEGB1_H); /* MPU IP Segment Border 1 Register */
+
+/* MPUCTL0 Control Bits */
+#define MPUENA (0x0001) /* MPU Enable */
+#define MPULOCK (0x0002) /* MPU Lock */
+#define MPUSEGIE (0x0010) /* MPU Enable NMI on Segment violation */
+
+/* MPUCTL0 Control Bits */
+#define MPUENA_L (0x0001) /* MPU Enable */
+#define MPULOCK_L (0x0002) /* MPU Lock */
+#define MPUSEGIE_L (0x0010) /* MPU Enable NMI on Segment violation */
+
+#define MPUPW (0xA500) /* MPU Access Password */
+#define MPUPW_H (0xA5) /* MPU Access Password */
+
+/* MPUCTL1 Control Bits */
+#define MPUSEG1IFG (0x0001) /* MPU Main Memory Segment 1 violation interupt flag */
+#define MPUSEG2IFG (0x0002) /* MPU Main Memory Segment 2 violation interupt flag */
+#define MPUSEG3IFG (0x0004) /* MPU Main Memory Segment 3 violation interupt flag */
+#define MPUSEGIIFG (0x0008) /* MPU Info Memory Segment violation interupt flag */
+#define MPUSEGIPIFG (0x0010) /* MPU IP Memory Segment violation interupt flag */
+
+/* MPUCTL1 Control Bits */
+#define MPUSEG1IFG_L (0x0001) /* MPU Main Memory Segment 1 violation interupt flag */
+#define MPUSEG2IFG_L (0x0002) /* MPU Main Memory Segment 2 violation interupt flag */
+#define MPUSEG3IFG_L (0x0004) /* MPU Main Memory Segment 3 violation interupt flag */
+#define MPUSEGIIFG_L (0x0008) /* MPU Info Memory Segment violation interupt flag */
+#define MPUSEGIPIFG_L (0x0010) /* MPU IP Memory Segment violation interupt flag */
+
+/* MPUSEGB2 Control Bits */
+
+/* MPUSEGB2 Control Bits */
+
+/* MPUSEGB2 Control Bits */
+
+/* MPUSEGB1 Control Bits */
+
+/* MPUSEGB1 Control Bits */
+
+/* MPUSEGB1 Control Bits */
+
+/* MPUSAM Control Bits */
+#define MPUSEG1RE (0x0001) /* MPU Main memory Segment 1 Read enable */
+#define MPUSEG1WE (0x0002) /* MPU Main memory Segment 1 Write enable */
+#define MPUSEG1XE (0x0004) /* MPU Main memory Segment 1 Execute enable */
+#define MPUSEG1VS (0x0008) /* MPU Main memory Segment 1 Violation select */
+#define MPUSEG2RE (0x0010) /* MPU Main memory Segment 2 Read enable */
+#define MPUSEG2WE (0x0020) /* MPU Main memory Segment 2 Write enable */
+#define MPUSEG2XE (0x0040) /* MPU Main memory Segment 2 Execute enable */
+#define MPUSEG2VS (0x0080) /* MPU Main memory Segment 2 Violation select */
+#define MPUSEG3RE (0x0100) /* MPU Main memory Segment 3 Read enable */
+#define MPUSEG3WE (0x0200) /* MPU Main memory Segment 3 Write enable */
+#define MPUSEG3XE (0x0400) /* MPU Main memory Segment 3 Execute enable */
+#define MPUSEG3VS (0x0800) /* MPU Main memory Segment 3 Violation select */
+#define MPUSEGIRE (0x1000) /* MPU Info memory Segment Read enable */
+#define MPUSEGIWE (0x2000) /* MPU Info memory Segment Write enable */
+#define MPUSEGIXE (0x4000) /* MPU Info memory Segment Execute enable */
+#define MPUSEGIVS (0x8000) /* MPU Info memory Segment Violation select */
+
+/* MPUSAM Control Bits */
+#define MPUSEG1RE_L (0x0001) /* MPU Main memory Segment 1 Read enable */
+#define MPUSEG1WE_L (0x0002) /* MPU Main memory Segment 1 Write enable */
+#define MPUSEG1XE_L (0x0004) /* MPU Main memory Segment 1 Execute enable */
+#define MPUSEG1VS_L (0x0008) /* MPU Main memory Segment 1 Violation select */
+#define MPUSEG2RE_L (0x0010) /* MPU Main memory Segment 2 Read enable */
+#define MPUSEG2WE_L (0x0020) /* MPU Main memory Segment 2 Write enable */
+#define MPUSEG2XE_L (0x0040) /* MPU Main memory Segment 2 Execute enable */
+#define MPUSEG2VS_L (0x0080) /* MPU Main memory Segment 2 Violation select */
+
+/* MPUSAM Control Bits */
+#define MPUSEG3RE_H (0x0001) /* MPU Main memory Segment 3 Read enable */
+#define MPUSEG3WE_H (0x0002) /* MPU Main memory Segment 3 Write enable */
+#define MPUSEG3XE_H (0x0004) /* MPU Main memory Segment 3 Execute enable */
+#define MPUSEG3VS_H (0x0008) /* MPU Main memory Segment 3 Violation select */
+#define MPUSEGIRE_H (0x0010) /* MPU Info memory Segment Read enable */
+#define MPUSEGIWE_H (0x0020) /* MPU Info memory Segment Write enable */
+#define MPUSEGIXE_H (0x0040) /* MPU Info memory Segment Execute enable */
+#define MPUSEGIVS_H (0x0080) /* MPU Info memory Segment Violation select */
+
+/* MPUIPC0 Control Bits */
+#define MPUIPVS (0x0020) /* MPU MPU IP protection segment Violation Select */
+#define MPUIPENA (0x0040) /* MPU MPU IP Protection Enable */
+#define MPUIPLOCK (0x0080) /* MPU IP Protection Lock */
+
+/* MPUIPC0 Control Bits */
+#define MPUIPVS_L (0x0020) /* MPU MPU IP protection segment Violation Select */
+#define MPUIPENA_L (0x0040) /* MPU MPU IP Protection Enable */
+#define MPUIPLOCK_L (0x0080) /* MPU IP Protection Lock */
+
+/* MPUIPSEGB2 Control Bits */
+
+/* MPUIPSEGB2 Control Bits */
+
+/* MPUIPSEGB2 Control Bits */
+
+/* MPUIPSEGB1 Control Bits */
+
+/* MPUIPSEGB1 Control Bits */
+
+/* MPUIPSEGB1 Control Bits */
+
+/************************************************************
+* HARDWARE MULTIPLIER 32Bit
+************************************************************/
+#define __MSP430_HAS_MPY32__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_MPY32__ 0x04C0
+#define MPY32_BASE __MSP430_BASEADDRESS_MPY32__
+
+sfr_w(MPY); /* Multiply Unsigned/Operand 1 */
+sfr_b(MPY_L); /* Multiply Unsigned/Operand 1 */
+sfr_b(MPY_H); /* Multiply Unsigned/Operand 1 */
+sfr_w(MPYS); /* Multiply Signed/Operand 1 */
+sfr_b(MPYS_L); /* Multiply Signed/Operand 1 */
+sfr_b(MPYS_H); /* Multiply Signed/Operand 1 */
+sfr_w(MAC); /* Multiply Unsigned and Accumulate/Operand 1 */
+sfr_b(MAC_L); /* Multiply Unsigned and Accumulate/Operand 1 */
+sfr_b(MAC_H); /* Multiply Unsigned and Accumulate/Operand 1 */
+sfr_w(MACS); /* Multiply Signed and Accumulate/Operand 1 */
+sfr_b(MACS_L); /* Multiply Signed and Accumulate/Operand 1 */
+sfr_b(MACS_H); /* Multiply Signed and Accumulate/Operand 1 */
+sfr_w(OP2); /* Operand 2 */
+sfr_b(OP2_L); /* Operand 2 */
+sfr_b(OP2_H); /* Operand 2 */
+sfr_w(RESLO); /* Result Low Word */
+sfr_b(RESLO_L); /* Result Low Word */
+sfr_b(RESLO_H); /* Result Low Word */
+sfr_w(RESHI); /* Result High Word */
+sfr_b(RESHI_L); /* Result High Word */
+sfr_b(RESHI_H); /* Result High Word */
+sfr_w(SUMEXT); /* Sum Extend */
+sfr_b(SUMEXT_L); /* Sum Extend */
+sfr_b(SUMEXT_H); /* Sum Extend */
+
+sfr_w(MPY32L); /* 32-bit operand 1 - multiply - low word */
+sfr_b(MPY32L_L); /* 32-bit operand 1 - multiply - low word */
+sfr_b(MPY32L_H); /* 32-bit operand 1 - multiply - low word */
+sfr_w(MPY32H); /* 32-bit operand 1 - multiply - high word */
+sfr_b(MPY32H_L); /* 32-bit operand 1 - multiply - high word */
+sfr_b(MPY32H_H); /* 32-bit operand 1 - multiply - high word */
+sfr_w(MPYS32L); /* 32-bit operand 1 - signed multiply - low word */
+sfr_b(MPYS32L_L); /* 32-bit operand 1 - signed multiply - low word */
+sfr_b(MPYS32L_H); /* 32-bit operand 1 - signed multiply - low word */
+sfr_w(MPYS32H); /* 32-bit operand 1 - signed multiply - high word */
+sfr_b(MPYS32H_L); /* 32-bit operand 1 - signed multiply - high word */
+sfr_b(MPYS32H_H); /* 32-bit operand 1 - signed multiply - high word */
+sfr_w(MAC32L); /* 32-bit operand 1 - multiply accumulate - low word */
+sfr_b(MAC32L_L); /* 32-bit operand 1 - multiply accumulate - low word */
+sfr_b(MAC32L_H); /* 32-bit operand 1 - multiply accumulate - low word */
+sfr_w(MAC32H); /* 32-bit operand 1 - multiply accumulate - high word */
+sfr_b(MAC32H_L); /* 32-bit operand 1 - multiply accumulate - high word */
+sfr_b(MAC32H_H); /* 32-bit operand 1 - multiply accumulate - high word */
+sfr_w(MACS32L); /* 32-bit operand 1 - signed multiply accumulate - low word */
+sfr_b(MACS32L_L); /* 32-bit operand 1 - signed multiply accumulate - low word */
+sfr_b(MACS32L_H); /* 32-bit operand 1 - signed multiply accumulate - low word */
+sfr_w(MACS32H); /* 32-bit operand 1 - signed multiply accumulate - high word */
+sfr_b(MACS32H_L); /* 32-bit operand 1 - signed multiply accumulate - high word */
+sfr_b(MACS32H_H); /* 32-bit operand 1 - signed multiply accumulate - high word */
+sfr_w(OP2L); /* 32-bit operand 2 - low word */
+sfr_b(OP2L_L); /* 32-bit operand 2 - low word */
+sfr_b(OP2L_H); /* 32-bit operand 2 - low word */
+sfr_w(OP2H); /* 32-bit operand 2 - high word */
+sfr_b(OP2H_L); /* 32-bit operand 2 - high word */
+sfr_b(OP2H_H); /* 32-bit operand 2 - high word */
+sfr_w(RES0); /* 32x32-bit result 0 - least significant word */
+sfr_b(RES0_L); /* 32x32-bit result 0 - least significant word */
+sfr_b(RES0_H); /* 32x32-bit result 0 - least significant word */
+sfr_w(RES1); /* 32x32-bit result 1 */
+sfr_b(RES1_L); /* 32x32-bit result 1 */
+sfr_b(RES1_H); /* 32x32-bit result 1 */
+sfr_w(RES2); /* 32x32-bit result 2 */
+sfr_b(RES2_L); /* 32x32-bit result 2 */
+sfr_b(RES2_H); /* 32x32-bit result 2 */
+sfr_w(RES3); /* 32x32-bit result 3 - most significant word */
+sfr_b(RES3_L); /* 32x32-bit result 3 - most significant word */
+sfr_b(RES3_H); /* 32x32-bit result 3 - most significant word */
+sfr_w(MPY32CTL0); /* MPY32 Control Register 0 */
+sfr_b(MPY32CTL0_L); /* MPY32 Control Register 0 */
+sfr_b(MPY32CTL0_H); /* MPY32 Control Register 0 */
+
+#define MPY_B MPY_L /* Multiply Unsigned/Operand 1 (Byte Access) */
+#define MPYS_B MPYS_L /* Multiply Signed/Operand 1 (Byte Access) */
+#define MAC_B MAC_L /* Multiply Unsigned and Accumulate/Operand 1 (Byte Access) */
+#define MACS_B MACS_L /* Multiply Signed and Accumulate/Operand 1 (Byte Access) */
+#define OP2_B OP2_L /* Operand 2 (Byte Access) */
+#define MPY32L_B MPY32L_L /* 32-bit operand 1 - multiply - low word (Byte Access) */
+#define MPY32H_B MPY32H_L /* 32-bit operand 1 - multiply - high word (Byte Access) */
+#define MPYS32L_B MPYS32L_L /* 32-bit operand 1 - signed multiply - low word (Byte Access) */
+#define MPYS32H_B MPYS32H_L /* 32-bit operand 1 - signed multiply - high word (Byte Access) */
+#define MAC32L_B MAC32L_L /* 32-bit operand 1 - multiply accumulate - low word (Byte Access) */
+#define MAC32H_B MAC32H_L /* 32-bit operand 1 - multiply accumulate - high word (Byte Access) */
+#define MACS32L_B MACS32L_L /* 32-bit operand 1 - signed multiply accumulate - low word (Byte Access) */
+#define MACS32H_B MACS32H_L /* 32-bit operand 1 - signed multiply accumulate - high word (Byte Access) */
+#define OP2L_B OP2L_L /* 32-bit operand 2 - low word (Byte Access) */
+#define OP2H_B OP2H_L /* 32-bit operand 2 - high word (Byte Access) */
+
+/* MPY32CTL0 Control Bits */
+#define MPYC (0x0001) /* Carry of the multiplier */
+//#define RESERVED (0x0002) /* Reserved */
+#define MPYFRAC (0x0004) /* Fractional mode */
+#define MPYSAT (0x0008) /* Saturation mode */
+#define MPYM0 (0x0010) /* Multiplier mode Bit:0 */
+#define MPYM1 (0x0020) /* Multiplier mode Bit:1 */
+#define OP1_32 (0x0040) /* Bit-width of operand 1 0:16Bit / 1:32Bit */
+#define OP2_32 (0x0080) /* Bit-width of operand 2 0:16Bit / 1:32Bit */
+#define MPYDLYWRTEN (0x0100) /* Delayed write enable */
+#define MPYDLY32 (0x0200) /* Delayed write mode */
+
+/* MPY32CTL0 Control Bits */
+#define MPYC_L (0x0001) /* Carry of the multiplier */
+//#define RESERVED (0x0002) /* Reserved */
+#define MPYFRAC_L (0x0004) /* Fractional mode */
+#define MPYSAT_L (0x0008) /* Saturation mode */
+#define MPYM0_L (0x0010) /* Multiplier mode Bit:0 */
+#define MPYM1_L (0x0020) /* Multiplier mode Bit:1 */
+#define OP1_32_L (0x0040) /* Bit-width of operand 1 0:16Bit / 1:32Bit */
+#define OP2_32_L (0x0080) /* Bit-width of operand 2 0:16Bit / 1:32Bit */
+
+/* MPY32CTL0 Control Bits */
+//#define RESERVED (0x0002) /* Reserved */
+#define MPYDLYWRTEN_H (0x0001) /* Delayed write enable */
+#define MPYDLY32_H (0x0002) /* Delayed write mode */
+
+#define MPYM_0 (0x0000) /* Multiplier mode: MPY */
+#define MPYM_1 (0x0010) /* Multiplier mode: MPYS */
+#define MPYM_2 (0x0020) /* Multiplier mode: MAC */
+#define MPYM_3 (0x0030) /* Multiplier mode: MACS */
+#define MPYM__MPY (0x0000) /* Multiplier mode: MPY */
+#define MPYM__MPYS (0x0010) /* Multiplier mode: MPYS */
+#define MPYM__MAC (0x0020) /* Multiplier mode: MAC */
+#define MPYM__MACS (0x0030) /* Multiplier mode: MACS */
+
+/************************************************************
+* PMM - Power Management System for FRAM
+************************************************************/
+#define __MSP430_HAS_PMM_FRAM__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PMM_FRAM__ 0x0120
+#define PMM_BASE __MSP430_BASEADDRESS_PMM_FRAM__
+
+sfr_w(PMMCTL0); /* PMM Control 0 */
+sfr_b(PMMCTL0_L); /* PMM Control 0 */
+sfr_b(PMMCTL0_H); /* PMM Control 0 */
+sfr_w(PMMIFG); /* PMM Interrupt Flag */
+sfr_b(PMMIFG_L); /* PMM Interrupt Flag */
+sfr_b(PMMIFG_H); /* PMM Interrupt Flag */
+sfr_w(PM5CTL0); /* PMM Power Mode 5 Control Register 0 */
+sfr_b(PM5CTL0_L); /* PMM Power Mode 5 Control Register 0 */
+sfr_b(PM5CTL0_H); /* PMM Power Mode 5 Control Register 0 */
+
+#define PMMPW (0xA500) /* PMM Register Write Password */
+#define PMMPW_H (0xA5) /* PMM Register Write Password for high word access */
+
+/* PMMCTL0 Control Bits */
+#define PMMSWBOR (0x0004) /* PMM Software BOR */
+#define PMMSWPOR (0x0008) /* PMM Software POR */
+#define PMMREGOFF (0x0010) /* PMM Turn Regulator off */
+#define SVSHE (0x0040) /* SVS high side enable */
+#define PMMLPRST (0x0080) /* PMM Low-Power Reset Enable */
+
+/* PMMCTL0 Control Bits */
+#define PMMSWBOR_L (0x0004) /* PMM Software BOR */
+#define PMMSWPOR_L (0x0008) /* PMM Software POR */
+#define PMMREGOFF_L (0x0010) /* PMM Turn Regulator off */
+#define SVSHE_L (0x0040) /* SVS high side enable */
+#define PMMLPRST_L (0x0080) /* PMM Low-Power Reset Enable */
+
+/* PMMIFG Control Bits */
+#define PMMBORIFG (0x0100) /* PMM Software BOR interrupt flag */
+#define PMMRSTIFG (0x0200) /* PMM RESET pin interrupt flag */
+#define PMMPORIFG (0x0400) /* PMM Software POR interrupt flag */
+#define SVSHIFG (0x2000) /* SVS low side interrupt flag */
+#define PMMLPM5IFG (0x8000) /* LPM5 indication Flag */
+
+/* PMMIFG Control Bits */
+#define PMMBORIFG_H (0x0001) /* PMM Software BOR interrupt flag */
+#define PMMRSTIFG_H (0x0002) /* PMM RESET pin interrupt flag */
+#define PMMPORIFG_H (0x0004) /* PMM Software POR interrupt flag */
+#define SVSHIFG_H (0x0020) /* SVS low side interrupt flag */
+#define PMMLPM5IFG_H (0x0080) /* LPM5 indication Flag */
+
+/* PM5CTL0 Power Mode 5 Control Bits */
+#define LOCKLPM5 (0x0001) /* Lock I/O pin configuration upon entry/exit to/from LPM5 */
+
+/* PM5CTL0 Power Mode 5 Control Bits */
+#define LOCKLPM5_L (0x0001) /* Lock I/O pin configuration upon entry/exit to/from LPM5 */
+
+
+/************************************************************
+* DIGITAL I/O Port1/2 Pull up / Pull down Resistors
+************************************************************/
+#define __MSP430_HAS_PORT1_R__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORT1_R__ 0x0200
+#define P1_BASE __MSP430_BASEADDRESS_PORT1_R__
+#define __MSP430_HAS_PORT2_R__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORT2_R__ 0x0200
+#define P2_BASE __MSP430_BASEADDRESS_PORT2_R__
+#define __MSP430_HAS_PORTA_R__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORTA_R__ 0x0200
+#define PA_BASE __MSP430_BASEADDRESS_PORTA_R__
+#define __MSP430_HAS_P1SEL0__ /* Define for DriverLib */
+#define __MSP430_HAS_P2SEL0__ /* Define for DriverLib */
+#define __MSP430_HAS_PASEL0__ /* Define for DriverLib */
+#define __MSP430_HAS_P1SEL1__ /* Define for DriverLib */
+#define __MSP430_HAS_P2SEL1__ /* Define for DriverLib */
+#define __MSP430_HAS_PASEL1__ /* Define for DriverLib */
+
+sfr_w(PAIN); /* Port A Input */
+sfr_b(PAIN_L); /* Port A Input */
+sfr_b(PAIN_H); /* Port A Input */
+sfr_w(PAOUT); /* Port A Output */
+sfr_b(PAOUT_L); /* Port A Output */
+sfr_b(PAOUT_H); /* Port A Output */
+sfr_w(PADIR); /* Port A Direction */
+sfr_b(PADIR_L); /* Port A Direction */
+sfr_b(PADIR_H); /* Port A Direction */
+sfr_w(PAREN); /* Port A Resistor Enable */
+sfr_b(PAREN_L); /* Port A Resistor Enable */
+sfr_b(PAREN_H); /* Port A Resistor Enable */
+sfr_w(PASEL0); /* Port A Selection 0 */
+sfr_b(PASEL0_L); /* Port A Selection 0 */
+sfr_b(PASEL0_H); /* Port A Selection 0 */
+sfr_w(PASEL1); /* Port A Selection 1 */
+sfr_b(PASEL1_L); /* Port A Selection 1 */
+sfr_b(PASEL1_H); /* Port A Selection 1 */
+sfr_w(PASELC); /* Port A Complement Selection */
+sfr_b(PASELC_L); /* Port A Complement Selection */
+sfr_b(PASELC_H); /* Port A Complement Selection */
+sfr_w(PAIES); /* Port A Interrupt Edge Select */
+sfr_b(PAIES_L); /* Port A Interrupt Edge Select */
+sfr_b(PAIES_H); /* Port A Interrupt Edge Select */
+sfr_w(PAIE); /* Port A Interrupt Enable */
+sfr_b(PAIE_L); /* Port A Interrupt Enable */
+sfr_b(PAIE_H); /* Port A Interrupt Enable */
+sfr_w(PAIFG); /* Port A Interrupt Flag */
+sfr_b(PAIFG_L); /* Port A Interrupt Flag */
+sfr_b(PAIFG_H); /* Port A Interrupt Flag */
+
+
+sfr_w(P1IV); /* Port 1 Interrupt Vector Word */
+sfr_w(P2IV); /* Port 2 Interrupt Vector Word */
+#define P1IN (PAIN_L) /* Port 1 Input */
+#define P1OUT (PAOUT_L) /* Port 1 Output */
+#define P1DIR (PADIR_L) /* Port 1 Direction */
+#define P1REN (PAREN_L) /* Port 1 Resistor Enable */
+#define P1SEL0 (PASEL0_L) /* Port 1 Selection 0 */
+#define P1SEL1 (PASEL1_L) /* Port 1 Selection 1 */
+#define P1SELC (PASELC_L) /* Port 1 Complement Selection */
+#define P1IES (PAIES_L) /* Port 1 Interrupt Edge Select */
+#define P1IE (PAIE_L) /* Port 1 Interrupt Enable */
+#define P1IFG (PAIFG_L) /* Port 1 Interrupt Flag */
+
+//Definitions for P1IV
+#define P1IV_NONE (0x0000) /* No Interrupt pending */
+#define P1IV_P1IFG0 (0x0002) /* P1IV P1IFG.0 */
+#define P1IV_P1IFG1 (0x0004) /* P1IV P1IFG.1 */
+#define P1IV_P1IFG2 (0x0006) /* P1IV P1IFG.2 */
+#define P1IV_P1IFG3 (0x0008) /* P1IV P1IFG.3 */
+#define P1IV_P1IFG4 (0x000A) /* P1IV P1IFG.4 */
+#define P1IV_P1IFG5 (0x000C) /* P1IV P1IFG.5 */
+#define P1IV_P1IFG6 (0x000E) /* P1IV P1IFG.6 */
+#define P1IV_P1IFG7 (0x0010) /* P1IV P1IFG.7 */
+
+#define P2IN (PAIN_H) /* Port 2 Input */
+#define P2OUT (PAOUT_H) /* Port 2 Output */
+#define P2DIR (PADIR_H) /* Port 2 Direction */
+#define P2REN (PAREN_H) /* Port 2 Resistor Enable */
+#define P2SEL0 (PASEL0_H) /* Port 2 Selection 0 */
+#define P2SEL1 (PASEL1_H) /* Port 2 Selection 1 */
+#define P2SELC (PASELC_H) /* Port 2 Complement Selection */
+#define P2IES (PAIES_H) /* Port 2 Interrupt Edge Select */
+#define P2IE (PAIE_H) /* Port 2 Interrupt Enable */
+#define P2IFG (PAIFG_H) /* Port 2 Interrupt Flag */
+
+//Definitions for P2IV
+#define P2IV_NONE (0x0000) /* No Interrupt pending */
+#define P2IV_P2IFG0 (0x0002) /* P2IV P2IFG.0 */
+#define P2IV_P2IFG1 (0x0004) /* P2IV P2IFG.1 */
+#define P2IV_P2IFG2 (0x0006) /* P2IV P2IFG.2 */
+#define P2IV_P2IFG3 (0x0008) /* P2IV P2IFG.3 */
+#define P2IV_P2IFG4 (0x000A) /* P2IV P2IFG.4 */
+#define P2IV_P2IFG5 (0x000C) /* P2IV P2IFG.5 */
+#define P2IV_P2IFG6 (0x000E) /* P2IV P2IFG.6 */
+#define P2IV_P2IFG7 (0x0010) /* P2IV P2IFG.7 */
+
+
+/************************************************************
+* DIGITAL I/O Port3/4 Pull up / Pull down Resistors
+************************************************************/
+#define __MSP430_HAS_PORT3_R__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORT3_R__ 0x0220
+#define P3_BASE __MSP430_BASEADDRESS_PORT3_R__
+#define __MSP430_HAS_PORT4_R__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORT4_R__ 0x0220
+#define P4_BASE __MSP430_BASEADDRESS_PORT4_R__
+#define __MSP430_HAS_PORTB_R__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORTB_R__ 0x0220
+#define PB_BASE __MSP430_BASEADDRESS_PORTB_R__
+#define __MSP430_HAS_P3SEL0__ /* Define for DriverLib */
+#define __MSP430_HAS_P4SEL0__ /* Define for DriverLib */
+#define __MSP430_HAS_PBSEL0__ /* Define for DriverLib */
+#define __MSP430_HAS_P3SEL1__ /* Define for DriverLib */
+#define __MSP430_HAS_P4SEL1__ /* Define for DriverLib */
+#define __MSP430_HAS_PBSEL1__ /* Define for DriverLib */
+
+sfr_w(PBIN); /* Port B Input */
+sfr_b(PBIN_L); /* Port B Input */
+sfr_b(PBIN_H); /* Port B Input */
+sfr_w(PBOUT); /* Port B Output */
+sfr_b(PBOUT_L); /* Port B Output */
+sfr_b(PBOUT_H); /* Port B Output */
+sfr_w(PBDIR); /* Port B Direction */
+sfr_b(PBDIR_L); /* Port B Direction */
+sfr_b(PBDIR_H); /* Port B Direction */
+sfr_w(PBREN); /* Port B Resistor Enable */
+sfr_b(PBREN_L); /* Port B Resistor Enable */
+sfr_b(PBREN_H); /* Port B Resistor Enable */
+sfr_w(PBSEL0); /* Port B Selection 0 */
+sfr_b(PBSEL0_L); /* Port B Selection 0 */
+sfr_b(PBSEL0_H); /* Port B Selection 0 */
+sfr_w(PBSEL1); /* Port B Selection 1 */
+sfr_b(PBSEL1_L); /* Port B Selection 1 */
+sfr_b(PBSEL1_H); /* Port B Selection 1 */
+sfr_w(PBSELC); /* Port B Complement Selection */
+sfr_b(PBSELC_L); /* Port B Complement Selection */
+sfr_b(PBSELC_H); /* Port B Complement Selection */
+sfr_w(PBIES); /* Port B Interrupt Edge Select */
+sfr_b(PBIES_L); /* Port B Interrupt Edge Select */
+sfr_b(PBIES_H); /* Port B Interrupt Edge Select */
+sfr_w(PBIE); /* Port B Interrupt Enable */
+sfr_b(PBIE_L); /* Port B Interrupt Enable */
+sfr_b(PBIE_H); /* Port B Interrupt Enable */
+sfr_w(PBIFG); /* Port B Interrupt Flag */
+sfr_b(PBIFG_L); /* Port B Interrupt Flag */
+sfr_b(PBIFG_H); /* Port B Interrupt Flag */
+
+
+sfr_w(P3IV); /* Port 3 Interrupt Vector Word */
+sfr_w(P4IV); /* Port 4 Interrupt Vector Word */
+#define P3IN (PBIN_L) /* Port 3 Input */
+#define P3OUT (PBOUT_L) /* Port 3 Output */
+#define P3DIR (PBDIR_L) /* Port 3 Direction */
+#define P3REN (PBREN_L) /* Port 3 Resistor Enable */
+#define P3SEL0 (PBSEL0_L) /* Port 3 Selection 0 */
+#define P3SEL1 (PBSEL1_L) /* Port 3 Selection 1 */
+#define P3SELC (PBSELC_L) /* Port 3 Complement Selection */
+#define P3IES (PBIES_L) /* Port 3 Interrupt Edge Select */
+#define P3IE (PBIE_L) /* Port 3 Interrupt Enable */
+#define P3IFG (PBIFG_L) /* Port 3 Interrupt Flag */
+
+//Definitions for P3IV
+#define P3IV_NONE (0x0000) /* No Interrupt pending */
+#define P3IV_P3IFG0 (0x0002) /* P3IV P3IFG.0 */
+#define P3IV_P3IFG1 (0x0004) /* P3IV P3IFG.1 */
+#define P3IV_P3IFG2 (0x0006) /* P3IV P3IFG.2 */
+#define P3IV_P3IFG3 (0x0008) /* P3IV P3IFG.3 */
+#define P3IV_P3IFG4 (0x000A) /* P3IV P3IFG.4 */
+#define P3IV_P3IFG5 (0x000C) /* P3IV P3IFG.5 */
+#define P3IV_P3IFG6 (0x000E) /* P3IV P3IFG.6 */
+#define P3IV_P3IFG7 (0x0010) /* P3IV P3IFG.7 */
+
+#define P4IN (PBIN_H) /* Port 4 Input */
+#define P4OUT (PBOUT_H) /* Port 4 Output */
+#define P4DIR (PBDIR_H) /* Port 4 Direction */
+#define P4REN (PBREN_H) /* Port 4 Resistor Enable */
+#define P4SEL0 (PBSEL0_H) /* Port 4 Selection 0 */
+#define P4SEL1 (PBSEL1_H) /* Port 4 Selection 1 */
+#define P4SELC (PBSELC_H) /* Port 4 Complement Selection */
+#define P4IES (PBIES_H) /* Port 4 Interrupt Edge Select */
+#define P4IE (PBIE_H) /* Port 4 Interrupt Enable */
+#define P4IFG (PBIFG_H) /* Port 4 Interrupt Flag */
+
+//Definitions for P4IV
+#define P4IV_NONE (0x0000) /* No Interrupt pending */
+#define P4IV_P4IFG0 (0x0002) /* P4IV P4IFG.0 */
+#define P4IV_P4IFG1 (0x0004) /* P4IV P4IFG.1 */
+#define P4IV_P4IFG2 (0x0006) /* P4IV P4IFG.2 */
+#define P4IV_P4IFG3 (0x0008) /* P4IV P4IFG.3 */
+#define P4IV_P4IFG4 (0x000A) /* P4IV P4IFG.4 */
+#define P4IV_P4IFG5 (0x000C) /* P4IV P4IFG.5 */
+#define P4IV_P4IFG6 (0x000E) /* P4IV P4IFG.6 */
+#define P4IV_P4IFG7 (0x0010) /* P4IV P4IFG.7 */
+
+
+/************************************************************
+* DIGITAL I/O Port5/6 Pull up / Pull down Resistors
+************************************************************/
+#define __MSP430_HAS_PORT5_R__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORT5_R__ 0x0240
+#define P5_BASE __MSP430_BASEADDRESS_PORT5_R__
+#define __MSP430_HAS_PORT6_R__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORT6_R__ 0x0240
+#define P6_BASE __MSP430_BASEADDRESS_PORT6_R__
+#define __MSP430_HAS_PORTC_R__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORTC_R__ 0x0240
+#define PC_BASE __MSP430_BASEADDRESS_PORTC_R__
+#define __MSP430_HAS_P5SEL0__ /* Define for DriverLib */
+#define __MSP430_HAS_P6SEL0__ /* Define for DriverLib */
+#define __MSP430_HAS_PCSEL0__ /* Define for DriverLib */
+#define __MSP430_HAS_P5SEL1__ /* Define for DriverLib */
+#define __MSP430_HAS_P6SEL1__ /* Define for DriverLib */
+#define __MSP430_HAS_PCSEL1__ /* Define for DriverLib */
+
+sfr_w(PCIN); /* Port C Input */
+sfr_b(PCIN_L); /* Port C Input */
+sfr_b(PCIN_H); /* Port C Input */
+sfr_w(PCOUT); /* Port C Output */
+sfr_b(PCOUT_L); /* Port C Output */
+sfr_b(PCOUT_H); /* Port C Output */
+sfr_w(PCDIR); /* Port C Direction */
+sfr_b(PCDIR_L); /* Port C Direction */
+sfr_b(PCDIR_H); /* Port C Direction */
+sfr_w(PCREN); /* Port C Resistor Enable */
+sfr_b(PCREN_L); /* Port C Resistor Enable */
+sfr_b(PCREN_H); /* Port C Resistor Enable */
+sfr_w(PCSEL0); /* Port C Selection 0 */
+sfr_b(PCSEL0_L); /* Port C Selection 0 */
+sfr_b(PCSEL0_H); /* Port C Selection 0 */
+sfr_w(PCSEL1); /* Port C Selection 1 */
+sfr_b(PCSEL1_L); /* Port C Selection 1 */
+sfr_b(PCSEL1_H); /* Port C Selection 1 */
+sfr_w(PCSELC); /* Port C Complement Selection */
+sfr_b(PCSELC_L); /* Port C Complement Selection */
+sfr_b(PCSELC_H); /* Port C Complement Selection */
+
+
+#define P5IN (PCIN_L) /* Port 5 Input */
+#define P5OUT (PCOUT_L) /* Port 5 Output */
+#define P5DIR (PCDIR_L) /* Port 5 Direction */
+#define P5REN (PCREN_L) /* Port 5 Resistor Enable */
+#define P5SEL0 (PCSEL0_L) /* Port 5 Selection 0 */
+#define P5SEL1 (PCSEL1_L) /* Port 5 Selection 1 */
+#define P5SELC (PCSELC_L) /* Port 5 Complement Selection */
+
+#define P6IN (PCIN_H) /* Port 6 Input */
+#define P6OUT (PCOUT_H) /* Port 6 Output */
+#define P6DIR (PCDIR_H) /* Port 6 Direction */
+#define P6REN (PCREN_H) /* Port 6 Resistor Enable */
+#define P6SEL0 (PCSEL0_H) /* Port 6 Selection 0 */
+#define P6SEL1 (PCSEL1_H) /* Port 6 Selection 1 */
+#define P6SELC (PCSELC_H) /* Port 6 Complement Selection */
+
+
+/************************************************************
+* DIGITAL I/O Port7/8 Pull up / Pull down Resistors
+************************************************************/
+#define __MSP430_HAS_PORT7_R__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORT7_R__ 0x0260
+#define P7_BASE __MSP430_BASEADDRESS_PORT7_R__
+#define __MSP430_HAS_PORT8_R__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORT8_R__ 0x0260
+#define P8_BASE __MSP430_BASEADDRESS_PORT8_R__
+#define __MSP430_HAS_PORTD_R__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORTD_R__ 0x0260
+#define PD_BASE __MSP430_BASEADDRESS_PORTD_R__
+#define __MSP430_HAS_P7SEL0__ /* Define for DriverLib */
+#define __MSP430_HAS_P8SEL0__ /* Define for DriverLib */
+#define __MSP430_HAS_PDSEL0__ /* Define for DriverLib */
+#define __MSP430_HAS_P7SEL1__ /* Define for DriverLib */
+#define __MSP430_HAS_P8SEL1__ /* Define for DriverLib */
+#define __MSP430_HAS_PDSEL1__ /* Define for DriverLib */
+
+sfr_w(PDIN); /* Port D Input */
+sfr_b(PDIN_L); /* Port D Input */
+sfr_b(PDIN_H); /* Port D Input */
+sfr_w(PDOUT); /* Port D Output */
+sfr_b(PDOUT_L); /* Port D Output */
+sfr_b(PDOUT_H); /* Port D Output */
+sfr_w(PDDIR); /* Port D Direction */
+sfr_b(PDDIR_L); /* Port D Direction */
+sfr_b(PDDIR_H); /* Port D Direction */
+sfr_w(PDREN); /* Port D Resistor Enable */
+sfr_b(PDREN_L); /* Port D Resistor Enable */
+sfr_b(PDREN_H); /* Port D Resistor Enable */
+sfr_w(PDSEL0); /* Port D Selection 0 */
+sfr_b(PDSEL0_L); /* Port D Selection 0 */
+sfr_b(PDSEL0_H); /* Port D Selection 0 */
+sfr_w(PDSEL1); /* Port D Selection 1 */
+sfr_b(PDSEL1_L); /* Port D Selection 1 */
+sfr_b(PDSEL1_H); /* Port D Selection 1 */
+sfr_w(PDSELC); /* Port D Complement Selection */
+sfr_b(PDSELC_L); /* Port D Complement Selection */
+sfr_b(PDSELC_H); /* Port D Complement Selection */
+
+
+#define P7IN (PDIN_L) /* Port 7 Input */
+#define P7OUT (PDOUT_L) /* Port 7 Output */
+#define P7DIR (PDDIR_L) /* Port 7 Direction */
+#define P7REN (PDREN_L) /* Port 7 Resistor Enable */
+#define P7SEL0 (PDSEL0_L) /* Port 7 Selection 0 */
+#define P7SEL1 (PDSEL1_L) /* Port 7 Selection 1 */
+#define P7SELC (PDSELC_L) /* Port 7 Complement Selection */
+
+#define P8IN (PDIN_H) /* Port 8 Input */
+#define P8OUT (PDOUT_H) /* Port 8 Output */
+#define P8DIR (PDDIR_H) /* Port 8 Direction */
+#define P8REN (PDREN_H) /* Port 8 Resistor Enable */
+#define P8SEL0 (PDSEL0_H) /* Port 8 Selection 0 */
+#define P8SEL1 (PDSEL1_H) /* Port 8 Selection 1 */
+#define P8SELC (PDSELC_H) /* Port 8 Complement Selection */
+
+
+/************************************************************
+* DIGITAL I/O Port9/10 Pull up / Pull down Resistors
+************************************************************/
+#define __MSP430_HAS_PORT9_R__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORT9_R__ 0x0280
+#define P9_BASE __MSP430_BASEADDRESS_PORT9_R__
+#define __MSP430_HAS_PORT10_R__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORT10_R__ 0x0280
+#define P10_BASE __MSP430_BASEADDRESS_PORT10_R__
+#define __MSP430_HAS_PORTE_R__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORTE_R__ 0x0280
+#define PE_BASE __MSP430_BASEADDRESS_PORTE_R__
+#define __MSP430_HAS_P9SEL0__ /* Define for DriverLib */
+#define __MSP430_HAS_P10SEL0__ /* Define for DriverLib */
+#define __MSP430_HAS_PESEL0__ /* Define for DriverLib */
+#define __MSP430_HAS_P9SEL1__ /* Define for DriverLib */
+#define __MSP430_HAS_P10SEL1__ /* Define for DriverLib */
+#define __MSP430_HAS_PESEL1__ /* Define for DriverLib */
+
+sfr_w(PEIN); /* Port E Input */
+sfr_b(PEIN_L); /* Port E Input */
+sfr_b(PEIN_H); /* Port E Input */
+sfr_w(PEOUT); /* Port E Output */
+sfr_b(PEOUT_L); /* Port E Output */
+sfr_b(PEOUT_H); /* Port E Output */
+sfr_w(PEDIR); /* Port E Direction */
+sfr_b(PEDIR_L); /* Port E Direction */
+sfr_b(PEDIR_H); /* Port E Direction */
+sfr_w(PEREN); /* Port E Resistor Enable */
+sfr_b(PEREN_L); /* Port E Resistor Enable */
+sfr_b(PEREN_H); /* Port E Resistor Enable */
+sfr_w(PESEL0); /* Port E Selection 0 */
+sfr_b(PESEL0_L); /* Port E Selection 0 */
+sfr_b(PESEL0_H); /* Port E Selection 0 */
+sfr_w(PESEL1); /* Port E Selection 1 */
+sfr_b(PESEL1_L); /* Port E Selection 1 */
+sfr_b(PESEL1_H); /* Port E Selection 1 */
+sfr_w(PESELC); /* Port E Complement Selection */
+sfr_b(PESELC_L); /* Port E Complement Selection */
+sfr_b(PESELC_H); /* Port E Complement Selection */
+
+
+#define P9IN (PEIN_L) /* Port 9 Input */
+#define P9OUT (PEOUT_L) /* Port 9 Output */
+#define P9DIR (PEDIR_L) /* Port 9 Direction */
+#define P9REN (PEREN_L) /* Port 9 Resistor Enable */
+#define P9SEL0 (PESEL0_L) /* Port 9 Selection 0 */
+#define P9SEL1 (PESEL1_L) /* Port 9 Selection 1 */
+#define P9SELC (PESELC_L) /* Port 9 Complement Selection */
+
+#define P10IN (PEIN_H) /* Port 10 Input */
+#define P10OUT (PEOUT_H) /* Port 10 Output */
+#define P10DIR (PEDIR_H) /* Port 10 Direction */
+#define P10REN (PEREN_H) /* Port 10 Resistor Enable */
+#define P10SEL0 (PESEL0_H) /* Port 10 Selection 0 */
+#define P10SEL1 (PESEL1_H) /* Port 10 Selection 1 */
+#define P10SELC (PESELC_H) /* Port 10 Complement Selection */
+
+
+/************************************************************
+* DIGITAL I/O PortJ Pull up / Pull down Resistors
+************************************************************/
+#define __MSP430_HAS_PORTJ_R__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_PORTJ_R__ 0x0320
+#define PJ_BASE __MSP430_BASEADDRESS_PORTJ_R__
+#define __MSP430_HAS_PJSEL0__ /* Define for DriverLib */
+#define __MSP430_HAS_PJSEL1__ /* Define for DriverLib */
+
+sfr_w(PJIN); /* Port J Input */
+sfr_b(PJIN_L); /* Port J Input */
+sfr_b(PJIN_H); /* Port J Input */
+sfr_w(PJOUT); /* Port J Output */
+sfr_b(PJOUT_L); /* Port J Output */
+sfr_b(PJOUT_H); /* Port J Output */
+sfr_w(PJDIR); /* Port J Direction */
+sfr_b(PJDIR_L); /* Port J Direction */
+sfr_b(PJDIR_H); /* Port J Direction */
+sfr_w(PJREN); /* Port J Resistor Enable */
+sfr_b(PJREN_L); /* Port J Resistor Enable */
+sfr_b(PJREN_H); /* Port J Resistor Enable */
+sfr_w(PJSEL0); /* Port J Selection 0 */
+sfr_b(PJSEL0_L); /* Port J Selection 0 */
+sfr_b(PJSEL0_H); /* Port J Selection 0 */
+sfr_w(PJSEL1); /* Port J Selection 1 */
+sfr_b(PJSEL1_L); /* Port J Selection 1 */
+sfr_b(PJSEL1_H); /* Port J Selection 1 */
+sfr_w(PJSELC); /* Port J Complement Selection */
+sfr_b(PJSELC_L); /* Port J Complement Selection */
+sfr_b(PJSELC_H); /* Port J Complement Selection */
+
+/*************************************************************
+* RAM Control Module for FRAM
+*************************************************************/
+#define __MSP430_HAS_RC_FRAM__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_RC_FRAM__ 0x0158
+#define RAM_BASE __MSP430_BASEADDRESS_RC_FRAM__
+
+sfr_w(RCCTL0); /* Ram Controller Control Register */
+sfr_b(RCCTL0_L); /* Ram Controller Control Register */
+sfr_b(RCCTL0_H); /* Ram Controller Control Register */
+
+/* RCCTL0 Control Bits */
+#define RCRS0OFF0 (0x0001) /* RAM Controller RAM Sector 0 Off Bit: 0 */
+#define RCRS0OFF1 (0x0002) /* RAM Controller RAM Sector 0 Off Bit: 1 */
+#define RCRS1OFF0 (0x0004) /* RAM Controller RAM Sector 1 Off Bit: 0 */
+#define RCRS1OFF1 (0x0008) /* RAM Controller RAM Sector 1 Off Bit: 1 */
+#define RCRS2OFF0 (0x0010) /* RAM Controller RAM Sector 2 Off Bit: 0 */
+#define RCRS2OFF1 (0x0020) /* RAM Controller RAM Sector 2 Off Bit: 1 */
+#define RCRS3OFF0 (0x0040) /* RAM Controller RAM Sector 3 Off Bit: 0 */
+#define RCRS3OFF1 (0x0080) /* RAM Controller RAM Sector 3 Off Bit: 1 */
+
+/* RCCTL0 Control Bits */
+#define RCRS0OFF0_L (0x0001) /* RAM Controller RAM Sector 0 Off Bit: 0 */
+#define RCRS0OFF1_L (0x0002) /* RAM Controller RAM Sector 0 Off Bit: 1 */
+#define RCRS1OFF0_L (0x0004) /* RAM Controller RAM Sector 1 Off Bit: 0 */
+#define RCRS1OFF1_L (0x0008) /* RAM Controller RAM Sector 1 Off Bit: 1 */
+#define RCRS2OFF0_L (0x0010) /* RAM Controller RAM Sector 2 Off Bit: 0 */
+#define RCRS2OFF1_L (0x0020) /* RAM Controller RAM Sector 2 Off Bit: 1 */
+#define RCRS3OFF0_L (0x0040) /* RAM Controller RAM Sector 3 Off Bit: 0 */
+#define RCRS3OFF1_L (0x0080) /* RAM Controller RAM Sector 3 Off Bit: 1 */
+
+#define RCKEY (0x5A00)
+
+#define RCRS0OFF_0 (0x0000) /* RAM Controller RAM Sector 0 Off : 0 */
+#define RCRS0OFF_1 (0x0001) /* RAM Controller RAM Sector 0 Off : 1 */
+#define RCRS0OFF_2 (0x0002) /* RAM Controller RAM Sector 0 Off : 2 */
+#define RCRS0OFF_3 (0x0003) /* RAM Controller RAM Sector 0 Off : 3 */
+#define RCRS1OFF_0 (0x0000) /* RAM Controller RAM Sector 1 Off : 0 */
+#define RCRS1OFF_1 (0x0004) /* RAM Controller RAM Sector 1 Off : 1 */
+#define RCRS1OFF_2 (0x0008) /* RAM Controller RAM Sector 1 Off : 2 */
+#define RCRS1OFF_3 (0x000C) /* RAM Controller RAM Sector 1 Off : 3 */
+#define RCRS2OFF_0 (0x0000) /* RAM Controller RAM Sector 2 Off : 0 */
+#define RCRS2OFF_1 (0x0010) /* RAM Controller RAM Sector 2 Off : 1 */
+#define RCRS2OFF_2 (0x0020) /* RAM Controller RAM Sector 2 Off : 2 */
+#define RCRS2OFF_3 (0x0030) /* RAM Controller RAM Sector 2 Off : 3 */
+#define RCRS3OFF_0 (0x0000) /* RAM Controller RAM Sector 3 Off : 0 */
+#define RCRS3OFF_1 (0x0040) /* RAM Controller RAM Sector 3 Off : 1 */
+#define RCRS3OFF_2 (0x0080) /* RAM Controller RAM Sector 3 Off : 2 */
+#define RCRS3OFF_3 (0x00C0) /* RAM Controller RAM Sector 3 Off : 3 */
+
+/************************************************************
+* Shared Reference
+************************************************************/
+#define __MSP430_HAS_REF_A__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_REF_A__ 0x01B0
+#define REF_A_BASE __MSP430_BASEADDRESS_REF_A__
+
+sfr_w(REFCTL0); /* REF Shared Reference control register 0 */
+sfr_b(REFCTL0_L); /* REF Shared Reference control register 0 */
+sfr_b(REFCTL0_H); /* REF Shared Reference control register 0 */
+
+/* REFCTL0 Control Bits */
+#define REFON (0x0001) /* REF Reference On */
+#define REFOUT (0x0002) /* REF Reference output Buffer On */
+//#define RESERVED (0x0004) /* Reserved */
+#define REFTCOFF (0x0008) /* REF Temp.Sensor off */
+#define REFVSEL0 (0x0010) /* REF Reference Voltage Level Select Bit:0 */
+#define REFVSEL1 (0x0020) /* REF Reference Voltage Level Select Bit:1 */
+#define REFGENOT (0x0040) /* REF Reference generator one-time trigger */
+#define REFBGOT (0x0080) /* REF Bandgap and bandgap buffer one-time trigger */
+#define REFGENACT (0x0100) /* REF Reference generator active */
+#define REFBGACT (0x0200) /* REF Reference bandgap active */
+#define REFGENBUSY (0x0400) /* REF Reference generator busy */
+#define BGMODE (0x0800) /* REF Bandgap mode */
+#define REFGENRDY (0x1000) /* REF Reference generator ready */
+#define REFBGRDY (0x2000) /* REF Reference bandgap ready */
+//#define RESERVED (0x4000) /* Reserved */
+//#define RESERVED (0x8000) /* Reserved */
+
+/* REFCTL0 Control Bits */
+#define REFON_L (0x0001) /* REF Reference On */
+#define REFOUT_L (0x0002) /* REF Reference output Buffer On */
+//#define RESERVED (0x0004) /* Reserved */
+#define REFTCOFF_L (0x0008) /* REF Temp.Sensor off */
+#define REFVSEL0_L (0x0010) /* REF Reference Voltage Level Select Bit:0 */
+#define REFVSEL1_L (0x0020) /* REF Reference Voltage Level Select Bit:1 */
+#define REFGENOT_L (0x0040) /* REF Reference generator one-time trigger */
+#define REFBGOT_L (0x0080) /* REF Bandgap and bandgap buffer one-time trigger */
+//#define RESERVED (0x4000) /* Reserved */
+//#define RESERVED (0x8000) /* Reserved */
+
+/* REFCTL0 Control Bits */
+//#define RESERVED (0x0004) /* Reserved */
+#define REFGENACT_H (0x0001) /* REF Reference generator active */
+#define REFBGACT_H (0x0002) /* REF Reference bandgap active */
+#define REFGENBUSY_H (0x0004) /* REF Reference generator busy */
+#define BGMODE_H (0x0008) /* REF Bandgap mode */
+#define REFGENRDY_H (0x0010) /* REF Reference generator ready */
+#define REFBGRDY_H (0x0020) /* REF Reference bandgap ready */
+//#define RESERVED (0x4000) /* Reserved */
+//#define RESERVED (0x8000) /* Reserved */
+
+#define REFVSEL_0 (0x0000) /* REF Reference Voltage Level Select 1.2V */
+#define REFVSEL_1 (0x0010) /* REF Reference Voltage Level Select 2.0V */
+#define REFVSEL_2 (0x0020) /* REF Reference Voltage Level Select 2.5V */
+#define REFVSEL_3 (0x0030) /* REF Reference Voltage Level Select 2.5V */
+
+/************************************************************
+* Real Time Clock
+************************************************************/
+#define __MSP430_HAS_RTC_C__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_RTC_C__ 0x04A0
+#define RTC_C_BASE __MSP430_BASEADDRESS_RTC_C__
+
+sfr_w(RTCCTL0); /* Real Timer Clock Control 0/Key */
+sfr_b(RTCCTL0_L); /* Real Timer Clock Control 0/Key */
+sfr_b(RTCCTL0_H); /* Real Timer Clock Control 0/Key */
+#define RTCPWD RTCCTL0_H
+sfr_w(RTCCTL13); /* Real Timer Clock Control 1/3 */
+sfr_b(RTCCTL13_L); /* Real Timer Clock Control 1/3 */
+sfr_b(RTCCTL13_H); /* Real Timer Clock Control 1/3 */
+#define RTCCTL1 RTCCTL13_L
+#define RTCCTL3 RTCCTL13_H
+sfr_w(RTCOCAL); /* Real Timer Clock Offset Calibartion */
+sfr_b(RTCOCAL_L); /* Real Timer Clock Offset Calibartion */
+sfr_b(RTCOCAL_H); /* Real Timer Clock Offset Calibartion */
+sfr_w(RTCTCMP); /* Real Timer Temperature Compensation */
+sfr_b(RTCTCMP_L); /* Real Timer Temperature Compensation */
+sfr_b(RTCTCMP_H); /* Real Timer Temperature Compensation */
+sfr_w(RTCPS0CTL); /* Real Timer Prescale Timer 0 Control */
+sfr_b(RTCPS0CTL_L); /* Real Timer Prescale Timer 0 Control */
+sfr_b(RTCPS0CTL_H); /* Real Timer Prescale Timer 0 Control */
+sfr_w(RTCPS1CTL); /* Real Timer Prescale Timer 1 Control */
+sfr_b(RTCPS1CTL_L); /* Real Timer Prescale Timer 1 Control */
+sfr_b(RTCPS1CTL_H); /* Real Timer Prescale Timer 1 Control */
+sfr_w(RTCPS); /* Real Timer Prescale Timer Control */
+sfr_b(RTCPS_L); /* Real Timer Prescale Timer Control */
+sfr_b(RTCPS_H); /* Real Timer Prescale Timer Control */
+sfr_w(RTCIV); /* Real Time Clock Interrupt Vector */
+sfr_w(RTCTIM0); /* Real Time Clock Time 0 */
+sfr_b(RTCTIM0_L); /* Real Time Clock Time 0 */
+sfr_b(RTCTIM0_H); /* Real Time Clock Time 0 */
+sfr_w(RTCTIM1); /* Real Time Clock Time 1 */
+sfr_b(RTCTIM1_L); /* Real Time Clock Time 1 */
+sfr_b(RTCTIM1_H); /* Real Time Clock Time 1 */
+sfr_w(RTCDATE); /* Real Time Clock Date */
+sfr_b(RTCDATE_L); /* Real Time Clock Date */
+sfr_b(RTCDATE_H); /* Real Time Clock Date */
+sfr_w(RTCYEAR); /* Real Time Clock Year */
+sfr_b(RTCYEAR_L); /* Real Time Clock Year */
+sfr_b(RTCYEAR_H); /* Real Time Clock Year */
+sfr_w(RTCAMINHR); /* Real Time Clock Alarm Min/Hour */
+sfr_b(RTCAMINHR_L); /* Real Time Clock Alarm Min/Hour */
+sfr_b(RTCAMINHR_H); /* Real Time Clock Alarm Min/Hour */
+sfr_w(RTCADOWDAY); /* Real Time Clock Alarm day of week/day */
+sfr_b(RTCADOWDAY_L); /* Real Time Clock Alarm day of week/day */
+sfr_b(RTCADOWDAY_H); /* Real Time Clock Alarm day of week/day */
+sfr_w(BIN2BCD); /* Real Time Binary-to-BCD conversion register */
+sfr_w(BCD2BIN); /* Real Time BCD-to-binary conversion register */
+
+#define RTCSEC RTCTIM0_L
+#define RTCMIN RTCTIM0_H
+#define RTCHOUR RTCTIM1_L
+#define RTCDOW RTCTIM1_H
+#define RTCDAY RTCDATE_L
+#define RTCMON RTCDATE_H
+#define RTCYEARL RTCYEAR_L
+#define RT0PS RTCPS_L
+#define RT1PS RTCPS_H
+#define RTCAMIN RTCAMINHR_L /* Real Time Clock Alarm Min */
+#define RTCAHOUR RTCAMINHR_H /* Real Time Clock Alarm Hour */
+#define RTCADOW RTCADOWDAY_L /* Real Time Clock Alarm day of week */
+#define RTCADAY RTCADOWDAY_H /* Real Time Clock Alarm day */
+
+/* RTCCTL0 Control Bits */
+#define RTCOFIE (0x0080) /* RTC 32kHz cyrstal oscillator fault interrupt enable */
+#define RTCTEVIE (0x0040) /* RTC Time Event Interrupt Enable Flag */
+#define RTCAIE (0x0020) /* RTC Alarm Interrupt Enable Flag */
+#define RTCRDYIE (0x0010) /* RTC Ready Interrupt Enable Flag */
+#define RTCOFIFG (0x0008) /* RTC 32kHz cyrstal oscillator fault interrupt flag */
+#define RTCTEVIFG (0x0004) /* RTC Time Event Interrupt Flag */
+#define RTCAIFG (0x0002) /* RTC Alarm Interrupt Flag */
+#define RTCRDYIFG (0x0001) /* RTC Ready Interrupt Flag */
+
+/* RTCCTL0 Control Bits */
+#define RTCOFIE_L (0x0080) /* RTC 32kHz cyrstal oscillator fault interrupt enable */
+#define RTCTEVIE_L (0x0040) /* RTC Time Event Interrupt Enable Flag */
+#define RTCAIE_L (0x0020) /* RTC Alarm Interrupt Enable Flag */
+#define RTCRDYIE_L (0x0010) /* RTC Ready Interrupt Enable Flag */
+#define RTCOFIFG_L (0x0008) /* RTC 32kHz cyrstal oscillator fault interrupt flag */
+#define RTCTEVIFG_L (0x0004) /* RTC Time Event Interrupt Flag */
+#define RTCAIFG_L (0x0002) /* RTC Alarm Interrupt Flag */
+#define RTCRDYIFG_L (0x0001) /* RTC Ready Interrupt Flag */
+
+#define RTCKEY (0xA500) /* RTC Key for RTC write access */
+#define RTCKEY_H (0xA5) /* RTC Key for RTC write access (high word) */
+
+/* RTCCTL13 Control Bits */
+#define RTCCALF1 (0x0200) /* RTC Calibration Frequency Bit 1 */
+#define RTCCALF0 (0x0100) /* RTC Calibration Frequency Bit 0 */
+#define RTCBCD (0x0080) /* RTC BCD 0:Binary / 1:BCD */
+#define RTCHOLD (0x0040) /* RTC Hold */
+#define RTCMODE (0x0020) /* RTC Mode 0:Counter / 1: Calendar */
+#define RTCRDY (0x0010) /* RTC Ready */
+#define RTCSSEL1 (0x0008) /* RTC Source Select 1 */
+#define RTCSSEL0 (0x0004) /* RTC Source Select 0 */
+#define RTCTEV1 (0x0002) /* RTC Time Event 1 */
+#define RTCTEV0 (0x0001) /* RTC Time Event 0 */
+
+/* RTCCTL13 Control Bits */
+#define RTCBCD_L (0x0080) /* RTC BCD 0:Binary / 1:BCD */
+#define RTCHOLD_L (0x0040) /* RTC Hold */
+#define RTCMODE_L (0x0020) /* RTC Mode 0:Counter / 1: Calendar */
+#define RTCRDY_L (0x0010) /* RTC Ready */
+#define RTCSSEL1_L (0x0008) /* RTC Source Select 1 */
+#define RTCSSEL0_L (0x0004) /* RTC Source Select 0 */
+#define RTCTEV1_L (0x0002) /* RTC Time Event 1 */
+#define RTCTEV0_L (0x0001) /* RTC Time Event 0 */
+
+/* RTCCTL13 Control Bits */
+#define RTCCALF1_H (0x0002) /* RTC Calibration Frequency Bit 1 */
+#define RTCCALF0_H (0x0001) /* RTC Calibration Frequency Bit 0 */
+
+#define RTCSSEL_0 (0x0000) /* RTC Source Select ACLK */
+#define RTCSSEL_1 (0x0004) /* RTC Source Select SMCLK */
+#define RTCSSEL_2 (0x0008) /* RTC Source Select RT1PS */
+#define RTCSSEL_3 (0x000C) /* RTC Source Select RT1PS */
+#define RTCSSEL__LFXT (0x0000) /* RTC Source Select LFXT */
+#define RTCSSEL__RT1PS (0x0008) /* RTC Source Select RT1PS */
+
+#define RTCSSEL__ACLK (0x0000) /* Legacy define */
+
+#define RTCTEV_0 (0x0000) /* RTC Time Event: 0 (Min. changed) */
+#define RTCTEV_1 (0x0001) /* RTC Time Event: 1 (Hour changed) */
+#define RTCTEV_2 (0x0002) /* RTC Time Event: 2 (12:00 changed) */
+#define RTCTEV_3 (0x0003) /* RTC Time Event: 3 (00:00 changed) */
+#define RTCTEV__MIN (0x0000) /* RTC Time Event: 0 (Min. changed) */
+#define RTCTEV__HOUR (0x0001) /* RTC Time Event: 1 (Hour changed) */
+#define RTCTEV__0000 (0x0002) /* RTC Time Event: 2 (00:00 changed) */
+#define RTCTEV__1200 (0x0003) /* RTC Time Event: 3 (12:00 changed) */
+
+#define RTCCALF_0 (0x0000) /* RTC Calibration Frequency: No Output */
+#define RTCCALF_1 (0x0100) /* RTC Calibration Frequency: 512 Hz */
+#define RTCCALF_2 (0x0200) /* RTC Calibration Frequency: 256 Hz */
+#define RTCCALF_3 (0x0300) /* RTC Calibration Frequency: 1 Hz */
+
+/* RTCOCAL Control Bits */
+#define RTCOCALS (0x8000) /* RTC Offset Calibration Sign */
+#define RTCOCAL7 (0x0080) /* RTC Offset Calibration Bit 7 */
+#define RTCOCAL6 (0x0040) /* RTC Offset Calibration Bit 6 */
+#define RTCOCAL5 (0x0020) /* RTC Offset Calibration Bit 5 */
+#define RTCOCAL4 (0x0010) /* RTC Offset Calibration Bit 4 */
+#define RTCOCAL3 (0x0008) /* RTC Offset Calibration Bit 3 */
+#define RTCOCAL2 (0x0004) /* RTC Offset Calibration Bit 2 */
+#define RTCOCAL1 (0x0002) /* RTC Offset Calibration Bit 1 */
+#define RTCOCAL0 (0x0001) /* RTC Offset Calibration Bit 0 */
+
+/* RTCOCAL Control Bits */
+#define RTCOCAL7_L (0x0080) /* RTC Offset Calibration Bit 7 */
+#define RTCOCAL6_L (0x0040) /* RTC Offset Calibration Bit 6 */
+#define RTCOCAL5_L (0x0020) /* RTC Offset Calibration Bit 5 */
+#define RTCOCAL4_L (0x0010) /* RTC Offset Calibration Bit 4 */
+#define RTCOCAL3_L (0x0008) /* RTC Offset Calibration Bit 3 */
+#define RTCOCAL2_L (0x0004) /* RTC Offset Calibration Bit 2 */
+#define RTCOCAL1_L (0x0002) /* RTC Offset Calibration Bit 1 */
+#define RTCOCAL0_L (0x0001) /* RTC Offset Calibration Bit 0 */
+
+/* RTCOCAL Control Bits */
+#define RTCOCALS_H (0x0080) /* RTC Offset Calibration Sign */
+
+/* RTCTCMP Control Bits */
+#define RTCTCMPS (0x8000) /* RTC Temperature Compensation Sign */
+#define RTCTCRDY (0x4000) /* RTC Temperature compensation ready */
+#define RTCTCOK (0x2000) /* RTC Temperature compensation write OK */
+#define RTCTCMP7 (0x0080) /* RTC Temperature Compensation Bit 7 */
+#define RTCTCMP6 (0x0040) /* RTC Temperature Compensation Bit 6 */
+#define RTCTCMP5 (0x0020) /* RTC Temperature Compensation Bit 5 */
+#define RTCTCMP4 (0x0010) /* RTC Temperature Compensation Bit 4 */
+#define RTCTCMP3 (0x0008) /* RTC Temperature Compensation Bit 3 */
+#define RTCTCMP2 (0x0004) /* RTC Temperature Compensation Bit 2 */
+#define RTCTCMP1 (0x0002) /* RTC Temperature Compensation Bit 1 */
+#define RTCTCMP0 (0x0001) /* RTC Temperature Compensation Bit 0 */
+
+/* RTCTCMP Control Bits */
+#define RTCTCMP7_L (0x0080) /* RTC Temperature Compensation Bit 7 */
+#define RTCTCMP6_L (0x0040) /* RTC Temperature Compensation Bit 6 */
+#define RTCTCMP5_L (0x0020) /* RTC Temperature Compensation Bit 5 */
+#define RTCTCMP4_L (0x0010) /* RTC Temperature Compensation Bit 4 */
+#define RTCTCMP3_L (0x0008) /* RTC Temperature Compensation Bit 3 */
+#define RTCTCMP2_L (0x0004) /* RTC Temperature Compensation Bit 2 */
+#define RTCTCMP1_L (0x0002) /* RTC Temperature Compensation Bit 1 */
+#define RTCTCMP0_L (0x0001) /* RTC Temperature Compensation Bit 0 */
+
+/* RTCTCMP Control Bits */
+#define RTCTCMPS_H (0x0080) /* RTC Temperature Compensation Sign */
+#define RTCTCRDY_H (0x0040) /* RTC Temperature compensation ready */
+#define RTCTCOK_H (0x0020) /* RTC Temperature compensation write OK */
+
+#define RTCAE (0x80) /* Real Time Clock Alarm enable */
+
+/* RTCPS0CTL Control Bits */
+//#define Reserved (0x8000)
+//#define Reserved (0x4000)
+#define RT0PSDIV2 (0x2000) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */
+#define RT0PSDIV1 (0x1000) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */
+#define RT0PSDIV0 (0x0800) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */
+//#define Reserved (0x0400)
+//#define Reserved (0x0200)
+#define RT0PSHOLD (0x0100) /* RTC Prescale Timer 0 Hold */
+//#define Reserved (0x0080)
+//#define Reserved (0x0040)
+//#define Reserved (0x0020)
+#define RT0IP2 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
+#define RT0IP1 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
+#define RT0IP0 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
+#define RT0PSIE (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */
+#define RT0PSIFG (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */
+
+/* RTCPS0CTL Control Bits */
+//#define Reserved (0x8000)
+//#define Reserved (0x4000)
+//#define Reserved (0x0400)
+//#define Reserved (0x0200)
+//#define Reserved (0x0080)
+//#define Reserved (0x0040)
+//#define Reserved (0x0020)
+#define RT0IP2_L (0x0010) /* RTC Prescale Timer 0 Interrupt Interval Bit: 2 */
+#define RT0IP1_L (0x0008) /* RTC Prescale Timer 0 Interrupt Interval Bit: 1 */
+#define RT0IP0_L (0x0004) /* RTC Prescale Timer 0 Interrupt Interval Bit: 0 */
+#define RT0PSIE_L (0x0002) /* RTC Prescale Timer 0 Interrupt Enable Flag */
+#define RT0PSIFG_L (0x0001) /* RTC Prescale Timer 0 Interrupt Flag */
+
+/* RTCPS0CTL Control Bits */
+//#define Reserved (0x8000)
+//#define Reserved (0x4000)
+#define RT0PSDIV2_H (0x0020) /* RTC Prescale Timer 0 Clock Divide Bit: 2 */
+#define RT0PSDIV1_H (0x0010) /* RTC Prescale Timer 0 Clock Divide Bit: 1 */
+#define RT0PSDIV0_H (0x0008) /* RTC Prescale Timer 0 Clock Divide Bit: 0 */
+//#define Reserved (0x0400)
+//#define Reserved (0x0200)
+#define RT0PSHOLD_H (0x0001) /* RTC Prescale Timer 0 Hold */
+//#define Reserved (0x0080)
+//#define Reserved (0x0040)
+//#define Reserved (0x0020)
+
+#define RT0IP_0 (0x0000) /* RTC Prescale Timer 0 Interrupt Interval /2 */
+#define RT0IP_1 (0x0004) /* RTC Prescale Timer 0 Interrupt Interval /4 */
+#define RT0IP_2 (0x0008) /* RTC Prescale Timer 0 Interrupt Interval /8 */
+#define RT0IP_3 (0x000C) /* RTC Prescale Timer 0 Interrupt Interval /16 */
+#define RT0IP_4 (0x0010) /* RTC Prescale Timer 0 Interrupt Interval /32 */
+#define RT0IP_5 (0x0014) /* RTC Prescale Timer 0 Interrupt Interval /64 */
+#define RT0IP_6 (0x0018) /* RTC Prescale Timer 0 Interrupt Interval /128 */
+#define RT0IP_7 (0x001C) /* RTC Prescale Timer 0 Interrupt Interval /256 */
+
+#define RT0PSDIV_0 (0x0000) /* RTC Prescale Timer 0 Clock Divide: /2 */
+#define RT0PSDIV_1 (0x0800) /* RTC Prescale Timer 0 Clock Divide: /4 */
+#define RT0PSDIV_2 (0x1000) /* RTC Prescale Timer 0 Clock Divide: /8 */
+#define RT0PSDIV_3 (0x1800) /* RTC Prescale Timer 0 Clock Divide: /16 */
+#define RT0PSDIV_4 (0x2000) /* RTC Prescale Timer 0 Clock Divide: /32 */
+#define RT0PSDIV_5 (0x2800) /* RTC Prescale Timer 0 Clock Divide: /64 */
+#define RT0PSDIV_6 (0x3000) /* RTC Prescale Timer 0 Clock Divide: /128 */
+#define RT0PSDIV_7 (0x3800) /* RTC Prescale Timer 0 Clock Divide: /256 */
+
+/* RTCPS1CTL Control Bits */
+#define RT1SSEL1 (0x8000) /* RTC Prescale Timer 1 Source Select Bit: 1 */
+#define RT1SSEL0 (0x4000) /* RTC Prescale Timer 1 Source Select Bit: 0 */
+#define RT1PSDIV2 (0x2000) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */
+#define RT1PSDIV1 (0x1000) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */
+#define RT1PSDIV0 (0x0800) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */
+//#define Reserved (0x0400)
+//#define Reserved (0x0200)
+#define RT1PSHOLD (0x0100) /* RTC Prescale Timer 1 Hold */
+//#define Reserved (0x0080)
+//#define Reserved (0x0040)
+//#define Reserved (0x0020)
+#define RT1IP2 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
+#define RT1IP1 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
+#define RT1IP0 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
+#define RT1PSIE (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */
+#define RT1PSIFG (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */
+
+/* RTCPS1CTL Control Bits */
+//#define Reserved (0x0400)
+//#define Reserved (0x0200)
+//#define Reserved (0x0080)
+//#define Reserved (0x0040)
+//#define Reserved (0x0020)
+#define RT1IP2_L (0x0010) /* RTC Prescale Timer 1 Interrupt Interval Bit: 2 */
+#define RT1IP1_L (0x0008) /* RTC Prescale Timer 1 Interrupt Interval Bit: 1 */
+#define RT1IP0_L (0x0004) /* RTC Prescale Timer 1 Interrupt Interval Bit: 0 */
+#define RT1PSIE_L (0x0002) /* RTC Prescale Timer 1 Interrupt Enable Flag */
+#define RT1PSIFG_L (0x0001) /* RTC Prescale Timer 1 Interrupt Flag */
+
+/* RTCPS1CTL Control Bits */
+#define RT1SSEL1_H (0x0080) /* RTC Prescale Timer 1 Source Select Bit: 1 */
+#define RT1SSEL0_H (0x0040) /* RTC Prescale Timer 1 Source Select Bit: 0 */
+#define RT1PSDIV2_H (0x0020) /* RTC Prescale Timer 1 Clock Divide Bit: 2 */
+#define RT1PSDIV1_H (0x0010) /* RTC Prescale Timer 1 Clock Divide Bit: 1 */
+#define RT1PSDIV0_H (0x0008) /* RTC Prescale Timer 1 Clock Divide Bit: 0 */
+//#define Reserved (0x0400)
+//#define Reserved (0x0200)
+#define RT1PSHOLD_H (0x0001) /* RTC Prescale Timer 1 Hold */
+//#define Reserved (0x0080)
+//#define Reserved (0x0040)
+//#define Reserved (0x0020)
+
+#define RT1IP_0 (0x0000) /* RTC Prescale Timer 1 Interrupt Interval /2 */
+#define RT1IP_1 (0x0004) /* RTC Prescale Timer 1 Interrupt Interval /4 */
+#define RT1IP_2 (0x0008) /* RTC Prescale Timer 1 Interrupt Interval /8 */
+#define RT1IP_3 (0x000C) /* RTC Prescale Timer 1 Interrupt Interval /16 */
+#define RT1IP_4 (0x0010) /* RTC Prescale Timer 1 Interrupt Interval /32 */
+#define RT1IP_5 (0x0014) /* RTC Prescale Timer 1 Interrupt Interval /64 */
+#define RT1IP_6 (0x0018) /* RTC Prescale Timer 1 Interrupt Interval /128 */
+#define RT1IP_7 (0x001C) /* RTC Prescale Timer 1 Interrupt Interval /256 */
+
+#define RT1PSDIV_0 (0x0000) /* RTC Prescale Timer 1 Clock Divide: /2 */
+#define RT1PSDIV_1 (0x0800) /* RTC Prescale Timer 1 Clock Divide: /4 */
+#define RT1PSDIV_2 (0x1000) /* RTC Prescale Timer 1 Clock Divide: /8 */
+#define RT1PSDIV_3 (0x1800) /* RTC Prescale Timer 1 Clock Divide: /16 */
+#define RT1PSDIV_4 (0x2000) /* RTC Prescale Timer 1 Clock Divide: /32 */
+#define RT1PSDIV_5 (0x2800) /* RTC Prescale Timer 1 Clock Divide: /64 */
+#define RT1PSDIV_6 (0x3000) /* RTC Prescale Timer 1 Clock Divide: /128 */
+#define RT1PSDIV_7 (0x3800) /* RTC Prescale Timer 1 Clock Divide: /256 */
+
+#define RT1SSEL_0 (0x0000) /* RTC Prescale Timer 1 Source Select: 0 */
+#define RT1SSEL_1 (0x4000) /* RTC Prescale Timer 1 Source Select: 1 */
+#define RT1SSEL_2 (0x8000) /* RTC Prescale Timer 1 Source Select: 2 */
+#define RT1SSEL_3 (0xC000) /* RTC Prescale Timer 1 Source Select: 3 */
+
+/* RTC Definitions */
+#define RTCIV_NONE (0x0000) /* No Interrupt pending */
+#define RTCIV_RTCOFIFG (0x0002) /* RTC Osc fault: RTCOFIFG */
+#define RTCIV_RTCRDYIFG (0x0004) /* RTC ready: RTCRDYIFG */
+#define RTCIV_RTCTEVIFG (0x0006) /* RTC interval timer: RTCTEVIFG */
+#define RTCIV_RTCAIFG (0x0008) /* RTC user alarm: RTCAIFG */
+#define RTCIV_RT0PSIFG (0x000A) /* RTC prescaler 0: RT0PSIFG */
+#define RTCIV_RT1PSIFG (0x000C) /* RTC prescaler 1: RT1PSIFG */
+
+/* Legacy Definitions */
+#define RTC_NONE (0x0000) /* No Interrupt pending */
+#define RTC_RTCOFIFG (0x0002) /* RTC Osc fault: RTCOFIFG */
+#define RTC_RTCRDYIFG (0x0004) /* RTC ready: RTCRDYIFG */
+#define RTC_RTCTEVIFG (0x0006) /* RTC interval timer: RTCTEVIFG */
+#define RTC_RTCAIFG (0x0008) /* RTC user alarm: RTCAIFG */
+#define RTC_RT0PSIFG (0x000A) /* RTC prescaler 0: RT0PSIFG */
+#define RTC_RT1PSIFG (0x000C) /* RTC prescaler 1: RT1PSIFG */
+
+/************************************************************
+* SFR - Special Function Register Module
+************************************************************/
+#define __MSP430_HAS_SFR__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_SFR__ 0x0100
+#define SFR_BASE __MSP430_BASEADDRESS_SFR__
+
+sfr_w(SFRIE1); /* Interrupt Enable 1 */
+sfr_b(SFRIE1_L); /* Interrupt Enable 1 */
+sfr_b(SFRIE1_H); /* Interrupt Enable 1 */
+
+/* SFRIE1 Control Bits */
+#define WDTIE (0x0001) /* WDT Interrupt Enable */
+#define OFIE (0x0002) /* Osc Fault Enable */
+//#define Reserved (0x0004)
+#define VMAIE (0x0008) /* Vacant Memory Interrupt Enable */
+#define NMIIE (0x0010) /* NMI Interrupt Enable */
+#define JMBINIE (0x0040) /* JTAG Mail Box input Interrupt Enable */
+#define JMBOUTIE (0x0080) /* JTAG Mail Box output Interrupt Enable */
+
+#define WDTIE_L (0x0001) /* WDT Interrupt Enable */
+#define OFIE_L (0x0002) /* Osc Fault Enable */
+//#define Reserved (0x0004)
+#define VMAIE_L (0x0008) /* Vacant Memory Interrupt Enable */
+#define NMIIE_L (0x0010) /* NMI Interrupt Enable */
+#define JMBINIE_L (0x0040) /* JTAG Mail Box input Interrupt Enable */
+#define JMBOUTIE_L (0x0080) /* JTAG Mail Box output Interrupt Enable */
+
+sfr_w(SFRIFG1); /* Interrupt Flag 1 */
+sfr_b(SFRIFG1_L); /* Interrupt Flag 1 */
+sfr_b(SFRIFG1_H); /* Interrupt Flag 1 */
+/* SFRIFG1 Control Bits */
+#define WDTIFG (0x0001) /* WDT Interrupt Flag */
+#define OFIFG (0x0002) /* Osc Fault Flag */
+//#define Reserved (0x0004)
+#define VMAIFG (0x0008) /* Vacant Memory Interrupt Flag */
+#define NMIIFG (0x0010) /* NMI Interrupt Flag */
+//#define Reserved (0x0020)
+#define JMBINIFG (0x0040) /* JTAG Mail Box input Interrupt Flag */
+#define JMBOUTIFG (0x0080) /* JTAG Mail Box output Interrupt Flag */
+
+#define WDTIFG_L (0x0001) /* WDT Interrupt Flag */
+#define OFIFG_L (0x0002) /* Osc Fault Flag */
+//#define Reserved (0x0004)
+#define VMAIFG_L (0x0008) /* Vacant Memory Interrupt Flag */
+#define NMIIFG_L (0x0010) /* NMI Interrupt Flag */
+//#define Reserved (0x0020)
+#define JMBINIFG_L (0x0040) /* JTAG Mail Box input Interrupt Flag */
+#define JMBOUTIFG_L (0x0080) /* JTAG Mail Box output Interrupt Flag */
+
+sfr_w(SFRRPCR); /* RESET Pin Control Register */
+sfr_b(SFRRPCR_L); /* RESET Pin Control Register */
+sfr_b(SFRRPCR_H); /* RESET Pin Control Register */
+/* SFRRPCR Control Bits */
+#define SYSNMI (0x0001) /* NMI select */
+#define SYSNMIIES (0x0002) /* NMI edge select */
+#define SYSRSTUP (0x0004) /* RESET Pin pull down/up select */
+#define SYSRSTRE (0x0008) /* RESET Pin Resistor enable */
+
+#define SYSNMI_L (0x0001) /* NMI select */
+#define SYSNMIIES_L (0x0002) /* NMI edge select */
+#define SYSRSTUP_L (0x0004) /* RESET Pin pull down/up select */
+#define SYSRSTRE_L (0x0008) /* RESET Pin Resistor enable */
+
+/************************************************************
+* SYS - System Module
+************************************************************/
+#define __MSP430_HAS_SYS__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_SYS__ 0x0180
+#define SYS_BASE __MSP430_BASEADDRESS_SYS__
+
+sfr_w(SYSCTL); /* System control */
+sfr_b(SYSCTL_L); /* System control */
+sfr_b(SYSCTL_H); /* System control */
+sfr_w(SYSJMBC); /* JTAG mailbox control */
+sfr_b(SYSJMBC_L); /* JTAG mailbox control */
+sfr_b(SYSJMBC_H); /* JTAG mailbox control */
+sfr_w(SYSJMBI0); /* JTAG mailbox input 0 */
+sfr_b(SYSJMBI0_L); /* JTAG mailbox input 0 */
+sfr_b(SYSJMBI0_H); /* JTAG mailbox input 0 */
+sfr_w(SYSJMBI1); /* JTAG mailbox input 1 */
+sfr_b(SYSJMBI1_L); /* JTAG mailbox input 1 */
+sfr_b(SYSJMBI1_H); /* JTAG mailbox input 1 */
+sfr_w(SYSJMBO0); /* JTAG mailbox output 0 */
+sfr_b(SYSJMBO0_L); /* JTAG mailbox output 0 */
+sfr_b(SYSJMBO0_H); /* JTAG mailbox output 0 */
+sfr_w(SYSJMBO1); /* JTAG mailbox output 1 */
+sfr_b(SYSJMBO1_L); /* JTAG mailbox output 1 */
+sfr_b(SYSJMBO1_H); /* JTAG mailbox output 1 */
+
+sfr_w(SYSUNIV); /* User NMI vector generator */
+sfr_b(SYSUNIV_L); /* User NMI vector generator */
+sfr_b(SYSUNIV_H); /* User NMI vector generator */
+sfr_w(SYSSNIV); /* System NMI vector generator */
+sfr_b(SYSSNIV_L); /* System NMI vector generator */
+sfr_b(SYSSNIV_H); /* System NMI vector generator */
+sfr_w(SYSRSTIV); /* Reset vector generator */
+sfr_b(SYSRSTIV_L); /* Reset vector generator */
+sfr_b(SYSRSTIV_H); /* Reset vector generator */
+
+/* SYSCTL Control Bits */
+#define SYSRIVECT (0x0001) /* SYS - RAM based interrupt vectors */
+//#define RESERVED (0x0002) /* SYS - Reserved */
+#define SYSPMMPE (0x0004) /* SYS - PMM access protect */
+//#define RESERVED (0x0008) /* SYS - Reserved */
+#define SYSBSLIND (0x0010) /* SYS - TCK/RST indication detected */
+#define SYSJTAGPIN (0x0020) /* SYS - Dedicated JTAG pins enabled */
+//#define RESERVED (0x0040) /* SYS - Reserved */
+//#define RESERVED (0x0080) /* SYS - Reserved */
+//#define RESERVED (0x0100) /* SYS - Reserved */
+//#define RESERVED (0x0200) /* SYS - Reserved */
+//#define RESERVED (0x0400) /* SYS - Reserved */
+//#define RESERVED (0x0800) /* SYS - Reserved */
+//#define RESERVED (0x1000) /* SYS - Reserved */
+//#define RESERVED (0x2000) /* SYS - Reserved */
+//#define RESERVED (0x4000) /* SYS - Reserved */
+//#define RESERVED (0x8000) /* SYS - Reserved */
+
+/* SYSCTL Control Bits */
+#define SYSRIVECT_L (0x0001) /* SYS - RAM based interrupt vectors */
+//#define RESERVED (0x0002) /* SYS - Reserved */
+#define SYSPMMPE_L (0x0004) /* SYS - PMM access protect */
+//#define RESERVED (0x0008) /* SYS - Reserved */
+#define SYSBSLIND_L (0x0010) /* SYS - TCK/RST indication detected */
+#define SYSJTAGPIN_L (0x0020) /* SYS - Dedicated JTAG pins enabled */
+//#define RESERVED (0x0040) /* SYS - Reserved */
+//#define RESERVED (0x0080) /* SYS - Reserved */
+//#define RESERVED (0x0100) /* SYS - Reserved */
+//#define RESERVED (0x0200) /* SYS - Reserved */
+//#define RESERVED (0x0400) /* SYS - Reserved */
+//#define RESERVED (0x0800) /* SYS - Reserved */
+//#define RESERVED (0x1000) /* SYS - Reserved */
+//#define RESERVED (0x2000) /* SYS - Reserved */
+//#define RESERVED (0x4000) /* SYS - Reserved */
+//#define RESERVED (0x8000) /* SYS - Reserved */
+
+/* SYSJMBC Control Bits */
+#define JMBIN0FG (0x0001) /* SYS - Incoming JTAG Mailbox 0 Flag */
+#define JMBIN1FG (0x0002) /* SYS - Incoming JTAG Mailbox 1 Flag */
+#define JMBOUT0FG (0x0004) /* SYS - Outgoing JTAG Mailbox 0 Flag */
+#define JMBOUT1FG (0x0008) /* SYS - Outgoing JTAG Mailbox 1 Flag */
+#define JMBMODE (0x0010) /* SYS - JMB 16/32 Bit Mode */
+//#define RESERVED (0x0020) /* SYS - Reserved */
+#define JMBCLR0OFF (0x0040) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */
+#define JMBCLR1OFF (0x0080) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */
+//#define RESERVED (0x0100) /* SYS - Reserved */
+//#define RESERVED (0x0200) /* SYS - Reserved */
+//#define RESERVED (0x0400) /* SYS - Reserved */
+//#define RESERVED (0x0800) /* SYS - Reserved */
+//#define RESERVED (0x1000) /* SYS - Reserved */
+//#define RESERVED (0x2000) /* SYS - Reserved */
+//#define RESERVED (0x4000) /* SYS - Reserved */
+//#define RESERVED (0x8000) /* SYS - Reserved */
+
+/* SYSJMBC Control Bits */
+#define JMBIN0FG_L (0x0001) /* SYS - Incoming JTAG Mailbox 0 Flag */
+#define JMBIN1FG_L (0x0002) /* SYS - Incoming JTAG Mailbox 1 Flag */
+#define JMBOUT0FG_L (0x0004) /* SYS - Outgoing JTAG Mailbox 0 Flag */
+#define JMBOUT1FG_L (0x0008) /* SYS - Outgoing JTAG Mailbox 1 Flag */
+#define JMBMODE_L (0x0010) /* SYS - JMB 16/32 Bit Mode */
+//#define RESERVED (0x0020) /* SYS - Reserved */
+#define JMBCLR0OFF_L (0x0040) /* SYS - Incoming JTAG Mailbox 0 Flag auto-clear disalbe */
+#define JMBCLR1OFF_L (0x0080) /* SYS - Incoming JTAG Mailbox 1 Flag auto-clear disalbe */
+//#define RESERVED (0x0100) /* SYS - Reserved */
+//#define RESERVED (0x0200) /* SYS - Reserved */
+//#define RESERVED (0x0400) /* SYS - Reserved */
+//#define RESERVED (0x0800) /* SYS - Reserved */
+//#define RESERVED (0x1000) /* SYS - Reserved */
+//#define RESERVED (0x2000) /* SYS - Reserved */
+//#define RESERVED (0x4000) /* SYS - Reserved */
+//#define RESERVED (0x8000) /* SYS - Reserved */
+
+
+/* SYSUNIV Definitions */
+#define SYSUNIV_NONE (0x0000) /* No Interrupt pending */
+#define SYSUNIV_NMIIFG (0x0002) /* SYSUNIV : NMIIFG */
+#define SYSUNIV_OFIFG (0x0004) /* SYSUNIV : Osc. Fail - OFIFG */
+
+/* SYSSNIV Definitions */
+#define SYSSNIV_NONE (0x0000) /* No Interrupt pending */
+#define SYSSNIV_RES02 (0x0002) /* SYSSNIV : Reserved */
+#define SYSSNIV_UBDIFG (0x0004) /* SYSSNIV : FRAM Uncorrectable bit Error */
+#define SYSSNIV_RES06 (0x0006) /* SYSSNIV : Reserved */
+#define SYSSNIV_MPUSEGPIFG (0x0008) /* SYSSNIV : MPUSEGPIFG violation */
+#define SYSSNIV_MPUSEGIIFG (0x000A) /* SYSSNIV : MPUSEGIIFG violation */
+#define SYSSNIV_MPUSEG1IFG (0x000C) /* SYSSNIV : MPUSEG1IFG violation */
+#define SYSSNIV_MPUSEG2IFG (0x000E) /* SYSSNIV : MPUSEG2IFG violation */
+#define SYSSNIV_MPUSEG3IFG (0x0010) /* SYSSNIV : MPUSEG3IFG violation */
+#define SYSSNIV_VMAIFG (0x0012) /* SYSSNIV : VMAIFG */
+#define SYSSNIV_JMBINIFG (0x0014) /* SYSSNIV : JMBINIFG */
+#define SYSSNIV_JMBOUTIFG (0x0016) /* SYSSNIV : JMBOUTIFG */
+#define SYSSNIV_CBDIFG (0x0018) /* SYSSNIV : FRAM Correctable Bit error */
+
+/* SYSRSTIV Definitions */
+#define SYSRSTIV_NONE (0x0000) /* No Interrupt pending */
+#define SYSRSTIV_BOR (0x0002) /* SYSRSTIV : BOR */
+#define SYSRSTIV_RSTNMI (0x0004) /* SYSRSTIV : RST/NMI */
+#define SYSRSTIV_DOBOR (0x0006) /* SYSRSTIV : Do BOR */
+#define SYSRSTIV_LPM5WU (0x0008) /* SYSRSTIV : Port LPM5 Wake Up */
+#define SYSRSTIV_SECYV (0x000A) /* SYSRSTIV : Security violation */
+#define SYSRSTIV_RES0C (0x000C) /* SYSRSTIV : Reserved */
+#define SYSRSTIV_SVSHIFG (0x000E) /* SYSRSTIV : SVSHIFG */
+#define SYSRSTIV_RES10 (0x0010) /* SYSRSTIV : Reserved */
+#define SYSRSTIV_RES12 (0x0012) /* SYSRSTIV : Reserved */
+#define SYSRSTIV_DOPOR (0x0014) /* SYSRSTIV : Do POR */
+#define SYSRSTIV_WDTTO (0x0016) /* SYSRSTIV : WDT Time out */
+#define SYSRSTIV_WDTKEY (0x0018) /* SYSRSTIV : WDTKEY violation */
+#define SYSRSTIV_FRCTLPW (0x001A) /* SYSRSTIV : FRAM Key violation */
+#define SYSRSTIV_UBDIFG (0x001C) /* SYSRSTIV : FRAM Uncorrectable bit Error */
+#define SYSRSTIV_PERF (0x001E) /* SYSRSTIV : peripheral/config area fetch */
+#define SYSRSTIV_PMMPW (0x0020) /* SYSRSTIV : PMM Password violation */
+#define SYSRSTIV_MPUPW (0x0022) /* SYSRSTIV : MPU Password violation */
+#define SYSRSTIV_CSPW (0x0024) /* SYSRSTIV : CS Password violation */
+#define SYSRSTIV_MPUSEGPIFG (0x0026) /* SYSRSTIV : MPUSEGPIFG violation */
+#define SYSRSTIV_MPUSEGIIFG (0x0028) /* SYSRSTIV : MPUSEGIIFG violation */
+#define SYSRSTIV_MPUSEG1IFG (0x002A) /* SYSRSTIV : MPUSEG1IFG violation */
+#define SYSRSTIV_MPUSEG2IFG (0x002C) /* SYSRSTIV : MPUSEG2IFG violation */
+#define SYSRSTIV_MPUSEG3IFG (0x002E) /* SYSRSTIV : MPUSEG3IFG violation */
+#define SYSRSTIV_ACCTEIFG (0x0030) /* SYSRSTIV : ACCTEIFG access time error */
+
+/************************************************************
+* Timer0_A3
+************************************************************/
+#define __MSP430_HAS_T0A3__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_T0A3__ 0x0340
+#define TIMER_A0_BASE __MSP430_BASEADDRESS_T0A3__
+
+sfr_w(TA0CTL); /* Timer0_A3 Control */
+sfr_w(TA0CCTL0); /* Timer0_A3 Capture/Compare Control 0 */
+sfr_w(TA0CCTL1); /* Timer0_A3 Capture/Compare Control 1 */
+sfr_w(TA0CCTL2); /* Timer0_A3 Capture/Compare Control 2 */
+sfr_w(TA0R); /* Timer0_A3 */
+sfr_w(TA0CCR0); /* Timer0_A3 Capture/Compare 0 */
+sfr_w(TA0CCR1); /* Timer0_A3 Capture/Compare 1 */
+sfr_w(TA0CCR2); /* Timer0_A3 Capture/Compare 2 */
+sfr_w(TA0IV); /* Timer0_A3 Interrupt Vector Word */
+sfr_w(TA0EX0); /* Timer0_A3 Expansion Register 0 */
+
+/* TAxCTL Control Bits */
+#define TASSEL1 (0x0200) /* Timer A clock source select 1 */
+#define TASSEL0 (0x0100) /* Timer A clock source select 0 */
+#define ID1 (0x0080) /* Timer A clock input divider 1 */
+#define ID0 (0x0040) /* Timer A clock input divider 0 */
+#define MC1 (0x0020) /* Timer A mode control 1 */
+#define MC0 (0x0010) /* Timer A mode control 0 */
+#define TACLR (0x0004) /* Timer A counter clear */
+#define TAIE (0x0002) /* Timer A counter interrupt enable */
+#define TAIFG (0x0001) /* Timer A counter interrupt flag */
+
+#define MC_0 (0x0000) /* Timer A mode control: 0 - Stop */
+#define MC_1 (0x0010) /* Timer A mode control: 1 - Up to CCR0 */
+#define MC_2 (0x0020) /* Timer A mode control: 2 - Continuous up */
+#define MC_3 (0x0030) /* Timer A mode control: 3 - Up/Down */
+#define ID_0 (0x0000) /* Timer A input divider: 0 - /1 */
+#define ID_1 (0x0040) /* Timer A input divider: 1 - /2 */
+#define ID_2 (0x0080) /* Timer A input divider: 2 - /4 */
+#define ID_3 (0x00C0) /* Timer A input divider: 3 - /8 */
+#define TASSEL_0 (0x0000) /* Timer A clock source select: 0 - TACLK */
+#define TASSEL_1 (0x0100) /* Timer A clock source select: 1 - ACLK */
+#define TASSEL_2 (0x0200) /* Timer A clock source select: 2 - SMCLK */
+#define TASSEL_3 (0x0300) /* Timer A clock source select: 3 - INCLK */
+#define MC__STOP (0x0000) /* Timer A mode control: 0 - Stop */
+#define MC__UP (0x0010) /* Timer A mode control: 1 - Up to CCR0 */
+#define MC__CONTINUOUS (0x0020) /* Timer A mode control: 2 - Continuous up */
+#define MC__CONTINOUS (0x0020) /* Legacy define */
+#define MC__UPDOWN (0x0030) /* Timer A mode control: 3 - Up/Down */
+#define ID__1 (0x0000) /* Timer A input divider: 0 - /1 */
+#define ID__2 (0x0040) /* Timer A input divider: 1 - /2 */
+#define ID__4 (0x0080) /* Timer A input divider: 2 - /4 */
+#define ID__8 (0x00C0) /* Timer A input divider: 3 - /8 */
+#define TASSEL__TACLK (0x0000) /* Timer A clock source select: 0 - TACLK */
+#define TASSEL__ACLK (0x0100) /* Timer A clock source select: 1 - ACLK */
+#define TASSEL__SMCLK (0x0200) /* Timer A clock source select: 2 - SMCLK */
+#define TASSEL__INCLK (0x0300) /* Timer A clock source select: 3 - INCLK */
+
+/* TAxCCTLx Control Bits */
+#define CM1 (0x8000) /* Capture mode 1 */
+#define CM0 (0x4000) /* Capture mode 0 */
+#define CCIS1 (0x2000) /* Capture input select 1 */
+#define CCIS0 (0x1000) /* Capture input select 0 */
+#define SCS (0x0800) /* Capture sychronize */
+#define SCCI (0x0400) /* Latched capture signal (read) */
+#define CAP (0x0100) /* Capture mode: 1 /Compare mode : 0 */
+#define OUTMOD2 (0x0080) /* Output mode 2 */
+#define OUTMOD1 (0x0040) /* Output mode 1 */
+#define OUTMOD0 (0x0020) /* Output mode 0 */
+#define CCIE (0x0010) /* Capture/compare interrupt enable */
+#define CCI (0x0008) /* Capture input signal (read) */
+#define OUT (0x0004) /* PWM Output signal if output mode 0 */
+#define COV (0x0002) /* Capture/compare overflow flag */
+#define CCIFG (0x0001) /* Capture/compare interrupt flag */
+
+#define OUTMOD_0 (0x0000) /* PWM output mode: 0 - output only */
+#define OUTMOD_1 (0x0020) /* PWM output mode: 1 - set */
+#define OUTMOD_2 (0x0040) /* PWM output mode: 2 - PWM toggle/reset */
+#define OUTMOD_3 (0x0060) /* PWM output mode: 3 - PWM set/reset */
+#define OUTMOD_4 (0x0080) /* PWM output mode: 4 - toggle */
+#define OUTMOD_5 (0x00A0) /* PWM output mode: 5 - Reset */
+#define OUTMOD_6 (0x00C0) /* PWM output mode: 6 - PWM toggle/set */
+#define OUTMOD_7 (0x00E0) /* PWM output mode: 7 - PWM reset/set */
+#define CCIS_0 (0x0000) /* Capture input select: 0 - CCIxA */
+#define CCIS_1 (0x1000) /* Capture input select: 1 - CCIxB */
+#define CCIS_2 (0x2000) /* Capture input select: 2 - GND */
+#define CCIS_3 (0x3000) /* Capture input select: 3 - Vcc */
+#define CM_0 (0x0000) /* Capture mode: 0 - disabled */
+#define CM_1 (0x4000) /* Capture mode: 1 - pos. edge */
+#define CM_2 (0x8000) /* Capture mode: 1 - neg. edge */
+#define CM_3 (0xC000) /* Capture mode: 1 - both edges */
+
+/* TAxEX0 Control Bits */
+#define TAIDEX0 (0x0001) /* Timer A Input divider expansion Bit: 0 */
+#define TAIDEX1 (0x0002) /* Timer A Input divider expansion Bit: 1 */
+#define TAIDEX2 (0x0004) /* Timer A Input divider expansion Bit: 2 */
+
+#define TAIDEX_0 (0x0000) /* Timer A Input divider expansion : /1 */
+#define TAIDEX_1 (0x0001) /* Timer A Input divider expansion : /2 */
+#define TAIDEX_2 (0x0002) /* Timer A Input divider expansion : /3 */
+#define TAIDEX_3 (0x0003) /* Timer A Input divider expansion : /4 */
+#define TAIDEX_4 (0x0004) /* Timer A Input divider expansion : /5 */
+#define TAIDEX_5 (0x0005) /* Timer A Input divider expansion : /6 */
+#define TAIDEX_6 (0x0006) /* Timer A Input divider expansion : /7 */
+#define TAIDEX_7 (0x0007) /* Timer A Input divider expansion : /8 */
+
+/* T0A3IV Definitions */
+#define TA0IV_NONE (0x0000) /* No Interrupt pending */
+#define TA0IV_TACCR1 (0x0002) /* TA0CCR1_CCIFG */
+#define TA0IV_TACCR2 (0x0004) /* TA0CCR2_CCIFG */
+#define TA0IV_3 (0x0006) /* Reserved */
+#define TA0IV_4 (0x0008) /* Reserved */
+#define TA0IV_5 (0x000A) /* Reserved */
+#define TA0IV_6 (0x000C) /* Reserved */
+#define TA0IV_TAIFG (0x000E) /* TA0IFG */
+
+/* Legacy Defines */
+#define TA0IV_TA0CCR1 (0x0002) /* TA0CCR1_CCIFG */
+#define TA0IV_TA0CCR2 (0x0004) /* TA0CCR2_CCIFG */
+#define TA0IV_TA0IFG (0x000E) /* TA0IFG */
+
+/************************************************************
+* Timer1_A3
+************************************************************/
+#define __MSP430_HAS_T1A3__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_T1A3__ 0x0380
+#define TIMER_A1_BASE __MSP430_BASEADDRESS_T1A3__
+
+sfr_w(TA1CTL); /* Timer1_A3 Control */
+sfr_w(TA1CCTL0); /* Timer1_A3 Capture/Compare Control 0 */
+sfr_w(TA1CCTL1); /* Timer1_A3 Capture/Compare Control 1 */
+sfr_w(TA1CCTL2); /* Timer1_A3 Capture/Compare Control 2 */
+sfr_w(TA1R); /* Timer1_A3 */
+sfr_w(TA1CCR0); /* Timer1_A3 Capture/Compare 0 */
+sfr_w(TA1CCR1); /* Timer1_A3 Capture/Compare 1 */
+sfr_w(TA1CCR2); /* Timer1_A3 Capture/Compare 2 */
+sfr_w(TA1IV); /* Timer1_A3 Interrupt Vector Word */
+sfr_w(TA1EX0); /* Timer1_A3 Expansion Register 0 */
+
+/* Bits are already defined within the Timer0_Ax */
+
+/* TA1IV Definitions */
+#define TA1IV_NONE (0x0000) /* No Interrupt pending */
+#define TA1IV_TACCR1 (0x0002) /* TA1CCR1_CCIFG */
+#define TA1IV_TACCR2 (0x0004) /* TA1CCR2_CCIFG */
+#define TA1IV_3 (0x0006) /* Reserved */
+#define TA1IV_4 (0x0008) /* Reserved */
+#define TA1IV_5 (0x000A) /* Reserved */
+#define TA1IV_6 (0x000C) /* Reserved */
+#define TA1IV_TAIFG (0x000E) /* TA1IFG */
+
+/* Legacy Defines */
+#define TA1IV_TA1CCR1 (0x0002) /* TA1CCR1_CCIFG */
+#define TA1IV_TA1CCR2 (0x0004) /* TA1CCR2_CCIFG */
+#define TA1IV_TA1IFG (0x000E) /* TA1IFG */
+
+/************************************************************
+* Timer2_A2
+************************************************************/
+#define __MSP430_HAS_T2A2__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_T2A2__ 0x0400
+#define TIMER_A2_BASE __MSP430_BASEADDRESS_T2A2__
+
+sfr_w(TA2CTL); /* Timer2_A2 Control */
+sfr_w(TA2CCTL0); /* Timer2_A2 Capture/Compare Control 0 */
+sfr_w(TA2CCTL1); /* Timer2_A2 Capture/Compare Control 1 */
+sfr_w(TA2R); /* Timer2_A2 */
+sfr_w(TA2CCR0); /* Timer2_A2 Capture/Compare 0 */
+sfr_w(TA2CCR1); /* Timer2_A2 Capture/Compare 1 */
+sfr_w(TA2IV); /* Timer2_A2 Interrupt Vector Word */
+sfr_w(TA2EX0); /* Timer2_A2 Expansion Register 0 */
+
+/* Bits are already defined within the Timer0_Ax */
+
+/* TA2IV Definitions */
+#define TA2IV_NONE (0x0000) /* No Interrupt pending */
+#define TA2IV_TACCR1 (0x0002) /* TA2CCR1_CCIFG */
+#define TA2IV_3 (0x0006) /* Reserved */
+#define TA2IV_4 (0x0008) /* Reserved */
+#define TA2IV_5 (0x000A) /* Reserved */
+#define TA2IV_6 (0x000C) /* Reserved */
+#define TA2IV_TAIFG (0x000E) /* TA2IFG */
+
+/* Legacy Defines */
+#define TA2IV_TA2CCR1 (0x0002) /* TA2CCR1_CCIFG */
+#define TA2IV_TA2IFG (0x000E) /* TA2IFG */
+
+/************************************************************
+* Timer3_A5
+************************************************************/
+#define __MSP430_HAS_T3A5__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_T3A5__ 0x0440
+#define TIMER_A3_BASE __MSP430_BASEADDRESS_T3A5__
+
+sfr_w(TA3CTL); /* Timer3_A5 Control */
+sfr_w(TA3CCTL0); /* Timer3_A5 Capture/Compare Control 0 */
+sfr_w(TA3CCTL1); /* Timer3_A5 Capture/Compare Control 1 */
+sfr_w(TA3CCTL2); /* Timer3_A5 Capture/Compare Control 2 */
+sfr_w(TA3CCTL3); /* Timer3_A5 Capture/Compare Control 3 */
+sfr_w(TA3CCTL4); /* Timer3_A5 Capture/Compare Control 4 */
+sfr_w(TA3R); /* Timer3_A5 */
+sfr_w(TA3CCR0); /* Timer3_A5 Capture/Compare 0 */
+sfr_w(TA3CCR1); /* Timer3_A5 Capture/Compare 1 */
+sfr_w(TA3CCR2); /* Timer3_A5 Capture/Compare 2 */
+sfr_w(TA3CCR3); /* Timer3_A5 Capture/Compare 3 */
+sfr_w(TA3CCR4); /* Timer3_A5 Capture/Compare 4 */
+sfr_w(TA3IV); /* Timer3_A5 Interrupt Vector Word */
+sfr_w(TA3EX0); /* Timer3_A5 Expansion Register 0 */
+
+/* Bits are already defined within the Timer0_Ax */
+
+/* TA3IV Definitions */
+#define TA3IV_NONE (0x0000) /* No Interrupt pending */
+#define TA3IV_TACCR1 (0x0002) /* TA3CCR1_CCIFG */
+#define TA3IV_TACCR2 (0x0004) /* TA3CCR2_CCIFG */
+#define TA3IV_TACCR3 (0x0006) /* TA3CCR3_CCIFG */
+#define TA3IV_TACCR4 (0x0008) /* TA3CCR4_CCIFG */
+#define TA3IV_TAIFG (0x000E) /* TA3IFG */
+
+/* Legacy Defines */
+#define TA3IV_TA3CCR1 (0x0002) /* TA3CCR1_CCIFG */
+#define TA3IV_TA3CCR2 (0x0004) /* TA3CCR2_CCIFG */
+#define TA3IV_TA3CCR3 (0x0006) /* TA3CCR3_CCIFG */
+#define TA3IV_TA3CCR4 (0x0008) /* TA3CCR4_CCIFG */
+#define TA3IV_TA3IFG (0x000E) /* TA3IFG */
+
+/************************************************************
+* Timer0_B7
+************************************************************/
+#define __MSP430_HAS_T0B7__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_T0B7__ 0x03C0
+#define TIMER_B0_BASE __MSP430_BASEADDRESS_T0B7__
+
+sfr_w(TB0CTL); /* Timer0_B7 Control */
+sfr_w(TB0CCTL0); /* Timer0_B7 Capture/Compare Control 0 */
+sfr_w(TB0CCTL1); /* Timer0_B7 Capture/Compare Control 1 */
+sfr_w(TB0CCTL2); /* Timer0_B7 Capture/Compare Control 2 */
+sfr_w(TB0CCTL3); /* Timer0_B7 Capture/Compare Control 3 */
+sfr_w(TB0CCTL4); /* Timer0_B7 Capture/Compare Control 4 */
+sfr_w(TB0CCTL5); /* Timer0_B7 Capture/Compare Control 5 */
+sfr_w(TB0CCTL6); /* Timer0_B7 Capture/Compare Control 6 */
+sfr_w(TB0R); /* Timer0_B7 */
+sfr_w(TB0CCR0); /* Timer0_B7 Capture/Compare 0 */
+sfr_w(TB0CCR1); /* Timer0_B7 Capture/Compare 1 */
+sfr_w(TB0CCR2); /* Timer0_B7 Capture/Compare 2 */
+sfr_w(TB0CCR3); /* Timer0_B7 Capture/Compare 3 */
+sfr_w(TB0CCR4); /* Timer0_B7 Capture/Compare 4 */
+sfr_w(TB0CCR5); /* Timer0_B7 Capture/Compare 5 */
+sfr_w(TB0CCR6); /* Timer0_B7 Capture/Compare 6 */
+sfr_w(TB0EX0); /* Timer0_B7 Expansion Register 0 */
+sfr_w(TB0IV); /* Timer0_B7 Interrupt Vector Word */
+
+/* Legacy Type Definitions for TimerB */
+#define TBCTL TB0CTL /* Timer0_B7 Control */
+#define TBCCTL0 TB0CCTL0 /* Timer0_B7 Capture/Compare Control 0 */
+#define TBCCTL1 TB0CCTL1 /* Timer0_B7 Capture/Compare Control 1 */
+#define TBCCTL2 TB0CCTL2 /* Timer0_B7 Capture/Compare Control 2 */
+#define TBCCTL3 TB0CCTL3 /* Timer0_B7 Capture/Compare Control 3 */
+#define TBCCTL4 TB0CCTL4 /* Timer0_B7 Capture/Compare Control 4 */
+#define TBCCTL5 TB0CCTL5 /* Timer0_B7 Capture/Compare Control 5 */
+#define TBCCTL6 TB0CCTL6 /* Timer0_B7 Capture/Compare Control 6 */
+#define TBR TB0R /* Timer0_B7 */
+#define TBCCR0 TB0CCR0 /* Timer0_B7 Capture/Compare 0 */
+#define TBCCR1 TB0CCR1 /* Timer0_B7 Capture/Compare 1 */
+#define TBCCR2 TB0CCR2 /* Timer0_B7 Capture/Compare 2 */
+#define TBCCR3 TB0CCR3 /* Timer0_B7 Capture/Compare 3 */
+#define TBCCR4 TB0CCR4 /* Timer0_B7 Capture/Compare 4 */
+#define TBCCR5 TB0CCR5 /* Timer0_B7 Capture/Compare 5 */
+#define TBCCR6 TB0CCR6 /* Timer0_B7 Capture/Compare 6 */
+#define TBEX0 TB0EX0 /* Timer0_B7 Expansion Register 0 */
+#define TBIV TB0IV /* Timer0_B7 Interrupt Vector Word */
+#define TIMERB1_VECTOR TIMER0_B1_VECTOR /* Timer0_B7 CC1-6, TB */
+#define TIMERB0_VECTOR TIMER0_B0_VECTOR /* Timer0_B7 CC0 */
+
+/* TBxCTL Control Bits */
+#define TBCLGRP1 (0x4000) /* Timer0_B7 Compare latch load group 1 */
+#define TBCLGRP0 (0x2000) /* Timer0_B7 Compare latch load group 0 */
+#define CNTL1 (0x1000) /* Counter lenght 1 */
+#define CNTL0 (0x0800) /* Counter lenght 0 */
+#define TBSSEL1 (0x0200) /* Clock source 1 */
+#define TBSSEL0 (0x0100) /* Clock source 0 */
+#define TBCLR (0x0004) /* Timer0_B7 counter clear */
+#define TBIE (0x0002) /* Timer0_B7 interrupt enable */
+#define TBIFG (0x0001) /* Timer0_B7 interrupt flag */
+
+#define SHR1 (0x4000) /* Timer0_B7 Compare latch load group 1 */
+#define SHR0 (0x2000) /* Timer0_B7 Compare latch load group 0 */
+
+#define TBSSEL_0 (0x0000) /* Clock Source: TBCLK */
+#define TBSSEL_1 (0x0100) /* Clock Source: ACLK */
+#define TBSSEL_2 (0x0200) /* Clock Source: SMCLK */
+#define TBSSEL_3 (0x0300) /* Clock Source: INCLK */
+#define CNTL_0 (0x0000) /* Counter lenght: 16 bit */
+#define CNTL_1 (0x0800) /* Counter lenght: 12 bit */
+#define CNTL_2 (0x1000) /* Counter lenght: 10 bit */
+#define CNTL_3 (0x1800) /* Counter lenght: 8 bit */
+#define SHR_0 (0x0000) /* Timer0_B7 Group: 0 - individually */
+#define SHR_1 (0x2000) /* Timer0_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
+#define SHR_2 (0x4000) /* Timer0_B7 Group: 2 - 2 groups (1-3, 4-6)*/
+#define SHR_3 (0x6000) /* Timer0_B7 Group: 3 - 1 group (all) */
+#define TBCLGRP_0 (0x0000) /* Timer0_B7 Group: 0 - individually */
+#define TBCLGRP_1 (0x2000) /* Timer0_B7 Group: 1 - 3 groups (1-2, 3-4, 5-6) */
+#define TBCLGRP_2 (0x4000) /* Timer0_B7 Group: 2 - 2 groups (1-3, 4-6)*/
+#define TBCLGRP_3 (0x6000) /* Timer0_B7 Group: 3 - 1 group (all) */
+#define TBSSEL__TBCLK (0x0000) /* Timer0_B7 clock source select: 0 - TBCLK */
+#define TBSSEL__TACLK (0x0000) /* Timer0_B7 clock source select: 0 - TBCLK (legacy) */
+#define TBSSEL__ACLK (0x0100) /* Timer0_B7 clock source select: 1 - ACLK */
+#define TBSSEL__SMCLK (0x0200) /* Timer0_B7 clock source select: 2 - SMCLK */
+#define TBSSEL__INCLK (0x0300) /* Timer0_B7 clock source select: 3 - INCLK */
+#define CNTL__16 (0x0000) /* Counter lenght: 16 bit */
+#define CNTL__12 (0x0800) /* Counter lenght: 12 bit */
+#define CNTL__10 (0x1000) /* Counter lenght: 10 bit */
+#define CNTL__8 (0x1800) /* Counter lenght: 8 bit */
+
+/* Additional Timer B Control Register bits are defined in Timer A */
+/* TBxCCTLx Control Bits */
+#define CLLD1 (0x0400) /* Compare latch load source 1 */
+#define CLLD0 (0x0200) /* Compare latch load source 0 */
+
+#define SLSHR1 (0x0400) /* Compare latch load source 1 */
+#define SLSHR0 (0x0200) /* Compare latch load source 0 */
+
+#define SLSHR_0 (0x0000) /* Compare latch load sourec : 0 - immediate */
+#define SLSHR_1 (0x0200) /* Compare latch load sourec : 1 - TBR counts to 0 */
+#define SLSHR_2 (0x0400) /* Compare latch load sourec : 2 - up/down */
+#define SLSHR_3 (0x0600) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
+
+#define CLLD_0 (0x0000) /* Compare latch load sourec : 0 - immediate */
+#define CLLD_1 (0x0200) /* Compare latch load sourec : 1 - TBR counts to 0 */
+#define CLLD_2 (0x0400) /* Compare latch load sourec : 2 - up/down */
+#define CLLD_3 (0x0600) /* Compare latch load sourec : 3 - TBR counts to TBCTL0 */
+
+/* TBxEX0 Control Bits */
+#define TBIDEX0 (0x0001) /* Timer0_B7 Input divider expansion Bit: 0 */
+#define TBIDEX1 (0x0002) /* Timer0_B7 Input divider expansion Bit: 1 */
+#define TBIDEX2 (0x0004) /* Timer0_B7 Input divider expansion Bit: 2 */
+
+#define TBIDEX_0 (0x0000) /* Timer0_B7 Input divider expansion : /1 */
+#define TBIDEX_1 (0x0001) /* Timer0_B7 Input divider expansion : /2 */
+#define TBIDEX_2 (0x0002) /* Timer0_B7 Input divider expansion : /3 */
+#define TBIDEX_3 (0x0003) /* Timer0_B7 Input divider expansion : /4 */
+#define TBIDEX_4 (0x0004) /* Timer0_B7 Input divider expansion : /5 */
+#define TBIDEX_5 (0x0005) /* Timer0_B7 Input divider expansion : /6 */
+#define TBIDEX_6 (0x0006) /* Timer0_B7 Input divider expansion : /7 */
+#define TBIDEX_7 (0x0007) /* Timer0_B7 Input divider expansion : /8 */
+#define TBIDEX__1 (0x0000) /* Timer0_B7 Input divider expansion : /1 */
+#define TBIDEX__2 (0x0001) /* Timer0_B7 Input divider expansion : /2 */
+#define TBIDEX__3 (0x0002) /* Timer0_B7 Input divider expansion : /3 */
+#define TBIDEX__4 (0x0003) /* Timer0_B7 Input divider expansion : /4 */
+#define TBIDEX__5 (0x0004) /* Timer0_B7 Input divider expansion : /5 */
+#define TBIDEX__6 (0x0005) /* Timer0_B7 Input divider expansion : /6 */
+#define TBIDEX__7 (0x0006) /* Timer0_B7 Input divider expansion : /7 */
+#define TBIDEX__8 (0x0007) /* Timer0_B7 Input divider expansion : /8 */
+
+/* TB0IV Definitions */
+#define TB0IV_NONE (0x0000) /* No Interrupt pending */
+#define TB0IV_TBCCR1 (0x0002) /* TB0CCR1_CCIFG */
+#define TB0IV_TBCCR2 (0x0004) /* TB0CCR2_CCIFG */
+#define TB0IV_TBCCR3 (0x0006) /* TB0CCR3_CCIFG */
+#define TB0IV_TBCCR4 (0x0008) /* TB0CCR4_CCIFG */
+#define TB0IV_TBCCR5 (0x000A) /* TB0CCR5_CCIFG */
+#define TB0IV_TBCCR6 (0x000C) /* TB0CCR6_CCIFG */
+#define TB0IV_TBIFG (0x000E) /* TB0IFG */
+
+/* Legacy Defines */
+#define TB0IV_TB0CCR1 (0x0002) /* TB0CCR1_CCIFG */
+#define TB0IV_TB0CCR2 (0x0004) /* TB0CCR2_CCIFG */
+#define TB0IV_TB0CCR3 (0x0006) /* TB0CCR3_CCIFG */
+#define TB0IV_TB0CCR4 (0x0008) /* TB0CCR4_CCIFG */
+#define TB0IV_TB0CCR5 (0x000A) /* TB0CCR5_CCIFG */
+#define TB0IV_TB0CCR6 (0x000C) /* TB0CCR6_CCIFG */
+#define TB0IV_TB0IFG (0x000E) /* TB0IFG */
+
+
+/************************************************************
+* USCI A0
+************************************************************/
+#define __MSP430_HAS_EUSCI_A0__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_EUSCI_A0__ 0x05C0
+#define EUSCI_A0_BASE __MSP430_BASEADDRESS_EUSCI_A0__
+
+sfr_w(UCA0CTLW0); /* USCI A0 Control Word Register 0 */
+sfr_b(UCA0CTLW0_L); /* USCI A0 Control Word Register 0 */
+sfr_b(UCA0CTLW0_H); /* USCI A0 Control Word Register 0 */
+#define UCA0CTL1 UCA0CTLW0_L /* USCI A0 Control Register 1 */
+#define UCA0CTL0 UCA0CTLW0_H /* USCI A0 Control Register 0 */
+sfr_w(UCA0CTLW1); /* USCI A0 Control Word Register 1 */
+sfr_b(UCA0CTLW1_L); /* USCI A0 Control Word Register 1 */
+sfr_b(UCA0CTLW1_H); /* USCI A0 Control Word Register 1 */
+sfr_w(UCA0BRW); /* USCI A0 Baud Word Rate 0 */
+sfr_b(UCA0BRW_L); /* USCI A0 Baud Word Rate 0 */
+sfr_b(UCA0BRW_H); /* USCI A0 Baud Word Rate 0 */
+#define UCA0BR0 UCA0BRW_L /* USCI A0 Baud Rate 0 */
+#define UCA0BR1 UCA0BRW_H /* USCI A0 Baud Rate 1 */
+sfr_w(UCA0MCTLW); /* USCI A0 Modulation Control */
+sfr_b(UCA0MCTLW_L); /* USCI A0 Modulation Control */
+sfr_b(UCA0MCTLW_H); /* USCI A0 Modulation Control */
+sfr_b(UCA0STATW); /* USCI A0 Status Register */
+sfr_w(UCA0RXBUF); /* USCI A0 Receive Buffer */
+sfr_b(UCA0RXBUF_L); /* USCI A0 Receive Buffer */
+sfr_b(UCA0RXBUF_H); /* USCI A0 Receive Buffer */
+sfr_w(UCA0TXBUF); /* USCI A0 Transmit Buffer */
+sfr_b(UCA0TXBUF_L); /* USCI A0 Transmit Buffer */
+sfr_b(UCA0TXBUF_H); /* USCI A0 Transmit Buffer */
+sfr_b(UCA0ABCTL); /* USCI A0 LIN Control */
+sfr_w(UCA0IRCTL); /* USCI A0 IrDA Transmit Control */
+sfr_b(UCA0IRCTL_L); /* USCI A0 IrDA Transmit Control */
+sfr_b(UCA0IRCTL_H); /* USCI A0 IrDA Transmit Control */
+#define UCA0IRTCTL UCA0IRCTL_L /* USCI A0 IrDA Transmit Control */
+#define UCA0IRRCTL UCA0IRCTL_H /* USCI A0 IrDA Receive Control */
+sfr_w(UCA0IE); /* USCI A0 Interrupt Enable Register */
+sfr_b(UCA0IE_L); /* USCI A0 Interrupt Enable Register */
+sfr_b(UCA0IE_H); /* USCI A0 Interrupt Enable Register */
+sfr_w(UCA0IFG); /* USCI A0 Interrupt Flags Register */
+sfr_b(UCA0IFG_L); /* USCI A0 Interrupt Flags Register */
+sfr_b(UCA0IFG_H); /* USCI A0 Interrupt Flags Register */
+sfr_w(UCA0IV); /* USCI A0 Interrupt Vector Register */
+
+
+/************************************************************
+* USCI A1
+************************************************************/
+#define __MSP430_HAS_EUSCI_A1__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_EUSCI_A1__ 0x05E0
+#define EUSCI_A1_BASE __MSP430_BASEADDRESS_EUSCI_A1__
+
+sfr_w(UCA1CTLW0); /* USCI A1 Control Word Register 0 */
+sfr_b(UCA1CTLW0_L); /* USCI A1 Control Word Register 0 */
+sfr_b(UCA1CTLW0_H); /* USCI A1 Control Word Register 0 */
+#define UCA1CTL1 UCA1CTLW0_L /* USCI A1 Control Register 1 */
+#define UCA1CTL0 UCA1CTLW0_H /* USCI A1 Control Register 0 */
+sfr_w(UCA1CTLW1); /* USCI A1 Control Word Register 1 */
+sfr_b(UCA1CTLW1_L); /* USCI A1 Control Word Register 1 */
+sfr_b(UCA1CTLW1_H); /* USCI A1 Control Word Register 1 */
+sfr_w(UCA1BRW); /* USCI A1 Baud Word Rate 0 */
+sfr_b(UCA1BRW_L); /* USCI A1 Baud Word Rate 0 */
+sfr_b(UCA1BRW_H); /* USCI A1 Baud Word Rate 0 */
+#define UCA1BR0 UCA1BRW_L /* USCI A1 Baud Rate 0 */
+#define UCA1BR1 UCA1BRW_H /* USCI A1 Baud Rate 1 */
+sfr_w(UCA1MCTLW); /* USCI A1 Modulation Control */
+sfr_b(UCA1MCTLW_L); /* USCI A1 Modulation Control */
+sfr_b(UCA1MCTLW_H); /* USCI A1 Modulation Control */
+sfr_b(UCA1STATW); /* USCI A1 Status Register */
+sfr_w(UCA1RXBUF); /* USCI A1 Receive Buffer */
+sfr_b(UCA1RXBUF_L); /* USCI A1 Receive Buffer */
+sfr_b(UCA1RXBUF_H); /* USCI A1 Receive Buffer */
+sfr_w(UCA1TXBUF); /* USCI A1 Transmit Buffer */
+sfr_b(UCA1TXBUF_L); /* USCI A1 Transmit Buffer */
+sfr_b(UCA1TXBUF_H); /* USCI A1 Transmit Buffer */
+sfr_b(UCA1ABCTL); /* USCI A1 LIN Control */
+sfr_w(UCA1IRCTL); /* USCI A1 IrDA Transmit Control */
+sfr_b(UCA1IRCTL_L); /* USCI A1 IrDA Transmit Control */
+sfr_b(UCA1IRCTL_H); /* USCI A1 IrDA Transmit Control */
+#define UCA1IRTCTL UCA1IRCTL_L /* USCI A1 IrDA Transmit Control */
+#define UCA1IRRCTL UCA1IRCTL_H /* USCI A1 IrDA Receive Control */
+sfr_w(UCA1IE); /* USCI A1 Interrupt Enable Register */
+sfr_b(UCA1IE_L); /* USCI A1 Interrupt Enable Register */
+sfr_b(UCA1IE_H); /* USCI A1 Interrupt Enable Register */
+sfr_w(UCA1IFG); /* USCI A1 Interrupt Flags Register */
+sfr_b(UCA1IFG_L); /* USCI A1 Interrupt Flags Register */
+sfr_b(UCA1IFG_H); /* USCI A1 Interrupt Flags Register */
+sfr_w(UCA1IV); /* USCI A1 Interrupt Vector Register */
+
+
+/************************************************************
+* USCI B0
+************************************************************/
+#define __MSP430_HAS_EUSCI_B0__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_EUSCI_B0__ 0x0640
+#define EUSCI_B0_BASE __MSP430_BASEADDRESS_EUSCI_B0__
+
+
+sfr_w(UCB0CTLW0); /* USCI B0 Control Word Register 0 */
+sfr_b(UCB0CTLW0_L); /* USCI B0 Control Word Register 0 */
+sfr_b(UCB0CTLW0_H); /* USCI B0 Control Word Register 0 */
+#define UCB0CTL1 UCB0CTLW0_L /* USCI B0 Control Register 1 */
+#define UCB0CTL0 UCB0CTLW0_H /* USCI B0 Control Register 0 */
+sfr_w(UCB0CTLW1); /* USCI B0 Control Word Register 1 */
+sfr_b(UCB0CTLW1_L); /* USCI B0 Control Word Register 1 */
+sfr_b(UCB0CTLW1_H); /* USCI B0 Control Word Register 1 */
+sfr_w(UCB0BRW); /* USCI B0 Baud Word Rate 0 */
+sfr_b(UCB0BRW_L); /* USCI B0 Baud Word Rate 0 */
+sfr_b(UCB0BRW_H); /* USCI B0 Baud Word Rate 0 */
+#define UCB0BR0 UCB0BRW_L /* USCI B0 Baud Rate 0 */
+#define UCB0BR1 UCB0BRW_H /* USCI B0 Baud Rate 1 */
+sfr_w(UCB0STATW); /* USCI B0 Status Word Register */
+sfr_b(UCB0STATW_L); /* USCI B0 Status Word Register */
+sfr_b(UCB0STATW_H); /* USCI B0 Status Word Register */
+#define UCB0STAT UCB0STATW_L /* USCI B0 Status Register */
+#define UCB0BCNT UCB0STATW_H /* USCI B0 Byte Counter Register */
+sfr_w(UCB0TBCNT); /* USCI B0 Byte Counter Threshold Register */
+sfr_b(UCB0TBCNT_L); /* USCI B0 Byte Counter Threshold Register */
+sfr_b(UCB0TBCNT_H); /* USCI B0 Byte Counter Threshold Register */
+sfr_w(UCB0RXBUF); /* USCI B0 Receive Buffer */
+sfr_b(UCB0RXBUF_L); /* USCI B0 Receive Buffer */
+sfr_b(UCB0RXBUF_H); /* USCI B0 Receive Buffer */
+sfr_w(UCB0TXBUF); /* USCI B0 Transmit Buffer */
+sfr_b(UCB0TXBUF_L); /* USCI B0 Transmit Buffer */
+sfr_b(UCB0TXBUF_H); /* USCI B0 Transmit Buffer */
+sfr_w(UCB0I2COA0); /* USCI B0 I2C Own Address 0 */
+sfr_b(UCB0I2COA0_L); /* USCI B0 I2C Own Address 0 */
+sfr_b(UCB0I2COA0_H); /* USCI B0 I2C Own Address 0 */
+sfr_w(UCB0I2COA1); /* USCI B0 I2C Own Address 1 */
+sfr_b(UCB0I2COA1_L); /* USCI B0 I2C Own Address 1 */
+sfr_b(UCB0I2COA1_H); /* USCI B0 I2C Own Address 1 */
+sfr_w(UCB0I2COA2); /* USCI B0 I2C Own Address 2 */
+sfr_b(UCB0I2COA2_L); /* USCI B0 I2C Own Address 2 */
+sfr_b(UCB0I2COA2_H); /* USCI B0 I2C Own Address 2 */
+sfr_w(UCB0I2COA3); /* USCI B0 I2C Own Address 3 */
+sfr_b(UCB0I2COA3_L); /* USCI B0 I2C Own Address 3 */
+sfr_b(UCB0I2COA3_H); /* USCI B0 I2C Own Address 3 */
+sfr_w(UCB0ADDRX); /* USCI B0 Received Address Register */
+sfr_b(UCB0ADDRX_L); /* USCI B0 Received Address Register */
+sfr_b(UCB0ADDRX_H); /* USCI B0 Received Address Register */
+sfr_w(UCB0ADDMASK); /* USCI B0 Address Mask Register */
+sfr_b(UCB0ADDMASK_L); /* USCI B0 Address Mask Register */
+sfr_b(UCB0ADDMASK_H); /* USCI B0 Address Mask Register */
+sfr_w(UCB0I2CSA); /* USCI B0 I2C Slave Address */
+sfr_b(UCB0I2CSA_L); /* USCI B0 I2C Slave Address */
+sfr_b(UCB0I2CSA_H); /* USCI B0 I2C Slave Address */
+sfr_w(UCB0IE); /* USCI B0 Interrupt Enable Register */
+sfr_b(UCB0IE_L); /* USCI B0 Interrupt Enable Register */
+sfr_b(UCB0IE_H); /* USCI B0 Interrupt Enable Register */
+sfr_w(UCB0IFG); /* USCI B0 Interrupt Flags Register */
+sfr_b(UCB0IFG_L); /* USCI B0 Interrupt Flags Register */
+sfr_b(UCB0IFG_H); /* USCI B0 Interrupt Flags Register */
+sfr_w(UCB0IV); /* USCI B0 Interrupt Vector Register */
+
+/************************************************************
+* USCI B1
+************************************************************/
+#define __MSP430_HAS_EUSCI_B1__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_EUSCI_B1__ 0x0680
+#define EUSCI_B1_BASE __MSP430_BASEADDRESS_EUSCI_B1__
+
+
+sfr_w(UCB1CTLW0); /* USCI B1 Control Word Register 0 */
+sfr_b(UCB1CTLW0_L); /* USCI B1 Control Word Register 0 */
+sfr_b(UCB1CTLW0_H); /* USCI B1 Control Word Register 0 */
+#define UCB1CTL1 UCB1CTLW0_L /* USCI B1 Control Register 1 */
+#define UCB1CTL0 UCB1CTLW0_H /* USCI B1 Control Register 0 */
+sfr_w(UCB1CTLW1); /* USCI B1 Control Word Register 1 */
+sfr_b(UCB1CTLW1_L); /* USCI B1 Control Word Register 1 */
+sfr_b(UCB1CTLW1_H); /* USCI B1 Control Word Register 1 */
+sfr_w(UCB1BRW); /* USCI B1 Baud Word Rate 0 */
+sfr_b(UCB1BRW_L); /* USCI B1 Baud Word Rate 0 */
+sfr_b(UCB1BRW_H); /* USCI B1 Baud Word Rate 0 */
+#define UCB1BR0 UCB1BRW_L /* USCI B1 Baud Rate 0 */
+#define UCB1BR1 UCB1BRW_H /* USCI B1 Baud Rate 1 */
+sfr_w(UCB1STATW); /* USCI B1 Status Word Register */
+sfr_b(UCB1STATW_L); /* USCI B1 Status Word Register */
+sfr_b(UCB1STATW_H); /* USCI B1 Status Word Register */
+#define UCB1STAT UCB1STATW_L /* USCI B1 Status Register */
+#define UCB1BCNT UCB1STATW_H /* USCI B1 Byte Counter Register */
+sfr_w(UCB1TBCNT); /* USCI B1 Byte Counter Threshold Register */
+sfr_b(UCB1TBCNT_L); /* USCI B1 Byte Counter Threshold Register */
+sfr_b(UCB1TBCNT_H); /* USCI B1 Byte Counter Threshold Register */
+sfr_w(UCB1RXBUF); /* USCI B1 Receive Buffer */
+sfr_b(UCB1RXBUF_L); /* USCI B1 Receive Buffer */
+sfr_b(UCB1RXBUF_H); /* USCI B1 Receive Buffer */
+sfr_w(UCB1TXBUF); /* USCI B1 Transmit Buffer */
+sfr_b(UCB1TXBUF_L); /* USCI B1 Transmit Buffer */
+sfr_b(UCB1TXBUF_H); /* USCI B1 Transmit Buffer */
+sfr_w(UCB1I2COA0); /* USCI B1 I2C Own Address 0 */
+sfr_b(UCB1I2COA0_L); /* USCI B1 I2C Own Address 0 */
+sfr_b(UCB1I2COA0_H); /* USCI B1 I2C Own Address 0 */
+sfr_w(UCB1I2COA1); /* USCI B1 I2C Own Address 1 */
+sfr_b(UCB1I2COA1_L); /* USCI B1 I2C Own Address 1 */
+sfr_b(UCB1I2COA1_H); /* USCI B1 I2C Own Address 1 */
+sfr_w(UCB1I2COA2); /* USCI B1 I2C Own Address 2 */
+sfr_b(UCB1I2COA2_L); /* USCI B1 I2C Own Address 2 */
+sfr_b(UCB1I2COA2_H); /* USCI B1 I2C Own Address 2 */
+sfr_w(UCB1I2COA3); /* USCI B1 I2C Own Address 3 */
+sfr_b(UCB1I2COA3_L); /* USCI B1 I2C Own Address 3 */
+sfr_b(UCB1I2COA3_H); /* USCI B1 I2C Own Address 3 */
+sfr_w(UCB1ADDRX); /* USCI B1 Received Address Register */
+sfr_b(UCB1ADDRX_L); /* USCI B1 Received Address Register */
+sfr_b(UCB1ADDRX_H); /* USCI B1 Received Address Register */
+sfr_w(UCB1ADDMASK); /* USCI B1 Address Mask Register */
+sfr_b(UCB1ADDMASK_L); /* USCI B1 Address Mask Register */
+sfr_b(UCB1ADDMASK_H); /* USCI B1 Address Mask Register */
+sfr_w(UCB1I2CSA); /* USCI B1 I2C Slave Address */
+sfr_b(UCB1I2CSA_L); /* USCI B1 I2C Slave Address */
+sfr_b(UCB1I2CSA_H); /* USCI B1 I2C Slave Address */
+sfr_w(UCB1IE); /* USCI B1 Interrupt Enable Register */
+sfr_b(UCB1IE_L); /* USCI B1 Interrupt Enable Register */
+sfr_b(UCB1IE_H); /* USCI B1 Interrupt Enable Register */
+sfr_w(UCB1IFG); /* USCI B1 Interrupt Flags Register */
+sfr_b(UCB1IFG_L); /* USCI B1 Interrupt Flags Register */
+sfr_b(UCB1IFG_H); /* USCI B1 Interrupt Flags Register */
+sfr_w(UCB1IV); /* USCI B1 Interrupt Vector Register */
+
+// UCAxCTLW0 UART-Mode Control Bits
+#define UCPEN (0x8000) /* Async. Mode: Parity enable */
+#define UCPAR (0x4000) /* Async. Mode: Parity 0:odd / 1:even */
+#define UCMSB (0x2000) /* Async. Mode: MSB first 0:LSB / 1:MSB */
+#define UC7BIT (0x1000) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */
+#define UCSPB (0x0800) /* Async. Mode: Stop Bits 0:one / 1: two */
+#define UCMODE1 (0x0400) /* Async. Mode: USCI Mode 1 */
+#define UCMODE0 (0x0200) /* Async. Mode: USCI Mode 0 */
+#define UCSYNC (0x0100) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */
+#define UCSSEL1 (0x0080) /* USCI 0 Clock Source Select 1 */
+#define UCSSEL0 (0x0040) /* USCI 0 Clock Source Select 0 */
+#define UCRXEIE (0x0020) /* RX Error interrupt enable */
+#define UCBRKIE (0x0010) /* Break interrupt enable */
+#define UCDORM (0x0008) /* Dormant (Sleep) Mode */
+#define UCTXADDR (0x0004) /* Send next Data as Address */
+#define UCTXBRK (0x0002) /* Send next Data as Break */
+#define UCSWRST (0x0001) /* USCI Software Reset */
+
+// UCAxCTLW0 UART-Mode Control Bits
+#define UCSSEL1_L (0x0080) /* USCI 0 Clock Source Select 1 */
+#define UCSSEL0_L (0x0040) /* USCI 0 Clock Source Select 0 */
+#define UCRXEIE_L (0x0020) /* RX Error interrupt enable */
+#define UCBRKIE_L (0x0010) /* Break interrupt enable */
+#define UCDORM_L (0x0008) /* Dormant (Sleep) Mode */
+#define UCTXADDR_L (0x0004) /* Send next Data as Address */
+#define UCTXBRK_L (0x0002) /* Send next Data as Break */
+#define UCSWRST_L (0x0001) /* USCI Software Reset */
+
+// UCAxCTLW0 UART-Mode Control Bits
+#define UCPEN_H (0x0080) /* Async. Mode: Parity enable */
+#define UCPAR_H (0x0040) /* Async. Mode: Parity 0:odd / 1:even */
+#define UCMSB_H (0x0020) /* Async. Mode: MSB first 0:LSB / 1:MSB */
+#define UC7BIT_H (0x0010) /* Async. Mode: Data Bits 0:8-bits / 1:7-bits */
+#define UCSPB_H (0x0008) /* Async. Mode: Stop Bits 0:one / 1: two */
+#define UCMODE1_H (0x0004) /* Async. Mode: USCI Mode 1 */
+#define UCMODE0_H (0x0002) /* Async. Mode: USCI Mode 0 */
+#define UCSYNC_H (0x0001) /* Sync-Mode 0:UART-Mode / 1:SPI-Mode */
+
+// UCxxCTLW0 SPI-Mode Control Bits
+#define UCCKPH (0x8000) /* Sync. Mode: Clock Phase */
+#define UCCKPL (0x4000) /* Sync. Mode: Clock Polarity */
+#define UCMST (0x0800) /* Sync. Mode: Master Select */
+//#define res (0x0020) /* reserved */
+//#define res (0x0010) /* reserved */
+//#define res (0x0008) /* reserved */
+//#define res (0x0004) /* reserved */
+#define UCSTEM (0x0002) /* USCI STE Mode */
+
+// UCBxCTLW0 I2C-Mode Control Bits
+#define UCA10 (0x8000) /* 10-bit Address Mode */
+#define UCSLA10 (0x4000) /* 10-bit Slave Address Mode */
+#define UCMM (0x2000) /* Multi-Master Environment */
+//#define res (0x1000) /* reserved */
+//#define res (0x0100) /* reserved */
+#define UCTXACK (0x0020) /* Transmit ACK */
+#define UCTR (0x0010) /* Transmit/Receive Select/Flag */
+#define UCTXNACK (0x0008) /* Transmit NACK */
+#define UCTXSTP (0x0004) /* Transmit STOP */
+#define UCTXSTT (0x0002) /* Transmit START */
+
+// UCBxCTLW0 I2C-Mode Control Bits
+//#define res (0x1000) /* reserved */
+//#define res (0x0100) /* reserved */
+#define UCTXACK_L (0x0020) /* Transmit ACK */
+#define UCTR_L (0x0010) /* Transmit/Receive Select/Flag */
+#define UCTXNACK_L (0x0008) /* Transmit NACK */
+#define UCTXSTP_L (0x0004) /* Transmit STOP */
+#define UCTXSTT_L (0x0002) /* Transmit START */
+
+// UCBxCTLW0 I2C-Mode Control Bits
+#define UCA10_H (0x0080) /* 10-bit Address Mode */
+#define UCSLA10_H (0x0040) /* 10-bit Slave Address Mode */
+#define UCMM_H (0x0020) /* Multi-Master Environment */
+//#define res (0x1000) /* reserved */
+//#define res (0x0100) /* reserved */
+
+#define UCMODE_0 (0x0000) /* Sync. Mode: USCI Mode: 0 */
+#define UCMODE_1 (0x0200) /* Sync. Mode: USCI Mode: 1 */
+#define UCMODE_2 (0x0400) /* Sync. Mode: USCI Mode: 2 */
+#define UCMODE_3 (0x0600) /* Sync. Mode: USCI Mode: 3 */
+
+#define UCSSEL_0 (0x0000) /* USCI 0 Clock Source: 0 */
+#define UCSSEL_1 (0x0040) /* USCI 0 Clock Source: 1 */
+#define UCSSEL_2 (0x0080) /* USCI 0 Clock Source: 2 */
+#define UCSSEL_3 (0x00C0) /* USCI 0 Clock Source: 3 */
+#define UCSSEL__UCLK (0x0000) /* USCI 0 Clock Source: UCLK */
+#define UCSSEL__ACLK (0x0040) /* USCI 0 Clock Source: ACLK */
+#define UCSSEL__SMCLK (0x0080) /* USCI 0 Clock Source: SMCLK */
+
+// UCAxCTLW1 UART-Mode Control Bits
+#define UCGLIT1 (0x0002) /* USCI Deglitch Time Bit 1 */
+#define UCGLIT0 (0x0001) /* USCI Deglitch Time Bit 0 */
+
+// UCAxCTLW1 UART-Mode Control Bits
+#define UCGLIT1_L (0x0002) /* USCI Deglitch Time Bit 1 */
+#define UCGLIT0_L (0x0001) /* USCI Deglitch Time Bit 0 */
+
+// UCBxCTLW1 I2C-Mode Control Bits
+#define UCETXINT (0x0100) /* USCI Early UCTXIFG0 */
+#define UCCLTO1 (0x0080) /* USCI Clock low timeout Bit: 1 */
+#define UCCLTO0 (0x0040) /* USCI Clock low timeout Bit: 0 */
+#define UCSTPNACK (0x0020) /* USCI Acknowledge Stop last byte */
+#define UCSWACK (0x0010) /* USCI Software controlled ACK */
+#define UCASTP1 (0x0008) /* USCI Automatic Stop condition generation Bit: 1 */
+#define UCASTP0 (0x0004) /* USCI Automatic Stop condition generation Bit: 0 */
+#define UCGLIT1 (0x0002) /* USCI Deglitch time Bit: 1 */
+#define UCGLIT0 (0x0001) /* USCI Deglitch time Bit: 0 */
+
+// UCBxCTLW1 I2C-Mode Control Bits
+#define UCCLTO1_L (0x0080) /* USCI Clock low timeout Bit: 1 */
+#define UCCLTO0_L (0x0040) /* USCI Clock low timeout Bit: 0 */
+#define UCSTPNACK_L (0x0020) /* USCI Acknowledge Stop last byte */
+#define UCSWACK_L (0x0010) /* USCI Software controlled ACK */
+#define UCASTP1_L (0x0008) /* USCI Automatic Stop condition generation Bit: 1 */
+#define UCASTP0_L (0x0004) /* USCI Automatic Stop condition generation Bit: 0 */
+#define UCGLIT1_L (0x0002) /* USCI Deglitch time Bit: 1 */
+#define UCGLIT0_L (0x0001) /* USCI Deglitch time Bit: 0 */
+
+// UCBxCTLW1 I2C-Mode Control Bits
+#define UCETXINT_H (0x0001) /* USCI Early UCTXIFG0 */
+
+#define UCGLIT_0 (0x0000) /* USCI Deglitch time: 0 */
+#define UCGLIT_1 (0x0001) /* USCI Deglitch time: 1 */
+#define UCGLIT_2 (0x0002) /* USCI Deglitch time: 2 */
+#define UCGLIT_3 (0x0003) /* USCI Deglitch time: 3 */
+
+#define UCASTP_0 (0x0000) /* USCI Automatic Stop condition generation: 0 */
+#define UCASTP_1 (0x0004) /* USCI Automatic Stop condition generation: 1 */
+#define UCASTP_2 (0x0008) /* USCI Automatic Stop condition generation: 2 */
+#define UCASTP_3 (0x000C) /* USCI Automatic Stop condition generation: 3 */
+
+#define UCCLTO_0 (0x0000) /* USCI Clock low timeout: 0 */
+#define UCCLTO_1 (0x0040) /* USCI Clock low timeout: 1 */
+#define UCCLTO_2 (0x0080) /* USCI Clock low timeout: 2 */
+#define UCCLTO_3 (0x00C0) /* USCI Clock low timeout: 3 */
+
+/* UCAxMCTLW Control Bits */
+#define UCBRS7 (0x8000) /* USCI Second Stage Modulation Select 7 */
+#define UCBRS6 (0x4000) /* USCI Second Stage Modulation Select 6 */
+#define UCBRS5 (0x2000) /* USCI Second Stage Modulation Select 5 */
+#define UCBRS4 (0x1000) /* USCI Second Stage Modulation Select 4 */
+#define UCBRS3 (0x0800) /* USCI Second Stage Modulation Select 3 */
+#define UCBRS2 (0x0400) /* USCI Second Stage Modulation Select 2 */
+#define UCBRS1 (0x0200) /* USCI Second Stage Modulation Select 1 */
+#define UCBRS0 (0x0100) /* USCI Second Stage Modulation Select 0 */
+#define UCBRF3 (0x0080) /* USCI First Stage Modulation Select 3 */
+#define UCBRF2 (0x0040) /* USCI First Stage Modulation Select 2 */
+#define UCBRF1 (0x0020) /* USCI First Stage Modulation Select 1 */
+#define UCBRF0 (0x0010) /* USCI First Stage Modulation Select 0 */
+#define UCOS16 (0x0001) /* USCI 16-times Oversampling enable */
+
+/* UCAxMCTLW Control Bits */
+#define UCBRF3_L (0x0080) /* USCI First Stage Modulation Select 3 */
+#define UCBRF2_L (0x0040) /* USCI First Stage Modulation Select 2 */
+#define UCBRF1_L (0x0020) /* USCI First Stage Modulation Select 1 */
+#define UCBRF0_L (0x0010) /* USCI First Stage Modulation Select 0 */
+#define UCOS16_L (0x0001) /* USCI 16-times Oversampling enable */
+
+/* UCAxMCTLW Control Bits */
+#define UCBRS7_H (0x0080) /* USCI Second Stage Modulation Select 7 */
+#define UCBRS6_H (0x0040) /* USCI Second Stage Modulation Select 6 */
+#define UCBRS5_H (0x0020) /* USCI Second Stage Modulation Select 5 */
+#define UCBRS4_H (0x0010) /* USCI Second Stage Modulation Select 4 */
+#define UCBRS3_H (0x0008) /* USCI Second Stage Modulation Select 3 */
+#define UCBRS2_H (0x0004) /* USCI Second Stage Modulation Select 2 */
+#define UCBRS1_H (0x0002) /* USCI Second Stage Modulation Select 1 */
+#define UCBRS0_H (0x0001) /* USCI Second Stage Modulation Select 0 */
+
+#define UCBRF_0 (0x00) /* USCI First Stage Modulation: 0 */
+#define UCBRF_1 (0x10) /* USCI First Stage Modulation: 1 */
+#define UCBRF_2 (0x20) /* USCI First Stage Modulation: 2 */
+#define UCBRF_3 (0x30) /* USCI First Stage Modulation: 3 */
+#define UCBRF_4 (0x40) /* USCI First Stage Modulation: 4 */
+#define UCBRF_5 (0x50) /* USCI First Stage Modulation: 5 */
+#define UCBRF_6 (0x60) /* USCI First Stage Modulation: 6 */
+#define UCBRF_7 (0x70) /* USCI First Stage Modulation: 7 */
+#define UCBRF_8 (0x80) /* USCI First Stage Modulation: 8 */
+#define UCBRF_9 (0x90) /* USCI First Stage Modulation: 9 */
+#define UCBRF_10 (0xA0) /* USCI First Stage Modulation: A */
+#define UCBRF_11 (0xB0) /* USCI First Stage Modulation: B */
+#define UCBRF_12 (0xC0) /* USCI First Stage Modulation: C */
+#define UCBRF_13 (0xD0) /* USCI First Stage Modulation: D */
+#define UCBRF_14 (0xE0) /* USCI First Stage Modulation: E */
+#define UCBRF_15 (0xF0) /* USCI First Stage Modulation: F */
+
+/* UCAxSTATW Control Bits */
+#define UCLISTEN (0x0080) /* USCI Listen mode */
+#define UCFE (0x0040) /* USCI Frame Error Flag */
+#define UCOE (0x0020) /* USCI Overrun Error Flag */
+#define UCPE (0x0010) /* USCI Parity Error Flag */
+#define UCBRK (0x0008) /* USCI Break received */
+#define UCRXERR (0x0004) /* USCI RX Error Flag */
+#define UCADDR (0x0002) /* USCI Address received Flag */
+#define UCBUSY (0x0001) /* USCI Busy Flag */
+#define UCIDLE (0x0002) /* USCI Idle line detected Flag */
+
+/* UCBxSTATW I2C Control Bits */
+#define UCBCNT7 (0x8000) /* USCI Byte Counter Bit 7 */
+#define UCBCNT6 (0x4000) /* USCI Byte Counter Bit 6 */
+#define UCBCNT5 (0x2000) /* USCI Byte Counter Bit 5 */
+#define UCBCNT4 (0x1000) /* USCI Byte Counter Bit 4 */
+#define UCBCNT3 (0x0800) /* USCI Byte Counter Bit 3 */
+#define UCBCNT2 (0x0400) /* USCI Byte Counter Bit 2 */
+#define UCBCNT1 (0x0200) /* USCI Byte Counter Bit 1 */
+#define UCBCNT0 (0x0100) /* USCI Byte Counter Bit 0 */
+#define UCSCLLOW (0x0040) /* SCL low */
+#define UCGC (0x0020) /* General Call address received Flag */
+#define UCBBUSY (0x0010) /* Bus Busy Flag */
+
+/* UCBxTBCNT I2C Control Bits */
+#define UCTBCNT7 (0x0080) /* USCI Byte Counter Bit 7 */
+#define UCTBCNT6 (0x0040) /* USCI Byte Counter Bit 6 */
+#define UCTBCNT5 (0x0020) /* USCI Byte Counter Bit 5 */
+#define UCTBCNT4 (0x0010) /* USCI Byte Counter Bit 4 */
+#define UCTBCNT3 (0x0008) /* USCI Byte Counter Bit 3 */
+#define UCTBCNT2 (0x0004) /* USCI Byte Counter Bit 2 */
+#define UCTBCNT1 (0x0002) /* USCI Byte Counter Bit 1 */
+#define UCTBCNT0 (0x0001) /* USCI Byte Counter Bit 0 */
+
+/* UCAxIRCTL Control Bits */
+#define UCIRRXFL5 (0x8000) /* IRDA Receive Filter Length 5 */
+#define UCIRRXFL4 (0x4000) /* IRDA Receive Filter Length 4 */
+#define UCIRRXFL3 (0x2000) /* IRDA Receive Filter Length 3 */
+#define UCIRRXFL2 (0x1000) /* IRDA Receive Filter Length 2 */
+#define UCIRRXFL1 (0x0800) /* IRDA Receive Filter Length 1 */
+#define UCIRRXFL0 (0x0400) /* IRDA Receive Filter Length 0 */
+#define UCIRRXPL (0x0200) /* IRDA Receive Input Polarity */
+#define UCIRRXFE (0x0100) /* IRDA Receive Filter enable */
+#define UCIRTXPL5 (0x0080) /* IRDA Transmit Pulse Length 5 */
+#define UCIRTXPL4 (0x0040) /* IRDA Transmit Pulse Length 4 */
+#define UCIRTXPL3 (0x0020) /* IRDA Transmit Pulse Length 3 */
+#define UCIRTXPL2 (0x0010) /* IRDA Transmit Pulse Length 2 */
+#define UCIRTXPL1 (0x0008) /* IRDA Transmit Pulse Length 1 */
+#define UCIRTXPL0 (0x0004) /* IRDA Transmit Pulse Length 0 */
+#define UCIRTXCLK (0x0002) /* IRDA Transmit Pulse Clock Select */
+#define UCIREN (0x0001) /* IRDA Encoder/Decoder enable */
+
+/* UCAxIRCTL Control Bits */
+#define UCIRTXPL5_L (0x0080) /* IRDA Transmit Pulse Length 5 */
+#define UCIRTXPL4_L (0x0040) /* IRDA Transmit Pulse Length 4 */
+#define UCIRTXPL3_L (0x0020) /* IRDA Transmit Pulse Length 3 */
+#define UCIRTXPL2_L (0x0010) /* IRDA Transmit Pulse Length 2 */
+#define UCIRTXPL1_L (0x0008) /* IRDA Transmit Pulse Length 1 */
+#define UCIRTXPL0_L (0x0004) /* IRDA Transmit Pulse Length 0 */
+#define UCIRTXCLK_L (0x0002) /* IRDA Transmit Pulse Clock Select */
+#define UCIREN_L (0x0001) /* IRDA Encoder/Decoder enable */
+
+/* UCAxIRCTL Control Bits */
+#define UCIRRXFL5_H (0x0080) /* IRDA Receive Filter Length 5 */
+#define UCIRRXFL4_H (0x0040) /* IRDA Receive Filter Length 4 */
+#define UCIRRXFL3_H (0x0020) /* IRDA Receive Filter Length 3 */
+#define UCIRRXFL2_H (0x0010) /* IRDA Receive Filter Length 2 */
+#define UCIRRXFL1_H (0x0008) /* IRDA Receive Filter Length 1 */
+#define UCIRRXFL0_H (0x0004) /* IRDA Receive Filter Length 0 */
+#define UCIRRXPL_H (0x0002) /* IRDA Receive Input Polarity */
+#define UCIRRXFE_H (0x0001) /* IRDA Receive Filter enable */
+
+/* UCAxABCTL Control Bits */
+//#define res (0x80) /* reserved */
+//#define res (0x40) /* reserved */
+#define UCDELIM1 (0x20) /* Break Sync Delimiter 1 */
+#define UCDELIM0 (0x10) /* Break Sync Delimiter 0 */
+#define UCSTOE (0x08) /* Sync-Field Timeout error */
+#define UCBTOE (0x04) /* Break Timeout error */
+//#define res (0x02) /* reserved */
+#define UCABDEN (0x01) /* Auto Baud Rate detect enable */
+
+/* UCBxI2COA0 Control Bits */
+#define UCGCEN (0x8000) /* I2C General Call enable */
+#define UCOAEN (0x0400) /* I2C Own Address enable */
+#define UCOA9 (0x0200) /* I2C Own Address Bit 9 */
+#define UCOA8 (0x0100) /* I2C Own Address Bit 8 */
+#define UCOA7 (0x0080) /* I2C Own Address Bit 7 */
+#define UCOA6 (0x0040) /* I2C Own Address Bit 6 */
+#define UCOA5 (0x0020) /* I2C Own Address Bit 5 */
+#define UCOA4 (0x0010) /* I2C Own Address Bit 4 */
+#define UCOA3 (0x0008) /* I2C Own Address Bit 3 */
+#define UCOA2 (0x0004) /* I2C Own Address Bit 2 */
+#define UCOA1 (0x0002) /* I2C Own Address Bit 1 */
+#define UCOA0 (0x0001) /* I2C Own Address Bit 0 */
+
+/* UCBxI2COA0 Control Bits */
+#define UCOA7_L (0x0080) /* I2C Own Address Bit 7 */
+#define UCOA6_L (0x0040) /* I2C Own Address Bit 6 */
+#define UCOA5_L (0x0020) /* I2C Own Address Bit 5 */
+#define UCOA4_L (0x0010) /* I2C Own Address Bit 4 */
+#define UCOA3_L (0x0008) /* I2C Own Address Bit 3 */
+#define UCOA2_L (0x0004) /* I2C Own Address Bit 2 */
+#define UCOA1_L (0x0002) /* I2C Own Address Bit 1 */
+#define UCOA0_L (0x0001) /* I2C Own Address Bit 0 */
+
+/* UCBxI2COA0 Control Bits */
+#define UCGCEN_H (0x0080) /* I2C General Call enable */
+#define UCOAEN_H (0x0004) /* I2C Own Address enable */
+#define UCOA9_H (0x0002) /* I2C Own Address Bit 9 */
+#define UCOA8_H (0x0001) /* I2C Own Address Bit 8 */
+
+/* UCBxI2COAx Control Bits */
+#define UCOAEN (0x0400) /* I2C Own Address enable */
+#define UCOA9 (0x0200) /* I2C Own Address Bit 9 */
+#define UCOA8 (0x0100) /* I2C Own Address Bit 8 */
+#define UCOA7 (0x0080) /* I2C Own Address Bit 7 */
+#define UCOA6 (0x0040) /* I2C Own Address Bit 6 */
+#define UCOA5 (0x0020) /* I2C Own Address Bit 5 */
+#define UCOA4 (0x0010) /* I2C Own Address Bit 4 */
+#define UCOA3 (0x0008) /* I2C Own Address Bit 3 */
+#define UCOA2 (0x0004) /* I2C Own Address Bit 2 */
+#define UCOA1 (0x0002) /* I2C Own Address Bit 1 */
+#define UCOA0 (0x0001) /* I2C Own Address Bit 0 */
+
+/* UCBxI2COAx Control Bits */
+#define UCOA7_L (0x0080) /* I2C Own Address Bit 7 */
+#define UCOA6_L (0x0040) /* I2C Own Address Bit 6 */
+#define UCOA5_L (0x0020) /* I2C Own Address Bit 5 */
+#define UCOA4_L (0x0010) /* I2C Own Address Bit 4 */
+#define UCOA3_L (0x0008) /* I2C Own Address Bit 3 */
+#define UCOA2_L (0x0004) /* I2C Own Address Bit 2 */
+#define UCOA1_L (0x0002) /* I2C Own Address Bit 1 */
+#define UCOA0_L (0x0001) /* I2C Own Address Bit 0 */
+
+/* UCBxI2COAx Control Bits */
+#define UCOAEN_H (0x0004) /* I2C Own Address enable */
+#define UCOA9_H (0x0002) /* I2C Own Address Bit 9 */
+#define UCOA8_H (0x0001) /* I2C Own Address Bit 8 */
+
+/* UCBxADDRX Control Bits */
+#define UCADDRX9 (0x0200) /* I2C Receive Address Bit 9 */
+#define UCADDRX8 (0x0100) /* I2C Receive Address Bit 8 */
+#define UCADDRX7 (0x0080) /* I2C Receive Address Bit 7 */
+#define UCADDRX6 (0x0040) /* I2C Receive Address Bit 6 */
+#define UCADDRX5 (0x0020) /* I2C Receive Address Bit 5 */
+#define UCADDRX4 (0x0010) /* I2C Receive Address Bit 4 */
+#define UCADDRX3 (0x0008) /* I2C Receive Address Bit 3 */
+#define UCADDRX2 (0x0004) /* I2C Receive Address Bit 2 */
+#define UCADDRX1 (0x0002) /* I2C Receive Address Bit 1 */
+#define UCADDRX0 (0x0001) /* I2C Receive Address Bit 0 */
+
+/* UCBxADDRX Control Bits */
+#define UCADDRX7_L (0x0080) /* I2C Receive Address Bit 7 */
+#define UCADDRX6_L (0x0040) /* I2C Receive Address Bit 6 */
+#define UCADDRX5_L (0x0020) /* I2C Receive Address Bit 5 */
+#define UCADDRX4_L (0x0010) /* I2C Receive Address Bit 4 */
+#define UCADDRX3_L (0x0008) /* I2C Receive Address Bit 3 */
+#define UCADDRX2_L (0x0004) /* I2C Receive Address Bit 2 */
+#define UCADDRX1_L (0x0002) /* I2C Receive Address Bit 1 */
+#define UCADDRX0_L (0x0001) /* I2C Receive Address Bit 0 */
+
+/* UCBxADDRX Control Bits */
+#define UCADDRX9_H (0x0002) /* I2C Receive Address Bit 9 */
+#define UCADDRX8_H (0x0001) /* I2C Receive Address Bit 8 */
+
+/* UCBxADDMASK Control Bits */
+#define UCADDMASK9 (0x0200) /* I2C Address Mask Bit 9 */
+#define UCADDMASK8 (0x0100) /* I2C Address Mask Bit 8 */
+#define UCADDMASK7 (0x0080) /* I2C Address Mask Bit 7 */
+#define UCADDMASK6 (0x0040) /* I2C Address Mask Bit 6 */
+#define UCADDMASK5 (0x0020) /* I2C Address Mask Bit 5 */
+#define UCADDMASK4 (0x0010) /* I2C Address Mask Bit 4 */
+#define UCADDMASK3 (0x0008) /* I2C Address Mask Bit 3 */
+#define UCADDMASK2 (0x0004) /* I2C Address Mask Bit 2 */
+#define UCADDMASK1 (0x0002) /* I2C Address Mask Bit 1 */
+#define UCADDMASK0 (0x0001) /* I2C Address Mask Bit 0 */
+
+/* UCBxADDMASK Control Bits */
+#define UCADDMASK7_L (0x0080) /* I2C Address Mask Bit 7 */
+#define UCADDMASK6_L (0x0040) /* I2C Address Mask Bit 6 */
+#define UCADDMASK5_L (0x0020) /* I2C Address Mask Bit 5 */
+#define UCADDMASK4_L (0x0010) /* I2C Address Mask Bit 4 */
+#define UCADDMASK3_L (0x0008) /* I2C Address Mask Bit 3 */
+#define UCADDMASK2_L (0x0004) /* I2C Address Mask Bit 2 */
+#define UCADDMASK1_L (0x0002) /* I2C Address Mask Bit 1 */
+#define UCADDMASK0_L (0x0001) /* I2C Address Mask Bit 0 */
+
+/* UCBxADDMASK Control Bits */
+#define UCADDMASK9_H (0x0002) /* I2C Address Mask Bit 9 */
+#define UCADDMASK8_H (0x0001) /* I2C Address Mask Bit 8 */
+
+/* UCBxI2CSA Control Bits */
+#define UCSA9 (0x0200) /* I2C Slave Address Bit 9 */
+#define UCSA8 (0x0100) /* I2C Slave Address Bit 8 */
+#define UCSA7 (0x0080) /* I2C Slave Address Bit 7 */
+#define UCSA6 (0x0040) /* I2C Slave Address Bit 6 */
+#define UCSA5 (0x0020) /* I2C Slave Address Bit 5 */
+#define UCSA4 (0x0010) /* I2C Slave Address Bit 4 */
+#define UCSA3 (0x0008) /* I2C Slave Address Bit 3 */
+#define UCSA2 (0x0004) /* I2C Slave Address Bit 2 */
+#define UCSA1 (0x0002) /* I2C Slave Address Bit 1 */
+#define UCSA0 (0x0001) /* I2C Slave Address Bit 0 */
+
+/* UCBxI2CSA Control Bits */
+#define UCSA7_L (0x0080) /* I2C Slave Address Bit 7 */
+#define UCSA6_L (0x0040) /* I2C Slave Address Bit 6 */
+#define UCSA5_L (0x0020) /* I2C Slave Address Bit 5 */
+#define UCSA4_L (0x0010) /* I2C Slave Address Bit 4 */
+#define UCSA3_L (0x0008) /* I2C Slave Address Bit 3 */
+#define UCSA2_L (0x0004) /* I2C Slave Address Bit 2 */
+#define UCSA1_L (0x0002) /* I2C Slave Address Bit 1 */
+#define UCSA0_L (0x0001) /* I2C Slave Address Bit 0 */
+
+/* UCBxI2CSA Control Bits */
+#define UCSA9_H (0x0002) /* I2C Slave Address Bit 9 */
+#define UCSA8_H (0x0001) /* I2C Slave Address Bit 8 */
+
+/* UCAxIE UART Control Bits */
+#define UCTXCPTIE (0x0008) /* UART Transmit Complete Interrupt Enable */
+#define UCSTTIE (0x0004) /* UART Start Bit Interrupt Enalble */
+#define UCTXIE (0x0002) /* UART Transmit Interrupt Enable */
+#define UCRXIE (0x0001) /* UART Receive Interrupt Enable */
+
+/* UCAxIE/UCBxIE SPI Control Bits */
+
+/* UCBxIE I2C Control Bits */
+#define UCBIT9IE (0x4000) /* I2C Bit 9 Position Interrupt Enable 3 */
+#define UCTXIE3 (0x2000) /* I2C Transmit Interrupt Enable 3 */
+#define UCRXIE3 (0x1000) /* I2C Receive Interrupt Enable 3 */
+#define UCTXIE2 (0x0800) /* I2C Transmit Interrupt Enable 2 */
+#define UCRXIE2 (0x0400) /* I2C Receive Interrupt Enable 2 */
+#define UCTXIE1 (0x0200) /* I2C Transmit Interrupt Enable 1 */
+#define UCRXIE1 (0x0100) /* I2C Receive Interrupt Enable 1 */
+#define UCCLTOIE (0x0080) /* I2C Clock Low Timeout interrupt enable */
+#define UCBCNTIE (0x0040) /* I2C Automatic stop assertion interrupt enable */
+#define UCNACKIE (0x0020) /* I2C NACK Condition interrupt enable */
+#define UCALIE (0x0010) /* I2C Arbitration Lost interrupt enable */
+#define UCSTPIE (0x0008) /* I2C STOP Condition interrupt enable */
+#define UCSTTIE (0x0004) /* I2C START Condition interrupt enable */
+#define UCTXIE0 (0x0002) /* I2C Transmit Interrupt Enable 0 */
+#define UCRXIE0 (0x0001) /* I2C Receive Interrupt Enable 0 */
+
+/* UCAxIFG UART Control Bits */
+#define UCTXCPTIFG (0x0008) /* UART Transmit Complete Interrupt Flag */
+#define UCSTTIFG (0x0004) /* UART Start Bit Interrupt Flag */
+#define UCTXIFG (0x0002) /* UART Transmit Interrupt Flag */
+#define UCRXIFG (0x0001) /* UART Receive Interrupt Flag */
+
+/* UCAxIFG/UCBxIFG SPI Control Bits */
+#define UCTXIFG (0x0002) /* SPI Transmit Interrupt Flag */
+#define UCRXIFG (0x0001) /* SPI Receive Interrupt Flag */
+
+/* UCBxIFG Control Bits */
+#define UCBIT9IFG (0x4000) /* I2C Bit 9 Possition Interrupt Flag 3 */
+#define UCTXIFG3 (0x2000) /* I2C Transmit Interrupt Flag 3 */
+#define UCRXIFG3 (0x1000) /* I2C Receive Interrupt Flag 3 */
+#define UCTXIFG2 (0x0800) /* I2C Transmit Interrupt Flag 2 */
+#define UCRXIFG2 (0x0400) /* I2C Receive Interrupt Flag 2 */
+#define UCTXIFG1 (0x0200) /* I2C Transmit Interrupt Flag 1 */
+#define UCRXIFG1 (0x0100) /* I2C Receive Interrupt Flag 1 */
+#define UCCLTOIFG (0x0080) /* I2C Clock low Timeout interrupt Flag */
+#define UCBCNTIFG (0x0040) /* I2C Byte counter interrupt flag */
+#define UCNACKIFG (0x0020) /* I2C NACK Condition interrupt Flag */
+#define UCALIFG (0x0010) /* I2C Arbitration Lost interrupt Flag */
+#define UCSTPIFG (0x0008) /* I2C STOP Condition interrupt Flag */
+#define UCSTTIFG (0x0004) /* I2C START Condition interrupt Flag */
+#define UCTXIFG0 (0x0002) /* I2C Transmit Interrupt Flag 0 */
+#define UCRXIFG0 (0x0001) /* I2C Receive Interrupt Flag 0 */
+
+/* USCI Interrupt Vector UART Definitions */
+#define USCI_NONE (0x0000) /* No Interrupt pending */
+#define USCI_UART_UCRXIFG (0x0002) /* Interrupt Vector: UCRXIFG */
+#define USCI_UART_UCTXIFG (0x0004) /* Interrupt Vector: UCTXIFG */
+#define USCI_UART_UCSTTIFG (0x0006) /* Interrupt Vector: UCSTTIFG */
+#define USCI_UART_UCTXCPTIFG (0x0008) /* Interrupt Vector: UCTXCPTIFG */
+
+/* USCI Interrupt Vector SPI Definitions */
+#define USCI_SPI_UCRXIFG (0x0002) /* Interrupt Vector: UCRXIFG */
+#define USCI_SPI_UCTXIFG (0x0004) /* Interrupt Vector: UCTXIFG */
+
+/* USCI Interrupt Vector I2C Definitions */
+#define USCI_I2C_UCALIFG (0x0002) /* Interrupt Vector: I2C Mode: UCALIFG */
+#define USCI_I2C_UCNACKIFG (0x0004) /* Interrupt Vector: I2C Mode: UCNACKIFG */
+#define USCI_I2C_UCSTTIFG (0x0006) /* Interrupt Vector: I2C Mode: UCSTTIFG*/
+#define USCI_I2C_UCSTPIFG (0x0008) /* Interrupt Vector: I2C Mode: UCSTPIFG*/
+#define USCI_I2C_UCRXIFG3 (0x000A) /* Interrupt Vector: I2C Mode: UCRXIFG3 */
+#define USCI_I2C_UCTXIFG3 (0x000C) /* Interrupt Vector: I2C Mode: UCTXIFG3 */
+#define USCI_I2C_UCRXIFG2 (0x000E) /* Interrupt Vector: I2C Mode: UCRXIFG2 */
+#define USCI_I2C_UCTXIFG2 (0x0010) /* Interrupt Vector: I2C Mode: UCTXIFG2 */
+#define USCI_I2C_UCRXIFG1 (0x0012) /* Interrupt Vector: I2C Mode: UCRXIFG1 */
+#define USCI_I2C_UCTXIFG1 (0x0014) /* Interrupt Vector: I2C Mode: UCTXIFG1 */
+#define USCI_I2C_UCRXIFG0 (0x0016) /* Interrupt Vector: I2C Mode: UCRXIFG0 */
+#define USCI_I2C_UCTXIFG0 (0x0018) /* Interrupt Vector: I2C Mode: UCTXIFG0 */
+#define USCI_I2C_UCBCNTIFG (0x001A) /* Interrupt Vector: I2C Mode: UCBCNTIFG */
+#define USCI_I2C_UCCLTOIFG (0x001C) /* Interrupt Vector: I2C Mode: UCCLTOIFG */
+#define USCI_I2C_UCBIT9IFG (0x001E) /* Interrupt Vector: I2C Mode: UCBIT9IFG */
+
+/************************************************************
+* WATCHDOG TIMER A
+************************************************************/
+#define __MSP430_HAS_WDT_A__ /* Definition to show that Module is available */
+#define __MSP430_BASEADDRESS_WDT_A__ 0x0150
+#define WDT_A_BASE __MSP430_BASEADDRESS_WDT_A__
+
+sfr_w(WDTCTL); /* Watchdog Timer Control */
+sfr_b(WDTCTL_L); /* Watchdog Timer Control */
+sfr_b(WDTCTL_H); /* Watchdog Timer Control */
+/* The bit names have been prefixed with "WDT" */
+/* WDTCTL Control Bits */
+#define WDTIS0 (0x0001) /* WDT - Timer Interval Select 0 */
+#define WDTIS1 (0x0002) /* WDT - Timer Interval Select 1 */
+#define WDTIS2 (0x0004) /* WDT - Timer Interval Select 2 */
+#define WDTCNTCL (0x0008) /* WDT - Timer Clear */
+#define WDTTMSEL (0x0010) /* WDT - Timer Mode Select */
+#define WDTSSEL0 (0x0020) /* WDT - Timer Clock Source Select 0 */
+#define WDTSSEL1 (0x0040) /* WDT - Timer Clock Source Select 1 */
+#define WDTHOLD (0x0080) /* WDT - Timer hold */
+
+/* WDTCTL Control Bits */
+#define WDTIS0_L (0x0001) /* WDT - Timer Interval Select 0 */
+#define WDTIS1_L (0x0002) /* WDT - Timer Interval Select 1 */
+#define WDTIS2_L (0x0004) /* WDT - Timer Interval Select 2 */
+#define WDTCNTCL_L (0x0008) /* WDT - Timer Clear */
+#define WDTTMSEL_L (0x0010) /* WDT - Timer Mode Select */
+#define WDTSSEL0_L (0x0020) /* WDT - Timer Clock Source Select 0 */
+#define WDTSSEL1_L (0x0040) /* WDT - Timer Clock Source Select 1 */
+#define WDTHOLD_L (0x0080) /* WDT - Timer hold */
+
+#define WDTPW (0x5A00)
+
+#define WDTIS_0 (0x0000) /* WDT - Timer Interval Select: /2G */
+#define WDTIS_1 (0x0001) /* WDT - Timer Interval Select: /128M */
+#define WDTIS_2 (0x0002) /* WDT - Timer Interval Select: /8192k */
+#define WDTIS_3 (0x0003) /* WDT - Timer Interval Select: /512k */
+#define WDTIS_4 (0x0004) /* WDT - Timer Interval Select: /32k */
+#define WDTIS_5 (0x0005) /* WDT - Timer Interval Select: /8192 */
+#define WDTIS_6 (0x0006) /* WDT - Timer Interval Select: /512 */
+#define WDTIS_7 (0x0007) /* WDT - Timer Interval Select: /64 */
+#define WDTIS__2G (0x0000) /* WDT - Timer Interval Select: /2G */
+#define WDTIS__128M (0x0001) /* WDT - Timer Interval Select: /128M */
+#define WDTIS__8192K (0x0002) /* WDT - Timer Interval Select: /8192k */
+#define WDTIS__512K (0x0003) /* WDT - Timer Interval Select: /512k */
+#define WDTIS__32K (0x0004) /* WDT - Timer Interval Select: /32k */
+#define WDTIS__8192 (0x0005) /* WDT - Timer Interval Select: /8192 */
+#define WDTIS__512 (0x0006) /* WDT - Timer Interval Select: /512 */
+#define WDTIS__64 (0x0007) /* WDT - Timer Interval Select: /64 */
+
+#define WDTSSEL_0 (0x0000) /* WDT - Timer Clock Source Select: SMCLK */
+#define WDTSSEL_1 (0x0020) /* WDT - Timer Clock Source Select: ACLK */
+#define WDTSSEL_2 (0x0040) /* WDT - Timer Clock Source Select: VLO_CLK */
+#define WDTSSEL_3 (0x0060) /* WDT - Timer Clock Source Select: reserved */
+#define WDTSSEL__SMCLK (0x0000) /* WDT - Timer Clock Source Select: SMCLK */
+#define WDTSSEL__ACLK (0x0020) /* WDT - Timer Clock Source Select: ACLK */
+#define WDTSSEL__VLO (0x0040) /* WDT - Timer Clock Source Select: VLO_CLK */
+
+/* WDT-interval times [1ms] coded with Bits 0-2 */
+/* WDT is clocked by fSMCLK (assumed 1MHz) */
+#define WDT_MDLY_32 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2) /* 32ms interval (default) */
+#define WDT_MDLY_8 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */
+#define WDT_MDLY_0_5 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */
+#define WDT_MDLY_0_064 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */
+/* WDT is clocked by fACLK (assumed 32KHz) */
+#define WDT_ADLY_1000 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0) /* 1000ms " */
+#define WDT_ADLY_250 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS0) /* 250ms " */
+#define WDT_ADLY_16 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1) /* 16ms " */
+#define WDT_ADLY_1_9 (WDTPW+WDTTMSEL+WDTCNTCL+WDTIS2+WDTSSEL0+WDTIS1+WDTIS0) /* 1.9ms " */
+/* Watchdog mode -> reset after expired time */
+/* WDT is clocked by fSMCLK (assumed 1MHz) */
+#define WDT_MRST_32 (WDTPW+WDTCNTCL+WDTIS2) /* 32ms interval (default) */
+#define WDT_MRST_8 (WDTPW+WDTCNTCL+WDTIS2+WDTIS0) /* 8ms " */
+#define WDT_MRST_0_5 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1) /* 0.5ms " */
+#define WDT_MRST_0_064 (WDTPW+WDTCNTCL+WDTIS2+WDTIS1+WDTIS0) /* 0.064ms " */
+/* WDT is clocked by fACLK (assumed 32KHz) */
+#define WDT_ARST_1000 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2) /* 1000ms " */
+#define WDT_ARST_250 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS0) /* 250ms " */
+#define WDT_ARST_16 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1) /* 16ms " */
+#define WDT_ARST_1_9 (WDTPW+WDTCNTCL+WDTSSEL0+WDTIS2+WDTIS1+WDTIS0) /* 1.9ms " */
+
+
+/************************************************************
+* TLV Descriptors
+************************************************************/
+#define __MSP430_HAS_TLV__ /* Definition to show that Module is available */
+#define TLV_BASE __MSP430_BASEADDRESS_TLV__
+
+#define TLV_CRC_LENGTH (0x1A01) /* CRC length of the TLV structure */
+#define TLV_CRC_VALUE (0x1A02) /* CRC value of the TLV structure */
+#define TLV_START (0x1A08) /* Start Address of the TLV structure */
+#define TLV_END (0x1AFF) /* End Address of the TLV structure */
+
+#define TLV_LDTAG (0x01) /* Legacy descriptor (1xx, 2xx, 4xx families) */
+#define TLV_PDTAG (0x02) /* Peripheral discovery descriptor */
+#define TLV_Reserved3 (0x03) /* Future usage */
+#define TLV_Reserved4 (0x04) /* Future usage */
+#define TLV_BLANK (0x05) /* Blank descriptor */
+#define TLV_Reserved6 (0x06) /* Future usage */
+#define TLV_Reserved7 (0x07) /* Serial Number */
+#define TLV_DIERECORD (0x08) /* Die Record */
+#define TLV_ADCCAL (0x11) /* ADC12 calibration */
+#define TLV_ADC12CAL (0x11) /* ADC12 calibration */
+#define TLV_ADC10CAL (0x13) /* ADC10 calibration */
+#define TLV_REFCAL (0x12) /* REF calibration */
+#define TLV_TAGEXT (0xFE) /* Tag extender */
+#define TLV_TAGEND (0xFF) // Tag End of Table
+
+/************************************************************
+* Interrupt Vectors (offset from 0xFF80 + 0x10 for Password)
+************************************************************/
+
+
+#define AES256_VECTOR (28) /* 0xFFC6 AES256 */
+#define RTC_VECTOR (29) /* 0xFFC8 RTC */
+#define LCD_C_VECTOR (30) /* 0xFFCA LCD C */
+#define PORT4_VECTOR (31) /* 0xFFCC Port 4 */
+#define PORT3_VECTOR (32) /* 0xFFCE Port 3 */
+#define TIMER3_A1_VECTOR (33) /* 0xFFD0 Timer3_A2 CC1, TA */
+#define TIMER3_A0_VECTOR (34) /* 0xFFD2 Timer3_A2 CC0 */
+#define PORT2_VECTOR (35) /* 0xFFD4 Port 2 */
+#define TIMER2_A1_VECTOR (36) /* 0xFFD6 Timer2_A3 CC1, TA */
+#define TIMER2_A0_VECTOR (37) /* 0xFFD8 Timer2_A3 CC0 */
+#define PORT1_VECTOR (38) /* 0xFFDA Port 1 */
+#define TIMER1_A1_VECTOR (39) /* 0xFFDC Timer1_A3 CC1-2, TA1 */
+#define TIMER1_A0_VECTOR (40) /* 0xFFDE Timer1_A3 CC0 */
+#define DMA_VECTOR (41) /* 0xFFE0 DMA */
+#define USCI_B1_VECTOR (42) /* 0xFFE2 USCI B1 Receive/Transmit */
+#define USCI_A1_VECTOR (43) /* 0xFFE4 USCI A1 Receive/Transmit */
+#define TIMER0_A1_VECTOR (44) /* 0xFFE6 Timer0_A5 CC1-4, TA */
+#define TIMER0_A0_VECTOR (45) /* 0xFFE8 Timer0_A5 CC0 */
+#define ADC12_VECTOR (46) /* 0xFFEA ADC */
+#define USCI_B0_VECTOR (47) /* 0xFFEC USCI B0 Receive/Transmit */
+#define USCI_A0_VECTOR (48) /* 0xFFEE USCI A0 Receive/Transmit */
+#define ESCAN_IF_VECTOR (49) /* 0xFFF0 Extended Scan IF */
+#define WDT_VECTOR (50) /* 0xFFF2 Watchdog Timer */
+#define TIMER0_B1_VECTOR (51) /* 0xFFF4 Timer0_B3 CC1-2, TB */
+#define TIMER0_B0_VECTOR (52) /* 0xFFF6 Timer0_B3 CC0 */
+#define COMP_E_VECTOR (53) /* 0xFFF8 Comparator E */
+#define UNMI_VECTOR (54) /* 0xFFFA User Non-maskable */
+#define SYSNMI_VECTOR (55) /* 0xFFFC System Non-maskable */
+#define RESET_VECTOR ("reset") /* 0xFFFE Reset [Highest Priority] */
+
+/************************************************************
+* End of Modules
+************************************************************/
+
+#ifdef __cplusplus
+}
+#endif /* extern "C" */
+
+#endif /* #ifndef __MSP430FR6989 */
+
diff --git a/os/common/ext/TivaWare/inc/asmdefs.h b/os/common/ext/TivaWare/inc/asmdefs.h
new file mode 100644
index 0000000..062cb09
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/asmdefs.h
@@ -0,0 +1,227 @@
+//*****************************************************************************
+//
+// asmdefs.h - Macros to allow assembly code be portable among toolchains.
+//
+// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __ASMDEFS_H__
+#define __ASMDEFS_H__
+
+//*****************************************************************************
+//
+// The defines required for code_red.
+//
+//*****************************************************************************
+#ifdef codered
+
+//
+// The assembly code preamble required to put the assembler into the correct
+// configuration.
+//
+ .syntax unified
+ .thumb
+
+//
+// Section headers.
+//
+#define __LIBRARY__ @
+#define __TEXT__ .text
+#define __DATA__ .data
+#define __BSS__ .bss
+#define __TEXT_NOROOT__ .text
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__ .balign 4
+#define __END__ .end
+#define __EXPORT__ .globl
+#define __IMPORT__ .extern
+#define __LABEL__ :
+#define __STR__ .ascii
+#define __THUMB_LABEL__ .thumb_func
+#define __WORD__ .word
+#define __INLINE_DATA__
+
+#endif // codered
+
+//*****************************************************************************
+//
+// The defines required for EW-ARM.
+//
+//*****************************************************************************
+#ifdef ewarm
+
+//
+// Section headers.
+//
+#define __LIBRARY__ module
+#define __TEXT__ rseg CODE:CODE(2)
+#define __DATA__ rseg DATA:DATA(2)
+#define __BSS__ rseg DATA:DATA(2)
+#define __TEXT_NOROOT__ rseg CODE:CODE:NOROOT(2)
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__ alignrom 2
+#define __END__ end
+#define __EXPORT__ export
+#define __IMPORT__ import
+#define __LABEL__
+#define __STR__ dcb
+#define __THUMB_LABEL__ thumb
+#define __WORD__ dcd
+#define __INLINE_DATA__ data
+
+#endif // ewarm
+
+//*****************************************************************************
+//
+// The defines required for GCC.
+//
+//*****************************************************************************
+#if defined(gcc)
+
+//
+// The assembly code preamble required to put the assembler into the correct
+// configuration.
+//
+ .syntax unified
+ .thumb
+
+//
+// Section headers.
+//
+#define __LIBRARY__ @
+#define __TEXT__ .text
+#define __DATA__ .data
+#define __BSS__ .bss
+#define __TEXT_NOROOT__ .text
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__ .balign 4
+#define __END__ .end
+#define __EXPORT__ .globl
+#define __IMPORT__ .extern
+#define __LABEL__ :
+#define __STR__ .ascii
+#define __THUMB_LABEL__ .thumb_func
+#define __WORD__ .word
+#define __INLINE_DATA__
+
+#endif // gcc
+
+//*****************************************************************************
+//
+// The defines required for RV-MDK.
+//
+//*****************************************************************************
+#ifdef rvmdk
+
+//
+// The assembly code preamble required to put the assembler into the correct
+// configuration.
+//
+ thumb
+ require8
+ preserve8
+
+//
+// Section headers.
+//
+#define __LIBRARY__ ;
+#define __TEXT__ area ||.text||, code, readonly, align=2
+#define __DATA__ area ||.data||, data, align=2
+#define __BSS__ area ||.bss||, noinit, align=2
+#define __TEXT_NOROOT__ area ||.text||, code, readonly, align=2
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__ align 4
+#define __END__ end
+#define __EXPORT__ export
+#define __IMPORT__ import
+#define __LABEL__
+#define __STR__ dcb
+#define __THUMB_LABEL__
+#define __WORD__ dcd
+#define __INLINE_DATA__
+
+#endif // rvmdk
+
+//*****************************************************************************
+//
+// The defines required for Sourcery G++.
+//
+//*****************************************************************************
+#if defined(sourcerygxx)
+
+//
+// The assembly code preamble required to put the assembler into the correct
+// configuration.
+//
+ .syntax unified
+ .thumb
+
+//
+// Section headers.
+//
+#define __LIBRARY__ @
+#define __TEXT__ .text
+#define __DATA__ .data
+#define __BSS__ .bss
+#define __TEXT_NOROOT__ .text
+
+//
+// Assembler nmenonics.
+//
+#define __ALIGN__ .balign 4
+#define __END__ .end
+#define __EXPORT__ .globl
+#define __IMPORT__ .extern
+#define __LABEL__ :
+#define __STR__ .ascii
+#define __THUMB_LABEL__ .thumb_func
+#define __WORD__ .word
+#define __INLINE_DATA__
+
+#endif // sourcerygxx
+
+#endif // __ASMDEF_H__
diff --git a/os/common/ext/TivaWare/inc/hw_adc.h b/os/common/ext/TivaWare/inc/hw_adc.h
new file mode 100644
index 0000000..27a384f
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_adc.h
@@ -0,0 +1,1306 @@
+//*****************************************************************************
+//
+// hw_adc.h - Macros used when accessing the ADC hardware.
+//
+// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_ADC_H__
+#define __HW_ADC_H__
+
+//*****************************************************************************
+//
+// The following are defines for the ADC register offsets.
+//
+//*****************************************************************************
+#define ADC_O_ACTSS 0x00000000 // ADC Active Sample Sequencer
+#define ADC_O_RIS 0x00000004 // ADC Raw Interrupt Status
+#define ADC_O_IM 0x00000008 // ADC Interrupt Mask
+#define ADC_O_ISC 0x0000000C // ADC Interrupt Status and Clear
+#define ADC_O_OSTAT 0x00000010 // ADC Overflow Status
+#define ADC_O_EMUX 0x00000014 // ADC Event Multiplexer Select
+#define ADC_O_USTAT 0x00000018 // ADC Underflow Status
+#define ADC_O_TSSEL 0x0000001C // ADC Trigger Source Select
+#define ADC_O_SSPRI 0x00000020 // ADC Sample Sequencer Priority
+#define ADC_O_SPC 0x00000024 // ADC Sample Phase Control
+#define ADC_O_PSSI 0x00000028 // ADC Processor Sample Sequence
+ // Initiate
+#define ADC_O_SAC 0x00000030 // ADC Sample Averaging Control
+#define ADC_O_DCISC 0x00000034 // ADC Digital Comparator Interrupt
+ // Status and Clear
+#define ADC_O_CTL 0x00000038 // ADC Control
+#define ADC_O_SSMUX0 0x00000040 // ADC Sample Sequence Input
+ // Multiplexer Select 0
+#define ADC_O_SSCTL0 0x00000044 // ADC Sample Sequence Control 0
+#define ADC_O_SSFIFO0 0x00000048 // ADC Sample Sequence Result FIFO
+ // 0
+#define ADC_O_SSFSTAT0 0x0000004C // ADC Sample Sequence FIFO 0
+ // Status
+#define ADC_O_SSOP0 0x00000050 // ADC Sample Sequence 0 Operation
+#define ADC_O_SSDC0 0x00000054 // ADC Sample Sequence 0 Digital
+ // Comparator Select
+#define ADC_O_SSEMUX0 0x00000058 // ADC Sample Sequence Extended
+ // Input Multiplexer Select 0
+#define ADC_O_SSTSH0 0x0000005C // ADC Sample Sequence 0 Sample and
+ // Hold Time
+#define ADC_O_SSMUX1 0x00000060 // ADC Sample Sequence Input
+ // Multiplexer Select 1
+#define ADC_O_SSCTL1 0x00000064 // ADC Sample Sequence Control 1
+#define ADC_O_SSFIFO1 0x00000068 // ADC Sample Sequence Result FIFO
+ // 1
+#define ADC_O_SSFSTAT1 0x0000006C // ADC Sample Sequence FIFO 1
+ // Status
+#define ADC_O_SSOP1 0x00000070 // ADC Sample Sequence 1 Operation
+#define ADC_O_SSDC1 0x00000074 // ADC Sample Sequence 1 Digital
+ // Comparator Select
+#define ADC_O_SSEMUX1 0x00000078 // ADC Sample Sequence Extended
+ // Input Multiplexer Select 1
+#define ADC_O_SSTSH1 0x0000007C // ADC Sample Sequence 1 Sample and
+ // Hold Time
+#define ADC_O_SSMUX2 0x00000080 // ADC Sample Sequence Input
+ // Multiplexer Select 2
+#define ADC_O_SSCTL2 0x00000084 // ADC Sample Sequence Control 2
+#define ADC_O_SSFIFO2 0x00000088 // ADC Sample Sequence Result FIFO
+ // 2
+#define ADC_O_SSFSTAT2 0x0000008C // ADC Sample Sequence FIFO 2
+ // Status
+#define ADC_O_SSOP2 0x00000090 // ADC Sample Sequence 2 Operation
+#define ADC_O_SSDC2 0x00000094 // ADC Sample Sequence 2 Digital
+ // Comparator Select
+#define ADC_O_SSEMUX2 0x00000098 // ADC Sample Sequence Extended
+ // Input Multiplexer Select 2
+#define ADC_O_SSTSH2 0x0000009C // ADC Sample Sequence 2 Sample and
+ // Hold Time
+#define ADC_O_SSMUX3 0x000000A0 // ADC Sample Sequence Input
+ // Multiplexer Select 3
+#define ADC_O_SSCTL3 0x000000A4 // ADC Sample Sequence Control 3
+#define ADC_O_SSFIFO3 0x000000A8 // ADC Sample Sequence Result FIFO
+ // 3
+#define ADC_O_SSFSTAT3 0x000000AC // ADC Sample Sequence FIFO 3
+ // Status
+#define ADC_O_SSOP3 0x000000B0 // ADC Sample Sequence 3 Operation
+#define ADC_O_SSDC3 0x000000B4 // ADC Sample Sequence 3 Digital
+ // Comparator Select
+#define ADC_O_SSEMUX3 0x000000B8 // ADC Sample Sequence Extended
+ // Input Multiplexer Select 3
+#define ADC_O_SSTSH3 0x000000BC // ADC Sample Sequence 3 Sample and
+ // Hold Time
+#define ADC_O_DCRIC 0x00000D00 // ADC Digital Comparator Reset
+ // Initial Conditions
+#define ADC_O_DCCTL0 0x00000E00 // ADC Digital Comparator Control 0
+#define ADC_O_DCCTL1 0x00000E04 // ADC Digital Comparator Control 1
+#define ADC_O_DCCTL2 0x00000E08 // ADC Digital Comparator Control 2
+#define ADC_O_DCCTL3 0x00000E0C // ADC Digital Comparator Control 3
+#define ADC_O_DCCTL4 0x00000E10 // ADC Digital Comparator Control 4
+#define ADC_O_DCCTL5 0x00000E14 // ADC Digital Comparator Control 5
+#define ADC_O_DCCTL6 0x00000E18 // ADC Digital Comparator Control 6
+#define ADC_O_DCCTL7 0x00000E1C // ADC Digital Comparator Control 7
+#define ADC_O_DCCMP0 0x00000E40 // ADC Digital Comparator Range 0
+#define ADC_O_DCCMP1 0x00000E44 // ADC Digital Comparator Range 1
+#define ADC_O_DCCMP2 0x00000E48 // ADC Digital Comparator Range 2
+#define ADC_O_DCCMP3 0x00000E4C // ADC Digital Comparator Range 3
+#define ADC_O_DCCMP4 0x00000E50 // ADC Digital Comparator Range 4
+#define ADC_O_DCCMP5 0x00000E54 // ADC Digital Comparator Range 5
+#define ADC_O_DCCMP6 0x00000E58 // ADC Digital Comparator Range 6
+#define ADC_O_DCCMP7 0x00000E5C // ADC Digital Comparator Range 7
+#define ADC_O_PP 0x00000FC0 // ADC Peripheral Properties
+#define ADC_O_PC 0x00000FC4 // ADC Peripheral Configuration
+#define ADC_O_CC 0x00000FC8 // ADC Clock Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_ACTSS register.
+//
+//*****************************************************************************
+#define ADC_ACTSS_BUSY 0x00010000 // ADC Busy
+#define ADC_ACTSS_ADEN3 0x00000800 // ADC SS3 DMA Enable
+#define ADC_ACTSS_ADEN2 0x00000400 // ADC SS2 DMA Enable
+#define ADC_ACTSS_ADEN1 0x00000200 // ADC SS1 DMA Enable
+#define ADC_ACTSS_ADEN0 0x00000100 // ADC SS1 DMA Enable
+#define ADC_ACTSS_ASEN3 0x00000008 // ADC SS3 Enable
+#define ADC_ACTSS_ASEN2 0x00000004 // ADC SS2 Enable
+#define ADC_ACTSS_ASEN1 0x00000002 // ADC SS1 Enable
+#define ADC_ACTSS_ASEN0 0x00000001 // ADC SS0 Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_RIS register.
+//
+//*****************************************************************************
+#define ADC_RIS_INRDC 0x00010000 // Digital Comparator Raw Interrupt
+ // Status
+#define ADC_RIS_DMAINR3 0x00000800 // SS3 DMA Raw Interrupt Status
+#define ADC_RIS_DMAINR2 0x00000400 // SS2 DMA Raw Interrupt Status
+#define ADC_RIS_DMAINR1 0x00000200 // SS1 DMA Raw Interrupt Status
+#define ADC_RIS_DMAINR0 0x00000100 // SS0 DMA Raw Interrupt Status
+#define ADC_RIS_INR3 0x00000008 // SS3 Raw Interrupt Status
+#define ADC_RIS_INR2 0x00000004 // SS2 Raw Interrupt Status
+#define ADC_RIS_INR1 0x00000002 // SS1 Raw Interrupt Status
+#define ADC_RIS_INR0 0x00000001 // SS0 Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_IM register.
+//
+//*****************************************************************************
+#define ADC_IM_DCONSS3 0x00080000 // Digital Comparator Interrupt on
+ // SS3
+#define ADC_IM_DCONSS2 0x00040000 // Digital Comparator Interrupt on
+ // SS2
+#define ADC_IM_DCONSS1 0x00020000 // Digital Comparator Interrupt on
+ // SS1
+#define ADC_IM_DCONSS0 0x00010000 // Digital Comparator Interrupt on
+ // SS0
+#define ADC_IM_DMAMASK3 0x00000800 // SS3 DMA Interrupt Mask
+#define ADC_IM_DMAMASK2 0x00000400 // SS2 DMA Interrupt Mask
+#define ADC_IM_DMAMASK1 0x00000200 // SS1 DMA Interrupt Mask
+#define ADC_IM_DMAMASK0 0x00000100 // SS0 DMA Interrupt Mask
+#define ADC_IM_MASK3 0x00000008 // SS3 Interrupt Mask
+#define ADC_IM_MASK2 0x00000004 // SS2 Interrupt Mask
+#define ADC_IM_MASK1 0x00000002 // SS1 Interrupt Mask
+#define ADC_IM_MASK0 0x00000001 // SS0 Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_ISC register.
+//
+//*****************************************************************************
+#define ADC_ISC_DCINSS3 0x00080000 // Digital Comparator Interrupt
+ // Status on SS3
+#define ADC_ISC_DCINSS2 0x00040000 // Digital Comparator Interrupt
+ // Status on SS2
+#define ADC_ISC_DCINSS1 0x00020000 // Digital Comparator Interrupt
+ // Status on SS1
+#define ADC_ISC_DCINSS0 0x00010000 // Digital Comparator Interrupt
+ // Status on SS0
+#define ADC_ISC_DMAIN3 0x00000800 // SS3 DMA Interrupt Status and
+ // Clear
+#define ADC_ISC_DMAIN2 0x00000400 // SS2 DMA Interrupt Status and
+ // Clear
+#define ADC_ISC_DMAIN1 0x00000200 // SS1 DMA Interrupt Status and
+ // Clear
+#define ADC_ISC_DMAIN0 0x00000100 // SS0 DMA Interrupt Status and
+ // Clear
+#define ADC_ISC_IN3 0x00000008 // SS3 Interrupt Status and Clear
+#define ADC_ISC_IN2 0x00000004 // SS2 Interrupt Status and Clear
+#define ADC_ISC_IN1 0x00000002 // SS1 Interrupt Status and Clear
+#define ADC_ISC_IN0 0x00000001 // SS0 Interrupt Status and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_OSTAT register.
+//
+//*****************************************************************************
+#define ADC_OSTAT_OV3 0x00000008 // SS3 FIFO Overflow
+#define ADC_OSTAT_OV2 0x00000004 // SS2 FIFO Overflow
+#define ADC_OSTAT_OV1 0x00000002 // SS1 FIFO Overflow
+#define ADC_OSTAT_OV0 0x00000001 // SS0 FIFO Overflow
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_EMUX register.
+//
+//*****************************************************************************
+#define ADC_EMUX_EM3_M 0x0000F000 // SS3 Trigger Select
+#define ADC_EMUX_EM3_PROCESSOR 0x00000000 // Processor (default)
+#define ADC_EMUX_EM3_COMP0 0x00001000 // Analog Comparator 0
+#define ADC_EMUX_EM3_COMP1 0x00002000 // Analog Comparator 1
+#define ADC_EMUX_EM3_COMP2 0x00003000 // Analog Comparator 2
+#define ADC_EMUX_EM3_EXTERNAL 0x00004000 // External (GPIO Pins)
+#define ADC_EMUX_EM3_TIMER 0x00005000 // Timer
+#define ADC_EMUX_EM3_PWM0 0x00006000 // PWM generator 0
+#define ADC_EMUX_EM3_PWM1 0x00007000 // PWM generator 1
+#define ADC_EMUX_EM3_PWM2 0x00008000 // PWM generator 2
+#define ADC_EMUX_EM3_PWM3 0x00009000 // PWM generator 3
+#define ADC_EMUX_EM3_NEVER 0x0000E000 // Never Trigger
+#define ADC_EMUX_EM3_ALWAYS 0x0000F000 // Always (continuously sample)
+#define ADC_EMUX_EM2_M 0x00000F00 // SS2 Trigger Select
+#define ADC_EMUX_EM2_PROCESSOR 0x00000000 // Processor (default)
+#define ADC_EMUX_EM2_COMP0 0x00000100 // Analog Comparator 0
+#define ADC_EMUX_EM2_COMP1 0x00000200 // Analog Comparator 1
+#define ADC_EMUX_EM2_COMP2 0x00000300 // Analog Comparator 2
+#define ADC_EMUX_EM2_EXTERNAL 0x00000400 // External (GPIO Pins)
+#define ADC_EMUX_EM2_TIMER 0x00000500 // Timer
+#define ADC_EMUX_EM2_PWM0 0x00000600 // PWM generator 0
+#define ADC_EMUX_EM2_PWM1 0x00000700 // PWM generator 1
+#define ADC_EMUX_EM2_PWM2 0x00000800 // PWM generator 2
+#define ADC_EMUX_EM2_PWM3 0x00000900 // PWM generator 3
+#define ADC_EMUX_EM2_NEVER 0x00000E00 // Never Trigger
+#define ADC_EMUX_EM2_ALWAYS 0x00000F00 // Always (continuously sample)
+#define ADC_EMUX_EM1_M 0x000000F0 // SS1 Trigger Select
+#define ADC_EMUX_EM1_PROCESSOR 0x00000000 // Processor (default)
+#define ADC_EMUX_EM1_COMP0 0x00000010 // Analog Comparator 0
+#define ADC_EMUX_EM1_COMP1 0x00000020 // Analog Comparator 1
+#define ADC_EMUX_EM1_COMP2 0x00000030 // Analog Comparator 2
+#define ADC_EMUX_EM1_EXTERNAL 0x00000040 // External (GPIO Pins)
+#define ADC_EMUX_EM1_TIMER 0x00000050 // Timer
+#define ADC_EMUX_EM1_PWM0 0x00000060 // PWM generator 0
+#define ADC_EMUX_EM1_PWM1 0x00000070 // PWM generator 1
+#define ADC_EMUX_EM1_PWM2 0x00000080 // PWM generator 2
+#define ADC_EMUX_EM1_PWM3 0x00000090 // PWM generator 3
+#define ADC_EMUX_EM1_NEVER 0x000000E0 // Never Trigger
+#define ADC_EMUX_EM1_ALWAYS 0x000000F0 // Always (continuously sample)
+#define ADC_EMUX_EM0_M 0x0000000F // SS0 Trigger Select
+#define ADC_EMUX_EM0_PROCESSOR 0x00000000 // Processor (default)
+#define ADC_EMUX_EM0_COMP0 0x00000001 // Analog Comparator 0
+#define ADC_EMUX_EM0_COMP1 0x00000002 // Analog Comparator 1
+#define ADC_EMUX_EM0_COMP2 0x00000003 // Analog Comparator 2
+#define ADC_EMUX_EM0_EXTERNAL 0x00000004 // External (GPIO Pins)
+#define ADC_EMUX_EM0_TIMER 0x00000005 // Timer
+#define ADC_EMUX_EM0_PWM0 0x00000006 // PWM generator 0
+#define ADC_EMUX_EM0_PWM1 0x00000007 // PWM generator 1
+#define ADC_EMUX_EM0_PWM2 0x00000008 // PWM generator 2
+#define ADC_EMUX_EM0_PWM3 0x00000009 // PWM generator 3
+#define ADC_EMUX_EM0_NEVER 0x0000000E // Never Trigger
+#define ADC_EMUX_EM0_ALWAYS 0x0000000F // Always (continuously sample)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_USTAT register.
+//
+//*****************************************************************************
+#define ADC_USTAT_UV3 0x00000008 // SS3 FIFO Underflow
+#define ADC_USTAT_UV2 0x00000004 // SS2 FIFO Underflow
+#define ADC_USTAT_UV1 0x00000002 // SS1 FIFO Underflow
+#define ADC_USTAT_UV0 0x00000001 // SS0 FIFO Underflow
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_TSSEL register.
+//
+//*****************************************************************************
+#define ADC_TSSEL_PS3_M 0x30000000 // Generator 3 PWM Module Trigger
+ // Select
+#define ADC_TSSEL_PS3_0 0x00000000 // Use Generator 3 (and its
+ // trigger) in PWM module 0
+#define ADC_TSSEL_PS3_1 0x10000000 // Use Generator 3 (and its
+ // trigger) in PWM module 1
+#define ADC_TSSEL_PS2_M 0x00300000 // Generator 2 PWM Module Trigger
+ // Select
+#define ADC_TSSEL_PS2_0 0x00000000 // Use Generator 2 (and its
+ // trigger) in PWM module 0
+#define ADC_TSSEL_PS2_1 0x00100000 // Use Generator 2 (and its
+ // trigger) in PWM module 1
+#define ADC_TSSEL_PS1_M 0x00003000 // Generator 1 PWM Module Trigger
+ // Select
+#define ADC_TSSEL_PS1_0 0x00000000 // Use Generator 1 (and its
+ // trigger) in PWM module 0
+#define ADC_TSSEL_PS1_1 0x00001000 // Use Generator 1 (and its
+ // trigger) in PWM module 1
+#define ADC_TSSEL_PS0_M 0x00000030 // Generator 0 PWM Module Trigger
+ // Select
+#define ADC_TSSEL_PS0_0 0x00000000 // Use Generator 0 (and its
+ // trigger) in PWM module 0
+#define ADC_TSSEL_PS0_1 0x00000010 // Use Generator 0 (and its
+ // trigger) in PWM module 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSPRI register.
+//
+//*****************************************************************************
+#define ADC_SSPRI_SS3_M 0x00003000 // SS3 Priority
+#define ADC_SSPRI_SS2_M 0x00000300 // SS2 Priority
+#define ADC_SSPRI_SS1_M 0x00000030 // SS1 Priority
+#define ADC_SSPRI_SS0_M 0x00000003 // SS0 Priority
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SPC register.
+//
+//*****************************************************************************
+#define ADC_SPC_PHASE_M 0x0000000F // Phase Difference
+#define ADC_SPC_PHASE_0 0x00000000 // ADC sample lags by 0.0
+#define ADC_SPC_PHASE_22_5 0x00000001 // ADC sample lags by 22.5
+#define ADC_SPC_PHASE_45 0x00000002 // ADC sample lags by 45.0
+#define ADC_SPC_PHASE_67_5 0x00000003 // ADC sample lags by 67.5
+#define ADC_SPC_PHASE_90 0x00000004 // ADC sample lags by 90.0
+#define ADC_SPC_PHASE_112_5 0x00000005 // ADC sample lags by 112.5
+#define ADC_SPC_PHASE_135 0x00000006 // ADC sample lags by 135.0
+#define ADC_SPC_PHASE_157_5 0x00000007 // ADC sample lags by 157.5
+#define ADC_SPC_PHASE_180 0x00000008 // ADC sample lags by 180.0
+#define ADC_SPC_PHASE_202_5 0x00000009 // ADC sample lags by 202.5
+#define ADC_SPC_PHASE_225 0x0000000A // ADC sample lags by 225.0
+#define ADC_SPC_PHASE_247_5 0x0000000B // ADC sample lags by 247.5
+#define ADC_SPC_PHASE_270 0x0000000C // ADC sample lags by 270.0
+#define ADC_SPC_PHASE_292_5 0x0000000D // ADC sample lags by 292.5
+#define ADC_SPC_PHASE_315 0x0000000E // ADC sample lags by 315.0
+#define ADC_SPC_PHASE_337_5 0x0000000F // ADC sample lags by 337.5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_PSSI register.
+//
+//*****************************************************************************
+#define ADC_PSSI_GSYNC 0x80000000 // Global Synchronize
+#define ADC_PSSI_SYNCWAIT 0x08000000 // Synchronize Wait
+#define ADC_PSSI_SS3 0x00000008 // SS3 Initiate
+#define ADC_PSSI_SS2 0x00000004 // SS2 Initiate
+#define ADC_PSSI_SS1 0x00000002 // SS1 Initiate
+#define ADC_PSSI_SS0 0x00000001 // SS0 Initiate
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SAC register.
+//
+//*****************************************************************************
+#define ADC_SAC_AVG_M 0x00000007 // Hardware Averaging Control
+#define ADC_SAC_AVG_OFF 0x00000000 // No hardware oversampling
+#define ADC_SAC_AVG_2X 0x00000001 // 2x hardware oversampling
+#define ADC_SAC_AVG_4X 0x00000002 // 4x hardware oversampling
+#define ADC_SAC_AVG_8X 0x00000003 // 8x hardware oversampling
+#define ADC_SAC_AVG_16X 0x00000004 // 16x hardware oversampling
+#define ADC_SAC_AVG_32X 0x00000005 // 32x hardware oversampling
+#define ADC_SAC_AVG_64X 0x00000006 // 64x hardware oversampling
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCISC register.
+//
+//*****************************************************************************
+#define ADC_DCISC_DCINT7 0x00000080 // Digital Comparator 7 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT6 0x00000040 // Digital Comparator 6 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT5 0x00000020 // Digital Comparator 5 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT4 0x00000010 // Digital Comparator 4 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT3 0x00000008 // Digital Comparator 3 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT2 0x00000004 // Digital Comparator 2 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT1 0x00000002 // Digital Comparator 1 Interrupt
+ // Status and Clear
+#define ADC_DCISC_DCINT0 0x00000001 // Digital Comparator 0 Interrupt
+ // Status and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_CTL register.
+//
+//*****************************************************************************
+#define ADC_CTL_VREF_M 0x00000003 // Voltage Reference Select
+#define ADC_CTL_VREF_INTERNAL 0x00000000 // VDDA and GNDA are the voltage
+ // references
+#define ADC_CTL_VREF_EXT_3V 0x00000001 // The external VREFA+ and VREFA-
+ // inputs are the voltage
+ // references
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX0 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX0_MUX7_M 0xF0000000 // 8th Sample Input Select
+#define ADC_SSMUX0_MUX6_M 0x0F000000 // 7th Sample Input Select
+#define ADC_SSMUX0_MUX5_M 0x00F00000 // 6th Sample Input Select
+#define ADC_SSMUX0_MUX4_M 0x000F0000 // 5th Sample Input Select
+#define ADC_SSMUX0_MUX3_M 0x0000F000 // 4th Sample Input Select
+#define ADC_SSMUX0_MUX2_M 0x00000F00 // 3rd Sample Input Select
+#define ADC_SSMUX0_MUX1_M 0x000000F0 // 2nd Sample Input Select
+#define ADC_SSMUX0_MUX0_M 0x0000000F // 1st Sample Input Select
+#define ADC_SSMUX0_MUX7_S 28
+#define ADC_SSMUX0_MUX6_S 24
+#define ADC_SSMUX0_MUX5_S 20
+#define ADC_SSMUX0_MUX4_S 16
+#define ADC_SSMUX0_MUX3_S 12
+#define ADC_SSMUX0_MUX2_S 8
+#define ADC_SSMUX0_MUX1_S 4
+#define ADC_SSMUX0_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL0 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL0_TS7 0x80000000 // 8th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE7 0x40000000 // 8th Sample Interrupt Enable
+#define ADC_SSCTL0_END7 0x20000000 // 8th Sample is End of Sequence
+#define ADC_SSCTL0_D7 0x10000000 // 8th Sample Differential Input
+ // Select
+#define ADC_SSCTL0_TS6 0x08000000 // 7th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE6 0x04000000 // 7th Sample Interrupt Enable
+#define ADC_SSCTL0_END6 0x02000000 // 7th Sample is End of Sequence
+#define ADC_SSCTL0_D6 0x01000000 // 7th Sample Differential Input
+ // Select
+#define ADC_SSCTL0_TS5 0x00800000 // 6th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE5 0x00400000 // 6th Sample Interrupt Enable
+#define ADC_SSCTL0_END5 0x00200000 // 6th Sample is End of Sequence
+#define ADC_SSCTL0_D5 0x00100000 // 6th Sample Differential Input
+ // Select
+#define ADC_SSCTL0_TS4 0x00080000 // 5th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE4 0x00040000 // 5th Sample Interrupt Enable
+#define ADC_SSCTL0_END4 0x00020000 // 5th Sample is End of Sequence
+#define ADC_SSCTL0_D4 0x00010000 // 5th Sample Differential Input
+ // Select
+#define ADC_SSCTL0_TS3 0x00008000 // 4th Sample Temp Sensor Select
+#define ADC_SSCTL0_IE3 0x00004000 // 4th Sample Interrupt Enable
+#define ADC_SSCTL0_END3 0x00002000 // 4th Sample is End of Sequence
+#define ADC_SSCTL0_D3 0x00001000 // 4th Sample Differential Input
+ // Select
+#define ADC_SSCTL0_TS2 0x00000800 // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL0_IE2 0x00000400 // 3rd Sample Interrupt Enable
+#define ADC_SSCTL0_END2 0x00000200 // 3rd Sample is End of Sequence
+#define ADC_SSCTL0_D2 0x00000100 // 3rd Sample Differential Input
+ // Select
+#define ADC_SSCTL0_TS1 0x00000080 // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL0_IE1 0x00000040 // 2nd Sample Interrupt Enable
+#define ADC_SSCTL0_END1 0x00000020 // 2nd Sample is End of Sequence
+#define ADC_SSCTL0_D1 0x00000010 // 2nd Sample Differential Input
+ // Select
+#define ADC_SSCTL0_TS0 0x00000008 // 1st Sample Temp Sensor Select
+#define ADC_SSCTL0_IE0 0x00000004 // 1st Sample Interrupt Enable
+#define ADC_SSCTL0_END0 0x00000002 // 1st Sample is End of Sequence
+#define ADC_SSCTL0_D0 0x00000001 // 1st Sample Differential Input
+ // Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO0 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO0_DATA_M 0x00000FFF // Conversion Result Data
+#define ADC_SSFIFO0_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT0 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT0_FULL 0x00001000 // FIFO Full
+#define ADC_SSFSTAT0_EMPTY 0x00000100 // FIFO Empty
+#define ADC_SSFSTAT0_HPTR_M 0x000000F0 // FIFO Head Pointer
+#define ADC_SSFSTAT0_TPTR_M 0x0000000F // FIFO Tail Pointer
+#define ADC_SSFSTAT0_HPTR_S 4
+#define ADC_SSFSTAT0_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP0 register.
+//
+//*****************************************************************************
+#define ADC_SSOP0_S7DCOP 0x10000000 // Sample 7 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S6DCOP 0x01000000 // Sample 6 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S5DCOP 0x00100000 // Sample 5 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S4DCOP 0x00010000 // Sample 4 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S3DCOP 0x00001000 // Sample 3 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S2DCOP 0x00000100 // Sample 2 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S1DCOP 0x00000010 // Sample 1 Digital Comparator
+ // Operation
+#define ADC_SSOP0_S0DCOP 0x00000001 // Sample 0 Digital Comparator
+ // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC0 register.
+//
+//*****************************************************************************
+#define ADC_SSDC0_S7DCSEL_M 0xF0000000 // Sample 7 Digital Comparator
+ // Select
+#define ADC_SSDC0_S6DCSEL_M 0x0F000000 // Sample 6 Digital Comparator
+ // Select
+#define ADC_SSDC0_S5DCSEL_M 0x00F00000 // Sample 5 Digital Comparator
+ // Select
+#define ADC_SSDC0_S4DCSEL_M 0x000F0000 // Sample 4 Digital Comparator
+ // Select
+#define ADC_SSDC0_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator
+ // Select
+#define ADC_SSDC0_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator
+ // Select
+#define ADC_SSDC0_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator
+ // Select
+#define ADC_SSDC0_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
+ // Select
+#define ADC_SSDC0_S6DCSEL_S 24
+#define ADC_SSDC0_S5DCSEL_S 20
+#define ADC_SSDC0_S4DCSEL_S 16
+#define ADC_SSDC0_S3DCSEL_S 12
+#define ADC_SSDC0_S2DCSEL_S 8
+#define ADC_SSDC0_S1DCSEL_S 4
+#define ADC_SSDC0_S0DCSEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSEMUX0 register.
+//
+//*****************************************************************************
+#define ADC_SSEMUX0_EMUX7 0x10000000 // 8th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX0_EMUX6 0x01000000 // 7th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX0_EMUX5 0x00100000 // 6th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX0_EMUX4 0x00010000 // 5th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX0_EMUX3 0x00001000 // 4th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX0_EMUX2 0x00000100 // 3rd Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX0_EMUX1 0x00000010 // 2th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX0_EMUX0 0x00000001 // 1st Sample Input Select (Upper
+ // Bit)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSTSH0 register.
+//
+//*****************************************************************************
+#define ADC_SSTSH0_TSH7_M 0xF0000000 // 8th Sample and Hold Period
+ // Select
+#define ADC_SSTSH0_TSH6_M 0x0F000000 // 7th Sample and Hold Period
+ // Select
+#define ADC_SSTSH0_TSH5_M 0x00F00000 // 6th Sample and Hold Period
+ // Select
+#define ADC_SSTSH0_TSH4_M 0x000F0000 // 5th Sample and Hold Period
+ // Select
+#define ADC_SSTSH0_TSH3_M 0x0000F000 // 4th Sample and Hold Period
+ // Select
+#define ADC_SSTSH0_TSH2_M 0x00000F00 // 3rd Sample and Hold Period
+ // Select
+#define ADC_SSTSH0_TSH1_M 0x000000F0 // 2nd Sample and Hold Period
+ // Select
+#define ADC_SSTSH0_TSH0_M 0x0000000F // 1st Sample and Hold Period
+ // Select
+#define ADC_SSTSH0_TSH7_S 28
+#define ADC_SSTSH0_TSH6_S 24
+#define ADC_SSTSH0_TSH5_S 20
+#define ADC_SSTSH0_TSH4_S 16
+#define ADC_SSTSH0_TSH3_S 12
+#define ADC_SSTSH0_TSH2_S 8
+#define ADC_SSTSH0_TSH1_S 4
+#define ADC_SSTSH0_TSH0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX1 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX1_MUX3_M 0x0000F000 // 4th Sample Input Select
+#define ADC_SSMUX1_MUX2_M 0x00000F00 // 3rd Sample Input Select
+#define ADC_SSMUX1_MUX1_M 0x000000F0 // 2nd Sample Input Select
+#define ADC_SSMUX1_MUX0_M 0x0000000F // 1st Sample Input Select
+#define ADC_SSMUX1_MUX3_S 12
+#define ADC_SSMUX1_MUX2_S 8
+#define ADC_SSMUX1_MUX1_S 4
+#define ADC_SSMUX1_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL1 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL1_TS3 0x00008000 // 4th Sample Temp Sensor Select
+#define ADC_SSCTL1_IE3 0x00004000 // 4th Sample Interrupt Enable
+#define ADC_SSCTL1_END3 0x00002000 // 4th Sample is End of Sequence
+#define ADC_SSCTL1_D3 0x00001000 // 4th Sample Differential Input
+ // Select
+#define ADC_SSCTL1_TS2 0x00000800 // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL1_IE2 0x00000400 // 3rd Sample Interrupt Enable
+#define ADC_SSCTL1_END2 0x00000200 // 3rd Sample is End of Sequence
+#define ADC_SSCTL1_D2 0x00000100 // 3rd Sample Differential Input
+ // Select
+#define ADC_SSCTL1_TS1 0x00000080 // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL1_IE1 0x00000040 // 2nd Sample Interrupt Enable
+#define ADC_SSCTL1_END1 0x00000020 // 2nd Sample is End of Sequence
+#define ADC_SSCTL1_D1 0x00000010 // 2nd Sample Differential Input
+ // Select
+#define ADC_SSCTL1_TS0 0x00000008 // 1st Sample Temp Sensor Select
+#define ADC_SSCTL1_IE0 0x00000004 // 1st Sample Interrupt Enable
+#define ADC_SSCTL1_END0 0x00000002 // 1st Sample is End of Sequence
+#define ADC_SSCTL1_D0 0x00000001 // 1st Sample Differential Input
+ // Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO1 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO1_DATA_M 0x00000FFF // Conversion Result Data
+#define ADC_SSFIFO1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT1 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT1_FULL 0x00001000 // FIFO Full
+#define ADC_SSFSTAT1_EMPTY 0x00000100 // FIFO Empty
+#define ADC_SSFSTAT1_HPTR_M 0x000000F0 // FIFO Head Pointer
+#define ADC_SSFSTAT1_TPTR_M 0x0000000F // FIFO Tail Pointer
+#define ADC_SSFSTAT1_HPTR_S 4
+#define ADC_SSFSTAT1_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP1 register.
+//
+//*****************************************************************************
+#define ADC_SSOP1_S3DCOP 0x00001000 // Sample 3 Digital Comparator
+ // Operation
+#define ADC_SSOP1_S2DCOP 0x00000100 // Sample 2 Digital Comparator
+ // Operation
+#define ADC_SSOP1_S1DCOP 0x00000010 // Sample 1 Digital Comparator
+ // Operation
+#define ADC_SSOP1_S0DCOP 0x00000001 // Sample 0 Digital Comparator
+ // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC1 register.
+//
+//*****************************************************************************
+#define ADC_SSDC1_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator
+ // Select
+#define ADC_SSDC1_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator
+ // Select
+#define ADC_SSDC1_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator
+ // Select
+#define ADC_SSDC1_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
+ // Select
+#define ADC_SSDC1_S2DCSEL_S 8
+#define ADC_SSDC1_S1DCSEL_S 4
+#define ADC_SSDC1_S0DCSEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSEMUX1 register.
+//
+//*****************************************************************************
+#define ADC_SSEMUX1_EMUX3 0x00001000 // 4th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX1_EMUX2 0x00000100 // 3rd Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX1_EMUX1 0x00000010 // 2th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX1_EMUX0 0x00000001 // 1st Sample Input Select (Upper
+ // Bit)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSTSH1 register.
+//
+//*****************************************************************************
+#define ADC_SSTSH1_TSH3_M 0x0000F000 // 4th Sample and Hold Period
+ // Select
+#define ADC_SSTSH1_TSH2_M 0x00000F00 // 3rd Sample and Hold Period
+ // Select
+#define ADC_SSTSH1_TSH1_M 0x000000F0 // 2nd Sample and Hold Period
+ // Select
+#define ADC_SSTSH1_TSH0_M 0x0000000F // 1st Sample and Hold Period
+ // Select
+#define ADC_SSTSH1_TSH3_S 12
+#define ADC_SSTSH1_TSH2_S 8
+#define ADC_SSTSH1_TSH1_S 4
+#define ADC_SSTSH1_TSH0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX2 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX2_MUX3_M 0x0000F000 // 4th Sample Input Select
+#define ADC_SSMUX2_MUX2_M 0x00000F00 // 3rd Sample Input Select
+#define ADC_SSMUX2_MUX1_M 0x000000F0 // 2nd Sample Input Select
+#define ADC_SSMUX2_MUX0_M 0x0000000F // 1st Sample Input Select
+#define ADC_SSMUX2_MUX3_S 12
+#define ADC_SSMUX2_MUX2_S 8
+#define ADC_SSMUX2_MUX1_S 4
+#define ADC_SSMUX2_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL2 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL2_TS3 0x00008000 // 4th Sample Temp Sensor Select
+#define ADC_SSCTL2_IE3 0x00004000 // 4th Sample Interrupt Enable
+#define ADC_SSCTL2_END3 0x00002000 // 4th Sample is End of Sequence
+#define ADC_SSCTL2_D3 0x00001000 // 4th Sample Differential Input
+ // Select
+#define ADC_SSCTL2_TS2 0x00000800 // 3rd Sample Temp Sensor Select
+#define ADC_SSCTL2_IE2 0x00000400 // 3rd Sample Interrupt Enable
+#define ADC_SSCTL2_END2 0x00000200 // 3rd Sample is End of Sequence
+#define ADC_SSCTL2_D2 0x00000100 // 3rd Sample Differential Input
+ // Select
+#define ADC_SSCTL2_TS1 0x00000080 // 2nd Sample Temp Sensor Select
+#define ADC_SSCTL2_IE1 0x00000040 // 2nd Sample Interrupt Enable
+#define ADC_SSCTL2_END1 0x00000020 // 2nd Sample is End of Sequence
+#define ADC_SSCTL2_D1 0x00000010 // 2nd Sample Differential Input
+ // Select
+#define ADC_SSCTL2_TS0 0x00000008 // 1st Sample Temp Sensor Select
+#define ADC_SSCTL2_IE0 0x00000004 // 1st Sample Interrupt Enable
+#define ADC_SSCTL2_END0 0x00000002 // 1st Sample is End of Sequence
+#define ADC_SSCTL2_D0 0x00000001 // 1st Sample Differential Input
+ // Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO2 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO2_DATA_M 0x00000FFF // Conversion Result Data
+#define ADC_SSFIFO2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT2 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT2_FULL 0x00001000 // FIFO Full
+#define ADC_SSFSTAT2_EMPTY 0x00000100 // FIFO Empty
+#define ADC_SSFSTAT2_HPTR_M 0x000000F0 // FIFO Head Pointer
+#define ADC_SSFSTAT2_TPTR_M 0x0000000F // FIFO Tail Pointer
+#define ADC_SSFSTAT2_HPTR_S 4
+#define ADC_SSFSTAT2_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP2 register.
+//
+//*****************************************************************************
+#define ADC_SSOP2_S3DCOP 0x00001000 // Sample 3 Digital Comparator
+ // Operation
+#define ADC_SSOP2_S2DCOP 0x00000100 // Sample 2 Digital Comparator
+ // Operation
+#define ADC_SSOP2_S1DCOP 0x00000010 // Sample 1 Digital Comparator
+ // Operation
+#define ADC_SSOP2_S0DCOP 0x00000001 // Sample 0 Digital Comparator
+ // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC2 register.
+//
+//*****************************************************************************
+#define ADC_SSDC2_S3DCSEL_M 0x0000F000 // Sample 3 Digital Comparator
+ // Select
+#define ADC_SSDC2_S2DCSEL_M 0x00000F00 // Sample 2 Digital Comparator
+ // Select
+#define ADC_SSDC2_S1DCSEL_M 0x000000F0 // Sample 1 Digital Comparator
+ // Select
+#define ADC_SSDC2_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
+ // Select
+#define ADC_SSDC2_S2DCSEL_S 8
+#define ADC_SSDC2_S1DCSEL_S 4
+#define ADC_SSDC2_S0DCSEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSEMUX2 register.
+//
+//*****************************************************************************
+#define ADC_SSEMUX2_EMUX3 0x00001000 // 4th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX2_EMUX2 0x00000100 // 3rd Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX2_EMUX1 0x00000010 // 2th Sample Input Select (Upper
+ // Bit)
+#define ADC_SSEMUX2_EMUX0 0x00000001 // 1st Sample Input Select (Upper
+ // Bit)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSTSH2 register.
+//
+//*****************************************************************************
+#define ADC_SSTSH2_TSH3_M 0x0000F000 // 4th Sample and Hold Period
+ // Select
+#define ADC_SSTSH2_TSH2_M 0x00000F00 // 3rd Sample and Hold Period
+ // Select
+#define ADC_SSTSH2_TSH1_M 0x000000F0 // 2nd Sample and Hold Period
+ // Select
+#define ADC_SSTSH2_TSH0_M 0x0000000F // 1st Sample and Hold Period
+ // Select
+#define ADC_SSTSH2_TSH3_S 12
+#define ADC_SSTSH2_TSH2_S 8
+#define ADC_SSTSH2_TSH1_S 4
+#define ADC_SSTSH2_TSH0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSMUX3 register.
+//
+//*****************************************************************************
+#define ADC_SSMUX3_MUX0_M 0x0000000F // 1st Sample Input Select
+#define ADC_SSMUX3_MUX0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSCTL3 register.
+//
+//*****************************************************************************
+#define ADC_SSCTL3_TS0 0x00000008 // 1st Sample Temp Sensor Select
+#define ADC_SSCTL3_IE0 0x00000004 // Sample Interrupt Enable
+#define ADC_SSCTL3_END0 0x00000002 // End of Sequence
+#define ADC_SSCTL3_D0 0x00000001 // Sample Differential Input Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFIFO3 register.
+//
+//*****************************************************************************
+#define ADC_SSFIFO3_DATA_M 0x00000FFF // Conversion Result Data
+#define ADC_SSFIFO3_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSFSTAT3 register.
+//
+//*****************************************************************************
+#define ADC_SSFSTAT3_FULL 0x00001000 // FIFO Full
+#define ADC_SSFSTAT3_EMPTY 0x00000100 // FIFO Empty
+#define ADC_SSFSTAT3_HPTR_M 0x000000F0 // FIFO Head Pointer
+#define ADC_SSFSTAT3_TPTR_M 0x0000000F // FIFO Tail Pointer
+#define ADC_SSFSTAT3_HPTR_S 4
+#define ADC_SSFSTAT3_TPTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSOP3 register.
+//
+//*****************************************************************************
+#define ADC_SSOP3_S0DCOP 0x00000001 // Sample 0 Digital Comparator
+ // Operation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSDC3 register.
+//
+//*****************************************************************************
+#define ADC_SSDC3_S0DCSEL_M 0x0000000F // Sample 0 Digital Comparator
+ // Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSEMUX3 register.
+//
+//*****************************************************************************
+#define ADC_SSEMUX3_EMUX0 0x00000001 // 1st Sample Input Select (Upper
+ // Bit)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_SSTSH3 register.
+//
+//*****************************************************************************
+#define ADC_SSTSH3_TSH0_M 0x0000000F // 1st Sample and Hold Period
+ // Select
+#define ADC_SSTSH3_TSH0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCRIC register.
+//
+//*****************************************************************************
+#define ADC_DCRIC_DCTRIG7 0x00800000 // Digital Comparator Trigger 7
+#define ADC_DCRIC_DCTRIG6 0x00400000 // Digital Comparator Trigger 6
+#define ADC_DCRIC_DCTRIG5 0x00200000 // Digital Comparator Trigger 5
+#define ADC_DCRIC_DCTRIG4 0x00100000 // Digital Comparator Trigger 4
+#define ADC_DCRIC_DCTRIG3 0x00080000 // Digital Comparator Trigger 3
+#define ADC_DCRIC_DCTRIG2 0x00040000 // Digital Comparator Trigger 2
+#define ADC_DCRIC_DCTRIG1 0x00020000 // Digital Comparator Trigger 1
+#define ADC_DCRIC_DCTRIG0 0x00010000 // Digital Comparator Trigger 0
+#define ADC_DCRIC_DCINT7 0x00000080 // Digital Comparator Interrupt 7
+#define ADC_DCRIC_DCINT6 0x00000040 // Digital Comparator Interrupt 6
+#define ADC_DCRIC_DCINT5 0x00000020 // Digital Comparator Interrupt 5
+#define ADC_DCRIC_DCINT4 0x00000010 // Digital Comparator Interrupt 4
+#define ADC_DCRIC_DCINT3 0x00000008 // Digital Comparator Interrupt 3
+#define ADC_DCRIC_DCINT2 0x00000004 // Digital Comparator Interrupt 2
+#define ADC_DCRIC_DCINT1 0x00000002 // Digital Comparator Interrupt 1
+#define ADC_DCRIC_DCINT0 0x00000001 // Digital Comparator Interrupt 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL0 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL0_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL0_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL0_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL0_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL0_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL0_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL0_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL0_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL0_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL0_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL0_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL0_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL0_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL0_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL0_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL0_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL0_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL0_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL0_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL0_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL1 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL1_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL1_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL1_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL1_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL1_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL1_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL1_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL1_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL1_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL1_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL1_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL1_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL1_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL1_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL1_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL1_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL1_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL1_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL1_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL1_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL2 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL2_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL2_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL2_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL2_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL2_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL2_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL2_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL2_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL2_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL2_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL2_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL2_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL2_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL2_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL2_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL2_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL2_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL2_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL2_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL2_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL3 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL3_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL3_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL3_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL3_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL3_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL3_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL3_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL3_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL3_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL3_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL3_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL3_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL3_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL3_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL3_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL3_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL3_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL3_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL3_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL3_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL4 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL4_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL4_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL4_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL4_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL4_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL4_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL4_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL4_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL4_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL4_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL4_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL4_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL4_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL4_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL4_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL4_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL4_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL4_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL4_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL4_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL5 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL5_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL5_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL5_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL5_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL5_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL5_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL5_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL5_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL5_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL5_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL5_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL5_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL5_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL5_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL5_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL5_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL5_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL5_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL5_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL5_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL6 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL6_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL6_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL6_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL6_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL6_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL6_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL6_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL6_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL6_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL6_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL6_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL6_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL6_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL6_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL6_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL6_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL6_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL6_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL6_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL6_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCTL7 register.
+//
+//*****************************************************************************
+#define ADC_DCCTL7_CTE 0x00001000 // Comparison Trigger Enable
+#define ADC_DCCTL7_CTC_M 0x00000C00 // Comparison Trigger Condition
+#define ADC_DCCTL7_CTC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL7_CTC_MID 0x00000400 // Mid Band
+#define ADC_DCCTL7_CTC_HIGH 0x00000C00 // High Band
+#define ADC_DCCTL7_CTM_M 0x00000300 // Comparison Trigger Mode
+#define ADC_DCCTL7_CTM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL7_CTM_ONCE 0x00000100 // Once
+#define ADC_DCCTL7_CTM_HALWAYS 0x00000200 // Hysteresis Always
+#define ADC_DCCTL7_CTM_HONCE 0x00000300 // Hysteresis Once
+#define ADC_DCCTL7_CIE 0x00000010 // Comparison Interrupt Enable
+#define ADC_DCCTL7_CIC_M 0x0000000C // Comparison Interrupt Condition
+#define ADC_DCCTL7_CIC_LOW 0x00000000 // Low Band
+#define ADC_DCCTL7_CIC_MID 0x00000004 // Mid Band
+#define ADC_DCCTL7_CIC_HIGH 0x0000000C // High Band
+#define ADC_DCCTL7_CIM_M 0x00000003 // Comparison Interrupt Mode
+#define ADC_DCCTL7_CIM_ALWAYS 0x00000000 // Always
+#define ADC_DCCTL7_CIM_ONCE 0x00000001 // Once
+#define ADC_DCCTL7_CIM_HALWAYS 0x00000002 // Hysteresis Always
+#define ADC_DCCTL7_CIM_HONCE 0x00000003 // Hysteresis Once
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP0 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP0_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP0_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP0_COMP1_S 16
+#define ADC_DCCMP0_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP1 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP1_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP1_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP1_COMP1_S 16
+#define ADC_DCCMP1_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP2 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP2_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP2_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP2_COMP1_S 16
+#define ADC_DCCMP2_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP3 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP3_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP3_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP3_COMP1_S 16
+#define ADC_DCCMP3_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP4 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP4_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP4_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP4_COMP1_S 16
+#define ADC_DCCMP4_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP5 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP5_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP5_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP5_COMP1_S 16
+#define ADC_DCCMP5_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP6 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP6_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP6_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP6_COMP1_S 16
+#define ADC_DCCMP6_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_DCCMP7 register.
+//
+//*****************************************************************************
+#define ADC_DCCMP7_COMP1_M 0x0FFF0000 // Compare 1
+#define ADC_DCCMP7_COMP0_M 0x00000FFF // Compare 0
+#define ADC_DCCMP7_COMP1_S 16
+#define ADC_DCCMP7_COMP0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_PP register.
+//
+//*****************************************************************************
+#define ADC_PP_APSHT 0x01000000 // Application-Programmable
+ // Sample-and-Hold Time
+#define ADC_PP_TS 0x00800000 // Temperature Sensor
+#define ADC_PP_RSL_M 0x007C0000 // Resolution
+#define ADC_PP_TYPE_M 0x00030000 // ADC Architecture
+#define ADC_PP_TYPE_SAR 0x00000000 // SAR
+#define ADC_PP_DC_M 0x0000FC00 // Digital Comparator Count
+#define ADC_PP_CH_M 0x000003F0 // ADC Channel Count
+#define ADC_PP_MCR_M 0x0000000F // Maximum Conversion Rate
+#define ADC_PP_MCR_FULL 0x00000007 // Full conversion rate (FCONV) as
+ // defined by TADC and NSH
+#define ADC_PP_MSR_M 0x0000000F // Maximum ADC Sample Rate
+#define ADC_PP_MSR_125K 0x00000001 // 125 ksps
+#define ADC_PP_MSR_250K 0x00000003 // 250 ksps
+#define ADC_PP_MSR_500K 0x00000005 // 500 ksps
+#define ADC_PP_MSR_1M 0x00000007 // 1 Msps
+#define ADC_PP_RSL_S 18
+#define ADC_PP_DC_S 10
+#define ADC_PP_CH_S 4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_PC register.
+//
+//*****************************************************************************
+#define ADC_PC_SR_M 0x0000000F // ADC Sample Rate
+#define ADC_PC_SR_125K 0x00000001 // 125 ksps
+#define ADC_PC_SR_250K 0x00000003 // 250 ksps
+#define ADC_PC_SR_500K 0x00000005 // 500 ksps
+#define ADC_PC_SR_1M 0x00000007 // 1 Msps
+#define ADC_PC_MCR_M 0x0000000F // Conversion Rate
+#define ADC_PC_MCR_1_8 0x00000001 // Eighth conversion rate. After a
+ // conversion completes, the logic
+ // pauses for 112 TADC periods
+ // before starting the next
+ // conversion
+#define ADC_PC_MCR_1_4 0x00000003 // Quarter conversion rate. After a
+ // conversion completes, the logic
+ // pauses for 48 TADC periods
+ // before starting the next
+ // conversion
+#define ADC_PC_MCR_1_2 0x00000005 // Half conversion rate. After a
+ // conversion completes, the logic
+ // pauses for 16 TADC periods
+ // before starting the next
+ // conversion
+#define ADC_PC_MCR_FULL 0x00000007 // Full conversion rate (FCONV) as
+ // defined by TADC and NSH
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ADC_O_CC register.
+//
+//*****************************************************************************
+#define ADC_CC_CLKDIV_M 0x000003F0 // PLL VCO Clock Divisor
+#define ADC_CC_CS_M 0x0000000F // ADC Clock Source
+#define ADC_CC_CS_SYSPLL 0x00000000 // PLL VCO divided by CLKDIV
+#define ADC_CC_CS_PIOSC 0x00000001 // PIOSC
+#define ADC_CC_CS_MOSC 0x00000002 // MOSC
+#define ADC_CC_CLKDIV_S 4
+
+#endif // __HW_ADC_H__
diff --git a/os/common/ext/TivaWare/inc/hw_aes.h b/os/common/ext/TivaWare/inc/hw_aes.h
new file mode 100644
index 0000000..49dda1e
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_aes.h
@@ -0,0 +1,545 @@
+//*****************************************************************************
+//
+// hw_aes.h - Macros used when accessing the AES hardware.
+//
+// Copyright (c) 2012-2016 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_AES_H__
+#define __HW_AES_H__
+
+//*****************************************************************************
+//
+// The following are defines for the AES register offsets.
+//
+//*****************************************************************************
+#define AES_O_KEY2_6 0x00000000 // AES Key 2_6
+#define AES_O_KEY2_7 0x00000004 // AES Key 2_7
+#define AES_O_KEY2_4 0x00000008 // AES Key 2_4
+#define AES_O_KEY2_5 0x0000000C // AES Key 2_5
+#define AES_O_KEY2_2 0x00000010 // AES Key 2_2
+#define AES_O_KEY2_3 0x00000014 // AES Key 2_3
+#define AES_O_KEY2_0 0x00000018 // AES Key 2_0
+#define AES_O_KEY2_1 0x0000001C // AES Key 2_1
+#define AES_O_KEY1_6 0x00000020 // AES Key 1_6
+#define AES_O_KEY1_7 0x00000024 // AES Key 1_7
+#define AES_O_KEY1_4 0x00000028 // AES Key 1_4
+#define AES_O_KEY1_5 0x0000002C // AES Key 1_5
+#define AES_O_KEY1_2 0x00000030 // AES Key 1_2
+#define AES_O_KEY1_3 0x00000034 // AES Key 1_3
+#define AES_O_KEY1_0 0x00000038 // AES Key 1_0
+#define AES_O_KEY1_1 0x0000003C // AES Key 1_1
+#define AES_O_IV_IN_0 0x00000040 // AES Initialization Vector Input
+ // 0
+#define AES_O_IV_IN_1 0x00000044 // AES Initialization Vector Input
+ // 1
+#define AES_O_IV_IN_2 0x00000048 // AES Initialization Vector Input
+ // 2
+#define AES_O_IV_IN_3 0x0000004C // AES Initialization Vector Input
+ // 3
+#define AES_O_CTRL 0x00000050 // AES Control
+#define AES_O_C_LENGTH_0 0x00000054 // AES Crypto Data Length 0
+#define AES_O_C_LENGTH_1 0x00000058 // AES Crypto Data Length 1
+#define AES_O_AUTH_LENGTH 0x0000005C // AES Authentication Data Length
+#define AES_O_DATA_IN_0 0x00000060 // AES Data RW Plaintext/Ciphertext
+ // 0
+#define AES_O_DATA_IN_1 0x00000064 // AES Data RW Plaintext/Ciphertext
+ // 1
+#define AES_O_DATA_IN_2 0x00000068 // AES Data RW Plaintext/Ciphertext
+ // 2
+#define AES_O_DATA_IN_3 0x0000006C // AES Data RW Plaintext/Ciphertext
+ // 3
+#define AES_O_TAG_OUT_0 0x00000070 // AES Hash Tag Out 0
+#define AES_O_TAG_OUT_1 0x00000074 // AES Hash Tag Out 1
+#define AES_O_TAG_OUT_2 0x00000078 // AES Hash Tag Out 2
+#define AES_O_TAG_OUT_3 0x0000007C // AES Hash Tag Out 3
+#define AES_O_REVISION 0x00000080 // AES IP Revision Identifier
+#define AES_O_SYSCONFIG 0x00000084 // AES System Configuration
+#define AES_O_SYSSTATUS 0x00000088 // AES System Status
+#define AES_O_IRQSTATUS 0x0000008C // AES Interrupt Status
+#define AES_O_IRQENABLE 0x00000090 // AES Interrupt Enable
+#define AES_O_DIRTYBITS 0x00000094 // AES Dirty Bits
+#define AES_O_DMAIM 0xFFFFA020 // AES DMA Interrupt Mask
+#define AES_O_DMARIS 0xFFFFA024 // AES DMA Raw Interrupt Status
+#define AES_O_DMAMIS 0xFFFFA028 // AES DMA Masked Interrupt Status
+#define AES_O_DMAIC 0xFFFFA02C // AES DMA Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_6 register.
+//
+//*****************************************************************************
+#define AES_KEY2_6_KEY_M 0xFFFFFFFF // Key Data
+#define AES_KEY2_6_KEY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_7 register.
+//
+//*****************************************************************************
+#define AES_KEY2_7_KEY_M 0xFFFFFFFF // Key Data
+#define AES_KEY2_7_KEY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_4 register.
+//
+//*****************************************************************************
+#define AES_KEY2_4_KEY_M 0xFFFFFFFF // Key Data
+#define AES_KEY2_4_KEY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_5 register.
+//
+//*****************************************************************************
+#define AES_KEY2_5_KEY_M 0xFFFFFFFF // Key Data
+#define AES_KEY2_5_KEY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_2 register.
+//
+//*****************************************************************************
+#define AES_KEY2_2_KEY_M 0xFFFFFFFF // Key Data
+#define AES_KEY2_2_KEY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_3 register.
+//
+//*****************************************************************************
+#define AES_KEY2_3_KEY_M 0xFFFFFFFF // Key Data
+#define AES_KEY2_3_KEY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_0 register.
+//
+//*****************************************************************************
+#define AES_KEY2_0_KEY_M 0xFFFFFFFF // Key Data
+#define AES_KEY2_0_KEY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY2_1 register.
+//
+//*****************************************************************************
+#define AES_KEY2_1_KEY_M 0xFFFFFFFF // Key Data
+#define AES_KEY2_1_KEY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_6 register.
+//
+//*****************************************************************************
+#define AES_KEY1_6_KEY_M 0xFFFFFFFF // Key Data
+#define AES_KEY1_6_KEY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_7 register.
+//
+//*****************************************************************************
+#define AES_KEY1_7_KEY_M 0xFFFFFFFF // Key Data
+#define AES_KEY1_7_KEY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_4 register.
+//
+//*****************************************************************************
+#define AES_KEY1_4_KEY_M 0xFFFFFFFF // Key Data
+#define AES_KEY1_4_KEY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_5 register.
+//
+//*****************************************************************************
+#define AES_KEY1_5_KEY_M 0xFFFFFFFF // Key Data
+#define AES_KEY1_5_KEY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_2 register.
+//
+//*****************************************************************************
+#define AES_KEY1_2_KEY_M 0xFFFFFFFF // Key Data
+#define AES_KEY1_2_KEY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_3 register.
+//
+//*****************************************************************************
+#define AES_KEY1_3_KEY_M 0xFFFFFFFF // Key Data
+#define AES_KEY1_3_KEY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_0 register.
+//
+//*****************************************************************************
+#define AES_KEY1_0_KEY_M 0xFFFFFFFF // Key Data
+#define AES_KEY1_0_KEY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_KEY1_1 register.
+//
+//*****************************************************************************
+#define AES_KEY1_1_KEY_M 0xFFFFFFFF // Key Data
+#define AES_KEY1_1_KEY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_IV_IN_0 register.
+//
+//*****************************************************************************
+#define AES_IV_IN_0_DATA_M 0xFFFFFFFF // Initialization Vector Input
+#define AES_IV_IN_0_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_IV_IN_1 register.
+//
+//*****************************************************************************
+#define AES_IV_IN_1_DATA_M 0xFFFFFFFF // Initialization Vector Input
+#define AES_IV_IN_1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_IV_IN_2 register.
+//
+//*****************************************************************************
+#define AES_IV_IN_2_DATA_M 0xFFFFFFFF // Initialization Vector Input
+#define AES_IV_IN_2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_IV_IN_3 register.
+//
+//*****************************************************************************
+#define AES_IV_IN_3_DATA_M 0xFFFFFFFF // Initialization Vector Input
+#define AES_IV_IN_3_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_CTRL register.
+//
+//*****************************************************************************
+#define AES_CTRL_CTXTRDY 0x80000000 // Context Data Registers Ready
+#define AES_CTRL_SVCTXTRDY 0x40000000 // AES TAG/IV Block(s) Ready
+#define AES_CTRL_SAVE_CONTEXT 0x20000000 // TAG or Result IV Save
+#define AES_CTRL_CCM_M_M 0x01C00000 // Counter with CBC-MAC (CCM)
+#define AES_CTRL_CCM_L_M 0x00380000 // L Value
+#define AES_CTRL_CCM_L_2 0x00080000 // width = 2
+#define AES_CTRL_CCM_L_4 0x00180000 // width = 4
+#define AES_CTRL_CCM_L_8 0x00380000 // width = 8
+#define AES_CTRL_CCM 0x00040000 // AES-CCM Mode Enable
+#define AES_CTRL_GCM_M 0x00030000 // AES-GCM Mode Enable
+#define AES_CTRL_GCM_NOP 0x00000000 // No operation
+#define AES_CTRL_GCM_HLY0ZERO 0x00010000 // GHASH with H loaded and
+ // Y0-encrypted forced to zero
+#define AES_CTRL_GCM_HLY0CALC 0x00020000 // GHASH with H loaded and
+ // Y0-encrypted calculated
+ // internally
+#define AES_CTRL_GCM_HY0CALC 0x00030000 // Autonomous GHASH (both H and
+ // Y0-encrypted calculated
+ // internally)
+#define AES_CTRL_CBCMAC 0x00008000 // AES-CBC MAC Enable
+#define AES_CTRL_F9 0x00004000 // AES f9 Mode Enable
+#define AES_CTRL_F8 0x00002000 // AES f8 Mode Enable
+#define AES_CTRL_XTS_M 0x00001800 // AES-XTS Operation Enabled
+#define AES_CTRL_XTS_NOP 0x00000000 // No operation
+#define AES_CTRL_XTS_TWEAKJL 0x00000800 // Previous/intermediate tweak
+ // value and j loaded (value is
+ // loaded via IV, j is loaded via
+ // the AAD length register)
+#define AES_CTRL_XTS_K2IJL 0x00001000 // Key2, n and j are loaded (n is
+ // loaded via IV, j is loaded via
+ // the AAD length register)
+#define AES_CTRL_XTS_K2ILJ0 0x00001800 // Key2 and n are loaded; j=0 (n is
+ // loaded via IV)
+#define AES_CTRL_CFB 0x00000400 // Full block AES cipher feedback
+ // mode (CFB128) Enable
+#define AES_CTRL_ICM 0x00000200 // AES Integer Counter Mode (ICM)
+ // Enable
+#define AES_CTRL_CTR_WIDTH_M 0x00000180 // AES-CTR Mode Counter Width
+#define AES_CTRL_CTR_WIDTH_32 0x00000000 // Counter is 32 bits
+#define AES_CTRL_CTR_WIDTH_64 0x00000080 // Counter is 64 bits
+#define AES_CTRL_CTR_WIDTH_96 0x00000100 // Counter is 96 bits
+#define AES_CTRL_CTR_WIDTH_128 0x00000180 // Counter is 128 bits
+#define AES_CTRL_CTR 0x00000040 // Counter Mode
+#define AES_CTRL_MODE 0x00000020 // ECB/CBC Mode
+#define AES_CTRL_KEY_SIZE_M 0x00000018 // Key Size
+#define AES_CTRL_KEY_SIZE_128 0x00000008 // Key is 128 bits
+#define AES_CTRL_KEY_SIZE_192 0x00000010 // Key is 192 bits
+#define AES_CTRL_KEY_SIZE_256 0x00000018 // Key is 256 bits
+#define AES_CTRL_DIRECTION 0x00000004 // Encryption/Decryption Selection
+#define AES_CTRL_INPUT_READY 0x00000002 // Input Ready Status
+#define AES_CTRL_OUTPUT_READY 0x00000001 // Output Ready Status
+#define AES_CTRL_CCM_M_S 22
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_C_LENGTH_0
+// register.
+//
+//*****************************************************************************
+#define AES_C_LENGTH_0_LENGTH_M 0xFFFFFFFF // Data Length
+#define AES_C_LENGTH_0_LENGTH_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_C_LENGTH_1
+// register.
+//
+//*****************************************************************************
+#define AES_C_LENGTH_1_LENGTH_M 0xFFFFFFFF // Data Length
+#define AES_C_LENGTH_1_LENGTH_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_AUTH_LENGTH
+// register.
+//
+//*****************************************************************************
+#define AES_AUTH_LENGTH_AUTH_M 0xFFFFFFFF // Authentication Data Length
+#define AES_AUTH_LENGTH_AUTH_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DATA_IN_0
+// register.
+//
+//*****************************************************************************
+#define AES_DATA_IN_0_DATA_M 0xFFFFFFFF // Secure Data RW
+ // Plaintext/Ciphertext
+#define AES_DATA_IN_0_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DATA_IN_1
+// register.
+//
+//*****************************************************************************
+#define AES_DATA_IN_1_DATA_M 0xFFFFFFFF // Secure Data RW
+ // Plaintext/Ciphertext
+#define AES_DATA_IN_1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DATA_IN_2
+// register.
+//
+//*****************************************************************************
+#define AES_DATA_IN_2_DATA_M 0xFFFFFFFF // Secure Data RW
+ // Plaintext/Ciphertext
+#define AES_DATA_IN_2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DATA_IN_3
+// register.
+//
+//*****************************************************************************
+#define AES_DATA_IN_3_DATA_M 0xFFFFFFFF // Secure Data RW
+ // Plaintext/Ciphertext
+#define AES_DATA_IN_3_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_TAG_OUT_0
+// register.
+//
+//*****************************************************************************
+#define AES_TAG_OUT_0_HASH_M 0xFFFFFFFF // Hash Result
+#define AES_TAG_OUT_0_HASH_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_TAG_OUT_1
+// register.
+//
+//*****************************************************************************
+#define AES_TAG_OUT_1_HASH_M 0xFFFFFFFF // Hash Result
+#define AES_TAG_OUT_1_HASH_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_TAG_OUT_2
+// register.
+//
+//*****************************************************************************
+#define AES_TAG_OUT_2_HASH_M 0xFFFFFFFF // Hash Result
+#define AES_TAG_OUT_2_HASH_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_TAG_OUT_3
+// register.
+//
+//*****************************************************************************
+#define AES_TAG_OUT_3_HASH_M 0xFFFFFFFF // Hash Result
+#define AES_TAG_OUT_3_HASH_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_REVISION register.
+//
+//*****************************************************************************
+#define AES_REVISION_M 0xFFFFFFFF // Revision number
+#define AES_REVISION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_SYSCONFIG
+// register.
+//
+//*****************************************************************************
+#define AES_SYSCONFIG_K3 0x00001000 // K3 Select
+#define AES_SYSCONFIG_KEYENC 0x00000800 // Key Encoding
+#define AES_SYSCONFIG_MAP_CONTEXT_OUT_ON_DATA_OUT \
+ 0x00000200 // Map Context Out on Data Out
+ // Enable
+#define AES_SYSCONFIG_DMA_REQ_CONTEXT_OUT_EN \
+ 0x00000100 // DMA Request Context Out Enable
+#define AES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \
+ 0x00000080 // DMA Request Context In Enable
+#define AES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \
+ 0x00000040 // DMA Request Data Out Enable
+#define AES_SYSCONFIG_DMA_REQ_DATA_IN_EN \
+ 0x00000020 // DMA Request Data In Enable
+#define AES_SYSCONFIG_SOFTRESET 0x00000002 // Soft reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_SYSSTATUS
+// register.
+//
+//*****************************************************************************
+#define AES_SYSSTATUS_RESETDONE 0x00000001 // Reset Done
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_IRQSTATUS
+// register.
+//
+//*****************************************************************************
+#define AES_IRQSTATUS_CONTEXT_OUT \
+ 0x00000008 // Context Output Interrupt Status
+#define AES_IRQSTATUS_DATA_OUT 0x00000004 // Data Out Interrupt Status
+#define AES_IRQSTATUS_DATA_IN 0x00000002 // Data In Interrupt Status
+#define AES_IRQSTATUS_CONTEXT_IN \
+ 0x00000001 // Context In Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_IRQENABLE
+// register.
+//
+//*****************************************************************************
+#define AES_IRQENABLE_CONTEXT_OUT \
+ 0x00000008 // Context Out Interrupt Enable
+#define AES_IRQENABLE_DATA_OUT 0x00000004 // Data Out Interrupt Enable
+#define AES_IRQENABLE_DATA_IN 0x00000002 // Data In Interrupt Enable
+#define AES_IRQENABLE_CONTEXT_IN \
+ 0x00000001 // Context In Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DIRTYBITS
+// register.
+//
+//*****************************************************************************
+#define AES_DIRTYBITS_S_DIRTY 0x00000002 // AES Dirty Bit
+#define AES_DIRTYBITS_S_ACCESS 0x00000001 // AES Access Bit
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DMAIM register.
+//
+//*****************************************************************************
+#define AES_DMAIM_DOUT 0x00000008 // Data Out DMA Done Interrupt Mask
+#define AES_DMAIM_DIN 0x00000004 // Data In DMA Done Interrupt Mask
+#define AES_DMAIM_COUT 0x00000002 // Context Out DMA Done Interrupt
+ // Mask
+#define AES_DMAIM_CIN 0x00000001 // Context In DMA Done Interrupt
+ // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DMARIS register.
+//
+//*****************************************************************************
+#define AES_DMARIS_DOUT 0x00000008 // Data Out DMA Done Raw Interrupt
+ // Status
+#define AES_DMARIS_DIN 0x00000004 // Data In DMA Done Raw Interrupt
+ // Status
+#define AES_DMARIS_COUT 0x00000002 // Context Out DMA Done Raw
+ // Interrupt Status
+#define AES_DMARIS_CIN 0x00000001 // Context In DMA Done Raw
+ // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DMAMIS register.
+//
+//*****************************************************************************
+#define AES_DMAMIS_DOUT 0x00000008 // Data Out DMA Done Masked
+ // Interrupt Status
+#define AES_DMAMIS_DIN 0x00000004 // Data In DMA Done Masked
+ // Interrupt Status
+#define AES_DMAMIS_COUT 0x00000002 // Context Out DMA Done Masked
+ // Interrupt Status
+#define AES_DMAMIS_CIN 0x00000001 // Context In DMA Done Raw
+ // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the AES_O_DMAIC register.
+//
+//*****************************************************************************
+#define AES_DMAIC_DOUT 0x00000008 // Data Out DMA Done Interrupt
+ // Clear
+#define AES_DMAIC_DIN 0x00000004 // Data In DMA Done Interrupt Clear
+#define AES_DMAIC_COUT 0x00000002 // Context Out DMA Done Masked
+ // Interrupt Status
+#define AES_DMAIC_CIN 0x00000001 // Context In DMA Done Raw
+ // Interrupt Status
+
+#endif // __HW_AES_H__
diff --git a/os/common/ext/TivaWare/inc/hw_can.h b/os/common/ext/TivaWare/inc/hw_can.h
new file mode 100644
index 0000000..a683e67
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_can.h
@@ -0,0 +1,462 @@
+//*****************************************************************************
+//
+// hw_can.h - Defines and macros used when accessing the CAN controllers.
+//
+// Copyright (c) 2006-2016 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_CAN_H__
+#define __HW_CAN_H__
+
+//*****************************************************************************
+//
+// The following are defines for the CAN register offsets.
+//
+//*****************************************************************************
+#define CAN_O_CTL 0x00000000 // CAN Control
+#define CAN_O_STS 0x00000004 // CAN Status
+#define CAN_O_ERR 0x00000008 // CAN Error Counter
+#define CAN_O_BIT 0x0000000C // CAN Bit Timing
+#define CAN_O_INT 0x00000010 // CAN Interrupt
+#define CAN_O_TST 0x00000014 // CAN Test
+#define CAN_O_BRPE 0x00000018 // CAN Baud Rate Prescaler
+ // Extension
+#define CAN_O_IF1CRQ 0x00000020 // CAN IF1 Command Request
+#define CAN_O_IF1CMSK 0x00000024 // CAN IF1 Command Mask
+#define CAN_O_IF1MSK1 0x00000028 // CAN IF1 Mask 1
+#define CAN_O_IF1MSK2 0x0000002C // CAN IF1 Mask 2
+#define CAN_O_IF1ARB1 0x00000030 // CAN IF1 Arbitration 1
+#define CAN_O_IF1ARB2 0x00000034 // CAN IF1 Arbitration 2
+#define CAN_O_IF1MCTL 0x00000038 // CAN IF1 Message Control
+#define CAN_O_IF1DA1 0x0000003C // CAN IF1 Data A1
+#define CAN_O_IF1DA2 0x00000040 // CAN IF1 Data A2
+#define CAN_O_IF1DB1 0x00000044 // CAN IF1 Data B1
+#define CAN_O_IF1DB2 0x00000048 // CAN IF1 Data B2
+#define CAN_O_IF2CRQ 0x00000080 // CAN IF2 Command Request
+#define CAN_O_IF2CMSK 0x00000084 // CAN IF2 Command Mask
+#define CAN_O_IF2MSK1 0x00000088 // CAN IF2 Mask 1
+#define CAN_O_IF2MSK2 0x0000008C // CAN IF2 Mask 2
+#define CAN_O_IF2ARB1 0x00000090 // CAN IF2 Arbitration 1
+#define CAN_O_IF2ARB2 0x00000094 // CAN IF2 Arbitration 2
+#define CAN_O_IF2MCTL 0x00000098 // CAN IF2 Message Control
+#define CAN_O_IF2DA1 0x0000009C // CAN IF2 Data A1
+#define CAN_O_IF2DA2 0x000000A0 // CAN IF2 Data A2
+#define CAN_O_IF2DB1 0x000000A4 // CAN IF2 Data B1
+#define CAN_O_IF2DB2 0x000000A8 // CAN IF2 Data B2
+#define CAN_O_TXRQ1 0x00000100 // CAN Transmission Request 1
+#define CAN_O_TXRQ2 0x00000104 // CAN Transmission Request 2
+#define CAN_O_NWDA1 0x00000120 // CAN New Data 1
+#define CAN_O_NWDA2 0x00000124 // CAN New Data 2
+#define CAN_O_MSG1INT 0x00000140 // CAN Message 1 Interrupt Pending
+#define CAN_O_MSG2INT 0x00000144 // CAN Message 2 Interrupt Pending
+#define CAN_O_MSG1VAL 0x00000160 // CAN Message 1 Valid
+#define CAN_O_MSG2VAL 0x00000164 // CAN Message 2 Valid
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_CTL register.
+//
+//*****************************************************************************
+#define CAN_CTL_TEST 0x00000080 // Test Mode Enable
+#define CAN_CTL_CCE 0x00000040 // Configuration Change Enable
+#define CAN_CTL_DAR 0x00000020 // Disable Automatic-Retransmission
+#define CAN_CTL_EIE 0x00000008 // Error Interrupt Enable
+#define CAN_CTL_SIE 0x00000004 // Status Interrupt Enable
+#define CAN_CTL_IE 0x00000002 // CAN Interrupt Enable
+#define CAN_CTL_INIT 0x00000001 // Initialization
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_STS register.
+//
+//*****************************************************************************
+#define CAN_STS_BOFF 0x00000080 // Bus-Off Status
+#define CAN_STS_EWARN 0x00000040 // Warning Status
+#define CAN_STS_EPASS 0x00000020 // Error Passive
+#define CAN_STS_RXOK 0x00000010 // Received a Message Successfully
+#define CAN_STS_TXOK 0x00000008 // Transmitted a Message
+ // Successfully
+#define CAN_STS_LEC_M 0x00000007 // Last Error Code
+#define CAN_STS_LEC_NONE 0x00000000 // No Error
+#define CAN_STS_LEC_STUFF 0x00000001 // Stuff Error
+#define CAN_STS_LEC_FORM 0x00000002 // Format Error
+#define CAN_STS_LEC_ACK 0x00000003 // ACK Error
+#define CAN_STS_LEC_BIT1 0x00000004 // Bit 1 Error
+#define CAN_STS_LEC_BIT0 0x00000005 // Bit 0 Error
+#define CAN_STS_LEC_CRC 0x00000006 // CRC Error
+#define CAN_STS_LEC_NOEVENT 0x00000007 // No Event
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_ERR register.
+//
+//*****************************************************************************
+#define CAN_ERR_RP 0x00008000 // Received Error Passive
+#define CAN_ERR_REC_M 0x00007F00 // Receive Error Counter
+#define CAN_ERR_TEC_M 0x000000FF // Transmit Error Counter
+#define CAN_ERR_REC_S 8
+#define CAN_ERR_TEC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_BIT register.
+//
+//*****************************************************************************
+#define CAN_BIT_TSEG2_M 0x00007000 // Time Segment after Sample Point
+#define CAN_BIT_TSEG1_M 0x00000F00 // Time Segment Before Sample Point
+#define CAN_BIT_SJW_M 0x000000C0 // (Re)Synchronization Jump Width
+#define CAN_BIT_BRP_M 0x0000003F // Baud Rate Prescaler
+#define CAN_BIT_TSEG2_S 12
+#define CAN_BIT_TSEG1_S 8
+#define CAN_BIT_SJW_S 6
+#define CAN_BIT_BRP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_INT register.
+//
+//*****************************************************************************
+#define CAN_INT_INTID_M 0x0000FFFF // Interrupt Identifier
+#define CAN_INT_INTID_NONE 0x00000000 // No interrupt pending
+#define CAN_INT_INTID_STATUS 0x00008000 // Status Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TST register.
+//
+//*****************************************************************************
+#define CAN_TST_RX 0x00000080 // Receive Observation
+#define CAN_TST_TX_M 0x00000060 // Transmit Control
+#define CAN_TST_TX_CANCTL 0x00000000 // CAN Module Control
+#define CAN_TST_TX_SAMPLE 0x00000020 // Sample Point
+#define CAN_TST_TX_DOMINANT 0x00000040 // Driven Low
+#define CAN_TST_TX_RECESSIVE 0x00000060 // Driven High
+#define CAN_TST_LBACK 0x00000010 // Loopback Mode
+#define CAN_TST_SILENT 0x00000008 // Silent Mode
+#define CAN_TST_BASIC 0x00000004 // Basic Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_BRPE register.
+//
+//*****************************************************************************
+#define CAN_BRPE_BRPE_M 0x0000000F // Baud Rate Prescaler Extension
+#define CAN_BRPE_BRPE_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1CRQ register.
+//
+//*****************************************************************************
+#define CAN_IF1CRQ_BUSY 0x00008000 // Busy Flag
+#define CAN_IF1CRQ_MNUM_M 0x0000003F // Message Number
+#define CAN_IF1CRQ_MNUM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1CMSK register.
+//
+//*****************************************************************************
+#define CAN_IF1CMSK_WRNRD 0x00000080 // Write, Not Read
+#define CAN_IF1CMSK_MASK 0x00000040 // Access Mask Bits
+#define CAN_IF1CMSK_ARB 0x00000020 // Access Arbitration Bits
+#define CAN_IF1CMSK_CONTROL 0x00000010 // Access Control Bits
+#define CAN_IF1CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit
+#define CAN_IF1CMSK_NEWDAT 0x00000004 // Access New Data
+#define CAN_IF1CMSK_TXRQST 0x00000004 // Access Transmission Request
+#define CAN_IF1CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3
+#define CAN_IF1CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MSK1 register.
+//
+//*****************************************************************************
+#define CAN_IF1MSK1_IDMSK_M 0x0000FFFF // Identifier Mask
+#define CAN_IF1MSK1_IDMSK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MSK2 register.
+//
+//*****************************************************************************
+#define CAN_IF1MSK2_MXTD 0x00008000 // Mask Extended Identifier
+#define CAN_IF1MSK2_MDIR 0x00004000 // Mask Message Direction
+#define CAN_IF1MSK2_IDMSK_M 0x00001FFF // Identifier Mask
+#define CAN_IF1MSK2_IDMSK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1ARB1 register.
+//
+//*****************************************************************************
+#define CAN_IF1ARB1_ID_M 0x0000FFFF // Message Identifier
+#define CAN_IF1ARB1_ID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1ARB2 register.
+//
+//*****************************************************************************
+#define CAN_IF1ARB2_MSGVAL 0x00008000 // Message Valid
+#define CAN_IF1ARB2_XTD 0x00004000 // Extended Identifier
+#define CAN_IF1ARB2_DIR 0x00002000 // Message Direction
+#define CAN_IF1ARB2_ID_M 0x00001FFF // Message Identifier
+#define CAN_IF1ARB2_ID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1MCTL register.
+//
+//*****************************************************************************
+#define CAN_IF1MCTL_NEWDAT 0x00008000 // New Data
+#define CAN_IF1MCTL_MSGLST 0x00004000 // Message Lost
+#define CAN_IF1MCTL_INTPND 0x00002000 // Interrupt Pending
+#define CAN_IF1MCTL_UMASK 0x00001000 // Use Acceptance Mask
+#define CAN_IF1MCTL_TXIE 0x00000800 // Transmit Interrupt Enable
+#define CAN_IF1MCTL_RXIE 0x00000400 // Receive Interrupt Enable
+#define CAN_IF1MCTL_RMTEN 0x00000200 // Remote Enable
+#define CAN_IF1MCTL_TXRQST 0x00000100 // Transmit Request
+#define CAN_IF1MCTL_EOB 0x00000080 // End of Buffer
+#define CAN_IF1MCTL_DLC_M 0x0000000F // Data Length Code
+#define CAN_IF1MCTL_DLC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DA1 register.
+//
+//*****************************************************************************
+#define CAN_IF1DA1_DATA_M 0x0000FFFF // Data
+#define CAN_IF1DA1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DA2 register.
+//
+//*****************************************************************************
+#define CAN_IF1DA2_DATA_M 0x0000FFFF // Data
+#define CAN_IF1DA2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DB1 register.
+//
+//*****************************************************************************
+#define CAN_IF1DB1_DATA_M 0x0000FFFF // Data
+#define CAN_IF1DB1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF1DB2 register.
+//
+//*****************************************************************************
+#define CAN_IF1DB2_DATA_M 0x0000FFFF // Data
+#define CAN_IF1DB2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2CRQ register.
+//
+//*****************************************************************************
+#define CAN_IF2CRQ_BUSY 0x00008000 // Busy Flag
+#define CAN_IF2CRQ_MNUM_M 0x0000003F // Message Number
+#define CAN_IF2CRQ_MNUM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2CMSK register.
+//
+//*****************************************************************************
+#define CAN_IF2CMSK_WRNRD 0x00000080 // Write, Not Read
+#define CAN_IF2CMSK_MASK 0x00000040 // Access Mask Bits
+#define CAN_IF2CMSK_ARB 0x00000020 // Access Arbitration Bits
+#define CAN_IF2CMSK_CONTROL 0x00000010 // Access Control Bits
+#define CAN_IF2CMSK_CLRINTPND 0x00000008 // Clear Interrupt Pending Bit
+#define CAN_IF2CMSK_NEWDAT 0x00000004 // Access New Data
+#define CAN_IF2CMSK_TXRQST 0x00000004 // Access Transmission Request
+#define CAN_IF2CMSK_DATAA 0x00000002 // Access Data Byte 0 to 3
+#define CAN_IF2CMSK_DATAB 0x00000001 // Access Data Byte 4 to 7
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MSK1 register.
+//
+//*****************************************************************************
+#define CAN_IF2MSK1_IDMSK_M 0x0000FFFF // Identifier Mask
+#define CAN_IF2MSK1_IDMSK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MSK2 register.
+//
+//*****************************************************************************
+#define CAN_IF2MSK2_MXTD 0x00008000 // Mask Extended Identifier
+#define CAN_IF2MSK2_MDIR 0x00004000 // Mask Message Direction
+#define CAN_IF2MSK2_IDMSK_M 0x00001FFF // Identifier Mask
+#define CAN_IF2MSK2_IDMSK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2ARB1 register.
+//
+//*****************************************************************************
+#define CAN_IF2ARB1_ID_M 0x0000FFFF // Message Identifier
+#define CAN_IF2ARB1_ID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2ARB2 register.
+//
+//*****************************************************************************
+#define CAN_IF2ARB2_MSGVAL 0x00008000 // Message Valid
+#define CAN_IF2ARB2_XTD 0x00004000 // Extended Identifier
+#define CAN_IF2ARB2_DIR 0x00002000 // Message Direction
+#define CAN_IF2ARB2_ID_M 0x00001FFF // Message Identifier
+#define CAN_IF2ARB2_ID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2MCTL register.
+//
+//*****************************************************************************
+#define CAN_IF2MCTL_NEWDAT 0x00008000 // New Data
+#define CAN_IF2MCTL_MSGLST 0x00004000 // Message Lost
+#define CAN_IF2MCTL_INTPND 0x00002000 // Interrupt Pending
+#define CAN_IF2MCTL_UMASK 0x00001000 // Use Acceptance Mask
+#define CAN_IF2MCTL_TXIE 0x00000800 // Transmit Interrupt Enable
+#define CAN_IF2MCTL_RXIE 0x00000400 // Receive Interrupt Enable
+#define CAN_IF2MCTL_RMTEN 0x00000200 // Remote Enable
+#define CAN_IF2MCTL_TXRQST 0x00000100 // Transmit Request
+#define CAN_IF2MCTL_EOB 0x00000080 // End of Buffer
+#define CAN_IF2MCTL_DLC_M 0x0000000F // Data Length Code
+#define CAN_IF2MCTL_DLC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DA1 register.
+//
+//*****************************************************************************
+#define CAN_IF2DA1_DATA_M 0x0000FFFF // Data
+#define CAN_IF2DA1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DA2 register.
+//
+//*****************************************************************************
+#define CAN_IF2DA2_DATA_M 0x0000FFFF // Data
+#define CAN_IF2DA2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DB1 register.
+//
+//*****************************************************************************
+#define CAN_IF2DB1_DATA_M 0x0000FFFF // Data
+#define CAN_IF2DB1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_IF2DB2 register.
+//
+//*****************************************************************************
+#define CAN_IF2DB2_DATA_M 0x0000FFFF // Data
+#define CAN_IF2DB2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TXRQ1 register.
+//
+//*****************************************************************************
+#define CAN_TXRQ1_TXRQST_M 0x0000FFFF // Transmission Request Bits
+#define CAN_TXRQ1_TXRQST_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_TXRQ2 register.
+//
+//*****************************************************************************
+#define CAN_TXRQ2_TXRQST_M 0x0000FFFF // Transmission Request Bits
+#define CAN_TXRQ2_TXRQST_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_NWDA1 register.
+//
+//*****************************************************************************
+#define CAN_NWDA1_NEWDAT_M 0x0000FFFF // New Data Bits
+#define CAN_NWDA1_NEWDAT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_NWDA2 register.
+//
+//*****************************************************************************
+#define CAN_NWDA2_NEWDAT_M 0x0000FFFF // New Data Bits
+#define CAN_NWDA2_NEWDAT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG1INT register.
+//
+//*****************************************************************************
+#define CAN_MSG1INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits
+#define CAN_MSG1INT_INTPND_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG2INT register.
+//
+//*****************************************************************************
+#define CAN_MSG2INT_INTPND_M 0x0000FFFF // Interrupt Pending Bits
+#define CAN_MSG2INT_INTPND_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG1VAL register.
+//
+//*****************************************************************************
+#define CAN_MSG1VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits
+#define CAN_MSG1VAL_MSGVAL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CAN_O_MSG2VAL register.
+//
+//*****************************************************************************
+#define CAN_MSG2VAL_MSGVAL_M 0x0000FFFF // Message Valid Bits
+#define CAN_MSG2VAL_MSGVAL_S 0
+
+#endif // __HW_CAN_H__
diff --git a/os/common/ext/TivaWare/inc/hw_ccm.h b/os/common/ext/TivaWare/inc/hw_ccm.h
new file mode 100644
index 0000000..19041b6
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_ccm.h
@@ -0,0 +1,115 @@
+//*****************************************************************************
+//
+// hw_ccm.h - Macros used when accessing the CCM hardware.
+//
+// Copyright (c) 2012-2016 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_CCM_H__
+#define __HW_CCM_H__
+
+//*****************************************************************************
+//
+// The following are defines for the EC register offsets.
+//
+//*****************************************************************************
+#define CCM_O_CRCCTRL 0x00000400 // CRC Control
+#define CCM_O_CRCSEED 0x00000410 // CRC SEED/Context
+#define CCM_O_CRCDIN 0x00000414 // CRC Data Input
+#define CCM_O_CRCRSLTPP 0x00000418 // CRC Post Processing Result
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CCM_O_CRCCTRL register.
+//
+//*****************************************************************************
+#define CCM_CRCCTRL_INIT_M 0x00006000 // CRC Initialization
+#define CCM_CRCCTRL_INIT_SEED 0x00000000 // Use the CRCSEED register context
+ // as the starting value
+#define CCM_CRCCTRL_INIT_0 0x00004000 // Initialize to all '0s'
+#define CCM_CRCCTRL_INIT_1 0x00006000 // Initialize to all '1s'
+#define CCM_CRCCTRL_SIZE 0x00001000 // Input Data Size
+#define CCM_CRCCTRL_RESINV 0x00000200 // Result Inverse Enable
+#define CCM_CRCCTRL_OBR 0x00000100 // Output Reverse Enable
+#define CCM_CRCCTRL_BR 0x00000080 // Bit reverse enable
+#define CCM_CRCCTRL_ENDIAN_M 0x00000030 // Endian Control
+#define CCM_CRCCTRL_ENDIAN_SBHW 0x00000000 // Configuration unchanged. (B3,
+ // B2, B1, B0)
+#define CCM_CRCCTRL_ENDIAN_SHW 0x00000010 // Bytes are swapped in half-words
+ // but half-words are not swapped
+ // (B2, B3, B0, B1)
+#define CCM_CRCCTRL_ENDIAN_SHWNB \
+ 0x00000020 // Half-words are swapped but bytes
+ // are not swapped in half-word.
+ // (B1, B0, B3, B2)
+#define CCM_CRCCTRL_ENDIAN_SBSW 0x00000030 // Bytes are swapped in half-words
+ // and half-words are swapped. (B0,
+ // B1, B2, B3)
+#define CCM_CRCCTRL_TYPE_M 0x0000000F // Operation Type
+#define CCM_CRCCTRL_TYPE_P8055 0x00000000 // Polynomial 0x8005
+#define CCM_CRCCTRL_TYPE_P1021 0x00000001 // Polynomial 0x1021
+#define CCM_CRCCTRL_TYPE_P4C11DB7 \
+ 0x00000002 // Polynomial 0x4C11DB7
+#define CCM_CRCCTRL_TYPE_P1EDC6F41 \
+ 0x00000003 // Polynomial 0x1EDC6F41
+#define CCM_CRCCTRL_TYPE_TCPCHKSUM \
+ 0x00000008 // TCP checksum
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CCM_O_CRCSEED register.
+//
+//*****************************************************************************
+#define CCM_CRCSEED_SEED_M 0xFFFFFFFF // SEED/Context Value
+#define CCM_CRCSEED_SEED_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CCM_O_CRCDIN register.
+//
+//*****************************************************************************
+#define CCM_CRCDIN_DATAIN_M 0xFFFFFFFF // Data Input
+#define CCM_CRCDIN_DATAIN_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the CCM_O_CRCRSLTPP
+// register.
+//
+//*****************************************************************************
+#define CCM_CRCRSLTPP_RSLTPP_M 0xFFFFFFFF // Post Processing Result
+#define CCM_CRCRSLTPP_RSLTPP_S 0
+
+#endif // __HW_CCM_H__
diff --git a/os/common/ext/TivaWare/inc/hw_comp.h b/os/common/ext/TivaWare/inc/hw_comp.h
new file mode 100644
index 0000000..aea2f84
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_comp.h
@@ -0,0 +1,211 @@
+//*****************************************************************************
+//
+// hw_comp.h - Macros used when accessing the comparator hardware.
+//
+// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_COMP_H__
+#define __HW_COMP_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Comparator register offsets.
+//
+//*****************************************************************************
+#define COMP_O_ACMIS 0x00000000 // Analog Comparator Masked
+ // Interrupt Status
+#define COMP_O_ACRIS 0x00000004 // Analog Comparator Raw Interrupt
+ // Status
+#define COMP_O_ACINTEN 0x00000008 // Analog Comparator Interrupt
+ // Enable
+#define COMP_O_ACREFCTL 0x00000010 // Analog Comparator Reference
+ // Voltage Control
+#define COMP_O_ACSTAT0 0x00000020 // Analog Comparator Status 0
+#define COMP_O_ACCTL0 0x00000024 // Analog Comparator Control 0
+#define COMP_O_ACSTAT1 0x00000040 // Analog Comparator Status 1
+#define COMP_O_ACCTL1 0x00000044 // Analog Comparator Control 1
+#define COMP_O_ACSTAT2 0x00000060 // Analog Comparator Status 2
+#define COMP_O_ACCTL2 0x00000064 // Analog Comparator Control 2
+#define COMP_O_PP 0x00000FC0 // Analog Comparator Peripheral
+ // Properties
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACMIS register.
+//
+//*****************************************************************************
+#define COMP_ACMIS_IN2 0x00000004 // Comparator 2 Masked Interrupt
+ // Status
+#define COMP_ACMIS_IN1 0x00000002 // Comparator 1 Masked Interrupt
+ // Status
+#define COMP_ACMIS_IN0 0x00000001 // Comparator 0 Masked Interrupt
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACRIS register.
+//
+//*****************************************************************************
+#define COMP_ACRIS_IN2 0x00000004 // Comparator 2 Interrupt Status
+#define COMP_ACRIS_IN1 0x00000002 // Comparator 1 Interrupt Status
+#define COMP_ACRIS_IN0 0x00000001 // Comparator 0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACINTEN register.
+//
+//*****************************************************************************
+#define COMP_ACINTEN_IN2 0x00000004 // Comparator 2 Interrupt Enable
+#define COMP_ACINTEN_IN1 0x00000002 // Comparator 1 Interrupt Enable
+#define COMP_ACINTEN_IN0 0x00000001 // Comparator 0 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACREFCTL
+// register.
+//
+//*****************************************************************************
+#define COMP_ACREFCTL_EN 0x00000200 // Resistor Ladder Enable
+#define COMP_ACREFCTL_RNG 0x00000100 // Resistor Ladder Range
+#define COMP_ACREFCTL_VREF_M 0x0000000F // Resistor Ladder Voltage Ref
+#define COMP_ACREFCTL_VREF_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT0 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT0_OVAL 0x00000002 // Comparator Output Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL0 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL0_TOEN 0x00000800 // Trigger Output Enable
+#define COMP_ACCTL0_ASRCP_M 0x00000600 // Analog Source Positive
+#define COMP_ACCTL0_ASRCP_PIN 0x00000000 // Pin value of Cn+
+#define COMP_ACCTL0_ASRCP_PIN0 0x00000200 // Pin value of C0+
+#define COMP_ACCTL0_ASRCP_REF 0x00000400 // Internal voltage reference
+#define COMP_ACCTL0_TSLVAL 0x00000080 // Trigger Sense Level Value
+#define COMP_ACCTL0_TSEN_M 0x00000060 // Trigger Sense
+#define COMP_ACCTL0_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
+#define COMP_ACCTL0_TSEN_FALL 0x00000020 // Falling edge
+#define COMP_ACCTL0_TSEN_RISE 0x00000040 // Rising edge
+#define COMP_ACCTL0_TSEN_BOTH 0x00000060 // Either edge
+#define COMP_ACCTL0_ISLVAL 0x00000010 // Interrupt Sense Level Value
+#define COMP_ACCTL0_ISEN_M 0x0000000C // Interrupt Sense
+#define COMP_ACCTL0_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
+#define COMP_ACCTL0_ISEN_FALL 0x00000004 // Falling edge
+#define COMP_ACCTL0_ISEN_RISE 0x00000008 // Rising edge
+#define COMP_ACCTL0_ISEN_BOTH 0x0000000C // Either edge
+#define COMP_ACCTL0_CINV 0x00000002 // Comparator Output Invert
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT1 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT1_OVAL 0x00000002 // Comparator Output Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL1 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL1_TOEN 0x00000800 // Trigger Output Enable
+#define COMP_ACCTL1_ASRCP_M 0x00000600 // Analog Source Positive
+#define COMP_ACCTL1_ASRCP_PIN 0x00000000 // Pin value of Cn+
+#define COMP_ACCTL1_ASRCP_PIN0 0x00000200 // Pin value of C0+
+#define COMP_ACCTL1_ASRCP_REF 0x00000400 // Internal voltage reference
+#define COMP_ACCTL1_TSLVAL 0x00000080 // Trigger Sense Level Value
+#define COMP_ACCTL1_TSEN_M 0x00000060 // Trigger Sense
+#define COMP_ACCTL1_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
+#define COMP_ACCTL1_TSEN_FALL 0x00000020 // Falling edge
+#define COMP_ACCTL1_TSEN_RISE 0x00000040 // Rising edge
+#define COMP_ACCTL1_TSEN_BOTH 0x00000060 // Either edge
+#define COMP_ACCTL1_ISLVAL 0x00000010 // Interrupt Sense Level Value
+#define COMP_ACCTL1_ISEN_M 0x0000000C // Interrupt Sense
+#define COMP_ACCTL1_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
+#define COMP_ACCTL1_ISEN_FALL 0x00000004 // Falling edge
+#define COMP_ACCTL1_ISEN_RISE 0x00000008 // Rising edge
+#define COMP_ACCTL1_ISEN_BOTH 0x0000000C // Either edge
+#define COMP_ACCTL1_CINV 0x00000002 // Comparator Output Invert
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACSTAT2 register.
+//
+//*****************************************************************************
+#define COMP_ACSTAT2_OVAL 0x00000002 // Comparator Output Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_ACCTL2 register.
+//
+//*****************************************************************************
+#define COMP_ACCTL2_TOEN 0x00000800 // Trigger Output Enable
+#define COMP_ACCTL2_ASRCP_M 0x00000600 // Analog Source Positive
+#define COMP_ACCTL2_ASRCP_PIN 0x00000000 // Pin value of Cn+
+#define COMP_ACCTL2_ASRCP_PIN0 0x00000200 // Pin value of C0+
+#define COMP_ACCTL2_ASRCP_REF 0x00000400 // Internal voltage reference
+#define COMP_ACCTL2_TSLVAL 0x00000080 // Trigger Sense Level Value
+#define COMP_ACCTL2_TSEN_M 0x00000060 // Trigger Sense
+#define COMP_ACCTL2_TSEN_LEVEL 0x00000000 // Level sense, see TSLVAL
+#define COMP_ACCTL2_TSEN_FALL 0x00000020 // Falling edge
+#define COMP_ACCTL2_TSEN_RISE 0x00000040 // Rising edge
+#define COMP_ACCTL2_TSEN_BOTH 0x00000060 // Either edge
+#define COMP_ACCTL2_ISLVAL 0x00000010 // Interrupt Sense Level Value
+#define COMP_ACCTL2_ISEN_M 0x0000000C // Interrupt Sense
+#define COMP_ACCTL2_ISEN_LEVEL 0x00000000 // Level sense, see ISLVAL
+#define COMP_ACCTL2_ISEN_FALL 0x00000004 // Falling edge
+#define COMP_ACCTL2_ISEN_RISE 0x00000008 // Rising edge
+#define COMP_ACCTL2_ISEN_BOTH 0x0000000C // Either edge
+#define COMP_ACCTL2_CINV 0x00000002 // Comparator Output Invert
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the COMP_O_PP register.
+//
+//*****************************************************************************
+#define COMP_PP_C2O 0x00040000 // Comparator Output 2 Present
+#define COMP_PP_C1O 0x00020000 // Comparator Output 1 Present
+#define COMP_PP_C0O 0x00010000 // Comparator Output 0 Present
+#define COMP_PP_CMP2 0x00000004 // Comparator 2 Present
+#define COMP_PP_CMP1 0x00000002 // Comparator 1 Present
+#define COMP_PP_CMP0 0x00000001 // Comparator 0 Present
+
+#endif // __HW_COMP_H__
diff --git a/os/common/ext/TivaWare/inc/hw_des.h b/os/common/ext/TivaWare/inc/hw_des.h
new file mode 100644
index 0000000..da46c52
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_des.h
@@ -0,0 +1,310 @@
+//*****************************************************************************
+//
+// hw_des.h - Macros used when accessing the DES hardware.
+//
+// Copyright (c) 2012-2016 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_DES_H__
+#define __HW_DES_H__
+
+//*****************************************************************************
+//
+// The following are defines for the DES register offsets.
+//
+//*****************************************************************************
+#define DES_O_KEY3_L 0x00000000 // DES Key 3 LSW for 192-Bit Key
+#define DES_O_KEY3_H 0x00000004 // DES Key 3 MSW for 192-Bit Key
+#define DES_O_KEY2_L 0x00000008 // DES Key 2 LSW for 128-Bit Key
+#define DES_O_KEY2_H 0x0000000C // DES Key 2 MSW for 128-Bit Key
+#define DES_O_KEY1_L 0x00000010 // DES Key 1 LSW for 64-Bit Key
+#define DES_O_KEY1_H 0x00000014 // DES Key 1 MSW for 64-Bit Key
+#define DES_O_IV_L 0x00000018 // DES Initialization Vector
+#define DES_O_IV_H 0x0000001C // DES Initialization Vector
+#define DES_O_CTRL 0x00000020 // DES Control
+#define DES_O_LENGTH 0x00000024 // DES Cryptographic Data Length
+#define DES_O_DATA_L 0x00000028 // DES LSW Data RW
+#define DES_O_DATA_H 0x0000002C // DES MSW Data RW
+#define DES_O_REVISION 0x00000030 // DES Revision Number
+#define DES_O_SYSCONFIG 0x00000034 // DES System Configuration
+#define DES_O_SYSSTATUS 0x00000038 // DES System Status
+#define DES_O_IRQSTATUS 0x0000003C // DES Interrupt Status
+#define DES_O_IRQENABLE 0x00000040 // DES Interrupt Enable
+#define DES_O_DIRTYBITS 0x00000044 // DES Dirty Bits
+#define DES_O_DMAIM 0xFFFF8030 // DES DMA Interrupt Mask
+#define DES_O_DMARIS 0xFFFF8034 // DES DMA Raw Interrupt Status
+#define DES_O_DMAMIS 0xFFFF8038 // DES DMA Masked Interrupt Status
+#define DES_O_DMAIC 0xFFFF803C // DES DMA Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_KEY3_L register.
+//
+//*****************************************************************************
+#define DES_KEY3_L_KEY_M 0xFFFFFFFF // Key Data
+#define DES_KEY3_L_KEY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_KEY3_H register.
+//
+//*****************************************************************************
+#define DES_KEY3_H_KEY_M 0xFFFFFFFF // Key Data
+#define DES_KEY3_H_KEY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_KEY2_L register.
+//
+//*****************************************************************************
+#define DES_KEY2_L_KEY_M 0xFFFFFFFF // Key Data
+#define DES_KEY2_L_KEY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_KEY2_H register.
+//
+//*****************************************************************************
+#define DES_KEY2_H_KEY_M 0xFFFFFFFF // Key Data
+#define DES_KEY2_H_KEY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_KEY1_L register.
+//
+//*****************************************************************************
+#define DES_KEY1_L_KEY_M 0xFFFFFFFF // Key Data
+#define DES_KEY1_L_KEY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_KEY1_H register.
+//
+//*****************************************************************************
+#define DES_KEY1_H_KEY_M 0xFFFFFFFF // Key Data
+#define DES_KEY1_H_KEY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_IV_L register.
+//
+//*****************************************************************************
+#define DES_IV_L_M 0xFFFFFFFF // Initialization vector for CBC,
+ // CFB modes (LSW)
+#define DES_IV_L_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_IV_H register.
+//
+//*****************************************************************************
+#define DES_IV_H_M 0xFFFFFFFF // Initialization vector for CBC,
+ // CFB modes (MSW)
+#define DES_IV_H_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_CTRL register.
+//
+//*****************************************************************************
+#define DES_CTRL_CONTEXT 0x80000000 // If 1, this read-only status bit
+ // indicates that the context data
+ // registers can be overwritten and
+ // the host is permitted to write
+ // the next context
+#define DES_CTRL_MODE_M 0x00000030 // Select CBC, ECB or CFB mode0x0:
+ // ECB mode0x1: CBC mode0x2: CFB
+ // mode0x3: reserved
+#define DES_CTRL_TDES 0x00000008 // Select DES or triple DES
+ // encryption/decryption
+#define DES_CTRL_DIRECTION 0x00000004 // Select encryption/decryption
+ // 0x0: decryption is selected0x1:
+ // Encryption is selected
+#define DES_CTRL_INPUT_READY 0x00000002 // When 1, ready to encrypt/decrypt
+ // data
+#define DES_CTRL_OUTPUT_READY 0x00000001 // When 1, Data decrypted/encrypted
+ // ready
+#define DES_CTRL_MODE_S 4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_LENGTH register.
+//
+//*****************************************************************************
+#define DES_LENGTH_M 0xFFFFFFFF // Cryptographic data length in
+ // bytes for all modes
+#define DES_LENGTH_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_DATA_L register.
+//
+//*****************************************************************************
+#define DES_DATA_L_M 0xFFFFFFFF // Data for encryption/decryption,
+ // LSW
+#define DES_DATA_L_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_DATA_H register.
+//
+//*****************************************************************************
+#define DES_DATA_H_M 0xFFFFFFFF // Data for encryption/decryption,
+ // MSW
+#define DES_DATA_H_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_REVISION register.
+//
+//*****************************************************************************
+#define DES_REVISION_M 0xFFFFFFFF // Revision number
+#define DES_REVISION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_SYSCONFIG
+// register.
+//
+//*****************************************************************************
+#define DES_SYSCONFIG_DMA_REQ_CONTEXT_IN_EN \
+ 0x00000080 // DMA Request Context In Enable
+#define DES_SYSCONFIG_DMA_REQ_DATA_OUT_EN \
+ 0x00000040 // DMA Request Data Out Enable
+#define DES_SYSCONFIG_DMA_REQ_DATA_IN_EN \
+ 0x00000020 // DMA Request Data In Enable
+#define DES_SYSCONFIG_SIDLE_M 0x0000000C // Sidle mode
+#define DES_SYSCONFIG_SIDLE_FORCE \
+ 0x00000000 // Force-idle mode
+#define DES_SYSCONFIG_SOFTRESET 0x00000002 // Soft reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_SYSSTATUS
+// register.
+//
+//*****************************************************************************
+#define DES_SYSSTATUS_RESETDONE 0x00000001 // Reset Done
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_IRQSTATUS
+// register.
+//
+//*****************************************************************************
+#define DES_IRQSTATUS_DATA_OUT 0x00000004 // This bit indicates data output
+ // interrupt is active and triggers
+ // the interrupt output
+#define DES_IRQSTATUS_DATA_IN 0x00000002 // This bit indicates data input
+ // interrupt is active and triggers
+ // the interrupt output
+#define DES_IRQSTATUS_CONTEX_IN 0x00000001 // This bit indicates context
+ // interrupt is active and triggers
+ // the interrupt output
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_IRQENABLE
+// register.
+//
+//*****************************************************************************
+#define DES_IRQENABLE_M_DATA_OUT \
+ 0x00000004 // If this bit is set to 1 the data
+ // output interrupt is enabled
+#define DES_IRQENABLE_M_DATA_IN 0x00000002 // If this bit is set to 1 the data
+ // input interrupt is enabled
+#define DES_IRQENABLE_M_CONTEX_IN \
+ 0x00000001 // If this bit is set to 1 the
+ // context interrupt is enabled
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_DIRTYBITS
+// register.
+//
+//*****************************************************************************
+#define DES_DIRTYBITS_S_DIRTY 0x00000002 // This bit is set to 1 by the
+ // module if any of the DES_*
+ // registers is written
+#define DES_DIRTYBITS_S_ACCESS 0x00000001 // This bit is set to 1 by the
+ // module if any of the DES_*
+ // registers is read
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_DMAIM register.
+//
+//*****************************************************************************
+#define DES_DMAIM_DOUT 0x00000004 // Data Out DMA Done Interrupt Mask
+#define DES_DMAIM_DIN 0x00000002 // Data In DMA Done Interrupt Mask
+#define DES_DMAIM_CIN 0x00000001 // Context In DMA Done Interrupt
+ // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_DMARIS register.
+//
+//*****************************************************************************
+#define DES_DMARIS_DOUT 0x00000004 // Data Out DMA Done Raw Interrupt
+ // Status
+#define DES_DMARIS_DIN 0x00000002 // Data In DMA Done Raw Interrupt
+ // Status
+#define DES_DMARIS_CIN 0x00000001 // Context In DMA Done Raw
+ // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_DMAMIS register.
+//
+//*****************************************************************************
+#define DES_DMAMIS_DOUT 0x00000004 // Data Out DMA Done Masked
+ // Interrupt Status
+#define DES_DMAMIS_DIN 0x00000002 // Data In DMA Done Masked
+ // Interrupt Status
+#define DES_DMAMIS_CIN 0x00000001 // Context In DMA Done Raw
+ // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the DES_O_DMAIC register.
+//
+//*****************************************************************************
+#define DES_DMAIC_DOUT 0x00000004 // Data Out DMA Done Interrupt
+ // Clear
+#define DES_DMAIC_DIN 0x00000002 // Data In DMA Done Interrupt Clear
+#define DES_DMAIC_CIN 0x00000001 // Context In DMA Done Raw
+ // Interrupt Status
+
+#endif // __HW_DES_H__
diff --git a/os/common/ext/TivaWare/inc/hw_eeprom.h b/os/common/ext/TivaWare/inc/hw_eeprom.h
new file mode 100644
index 0000000..7ba282d
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_eeprom.h
@@ -0,0 +1,251 @@
+//*****************************************************************************
+//
+// hw_eeprom.h - Macros used when accessing the EEPROM controller.
+//
+// Copyright (c) 2011-2016 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_EEPROM_H__
+#define __HW_EEPROM_H__
+
+//*****************************************************************************
+//
+// The following are defines for the EEPROM register offsets.
+//
+//*****************************************************************************
+#define EEPROM_EESIZE 0x400AF000 // EEPROM Size Information
+#define EEPROM_EEBLOCK 0x400AF004 // EEPROM Current Block
+#define EEPROM_EEOFFSET 0x400AF008 // EEPROM Current Offset
+#define EEPROM_EERDWR 0x400AF010 // EEPROM Read-Write
+#define EEPROM_EERDWRINC 0x400AF014 // EEPROM Read-Write with Increment
+#define EEPROM_EEDONE 0x400AF018 // EEPROM Done Status
+#define EEPROM_EESUPP 0x400AF01C // EEPROM Support Control and
+ // Status
+#define EEPROM_EEUNLOCK 0x400AF020 // EEPROM Unlock
+#define EEPROM_EEPROT 0x400AF030 // EEPROM Protection
+#define EEPROM_EEPASS0 0x400AF034 // EEPROM Password
+#define EEPROM_EEPASS1 0x400AF038 // EEPROM Password
+#define EEPROM_EEPASS2 0x400AF03C // EEPROM Password
+#define EEPROM_EEINT 0x400AF040 // EEPROM Interrupt
+#define EEPROM_EEHIDE0 0x400AF050 // EEPROM Block Hide 0
+#define EEPROM_EEHIDE 0x400AF050 // EEPROM Block Hide
+#define EEPROM_EEHIDE1 0x400AF054 // EEPROM Block Hide 1
+#define EEPROM_EEHIDE2 0x400AF058 // EEPROM Block Hide 2
+#define EEPROM_EEDBGME 0x400AF080 // EEPROM Debug Mass Erase
+#define EEPROM_PP 0x400AFFC0 // EEPROM Peripheral Properties
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EESIZE register.
+//
+//*****************************************************************************
+#define EEPROM_EESIZE_WORDCNT_M 0x0000FFFF // Number of 32-Bit Words
+#define EEPROM_EESIZE_BLKCNT_M 0x07FF0000 // Number of 16-Word Blocks
+#define EEPROM_EESIZE_WORDCNT_S 0
+#define EEPROM_EESIZE_BLKCNT_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEBLOCK register.
+//
+//*****************************************************************************
+#define EEPROM_EEBLOCK_BLOCK_M 0x0000FFFF // Current Block
+#define EEPROM_EEBLOCK_BLOCK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEOFFSET
+// register.
+//
+//*****************************************************************************
+#define EEPROM_EEOFFSET_OFFSET_M \
+ 0x0000000F // Current Address Offset
+#define EEPROM_EEOFFSET_OFFSET_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EERDWR register.
+//
+//*****************************************************************************
+#define EEPROM_EERDWR_VALUE_M 0xFFFFFFFF // EEPROM Read or Write Data
+#define EEPROM_EERDWR_VALUE_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EERDWRINC
+// register.
+//
+//*****************************************************************************
+#define EEPROM_EERDWRINC_VALUE_M \
+ 0xFFFFFFFF // EEPROM Read or Write Data with
+ // Increment
+#define EEPROM_EERDWRINC_VALUE_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEDONE register.
+//
+//*****************************************************************************
+#define EEPROM_EEDONE_WORKING 0x00000001 // EEPROM Working
+#define EEPROM_EEDONE_WKERASE 0x00000004 // Working on an Erase
+#define EEPROM_EEDONE_WKCOPY 0x00000008 // Working on a Copy
+#define EEPROM_EEDONE_NOPERM 0x00000010 // Write Without Permission
+#define EEPROM_EEDONE_WRBUSY 0x00000020 // Write Busy
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EESUPP register.
+//
+//*****************************************************************************
+#define EEPROM_EESUPP_ERETRY 0x00000004 // Erase Must Be Retried
+#define EEPROM_EESUPP_PRETRY 0x00000008 // Programming Must Be Retried
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEUNLOCK
+// register.
+//
+//*****************************************************************************
+#define EEPROM_EEUNLOCK_UNLOCK_M \
+ 0xFFFFFFFF // EEPROM Unlock
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEPROT register.
+//
+//*****************************************************************************
+#define EEPROM_EEPROT_PROT_M 0x00000007 // Protection Control
+#define EEPROM_EEPROT_PROT_RWNPW \
+ 0x00000000 // This setting is the default. If
+ // there is no password, the block
+ // is not protected and is readable
+ // and writable
+#define EEPROM_EEPROT_PROT_RWPW 0x00000001 // If there is a password, the
+ // block is readable or writable
+ // only when unlocked
+#define EEPROM_EEPROT_PROT_RONPW \
+ 0x00000002 // If there is no password, the
+ // block is readable, not writable
+#define EEPROM_EEPROT_ACC 0x00000008 // Access Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEPASS0 register.
+//
+//*****************************************************************************
+#define EEPROM_EEPASS0_PASS_M 0xFFFFFFFF // Password
+#define EEPROM_EEPASS0_PASS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEPASS1 register.
+//
+//*****************************************************************************
+#define EEPROM_EEPASS1_PASS_M 0xFFFFFFFF // Password
+#define EEPROM_EEPASS1_PASS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEPASS2 register.
+//
+//*****************************************************************************
+#define EEPROM_EEPASS2_PASS_M 0xFFFFFFFF // Password
+#define EEPROM_EEPASS2_PASS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEINT register.
+//
+//*****************************************************************************
+#define EEPROM_EEINT_INT 0x00000001 // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEHIDE0 register.
+//
+//*****************************************************************************
+#define EEPROM_EEHIDE0_HN_M 0xFFFFFFFE // Hide Block
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEHIDE register.
+//
+//*****************************************************************************
+#define EEPROM_EEHIDE_HN_M 0xFFFFFFFE // Hide Block
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEHIDE1 register.
+//
+//*****************************************************************************
+#define EEPROM_EEHIDE1_HN_M 0xFFFFFFFF // Hide Block
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEHIDE2 register.
+//
+//*****************************************************************************
+#define EEPROM_EEHIDE2_HN_M 0xFFFFFFFF // Hide Block
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_EEDBGME register.
+//
+//*****************************************************************************
+#define EEPROM_EEDBGME_ME 0x00000001 // Mass Erase
+#define EEPROM_EEDBGME_KEY_M 0xFFFF0000 // Erase Key
+#define EEPROM_EEDBGME_KEY_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EEPROM_PP register.
+//
+//*****************************************************************************
+#define EEPROM_PP_SIZE_M 0x0000FFFF // EEPROM Size
+#define EEPROM_PP_SIZE_64 0x00000000 // 64 bytes of EEPROM
+#define EEPROM_PP_SIZE_128 0x00000001 // 128 bytes of EEPROM
+#define EEPROM_PP_SIZE_256 0x00000003 // 256 bytes of EEPROM
+#define EEPROM_PP_SIZE_512 0x00000007 // 512 bytes of EEPROM
+#define EEPROM_PP_SIZE_1K 0x0000000F // 1 KB of EEPROM
+#define EEPROM_PP_SIZE_2K 0x0000001F // 2 KB of EEPROM
+#define EEPROM_PP_SIZE_3K 0x0000003F // 3 KB of EEPROM
+#define EEPROM_PP_SIZE_4K 0x0000007F // 4 KB of EEPROM
+#define EEPROM_PP_SIZE_5K 0x000000FF // 5 KB of EEPROM
+#define EEPROM_PP_SIZE_6K 0x000001FF // 6 KB of EEPROM
+#define EEPROM_PP_SIZE_S 0
+
+#endif // __HW_EEPROM_H__
diff --git a/os/common/ext/TivaWare/inc/hw_emac.h b/os/common/ext/TivaWare/inc/hw_emac.h
new file mode 100644
index 0000000..67cb03e
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_emac.h
@@ -0,0 +1,1839 @@
+//*****************************************************************************
+//
+// hw_emac.h - Macros used when accessing the EMAC hardware.
+//
+// Copyright (c) 2012-2016 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_EMAC_H__
+#define __HW_EMAC_H__
+
+//*****************************************************************************
+//
+// The following are defines for the EMAC register offsets.
+//
+//*****************************************************************************
+#define EMAC_O_CFG 0x00000000 // Ethernet MAC Configuration
+#define EMAC_O_FRAMEFLTR 0x00000004 // Ethernet MAC Frame Filter
+#define EMAC_O_HASHTBLH 0x00000008 // Ethernet MAC Hash Table High
+#define EMAC_O_HASHTBLL 0x0000000C // Ethernet MAC Hash Table Low
+#define EMAC_O_MIIADDR 0x00000010 // Ethernet MAC MII Address
+#define EMAC_O_MIIDATA 0x00000014 // Ethernet MAC MII Data Register
+#define EMAC_O_FLOWCTL 0x00000018 // Ethernet MAC Flow Control
+#define EMAC_O_VLANTG 0x0000001C // Ethernet MAC VLAN Tag
+#define EMAC_O_STATUS 0x00000024 // Ethernet MAC Status
+#define EMAC_O_RWUFF 0x00000028 // Ethernet MAC Remote Wake-Up
+ // Frame Filter
+#define EMAC_O_PMTCTLSTAT 0x0000002C // Ethernet MAC PMT Control and
+ // Status Register
+#define EMAC_O_RIS 0x00000038 // Ethernet MAC Raw Interrupt
+ // Status
+#define EMAC_O_IM 0x0000003C // Ethernet MAC Interrupt Mask
+#define EMAC_O_ADDR0H 0x00000040 // Ethernet MAC Address 0 High
+#define EMAC_O_ADDR0L 0x00000044 // Ethernet MAC Address 0 Low
+ // Register
+#define EMAC_O_ADDR1H 0x00000048 // Ethernet MAC Address 1 High
+#define EMAC_O_ADDR1L 0x0000004C // Ethernet MAC Address 1 Low
+#define EMAC_O_ADDR2H 0x00000050 // Ethernet MAC Address 2 High
+#define EMAC_O_ADDR2L 0x00000054 // Ethernet MAC Address 2 Low
+#define EMAC_O_ADDR3H 0x00000058 // Ethernet MAC Address 3 High
+#define EMAC_O_ADDR3L 0x0000005C // Ethernet MAC Address 3 Low
+#define EMAC_O_WDOGTO 0x000000DC // Ethernet MAC Watchdog Timeout
+#define EMAC_O_MMCCTRL 0x00000100 // Ethernet MAC MMC Control
+#define EMAC_O_MMCRXRIS 0x00000104 // Ethernet MAC MMC Receive Raw
+ // Interrupt Status
+#define EMAC_O_MMCTXRIS 0x00000108 // Ethernet MAC MMC Transmit Raw
+ // Interrupt Status
+#define EMAC_O_MMCRXIM 0x0000010C // Ethernet MAC MMC Receive
+ // Interrupt Mask
+#define EMAC_O_MMCTXIM 0x00000110 // Ethernet MAC MMC Transmit
+ // Interrupt Mask
+#define EMAC_O_TXCNTGB 0x00000118 // Ethernet MAC Transmit Frame
+ // Count for Good and Bad Frames
+#define EMAC_O_TXCNTSCOL 0x0000014C // Ethernet MAC Transmit Frame
+ // Count for Frames Transmitted
+ // after Single Collision
+#define EMAC_O_TXCNTMCOL 0x00000150 // Ethernet MAC Transmit Frame
+ // Count for Frames Transmitted
+ // after Multiple Collisions
+#define EMAC_O_TXOCTCNTG 0x00000164 // Ethernet MAC Transmit Octet
+ // Count Good
+#define EMAC_O_RXCNTGB 0x00000180 // Ethernet MAC Receive Frame Count
+ // for Good and Bad Frames
+#define EMAC_O_RXCNTCRCERR 0x00000194 // Ethernet MAC Receive Frame Count
+ // for CRC Error Frames
+#define EMAC_O_RXCNTALGNERR 0x00000198 // Ethernet MAC Receive Frame Count
+ // for Alignment Error Frames
+#define EMAC_O_RXCNTGUNI 0x000001C4 // Ethernet MAC Receive Frame Count
+ // for Good Unicast Frames
+#define EMAC_O_VLNINCREP 0x00000584 // Ethernet MAC VLAN Tag Inclusion
+ // or Replacement
+#define EMAC_O_VLANHASH 0x00000588 // Ethernet MAC VLAN Hash Table
+#define EMAC_O_TIMSTCTRL 0x00000700 // Ethernet MAC Timestamp Control
+#define EMAC_O_SUBSECINC 0x00000704 // Ethernet MAC Sub-Second
+ // Increment
+#define EMAC_O_TIMSEC 0x00000708 // Ethernet MAC System Time -
+ // Seconds
+#define EMAC_O_TIMNANO 0x0000070C // Ethernet MAC System Time -
+ // Nanoseconds
+#define EMAC_O_TIMSECU 0x00000710 // Ethernet MAC System Time -
+ // Seconds Update
+#define EMAC_O_TIMNANOU 0x00000714 // Ethernet MAC System Time -
+ // Nanoseconds Update
+#define EMAC_O_TIMADD 0x00000718 // Ethernet MAC Timestamp Addend
+#define EMAC_O_TARGSEC 0x0000071C // Ethernet MAC Target Time Seconds
+#define EMAC_O_TARGNANO 0x00000720 // Ethernet MAC Target Time
+ // Nanoseconds
+#define EMAC_O_HWORDSEC 0x00000724 // Ethernet MAC System Time-Higher
+ // Word Seconds
+#define EMAC_O_TIMSTAT 0x00000728 // Ethernet MAC Timestamp Status
+#define EMAC_O_PPSCTRL 0x0000072C // Ethernet MAC PPS Control
+#define EMAC_O_PPS0INTVL 0x00000760 // Ethernet MAC PPS0 Interval
+#define EMAC_O_PPS0WIDTH 0x00000764 // Ethernet MAC PPS0 Width
+#define EMAC_O_DMABUSMOD 0x00000C00 // Ethernet MAC DMA Bus Mode
+#define EMAC_O_TXPOLLD 0x00000C04 // Ethernet MAC Transmit Poll
+ // Demand
+#define EMAC_O_RXPOLLD 0x00000C08 // Ethernet MAC Receive Poll Demand
+#define EMAC_O_RXDLADDR 0x00000C0C // Ethernet MAC Receive Descriptor
+ // List Address
+#define EMAC_O_TXDLADDR 0x00000C10 // Ethernet MAC Transmit Descriptor
+ // List Address
+#define EMAC_O_DMARIS 0x00000C14 // Ethernet MAC DMA Interrupt
+ // Status
+#define EMAC_O_DMAOPMODE 0x00000C18 // Ethernet MAC DMA Operation Mode
+#define EMAC_O_DMAIM 0x00000C1C // Ethernet MAC DMA Interrupt Mask
+ // Register
+#define EMAC_O_MFBOC 0x00000C20 // Ethernet MAC Missed Frame and
+ // Buffer Overflow Counter
+#define EMAC_O_RXINTWDT 0x00000C24 // Ethernet MAC Receive Interrupt
+ // Watchdog Timer
+#define EMAC_O_HOSTXDESC 0x00000C48 // Ethernet MAC Current Host
+ // Transmit Descriptor
+#define EMAC_O_HOSRXDESC 0x00000C4C // Ethernet MAC Current Host
+ // Receive Descriptor
+#define EMAC_O_HOSTXBA 0x00000C50 // Ethernet MAC Current Host
+ // Transmit Buffer Address
+#define EMAC_O_HOSRXBA 0x00000C54 // Ethernet MAC Current Host
+ // Receive Buffer Address
+#define EMAC_O_PP 0x00000FC0 // Ethernet MAC Peripheral Property
+ // Register
+#define EMAC_O_PC 0x00000FC4 // Ethernet MAC Peripheral
+ // Configuration Register
+#define EMAC_O_CC 0x00000FC8 // Ethernet MAC Clock Configuration
+ // Register
+#define EMAC_O_EPHYRIS 0x00000FD0 // Ethernet PHY Raw Interrupt
+ // Status
+#define EMAC_O_EPHYIM 0x00000FD4 // Ethernet PHY Interrupt Mask
+#define EMAC_O_EPHYMISC 0x00000FD8 // Ethernet PHY Masked Interrupt
+ // Status and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_CFG register.
+//
+//*****************************************************************************
+#define EMAC_CFG_TWOKPEN 0x08000000 // IEEE 802
+#define EMAC_CFG_CST 0x02000000 // CRC Stripping for Type Frames
+#define EMAC_CFG_WDDIS 0x00800000 // Watchdog Disable
+#define EMAC_CFG_JD 0x00400000 // Jabber Disable
+#define EMAC_CFG_JFEN 0x00100000 // Jumbo Frame Enable
+#define EMAC_CFG_IFG_M 0x000E0000 // Inter-Frame Gap (IFG)
+#define EMAC_CFG_IFG_96 0x00000000 // 96 bit times
+#define EMAC_CFG_IFG_88 0x00020000 // 88 bit times
+#define EMAC_CFG_IFG_80 0x00040000 // 80 bit times
+#define EMAC_CFG_IFG_72 0x00060000 // 72 bit times
+#define EMAC_CFG_IFG_64 0x00080000 // 64 bit times
+#define EMAC_CFG_IFG_56 0x000A0000 // 56 bit times
+#define EMAC_CFG_IFG_48 0x000C0000 // 48 bit times
+#define EMAC_CFG_IFG_40 0x000E0000 // 40 bit times
+#define EMAC_CFG_DISCRS 0x00010000 // Disable Carrier Sense During
+ // Transmission
+#define EMAC_CFG_PS 0x00008000 // Port Select
+#define EMAC_CFG_FES 0x00004000 // Speed
+#define EMAC_CFG_DRO 0x00002000 // Disable Receive Own
+#define EMAC_CFG_LOOPBM 0x00001000 // Loopback Mode
+#define EMAC_CFG_DUPM 0x00000800 // Duplex Mode
+#define EMAC_CFG_IPC 0x00000400 // Checksum Offload
+#define EMAC_CFG_DR 0x00000200 // Disable Retry
+#define EMAC_CFG_ACS 0x00000080 // Automatic Pad or CRC Stripping
+#define EMAC_CFG_BL_M 0x00000060 // Back-Off Limit
+#define EMAC_CFG_BL_1024 0x00000000 // k = min (n,10)
+#define EMAC_CFG_BL_256 0x00000020 // k = min (n,8)
+#define EMAC_CFG_BL_8 0x00000040 // k = min (n,4)
+#define EMAC_CFG_BL_2 0x00000060 // k = min (n,1)
+#define EMAC_CFG_DC 0x00000010 // Deferral Check
+#define EMAC_CFG_TE 0x00000008 // Transmitter Enable
+#define EMAC_CFG_RE 0x00000004 // Receiver Enable
+#define EMAC_CFG_PRELEN_M 0x00000003 // Preamble Length for Transmit
+ // Frames
+#define EMAC_CFG_PRELEN_7 0x00000000 // 7 bytes of preamble
+#define EMAC_CFG_PRELEN_5 0x00000001 // 5 bytes of preamble
+#define EMAC_CFG_PRELEN_3 0x00000002 // 3 bytes of preamble
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_FRAMEFLTR
+// register.
+//
+//*****************************************************************************
+#define EMAC_FRAMEFLTR_RA 0x80000000 // Receive All
+#define EMAC_FRAMEFLTR_VTFE 0x00010000 // VLAN Tag Filter Enable
+#define EMAC_FRAMEFLTR_HPF 0x00000400 // Hash or Perfect Filter
+#define EMAC_FRAMEFLTR_SAF 0x00000200 // Source Address Filter Enable
+#define EMAC_FRAMEFLTR_SAIF 0x00000100 // Source Address (SA) Inverse
+ // Filtering
+#define EMAC_FRAMEFLTR_PCF_M 0x000000C0 // Pass Control Frames
+#define EMAC_FRAMEFLTR_PCF_ALL 0x00000000 // The MAC filters all control
+ // frames from reaching application
+#define EMAC_FRAMEFLTR_PCF_PAUSE \
+ 0x00000040 // MAC forwards all control frames
+ // except PAUSE control frames to
+ // application even if they fail
+ // the address filter
+#define EMAC_FRAMEFLTR_PCF_NONE 0x00000080 // MAC forwards all control frames
+ // to application even if they fail
+ // the address Filter
+#define EMAC_FRAMEFLTR_PCF_ADDR 0x000000C0 // MAC forwards control frames that
+ // pass the address Filter
+#define EMAC_FRAMEFLTR_DBF 0x00000020 // Disable Broadcast Frames
+#define EMAC_FRAMEFLTR_PM 0x00000010 // Pass All Multicast
+#define EMAC_FRAMEFLTR_DAIF 0x00000008 // Destination Address (DA) Inverse
+ // Filtering
+#define EMAC_FRAMEFLTR_HMC 0x00000004 // Hash Multicast
+#define EMAC_FRAMEFLTR_HUC 0x00000002 // Hash Unicast
+#define EMAC_FRAMEFLTR_PR 0x00000001 // Promiscuous Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_HASHTBLH
+// register.
+//
+//*****************************************************************************
+#define EMAC_HASHTBLH_HTH_M 0xFFFFFFFF // Hash Table High
+#define EMAC_HASHTBLH_HTH_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_HASHTBLL
+// register.
+//
+//*****************************************************************************
+#define EMAC_HASHTBLL_HTL_M 0xFFFFFFFF // Hash Table Low
+#define EMAC_HASHTBLL_HTL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_MIIADDR register.
+//
+//*****************************************************************************
+#define EMAC_MIIADDR_PLA_M 0x0000F800 // Physical Layer Address
+#define EMAC_MIIADDR_MII_M 0x000007C0 // MII Register
+#define EMAC_MIIADDR_CR_M 0x0000003C // Clock Reference Frequency
+ // Selection
+#define EMAC_MIIADDR_CR_60_100 0x00000000 // The frequency of the System
+ // Clock is 60 to 100 MHz providing
+ // a MDIO clock of SYSCLK/42
+#define EMAC_MIIADDR_CR_100_150 0x00000004 // The frequency of the System
+ // Clock is 100 to 150 MHz
+ // providing a MDIO clock of
+ // SYSCLK/62
+#define EMAC_MIIADDR_CR_20_35 0x00000008 // The frequency of the System
+ // Clock is 20-35 MHz providing a
+ // MDIO clock of System Clock/16
+#define EMAC_MIIADDR_CR_35_60 0x0000000C // The frequency of the System
+ // Clock is 35 to 60 MHz providing
+ // a MDIO clock of System Clock/26
+#define EMAC_MIIADDR_MIIW 0x00000002 // MII Write
+#define EMAC_MIIADDR_MIIB 0x00000001 // MII Busy
+#define EMAC_MIIADDR_PLA_S 11
+#define EMAC_MIIADDR_MII_S 6
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_MIIDATA register.
+//
+//*****************************************************************************
+#define EMAC_MIIDATA_DATA_M 0x0000FFFF // MII Data
+#define EMAC_MIIDATA_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_FLOWCTL register.
+//
+//*****************************************************************************
+#define EMAC_FLOWCTL_PT_M 0xFFFF0000 // Pause Time
+#define EMAC_FLOWCTL_DZQP 0x00000080 // Disable Zero-Quanta Pause
+#define EMAC_FLOWCTL_UP 0x00000008 // Unicast Pause Frame Detect
+#define EMAC_FLOWCTL_RFE 0x00000004 // Receive Flow Control Enable
+#define EMAC_FLOWCTL_TFE 0x00000002 // Transmit Flow Control Enable
+#define EMAC_FLOWCTL_FCBBPA 0x00000001 // Flow Control Busy or
+ // Back-pressure Activate
+#define EMAC_FLOWCTL_PT_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_VLANTG register.
+//
+//*****************************************************************************
+#define EMAC_VLANTG_VTHM 0x00080000 // VLAN Tag Hash Table Match Enable
+#define EMAC_VLANTG_ESVL 0x00040000 // Enable S-VLAN
+#define EMAC_VLANTG_VTIM 0x00020000 // VLAN Tag Inverse Match Enable
+#define EMAC_VLANTG_ETV 0x00010000 // Enable 12-Bit VLAN Tag
+ // Comparison
+#define EMAC_VLANTG_VL_M 0x0000FFFF // VLAN Tag Identifier for Receive
+ // Frames
+#define EMAC_VLANTG_VL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_STATUS register.
+//
+//*****************************************************************************
+#define EMAC_STATUS_TXFF 0x02000000 // TX/RX Controller TX FIFO Full
+ // Status
+#define EMAC_STATUS_TXFE 0x01000000 // TX/RX Controller TX FIFO Not
+ // Empty Status
+#define EMAC_STATUS_TWC 0x00400000 // TX/RX Controller TX FIFO Write
+ // Controller Active Status
+#define EMAC_STATUS_TRC_M 0x00300000 // TX/RX Controller's TX FIFO Read
+ // Controller Status
+#define EMAC_STATUS_TRC_IDLE 0x00000000 // IDLE state
+#define EMAC_STATUS_TRC_READ 0x00100000 // READ state (transferring data to
+ // MAC transmitter)
+#define EMAC_STATUS_TRC_WAIT 0x00200000 // Waiting for TX Status from MAC
+ // transmitter
+#define EMAC_STATUS_TRC_WRFLUSH 0x00300000 // Writing the received TX Status
+ // or flushing the TX FIFO
+#define EMAC_STATUS_TXPAUSED 0x00080000 // MAC Transmitter PAUSE
+#define EMAC_STATUS_TFC_M 0x00060000 // MAC Transmit Frame Controller
+ // Status
+#define EMAC_STATUS_TFC_IDLE 0x00000000 // IDLE state
+#define EMAC_STATUS_TFC_STATUS 0x00020000 // Waiting for status of previous
+ // frame or IFG or backoff period
+ // to be over
+#define EMAC_STATUS_TFC_PAUSE 0x00040000 // Generating and transmitting a
+ // PAUSE control frame (in the
+ // full-duplex mode)
+#define EMAC_STATUS_TFC_INPUT 0x00060000 // Transferring input frame for
+ // transmission
+#define EMAC_STATUS_TPE 0x00010000 // MAC MII Transmit Protocol Engine
+ // Status
+#define EMAC_STATUS_RXF_M 0x00000300 // TX/RX Controller RX FIFO
+ // Fill-level Status
+#define EMAC_STATUS_RXF_EMPTY 0x00000000 // RX FIFO Empty
+#define EMAC_STATUS_RXF_BELOW 0x00000100 // RX FIFO fill level is below the
+ // flow-control deactivate
+ // threshold
+#define EMAC_STATUS_RXF_ABOVE 0x00000200 // RX FIFO fill level is above the
+ // flow-control activate threshold
+#define EMAC_STATUS_RXF_FULL 0x00000300 // RX FIFO Full
+#define EMAC_STATUS_RRC_M 0x00000060 // TX/RX Controller Read Controller
+ // State
+#define EMAC_STATUS_RRC_IDLE 0x00000000 // IDLE state
+#define EMAC_STATUS_RRC_STATUS 0x00000020 // Reading frame data
+#define EMAC_STATUS_RRC_DATA 0x00000040 // Reading frame status (or
+ // timestamp)
+#define EMAC_STATUS_RRC_FLUSH 0x00000060 // Flushing the frame data and
+ // status
+#define EMAC_STATUS_RWC 0x00000010 // TX/RX Controller RX FIFO Write
+ // Controller Active Status
+#define EMAC_STATUS_RFCFC_M 0x00000006 // MAC Receive Frame Controller
+ // FIFO Status
+#define EMAC_STATUS_RPE 0x00000001 // MAC MII Receive Protocol Engine
+ // Status
+#define EMAC_STATUS_RFCFC_S 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_RWUFF register.
+//
+//*****************************************************************************
+#define EMAC_RWUFF_WAKEUPFIL_M 0xFFFFFFFF // Remote Wake-Up Frame Filter
+#define EMAC_RWUFF_WAKEUPFIL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_PMTCTLSTAT
+// register.
+//
+//*****************************************************************************
+#define EMAC_PMTCTLSTAT_WUPFRRST \
+ 0x80000000 // Wake-Up Frame Filter Register
+ // Pointer Reset
+#define EMAC_PMTCTLSTAT_RWKPTR_M \
+ 0x07000000 // Remote Wake-Up FIFO Pointer
+#define EMAC_PMTCTLSTAT_GLBLUCAST \
+ 0x00000200 // Global Unicast
+#define EMAC_PMTCTLSTAT_WUPRX 0x00000040 // Wake-Up Frame Received
+#define EMAC_PMTCTLSTAT_MGKPRX 0x00000020 // Magic Packet Received
+#define EMAC_PMTCTLSTAT_WUPFREN 0x00000004 // Wake-Up Frame Enable
+#define EMAC_PMTCTLSTAT_MGKPKTEN \
+ 0x00000002 // Magic Packet Enable
+#define EMAC_PMTCTLSTAT_PWRDWN 0x00000001 // Power Down
+#define EMAC_PMTCTLSTAT_RWKPTR_S \
+ 24
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_RIS register.
+//
+//*****************************************************************************
+#define EMAC_RIS_TS 0x00000200 // Timestamp Interrupt Status
+#define EMAC_RIS_MMCTX 0x00000040 // MMC Transmit Interrupt Status
+#define EMAC_RIS_MMCRX 0x00000020 // MMC Receive Interrupt Status
+#define EMAC_RIS_MMC 0x00000010 // MMC Interrupt Status
+#define EMAC_RIS_PMT 0x00000008 // PMT Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_IM register.
+//
+//*****************************************************************************
+#define EMAC_IM_TSI 0x00000200 // Timestamp Interrupt Mask
+#define EMAC_IM_PMT 0x00000008 // PMT Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_ADDR0H register.
+//
+//*****************************************************************************
+#define EMAC_ADDR0H_AE 0x80000000 // Address Enable
+#define EMAC_ADDR0H_ADDRHI_M 0x0000FFFF // MAC Address0 [47:32]
+#define EMAC_ADDR0H_ADDRHI_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_ADDR0L register.
+//
+//*****************************************************************************
+#define EMAC_ADDR0L_ADDRLO_M 0xFFFFFFFF // MAC Address0 [31:0]
+#define EMAC_ADDR0L_ADDRLO_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_ADDR1H register.
+//
+//*****************************************************************************
+#define EMAC_ADDR1H_AE 0x80000000 // Address Enable
+#define EMAC_ADDR1H_SA 0x40000000 // Source Address
+#define EMAC_ADDR1H_MBC_M 0x3F000000 // Mask Byte Control
+#define EMAC_ADDR1H_ADDRHI_M 0x0000FFFF // MAC Address1 [47:32]
+#define EMAC_ADDR1H_MBC_S 24
+#define EMAC_ADDR1H_ADDRHI_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_ADDR1L register.
+//
+//*****************************************************************************
+#define EMAC_ADDR1L_ADDRLO_M 0xFFFFFFFF // MAC Address1 [31:0]
+#define EMAC_ADDR1L_ADDRLO_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_ADDR2H register.
+//
+//*****************************************************************************
+#define EMAC_ADDR2H_AE 0x80000000 // Address Enable
+#define EMAC_ADDR2H_SA 0x40000000 // Source Address
+#define EMAC_ADDR2H_MBC_M 0x3F000000 // Mask Byte Control
+#define EMAC_ADDR2H_ADDRHI_M 0x0000FFFF // MAC Address2 [47:32]
+#define EMAC_ADDR2H_MBC_S 24
+#define EMAC_ADDR2H_ADDRHI_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_ADDR2L register.
+//
+//*****************************************************************************
+#define EMAC_ADDR2L_ADDRLO_M 0xFFFFFFFF // MAC Address2 [31:0]
+#define EMAC_ADDR2L_ADDRLO_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_ADDR3H register.
+//
+//*****************************************************************************
+#define EMAC_ADDR3H_AE 0x80000000 // Address Enable
+#define EMAC_ADDR3H_SA 0x40000000 // Source Address
+#define EMAC_ADDR3H_MBC_M 0x3F000000 // Mask Byte Control
+#define EMAC_ADDR3H_ADDRHI_M 0x0000FFFF // MAC Address3 [47:32]
+#define EMAC_ADDR3H_MBC_S 24
+#define EMAC_ADDR3H_ADDRHI_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_ADDR3L register.
+//
+//*****************************************************************************
+#define EMAC_ADDR3L_ADDRLO_M 0xFFFFFFFF // MAC Address3 [31:0]
+#define EMAC_ADDR3L_ADDRLO_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_WDOGTO register.
+//
+//*****************************************************************************
+#define EMAC_WDOGTO_PWE 0x00010000 // Programmable Watchdog Enable
+#define EMAC_WDOGTO_WTO_M 0x00003FFF // Watchdog Timeout
+#define EMAC_WDOGTO_WTO_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_MMCCTRL register.
+//
+//*****************************************************************************
+#define EMAC_MMCCTRL_UCDBC 0x00000100 // Update MMC Counters for Dropped
+ // Broadcast Frames
+#define EMAC_MMCCTRL_CNTPRSTLVL 0x00000020 // Full/Half Preset Level Value
+#define EMAC_MMCCTRL_CNTPRST 0x00000010 // Counters Preset
+#define EMAC_MMCCTRL_CNTFREEZ 0x00000008 // MMC Counter Freeze
+#define EMAC_MMCCTRL_RSTONRD 0x00000004 // Reset on Read
+#define EMAC_MMCCTRL_CNTSTPRO 0x00000002 // Counters Stop Rollover
+#define EMAC_MMCCTRL_CNTRST 0x00000001 // Counters Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_MMCRXRIS
+// register.
+//
+//*****************************************************************************
+#define EMAC_MMCRXRIS_UCGF 0x00020000 // MMC Receive Unicast Good Frame
+ // Counter Interrupt Status
+#define EMAC_MMCRXRIS_ALGNERR 0x00000040 // MMC Receive Alignment Error
+ // Frame Counter Interrupt Status
+#define EMAC_MMCRXRIS_CRCERR 0x00000020 // MMC Receive CRC Error Frame
+ // Counter Interrupt Status
+#define EMAC_MMCRXRIS_GBF 0x00000001 // MMC Receive Good Bad Frame
+ // Counter Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_MMCTXRIS
+// register.
+//
+//*****************************************************************************
+#define EMAC_MMCTXRIS_OCTCNT 0x00100000 // Octet Counter Interrupt Status
+#define EMAC_MMCTXRIS_MCOLLGF 0x00008000 // MMC Transmit Multiple Collision
+ // Good Frame Counter Interrupt
+ // Status
+#define EMAC_MMCTXRIS_SCOLLGF 0x00004000 // MMC Transmit Single Collision
+ // Good Frame Counter Interrupt
+ // Status
+#define EMAC_MMCTXRIS_GBF 0x00000002 // MMC Transmit Good Bad Frame
+ // Counter Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_MMCRXIM register.
+//
+//*****************************************************************************
+#define EMAC_MMCRXIM_UCGF 0x00020000 // MMC Receive Unicast Good Frame
+ // Counter Interrupt Mask
+#define EMAC_MMCRXIM_ALGNERR 0x00000040 // MMC Receive Alignment Error
+ // Frame Counter Interrupt Mask
+#define EMAC_MMCRXIM_CRCERR 0x00000020 // MMC Receive CRC Error Frame
+ // Counter Interrupt Mask
+#define EMAC_MMCRXIM_GBF 0x00000001 // MMC Receive Good Bad Frame
+ // Counter Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_MMCTXIM register.
+//
+//*****************************************************************************
+#define EMAC_MMCTXIM_OCTCNT 0x00100000 // MMC Transmit Good Octet Counter
+ // Interrupt Mask
+#define EMAC_MMCTXIM_MCOLLGF 0x00008000 // MMC Transmit Multiple Collision
+ // Good Frame Counter Interrupt
+ // Mask
+#define EMAC_MMCTXIM_SCOLLGF 0x00004000 // MMC Transmit Single Collision
+ // Good Frame Counter Interrupt
+ // Mask
+#define EMAC_MMCTXIM_GBF 0x00000002 // MMC Transmit Good Bad Frame
+ // Counter Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TXCNTGB register.
+//
+//*****************************************************************************
+#define EMAC_TXCNTGB_TXFRMGB_M 0xFFFFFFFF // This field indicates the number
+ // of good and bad frames
+ // transmitted, exclusive of
+ // retried frames
+#define EMAC_TXCNTGB_TXFRMGB_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TXCNTSCOL
+// register.
+//
+//*****************************************************************************
+#define EMAC_TXCNTSCOL_TXSNGLCOLG_M \
+ 0xFFFFFFFF // This field indicates the number
+ // of successfully transmitted
+ // frames after a single collision
+ // in the half-duplex mode
+#define EMAC_TXCNTSCOL_TXSNGLCOLG_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TXCNTMCOL
+// register.
+//
+//*****************************************************************************
+#define EMAC_TXCNTMCOL_TXMULTCOLG_M \
+ 0xFFFFFFFF // This field indicates the number
+ // of successfully transmitted
+ // frames after multiple collisions
+ // in the half-duplex mode
+#define EMAC_TXCNTMCOL_TXMULTCOLG_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TXOCTCNTG
+// register.
+//
+//*****************************************************************************
+#define EMAC_TXOCTCNTG_TXOCTG_M 0xFFFFFFFF // This field indicates the number
+ // of bytes transmitted, exclusive
+ // of preamble, in good frames
+#define EMAC_TXOCTCNTG_TXOCTG_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_RXCNTGB register.
+//
+//*****************************************************************************
+#define EMAC_RXCNTGB_RXFRMGB_M 0xFFFFFFFF // This field indicates the number
+ // of received good and bad frames
+#define EMAC_RXCNTGB_RXFRMGB_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_RXCNTCRCERR
+// register.
+//
+//*****************************************************************************
+#define EMAC_RXCNTCRCERR_RXCRCERR_M \
+ 0xFFFFFFFF // This field indicates the number
+ // of frames received with CRC
+ // error
+#define EMAC_RXCNTCRCERR_RXCRCERR_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_RXCNTALGNERR
+// register.
+//
+//*****************************************************************************
+#define EMAC_RXCNTALGNERR_RXALGNERR_M \
+ 0xFFFFFFFF // This field indicates the number
+ // of frames received with
+ // alignment (dribble) error
+#define EMAC_RXCNTALGNERR_RXALGNERR_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_RXCNTGUNI
+// register.
+//
+//*****************************************************************************
+#define EMAC_RXCNTGUNI_RXUCASTG_M \
+ 0xFFFFFFFF // This field indicates the number
+ // of received good unicast frames
+#define EMAC_RXCNTGUNI_RXUCASTG_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_VLNINCREP
+// register.
+//
+//*****************************************************************************
+#define EMAC_VLNINCREP_CSVL 0x00080000 // C-VLAN or S-VLAN
+#define EMAC_VLNINCREP_VLP 0x00040000 // VLAN Priority Control
+#define EMAC_VLNINCREP_VLC_M 0x00030000 // VLAN Tag Control in Transmit
+ // Frames
+#define EMAC_VLNINCREP_VLC_NONE 0x00000000 // No VLAN tag deletion, insertion,
+ // or replacement
+#define EMAC_VLNINCREP_VLC_TAGDEL \
+ 0x00010000 // VLAN tag deletion
+#define EMAC_VLNINCREP_VLC_TAGINS \
+ 0x00020000 // VLAN tag insertion
+#define EMAC_VLNINCREP_VLC_TAGREP \
+ 0x00030000 // VLAN tag replacement
+#define EMAC_VLNINCREP_VLT_M 0x0000FFFF // VLAN Tag for Transmit Frames
+#define EMAC_VLNINCREP_VLT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_VLANHASH
+// register.
+//
+//*****************************************************************************
+#define EMAC_VLANHASH_VLHT_M 0x0000FFFF // VLAN Hash Table
+#define EMAC_VLANHASH_VLHT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TIMSTCTRL
+// register.
+//
+//*****************************************************************************
+#define EMAC_TIMSTCTRL_PTPFLTR 0x00040000 // Enable MAC address for PTP Frame
+ // Filtering
+#define EMAC_TIMSTCTRL_SELPTP_M 0x00030000 // Select PTP packets for Taking
+ // Snapshots
+#define EMAC_TIMSTCTRL_TSMAST 0x00008000 // Enable Snapshot for Messages
+ // Relevant to Master
+#define EMAC_TIMSTCTRL_TSEVNT 0x00004000 // Enable Timestamp Snapshot for
+ // Event Messages
+#define EMAC_TIMSTCTRL_PTPIPV4 0x00002000 // Enable Processing of PTP Frames
+ // Sent over IPv4-UDP
+#define EMAC_TIMSTCTRL_PTPIPV6 0x00001000 // Enable Processing of PTP Frames
+ // Sent Over IPv6-UDP
+#define EMAC_TIMSTCTRL_PTPETH 0x00000800 // Enable Processing of PTP Over
+ // Ethernet Frames
+#define EMAC_TIMSTCTRL_PTPVER2 0x00000400 // Enable PTP Packet Processing For
+ // Version 2 Format
+#define EMAC_TIMSTCTRL_DGTLBIN 0x00000200 // Timestamp Digital or Binary
+ // Rollover Control
+#define EMAC_TIMSTCTRL_ALLF 0x00000100 // Enable Timestamp For All Frames
+#define EMAC_TIMSTCTRL_ADDREGUP 0x00000020 // Addend Register Update
+#define EMAC_TIMSTCTRL_INTTRIG 0x00000010 // Timestamp Interrupt Trigger
+ // Enable
+#define EMAC_TIMSTCTRL_TSUPDT 0x00000008 // Timestamp Update
+#define EMAC_TIMSTCTRL_TSINIT 0x00000004 // Timestamp Initialize
+#define EMAC_TIMSTCTRL_TSFCUPDT 0x00000002 // Timestamp Fine or Coarse Update
+#define EMAC_TIMSTCTRL_TSEN 0x00000001 // Timestamp Enable
+#define EMAC_TIMSTCTRL_SELPTP_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_SUBSECINC
+// register.
+//
+//*****************************************************************************
+#define EMAC_SUBSECINC_SSINC_M 0x000000FF // Sub-second Increment Value
+#define EMAC_SUBSECINC_SSINC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TIMSEC register.
+//
+//*****************************************************************************
+#define EMAC_TIMSEC_TSS_M 0xFFFFFFFF // Timestamp Second
+#define EMAC_TIMSEC_TSS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TIMNANO register.
+//
+//*****************************************************************************
+#define EMAC_TIMNANO_TSSS_M 0x7FFFFFFF // Timestamp Sub-Seconds
+#define EMAC_TIMNANO_TSSS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TIMSECU register.
+//
+//*****************************************************************************
+#define EMAC_TIMSECU_TSS_M 0xFFFFFFFF // Timestamp Second
+#define EMAC_TIMSECU_TSS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TIMNANOU
+// register.
+//
+//*****************************************************************************
+#define EMAC_TIMNANOU_ADDSUB 0x80000000 // Add or subtract time
+#define EMAC_TIMNANOU_TSSS_M 0x7FFFFFFF // Timestamp Sub-Second
+#define EMAC_TIMNANOU_TSSS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TIMADD register.
+//
+//*****************************************************************************
+#define EMAC_TIMADD_TSAR_M 0xFFFFFFFF // Timestamp Addend Register
+#define EMAC_TIMADD_TSAR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TARGSEC register.
+//
+//*****************************************************************************
+#define EMAC_TARGSEC_TSTR_M 0xFFFFFFFF // Target Time Seconds Register
+#define EMAC_TARGSEC_TSTR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TARGNANO
+// register.
+//
+//*****************************************************************************
+#define EMAC_TARGNANO_TRGTBUSY 0x80000000 // Target Time Register Busy
+#define EMAC_TARGNANO_TTSLO_M 0x7FFFFFFF // Target Timestamp Low Register
+#define EMAC_TARGNANO_TTSLO_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_HWORDSEC
+// register.
+//
+//*****************************************************************************
+#define EMAC_HWORDSEC_TSHWR_M 0x0000FFFF // Target Timestamp Higher Word
+ // Register
+#define EMAC_HWORDSEC_TSHWR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TIMSTAT register.
+//
+//*****************************************************************************
+#define EMAC_TIMSTAT_TSTARGT 0x00000002 // Timestamp Target Time Reached
+#define EMAC_TIMSTAT_TSSOVF 0x00000001 // Timestamp Seconds Overflow
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_PPSCTRL register.
+//
+//*****************************************************************************
+#define EMAC_PPSCTRL_TRGMODS0_M 0x00000060 // Target Time Register Mode for
+ // PPS0 Output
+#define EMAC_PPSCTRL_TRGMODS0_INTONLY \
+ 0x00000000 // Indicates that the Target Time
+ // registers are programmed only
+ // for generating the interrupt
+ // event
+#define EMAC_PPSCTRL_TRGMODS0_INTPPS0 \
+ 0x00000040 // Indicates that the Target Time
+ // registers are programmed for
+ // generating the interrupt event
+ // and starting or stopping the
+ // generation of the EN0PPS output
+ // signal
+#define EMAC_PPSCTRL_TRGMODS0_PPS0ONLY \
+ 0x00000060 // Indicates that the Target Time
+ // registers are programmed only
+ // for starting or stopping the
+ // generation of the EN0PPS output
+ // signal. No interrupt is asserted
+#define EMAC_PPSCTRL_PPSEN0 0x00000010 // Flexible PPS Output Mode Enable
+#define EMAC_PPSCTRL_PPSCTRL_M 0x0000000F // EN0PPS Output Frequency Control
+ // (PPSCTRL) or Command Control
+ // (PPSCMD)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_PPS0INTVL
+// register.
+//
+//*****************************************************************************
+#define EMAC_PPS0INTVL_PPS0INT_M \
+ 0xFFFFFFFF // PPS0 Output Signal Interval
+#define EMAC_PPS0INTVL_PPS0INT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_PPS0WIDTH
+// register.
+//
+//*****************************************************************************
+#define EMAC_PPS0WIDTH_M 0xFFFFFFFF // EN0PPS Output Signal Width
+#define EMAC_PPS0WIDTH_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_DMABUSMOD
+// register.
+//
+//*****************************************************************************
+#define EMAC_DMABUSMOD_RIB 0x80000000 // Rebuild Burst
+#define EMAC_DMABUSMOD_TXPR 0x08000000 // Transmit Priority
+#define EMAC_DMABUSMOD_MB 0x04000000 // Mixed Burst
+#define EMAC_DMABUSMOD_AAL 0x02000000 // Address Aligned Beats
+#define EMAC_DMABUSMOD_8XPBL 0x01000000 // 8 x Programmable Burst Length
+ // (PBL) Mode
+#define EMAC_DMABUSMOD_USP 0x00800000 // Use Separate Programmable Burst
+ // Length (PBL)
+#define EMAC_DMABUSMOD_RPBL_M 0x007E0000 // RX DMA Programmable Burst Length
+ // (PBL)
+#define EMAC_DMABUSMOD_FB 0x00010000 // Fixed Burst
+#define EMAC_DMABUSMOD_PR_M 0x0000C000 // Priority Ratio
+#define EMAC_DMABUSMOD_PBL_M 0x00003F00 // Programmable Burst Length
+#define EMAC_DMABUSMOD_ATDS 0x00000080 // Alternate Descriptor Size
+#define EMAC_DMABUSMOD_DSL_M 0x0000007C // Descriptor Skip Length
+#define EMAC_DMABUSMOD_DA 0x00000002 // DMA Arbitration Scheme
+#define EMAC_DMABUSMOD_SWR 0x00000001 // DMA Software Reset
+#define EMAC_DMABUSMOD_RPBL_S 17
+#define EMAC_DMABUSMOD_PR_S 14
+#define EMAC_DMABUSMOD_PBL_S 8
+#define EMAC_DMABUSMOD_DSL_S 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TXPOLLD register.
+//
+//*****************************************************************************
+#define EMAC_TXPOLLD_TPD_M 0xFFFFFFFF // Transmit Poll Demand
+#define EMAC_TXPOLLD_TPD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_RXPOLLD register.
+//
+//*****************************************************************************
+#define EMAC_RXPOLLD_RPD_M 0xFFFFFFFF // Receive Poll Demand
+#define EMAC_RXPOLLD_RPD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_RXDLADDR
+// register.
+//
+//*****************************************************************************
+#define EMAC_RXDLADDR_STRXLIST_M \
+ 0xFFFFFFFC // Start of Receive List
+#define EMAC_RXDLADDR_STRXLIST_S \
+ 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_TXDLADDR
+// register.
+//
+//*****************************************************************************
+#define EMAC_TXDLADDR_TXDLADDR_M \
+ 0xFFFFFFFC // Start of Transmit List Base
+ // Address
+#define EMAC_TXDLADDR_TXDLADDR_S \
+ 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_DMARIS register.
+//
+//*****************************************************************************
+#define EMAC_DMARIS_TT 0x20000000 // Timestamp Trigger Interrupt
+ // Status
+#define EMAC_DMARIS_PMT 0x10000000 // MAC PMT Interrupt Status
+#define EMAC_DMARIS_MMC 0x08000000 // MAC MMC Interrupt
+#define EMAC_DMARIS_AE_M 0x03800000 // Access Error
+#define EMAC_DMARIS_AE_RXDMAWD 0x00000000 // Error during RX DMA Write Data
+ // Transfer
+#define EMAC_DMARIS_AE_TXDMARD 0x01800000 // Error during TX DMA Read Data
+ // Transfer
+#define EMAC_DMARIS_AE_RXDMADW 0x02000000 // Error during RX DMA Descriptor
+ // Write Access
+#define EMAC_DMARIS_AE_TXDMADW 0x02800000 // Error during TX DMA Descriptor
+ // Write Access
+#define EMAC_DMARIS_AE_RXDMADR 0x03000000 // Error during RX DMA Descriptor
+ // Read Access
+#define EMAC_DMARIS_AE_TXDMADR 0x03800000 // Error during TX DMA Descriptor
+ // Read Access
+#define EMAC_DMARIS_TS_M 0x00700000 // Transmit Process State
+#define EMAC_DMARIS_TS_STOP 0x00000000 // Stopped; Reset or Stop transmit
+ // command processed
+#define EMAC_DMARIS_TS_RUNTXTD 0x00100000 // Running; Fetching transmit
+ // transfer descriptor
+#define EMAC_DMARIS_TS_STATUS 0x00200000 // Running; Waiting for status
+#define EMAC_DMARIS_TS_RUNTX 0x00300000 // Running; Reading data from host
+ // memory buffer and queuing it to
+ // transmit buffer (TX FIFO)
+#define EMAC_DMARIS_TS_TSTAMP 0x00400000 // Writing Timestamp
+#define EMAC_DMARIS_TS_SUSPEND 0x00600000 // Suspended; Transmit descriptor
+ // unavailable or transmit buffer
+ // underflow
+#define EMAC_DMARIS_TS_RUNCTD 0x00700000 // Running; Closing transmit
+ // descriptor
+#define EMAC_DMARIS_RS_M 0x000E0000 // Received Process State
+#define EMAC_DMARIS_RS_STOP 0x00000000 // Stopped: Reset or stop receive
+ // command issued
+#define EMAC_DMARIS_RS_RUNRXTD 0x00020000 // Running: Fetching receive
+ // transfer descriptor
+#define EMAC_DMARIS_RS_RUNRXD 0x00060000 // Running: Waiting for receive
+ // packet
+#define EMAC_DMARIS_RS_SUSPEND 0x00080000 // Suspended: Receive descriptor
+ // unavailable
+#define EMAC_DMARIS_RS_RUNCRD 0x000A0000 // Running: Closing receive
+ // descriptor
+#define EMAC_DMARIS_RS_TSWS 0x000C0000 // Writing Timestamp
+#define EMAC_DMARIS_RS_RUNTXD 0x000E0000 // Running: Transferring the
+ // receive packet data from receive
+ // buffer to host memory
+#define EMAC_DMARIS_NIS 0x00010000 // Normal Interrupt Summary
+#define EMAC_DMARIS_AIS 0x00008000 // Abnormal Interrupt Summary
+#define EMAC_DMARIS_ERI 0x00004000 // Early Receive Interrupt
+#define EMAC_DMARIS_FBI 0x00002000 // Fatal Bus Error Interrupt
+#define EMAC_DMARIS_ETI 0x00000400 // Early Transmit Interrupt
+#define EMAC_DMARIS_RWT 0x00000200 // Receive Watchdog Timeout
+#define EMAC_DMARIS_RPS 0x00000100 // Receive Process Stopped
+#define EMAC_DMARIS_RU 0x00000080 // Receive Buffer Unavailable
+#define EMAC_DMARIS_RI 0x00000040 // Receive Interrupt
+#define EMAC_DMARIS_UNF 0x00000020 // Transmit Underflow
+#define EMAC_DMARIS_OVF 0x00000010 // Receive Overflow
+#define EMAC_DMARIS_TJT 0x00000008 // Transmit Jabber Timeout
+#define EMAC_DMARIS_TU 0x00000004 // Transmit Buffer Unavailable
+#define EMAC_DMARIS_TPS 0x00000002 // Transmit Process Stopped
+#define EMAC_DMARIS_TI 0x00000001 // Transmit Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_DMAOPMODE
+// register.
+//
+//*****************************************************************************
+#define EMAC_DMAOPMODE_DT 0x04000000 // Disable Dropping of TCP/IP
+ // Checksum Error Frames
+#define EMAC_DMAOPMODE_RSF 0x02000000 // Receive Store and Forward
+#define EMAC_DMAOPMODE_DFF 0x01000000 // Disable Flushing of Received
+ // Frames
+#define EMAC_DMAOPMODE_TSF 0x00200000 // Transmit Store and Forward
+#define EMAC_DMAOPMODE_FTF 0x00100000 // Flush Transmit FIFO
+#define EMAC_DMAOPMODE_TTC_M 0x0001C000 // Transmit Threshold Control
+#define EMAC_DMAOPMODE_TTC_64 0x00000000 // 64 bytes
+#define EMAC_DMAOPMODE_TTC_128 0x00004000 // 128 bytes
+#define EMAC_DMAOPMODE_TTC_192 0x00008000 // 192 bytes
+#define EMAC_DMAOPMODE_TTC_256 0x0000C000 // 256 bytes
+#define EMAC_DMAOPMODE_TTC_40 0x00010000 // 40 bytes
+#define EMAC_DMAOPMODE_TTC_32 0x00014000 // 32 bytes
+#define EMAC_DMAOPMODE_TTC_24 0x00018000 // 24 bytes
+#define EMAC_DMAOPMODE_TTC_16 0x0001C000 // 16 bytes
+#define EMAC_DMAOPMODE_ST 0x00002000 // Start or Stop Transmission
+ // Command
+#define EMAC_DMAOPMODE_FEF 0x00000080 // Forward Error Frames
+#define EMAC_DMAOPMODE_FUF 0x00000040 // Forward Undersized Good Frames
+#define EMAC_DMAOPMODE_DGF 0x00000020 // Drop Giant Frame Enable
+#define EMAC_DMAOPMODE_RTC_M 0x00000018 // Receive Threshold Control
+#define EMAC_DMAOPMODE_RTC_64 0x00000000 // 64 bytes
+#define EMAC_DMAOPMODE_RTC_32 0x00000008 // 32 bytes
+#define EMAC_DMAOPMODE_RTC_96 0x00000010 // 96 bytes
+#define EMAC_DMAOPMODE_RTC_128 0x00000018 // 128 bytes
+#define EMAC_DMAOPMODE_OSF 0x00000004 // Operate on Second Frame
+#define EMAC_DMAOPMODE_SR 0x00000002 // Start or Stop Receive
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_DMAIM register.
+//
+//*****************************************************************************
+#define EMAC_DMAIM_NIE 0x00010000 // Normal Interrupt Summary Enable
+#define EMAC_DMAIM_AIE 0x00008000 // Abnormal Interrupt Summary
+ // Enable
+#define EMAC_DMAIM_ERE 0x00004000 // Early Receive Interrupt Enable
+#define EMAC_DMAIM_FBE 0x00002000 // Fatal Bus Error Enable
+#define EMAC_DMAIM_ETE 0x00000400 // Early Transmit Interrupt Enable
+#define EMAC_DMAIM_RWE 0x00000200 // Receive Watchdog Timeout Enable
+#define EMAC_DMAIM_RSE 0x00000100 // Receive Stopped Enable
+#define EMAC_DMAIM_RUE 0x00000080 // Receive Buffer Unavailable
+ // Enable
+#define EMAC_DMAIM_RIE 0x00000040 // Receive Interrupt Enable
+#define EMAC_DMAIM_UNE 0x00000020 // Underflow Interrupt Enable
+#define EMAC_DMAIM_OVE 0x00000010 // Overflow Interrupt Enable
+#define EMAC_DMAIM_TJE 0x00000008 // Transmit Jabber Timeout Enable
+#define EMAC_DMAIM_TUE 0x00000004 // Transmit Buffer Unvailable
+ // Enable
+#define EMAC_DMAIM_TSE 0x00000002 // Transmit Stopped Enable
+#define EMAC_DMAIM_TIE 0x00000001 // Transmit Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_MFBOC register.
+//
+//*****************************************************************************
+#define EMAC_MFBOC_OVFCNTOVF 0x10000000 // Overflow Bit for FIFO Overflow
+ // Counter
+#define EMAC_MFBOC_OVFFRMCNT_M 0x0FFE0000 // Overflow Frame Counter
+#define EMAC_MFBOC_MISCNTOVF 0x00010000 // Overflow bit for Missed Frame
+ // Counter
+#define EMAC_MFBOC_MISFRMCNT_M 0x0000FFFF // Missed Frame Counter
+#define EMAC_MFBOC_OVFFRMCNT_S 17
+#define EMAC_MFBOC_MISFRMCNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_RXINTWDT
+// register.
+//
+//*****************************************************************************
+#define EMAC_RXINTWDT_RIWT_M 0x000000FF // Receive Interrupt Watchdog Timer
+ // Count
+#define EMAC_RXINTWDT_RIWT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_HOSTXDESC
+// register.
+//
+//*****************************************************************************
+#define EMAC_HOSTXDESC_CURTXDESC_M \
+ 0xFFFFFFFF // Host Transmit Descriptor Address
+ // Pointer
+#define EMAC_HOSTXDESC_CURTXDESC_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_HOSRXDESC
+// register.
+//
+//*****************************************************************************
+#define EMAC_HOSRXDESC_CURRXDESC_M \
+ 0xFFFFFFFF // Host Receive Descriptor Address
+ // Pointer
+#define EMAC_HOSRXDESC_CURRXDESC_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_HOSTXBA register.
+//
+//*****************************************************************************
+#define EMAC_HOSTXBA_CURTXBUFA_M \
+ 0xFFFFFFFF // Host Transmit Buffer Address
+ // Pointer
+#define EMAC_HOSTXBA_CURTXBUFA_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_HOSRXBA register.
+//
+//*****************************************************************************
+#define EMAC_HOSRXBA_CURRXBUFA_M \
+ 0xFFFFFFFF // Host Receive Buffer Address
+ // Pointer
+#define EMAC_HOSRXBA_CURRXBUFA_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_PP register.
+//
+//*****************************************************************************
+#define EMAC_PP_MACTYPE_M 0x00000700 // Ethernet MAC Type
+#define EMAC_PP_MACTYPE_1 0x00000100 // Tiva TM4E129x-class MAC
+#define EMAC_PP_PHYTYPE_M 0x00000007 // Ethernet PHY Type
+#define EMAC_PP_PHYTYPE_NONE 0x00000000 // No PHY
+#define EMAC_PP_PHYTYPE_1 0x00000003 // Snowflake class PHY
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_PC register.
+//
+//*****************************************************************************
+#define EMAC_PC_PHYEXT 0x80000000 // PHY Select
+#define EMAC_PC_PINTFS_M 0x70000000 // Ethernet Interface Select
+#define EMAC_PC_PINTFS_IMII 0x00000000 // MII (default) Used for internal
+ // PHY or external PHY connected
+ // via MII
+#define EMAC_PC_PINTFS_RMII 0x40000000 // RMII: Used for external PHY
+ // connected via RMII
+#define EMAC_PC_DIGRESTART 0x02000000 // PHY Soft Restart
+#define EMAC_PC_NIBDETDIS 0x01000000 // Odd Nibble TXER Detection
+ // Disable
+#define EMAC_PC_RXERIDLE 0x00800000 // RXER Detection During Idle
+#define EMAC_PC_ISOMIILL 0x00400000 // Isolate MII in Link Loss
+#define EMAC_PC_LRR 0x00200000 // Link Loss Recovery
+#define EMAC_PC_TDRRUN 0x00100000 // TDR Auto Run
+#define EMAC_PC_FASTLDMODE_M 0x000F8000 // Fast Link Down Mode
+#define EMAC_PC_POLSWAP 0x00004000 // Polarity Swap
+#define EMAC_PC_MDISWAP 0x00002000 // MDI Swap
+#define EMAC_PC_RBSTMDIX 0x00001000 // Robust Auto MDI-X
+#define EMAC_PC_FASTMDIX 0x00000800 // Fast Auto MDI-X
+#define EMAC_PC_MDIXEN 0x00000400 // MDIX Enable
+#define EMAC_PC_FASTRXDV 0x00000200 // Fast RXDV Detection
+#define EMAC_PC_FASTLUPD 0x00000100 // FAST Link-Up in Parallel Detect
+#define EMAC_PC_EXTFD 0x00000080 // Extended Full Duplex Ability
+#define EMAC_PC_FASTANEN 0x00000040 // Fast Auto Negotiation Enable
+#define EMAC_PC_FASTANSEL_M 0x00000030 // Fast Auto Negotiation Select
+#define EMAC_PC_ANEN 0x00000008 // Auto Negotiation Enable
+#define EMAC_PC_ANMODE_M 0x00000006 // Auto Negotiation Mode
+#define EMAC_PC_ANMODE_10HD 0x00000000 // When ANEN = 0x0, the mode is
+ // 10Base-T, Half-Duplex
+#define EMAC_PC_ANMODE_10FD 0x00000002 // When ANEN = 0x0, the mode is
+ // 10Base-T, Full-Duplex
+#define EMAC_PC_ANMODE_100HD 0x00000004 // When ANEN = 0x0, the mode is
+ // 100Base-TX, Half-Duplex
+#define EMAC_PC_ANMODE_100FD 0x00000006 // When ANEN = 0x0, the mode is
+ // 100Base-TX, Full-Duplex
+#define EMAC_PC_PHYHOLD 0x00000001 // Ethernet PHY Hold
+#define EMAC_PC_FASTLDMODE_S 15
+#define EMAC_PC_FASTANSEL_S 4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_CC register.
+//
+//*****************************************************************************
+#define EMAC_CC_PTPCEN 0x00040000 // PTP Clock Reference Enable
+#define EMAC_CC_POL 0x00020000 // LED Polarity Control
+#define EMAC_CC_CLKEN 0x00010000 // EN0RREF_CLK Signal Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_EPHYRIS register.
+//
+//*****************************************************************************
+#define EMAC_EPHYRIS_INT 0x00000001 // Ethernet PHY Raw Interrupt
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_EPHYIM register.
+//
+//*****************************************************************************
+#define EMAC_EPHYIM_INT 0x00000001 // Ethernet PHY Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EMAC_O_EPHYMISC
+// register.
+//
+//*****************************************************************************
+#define EMAC_EPHYMISC_INT 0x00000001 // Ethernet PHY Status and Clear
+ // register
+
+//*****************************************************************************
+//
+// The following are defines for the EPHY register offsets.
+//
+//*****************************************************************************
+#define EPHY_BMCR 0x00000000 // Ethernet PHY Basic Mode Control
+#define EPHY_BMSR 0x00000001 // Ethernet PHY Basic Mode Status
+#define EPHY_ID1 0x00000002 // Ethernet PHY Identifier Register
+ // 1
+#define EPHY_ID2 0x00000003 // Ethernet PHY Identifier Register
+ // 2
+#define EPHY_ANA 0x00000004 // Ethernet PHY Auto-Negotiation
+ // Advertisement
+#define EPHY_ANLPA 0x00000005 // Ethernet PHY Auto-Negotiation
+ // Link Partner Ability
+#define EPHY_ANER 0x00000006 // Ethernet PHY Auto-Negotiation
+ // Expansion
+#define EPHY_ANNPTR 0x00000007 // Ethernet PHY Auto-Negotiation
+ // Next Page TX
+#define EPHY_ANLNPTR 0x00000008 // Ethernet PHY Auto-Negotiation
+ // Link Partner Ability Next Page
+#define EPHY_CFG1 0x00000009 // Ethernet PHY Configuration 1
+#define EPHY_CFG2 0x0000000A // Ethernet PHY Configuration 2
+#define EPHY_CFG3 0x0000000B // Ethernet PHY Configuration 3
+#define EPHY_REGCTL 0x0000000D // Ethernet PHY Register Control
+#define EPHY_ADDAR 0x0000000E // Ethernet PHY Address or Data
+#define EPHY_STS 0x00000010 // Ethernet PHY Status
+#define EPHY_SCR 0x00000011 // Ethernet PHY Specific Control
+#define EPHY_MISR1 0x00000012 // Ethernet PHY MII Interrupt
+ // Status 1
+#define EPHY_MISR2 0x00000013 // Ethernet PHY MII Interrupt
+ // Status 2
+#define EPHY_FCSCR 0x00000014 // Ethernet PHY False Carrier Sense
+ // Counter
+#define EPHY_RXERCNT 0x00000015 // Ethernet PHY Receive Error Count
+#define EPHY_BISTCR 0x00000016 // Ethernet PHY BIST Control
+#define EPHY_LEDCR 0x00000018 // Ethernet PHY LED Control
+#define EPHY_CTL 0x00000019 // Ethernet PHY Control
+#define EPHY_10BTSC 0x0000001A // Ethernet PHY 10Base-T
+ // Status/Control - MR26
+#define EPHY_BICSR1 0x0000001B // Ethernet PHY BIST Control and
+ // Status 1
+#define EPHY_BICSR2 0x0000001C // Ethernet PHY BIST Control and
+ // Status 2
+#define EPHY_CDCR 0x0000001E // Ethernet PHY Cable Diagnostic
+ // Control
+#define EPHY_RCR 0x0000001F // Ethernet PHY Reset Control
+#define EPHY_LEDCFG 0x00000025 // Ethernet PHY LED Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_BMCR register.
+//
+//*****************************************************************************
+#define EPHY_BMCR_MIIRESET 0x00008000 // MII Register reset
+#define EPHY_BMCR_MIILOOPBK 0x00004000 // MII Loopback
+#define EPHY_BMCR_SPEED 0x00002000 // Speed Select
+#define EPHY_BMCR_ANEN 0x00001000 // Auto-Negotiate Enable
+#define EPHY_BMCR_PWRDWN 0x00000800 // Power Down
+#define EPHY_BMCR_ISOLATE 0x00000400 // Port Isolate
+#define EPHY_BMCR_RESTARTAN 0x00000200 // Restart Auto-Negotiation
+#define EPHY_BMCR_DUPLEXM 0x00000100 // Duplex Mode
+#define EPHY_BMCR_COLLTST 0x00000080 // Collision Test
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_BMSR register.
+//
+//*****************************************************************************
+#define EPHY_BMSR_100BTXFD 0x00004000 // 100Base-TX Full Duplex Capable
+#define EPHY_BMSR_100BTXHD 0x00002000 // 100Base-TX Half Duplex Capable
+#define EPHY_BMSR_10BTFD 0x00001000 // 10 Base-T Full Duplex Capable
+#define EPHY_BMSR_10BTHD 0x00000800 // 10 Base-T Half Duplex Capable
+#define EPHY_BMSR_MFPRESUP 0x00000040 // Preamble Suppression Capable
+#define EPHY_BMSR_ANC 0x00000020 // Auto-Negotiation Complete
+#define EPHY_BMSR_RFAULT 0x00000010 // Remote Fault
+#define EPHY_BMSR_ANEN 0x00000008 // Auto Negotiation Enabled
+#define EPHY_BMSR_LINKSTAT 0x00000004 // Link Status
+#define EPHY_BMSR_JABBER 0x00000002 // Jabber Detect
+#define EPHY_BMSR_EXTEN 0x00000001 // Extended Capability Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_ID1 register.
+//
+//*****************************************************************************
+#define EPHY_ID1_OUIMSB_M 0x0000FFFF // OUI Most Significant Bits
+#define EPHY_ID1_OUIMSB_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_ID2 register.
+//
+//*****************************************************************************
+#define EPHY_ID2_OUILSB_M 0x0000FC00 // OUI Least Significant Bits
+#define EPHY_ID2_VNDRMDL_M 0x000003F0 // Vendor Model Number
+#define EPHY_ID2_MDLREV_M 0x0000000F // Model Revision Number
+#define EPHY_ID2_OUILSB_S 10
+#define EPHY_ID2_VNDRMDL_S 4
+#define EPHY_ID2_MDLREV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_ANA register.
+//
+//*****************************************************************************
+#define EPHY_ANA_NP 0x00008000 // Next Page Indication
+#define EPHY_ANA_RF 0x00002000 // Remote Fault
+#define EPHY_ANA_ASMDUP 0x00000800 // Asymmetric PAUSE support for
+ // Full Duplex Links
+#define EPHY_ANA_PAUSE 0x00000400 // PAUSE Support for Full Duplex
+ // Links
+#define EPHY_ANA_100BT4 0x00000200 // 100Base-T4 Support
+#define EPHY_ANA_100BTXFD 0x00000100 // 100Base-TX Full Duplex Support
+#define EPHY_ANA_100BTX 0x00000080 // 100Base-TX Support
+#define EPHY_ANA_10BTFD 0x00000040 // 10Base-T Full Duplex Support
+#define EPHY_ANA_10BT 0x00000020 // 10Base-T Support
+#define EPHY_ANA_SELECT_M 0x0000001F // Protocol Selection
+#define EPHY_ANA_SELECT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_ANLPA register.
+//
+//*****************************************************************************
+#define EPHY_ANLPA_NP 0x00008000 // Next Page Indication
+#define EPHY_ANLPA_ACK 0x00004000 // Acknowledge
+#define EPHY_ANLPA_RF 0x00002000 // Remote Fault
+#define EPHY_ANLPA_ASMDUP 0x00000800 // Asymmetric PAUSE
+#define EPHY_ANLPA_PAUSE 0x00000400 // PAUSE
+#define EPHY_ANLPA_100BT4 0x00000200 // 100Base-T4 Support
+#define EPHY_ANLPA_100BTXFD 0x00000100 // 100Base-TX Full Duplex Support
+#define EPHY_ANLPA_100BTX 0x00000080 // 100Base-TX Support
+#define EPHY_ANLPA_10BTFD 0x00000040 // 10Base-T Full Duplex Support
+#define EPHY_ANLPA_10BT 0x00000020 // 10Base-T Support
+#define EPHY_ANLPA_SELECT_M 0x0000001F // Protocol Selection
+#define EPHY_ANLPA_SELECT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_ANER register.
+//
+//*****************************************************************************
+#define EPHY_ANER_PDF 0x00000010 // Parallel Detection Fault
+#define EPHY_ANER_LPNPABLE 0x00000008 // Link Partner Next Page Able
+#define EPHY_ANER_NPABLE 0x00000004 // Next Page Able
+#define EPHY_ANER_PAGERX 0x00000002 // Link Code Word Page Received
+#define EPHY_ANER_LPANABLE 0x00000001 // Link Partner Auto-Negotiation
+ // Able
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_ANNPTR register.
+//
+//*****************************************************************************
+#define EPHY_ANNPTR_NP 0x00008000 // Next Page Indication
+#define EPHY_ANNPTR_MP 0x00002000 // Message Page
+#define EPHY_ANNPTR_ACK2 0x00001000 // Acknowledge 2
+#define EPHY_ANNPTR_TOGTX 0x00000800 // Toggle
+#define EPHY_ANNPTR_CODE_M 0x000007FF // Code
+#define EPHY_ANNPTR_CODE_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_ANLNPTR register.
+//
+//*****************************************************************************
+#define EPHY_ANLNPTR_NP 0x00008000 // Next Page Indication
+#define EPHY_ANLNPTR_ACK 0x00004000 // Acknowledge
+#define EPHY_ANLNPTR_MP 0x00002000 // Message Page
+#define EPHY_ANLNPTR_ACK2 0x00001000 // Acknowledge 2
+#define EPHY_ANLNPTR_TOG 0x00000800 // Toggle
+#define EPHY_ANLNPTR_CODE_M 0x000007FF // Code
+#define EPHY_ANLNPTR_CODE_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_CFG1 register.
+//
+//*****************************************************************************
+#define EPHY_CFG1_DONE 0x00008000 // Configuration Done
+#define EPHY_CFG1_TDRAR 0x00000100 // TDR Auto-Run at Link Down
+#define EPHY_CFG1_LLR 0x00000080 // Link Loss Recovery
+#define EPHY_CFG1_FAMDIX 0x00000040 // Fast Auto MDI/MDIX
+#define EPHY_CFG1_RAMDIX 0x00000020 // Robust Auto MDI/MDIX
+#define EPHY_CFG1_FASTANEN 0x00000010 // Fast Auto Negotiation Enable
+#define EPHY_CFG1_FANSEL_M 0x0000000C // Fast Auto-Negotiation Select
+ // Configuration
+#define EPHY_CFG1_FANSEL_BLT80 0x00000000 // Break Link Timer: 80 ms
+#define EPHY_CFG1_FANSEL_BLT120 0x00000004 // Break Link Timer: 120 ms
+#define EPHY_CFG1_FANSEL_BLT240 0x00000008 // Break Link Timer: 240 ms
+#define EPHY_CFG1_FRXDVDET 0x00000002 // FAST RXDV Detection
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_CFG2 register.
+//
+//*****************************************************************************
+#define EPHY_CFG2_FLUPPD 0x00000040 // Fast Link-Up in Parallel Detect
+ // Mode
+#define EPHY_CFG2_EXTFD 0x00000020 // Extended Full-Duplex Ability
+#define EPHY_CFG2_ENLEDLINK 0x00000010 // Enhanced LED Functionality
+#define EPHY_CFG2_ISOMIILL 0x00000008 // Isolate MII outputs when
+ // Enhanced Link is not Achievable
+#define EPHY_CFG2_RXERRIDLE 0x00000004 // Detection of Receive Symbol
+ // Error During IDLE State
+#define EPHY_CFG2_ODDNDETDIS 0x00000002 // Detection of Transmit Error
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_CFG3 register.
+//
+//*****************************************************************************
+#define EPHY_CFG3_POLSWAP 0x00000080 // Polarity Swap
+#define EPHY_CFG3_MDIMDIXS 0x00000040 // MDI/MDIX Swap
+#define EPHY_CFG3_FLDWNM_M 0x0000001F // Fast Link Down Modes
+#define EPHY_CFG3_FLDWNM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_REGCTL register.
+//
+//*****************************************************************************
+#define EPHY_REGCTL_FUNC_M 0x0000C000 // Function
+#define EPHY_REGCTL_FUNC_ADDR 0x00000000 // Address
+#define EPHY_REGCTL_FUNC_DATANI 0x00004000 // Data, no post increment
+#define EPHY_REGCTL_FUNC_DATAPIRW \
+ 0x00008000 // Data, post increment on read and
+ // write
+#define EPHY_REGCTL_FUNC_DATAPIWO \
+ 0x0000C000 // Data, post increment on write
+ // only
+#define EPHY_REGCTL_DEVAD_M 0x0000001F // Device Address
+#define EPHY_REGCTL_DEVAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_ADDAR register.
+//
+//*****************************************************************************
+#define EPHY_ADDAR_ADDRDATA_M 0x0000FFFF // Address or Data
+#define EPHY_ADDAR_ADDRDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_STS register.
+//
+//*****************************************************************************
+#define EPHY_STS_MDIXM 0x00004000 // MDI-X Mode
+#define EPHY_STS_RXLERR 0x00002000 // Receive Error Latch
+#define EPHY_STS_POLSTAT 0x00001000 // Polarity Status
+#define EPHY_STS_FCSL 0x00000800 // False Carrier Sense Latch
+#define EPHY_STS_SD 0x00000400 // Signal Detect
+#define EPHY_STS_DL 0x00000200 // Descrambler Lock
+#define EPHY_STS_PAGERX 0x00000100 // Link Code Page Received
+#define EPHY_STS_MIIREQ 0x00000080 // MII Interrupt Pending
+#define EPHY_STS_RF 0x00000040 // Remote Fault
+#define EPHY_STS_JD 0x00000020 // Jabber Detect
+#define EPHY_STS_ANS 0x00000010 // Auto-Negotiation Status
+#define EPHY_STS_MIILB 0x00000008 // MII Loopback Status
+#define EPHY_STS_DUPLEX 0x00000004 // Duplex Status
+#define EPHY_STS_SPEED 0x00000002 // Speed Status
+#define EPHY_STS_LINK 0x00000001 // Link Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_SCR register.
+//
+//*****************************************************************************
+#define EPHY_SCR_DISCLK 0x00008000 // Disable CLK
+#define EPHY_SCR_PSEN 0x00004000 // Power Saving Modes Enable
+#define EPHY_SCR_PSMODE_M 0x00003000 // Power Saving Modes
+#define EPHY_SCR_PSMODE_NORMAL 0x00000000 // Normal: Normal operation mode.
+ // PHY is fully functional
+#define EPHY_SCR_PSMODE_LOWPWR 0x00001000 // IEEE Power Down
+#define EPHY_SCR_PSMODE_ACTWOL 0x00002000 // Active Sleep
+#define EPHY_SCR_PSMODE_PASWOL 0x00003000 // Passive Sleep
+#define EPHY_SCR_SBPYASS 0x00000800 // Scrambler Bypass
+#define EPHY_SCR_LBFIFO_M 0x00000300 // Loopback FIFO Depth
+#define EPHY_SCR_LBFIFO_4 0x00000000 // Four nibble FIFO
+#define EPHY_SCR_LBFIFO_5 0x00000100 // Five nibble FIFO
+#define EPHY_SCR_LBFIFO_6 0x00000200 // Six nibble FIFO
+#define EPHY_SCR_LBFIFO_8 0x00000300 // Eight nibble FIFO
+#define EPHY_SCR_COLFDM 0x00000010 // Collision in Full-Duplex Mode
+#define EPHY_SCR_TINT 0x00000004 // Test Interrupt
+#define EPHY_SCR_INTEN 0x00000002 // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_MISR1 register.
+//
+//*****************************************************************************
+#define EPHY_MISR1_LINKSTAT 0x00002000 // Change of Link Status Interrupt
+#define EPHY_MISR1_SPEED 0x00001000 // Change of Speed Status Interrupt
+#define EPHY_MISR1_DUPLEXM 0x00000800 // Change of Duplex Status
+ // Interrupt
+#define EPHY_MISR1_ANC 0x00000400 // Auto-Negotiation Complete
+ // Interrupt
+#define EPHY_MISR1_FCHF 0x00000200 // False Carrier Counter Half-Full
+ // Interrupt
+#define EPHY_MISR1_RXHF 0x00000100 // Receive Error Counter Half-Full
+ // Interrupt
+#define EPHY_MISR1_LINKSTATEN 0x00000020 // Link Status Interrupt Enable
+#define EPHY_MISR1_SPEEDEN 0x00000010 // Speed Change Interrupt Enable
+#define EPHY_MISR1_DUPLEXMEN 0x00000008 // Duplex Status Interrupt Enable
+#define EPHY_MISR1_ANCEN 0x00000004 // Auto-Negotiation Complete
+ // Interrupt Enable
+#define EPHY_MISR1_FCHFEN 0x00000002 // False Carrier Counter Register
+ // half-full Interrupt Enable
+#define EPHY_MISR1_RXHFEN 0x00000001 // Receive Error Counter Register
+ // Half-Full Event Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_MISR2 register.
+//
+//*****************************************************************************
+#define EPHY_MISR2_ANERR 0x00004000 // Auto-Negotiation Error Interrupt
+#define EPHY_MISR2_PAGERX 0x00002000 // Page Receive Interrupt
+#define EPHY_MISR2_LBFIFO 0x00001000 // Loopback FIFO Overflow/Underflow
+ // Event Interrupt
+#define EPHY_MISR2_MDICO 0x00000800 // MDI/MDIX Crossover Status
+ // Changed Interrupt
+#define EPHY_MISR2_SLEEP 0x00000400 // Sleep Mode Event Interrupt
+#define EPHY_MISR2_POLINT 0x00000200 // Polarity Changed Interrupt
+#define EPHY_MISR2_JABBER 0x00000100 // Jabber Detect Event Interrupt
+#define EPHY_MISR2_ANERREN 0x00000040 // Auto-Negotiation Error Interrupt
+ // Enable
+#define EPHY_MISR2_PAGERXEN 0x00000020 // Page Receive Interrupt Enable
+#define EPHY_MISR2_LBFIFOEN 0x00000010 // Loopback FIFO Overflow/Underflow
+ // Interrupt Enable
+#define EPHY_MISR2_MDICOEN 0x00000008 // MDI/MDIX Crossover Status
+ // Changed Interrupt Enable
+#define EPHY_MISR2_SLEEPEN 0x00000004 // Sleep Mode Event Interrupt
+ // Enable
+#define EPHY_MISR2_POLINTEN 0x00000002 // Polarity Changed Interrupt
+ // Enable
+#define EPHY_MISR2_JABBEREN 0x00000001 // Jabber Detect Event Interrupt
+ // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_FCSCR register.
+//
+//*****************************************************************************
+#define EPHY_FCSCR_FCSCNT_M 0x000000FF // False Carrier Event Counter
+#define EPHY_FCSCR_FCSCNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_RXERCNT register.
+//
+//*****************************************************************************
+#define EPHY_RXERCNT_RXERRCNT_M 0x0000FFFF // Receive Error Count
+#define EPHY_RXERCNT_RXERRCNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_BISTCR register.
+//
+//*****************************************************************************
+#define EPHY_BISTCR_PRBSM 0x00004000 // PRBS Single/Continuous Mode
+#define EPHY_BISTCR_PRBSPKT 0x00002000 // Generated PRBS Packets
+#define EPHY_BISTCR_PKTEN 0x00001000 // Packet Generation Enable
+#define EPHY_BISTCR_PRBSCHKLK 0x00000800 // PRBS Checker Lock Indication
+#define EPHY_BISTCR_PRBSCHKSYNC 0x00000400 // PRBS Checker Lock Sync Loss
+ // Indication
+#define EPHY_BISTCR_PKTGENSTAT 0x00000200 // Packet Generator Status
+ // Indication
+#define EPHY_BISTCR_PWRMODE 0x00000100 // Power Mode Indication
+#define EPHY_BISTCR_TXMIILB 0x00000040 // Transmit Data in MII Loopback
+ // Mode
+#define EPHY_BISTCR_LBMODE_M 0x0000001F // Loopback Mode Select
+#define EPHY_BISTCR_LBMODE_NPCSIN \
+ 0x00000001 // Near-end loopback: PCS Input
+ // Loopback
+#define EPHY_BISTCR_LBMODE_NPCSOUT \
+ 0x00000002 // Near-end loopback: PCS Output
+ // Loopback (In 100Base-TX only)
+#define EPHY_BISTCR_LBMODE_NDIG 0x00000004 // Near-end loopback: Digital
+ // Loopback
+#define EPHY_BISTCR_LBMODE_NANA 0x00000008 // Near-end loopback: Analog
+ // Loopback (requires 100 Ohm
+ // termination)
+#define EPHY_BISTCR_LBMODE_FREV 0x00000010 // Far-end Loopback: Reverse
+ // Loopback
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_LEDCR register.
+//
+//*****************************************************************************
+#define EPHY_LEDCR_BLINKRATE_M 0x00000600 // LED Blinking Rate (ON/OFF
+ // duration):
+#define EPHY_LEDCR_BLINKRATE_20HZ \
+ 0x00000000 // 20 Hz (50 ms)
+#define EPHY_LEDCR_BLINKRATE_10HZ \
+ 0x00000200 // 10 Hz (100 ms)
+#define EPHY_LEDCR_BLINKRATE_5HZ \
+ 0x00000400 // 5 Hz (200 ms)
+#define EPHY_LEDCR_BLINKRATE_2HZ \
+ 0x00000600 // 2 Hz (500 ms)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_CTL register.
+//
+//*****************************************************************************
+#define EPHY_CTL_AUTOMDI 0x00008000 // Auto-MDIX Enable
+#define EPHY_CTL_FORCEMDI 0x00004000 // Force MDIX
+#define EPHY_CTL_PAUSERX 0x00002000 // Pause Receive Negotiated Status
+#define EPHY_CTL_PAUSETX 0x00001000 // Pause Transmit Negotiated Status
+#define EPHY_CTL_MIILNKSTAT 0x00000800 // MII Link Status
+#define EPHY_CTL_BYPLEDSTRCH 0x00000080 // Bypass LED Stretching
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_10BTSC register.
+//
+//*****************************************************************************
+#define EPHY_10BTSC_RXTHEN 0x00002000 // Lower Receiver Threshold Enable
+#define EPHY_10BTSC_SQUELCH_M 0x00001E00 // Squelch Configuration
+#define EPHY_10BTSC_NLPDIS 0x00000080 // Normal Link Pulse (NLP)
+ // Transmission Control
+#define EPHY_10BTSC_POLSTAT 0x00000010 // 10 Mb Polarity Status
+#define EPHY_10BTSC_JABBERD 0x00000001 // Jabber Disable
+#define EPHY_10BTSC_SQUELCH_S 9
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_BICSR1 register.
+//
+//*****************************************************************************
+#define EPHY_BICSR1_ERRCNT_M 0x0000FF00 // BIST Error Count
+#define EPHY_BICSR1_IPGLENGTH_M 0x000000FF // BIST IPG Length
+#define EPHY_BICSR1_ERRCNT_S 8
+#define EPHY_BICSR1_IPGLENGTH_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_BICSR2 register.
+//
+//*****************************************************************************
+#define EPHY_BICSR2_PKTLENGTH_M 0x000007FF // BIST Packet Length
+#define EPHY_BICSR2_PKTLENGTH_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_CDCR register.
+//
+//*****************************************************************************
+#define EPHY_CDCR_START 0x00008000 // Cable Diagnostic Process Start
+#define EPHY_CDCR_LINKQUAL_M 0x00000300 // Link Quality Indication
+#define EPHY_CDCR_LINKQUAL_GOOD 0x00000100 // Good Quality Link Indication
+#define EPHY_CDCR_LINKQUAL_MILD 0x00000200 // Mid- Quality Link Indication
+#define EPHY_CDCR_LINKQUAL_POOR 0x00000300 // Poor Quality Link Indication
+#define EPHY_CDCR_DONE 0x00000002 // Cable Diagnostic Process Done
+#define EPHY_CDCR_FAIL 0x00000001 // Cable Diagnostic Process Fail
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_RCR register.
+//
+//*****************************************************************************
+#define EPHY_RCR_SWRST 0x00008000 // Software Reset
+#define EPHY_RCR_SWRESTART 0x00004000 // Software Restart
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPHY_LEDCFG register.
+//
+//*****************************************************************************
+#define EPHY_LEDCFG_LED2_M 0x00000F00 // LED2 Configuration
+#define EPHY_LEDCFG_LED2_LINK 0x00000000 // Link OK
+#define EPHY_LEDCFG_LED2_RXTX 0x00000100 // RX/TX Activity
+#define EPHY_LEDCFG_LED2_TX 0x00000200 // TX Activity
+#define EPHY_LEDCFG_LED2_RX 0x00000300 // RX Activity
+#define EPHY_LEDCFG_LED2_COL 0x00000400 // Collision
+#define EPHY_LEDCFG_LED2_100BT 0x00000500 // 100-Base TX
+#define EPHY_LEDCFG_LED2_10BT 0x00000600 // 10-Base TX
+#define EPHY_LEDCFG_LED2_FD 0x00000700 // Full Duplex
+#define EPHY_LEDCFG_LED2_LINKTXRX \
+ 0x00000800 // Link OK/Blink on TX/RX Activity
+#define EPHY_LEDCFG_LED1_M 0x000000F0 // LED1 Configuration
+#define EPHY_LEDCFG_LED1_LINK 0x00000000 // Link OK
+#define EPHY_LEDCFG_LED1_RXTX 0x00000010 // RX/TX Activity
+#define EPHY_LEDCFG_LED1_TX 0x00000020 // TX Activity
+#define EPHY_LEDCFG_LED1_RX 0x00000030 // RX Activity
+#define EPHY_LEDCFG_LED1_COL 0x00000040 // Collision
+#define EPHY_LEDCFG_LED1_100BT 0x00000050 // 100-Base TX
+#define EPHY_LEDCFG_LED1_10BT 0x00000060 // 10-Base TX
+#define EPHY_LEDCFG_LED1_FD 0x00000070 // Full Duplex
+#define EPHY_LEDCFG_LED1_LINKTXRX \
+ 0x00000080 // Link OK/Blink on TX/RX Activity
+#define EPHY_LEDCFG_LED0_M 0x0000000F // LED0 Configuration
+#define EPHY_LEDCFG_LED0_LINK 0x00000000 // Link OK
+#define EPHY_LEDCFG_LED0_RXTX 0x00000001 // RX/TX Activity
+#define EPHY_LEDCFG_LED0_TX 0x00000002 // TX Activity
+#define EPHY_LEDCFG_LED0_RX 0x00000003 // RX Activity
+#define EPHY_LEDCFG_LED0_COL 0x00000004 // Collision
+#define EPHY_LEDCFG_LED0_100BT 0x00000005 // 100-Base TX
+#define EPHY_LEDCFG_LED0_10BT 0x00000006 // 10-Base TX
+#define EPHY_LEDCFG_LED0_FD 0x00000007 // Full Duplex
+#define EPHY_LEDCFG_LED0_LINKTXRX \
+ 0x00000008 // Link OK/Blink on TX/RX Activity
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the
+// EMAC_O_PPSCTRL register.
+//
+//*****************************************************************************
+#define EMAC_PPSCTRL_PPSCTRL_1HZ \
+ 0x00000000 // When the PPSEN0 bit = 0x0, the
+ // EN0PPS signal is 1 pulse of the
+ // PTP reference clock.(of width
+ // clk_ptp_i) every second
+#define EMAC_PPSCTRL_PPSCTRL_2HZ \
+ 0x00000001 // When the PPSEN0 bit = 0x0, the
+ // binary rollover is 2 Hz, and the
+ // digital rollover is 1 Hz
+#define EMAC_PPSCTRL_PPSCTRL_4HZ \
+ 0x00000002 // When the PPSEN0 bit = 0x0, the
+ // binary rollover is 4 Hz, and the
+ // digital rollover is 2 Hz
+#define EMAC_PPSCTRL_PPSCTRL_8HZ \
+ 0x00000003 // When thePPSEN0 bit = 0x0, the
+ // binary rollover is 8 Hz, and the
+ // digital rollover is 4 Hz,
+#define EMAC_PPSCTRL_PPSCTRL_16HZ \
+ 0x00000004 // When thePPSEN0 bit = 0x0, the
+ // binary rollover is 16 Hz, and
+ // the digital rollover is 8 Hz
+#define EMAC_PPSCTRL_PPSCTRL_32HZ \
+ 0x00000005 // When thePPSEN0 bit = 0x0, the
+ // binary rollover is 32 Hz, and
+ // the digital rollover is 16 Hz
+#define EMAC_PPSCTRL_PPSCTRL_64HZ \
+ 0x00000006 // When thePPSEN0 bit = 0x0, the
+ // binary rollover is 64 Hz, and
+ // the digital rollover is 32 Hz
+#define EMAC_PPSCTRL_PPSCTRL_128HZ \
+ 0x00000007 // When thePPSEN0 bit = 0x0, the
+ // binary rollover is 128 Hz, and
+ // the digital rollover is 64 Hz
+#define EMAC_PPSCTRL_PPSCTRL_256HZ \
+ 0x00000008 // When thePPSEN0 bit = 0x0, the
+ // binary rollover is 256 Hz, and
+ // the digital rollover is 128 Hz
+#define EMAC_PPSCTRL_PPSCTRL_512HZ \
+ 0x00000009 // When thePPSEN0 bit = 0x0, the
+ // binary rollover is 512 Hz, and
+ // the digital rollover is 256 Hz
+#define EMAC_PPSCTRL_PPSCTRL_1024HZ \
+ 0x0000000A // When the PPSEN0 bit = 0x0, the
+ // binary rollover is 1.024 kHz,
+ // and the digital rollover is 512
+ // Hz
+#define EMAC_PPSCTRL_PPSCTRL_2048HZ \
+ 0x0000000B // When thePPSEN0 bit = 0x0, the
+ // binary rollover is 2.048 kHz,
+ // and the digital rollover is
+ // 1.024 kHz
+#define EMAC_PPSCTRL_PPSCTRL_4096HZ \
+ 0x0000000C // When thePPSEN0 bit = 0x0, the
+ // binary rollover is 4.096 kHz,
+ // and the digital rollover is
+ // 2.048 kHz
+#define EMAC_PPSCTRL_PPSCTRL_8192HZ \
+ 0x0000000D // When thePPSEN0 bit = 0x0, the
+ // binary rollover is 8.192 kHz,
+ // and the digital rollover is
+ // 4.096 kHz
+#define EMAC_PPSCTRL_PPSCTRL_16384HZ \
+ 0x0000000E // When thePPSEN0 bit = 0x0, the
+ // binary rollover is 16.384 kHz,
+ // and the digital rollover is
+ // 8.092 kHz
+#define EMAC_PPSCTRL_PPSCTRL_32768HZ \
+ 0x0000000F // When thePPSEN0 bit = 0x0, the
+ // binary rollover is 32.768 KHz,
+ // and the digital rollover is
+ // 16.384 KHz
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the EMAC_O_CC
+// register.
+//
+//*****************************************************************************
+#define EMAC_CC_CS_PA7 0x00000001 // GPIO
+
+#endif
+
+#endif // __HW_EMAC_H__
diff --git a/os/common/ext/TivaWare/inc/hw_epi.h b/os/common/ext/TivaWare/inc/hw_epi.h
new file mode 100644
index 0000000..54b59c3
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_epi.h
@@ -0,0 +1,933 @@
+//*****************************************************************************
+//
+// hw_epi.h - Macros for use in accessing the EPI registers.
+//
+// Copyright (c) 2008-2016 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_EPI_H__
+#define __HW_EPI_H__
+
+//*****************************************************************************
+//
+// The following are defines for the External Peripheral Interface register
+// offsets.
+//
+//*****************************************************************************
+#define EPI_O_CFG 0x00000000 // EPI Configuration
+#define EPI_O_BAUD 0x00000004 // EPI Main Baud Rate
+#define EPI_O_BAUD2 0x00000008 // EPI Main Baud Rate
+#define EPI_O_HB16CFG 0x00000010 // EPI Host-Bus 16 Configuration
+#define EPI_O_GPCFG 0x00000010 // EPI General-Purpose
+ // Configuration
+#define EPI_O_SDRAMCFG 0x00000010 // EPI SDRAM Configuration
+#define EPI_O_HB8CFG 0x00000010 // EPI Host-Bus 8 Configuration
+#define EPI_O_HB8CFG2 0x00000014 // EPI Host-Bus 8 Configuration 2
+#define EPI_O_HB16CFG2 0x00000014 // EPI Host-Bus 16 Configuration 2
+#define EPI_O_ADDRMAP 0x0000001C // EPI Address Map
+#define EPI_O_RSIZE0 0x00000020 // EPI Read Size 0
+#define EPI_O_RADDR0 0x00000024 // EPI Read Address 0
+#define EPI_O_RPSTD0 0x00000028 // EPI Non-Blocking Read Data 0
+#define EPI_O_RSIZE1 0x00000030 // EPI Read Size 1
+#define EPI_O_RADDR1 0x00000034 // EPI Read Address 1
+#define EPI_O_RPSTD1 0x00000038 // EPI Non-Blocking Read Data 1
+#define EPI_O_STAT 0x00000060 // EPI Status
+#define EPI_O_RFIFOCNT 0x0000006C // EPI Read FIFO Count
+#define EPI_O_READFIFO0 0x00000070 // EPI Read FIFO
+#define EPI_O_READFIFO1 0x00000074 // EPI Read FIFO Alias 1
+#define EPI_O_READFIFO2 0x00000078 // EPI Read FIFO Alias 2
+#define EPI_O_READFIFO3 0x0000007C // EPI Read FIFO Alias 3
+#define EPI_O_READFIFO4 0x00000080 // EPI Read FIFO Alias 4
+#define EPI_O_READFIFO5 0x00000084 // EPI Read FIFO Alias 5
+#define EPI_O_READFIFO6 0x00000088 // EPI Read FIFO Alias 6
+#define EPI_O_READFIFO7 0x0000008C // EPI Read FIFO Alias 7
+#define EPI_O_FIFOLVL 0x00000200 // EPI FIFO Level Selects
+#define EPI_O_WFIFOCNT 0x00000204 // EPI Write FIFO Count
+#define EPI_O_DMATXCNT 0x00000208 // EPI DMA Transmit Count
+#define EPI_O_IM 0x00000210 // EPI Interrupt Mask
+#define EPI_O_RIS 0x00000214 // EPI Raw Interrupt Status
+#define EPI_O_MIS 0x00000218 // EPI Masked Interrupt Status
+#define EPI_O_EISC 0x0000021C // EPI Error and Interrupt Status
+ // and Clear
+#define EPI_O_HB8CFG3 0x00000308 // EPI Host-Bus 8 Configuration 3
+#define EPI_O_HB16CFG3 0x00000308 // EPI Host-Bus 16 Configuration 3
+#define EPI_O_HB16CFG4 0x0000030C // EPI Host-Bus 16 Configuration 4
+#define EPI_O_HB8CFG4 0x0000030C // EPI Host-Bus 8 Configuration 4
+#define EPI_O_HB8TIME 0x00000310 // EPI Host-Bus 8 Timing Extension
+#define EPI_O_HB16TIME 0x00000310 // EPI Host-Bus 16 Timing Extension
+#define EPI_O_HB8TIME2 0x00000314 // EPI Host-Bus 8 Timing Extension
+#define EPI_O_HB16TIME2 0x00000314 // EPI Host-Bus 16 Timing Extension
+#define EPI_O_HB16TIME3 0x00000318 // EPI Host-Bus 16 Timing Extension
+#define EPI_O_HB8TIME3 0x00000318 // EPI Host-Bus 8 Timing Extension
+#define EPI_O_HB8TIME4 0x0000031C // EPI Host-Bus 8 Timing Extension
+#define EPI_O_HB16TIME4 0x0000031C // EPI Host-Bus 16 Timing Extension
+#define EPI_O_HBPSRAM 0x00000360 // EPI Host-Bus PSRAM
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_CFG register.
+//
+//*****************************************************************************
+#define EPI_CFG_INTDIV 0x00000100 // Integer Clock Divider Enable
+#define EPI_CFG_BLKEN 0x00000010 // Block Enable
+#define EPI_CFG_MODE_M 0x0000000F // Mode Select
+#define EPI_CFG_MODE_NONE 0x00000000 // General Purpose
+#define EPI_CFG_MODE_SDRAM 0x00000001 // SDRAM
+#define EPI_CFG_MODE_HB8 0x00000002 // 8-Bit Host-Bus (HB8)
+#define EPI_CFG_MODE_HB16 0x00000003 // 16-Bit Host-Bus (HB16)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_BAUD register.
+//
+//*****************************************************************************
+#define EPI_BAUD_COUNT1_M 0xFFFF0000 // Baud Rate Counter 1
+#define EPI_BAUD_COUNT0_M 0x0000FFFF // Baud Rate Counter 0
+#define EPI_BAUD_COUNT1_S 16
+#define EPI_BAUD_COUNT0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_BAUD2 register.
+//
+//*****************************************************************************
+#define EPI_BAUD2_COUNT1_M 0xFFFF0000 // CS3n Baud Rate Counter 1
+#define EPI_BAUD2_COUNT0_M 0x0000FFFF // CS2n Baud Rate Counter 0
+#define EPI_BAUD2_COUNT1_S 16
+#define EPI_BAUD2_COUNT0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16CFG register.
+//
+//*****************************************************************************
+#define EPI_HB16CFG_CLKGATE 0x80000000 // Clock Gated
+#define EPI_HB16CFG_CLKGATEI 0x40000000 // Clock Gated Idle
+#define EPI_HB16CFG_CLKINV 0x20000000 // Invert Output Clock Enable
+#define EPI_HB16CFG_RDYEN 0x10000000 // Input Ready Enable
+#define EPI_HB16CFG_IRDYINV 0x08000000 // Input Ready Invert
+#define EPI_HB16CFG_XFFEN 0x00800000 // External FIFO FULL Enable
+#define EPI_HB16CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable
+#define EPI_HB16CFG_WRHIGH 0x00200000 // WRITE Strobe Polarity
+#define EPI_HB16CFG_RDHIGH 0x00100000 // READ Strobe Polarity
+#define EPI_HB16CFG_ALEHIGH 0x00080000 // ALE Strobe Polarity
+#define EPI_HB16CFG_WRCRE 0x00040000 // PSRAM Configuration Register
+ // Write
+#define EPI_HB16CFG_RDCRE 0x00020000 // PSRAM Configuration Register
+ // Read
+#define EPI_HB16CFG_BURST 0x00010000 // Burst Mode
+#define EPI_HB16CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait
+#define EPI_HB16CFG_WRWS_M 0x000000C0 // Write Wait States
+#define EPI_HB16CFG_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks
+#define EPI_HB16CFG_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks
+#define EPI_HB16CFG_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks
+#define EPI_HB16CFG_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks
+#define EPI_HB16CFG_RDWS_M 0x00000030 // Read Wait States
+#define EPI_HB16CFG_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks
+#define EPI_HB16CFG_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks
+#define EPI_HB16CFG_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks
+#define EPI_HB16CFG_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks
+#define EPI_HB16CFG_BSEL 0x00000004 // Byte Select Configuration
+#define EPI_HB16CFG_MODE_M 0x00000003 // Host Bus Sub-Mode
+#define EPI_HB16CFG_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0]
+#define EPI_HB16CFG_MODE_ADNMUX 0x00000001 // ADNONMUX - D[15:0]
+#define EPI_HB16CFG_MODE_SRAM 0x00000002 // Continuous Read - D[15:0]
+#define EPI_HB16CFG_MODE_XFIFO 0x00000003 // XFIFO - D[15:0]
+#define EPI_HB16CFG_MAXWAIT_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_GPCFG register.
+//
+//*****************************************************************************
+#define EPI_GPCFG_CLKPIN 0x80000000 // Clock Pin
+#define EPI_GPCFG_CLKGATE 0x40000000 // Clock Gated
+#define EPI_GPCFG_FRM50 0x04000000 // 50/50 Frame
+#define EPI_GPCFG_FRMCNT_M 0x03C00000 // Frame Count
+#define EPI_GPCFG_WR2CYC 0x00080000 // 2-Cycle Writes
+#define EPI_GPCFG_ASIZE_M 0x00000030 // Address Bus Size
+#define EPI_GPCFG_ASIZE_NONE 0x00000000 // No address
+#define EPI_GPCFG_ASIZE_4BIT 0x00000010 // Up to 4 bits wide
+#define EPI_GPCFG_ASIZE_12BIT 0x00000020 // Up to 12 bits wide. This size
+ // cannot be used with 24-bit data
+#define EPI_GPCFG_ASIZE_20BIT 0x00000030 // Up to 20 bits wide. This size
+ // cannot be used with data sizes
+ // other than 8
+#define EPI_GPCFG_DSIZE_M 0x00000003 // Size of Data Bus
+#define EPI_GPCFG_DSIZE_4BIT 0x00000000 // 8 Bits Wide (EPI0S0 to EPI0S7)
+#define EPI_GPCFG_DSIZE_16BIT 0x00000001 // 16 Bits Wide (EPI0S0 to EPI0S15)
+#define EPI_GPCFG_DSIZE_24BIT 0x00000002 // 24 Bits Wide (EPI0S0 to EPI0S23)
+#define EPI_GPCFG_DSIZE_32BIT 0x00000003 // 32 Bits Wide (EPI0S0 to EPI0S31)
+#define EPI_GPCFG_FRMCNT_S 22
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_SDRAMCFG register.
+//
+//*****************************************************************************
+#define EPI_SDRAMCFG_FREQ_M 0xC0000000 // EPI Frequency Range
+#define EPI_SDRAMCFG_FREQ_NONE 0x00000000 // 0 - 15 MHz
+#define EPI_SDRAMCFG_FREQ_15MHZ 0x40000000 // 15 - 30 MHz
+#define EPI_SDRAMCFG_FREQ_30MHZ 0x80000000 // 30 - 50 MHz
+#define EPI_SDRAMCFG_RFSH_M 0x07FF0000 // Refresh Counter
+#define EPI_SDRAMCFG_SLEEP 0x00000200 // Sleep Mode
+#define EPI_SDRAMCFG_SIZE_M 0x00000003 // Size of SDRAM
+#define EPI_SDRAMCFG_SIZE_8MB 0x00000000 // 64 megabits (8MB)
+#define EPI_SDRAMCFG_SIZE_16MB 0x00000001 // 128 megabits (16MB)
+#define EPI_SDRAMCFG_SIZE_32MB 0x00000002 // 256 megabits (32MB)
+#define EPI_SDRAMCFG_SIZE_64MB 0x00000003 // 512 megabits (64MB)
+#define EPI_SDRAMCFG_RFSH_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8CFG register.
+//
+//*****************************************************************************
+#define EPI_HB8CFG_CLKGATE 0x80000000 // Clock Gated
+#define EPI_HB8CFG_CLKGATEI 0x40000000 // Clock Gated when Idle
+#define EPI_HB8CFG_CLKINV 0x20000000 // Invert Output Clock Enable
+#define EPI_HB8CFG_RDYEN 0x10000000 // Input Ready Enable
+#define EPI_HB8CFG_IRDYINV 0x08000000 // Input Ready Invert
+#define EPI_HB8CFG_XFFEN 0x00800000 // External FIFO FULL Enable
+#define EPI_HB8CFG_XFEEN 0x00400000 // External FIFO EMPTY Enable
+#define EPI_HB8CFG_WRHIGH 0x00200000 // WRITE Strobe Polarity
+#define EPI_HB8CFG_RDHIGH 0x00100000 // READ Strobe Polarity
+#define EPI_HB8CFG_ALEHIGH 0x00080000 // ALE Strobe Polarity
+#define EPI_HB8CFG_MAXWAIT_M 0x0000FF00 // Maximum Wait
+#define EPI_HB8CFG_WRWS_M 0x000000C0 // Write Wait States
+#define EPI_HB8CFG_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks
+#define EPI_HB8CFG_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks
+#define EPI_HB8CFG_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks
+#define EPI_HB8CFG_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks
+#define EPI_HB8CFG_RDWS_M 0x00000030 // Read Wait States
+#define EPI_HB8CFG_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks
+#define EPI_HB8CFG_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks
+#define EPI_HB8CFG_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks
+#define EPI_HB8CFG_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks
+#define EPI_HB8CFG_MODE_M 0x00000003 // Host Bus Sub-Mode
+#define EPI_HB8CFG_MODE_MUX 0x00000000 // ADMUX - AD[7:0]
+#define EPI_HB8CFG_MODE_NMUX 0x00000001 // ADNONMUX - D[7:0]
+#define EPI_HB8CFG_MODE_SRAM 0x00000002 // Continuous Read - D[7:0]
+#define EPI_HB8CFG_MODE_FIFO 0x00000003 // XFIFO - D[7:0]
+#define EPI_HB8CFG_MAXWAIT_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8CFG2 register.
+//
+//*****************************************************************************
+#define EPI_HB8CFG2_CSCFGEXT 0x08000000 // Chip Select Extended
+ // Configuration
+#define EPI_HB8CFG2_CSBAUD 0x04000000 // Chip Select Baud Rate and
+ // Multiple Sub-Mode Configuration
+ // enable
+#define EPI_HB8CFG2_CSCFG_M 0x03000000 // Chip Select Configuration
+#define EPI_HB8CFG2_CSCFG_ALE 0x00000000 // ALE Configuration
+#define EPI_HB8CFG2_CSCFG_CS 0x01000000 // CSn Configuration
+#define EPI_HB8CFG2_CSCFG_DCS 0x02000000 // Dual CSn Configuration
+#define EPI_HB8CFG2_CSCFG_ADCS 0x03000000 // ALE with Dual CSn Configuration
+#define EPI_HB8CFG2_WRHIGH 0x00200000 // CS1n WRITE Strobe Polarity
+#define EPI_HB8CFG2_RDHIGH 0x00100000 // CS1n READ Strobe Polarity
+#define EPI_HB8CFG2_ALEHIGH 0x00080000 // CS1n ALE Strobe Polarity
+#define EPI_HB8CFG2_WRWS_M 0x000000C0 // CS1n Write Wait States
+#define EPI_HB8CFG2_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks
+#define EPI_HB8CFG2_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks
+#define EPI_HB8CFG2_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks
+#define EPI_HB8CFG2_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks
+#define EPI_HB8CFG2_RDWS_M 0x00000030 // CS1n Read Wait States
+#define EPI_HB8CFG2_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks
+#define EPI_HB8CFG2_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks
+#define EPI_HB8CFG2_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks
+#define EPI_HB8CFG2_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks
+#define EPI_HB8CFG2_MODE_M 0x00000003 // CS1n Host Bus Sub-Mode
+#define EPI_HB8CFG2_MODE_ADMUX 0x00000000 // ADMUX - AD[7:0]
+#define EPI_HB8CFG2_MODE_AD 0x00000001 // ADNONMUX - D[7:0]
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16CFG2 register.
+//
+//*****************************************************************************
+#define EPI_HB16CFG2_CSCFGEXT 0x08000000 // Chip Select Extended
+ // Configuration
+#define EPI_HB16CFG2_CSBAUD 0x04000000 // Chip Select Baud Rate and
+ // Multiple Sub-Mode Configuration
+ // enable
+#define EPI_HB16CFG2_CSCFG_M 0x03000000 // Chip Select Configuration
+#define EPI_HB16CFG2_CSCFG_ALE 0x00000000 // ALE Configuration
+#define EPI_HB16CFG2_CSCFG_CS 0x01000000 // CSn Configuration
+#define EPI_HB16CFG2_CSCFG_DCS 0x02000000 // Dual CSn Configuration
+#define EPI_HB16CFG2_CSCFG_ADCS 0x03000000 // ALE with Dual CSn Configuration
+#define EPI_HB16CFG2_WRHIGH 0x00200000 // CS1n WRITE Strobe Polarity
+#define EPI_HB16CFG2_RDHIGH 0x00100000 // CS1n READ Strobe Polarity
+#define EPI_HB16CFG2_ALEHIGH 0x00080000 // CS1n ALE Strobe Polarity
+#define EPI_HB16CFG2_WRCRE 0x00040000 // CS1n PSRAM Configuration
+ // Register Write
+#define EPI_HB16CFG2_RDCRE 0x00020000 // CS1n PSRAM Configuration
+ // Register Read
+#define EPI_HB16CFG2_BURST 0x00010000 // CS1n Burst Mode
+#define EPI_HB16CFG2_WRWS_M 0x000000C0 // CS1n Write Wait States
+#define EPI_HB16CFG2_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks
+#define EPI_HB16CFG2_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks
+#define EPI_HB16CFG2_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks
+#define EPI_HB16CFG2_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks
+#define EPI_HB16CFG2_RDWS_M 0x00000030 // CS1n Read Wait States
+#define EPI_HB16CFG2_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks
+#define EPI_HB16CFG2_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks
+#define EPI_HB16CFG2_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks
+#define EPI_HB16CFG2_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks
+#define EPI_HB16CFG2_MODE_M 0x00000003 // CS1n Host Bus Sub-Mode
+#define EPI_HB16CFG2_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0]
+#define EPI_HB16CFG2_MODE_AD 0x00000001 // ADNONMUX - D[15:0]
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_ADDRMAP register.
+//
+//*****************************************************************************
+#define EPI_ADDRMAP_ECSZ_M 0x00000C00 // External Code Size
+#define EPI_ADDRMAP_ECSZ_256B 0x00000000 // 256 bytes; lower address range:
+ // 0x00 to 0xFF
+#define EPI_ADDRMAP_ECSZ_64KB 0x00000400 // 64 KB; lower address range:
+ // 0x0000 to 0xFFFF
+#define EPI_ADDRMAP_ECSZ_16MB 0x00000800 // 16 MB; lower address range:
+ // 0x00.0000 to 0xFF.FFFF
+#define EPI_ADDRMAP_ECSZ_256MB 0x00000C00 // 256MB; lower address range:
+ // 0x000.0000 to 0x0FFF.FFFF
+#define EPI_ADDRMAP_ECADR_M 0x00000300 // External Code Address
+#define EPI_ADDRMAP_ECADR_NONE 0x00000000 // Not mapped
+#define EPI_ADDRMAP_ECADR_1000 0x00000100 // At 0x1000.0000
+#define EPI_ADDRMAP_EPSZ_M 0x000000C0 // External Peripheral Size
+#define EPI_ADDRMAP_EPSZ_256B 0x00000000 // 256 bytes; lower address range:
+ // 0x00 to 0xFF
+#define EPI_ADDRMAP_EPSZ_64KB 0x00000040 // 64 KB; lower address range:
+ // 0x0000 to 0xFFFF
+#define EPI_ADDRMAP_EPSZ_16MB 0x00000080 // 16 MB; lower address range:
+ // 0x00.0000 to 0xFF.FFFF
+#define EPI_ADDRMAP_EPSZ_256MB 0x000000C0 // 256 MB; lower address range:
+ // 0x000.0000 to 0xFFF.FFFF
+#define EPI_ADDRMAP_EPADR_M 0x00000030 // External Peripheral Address
+#define EPI_ADDRMAP_EPADR_NONE 0x00000000 // Not mapped
+#define EPI_ADDRMAP_EPADR_A000 0x00000010 // At 0xA000.0000
+#define EPI_ADDRMAP_EPADR_C000 0x00000020 // At 0xC000.0000
+#define EPI_ADDRMAP_EPADR_HBQS 0x00000030 // Only to be used with Host Bus
+ // quad chip select. In quad chip
+ // select mode, CS2n maps to
+ // 0xA000.0000 and CS3n maps to
+ // 0xC000.0000
+#define EPI_ADDRMAP_ERSZ_M 0x0000000C // External RAM Size
+#define EPI_ADDRMAP_ERSZ_256B 0x00000000 // 256 bytes; lower address range:
+ // 0x00 to 0xFF
+#define EPI_ADDRMAP_ERSZ_64KB 0x00000004 // 64 KB; lower address range:
+ // 0x0000 to 0xFFFF
+#define EPI_ADDRMAP_ERSZ_16MB 0x00000008 // 16 MB; lower address range:
+ // 0x00.0000 to 0xFF.FFFF
+#define EPI_ADDRMAP_ERSZ_256MB 0x0000000C // 256 MB; lower address range:
+ // 0x000.0000 to 0xFFF.FFFF
+#define EPI_ADDRMAP_ERADR_M 0x00000003 // External RAM Address
+#define EPI_ADDRMAP_ERADR_NONE 0x00000000 // Not mapped
+#define EPI_ADDRMAP_ERADR_6000 0x00000001 // At 0x6000.0000
+#define EPI_ADDRMAP_ERADR_8000 0x00000002 // At 0x8000.0000
+#define EPI_ADDRMAP_ERADR_HBQS 0x00000003 // Only to be used with Host Bus
+ // quad chip select. In quad chip
+ // select mode, CS0n maps to
+ // 0x6000.0000 and CS1n maps to
+ // 0x8000.0000
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RSIZE0 register.
+//
+//*****************************************************************************
+#define EPI_RSIZE0_SIZE_M 0x00000003 // Current Size
+#define EPI_RSIZE0_SIZE_8BIT 0x00000001 // Byte (8 bits)
+#define EPI_RSIZE0_SIZE_16BIT 0x00000002 // Half-word (16 bits)
+#define EPI_RSIZE0_SIZE_32BIT 0x00000003 // Word (32 bits)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RADDR0 register.
+//
+//*****************************************************************************
+#define EPI_RADDR0_ADDR_M 0xFFFFFFFF // Current Address
+#define EPI_RADDR0_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RPSTD0 register.
+//
+//*****************************************************************************
+#define EPI_RPSTD0_POSTCNT_M 0x00001FFF // Post Count
+#define EPI_RPSTD0_POSTCNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RSIZE1 register.
+//
+//*****************************************************************************
+#define EPI_RSIZE1_SIZE_M 0x00000003 // Current Size
+#define EPI_RSIZE1_SIZE_8BIT 0x00000001 // Byte (8 bits)
+#define EPI_RSIZE1_SIZE_16BIT 0x00000002 // Half-word (16 bits)
+#define EPI_RSIZE1_SIZE_32BIT 0x00000003 // Word (32 bits)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RADDR1 register.
+//
+//*****************************************************************************
+#define EPI_RADDR1_ADDR_M 0xFFFFFFFF // Current Address
+#define EPI_RADDR1_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RPSTD1 register.
+//
+//*****************************************************************************
+#define EPI_RPSTD1_POSTCNT_M 0x00001FFF // Post Count
+#define EPI_RPSTD1_POSTCNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_STAT register.
+//
+//*****************************************************************************
+#define EPI_STAT_XFFULL 0x00000100 // External FIFO Full
+#define EPI_STAT_XFEMPTY 0x00000080 // External FIFO Empty
+#define EPI_STAT_INITSEQ 0x00000040 // Initialization Sequence
+#define EPI_STAT_WBUSY 0x00000020 // Write Busy
+#define EPI_STAT_NBRBUSY 0x00000010 // Non-Blocking Read Busy
+#define EPI_STAT_ACTIVE 0x00000001 // Register Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RFIFOCNT register.
+//
+//*****************************************************************************
+#define EPI_RFIFOCNT_COUNT_M 0x0000000F // FIFO Count
+#define EPI_RFIFOCNT_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO0
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO0_DATA_M 0xFFFFFFFF // Reads Data
+#define EPI_READFIFO0_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO1
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO1_DATA_M 0xFFFFFFFF // Reads Data
+#define EPI_READFIFO1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO2
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO2_DATA_M 0xFFFFFFFF // Reads Data
+#define EPI_READFIFO2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO3
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO3_DATA_M 0xFFFFFFFF // Reads Data
+#define EPI_READFIFO3_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO4
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO4_DATA_M 0xFFFFFFFF // Reads Data
+#define EPI_READFIFO4_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO5
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO5_DATA_M 0xFFFFFFFF // Reads Data
+#define EPI_READFIFO5_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO6
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO6_DATA_M 0xFFFFFFFF // Reads Data
+#define EPI_READFIFO6_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_READFIFO7
+// register.
+//
+//*****************************************************************************
+#define EPI_READFIFO7_DATA_M 0xFFFFFFFF // Reads Data
+#define EPI_READFIFO7_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_FIFOLVL register.
+//
+//*****************************************************************************
+#define EPI_FIFOLVL_WFERR 0x00020000 // Write Full Error
+#define EPI_FIFOLVL_RSERR 0x00010000 // Read Stall Error
+#define EPI_FIFOLVL_WRFIFO_M 0x00000070 // Write FIFO
+#define EPI_FIFOLVL_WRFIFO_EMPT 0x00000000 // Interrupt is triggered while
+ // WRFIFO is empty.
+#define EPI_FIFOLVL_WRFIFO_2 0x00000020 // Interrupt is triggered until
+ // there are only two slots
+ // available. Thus, trigger is
+ // deasserted when there are two
+ // WRFIFO entries present. This
+ // configuration is optimized for
+ // bursts of 2
+#define EPI_FIFOLVL_WRFIFO_1 0x00000030 // Interrupt is triggered until
+ // there is one WRFIFO entry
+ // available. This configuration
+ // expects only single writes
+#define EPI_FIFOLVL_WRFIFO_NFULL \
+ 0x00000040 // Trigger interrupt when WRFIFO is
+ // not full, meaning trigger will
+ // continue to assert until there
+ // are four entries in the WRFIFO
+#define EPI_FIFOLVL_RDFIFO_M 0x00000007 // Read FIFO
+#define EPI_FIFOLVL_RDFIFO_EMPT 0x00000000 // Empty
+#define EPI_FIFOLVL_RDFIFO_1 0x00000001 // Trigger when there are 1 or more
+ // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_2 0x00000002 // Trigger when there are 2 or more
+ // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_4 0x00000003 // Trigger when there are 4 or more
+ // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_6 0x00000004 // Trigger when there are 6 or more
+ // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_7 0x00000005 // Trigger when there are 7 or more
+ // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_8 0x00000006 // Trigger when there are 8 entries
+ // in the NBRFIFO
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_WFIFOCNT register.
+//
+//*****************************************************************************
+#define EPI_WFIFOCNT_WTAV_M 0x00000007 // Available Write Transactions
+#define EPI_WFIFOCNT_WTAV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_DMATXCNT register.
+//
+//*****************************************************************************
+#define EPI_DMATXCNT_TXCNT_M 0x0000FFFF // DMA Count
+#define EPI_DMATXCNT_TXCNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_IM register.
+//
+//*****************************************************************************
+#define EPI_IM_DMAWRIM 0x00000010 // Write uDMA Interrupt Mask
+#define EPI_IM_DMARDIM 0x00000008 // Read uDMA Interrupt Mask
+#define EPI_IM_WRIM 0x00000004 // Write FIFO Empty Interrupt Mask
+#define EPI_IM_RDIM 0x00000002 // Read FIFO Full Interrupt Mask
+#define EPI_IM_ERRIM 0x00000001 // Error Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_RIS register.
+//
+//*****************************************************************************
+#define EPI_RIS_DMAWRRIS 0x00000010 // Write uDMA Raw Interrupt Status
+#define EPI_RIS_DMARDRIS 0x00000008 // Read uDMA Raw Interrupt Status
+#define EPI_RIS_WRRIS 0x00000004 // Write Raw Interrupt Status
+#define EPI_RIS_RDRIS 0x00000002 // Read Raw Interrupt Status
+#define EPI_RIS_ERRRIS 0x00000001 // Error Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_MIS register.
+//
+//*****************************************************************************
+#define EPI_MIS_DMAWRMIS 0x00000010 // Write uDMA Masked Interrupt
+ // Status
+#define EPI_MIS_DMARDMIS 0x00000008 // Read uDMA Masked Interrupt
+ // Status
+#define EPI_MIS_WRMIS 0x00000004 // Write Masked Interrupt Status
+#define EPI_MIS_RDMIS 0x00000002 // Read Masked Interrupt Status
+#define EPI_MIS_ERRMIS 0x00000001 // Error Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_EISC register.
+//
+//*****************************************************************************
+#define EPI_EISC_DMAWRIC 0x00000010 // Write uDMA Interrupt Clear
+#define EPI_EISC_DMARDIC 0x00000008 // Read uDMA Interrupt Clear
+#define EPI_EISC_WTFULL 0x00000004 // Write FIFO Full Error
+#define EPI_EISC_RSTALL 0x00000002 // Read Stalled Error
+#define EPI_EISC_TOUT 0x00000001 // Timeout Error
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8CFG3 register.
+//
+//*****************************************************************************
+#define EPI_HB8CFG3_WRHIGH 0x00200000 // CS2n WRITE Strobe Polarity
+#define EPI_HB8CFG3_RDHIGH 0x00100000 // CS2n READ Strobe Polarity
+#define EPI_HB8CFG3_ALEHIGH 0x00080000 // CS2n ALE Strobe Polarity
+#define EPI_HB8CFG3_WRWS_M 0x000000C0 // CS2n Write Wait States
+#define EPI_HB8CFG3_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks
+#define EPI_HB8CFG3_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks
+#define EPI_HB8CFG3_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks
+#define EPI_HB8CFG3_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks
+#define EPI_HB8CFG3_RDWS_M 0x00000030 // CS2n Read Wait States
+#define EPI_HB8CFG3_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks
+#define EPI_HB8CFG3_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks
+#define EPI_HB8CFG3_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks
+#define EPI_HB8CFG3_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks
+#define EPI_HB8CFG3_MODE_M 0x00000003 // CS2n Host Bus Sub-Mode
+#define EPI_HB8CFG3_MODE_ADMUX 0x00000000 // ADMUX - AD[7:0]
+#define EPI_HB8CFG3_MODE_AD 0x00000001 // ADNONMUX - D[7:0]
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16CFG3 register.
+//
+//*****************************************************************************
+#define EPI_HB16CFG3_WRHIGH 0x00200000 // CS2n WRITE Strobe Polarity
+#define EPI_HB16CFG3_RDHIGH 0x00100000 // CS2n READ Strobe Polarity
+#define EPI_HB16CFG3_ALEHIGH 0x00080000 // CS2n ALE Strobe Polarity
+#define EPI_HB16CFG3_WRCRE 0x00040000 // CS2n PSRAM Configuration
+ // Register Write
+#define EPI_HB16CFG3_RDCRE 0x00020000 // CS2n PSRAM Configuration
+ // Register Read
+#define EPI_HB16CFG3_BURST 0x00010000 // CS2n Burst Mode
+#define EPI_HB16CFG3_WRWS_M 0x000000C0 // CS2n Write Wait States
+#define EPI_HB16CFG3_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks
+#define EPI_HB16CFG3_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks
+#define EPI_HB16CFG3_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks
+#define EPI_HB16CFG3_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks
+#define EPI_HB16CFG3_RDWS_M 0x00000030 // CS2n Read Wait States
+#define EPI_HB16CFG3_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks
+#define EPI_HB16CFG3_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks
+#define EPI_HB16CFG3_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks
+#define EPI_HB16CFG3_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks
+#define EPI_HB16CFG3_MODE_M 0x00000003 // CS2n Host Bus Sub-Mode
+#define EPI_HB16CFG3_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0]
+#define EPI_HB16CFG3_MODE_AD 0x00000001 // ADNONMUX - D[15:0]
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16CFG4 register.
+//
+//*****************************************************************************
+#define EPI_HB16CFG4_WRHIGH 0x00200000 // CS3n WRITE Strobe Polarity
+#define EPI_HB16CFG4_RDHIGH 0x00100000 // CS3n READ Strobe Polarity
+#define EPI_HB16CFG4_ALEHIGH 0x00080000 // CS3n ALE Strobe Polarity
+#define EPI_HB16CFG4_WRCRE 0x00040000 // CS3n PSRAM Configuration
+ // Register Write
+#define EPI_HB16CFG4_RDCRE 0x00020000 // CS3n PSRAM Configuration
+ // Register Read
+#define EPI_HB16CFG4_BURST 0x00010000 // CS3n Burst Mode
+#define EPI_HB16CFG4_WRWS_M 0x000000C0 // CS3n Write Wait States
+#define EPI_HB16CFG4_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks
+#define EPI_HB16CFG4_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks
+#define EPI_HB16CFG4_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks
+#define EPI_HB16CFG4_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks
+#define EPI_HB16CFG4_RDWS_M 0x00000030 // CS3n Read Wait States
+#define EPI_HB16CFG4_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks
+#define EPI_HB16CFG4_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks
+#define EPI_HB16CFG4_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks
+#define EPI_HB16CFG4_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks
+#define EPI_HB16CFG4_MODE_M 0x00000003 // CS3n Host Bus Sub-Mode
+#define EPI_HB16CFG4_MODE_ADMUX 0x00000000 // ADMUX - AD[15:0]
+#define EPI_HB16CFG4_MODE_AD 0x00000001 // ADNONMUX - D[15:0]
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8CFG4 register.
+//
+//*****************************************************************************
+#define EPI_HB8CFG4_WRHIGH 0x00200000 // CS3n WRITE Strobe Polarity
+#define EPI_HB8CFG4_RDHIGH 0x00100000 // CS2n READ Strobe Polarity
+#define EPI_HB8CFG4_ALEHIGH 0x00080000 // CS3n ALE Strobe Polarity
+#define EPI_HB8CFG4_WRWS_M 0x000000C0 // CS3n Write Wait States
+#define EPI_HB8CFG4_WRWS_2 0x00000000 // Active WRn is 2 EPI clocks
+#define EPI_HB8CFG4_WRWS_4 0x00000040 // Active WRn is 4 EPI clocks
+#define EPI_HB8CFG4_WRWS_6 0x00000080 // Active WRn is 6 EPI clocks
+#define EPI_HB8CFG4_WRWS_8 0x000000C0 // Active WRn is 8 EPI clocks
+#define EPI_HB8CFG4_RDWS_M 0x00000030 // CS3n Read Wait States
+#define EPI_HB8CFG4_RDWS_2 0x00000000 // Active RDn is 2 EPI clocks
+#define EPI_HB8CFG4_RDWS_4 0x00000010 // Active RDn is 4 EPI clocks
+#define EPI_HB8CFG4_RDWS_6 0x00000020 // Active RDn is 6 EPI clocks
+#define EPI_HB8CFG4_RDWS_8 0x00000030 // Active RDn is 8 EPI clocks
+#define EPI_HB8CFG4_MODE_M 0x00000003 // CS3n Host Bus Sub-Mode
+#define EPI_HB8CFG4_MODE_ADMUX 0x00000000 // ADMUX - AD[7:0]
+#define EPI_HB8CFG4_MODE_AD 0x00000001 // ADNONMUX - D[7:0]
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8TIME register.
+//
+//*****************************************************************************
+#define EPI_HB8TIME_IRDYDLY_M 0x03000000 // CS0n Input Ready Delay
+#define EPI_HB8TIME_CAPWIDTH_M 0x00003000 // CS0n Inter-transfer Capture
+ // Width
+#define EPI_HB8TIME_WRWSM 0x00000010 // Write Wait State Minus One
+#define EPI_HB8TIME_RDWSM 0x00000001 // Read Wait State Minus One
+#define EPI_HB8TIME_IRDYDLY_S 24
+#define EPI_HB8TIME_CAPWIDTH_S 12
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16TIME register.
+//
+//*****************************************************************************
+#define EPI_HB16TIME_IRDYDLY_M 0x03000000 // CS0n Input Ready Delay
+#define EPI_HB16TIME_PSRAMSZ_M 0x00070000 // PSRAM Row Size
+#define EPI_HB16TIME_PSRAMSZ_0 0x00000000 // No row size limitation
+#define EPI_HB16TIME_PSRAMSZ_128B \
+ 0x00010000 // 128 B
+#define EPI_HB16TIME_PSRAMSZ_256B \
+ 0x00020000 // 256 B
+#define EPI_HB16TIME_PSRAMSZ_512B \
+ 0x00030000 // 512 B
+#define EPI_HB16TIME_PSRAMSZ_1KB \
+ 0x00040000 // 1024 B
+#define EPI_HB16TIME_PSRAMSZ_2KB \
+ 0x00050000 // 2048 B
+#define EPI_HB16TIME_PSRAMSZ_4KB \
+ 0x00060000 // 4096 B
+#define EPI_HB16TIME_PSRAMSZ_8KB \
+ 0x00070000 // 8192 B
+#define EPI_HB16TIME_CAPWIDTH_M 0x00003000 // CS0n Inter-transfer Capture
+ // Width
+#define EPI_HB16TIME_WRWSM 0x00000010 // Write Wait State Minus One
+#define EPI_HB16TIME_RDWSM 0x00000001 // Read Wait State Minus One
+#define EPI_HB16TIME_IRDYDLY_S 24
+#define EPI_HB16TIME_CAPWIDTH_S 12
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8TIME2 register.
+//
+//*****************************************************************************
+#define EPI_HB8TIME2_IRDYDLY_M 0x03000000 // CS1n Input Ready Delay
+#define EPI_HB8TIME2_CAPWIDTH_M 0x00003000 // CS1n Inter-transfer Capture
+ // Width
+#define EPI_HB8TIME2_WRWSM 0x00000010 // CS1n Write Wait State Minus One
+#define EPI_HB8TIME2_RDWSM 0x00000001 // CS1n Read Wait State Minus One
+#define EPI_HB8TIME2_IRDYDLY_S 24
+#define EPI_HB8TIME2_CAPWIDTH_S 12
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16TIME2
+// register.
+//
+//*****************************************************************************
+#define EPI_HB16TIME2_IRDYDLY_M 0x03000000 // CS1n Input Ready Delay
+#define EPI_HB16TIME2_PSRAMSZ_M 0x00070000 // PSRAM Row Size
+#define EPI_HB16TIME2_PSRAMSZ_0 0x00000000 // No row size limitation
+#define EPI_HB16TIME2_PSRAMSZ_128B \
+ 0x00010000 // 128 B
+#define EPI_HB16TIME2_PSRAMSZ_256B \
+ 0x00020000 // 256 B
+#define EPI_HB16TIME2_PSRAMSZ_512B \
+ 0x00030000 // 512 B
+#define EPI_HB16TIME2_PSRAMSZ_1KB \
+ 0x00040000 // 1024 B
+#define EPI_HB16TIME2_PSRAMSZ_2KB \
+ 0x00050000 // 2048 B
+#define EPI_HB16TIME2_PSRAMSZ_4KB \
+ 0x00060000 // 4096 B
+#define EPI_HB16TIME2_PSRAMSZ_8KB \
+ 0x00070000 // 8192 B
+#define EPI_HB16TIME2_CAPWIDTH_M \
+ 0x00003000 // CS1n Inter-transfer Capture
+ // Width
+#define EPI_HB16TIME2_WRWSM 0x00000010 // CS1n Write Wait State Minus One
+#define EPI_HB16TIME2_RDWSM 0x00000001 // CS1n Read Wait State Minus One
+#define EPI_HB16TIME2_IRDYDLY_S 24
+#define EPI_HB16TIME2_CAPWIDTH_S \
+ 12
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16TIME3
+// register.
+//
+//*****************************************************************************
+#define EPI_HB16TIME3_IRDYDLY_M 0x03000000 // CS2n Input Ready Delay
+#define EPI_HB16TIME3_PSRAMSZ_M 0x00070000 // PSRAM Row Size
+#define EPI_HB16TIME3_PSRAMSZ_0 0x00000000 // No row size limitation
+#define EPI_HB16TIME3_PSRAMSZ_128B \
+ 0x00010000 // 128 B
+#define EPI_HB16TIME3_PSRAMSZ_256B \
+ 0x00020000 // 256 B
+#define EPI_HB16TIME3_PSRAMSZ_512B \
+ 0x00030000 // 512 B
+#define EPI_HB16TIME3_PSRAMSZ_1KB \
+ 0x00040000 // 1024 B
+#define EPI_HB16TIME3_PSRAMSZ_2KB \
+ 0x00050000 // 2048 B
+#define EPI_HB16TIME3_PSRAMSZ_4KB \
+ 0x00060000 // 4096 B
+#define EPI_HB16TIME3_PSRAMSZ_8KB \
+ 0x00070000 // 8192 B
+#define EPI_HB16TIME3_CAPWIDTH_M \
+ 0x00003000 // CS2n Inter-transfer Capture
+ // Width
+#define EPI_HB16TIME3_WRWSM 0x00000010 // CS2n Write Wait State Minus One
+#define EPI_HB16TIME3_RDWSM 0x00000001 // CS2n Read Wait State Minus One
+#define EPI_HB16TIME3_IRDYDLY_S 24
+#define EPI_HB16TIME3_CAPWIDTH_S \
+ 12
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8TIME3 register.
+//
+//*****************************************************************************
+#define EPI_HB8TIME3_IRDYDLY_M 0x03000000 // CS2n Input Ready Delay
+#define EPI_HB8TIME3_CAPWIDTH_M 0x00003000 // CS2n Inter-transfer Capture
+ // Width
+#define EPI_HB8TIME3_WRWSM 0x00000010 // CS2n Write Wait State Minus One
+#define EPI_HB8TIME3_RDWSM 0x00000001 // CS2n Read Wait State Minus One
+#define EPI_HB8TIME3_IRDYDLY_S 24
+#define EPI_HB8TIME3_CAPWIDTH_S 12
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB8TIME4 register.
+//
+//*****************************************************************************
+#define EPI_HB8TIME4_IRDYDLY_M 0x03000000 // CS3n Input Ready Delay
+#define EPI_HB8TIME4_CAPWIDTH_M 0x00003000 // CS3n Inter-transfer Capture
+ // Width
+#define EPI_HB8TIME4_WRWSM 0x00000010 // CS3n Write Wait State Minus One
+#define EPI_HB8TIME4_RDWSM 0x00000001 // CS3n Read Wait State Minus One
+#define EPI_HB8TIME4_IRDYDLY_S 24
+#define EPI_HB8TIME4_CAPWIDTH_S 12
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HB16TIME4
+// register.
+//
+//*****************************************************************************
+#define EPI_HB16TIME4_IRDYDLY_M 0x03000000 // CS3n Input Ready Delay
+#define EPI_HB16TIME4_PSRAMSZ_M 0x00070000 // PSRAM Row Size
+#define EPI_HB16TIME4_PSRAMSZ_0 0x00000000 // No row size limitation
+#define EPI_HB16TIME4_PSRAMSZ_128B \
+ 0x00010000 // 128 B
+#define EPI_HB16TIME4_PSRAMSZ_256B \
+ 0x00020000 // 256 B
+#define EPI_HB16TIME4_PSRAMSZ_512B \
+ 0x00030000 // 512 B
+#define EPI_HB16TIME4_PSRAMSZ_1KB \
+ 0x00040000 // 1024 B
+#define EPI_HB16TIME4_PSRAMSZ_2KB \
+ 0x00050000 // 2048 B
+#define EPI_HB16TIME4_PSRAMSZ_4KB \
+ 0x00060000 // 4096 B
+#define EPI_HB16TIME4_PSRAMSZ_8KB \
+ 0x00070000 // 8192 B
+#define EPI_HB16TIME4_CAPWIDTH_M \
+ 0x00003000 // CS3n Inter-transfer Capture
+ // Width
+#define EPI_HB16TIME4_WRWSM 0x00000010 // CS3n Write Wait State Minus One
+#define EPI_HB16TIME4_RDWSM 0x00000001 // CS3n Read Wait State Minus One
+#define EPI_HB16TIME4_IRDYDLY_S 24
+#define EPI_HB16TIME4_CAPWIDTH_S \
+ 12
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the EPI_O_HBPSRAM register.
+//
+//*****************************************************************************
+#define EPI_HBPSRAM_CR_M 0x001FFFFF // PSRAM Config Register
+#define EPI_HBPSRAM_CR_S 0
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the EPI_O_FIFOLVL
+// register.
+//
+//*****************************************************************************
+#define EPI_FIFOLVL_WRFIFO_1_4 0x00000020 // Trigger when there are up to 3
+ // spaces available in the WFIFO
+#define EPI_FIFOLVL_WRFIFO_1_2 0x00000030 // Trigger when there are up to 2
+ // spaces available in the WFIFO
+#define EPI_FIFOLVL_WRFIFO_3_4 0x00000040 // Trigger when there is 1 space
+ // available in the WFIFO
+#define EPI_FIFOLVL_RDFIFO_1_8 0x00000001 // Trigger when there are 1 or more
+ // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_1_4 0x00000002 // Trigger when there are 2 or more
+ // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_1_2 0x00000003 // Trigger when there are 4 or more
+ // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_3_4 0x00000004 // Trigger when there are 6 or more
+ // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_7_8 0x00000005 // Trigger when there are 7 or more
+ // entries in the NBRFIFO
+#define EPI_FIFOLVL_RDFIFO_FULL 0x00000006 // Trigger when there are 8 entries
+ // in the NBRFIFO
+
+#endif
+
+#endif // __HW_EPI_H__
diff --git a/os/common/ext/TivaWare/inc/hw_fan.h b/os/common/ext/TivaWare/inc/hw_fan.h
new file mode 100644
index 0000000..089a8ea
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_fan.h
@@ -0,0 +1,49 @@
+//*****************************************************************************
+//
+// hw_fan.h - Macros used when accessing the fan control hardware.
+//
+// Copyright (c) 2010-2016 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_FAN_H__
+#define __HW_FAN_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Fan Control register offsets.
+//
+//*****************************************************************************
+
+#endif // __HW_FAN_H__
diff --git a/os/common/ext/TivaWare/inc/hw_flash.h b/os/common/ext/TivaWare/inc/hw_flash.h
new file mode 100644
index 0000000..0133b35
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_flash.h
@@ -0,0 +1,625 @@
+//*****************************************************************************
+//
+// hw_flash.h - Macros used when accessing the flash controller.
+//
+// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_FLASH_H__
+#define __HW_FLASH_H__
+
+//*****************************************************************************
+//
+// The following are defines for the FLASH register offsets.
+//
+//*****************************************************************************
+#define FLASH_FMA 0x400FD000 // Flash Memory Address
+#define FLASH_FMD 0x400FD004 // Flash Memory Data
+#define FLASH_FMC 0x400FD008 // Flash Memory Control
+#define FLASH_FCRIS 0x400FD00C // Flash Controller Raw Interrupt
+ // Status
+#define FLASH_FCIM 0x400FD010 // Flash Controller Interrupt Mask
+#define FLASH_FCMISC 0x400FD014 // Flash Controller Masked
+ // Interrupt Status and Clear
+#define FLASH_FMC2 0x400FD020 // Flash Memory Control 2
+#define FLASH_FWBVAL 0x400FD030 // Flash Write Buffer Valid
+#define FLASH_FLPEKEY 0x400FD03C // Flash Program/Erase Key
+#define FLASH_FWBN 0x400FD100 // Flash Write Buffer n
+#define FLASH_PP 0x400FDFC0 // Flash Peripheral Properties
+#define FLASH_FSIZE 0x400FDFC0 // Flash Size
+#define FLASH_SSIZE 0x400FDFC4 // SRAM Size
+#define FLASH_CONF 0x400FDFC8 // Flash Configuration Register
+#define FLASH_ROMSWMAP 0x400FDFCC // ROM Software Map
+#define FLASH_DMASZ 0x400FDFD0 // Flash DMA Address Size
+#define FLASH_DMAST 0x400FDFD4 // Flash DMA Starting Address
+#define FLASH_RVP 0x400FE0D4 // Reset Vector Pointer
+#define FLASH_RMCTL 0x400FE0F0 // ROM Control
+#define FLASH_BOOTCFG 0x400FE1D0 // Boot Configuration
+#define FLASH_USERREG0 0x400FE1E0 // User Register 0
+#define FLASH_USERREG1 0x400FE1E4 // User Register 1
+#define FLASH_USERREG2 0x400FE1E8 // User Register 2
+#define FLASH_USERREG3 0x400FE1EC // User Register 3
+#define FLASH_FMPRE0 0x400FE200 // Flash Memory Protection Read
+ // Enable 0
+#define FLASH_FMPRE1 0x400FE204 // Flash Memory Protection Read
+ // Enable 1
+#define FLASH_FMPRE2 0x400FE208 // Flash Memory Protection Read
+ // Enable 2
+#define FLASH_FMPRE3 0x400FE20C // Flash Memory Protection Read
+ // Enable 3
+#define FLASH_FMPRE4 0x400FE210 // Flash Memory Protection Read
+ // Enable 4
+#define FLASH_FMPRE5 0x400FE214 // Flash Memory Protection Read
+ // Enable 5
+#define FLASH_FMPRE6 0x400FE218 // Flash Memory Protection Read
+ // Enable 6
+#define FLASH_FMPRE7 0x400FE21C // Flash Memory Protection Read
+ // Enable 7
+#define FLASH_FMPRE8 0x400FE220 // Flash Memory Protection Read
+ // Enable 8
+#define FLASH_FMPRE9 0x400FE224 // Flash Memory Protection Read
+ // Enable 9
+#define FLASH_FMPRE10 0x400FE228 // Flash Memory Protection Read
+ // Enable 10
+#define FLASH_FMPRE11 0x400FE22C // Flash Memory Protection Read
+ // Enable 11
+#define FLASH_FMPRE12 0x400FE230 // Flash Memory Protection Read
+ // Enable 12
+#define FLASH_FMPRE13 0x400FE234 // Flash Memory Protection Read
+ // Enable 13
+#define FLASH_FMPRE14 0x400FE238 // Flash Memory Protection Read
+ // Enable 14
+#define FLASH_FMPRE15 0x400FE23C // Flash Memory Protection Read
+ // Enable 15
+#define FLASH_FMPPE0 0x400FE400 // Flash Memory Protection Program
+ // Enable 0
+#define FLASH_FMPPE1 0x400FE404 // Flash Memory Protection Program
+ // Enable 1
+#define FLASH_FMPPE2 0x400FE408 // Flash Memory Protection Program
+ // Enable 2
+#define FLASH_FMPPE3 0x400FE40C // Flash Memory Protection Program
+ // Enable 3
+#define FLASH_FMPPE4 0x400FE410 // Flash Memory Protection Program
+ // Enable 4
+#define FLASH_FMPPE5 0x400FE414 // Flash Memory Protection Program
+ // Enable 5
+#define FLASH_FMPPE6 0x400FE418 // Flash Memory Protection Program
+ // Enable 6
+#define FLASH_FMPPE7 0x400FE41C // Flash Memory Protection Program
+ // Enable 7
+#define FLASH_FMPPE8 0x400FE420 // Flash Memory Protection Program
+ // Enable 8
+#define FLASH_FMPPE9 0x400FE424 // Flash Memory Protection Program
+ // Enable 9
+#define FLASH_FMPPE10 0x400FE428 // Flash Memory Protection Program
+ // Enable 10
+#define FLASH_FMPPE11 0x400FE42C // Flash Memory Protection Program
+ // Enable 11
+#define FLASH_FMPPE12 0x400FE430 // Flash Memory Protection Program
+ // Enable 12
+#define FLASH_FMPPE13 0x400FE434 // Flash Memory Protection Program
+ // Enable 13
+#define FLASH_FMPPE14 0x400FE438 // Flash Memory Protection Program
+ // Enable 14
+#define FLASH_FMPPE15 0x400FE43C // Flash Memory Protection Program
+ // Enable 15
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMA register.
+//
+//*****************************************************************************
+#define FLASH_FMA_OFFSET_M 0x000FFFFF // Address Offset
+#define FLASH_FMA_OFFSET_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMD register.
+//
+//*****************************************************************************
+#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value
+#define FLASH_FMD_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMC register.
+//
+//*****************************************************************************
+#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key
+#define FLASH_FMC_COMT 0x00000008 // Commit Register Value
+#define FLASH_FMC_MERASE 0x00000004 // Mass Erase Flash Memory
+#define FLASH_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory
+#define FLASH_FMC_WRITE 0x00000001 // Write a Word into Flash Memory
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCRIS register.
+//
+//*****************************************************************************
+#define FLASH_FCRIS_PROGRIS 0x00002000 // Program Verify Error Raw
+ // Interrupt Status
+#define FLASH_FCRIS_ERRIS 0x00000800 // Erase Verify Error Raw Interrupt
+ // Status
+#define FLASH_FCRIS_INVDRIS 0x00000400 // Invalid Data Raw Interrupt
+ // Status
+#define FLASH_FCRIS_VOLTRIS 0x00000200 // Pump Voltage Raw Interrupt
+ // Status
+#define FLASH_FCRIS_ERIS 0x00000004 // EEPROM Raw Interrupt Status
+#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status
+#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCIM register.
+//
+//*****************************************************************************
+#define FLASH_FCIM_PROGMASK 0x00002000 // PROGVER Interrupt Mask
+#define FLASH_FCIM_ERMASK 0x00000800 // ERVER Interrupt Mask
+#define FLASH_FCIM_INVDMASK 0x00000400 // Invalid Data Interrupt Mask
+#define FLASH_FCIM_VOLTMASK 0x00000200 // VOLT Interrupt Mask
+#define FLASH_FCIM_EMASK 0x00000004 // EEPROM Interrupt Mask
+#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask
+#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FCMISC register.
+//
+//*****************************************************************************
+#define FLASH_FCMISC_PROGMISC 0x00002000 // PROGVER Masked Interrupt Status
+ // and Clear
+#define FLASH_FCMISC_ERMISC 0x00000800 // ERVER Masked Interrupt Status
+ // and Clear
+#define FLASH_FCMISC_INVDMISC 0x00000400 // Invalid Data Masked Interrupt
+ // Status and Clear
+#define FLASH_FCMISC_VOLTMISC 0x00000200 // VOLT Masked Interrupt Status and
+ // Clear
+#define FLASH_FCMISC_EMISC 0x00000004 // EEPROM Masked Interrupt Status
+ // and Clear
+#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt
+ // Status and Clear
+#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status
+ // and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMC2 register.
+//
+//*****************************************************************************
+#define FLASH_FMC2_WRKEY 0xA4420000 // FLASH write key
+#define FLASH_FMC2_WRBUF 0x00000001 // Buffered Flash Memory Write
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FWBVAL register.
+//
+//*****************************************************************************
+#define FLASH_FWBVAL_FWB_M 0xFFFFFFFF // Flash Memory Write Buffer
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FLPEKEY register.
+//
+//*****************************************************************************
+#define FLASH_FLPEKEY_PEKEY_M 0x0000FFFF // Key Value
+#define FLASH_FLPEKEY_PEKEY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FWBN register.
+//
+//*****************************************************************************
+#define FLASH_FWBN_DATA_M 0xFFFFFFFF // Data
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_PP register.
+//
+//*****************************************************************************
+#define FLASH_PP_PFC 0x40000000 // Prefetch Buffer Mode
+#define FLASH_PP_FMM 0x20000000 // Flash Mirror Mode
+#define FLASH_PP_DFA 0x10000000 // DMA Flash Access
+#define FLASH_PP_EESS_M 0x00780000 // EEPROM Sector Size of the
+ // physical bank
+#define FLASH_PP_EESS_1KB 0x00000000 // 1 KB
+#define FLASH_PP_EESS_2KB 0x00080000 // 2 KB
+#define FLASH_PP_EESS_4KB 0x00100000 // 4 KB
+#define FLASH_PP_EESS_8KB 0x00180000 // 8 KB
+#define FLASH_PP_MAINSS_M 0x00070000 // Flash Sector Size of the
+ // physical bank
+#define FLASH_PP_MAINSS_1KB 0x00000000 // 1 KB
+#define FLASH_PP_MAINSS_2KB 0x00010000 // 2 KB
+#define FLASH_PP_MAINSS_4KB 0x00020000 // 4 KB
+#define FLASH_PP_MAINSS_8KB 0x00030000 // 8 KB
+#define FLASH_PP_MAINSS_16KB 0x00040000 // 16 KB
+#define FLASH_PP_SIZE_M 0x0000FFFF // Flash Size
+#define FLASH_PP_SIZE_512KB 0x000000FF // 512 KB of Flash
+#define FLASH_PP_SIZE_1MB 0x000001FF // 1024 KB of Flash
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FSIZE register.
+//
+//*****************************************************************************
+#define FLASH_FSIZE_SIZE_M 0x0000FFFF // Flash Size
+#define FLASH_FSIZE_SIZE_32KB 0x0000000F // 32 KB of Flash
+#define FLASH_FSIZE_SIZE_64KB 0x0000001F // 64 KB of Flash
+#define FLASH_FSIZE_SIZE_128KB 0x0000003F // 128 KB of Flash
+#define FLASH_FSIZE_SIZE_256KB 0x0000007F // 256 KB of Flash
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_SSIZE register.
+//
+//*****************************************************************************
+#define FLASH_SSIZE_SIZE_M 0x0000FFFF // SRAM Size
+#define FLASH_SSIZE_SIZE_12KB 0x0000002F // 12 KB of SRAM
+#define FLASH_SSIZE_SIZE_24KB 0x0000005F // 24 KB of SRAM
+#define FLASH_SSIZE_SIZE_32KB 0x0000007F // 32 KB of SRAM
+#define FLASH_SSIZE_SIZE_256KB 0x000003FF // 256 KB of SRAM
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_CONF register.
+//
+//*****************************************************************************
+#define FLASH_CONF_FMME 0x40000000 // Flash Mirror Mode Enable
+#define FLASH_CONF_SPFE 0x20000000 // Single Prefetch Mode Enable
+#define FLASH_CONF_CLRTV 0x00100000 // Clear Valid Tags
+#define FLASH_CONF_FPFON 0x00020000 // Force Prefetch On
+#define FLASH_CONF_FPFOFF 0x00010000 // Force Prefetch Off
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_ROMSWMAP register.
+//
+//*****************************************************************************
+#define FLASH_ROMSWMAP_SAFERTOS 0x00000001 // SafeRTOS Present
+#define FLASH_ROMSWMAP_SW0EN_M 0x00000003 // ROM SW Region 0 Availability
+#define FLASH_ROMSWMAP_SW0EN_NOTVIS \
+ 0x00000000 // Software region not available to
+ // the core
+#define FLASH_ROMSWMAP_SW0EN_CORE \
+ 0x00000001 // Region available to core
+#define FLASH_ROMSWMAP_SW1EN_M 0x0000000C // ROM SW Region 1 Availability
+#define FLASH_ROMSWMAP_SW1EN_NOTVIS \
+ 0x00000000 // Software region not available to
+ // the core
+#define FLASH_ROMSWMAP_SW1EN_CORE \
+ 0x00000004 // Region available to core
+#define FLASH_ROMSWMAP_SW2EN_M 0x00000030 // ROM SW Region 2 Availability
+#define FLASH_ROMSWMAP_SW2EN_NOTVIS \
+ 0x00000000 // Software region not available to
+ // the core
+#define FLASH_ROMSWMAP_SW2EN_CORE \
+ 0x00000010 // Region available to core
+#define FLASH_ROMSWMAP_SW3EN_M 0x000000C0 // ROM SW Region 3 Availability
+#define FLASH_ROMSWMAP_SW3EN_NOTVIS \
+ 0x00000000 // Software region not available to
+ // the core
+#define FLASH_ROMSWMAP_SW3EN_CORE \
+ 0x00000040 // Region available to core
+#define FLASH_ROMSWMAP_SW4EN_M 0x00000300 // ROM SW Region 4 Availability
+#define FLASH_ROMSWMAP_SW4EN_NOTVIS \
+ 0x00000000 // Software region not available to
+ // the core
+#define FLASH_ROMSWMAP_SW4EN_CORE \
+ 0x00000100 // Region available to core
+#define FLASH_ROMSWMAP_SW5EN_M 0x00000C00 // ROM SW Region 5 Availability
+#define FLASH_ROMSWMAP_SW5EN_NOTVIS \
+ 0x00000000 // Software region not available to
+ // the core
+#define FLASH_ROMSWMAP_SW5EN_CORE \
+ 0x00000400 // Region available to core
+#define FLASH_ROMSWMAP_SW6EN_M 0x00003000 // ROM SW Region 6 Availability
+#define FLASH_ROMSWMAP_SW6EN_NOTVIS \
+ 0x00000000 // Software region not available to
+ // the core
+#define FLASH_ROMSWMAP_SW6EN_CORE \
+ 0x00001000 // Region available to core
+#define FLASH_ROMSWMAP_SW7EN_M 0x0000C000 // ROM SW Region 7 Availability
+#define FLASH_ROMSWMAP_SW7EN_NOTVIS \
+ 0x00000000 // Software region not available to
+ // the core
+#define FLASH_ROMSWMAP_SW7EN_CORE \
+ 0x00004000 // Region available to core
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_DMASZ register.
+//
+//*****************************************************************************
+#define FLASH_DMASZ_SIZE_M 0x0003FFFF // uDMA-accessible Memory Size
+#define FLASH_DMASZ_SIZE_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_DMAST register.
+//
+//*****************************************************************************
+#define FLASH_DMAST_ADDR_M 0x1FFFF800 // Contains the starting address of
+ // the flash region accessible by
+ // uDMA if the FLASHPP register DFA
+ // bit is set
+#define FLASH_DMAST_ADDR_S 11
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_RVP register.
+//
+//*****************************************************************************
+#define FLASH_RVP_RV_M 0xFFFFFFFF // Reset Vector Pointer Address
+#define FLASH_RVP_RV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_RMCTL register.
+//
+//*****************************************************************************
+#define FLASH_RMCTL_BA 0x00000001 // Boot Alias
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_BOOTCFG register.
+//
+//*****************************************************************************
+#define FLASH_BOOTCFG_NW 0x80000000 // Not Written
+#define FLASH_BOOTCFG_PORT_M 0x0000E000 // Boot GPIO Port
+#define FLASH_BOOTCFG_PORT_A 0x00000000 // Port A
+#define FLASH_BOOTCFG_PORT_B 0x00002000 // Port B
+#define FLASH_BOOTCFG_PORT_C 0x00004000 // Port C
+#define FLASH_BOOTCFG_PORT_D 0x00006000 // Port D
+#define FLASH_BOOTCFG_PORT_E 0x00008000 // Port E
+#define FLASH_BOOTCFG_PORT_F 0x0000A000 // Port F
+#define FLASH_BOOTCFG_PORT_G 0x0000C000 // Port G
+#define FLASH_BOOTCFG_PORT_H 0x0000E000 // Port H
+#define FLASH_BOOTCFG_PIN_M 0x00001C00 // Boot GPIO Pin
+#define FLASH_BOOTCFG_PIN_0 0x00000000 // Pin 0
+#define FLASH_BOOTCFG_PIN_1 0x00000400 // Pin 1
+#define FLASH_BOOTCFG_PIN_2 0x00000800 // Pin 2
+#define FLASH_BOOTCFG_PIN_3 0x00000C00 // Pin 3
+#define FLASH_BOOTCFG_PIN_4 0x00001000 // Pin 4
+#define FLASH_BOOTCFG_PIN_5 0x00001400 // Pin 5
+#define FLASH_BOOTCFG_PIN_6 0x00001800 // Pin 6
+#define FLASH_BOOTCFG_PIN_7 0x00001C00 // Pin 7
+#define FLASH_BOOTCFG_POL 0x00000200 // Boot GPIO Polarity
+#define FLASH_BOOTCFG_EN 0x00000100 // Boot GPIO Enable
+#define FLASH_BOOTCFG_KEY 0x00000010 // KEY Select
+#define FLASH_BOOTCFG_DBG1 0x00000002 // Debug Control 1
+#define FLASH_BOOTCFG_DBG0 0x00000001 // Debug Control 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG0 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG0_DATA_M 0xFFFFFFFF // User Data
+#define FLASH_USERREG0_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG1 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG1_DATA_M 0xFFFFFFFF // User Data
+#define FLASH_USERREG1_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG2 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG2_DATA_M 0xFFFFFFFF // User Data
+#define FLASH_USERREG2_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_USERREG3 register.
+//
+//*****************************************************************************
+#define FLASH_USERREG3_DATA_M 0xFFFFFFFF // User Data
+#define FLASH_USERREG3_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPRE8 register.
+//
+//*****************************************************************************
+#define FLASH_FMPRE8_READ_ENABLE_M \
+ 0xFFFFFFFF // Flash Read Enable
+#define FLASH_FMPRE8_READ_ENABLE_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPRE9 register.
+//
+//*****************************************************************************
+#define FLASH_FMPRE9_READ_ENABLE_M \
+ 0xFFFFFFFF // Flash Read Enable
+#define FLASH_FMPRE9_READ_ENABLE_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPRE10 register.
+//
+//*****************************************************************************
+#define FLASH_FMPRE10_READ_ENABLE_M \
+ 0xFFFFFFFF // Flash Read Enable
+#define FLASH_FMPRE10_READ_ENABLE_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPRE11 register.
+//
+//*****************************************************************************
+#define FLASH_FMPRE11_READ_ENABLE_M \
+ 0xFFFFFFFF // Flash Read Enable
+#define FLASH_FMPRE11_READ_ENABLE_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPRE12 register.
+//
+//*****************************************************************************
+#define FLASH_FMPRE12_READ_ENABLE_M \
+ 0xFFFFFFFF // Flash Read Enable
+#define FLASH_FMPRE12_READ_ENABLE_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPRE13 register.
+//
+//*****************************************************************************
+#define FLASH_FMPRE13_READ_ENABLE_M \
+ 0xFFFFFFFF // Flash Read Enable
+#define FLASH_FMPRE13_READ_ENABLE_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPRE14 register.
+//
+//*****************************************************************************
+#define FLASH_FMPRE14_READ_ENABLE_M \
+ 0xFFFFFFFF // Flash Read Enable
+#define FLASH_FMPRE14_READ_ENABLE_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPRE15 register.
+//
+//*****************************************************************************
+#define FLASH_FMPRE15_READ_ENABLE_M \
+ 0xFFFFFFFF // Flash Read Enable
+#define FLASH_FMPRE15_READ_ENABLE_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPPE8 register.
+//
+//*****************************************************************************
+#define FLASH_FMPPE8_PROG_ENABLE_M \
+ 0xFFFFFFFF // Flash Programming Enable
+#define FLASH_FMPPE8_PROG_ENABLE_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPPE9 register.
+//
+//*****************************************************************************
+#define FLASH_FMPPE9_PROG_ENABLE_M \
+ 0xFFFFFFFF // Flash Programming Enable
+#define FLASH_FMPPE9_PROG_ENABLE_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPPE10 register.
+//
+//*****************************************************************************
+#define FLASH_FMPPE10_PROG_ENABLE_M \
+ 0xFFFFFFFF // Flash Programming Enable
+#define FLASH_FMPPE10_PROG_ENABLE_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPPE11 register.
+//
+//*****************************************************************************
+#define FLASH_FMPPE11_PROG_ENABLE_M \
+ 0xFFFFFFFF // Flash Programming Enable
+#define FLASH_FMPPE11_PROG_ENABLE_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPPE12 register.
+//
+//*****************************************************************************
+#define FLASH_FMPPE12_PROG_ENABLE_M \
+ 0xFFFFFFFF // Flash Programming Enable
+#define FLASH_FMPPE12_PROG_ENABLE_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPPE13 register.
+//
+//*****************************************************************************
+#define FLASH_FMPPE13_PROG_ENABLE_M \
+ 0xFFFFFFFF // Flash Programming Enable
+#define FLASH_FMPPE13_PROG_ENABLE_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPPE14 register.
+//
+//*****************************************************************************
+#define FLASH_FMPPE14_PROG_ENABLE_M \
+ 0xFFFFFFFF // Flash Programming Enable
+#define FLASH_FMPPE14_PROG_ENABLE_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the FLASH_FMPPE15 register.
+//
+//*****************************************************************************
+#define FLASH_FMPPE15_PROG_ENABLE_M \
+ 0xFFFFFFFF // Flash Programming Enable
+#define FLASH_FMPPE15_PROG_ENABLE_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the erase size of the FLASH block that is
+// erased by an erase operation, and the protect size is the size of the FLASH
+// block that is protected by each protection register.
+//
+//*****************************************************************************
+#define FLASH_PROTECT_SIZE 0x00000800
+#define FLASH_ERASE_SIZE 0x00000400
+
+#endif // __HW_FLASH_H__
diff --git a/os/common/ext/TivaWare/inc/hw_gpio.h b/os/common/ext/TivaWare/inc/hw_gpio.h
new file mode 100644
index 0000000..a2ef2e7
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_gpio.h
@@ -0,0 +1,213 @@
+//*****************************************************************************
+//
+// hw_gpio.h - Defines and Macros for GPIO hardware.
+//
+// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_GPIO_H__
+#define __HW_GPIO_H__
+
+//*****************************************************************************
+//
+// The following are defines for the GPIO register offsets.
+//
+//*****************************************************************************
+#define GPIO_O_DATA 0x00000000 // GPIO Data
+#define GPIO_O_DIR 0x00000400 // GPIO Direction
+#define GPIO_O_IS 0x00000404 // GPIO Interrupt Sense
+#define GPIO_O_IBE 0x00000408 // GPIO Interrupt Both Edges
+#define GPIO_O_IEV 0x0000040C // GPIO Interrupt Event
+#define GPIO_O_IM 0x00000410 // GPIO Interrupt Mask
+#define GPIO_O_RIS 0x00000414 // GPIO Raw Interrupt Status
+#define GPIO_O_MIS 0x00000418 // GPIO Masked Interrupt Status
+#define GPIO_O_ICR 0x0000041C // GPIO Interrupt Clear
+#define GPIO_O_AFSEL 0x00000420 // GPIO Alternate Function Select
+#define GPIO_O_DR2R 0x00000500 // GPIO 2-mA Drive Select
+#define GPIO_O_DR4R 0x00000504 // GPIO 4-mA Drive Select
+#define GPIO_O_DR8R 0x00000508 // GPIO 8-mA Drive Select
+#define GPIO_O_ODR 0x0000050C // GPIO Open Drain Select
+#define GPIO_O_PUR 0x00000510 // GPIO Pull-Up Select
+#define GPIO_O_PDR 0x00000514 // GPIO Pull-Down Select
+#define GPIO_O_SLR 0x00000518 // GPIO Slew Rate Control Select
+#define GPIO_O_DEN 0x0000051C // GPIO Digital Enable
+#define GPIO_O_LOCK 0x00000520 // GPIO Lock
+#define GPIO_O_CR 0x00000524 // GPIO Commit
+#define GPIO_O_AMSEL 0x00000528 // GPIO Analog Mode Select
+#define GPIO_O_PCTL 0x0000052C // GPIO Port Control
+#define GPIO_O_ADCCTL 0x00000530 // GPIO ADC Control
+#define GPIO_O_DMACTL 0x00000534 // GPIO DMA Control
+#define GPIO_O_SI 0x00000538 // GPIO Select Interrupt
+#define GPIO_O_DR12R 0x0000053C // GPIO 12-mA Drive Select
+#define GPIO_O_WAKEPEN 0x00000540 // GPIO Wake Pin Enable
+#define GPIO_O_WAKELVL 0x00000544 // GPIO Wake Level
+#define GPIO_O_WAKESTAT 0x00000548 // GPIO Wake Status
+#define GPIO_O_PP 0x00000FC0 // GPIO Peripheral Property
+#define GPIO_O_PC 0x00000FC4 // GPIO Peripheral Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_IM register.
+//
+//*****************************************************************************
+#define GPIO_IM_DMAIME 0x00000100 // GPIO uDMA Done Interrupt Mask
+ // Enable
+#define GPIO_IM_GPIO_M 0x000000FF // GPIO Interrupt Mask Enable
+#define GPIO_IM_GPIO_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_RIS register.
+//
+//*****************************************************************************
+#define GPIO_RIS_DMARIS 0x00000100 // GPIO uDMA Done Interrupt Raw
+ // Status
+#define GPIO_RIS_GPIO_M 0x000000FF // GPIO Interrupt Raw Status
+#define GPIO_RIS_GPIO_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_MIS register.
+//
+//*****************************************************************************
+#define GPIO_MIS_DMAMIS 0x00000100 // GPIO uDMA Done Masked Interrupt
+ // Status
+#define GPIO_MIS_GPIO_M 0x000000FF // GPIO Masked Interrupt Status
+#define GPIO_MIS_GPIO_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_ICR register.
+//
+//*****************************************************************************
+#define GPIO_ICR_DMAIC 0x00000100 // GPIO uDMA Interrupt Clear
+#define GPIO_ICR_GPIO_M 0x000000FF // GPIO Interrupt Clear
+#define GPIO_ICR_GPIO_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_LOCK register.
+//
+//*****************************************************************************
+#define GPIO_LOCK_M 0xFFFFFFFF // GPIO Lock
+#define GPIO_LOCK_UNLOCKED 0x00000000 // The GPIOCR register is unlocked
+ // and may be modified
+#define GPIO_LOCK_LOCKED 0x00000001 // The GPIOCR register is locked
+ // and may not be modified
+#define GPIO_LOCK_KEY 0x4C4F434B // Unlocks the GPIO_CR register
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_SI register.
+//
+//*****************************************************************************
+#define GPIO_SI_SUM 0x00000001 // Summary Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_DR12R register.
+//
+//*****************************************************************************
+#define GPIO_DR12R_DRV12_M 0x000000FF // Output Pad 12-mA Drive Enable
+#define GPIO_DR12R_DRV12_12MA 0x00000001 // The corresponding GPIO pin has
+ // 12-mA drive. This encoding is
+ // only valid if the GPIOPP EDE bit
+ // is set and the appropriate
+ // GPIOPC EDM bit field is
+ // programmed to 0x3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_WAKEPEN register.
+//
+//*****************************************************************************
+#define GPIO_WAKEPEN_WAKEP4 0x00000010 // P[4] Wake Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_WAKELVL register.
+//
+//*****************************************************************************
+#define GPIO_WAKELVL_WAKELVL4 0x00000010 // P[4] Wake Level
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_WAKESTAT
+// register.
+//
+//*****************************************************************************
+#define GPIO_WAKESTAT_STAT4 0x00000010 // P[4] Wake Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_PP register.
+//
+//*****************************************************************************
+#define GPIO_PP_EDE 0x00000001 // Extended Drive Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the GPIO_O_PC register.
+//
+//*****************************************************************************
+#define GPIO_PC_EDM7_M 0x0000C000 // Extended Drive Mode Bit 7
+#define GPIO_PC_EDM6_M 0x00003000 // Extended Drive Mode Bit 6
+#define GPIO_PC_EDM5_M 0x00000C00 // Extended Drive Mode Bit 5
+#define GPIO_PC_EDM4_M 0x00000300 // Extended Drive Mode Bit 4
+#define GPIO_PC_EDM3_M 0x000000C0 // Extended Drive Mode Bit 3
+#define GPIO_PC_EDM2_M 0x00000030 // Extended Drive Mode Bit 2
+#define GPIO_PC_EDM1_M 0x0000000C // Extended Drive Mode Bit 1
+#define GPIO_PC_EDM0_M 0x00000003 // Extended Drive Mode Bit 0
+#define GPIO_PC_EDM0_DISABLE 0x00000000 // Drive values of 2, 4 and 8 mA
+ // are maintained. GPIO n Drive
+ // Select (GPIODRnR) registers
+ // function as normal
+#define GPIO_PC_EDM0_6MA 0x00000001 // An additional 6 mA option is
+ // provided
+#define GPIO_PC_EDM0_PLUS2MA 0x00000003 // A 2 mA driver is always enabled;
+ // setting the corresponding
+ // GPIODR4R register bit adds 2 mA
+ // and setting the corresponding
+ // GPIODR8R of GPIODR12R register
+ // bit adds an additional 4 mA
+#define GPIO_PC_EDM7_S 14
+#define GPIO_PC_EDM6_S 12
+#define GPIO_PC_EDM5_S 10
+#define GPIO_PC_EDM4_S 8
+#define GPIO_PC_EDM3_S 6
+#define GPIO_PC_EDM2_S 4
+#define GPIO_PC_EDM1_S 2
+
+#endif // __HW_GPIO_H__
diff --git a/os/common/ext/TivaWare/inc/hw_hibernate.h b/os/common/ext/TivaWare/inc/hw_hibernate.h
new file mode 100644
index 0000000..6c9b4be
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_hibernate.h
@@ -0,0 +1,483 @@
+//*****************************************************************************
+//
+// hw_hibernate.h - Defines and Macros for the Hibernation module.
+//
+// Copyright (c) 2007-2016 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_HIBERNATE_H__
+#define __HW_HIBERNATE_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Hibernation module register addresses.
+//
+//*****************************************************************************
+#define HIB_RTCC 0x400FC000 // Hibernation RTC Counter
+#define HIB_RTCM0 0x400FC004 // Hibernation RTC Match 0
+#define HIB_RTCLD 0x400FC00C // Hibernation RTC Load
+#define HIB_CTL 0x400FC010 // Hibernation Control
+#define HIB_IM 0x400FC014 // Hibernation Interrupt Mask
+#define HIB_RIS 0x400FC018 // Hibernation Raw Interrupt Status
+#define HIB_MIS 0x400FC01C // Hibernation Masked Interrupt
+ // Status
+#define HIB_IC 0x400FC020 // Hibernation Interrupt Clear
+#define HIB_RTCT 0x400FC024 // Hibernation RTC Trim
+#define HIB_RTCSS 0x400FC028 // Hibernation RTC Sub Seconds
+#define HIB_IO 0x400FC02C // Hibernation IO Configuration
+#define HIB_DATA 0x400FC030 // Hibernation Data
+#define HIB_CALCTL 0x400FC300 // Hibernation Calendar Control
+#define HIB_CAL0 0x400FC310 // Hibernation Calendar 0
+#define HIB_CAL1 0x400FC314 // Hibernation Calendar 1
+#define HIB_CALLD0 0x400FC320 // Hibernation Calendar Load 0
+#define HIB_CALLD1 0x400FC324 // Hibernation Calendar Load
+#define HIB_CALM0 0x400FC330 // Hibernation Calendar Match 0
+#define HIB_CALM1 0x400FC334 // Hibernation Calendar Match 1
+#define HIB_LOCK 0x400FC360 // Hibernation Lock
+#define HIB_TPCTL 0x400FC400 // HIB Tamper Control
+#define HIB_TPSTAT 0x400FC404 // HIB Tamper Status
+#define HIB_TPIO 0x400FC410 // HIB Tamper I/O Control
+#define HIB_TPLOG0 0x400FC4E0 // HIB Tamper Log 0
+#define HIB_TPLOG1 0x400FC4E4 // HIB Tamper Log 1
+#define HIB_TPLOG2 0x400FC4E8 // HIB Tamper Log 2
+#define HIB_TPLOG3 0x400FC4EC // HIB Tamper Log 3
+#define HIB_TPLOG4 0x400FC4F0 // HIB Tamper Log 4
+#define HIB_TPLOG5 0x400FC4F4 // HIB Tamper Log 5
+#define HIB_TPLOG6 0x400FC4F8 // HIB Tamper Log 6
+#define HIB_TPLOG7 0x400FC4FC // HIB Tamper Log 7
+#define HIB_PP 0x400FCFC0 // Hibernation Peripheral
+ // Properties
+#define HIB_CC 0x400FCFC8 // Hibernation Clock Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCC register.
+//
+//*****************************************************************************
+#define HIB_RTCC_M 0xFFFFFFFF // RTC Counter
+#define HIB_RTCC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCM0 register.
+//
+//*****************************************************************************
+#define HIB_RTCM0_M 0xFFFFFFFF // RTC Match 0
+#define HIB_RTCM0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCLD register.
+//
+//*****************************************************************************
+#define HIB_RTCLD_M 0xFFFFFFFF // RTC Load
+#define HIB_RTCLD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CTL register.
+//
+//*****************************************************************************
+#define HIB_CTL_WRC 0x80000000 // Write Complete/Capable
+#define HIB_CTL_RETCLR 0x40000000 // GPIO Retention/Clear
+#define HIB_CTL_OSCSEL 0x00080000 // Oscillator Select
+#define HIB_CTL_OSCDRV 0x00020000 // Oscillator Drive Capability
+#define HIB_CTL_OSCBYP 0x00010000 // Oscillator Bypass
+#define HIB_CTL_VBATSEL_M 0x00006000 // Select for Low-Battery
+ // Comparator
+#define HIB_CTL_VBATSEL_1_9V 0x00000000 // 1.9 Volts
+#define HIB_CTL_VBATSEL_2_1V 0x00002000 // 2.1 Volts (default)
+#define HIB_CTL_VBATSEL_2_3V 0x00004000 // 2.3 Volts
+#define HIB_CTL_VBATSEL_2_5V 0x00006000 // 2.5 Volts
+#define HIB_CTL_BATCHK 0x00000400 // Check Battery Status
+#define HIB_CTL_BATWKEN 0x00000200 // Wake on Low Battery
+#define HIB_CTL_VDD3ON 0x00000100 // VDD Powered
+#define HIB_CTL_VABORT 0x00000080 // Power Cut Abort Enable
+#define HIB_CTL_CLK32EN 0x00000040 // Clocking Enable
+#define HIB_CTL_PINWEN 0x00000010 // External Wake Pin Enable
+#define HIB_CTL_RTCWEN 0x00000008 // RTC Wake-up Enable
+#define HIB_CTL_HIBREQ 0x00000002 // Hibernation Request
+#define HIB_CTL_RTCEN 0x00000001 // RTC Timer Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_IM register.
+//
+//*****************************************************************************
+#define HIB_IM_VDDFAIL 0x00000080 // VDD Fail Interrupt Mask
+#define HIB_IM_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Interrupt
+ // Mask
+#define HIB_IM_PADIOWK 0x00000020 // Pad I/O Wake-Up Interrupt Mask
+#define HIB_IM_WC 0x00000010 // External Write Complete/Capable
+ // Interrupt Mask
+#define HIB_IM_EXTW 0x00000008 // External Wake-Up Interrupt Mask
+#define HIB_IM_LOWBAT 0x00000004 // Low Battery Voltage Interrupt
+ // Mask
+#define HIB_IM_RTCALT0 0x00000001 // RTC Alert 0 Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RIS register.
+//
+//*****************************************************************************
+#define HIB_RIS_VDDFAIL 0x00000080 // VDD Fail Raw Interrupt Status
+#define HIB_RIS_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Raw
+ // Interrupt Status
+#define HIB_RIS_PADIOWK 0x00000020 // Pad I/O Wake-Up Raw Interrupt
+ // Status
+#define HIB_RIS_WC 0x00000010 // Write Complete/Capable Raw
+ // Interrupt Status
+#define HIB_RIS_EXTW 0x00000008 // External Wake-Up Raw Interrupt
+ // Status
+#define HIB_RIS_LOWBAT 0x00000004 // Low Battery Voltage Raw
+ // Interrupt Status
+#define HIB_RIS_RTCALT0 0x00000001 // RTC Alert 0 Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_MIS register.
+//
+//*****************************************************************************
+#define HIB_MIS_VDDFAIL 0x00000080 // VDD Fail Interrupt Mask
+#define HIB_MIS_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Interrupt
+ // Mask
+#define HIB_MIS_PADIOWK 0x00000020 // Pad I/O Wake-Up Interrupt Mask
+#define HIB_MIS_WC 0x00000010 // Write Complete/Capable Masked
+ // Interrupt Status
+#define HIB_MIS_EXTW 0x00000008 // External Wake-Up Masked
+ // Interrupt Status
+#define HIB_MIS_LOWBAT 0x00000004 // Low Battery Voltage Masked
+ // Interrupt Status
+#define HIB_MIS_RTCALT0 0x00000001 // RTC Alert 0 Masked Interrupt
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_IC register.
+//
+//*****************************************************************************
+#define HIB_IC_VDDFAIL 0x00000080 // VDD Fail Interrupt Clear
+#define HIB_IC_RSTWK 0x00000040 // Reset Pad I/O Wake-Up Interrupt
+ // Clear
+#define HIB_IC_PADIOWK 0x00000020 // Pad I/O Wake-Up Interrupt Clear
+#define HIB_IC_WC 0x00000010 // Write Complete/Capable Interrupt
+ // Clear
+#define HIB_IC_EXTW 0x00000008 // External Wake-Up Interrupt Clear
+#define HIB_IC_LOWBAT 0x00000004 // Low Battery Voltage Interrupt
+ // Clear
+#define HIB_IC_RTCALT0 0x00000001 // RTC Alert0 Masked Interrupt
+ // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCT register.
+//
+//*****************************************************************************
+#define HIB_RTCT_TRIM_M 0x0000FFFF // RTC Trim Value
+#define HIB_RTCT_TRIM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_RTCSS register.
+//
+//*****************************************************************************
+#define HIB_RTCSS_RTCSSM_M 0x7FFF0000 // RTC Sub Seconds Match
+#define HIB_RTCSS_RTCSSC_M 0x00007FFF // RTC Sub Seconds Count
+#define HIB_RTCSS_RTCSSM_S 16
+#define HIB_RTCSS_RTCSSC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_IO register.
+//
+//*****************************************************************************
+#define HIB_IO_IOWRC 0x80000000 // I/O Write Complete
+#define HIB_IO_WURSTEN 0x00000010 // Reset Wake Source Enable
+#define HIB_IO_WUUNLK 0x00000001 // I/O Wake Pad Configuration
+ // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_DATA register.
+//
+//*****************************************************************************
+#define HIB_DATA_RTD_M 0xFFFFFFFF // Hibernation Module NV Data
+#define HIB_DATA_RTD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CALCTL register.
+//
+//*****************************************************************************
+#define HIB_CALCTL_CAL24 0x00000004 // Calendar Mode
+#define HIB_CALCTL_CALEN 0x00000001 // RTC Calendar/Counter Mode Select
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CAL0 register.
+//
+//*****************************************************************************
+#define HIB_CAL0_VALID 0x80000000 // Valid Calendar Load
+#define HIB_CAL0_AMPM 0x00400000 // AM/PM Designation
+#define HIB_CAL0_HR_M 0x001F0000 // Hours
+#define HIB_CAL0_MIN_M 0x00003F00 // Minutes
+#define HIB_CAL0_SEC_M 0x0000003F // Seconds
+#define HIB_CAL0_HR_S 16
+#define HIB_CAL0_MIN_S 8
+#define HIB_CAL0_SEC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CAL1 register.
+//
+//*****************************************************************************
+#define HIB_CAL1_VALID 0x80000000 // Valid Calendar Load
+#define HIB_CAL1_DOW_M 0x07000000 // Day of Week
+#define HIB_CAL1_YEAR_M 0x007F0000 // Year Value
+#define HIB_CAL1_MON_M 0x00000F00 // Month
+#define HIB_CAL1_DOM_M 0x0000001F // Day of Month
+#define HIB_CAL1_DOW_S 24
+#define HIB_CAL1_YEAR_S 16
+#define HIB_CAL1_MON_S 8
+#define HIB_CAL1_DOM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CALLD0 register.
+//
+//*****************************************************************************
+#define HIB_CALLD0_AMPM 0x00400000 // AM/PM Designation
+#define HIB_CALLD0_HR_M 0x001F0000 // Hours
+#define HIB_CALLD0_MIN_M 0x00003F00 // Minutes
+#define HIB_CALLD0_SEC_M 0x0000003F // Seconds
+#define HIB_CALLD0_HR_S 16
+#define HIB_CALLD0_MIN_S 8
+#define HIB_CALLD0_SEC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CALLD1 register.
+//
+//*****************************************************************************
+#define HIB_CALLD1_DOW_M 0x07000000 // Day of Week
+#define HIB_CALLD1_YEAR_M 0x007F0000 // Year Value
+#define HIB_CALLD1_MON_M 0x00000F00 // Month
+#define HIB_CALLD1_DOM_M 0x0000001F // Day of Month
+#define HIB_CALLD1_DOW_S 24
+#define HIB_CALLD1_YEAR_S 16
+#define HIB_CALLD1_MON_S 8
+#define HIB_CALLD1_DOM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CALM0 register.
+//
+//*****************************************************************************
+#define HIB_CALM0_AMPM 0x00400000 // AM/PM Designation
+#define HIB_CALM0_HR_M 0x001F0000 // Hours
+#define HIB_CALM0_MIN_M 0x00003F00 // Minutes
+#define HIB_CALM0_SEC_M 0x0000003F // Seconds
+#define HIB_CALM0_HR_S 16
+#define HIB_CALM0_MIN_S 8
+#define HIB_CALM0_SEC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CALM1 register.
+//
+//*****************************************************************************
+#define HIB_CALM1_DOM_M 0x0000001F // Day of Month
+#define HIB_CALM1_DOM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_LOCK register.
+//
+//*****************************************************************************
+#define HIB_LOCK_HIBLOCK_M 0xFFFFFFFF // HIbernate Lock
+#define HIB_LOCK_HIBLOCK_KEY 0xA3359554 // Hibernate Lock Key
+#define HIB_LOCK_HIBLOCK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPCTL register.
+//
+//*****************************************************************************
+#define HIB_TPCTL_WAKE 0x00000800 // Wake from Hibernate on a Tamper
+ // Event
+#define HIB_TPCTL_MEMCLR_M 0x00000300 // HIB Memory Clear on Tamper Event
+#define HIB_TPCTL_MEMCLR_NONE 0x00000000 // Do not Clear HIB memory on
+ // tamper event
+#define HIB_TPCTL_MEMCLR_LOW32 0x00000100 // Clear Lower 32 Bytes of HIB
+ // memory on tamper event
+#define HIB_TPCTL_MEMCLR_HIGH32 0x00000200 // Clear upper 32 Bytes of HIB
+ // memory on tamper event
+#define HIB_TPCTL_MEMCLR_ALL 0x00000300 // Clear all HIB memory on tamper
+ // event
+#define HIB_TPCTL_TPCLR 0x00000010 // Tamper Event Clear
+#define HIB_TPCTL_TPEN 0x00000001 // Tamper Module Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPSTAT register.
+//
+//*****************************************************************************
+#define HIB_TPSTAT_STATE_M 0x0000000C // Tamper Module Status
+#define HIB_TPSTAT_STATE_DISABLED \
+ 0x00000000 // Tamper disabled
+#define HIB_TPSTAT_STATE_CONFIGED \
+ 0x00000004 // Tamper configured
+#define HIB_TPSTAT_STATE_ERROR 0x00000008 // Tamper pin event occurred
+#define HIB_TPSTAT_XOSCST 0x00000002 // External Oscillator Status
+#define HIB_TPSTAT_XOSCFAIL 0x00000001 // External Oscillator Failure
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPIO register.
+//
+//*****************************************************************************
+#define HIB_TPIO_GFLTR3 0x08000000 // TMPR3 Glitch Filtering
+#define HIB_TPIO_PUEN3 0x04000000 // TMPR3 Internal Weak Pull-up
+ // Enable
+#define HIB_TPIO_LEV3 0x02000000 // TMPR3 Trigger Level
+#define HIB_TPIO_EN3 0x01000000 // TMPR3 Enable
+#define HIB_TPIO_GFLTR2 0x00080000 // TMPR2 Glitch Filtering
+#define HIB_TPIO_PUEN2 0x00040000 // TMPR2 Internal Weak Pull-up
+ // Enable
+#define HIB_TPIO_LEV2 0x00020000 // TMPR2 Trigger Level
+#define HIB_TPIO_EN2 0x00010000 // TMPR2 Enable
+#define HIB_TPIO_GFLTR1 0x00000800 // TMPR1 Glitch Filtering
+#define HIB_TPIO_PUEN1 0x00000400 // TMPR1 Internal Weak Pull-up
+ // Enable
+#define HIB_TPIO_LEV1 0x00000200 // TMPR1 Trigger Level
+#define HIB_TPIO_EN1 0x00000100 // TMPR1Enable
+#define HIB_TPIO_GFLTR0 0x00000008 // TMPR0 Glitch Filtering
+#define HIB_TPIO_PUEN0 0x00000004 // TMPR0 Internal Weak Pull-up
+ // Enable
+#define HIB_TPIO_LEV0 0x00000002 // TMPR0 Trigger Level
+#define HIB_TPIO_EN0 0x00000001 // TMPR0 Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPLOG0 register.
+//
+//*****************************************************************************
+#define HIB_TPLOG0_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information
+#define HIB_TPLOG0_TIME_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPLOG1 register.
+//
+//*****************************************************************************
+#define HIB_TPLOG1_XOSC 0x00010000 // Status of external 32
+#define HIB_TPLOG1_TRIG3 0x00000008 // Status of TMPR[3] Trigger
+#define HIB_TPLOG1_TRIG2 0x00000004 // Status of TMPR[2] Trigger
+#define HIB_TPLOG1_TRIG1 0x00000002 // Status of TMPR[1] Trigger
+#define HIB_TPLOG1_TRIG0 0x00000001 // Status of TMPR[0] Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPLOG2 register.
+//
+//*****************************************************************************
+#define HIB_TPLOG2_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information
+#define HIB_TPLOG2_TIME_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPLOG3 register.
+//
+//*****************************************************************************
+#define HIB_TPLOG3_XOSC 0x00010000 // Status of external 32
+#define HIB_TPLOG3_TRIG3 0x00000008 // Status of TMPR[3] Trigger
+#define HIB_TPLOG3_TRIG2 0x00000004 // Status of TMPR[2] Trigger
+#define HIB_TPLOG3_TRIG1 0x00000002 // Status of TMPR[1] Trigger
+#define HIB_TPLOG3_TRIG0 0x00000001 // Status of TMPR[0] Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPLOG4 register.
+//
+//*****************************************************************************
+#define HIB_TPLOG4_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information
+#define HIB_TPLOG4_TIME_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPLOG5 register.
+//
+//*****************************************************************************
+#define HIB_TPLOG5_XOSC 0x00010000 // Status of external 32
+#define HIB_TPLOG5_TRIG3 0x00000008 // Status of TMPR[3] Trigger
+#define HIB_TPLOG5_TRIG2 0x00000004 // Status of TMPR[2] Trigger
+#define HIB_TPLOG5_TRIG1 0x00000002 // Status of TMPR[1] Trigger
+#define HIB_TPLOG5_TRIG0 0x00000001 // Status of TMPR[0] Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPLOG6 register.
+//
+//*****************************************************************************
+#define HIB_TPLOG6_TIME_M 0xFFFFFFFF // Tamper Log Calendar Information
+#define HIB_TPLOG6_TIME_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_TPLOG7 register.
+//
+//*****************************************************************************
+#define HIB_TPLOG7_XOSC 0x00010000 // Status of external 32
+#define HIB_TPLOG7_TRIG3 0x00000008 // Status of TMPR[3] Trigger
+#define HIB_TPLOG7_TRIG2 0x00000004 // Status of TMPR[2] Trigger
+#define HIB_TPLOG7_TRIG1 0x00000002 // Status of TMPR[1] Trigger
+#define HIB_TPLOG7_TRIG0 0x00000001 // Status of TMPR[0] Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_PP register.
+//
+//*****************************************************************************
+#define HIB_PP_TAMPER 0x00000002 // Tamper Pin Presence
+#define HIB_PP_WAKENC 0x00000001 // Wake Pin Presence
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the HIB_CC register.
+//
+//*****************************************************************************
+#define HIB_CC_SYSCLKEN 0x00000001 // RTCOSC to System Clock Enable
+
+#endif // __HW_HIBERNATE_H__
diff --git a/os/common/ext/TivaWare/inc/hw_i2c.h b/os/common/ext/TivaWare/inc/hw_i2c.h
new file mode 100644
index 0000000..2cc2032
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_i2c.h
@@ -0,0 +1,470 @@
+//*****************************************************************************
+//
+// hw_i2c.h - Macros used when accessing the I2C master and slave hardware.
+//
+// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_I2C_H__
+#define __HW_I2C_H__
+
+//*****************************************************************************
+//
+// The following are defines for the I2C register offsets.
+//
+//*****************************************************************************
+#define I2C_O_MSA 0x00000000 // I2C Master Slave Address
+#define I2C_O_MCS 0x00000004 // I2C Master Control/Status
+#define I2C_O_MDR 0x00000008 // I2C Master Data
+#define I2C_O_MTPR 0x0000000C // I2C Master Timer Period
+#define I2C_O_MIMR 0x00000010 // I2C Master Interrupt Mask
+#define I2C_O_MRIS 0x00000014 // I2C Master Raw Interrupt Status
+#define I2C_O_MMIS 0x00000018 // I2C Master Masked Interrupt
+ // Status
+#define I2C_O_MICR 0x0000001C // I2C Master Interrupt Clear
+#define I2C_O_MCR 0x00000020 // I2C Master Configuration
+#define I2C_O_MCLKOCNT 0x00000024 // I2C Master Clock Low Timeout
+ // Count
+#define I2C_O_MBMON 0x0000002C // I2C Master Bus Monitor
+#define I2C_O_MBLEN 0x00000030 // I2C Master Burst Length
+#define I2C_O_MBCNT 0x00000034 // I2C Master Burst Count
+#define I2C_O_MCR2 0x00000038 // I2C Master Configuration 2
+#define I2C_O_SOAR 0x00000800 // I2C Slave Own Address
+#define I2C_O_SCSR 0x00000804 // I2C Slave Control/Status
+#define I2C_O_SDR 0x00000808 // I2C Slave Data
+#define I2C_O_SIMR 0x0000080C // I2C Slave Interrupt Mask
+#define I2C_O_SRIS 0x00000810 // I2C Slave Raw Interrupt Status
+#define I2C_O_SMIS 0x00000814 // I2C Slave Masked Interrupt
+ // Status
+#define I2C_O_SICR 0x00000818 // I2C Slave Interrupt Clear
+#define I2C_O_SOAR2 0x0000081C // I2C Slave Own Address 2
+#define I2C_O_SACKCTL 0x00000820 // I2C Slave ACK Control
+#define I2C_O_FIFODATA 0x00000F00 // I2C FIFO Data
+#define I2C_O_FIFOCTL 0x00000F04 // I2C FIFO Control
+#define I2C_O_FIFOSTATUS 0x00000F08 // I2C FIFO Status
+#define I2C_O_PP 0x00000FC0 // I2C Peripheral Properties
+#define I2C_O_PC 0x00000FC4 // I2C Peripheral Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MSA register.
+//
+//*****************************************************************************
+#define I2C_MSA_SA_M 0x000000FE // I2C Slave Address
+#define I2C_MSA_RS 0x00000001 // Receive not send
+#define I2C_MSA_SA_S 1
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCS register.
+//
+//*****************************************************************************
+#define I2C_MCS_ACTDMARX 0x80000000 // DMA RX Active Status
+#define I2C_MCS_ACTDMATX 0x40000000 // DMA TX Active Status
+#define I2C_MCS_CLKTO 0x00000080 // Clock Timeout Error
+#define I2C_MCS_BURST 0x00000040 // Burst Enable
+#define I2C_MCS_BUSBSY 0x00000040 // Bus Busy
+#define I2C_MCS_IDLE 0x00000020 // I2C Idle
+#define I2C_MCS_QCMD 0x00000020 // Quick Command
+#define I2C_MCS_ARBLST 0x00000010 // Arbitration Lost
+#define I2C_MCS_HS 0x00000010 // High-Speed Enable
+#define I2C_MCS_ACK 0x00000008 // Data Acknowledge Enable
+#define I2C_MCS_DATACK 0x00000008 // Acknowledge Data
+#define I2C_MCS_ADRACK 0x00000004 // Acknowledge Address
+#define I2C_MCS_STOP 0x00000004 // Generate STOP
+#define I2C_MCS_ERROR 0x00000002 // Error
+#define I2C_MCS_START 0x00000002 // Generate START
+#define I2C_MCS_RUN 0x00000001 // I2C Master Enable
+#define I2C_MCS_BUSY 0x00000001 // I2C Busy
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MDR register.
+//
+//*****************************************************************************
+#define I2C_MDR_DATA_M 0x000000FF // This byte contains the data
+ // transferred during a transaction
+#define I2C_MDR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MTPR register.
+//
+//*****************************************************************************
+#define I2C_MTPR_PULSEL_M 0x00070000 // Glitch Suppression Pulse Width
+#define I2C_MTPR_PULSEL_BYPASS 0x00000000 // Bypass
+#define I2C_MTPR_PULSEL_1 0x00010000 // 1 clock
+#define I2C_MTPR_PULSEL_2 0x00020000 // 2 clocks
+#define I2C_MTPR_PULSEL_3 0x00030000 // 3 clocks
+#define I2C_MTPR_PULSEL_4 0x00040000 // 4 clocks
+#define I2C_MTPR_PULSEL_8 0x00050000 // 8 clocks
+#define I2C_MTPR_PULSEL_16 0x00060000 // 16 clocks
+#define I2C_MTPR_PULSEL_31 0x00070000 // 31 clocks
+#define I2C_MTPR_HS 0x00000080 // High-Speed Enable
+#define I2C_MTPR_TPR_M 0x0000007F // Timer Period
+#define I2C_MTPR_TPR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MIMR register.
+//
+//*****************************************************************************
+#define I2C_MIMR_RXFFIM 0x00000800 // Receive FIFO Full Interrupt Mask
+#define I2C_MIMR_TXFEIM 0x00000400 // Transmit FIFO Empty Interrupt
+ // Mask
+#define I2C_MIMR_RXIM 0x00000200 // Receive FIFO Request Interrupt
+ // Mask
+#define I2C_MIMR_TXIM 0x00000100 // Transmit FIFO Request Interrupt
+ // Mask
+#define I2C_MIMR_ARBLOSTIM 0x00000080 // Arbitration Lost Interrupt Mask
+#define I2C_MIMR_STOPIM 0x00000040 // STOP Detection Interrupt Mask
+#define I2C_MIMR_STARTIM 0x00000020 // START Detection Interrupt Mask
+#define I2C_MIMR_NACKIM 0x00000010 // Address/Data NACK Interrupt Mask
+#define I2C_MIMR_DMATXIM 0x00000008 // Transmit DMA Interrupt Mask
+#define I2C_MIMR_DMARXIM 0x00000004 // Receive DMA Interrupt Mask
+#define I2C_MIMR_CLKIM 0x00000002 // Clock Timeout Interrupt Mask
+#define I2C_MIMR_IM 0x00000001 // Master Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MRIS register.
+//
+//*****************************************************************************
+#define I2C_MRIS_RXFFRIS 0x00000800 // Receive FIFO Full Raw Interrupt
+ // Status
+#define I2C_MRIS_TXFERIS 0x00000400 // Transmit FIFO Empty Raw
+ // Interrupt Status
+#define I2C_MRIS_RXRIS 0x00000200 // Receive FIFO Request Raw
+ // Interrupt Status
+#define I2C_MRIS_TXRIS 0x00000100 // Transmit Request Raw Interrupt
+ // Status
+#define I2C_MRIS_ARBLOSTRIS 0x00000080 // Arbitration Lost Raw Interrupt
+ // Status
+#define I2C_MRIS_STOPRIS 0x00000040 // STOP Detection Raw Interrupt
+ // Status
+#define I2C_MRIS_STARTRIS 0x00000020 // START Detection Raw Interrupt
+ // Status
+#define I2C_MRIS_NACKRIS 0x00000010 // Address/Data NACK Raw Interrupt
+ // Status
+#define I2C_MRIS_DMATXRIS 0x00000008 // Transmit DMA Raw Interrupt
+ // Status
+#define I2C_MRIS_DMARXRIS 0x00000004 // Receive DMA Raw Interrupt Status
+#define I2C_MRIS_CLKRIS 0x00000002 // Clock Timeout Raw Interrupt
+ // Status
+#define I2C_MRIS_RIS 0x00000001 // Master Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MMIS register.
+//
+//*****************************************************************************
+#define I2C_MMIS_RXFFMIS 0x00000800 // Receive FIFO Full Interrupt Mask
+#define I2C_MMIS_TXFEMIS 0x00000400 // Transmit FIFO Empty Interrupt
+ // Mask
+#define I2C_MMIS_RXMIS 0x00000200 // Receive FIFO Request Interrupt
+ // Mask
+#define I2C_MMIS_TXMIS 0x00000100 // Transmit Request Interrupt Mask
+#define I2C_MMIS_ARBLOSTMIS 0x00000080 // Arbitration Lost Interrupt Mask
+#define I2C_MMIS_STOPMIS 0x00000040 // STOP Detection Interrupt Mask
+#define I2C_MMIS_STARTMIS 0x00000020 // START Detection Interrupt Mask
+#define I2C_MMIS_NACKMIS 0x00000010 // Address/Data NACK Interrupt Mask
+#define I2C_MMIS_DMATXMIS 0x00000008 // Transmit DMA Interrupt Status
+#define I2C_MMIS_DMARXMIS 0x00000004 // Receive DMA Interrupt Status
+#define I2C_MMIS_CLKMIS 0x00000002 // Clock Timeout Masked Interrupt
+ // Status
+#define I2C_MMIS_MIS 0x00000001 // Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MICR register.
+//
+//*****************************************************************************
+#define I2C_MICR_RXFFIC 0x00000800 // Receive FIFO Full Interrupt
+ // Clear
+#define I2C_MICR_TXFEIC 0x00000400 // Transmit FIFO Empty Interrupt
+ // Clear
+#define I2C_MICR_RXIC 0x00000200 // Receive FIFO Request Interrupt
+ // Clear
+#define I2C_MICR_TXIC 0x00000100 // Transmit FIFO Request Interrupt
+ // Clear
+#define I2C_MICR_ARBLOSTIC 0x00000080 // Arbitration Lost Interrupt Clear
+#define I2C_MICR_STOPIC 0x00000040 // STOP Detection Interrupt Clear
+#define I2C_MICR_STARTIC 0x00000020 // START Detection Interrupt Clear
+#define I2C_MICR_NACKIC 0x00000010 // Address/Data NACK Interrupt
+ // Clear
+#define I2C_MICR_DMATXIC 0x00000008 // Transmit DMA Interrupt Clear
+#define I2C_MICR_DMARXIC 0x00000004 // Receive DMA Interrupt Clear
+#define I2C_MICR_CLKIC 0x00000002 // Clock Timeout Interrupt Clear
+#define I2C_MICR_IC 0x00000001 // Master Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCR register.
+//
+//*****************************************************************************
+#define I2C_MCR_GFE 0x00000040 // I2C Glitch Filter Enable
+#define I2C_MCR_SFE 0x00000020 // I2C Slave Function Enable
+#define I2C_MCR_MFE 0x00000010 // I2C Master Function Enable
+#define I2C_MCR_LPBK 0x00000001 // I2C Loopback
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCLKOCNT register.
+//
+//*****************************************************************************
+#define I2C_MCLKOCNT_CNTL_M 0x000000FF // I2C Master Count
+#define I2C_MCLKOCNT_CNTL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MBMON register.
+//
+//*****************************************************************************
+#define I2C_MBMON_SDA 0x00000002 // I2C SDA Status
+#define I2C_MBMON_SCL 0x00000001 // I2C SCL Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MBLEN register.
+//
+//*****************************************************************************
+#define I2C_MBLEN_CNTL_M 0x000000FF // I2C Burst Length
+#define I2C_MBLEN_CNTL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MBCNT register.
+//
+//*****************************************************************************
+#define I2C_MBCNT_CNTL_M 0x000000FF // I2C Master Burst Count
+#define I2C_MBCNT_CNTL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_MCR2 register.
+//
+//*****************************************************************************
+#define I2C_MCR2_GFPW_M 0x00000070 // I2C Glitch Filter Pulse Width
+#define I2C_MCR2_GFPW_BYPASS 0x00000000 // Bypass
+#define I2C_MCR2_GFPW_1 0x00000010 // 1 clock
+#define I2C_MCR2_GFPW_2 0x00000020 // 2 clocks
+#define I2C_MCR2_GFPW_3 0x00000030 // 3 clocks
+#define I2C_MCR2_GFPW_4 0x00000040 // 4 clocks
+#define I2C_MCR2_GFPW_8 0x00000050 // 8 clocks
+#define I2C_MCR2_GFPW_16 0x00000060 // 16 clocks
+#define I2C_MCR2_GFPW_31 0x00000070 // 31 clocks
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SOAR register.
+//
+//*****************************************************************************
+#define I2C_SOAR_OAR_M 0x0000007F // I2C Slave Own Address
+#define I2C_SOAR_OAR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SCSR register.
+//
+//*****************************************************************************
+#define I2C_SCSR_ACTDMARX 0x80000000 // DMA RX Active Status
+#define I2C_SCSR_ACTDMATX 0x40000000 // DMA TX Active Status
+#define I2C_SCSR_QCMDRW 0x00000020 // Quick Command Read / Write
+#define I2C_SCSR_QCMDST 0x00000010 // Quick Command Status
+#define I2C_SCSR_OAR2SEL 0x00000008 // OAR2 Address Matched
+#define I2C_SCSR_FBR 0x00000004 // First Byte Received
+#define I2C_SCSR_RXFIFO 0x00000004 // RX FIFO Enable
+#define I2C_SCSR_TXFIFO 0x00000002 // TX FIFO Enable
+#define I2C_SCSR_TREQ 0x00000002 // Transmit Request
+#define I2C_SCSR_DA 0x00000001 // Device Active
+#define I2C_SCSR_RREQ 0x00000001 // Receive Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SDR register.
+//
+//*****************************************************************************
+#define I2C_SDR_DATA_M 0x000000FF // Data for Transfer
+#define I2C_SDR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SIMR register.
+//
+//*****************************************************************************
+#define I2C_SIMR_RXFFIM 0x00000100 // Receive FIFO Full Interrupt Mask
+#define I2C_SIMR_TXFEIM 0x00000080 // Transmit FIFO Empty Interrupt
+ // Mask
+#define I2C_SIMR_RXIM 0x00000040 // Receive FIFO Request Interrupt
+ // Mask
+#define I2C_SIMR_TXIM 0x00000020 // Transmit FIFO Request Interrupt
+ // Mask
+#define I2C_SIMR_DMATXIM 0x00000010 // Transmit DMA Interrupt Mask
+#define I2C_SIMR_DMARXIM 0x00000008 // Receive DMA Interrupt Mask
+#define I2C_SIMR_STOPIM 0x00000004 // Stop Condition Interrupt Mask
+#define I2C_SIMR_STARTIM 0x00000002 // Start Condition Interrupt Mask
+#define I2C_SIMR_DATAIM 0x00000001 // Data Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SRIS register.
+//
+//*****************************************************************************
+#define I2C_SRIS_RXFFRIS 0x00000100 // Receive FIFO Full Raw Interrupt
+ // Status
+#define I2C_SRIS_TXFERIS 0x00000080 // Transmit FIFO Empty Raw
+ // Interrupt Status
+#define I2C_SRIS_RXRIS 0x00000040 // Receive FIFO Request Raw
+ // Interrupt Status
+#define I2C_SRIS_TXRIS 0x00000020 // Transmit Request Raw Interrupt
+ // Status
+#define I2C_SRIS_DMATXRIS 0x00000010 // Transmit DMA Raw Interrupt
+ // Status
+#define I2C_SRIS_DMARXRIS 0x00000008 // Receive DMA Raw Interrupt Status
+#define I2C_SRIS_STOPRIS 0x00000004 // Stop Condition Raw Interrupt
+ // Status
+#define I2C_SRIS_STARTRIS 0x00000002 // Start Condition Raw Interrupt
+ // Status
+#define I2C_SRIS_DATARIS 0x00000001 // Data Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SMIS register.
+//
+//*****************************************************************************
+#define I2C_SMIS_RXFFMIS 0x00000100 // Receive FIFO Full Interrupt Mask
+#define I2C_SMIS_TXFEMIS 0x00000080 // Transmit FIFO Empty Interrupt
+ // Mask
+#define I2C_SMIS_RXMIS 0x00000040 // Receive FIFO Request Interrupt
+ // Mask
+#define I2C_SMIS_TXMIS 0x00000020 // Transmit FIFO Request Interrupt
+ // Mask
+#define I2C_SMIS_DMATXMIS 0x00000010 // Transmit DMA Masked Interrupt
+ // Status
+#define I2C_SMIS_DMARXMIS 0x00000008 // Receive DMA Masked Interrupt
+ // Status
+#define I2C_SMIS_STOPMIS 0x00000004 // Stop Condition Masked Interrupt
+ // Status
+#define I2C_SMIS_STARTMIS 0x00000002 // Start Condition Masked Interrupt
+ // Status
+#define I2C_SMIS_DATAMIS 0x00000001 // Data Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SICR register.
+//
+//*****************************************************************************
+#define I2C_SICR_RXFFIC 0x00000100 // Receive FIFO Full Interrupt Mask
+#define I2C_SICR_TXFEIC 0x00000080 // Transmit FIFO Empty Interrupt
+ // Mask
+#define I2C_SICR_RXIC 0x00000040 // Receive Request Interrupt Mask
+#define I2C_SICR_TXIC 0x00000020 // Transmit Request Interrupt Mask
+#define I2C_SICR_DMATXIC 0x00000010 // Transmit DMA Interrupt Clear
+#define I2C_SICR_DMARXIC 0x00000008 // Receive DMA Interrupt Clear
+#define I2C_SICR_STOPIC 0x00000004 // Stop Condition Interrupt Clear
+#define I2C_SICR_STARTIC 0x00000002 // Start Condition Interrupt Clear
+#define I2C_SICR_DATAIC 0x00000001 // Data Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SOAR2 register.
+//
+//*****************************************************************************
+#define I2C_SOAR2_OAR2EN 0x00000080 // I2C Slave Own Address 2 Enable
+#define I2C_SOAR2_OAR2_M 0x0000007F // I2C Slave Own Address 2
+#define I2C_SOAR2_OAR2_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_SACKCTL register.
+//
+//*****************************************************************************
+#define I2C_SACKCTL_ACKOVAL 0x00000002 // I2C Slave ACK Override Value
+#define I2C_SACKCTL_ACKOEN 0x00000001 // I2C Slave ACK Override Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_FIFODATA register.
+//
+//*****************************************************************************
+#define I2C_FIFODATA_DATA_M 0x000000FF // I2C TX FIFO Write Data Byte
+#define I2C_FIFODATA_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_FIFOCTL register.
+//
+//*****************************************************************************
+#define I2C_FIFOCTL_RXASGNMT 0x80000000 // RX Control Assignment
+#define I2C_FIFOCTL_RXFLUSH 0x40000000 // RX FIFO Flush
+#define I2C_FIFOCTL_DMARXENA 0x20000000 // DMA RX Channel Enable
+#define I2C_FIFOCTL_RXTRIG_M 0x00070000 // RX FIFO Trigger
+#define I2C_FIFOCTL_TXASGNMT 0x00008000 // TX Control Assignment
+#define I2C_FIFOCTL_TXFLUSH 0x00004000 // TX FIFO Flush
+#define I2C_FIFOCTL_DMATXENA 0x00002000 // DMA TX Channel Enable
+#define I2C_FIFOCTL_TXTRIG_M 0x00000007 // TX FIFO Trigger
+#define I2C_FIFOCTL_RXTRIG_S 16
+#define I2C_FIFOCTL_TXTRIG_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_FIFOSTATUS
+// register.
+//
+//*****************************************************************************
+#define I2C_FIFOSTATUS_RXABVTRIG \
+ 0x00040000 // RX FIFO Above Trigger Level
+#define I2C_FIFOSTATUS_RXFF 0x00020000 // RX FIFO Full
+#define I2C_FIFOSTATUS_RXFE 0x00010000 // RX FIFO Empty
+#define I2C_FIFOSTATUS_TXBLWTRIG \
+ 0x00000004 // TX FIFO Below Trigger Level
+#define I2C_FIFOSTATUS_TXFF 0x00000002 // TX FIFO Full
+#define I2C_FIFOSTATUS_TXFE 0x00000001 // TX FIFO Empty
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_PP register.
+//
+//*****************************************************************************
+#define I2C_PP_HS 0x00000001 // High-Speed Capable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the I2C_O_PC register.
+//
+//*****************************************************************************
+#define I2C_PC_HS 0x00000001 // High-Speed Capable
+
+#endif // __HW_I2C_H__
diff --git a/os/common/ext/TivaWare/inc/hw_ints.h b/os/common/ext/TivaWare/inc/hw_ints.h
new file mode 100644
index 0000000..d8efb43
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_ints.h
@@ -0,0 +1,491 @@
+//*****************************************************************************
+//
+// hw_ints.h - Macros that define the interrupt assignment on Tiva C Series
+// MCUs.
+//
+// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_INTS_H__
+#define __HW_INTS_H__
+
+//*****************************************************************************
+//
+// The following are defines for the fault assignments.
+//
+//*****************************************************************************
+#define FAULT_NMI 2 // NMI fault
+#define FAULT_HARD 3 // Hard fault
+#define FAULT_MPU 4 // MPU fault
+#define FAULT_BUS 5 // Bus fault
+#define FAULT_USAGE 6 // Usage fault
+#define FAULT_SVCALL 11 // SVCall
+#define FAULT_DEBUG 12 // Debug monitor
+#define FAULT_PENDSV 14 // PendSV
+#define FAULT_SYSTICK 15 // System Tick
+
+//*****************************************************************************
+//
+// TM4C123 Class Interrupts
+//
+//*****************************************************************************
+#define INT_GPIOA_TM4C123 16 // GPIO Port A
+#define INT_GPIOB_TM4C123 17 // GPIO Port B
+#define INT_GPIOC_TM4C123 18 // GPIO Port C
+#define INT_GPIOD_TM4C123 19 // GPIO Port D
+#define INT_GPIOE_TM4C123 20 // GPIO Port E
+#define INT_UART0_TM4C123 21 // UART0
+#define INT_UART1_TM4C123 22 // UART1
+#define INT_SSI0_TM4C123 23 // SSI0
+#define INT_I2C0_TM4C123 24 // I2C0
+#define INT_PWM0_FAULT_TM4C123 25 // PWM0 Fault
+#define INT_PWM0_0_TM4C123 26 // PWM0 Generator 0
+#define INT_PWM0_1_TM4C123 27 // PWM0 Generator 1
+#define INT_PWM0_2_TM4C123 28 // PWM0 Generator 2
+#define INT_QEI0_TM4C123 29 // QEI0
+#define INT_ADC0SS0_TM4C123 30 // ADC0 Sequence 0
+#define INT_ADC0SS1_TM4C123 31 // ADC0 Sequence 1
+#define INT_ADC0SS2_TM4C123 32 // ADC0 Sequence 2
+#define INT_ADC0SS3_TM4C123 33 // ADC0 Sequence 3
+#define INT_WATCHDOG_TM4C123 34 // Watchdog Timers 0 and 1
+#define INT_TIMER0A_TM4C123 35 // 16/32-Bit Timer 0A
+#define INT_TIMER0B_TM4C123 36 // 16/32-Bit Timer 0B
+#define INT_TIMER1A_TM4C123 37 // 16/32-Bit Timer 1A
+#define INT_TIMER1B_TM4C123 38 // 16/32-Bit Timer 1B
+#define INT_TIMER2A_TM4C123 39 // 16/32-Bit Timer 2A
+#define INT_TIMER2B_TM4C123 40 // 16/32-Bit Timer 2B
+#define INT_COMP0_TM4C123 41 // Analog Comparator 0
+#define INT_COMP1_TM4C123 42 // Analog Comparator 1
+#define INT_COMP2_TM4C123 43 // Analog Comparator 2
+#define INT_SYSCTL_TM4C123 44 // System Control
+#define INT_FLASH_TM4C123 45 // Flash Memory Control and EEPROM
+ // Control
+#define INT_GPIOF_TM4C123 46 // GPIO Port F
+#define INT_GPIOG_TM4C123 47 // GPIO Port G
+#define INT_GPIOH_TM4C123 48 // GPIO Port H
+#define INT_UART2_TM4C123 49 // UART2
+#define INT_SSI1_TM4C123 50 // SSI1
+#define INT_TIMER3A_TM4C123 51 // 16/32-Bit Timer 3A
+#define INT_TIMER3B_TM4C123 52 // Timer 3B
+#define INT_I2C1_TM4C123 53 // I2C1
+#define INT_QEI1_TM4C123 54 // QEI1
+#define INT_CAN0_TM4C123 55 // CAN0
+#define INT_CAN1_TM4C123 56 // CAN1
+#define INT_HIBERNATE_TM4C123 59 // Hibernation Module
+#define INT_USB0_TM4C123 60 // USB
+#define INT_PWM0_3_TM4C123 61 // PWM Generator 3
+#define INT_UDMA_TM4C123 62 // uDMA Software
+#define INT_UDMAERR_TM4C123 63 // uDMA Error
+#define INT_ADC1SS0_TM4C123 64 // ADC1 Sequence 0
+#define INT_ADC1SS1_TM4C123 65 // ADC1 Sequence 1
+#define INT_ADC1SS2_TM4C123 66 // ADC1 Sequence 2
+#define INT_ADC1SS3_TM4C123 67 // ADC1 Sequence 3
+#define INT_GPIOJ_TM4C123 70 // GPIO Port J
+#define INT_GPIOK_TM4C123 71 // GPIO Port K
+#define INT_GPIOL_TM4C123 72 // GPIO Port L
+#define INT_SSI2_TM4C123 73 // SSI2
+#define INT_SSI3_TM4C123 74 // SSI3
+#define INT_UART3_TM4C123 75 // UART3
+#define INT_UART4_TM4C123 76 // UART4
+#define INT_UART5_TM4C123 77 // UART5
+#define INT_UART6_TM4C123 78 // UART6
+#define INT_UART7_TM4C123 79 // UART7
+#define INT_I2C2_TM4C123 84 // I2C2
+#define INT_I2C3_TM4C123 85 // I2C3
+#define INT_TIMER4A_TM4C123 86 // 16/32-Bit Timer 4A
+#define INT_TIMER4B_TM4C123 87 // 16/32-Bit Timer 4B
+#define INT_TIMER5A_TM4C123 108 // 16/32-Bit Timer 5A
+#define INT_TIMER5B_TM4C123 109 // 16/32-Bit Timer 5B
+#define INT_WTIMER0A_TM4C123 110 // 32/64-Bit Timer 0A
+#define INT_WTIMER0B_TM4C123 111 // 32/64-Bit Timer 0B
+#define INT_WTIMER1A_TM4C123 112 // 32/64-Bit Timer 1A
+#define INT_WTIMER1B_TM4C123 113 // 32/64-Bit Timer 1B
+#define INT_WTIMER2A_TM4C123 114 // 32/64-Bit Timer 2A
+#define INT_WTIMER2B_TM4C123 115 // 32/64-Bit Timer 2B
+#define INT_WTIMER3A_TM4C123 116 // 32/64-Bit Timer 3A
+#define INT_WTIMER3B_TM4C123 117 // 32/64-Bit Timer 3B
+#define INT_WTIMER4A_TM4C123 118 // 32/64-Bit Timer 4A
+#define INT_WTIMER4B_TM4C123 119 // 32/64-Bit Timer 4B
+#define INT_WTIMER5A_TM4C123 120 // 32/64-Bit Timer 5A
+#define INT_WTIMER5B_TM4C123 121 // 32/64-Bit Timer 5B
+#define INT_SYSEXC_TM4C123 122 // System Exception (imprecise)
+#define INT_I2C4_TM4C123 125 // I2C4
+#define INT_I2C5_TM4C123 126 // I2C5
+#define INT_GPIOM_TM4C123 127 // GPIO Port M
+#define INT_GPION_TM4C123 128 // GPIO Port N
+#define INT_GPIOP0_TM4C123 132 // GPIO Port P (Summary or P0)
+#define INT_GPIOP1_TM4C123 133 // GPIO Port P1
+#define INT_GPIOP2_TM4C123 134 // GPIO Port P2
+#define INT_GPIOP3_TM4C123 135 // GPIO Port P3
+#define INT_GPIOP4_TM4C123 136 // GPIO Port P4
+#define INT_GPIOP5_TM4C123 137 // GPIO Port P5
+#define INT_GPIOP6_TM4C123 138 // GPIO Port P6
+#define INT_GPIOP7_TM4C123 139 // GPIO Port P7
+#define INT_GPIOQ0_TM4C123 140 // GPIO Port Q (Summary or Q0)
+#define INT_GPIOQ1_TM4C123 141 // GPIO Port Q1
+#define INT_GPIOQ2_TM4C123 142 // GPIO Port Q2
+#define INT_GPIOQ3_TM4C123 143 // GPIO Port Q3
+#define INT_GPIOQ4_TM4C123 144 // GPIO Port Q4
+#define INT_GPIOQ5_TM4C123 145 // GPIO Port Q5
+#define INT_GPIOQ6_TM4C123 146 // GPIO Port Q6
+#define INT_GPIOQ7_TM4C123 147 // GPIO Port Q7
+#define INT_PWM1_0_TM4C123 150 // PWM1 Generator 0
+#define INT_PWM1_1_TM4C123 151 // PWM1 Generator 1
+#define INT_PWM1_2_TM4C123 152 // PWM1 Generator 2
+#define INT_PWM1_3_TM4C123 153 // PWM1 Generator 3
+#define INT_PWM1_FAULT_TM4C123 154 // PWM1 Fault
+#define NUM_INTERRUPTS_TM4C123 155
+
+//*****************************************************************************
+//
+// TM4C129 Class Interrupts
+//
+//*****************************************************************************
+#define INT_GPIOA_TM4C129 16 // GPIO Port A
+#define INT_GPIOB_TM4C129 17 // GPIO Port B
+#define INT_GPIOC_TM4C129 18 // GPIO Port C
+#define INT_GPIOD_TM4C129 19 // GPIO Port D
+#define INT_GPIOE_TM4C129 20 // GPIO Port E
+#define INT_UART0_TM4C129 21 // UART0
+#define INT_UART1_TM4C129 22 // UART1
+#define INT_SSI0_TM4C129 23 // SSI0
+#define INT_I2C0_TM4C129 24 // I2C0
+#define INT_PWM0_FAULT_TM4C129 25 // PWM Fault
+#define INT_PWM0_0_TM4C129 26 // PWM Generator 0
+#define INT_PWM0_1_TM4C129 27 // PWM Generator 1
+#define INT_PWM0_2_TM4C129 28 // PWM Generator 2
+#define INT_QEI0_TM4C129 29 // QEI0
+#define INT_ADC0SS0_TM4C129 30 // ADC0 Sequence 0
+#define INT_ADC0SS1_TM4C129 31 // ADC0 Sequence 1
+#define INT_ADC0SS2_TM4C129 32 // ADC0 Sequence 2
+#define INT_ADC0SS3_TM4C129 33 // ADC0 Sequence 3
+#define INT_WATCHDOG_TM4C129 34 // Watchdog Timers 0 and 1
+#define INT_TIMER0A_TM4C129 35 // 16/32-Bit Timer 0A
+#define INT_TIMER0B_TM4C129 36 // 16/32-Bit Timer 0B
+#define INT_TIMER1A_TM4C129 37 // 16/32-Bit Timer 1A
+#define INT_TIMER1B_TM4C129 38 // 16/32-Bit Timer 1B
+#define INT_TIMER2A_TM4C129 39 // 16/32-Bit Timer 2A
+#define INT_TIMER2B_TM4C129 40 // 16/32-Bit Timer 2B
+#define INT_COMP0_TM4C129 41 // Analog Comparator 0
+#define INT_COMP1_TM4C129 42 // Analog Comparator 1
+#define INT_COMP2_TM4C129 43 // Analog Comparator 2
+#define INT_SYSCTL_TM4C129 44 // System Control
+#define INT_FLASH_TM4C129 45 // Flash Memory Control
+#define INT_GPIOF_TM4C129 46 // GPIO Port F
+#define INT_GPIOG_TM4C129 47 // GPIO Port G
+#define INT_GPIOH_TM4C129 48 // GPIO Port H
+#define INT_UART2_TM4C129 49 // UART2
+#define INT_SSI1_TM4C129 50 // SSI1
+#define INT_TIMER3A_TM4C129 51 // 16/32-Bit Timer 3A
+#define INT_TIMER3B_TM4C129 52 // 16/32-Bit Timer 3B
+#define INT_I2C1_TM4C129 53 // I2C1
+#define INT_CAN0_TM4C129 54 // CAN 0
+#define INT_CAN1_TM4C129 55 // CAN1
+#define INT_EMAC0_TM4C129 56 // Ethernet MAC
+#define INT_HIBERNATE_TM4C129 57 // HIB
+#define INT_USB0_TM4C129 58 // USB MAC
+#define INT_PWM0_3_TM4C129 59 // PWM Generator 3
+#define INT_UDMA_TM4C129 60 // uDMA 0 Software
+#define INT_UDMAERR_TM4C129 61 // uDMA 0 Error
+#define INT_ADC1SS0_TM4C129 62 // ADC1 Sequence 0
+#define INT_ADC1SS1_TM4C129 63 // ADC1 Sequence 1
+#define INT_ADC1SS2_TM4C129 64 // ADC1 Sequence 2
+#define INT_ADC1SS3_TM4C129 65 // ADC1 Sequence 3
+#define INT_EPI0_TM4C129 66 // EPI 0
+#define INT_GPIOJ_TM4C129 67 // GPIO Port J
+#define INT_GPIOK_TM4C129 68 // GPIO Port K
+#define INT_GPIOL_TM4C129 69 // GPIO Port L
+#define INT_SSI2_TM4C129 70 // SSI 2
+#define INT_SSI3_TM4C129 71 // SSI 3
+#define INT_UART3_TM4C129 72 // UART 3
+#define INT_UART4_TM4C129 73 // UART 4
+#define INT_UART5_TM4C129 74 // UART 5
+#define INT_UART6_TM4C129 75 // UART 6
+#define INT_UART7_TM4C129 76 // UART 7
+#define INT_I2C2_TM4C129 77 // I2C 2
+#define INT_I2C3_TM4C129 78 // I2C 3
+#define INT_TIMER4A_TM4C129 79 // Timer 4A
+#define INT_TIMER4B_TM4C129 80 // Timer 4B
+#define INT_TIMER5A_TM4C129 81 // Timer 5A
+#define INT_TIMER5B_TM4C129 82 // Timer 5B
+#define INT_SYSEXC_TM4C129 83 // Floating-Point Exception
+ // (imprecise)
+#define INT_I2C4_TM4C129 86 // I2C 4
+#define INT_I2C5_TM4C129 87 // I2C 5
+#define INT_GPIOM_TM4C129 88 // GPIO Port M
+#define INT_GPION_TM4C129 89 // GPIO Port N
+#define INT_TAMPER0_TM4C129 91 // Tamper
+#define INT_GPIOP0_TM4C129 92 // GPIO Port P (Summary or P0)
+#define INT_GPIOP1_TM4C129 93 // GPIO Port P1
+#define INT_GPIOP2_TM4C129 94 // GPIO Port P2
+#define INT_GPIOP3_TM4C129 95 // GPIO Port P3
+#define INT_GPIOP4_TM4C129 96 // GPIO Port P4
+#define INT_GPIOP5_TM4C129 97 // GPIO Port P5
+#define INT_GPIOP6_TM4C129 98 // GPIO Port P6
+#define INT_GPIOP7_TM4C129 99 // GPIO Port P7
+#define INT_GPIOQ0_TM4C129 100 // GPIO Port Q (Summary or Q0)
+#define INT_GPIOQ1_TM4C129 101 // GPIO Port Q1
+#define INT_GPIOQ2_TM4C129 102 // GPIO Port Q2
+#define INT_GPIOQ3_TM4C129 103 // GPIO Port Q3
+#define INT_GPIOQ4_TM4C129 104 // GPIO Port Q4
+#define INT_GPIOQ5_TM4C129 105 // GPIO Port Q5
+#define INT_GPIOQ6_TM4C129 106 // GPIO Port Q6
+#define INT_GPIOQ7_TM4C129 107 // GPIO Port Q7
+#define INT_GPIOR_TM4C129 108 // GPIO Port R
+#define INT_GPIOS_TM4C129 109 // GPIO Port S
+#define INT_SHA0_TM4C129 110 // SHA/MD5
+#define INT_AES0_TM4C129 111 // AES
+#define INT_DES0_TM4C129 112 // DES
+#define INT_LCD0_TM4C129 113 // LCD
+#define INT_TIMER6A_TM4C129 114 // 16/32-Bit Timer 6A
+#define INT_TIMER6B_TM4C129 115 // 16/32-Bit Timer 6B
+#define INT_TIMER7A_TM4C129 116 // 16/32-Bit Timer 7A
+#define INT_TIMER7B_TM4C129 117 // 16/32-Bit Timer 7B
+#define INT_I2C6_TM4C129 118 // I2C 6
+#define INT_I2C7_TM4C129 119 // I2C 7
+#define INT_ONEWIRE0_TM4C129 121 // 1-Wire
+#define INT_I2C8_TM4C129 125 // I2C 8
+#define INT_I2C9_TM4C129 126 // I2C 9
+#define INT_GPIOT_TM4C129 127 // GPIO T
+#define NUM_INTERRUPTS_TM4C129 129
+
+//*****************************************************************************
+//
+// TM4C123 Interrupt Class Definition
+//
+//*****************************************************************************
+#if defined(TARGET_IS_TM4C123_RA1) || defined(TARGET_IS_TM4C123_RA2) || \
+ defined(TARGET_IS_TM4C123_RA3) || defined(TARGET_IS_TM4C123_RB0) || \
+ defined(TARGET_IS_TM4C123_RB1) || defined(PART_TM4C1230C3PM) || \
+ defined(PART_TM4C1230D5PM) || defined(PART_TM4C1230E6PM) || \
+ defined(PART_TM4C1230H6PM) || defined(PART_TM4C1231C3PM) || \
+ defined(PART_TM4C1231D5PM) || defined(PART_TM4C1231D5PZ) || \
+ defined(PART_TM4C1231E6PM) || defined(PART_TM4C1231E6PZ) || \
+ defined(PART_TM4C1231H6PM) || defined(PART_TM4C1231H6PZ) || \
+ defined(PART_TM4C1232C3PM) || defined(PART_TM4C1232D5PM) || \
+ defined(PART_TM4C1232E6PM) || defined(PART_TM4C1232H6PM) || \
+ defined(PART_TM4C1233C3PM) || defined(PART_TM4C1233D5PM) || \
+ defined(PART_TM4C1233D5PZ) || defined(PART_TM4C1233E6PM) || \
+ defined(PART_TM4C1233E6PZ) || defined(PART_TM4C1233H6PM) || \
+ defined(PART_TM4C1233H6PZ) || defined(PART_TM4C1236D5PM) || \
+ defined(PART_TM4C1236E6PM) || defined(PART_TM4C1236H6PM) || \
+ defined(PART_TM4C1237D5PM) || defined(PART_TM4C1237D5PZ) || \
+ defined(PART_TM4C1237E6PM) || defined(PART_TM4C1237E6PZ) || \
+ defined(PART_TM4C1237H6PM) || defined(PART_TM4C1237H6PZ) || \
+ defined(PART_TM4C123AE6PM) || defined(PART_TM4C123AH6PM) || \
+ defined(PART_TM4C123BE6PM) || defined(PART_TM4C123BE6PZ) || \
+ defined(PART_TM4C123BH6PM) || defined(PART_TM4C123BH6PZ) || \
+ defined(PART_TM4C123FE6PM) || defined(PART_TM4C123FH6PM) || \
+ defined(PART_TM4C123GE6PM) || defined(PART_TM4C123GE6PZ) || \
+ defined(PART_TM4C123GH6PM) || defined(PART_TM4C123GH6PZ) || \
+ defined(PART_TM4C1231H6PGE) || defined(PART_TM4C1233H6PGE) || \
+ defined(PART_TM4C1237H6PGE) || defined(PART_TM4C123BH6PGE) || \
+ defined(PART_TM4C123BH6ZRB) || defined(PART_TM4C123GH6PGE) || \
+ defined(PART_TM4C123GH6ZRB) || defined(PART_TM4C123GH6ZXR)
+#define INT_RESOLVE(intname, class) intname##TM4C123
+
+//*****************************************************************************
+//
+// TM4C129 Interrupt Class Definition
+//
+//*****************************************************************************
+#elif defined(TARGET_IS_TM4C129_RA0) || defined(PART_TM4C1290NCPDT) || \
+ defined(PART_TM4C1290NCZAD) || defined(PART_TM4C1292NCPDT) || \
+ defined(PART_TM4C1292NCZAD) || defined(PART_TM4C1294KCPDT) || \
+ defined(PART_TM4C1294NCPDT) || defined(PART_TM4C1294NCZAD) || \
+ defined(PART_TM4C1297NCZAD) || defined(PART_TM4C1299KCZAD) || \
+ defined(PART_TM4C1299NCZAD) || defined(PART_TM4C129CNCPDT) || \
+ defined(PART_TM4C129CNCZAD) || defined(PART_TM4C129DNCPDT) || \
+ defined(PART_TM4C129DNCZAD) || defined(PART_TM4C129EKCPDT) || \
+ defined(PART_TM4C129ENCPDT) || defined(PART_TM4C129ENCZAD) || \
+ defined(PART_TM4C129LNCZAD) || defined(PART_TM4C129XKCZAD) || \
+ defined(PART_TM4C129XNCZAD)
+#define INT_RESOLVE(intname, class) intname##TM4C129
+#else
+#define INT_DEVICE_CLASS "UNKNOWN"
+#endif
+
+//*****************************************************************************
+//
+// Macros to resolve the INT_PERIPH_CLASS name to a common INT_PERIPH name.
+//
+//*****************************************************************************
+#define INT_CONCAT(intname, class) INT_RESOLVE(intname, class)
+
+//*****************************************************************************
+//
+// The following are defines for the interrupt assignments.
+//
+//*****************************************************************************
+#define INT_ADC0SS0 INT_CONCAT(INT_ADC0SS0_, INT_DEVICE_CLASS)
+#define INT_ADC0SS1 INT_CONCAT(INT_ADC0SS1_, INT_DEVICE_CLASS)
+#define INT_ADC0SS2 INT_CONCAT(INT_ADC0SS2_, INT_DEVICE_CLASS)
+#define INT_ADC0SS3 INT_CONCAT(INT_ADC0SS3_, INT_DEVICE_CLASS)
+#define INT_ADC1SS0 INT_CONCAT(INT_ADC1SS0_, INT_DEVICE_CLASS)
+#define INT_ADC1SS1 INT_CONCAT(INT_ADC1SS1_, INT_DEVICE_CLASS)
+#define INT_ADC1SS2 INT_CONCAT(INT_ADC1SS2_, INT_DEVICE_CLASS)
+#define INT_ADC1SS3 INT_CONCAT(INT_ADC1SS3_, INT_DEVICE_CLASS)
+#define INT_AES0 INT_CONCAT(INT_AES0_, INT_DEVICE_CLASS)
+#define INT_CAN0 INT_CONCAT(INT_CAN0_, INT_DEVICE_CLASS)
+#define INT_CAN1 INT_CONCAT(INT_CAN1_, INT_DEVICE_CLASS)
+#define INT_COMP0 INT_CONCAT(INT_COMP0_, INT_DEVICE_CLASS)
+#define INT_COMP1 INT_CONCAT(INT_COMP1_, INT_DEVICE_CLASS)
+#define INT_COMP2 INT_CONCAT(INT_COMP2_, INT_DEVICE_CLASS)
+#define INT_DES0 INT_CONCAT(INT_DES0_, INT_DEVICE_CLASS)
+#define INT_EMAC0 INT_CONCAT(INT_EMAC0_, INT_DEVICE_CLASS)
+#define INT_EPI0 INT_CONCAT(INT_EPI0_, INT_DEVICE_CLASS)
+#define INT_FLASH INT_CONCAT(INT_FLASH_, INT_DEVICE_CLASS)
+#define INT_GPIOA INT_CONCAT(INT_GPIOA_, INT_DEVICE_CLASS)
+#define INT_GPIOB INT_CONCAT(INT_GPIOB_, INT_DEVICE_CLASS)
+#define INT_GPIOC INT_CONCAT(INT_GPIOC_, INT_DEVICE_CLASS)
+#define INT_GPIOD INT_CONCAT(INT_GPIOD_, INT_DEVICE_CLASS)
+#define INT_GPIOE INT_CONCAT(INT_GPIOE_, INT_DEVICE_CLASS)
+#define INT_GPIOF INT_CONCAT(INT_GPIOF_, INT_DEVICE_CLASS)
+#define INT_GPIOG INT_CONCAT(INT_GPIOG_, INT_DEVICE_CLASS)
+#define INT_GPIOH INT_CONCAT(INT_GPIOH_, INT_DEVICE_CLASS)
+#define INT_GPIOJ INT_CONCAT(INT_GPIOJ_, INT_DEVICE_CLASS)
+#define INT_GPIOK INT_CONCAT(INT_GPIOK_, INT_DEVICE_CLASS)
+#define INT_GPIOL INT_CONCAT(INT_GPIOL_, INT_DEVICE_CLASS)
+#define INT_GPIOM INT_CONCAT(INT_GPIOM_, INT_DEVICE_CLASS)
+#define INT_GPION INT_CONCAT(INT_GPION_, INT_DEVICE_CLASS)
+#define INT_GPIOP0 INT_CONCAT(INT_GPIOP0_, INT_DEVICE_CLASS)
+#define INT_GPIOP1 INT_CONCAT(INT_GPIOP1_, INT_DEVICE_CLASS)
+#define INT_GPIOP2 INT_CONCAT(INT_GPIOP2_, INT_DEVICE_CLASS)
+#define INT_GPIOP3 INT_CONCAT(INT_GPIOP3_, INT_DEVICE_CLASS)
+#define INT_GPIOP4 INT_CONCAT(INT_GPIOP4_, INT_DEVICE_CLASS)
+#define INT_GPIOP5 INT_CONCAT(INT_GPIOP5_, INT_DEVICE_CLASS)
+#define INT_GPIOP6 INT_CONCAT(INT_GPIOP6_, INT_DEVICE_CLASS)
+#define INT_GPIOP7 INT_CONCAT(INT_GPIOP7_, INT_DEVICE_CLASS)
+#define INT_GPIOQ0 INT_CONCAT(INT_GPIOQ0_, INT_DEVICE_CLASS)
+#define INT_GPIOQ1 INT_CONCAT(INT_GPIOQ1_, INT_DEVICE_CLASS)
+#define INT_GPIOQ2 INT_CONCAT(INT_GPIOQ2_, INT_DEVICE_CLASS)
+#define INT_GPIOQ3 INT_CONCAT(INT_GPIOQ3_, INT_DEVICE_CLASS)
+#define INT_GPIOQ4 INT_CONCAT(INT_GPIOQ4_, INT_DEVICE_CLASS)
+#define INT_GPIOQ5 INT_CONCAT(INT_GPIOQ5_, INT_DEVICE_CLASS)
+#define INT_GPIOQ6 INT_CONCAT(INT_GPIOQ6_, INT_DEVICE_CLASS)
+#define INT_GPIOQ7 INT_CONCAT(INT_GPIOQ7_, INT_DEVICE_CLASS)
+#define INT_GPIOR INT_CONCAT(INT_GPIOR_, INT_DEVICE_CLASS)
+#define INT_GPIOS INT_CONCAT(INT_GPIOS_, INT_DEVICE_CLASS)
+#define INT_GPIOT INT_CONCAT(INT_GPIOT_, INT_DEVICE_CLASS)
+#define INT_HIBERNATE INT_CONCAT(INT_HIBERNATE_, INT_DEVICE_CLASS)
+#define INT_I2C0 INT_CONCAT(INT_I2C0_, INT_DEVICE_CLASS)
+#define INT_I2C1 INT_CONCAT(INT_I2C1_, INT_DEVICE_CLASS)
+#define INT_I2C2 INT_CONCAT(INT_I2C2_, INT_DEVICE_CLASS)
+#define INT_I2C3 INT_CONCAT(INT_I2C3_, INT_DEVICE_CLASS)
+#define INT_I2C4 INT_CONCAT(INT_I2C4_, INT_DEVICE_CLASS)
+#define INT_I2C5 INT_CONCAT(INT_I2C5_, INT_DEVICE_CLASS)
+#define INT_I2C6 INT_CONCAT(INT_I2C6_, INT_DEVICE_CLASS)
+#define INT_I2C7 INT_CONCAT(INT_I2C7_, INT_DEVICE_CLASS)
+#define INT_I2C8 INT_CONCAT(INT_I2C8_, INT_DEVICE_CLASS)
+#define INT_I2C9 INT_CONCAT(INT_I2C9_, INT_DEVICE_CLASS)
+#define INT_LCD0 INT_CONCAT(INT_LCD0_, INT_DEVICE_CLASS)
+#define INT_ONEWIRE0 INT_CONCAT(INT_ONEWIRE0_, INT_DEVICE_CLASS)
+#define INT_PWM0_0 INT_CONCAT(INT_PWM0_0_, INT_DEVICE_CLASS)
+#define INT_PWM0_1 INT_CONCAT(INT_PWM0_1_, INT_DEVICE_CLASS)
+#define INT_PWM0_2 INT_CONCAT(INT_PWM0_2_, INT_DEVICE_CLASS)
+#define INT_PWM0_3 INT_CONCAT(INT_PWM0_3_, INT_DEVICE_CLASS)
+#define INT_PWM0_FAULT INT_CONCAT(INT_PWM0_FAULT_, INT_DEVICE_CLASS)
+#define INT_PWM1_0 INT_CONCAT(INT_PWM1_0_, INT_DEVICE_CLASS)
+#define INT_PWM1_1 INT_CONCAT(INT_PWM1_1_, INT_DEVICE_CLASS)
+#define INT_PWM1_2 INT_CONCAT(INT_PWM1_2_, INT_DEVICE_CLASS)
+#define INT_PWM1_3 INT_CONCAT(INT_PWM1_3_, INT_DEVICE_CLASS)
+#define INT_PWM1_FAULT INT_CONCAT(INT_PWM1_FAULT_, INT_DEVICE_CLASS)
+#define INT_QEI0 INT_CONCAT(INT_QEI0_, INT_DEVICE_CLASS)
+#define INT_QEI1 INT_CONCAT(INT_QEI1_, INT_DEVICE_CLASS)
+#define INT_SHA0 INT_CONCAT(INT_SHA0_, INT_DEVICE_CLASS)
+#define INT_SSI0 INT_CONCAT(INT_SSI0_, INT_DEVICE_CLASS)
+#define INT_SSI1 INT_CONCAT(INT_SSI1_, INT_DEVICE_CLASS)
+#define INT_SSI2 INT_CONCAT(INT_SSI2_, INT_DEVICE_CLASS)
+#define INT_SSI3 INT_CONCAT(INT_SSI3_, INT_DEVICE_CLASS)
+#define INT_SYSCTL INT_CONCAT(INT_SYSCTL_, INT_DEVICE_CLASS)
+#define INT_SYSEXC INT_CONCAT(INT_SYSEXC_, INT_DEVICE_CLASS)
+#define INT_TAMPER0 INT_CONCAT(INT_TAMPER0_, INT_DEVICE_CLASS)
+#define INT_TIMER0A INT_CONCAT(INT_TIMER0A_, INT_DEVICE_CLASS)
+#define INT_TIMER0B INT_CONCAT(INT_TIMER0B_, INT_DEVICE_CLASS)
+#define INT_TIMER1A INT_CONCAT(INT_TIMER1A_, INT_DEVICE_CLASS)
+#define INT_TIMER1B INT_CONCAT(INT_TIMER1B_, INT_DEVICE_CLASS)
+#define INT_TIMER2A INT_CONCAT(INT_TIMER2A_, INT_DEVICE_CLASS)
+#define INT_TIMER2B INT_CONCAT(INT_TIMER2B_, INT_DEVICE_CLASS)
+#define INT_TIMER3A INT_CONCAT(INT_TIMER3A_, INT_DEVICE_CLASS)
+#define INT_TIMER3B INT_CONCAT(INT_TIMER3B_, INT_DEVICE_CLASS)
+#define INT_TIMER4A INT_CONCAT(INT_TIMER4A_, INT_DEVICE_CLASS)
+#define INT_TIMER4B INT_CONCAT(INT_TIMER4B_, INT_DEVICE_CLASS)
+#define INT_TIMER5A INT_CONCAT(INT_TIMER5A_, INT_DEVICE_CLASS)
+#define INT_TIMER5B INT_CONCAT(INT_TIMER5B_, INT_DEVICE_CLASS)
+#define INT_TIMER6A INT_CONCAT(INT_TIMER6A_, INT_DEVICE_CLASS)
+#define INT_TIMER6B INT_CONCAT(INT_TIMER6B_, INT_DEVICE_CLASS)
+#define INT_TIMER7A INT_CONCAT(INT_TIMER7A_, INT_DEVICE_CLASS)
+#define INT_TIMER7B INT_CONCAT(INT_TIMER7B_, INT_DEVICE_CLASS)
+#define INT_UART0 INT_CONCAT(INT_UART0_, INT_DEVICE_CLASS)
+#define INT_UART1 INT_CONCAT(INT_UART1_, INT_DEVICE_CLASS)
+#define INT_UART2 INT_CONCAT(INT_UART2_, INT_DEVICE_CLASS)
+#define INT_UART3 INT_CONCAT(INT_UART3_, INT_DEVICE_CLASS)
+#define INT_UART4 INT_CONCAT(INT_UART4_, INT_DEVICE_CLASS)
+#define INT_UART5 INT_CONCAT(INT_UART5_, INT_DEVICE_CLASS)
+#define INT_UART6 INT_CONCAT(INT_UART6_, INT_DEVICE_CLASS)
+#define INT_UART7 INT_CONCAT(INT_UART7_, INT_DEVICE_CLASS)
+#define INT_UDMA INT_CONCAT(INT_UDMA_, INT_DEVICE_CLASS)
+#define INT_UDMAERR INT_CONCAT(INT_UDMAERR_, INT_DEVICE_CLASS)
+#define INT_USB0 INT_CONCAT(INT_USB0_, INT_DEVICE_CLASS)
+#define INT_WATCHDOG INT_CONCAT(INT_WATCHDOG_, INT_DEVICE_CLASS)
+#define INT_WTIMER0A INT_CONCAT(INT_WTIMER0A_, INT_DEVICE_CLASS)
+#define INT_WTIMER0B INT_CONCAT(INT_WTIMER0B_, INT_DEVICE_CLASS)
+#define INT_WTIMER1A INT_CONCAT(INT_WTIMER1A_, INT_DEVICE_CLASS)
+#define INT_WTIMER1B INT_CONCAT(INT_WTIMER1B_, INT_DEVICE_CLASS)
+#define INT_WTIMER2A INT_CONCAT(INT_WTIMER2A_, INT_DEVICE_CLASS)
+#define INT_WTIMER2B INT_CONCAT(INT_WTIMER2B_, INT_DEVICE_CLASS)
+#define INT_WTIMER3A INT_CONCAT(INT_WTIMER3A_, INT_DEVICE_CLASS)
+#define INT_WTIMER3B INT_CONCAT(INT_WTIMER3B_, INT_DEVICE_CLASS)
+#define INT_WTIMER4A INT_CONCAT(INT_WTIMER4A_, INT_DEVICE_CLASS)
+#define INT_WTIMER4B INT_CONCAT(INT_WTIMER4B_, INT_DEVICE_CLASS)
+#define INT_WTIMER5A INT_CONCAT(INT_WTIMER5A_, INT_DEVICE_CLASS)
+#define INT_WTIMER5B INT_CONCAT(INT_WTIMER5B_, INT_DEVICE_CLASS)
+
+//*****************************************************************************
+//
+// The following are defines for the total number of interrupts.
+//
+//*****************************************************************************
+#define NUM_INTERRUPTS INT_CONCAT(NUM_INTERRUPTS_, INT_DEVICE_CLASS)
+
+//*****************************************************************************
+//
+// The following are defines for the total number of priority levels.
+//
+//*****************************************************************************
+#define NUM_PRIORITY 8
+#define NUM_PRIORITY_BITS 3
+
+#endif // __HW_INTS_H__
diff --git a/os/common/ext/TivaWare/inc/hw_lcd.h b/os/common/ext/TivaWare/inc/hw_lcd.h
new file mode 100644
index 0000000..f8711be
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_lcd.h
@@ -0,0 +1,575 @@
+//*****************************************************************************
+//
+// hw_lcd.h - Defines and macros used when accessing the LCD controller.
+//
+// Copyright (c) 2011-2016 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_LCD_H__
+#define __HW_LCD_H__
+
+//*****************************************************************************
+//
+// The following are defines for the LCD register offsets.
+//
+//*****************************************************************************
+#define LCD_O_PID 0x00000000 // LCD PID Register Format
+#define LCD_O_CTL 0x00000004 // LCD Control
+#define LCD_O_LIDDCTL 0x0000000C // LCD LIDD Control
+#define LCD_O_LIDDCS0CFG 0x00000010 // LCD LIDD CS0 Configuration
+#define LCD_O_LIDDCS0ADDR 0x00000014 // LIDD CS0 Read/Write Address
+#define LCD_O_LIDDCS0DATA 0x00000018 // LIDD CS0 Data Read/Write
+ // Initiation
+#define LCD_O_LIDDCS1CFG 0x0000001C // LIDD CS1 Configuration
+#define LCD_O_LIDDCS1ADDR 0x00000020 // LIDD CS1 Address Read/Write
+ // Initiation
+#define LCD_O_LIDDCS1DATA 0x00000024 // LIDD CS1 Data Read/Write
+ // Initiation
+#define LCD_O_RASTRCTL 0x00000028 // LCD Raster Control
+#define LCD_O_RASTRTIM0 0x0000002C // LCD Raster Timing 0
+#define LCD_O_RASTRTIM1 0x00000030 // LCD Raster Timing 1
+#define LCD_O_RASTRTIM2 0x00000034 // LCD Raster Timing 2
+#define LCD_O_RASTRSUBP1 0x00000038 // LCD Raster Subpanel Display 1
+#define LCD_O_RASTRSUBP2 0x0000003C // LCD Raster Subpanel Display 2
+#define LCD_O_DMACTL 0x00000040 // LCD DMA Control
+#define LCD_O_DMABAFB0 0x00000044 // LCD DMA Frame Buffer 0 Base
+ // Address
+#define LCD_O_DMACAFB0 0x00000048 // LCD DMA Frame Buffer 0 Ceiling
+ // Address
+#define LCD_O_DMABAFB1 0x0000004C // LCD DMA Frame Buffer 1 Base
+ // Address
+#define LCD_O_DMACAFB1 0x00000050 // LCD DMA Frame Buffer 1 Ceiling
+ // Address
+#define LCD_O_SYSCFG 0x00000054 // LCD System Configuration
+ // Register
+#define LCD_O_RISSET 0x00000058 // LCD Interrupt Raw Status and Set
+ // Register
+#define LCD_O_MISCLR 0x0000005C // LCD Interrupt Status and Clear
+#define LCD_O_IM 0x00000060 // LCD Interrupt Mask
+#define LCD_O_IENC 0x00000064 // LCD Interrupt Enable Clear
+#define LCD_O_CLKEN 0x0000006C // LCD Clock Enable
+#define LCD_O_CLKRESET 0x00000070 // LCD Clock Resets
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_PID register.
+//
+//*****************************************************************************
+#define LCD_PID_MAJOR_M 0x00000700 // Major Release Number
+#define LCD_PID_MINOR_M 0x0000003F // Minor Release Number
+#define LCD_PID_MAJOR_S 8
+#define LCD_PID_MINOR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_CTL register.
+//
+//*****************************************************************************
+#define LCD_CTL_CLKDIV_M 0x0000FF00 // Clock Divisor
+#define LCD_CTL_UFLOWRST 0x00000002 // Underflow Restart
+#define LCD_CTL_LCDMODE 0x00000001 // LCD Mode Select
+#define LCD_CTL_CLKDIV_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_LIDDCTL register.
+//
+//*****************************************************************************
+#define LCD_LIDDCTL_DMACS 0x00000200 // CS0/CS1 Select for LIDD DMA
+ // Writes
+#define LCD_LIDDCTL_DMAEN 0x00000100 // LIDD DMA Enable
+#define LCD_LIDDCTL_CS1E1 0x00000080 // Chip Select 1 (CS1)/Enable 1(E1)
+ // Polarity Control
+#define LCD_LIDDCTL_CS0E0 0x00000040 // Chip Select 0 (CS0)/Enable 0
+ // (E0) Polarity Control
+#define LCD_LIDDCTL_WRDIRINV 0x00000020 // Write Strobe (WR) /Direction
+ // (DIR) Polarity Control
+#define LCD_LIDDCTL_RDEN 0x00000010 // Read Strobe (RD) /Direct Enable
+ // (EN) Polarity Control
+#define LCD_LIDDCTL_ALE 0x00000008 // Address Latch Enable (ALE)
+ // Polarity Control
+#define LCD_LIDDCTL_MODE_M 0x00000007 // LIDD Mode Select
+#define LCD_LIDDCTL_MODE_SYNCM68 \
+ 0x00000000 // Synchronous Motorola 6800 Mode
+#define LCD_LIDDCTL_MODE_ASYNCM68 \
+ 0x00000001 // Asynchronous Motorola 6800 Mode
+#define LCD_LIDDCTL_MODE_SYNCM80 \
+ 0x00000002 // Synchronous Intel 8080 mode
+#define LCD_LIDDCTL_MODE_ASYNCM80 \
+ 0x00000003 // Asynchronous Intel 8080 mode
+#define LCD_LIDDCTL_MODE_ASYNCHIT \
+ 0x00000004 // Asynchronous Hitachi mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_LIDDCS0CFG
+// register.
+//
+//*****************************************************************************
+#define LCD_LIDDCS0CFG_WRSU_M 0xF8000000 // Write Strobe (WR) Set-Up Cycles
+#define LCD_LIDDCS0CFG_WRDUR_M 0x07E00000 // Write Strobe (WR) Duration
+ // Cycles
+#define LCD_LIDDCS0CFG_WRHOLD_M 0x001E0000 // Write Strobe (WR) Hold cycles
+#define LCD_LIDDCS0CFG_RDSU_M 0x0001F000 // Read Strobe (RD) Set-Up cycles
+#define LCD_LIDDCS0CFG_RDDUR_M 0x00000FC0 // Read Strobe (RD) Duration cycles
+#define LCD_LIDDCS0CFG_RDHOLD_M 0x0000003C // Read Strobe (RD) Hold cycles
+#define LCD_LIDDCS0CFG_GAP_M 0x00000003 // Field value defines the number
+ // of LCDMCLK cycles (GAP +1)
+ // between the end of one CS0
+ // (LCDAC) device access and the
+ // start of another CS0 (LCDAC)
+ // device access unless the two
+ // accesses are both reads
+#define LCD_LIDDCS0CFG_WRSU_S 27
+#define LCD_LIDDCS0CFG_WRDUR_S 21
+#define LCD_LIDDCS0CFG_WRHOLD_S 17
+#define LCD_LIDDCS0CFG_RDSU_S 12
+#define LCD_LIDDCS0CFG_RDDUR_S 6
+#define LCD_LIDDCS0CFG_RDHOLD_S 2
+#define LCD_LIDDCS0CFG_GAP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_LIDDCS0ADDR
+// register.
+//
+//*****************************************************************************
+#define LCD_LIDDCS0ADDR_CS0ADDR_M \
+ 0x0000FFFF // LCD Address
+#define LCD_LIDDCS0ADDR_CS0ADDR_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_LIDDCS0DATA
+// register.
+//
+//*****************************************************************************
+#define LCD_LIDDCS0DATA_CS0DATA_M \
+ 0x0000FFFF // LCD Data Read/Write
+#define LCD_LIDDCS0DATA_CS0DATA_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_LIDDCS1CFG
+// register.
+//
+//*****************************************************************************
+#define LCD_LIDDCS1CFG_WRSU_M 0xF8000000 // Write Strobe (WR) Set-Up Cycles
+#define LCD_LIDDCS1CFG_WRDUR_M 0x07E00000 // Write Strobe (WR) Duration
+ // Cycles
+#define LCD_LIDDCS1CFG_WRHOLD_M 0x001E0000 // Write Strobe (WR) Hold cycles
+#define LCD_LIDDCS1CFG_RDSU_M 0x0001F000 // Read Strobe (RD) Set-Up cycles
+#define LCD_LIDDCS1CFG_RDDUR_M 0x00000FC0 // Read Strobe (RD) Duration cycles
+#define LCD_LIDDCS1CFG_RDHOLD_M 0x0000003C // Read Strobe (RD) Hold cycles
+#define LCD_LIDDCS1CFG_GAP_M 0x00000003 // Field value defines the number
+ // of LCDMCLK cycles (GAP + 1)
+ // between the end of one CS1
+ // (LCDAC) device access and the
+ // start of another CS0 (LCDAC)
+ // device access unless the two
+ // accesses are both reads
+#define LCD_LIDDCS1CFG_WRSU_S 27
+#define LCD_LIDDCS1CFG_WRDUR_S 21
+#define LCD_LIDDCS1CFG_WRHOLD_S 17
+#define LCD_LIDDCS1CFG_RDSU_S 12
+#define LCD_LIDDCS1CFG_RDDUR_S 6
+#define LCD_LIDDCS1CFG_RDHOLD_S 2
+#define LCD_LIDDCS1CFG_GAP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_LIDDCS1ADDR
+// register.
+//
+//*****************************************************************************
+#define LCD_LIDDCS1ADDR_CS1ADDR_M \
+ 0x0000FFFF // LCD Address Bus
+#define LCD_LIDDCS1ADDR_CS1ADDR_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_LIDDCS1DATA
+// register.
+//
+//*****************************************************************************
+#define LCD_LIDDCS1DATA_CS0DATA_M \
+ 0x0000FFFF // LCD Data Read/Write Initiation
+#define LCD_LIDDCS1DATA_CS0DATA_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_RASTRCTL register.
+//
+//*****************************************************************************
+#define LCD_RASTRCTL_TFT24UPCK 0x04000000 // 24-bit TFT Mode Packing
+#define LCD_RASTRCTL_TFT24 0x02000000 // 24-Bit TFT Mode
+#define LCD_RASTRCTL_FRMBUFSZ 0x01000000 // Frame Buffer Select
+#define LCD_RASTRCTL_TFTMAP 0x00800000 // TFT Mode Alternate Signal
+ // Mapping for Palettized
+ // Framebuffer
+#define LCD_RASTRCTL_NIBMODE 0x00400000 // Nibble Mode
+#define LCD_RASTRCTL_PALMODE_M 0x00300000 // Pallette Loading Mode
+#define LCD_RASTRCTL_PALMODE_PALDAT \
+ 0x00000000 // Palette and data loading, reset
+ // value
+#define LCD_RASTRCTL_PALMODE_PAL \
+ 0x00100000 // Palette loading only
+#define LCD_RASTRCTL_PALMODE_DAT \
+ 0x00200000 // Data loading only
+#define LCD_RASTRCTL_REQDLY_M 0x000FF000 // Palette Loading Delay
+#define LCD_RASTRCTL_MONO8B 0x00000200 // Mono 8-Bit
+#define LCD_RASTRCTL_RDORDER 0x00000100 // Raster Data Order Select
+#define LCD_RASTRCTL_LCDTFT 0x00000080 // LCD TFT
+#define LCD_RASTRCTL_LCDBW 0x00000002 // LCD Monochrome
+#define LCD_RASTRCTL_LCDEN 0x00000001 // LCD Controller Enable for Raster
+ // Operations
+#define LCD_RASTRCTL_REQDLY_S 12
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_RASTRTIM0
+// register.
+//
+//*****************************************************************************
+#define LCD_RASTRTIM0_HBP_M 0xFF000000 // Horizontal Back Porch Lowbits
+#define LCD_RASTRTIM0_HFP_M 0x00FF0000 // Horizontal Front Porch Lowbits
+#define LCD_RASTRTIM0_HSW_M 0x0000FC00 // Horizontal Sync Pulse Width
+ // Lowbits
+#define LCD_RASTRTIM0_PPL_M 0x000003F0 // Pixels-per-line LSB[9:4]
+#define LCD_RASTRTIM0_MSBPPL 0x00000008 // Pixels-per-line MSB[10]
+#define LCD_RASTRTIM0_HBP_S 24
+#define LCD_RASTRTIM0_HFP_S 16
+#define LCD_RASTRTIM0_HSW_S 10
+#define LCD_RASTRTIM0_PPL_S 4
+#define LCD_RASTRTIM0_MSBPPL_S 3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_RASTRTIM1
+// register.
+//
+//*****************************************************************************
+#define LCD_RASTRTIM1_VBP_M 0xFF000000 // Vertical Back Porch
+#define LCD_RASTRTIM1_VFP_M 0x00FF0000 // Vertical Front Porch
+#define LCD_RASTRTIM1_VSW_M 0x0000FC00 // Vertical Sync Width Pulse
+#define LCD_RASTRTIM1_LPP_M 0x000003FF // Lines Per Panel
+#define LCD_RASTRTIM1_VBP_S 24
+#define LCD_RASTRTIM1_VFP_S 16
+#define LCD_RASTRTIM1_VSW_S 10
+#define LCD_RASTRTIM1_LPP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_RASTRTIM2
+// register.
+//
+//*****************************************************************************
+#define LCD_RASTRTIM2_HSW_M 0x78000000 // Bits 9:6 of the horizontal sync
+ // width field
+#define LCD_RASTRTIM2_MSBLPP 0x04000000 // MSB of Lines Per Panel
+#define LCD_RASTRTIM2_PXLCLKCTL 0x02000000 // Hsync/Vsync Pixel Clock Control
+ // On/Off
+#define LCD_RASTRTIM2_PSYNCRF 0x01000000 // Program HSYNC/VSYNC Rise or Fall
+#define LCD_RASTRTIM2_INVOE 0x00800000 // Invert Output Enable
+#define LCD_RASTRTIM2_INVPXLCLK 0x00400000 // Invert Pixel Clock
+#define LCD_RASTRTIM2_IHS 0x00200000 // Invert Hysync
+#define LCD_RASTRTIM2_IVS 0x00100000 // Invert Vsync
+#define LCD_RASTRTIM2_ACBI_M 0x000F0000 // AC Bias Pins Transitions per
+ // Interrupt
+#define LCD_RASTRTIM2_ACBF_M 0x0000FF00 // AC Bias Pin Frequency
+#define LCD_RASTRTIM2_MSBHBP_M 0x00000030 // Bits 9:8 of the horizontal back
+ // porch field
+#define LCD_RASTRTIM2_MSBHFP_M 0x00000003 // Bits 9:8 of the horizontal front
+ // porch field
+#define LCD_RASTRTIM2_HSW_S 27
+#define LCD_RASTRTIM2_MSBLPP_S 26
+#define LCD_RASTRTIM2_ACBI_S 16
+#define LCD_RASTRTIM2_ACBF_S 8
+#define LCD_RASTRTIM2_MSBHBP_S 4
+#define LCD_RASTRTIM2_MSBHFP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_RASTRSUBP1
+// register.
+//
+//*****************************************************************************
+#define LCD_RASTRSUBP1_SPEN 0x80000000 // Sub Panel Enable
+#define LCD_RASTRSUBP1_HOLS 0x20000000 // High or Low Signal
+#define LCD_RASTRSUBP1_LPPT_M 0x03FF0000 // Line Per Panel Threshold
+#define LCD_RASTRSUBP1_DPDLSB_M 0x0000FFFF // Default Pixel Data LSB[15:0]
+#define LCD_RASTRSUBP1_LPPT_S 16
+#define LCD_RASTRSUBP1_DPDLSB_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_RASTRSUBP2
+// register.
+//
+//*****************************************************************************
+#define LCD_RASTRSUBP2_LPPTMSB 0x00000100 // Lines Per Panel Threshold Bit 10
+#define LCD_RASTRSUBP2_DPDMSB_M 0x000000FF // Default Pixel Data MSB [23:16]
+#define LCD_RASTRSUBP2_DPDMSB_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_DMACTL register.
+//
+//*****************************************************************************
+#define LCD_DMACTL_FIFORDY_M 0x00000700 // DMA FIFO threshold
+#define LCD_DMACTL_FIFORDY_8 0x00000000 // 8 words
+#define LCD_DMACTL_FIFORDY_16 0x00000100 // 16 words
+#define LCD_DMACTL_FIFORDY_32 0x00000200 // 32 words
+#define LCD_DMACTL_FIFORDY_64 0x00000300 // 64 words
+#define LCD_DMACTL_FIFORDY_128 0x00000400 // 128 words
+#define LCD_DMACTL_FIFORDY_256 0x00000500 // 256 words
+#define LCD_DMACTL_FIFORDY_512 0x00000600 // 512 words
+#define LCD_DMACTL_BURSTSZ_M 0x00000070 // Burst Size setting for DMA
+ // transfers (all DMA transfers are
+ // 32 bits wide):
+#define LCD_DMACTL_BURSTSZ_4 0x00000020 // burst size of 4
+#define LCD_DMACTL_BURSTSZ_8 0x00000030 // burst size of 8
+#define LCD_DMACTL_BURSTSZ_16 0x00000040 // burst size of 16
+#define LCD_DMACTL_BYTESWAP 0x00000008 // This bit controls the bytelane
+ // ordering of the data on the
+ // output of the DMA module
+#define LCD_DMACTL_BIGDEND 0x00000002 // Big Endian Enable
+#define LCD_DMACTL_FMODE 0x00000001 // Frame Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_DMABAFB0 register.
+//
+//*****************************************************************************
+#define LCD_DMABAFB0_FB0BA_M 0xFFFFFFFC // Frame Buffer 0 Base Address
+ // pointer
+#define LCD_DMABAFB0_FB0BA_S 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_DMACAFB0 register.
+//
+//*****************************************************************************
+#define LCD_DMACAFB0_FB0CA_M 0xFFFFFFFC // Frame Buffer 0 Ceiling Address
+ // pointer
+#define LCD_DMACAFB0_FB0CA_S 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_DMABAFB1 register.
+//
+//*****************************************************************************
+#define LCD_DMABAFB1_FB1BA_M 0xFFFFFFFC // Frame Buffer 1 Base Address
+ // pointer
+#define LCD_DMABAFB1_FB1BA_S 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_DMACAFB1 register.
+//
+//*****************************************************************************
+#define LCD_DMACAFB1_FB1CA_M 0xFFFFFFFC // Frame Buffer 1 Ceiling Address
+ // pointer
+#define LCD_DMACAFB1_FB1CA_S 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_SYSCFG register.
+//
+//*****************************************************************************
+#define LCD_SYSCFG_STDBY_M 0x00000030 // Standby Mode
+#define LCD_SYSCFG_STDBY_FORCE 0x00000000 // Force-standby mode: local
+ // initiator is unconditionally
+ // placed in standby state. Backup
+ // mode, for debug only
+#define LCD_SYSCFG_STDBY_NONE 0x00000010 // No-standby mode: local initiator
+ // is unconditionally placed out of
+ // standby state. Backup mode, for
+ // debug only
+#define LCD_SYSCFG_STDBY_SMART 0x00000020 // Smart-standby mode: local
+ // initiator standby status depends
+ // on local conditions, that is,
+ // the module's functional
+ // requirement from the initiator.
+ // IP module shall not generate
+ // (initiator-related) wakeup
+ // events
+#define LCD_SYSCFG_IDLEMODE_M 0x0000000C // Idle Mode
+#define LCD_SYSCFG_IDLEMODE_FORCE \
+ 0x00000000 // Force-idle mode: local target's
+ // idle state follows
+ // (acknowledges) the system's idle
+ // requests unconditionally, that
+ // is, regardless of the IP
+ // module's internal requirements.
+ // Backup mode, for debug only
+#define LCD_SYSCFG_IDLEMODE_NONE \
+ 0x00000004 // No-idle mode: local target never
+ // enters idle state. Backup mode,
+ // for debug only
+#define LCD_SYSCFG_IDLEMODE_SMART \
+ 0x00000008 // Smart-idle mode: local target's
+ // idle state eventually follows
+ // (acknowledges) the system's idle
+ // requests, depending on the IP
+ // module's internal requirements.
+ // IP module shall not generate
+ // (IRQ- or DMA-requestrelated)
+ // wakeup events
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_RISSET register.
+//
+//*****************************************************************************
+#define LCD_RISSET_EOF1 0x00000200 // DMA End-of-Frame 1 Raw Interrupt
+ // Status and Set
+#define LCD_RISSET_EOF0 0x00000100 // DMA End-of-Frame 0 Raw Interrupt
+ // Status and Set
+#define LCD_RISSET_PALLOAD 0x00000040 // DMA Palette Loaded Raw Interrupt
+ // Status and Set
+#define LCD_RISSET_FIFOU 0x00000020 // DMA FIFO Underflow Raw Interrupt
+ // Status and Set
+#define LCD_RISSET_ACBS 0x00000008 // AC Bias Count Raw Interrupt
+ // Status and Set
+#define LCD_RISSET_SYNCS 0x00000004 // Frame Synchronization Lost Raw
+ // Interrupt Status and Set
+#define LCD_RISSET_RRASTRDONE 0x00000002 // Raster Mode Frame Done interrupt
+#define LCD_RISSET_DONE 0x00000001 // Raster or LIDD Frame Done
+ // (shared, depends on whether
+ // Raster or LIDD mode enabled) Raw
+ // Interrupt Status and Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_MISCLR register.
+//
+//*****************************************************************************
+#define LCD_MISCLR_EOF1 0x00000200 // DMA End-of-Frame 1 Enabled
+ // Interrupt and Clear
+#define LCD_MISCLR_EOF0 0x00000100 // DMA End-of-Frame 0 Raw Interrupt
+ // and Clear
+#define LCD_MISCLR_PALLOAD 0x00000040 // DMA Palette Loaded Enabled
+ // Interrupt and Clear
+#define LCD_MISCLR_FIFOU 0x00000020 // DMA FIFO Underflow Enabled
+ // Interrupt and Clear
+#define LCD_MISCLR_ACBS 0x00000008 // AC Bias Count Enabled Interrupt
+ // and Clear
+#define LCD_MISCLR_SYNCS 0x00000004 // Frame Synchronization Lost
+ // Enabled Interrupt and Clear
+#define LCD_MISCLR_RRASTRDONE 0x00000002 // Raster Mode Frame Done interrupt
+#define LCD_MISCLR_DONE 0x00000001 // Raster or LIDD Frame Done
+ // (shared, depends on whether
+ // Raster or LIDD mode enabled)
+ // Enabled Interrupt and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_IM register.
+//
+//*****************************************************************************
+#define LCD_IM_EOF1 0x00000200 // DMA End-of-Frame 1 Interrupt
+ // Enable Set
+#define LCD_IM_EOF0 0x00000100 // DMA End-of-Frame 0 Interrupt
+ // Enable Set
+#define LCD_IM_PALLOAD 0x00000040 // DMA Palette Loaded Interrupt
+ // Enable Set
+#define LCD_IM_FIFOU 0x00000020 // DMA FIFO Underflow Interrupt
+ // Enable Set
+#define LCD_IM_ACBS 0x00000008 // AC Bias Count Interrupt Enable
+ // Set
+#define LCD_IM_SYNCS 0x00000004 // Frame Synchronization Lost
+ // Interrupt Enable Set
+#define LCD_IM_RRASTRDONE 0x00000002 // Raster Mode Frame Done Interrupt
+ // Enable Set
+#define LCD_IM_DONE 0x00000001 // Raster or LIDD Frame Done
+ // (shared, depends on whether
+ // Raster or LIDD mode enabled)
+ // Interrupt Enable Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_IENC register.
+//
+//*****************************************************************************
+#define LCD_IENC_EOF1 0x00000200 // DMA End-of-Frame 1 Interrupt
+ // Enable Clear
+#define LCD_IENC_EOF0 0x00000100 // DMA End-of-Frame 0 Interrupt
+ // Enable Clear
+#define LCD_IENC_PALLOAD 0x00000040 // DMA Palette Loaded Interrupt
+ // Enable Clear
+#define LCD_IENC_FIFOU 0x00000020 // DMA FIFO Underflow Interrupt
+ // Enable Clear
+#define LCD_IENC_ACBS 0x00000008 // AC Bias Count Interrupt Enable
+ // Clear
+#define LCD_IENC_SYNCS 0x00000004 // Frame Synchronization Lost
+ // Interrupt Enable Clear
+#define LCD_IENC_RRASTRDONE 0x00000002 // Raster Mode Frame Done Interrupt
+ // Enable Clear
+#define LCD_IENC_DONE 0x00000001 // Raster or LIDD Frame Done
+ // (shared, depends on whether
+ // Raster or LIDD mode enabled)
+ // Interrupt Enable Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_CLKEN register.
+//
+//*****************************************************************************
+#define LCD_CLKEN_DMA 0x00000004 // DMA Clock Enable
+#define LCD_CLKEN_LIDD 0x00000002 // LIDD Submodule Clock Enable
+#define LCD_CLKEN_CORE 0x00000001 // LCD Core Clock Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the LCD_O_CLKRESET register.
+//
+//*****************************************************************************
+#define LCD_CLKRESET_MAIN 0x00000008 // Software Reset for the entire
+ // LCD module
+#define LCD_CLKRESET_DMA 0x00000004 // Software Reset for the DMA
+ // submodule
+#define LCD_CLKRESET_LIDD 0x00000002 // Software Reset for the LIDD
+ // submodule (character displays)
+#define LCD_CLKRESET_CORE 0x00000001 // Software Reset for the Core,
+ // which encompasses the Raster
+ // Active Matrix and Passive Matrix
+ // logic
+
+#endif // __HW_LCD_H__
diff --git a/os/common/ext/TivaWare/inc/hw_memmap.h b/os/common/ext/TivaWare/inc/hw_memmap.h
new file mode 100644
index 0000000..dafd4f7
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_memmap.h
@@ -0,0 +1,151 @@
+//*****************************************************************************
+//
+// hw_memmap.h - Macros defining the memory map of the device.
+//
+// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_MEMMAP_H__
+#define __HW_MEMMAP_H__
+
+//*****************************************************************************
+//
+// The following are defines for the base address of the memories and
+// peripherals.
+//
+//*****************************************************************************
+#define FLASH_BASE 0x00000000 // FLASH memory
+#define SRAM_BASE 0x20000000 // SRAM memory
+#define WATCHDOG0_BASE 0x40000000 // Watchdog0
+#define WATCHDOG1_BASE 0x40001000 // Watchdog1
+#define GPIO_PORTA_BASE 0x40004000 // GPIO Port A
+#define GPIO_PORTB_BASE 0x40005000 // GPIO Port B
+#define GPIO_PORTC_BASE 0x40006000 // GPIO Port C
+#define GPIO_PORTD_BASE 0x40007000 // GPIO Port D
+#define SSI0_BASE 0x40008000 // SSI0
+#define SSI1_BASE 0x40009000 // SSI1
+#define SSI2_BASE 0x4000A000 // SSI2
+#define SSI3_BASE 0x4000B000 // SSI3
+#define UART0_BASE 0x4000C000 // UART0
+#define UART1_BASE 0x4000D000 // UART1
+#define UART2_BASE 0x4000E000 // UART2
+#define UART3_BASE 0x4000F000 // UART3
+#define UART4_BASE 0x40010000 // UART4
+#define UART5_BASE 0x40011000 // UART5
+#define UART6_BASE 0x40012000 // UART6
+#define UART7_BASE 0x40013000 // UART7
+#define I2C0_BASE 0x40020000 // I2C0
+#define I2C1_BASE 0x40021000 // I2C1
+#define I2C2_BASE 0x40022000 // I2C2
+#define I2C3_BASE 0x40023000 // I2C3
+#define GPIO_PORTE_BASE 0x40024000 // GPIO Port E
+#define GPIO_PORTF_BASE 0x40025000 // GPIO Port F
+#define GPIO_PORTG_BASE 0x40026000 // GPIO Port G
+#define GPIO_PORTH_BASE 0x40027000 // GPIO Port H
+#define PWM0_BASE 0x40028000 // Pulse Width Modulator (PWM)
+#define PWM1_BASE 0x40029000 // Pulse Width Modulator (PWM)
+#define QEI0_BASE 0x4002C000 // QEI0
+#define QEI1_BASE 0x4002D000 // QEI1
+#define TIMER0_BASE 0x40030000 // Timer0
+#define TIMER1_BASE 0x40031000 // Timer1
+#define TIMER2_BASE 0x40032000 // Timer2
+#define TIMER3_BASE 0x40033000 // Timer3
+#define TIMER4_BASE 0x40034000 // Timer4
+#define TIMER5_BASE 0x40035000 // Timer5
+#define WTIMER0_BASE 0x40036000 // Wide Timer0
+#define WTIMER1_BASE 0x40037000 // Wide Timer1
+#define ADC0_BASE 0x40038000 // ADC0
+#define ADC1_BASE 0x40039000 // ADC1
+#define COMP_BASE 0x4003C000 // Analog comparators
+#define GPIO_PORTJ_BASE 0x4003D000 // GPIO Port J
+#define CAN0_BASE 0x40040000 // CAN0
+#define CAN1_BASE 0x40041000 // CAN1
+#define WTIMER2_BASE 0x4004C000 // Wide Timer2
+#define WTIMER3_BASE 0x4004D000 // Wide Timer3
+#define WTIMER4_BASE 0x4004E000 // Wide Timer4
+#define WTIMER5_BASE 0x4004F000 // Wide Timer5
+#define USB0_BASE 0x40050000 // USB 0 Controller
+#define GPIO_PORTA_AHB_BASE 0x40058000 // GPIO Port A (high speed)
+#define GPIO_PORTB_AHB_BASE 0x40059000 // GPIO Port B (high speed)
+#define GPIO_PORTC_AHB_BASE 0x4005A000 // GPIO Port C (high speed)
+#define GPIO_PORTD_AHB_BASE 0x4005B000 // GPIO Port D (high speed)
+#define GPIO_PORTE_AHB_BASE 0x4005C000 // GPIO Port E (high speed)
+#define GPIO_PORTF_AHB_BASE 0x4005D000 // GPIO Port F (high speed)
+#define GPIO_PORTG_AHB_BASE 0x4005E000 // GPIO Port G (high speed)
+#define GPIO_PORTH_AHB_BASE 0x4005F000 // GPIO Port H (high speed)
+#define GPIO_PORTJ_AHB_BASE 0x40060000 // GPIO Port J (high speed)
+#define GPIO_PORTK_BASE 0x40061000 // GPIO Port K
+#define GPIO_PORTL_BASE 0x40062000 // GPIO Port L
+#define GPIO_PORTM_BASE 0x40063000 // GPIO Port M
+#define GPIO_PORTN_BASE 0x40064000 // GPIO Port N
+#define GPIO_PORTP_BASE 0x40065000 // GPIO Port P
+#define GPIO_PORTQ_BASE 0x40066000 // GPIO Port Q
+#define GPIO_PORTR_BASE 0x40067000 // General-Purpose Input/Outputs
+ // (GPIOs)
+#define GPIO_PORTS_BASE 0x40068000 // General-Purpose Input/Outputs
+ // (GPIOs)
+#define GPIO_PORTT_BASE 0x40069000 // General-Purpose Input/Outputs
+ // (GPIOs)
+#define EEPROM_BASE 0x400AF000 // EEPROM memory
+#define ONEWIRE0_BASE 0x400B6000 // 1-Wire Master Module
+#define I2C8_BASE 0x400B8000 // I2C8
+#define I2C9_BASE 0x400B9000 // I2C9
+#define I2C4_BASE 0x400C0000 // I2C4
+#define I2C5_BASE 0x400C1000 // I2C5
+#define I2C6_BASE 0x400C2000 // I2C6
+#define I2C7_BASE 0x400C3000 // I2C7
+#define EPI0_BASE 0x400D0000 // EPI0
+#define TIMER6_BASE 0x400E0000 // General-Purpose Timers
+#define TIMER7_BASE 0x400E1000 // General-Purpose Timers
+#define EMAC0_BASE 0x400EC000 // Ethernet Controller
+#define SYSEXC_BASE 0x400F9000 // System Exception Module
+#define HIB_BASE 0x400FC000 // Hibernation Module
+#define FLASH_CTRL_BASE 0x400FD000 // FLASH Controller
+#define SYSCTL_BASE 0x400FE000 // System Control
+#define UDMA_BASE 0x400FF000 // uDMA Controller
+#define CCM0_BASE 0x44030000 // Cyclical Redundancy Check (CRC)
+#define SHAMD5_BASE 0x44034000 // SHA/MD5 Accelerator
+#define AES_BASE 0x44036000 // Advance Encryption
+ // Hardware-Accelerated Module
+#define DES_BASE 0x44038000 // Data Encryption Standard
+ // Accelerator (DES)
+#define LCD0_BASE 0x44050000 // LCD Controller
+// #define ITM_BASE 0xE0000000 // Instrumentation Trace Macrocell
+// #define DWT_BASE 0xE0001000 // Data Watchpoint and Trace
+// #define FPB_BASE 0xE0002000 // FLASH Patch and Breakpoint
+// #define NVIC_BASE 0xE000E000 // Nested Vectored Interrupt Ctrl
+// #define TPIU_BASE 0xE0040000 // Trace Port Interface Unit
+
+#endif // __HW_MEMMAP_H__
diff --git a/os/common/ext/TivaWare/inc/hw_nvic.h b/os/common/ext/TivaWare/inc/hw_nvic.h
new file mode 100644
index 0000000..c7b3568
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_nvic.h
@@ -0,0 +1,1414 @@
+//*****************************************************************************
+//
+// hw_nvic.h - Macros used when accessing the NVIC hardware.
+//
+// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_NVIC_H__
+#define __HW_NVIC_H__
+
+//*****************************************************************************
+//
+// The following are defines for the NVIC register addresses.
+//
+//*****************************************************************************
+#define NVIC_ACTLR 0xE000E008 // Auxiliary Control
+#define NVIC_ST_CTRL 0xE000E010 // SysTick Control and Status
+ // Register
+#define NVIC_ST_RELOAD 0xE000E014 // SysTick Reload Value Register
+#define NVIC_ST_CURRENT 0xE000E018 // SysTick Current Value Register
+#define NVIC_EN0 0xE000E100 // Interrupt 0-31 Set Enable
+#define NVIC_EN1 0xE000E104 // Interrupt 32-63 Set Enable
+#define NVIC_EN2 0xE000E108 // Interrupt 64-95 Set Enable
+#define NVIC_EN3 0xE000E10C // Interrupt 96-127 Set Enable
+#define NVIC_EN4 0xE000E110 // Interrupt 128-159 Set Enable
+#define NVIC_DIS0 0xE000E180 // Interrupt 0-31 Clear Enable
+#define NVIC_DIS1 0xE000E184 // Interrupt 32-63 Clear Enable
+#define NVIC_DIS2 0xE000E188 // Interrupt 64-95 Clear Enable
+#define NVIC_DIS3 0xE000E18C // Interrupt 96-127 Clear Enable
+#define NVIC_DIS4 0xE000E190 // Interrupt 128-159 Clear Enable
+#define NVIC_PEND0 0xE000E200 // Interrupt 0-31 Set Pending
+#define NVIC_PEND1 0xE000E204 // Interrupt 32-63 Set Pending
+#define NVIC_PEND2 0xE000E208 // Interrupt 64-95 Set Pending
+#define NVIC_PEND3 0xE000E20C // Interrupt 96-127 Set Pending
+#define NVIC_PEND4 0xE000E210 // Interrupt 128-159 Set Pending
+#define NVIC_UNPEND0 0xE000E280 // Interrupt 0-31 Clear Pending
+#define NVIC_UNPEND1 0xE000E284 // Interrupt 32-63 Clear Pending
+#define NVIC_UNPEND2 0xE000E288 // Interrupt 64-95 Clear Pending
+#define NVIC_UNPEND3 0xE000E28C // Interrupt 96-127 Clear Pending
+#define NVIC_UNPEND4 0xE000E290 // Interrupt 128-159 Clear Pending
+#define NVIC_ACTIVE0 0xE000E300 // Interrupt 0-31 Active Bit
+#define NVIC_ACTIVE1 0xE000E304 // Interrupt 32-63 Active Bit
+#define NVIC_ACTIVE2 0xE000E308 // Interrupt 64-95 Active Bit
+#define NVIC_ACTIVE3 0xE000E30C // Interrupt 96-127 Active Bit
+#define NVIC_ACTIVE4 0xE000E310 // Interrupt 128-159 Active Bit
+#define NVIC_PRI0 0xE000E400 // Interrupt 0-3 Priority
+#define NVIC_PRI1 0xE000E404 // Interrupt 4-7 Priority
+#define NVIC_PRI2 0xE000E408 // Interrupt 8-11 Priority
+#define NVIC_PRI3 0xE000E40C // Interrupt 12-15 Priority
+#define NVIC_PRI4 0xE000E410 // Interrupt 16-19 Priority
+#define NVIC_PRI5 0xE000E414 // Interrupt 20-23 Priority
+#define NVIC_PRI6 0xE000E418 // Interrupt 24-27 Priority
+#define NVIC_PRI7 0xE000E41C // Interrupt 28-31 Priority
+#define NVIC_PRI8 0xE000E420 // Interrupt 32-35 Priority
+#define NVIC_PRI9 0xE000E424 // Interrupt 36-39 Priority
+#define NVIC_PRI10 0xE000E428 // Interrupt 40-43 Priority
+#define NVIC_PRI11 0xE000E42C // Interrupt 44-47 Priority
+#define NVIC_PRI12 0xE000E430 // Interrupt 48-51 Priority
+#define NVIC_PRI13 0xE000E434 // Interrupt 52-55 Priority
+#define NVIC_PRI14 0xE000E438 // Interrupt 56-59 Priority
+#define NVIC_PRI15 0xE000E43C // Interrupt 60-63 Priority
+#define NVIC_PRI16 0xE000E440 // Interrupt 64-67 Priority
+#define NVIC_PRI17 0xE000E444 // Interrupt 68-71 Priority
+#define NVIC_PRI18 0xE000E448 // Interrupt 72-75 Priority
+#define NVIC_PRI19 0xE000E44C // Interrupt 76-79 Priority
+#define NVIC_PRI20 0xE000E450 // Interrupt 80-83 Priority
+#define NVIC_PRI21 0xE000E454 // Interrupt 84-87 Priority
+#define NVIC_PRI22 0xE000E458 // Interrupt 88-91 Priority
+#define NVIC_PRI23 0xE000E45C // Interrupt 92-95 Priority
+#define NVIC_PRI24 0xE000E460 // Interrupt 96-99 Priority
+#define NVIC_PRI25 0xE000E464 // Interrupt 100-103 Priority
+#define NVIC_PRI26 0xE000E468 // Interrupt 104-107 Priority
+#define NVIC_PRI27 0xE000E46C // Interrupt 108-111 Priority
+#define NVIC_PRI28 0xE000E470 // Interrupt 112-115 Priority
+#define NVIC_PRI29 0xE000E474 // Interrupt 116-119 Priority
+#define NVIC_PRI30 0xE000E478 // Interrupt 120-123 Priority
+#define NVIC_PRI31 0xE000E47C // Interrupt 124-127 Priority
+#define NVIC_PRI32 0xE000E480 // Interrupt 128-131 Priority
+#define NVIC_PRI33 0xE000E484 // Interrupt 132-135 Priority
+#define NVIC_PRI34 0xE000E488 // Interrupt 136-139 Priority
+#define NVIC_CPUID 0xE000ED00 // CPU ID Base
+#define NVIC_INT_CTRL 0xE000ED04 // Interrupt Control and State
+#define NVIC_VTABLE 0xE000ED08 // Vector Table Offset
+#define NVIC_APINT 0xE000ED0C // Application Interrupt and Reset
+ // Control
+#define NVIC_SYS_CTRL 0xE000ED10 // System Control
+#define NVIC_CFG_CTRL 0xE000ED14 // Configuration and Control
+#define NVIC_SYS_PRI1 0xE000ED18 // System Handler Priority 1
+#define NVIC_SYS_PRI2 0xE000ED1C // System Handler Priority 2
+#define NVIC_SYS_PRI3 0xE000ED20 // System Handler Priority 3
+#define NVIC_SYS_HND_CTRL 0xE000ED24 // System Handler Control and State
+#define NVIC_FAULT_STAT 0xE000ED28 // Configurable Fault Status
+#define NVIC_HFAULT_STAT 0xE000ED2C // Hard Fault Status
+#define NVIC_DEBUG_STAT 0xE000ED30 // Debug Status Register
+#define NVIC_MM_ADDR 0xE000ED34 // Memory Management Fault Address
+#define NVIC_FAULT_ADDR 0xE000ED38 // Bus Fault Address
+#define NVIC_CPAC 0xE000ED88 // Coprocessor Access Control
+#define NVIC_MPU_TYPE 0xE000ED90 // MPU Type
+#define NVIC_MPU_CTRL 0xE000ED94 // MPU Control
+#define NVIC_MPU_NUMBER 0xE000ED98 // MPU Region Number
+#define NVIC_MPU_BASE 0xE000ED9C // MPU Region Base Address
+#define NVIC_MPU_ATTR 0xE000EDA0 // MPU Region Attribute and Size
+#define NVIC_MPU_BASE1 0xE000EDA4 // MPU Region Base Address Alias 1
+#define NVIC_MPU_ATTR1 0xE000EDA8 // MPU Region Attribute and Size
+ // Alias 1
+#define NVIC_MPU_BASE2 0xE000EDAC // MPU Region Base Address Alias 2
+#define NVIC_MPU_ATTR2 0xE000EDB0 // MPU Region Attribute and Size
+ // Alias 2
+#define NVIC_MPU_BASE3 0xE000EDB4 // MPU Region Base Address Alias 3
+#define NVIC_MPU_ATTR3 0xE000EDB8 // MPU Region Attribute and Size
+ // Alias 3
+#define NVIC_DBG_CTRL 0xE000EDF0 // Debug Control and Status Reg
+#define NVIC_DBG_XFER 0xE000EDF4 // Debug Core Reg. Transfer Select
+#define NVIC_DBG_DATA 0xE000EDF8 // Debug Core Register Data
+#define NVIC_DBG_INT 0xE000EDFC // Debug Reset Interrupt Control
+#define NVIC_SW_TRIG 0xE000EF00 // Software Trigger Interrupt
+#define NVIC_FPCC 0xE000EF34 // Floating-Point Context Control
+#define NVIC_FPCA 0xE000EF38 // Floating-Point Context Address
+#define NVIC_FPDSC 0xE000EF3C // Floating-Point Default Status
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTLR register.
+//
+//*****************************************************************************
+#define NVIC_ACTLR_DISOOFP 0x00000200 // Disable Out-Of-Order Floating
+ // Point
+#define NVIC_ACTLR_DISFPCA 0x00000100 // Disable CONTROL
+#define NVIC_ACTLR_DISFOLD 0x00000004 // Disable IT Folding
+#define NVIC_ACTLR_DISWBUF 0x00000002 // Disable Write Buffer
+#define NVIC_ACTLR_DISMCYC 0x00000001 // Disable Interrupts of Multiple
+ // Cycle Instructions
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_ST_CTRL_COUNT 0x00010000 // Count Flag
+#define NVIC_ST_CTRL_CLK_SRC 0x00000004 // Clock Source
+#define NVIC_ST_CTRL_INTEN 0x00000002 // Interrupt Enable
+#define NVIC_ST_CTRL_ENABLE 0x00000001 // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_RELOAD register.
+//
+//*****************************************************************************
+#define NVIC_ST_RELOAD_M 0x00FFFFFF // Reload Value
+#define NVIC_ST_RELOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ST_CURRENT
+// register.
+//
+//*****************************************************************************
+#define NVIC_ST_CURRENT_M 0x00FFFFFF // Current Value
+#define NVIC_ST_CURRENT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN0 register.
+//
+//*****************************************************************************
+#define NVIC_EN0_INT_M 0xFFFFFFFF // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN1 register.
+//
+//*****************************************************************************
+#define NVIC_EN1_INT_M 0xFFFFFFFF // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN2 register.
+//
+//*****************************************************************************
+#define NVIC_EN2_INT_M 0xFFFFFFFF // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN3 register.
+//
+//*****************************************************************************
+#define NVIC_EN3_INT_M 0xFFFFFFFF // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_EN4 register.
+//
+//*****************************************************************************
+#define NVIC_EN4_INT_M 0x000007FF // Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS0 register.
+//
+//*****************************************************************************
+#define NVIC_DIS0_INT_M 0xFFFFFFFF // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS1 register.
+//
+//*****************************************************************************
+#define NVIC_DIS1_INT_M 0xFFFFFFFF // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS2 register.
+//
+//*****************************************************************************
+#define NVIC_DIS2_INT_M 0xFFFFFFFF // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS3 register.
+//
+//*****************************************************************************
+#define NVIC_DIS3_INT_M 0xFFFFFFFF // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DIS4 register.
+//
+//*****************************************************************************
+#define NVIC_DIS4_INT_M 0x000007FF // Interrupt Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND0 register.
+//
+//*****************************************************************************
+#define NVIC_PEND0_INT_M 0xFFFFFFFF // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND1 register.
+//
+//*****************************************************************************
+#define NVIC_PEND1_INT_M 0xFFFFFFFF // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND2 register.
+//
+//*****************************************************************************
+#define NVIC_PEND2_INT_M 0xFFFFFFFF // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND3 register.
+//
+//*****************************************************************************
+#define NVIC_PEND3_INT_M 0xFFFFFFFF // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PEND4 register.
+//
+//*****************************************************************************
+#define NVIC_PEND4_INT_M 0x000007FF // Interrupt Set Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND0 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND0_INT_M 0xFFFFFFFF // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND1 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND1_INT_M 0xFFFFFFFF // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND2 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND2_INT_M 0xFFFFFFFF // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND3 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND3_INT_M 0xFFFFFFFF // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_UNPEND4 register.
+//
+//*****************************************************************************
+#define NVIC_UNPEND4_INT_M 0x000007FF // Interrupt Clear Pending
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE0 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE0_INT_M 0xFFFFFFFF // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE1 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE1_INT_M 0xFFFFFFFF // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE2 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE2_INT_M 0xFFFFFFFF // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE3 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE3_INT_M 0xFFFFFFFF // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_ACTIVE4 register.
+//
+//*****************************************************************************
+#define NVIC_ACTIVE4_INT_M 0x000007FF // Interrupt Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI0 register.
+//
+//*****************************************************************************
+#define NVIC_PRI0_INT3_M 0xE0000000 // Interrupt 3 Priority Mask
+#define NVIC_PRI0_INT2_M 0x00E00000 // Interrupt 2 Priority Mask
+#define NVIC_PRI0_INT1_M 0x0000E000 // Interrupt 1 Priority Mask
+#define NVIC_PRI0_INT0_M 0x000000E0 // Interrupt 0 Priority Mask
+#define NVIC_PRI0_INT3_S 29
+#define NVIC_PRI0_INT2_S 21
+#define NVIC_PRI0_INT1_S 13
+#define NVIC_PRI0_INT0_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_PRI1_INT7_M 0xE0000000 // Interrupt 7 Priority Mask
+#define NVIC_PRI1_INT6_M 0x00E00000 // Interrupt 6 Priority Mask
+#define NVIC_PRI1_INT5_M 0x0000E000 // Interrupt 5 Priority Mask
+#define NVIC_PRI1_INT4_M 0x000000E0 // Interrupt 4 Priority Mask
+#define NVIC_PRI1_INT7_S 29
+#define NVIC_PRI1_INT6_S 21
+#define NVIC_PRI1_INT5_S 13
+#define NVIC_PRI1_INT4_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_PRI2_INT11_M 0xE0000000 // Interrupt 11 Priority Mask
+#define NVIC_PRI2_INT10_M 0x00E00000 // Interrupt 10 Priority Mask
+#define NVIC_PRI2_INT9_M 0x0000E000 // Interrupt 9 Priority Mask
+#define NVIC_PRI2_INT8_M 0x000000E0 // Interrupt 8 Priority Mask
+#define NVIC_PRI2_INT11_S 29
+#define NVIC_PRI2_INT10_S 21
+#define NVIC_PRI2_INT9_S 13
+#define NVIC_PRI2_INT8_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_PRI3_INT15_M 0xE0000000 // Interrupt 15 Priority Mask
+#define NVIC_PRI3_INT14_M 0x00E00000 // Interrupt 14 Priority Mask
+#define NVIC_PRI3_INT13_M 0x0000E000 // Interrupt 13 Priority Mask
+#define NVIC_PRI3_INT12_M 0x000000E0 // Interrupt 12 Priority Mask
+#define NVIC_PRI3_INT15_S 29
+#define NVIC_PRI3_INT14_S 21
+#define NVIC_PRI3_INT13_S 13
+#define NVIC_PRI3_INT12_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI4 register.
+//
+//*****************************************************************************
+#define NVIC_PRI4_INT19_M 0xE0000000 // Interrupt 19 Priority Mask
+#define NVIC_PRI4_INT18_M 0x00E00000 // Interrupt 18 Priority Mask
+#define NVIC_PRI4_INT17_M 0x0000E000 // Interrupt 17 Priority Mask
+#define NVIC_PRI4_INT16_M 0x000000E0 // Interrupt 16 Priority Mask
+#define NVIC_PRI4_INT19_S 29
+#define NVIC_PRI4_INT18_S 21
+#define NVIC_PRI4_INT17_S 13
+#define NVIC_PRI4_INT16_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI5 register.
+//
+//*****************************************************************************
+#define NVIC_PRI5_INT23_M 0xE0000000 // Interrupt 23 Priority Mask
+#define NVIC_PRI5_INT22_M 0x00E00000 // Interrupt 22 Priority Mask
+#define NVIC_PRI5_INT21_M 0x0000E000 // Interrupt 21 Priority Mask
+#define NVIC_PRI5_INT20_M 0x000000E0 // Interrupt 20 Priority Mask
+#define NVIC_PRI5_INT23_S 29
+#define NVIC_PRI5_INT22_S 21
+#define NVIC_PRI5_INT21_S 13
+#define NVIC_PRI5_INT20_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI6 register.
+//
+//*****************************************************************************
+#define NVIC_PRI6_INT27_M 0xE0000000 // Interrupt 27 Priority Mask
+#define NVIC_PRI6_INT26_M 0x00E00000 // Interrupt 26 Priority Mask
+#define NVIC_PRI6_INT25_M 0x0000E000 // Interrupt 25 Priority Mask
+#define NVIC_PRI6_INT24_M 0x000000E0 // Interrupt 24 Priority Mask
+#define NVIC_PRI6_INT27_S 29
+#define NVIC_PRI6_INT26_S 21
+#define NVIC_PRI6_INT25_S 13
+#define NVIC_PRI6_INT24_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI7 register.
+//
+//*****************************************************************************
+#define NVIC_PRI7_INT31_M 0xE0000000 // Interrupt 31 Priority Mask
+#define NVIC_PRI7_INT30_M 0x00E00000 // Interrupt 30 Priority Mask
+#define NVIC_PRI7_INT29_M 0x0000E000 // Interrupt 29 Priority Mask
+#define NVIC_PRI7_INT28_M 0x000000E0 // Interrupt 28 Priority Mask
+#define NVIC_PRI7_INT31_S 29
+#define NVIC_PRI7_INT30_S 21
+#define NVIC_PRI7_INT29_S 13
+#define NVIC_PRI7_INT28_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI8 register.
+//
+//*****************************************************************************
+#define NVIC_PRI8_INT35_M 0xE0000000 // Interrupt 35 Priority Mask
+#define NVIC_PRI8_INT34_M 0x00E00000 // Interrupt 34 Priority Mask
+#define NVIC_PRI8_INT33_M 0x0000E000 // Interrupt 33 Priority Mask
+#define NVIC_PRI8_INT32_M 0x000000E0 // Interrupt 32 Priority Mask
+#define NVIC_PRI8_INT35_S 29
+#define NVIC_PRI8_INT34_S 21
+#define NVIC_PRI8_INT33_S 13
+#define NVIC_PRI8_INT32_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI9 register.
+//
+//*****************************************************************************
+#define NVIC_PRI9_INT39_M 0xE0000000 // Interrupt 39 Priority Mask
+#define NVIC_PRI9_INT38_M 0x00E00000 // Interrupt 38 Priority Mask
+#define NVIC_PRI9_INT37_M 0x0000E000 // Interrupt 37 Priority Mask
+#define NVIC_PRI9_INT36_M 0x000000E0 // Interrupt 36 Priority Mask
+#define NVIC_PRI9_INT39_S 29
+#define NVIC_PRI9_INT38_S 21
+#define NVIC_PRI9_INT37_S 13
+#define NVIC_PRI9_INT36_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI10 register.
+//
+//*****************************************************************************
+#define NVIC_PRI10_INT43_M 0xE0000000 // Interrupt 43 Priority Mask
+#define NVIC_PRI10_INT42_M 0x00E00000 // Interrupt 42 Priority Mask
+#define NVIC_PRI10_INT41_M 0x0000E000 // Interrupt 41 Priority Mask
+#define NVIC_PRI10_INT40_M 0x000000E0 // Interrupt 40 Priority Mask
+#define NVIC_PRI10_INT43_S 29
+#define NVIC_PRI10_INT42_S 21
+#define NVIC_PRI10_INT41_S 13
+#define NVIC_PRI10_INT40_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI11 register.
+//
+//*****************************************************************************
+#define NVIC_PRI11_INT47_M 0xE0000000 // Interrupt 47 Priority Mask
+#define NVIC_PRI11_INT46_M 0x00E00000 // Interrupt 46 Priority Mask
+#define NVIC_PRI11_INT45_M 0x0000E000 // Interrupt 45 Priority Mask
+#define NVIC_PRI11_INT44_M 0x000000E0 // Interrupt 44 Priority Mask
+#define NVIC_PRI11_INT47_S 29
+#define NVIC_PRI11_INT46_S 21
+#define NVIC_PRI11_INT45_S 13
+#define NVIC_PRI11_INT44_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI12 register.
+//
+//*****************************************************************************
+#define NVIC_PRI12_INT51_M 0xE0000000 // Interrupt 51 Priority Mask
+#define NVIC_PRI12_INT50_M 0x00E00000 // Interrupt 50 Priority Mask
+#define NVIC_PRI12_INT49_M 0x0000E000 // Interrupt 49 Priority Mask
+#define NVIC_PRI12_INT48_M 0x000000E0 // Interrupt 48 Priority Mask
+#define NVIC_PRI12_INT51_S 29
+#define NVIC_PRI12_INT50_S 21
+#define NVIC_PRI12_INT49_S 13
+#define NVIC_PRI12_INT48_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI13 register.
+//
+//*****************************************************************************
+#define NVIC_PRI13_INT55_M 0xE0000000 // Interrupt 55 Priority Mask
+#define NVIC_PRI13_INT54_M 0x00E00000 // Interrupt 54 Priority Mask
+#define NVIC_PRI13_INT53_M 0x0000E000 // Interrupt 53 Priority Mask
+#define NVIC_PRI13_INT52_M 0x000000E0 // Interrupt 52 Priority Mask
+#define NVIC_PRI13_INT55_S 29
+#define NVIC_PRI13_INT54_S 21
+#define NVIC_PRI13_INT53_S 13
+#define NVIC_PRI13_INT52_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI14 register.
+//
+//*****************************************************************************
+#define NVIC_PRI14_INTD_M 0xE0000000 // Interrupt 59 Priority Mask
+#define NVIC_PRI14_INTC_M 0x00E00000 // Interrupt 58 Priority Mask
+#define NVIC_PRI14_INTB_M 0x0000E000 // Interrupt 57 Priority Mask
+#define NVIC_PRI14_INTA_M 0x000000E0 // Interrupt 56 Priority Mask
+#define NVIC_PRI14_INTD_S 29
+#define NVIC_PRI14_INTC_S 21
+#define NVIC_PRI14_INTB_S 13
+#define NVIC_PRI14_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI15 register.
+//
+//*****************************************************************************
+#define NVIC_PRI15_INTD_M 0xE0000000 // Interrupt 63 Priority Mask
+#define NVIC_PRI15_INTC_M 0x00E00000 // Interrupt 62 Priority Mask
+#define NVIC_PRI15_INTB_M 0x0000E000 // Interrupt 61 Priority Mask
+#define NVIC_PRI15_INTA_M 0x000000E0 // Interrupt 60 Priority Mask
+#define NVIC_PRI15_INTD_S 29
+#define NVIC_PRI15_INTC_S 21
+#define NVIC_PRI15_INTB_S 13
+#define NVIC_PRI15_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI16 register.
+//
+//*****************************************************************************
+#define NVIC_PRI16_INTD_M 0xE0000000 // Interrupt 67 Priority Mask
+#define NVIC_PRI16_INTC_M 0x00E00000 // Interrupt 66 Priority Mask
+#define NVIC_PRI16_INTB_M 0x0000E000 // Interrupt 65 Priority Mask
+#define NVIC_PRI16_INTA_M 0x000000E0 // Interrupt 64 Priority Mask
+#define NVIC_PRI16_INTD_S 29
+#define NVIC_PRI16_INTC_S 21
+#define NVIC_PRI16_INTB_S 13
+#define NVIC_PRI16_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI17 register.
+//
+//*****************************************************************************
+#define NVIC_PRI17_INTD_M 0xE0000000 // Interrupt 71 Priority Mask
+#define NVIC_PRI17_INTC_M 0x00E00000 // Interrupt 70 Priority Mask
+#define NVIC_PRI17_INTB_M 0x0000E000 // Interrupt 69 Priority Mask
+#define NVIC_PRI17_INTA_M 0x000000E0 // Interrupt 68 Priority Mask
+#define NVIC_PRI17_INTD_S 29
+#define NVIC_PRI17_INTC_S 21
+#define NVIC_PRI17_INTB_S 13
+#define NVIC_PRI17_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI18 register.
+//
+//*****************************************************************************
+#define NVIC_PRI18_INTD_M 0xE0000000 // Interrupt 75 Priority Mask
+#define NVIC_PRI18_INTC_M 0x00E00000 // Interrupt 74 Priority Mask
+#define NVIC_PRI18_INTB_M 0x0000E000 // Interrupt 73 Priority Mask
+#define NVIC_PRI18_INTA_M 0x000000E0 // Interrupt 72 Priority Mask
+#define NVIC_PRI18_INTD_S 29
+#define NVIC_PRI18_INTC_S 21
+#define NVIC_PRI18_INTB_S 13
+#define NVIC_PRI18_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI19 register.
+//
+//*****************************************************************************
+#define NVIC_PRI19_INTD_M 0xE0000000 // Interrupt 79 Priority Mask
+#define NVIC_PRI19_INTC_M 0x00E00000 // Interrupt 78 Priority Mask
+#define NVIC_PRI19_INTB_M 0x0000E000 // Interrupt 77 Priority Mask
+#define NVIC_PRI19_INTA_M 0x000000E0 // Interrupt 76 Priority Mask
+#define NVIC_PRI19_INTD_S 29
+#define NVIC_PRI19_INTC_S 21
+#define NVIC_PRI19_INTB_S 13
+#define NVIC_PRI19_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI20 register.
+//
+//*****************************************************************************
+#define NVIC_PRI20_INTD_M 0xE0000000 // Interrupt 83 Priority Mask
+#define NVIC_PRI20_INTC_M 0x00E00000 // Interrupt 82 Priority Mask
+#define NVIC_PRI20_INTB_M 0x0000E000 // Interrupt 81 Priority Mask
+#define NVIC_PRI20_INTA_M 0x000000E0 // Interrupt 80 Priority Mask
+#define NVIC_PRI20_INTD_S 29
+#define NVIC_PRI20_INTC_S 21
+#define NVIC_PRI20_INTB_S 13
+#define NVIC_PRI20_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI21 register.
+//
+//*****************************************************************************
+#define NVIC_PRI21_INTD_M 0xE0000000 // Interrupt 87 Priority Mask
+#define NVIC_PRI21_INTC_M 0x00E00000 // Interrupt 86 Priority Mask
+#define NVIC_PRI21_INTB_M 0x0000E000 // Interrupt 85 Priority Mask
+#define NVIC_PRI21_INTA_M 0x000000E0 // Interrupt 84 Priority Mask
+#define NVIC_PRI21_INTD_S 29
+#define NVIC_PRI21_INTC_S 21
+#define NVIC_PRI21_INTB_S 13
+#define NVIC_PRI21_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI22 register.
+//
+//*****************************************************************************
+#define NVIC_PRI22_INTD_M 0xE0000000 // Interrupt 91 Priority Mask
+#define NVIC_PRI22_INTC_M 0x00E00000 // Interrupt 90 Priority Mask
+#define NVIC_PRI22_INTB_M 0x0000E000 // Interrupt 89 Priority Mask
+#define NVIC_PRI22_INTA_M 0x000000E0 // Interrupt 88 Priority Mask
+#define NVIC_PRI22_INTD_S 29
+#define NVIC_PRI22_INTC_S 21
+#define NVIC_PRI22_INTB_S 13
+#define NVIC_PRI22_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI23 register.
+//
+//*****************************************************************************
+#define NVIC_PRI23_INTD_M 0xE0000000 // Interrupt 95 Priority Mask
+#define NVIC_PRI23_INTC_M 0x00E00000 // Interrupt 94 Priority Mask
+#define NVIC_PRI23_INTB_M 0x0000E000 // Interrupt 93 Priority Mask
+#define NVIC_PRI23_INTA_M 0x000000E0 // Interrupt 92 Priority Mask
+#define NVIC_PRI23_INTD_S 29
+#define NVIC_PRI23_INTC_S 21
+#define NVIC_PRI23_INTB_S 13
+#define NVIC_PRI23_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI24 register.
+//
+//*****************************************************************************
+#define NVIC_PRI24_INTD_M 0xE0000000 // Interrupt 99 Priority Mask
+#define NVIC_PRI24_INTC_M 0x00E00000 // Interrupt 98 Priority Mask
+#define NVIC_PRI24_INTB_M 0x0000E000 // Interrupt 97 Priority Mask
+#define NVIC_PRI24_INTA_M 0x000000E0 // Interrupt 96 Priority Mask
+#define NVIC_PRI24_INTD_S 29
+#define NVIC_PRI24_INTC_S 21
+#define NVIC_PRI24_INTB_S 13
+#define NVIC_PRI24_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI25 register.
+//
+//*****************************************************************************
+#define NVIC_PRI25_INTD_M 0xE0000000 // Interrupt 103 Priority Mask
+#define NVIC_PRI25_INTC_M 0x00E00000 // Interrupt 102 Priority Mask
+#define NVIC_PRI25_INTB_M 0x0000E000 // Interrupt 101 Priority Mask
+#define NVIC_PRI25_INTA_M 0x000000E0 // Interrupt 100 Priority Mask
+#define NVIC_PRI25_INTD_S 29
+#define NVIC_PRI25_INTC_S 21
+#define NVIC_PRI25_INTB_S 13
+#define NVIC_PRI25_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI26 register.
+//
+//*****************************************************************************
+#define NVIC_PRI26_INTD_M 0xE0000000 // Interrupt 107 Priority Mask
+#define NVIC_PRI26_INTC_M 0x00E00000 // Interrupt 106 Priority Mask
+#define NVIC_PRI26_INTB_M 0x0000E000 // Interrupt 105 Priority Mask
+#define NVIC_PRI26_INTA_M 0x000000E0 // Interrupt 104 Priority Mask
+#define NVIC_PRI26_INTD_S 29
+#define NVIC_PRI26_INTC_S 21
+#define NVIC_PRI26_INTB_S 13
+#define NVIC_PRI26_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI27 register.
+//
+//*****************************************************************************
+#define NVIC_PRI27_INTD_M 0xE0000000 // Interrupt 111 Priority Mask
+#define NVIC_PRI27_INTC_M 0x00E00000 // Interrupt 110 Priority Mask
+#define NVIC_PRI27_INTB_M 0x0000E000 // Interrupt 109 Priority Mask
+#define NVIC_PRI27_INTA_M 0x000000E0 // Interrupt 108 Priority Mask
+#define NVIC_PRI27_INTD_S 29
+#define NVIC_PRI27_INTC_S 21
+#define NVIC_PRI27_INTB_S 13
+#define NVIC_PRI27_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI28 register.
+//
+//*****************************************************************************
+#define NVIC_PRI28_INTD_M 0xE0000000 // Interrupt 115 Priority Mask
+#define NVIC_PRI28_INTC_M 0x00E00000 // Interrupt 114 Priority Mask
+#define NVIC_PRI28_INTB_M 0x0000E000 // Interrupt 113 Priority Mask
+#define NVIC_PRI28_INTA_M 0x000000E0 // Interrupt 112 Priority Mask
+#define NVIC_PRI28_INTD_S 29
+#define NVIC_PRI28_INTC_S 21
+#define NVIC_PRI28_INTB_S 13
+#define NVIC_PRI28_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI29 register.
+//
+//*****************************************************************************
+#define NVIC_PRI29_INTD_M 0xE0000000 // Interrupt 119 Priority Mask
+#define NVIC_PRI29_INTC_M 0x00E00000 // Interrupt 118 Priority Mask
+#define NVIC_PRI29_INTB_M 0x0000E000 // Interrupt 117 Priority Mask
+#define NVIC_PRI29_INTA_M 0x000000E0 // Interrupt 116 Priority Mask
+#define NVIC_PRI29_INTD_S 29
+#define NVIC_PRI29_INTC_S 21
+#define NVIC_PRI29_INTB_S 13
+#define NVIC_PRI29_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI30 register.
+//
+//*****************************************************************************
+#define NVIC_PRI30_INTD_M 0xE0000000 // Interrupt 123 Priority Mask
+#define NVIC_PRI30_INTC_M 0x00E00000 // Interrupt 122 Priority Mask
+#define NVIC_PRI30_INTB_M 0x0000E000 // Interrupt 121 Priority Mask
+#define NVIC_PRI30_INTA_M 0x000000E0 // Interrupt 120 Priority Mask
+#define NVIC_PRI30_INTD_S 29
+#define NVIC_PRI30_INTC_S 21
+#define NVIC_PRI30_INTB_S 13
+#define NVIC_PRI30_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI31 register.
+//
+//*****************************************************************************
+#define NVIC_PRI31_INTD_M 0xE0000000 // Interrupt 127 Priority Mask
+#define NVIC_PRI31_INTC_M 0x00E00000 // Interrupt 126 Priority Mask
+#define NVIC_PRI31_INTB_M 0x0000E000 // Interrupt 125 Priority Mask
+#define NVIC_PRI31_INTA_M 0x000000E0 // Interrupt 124 Priority Mask
+#define NVIC_PRI31_INTD_S 29
+#define NVIC_PRI31_INTC_S 21
+#define NVIC_PRI31_INTB_S 13
+#define NVIC_PRI31_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI32 register.
+//
+//*****************************************************************************
+#define NVIC_PRI32_INTD_M 0xE0000000 // Interrupt 131 Priority Mask
+#define NVIC_PRI32_INTC_M 0x00E00000 // Interrupt 130 Priority Mask
+#define NVIC_PRI32_INTB_M 0x0000E000 // Interrupt 129 Priority Mask
+#define NVIC_PRI32_INTA_M 0x000000E0 // Interrupt 128 Priority Mask
+#define NVIC_PRI32_INTD_S 29
+#define NVIC_PRI32_INTC_S 21
+#define NVIC_PRI32_INTB_S 13
+#define NVIC_PRI32_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI33 register.
+//
+//*****************************************************************************
+#define NVIC_PRI33_INTD_M 0xE0000000 // Interrupt Priority for Interrupt
+ // [4n+3]
+#define NVIC_PRI33_INTC_M 0x00E00000 // Interrupt Priority for Interrupt
+ // [4n+2]
+#define NVIC_PRI33_INTB_M 0x0000E000 // Interrupt Priority for Interrupt
+ // [4n+1]
+#define NVIC_PRI33_INTA_M 0x000000E0 // Interrupt Priority for Interrupt
+ // [4n]
+#define NVIC_PRI33_INTD_S 29
+#define NVIC_PRI33_INTC_S 21
+#define NVIC_PRI33_INTB_S 13
+#define NVIC_PRI33_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_PRI34 register.
+//
+//*****************************************************************************
+#define NVIC_PRI34_INTD_M 0xE0000000 // Interrupt Priority for Interrupt
+ // [4n+3]
+#define NVIC_PRI34_INTC_M 0x00E00000 // Interrupt Priority for Interrupt
+ // [4n+2]
+#define NVIC_PRI34_INTB_M 0x0000E000 // Interrupt Priority for Interrupt
+ // [4n+1]
+#define NVIC_PRI34_INTA_M 0x000000E0 // Interrupt Priority for Interrupt
+ // [4n]
+#define NVIC_PRI34_INTD_S 29
+#define NVIC_PRI34_INTC_S 21
+#define NVIC_PRI34_INTB_S 13
+#define NVIC_PRI34_INTA_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CPUID register.
+//
+//*****************************************************************************
+#define NVIC_CPUID_IMP_M 0xFF000000 // Implementer Code
+#define NVIC_CPUID_IMP_ARM 0x41000000 // ARM
+#define NVIC_CPUID_VAR_M 0x00F00000 // Variant Number
+#define NVIC_CPUID_CON_M 0x000F0000 // Constant
+#define NVIC_CPUID_PARTNO_M 0x0000FFF0 // Part Number
+#define NVIC_CPUID_PARTNO_CM4 0x0000C240 // Cortex-M4 processor
+#define NVIC_CPUID_REV_M 0x0000000F // Revision Number
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_INT_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_INT_CTRL_NMI_SET 0x80000000 // NMI Set Pending
+#define NVIC_INT_CTRL_PEND_SV 0x10000000 // PendSV Set Pending
+#define NVIC_INT_CTRL_UNPEND_SV 0x08000000 // PendSV Clear Pending
+#define NVIC_INT_CTRL_PENDSTSET 0x04000000 // SysTick Set Pending
+#define NVIC_INT_CTRL_PENDSTCLR 0x02000000 // SysTick Clear Pending
+#define NVIC_INT_CTRL_ISR_PRE 0x00800000 // Debug Interrupt Handling
+#define NVIC_INT_CTRL_ISR_PEND 0x00400000 // Interrupt Pending
+#define NVIC_INT_CTRL_VEC_PEN_M 0x000FF000 // Interrupt Pending Vector Number
+#define NVIC_INT_CTRL_VEC_PEN_NMI \
+ 0x00002000 // NMI
+#define NVIC_INT_CTRL_VEC_PEN_HARD \
+ 0x00003000 // Hard fault
+#define NVIC_INT_CTRL_VEC_PEN_MEM \
+ 0x00004000 // Memory management fault
+#define NVIC_INT_CTRL_VEC_PEN_BUS \
+ 0x00005000 // Bus fault
+#define NVIC_INT_CTRL_VEC_PEN_USG \
+ 0x00006000 // Usage fault
+#define NVIC_INT_CTRL_VEC_PEN_SVC \
+ 0x0000B000 // SVCall
+#define NVIC_INT_CTRL_VEC_PEN_PNDSV \
+ 0x0000E000 // PendSV
+#define NVIC_INT_CTRL_VEC_PEN_TICK \
+ 0x0000F000 // SysTick
+#define NVIC_INT_CTRL_RET_BASE 0x00000800 // Return to Base
+#define NVIC_INT_CTRL_VEC_ACT_M 0x000000FF // Interrupt Pending Vector Number
+#define NVIC_INT_CTRL_VEC_ACT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_VTABLE register.
+//
+//*****************************************************************************
+#define NVIC_VTABLE_OFFSET_M 0xFFFFFC00 // Vector Table Offset
+#define NVIC_VTABLE_OFFSET_S 10
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_APINT register.
+//
+//*****************************************************************************
+#define NVIC_APINT_VECTKEY_M 0xFFFF0000 // Register Key
+#define NVIC_APINT_VECTKEY 0x05FA0000 // Vector key
+#define NVIC_APINT_ENDIANESS 0x00008000 // Data Endianess
+#define NVIC_APINT_PRIGROUP_M 0x00000700 // Interrupt Priority Grouping
+#define NVIC_APINT_PRIGROUP_7_1 0x00000000 // Priority group 7.1 split
+#define NVIC_APINT_PRIGROUP_6_2 0x00000100 // Priority group 6.2 split
+#define NVIC_APINT_PRIGROUP_5_3 0x00000200 // Priority group 5.3 split
+#define NVIC_APINT_PRIGROUP_4_4 0x00000300 // Priority group 4.4 split
+#define NVIC_APINT_PRIGROUP_3_5 0x00000400 // Priority group 3.5 split
+#define NVIC_APINT_PRIGROUP_2_6 0x00000500 // Priority group 2.6 split
+#define NVIC_APINT_PRIGROUP_1_7 0x00000600 // Priority group 1.7 split
+#define NVIC_APINT_PRIGROUP_0_8 0x00000700 // Priority group 0.8 split
+#define NVIC_APINT_SYSRESETREQ 0x00000004 // System Reset Request
+#define NVIC_APINT_VECT_CLR_ACT 0x00000002 // Clear Active NMI / Fault
+#define NVIC_APINT_VECT_RESET 0x00000001 // System Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_SYS_CTRL_SEVONPEND 0x00000010 // Wake Up on Pending
+#define NVIC_SYS_CTRL_SLEEPDEEP 0x00000004 // Deep Sleep Enable
+#define NVIC_SYS_CTRL_SLEEPEXIT 0x00000002 // Sleep on ISR Exit
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CFG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_CFG_CTRL_STKALIGN 0x00000200 // Stack Alignment on Exception
+ // Entry
+#define NVIC_CFG_CTRL_BFHFNMIGN 0x00000100 // Ignore Bus Fault in NMI and
+ // Fault
+#define NVIC_CFG_CTRL_DIV0 0x00000010 // Trap on Divide by 0
+#define NVIC_CFG_CTRL_UNALIGNED 0x00000008 // Trap on Unaligned Access
+#define NVIC_CFG_CTRL_MAIN_PEND 0x00000002 // Allow Main Interrupt Trigger
+#define NVIC_CFG_CTRL_BASE_THR 0x00000001 // Thread State Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI1 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI1_USAGE_M 0x00E00000 // Usage Fault Priority
+#define NVIC_SYS_PRI1_BUS_M 0x0000E000 // Bus Fault Priority
+#define NVIC_SYS_PRI1_MEM_M 0x000000E0 // Memory Management Fault Priority
+#define NVIC_SYS_PRI1_USAGE_S 21
+#define NVIC_SYS_PRI1_BUS_S 13
+#define NVIC_SYS_PRI1_MEM_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI2 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI2_SVC_M 0xE0000000 // SVCall Priority
+#define NVIC_SYS_PRI2_SVC_S 29
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_PRI3 register.
+//
+//*****************************************************************************
+#define NVIC_SYS_PRI3_TICK_M 0xE0000000 // SysTick Exception Priority
+#define NVIC_SYS_PRI3_PENDSV_M 0x00E00000 // PendSV Priority
+#define NVIC_SYS_PRI3_DEBUG_M 0x000000E0 // Debug Priority
+#define NVIC_SYS_PRI3_TICK_S 29
+#define NVIC_SYS_PRI3_PENDSV_S 21
+#define NVIC_SYS_PRI3_DEBUG_S 5
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SYS_HND_CTRL
+// register.
+//
+//*****************************************************************************
+#define NVIC_SYS_HND_CTRL_USAGE 0x00040000 // Usage Fault Enable
+#define NVIC_SYS_HND_CTRL_BUS 0x00020000 // Bus Fault Enable
+#define NVIC_SYS_HND_CTRL_MEM 0x00010000 // Memory Management Fault Enable
+#define NVIC_SYS_HND_CTRL_SVC 0x00008000 // SVC Call Pending
+#define NVIC_SYS_HND_CTRL_BUSP 0x00004000 // Bus Fault Pending
+#define NVIC_SYS_HND_CTRL_MEMP 0x00002000 // Memory Management Fault Pending
+#define NVIC_SYS_HND_CTRL_USAGEP \
+ 0x00001000 // Usage Fault Pending
+#define NVIC_SYS_HND_CTRL_TICK 0x00000800 // SysTick Exception Active
+#define NVIC_SYS_HND_CTRL_PNDSV 0x00000400 // PendSV Exception Active
+#define NVIC_SYS_HND_CTRL_MON 0x00000100 // Debug Monitor Active
+#define NVIC_SYS_HND_CTRL_SVCA 0x00000080 // SVC Call Active
+#define NVIC_SYS_HND_CTRL_USGA 0x00000008 // Usage Fault Active
+#define NVIC_SYS_HND_CTRL_BUSA 0x00000002 // Bus Fault Active
+#define NVIC_SYS_HND_CTRL_MEMA 0x00000001 // Memory Management Fault Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_STAT_DIV0 0x02000000 // Divide-by-Zero Usage Fault
+#define NVIC_FAULT_STAT_UNALIGN 0x01000000 // Unaligned Access Usage Fault
+#define NVIC_FAULT_STAT_NOCP 0x00080000 // No Coprocessor Usage Fault
+#define NVIC_FAULT_STAT_INVPC 0x00040000 // Invalid PC Load Usage Fault
+#define NVIC_FAULT_STAT_INVSTAT 0x00020000 // Invalid State Usage Fault
+#define NVIC_FAULT_STAT_UNDEF 0x00010000 // Undefined Instruction Usage
+ // Fault
+#define NVIC_FAULT_STAT_BFARV 0x00008000 // Bus Fault Address Register Valid
+#define NVIC_FAULT_STAT_BLSPERR 0x00002000 // Bus Fault on Floating-Point Lazy
+ // State Preservation
+#define NVIC_FAULT_STAT_BSTKE 0x00001000 // Stack Bus Fault
+#define NVIC_FAULT_STAT_BUSTKE 0x00000800 // Unstack Bus Fault
+#define NVIC_FAULT_STAT_IMPRE 0x00000400 // Imprecise Data Bus Error
+#define NVIC_FAULT_STAT_PRECISE 0x00000200 // Precise Data Bus Error
+#define NVIC_FAULT_STAT_IBUS 0x00000100 // Instruction Bus Error
+#define NVIC_FAULT_STAT_MMARV 0x00000080 // Memory Management Fault Address
+ // Register Valid
+#define NVIC_FAULT_STAT_MLSPERR 0x00000020 // Memory Management Fault on
+ // Floating-Point Lazy State
+ // Preservation
+#define NVIC_FAULT_STAT_MSTKE 0x00000010 // Stack Access Violation
+#define NVIC_FAULT_STAT_MUSTKE 0x00000008 // Unstack Access Violation
+#define NVIC_FAULT_STAT_DERR 0x00000002 // Data Access Violation
+#define NVIC_FAULT_STAT_IERR 0x00000001 // Instruction Access Violation
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_HFAULT_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_HFAULT_STAT_DBG 0x80000000 // Debug Event
+#define NVIC_HFAULT_STAT_FORCED 0x40000000 // Forced Hard Fault
+#define NVIC_HFAULT_STAT_VECT 0x00000002 // Vector Table Read Fault
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DEBUG_STAT
+// register.
+//
+//*****************************************************************************
+#define NVIC_DEBUG_STAT_EXTRNL 0x00000010 // EDBGRQ asserted
+#define NVIC_DEBUG_STAT_VCATCH 0x00000008 // Vector catch
+#define NVIC_DEBUG_STAT_DWTTRAP 0x00000004 // DWT match
+#define NVIC_DEBUG_STAT_BKPT 0x00000002 // Breakpoint instruction
+#define NVIC_DEBUG_STAT_HALTED 0x00000001 // Halt request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MM_ADDR register.
+//
+//*****************************************************************************
+#define NVIC_MM_ADDR_M 0xFFFFFFFF // Fault Address
+#define NVIC_MM_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FAULT_ADDR
+// register.
+//
+//*****************************************************************************
+#define NVIC_FAULT_ADDR_M 0xFFFFFFFF // Fault Address
+#define NVIC_FAULT_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_CPAC register.
+//
+//*****************************************************************************
+#define NVIC_CPAC_CP11_M 0x00C00000 // CP11 Coprocessor Access
+ // Privilege
+#define NVIC_CPAC_CP11_DIS 0x00000000 // Access Denied
+#define NVIC_CPAC_CP11_PRIV 0x00400000 // Privileged Access Only
+#define NVIC_CPAC_CP11_FULL 0x00C00000 // Full Access
+#define NVIC_CPAC_CP10_M 0x00300000 // CP10 Coprocessor Access
+ // Privilege
+#define NVIC_CPAC_CP10_DIS 0x00000000 // Access Denied
+#define NVIC_CPAC_CP10_PRIV 0x00100000 // Privileged Access Only
+#define NVIC_CPAC_CP10_FULL 0x00300000 // Full Access
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_TYPE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_TYPE_IREGION_M 0x00FF0000 // Number of I Regions
+#define NVIC_MPU_TYPE_DREGION_M 0x0000FF00 // Number of D Regions
+#define NVIC_MPU_TYPE_SEPARATE 0x00000001 // Separate or Unified MPU
+#define NVIC_MPU_TYPE_IREGION_S 16
+#define NVIC_MPU_TYPE_DREGION_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_MPU_CTRL_PRIVDEFEN 0x00000004 // MPU Default Region
+#define NVIC_MPU_CTRL_HFNMIENA 0x00000002 // MPU Enabled During Faults
+#define NVIC_MPU_CTRL_ENABLE 0x00000001 // MPU Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_NUMBER
+// register.
+//
+//*****************************************************************************
+#define NVIC_MPU_NUMBER_M 0x00000007 // MPU Region to Access
+#define NVIC_MPU_NUMBER_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE_ADDR_M 0xFFFFFFE0 // Base Address Mask
+#define NVIC_MPU_BASE_VALID 0x00000010 // Region Number Valid
+#define NVIC_MPU_BASE_REGION_M 0x00000007 // Region Number
+#define NVIC_MPU_BASE_ADDR_S 5
+#define NVIC_MPU_BASE_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR_XN 0x10000000 // Instruction Access Disable
+#define NVIC_MPU_ATTR_AP_M 0x07000000 // Access Privilege
+#define NVIC_MPU_ATTR_AP_NO_NO 0x00000000 // prv: no access, usr: no access
+#define NVIC_MPU_ATTR_AP_RW_NO 0x01000000 // prv: rw, usr: none
+#define NVIC_MPU_ATTR_AP_RW_RO 0x02000000 // prv: rw, usr: read-only
+#define NVIC_MPU_ATTR_AP_RW_RW 0x03000000 // prv: rw, usr: rw
+#define NVIC_MPU_ATTR_AP_RO_NO 0x05000000 // prv: ro, usr: none
+#define NVIC_MPU_ATTR_AP_RO_RO 0x06000000 // prv: ro, usr: ro
+#define NVIC_MPU_ATTR_TEX_M 0x00380000 // Type Extension Mask
+#define NVIC_MPU_ATTR_SHAREABLE 0x00040000 // Shareable
+#define NVIC_MPU_ATTR_CACHEABLE 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR_BUFFRABLE 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR_SRD_M 0x0000FF00 // Subregion Disable Bits
+#define NVIC_MPU_ATTR_SRD_0 0x00000100 // Sub-region 0 disable
+#define NVIC_MPU_ATTR_SRD_1 0x00000200 // Sub-region 1 disable
+#define NVIC_MPU_ATTR_SRD_2 0x00000400 // Sub-region 2 disable
+#define NVIC_MPU_ATTR_SRD_3 0x00000800 // Sub-region 3 disable
+#define NVIC_MPU_ATTR_SRD_4 0x00001000 // Sub-region 4 disable
+#define NVIC_MPU_ATTR_SRD_5 0x00002000 // Sub-region 5 disable
+#define NVIC_MPU_ATTR_SRD_6 0x00004000 // Sub-region 6 disable
+#define NVIC_MPU_ATTR_SRD_7 0x00008000 // Sub-region 7 disable
+#define NVIC_MPU_ATTR_SIZE_M 0x0000003E // Region Size Mask
+#define NVIC_MPU_ATTR_SIZE_32B 0x00000008 // Region size 32 bytes
+#define NVIC_MPU_ATTR_SIZE_64B 0x0000000A // Region size 64 bytes
+#define NVIC_MPU_ATTR_SIZE_128B 0x0000000C // Region size 128 bytes
+#define NVIC_MPU_ATTR_SIZE_256B 0x0000000E // Region size 256 bytes
+#define NVIC_MPU_ATTR_SIZE_512B 0x00000010 // Region size 512 bytes
+#define NVIC_MPU_ATTR_SIZE_1K 0x00000012 // Region size 1 Kbytes
+#define NVIC_MPU_ATTR_SIZE_2K 0x00000014 // Region size 2 Kbytes
+#define NVIC_MPU_ATTR_SIZE_4K 0x00000016 // Region size 4 Kbytes
+#define NVIC_MPU_ATTR_SIZE_8K 0x00000018 // Region size 8 Kbytes
+#define NVIC_MPU_ATTR_SIZE_16K 0x0000001A // Region size 16 Kbytes
+#define NVIC_MPU_ATTR_SIZE_32K 0x0000001C // Region size 32 Kbytes
+#define NVIC_MPU_ATTR_SIZE_64K 0x0000001E // Region size 64 Kbytes
+#define NVIC_MPU_ATTR_SIZE_128K 0x00000020 // Region size 128 Kbytes
+#define NVIC_MPU_ATTR_SIZE_256K 0x00000022 // Region size 256 Kbytes
+#define NVIC_MPU_ATTR_SIZE_512K 0x00000024 // Region size 512 Kbytes
+#define NVIC_MPU_ATTR_SIZE_1M 0x00000026 // Region size 1 Mbytes
+#define NVIC_MPU_ATTR_SIZE_2M 0x00000028 // Region size 2 Mbytes
+#define NVIC_MPU_ATTR_SIZE_4M 0x0000002A // Region size 4 Mbytes
+#define NVIC_MPU_ATTR_SIZE_8M 0x0000002C // Region size 8 Mbytes
+#define NVIC_MPU_ATTR_SIZE_16M 0x0000002E // Region size 16 Mbytes
+#define NVIC_MPU_ATTR_SIZE_32M 0x00000030 // Region size 32 Mbytes
+#define NVIC_MPU_ATTR_SIZE_64M 0x00000032 // Region size 64 Mbytes
+#define NVIC_MPU_ATTR_SIZE_128M 0x00000034 // Region size 128 Mbytes
+#define NVIC_MPU_ATTR_SIZE_256M 0x00000036 // Region size 256 Mbytes
+#define NVIC_MPU_ATTR_SIZE_512M 0x00000038 // Region size 512 Mbytes
+#define NVIC_MPU_ATTR_SIZE_1G 0x0000003A // Region size 1 Gbytes
+#define NVIC_MPU_ATTR_SIZE_2G 0x0000003C // Region size 2 Gbytes
+#define NVIC_MPU_ATTR_SIZE_4G 0x0000003E // Region size 4 Gbytes
+#define NVIC_MPU_ATTR_ENABLE 0x00000001 // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE1 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE1_ADDR_M 0xFFFFFFE0 // Base Address Mask
+#define NVIC_MPU_BASE1_VALID 0x00000010 // Region Number Valid
+#define NVIC_MPU_BASE1_REGION_M 0x00000007 // Region Number
+#define NVIC_MPU_BASE1_ADDR_S 5
+#define NVIC_MPU_BASE1_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR1 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR1_XN 0x10000000 // Instruction Access Disable
+#define NVIC_MPU_ATTR1_AP_M 0x07000000 // Access Privilege
+#define NVIC_MPU_ATTR1_TEX_M 0x00380000 // Type Extension Mask
+#define NVIC_MPU_ATTR1_SHAREABLE \
+ 0x00040000 // Shareable
+#define NVIC_MPU_ATTR1_CACHEABLE \
+ 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR1_BUFFRABLE \
+ 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR1_SRD_M 0x0000FF00 // Subregion Disable Bits
+#define NVIC_MPU_ATTR1_SIZE_M 0x0000003E // Region Size Mask
+#define NVIC_MPU_ATTR1_ENABLE 0x00000001 // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE2 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE2_ADDR_M 0xFFFFFFE0 // Base Address Mask
+#define NVIC_MPU_BASE2_VALID 0x00000010 // Region Number Valid
+#define NVIC_MPU_BASE2_REGION_M 0x00000007 // Region Number
+#define NVIC_MPU_BASE2_ADDR_S 5
+#define NVIC_MPU_BASE2_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR2 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR2_XN 0x10000000 // Instruction Access Disable
+#define NVIC_MPU_ATTR2_AP_M 0x07000000 // Access Privilege
+#define NVIC_MPU_ATTR2_TEX_M 0x00380000 // Type Extension Mask
+#define NVIC_MPU_ATTR2_SHAREABLE \
+ 0x00040000 // Shareable
+#define NVIC_MPU_ATTR2_CACHEABLE \
+ 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR2_BUFFRABLE \
+ 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR2_SRD_M 0x0000FF00 // Subregion Disable Bits
+#define NVIC_MPU_ATTR2_SIZE_M 0x0000003E // Region Size Mask
+#define NVIC_MPU_ATTR2_ENABLE 0x00000001 // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_BASE3 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_BASE3_ADDR_M 0xFFFFFFE0 // Base Address Mask
+#define NVIC_MPU_BASE3_VALID 0x00000010 // Region Number Valid
+#define NVIC_MPU_BASE3_REGION_M 0x00000007 // Region Number
+#define NVIC_MPU_BASE3_ADDR_S 5
+#define NVIC_MPU_BASE3_REGION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_MPU_ATTR3 register.
+//
+//*****************************************************************************
+#define NVIC_MPU_ATTR3_XN 0x10000000 // Instruction Access Disable
+#define NVIC_MPU_ATTR3_AP_M 0x07000000 // Access Privilege
+#define NVIC_MPU_ATTR3_TEX_M 0x00380000 // Type Extension Mask
+#define NVIC_MPU_ATTR3_SHAREABLE \
+ 0x00040000 // Shareable
+#define NVIC_MPU_ATTR3_CACHEABLE \
+ 0x00020000 // Cacheable
+#define NVIC_MPU_ATTR3_BUFFRABLE \
+ 0x00010000 // Bufferable
+#define NVIC_MPU_ATTR3_SRD_M 0x0000FF00 // Subregion Disable Bits
+#define NVIC_MPU_ATTR3_SIZE_M 0x0000003E // Region Size Mask
+#define NVIC_MPU_ATTR3_ENABLE 0x00000001 // Region Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_CTRL register.
+//
+//*****************************************************************************
+#define NVIC_DBG_CTRL_DBGKEY_M 0xFFFF0000 // Debug key mask
+#define NVIC_DBG_CTRL_DBGKEY 0xA05F0000 // Debug key
+#define NVIC_DBG_CTRL_S_RESET_ST \
+ 0x02000000 // Core has reset since last read
+#define NVIC_DBG_CTRL_S_RETIRE_ST \
+ 0x01000000 // Core has executed insruction
+ // since last read
+#define NVIC_DBG_CTRL_S_LOCKUP 0x00080000 // Core is locked up
+#define NVIC_DBG_CTRL_S_SLEEP 0x00040000 // Core is sleeping
+#define NVIC_DBG_CTRL_S_HALT 0x00020000 // Core status on halt
+#define NVIC_DBG_CTRL_S_REGRDY 0x00010000 // Register read/write available
+#define NVIC_DBG_CTRL_C_SNAPSTALL \
+ 0x00000020 // Breaks a stalled load/store
+#define NVIC_DBG_CTRL_C_MASKINT 0x00000008 // Mask interrupts when stepping
+#define NVIC_DBG_CTRL_C_STEP 0x00000004 // Step the core
+#define NVIC_DBG_CTRL_C_HALT 0x00000002 // Halt the core
+#define NVIC_DBG_CTRL_C_DEBUGEN 0x00000001 // Enable debug
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_XFER register.
+//
+//*****************************************************************************
+#define NVIC_DBG_XFER_REG_WNR 0x00010000 // Write or not read
+#define NVIC_DBG_XFER_REG_SEL_M 0x0000001F // Register
+#define NVIC_DBG_XFER_REG_R0 0x00000000 // Register R0
+#define NVIC_DBG_XFER_REG_R1 0x00000001 // Register R1
+#define NVIC_DBG_XFER_REG_R2 0x00000002 // Register R2
+#define NVIC_DBG_XFER_REG_R3 0x00000003 // Register R3
+#define NVIC_DBG_XFER_REG_R4 0x00000004 // Register R4
+#define NVIC_DBG_XFER_REG_R5 0x00000005 // Register R5
+#define NVIC_DBG_XFER_REG_R6 0x00000006 // Register R6
+#define NVIC_DBG_XFER_REG_R7 0x00000007 // Register R7
+#define NVIC_DBG_XFER_REG_R8 0x00000008 // Register R8
+#define NVIC_DBG_XFER_REG_R9 0x00000009 // Register R9
+#define NVIC_DBG_XFER_REG_R10 0x0000000A // Register R10
+#define NVIC_DBG_XFER_REG_R11 0x0000000B // Register R11
+#define NVIC_DBG_XFER_REG_R12 0x0000000C // Register R12
+#define NVIC_DBG_XFER_REG_R13 0x0000000D // Register R13
+#define NVIC_DBG_XFER_REG_R14 0x0000000E // Register R14
+#define NVIC_DBG_XFER_REG_R15 0x0000000F // Register R15
+#define NVIC_DBG_XFER_REG_FLAGS 0x00000010 // xPSR/Flags register
+#define NVIC_DBG_XFER_REG_MSP 0x00000011 // Main SP
+#define NVIC_DBG_XFER_REG_PSP 0x00000012 // Process SP
+#define NVIC_DBG_XFER_REG_DSP 0x00000013 // Deep SP
+#define NVIC_DBG_XFER_REG_CFBP 0x00000014 // Control/Fault/BasePri/PriMask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_DATA register.
+//
+//*****************************************************************************
+#define NVIC_DBG_DATA_M 0xFFFFFFFF // Data temporary cache
+#define NVIC_DBG_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_DBG_INT register.
+//
+//*****************************************************************************
+#define NVIC_DBG_INT_HARDERR 0x00000400 // Debug trap on hard fault
+#define NVIC_DBG_INT_INTERR 0x00000200 // Debug trap on interrupt errors
+#define NVIC_DBG_INT_BUSERR 0x00000100 // Debug trap on bus error
+#define NVIC_DBG_INT_STATERR 0x00000080 // Debug trap on usage fault state
+#define NVIC_DBG_INT_CHKERR 0x00000040 // Debug trap on usage fault check
+#define NVIC_DBG_INT_NOCPERR 0x00000020 // Debug trap on coprocessor error
+#define NVIC_DBG_INT_MMERR 0x00000010 // Debug trap on mem manage fault
+#define NVIC_DBG_INT_RESET 0x00000008 // Core reset status
+#define NVIC_DBG_INT_RSTPENDCLR 0x00000004 // Clear pending core reset
+#define NVIC_DBG_INT_RSTPENDING 0x00000002 // Core reset is pending
+#define NVIC_DBG_INT_RSTVCATCH 0x00000001 // Reset vector catch
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_SW_TRIG register.
+//
+//*****************************************************************************
+#define NVIC_SW_TRIG_INTID_M 0x000000FF // Interrupt ID
+#define NVIC_SW_TRIG_INTID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FPCC register.
+//
+//*****************************************************************************
+#define NVIC_FPCC_ASPEN 0x80000000 // Automatic State Preservation
+ // Enable
+#define NVIC_FPCC_LSPEN 0x40000000 // Lazy State Preservation Enable
+#define NVIC_FPCC_MONRDY 0x00000100 // Monitor Ready
+#define NVIC_FPCC_BFRDY 0x00000040 // Bus Fault Ready
+#define NVIC_FPCC_MMRDY 0x00000020 // Memory Management Fault Ready
+#define NVIC_FPCC_HFRDY 0x00000010 // Hard Fault Ready
+#define NVIC_FPCC_THREAD 0x00000008 // Thread Mode
+#define NVIC_FPCC_USER 0x00000002 // User Privilege Level
+#define NVIC_FPCC_LSPACT 0x00000001 // Lazy State Preservation Active
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FPCA register.
+//
+//*****************************************************************************
+#define NVIC_FPCA_ADDRESS_M 0xFFFFFFF8 // Address
+#define NVIC_FPCA_ADDRESS_S 3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the NVIC_FPDSC register.
+//
+//*****************************************************************************
+#define NVIC_FPDSC_AHP 0x04000000 // AHP Bit Default
+#define NVIC_FPDSC_DN 0x02000000 // DN Bit Default
+#define NVIC_FPDSC_FZ 0x01000000 // FZ Bit Default
+#define NVIC_FPDSC_RMODE_M 0x00C00000 // RMODE Bit Default
+#define NVIC_FPDSC_RMODE_RN 0x00000000 // Round to Nearest (RN) mode
+#define NVIC_FPDSC_RMODE_RP 0x00400000 // Round towards Plus Infinity (RP)
+ // mode
+#define NVIC_FPDSC_RMODE_RM 0x00800000 // Round towards Minus Infinity
+ // (RM) mode
+#define NVIC_FPDSC_RMODE_RZ 0x00C00000 // Round towards Zero (RZ) mode
+
+#endif // __HW_NVIC_H__
diff --git a/os/common/ext/TivaWare/inc/hw_onewire.h b/os/common/ext/TivaWare/inc/hw_onewire.h
new file mode 100644
index 0000000..8910a7d
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_onewire.h
@@ -0,0 +1,223 @@
+//*****************************************************************************
+//
+// hw_onewire.h - Macros used when accessing the One wire hardware.
+//
+// Copyright (c) 2012-2016 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_ONEWIRE_H__
+#define __HW_ONEWIRE_H__
+
+//*****************************************************************************
+//
+// The following are defines for the One wire register offsets.
+//
+//*****************************************************************************
+#define ONEWIRE_O_CS 0x00000000 // 1-Wire Control and Status
+#define ONEWIRE_O_TIM 0x00000004 // 1-Wire Timing Override
+#define ONEWIRE_O_DATW 0x00000008 // 1-Wire Data Write
+#define ONEWIRE_O_DATR 0x0000000C // 1-Wire Data Read
+#define ONEWIRE_O_IM 0x00000100 // 1-Wire Interrupt Mask
+#define ONEWIRE_O_RIS 0x00000104 // 1-Wire Raw Interrupt Status
+#define ONEWIRE_O_MIS 0x00000108 // 1-Wire Masked Interrupt Status
+#define ONEWIRE_O_ICR 0x0000010C // 1-Wire Interrupt Clear
+#define ONEWIRE_O_DMA 0x00000120 // 1-Wire uDMA Control
+#define ONEWIRE_O_PP 0x00000FC0 // 1-Wire Peripheral Properties
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ONEWIRE_O_CS register.
+//
+//*****************************************************************************
+#define ONEWIRE_CS_USEALT 0x80000000 // Two Wire Enable
+#define ONEWIRE_CS_ALTP 0x40000000 // Alternate Polarity Enable
+#define ONEWIRE_CS_BSIZE_M 0x00070000 // Last Byte Size
+#define ONEWIRE_CS_BSIZE_8 0x00000000 // 8 bits (1 byte)
+#define ONEWIRE_CS_BSIZE_1 0x00010000 // 1 bit
+#define ONEWIRE_CS_BSIZE_2 0x00020000 // 2 bits
+#define ONEWIRE_CS_BSIZE_3 0x00030000 // 3 bits
+#define ONEWIRE_CS_BSIZE_4 0x00040000 // 4 bits
+#define ONEWIRE_CS_BSIZE_5 0x00050000 // 5 bits
+#define ONEWIRE_CS_BSIZE_6 0x00060000 // 6 bits
+#define ONEWIRE_CS_BSIZE_7 0x00070000 // 7 bits
+#define ONEWIRE_CS_STUCK 0x00000400 // STUCK Status
+#define ONEWIRE_CS_NOATR 0x00000200 // Answer-to-Reset Status
+#define ONEWIRE_CS_BUSY 0x00000100 // Busy Status
+#define ONEWIRE_CS_SKATR 0x00000080 // Skip Answer-to-Reset Enable
+#define ONEWIRE_CS_LSAM 0x00000040 // Late Sample Enable
+#define ONEWIRE_CS_ODRV 0x00000020 // Overdrive Enable
+#define ONEWIRE_CS_SZ_M 0x00000018 // Data Operation Size
+#define ONEWIRE_CS_OP_M 0x00000006 // Operation Request
+#define ONEWIRE_CS_OP_NONE 0x00000000 // No operation
+#define ONEWIRE_CS_OP_RD 0x00000002 // Read
+#define ONEWIRE_CS_OP_WR 0x00000004 // Write
+#define ONEWIRE_CS_OP_WRRD 0x00000006 // Write/Read
+#define ONEWIRE_CS_RST 0x00000001 // Reset Request
+#define ONEWIRE_CS_SZ_S 3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ONEWIRE_O_TIM register.
+//
+//*****************************************************************************
+#define ONEWIRE_TIM_W1TIM_M 0xF0000000 // Value '1' Timing
+#define ONEWIRE_TIM_W0TIM_M 0x0F800000 // Value '0' Timing
+#define ONEWIRE_TIM_W0REST_M 0x00780000 // Rest Time
+#define ONEWIRE_TIM_W1SAM_M 0x00078000 // Sample Time
+#define ONEWIRE_TIM_ATRSAM_M 0x00007800 // Answer-to-Reset Sample
+#define ONEWIRE_TIM_ATRTIM_M 0x000007C0 // Answer-to-Reset/Rest Period
+#define ONEWIRE_TIM_RSTTIM_M 0x0000003F // Reset Low Time
+#define ONEWIRE_TIM_W1TIM_S 28
+#define ONEWIRE_TIM_W0TIM_S 23
+#define ONEWIRE_TIM_W0REST_S 19
+#define ONEWIRE_TIM_W1SAM_S 15
+#define ONEWIRE_TIM_ATRSAM_S 11
+#define ONEWIRE_TIM_ATRTIM_S 6
+#define ONEWIRE_TIM_RSTTIM_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ONEWIRE_O_DATW register.
+//
+//*****************************************************************************
+#define ONEWIRE_DATW_B3_M 0xFF000000 // Upper Data Byte
+#define ONEWIRE_DATW_B2_M 0x00FF0000 // Upper Middle Data Byte
+#define ONEWIRE_DATW_B1_M 0x0000FF00 // Lower Middle Data Byte
+#define ONEWIRE_DATW_B0_M 0x000000FF // Lowest Data Byte
+#define ONEWIRE_DATW_B3_S 24
+#define ONEWIRE_DATW_B2_S 16
+#define ONEWIRE_DATW_B1_S 8
+#define ONEWIRE_DATW_B0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ONEWIRE_O_DATR register.
+//
+//*****************************************************************************
+#define ONEWIRE_DATR_B3_M 0xFF000000 // Upper Data Byte
+#define ONEWIRE_DATR_B2_M 0x00FF0000 // Upper Middle Data Byte
+#define ONEWIRE_DATR_B1_M 0x0000FF00 // Lower Middle Data Byte
+#define ONEWIRE_DATR_B0_M 0x000000FF // Lowest Data Byte
+#define ONEWIRE_DATR_B3_S 24
+#define ONEWIRE_DATR_B2_S 16
+#define ONEWIRE_DATR_B1_S 8
+#define ONEWIRE_DATR_B0_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ONEWIRE_O_IM register.
+//
+//*****************************************************************************
+#define ONEWIRE_IM_DMA 0x00000010 // DMA Done Interrupt Mask
+#define ONEWIRE_IM_STUCK 0x00000008 // Stuck Status Interrupt Mask
+#define ONEWIRE_IM_NOATR 0x00000004 // No Answer-to-Reset Interrupt
+ // Mask
+#define ONEWIRE_IM_OPC 0x00000002 // Operation Complete Interrupt
+ // Mask
+#define ONEWIRE_IM_RST 0x00000001 // Reset Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ONEWIRE_O_RIS register.
+//
+//*****************************************************************************
+#define ONEWIRE_RIS_DMA 0x00000010 // DMA Done Raw Interrupt Status
+#define ONEWIRE_RIS_STUCK 0x00000008 // Stuck Status Raw Interrupt
+ // Status
+#define ONEWIRE_RIS_NOATR 0x00000004 // No Answer-to-Reset Raw Interrupt
+ // Status
+#define ONEWIRE_RIS_OPC 0x00000002 // Operation Complete Raw Interrupt
+ // Status
+#define ONEWIRE_RIS_RST 0x00000001 // Reset Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ONEWIRE_O_MIS register.
+//
+//*****************************************************************************
+#define ONEWIRE_MIS_DMA 0x00000010 // DMA Done Masked Interrupt Status
+#define ONEWIRE_MIS_STUCK 0x00000008 // Stuck Status Masked Interrupt
+ // Status
+#define ONEWIRE_MIS_NOATR 0x00000004 // No Answer-to-Reset Masked
+ // Interrupt Status
+#define ONEWIRE_MIS_OPC 0x00000002 // Operation Complete Masked
+ // Interrupt Status
+#define ONEWIRE_MIS_RST 0x00000001 // Reset Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ONEWIRE_O_ICR register.
+//
+//*****************************************************************************
+#define ONEWIRE_ICR_DMA 0x00000010 // DMA Done Interrupt Clear
+#define ONEWIRE_ICR_STUCK 0x00000008 // Stuck Status Interrupt Clear
+#define ONEWIRE_ICR_NOATR 0x00000004 // No Answer-to-Reset Interrupt
+ // Clear
+#define ONEWIRE_ICR_OPC 0x00000002 // Operation Complete Interrupt
+ // Clear
+#define ONEWIRE_ICR_RST 0x00000001 // Reset Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ONEWIRE_O_DMA register.
+//
+//*****************************************************************************
+#define ONEWIRE_DMA_SG 0x00000008 // Scatter-Gather Enable
+#define ONEWIRE_DMA_DMAOP_M 0x00000006 // uDMA Operation
+#define ONEWIRE_DMA_DMAOP_DIS 0x00000000 // uDMA disabled
+#define ONEWIRE_DMA_DMAOP_RDSNG 0x00000002 // uDMA single read: 1-Wire
+ // requests uDMA to read
+ // ONEWIREDATR register after each
+ // read transaction
+#define ONEWIRE_DMA_DMAOP_WRMUL 0x00000004 // uDMA multiple write: 1-Wire
+ // requests uDMA to load whenever
+ // the ONEWIREDATW register is
+ // empty
+#define ONEWIRE_DMA_DMAOP_RDMUL 0x00000006 // uDMA multiple read: An initial
+ // read occurs and subsequent reads
+ // start after uDMA has read the
+ // ONEWIREDATR register
+#define ONEWIRE_DMA_RST 0x00000001 // uDMA Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the ONEWIRE_O_PP register.
+//
+//*****************************************************************************
+#define ONEWIRE_PP_DMAP 0x00000010 // uDMA Present
+#define ONEWIRE_PP_CNT_M 0x00000003 // 1-Wire Bus Count
+#define ONEWIRE_PP_CNT_S 0
+
+#endif // __HW_ONEWIRE_H__
diff --git a/os/common/ext/TivaWare/inc/hw_pwm.h b/os/common/ext/TivaWare/inc/hw_pwm.h
new file mode 100644
index 0000000..00d42bf
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_pwm.h
@@ -0,0 +1,1885 @@
+//*****************************************************************************
+//
+// hw_pwm.h - Defines and Macros for Pulse Width Modulation (PWM) ports.
+//
+// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_PWM_H__
+#define __HW_PWM_H__
+
+//*****************************************************************************
+//
+// The following are defines for the PWM register offsets.
+//
+//*****************************************************************************
+#define PWM_O_CTL 0x00000000 // PWM Master Control
+#define PWM_O_SYNC 0x00000004 // PWM Time Base Sync
+#define PWM_O_ENABLE 0x00000008 // PWM Output Enable
+#define PWM_O_INVERT 0x0000000C // PWM Output Inversion
+#define PWM_O_FAULT 0x00000010 // PWM Output Fault
+#define PWM_O_INTEN 0x00000014 // PWM Interrupt Enable
+#define PWM_O_RIS 0x00000018 // PWM Raw Interrupt Status
+#define PWM_O_ISC 0x0000001C // PWM Interrupt Status and Clear
+#define PWM_O_STATUS 0x00000020 // PWM Status
+#define PWM_O_FAULTVAL 0x00000024 // PWM Fault Condition Value
+#define PWM_O_ENUPD 0x00000028 // PWM Enable Update
+#define PWM_O_0_CTL 0x00000040 // PWM0 Control
+#define PWM_O_0_INTEN 0x00000044 // PWM0 Interrupt and Trigger
+ // Enable
+#define PWM_O_0_RIS 0x00000048 // PWM0 Raw Interrupt Status
+#define PWM_O_0_ISC 0x0000004C // PWM0 Interrupt Status and Clear
+#define PWM_O_0_LOAD 0x00000050 // PWM0 Load
+#define PWM_O_0_COUNT 0x00000054 // PWM0 Counter
+#define PWM_O_0_CMPA 0x00000058 // PWM0 Compare A
+#define PWM_O_0_CMPB 0x0000005C // PWM0 Compare B
+#define PWM_O_0_GENA 0x00000060 // PWM0 Generator A Control
+#define PWM_O_0_GENB 0x00000064 // PWM0 Generator B Control
+#define PWM_O_0_DBCTL 0x00000068 // PWM0 Dead-Band Control
+#define PWM_O_0_DBRISE 0x0000006C // PWM0 Dead-Band Rising-Edge Delay
+#define PWM_O_0_DBFALL 0x00000070 // PWM0 Dead-Band
+ // Falling-Edge-Delay
+#define PWM_O_0_FLTSRC0 0x00000074 // PWM0 Fault Source 0
+#define PWM_O_0_FLTSRC1 0x00000078 // PWM0 Fault Source 1
+#define PWM_O_0_MINFLTPER 0x0000007C // PWM0 Minimum Fault Period
+#define PWM_O_1_CTL 0x00000080 // PWM1 Control
+#define PWM_O_1_INTEN 0x00000084 // PWM1 Interrupt and Trigger
+ // Enable
+#define PWM_O_1_RIS 0x00000088 // PWM1 Raw Interrupt Status
+#define PWM_O_1_ISC 0x0000008C // PWM1 Interrupt Status and Clear
+#define PWM_O_1_LOAD 0x00000090 // PWM1 Load
+#define PWM_O_1_COUNT 0x00000094 // PWM1 Counter
+#define PWM_O_1_CMPA 0x00000098 // PWM1 Compare A
+#define PWM_O_1_CMPB 0x0000009C // PWM1 Compare B
+#define PWM_O_1_GENA 0x000000A0 // PWM1 Generator A Control
+#define PWM_O_1_GENB 0x000000A4 // PWM1 Generator B Control
+#define PWM_O_1_DBCTL 0x000000A8 // PWM1 Dead-Band Control
+#define PWM_O_1_DBRISE 0x000000AC // PWM1 Dead-Band Rising-Edge Delay
+#define PWM_O_1_DBFALL 0x000000B0 // PWM1 Dead-Band
+ // Falling-Edge-Delay
+#define PWM_O_1_FLTSRC0 0x000000B4 // PWM1 Fault Source 0
+#define PWM_O_1_FLTSRC1 0x000000B8 // PWM1 Fault Source 1
+#define PWM_O_1_MINFLTPER 0x000000BC // PWM1 Minimum Fault Period
+#define PWM_O_2_CTL 0x000000C0 // PWM2 Control
+#define PWM_O_2_INTEN 0x000000C4 // PWM2 Interrupt and Trigger
+ // Enable
+#define PWM_O_2_RIS 0x000000C8 // PWM2 Raw Interrupt Status
+#define PWM_O_2_ISC 0x000000CC // PWM2 Interrupt Status and Clear
+#define PWM_O_2_LOAD 0x000000D0 // PWM2 Load
+#define PWM_O_2_COUNT 0x000000D4 // PWM2 Counter
+#define PWM_O_2_CMPA 0x000000D8 // PWM2 Compare A
+#define PWM_O_2_CMPB 0x000000DC // PWM2 Compare B
+#define PWM_O_2_GENA 0x000000E0 // PWM2 Generator A Control
+#define PWM_O_2_GENB 0x000000E4 // PWM2 Generator B Control
+#define PWM_O_2_DBCTL 0x000000E8 // PWM2 Dead-Band Control
+#define PWM_O_2_DBRISE 0x000000EC // PWM2 Dead-Band Rising-Edge Delay
+#define PWM_O_2_DBFALL 0x000000F0 // PWM2 Dead-Band
+ // Falling-Edge-Delay
+#define PWM_O_2_FLTSRC0 0x000000F4 // PWM2 Fault Source 0
+#define PWM_O_2_FLTSRC1 0x000000F8 // PWM2 Fault Source 1
+#define PWM_O_2_MINFLTPER 0x000000FC // PWM2 Minimum Fault Period
+#define PWM_O_3_CTL 0x00000100 // PWM3 Control
+#define PWM_O_3_INTEN 0x00000104 // PWM3 Interrupt and Trigger
+ // Enable
+#define PWM_O_3_RIS 0x00000108 // PWM3 Raw Interrupt Status
+#define PWM_O_3_ISC 0x0000010C // PWM3 Interrupt Status and Clear
+#define PWM_O_3_LOAD 0x00000110 // PWM3 Load
+#define PWM_O_3_COUNT 0x00000114 // PWM3 Counter
+#define PWM_O_3_CMPA 0x00000118 // PWM3 Compare A
+#define PWM_O_3_CMPB 0x0000011C // PWM3 Compare B
+#define PWM_O_3_GENA 0x00000120 // PWM3 Generator A Control
+#define PWM_O_3_GENB 0x00000124 // PWM3 Generator B Control
+#define PWM_O_3_DBCTL 0x00000128 // PWM3 Dead-Band Control
+#define PWM_O_3_DBRISE 0x0000012C // PWM3 Dead-Band Rising-Edge Delay
+#define PWM_O_3_DBFALL 0x00000130 // PWM3 Dead-Band
+ // Falling-Edge-Delay
+#define PWM_O_3_FLTSRC0 0x00000134 // PWM3 Fault Source 0
+#define PWM_O_3_FLTSRC1 0x00000138 // PWM3 Fault Source 1
+#define PWM_O_3_MINFLTPER 0x0000013C // PWM3 Minimum Fault Period
+#define PWM_O_0_FLTSEN 0x00000800 // PWM0 Fault Pin Logic Sense
+#define PWM_O_0_FLTSTAT0 0x00000804 // PWM0 Fault Status 0
+#define PWM_O_0_FLTSTAT1 0x00000808 // PWM0 Fault Status 1
+#define PWM_O_1_FLTSEN 0x00000880 // PWM1 Fault Pin Logic Sense
+#define PWM_O_1_FLTSTAT0 0x00000884 // PWM1 Fault Status 0
+#define PWM_O_1_FLTSTAT1 0x00000888 // PWM1 Fault Status 1
+#define PWM_O_2_FLTSEN 0x00000900 // PWM2 Fault Pin Logic Sense
+#define PWM_O_2_FLTSTAT0 0x00000904 // PWM2 Fault Status 0
+#define PWM_O_2_FLTSTAT1 0x00000908 // PWM2 Fault Status 1
+#define PWM_O_3_FLTSEN 0x00000980 // PWM3 Fault Pin Logic Sense
+#define PWM_O_3_FLTSTAT0 0x00000984 // PWM3 Fault Status 0
+#define PWM_O_3_FLTSTAT1 0x00000988 // PWM3 Fault Status 1
+#define PWM_O_PP 0x00000FC0 // PWM Peripheral Properties
+#define PWM_O_CC 0x00000FC8 // PWM Clock Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_CTL register.
+//
+//*****************************************************************************
+#define PWM_CTL_GLOBALSYNC3 0x00000008 // Update PWM Generator 3
+#define PWM_CTL_GLOBALSYNC2 0x00000004 // Update PWM Generator 2
+#define PWM_CTL_GLOBALSYNC1 0x00000002 // Update PWM Generator 1
+#define PWM_CTL_GLOBALSYNC0 0x00000001 // Update PWM Generator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_SYNC register.
+//
+//*****************************************************************************
+#define PWM_SYNC_SYNC3 0x00000008 // Reset Generator 3 Counter
+#define PWM_SYNC_SYNC2 0x00000004 // Reset Generator 2 Counter
+#define PWM_SYNC_SYNC1 0x00000002 // Reset Generator 1 Counter
+#define PWM_SYNC_SYNC0 0x00000001 // Reset Generator 0 Counter
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ENABLE register.
+//
+//*****************************************************************************
+#define PWM_ENABLE_PWM7EN 0x00000080 // MnPWM7 Output Enable
+#define PWM_ENABLE_PWM6EN 0x00000040 // MnPWM6 Output Enable
+#define PWM_ENABLE_PWM5EN 0x00000020 // MnPWM5 Output Enable
+#define PWM_ENABLE_PWM4EN 0x00000010 // MnPWM4 Output Enable
+#define PWM_ENABLE_PWM3EN 0x00000008 // MnPWM3 Output Enable
+#define PWM_ENABLE_PWM2EN 0x00000004 // MnPWM2 Output Enable
+#define PWM_ENABLE_PWM1EN 0x00000002 // MnPWM1 Output Enable
+#define PWM_ENABLE_PWM0EN 0x00000001 // MnPWM0 Output Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_INVERT register.
+//
+//*****************************************************************************
+#define PWM_INVERT_PWM7INV 0x00000080 // Invert MnPWM7 Signal
+#define PWM_INVERT_PWM6INV 0x00000040 // Invert MnPWM6 Signal
+#define PWM_INVERT_PWM5INV 0x00000020 // Invert MnPWM5 Signal
+#define PWM_INVERT_PWM4INV 0x00000010 // Invert MnPWM4 Signal
+#define PWM_INVERT_PWM3INV 0x00000008 // Invert MnPWM3 Signal
+#define PWM_INVERT_PWM2INV 0x00000004 // Invert MnPWM2 Signal
+#define PWM_INVERT_PWM1INV 0x00000002 // Invert MnPWM1 Signal
+#define PWM_INVERT_PWM0INV 0x00000001 // Invert MnPWM0 Signal
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_FAULT register.
+//
+//*****************************************************************************
+#define PWM_FAULT_FAULT7 0x00000080 // MnPWM7 Fault
+#define PWM_FAULT_FAULT6 0x00000040 // MnPWM6 Fault
+#define PWM_FAULT_FAULT5 0x00000020 // MnPWM5 Fault
+#define PWM_FAULT_FAULT4 0x00000010 // MnPWM4 Fault
+#define PWM_FAULT_FAULT3 0x00000008 // MnPWM3 Fault
+#define PWM_FAULT_FAULT2 0x00000004 // MnPWM2 Fault
+#define PWM_FAULT_FAULT1 0x00000002 // MnPWM1 Fault
+#define PWM_FAULT_FAULT0 0x00000001 // MnPWM0 Fault
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_INTEN register.
+//
+//*****************************************************************************
+#define PWM_INTEN_INTFAULT3 0x00080000 // Interrupt Fault 3
+#define PWM_INTEN_INTFAULT2 0x00040000 // Interrupt Fault 2
+#define PWM_INTEN_INTFAULT1 0x00020000 // Interrupt Fault 1
+#define PWM_INTEN_INTFAULT0 0x00010000 // Interrupt Fault 0
+#define PWM_INTEN_INTPWM3 0x00000008 // PWM3 Interrupt Enable
+#define PWM_INTEN_INTPWM2 0x00000004 // PWM2 Interrupt Enable
+#define PWM_INTEN_INTPWM1 0x00000002 // PWM1 Interrupt Enable
+#define PWM_INTEN_INTPWM0 0x00000001 // PWM0 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_RIS register.
+//
+//*****************************************************************************
+#define PWM_RIS_INTFAULT3 0x00080000 // Interrupt Fault PWM 3
+#define PWM_RIS_INTFAULT2 0x00040000 // Interrupt Fault PWM 2
+#define PWM_RIS_INTFAULT1 0x00020000 // Interrupt Fault PWM 1
+#define PWM_RIS_INTFAULT0 0x00010000 // Interrupt Fault PWM 0
+#define PWM_RIS_INTPWM3 0x00000008 // PWM3 Interrupt Asserted
+#define PWM_RIS_INTPWM2 0x00000004 // PWM2 Interrupt Asserted
+#define PWM_RIS_INTPWM1 0x00000002 // PWM1 Interrupt Asserted
+#define PWM_RIS_INTPWM0 0x00000001 // PWM0 Interrupt Asserted
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ISC register.
+//
+//*****************************************************************************
+#define PWM_ISC_INTFAULT3 0x00080000 // FAULT3 Interrupt Asserted
+#define PWM_ISC_INTFAULT2 0x00040000 // FAULT2 Interrupt Asserted
+#define PWM_ISC_INTFAULT1 0x00020000 // FAULT1 Interrupt Asserted
+#define PWM_ISC_INTFAULT0 0x00010000 // FAULT0 Interrupt Asserted
+#define PWM_ISC_INTPWM3 0x00000008 // PWM3 Interrupt Status
+#define PWM_ISC_INTPWM2 0x00000004 // PWM2 Interrupt Status
+#define PWM_ISC_INTPWM1 0x00000002 // PWM1 Interrupt Status
+#define PWM_ISC_INTPWM0 0x00000001 // PWM0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_STATUS register.
+//
+//*****************************************************************************
+#define PWM_STATUS_FAULT3 0x00000008 // Generator 3 Fault Status
+#define PWM_STATUS_FAULT2 0x00000004 // Generator 2 Fault Status
+#define PWM_STATUS_FAULT1 0x00000002 // Generator 1 Fault Status
+#define PWM_STATUS_FAULT0 0x00000001 // Generator 0 Fault Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_FAULTVAL register.
+//
+//*****************************************************************************
+#define PWM_FAULTVAL_PWM7 0x00000080 // MnPWM7 Fault Value
+#define PWM_FAULTVAL_PWM6 0x00000040 // MnPWM6 Fault Value
+#define PWM_FAULTVAL_PWM5 0x00000020 // MnPWM5 Fault Value
+#define PWM_FAULTVAL_PWM4 0x00000010 // MnPWM4 Fault Value
+#define PWM_FAULTVAL_PWM3 0x00000008 // MnPWM3 Fault Value
+#define PWM_FAULTVAL_PWM2 0x00000004 // MnPWM2 Fault Value
+#define PWM_FAULTVAL_PWM1 0x00000002 // MnPWM1 Fault Value
+#define PWM_FAULTVAL_PWM0 0x00000001 // MnPWM0 Fault Value
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_ENUPD register.
+//
+//*****************************************************************************
+#define PWM_ENUPD_ENUPD7_M 0x0000C000 // MnPWM7 Enable Update Mode
+#define PWM_ENUPD_ENUPD7_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD7_LSYNC 0x00008000 // Locally Synchronized
+#define PWM_ENUPD_ENUPD7_GSYNC 0x0000C000 // Globally Synchronized
+#define PWM_ENUPD_ENUPD6_M 0x00003000 // MnPWM6 Enable Update Mode
+#define PWM_ENUPD_ENUPD6_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD6_LSYNC 0x00002000 // Locally Synchronized
+#define PWM_ENUPD_ENUPD6_GSYNC 0x00003000 // Globally Synchronized
+#define PWM_ENUPD_ENUPD5_M 0x00000C00 // MnPWM5 Enable Update Mode
+#define PWM_ENUPD_ENUPD5_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD5_LSYNC 0x00000800 // Locally Synchronized
+#define PWM_ENUPD_ENUPD5_GSYNC 0x00000C00 // Globally Synchronized
+#define PWM_ENUPD_ENUPD4_M 0x00000300 // MnPWM4 Enable Update Mode
+#define PWM_ENUPD_ENUPD4_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD4_LSYNC 0x00000200 // Locally Synchronized
+#define PWM_ENUPD_ENUPD4_GSYNC 0x00000300 // Globally Synchronized
+#define PWM_ENUPD_ENUPD3_M 0x000000C0 // MnPWM3 Enable Update Mode
+#define PWM_ENUPD_ENUPD3_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD3_LSYNC 0x00000080 // Locally Synchronized
+#define PWM_ENUPD_ENUPD3_GSYNC 0x000000C0 // Globally Synchronized
+#define PWM_ENUPD_ENUPD2_M 0x00000030 // MnPWM2 Enable Update Mode
+#define PWM_ENUPD_ENUPD2_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD2_LSYNC 0x00000020 // Locally Synchronized
+#define PWM_ENUPD_ENUPD2_GSYNC 0x00000030 // Globally Synchronized
+#define PWM_ENUPD_ENUPD1_M 0x0000000C // MnPWM1 Enable Update Mode
+#define PWM_ENUPD_ENUPD1_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD1_LSYNC 0x00000008 // Locally Synchronized
+#define PWM_ENUPD_ENUPD1_GSYNC 0x0000000C // Globally Synchronized
+#define PWM_ENUPD_ENUPD0_M 0x00000003 // MnPWM0 Enable Update Mode
+#define PWM_ENUPD_ENUPD0_IMM 0x00000000 // Immediate
+#define PWM_ENUPD_ENUPD0_LSYNC 0x00000002 // Locally Synchronized
+#define PWM_ENUPD_ENUPD0_GSYNC 0x00000003 // Globally Synchronized
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_CTL register.
+//
+//*****************************************************************************
+#define PWM_0_CTL_LATCH 0x00040000 // Latch Fault Input
+#define PWM_0_CTL_MINFLTPER 0x00020000 // Minimum Fault Period
+#define PWM_0_CTL_FLTSRC 0x00010000 // Fault Condition Source
+#define PWM_0_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode
+#define PWM_0_CTL_DBFALLUPD_I 0x00000000 // Immediate
+#define PWM_0_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized
+#define PWM_0_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized
+#define PWM_0_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode
+#define PWM_0_CTL_DBRISEUPD_I 0x00000000 // Immediate
+#define PWM_0_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized
+#define PWM_0_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized
+#define PWM_0_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode
+#define PWM_0_CTL_DBCTLUPD_I 0x00000000 // Immediate
+#define PWM_0_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized
+#define PWM_0_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized
+#define PWM_0_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode
+#define PWM_0_CTL_GENBUPD_I 0x00000000 // Immediate
+#define PWM_0_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized
+#define PWM_0_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized
+#define PWM_0_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode
+#define PWM_0_CTL_GENAUPD_I 0x00000000 // Immediate
+#define PWM_0_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized
+#define PWM_0_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized
+#define PWM_0_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode
+#define PWM_0_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode
+#define PWM_0_CTL_LOADUPD 0x00000008 // Load Register Update Mode
+#define PWM_0_CTL_DEBUG 0x00000004 // Debug Mode
+#define PWM_0_CTL_MODE 0x00000002 // Counter Mode
+#define PWM_0_CTL_ENABLE 0x00000001 // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_INTEN register.
+//
+//*****************************************************************************
+#define PWM_0_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB
+ // Down
+#define PWM_0_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up
+#define PWM_0_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA
+ // Down
+#define PWM_0_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up
+#define PWM_0_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD
+#define PWM_0_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0
+#define PWM_0_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB
+ // Down
+#define PWM_0_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB
+ // Up
+#define PWM_0_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA
+ // Down
+#define PWM_0_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA
+ // Up
+#define PWM_0_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD
+#define PWM_0_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_RIS register.
+//
+//*****************************************************************************
+#define PWM_0_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+ // Status
+#define PWM_0_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status
+#define PWM_0_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+ // Status
+#define PWM_0_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status
+#define PWM_0_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status
+#define PWM_0_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_ISC register.
+//
+//*****************************************************************************
+#define PWM_0_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+#define PWM_0_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt
+#define PWM_0_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+#define PWM_0_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt
+#define PWM_0_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt
+#define PWM_0_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_LOAD register.
+//
+//*****************************************************************************
+#define PWM_0_LOAD_M 0x0000FFFF // Counter Load Value
+#define PWM_0_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_COUNT register.
+//
+//*****************************************************************************
+#define PWM_0_COUNT_M 0x0000FFFF // Counter Value
+#define PWM_0_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_CMPA register.
+//
+//*****************************************************************************
+#define PWM_0_CMPA_M 0x0000FFFF // Comparator A Value
+#define PWM_0_CMPA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_CMPB register.
+//
+//*****************************************************************************
+#define PWM_0_CMPB_M 0x0000FFFF // Comparator B Value
+#define PWM_0_CMPB_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_GENA register.
+//
+//*****************************************************************************
+#define PWM_0_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_0_GENA_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_0_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA
+#define PWM_0_GENA_ACTCMPBD_ZERO \
+ 0x00000800 // Drive pwmA Low
+#define PWM_0_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High
+#define PWM_0_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_0_GENA_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_0_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA
+#define PWM_0_GENA_ACTCMPBU_ZERO \
+ 0x00000200 // Drive pwmA Low
+#define PWM_0_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High
+#define PWM_0_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_0_GENA_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_0_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA
+#define PWM_0_GENA_ACTCMPAD_ZERO \
+ 0x00000080 // Drive pwmA Low
+#define PWM_0_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High
+#define PWM_0_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_0_GENA_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_0_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA
+#define PWM_0_GENA_ACTCMPAU_ZERO \
+ 0x00000020 // Drive pwmA Low
+#define PWM_0_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High
+#define PWM_0_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD
+#define PWM_0_GENA_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_0_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA
+#define PWM_0_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low
+#define PWM_0_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High
+#define PWM_0_GENA_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_0_GENA_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_0_GENA_ACTZERO_INV 0x00000001 // Invert pwmA
+#define PWM_0_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low
+#define PWM_0_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_GENB register.
+//
+//*****************************************************************************
+#define PWM_0_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_0_GENB_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_0_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB
+#define PWM_0_GENB_ACTCMPBD_ZERO \
+ 0x00000800 // Drive pwmB Low
+#define PWM_0_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High
+#define PWM_0_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_0_GENB_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_0_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB
+#define PWM_0_GENB_ACTCMPBU_ZERO \
+ 0x00000200 // Drive pwmB Low
+#define PWM_0_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High
+#define PWM_0_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_0_GENB_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_0_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB
+#define PWM_0_GENB_ACTCMPAD_ZERO \
+ 0x00000080 // Drive pwmB Low
+#define PWM_0_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High
+#define PWM_0_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_0_GENB_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_0_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB
+#define PWM_0_GENB_ACTCMPAU_ZERO \
+ 0x00000020 // Drive pwmB Low
+#define PWM_0_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High
+#define PWM_0_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD
+#define PWM_0_GENB_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_0_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB
+#define PWM_0_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low
+#define PWM_0_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High
+#define PWM_0_GENB_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_0_GENB_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_0_GENB_ACTZERO_INV 0x00000001 // Invert pwmB
+#define PWM_0_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low
+#define PWM_0_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_0_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_0_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay
+#define PWM_0_DBRISE_DELAY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_0_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay
+#define PWM_0_DBFALL_DELAY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSRC0_FAULT3 0x00000008 // Fault3 Input
+#define PWM_0_FLTSRC0_FAULT2 0x00000004 // Fault2 Input
+#define PWM_0_FLTSRC0_FAULT1 0x00000002 // Fault1 Input
+#define PWM_0_FLTSRC0_FAULT0 0x00000001 // Fault0 Input
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7
+#define PWM_0_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6
+#define PWM_0_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5
+#define PWM_0_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4
+#define PWM_0_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3
+#define PWM_0_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2
+#define PWM_0_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1
+#define PWM_0_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_0_MINFLTPER_M 0x0000FFFF // Minimum Fault Period
+#define PWM_0_MINFLTPER_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_CTL register.
+//
+//*****************************************************************************
+#define PWM_1_CTL_LATCH 0x00040000 // Latch Fault Input
+#define PWM_1_CTL_MINFLTPER 0x00020000 // Minimum Fault Period
+#define PWM_1_CTL_FLTSRC 0x00010000 // Fault Condition Source
+#define PWM_1_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode
+#define PWM_1_CTL_DBFALLUPD_I 0x00000000 // Immediate
+#define PWM_1_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized
+#define PWM_1_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized
+#define PWM_1_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode
+#define PWM_1_CTL_DBRISEUPD_I 0x00000000 // Immediate
+#define PWM_1_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized
+#define PWM_1_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized
+#define PWM_1_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode
+#define PWM_1_CTL_DBCTLUPD_I 0x00000000 // Immediate
+#define PWM_1_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized
+#define PWM_1_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized
+#define PWM_1_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode
+#define PWM_1_CTL_GENBUPD_I 0x00000000 // Immediate
+#define PWM_1_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized
+#define PWM_1_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized
+#define PWM_1_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode
+#define PWM_1_CTL_GENAUPD_I 0x00000000 // Immediate
+#define PWM_1_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized
+#define PWM_1_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized
+#define PWM_1_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode
+#define PWM_1_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode
+#define PWM_1_CTL_LOADUPD 0x00000008 // Load Register Update Mode
+#define PWM_1_CTL_DEBUG 0x00000004 // Debug Mode
+#define PWM_1_CTL_MODE 0x00000002 // Counter Mode
+#define PWM_1_CTL_ENABLE 0x00000001 // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_INTEN register.
+//
+//*****************************************************************************
+#define PWM_1_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB
+ // Down
+#define PWM_1_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up
+#define PWM_1_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA
+ // Down
+#define PWM_1_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up
+#define PWM_1_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD
+#define PWM_1_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0
+#define PWM_1_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB
+ // Down
+#define PWM_1_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB
+ // Up
+#define PWM_1_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA
+ // Down
+#define PWM_1_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA
+ // Up
+#define PWM_1_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD
+#define PWM_1_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_RIS register.
+//
+//*****************************************************************************
+#define PWM_1_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+ // Status
+#define PWM_1_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status
+#define PWM_1_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+ // Status
+#define PWM_1_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status
+#define PWM_1_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status
+#define PWM_1_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_ISC register.
+//
+//*****************************************************************************
+#define PWM_1_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+#define PWM_1_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt
+#define PWM_1_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+#define PWM_1_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt
+#define PWM_1_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt
+#define PWM_1_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_LOAD register.
+//
+//*****************************************************************************
+#define PWM_1_LOAD_LOAD_M 0x0000FFFF // Counter Load Value
+#define PWM_1_LOAD_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_COUNT register.
+//
+//*****************************************************************************
+#define PWM_1_COUNT_COUNT_M 0x0000FFFF // Counter Value
+#define PWM_1_COUNT_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_CMPA register.
+//
+//*****************************************************************************
+#define PWM_1_CMPA_COMPA_M 0x0000FFFF // Comparator A Value
+#define PWM_1_CMPA_COMPA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_CMPB register.
+//
+//*****************************************************************************
+#define PWM_1_CMPB_COMPB_M 0x0000FFFF // Comparator B Value
+#define PWM_1_CMPB_COMPB_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_GENA register.
+//
+//*****************************************************************************
+#define PWM_1_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_1_GENA_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_1_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA
+#define PWM_1_GENA_ACTCMPBD_ZERO \
+ 0x00000800 // Drive pwmA Low
+#define PWM_1_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High
+#define PWM_1_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_1_GENA_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_1_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA
+#define PWM_1_GENA_ACTCMPBU_ZERO \
+ 0x00000200 // Drive pwmA Low
+#define PWM_1_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High
+#define PWM_1_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_1_GENA_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_1_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA
+#define PWM_1_GENA_ACTCMPAD_ZERO \
+ 0x00000080 // Drive pwmA Low
+#define PWM_1_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High
+#define PWM_1_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_1_GENA_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_1_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA
+#define PWM_1_GENA_ACTCMPAU_ZERO \
+ 0x00000020 // Drive pwmA Low
+#define PWM_1_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High
+#define PWM_1_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD
+#define PWM_1_GENA_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_1_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA
+#define PWM_1_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low
+#define PWM_1_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High
+#define PWM_1_GENA_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_1_GENA_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_1_GENA_ACTZERO_INV 0x00000001 // Invert pwmA
+#define PWM_1_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low
+#define PWM_1_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_GENB register.
+//
+//*****************************************************************************
+#define PWM_1_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_1_GENB_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_1_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB
+#define PWM_1_GENB_ACTCMPBD_ZERO \
+ 0x00000800 // Drive pwmB Low
+#define PWM_1_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High
+#define PWM_1_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_1_GENB_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_1_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB
+#define PWM_1_GENB_ACTCMPBU_ZERO \
+ 0x00000200 // Drive pwmB Low
+#define PWM_1_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High
+#define PWM_1_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_1_GENB_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_1_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB
+#define PWM_1_GENB_ACTCMPAD_ZERO \
+ 0x00000080 // Drive pwmB Low
+#define PWM_1_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High
+#define PWM_1_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_1_GENB_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_1_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB
+#define PWM_1_GENB_ACTCMPAU_ZERO \
+ 0x00000020 // Drive pwmB Low
+#define PWM_1_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High
+#define PWM_1_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD
+#define PWM_1_GENB_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_1_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB
+#define PWM_1_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low
+#define PWM_1_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High
+#define PWM_1_GENB_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_1_GENB_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_1_GENB_ACTZERO_INV 0x00000001 // Invert pwmB
+#define PWM_1_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low
+#define PWM_1_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_1_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_1_DBRISE_RISEDELAY_M \
+ 0x00000FFF // Dead-Band Rise Delay
+#define PWM_1_DBRISE_RISEDELAY_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_1_DBFALL_FALLDELAY_M \
+ 0x00000FFF // Dead-Band Fall Delay
+#define PWM_1_DBFALL_FALLDELAY_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSRC0_FAULT3 0x00000008 // Fault3 Input
+#define PWM_1_FLTSRC0_FAULT2 0x00000004 // Fault2 Input
+#define PWM_1_FLTSRC0_FAULT1 0x00000002 // Fault1 Input
+#define PWM_1_FLTSRC0_FAULT0 0x00000001 // Fault0 Input
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7
+#define PWM_1_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6
+#define PWM_1_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5
+#define PWM_1_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4
+#define PWM_1_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3
+#define PWM_1_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2
+#define PWM_1_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1
+#define PWM_1_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_1_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period
+#define PWM_1_MINFLTPER_MFP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_CTL register.
+//
+//*****************************************************************************
+#define PWM_2_CTL_LATCH 0x00040000 // Latch Fault Input
+#define PWM_2_CTL_MINFLTPER 0x00020000 // Minimum Fault Period
+#define PWM_2_CTL_FLTSRC 0x00010000 // Fault Condition Source
+#define PWM_2_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode
+#define PWM_2_CTL_DBFALLUPD_I 0x00000000 // Immediate
+#define PWM_2_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized
+#define PWM_2_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized
+#define PWM_2_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode
+#define PWM_2_CTL_DBRISEUPD_I 0x00000000 // Immediate
+#define PWM_2_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized
+#define PWM_2_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized
+#define PWM_2_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode
+#define PWM_2_CTL_DBCTLUPD_I 0x00000000 // Immediate
+#define PWM_2_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized
+#define PWM_2_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized
+#define PWM_2_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode
+#define PWM_2_CTL_GENBUPD_I 0x00000000 // Immediate
+#define PWM_2_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized
+#define PWM_2_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized
+#define PWM_2_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode
+#define PWM_2_CTL_GENAUPD_I 0x00000000 // Immediate
+#define PWM_2_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized
+#define PWM_2_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized
+#define PWM_2_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode
+#define PWM_2_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode
+#define PWM_2_CTL_LOADUPD 0x00000008 // Load Register Update Mode
+#define PWM_2_CTL_DEBUG 0x00000004 // Debug Mode
+#define PWM_2_CTL_MODE 0x00000002 // Counter Mode
+#define PWM_2_CTL_ENABLE 0x00000001 // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_INTEN register.
+//
+//*****************************************************************************
+#define PWM_2_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB
+ // Down
+#define PWM_2_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up
+#define PWM_2_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA
+ // Down
+#define PWM_2_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up
+#define PWM_2_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD
+#define PWM_2_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0
+#define PWM_2_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB
+ // Down
+#define PWM_2_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB
+ // Up
+#define PWM_2_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA
+ // Down
+#define PWM_2_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA
+ // Up
+#define PWM_2_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD
+#define PWM_2_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_RIS register.
+//
+//*****************************************************************************
+#define PWM_2_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+ // Status
+#define PWM_2_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status
+#define PWM_2_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+ // Status
+#define PWM_2_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status
+#define PWM_2_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status
+#define PWM_2_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_ISC register.
+//
+//*****************************************************************************
+#define PWM_2_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+#define PWM_2_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt
+#define PWM_2_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+#define PWM_2_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt
+#define PWM_2_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt
+#define PWM_2_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_LOAD register.
+//
+//*****************************************************************************
+#define PWM_2_LOAD_LOAD_M 0x0000FFFF // Counter Load Value
+#define PWM_2_LOAD_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_COUNT register.
+//
+//*****************************************************************************
+#define PWM_2_COUNT_COUNT_M 0x0000FFFF // Counter Value
+#define PWM_2_COUNT_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_CMPA register.
+//
+//*****************************************************************************
+#define PWM_2_CMPA_COMPA_M 0x0000FFFF // Comparator A Value
+#define PWM_2_CMPA_COMPA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_CMPB register.
+//
+//*****************************************************************************
+#define PWM_2_CMPB_COMPB_M 0x0000FFFF // Comparator B Value
+#define PWM_2_CMPB_COMPB_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_GENA register.
+//
+//*****************************************************************************
+#define PWM_2_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_2_GENA_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_2_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA
+#define PWM_2_GENA_ACTCMPBD_ZERO \
+ 0x00000800 // Drive pwmA Low
+#define PWM_2_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High
+#define PWM_2_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_2_GENA_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_2_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA
+#define PWM_2_GENA_ACTCMPBU_ZERO \
+ 0x00000200 // Drive pwmA Low
+#define PWM_2_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High
+#define PWM_2_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_2_GENA_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_2_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA
+#define PWM_2_GENA_ACTCMPAD_ZERO \
+ 0x00000080 // Drive pwmA Low
+#define PWM_2_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High
+#define PWM_2_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_2_GENA_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_2_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA
+#define PWM_2_GENA_ACTCMPAU_ZERO \
+ 0x00000020 // Drive pwmA Low
+#define PWM_2_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High
+#define PWM_2_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD
+#define PWM_2_GENA_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_2_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA
+#define PWM_2_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low
+#define PWM_2_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High
+#define PWM_2_GENA_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_2_GENA_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_2_GENA_ACTZERO_INV 0x00000001 // Invert pwmA
+#define PWM_2_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low
+#define PWM_2_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_GENB register.
+//
+//*****************************************************************************
+#define PWM_2_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_2_GENB_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_2_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB
+#define PWM_2_GENB_ACTCMPBD_ZERO \
+ 0x00000800 // Drive pwmB Low
+#define PWM_2_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High
+#define PWM_2_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_2_GENB_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_2_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB
+#define PWM_2_GENB_ACTCMPBU_ZERO \
+ 0x00000200 // Drive pwmB Low
+#define PWM_2_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High
+#define PWM_2_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_2_GENB_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_2_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB
+#define PWM_2_GENB_ACTCMPAD_ZERO \
+ 0x00000080 // Drive pwmB Low
+#define PWM_2_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High
+#define PWM_2_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_2_GENB_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_2_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB
+#define PWM_2_GENB_ACTCMPAU_ZERO \
+ 0x00000020 // Drive pwmB Low
+#define PWM_2_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High
+#define PWM_2_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD
+#define PWM_2_GENB_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_2_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB
+#define PWM_2_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low
+#define PWM_2_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High
+#define PWM_2_GENB_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_2_GENB_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_2_GENB_ACTZERO_INV 0x00000001 // Invert pwmB
+#define PWM_2_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low
+#define PWM_2_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_2_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_2_DBRISE_RISEDELAY_M \
+ 0x00000FFF // Dead-Band Rise Delay
+#define PWM_2_DBRISE_RISEDELAY_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_2_DBFALL_FALLDELAY_M \
+ 0x00000FFF // Dead-Band Fall Delay
+#define PWM_2_DBFALL_FALLDELAY_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSRC0_FAULT3 0x00000008 // Fault3 Input
+#define PWM_2_FLTSRC0_FAULT2 0x00000004 // Fault2 Input
+#define PWM_2_FLTSRC0_FAULT1 0x00000002 // Fault1 Input
+#define PWM_2_FLTSRC0_FAULT0 0x00000001 // Fault0 Input
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7
+#define PWM_2_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6
+#define PWM_2_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5
+#define PWM_2_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4
+#define PWM_2_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3
+#define PWM_2_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2
+#define PWM_2_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1
+#define PWM_2_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_2_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period
+#define PWM_2_MINFLTPER_MFP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_CTL register.
+//
+//*****************************************************************************
+#define PWM_3_CTL_LATCH 0x00040000 // Latch Fault Input
+#define PWM_3_CTL_MINFLTPER 0x00020000 // Minimum Fault Period
+#define PWM_3_CTL_FLTSRC 0x00010000 // Fault Condition Source
+#define PWM_3_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode
+#define PWM_3_CTL_DBFALLUPD_I 0x00000000 // Immediate
+#define PWM_3_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized
+#define PWM_3_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized
+#define PWM_3_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode
+#define PWM_3_CTL_DBRISEUPD_I 0x00000000 // Immediate
+#define PWM_3_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized
+#define PWM_3_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized
+#define PWM_3_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode
+#define PWM_3_CTL_DBCTLUPD_I 0x00000000 // Immediate
+#define PWM_3_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized
+#define PWM_3_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized
+#define PWM_3_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode
+#define PWM_3_CTL_GENBUPD_I 0x00000000 // Immediate
+#define PWM_3_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized
+#define PWM_3_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized
+#define PWM_3_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode
+#define PWM_3_CTL_GENAUPD_I 0x00000000 // Immediate
+#define PWM_3_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized
+#define PWM_3_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized
+#define PWM_3_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode
+#define PWM_3_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode
+#define PWM_3_CTL_LOADUPD 0x00000008 // Load Register Update Mode
+#define PWM_3_CTL_DEBUG 0x00000004 // Debug Mode
+#define PWM_3_CTL_MODE 0x00000002 // Counter Mode
+#define PWM_3_CTL_ENABLE 0x00000001 // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_INTEN register.
+//
+//*****************************************************************************
+#define PWM_3_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB
+ // Down
+#define PWM_3_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up
+#define PWM_3_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA
+ // Down
+#define PWM_3_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up
+#define PWM_3_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD
+#define PWM_3_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0
+#define PWM_3_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB
+ // Down
+#define PWM_3_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB
+ // Up
+#define PWM_3_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA
+ // Down
+#define PWM_3_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA
+ // Up
+#define PWM_3_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD
+#define PWM_3_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_RIS register.
+//
+//*****************************************************************************
+#define PWM_3_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+ // Status
+#define PWM_3_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status
+#define PWM_3_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+ // Status
+#define PWM_3_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status
+#define PWM_3_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status
+#define PWM_3_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_ISC register.
+//
+//*****************************************************************************
+#define PWM_3_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+#define PWM_3_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt
+#define PWM_3_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+#define PWM_3_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt
+#define PWM_3_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt
+#define PWM_3_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_LOAD register.
+//
+//*****************************************************************************
+#define PWM_3_LOAD_LOAD_M 0x0000FFFF // Counter Load Value
+#define PWM_3_LOAD_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_COUNT register.
+//
+//*****************************************************************************
+#define PWM_3_COUNT_COUNT_M 0x0000FFFF // Counter Value
+#define PWM_3_COUNT_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_CMPA register.
+//
+//*****************************************************************************
+#define PWM_3_CMPA_COMPA_M 0x0000FFFF // Comparator A Value
+#define PWM_3_CMPA_COMPA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_CMPB register.
+//
+//*****************************************************************************
+#define PWM_3_CMPB_COMPB_M 0x0000FFFF // Comparator B Value
+#define PWM_3_CMPB_COMPB_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_GENA register.
+//
+//*****************************************************************************
+#define PWM_3_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_3_GENA_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_3_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA
+#define PWM_3_GENA_ACTCMPBD_ZERO \
+ 0x00000800 // Drive pwmA Low
+#define PWM_3_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High
+#define PWM_3_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_3_GENA_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_3_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA
+#define PWM_3_GENA_ACTCMPBU_ZERO \
+ 0x00000200 // Drive pwmA Low
+#define PWM_3_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High
+#define PWM_3_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_3_GENA_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_3_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA
+#define PWM_3_GENA_ACTCMPAD_ZERO \
+ 0x00000080 // Drive pwmA Low
+#define PWM_3_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High
+#define PWM_3_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_3_GENA_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_3_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA
+#define PWM_3_GENA_ACTCMPAU_ZERO \
+ 0x00000020 // Drive pwmA Low
+#define PWM_3_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High
+#define PWM_3_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD
+#define PWM_3_GENA_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_3_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA
+#define PWM_3_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low
+#define PWM_3_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High
+#define PWM_3_GENA_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_3_GENA_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_3_GENA_ACTZERO_INV 0x00000001 // Invert pwmA
+#define PWM_3_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low
+#define PWM_3_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_GENB register.
+//
+//*****************************************************************************
+#define PWM_3_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_3_GENB_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_3_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB
+#define PWM_3_GENB_ACTCMPBD_ZERO \
+ 0x00000800 // Drive pwmB Low
+#define PWM_3_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High
+#define PWM_3_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_3_GENB_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_3_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB
+#define PWM_3_GENB_ACTCMPBU_ZERO \
+ 0x00000200 // Drive pwmB Low
+#define PWM_3_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High
+#define PWM_3_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_3_GENB_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_3_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB
+#define PWM_3_GENB_ACTCMPAD_ZERO \
+ 0x00000080 // Drive pwmB Low
+#define PWM_3_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High
+#define PWM_3_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_3_GENB_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_3_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB
+#define PWM_3_GENB_ACTCMPAU_ZERO \
+ 0x00000020 // Drive pwmB Low
+#define PWM_3_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High
+#define PWM_3_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD
+#define PWM_3_GENB_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_3_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB
+#define PWM_3_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low
+#define PWM_3_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High
+#define PWM_3_GENB_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_3_GENB_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_3_GENB_ACTZERO_INV 0x00000001 // Invert pwmB
+#define PWM_3_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low
+#define PWM_3_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_3_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_3_DBRISE_RISEDELAY_M \
+ 0x00000FFF // Dead-Band Rise Delay
+#define PWM_3_DBRISE_RISEDELAY_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_3_DBFALL_FALLDELAY_M \
+ 0x00000FFF // Dead-Band Fall Delay
+#define PWM_3_DBFALL_FALLDELAY_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSRC0_FAULT3 0x00000008 // Fault3 Input
+#define PWM_3_FLTSRC0_FAULT2 0x00000004 // Fault2 Input
+#define PWM_3_FLTSRC0_FAULT1 0x00000002 // Fault1 Input
+#define PWM_3_FLTSRC0_FAULT0 0x00000001 // Fault0 Input
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7
+#define PWM_3_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6
+#define PWM_3_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5
+#define PWM_3_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4
+#define PWM_3_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3
+#define PWM_3_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2
+#define PWM_3_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1
+#define PWM_3_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_3_MINFLTPER_MFP_M 0x0000FFFF // Minimum Fault Period
+#define PWM_3_MINFLTPER_MFP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSEN_FAULT3 0x00000008 // Fault3 Sense
+#define PWM_0_FLTSEN_FAULT2 0x00000004 // Fault2 Sense
+#define PWM_0_FLTSEN_FAULT1 0x00000002 // Fault1 Sense
+#define PWM_0_FLTSEN_FAULT0 0x00000001 // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3
+#define PWM_0_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2
+#define PWM_0_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1
+#define PWM_0_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_0_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_0_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger
+#define PWM_0_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger
+#define PWM_0_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger
+#define PWM_0_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger
+#define PWM_0_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger
+#define PWM_0_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger
+#define PWM_0_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger
+#define PWM_0_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSEN_FAULT3 0x00000008 // Fault3 Sense
+#define PWM_1_FLTSEN_FAULT2 0x00000004 // Fault2 Sense
+#define PWM_1_FLTSEN_FAULT1 0x00000002 // Fault1 Sense
+#define PWM_1_FLTSEN_FAULT0 0x00000001 // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3
+#define PWM_1_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2
+#define PWM_1_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1
+#define PWM_1_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_1_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_1_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger
+#define PWM_1_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger
+#define PWM_1_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger
+#define PWM_1_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger
+#define PWM_1_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger
+#define PWM_1_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger
+#define PWM_1_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger
+#define PWM_1_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSEN_FAULT3 0x00000008 // Fault3 Sense
+#define PWM_2_FLTSEN_FAULT2 0x00000004 // Fault2 Sense
+#define PWM_2_FLTSEN_FAULT1 0x00000002 // Fault1 Sense
+#define PWM_2_FLTSEN_FAULT0 0x00000001 // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3
+#define PWM_2_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2
+#define PWM_2_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1
+#define PWM_2_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_2_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_2_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger
+#define PWM_2_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger
+#define PWM_2_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger
+#define PWM_2_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger
+#define PWM_2_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger
+#define PWM_2_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger
+#define PWM_2_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger
+#define PWM_2_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSEN_FAULT3 0x00000008 // Fault3 Sense
+#define PWM_3_FLTSEN_FAULT2 0x00000004 // Fault2 Sense
+#define PWM_3_FLTSEN_FAULT1 0x00000002 // Fault1 Sense
+#define PWM_3_FLTSEN_FAULT0 0x00000001 // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3
+#define PWM_3_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2
+#define PWM_3_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1
+#define PWM_3_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_3_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_3_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger
+#define PWM_3_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger
+#define PWM_3_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger
+#define PWM_3_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger
+#define PWM_3_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger
+#define PWM_3_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger
+#define PWM_3_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger
+#define PWM_3_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_PP register.
+//
+//*****************************************************************************
+#define PWM_PP_GCNT_M 0x0000000F // Generators
+#define PWM_PP_FCNT_M 0x000000F0 // Fault Inputs (per PWM unit)
+#define PWM_PP_ESYNC 0x00000100 // Extended Synchronization
+#define PWM_PP_EFAULT 0x00000200 // Extended Fault
+#define PWM_PP_ONE 0x00000400 // One-Shot Mode
+#define PWM_PP_GCNT_S 0
+#define PWM_PP_FCNT_S 4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_CC register.
+//
+//*****************************************************************************
+#define PWM_CC_USEPWM 0x00000100 // Use PWM Clock Divisor
+#define PWM_CC_PWMDIV_M 0x00000007 // PWM Clock Divider
+#define PWM_CC_PWMDIV_2 0x00000000 // /2
+#define PWM_CC_PWMDIV_4 0x00000001 // /4
+#define PWM_CC_PWMDIV_8 0x00000002 // /8
+#define PWM_CC_PWMDIV_16 0x00000003 // /16
+#define PWM_CC_PWMDIV_32 0x00000004 // /32
+#define PWM_CC_PWMDIV_64 0x00000005 // /64
+
+//*****************************************************************************
+//
+// The following are defines for the PWM Generator standard offsets.
+//
+//*****************************************************************************
+#define PWM_O_X_CTL 0x00000000 // Gen Control Reg
+#define PWM_O_X_INTEN 0x00000004 // Gen Int/Trig Enable Reg
+#define PWM_O_X_RIS 0x00000008 // Gen Raw Int Status Reg
+#define PWM_O_X_ISC 0x0000000C // Gen Int Status Reg
+#define PWM_O_X_LOAD 0x00000010 // Gen Load Reg
+#define PWM_O_X_COUNT 0x00000014 // Gen Counter Reg
+#define PWM_O_X_CMPA 0x00000018 // Gen Compare A Reg
+#define PWM_O_X_CMPB 0x0000001C // Gen Compare B Reg
+#define PWM_O_X_GENA 0x00000020 // Gen Generator A Ctrl Reg
+#define PWM_O_X_GENB 0x00000024 // Gen Generator B Ctrl Reg
+#define PWM_O_X_DBCTL 0x00000028 // Gen Dead Band Ctrl Reg
+#define PWM_O_X_DBRISE 0x0000002C // Gen DB Rising Edge Delay Reg
+#define PWM_O_X_DBFALL 0x00000030 // Gen DB Falling Edge Delay Reg
+#define PWM_O_X_FLTSRC0 0x00000034 // Fault pin, comparator condition
+#define PWM_O_X_FLTSRC1 0x00000038 // Digital comparator condition
+#define PWM_O_X_MINFLTPER 0x0000003C // Fault minimum period extension
+#define PWM_GEN_0_OFFSET 0x00000040 // PWM0 base
+#define PWM_GEN_1_OFFSET 0x00000080 // PWM1 base
+#define PWM_GEN_2_OFFSET 0x000000C0 // PWM2 base
+#define PWM_GEN_3_OFFSET 0x00000100 // PWM3 base
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_CTL register.
+//
+//*****************************************************************************
+#define PWM_X_CTL_LATCH 0x00040000 // Latch Fault Input
+#define PWM_X_CTL_MINFLTPER 0x00020000 // Minimum Fault Period
+#define PWM_X_CTL_FLTSRC 0x00010000 // Fault Condition Source
+#define PWM_X_CTL_DBFALLUPD_M 0x0000C000 // PWMnDBFALL Update Mode
+#define PWM_X_CTL_DBFALLUPD_I 0x00000000 // Immediate
+#define PWM_X_CTL_DBFALLUPD_LS 0x00008000 // Locally Synchronized
+#define PWM_X_CTL_DBFALLUPD_GS 0x0000C000 // Globally Synchronized
+#define PWM_X_CTL_DBRISEUPD_M 0x00003000 // PWMnDBRISE Update Mode
+#define PWM_X_CTL_DBRISEUPD_I 0x00000000 // Immediate
+#define PWM_X_CTL_DBRISEUPD_LS 0x00002000 // Locally Synchronized
+#define PWM_X_CTL_DBRISEUPD_GS 0x00003000 // Globally Synchronized
+#define PWM_X_CTL_DBCTLUPD_M 0x00000C00 // PWMnDBCTL Update Mode
+#define PWM_X_CTL_DBCTLUPD_I 0x00000000 // Immediate
+#define PWM_X_CTL_DBCTLUPD_LS 0x00000800 // Locally Synchronized
+#define PWM_X_CTL_DBCTLUPD_GS 0x00000C00 // Globally Synchronized
+#define PWM_X_CTL_GENBUPD_M 0x00000300 // PWMnGENB Update Mode
+#define PWM_X_CTL_GENBUPD_I 0x00000000 // Immediate
+#define PWM_X_CTL_GENBUPD_LS 0x00000200 // Locally Synchronized
+#define PWM_X_CTL_GENBUPD_GS 0x00000300 // Globally Synchronized
+#define PWM_X_CTL_GENAUPD_M 0x000000C0 // PWMnGENA Update Mode
+#define PWM_X_CTL_GENAUPD_I 0x00000000 // Immediate
+#define PWM_X_CTL_GENAUPD_LS 0x00000080 // Locally Synchronized
+#define PWM_X_CTL_GENAUPD_GS 0x000000C0 // Globally Synchronized
+#define PWM_X_CTL_CMPBUPD 0x00000020 // Comparator B Update Mode
+#define PWM_X_CTL_CMPAUPD 0x00000010 // Comparator A Update Mode
+#define PWM_X_CTL_LOADUPD 0x00000008 // Load Register Update Mode
+#define PWM_X_CTL_DEBUG 0x00000004 // Debug Mode
+#define PWM_X_CTL_MODE 0x00000002 // Counter Mode
+#define PWM_X_CTL_ENABLE 0x00000001 // PWM Block Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_INTEN register.
+//
+//*****************************************************************************
+#define PWM_X_INTEN_TRCMPBD 0x00002000 // Trigger for Counter=PWMnCMPB
+ // Down
+#define PWM_X_INTEN_TRCMPBU 0x00001000 // Trigger for Counter=PWMnCMPB Up
+#define PWM_X_INTEN_TRCMPAD 0x00000800 // Trigger for Counter=PWMnCMPA
+ // Down
+#define PWM_X_INTEN_TRCMPAU 0x00000400 // Trigger for Counter=PWMnCMPA Up
+#define PWM_X_INTEN_TRCNTLOAD 0x00000200 // Trigger for Counter=PWMnLOAD
+#define PWM_X_INTEN_TRCNTZERO 0x00000100 // Trigger for Counter=0
+#define PWM_X_INTEN_INTCMPBD 0x00000020 // Interrupt for Counter=PWMnCMPB
+ // Down
+#define PWM_X_INTEN_INTCMPBU 0x00000010 // Interrupt for Counter=PWMnCMPB
+ // Up
+#define PWM_X_INTEN_INTCMPAD 0x00000008 // Interrupt for Counter=PWMnCMPA
+ // Down
+#define PWM_X_INTEN_INTCMPAU 0x00000004 // Interrupt for Counter=PWMnCMPA
+ // Up
+#define PWM_X_INTEN_INTCNTLOAD 0x00000002 // Interrupt for Counter=PWMnLOAD
+#define PWM_X_INTEN_INTCNTZERO 0x00000001 // Interrupt for Counter=0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_RIS register.
+//
+//*****************************************************************************
+#define PWM_X_RIS_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+ // Status
+#define PWM_X_RIS_INTCMPBU 0x00000010 // Comparator B Up Interrupt Status
+#define PWM_X_RIS_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+ // Status
+#define PWM_X_RIS_INTCMPAU 0x00000004 // Comparator A Up Interrupt Status
+#define PWM_X_RIS_INTCNTLOAD 0x00000002 // Counter=Load Interrupt Status
+#define PWM_X_RIS_INTCNTZERO 0x00000001 // Counter=0 Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_ISC register.
+//
+//*****************************************************************************
+#define PWM_X_ISC_INTCMPBD 0x00000020 // Comparator B Down Interrupt
+#define PWM_X_ISC_INTCMPBU 0x00000010 // Comparator B Up Interrupt
+#define PWM_X_ISC_INTCMPAD 0x00000008 // Comparator A Down Interrupt
+#define PWM_X_ISC_INTCMPAU 0x00000004 // Comparator A Up Interrupt
+#define PWM_X_ISC_INTCNTLOAD 0x00000002 // Counter=Load Interrupt
+#define PWM_X_ISC_INTCNTZERO 0x00000001 // Counter=0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_LOAD register.
+//
+//*****************************************************************************
+#define PWM_X_LOAD_M 0x0000FFFF // Counter Load Value
+#define PWM_X_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_COUNT register.
+//
+//*****************************************************************************
+#define PWM_X_COUNT_M 0x0000FFFF // Counter Value
+#define PWM_X_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_CMPA register.
+//
+//*****************************************************************************
+#define PWM_X_CMPA_M 0x0000FFFF // Comparator A Value
+#define PWM_X_CMPA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_CMPB register.
+//
+//*****************************************************************************
+#define PWM_X_CMPB_M 0x0000FFFF // Comparator B Value
+#define PWM_X_CMPB_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_GENA register.
+//
+//*****************************************************************************
+#define PWM_X_GENA_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_X_GENA_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENA_ACTCMPBD_INV 0x00000400 // Invert pwmA
+#define PWM_X_GENA_ACTCMPBD_ZERO \
+ 0x00000800 // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPBD_ONE 0x00000C00 // Drive pwmA High
+#define PWM_X_GENA_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_X_GENA_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENA_ACTCMPBU_INV 0x00000100 // Invert pwmA
+#define PWM_X_GENA_ACTCMPBU_ZERO \
+ 0x00000200 // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPBU_ONE 0x00000300 // Drive pwmA High
+#define PWM_X_GENA_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_X_GENA_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENA_ACTCMPAD_INV 0x00000040 // Invert pwmA
+#define PWM_X_GENA_ACTCMPAD_ZERO \
+ 0x00000080 // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPAD_ONE 0x000000C0 // Drive pwmA High
+#define PWM_X_GENA_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_X_GENA_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENA_ACTCMPAU_INV 0x00000010 // Invert pwmA
+#define PWM_X_GENA_ACTCMPAU_ZERO \
+ 0x00000020 // Drive pwmA Low
+#define PWM_X_GENA_ACTCMPAU_ONE 0x00000030 // Drive pwmA High
+#define PWM_X_GENA_ACTLOAD_M 0x0000000C // Action for Counter=LOAD
+#define PWM_X_GENA_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_X_GENA_ACTLOAD_INV 0x00000004 // Invert pwmA
+#define PWM_X_GENA_ACTLOAD_ZERO 0x00000008 // Drive pwmA Low
+#define PWM_X_GENA_ACTLOAD_ONE 0x0000000C // Drive pwmA High
+#define PWM_X_GENA_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_X_GENA_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_X_GENA_ACTZERO_INV 0x00000001 // Invert pwmA
+#define PWM_X_GENA_ACTZERO_ZERO 0x00000002 // Drive pwmA Low
+#define PWM_X_GENA_ACTZERO_ONE 0x00000003 // Drive pwmA High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_GENB register.
+//
+//*****************************************************************************
+#define PWM_X_GENB_ACTCMPBD_M 0x00000C00 // Action for Comparator B Down
+#define PWM_X_GENB_ACTCMPBD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENB_ACTCMPBD_INV 0x00000400 // Invert pwmB
+#define PWM_X_GENB_ACTCMPBD_ZERO \
+ 0x00000800 // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPBD_ONE 0x00000C00 // Drive pwmB High
+#define PWM_X_GENB_ACTCMPBU_M 0x00000300 // Action for Comparator B Up
+#define PWM_X_GENB_ACTCMPBU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENB_ACTCMPBU_INV 0x00000100 // Invert pwmB
+#define PWM_X_GENB_ACTCMPBU_ZERO \
+ 0x00000200 // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPBU_ONE 0x00000300 // Drive pwmB High
+#define PWM_X_GENB_ACTCMPAD_M 0x000000C0 // Action for Comparator A Down
+#define PWM_X_GENB_ACTCMPAD_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENB_ACTCMPAD_INV 0x00000040 // Invert pwmB
+#define PWM_X_GENB_ACTCMPAD_ZERO \
+ 0x00000080 // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPAD_ONE 0x000000C0 // Drive pwmB High
+#define PWM_X_GENB_ACTCMPAU_M 0x00000030 // Action for Comparator A Up
+#define PWM_X_GENB_ACTCMPAU_NONE \
+ 0x00000000 // Do nothing
+#define PWM_X_GENB_ACTCMPAU_INV 0x00000010 // Invert pwmB
+#define PWM_X_GENB_ACTCMPAU_ZERO \
+ 0x00000020 // Drive pwmB Low
+#define PWM_X_GENB_ACTCMPAU_ONE 0x00000030 // Drive pwmB High
+#define PWM_X_GENB_ACTLOAD_M 0x0000000C // Action for Counter=LOAD
+#define PWM_X_GENB_ACTLOAD_NONE 0x00000000 // Do nothing
+#define PWM_X_GENB_ACTLOAD_INV 0x00000004 // Invert pwmB
+#define PWM_X_GENB_ACTLOAD_ZERO 0x00000008 // Drive pwmB Low
+#define PWM_X_GENB_ACTLOAD_ONE 0x0000000C // Drive pwmB High
+#define PWM_X_GENB_ACTZERO_M 0x00000003 // Action for Counter=0
+#define PWM_X_GENB_ACTZERO_NONE 0x00000000 // Do nothing
+#define PWM_X_GENB_ACTZERO_INV 0x00000001 // Invert pwmB
+#define PWM_X_GENB_ACTZERO_ZERO 0x00000002 // Drive pwmB Low
+#define PWM_X_GENB_ACTZERO_ONE 0x00000003 // Drive pwmB High
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_DBCTL register.
+//
+//*****************************************************************************
+#define PWM_X_DBCTL_ENABLE 0x00000001 // Dead-Band Generator Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_DBRISE register.
+//
+//*****************************************************************************
+#define PWM_X_DBRISE_DELAY_M 0x00000FFF // Dead-Band Rise Delay
+#define PWM_X_DBRISE_DELAY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_DBFALL register.
+//
+//*****************************************************************************
+#define PWM_X_DBFALL_DELAY_M 0x00000FFF // Dead-Band Fall Delay
+#define PWM_X_DBFALL_DELAY_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSRC0
+// register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSRC0_FAULT3 0x00000008 // Fault3 Input
+#define PWM_X_FLTSRC0_FAULT2 0x00000004 // Fault2 Input
+#define PWM_X_FLTSRC0_FAULT1 0x00000002 // Fault1 Input
+#define PWM_X_FLTSRC0_FAULT0 0x00000001 // Fault0 Input
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSRC1
+// register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSRC1_DCMP7 0x00000080 // Digital Comparator 7
+#define PWM_X_FLTSRC1_DCMP6 0x00000040 // Digital Comparator 6
+#define PWM_X_FLTSRC1_DCMP5 0x00000020 // Digital Comparator 5
+#define PWM_X_FLTSRC1_DCMP4 0x00000010 // Digital Comparator 4
+#define PWM_X_FLTSRC1_DCMP3 0x00000008 // Digital Comparator 3
+#define PWM_X_FLTSRC1_DCMP2 0x00000004 // Digital Comparator 2
+#define PWM_X_FLTSRC1_DCMP1 0x00000002 // Digital Comparator 1
+#define PWM_X_FLTSRC1_DCMP0 0x00000001 // Digital Comparator 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_MINFLTPER
+// register.
+//
+//*****************************************************************************
+#define PWM_X_MINFLTPER_M 0x0000FFFF // Minimum Fault Period
+#define PWM_X_MINFLTPER_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the PWM Generator extended offsets.
+//
+//*****************************************************************************
+#define PWM_O_X_FLTSEN 0x00000000 // Fault logic sense
+#define PWM_O_X_FLTSTAT0 0x00000004 // Pin and comparator status
+#define PWM_O_X_FLTSTAT1 0x00000008 // Digital comparator status
+#define PWM_EXT_0_OFFSET 0x00000800 // PWM0 extended base
+#define PWM_EXT_1_OFFSET 0x00000880 // PWM1 extended base
+#define PWM_EXT_2_OFFSET 0x00000900 // PWM2 extended base
+#define PWM_EXT_3_OFFSET 0x00000980 // PWM3 extended base
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSEN register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSEN_FAULT3 0x00000008 // Fault3 Sense
+#define PWM_X_FLTSEN_FAULT2 0x00000004 // Fault2 Sense
+#define PWM_X_FLTSEN_FAULT1 0x00000002 // Fault1 Sense
+#define PWM_X_FLTSEN_FAULT0 0x00000001 // Fault0 Sense
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSTAT0
+// register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSTAT0_FAULT3 0x00000008 // Fault Input 3
+#define PWM_X_FLTSTAT0_FAULT2 0x00000004 // Fault Input 2
+#define PWM_X_FLTSTAT0_FAULT1 0x00000002 // Fault Input 1
+#define PWM_X_FLTSTAT0_FAULT0 0x00000001 // Fault Input 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the PWM_O_X_FLTSTAT1
+// register.
+//
+//*****************************************************************************
+#define PWM_X_FLTSTAT1_DCMP7 0x00000080 // Digital Comparator 7 Trigger
+#define PWM_X_FLTSTAT1_DCMP6 0x00000040 // Digital Comparator 6 Trigger
+#define PWM_X_FLTSTAT1_DCMP5 0x00000020 // Digital Comparator 5 Trigger
+#define PWM_X_FLTSTAT1_DCMP4 0x00000010 // Digital Comparator 4 Trigger
+#define PWM_X_FLTSTAT1_DCMP3 0x00000008 // Digital Comparator 3 Trigger
+#define PWM_X_FLTSTAT1_DCMP2 0x00000004 // Digital Comparator 2 Trigger
+#define PWM_X_FLTSTAT1_DCMP1 0x00000002 // Digital Comparator 1 Trigger
+#define PWM_X_FLTSTAT1_DCMP0 0x00000001 // Digital Comparator 0 Trigger
+
+#endif // __HW_PWM_H__
diff --git a/os/common/ext/TivaWare/inc/hw_qei.h b/os/common/ext/TivaWare/inc/hw_qei.h
new file mode 100644
index 0000000..93c4a07
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_qei.h
@@ -0,0 +1,178 @@
+//*****************************************************************************
+//
+// hw_qei.h - Macros used when accessing the QEI hardware.
+//
+// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_QEI_H__
+#define __HW_QEI_H__
+
+//*****************************************************************************
+//
+// The following are defines for the QEI register offsets.
+//
+//*****************************************************************************
+#define QEI_O_CTL 0x00000000 // QEI Control
+#define QEI_O_STAT 0x00000004 // QEI Status
+#define QEI_O_POS 0x00000008 // QEI Position
+#define QEI_O_MAXPOS 0x0000000C // QEI Maximum Position
+#define QEI_O_LOAD 0x00000010 // QEI Timer Load
+#define QEI_O_TIME 0x00000014 // QEI Timer
+#define QEI_O_COUNT 0x00000018 // QEI Velocity Counter
+#define QEI_O_SPEED 0x0000001C // QEI Velocity
+#define QEI_O_INTEN 0x00000020 // QEI Interrupt Enable
+#define QEI_O_RIS 0x00000024 // QEI Raw Interrupt Status
+#define QEI_O_ISC 0x00000028 // QEI Interrupt Status and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_CTL register.
+//
+//*****************************************************************************
+#define QEI_CTL_FILTCNT_M 0x000F0000 // Input Filter Prescale Count
+#define QEI_CTL_FILTEN 0x00002000 // Enable Input Filter
+#define QEI_CTL_STALLEN 0x00001000 // Stall QEI
+#define QEI_CTL_INVI 0x00000800 // Invert Index Pulse
+#define QEI_CTL_INVB 0x00000400 // Invert PhB
+#define QEI_CTL_INVA 0x00000200 // Invert PhA
+#define QEI_CTL_VELDIV_M 0x000001C0 // Predivide Velocity
+#define QEI_CTL_VELDIV_1 0x00000000 // QEI clock /1
+#define QEI_CTL_VELDIV_2 0x00000040 // QEI clock /2
+#define QEI_CTL_VELDIV_4 0x00000080 // QEI clock /4
+#define QEI_CTL_VELDIV_8 0x000000C0 // QEI clock /8
+#define QEI_CTL_VELDIV_16 0x00000100 // QEI clock /16
+#define QEI_CTL_VELDIV_32 0x00000140 // QEI clock /32
+#define QEI_CTL_VELDIV_64 0x00000180 // QEI clock /64
+#define QEI_CTL_VELDIV_128 0x000001C0 // QEI clock /128
+#define QEI_CTL_VELEN 0x00000020 // Capture Velocity
+#define QEI_CTL_RESMODE 0x00000010 // Reset Mode
+#define QEI_CTL_CAPMODE 0x00000008 // Capture Mode
+#define QEI_CTL_SIGMODE 0x00000004 // Signal Mode
+#define QEI_CTL_SWAP 0x00000002 // Swap Signals
+#define QEI_CTL_ENABLE 0x00000001 // Enable QEI
+#define QEI_CTL_FILTCNT_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_STAT register.
+//
+//*****************************************************************************
+#define QEI_STAT_DIRECTION 0x00000002 // Direction of Rotation
+#define QEI_STAT_ERROR 0x00000001 // Error Detected
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_POS register.
+//
+//*****************************************************************************
+#define QEI_POS_M 0xFFFFFFFF // Current Position Integrator
+ // Value
+#define QEI_POS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_MAXPOS register.
+//
+//*****************************************************************************
+#define QEI_MAXPOS_M 0xFFFFFFFF // Maximum Position Integrator
+ // Value
+#define QEI_MAXPOS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_LOAD register.
+//
+//*****************************************************************************
+#define QEI_LOAD_M 0xFFFFFFFF // Velocity Timer Load Value
+#define QEI_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_TIME register.
+//
+//*****************************************************************************
+#define QEI_TIME_M 0xFFFFFFFF // Velocity Timer Current Value
+#define QEI_TIME_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_COUNT register.
+//
+//*****************************************************************************
+#define QEI_COUNT_M 0xFFFFFFFF // Velocity Pulse Count
+#define QEI_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_SPEED register.
+//
+//*****************************************************************************
+#define QEI_SPEED_M 0xFFFFFFFF // Velocity
+#define QEI_SPEED_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_INTEN register.
+//
+//*****************************************************************************
+#define QEI_INTEN_ERROR 0x00000008 // Phase Error Interrupt Enable
+#define QEI_INTEN_DIR 0x00000004 // Direction Change Interrupt
+ // Enable
+#define QEI_INTEN_TIMER 0x00000002 // Timer Expires Interrupt Enable
+#define QEI_INTEN_INDEX 0x00000001 // Index Pulse Detected Interrupt
+ // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_RIS register.
+//
+//*****************************************************************************
+#define QEI_RIS_ERROR 0x00000008 // Phase Error Detected
+#define QEI_RIS_DIR 0x00000004 // Direction Change Detected
+#define QEI_RIS_TIMER 0x00000002 // Velocity Timer Expired
+#define QEI_RIS_INDEX 0x00000001 // Index Pulse Asserted
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the QEI_O_ISC register.
+//
+//*****************************************************************************
+#define QEI_ISC_ERROR 0x00000008 // Phase Error Interrupt
+#define QEI_ISC_DIR 0x00000004 // Direction Change Interrupt
+#define QEI_ISC_TIMER 0x00000002 // Velocity Timer Expired Interrupt
+#define QEI_ISC_INDEX 0x00000001 // Index Pulse Interrupt
+
+#endif // __HW_QEI_H__
diff --git a/os/common/ext/TivaWare/inc/hw_shamd5.h b/os/common/ext/TivaWare/inc/hw_shamd5.h
new file mode 100644
index 0000000..1f697fe
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_shamd5.h
@@ -0,0 +1,548 @@
+//*****************************************************************************
+//
+// hw_shamd5.h - Macros used when accessing the SHA/MD5 hardware.
+//
+// Copyright (c) 2012-2016 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_SHAMD5_H__
+#define __HW_SHAMD5_H__
+
+//*****************************************************************************
+//
+// The following are defines for the SHA/MD5 register offsets.
+//
+//*****************************************************************************
+#define SHAMD5_O_ODIGEST_A 0x00000000 // SHA Outer Digest A
+#define SHAMD5_O_ODIGEST_B 0x00000004 // SHA Outer Digest B
+#define SHAMD5_O_ODIGEST_C 0x00000008 // SHA Outer Digest C
+#define SHAMD5_O_ODIGEST_D 0x0000000C // SHA Outer Digest D
+#define SHAMD5_O_ODIGEST_E 0x00000010 // SHA Outer Digest E
+#define SHAMD5_O_ODIGEST_F 0x00000014 // SHA Outer Digest F
+#define SHAMD5_O_ODIGEST_G 0x00000018 // SHA Outer Digest G
+#define SHAMD5_O_ODIGEST_H 0x0000001C // SHA Outer Digest H
+#define SHAMD5_O_IDIGEST_A 0x00000020 // SHA Inner Digest A
+#define SHAMD5_O_IDIGEST_B 0x00000024 // SHA Inner Digest B
+#define SHAMD5_O_IDIGEST_C 0x00000028 // SHA Inner Digest C
+#define SHAMD5_O_IDIGEST_D 0x0000002C // SHA Inner Digest D
+#define SHAMD5_O_IDIGEST_E 0x00000030 // SHA Inner Digest E
+#define SHAMD5_O_IDIGEST_F 0x00000034 // SHA Inner Digest F
+#define SHAMD5_O_IDIGEST_G 0x00000038 // SHA Inner Digest G
+#define SHAMD5_O_IDIGEST_H 0x0000003C // SHA Inner Digest H
+#define SHAMD5_O_DIGEST_COUNT 0x00000040 // SHA Digest Count
+#define SHAMD5_O_MODE 0x00000044 // SHA Mode
+#define SHAMD5_O_LENGTH 0x00000048 // SHA Length
+#define SHAMD5_O_DATA_0_IN 0x00000080 // SHA Data 0 Input
+#define SHAMD5_O_DATA_1_IN 0x00000084 // SHA Data 1 Input
+#define SHAMD5_O_DATA_2_IN 0x00000088 // SHA Data 2 Input
+#define SHAMD5_O_DATA_3_IN 0x0000008C // SHA Data 3 Input
+#define SHAMD5_O_DATA_4_IN 0x00000090 // SHA Data 4 Input
+#define SHAMD5_O_DATA_5_IN 0x00000094 // SHA Data 5 Input
+#define SHAMD5_O_DATA_6_IN 0x00000098 // SHA Data 6 Input
+#define SHAMD5_O_DATA_7_IN 0x0000009C // SHA Data 7 Input
+#define SHAMD5_O_DATA_8_IN 0x000000A0 // SHA Data 8 Input
+#define SHAMD5_O_DATA_9_IN 0x000000A4 // SHA Data 9 Input
+#define SHAMD5_O_DATA_10_IN 0x000000A8 // SHA Data 10 Input
+#define SHAMD5_O_DATA_11_IN 0x000000AC // SHA Data 11 Input
+#define SHAMD5_O_DATA_12_IN 0x000000B0 // SHA Data 12 Input
+#define SHAMD5_O_DATA_13_IN 0x000000B4 // SHA Data 13 Input
+#define SHAMD5_O_DATA_14_IN 0x000000B8 // SHA Data 14 Input
+#define SHAMD5_O_DATA_15_IN 0x000000BC // SHA Data 15 Input
+#define SHAMD5_O_REVISION 0x00000100 // SHA Revision
+#define SHAMD5_O_SYSCONFIG 0x00000110 // SHA System Configuration
+#define SHAMD5_O_SYSSTATUS 0x00000114 // SHA System Status
+#define SHAMD5_O_IRQSTATUS 0x00000118 // SHA Interrupt Status
+#define SHAMD5_O_IRQENABLE 0x0000011C // SHA Interrupt Enable
+#define SHAMD5_O_DMAIM 0xFFFFC010 // SHA DMA Interrupt Mask
+#define SHAMD5_O_DMARIS 0xFFFFC014 // SHA DMA Raw Interrupt Status
+#define SHAMD5_O_DMAMIS 0xFFFFC018 // SHA DMA Masked Interrupt Status
+#define SHAMD5_O_DMAIC 0xFFFFC01C // SHA DMA Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_A
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_ODIGEST_A_DATA_M 0xFFFFFFFF // Digest/Key Data
+#define SHAMD5_ODIGEST_A_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_B
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_ODIGEST_B_DATA_M 0xFFFFFFFF // Digest/Key Data
+#define SHAMD5_ODIGEST_B_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_C
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_ODIGEST_C_DATA_M 0xFFFFFFFF // Digest/Key Data
+#define SHAMD5_ODIGEST_C_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_D
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_ODIGEST_D_DATA_M 0xFFFFFFFF // Digest/Key Data
+#define SHAMD5_ODIGEST_D_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_E
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_ODIGEST_E_DATA_M 0xFFFFFFFF // Digest/Key Data
+#define SHAMD5_ODIGEST_E_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_F
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_ODIGEST_F_DATA_M 0xFFFFFFFF // Digest/Key Data
+#define SHAMD5_ODIGEST_F_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_G
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_ODIGEST_G_DATA_M 0xFFFFFFFF // Digest/Key Data
+#define SHAMD5_ODIGEST_G_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_ODIGEST_H
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_ODIGEST_H_DATA_M 0xFFFFFFFF // Digest/Key Data
+#define SHAMD5_ODIGEST_H_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_A
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IDIGEST_A_DATA_M 0xFFFFFFFF // Digest/Key Data
+#define SHAMD5_IDIGEST_A_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_B
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IDIGEST_B_DATA_M 0xFFFFFFFF // Digest/Key Data
+#define SHAMD5_IDIGEST_B_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_C
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IDIGEST_C_DATA_M 0xFFFFFFFF // Digest/Key Data
+#define SHAMD5_IDIGEST_C_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_D
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IDIGEST_D_DATA_M 0xFFFFFFFF // Digest/Key Data
+#define SHAMD5_IDIGEST_D_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_E
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IDIGEST_E_DATA_M 0xFFFFFFFF // Digest/Key Data
+#define SHAMD5_IDIGEST_E_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_F
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IDIGEST_F_DATA_M 0xFFFFFFFF // Digest/Key Data
+#define SHAMD5_IDIGEST_F_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_G
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IDIGEST_G_DATA_M 0xFFFFFFFF // Digest/Key Data
+#define SHAMD5_IDIGEST_G_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IDIGEST_H
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IDIGEST_H_DATA_M 0xFFFFFFFF // Digest/Key Data
+#define SHAMD5_IDIGEST_H_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DIGEST_COUNT
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DIGEST_COUNT_M 0xFFFFFFFF // Digest Count
+#define SHAMD5_DIGEST_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_MODE register.
+//
+//*****************************************************************************
+#define SHAMD5_MODE_HMAC_OUTER_HASH \
+ 0x00000080 // HMAC Outer Hash Processing
+ // Enable
+#define SHAMD5_MODE_HMAC_KEY_PROC \
+ 0x00000020 // HMAC Key Processing Enable
+#define SHAMD5_MODE_CLOSE_HASH 0x00000010 // Performs the padding, the
+ // Hash/HMAC will be 'closed' at
+ // the end of the block, as per
+ // MD5/SHA-1/SHA-2 specification
+#define SHAMD5_MODE_ALGO_CONSTANT \
+ 0x00000008 // The initial digest register will
+ // be overwritten with the
+ // algorithm constants for the
+ // selected algorithm when hashing
+ // and the initial digest count
+ // register will be reset to 0
+#define SHAMD5_MODE_ALGO_M 0x00000007 // Hash Algorithm
+#define SHAMD5_MODE_ALGO_MD5 0x00000000 // MD5
+#define SHAMD5_MODE_ALGO_SHA1 0x00000002 // SHA-1
+#define SHAMD5_MODE_ALGO_SHA224 0x00000004 // SHA-224
+#define SHAMD5_MODE_ALGO_SHA256 0x00000006 // SHA-256
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_LENGTH
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_LENGTH_M 0xFFFFFFFF // Block Length/Remaining Byte
+ // Count
+#define SHAMD5_LENGTH_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_0_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_0_IN_DATA_M 0xFFFFFFFF // Digest/Key Data
+#define SHAMD5_DATA_0_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_1_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_1_IN_DATA_M 0xFFFFFFFF // Digest/Key Data
+#define SHAMD5_DATA_1_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_2_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_2_IN_DATA_M 0xFFFFFFFF // Digest/Key Data
+#define SHAMD5_DATA_2_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_3_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_3_IN_DATA_M 0xFFFFFFFF // Digest/Key Data
+#define SHAMD5_DATA_3_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_4_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_4_IN_DATA_M 0xFFFFFFFF // Digest/Key Data
+#define SHAMD5_DATA_4_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_5_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_5_IN_DATA_M 0xFFFFFFFF // Digest/Key Data
+#define SHAMD5_DATA_5_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_6_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_6_IN_DATA_M 0xFFFFFFFF // Digest/Key Data
+#define SHAMD5_DATA_6_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_7_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_7_IN_DATA_M 0xFFFFFFFF // Digest/Key Data
+#define SHAMD5_DATA_7_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_8_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_8_IN_DATA_M 0xFFFFFFFF // Digest/Key Data
+#define SHAMD5_DATA_8_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_9_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_9_IN_DATA_M 0xFFFFFFFF // Digest/Key Data
+#define SHAMD5_DATA_9_IN_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_10_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_10_IN_DATA_M \
+ 0xFFFFFFFF // Digest/Key Data
+#define SHAMD5_DATA_10_IN_DATA_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_11_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_11_IN_DATA_M \
+ 0xFFFFFFFF // Digest/Key Data
+#define SHAMD5_DATA_11_IN_DATA_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_12_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_12_IN_DATA_M \
+ 0xFFFFFFFF // Digest/Key Data
+#define SHAMD5_DATA_12_IN_DATA_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_13_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_13_IN_DATA_M \
+ 0xFFFFFFFF // Digest/Key Data
+#define SHAMD5_DATA_13_IN_DATA_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_14_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_14_IN_DATA_M \
+ 0xFFFFFFFF // Digest/Key Data
+#define SHAMD5_DATA_14_IN_DATA_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DATA_15_IN
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DATA_15_IN_DATA_M \
+ 0xFFFFFFFF // Digest/Key Data
+#define SHAMD5_DATA_15_IN_DATA_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_REVISION
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_REVISION_M 0xFFFFFFFF // Revision Number
+#define SHAMD5_REVISION_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_SYSCONFIG
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_SYSCONFIG_SADVANCED \
+ 0x00000080 // Advanced Mode Enable
+#define SHAMD5_SYSCONFIG_SIDLE_M \
+ 0x00000030 // Sidle mode
+#define SHAMD5_SYSCONFIG_SIDLE_FORCE \
+ 0x00000000 // Force-idle mode
+#define SHAMD5_SYSCONFIG_DMA_EN 0x00000008 // uDMA Request Enable
+#define SHAMD5_SYSCONFIG_IT_EN 0x00000004 // Interrupt Enable
+#define SHAMD5_SYSCONFIG_SOFTRESET \
+ 0x00000002 // Soft reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_SYSSTATUS
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_SYSSTATUS_RESETDONE \
+ 0x00000001 // Reset done status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IRQSTATUS
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IRQSTATUS_CONTEXT_READY \
+ 0x00000008 // Context Ready Status
+#define SHAMD5_IRQSTATUS_INPUT_READY \
+ 0x00000002 // Input Ready Status
+#define SHAMD5_IRQSTATUS_OUTPUT_READY \
+ 0x00000001 // Output Ready Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_IRQENABLE
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_IRQENABLE_CONTEXT_READY \
+ 0x00000008 // Mask for context ready interrupt
+#define SHAMD5_IRQENABLE_INPUT_READY \
+ 0x00000002 // Mask for input ready interrupt
+#define SHAMD5_IRQENABLE_OUTPUT_READY \
+ 0x00000001 // Mask for output ready interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DMAIM register.
+//
+//*****************************************************************************
+#define SHAMD5_DMAIM_COUT 0x00000004 // Context Out DMA Done Interrupt
+ // Mask
+#define SHAMD5_DMAIM_DIN 0x00000002 // Data In DMA Done Interrupt Mask
+#define SHAMD5_DMAIM_CIN 0x00000001 // Context In DMA Done Interrupt
+ // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DMARIS
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DMARIS_COUT 0x00000004 // Context Out DMA Done Raw
+ // Interrupt Status
+#define SHAMD5_DMARIS_DIN 0x00000002 // Data In DMA Done Raw Interrupt
+ // Status
+#define SHAMD5_DMARIS_CIN 0x00000001 // Context In DMA Done Raw
+ // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DMAMIS
+// register.
+//
+//*****************************************************************************
+#define SHAMD5_DMAMIS_COUT 0x00000004 // Context Out DMA Done Masked
+ // Interrupt Status
+#define SHAMD5_DMAMIS_DIN 0x00000002 // Data In DMA Done Masked
+ // Interrupt Status
+#define SHAMD5_DMAMIS_CIN 0x00000001 // Context In DMA Done Raw
+ // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SHAMD5_O_DMAIC register.
+//
+//*****************************************************************************
+#define SHAMD5_DMAIC_COUT 0x00000004 // Context Out DMA Done Masked
+ // Interrupt Status
+#define SHAMD5_DMAIC_DIN 0x00000002 // Data In DMA Done Interrupt Clear
+#define SHAMD5_DMAIC_CIN 0x00000001 // Context In DMA Done Raw
+ // Interrupt Status
+
+#endif // __HW_SHAMD5_H__
diff --git a/os/common/ext/TivaWare/inc/hw_ssi.h b/os/common/ext/TivaWare/inc/hw_ssi.h
new file mode 100644
index 0000000..3a1503d
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_ssi.h
@@ -0,0 +1,237 @@
+//*****************************************************************************
+//
+// hw_ssi.h - Macros used when accessing the SSI hardware.
+//
+// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_SSI_H__
+#define __HW_SSI_H__
+
+//*****************************************************************************
+//
+// The following are defines for the SSI register offsets.
+//
+//*****************************************************************************
+#define SSI_O_CR0 0x00000000 // SSI Control 0
+#define SSI_O_CR1 0x00000004 // SSI Control 1
+#define SSI_O_DR 0x00000008 // SSI Data
+#define SSI_O_SR 0x0000000C // SSI Status
+#define SSI_O_CPSR 0x00000010 // SSI Clock Prescale
+#define SSI_O_IM 0x00000014 // SSI Interrupt Mask
+#define SSI_O_RIS 0x00000018 // SSI Raw Interrupt Status
+#define SSI_O_MIS 0x0000001C // SSI Masked Interrupt Status
+#define SSI_O_ICR 0x00000020 // SSI Interrupt Clear
+#define SSI_O_DMACTL 0x00000024 // SSI DMA Control
+#define SSI_O_PP 0x00000FC0 // SSI Peripheral Properties
+#define SSI_O_CC 0x00000FC8 // SSI Clock Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CR0 register.
+//
+//*****************************************************************************
+#define SSI_CR0_SCR_M 0x0000FF00 // SSI Serial Clock Rate
+#define SSI_CR0_SPH 0x00000080 // SSI Serial Clock Phase
+#define SSI_CR0_SPO 0x00000040 // SSI Serial Clock Polarity
+#define SSI_CR0_FRF_M 0x00000030 // SSI Frame Format Select
+#define SSI_CR0_FRF_MOTO 0x00000000 // Freescale SPI Frame Format
+#define SSI_CR0_FRF_TI 0x00000010 // Synchronous Serial Frame Format
+#define SSI_CR0_FRF_NMW 0x00000020 // MICROWIRE Frame Format
+#define SSI_CR0_DSS_M 0x0000000F // SSI Data Size Select
+#define SSI_CR0_DSS_4 0x00000003 // 4-bit data
+#define SSI_CR0_DSS_5 0x00000004 // 5-bit data
+#define SSI_CR0_DSS_6 0x00000005 // 6-bit data
+#define SSI_CR0_DSS_7 0x00000006 // 7-bit data
+#define SSI_CR0_DSS_8 0x00000007 // 8-bit data
+#define SSI_CR0_DSS_9 0x00000008 // 9-bit data
+#define SSI_CR0_DSS_10 0x00000009 // 10-bit data
+#define SSI_CR0_DSS_11 0x0000000A // 11-bit data
+#define SSI_CR0_DSS_12 0x0000000B // 12-bit data
+#define SSI_CR0_DSS_13 0x0000000C // 13-bit data
+#define SSI_CR0_DSS_14 0x0000000D // 14-bit data
+#define SSI_CR0_DSS_15 0x0000000E // 15-bit data
+#define SSI_CR0_DSS_16 0x0000000F // 16-bit data
+#define SSI_CR0_SCR_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CR1 register.
+//
+//*****************************************************************************
+#define SSI_CR1_EOM 0x00000800 // Stop Frame (End of Message)
+#define SSI_CR1_FSSHLDFRM 0x00000400 // FSS Hold Frame
+#define SSI_CR1_HSCLKEN 0x00000200 // High Speed Clock Enable
+#define SSI_CR1_DIR 0x00000100 // SSI Direction of Operation
+#define SSI_CR1_MODE_M 0x000000C0 // SSI Mode
+#define SSI_CR1_MODE_LEGACY 0x00000000 // Legacy SSI mode
+#define SSI_CR1_MODE_BI 0x00000040 // Bi-SSI mode
+#define SSI_CR1_MODE_QUAD 0x00000080 // Quad-SSI Mode
+#define SSI_CR1_MODE_ADVANCED 0x000000C0 // Advanced SSI Mode with 8-bit
+ // packet size
+#define SSI_CR1_EOT 0x00000010 // End of Transmission
+#define SSI_CR1_MS 0x00000004 // SSI Master/Slave Select
+#define SSI_CR1_SSE 0x00000002 // SSI Synchronous Serial Port
+ // Enable
+#define SSI_CR1_LBM 0x00000001 // SSI Loopback Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_DR register.
+//
+//*****************************************************************************
+#define SSI_DR_DATA_M 0x0000FFFF // SSI Receive/Transmit Data
+#define SSI_DR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_SR register.
+//
+//*****************************************************************************
+#define SSI_SR_BSY 0x00000010 // SSI Busy Bit
+#define SSI_SR_RFF 0x00000008 // SSI Receive FIFO Full
+#define SSI_SR_RNE 0x00000004 // SSI Receive FIFO Not Empty
+#define SSI_SR_TNF 0x00000002 // SSI Transmit FIFO Not Full
+#define SSI_SR_TFE 0x00000001 // SSI Transmit FIFO Empty
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CPSR register.
+//
+//*****************************************************************************
+#define SSI_CPSR_CPSDVSR_M 0x000000FF // SSI Clock Prescale Divisor
+#define SSI_CPSR_CPSDVSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_IM register.
+//
+//*****************************************************************************
+#define SSI_IM_EOTIM 0x00000040 // End of Transmit Interrupt Mask
+#define SSI_IM_DMATXIM 0x00000020 // SSI Transmit DMA Interrupt Mask
+#define SSI_IM_DMARXIM 0x00000010 // SSI Receive DMA Interrupt Mask
+#define SSI_IM_TXIM 0x00000008 // SSI Transmit FIFO Interrupt Mask
+#define SSI_IM_RXIM 0x00000004 // SSI Receive FIFO Interrupt Mask
+#define SSI_IM_RTIM 0x00000002 // SSI Receive Time-Out Interrupt
+ // Mask
+#define SSI_IM_RORIM 0x00000001 // SSI Receive Overrun Interrupt
+ // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_RIS register.
+//
+//*****************************************************************************
+#define SSI_RIS_EOTRIS 0x00000040 // End of Transmit Raw Interrupt
+ // Status
+#define SSI_RIS_DMATXRIS 0x00000020 // SSI Transmit DMA Raw Interrupt
+ // Status
+#define SSI_RIS_DMARXRIS 0x00000010 // SSI Receive DMA Raw Interrupt
+ // Status
+#define SSI_RIS_TXRIS 0x00000008 // SSI Transmit FIFO Raw Interrupt
+ // Status
+#define SSI_RIS_RXRIS 0x00000004 // SSI Receive FIFO Raw Interrupt
+ // Status
+#define SSI_RIS_RTRIS 0x00000002 // SSI Receive Time-Out Raw
+ // Interrupt Status
+#define SSI_RIS_RORRIS 0x00000001 // SSI Receive Overrun Raw
+ // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_MIS register.
+//
+//*****************************************************************************
+#define SSI_MIS_EOTMIS 0x00000040 // End of Transmit Masked Interrupt
+ // Status
+#define SSI_MIS_DMATXMIS 0x00000020 // SSI Transmit DMA Masked
+ // Interrupt Status
+#define SSI_MIS_DMARXMIS 0x00000010 // SSI Receive DMA Masked Interrupt
+ // Status
+#define SSI_MIS_TXMIS 0x00000008 // SSI Transmit FIFO Masked
+ // Interrupt Status
+#define SSI_MIS_RXMIS 0x00000004 // SSI Receive FIFO Masked
+ // Interrupt Status
+#define SSI_MIS_RTMIS 0x00000002 // SSI Receive Time-Out Masked
+ // Interrupt Status
+#define SSI_MIS_RORMIS 0x00000001 // SSI Receive Overrun Masked
+ // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_ICR register.
+//
+//*****************************************************************************
+#define SSI_ICR_EOTIC 0x00000040 // End of Transmit Interrupt Clear
+#define SSI_ICR_DMATXIC 0x00000020 // SSI Transmit DMA Interrupt Clear
+#define SSI_ICR_DMARXIC 0x00000010 // SSI Receive DMA Interrupt Clear
+#define SSI_ICR_RTIC 0x00000002 // SSI Receive Time-Out Interrupt
+ // Clear
+#define SSI_ICR_RORIC 0x00000001 // SSI Receive Overrun Interrupt
+ // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_DMACTL register.
+//
+//*****************************************************************************
+#define SSI_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable
+#define SSI_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_PP register.
+//
+//*****************************************************************************
+#define SSI_PP_FSSHLDFRM 0x00000008 // FSS Hold Frame Capability
+#define SSI_PP_MODE_M 0x00000006 // Mode of Operation
+#define SSI_PP_MODE_LEGACY 0x00000000 // Legacy SSI mode
+#define SSI_PP_MODE_ADVBI 0x00000002 // Legacy mode, Advanced SSI mode
+ // and Bi-SSI mode enabled
+#define SSI_PP_MODE_ADVBIQUAD 0x00000004 // Legacy mode, Advanced mode,
+ // Bi-SSI and Quad-SSI mode enabled
+#define SSI_PP_HSCLK 0x00000001 // High Speed Capability
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SSI_O_CC register.
+//
+//*****************************************************************************
+#define SSI_CC_CS_M 0x0000000F // SSI Baud Clock Source
+#define SSI_CC_CS_SYSPLL 0x00000000 // System clock (based on clock
+ // source and divisor factor)
+#define SSI_CC_CS_PIOSC 0x00000005 // PIOSC
+
+#endif // __HW_SSI_H__
diff --git a/os/common/ext/TivaWare/inc/hw_sysctl.h b/os/common/ext/TivaWare/inc/hw_sysctl.h
new file mode 100644
index 0000000..6f78204
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_sysctl.h
@@ -0,0 +1,3749 @@
+//*****************************************************************************
+//
+// hw_sysctl.h - Macros used when accessing the system control hardware.
+//
+// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_SYSCTL_H__
+#define __HW_SYSCTL_H__
+
+//*****************************************************************************
+//
+// The following are defines for the System Control register addresses.
+//
+//*****************************************************************************
+#define SYSCTL_DID0 0x400FE000 // Device Identification 0
+#define SYSCTL_DID1 0x400FE004 // Device Identification 1
+#define SYSCTL_DC0 0x400FE008 // Device Capabilities 0
+#define SYSCTL_DC1 0x400FE010 // Device Capabilities 1
+#define SYSCTL_DC2 0x400FE014 // Device Capabilities 2
+#define SYSCTL_DC3 0x400FE018 // Device Capabilities 3
+#define SYSCTL_DC4 0x400FE01C // Device Capabilities 4
+#define SYSCTL_DC5 0x400FE020 // Device Capabilities 5
+#define SYSCTL_DC6 0x400FE024 // Device Capabilities 6
+#define SYSCTL_DC7 0x400FE028 // Device Capabilities 7
+#define SYSCTL_DC8 0x400FE02C // Device Capabilities 8
+#define SYSCTL_PBORCTL 0x400FE030 // Brown-Out Reset Control
+#define SYSCTL_PTBOCTL 0x400FE038 // Power-Temp Brown Out Control
+#define SYSCTL_SRCR0 0x400FE040 // Software Reset Control 0
+#define SYSCTL_SRCR1 0x400FE044 // Software Reset Control 1
+#define SYSCTL_SRCR2 0x400FE048 // Software Reset Control 2
+#define SYSCTL_RIS 0x400FE050 // Raw Interrupt Status
+#define SYSCTL_IMC 0x400FE054 // Interrupt Mask Control
+#define SYSCTL_MISC 0x400FE058 // Masked Interrupt Status and
+ // Clear
+#define SYSCTL_RESC 0x400FE05C // Reset Cause
+#define SYSCTL_PWRTC 0x400FE060 // Power-Temperature Cause
+#define SYSCTL_RCC 0x400FE060 // Run-Mode Clock Configuration
+#define SYSCTL_NMIC 0x400FE064 // NMI Cause Register
+#define SYSCTL_GPIOHBCTL 0x400FE06C // GPIO High-Performance Bus
+ // Control
+#define SYSCTL_RCC2 0x400FE070 // Run-Mode Clock Configuration 2
+#define SYSCTL_MOSCCTL 0x400FE07C // Main Oscillator Control
+#define SYSCTL_RSCLKCFG 0x400FE0B0 // Run and Sleep Mode Configuration
+ // Register
+#define SYSCTL_MEMTIM0 0x400FE0C0 // Memory Timing Parameter Register
+ // 0 for Main Flash and EEPROM
+#define SYSCTL_RCGC0 0x400FE100 // Run Mode Clock Gating Control
+ // Register 0
+#define SYSCTL_RCGC1 0x400FE104 // Run Mode Clock Gating Control
+ // Register 1
+#define SYSCTL_RCGC2 0x400FE108 // Run Mode Clock Gating Control
+ // Register 2
+#define SYSCTL_SCGC0 0x400FE110 // Sleep Mode Clock Gating Control
+ // Register 0
+#define SYSCTL_SCGC1 0x400FE114 // Sleep Mode Clock Gating Control
+ // Register 1
+#define SYSCTL_SCGC2 0x400FE118 // Sleep Mode Clock Gating Control
+ // Register 2
+#define SYSCTL_DCGC0 0x400FE120 // Deep Sleep Mode Clock Gating
+ // Control Register 0
+#define SYSCTL_DCGC1 0x400FE124 // Deep-Sleep Mode Clock Gating
+ // Control Register 1
+#define SYSCTL_DCGC2 0x400FE128 // Deep Sleep Mode Clock Gating
+ // Control Register 2
+#define SYSCTL_ALTCLKCFG 0x400FE138 // Alternate Clock Configuration
+#define SYSCTL_DSLPCLKCFG 0x400FE144 // Deep Sleep Clock Configuration
+#define SYSCTL_DSCLKCFG 0x400FE144 // Deep Sleep Clock Configuration
+ // Register
+#define SYSCTL_DIVSCLK 0x400FE148 // Divisor and Source Clock
+ // Configuration
+#define SYSCTL_SYSPROP 0x400FE14C // System Properties
+#define SYSCTL_PIOSCCAL 0x400FE150 // Precision Internal Oscillator
+ // Calibration
+#define SYSCTL_PIOSCSTAT 0x400FE154 // Precision Internal Oscillator
+ // Statistics
+#define SYSCTL_PLLFREQ0 0x400FE160 // PLL Frequency 0
+#define SYSCTL_PLLFREQ1 0x400FE164 // PLL Frequency 1
+#define SYSCTL_PLLSTAT 0x400FE168 // PLL Status
+#define SYSCTL_SLPPWRCFG 0x400FE188 // Sleep Power Configuration
+#define SYSCTL_DSLPPWRCFG 0x400FE18C // Deep-Sleep Power Configuration
+#define SYSCTL_DC9 0x400FE190 // Device Capabilities 9
+#define SYSCTL_NVMSTAT 0x400FE1A0 // Non-Volatile Memory Information
+#define SYSCTL_LDOSPCTL 0x400FE1B4 // LDO Sleep Power Control
+#define SYSCTL_LDODPCTL 0x400FE1BC // LDO Deep-Sleep Power Control
+#define SYSCTL_RESBEHAVCTL 0x400FE1D8 // Reset Behavior Control Register
+#define SYSCTL_HSSR 0x400FE1F4 // Hardware System Service Request
+#define SYSCTL_USBPDS 0x400FE280 // USB Power Domain Status
+#define SYSCTL_USBMPC 0x400FE284 // USB Memory Power Control
+#define SYSCTL_EMACPDS 0x400FE288 // Ethernet MAC Power Domain Status
+#define SYSCTL_EMACMPC 0x400FE28C // Ethernet MAC Memory Power
+ // Control
+#define SYSCTL_LCDMPC 0x400FE294 // LCD Memory Power Control
+#define SYSCTL_PPWD 0x400FE300 // Watchdog Timer Peripheral
+ // Present
+#define SYSCTL_PPTIMER 0x400FE304 // 16/32-Bit General-Purpose Timer
+ // Peripheral Present
+#define SYSCTL_PPGPIO 0x400FE308 // General-Purpose Input/Output
+ // Peripheral Present
+#define SYSCTL_PPDMA 0x400FE30C // Micro Direct Memory Access
+ // Peripheral Present
+#define SYSCTL_PPEPI 0x400FE310 // EPI Peripheral Present
+#define SYSCTL_PPHIB 0x400FE314 // Hibernation Peripheral Present
+#define SYSCTL_PPUART 0x400FE318 // Universal Asynchronous
+ // Receiver/Transmitter Peripheral
+ // Present
+#define SYSCTL_PPSSI 0x400FE31C // Synchronous Serial Interface
+ // Peripheral Present
+#define SYSCTL_PPI2C 0x400FE320 // Inter-Integrated Circuit
+ // Peripheral Present
+#define SYSCTL_PPUSB 0x400FE328 // Universal Serial Bus Peripheral
+ // Present
+#define SYSCTL_PPEPHY 0x400FE330 // Ethernet PHY Peripheral Present
+#define SYSCTL_PPCAN 0x400FE334 // Controller Area Network
+ // Peripheral Present
+#define SYSCTL_PPADC 0x400FE338 // Analog-to-Digital Converter
+ // Peripheral Present
+#define SYSCTL_PPACMP 0x400FE33C // Analog Comparator Peripheral
+ // Present
+#define SYSCTL_PPPWM 0x400FE340 // Pulse Width Modulator Peripheral
+ // Present
+#define SYSCTL_PPQEI 0x400FE344 // Quadrature Encoder Interface
+ // Peripheral Present
+#define SYSCTL_PPLPC 0x400FE348 // Low Pin Count Interface
+ // Peripheral Present
+#define SYSCTL_PPPECI 0x400FE350 // Platform Environment Control
+ // Interface Peripheral Present
+#define SYSCTL_PPFAN 0x400FE354 // Fan Control Peripheral Present
+#define SYSCTL_PPEEPROM 0x400FE358 // EEPROM Peripheral Present
+#define SYSCTL_PPWTIMER 0x400FE35C // 32/64-Bit Wide General-Purpose
+ // Timer Peripheral Present
+#define SYSCTL_PPRTS 0x400FE370 // Remote Temperature Sensor
+ // Peripheral Present
+#define SYSCTL_PPCCM 0x400FE374 // CRC and Cryptographic Modules
+ // Peripheral Present
+#define SYSCTL_PPLCD 0x400FE390 // LCD Peripheral Present
+#define SYSCTL_PPOWIRE 0x400FE398 // 1-Wire Peripheral Present
+#define SYSCTL_PPEMAC 0x400FE39C // Ethernet MAC Peripheral Present
+#define SYSCTL_PPHIM 0x400FE3A4 // Human Interface Master
+ // Peripheral Present
+#define SYSCTL_SRWD 0x400FE500 // Watchdog Timer Software Reset
+#define SYSCTL_SRTIMER 0x400FE504 // 16/32-Bit General-Purpose Timer
+ // Software Reset
+#define SYSCTL_SRGPIO 0x400FE508 // General-Purpose Input/Output
+ // Software Reset
+#define SYSCTL_SRDMA 0x400FE50C // Micro Direct Memory Access
+ // Software Reset
+#define SYSCTL_SREPI 0x400FE510 // EPI Software Reset
+#define SYSCTL_SRHIB 0x400FE514 // Hibernation Software Reset
+#define SYSCTL_SRUART 0x400FE518 // Universal Asynchronous
+ // Receiver/Transmitter Software
+ // Reset
+#define SYSCTL_SRSSI 0x400FE51C // Synchronous Serial Interface
+ // Software Reset
+#define SYSCTL_SRI2C 0x400FE520 // Inter-Integrated Circuit
+ // Software Reset
+#define SYSCTL_SRUSB 0x400FE528 // Universal Serial Bus Software
+ // Reset
+#define SYSCTL_SREPHY 0x400FE530 // Ethernet PHY Software Reset
+#define SYSCTL_SRCAN 0x400FE534 // Controller Area Network Software
+ // Reset
+#define SYSCTL_SRADC 0x400FE538 // Analog-to-Digital Converter
+ // Software Reset
+#define SYSCTL_SRACMP 0x400FE53C // Analog Comparator Software Reset
+#define SYSCTL_SRPWM 0x400FE540 // Pulse Width Modulator Software
+ // Reset
+#define SYSCTL_SRQEI 0x400FE544 // Quadrature Encoder Interface
+ // Software Reset
+#define SYSCTL_SREEPROM 0x400FE558 // EEPROM Software Reset
+#define SYSCTL_SRWTIMER 0x400FE55C // 32/64-Bit Wide General-Purpose
+ // Timer Software Reset
+#define SYSCTL_SRCCM 0x400FE574 // CRC and Cryptographic Modules
+ // Software Reset
+#define SYSCTL_SRLCD 0x400FE590 // LCD Controller Software Reset
+#define SYSCTL_SROWIRE 0x400FE598 // 1-Wire Software Reset
+#define SYSCTL_SREMAC 0x400FE59C // Ethernet MAC Software Reset
+#define SYSCTL_RCGCWD 0x400FE600 // Watchdog Timer Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCTIMER 0x400FE604 // 16/32-Bit General-Purpose Timer
+ // Run Mode Clock Gating Control
+#define SYSCTL_RCGCGPIO 0x400FE608 // General-Purpose Input/Output Run
+ // Mode Clock Gating Control
+#define SYSCTL_RCGCDMA 0x400FE60C // Micro Direct Memory Access Run
+ // Mode Clock Gating Control
+#define SYSCTL_RCGCEPI 0x400FE610 // EPI Run Mode Clock Gating
+ // Control
+#define SYSCTL_RCGCHIB 0x400FE614 // Hibernation Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART 0x400FE618 // Universal Asynchronous
+ // Receiver/Transmitter Run Mode
+ // Clock Gating Control
+#define SYSCTL_RCGCSSI 0x400FE61C // Synchronous Serial Interface Run
+ // Mode Clock Gating Control
+#define SYSCTL_RCGCI2C 0x400FE620 // Inter-Integrated Circuit Run
+ // Mode Clock Gating Control
+#define SYSCTL_RCGCUSB 0x400FE628 // Universal Serial Bus Run Mode
+ // Clock Gating Control
+#define SYSCTL_RCGCEPHY 0x400FE630 // Ethernet PHY Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCCAN 0x400FE634 // Controller Area Network Run Mode
+ // Clock Gating Control
+#define SYSCTL_RCGCADC 0x400FE638 // Analog-to-Digital Converter Run
+ // Mode Clock Gating Control
+#define SYSCTL_RCGCACMP 0x400FE63C // Analog Comparator Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCPWM 0x400FE640 // Pulse Width Modulator Run Mode
+ // Clock Gating Control
+#define SYSCTL_RCGCQEI 0x400FE644 // Quadrature Encoder Interface Run
+ // Mode Clock Gating Control
+#define SYSCTL_RCGCEEPROM 0x400FE658 // EEPROM Run Mode Clock Gating
+ // Control
+#define SYSCTL_RCGCWTIMER 0x400FE65C // 32/64-Bit Wide General-Purpose
+ // Timer Run Mode Clock Gating
+ // Control
+#define SYSCTL_RCGCCCM 0x400FE674 // CRC and Cryptographic Modules
+ // Run Mode Clock Gating Control
+#define SYSCTL_RCGCLCD 0x400FE690 // LCD Controller Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCOWIRE 0x400FE698 // 1-Wire Run Mode Clock Gating
+ // Control
+#define SYSCTL_RCGCEMAC 0x400FE69C // Ethernet MAC Run Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCWD 0x400FE700 // Watchdog Timer Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCTIMER 0x400FE704 // 16/32-Bit General-Purpose Timer
+ // Sleep Mode Clock Gating Control
+#define SYSCTL_SCGCGPIO 0x400FE708 // General-Purpose Input/Output
+ // Sleep Mode Clock Gating Control
+#define SYSCTL_SCGCDMA 0x400FE70C // Micro Direct Memory Access Sleep
+ // Mode Clock Gating Control
+#define SYSCTL_SCGCEPI 0x400FE710 // EPI Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCHIB 0x400FE714 // Hibernation Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART 0x400FE718 // Universal Asynchronous
+ // Receiver/Transmitter Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_SCGCSSI 0x400FE71C // Synchronous Serial Interface
+ // Sleep Mode Clock Gating Control
+#define SYSCTL_SCGCI2C 0x400FE720 // Inter-Integrated Circuit Sleep
+ // Mode Clock Gating Control
+#define SYSCTL_SCGCUSB 0x400FE728 // Universal Serial Bus Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_SCGCEPHY 0x400FE730 // Ethernet PHY Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCCAN 0x400FE734 // Controller Area Network Sleep
+ // Mode Clock Gating Control
+#define SYSCTL_SCGCADC 0x400FE738 // Analog-to-Digital Converter
+ // Sleep Mode Clock Gating Control
+#define SYSCTL_SCGCACMP 0x400FE73C // Analog Comparator Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_SCGCPWM 0x400FE740 // Pulse Width Modulator Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_SCGCQEI 0x400FE744 // Quadrature Encoder Interface
+ // Sleep Mode Clock Gating Control
+#define SYSCTL_SCGCEEPROM 0x400FE758 // EEPROM Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCWTIMER 0x400FE75C // 32/64-Bit Wide General-Purpose
+ // Timer Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCCCM 0x400FE774 // CRC and Cryptographic Modules
+ // Sleep Mode Clock Gating Control
+#define SYSCTL_SCGCLCD 0x400FE790 // LCD Controller Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCOWIRE 0x400FE798 // 1-Wire Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCEMAC 0x400FE79C // Ethernet MAC Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_DCGCWD 0x400FE800 // Watchdog Timer Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCTIMER 0x400FE804 // 16/32-Bit General-Purpose Timer
+ // Deep-Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_DCGCGPIO 0x400FE808 // General-Purpose Input/Output
+ // Deep-Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_DCGCDMA 0x400FE80C // Micro Direct Memory Access
+ // Deep-Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_DCGCEPI 0x400FE810 // EPI Deep-Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_DCGCHIB 0x400FE814 // Hibernation Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART 0x400FE818 // Universal Asynchronous
+ // Receiver/Transmitter Deep-Sleep
+ // Mode Clock Gating Control
+#define SYSCTL_DCGCSSI 0x400FE81C // Synchronous Serial Interface
+ // Deep-Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_DCGCI2C 0x400FE820 // Inter-Integrated Circuit
+ // Deep-Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_DCGCUSB 0x400FE828 // Universal Serial Bus Deep-Sleep
+ // Mode Clock Gating Control
+#define SYSCTL_DCGCEPHY 0x400FE830 // Ethernet PHY Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCCAN 0x400FE834 // Controller Area Network
+ // Deep-Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_DCGCADC 0x400FE838 // Analog-to-Digital Converter
+ // Deep-Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_DCGCACMP 0x400FE83C // Analog Comparator Deep-Sleep
+ // Mode Clock Gating Control
+#define SYSCTL_DCGCPWM 0x400FE840 // Pulse Width Modulator Deep-Sleep
+ // Mode Clock Gating Control
+#define SYSCTL_DCGCQEI 0x400FE844 // Quadrature Encoder Interface
+ // Deep-Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_DCGCEEPROM 0x400FE858 // EEPROM Deep-Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_DCGCWTIMER 0x400FE85C // 32/64-Bit Wide General-Purpose
+ // Timer Deep-Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_DCGCCCM 0x400FE874 // CRC and Cryptographic Modules
+ // Deep-Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_DCGCLCD 0x400FE890 // LCD Controller Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCOWIRE 0x400FE898 // 1-Wire Deep-Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_DCGCEMAC 0x400FE89C // Ethernet MAC Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_PCWD 0x400FE900 // Watchdog Timer Power Control
+#define SYSCTL_PCTIMER 0x400FE904 // 16/32-Bit General-Purpose Timer
+ // Power Control
+#define SYSCTL_PCGPIO 0x400FE908 // General-Purpose Input/Output
+ // Power Control
+#define SYSCTL_PCDMA 0x400FE90C // Micro Direct Memory Access Power
+ // Control
+#define SYSCTL_PCEPI 0x400FE910 // External Peripheral Interface
+ // Power Control
+#define SYSCTL_PCHIB 0x400FE914 // Hibernation Power Control
+#define SYSCTL_PCUART 0x400FE918 // Universal Asynchronous
+ // Receiver/Transmitter Power
+ // Control
+#define SYSCTL_PCSSI 0x400FE91C // Synchronous Serial Interface
+ // Power Control
+#define SYSCTL_PCI2C 0x400FE920 // Inter-Integrated Circuit Power
+ // Control
+#define SYSCTL_PCUSB 0x400FE928 // Universal Serial Bus Power
+ // Control
+#define SYSCTL_PCEPHY 0x400FE930 // Ethernet PHY Power Control
+#define SYSCTL_PCCAN 0x400FE934 // Controller Area Network Power
+ // Control
+#define SYSCTL_PCADC 0x400FE938 // Analog-to-Digital Converter
+ // Power Control
+#define SYSCTL_PCACMP 0x400FE93C // Analog Comparator Power Control
+#define SYSCTL_PCPWM 0x400FE940 // Pulse Width Modulator Power
+ // Control
+#define SYSCTL_PCQEI 0x400FE944 // Quadrature Encoder Interface
+ // Power Control
+#define SYSCTL_PCEEPROM 0x400FE958 // EEPROM Power Control
+#define SYSCTL_PCCCM 0x400FE974 // CRC and Cryptographic Modules
+ // Power Control
+#define SYSCTL_PCLCD 0x400FE990 // LCD Controller Power Control
+#define SYSCTL_PCOWIRE 0x400FE998 // 1-Wire Power Control
+#define SYSCTL_PCEMAC 0x400FE99C // Ethernet MAC Power Control
+#define SYSCTL_PRWD 0x400FEA00 // Watchdog Timer Peripheral Ready
+#define SYSCTL_PRTIMER 0x400FEA04 // 16/32-Bit General-Purpose Timer
+ // Peripheral Ready
+#define SYSCTL_PRGPIO 0x400FEA08 // General-Purpose Input/Output
+ // Peripheral Ready
+#define SYSCTL_PRDMA 0x400FEA0C // Micro Direct Memory Access
+ // Peripheral Ready
+#define SYSCTL_PREPI 0x400FEA10 // EPI Peripheral Ready
+#define SYSCTL_PRHIB 0x400FEA14 // Hibernation Peripheral Ready
+#define SYSCTL_PRUART 0x400FEA18 // Universal Asynchronous
+ // Receiver/Transmitter Peripheral
+ // Ready
+#define SYSCTL_PRSSI 0x400FEA1C // Synchronous Serial Interface
+ // Peripheral Ready
+#define SYSCTL_PRI2C 0x400FEA20 // Inter-Integrated Circuit
+ // Peripheral Ready
+#define SYSCTL_PRUSB 0x400FEA28 // Universal Serial Bus Peripheral
+ // Ready
+#define SYSCTL_PREPHY 0x400FEA30 // Ethernet PHY Peripheral Ready
+#define SYSCTL_PRCAN 0x400FEA34 // Controller Area Network
+ // Peripheral Ready
+#define SYSCTL_PRADC 0x400FEA38 // Analog-to-Digital Converter
+ // Peripheral Ready
+#define SYSCTL_PRACMP 0x400FEA3C // Analog Comparator Peripheral
+ // Ready
+#define SYSCTL_PRPWM 0x400FEA40 // Pulse Width Modulator Peripheral
+ // Ready
+#define SYSCTL_PRQEI 0x400FEA44 // Quadrature Encoder Interface
+ // Peripheral Ready
+#define SYSCTL_PREEPROM 0x400FEA58 // EEPROM Peripheral Ready
+#define SYSCTL_PRWTIMER 0x400FEA5C // 32/64-Bit Wide General-Purpose
+ // Timer Peripheral Ready
+#define SYSCTL_PRCCM 0x400FEA74 // CRC and Cryptographic Modules
+ // Peripheral Ready
+#define SYSCTL_PRLCD 0x400FEA90 // LCD Controller Peripheral Ready
+#define SYSCTL_PROWIRE 0x400FEA98 // 1-Wire Peripheral Ready
+#define SYSCTL_PREMAC 0x400FEA9C // Ethernet MAC Peripheral Ready
+#define SYSCTL_UNIQUEID0 0x400FEF20 // Unique ID 0
+#define SYSCTL_UNIQUEID1 0x400FEF24 // Unique ID 1
+#define SYSCTL_UNIQUEID2 0x400FEF28 // Unique ID 2
+#define SYSCTL_UNIQUEID3 0x400FEF2C // Unique ID 3
+#define SYSCTL_CCMCGREQ 0x44030204 // Cryptographic Modules Clock
+ // Gating Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID0_VER_M 0x70000000 // DID0 Version
+#define SYSCTL_DID0_VER_1 0x10000000 // Second version of the DID0
+ // register format.
+#define SYSCTL_DID0_CLASS_M 0x00FF0000 // Device Class
+#define SYSCTL_DID0_CLASS_TM4C123 \
+ 0x00050000 // Tiva TM4C123x and TM4E123x
+ // microcontrollers
+#define SYSCTL_DID0_CLASS_TM4C129 \
+ 0x000A0000 // Tiva(TM) TM4C129-class
+ // microcontrollers
+#define SYSCTL_DID0_MAJ_M 0x0000FF00 // Major Revision
+#define SYSCTL_DID0_MAJ_REVA 0x00000000 // Revision A (initial device)
+#define SYSCTL_DID0_MAJ_REVB 0x00000100 // Revision B (first base layer
+ // revision)
+#define SYSCTL_DID0_MAJ_REVC 0x00000200 // Revision C (second base layer
+ // revision)
+#define SYSCTL_DID0_MIN_M 0x000000FF // Minor Revision
+#define SYSCTL_DID0_MIN_0 0x00000000 // Initial device, or a major
+ // revision update
+#define SYSCTL_DID0_MIN_1 0x00000001 // First metal layer change
+#define SYSCTL_DID0_MIN_2 0x00000002 // Second metal layer change
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DID1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DID1_VER_M 0xF0000000 // DID1 Version
+#define SYSCTL_DID1_VER_1 0x10000000 // fury_ib
+#define SYSCTL_DID1_FAM_M 0x0F000000 // Family
+#define SYSCTL_DID1_FAM_TIVA 0x00000000 // Tiva family of microcontollers
+#define SYSCTL_DID1_PRTNO_M 0x00FF0000 // Part Number
+#define SYSCTL_DID1_PRTNO_TM4C1230C3PM \
+ 0x00220000 // TM4C1230C3PM
+#define SYSCTL_DID1_PRTNO_TM4C1230D5PM \
+ 0x00230000 // TM4C1230D5PM
+#define SYSCTL_DID1_PRTNO_TM4C1230E6PM \
+ 0x00200000 // TM4C1230E6PM
+#define SYSCTL_DID1_PRTNO_TM4C1230H6PM \
+ 0x00210000 // TM4C1230H6PM
+#define SYSCTL_DID1_PRTNO_TM4C1231C3PM \
+ 0x00180000 // TM4C1231C3PM
+#define SYSCTL_DID1_PRTNO_TM4C1231D5PM \
+ 0x00190000 // TM4C1231D5PM
+#define SYSCTL_DID1_PRTNO_TM4C1231D5PZ \
+ 0x00360000 // TM4C1231D5PZ
+#define SYSCTL_DID1_PRTNO_TM4C1231E6PM \
+ 0x00100000 // TM4C1231E6PM
+#define SYSCTL_DID1_PRTNO_TM4C1231E6PZ \
+ 0x00300000 // TM4C1231E6PZ
+#define SYSCTL_DID1_PRTNO_TM4C1231H6PGE \
+ 0x00350000 // TM4C1231H6PGE
+#define SYSCTL_DID1_PRTNO_TM4C1231H6PM \
+ 0x00110000 // TM4C1231H6PM
+#define SYSCTL_DID1_PRTNO_TM4C1231H6PZ \
+ 0x00310000 // TM4C1231H6PZ
+#define SYSCTL_DID1_PRTNO_TM4C1232C3PM \
+ 0x00080000 // TM4C1232C3PM
+#define SYSCTL_DID1_PRTNO_TM4C1232D5PM \
+ 0x00090000 // TM4C1232D5PM
+#define SYSCTL_DID1_PRTNO_TM4C1232E6PM \
+ 0x000A0000 // TM4C1232E6PM
+#define SYSCTL_DID1_PRTNO_TM4C1232H6PM \
+ 0x000B0000 // TM4C1232H6PM
+#define SYSCTL_DID1_PRTNO_TM4C1233C3PM \
+ 0x00010000 // TM4C1233C3PM
+#define SYSCTL_DID1_PRTNO_TM4C1233D5PM \
+ 0x00020000 // TM4C1233D5PM
+#define SYSCTL_DID1_PRTNO_TM4C1233D5PZ \
+ 0x00D00000 // TM4C1233D5PZ
+#define SYSCTL_DID1_PRTNO_TM4C1233E6PM \
+ 0x00030000 // TM4C1233E6PM
+#define SYSCTL_DID1_PRTNO_TM4C1233E6PZ \
+ 0x00D10000 // TM4C1233E6PZ
+#define SYSCTL_DID1_PRTNO_TM4C1233H6PGE \
+ 0x00D60000 // TM4C1233H6PGE
+#define SYSCTL_DID1_PRTNO_TM4C1233H6PM \
+ 0x00040000 // TM4C1233H6PM
+#define SYSCTL_DID1_PRTNO_TM4C1233H6PZ \
+ 0x00D20000 // TM4C1233H6PZ
+#define SYSCTL_DID1_PRTNO_TM4C1236D5PM \
+ 0x00520000 // TM4C1236D5PM
+#define SYSCTL_DID1_PRTNO_TM4C1236E6PM \
+ 0x00500000 // TM4C1236E6PM
+#define SYSCTL_DID1_PRTNO_TM4C1236H6PM \
+ 0x00510000 // TM4C1236H6PM
+#define SYSCTL_DID1_PRTNO_TM4C1237D5PM \
+ 0x00480000 // TM4C1237D5PM
+#define SYSCTL_DID1_PRTNO_TM4C1237D5PZ \
+ 0x00660000 // TM4C1237D5PZ
+#define SYSCTL_DID1_PRTNO_TM4C1237E6PM \
+ 0x00400000 // TM4C1237E6PM
+#define SYSCTL_DID1_PRTNO_TM4C1237E6PZ \
+ 0x00600000 // TM4C1237E6PZ
+#define SYSCTL_DID1_PRTNO_TM4C1237H6PGE \
+ 0x00650000 // TM4C1237H6PGE
+#define SYSCTL_DID1_PRTNO_TM4C1237H6PM \
+ 0x00410000 // TM4C1237H6PM
+#define SYSCTL_DID1_PRTNO_TM4C1237H6PZ \
+ 0x00610000 // TM4C1237H6PZ
+#define SYSCTL_DID1_PRTNO_TM4C123AE6PM \
+ 0x00800000 // TM4C123AE6PM
+#define SYSCTL_DID1_PRTNO_TM4C123AH6PM \
+ 0x00830000 // TM4C123AH6PM
+#define SYSCTL_DID1_PRTNO_TM4C123BE6PM \
+ 0x00700000 // TM4C123BE6PM
+#define SYSCTL_DID1_PRTNO_TM4C123BE6PZ \
+ 0x00C30000 // TM4C123BE6PZ
+#define SYSCTL_DID1_PRTNO_TM4C123BH6PGE \
+ 0x00C60000 // TM4C123BH6PGE
+#define SYSCTL_DID1_PRTNO_TM4C123BH6PM \
+ 0x00730000 // TM4C123BH6PM
+#define SYSCTL_DID1_PRTNO_TM4C123BH6PZ \
+ 0x00C40000 // TM4C123BH6PZ
+#define SYSCTL_DID1_PRTNO_TM4C123BH6ZRB \
+ 0x00E90000 // TM4C123BH6ZRB
+#define SYSCTL_DID1_PRTNO_TM4C123FE6PM \
+ 0x00B00000 // TM4C123FE6PM
+#define SYSCTL_DID1_PRTNO_TM4C123FH6PM \
+ 0x00B10000 // TM4C123FH6PM
+#define SYSCTL_DID1_PRTNO_TM4C123GE6PM \
+ 0x00A00000 // TM4C123GE6PM
+#define SYSCTL_DID1_PRTNO_TM4C123GE6PZ \
+ 0x00C00000 // TM4C123GE6PZ
+#define SYSCTL_DID1_PRTNO_TM4C123GH6PGE \
+ 0x00C50000 // TM4C123GH6PGE
+#define SYSCTL_DID1_PRTNO_TM4C123GH6PM \
+ 0x00A10000 // TM4C123GH6PM
+#define SYSCTL_DID1_PRTNO_TM4C123GH6PZ \
+ 0x00C10000 // TM4C123GH6PZ
+#define SYSCTL_DID1_PRTNO_TM4C123GH6ZRB \
+ 0x00E30000 // TM4C123GH6ZRB
+#define SYSCTL_DID1_PRTNO_TM4C1290NCPDT \
+ 0x00190000 // TM4C1290NCPDT
+#define SYSCTL_DID1_PRTNO_TM4C1290NCZAD \
+ 0x001B0000 // TM4C1290NCZAD
+#define SYSCTL_DID1_PRTNO_TM4C1292NCPDT \
+ 0x001C0000 // TM4C1292NCPDT
+#define SYSCTL_DID1_PRTNO_TM4C1292NCZAD \
+ 0x001E0000 // TM4C1292NCZAD
+#define SYSCTL_DID1_PRTNO_TM4C1294KCPDT \
+ 0x00340000 // TM4C1294KCPDT
+#define SYSCTL_DID1_PRTNO_TM4C1294NCPDT \
+ 0x001F0000 // TM4C1294NCPDT
+#define SYSCTL_DID1_PRTNO_TM4C1294NCZAD \
+ 0x00210000 // TM4C1294NCZAD
+#define SYSCTL_DID1_PRTNO_TM4C1297NCZAD \
+ 0x00220000 // TM4C1297NCZAD
+#define SYSCTL_DID1_PRTNO_TM4C1299KCZAD \
+ 0x00360000 // TM4C1299KCZAD
+#define SYSCTL_DID1_PRTNO_TM4C1299NCZAD \
+ 0x00230000 // TM4C1299NCZAD
+#define SYSCTL_DID1_PRTNO_TM4C129CNCPDT \
+ 0x00240000 // TM4C129CNCPDT
+#define SYSCTL_DID1_PRTNO_TM4C129CNCZAD \
+ 0x00260000 // TM4C129CNCZAD
+#define SYSCTL_DID1_PRTNO_TM4C129DNCPDT \
+ 0x00270000 // TM4C129DNCPDT
+#define SYSCTL_DID1_PRTNO_TM4C129DNCZAD \
+ 0x00290000 // TM4C129DNCZAD
+#define SYSCTL_DID1_PRTNO_TM4C129EKCPDT \
+ 0x00350000 // TM4C129EKCPDT
+#define SYSCTL_DID1_PRTNO_TM4C129ENCPDT \
+ 0x002D0000 // TM4C129ENCPDT
+#define SYSCTL_DID1_PRTNO_TM4C129ENCZAD \
+ 0x002F0000 // TM4C129ENCZAD
+#define SYSCTL_DID1_PRTNO_TM4C129LNCZAD \
+ 0x00300000 // TM4C129LNCZAD
+#define SYSCTL_DID1_PRTNO_TM4C129XKCZAD \
+ 0x00370000 // TM4C129XKCZAD
+#define SYSCTL_DID1_PRTNO_TM4C129XNCZAD \
+ 0x00320000 // TM4C129XNCZAD
+#define SYSCTL_DID1_PINCNT_M 0x0000E000 // Package Pin Count
+#define SYSCTL_DID1_PINCNT_100 0x00004000 // 100-pin LQFP package
+#define SYSCTL_DID1_PINCNT_64 0x00006000 // 64-pin LQFP package
+#define SYSCTL_DID1_PINCNT_144 0x00008000 // 144-pin LQFP package
+#define SYSCTL_DID1_PINCNT_157 0x0000A000 // 157-pin BGA package
+#define SYSCTL_DID1_PINCNT_128 0x0000C000 // 128-pin TQFP package
+#define SYSCTL_DID1_TEMP_M 0x000000E0 // Temperature Range
+#define SYSCTL_DID1_TEMP_C 0x00000000 // Commercial temperature range
+#define SYSCTL_DID1_TEMP_I 0x00000020 // Industrial temperature range
+#define SYSCTL_DID1_TEMP_E 0x00000040 // Extended temperature range
+#define SYSCTL_DID1_TEMP_IE 0x00000060 // Available in both industrial
+ // temperature range (-40C to 85C)
+ // and extended temperature range
+ // (-40C to 105C) devices. See
+#define SYSCTL_DID1_PKG_M 0x00000018 // Package Type
+#define SYSCTL_DID1_PKG_QFP 0x00000008 // QFP package
+#define SYSCTL_DID1_PKG_BGA 0x00000010 // BGA package
+#define SYSCTL_DID1_ROHS 0x00000004 // RoHS-Compliance
+#define SYSCTL_DID1_QUAL_M 0x00000003 // Qualification Status
+#define SYSCTL_DID1_QUAL_ES 0x00000000 // Engineering Sample (unqualified)
+#define SYSCTL_DID1_QUAL_PP 0x00000001 // Pilot Production (unqualified)
+#define SYSCTL_DID1_QUAL_FQ 0x00000002 // Fully Qualified
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC0_SRAMSZ_M 0xFFFF0000 // SRAM Size
+#define SYSCTL_DC0_SRAMSZ_2KB 0x00070000 // 2 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_4KB 0x000F0000 // 4 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_6KB 0x00170000 // 6 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_8KB 0x001F0000 // 8 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_12KB 0x002F0000 // 12 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_16KB 0x003F0000 // 16 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_20KB 0x004F0000 // 20 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_24KB 0x005F0000 // 24 KB of SRAM
+#define SYSCTL_DC0_SRAMSZ_32KB 0x007F0000 // 32 KB of SRAM
+#define SYSCTL_DC0_FLASHSZ_M 0x0000FFFF // Flash Size
+#define SYSCTL_DC0_FLASHSZ_8KB 0x00000003 // 8 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_16KB 0x00000007 // 16 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_32KB 0x0000000F // 32 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_64KB 0x0000001F // 64 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_96KB 0x0000002F // 96 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_128K 0x0000003F // 128 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_192K 0x0000005F // 192 KB of Flash
+#define SYSCTL_DC0_FLASHSZ_256K 0x0000007F // 256 KB of Flash
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC1_WDT1 0x10000000 // Watchdog Timer1 Present
+#define SYSCTL_DC1_CAN1 0x02000000 // CAN Module 1 Present
+#define SYSCTL_DC1_CAN0 0x01000000 // CAN Module 0 Present
+#define SYSCTL_DC1_PWM1 0x00200000 // PWM Module 1 Present
+#define SYSCTL_DC1_PWM0 0x00100000 // PWM Module 0 Present
+#define SYSCTL_DC1_ADC1 0x00020000 // ADC Module 1 Present
+#define SYSCTL_DC1_ADC0 0x00010000 // ADC Module 0 Present
+#define SYSCTL_DC1_MINSYSDIV_M 0x0000F000 // System Clock Divider
+#define SYSCTL_DC1_MINSYSDIV_80 0x00002000 // Specifies an 80-MHz CPU clock
+ // with a PLL divider of 2.5
+#define SYSCTL_DC1_MINSYSDIV_50 0x00003000 // Specifies a 50-MHz CPU clock
+ // with a PLL divider of 4
+#define SYSCTL_DC1_MINSYSDIV_40 0x00004000 // Specifies a 40-MHz CPU clock
+ // with a PLL divider of 5
+#define SYSCTL_DC1_MINSYSDIV_25 0x00007000 // Specifies a 25-MHz clock with a
+ // PLL divider of 8
+#define SYSCTL_DC1_MINSYSDIV_20 0x00009000 // Specifies a 20-MHz clock with a
+ // PLL divider of 10
+#define SYSCTL_DC1_ADC1SPD_M 0x00000C00 // Max ADC1 Speed
+#define SYSCTL_DC1_ADC1SPD_125K 0x00000000 // 125K samples/second
+#define SYSCTL_DC1_ADC1SPD_250K 0x00000400 // 250K samples/second
+#define SYSCTL_DC1_ADC1SPD_500K 0x00000800 // 500K samples/second
+#define SYSCTL_DC1_ADC1SPD_1M 0x00000C00 // 1M samples/second
+#define SYSCTL_DC1_ADC0SPD_M 0x00000300 // Max ADC0 Speed
+#define SYSCTL_DC1_ADC0SPD_125K 0x00000000 // 125K samples/second
+#define SYSCTL_DC1_ADC0SPD_250K 0x00000100 // 250K samples/second
+#define SYSCTL_DC1_ADC0SPD_500K 0x00000200 // 500K samples/second
+#define SYSCTL_DC1_ADC0SPD_1M 0x00000300 // 1M samples/second
+#define SYSCTL_DC1_MPU 0x00000080 // MPU Present
+#define SYSCTL_DC1_HIB 0x00000040 // Hibernation Module Present
+#define SYSCTL_DC1_TEMP 0x00000020 // Temp Sensor Present
+#define SYSCTL_DC1_PLL 0x00000010 // PLL Present
+#define SYSCTL_DC1_WDT0 0x00000008 // Watchdog Timer 0 Present
+#define SYSCTL_DC1_SWO 0x00000004 // SWO Trace Port Present
+#define SYSCTL_DC1_SWD 0x00000002 // SWD Present
+#define SYSCTL_DC1_JTAG 0x00000001 // JTAG Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC2_EPI0 0x40000000 // EPI Module 0 Present
+#define SYSCTL_DC2_I2S0 0x10000000 // I2S Module 0 Present
+#define SYSCTL_DC2_COMP2 0x04000000 // Analog Comparator 2 Present
+#define SYSCTL_DC2_COMP1 0x02000000 // Analog Comparator 1 Present
+#define SYSCTL_DC2_COMP0 0x01000000 // Analog Comparator 0 Present
+#define SYSCTL_DC2_TIMER3 0x00080000 // Timer Module 3 Present
+#define SYSCTL_DC2_TIMER2 0x00040000 // Timer Module 2 Present
+#define SYSCTL_DC2_TIMER1 0x00020000 // Timer Module 1 Present
+#define SYSCTL_DC2_TIMER0 0x00010000 // Timer Module 0 Present
+#define SYSCTL_DC2_I2C1HS 0x00008000 // I2C Module 1 Speed
+#define SYSCTL_DC2_I2C1 0x00004000 // I2C Module 1 Present
+#define SYSCTL_DC2_I2C0HS 0x00002000 // I2C Module 0 Speed
+#define SYSCTL_DC2_I2C0 0x00001000 // I2C Module 0 Present
+#define SYSCTL_DC2_QEI1 0x00000200 // QEI Module 1 Present
+#define SYSCTL_DC2_QEI0 0x00000100 // QEI Module 0 Present
+#define SYSCTL_DC2_SSI1 0x00000020 // SSI Module 1 Present
+#define SYSCTL_DC2_SSI0 0x00000010 // SSI Module 0 Present
+#define SYSCTL_DC2_UART2 0x00000004 // UART Module 2 Present
+#define SYSCTL_DC2_UART1 0x00000002 // UART Module 1 Present
+#define SYSCTL_DC2_UART0 0x00000001 // UART Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC3 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC3_32KHZ 0x80000000 // 32KHz Input Clock Available
+#define SYSCTL_DC3_CCP5 0x20000000 // T2CCP1 Pin Present
+#define SYSCTL_DC3_CCP4 0x10000000 // T2CCP0 Pin Present
+#define SYSCTL_DC3_CCP3 0x08000000 // T1CCP1 Pin Present
+#define SYSCTL_DC3_CCP2 0x04000000 // T1CCP0 Pin Present
+#define SYSCTL_DC3_CCP1 0x02000000 // T0CCP1 Pin Present
+#define SYSCTL_DC3_CCP0 0x01000000 // T0CCP0 Pin Present
+#define SYSCTL_DC3_ADC0AIN7 0x00800000 // ADC Module 0 AIN7 Pin Present
+#define SYSCTL_DC3_ADC0AIN6 0x00400000 // ADC Module 0 AIN6 Pin Present
+#define SYSCTL_DC3_ADC0AIN5 0x00200000 // ADC Module 0 AIN5 Pin Present
+#define SYSCTL_DC3_ADC0AIN4 0x00100000 // ADC Module 0 AIN4 Pin Present
+#define SYSCTL_DC3_ADC0AIN3 0x00080000 // ADC Module 0 AIN3 Pin Present
+#define SYSCTL_DC3_ADC0AIN2 0x00040000 // ADC Module 0 AIN2 Pin Present
+#define SYSCTL_DC3_ADC0AIN1 0x00020000 // ADC Module 0 AIN1 Pin Present
+#define SYSCTL_DC3_ADC0AIN0 0x00010000 // ADC Module 0 AIN0 Pin Present
+#define SYSCTL_DC3_PWMFAULT 0x00008000 // PWM Fault Pin Present
+#define SYSCTL_DC3_C2O 0x00004000 // C2o Pin Present
+#define SYSCTL_DC3_C2PLUS 0x00002000 // C2+ Pin Present
+#define SYSCTL_DC3_C2MINUS 0x00001000 // C2- Pin Present
+#define SYSCTL_DC3_C1O 0x00000800 // C1o Pin Present
+#define SYSCTL_DC3_C1PLUS 0x00000400 // C1+ Pin Present
+#define SYSCTL_DC3_C1MINUS 0x00000200 // C1- Pin Present
+#define SYSCTL_DC3_C0O 0x00000100 // C0o Pin Present
+#define SYSCTL_DC3_C0PLUS 0x00000080 // C0+ Pin Present
+#define SYSCTL_DC3_C0MINUS 0x00000040 // C0- Pin Present
+#define SYSCTL_DC3_PWM5 0x00000020 // PWM5 Pin Present
+#define SYSCTL_DC3_PWM4 0x00000010 // PWM4 Pin Present
+#define SYSCTL_DC3_PWM3 0x00000008 // PWM3 Pin Present
+#define SYSCTL_DC3_PWM2 0x00000004 // PWM2 Pin Present
+#define SYSCTL_DC3_PWM1 0x00000002 // PWM1 Pin Present
+#define SYSCTL_DC3_PWM0 0x00000001 // PWM0 Pin Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC4 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC4_EPHY0 0x40000000 // Ethernet PHY Layer 0 Present
+#define SYSCTL_DC4_EMAC0 0x10000000 // Ethernet MAC Layer 0 Present
+#define SYSCTL_DC4_E1588 0x01000000 // 1588 Capable
+#define SYSCTL_DC4_PICAL 0x00040000 // PIOSC Calibrate
+#define SYSCTL_DC4_CCP7 0x00008000 // T3CCP1 Pin Present
+#define SYSCTL_DC4_CCP6 0x00004000 // T3CCP0 Pin Present
+#define SYSCTL_DC4_UDMA 0x00002000 // Micro-DMA Module Present
+#define SYSCTL_DC4_ROM 0x00001000 // Internal Code ROM Present
+#define SYSCTL_DC4_GPIOJ 0x00000100 // GPIO Port J Present
+#define SYSCTL_DC4_GPIOH 0x00000080 // GPIO Port H Present
+#define SYSCTL_DC4_GPIOG 0x00000040 // GPIO Port G Present
+#define SYSCTL_DC4_GPIOF 0x00000020 // GPIO Port F Present
+#define SYSCTL_DC4_GPIOE 0x00000010 // GPIO Port E Present
+#define SYSCTL_DC4_GPIOD 0x00000008 // GPIO Port D Present
+#define SYSCTL_DC4_GPIOC 0x00000004 // GPIO Port C Present
+#define SYSCTL_DC4_GPIOB 0x00000002 // GPIO Port B Present
+#define SYSCTL_DC4_GPIOA 0x00000001 // GPIO Port A Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC5 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC5_PWMFAULT3 0x08000000 // PWM Fault 3 Pin Present
+#define SYSCTL_DC5_PWMFAULT2 0x04000000 // PWM Fault 2 Pin Present
+#define SYSCTL_DC5_PWMFAULT1 0x02000000 // PWM Fault 1 Pin Present
+#define SYSCTL_DC5_PWMFAULT0 0x01000000 // PWM Fault 0 Pin Present
+#define SYSCTL_DC5_PWMEFLT 0x00200000 // PWM Extended Fault Active
+#define SYSCTL_DC5_PWMESYNC 0x00100000 // PWM Extended SYNC Active
+#define SYSCTL_DC5_PWM7 0x00000080 // PWM7 Pin Present
+#define SYSCTL_DC5_PWM6 0x00000040 // PWM6 Pin Present
+#define SYSCTL_DC5_PWM5 0x00000020 // PWM5 Pin Present
+#define SYSCTL_DC5_PWM4 0x00000010 // PWM4 Pin Present
+#define SYSCTL_DC5_PWM3 0x00000008 // PWM3 Pin Present
+#define SYSCTL_DC5_PWM2 0x00000004 // PWM2 Pin Present
+#define SYSCTL_DC5_PWM1 0x00000002 // PWM1 Pin Present
+#define SYSCTL_DC5_PWM0 0x00000001 // PWM0 Pin Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC6 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC6_USB0PHY 0x00000010 // USB Module 0 PHY Present
+#define SYSCTL_DC6_USB0_M 0x00000003 // USB Module 0 Present
+#define SYSCTL_DC6_USB0_DEV 0x00000001 // USB0 is Device Only
+#define SYSCTL_DC6_USB0_HOSTDEV 0x00000002 // USB is Device or Host
+#define SYSCTL_DC6_USB0_OTG 0x00000003 // USB0 is OTG
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC7 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC7_DMACH30 0x40000000 // DMA Channel 30
+#define SYSCTL_DC7_DMACH29 0x20000000 // DMA Channel 29
+#define SYSCTL_DC7_DMACH28 0x10000000 // DMA Channel 28
+#define SYSCTL_DC7_DMACH27 0x08000000 // DMA Channel 27
+#define SYSCTL_DC7_DMACH26 0x04000000 // DMA Channel 26
+#define SYSCTL_DC7_DMACH25 0x02000000 // DMA Channel 25
+#define SYSCTL_DC7_DMACH24 0x01000000 // DMA Channel 24
+#define SYSCTL_DC7_DMACH23 0x00800000 // DMA Channel 23
+#define SYSCTL_DC7_DMACH22 0x00400000 // DMA Channel 22
+#define SYSCTL_DC7_DMACH21 0x00200000 // DMA Channel 21
+#define SYSCTL_DC7_DMACH20 0x00100000 // DMA Channel 20
+#define SYSCTL_DC7_DMACH19 0x00080000 // DMA Channel 19
+#define SYSCTL_DC7_DMACH18 0x00040000 // DMA Channel 18
+#define SYSCTL_DC7_DMACH17 0x00020000 // DMA Channel 17
+#define SYSCTL_DC7_DMACH16 0x00010000 // DMA Channel 16
+#define SYSCTL_DC7_DMACH15 0x00008000 // DMA Channel 15
+#define SYSCTL_DC7_DMACH14 0x00004000 // DMA Channel 14
+#define SYSCTL_DC7_DMACH13 0x00002000 // DMA Channel 13
+#define SYSCTL_DC7_DMACH12 0x00001000 // DMA Channel 12
+#define SYSCTL_DC7_DMACH11 0x00000800 // DMA Channel 11
+#define SYSCTL_DC7_DMACH10 0x00000400 // DMA Channel 10
+#define SYSCTL_DC7_DMACH9 0x00000200 // DMA Channel 9
+#define SYSCTL_DC7_DMACH8 0x00000100 // DMA Channel 8
+#define SYSCTL_DC7_DMACH7 0x00000080 // DMA Channel 7
+#define SYSCTL_DC7_DMACH6 0x00000040 // DMA Channel 6
+#define SYSCTL_DC7_DMACH5 0x00000020 // DMA Channel 5
+#define SYSCTL_DC7_DMACH4 0x00000010 // DMA Channel 4
+#define SYSCTL_DC7_DMACH3 0x00000008 // DMA Channel 3
+#define SYSCTL_DC7_DMACH2 0x00000004 // DMA Channel 2
+#define SYSCTL_DC7_DMACH1 0x00000002 // DMA Channel 1
+#define SYSCTL_DC7_DMACH0 0x00000001 // DMA Channel 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC8 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC8_ADC1AIN15 0x80000000 // ADC Module 1 AIN15 Pin Present
+#define SYSCTL_DC8_ADC1AIN14 0x40000000 // ADC Module 1 AIN14 Pin Present
+#define SYSCTL_DC8_ADC1AIN13 0x20000000 // ADC Module 1 AIN13 Pin Present
+#define SYSCTL_DC8_ADC1AIN12 0x10000000 // ADC Module 1 AIN12 Pin Present
+#define SYSCTL_DC8_ADC1AIN11 0x08000000 // ADC Module 1 AIN11 Pin Present
+#define SYSCTL_DC8_ADC1AIN10 0x04000000 // ADC Module 1 AIN10 Pin Present
+#define SYSCTL_DC8_ADC1AIN9 0x02000000 // ADC Module 1 AIN9 Pin Present
+#define SYSCTL_DC8_ADC1AIN8 0x01000000 // ADC Module 1 AIN8 Pin Present
+#define SYSCTL_DC8_ADC1AIN7 0x00800000 // ADC Module 1 AIN7 Pin Present
+#define SYSCTL_DC8_ADC1AIN6 0x00400000 // ADC Module 1 AIN6 Pin Present
+#define SYSCTL_DC8_ADC1AIN5 0x00200000 // ADC Module 1 AIN5 Pin Present
+#define SYSCTL_DC8_ADC1AIN4 0x00100000 // ADC Module 1 AIN4 Pin Present
+#define SYSCTL_DC8_ADC1AIN3 0x00080000 // ADC Module 1 AIN3 Pin Present
+#define SYSCTL_DC8_ADC1AIN2 0x00040000 // ADC Module 1 AIN2 Pin Present
+#define SYSCTL_DC8_ADC1AIN1 0x00020000 // ADC Module 1 AIN1 Pin Present
+#define SYSCTL_DC8_ADC1AIN0 0x00010000 // ADC Module 1 AIN0 Pin Present
+#define SYSCTL_DC8_ADC0AIN15 0x00008000 // ADC Module 0 AIN15 Pin Present
+#define SYSCTL_DC8_ADC0AIN14 0x00004000 // ADC Module 0 AIN14 Pin Present
+#define SYSCTL_DC8_ADC0AIN13 0x00002000 // ADC Module 0 AIN13 Pin Present
+#define SYSCTL_DC8_ADC0AIN12 0x00001000 // ADC Module 0 AIN12 Pin Present
+#define SYSCTL_DC8_ADC0AIN11 0x00000800 // ADC Module 0 AIN11 Pin Present
+#define SYSCTL_DC8_ADC0AIN10 0x00000400 // ADC Module 0 AIN10 Pin Present
+#define SYSCTL_DC8_ADC0AIN9 0x00000200 // ADC Module 0 AIN9 Pin Present
+#define SYSCTL_DC8_ADC0AIN8 0x00000100 // ADC Module 0 AIN8 Pin Present
+#define SYSCTL_DC8_ADC0AIN7 0x00000080 // ADC Module 0 AIN7 Pin Present
+#define SYSCTL_DC8_ADC0AIN6 0x00000040 // ADC Module 0 AIN6 Pin Present
+#define SYSCTL_DC8_ADC0AIN5 0x00000020 // ADC Module 0 AIN5 Pin Present
+#define SYSCTL_DC8_ADC0AIN4 0x00000010 // ADC Module 0 AIN4 Pin Present
+#define SYSCTL_DC8_ADC0AIN3 0x00000008 // ADC Module 0 AIN3 Pin Present
+#define SYSCTL_DC8_ADC0AIN2 0x00000004 // ADC Module 0 AIN2 Pin Present
+#define SYSCTL_DC8_ADC0AIN1 0x00000002 // ADC Module 0 AIN1 Pin Present
+#define SYSCTL_DC8_ADC0AIN0 0x00000001 // ADC Module 0 AIN0 Pin Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PBORCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_PBORCTL_BOR0 0x00000004 // VDD under BOR0 Event Action
+#define SYSCTL_PBORCTL_BOR1 0x00000002 // VDD under BOR1 Event Action
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PTBOCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_PTBOCTL_VDDA_UBOR_M \
+ 0x00000300 // VDDA under BOR Event Action
+#define SYSCTL_PTBOCTL_VDDA_UBOR_NONE \
+ 0x00000000 // No Action
+#define SYSCTL_PTBOCTL_VDDA_UBOR_SYSINT \
+ 0x00000100 // System control interrupt
+#define SYSCTL_PTBOCTL_VDDA_UBOR_NMI \
+ 0x00000200 // NMI
+#define SYSCTL_PTBOCTL_VDDA_UBOR_RST \
+ 0x00000300 // Reset
+#define SYSCTL_PTBOCTL_VDD_UBOR_M \
+ 0x00000003 // VDD (VDDS) under BOR Event
+ // Action
+#define SYSCTL_PTBOCTL_VDD_UBOR_NONE \
+ 0x00000000 // No Action
+#define SYSCTL_PTBOCTL_VDD_UBOR_SYSINT \
+ 0x00000001 // System control interrupt
+#define SYSCTL_PTBOCTL_VDD_UBOR_NMI \
+ 0x00000002 // NMI
+#define SYSCTL_PTBOCTL_VDD_UBOR_RST \
+ 0x00000003 // Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR0_WDT1 0x10000000 // WDT1 Reset Control
+#define SYSCTL_SRCR0_CAN1 0x02000000 // CAN1 Reset Control
+#define SYSCTL_SRCR0_CAN0 0x01000000 // CAN0 Reset Control
+#define SYSCTL_SRCR0_PWM0 0x00100000 // PWM Reset Control
+#define SYSCTL_SRCR0_ADC1 0x00020000 // ADC1 Reset Control
+#define SYSCTL_SRCR0_ADC0 0x00010000 // ADC0 Reset Control
+#define SYSCTL_SRCR0_HIB 0x00000040 // HIB Reset Control
+#define SYSCTL_SRCR0_WDT0 0x00000008 // WDT0 Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR1_COMP2 0x04000000 // Analog Comp 2 Reset Control
+#define SYSCTL_SRCR1_COMP1 0x02000000 // Analog Comp 1 Reset Control
+#define SYSCTL_SRCR1_COMP0 0x01000000 // Analog Comp 0 Reset Control
+#define SYSCTL_SRCR1_TIMER3 0x00080000 // Timer 3 Reset Control
+#define SYSCTL_SRCR1_TIMER2 0x00040000 // Timer 2 Reset Control
+#define SYSCTL_SRCR1_TIMER1 0x00020000 // Timer 1 Reset Control
+#define SYSCTL_SRCR1_TIMER0 0x00010000 // Timer 0 Reset Control
+#define SYSCTL_SRCR1_I2C1 0x00004000 // I2C1 Reset Control
+#define SYSCTL_SRCR1_I2C0 0x00001000 // I2C0 Reset Control
+#define SYSCTL_SRCR1_QEI1 0x00000200 // QEI1 Reset Control
+#define SYSCTL_SRCR1_QEI0 0x00000100 // QEI0 Reset Control
+#define SYSCTL_SRCR1_SSI1 0x00000020 // SSI1 Reset Control
+#define SYSCTL_SRCR1_SSI0 0x00000010 // SSI0 Reset Control
+#define SYSCTL_SRCR1_UART2 0x00000004 // UART2 Reset Control
+#define SYSCTL_SRCR1_UART1 0x00000002 // UART1 Reset Control
+#define SYSCTL_SRCR1_UART0 0x00000001 // UART0 Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCR2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCR2_USB0 0x00010000 // USB0 Reset Control
+#define SYSCTL_SRCR2_UDMA 0x00002000 // Micro-DMA Reset Control
+#define SYSCTL_SRCR2_GPIOJ 0x00000100 // Port J Reset Control
+#define SYSCTL_SRCR2_GPIOH 0x00000080 // Port H Reset Control
+#define SYSCTL_SRCR2_GPIOG 0x00000040 // Port G Reset Control
+#define SYSCTL_SRCR2_GPIOF 0x00000020 // Port F Reset Control
+#define SYSCTL_SRCR2_GPIOE 0x00000010 // Port E Reset Control
+#define SYSCTL_SRCR2_GPIOD 0x00000008 // Port D Reset Control
+#define SYSCTL_SRCR2_GPIOC 0x00000004 // Port C Reset Control
+#define SYSCTL_SRCR2_GPIOB 0x00000002 // Port B Reset Control
+#define SYSCTL_SRCR2_GPIOA 0x00000001 // Port A Reset Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RIS register.
+//
+//*****************************************************************************
+#define SYSCTL_RIS_BOR0RIS 0x00000800 // VDD under BOR0 Raw Interrupt
+ // Status
+#define SYSCTL_RIS_VDDARIS 0x00000400 // VDDA Power OK Event Raw
+ // Interrupt Status
+#define SYSCTL_RIS_MOSCPUPRIS 0x00000100 // MOSC Power Up Raw Interrupt
+ // Status
+#define SYSCTL_RIS_USBPLLLRIS 0x00000080 // USB PLL Lock Raw Interrupt
+ // Status
+#define SYSCTL_RIS_PLLLRIS 0x00000040 // PLL Lock Raw Interrupt Status
+#define SYSCTL_RIS_MOFRIS 0x00000008 // Main Oscillator Failure Raw
+ // Interrupt Status
+#define SYSCTL_RIS_BOR1RIS 0x00000002 // VDD under BOR1 Raw Interrupt
+ // Status
+#define SYSCTL_RIS_BORRIS 0x00000002 // Brown-Out Reset Raw Interrupt
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_IMC register.
+//
+//*****************************************************************************
+#define SYSCTL_IMC_BOR0IM 0x00000800 // VDD under BOR0 Interrupt Mask
+#define SYSCTL_IMC_VDDAIM 0x00000400 // VDDA Power OK Interrupt Mask
+#define SYSCTL_IMC_MOSCPUPIM 0x00000100 // MOSC Power Up Interrupt Mask
+#define SYSCTL_IMC_USBPLLLIM 0x00000080 // USB PLL Lock Interrupt Mask
+#define SYSCTL_IMC_PLLLIM 0x00000040 // PLL Lock Interrupt Mask
+#define SYSCTL_IMC_MOFIM 0x00000008 // Main Oscillator Failure
+ // Interrupt Mask
+#define SYSCTL_IMC_BORIM 0x00000002 // Brown-Out Reset Interrupt Mask
+#define SYSCTL_IMC_BOR1IM 0x00000002 // VDD under BOR1 Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MISC register.
+//
+//*****************************************************************************
+#define SYSCTL_MISC_BOR0MIS 0x00000800 // VDD under BOR0 Masked Interrupt
+ // Status
+#define SYSCTL_MISC_VDDAMIS 0x00000400 // VDDA Power OK Masked Interrupt
+ // Status
+#define SYSCTL_MISC_MOSCPUPMIS 0x00000100 // MOSC Power Up Masked Interrupt
+ // Status
+#define SYSCTL_MISC_USBPLLLMIS 0x00000080 // USB PLL Lock Masked Interrupt
+ // Status
+#define SYSCTL_MISC_PLLLMIS 0x00000040 // PLL Lock Masked Interrupt Status
+#define SYSCTL_MISC_MOFMIS 0x00000008 // Main Oscillator Failure Masked
+ // Interrupt Status
+#define SYSCTL_MISC_BORMIS 0x00000002 // BOR Masked Interrupt Status
+#define SYSCTL_MISC_BOR1MIS 0x00000002 // VDD under BOR1 Masked Interrupt
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RESC register.
+//
+//*****************************************************************************
+#define SYSCTL_RESC_MOSCFAIL 0x00010000 // MOSC Failure Reset
+#define SYSCTL_RESC_HSSR 0x00001000 // HSSR Reset
+#define SYSCTL_RESC_WDT1 0x00000020 // Watchdog Timer 1 Reset
+#define SYSCTL_RESC_SW 0x00000010 // Software Reset
+#define SYSCTL_RESC_WDT0 0x00000008 // Watchdog Timer 0 Reset
+#define SYSCTL_RESC_BOR 0x00000004 // Brown-Out Reset
+#define SYSCTL_RESC_POR 0x00000002 // Power-On Reset
+#define SYSCTL_RESC_EXT 0x00000001 // External Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PWRTC register.
+//
+//*****************************************************************************
+#define SYSCTL_PWRTC_VDDA_UBOR 0x00000010 // VDDA Under BOR Status
+#define SYSCTL_PWRTC_VDD_UBOR 0x00000001 // VDD Under BOR Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCC register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC_ACG 0x08000000 // Auto Clock Gating
+#define SYSCTL_RCC_SYSDIV_M 0x07800000 // System Clock Divisor
+#define SYSCTL_RCC_USESYSDIV 0x00400000 // Enable System Clock Divider
+#define SYSCTL_RCC_USEPWMDIV 0x00100000 // Enable PWM Clock Divisor
+#define SYSCTL_RCC_PWMDIV_M 0x000E0000 // PWM Unit Clock Divisor
+#define SYSCTL_RCC_PWMDIV_2 0x00000000 // PWM clock /2
+#define SYSCTL_RCC_PWMDIV_4 0x00020000 // PWM clock /4
+#define SYSCTL_RCC_PWMDIV_8 0x00040000 // PWM clock /8
+#define SYSCTL_RCC_PWMDIV_16 0x00060000 // PWM clock /16
+#define SYSCTL_RCC_PWMDIV_32 0x00080000 // PWM clock /32
+#define SYSCTL_RCC_PWMDIV_64 0x000A0000 // PWM clock /64
+#define SYSCTL_RCC_PWRDN 0x00002000 // PLL Power Down
+#define SYSCTL_RCC_BYPASS 0x00000800 // PLL Bypass
+#define SYSCTL_RCC_XTAL_M 0x000007C0 // Crystal Value
+#define SYSCTL_RCC_XTAL_4MHZ 0x00000180 // 4 MHz
+#define SYSCTL_RCC_XTAL_4_09MHZ 0x000001C0 // 4.096 MHz
+#define SYSCTL_RCC_XTAL_4_91MHZ 0x00000200 // 4.9152 MHz
+#define SYSCTL_RCC_XTAL_5MHZ 0x00000240 // 5 MHz
+#define SYSCTL_RCC_XTAL_5_12MHZ 0x00000280 // 5.12 MHz
+#define SYSCTL_RCC_XTAL_6MHZ 0x000002C0 // 6 MHz
+#define SYSCTL_RCC_XTAL_6_14MHZ 0x00000300 // 6.144 MHz
+#define SYSCTL_RCC_XTAL_7_37MHZ 0x00000340 // 7.3728 MHz
+#define SYSCTL_RCC_XTAL_8MHZ 0x00000380 // 8 MHz
+#define SYSCTL_RCC_XTAL_8_19MHZ 0x000003C0 // 8.192 MHz
+#define SYSCTL_RCC_XTAL_10MHZ 0x00000400 // 10 MHz
+#define SYSCTL_RCC_XTAL_12MHZ 0x00000440 // 12 MHz
+#define SYSCTL_RCC_XTAL_12_2MHZ 0x00000480 // 12.288 MHz
+#define SYSCTL_RCC_XTAL_13_5MHZ 0x000004C0 // 13.56 MHz
+#define SYSCTL_RCC_XTAL_14_3MHZ 0x00000500 // 14.31818 MHz
+#define SYSCTL_RCC_XTAL_16MHZ 0x00000540 // 16 MHz
+#define SYSCTL_RCC_XTAL_16_3MHZ 0x00000580 // 16.384 MHz
+#define SYSCTL_RCC_XTAL_18MHZ 0x000005C0 // 18.0 MHz (USB)
+#define SYSCTL_RCC_XTAL_20MHZ 0x00000600 // 20.0 MHz (USB)
+#define SYSCTL_RCC_XTAL_24MHZ 0x00000640 // 24.0 MHz (USB)
+#define SYSCTL_RCC_XTAL_25MHZ 0x00000680 // 25.0 MHz (USB)
+#define SYSCTL_RCC_OSCSRC_M 0x00000030 // Oscillator Source
+#define SYSCTL_RCC_OSCSRC_MAIN 0x00000000 // MOSC
+#define SYSCTL_RCC_OSCSRC_INT 0x00000010 // IOSC
+#define SYSCTL_RCC_OSCSRC_INT4 0x00000020 // IOSC/4
+#define SYSCTL_RCC_OSCSRC_30 0x00000030 // LFIOSC
+#define SYSCTL_RCC_MOSCDIS 0x00000001 // Main Oscillator Disable
+#define SYSCTL_RCC_SYSDIV_S 23
+#define SYSCTL_RCC_XTAL_S 6 // Shift to the XTAL field
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_NMIC register.
+//
+//*****************************************************************************
+#define SYSCTL_NMIC_MOSCFAIL 0x00010000 // MOSC Failure NMI
+#define SYSCTL_NMIC_TAMPER 0x00000200 // Tamper Event NMI
+#define SYSCTL_NMIC_WDT1 0x00000020 // Watch Dog Timer (WDT) 1 NMI
+#define SYSCTL_NMIC_WDT0 0x00000008 // Watch Dog Timer (WDT) 0 NMI
+#define SYSCTL_NMIC_POWER 0x00000004 // Power/Brown Out Event NMI
+#define SYSCTL_NMIC_EXTERNAL 0x00000001 // External Pin NMI
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_GPIOHBCTL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_GPIOHBCTL_PORTJ 0x00000100 // Port J Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTH 0x00000080 // Port H Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTG 0x00000040 // Port G Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTF 0x00000020 // Port F Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTE 0x00000010 // Port E Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTD 0x00000008 // Port D Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTC 0x00000004 // Port C Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTB 0x00000002 // Port B Advanced High-Performance
+ // Bus
+#define SYSCTL_GPIOHBCTL_PORTA 0x00000001 // Port A Advanced High-Performance
+ // Bus
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCC2_USERCC2 0x80000000 // Use RCC2
+#define SYSCTL_RCC2_DIV400 0x40000000 // Divide PLL as 400 MHz vs. 200
+ // MHz
+#define SYSCTL_RCC2_SYSDIV2_M 0x1F800000 // System Clock Divisor 2
+#define SYSCTL_RCC2_SYSDIV2LSB 0x00400000 // Additional LSB for SYSDIV2
+#define SYSCTL_RCC2_USBPWRDN 0x00004000 // Power-Down USB PLL
+#define SYSCTL_RCC2_PWRDN2 0x00002000 // Power-Down PLL 2
+#define SYSCTL_RCC2_BYPASS2 0x00000800 // PLL Bypass 2
+#define SYSCTL_RCC2_OSCSRC2_M 0x00000070 // Oscillator Source 2
+#define SYSCTL_RCC2_OSCSRC2_MO 0x00000000 // MOSC
+#define SYSCTL_RCC2_OSCSRC2_IO 0x00000010 // PIOSC
+#define SYSCTL_RCC2_OSCSRC2_IO4 0x00000020 // PIOSC/4
+#define SYSCTL_RCC2_OSCSRC2_30 0x00000030 // LFIOSC
+#define SYSCTL_RCC2_OSCSRC2_32 0x00000070 // 32.768 kHz
+#define SYSCTL_RCC2_SYSDIV2_S 23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MOSCCTL register.
+//
+//*****************************************************************************
+#define SYSCTL_MOSCCTL_OSCRNG 0x00000010 // Oscillator Range
+#define SYSCTL_MOSCCTL_PWRDN 0x00000008 // Power Down
+#define SYSCTL_MOSCCTL_NOXTAL 0x00000004 // No Crystal Connected
+#define SYSCTL_MOSCCTL_MOSCIM 0x00000002 // MOSC Failure Action
+#define SYSCTL_MOSCCTL_CVAL 0x00000001 // Clock Validation for MOSC
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RSCLKCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RSCLKCFG_MEMTIMU 0x80000000 // Memory Timing Register Update
+#define SYSCTL_RSCLKCFG_NEWFREQ 0x40000000 // New PLLFREQ Accept
+#define SYSCTL_RSCLKCFG_ACG 0x20000000 // Auto Clock Gating
+#define SYSCTL_RSCLKCFG_USEPLL 0x10000000 // Use PLL
+#define SYSCTL_RSCLKCFG_PLLSRC_M \
+ 0x0F000000 // PLL Source
+#define SYSCTL_RSCLKCFG_PLLSRC_PIOSC \
+ 0x00000000 // PIOSC is PLL input clock source
+#define SYSCTL_RSCLKCFG_PLLSRC_MOSC \
+ 0x03000000 // MOSC is the PLL input clock
+ // source
+#define SYSCTL_RSCLKCFG_OSCSRC_M \
+ 0x00F00000 // Oscillator Source
+#define SYSCTL_RSCLKCFG_OSCSRC_PIOSC \
+ 0x00000000 // PIOSC is oscillator source
+#define SYSCTL_RSCLKCFG_OSCSRC_LFIOSC \
+ 0x00200000 // LFIOSC is oscillator source
+#define SYSCTL_RSCLKCFG_OSCSRC_MOSC \
+ 0x00300000 // MOSC is oscillator source
+#define SYSCTL_RSCLKCFG_OSCSRC_RTC \
+ 0x00400000 // Hibernation Module RTC
+ // Oscillator (RTCOSC)
+#define SYSCTL_RSCLKCFG_OSYSDIV_M \
+ 0x000FFC00 // Oscillator System Clock Divisor
+#define SYSCTL_RSCLKCFG_PSYSDIV_M \
+ 0x000003FF // PLL System Clock Divisor
+#define SYSCTL_RSCLKCFG_OSYSDIV_S \
+ 10
+#define SYSCTL_RSCLKCFG_PSYSDIV_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_MEMTIM0 register.
+//
+//*****************************************************************************
+#define SYSCTL_MEMTIM0_EBCHT_M 0x03C00000 // EEPROM Clock High Time
+#define SYSCTL_MEMTIM0_EBCHT_0_5 \
+ 0x00000000 // 1/2 system clock period
+#define SYSCTL_MEMTIM0_EBCHT_1 0x00400000 // 1 system clock period
+#define SYSCTL_MEMTIM0_EBCHT_1_5 \
+ 0x00800000 // 1.5 system clock periods
+#define SYSCTL_MEMTIM0_EBCHT_2 0x00C00000 // 2 system clock periods
+#define SYSCTL_MEMTIM0_EBCHT_2_5 \
+ 0x01000000 // 2.5 system clock periods
+#define SYSCTL_MEMTIM0_EBCHT_3 0x01400000 // 3 system clock periods
+#define SYSCTL_MEMTIM0_EBCHT_3_5 \
+ 0x01800000 // 3.5 system clock periods
+#define SYSCTL_MEMTIM0_EBCHT_4 0x01C00000 // 4 system clock periods
+#define SYSCTL_MEMTIM0_EBCHT_4_5 \
+ 0x02000000 // 4.5 system clock periods
+#define SYSCTL_MEMTIM0_EBCE 0x00200000 // EEPROM Bank Clock Edge
+#define SYSCTL_MEMTIM0_MB1 0x00100010 // Must be one
+#define SYSCTL_MEMTIM0_EWS_M 0x000F0000 // EEPROM Wait States
+#define SYSCTL_MEMTIM0_FBCHT_M 0x000003C0 // Flash Bank Clock High Time
+#define SYSCTL_MEMTIM0_FBCHT_0_5 \
+ 0x00000000 // 1/2 system clock period
+#define SYSCTL_MEMTIM0_FBCHT_1 0x00000040 // 1 system clock period
+#define SYSCTL_MEMTIM0_FBCHT_1_5 \
+ 0x00000080 // 1.5 system clock periods
+#define SYSCTL_MEMTIM0_FBCHT_2 0x000000C0 // 2 system clock periods
+#define SYSCTL_MEMTIM0_FBCHT_2_5 \
+ 0x00000100 // 2.5 system clock periods
+#define SYSCTL_MEMTIM0_FBCHT_3 0x00000140 // 3 system clock periods
+#define SYSCTL_MEMTIM0_FBCHT_3_5 \
+ 0x00000180 // 3.5 system clock periods
+#define SYSCTL_MEMTIM0_FBCHT_4 0x000001C0 // 4 system clock periods
+#define SYSCTL_MEMTIM0_FBCHT_4_5 \
+ 0x00000200 // 4.5 system clock periods
+#define SYSCTL_MEMTIM0_FBCE 0x00000020 // Flash Bank Clock Edge
+#define SYSCTL_MEMTIM0_FWS_M 0x0000000F // Flash Wait State
+#define SYSCTL_MEMTIM0_EWS_S 16
+#define SYSCTL_MEMTIM0_FWS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control
+#define SYSCTL_RCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control
+#define SYSCTL_RCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control
+#define SYSCTL_RCGC0_PWM0 0x00100000 // PWM Clock Gating Control
+#define SYSCTL_RCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control
+#define SYSCTL_RCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control
+#define SYSCTL_RCGC0_ADC1SPD_M 0x00000C00 // ADC1 Sample Speed
+#define SYSCTL_RCGC0_ADC1SPD_125K \
+ 0x00000000 // 125K samples/second
+#define SYSCTL_RCGC0_ADC1SPD_250K \
+ 0x00000400 // 250K samples/second
+#define SYSCTL_RCGC0_ADC1SPD_500K \
+ 0x00000800 // 500K samples/second
+#define SYSCTL_RCGC0_ADC1SPD_1M 0x00000C00 // 1M samples/second
+#define SYSCTL_RCGC0_ADC0SPD_M 0x00000300 // ADC0 Sample Speed
+#define SYSCTL_RCGC0_ADC0SPD_125K \
+ 0x00000000 // 125K samples/second
+#define SYSCTL_RCGC0_ADC0SPD_250K \
+ 0x00000100 // 250K samples/second
+#define SYSCTL_RCGC0_ADC0SPD_500K \
+ 0x00000200 // 500K samples/second
+#define SYSCTL_RCGC0_ADC0SPD_1M 0x00000300 // 1M samples/second
+#define SYSCTL_RCGC0_HIB 0x00000040 // HIB Clock Gating Control
+#define SYSCTL_RCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating
+#define SYSCTL_RCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating
+#define SYSCTL_RCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating
+#define SYSCTL_RCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control
+#define SYSCTL_RCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control
+#define SYSCTL_RCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control
+#define SYSCTL_RCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control
+#define SYSCTL_RCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control
+#define SYSCTL_RCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control
+#define SYSCTL_RCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control
+#define SYSCTL_RCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control
+#define SYSCTL_RCGC1_UART2 0x00000004 // UART2 Clock Gating Control
+#define SYSCTL_RCGC1_UART1 0x00000002 // UART1 Clock Gating Control
+#define SYSCTL_RCGC1_UART0 0x00000001 // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGC2_USB0 0x00010000 // USB0 Clock Gating Control
+#define SYSCTL_RCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control
+#define SYSCTL_RCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control
+#define SYSCTL_RCGC2_GPIOH 0x00000080 // Port H Clock Gating Control
+#define SYSCTL_RCGC2_GPIOG 0x00000040 // Port G Clock Gating Control
+#define SYSCTL_RCGC2_GPIOF 0x00000020 // Port F Clock Gating Control
+#define SYSCTL_RCGC2_GPIOE 0x00000010 // Port E Clock Gating Control
+#define SYSCTL_RCGC2_GPIOD 0x00000008 // Port D Clock Gating Control
+#define SYSCTL_RCGC2_GPIOC 0x00000004 // Port C Clock Gating Control
+#define SYSCTL_RCGC2_GPIOB 0x00000002 // Port B Clock Gating Control
+#define SYSCTL_RCGC2_GPIOA 0x00000001 // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control
+#define SYSCTL_SCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control
+#define SYSCTL_SCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control
+#define SYSCTL_SCGC0_PWM0 0x00100000 // PWM Clock Gating Control
+#define SYSCTL_SCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control
+#define SYSCTL_SCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control
+#define SYSCTL_SCGC0_ADCSPD_M 0x00000F00 // ADC Sample Speed
+#define SYSCTL_SCGC0_HIB 0x00000040 // HIB Clock Gating Control
+#define SYSCTL_SCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating
+#define SYSCTL_SCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating
+#define SYSCTL_SCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating
+#define SYSCTL_SCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control
+#define SYSCTL_SCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control
+#define SYSCTL_SCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control
+#define SYSCTL_SCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control
+#define SYSCTL_SCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control
+#define SYSCTL_SCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control
+#define SYSCTL_SCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control
+#define SYSCTL_SCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control
+#define SYSCTL_SCGC1_UART2 0x00000004 // UART2 Clock Gating Control
+#define SYSCTL_SCGC1_UART1 0x00000002 // UART1 Clock Gating Control
+#define SYSCTL_SCGC1_UART0 0x00000001 // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGC2_USB0 0x00010000 // USB0 Clock Gating Control
+#define SYSCTL_SCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control
+#define SYSCTL_SCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control
+#define SYSCTL_SCGC2_GPIOH 0x00000080 // Port H Clock Gating Control
+#define SYSCTL_SCGC2_GPIOG 0x00000040 // Port G Clock Gating Control
+#define SYSCTL_SCGC2_GPIOF 0x00000020 // Port F Clock Gating Control
+#define SYSCTL_SCGC2_GPIOE 0x00000010 // Port E Clock Gating Control
+#define SYSCTL_SCGC2_GPIOD 0x00000008 // Port D Clock Gating Control
+#define SYSCTL_SCGC2_GPIOC 0x00000004 // Port C Clock Gating Control
+#define SYSCTL_SCGC2_GPIOB 0x00000002 // Port B Clock Gating Control
+#define SYSCTL_SCGC2_GPIOA 0x00000001 // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC0 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC0_WDT1 0x10000000 // WDT1 Clock Gating Control
+#define SYSCTL_DCGC0_CAN1 0x02000000 // CAN1 Clock Gating Control
+#define SYSCTL_DCGC0_CAN0 0x01000000 // CAN0 Clock Gating Control
+#define SYSCTL_DCGC0_PWM0 0x00100000 // PWM Clock Gating Control
+#define SYSCTL_DCGC0_ADC1 0x00020000 // ADC1 Clock Gating Control
+#define SYSCTL_DCGC0_ADC0 0x00010000 // ADC0 Clock Gating Control
+#define SYSCTL_DCGC0_HIB 0x00000040 // HIB Clock Gating Control
+#define SYSCTL_DCGC0_WDT0 0x00000008 // WDT0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC1 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC1_COMP2 0x04000000 // Analog Comparator 2 Clock Gating
+#define SYSCTL_DCGC1_COMP1 0x02000000 // Analog Comparator 1 Clock Gating
+#define SYSCTL_DCGC1_COMP0 0x01000000 // Analog Comparator 0 Clock Gating
+#define SYSCTL_DCGC1_TIMER3 0x00080000 // Timer 3 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER2 0x00040000 // Timer 2 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER1 0x00020000 // Timer 1 Clock Gating Control
+#define SYSCTL_DCGC1_TIMER0 0x00010000 // Timer 0 Clock Gating Control
+#define SYSCTL_DCGC1_I2C1 0x00004000 // I2C1 Clock Gating Control
+#define SYSCTL_DCGC1_I2C0 0x00001000 // I2C0 Clock Gating Control
+#define SYSCTL_DCGC1_QEI1 0x00000200 // QEI1 Clock Gating Control
+#define SYSCTL_DCGC1_QEI0 0x00000100 // QEI0 Clock Gating Control
+#define SYSCTL_DCGC1_SSI1 0x00000020 // SSI1 Clock Gating Control
+#define SYSCTL_DCGC1_SSI0 0x00000010 // SSI0 Clock Gating Control
+#define SYSCTL_DCGC1_UART2 0x00000004 // UART2 Clock Gating Control
+#define SYSCTL_DCGC1_UART1 0x00000002 // UART1 Clock Gating Control
+#define SYSCTL_DCGC1_UART0 0x00000001 // UART0 Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGC2 register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGC2_USB0 0x00010000 // USB0 Clock Gating Control
+#define SYSCTL_DCGC2_UDMA 0x00002000 // Micro-DMA Clock Gating Control
+#define SYSCTL_DCGC2_GPIOJ 0x00000100 // Port J Clock Gating Control
+#define SYSCTL_DCGC2_GPIOH 0x00000080 // Port H Clock Gating Control
+#define SYSCTL_DCGC2_GPIOG 0x00000040 // Port G Clock Gating Control
+#define SYSCTL_DCGC2_GPIOF 0x00000020 // Port F Clock Gating Control
+#define SYSCTL_DCGC2_GPIOE 0x00000010 // Port E Clock Gating Control
+#define SYSCTL_DCGC2_GPIOD 0x00000008 // Port D Clock Gating Control
+#define SYSCTL_DCGC2_GPIOC 0x00000004 // Port C Clock Gating Control
+#define SYSCTL_DCGC2_GPIOB 0x00000002 // Port B Clock Gating Control
+#define SYSCTL_DCGC2_GPIOA 0x00000001 // Port A Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_ALTCLKCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_ALTCLKCFG_ALTCLK_M \
+ 0x0000000F // Alternate Clock Source
+#define SYSCTL_ALTCLKCFG_ALTCLK_PIOSC \
+ 0x00000000 // PIOSC
+#define SYSCTL_ALTCLKCFG_ALTCLK_RTCOSC \
+ 0x00000003 // Hibernation Module Real-time
+ // clock output (RTCOSC)
+#define SYSCTL_ALTCLKCFG_ALTCLK_LFIOSC \
+ 0x00000004 // Low-frequency internal
+ // oscillator (LFIOSC)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DSLPCLKCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DSLPCLKCFG_D_M 0x1F800000 // Divider Field Override
+#define SYSCTL_DSLPCLKCFG_O_M 0x00000070 // Clock Source
+#define SYSCTL_DSLPCLKCFG_O_IGN 0x00000000 // MOSC
+#define SYSCTL_DSLPCLKCFG_O_IO 0x00000010 // PIOSC
+#define SYSCTL_DSLPCLKCFG_O_30 0x00000030 // LFIOSC
+#define SYSCTL_DSLPCLKCFG_O_32 0x00000070 // 32.768 kHz
+#define SYSCTL_DSLPCLKCFG_PIOSCPD \
+ 0x00000002 // PIOSC Power Down Request
+#define SYSCTL_DSLPCLKCFG_D_S 23
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DSCLKCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DSCLKCFG_PIOSCPD 0x80000000 // PIOSC Power Down
+#define SYSCTL_DSCLKCFG_MOSCDPD 0x40000000 // MOSC Disable Power Down
+#define SYSCTL_DSCLKCFG_DSOSCSRC_M \
+ 0x00F00000 // Deep Sleep Oscillator Source
+#define SYSCTL_DSCLKCFG_DSOSCSRC_PIOSC \
+ 0x00000000 // PIOSC
+#define SYSCTL_DSCLKCFG_DSOSCSRC_LFIOSC \
+ 0x00200000 // LFIOSC
+#define SYSCTL_DSCLKCFG_DSOSCSRC_MOSC \
+ 0x00300000 // MOSC
+#define SYSCTL_DSCLKCFG_DSOSCSRC_RTC \
+ 0x00400000 // Hibernation Module RTCOSC
+#define SYSCTL_DSCLKCFG_DSSYSDIV_M \
+ 0x000003FF // Deep Sleep Clock Divisor
+#define SYSCTL_DSCLKCFG_DSSYSDIV_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DIVSCLK register.
+//
+//*****************************************************************************
+#define SYSCTL_DIVSCLK_EN 0x80000000 // DIVSCLK Enable
+#define SYSCTL_DIVSCLK_SRC_M 0x00030000 // Clock Source
+#define SYSCTL_DIVSCLK_SRC_SYSCLK \
+ 0x00000000 // System Clock
+#define SYSCTL_DIVSCLK_SRC_PIOSC \
+ 0x00010000 // PIOSC
+#define SYSCTL_DIVSCLK_SRC_MOSC 0x00020000 // MOSC
+#define SYSCTL_DIVSCLK_DIV_M 0x000000FF // Divisor Value
+#define SYSCTL_DIVSCLK_DIV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SYSPROP register.
+//
+//*****************************************************************************
+#define SYSCTL_SYSPROP_FPU 0x00000001 // FPU Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PIOSCCAL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PIOSCCAL_UTEN 0x80000000 // Use User Trim Value
+#define SYSCTL_PIOSCCAL_CAL 0x00000200 // Start Calibration
+#define SYSCTL_PIOSCCAL_UPDATE 0x00000100 // Update Trim
+#define SYSCTL_PIOSCCAL_UT_M 0x0000007F // User Trim Value
+#define SYSCTL_PIOSCCAL_UT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PIOSCSTAT
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PIOSCSTAT_DT_M 0x007F0000 // Default Trim Value
+#define SYSCTL_PIOSCSTAT_CR_M 0x00000300 // Calibration Result
+#define SYSCTL_PIOSCSTAT_CRNONE 0x00000000 // Calibration has not been
+ // attempted
+#define SYSCTL_PIOSCSTAT_CRPASS 0x00000100 // The last calibration operation
+ // completed to meet 1% accuracy
+#define SYSCTL_PIOSCSTAT_CRFAIL 0x00000200 // The last calibration operation
+ // failed to meet 1% accuracy
+#define SYSCTL_PIOSCSTAT_CT_M 0x0000007F // Calibration Trim Value
+#define SYSCTL_PIOSCSTAT_DT_S 16
+#define SYSCTL_PIOSCSTAT_CT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLFREQ0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLFREQ0_PLLPWR 0x00800000 // PLL Power
+#define SYSCTL_PLLFREQ0_MFRAC_M 0x000FFC00 // PLL M Fractional Value
+#define SYSCTL_PLLFREQ0_MINT_M 0x000003FF // PLL M Integer Value
+#define SYSCTL_PLLFREQ0_MFRAC_S 10
+#define SYSCTL_PLLFREQ0_MINT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLFREQ1
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLFREQ1_Q_M 0x00001F00 // PLL Q Value
+#define SYSCTL_PLLFREQ1_N_M 0x0000001F // PLL N Value
+#define SYSCTL_PLLFREQ1_Q_S 8
+#define SYSCTL_PLLFREQ1_N_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PLLSTAT register.
+//
+//*****************************************************************************
+#define SYSCTL_PLLSTAT_LOCK 0x00000001 // PLL Lock
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SLPPWRCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SLPPWRCFG_FLASHPM_M \
+ 0x00000030 // Flash Power Modes
+#define SYSCTL_SLPPWRCFG_FLASHPM_NRM \
+ 0x00000000 // Active Mode
+#define SYSCTL_SLPPWRCFG_FLASHPM_SLP \
+ 0x00000020 // Low Power Mode
+#define SYSCTL_SLPPWRCFG_SRAMPM_M \
+ 0x00000003 // SRAM Power Modes
+#define SYSCTL_SLPPWRCFG_SRAMPM_NRM \
+ 0x00000000 // Active Mode
+#define SYSCTL_SLPPWRCFG_SRAMPM_SBY \
+ 0x00000001 // Standby Mode
+#define SYSCTL_SLPPWRCFG_SRAMPM_LP \
+ 0x00000003 // Low Power Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DSLPPWRCFG
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DSLPPWRCFG_LDOSM 0x00000200 // LDO Sleep Mode
+#define SYSCTL_DSLPPWRCFG_TSPD 0x00000100 // Temperature Sense Power Down
+#define SYSCTL_DSLPPWRCFG_FLASHPM_M \
+ 0x00000030 // Flash Power Modes
+#define SYSCTL_DSLPPWRCFG_FLASHPM_NRM \
+ 0x00000000 // Active Mode
+#define SYSCTL_DSLPPWRCFG_FLASHPM_SLP \
+ 0x00000020 // Low Power Mode
+#define SYSCTL_DSLPPWRCFG_SRAMPM_M \
+ 0x00000003 // SRAM Power Modes
+#define SYSCTL_DSLPPWRCFG_SRAMPM_NRM \
+ 0x00000000 // Active Mode
+#define SYSCTL_DSLPPWRCFG_SRAMPM_SBY \
+ 0x00000001 // Standby Mode
+#define SYSCTL_DSLPPWRCFG_SRAMPM_LP \
+ 0x00000003 // Low Power Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DC9 register.
+//
+//*****************************************************************************
+#define SYSCTL_DC9_ADC1DC7 0x00800000 // ADC1 DC7 Present
+#define SYSCTL_DC9_ADC1DC6 0x00400000 // ADC1 DC6 Present
+#define SYSCTL_DC9_ADC1DC5 0x00200000 // ADC1 DC5 Present
+#define SYSCTL_DC9_ADC1DC4 0x00100000 // ADC1 DC4 Present
+#define SYSCTL_DC9_ADC1DC3 0x00080000 // ADC1 DC3 Present
+#define SYSCTL_DC9_ADC1DC2 0x00040000 // ADC1 DC2 Present
+#define SYSCTL_DC9_ADC1DC1 0x00020000 // ADC1 DC1 Present
+#define SYSCTL_DC9_ADC1DC0 0x00010000 // ADC1 DC0 Present
+#define SYSCTL_DC9_ADC0DC7 0x00000080 // ADC0 DC7 Present
+#define SYSCTL_DC9_ADC0DC6 0x00000040 // ADC0 DC6 Present
+#define SYSCTL_DC9_ADC0DC5 0x00000020 // ADC0 DC5 Present
+#define SYSCTL_DC9_ADC0DC4 0x00000010 // ADC0 DC4 Present
+#define SYSCTL_DC9_ADC0DC3 0x00000008 // ADC0 DC3 Present
+#define SYSCTL_DC9_ADC0DC2 0x00000004 // ADC0 DC2 Present
+#define SYSCTL_DC9_ADC0DC1 0x00000002 // ADC0 DC1 Present
+#define SYSCTL_DC9_ADC0DC0 0x00000001 // ADC0 DC0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_NVMSTAT register.
+//
+//*****************************************************************************
+#define SYSCTL_NVMSTAT_FWB 0x00000001 // 32 Word Flash Write Buffer
+ // Available
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_LDOSPCTL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_LDOSPCTL_VADJEN 0x80000000 // Voltage Adjust Enable
+#define SYSCTL_LDOSPCTL_VLDO_M 0x000000FF // LDO Output Voltage
+#define SYSCTL_LDOSPCTL_VLDO_0_90V \
+ 0x00000012 // 0.90 V
+#define SYSCTL_LDOSPCTL_VLDO_0_95V \
+ 0x00000013 // 0.95 V
+#define SYSCTL_LDOSPCTL_VLDO_1_00V \
+ 0x00000014 // 1.00 V
+#define SYSCTL_LDOSPCTL_VLDO_1_05V \
+ 0x00000015 // 1.05 V
+#define SYSCTL_LDOSPCTL_VLDO_1_10V \
+ 0x00000016 // 1.10 V
+#define SYSCTL_LDOSPCTL_VLDO_1_15V \
+ 0x00000017 // 1.15 V
+#define SYSCTL_LDOSPCTL_VLDO_1_20V \
+ 0x00000018 // 1.20 V
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_LDODPCTL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_LDODPCTL_VADJEN 0x80000000 // Voltage Adjust Enable
+#define SYSCTL_LDODPCTL_VLDO_M 0x000000FF // LDO Output Voltage
+#define SYSCTL_LDODPCTL_VLDO_0_90V \
+ 0x00000012 // 0.90 V
+#define SYSCTL_LDODPCTL_VLDO_0_95V \
+ 0x00000013 // 0.95 V
+#define SYSCTL_LDODPCTL_VLDO_1_00V \
+ 0x00000014 // 1.00 V
+#define SYSCTL_LDODPCTL_VLDO_1_05V \
+ 0x00000015 // 1.05 V
+#define SYSCTL_LDODPCTL_VLDO_1_10V \
+ 0x00000016 // 1.10 V
+#define SYSCTL_LDODPCTL_VLDO_1_15V \
+ 0x00000017 // 1.15 V
+#define SYSCTL_LDODPCTL_VLDO_1_20V \
+ 0x00000018 // 1.20 V
+#define SYSCTL_LDODPCTL_VLDO_1_25V \
+ 0x00000019 // 1.25 V
+#define SYSCTL_LDODPCTL_VLDO_1_30V \
+ 0x0000001A // 1.30 V
+#define SYSCTL_LDODPCTL_VLDO_1_35V \
+ 0x0000001B // 1.35 V
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RESBEHAVCTL
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RESBEHAVCTL_WDOG1_M \
+ 0x000000C0 // Watchdog 1 Reset Operation
+#define SYSCTL_RESBEHAVCTL_WDOG1_SYSRST \
+ 0x00000080 // Watchdog 1 issues a system
+ // reset. The application starts
+ // within 10 us
+#define SYSCTL_RESBEHAVCTL_WDOG1_POR \
+ 0x000000C0 // Watchdog 1 issues a simulated
+ // POR sequence. Application starts
+ // less than 500 us after
+ // deassertion (Default)
+#define SYSCTL_RESBEHAVCTL_WDOG0_M \
+ 0x00000030 // Watchdog 0 Reset Operation
+#define SYSCTL_RESBEHAVCTL_WDOG0_SYSRST \
+ 0x00000020 // Watchdog 0 issues a system
+ // reset. The application starts
+ // within 10 us
+#define SYSCTL_RESBEHAVCTL_WDOG0_POR \
+ 0x00000030 // Watchdog 0 issues a simulated
+ // POR sequence. Application starts
+ // less than 500 us after
+ // deassertion (Default)
+#define SYSCTL_RESBEHAVCTL_BOR_M \
+ 0x0000000C // BOR Reset operation
+#define SYSCTL_RESBEHAVCTL_BOR_SYSRST \
+ 0x00000008 // Brown Out Reset issues system
+ // reset. The application starts
+ // within 10 us
+#define SYSCTL_RESBEHAVCTL_BOR_POR \
+ 0x0000000C // Brown Out Reset issues a
+ // simulated POR sequence. The
+ // application starts less than 500
+ // us after deassertion (Default)
+#define SYSCTL_RESBEHAVCTL_EXTRES_M \
+ 0x00000003 // External RST Pin Operation
+#define SYSCTL_RESBEHAVCTL_EXTRES_SYSRST \
+ 0x00000002 // External RST assertion issues a
+ // system reset. The application
+ // starts within 10 us
+#define SYSCTL_RESBEHAVCTL_EXTRES_POR \
+ 0x00000003 // External RST assertion issues a
+ // simulated POR sequence.
+ // Application starts less than 500
+ // us after deassertion (Default)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_HSSR register.
+//
+//*****************************************************************************
+#define SYSCTL_HSSR_KEY_M 0xFF000000 // Write Key
+#define SYSCTL_HSSR_CDOFF_M 0x00FFFFFF // Command Descriptor Pointer
+#define SYSCTL_HSSR_KEY_S 24
+#define SYSCTL_HSSR_CDOFF_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_USBPDS register.
+//
+//*****************************************************************************
+#define SYSCTL_USBPDS_MEMSTAT_M 0x0000000C // Memory Array Power Status
+#define SYSCTL_USBPDS_MEMSTAT_OFF \
+ 0x00000000 // Array OFF
+#define SYSCTL_USBPDS_MEMSTAT_RETAIN \
+ 0x00000004 // SRAM Retention
+#define SYSCTL_USBPDS_MEMSTAT_ON \
+ 0x0000000C // Array On
+#define SYSCTL_USBPDS_PWRSTAT_M 0x00000003 // Power Domain Status
+#define SYSCTL_USBPDS_PWRSTAT_OFF \
+ 0x00000000 // OFF
+#define SYSCTL_USBPDS_PWRSTAT_ON \
+ 0x00000003 // ON
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_USBMPC register.
+//
+//*****************************************************************************
+#define SYSCTL_USBMPC_PWRCTL_M 0x00000003 // Memory Array Power Control
+#define SYSCTL_USBMPC_PWRCTL_OFF \
+ 0x00000000 // Array OFF
+#define SYSCTL_USBMPC_PWRCTL_RETAIN \
+ 0x00000001 // SRAM Retention
+#define SYSCTL_USBMPC_PWRCTL_ON 0x00000003 // Array On
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_EMACPDS register.
+//
+//*****************************************************************************
+#define SYSCTL_EMACPDS_MEMSTAT_M \
+ 0x0000000C // Memory Array Power Status
+#define SYSCTL_EMACPDS_MEMSTAT_OFF \
+ 0x00000000 // Array OFF
+#define SYSCTL_EMACPDS_MEMSTAT_ON \
+ 0x0000000C // Array On
+#define SYSCTL_EMACPDS_PWRSTAT_M \
+ 0x00000003 // Power Domain Status
+#define SYSCTL_EMACPDS_PWRSTAT_OFF \
+ 0x00000000 // OFF
+#define SYSCTL_EMACPDS_PWRSTAT_ON \
+ 0x00000003 // ON
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_EMACMPC register.
+//
+//*****************************************************************************
+#define SYSCTL_EMACMPC_PWRCTL_M 0x00000003 // Memory Array Power Control
+#define SYSCTL_EMACMPC_PWRCTL_OFF \
+ 0x00000000 // Array OFF
+#define SYSCTL_EMACMPC_PWRCTL_ON \
+ 0x00000003 // Array On
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_LCDMPC register.
+//
+//*****************************************************************************
+#define SYSCTL_LCDMPC_PWRCTL_M 0x00000003 // Memory Array Power Control
+#define SYSCTL_LCDMPC_PWRCTL_OFF \
+ 0x00000000 // Array OFF
+#define SYSCTL_LCDMPC_PWRCTL_ON 0x00000003 // Array On
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPWD register.
+//
+//*****************************************************************************
+#define SYSCTL_PPWD_P1 0x00000002 // Watchdog Timer 1 Present
+#define SYSCTL_PPWD_P0 0x00000001 // Watchdog Timer 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPTIMER register.
+//
+//*****************************************************************************
+#define SYSCTL_PPTIMER_P7 0x00000080 // 16/32-Bit General-Purpose Timer
+ // 7 Present
+#define SYSCTL_PPTIMER_P6 0x00000040 // 16/32-Bit General-Purpose Timer
+ // 6 Present
+#define SYSCTL_PPTIMER_P5 0x00000020 // 16/32-Bit General-Purpose Timer
+ // 5 Present
+#define SYSCTL_PPTIMER_P4 0x00000010 // 16/32-Bit General-Purpose Timer
+ // 4 Present
+#define SYSCTL_PPTIMER_P3 0x00000008 // 16/32-Bit General-Purpose Timer
+ // 3 Present
+#define SYSCTL_PPTIMER_P2 0x00000004 // 16/32-Bit General-Purpose Timer
+ // 2 Present
+#define SYSCTL_PPTIMER_P1 0x00000002 // 16/32-Bit General-Purpose Timer
+ // 1 Present
+#define SYSCTL_PPTIMER_P0 0x00000001 // 16/32-Bit General-Purpose Timer
+ // 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPGPIO register.
+//
+//*****************************************************************************
+#define SYSCTL_PPGPIO_P17 0x00020000 // GPIO Port T Present
+#define SYSCTL_PPGPIO_P16 0x00010000 // GPIO Port S Present
+#define SYSCTL_PPGPIO_P15 0x00008000 // GPIO Port R Present
+#define SYSCTL_PPGPIO_P14 0x00004000 // GPIO Port Q Present
+#define SYSCTL_PPGPIO_P13 0x00002000 // GPIO Port P Present
+#define SYSCTL_PPGPIO_P12 0x00001000 // GPIO Port N Present
+#define SYSCTL_PPGPIO_P11 0x00000800 // GPIO Port M Present
+#define SYSCTL_PPGPIO_P10 0x00000400 // GPIO Port L Present
+#define SYSCTL_PPGPIO_P9 0x00000200 // GPIO Port K Present
+#define SYSCTL_PPGPIO_P8 0x00000100 // GPIO Port J Present
+#define SYSCTL_PPGPIO_P7 0x00000080 // GPIO Port H Present
+#define SYSCTL_PPGPIO_P6 0x00000040 // GPIO Port G Present
+#define SYSCTL_PPGPIO_P5 0x00000020 // GPIO Port F Present
+#define SYSCTL_PPGPIO_P4 0x00000010 // GPIO Port E Present
+#define SYSCTL_PPGPIO_P3 0x00000008 // GPIO Port D Present
+#define SYSCTL_PPGPIO_P2 0x00000004 // GPIO Port C Present
+#define SYSCTL_PPGPIO_P1 0x00000002 // GPIO Port B Present
+#define SYSCTL_PPGPIO_P0 0x00000001 // GPIO Port A Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_PPDMA_P0 0x00000001 // uDMA Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPEPI register.
+//
+//*****************************************************************************
+#define SYSCTL_PPEPI_P0 0x00000001 // EPI Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_PPHIB_P0 0x00000001 // Hibernation Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPUART register.
+//
+//*****************************************************************************
+#define SYSCTL_PPUART_P7 0x00000080 // UART Module 7 Present
+#define SYSCTL_PPUART_P6 0x00000040 // UART Module 6 Present
+#define SYSCTL_PPUART_P5 0x00000020 // UART Module 5 Present
+#define SYSCTL_PPUART_P4 0x00000010 // UART Module 4 Present
+#define SYSCTL_PPUART_P3 0x00000008 // UART Module 3 Present
+#define SYSCTL_PPUART_P2 0x00000004 // UART Module 2 Present
+#define SYSCTL_PPUART_P1 0x00000002 // UART Module 1 Present
+#define SYSCTL_PPUART_P0 0x00000001 // UART Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_PPSSI_P3 0x00000008 // SSI Module 3 Present
+#define SYSCTL_PPSSI_P2 0x00000004 // SSI Module 2 Present
+#define SYSCTL_PPSSI_P1 0x00000002 // SSI Module 1 Present
+#define SYSCTL_PPSSI_P0 0x00000001 // SSI Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_PPI2C_P9 0x00000200 // I2C Module 9 Present
+#define SYSCTL_PPI2C_P8 0x00000100 // I2C Module 8 Present
+#define SYSCTL_PPI2C_P7 0x00000080 // I2C Module 7 Present
+#define SYSCTL_PPI2C_P6 0x00000040 // I2C Module 6 Present
+#define SYSCTL_PPI2C_P5 0x00000020 // I2C Module 5 Present
+#define SYSCTL_PPI2C_P4 0x00000010 // I2C Module 4 Present
+#define SYSCTL_PPI2C_P3 0x00000008 // I2C Module 3 Present
+#define SYSCTL_PPI2C_P2 0x00000004 // I2C Module 2 Present
+#define SYSCTL_PPI2C_P1 0x00000002 // I2C Module 1 Present
+#define SYSCTL_PPI2C_P0 0x00000001 // I2C Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_PPUSB_P0 0x00000001 // USB Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPEPHY register.
+//
+//*****************************************************************************
+#define SYSCTL_PPEPHY_P0 0x00000001 // Ethernet PHY Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_PPCAN_P1 0x00000002 // CAN Module 1 Present
+#define SYSCTL_PPCAN_P0 0x00000001 // CAN Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPADC register.
+//
+//*****************************************************************************
+#define SYSCTL_PPADC_P1 0x00000002 // ADC Module 1 Present
+#define SYSCTL_PPADC_P0 0x00000001 // ADC Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPACMP register.
+//
+//*****************************************************************************
+#define SYSCTL_PPACMP_P0 0x00000001 // Analog Comparator Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_PPPWM_P1 0x00000002 // PWM Module 1 Present
+#define SYSCTL_PPPWM_P0 0x00000001 // PWM Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_PPQEI_P1 0x00000002 // QEI Module 1 Present
+#define SYSCTL_PPQEI_P0 0x00000001 // QEI Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPLPC register.
+//
+//*****************************************************************************
+#define SYSCTL_PPLPC_P0 0x00000001 // LPC Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPPECI register.
+//
+//*****************************************************************************
+#define SYSCTL_PPPECI_P0 0x00000001 // PECI Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPFAN register.
+//
+//*****************************************************************************
+#define SYSCTL_PPFAN_P0 0x00000001 // FAN Module 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PPEEPROM_P0 0x00000001 // EEPROM Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PPWTIMER_P5 0x00000020 // 32/64-Bit Wide General-Purpose
+ // Timer 5 Present
+#define SYSCTL_PPWTIMER_P4 0x00000010 // 32/64-Bit Wide General-Purpose
+ // Timer 4 Present
+#define SYSCTL_PPWTIMER_P3 0x00000008 // 32/64-Bit Wide General-Purpose
+ // Timer 3 Present
+#define SYSCTL_PPWTIMER_P2 0x00000004 // 32/64-Bit Wide General-Purpose
+ // Timer 2 Present
+#define SYSCTL_PPWTIMER_P1 0x00000002 // 32/64-Bit Wide General-Purpose
+ // Timer 1 Present
+#define SYSCTL_PPWTIMER_P0 0x00000001 // 32/64-Bit Wide General-Purpose
+ // Timer 0 Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPRTS register.
+//
+//*****************************************************************************
+#define SYSCTL_PPRTS_P0 0x00000001 // RTS Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPCCM register.
+//
+//*****************************************************************************
+#define SYSCTL_PPCCM_P0 0x00000001 // CRC and Cryptographic Modules
+ // Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPLCD register.
+//
+//*****************************************************************************
+#define SYSCTL_PPLCD_P0 0x00000001 // LCD Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPOWIRE register.
+//
+//*****************************************************************************
+#define SYSCTL_PPOWIRE_P0 0x00000001 // 1-Wire Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPEMAC register.
+//
+//*****************************************************************************
+#define SYSCTL_PPEMAC_P0 0x00000001 // Ethernet Controller Module
+ // Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PPHIM register.
+//
+//*****************************************************************************
+#define SYSCTL_PPHIM_P0 0x00000001 // HIM Module Present
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRWD register.
+//
+//*****************************************************************************
+#define SYSCTL_SRWD_R1 0x00000002 // Watchdog Timer 1 Software Reset
+#define SYSCTL_SRWD_R0 0x00000001 // Watchdog Timer 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRTIMER register.
+//
+//*****************************************************************************
+#define SYSCTL_SRTIMER_R7 0x00000080 // 16/32-Bit General-Purpose Timer
+ // 7 Software Reset
+#define SYSCTL_SRTIMER_R6 0x00000040 // 16/32-Bit General-Purpose Timer
+ // 6 Software Reset
+#define SYSCTL_SRTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer
+ // 5 Software Reset
+#define SYSCTL_SRTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer
+ // 4 Software Reset
+#define SYSCTL_SRTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer
+ // 3 Software Reset
+#define SYSCTL_SRTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer
+ // 2 Software Reset
+#define SYSCTL_SRTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer
+ // 1 Software Reset
+#define SYSCTL_SRTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer
+ // 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRGPIO register.
+//
+//*****************************************************************************
+#define SYSCTL_SRGPIO_R17 0x00020000 // GPIO Port T Software Reset
+#define SYSCTL_SRGPIO_R16 0x00010000 // GPIO Port S Software Reset
+#define SYSCTL_SRGPIO_R15 0x00008000 // GPIO Port R Software Reset
+#define SYSCTL_SRGPIO_R14 0x00004000 // GPIO Port Q Software Reset
+#define SYSCTL_SRGPIO_R13 0x00002000 // GPIO Port P Software Reset
+#define SYSCTL_SRGPIO_R12 0x00001000 // GPIO Port N Software Reset
+#define SYSCTL_SRGPIO_R11 0x00000800 // GPIO Port M Software Reset
+#define SYSCTL_SRGPIO_R10 0x00000400 // GPIO Port L Software Reset
+#define SYSCTL_SRGPIO_R9 0x00000200 // GPIO Port K Software Reset
+#define SYSCTL_SRGPIO_R8 0x00000100 // GPIO Port J Software Reset
+#define SYSCTL_SRGPIO_R7 0x00000080 // GPIO Port H Software Reset
+#define SYSCTL_SRGPIO_R6 0x00000040 // GPIO Port G Software Reset
+#define SYSCTL_SRGPIO_R5 0x00000020 // GPIO Port F Software Reset
+#define SYSCTL_SRGPIO_R4 0x00000010 // GPIO Port E Software Reset
+#define SYSCTL_SRGPIO_R3 0x00000008 // GPIO Port D Software Reset
+#define SYSCTL_SRGPIO_R2 0x00000004 // GPIO Port C Software Reset
+#define SYSCTL_SRGPIO_R1 0x00000002 // GPIO Port B Software Reset
+#define SYSCTL_SRGPIO_R0 0x00000001 // GPIO Port A Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_SRDMA_R0 0x00000001 // uDMA Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SREPI register.
+//
+//*****************************************************************************
+#define SYSCTL_SREPI_R0 0x00000001 // EPI Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_SRHIB_R0 0x00000001 // Hibernation Module Software
+ // Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRUART register.
+//
+//*****************************************************************************
+#define SYSCTL_SRUART_R7 0x00000080 // UART Module 7 Software Reset
+#define SYSCTL_SRUART_R6 0x00000040 // UART Module 6 Software Reset
+#define SYSCTL_SRUART_R5 0x00000020 // UART Module 5 Software Reset
+#define SYSCTL_SRUART_R4 0x00000010 // UART Module 4 Software Reset
+#define SYSCTL_SRUART_R3 0x00000008 // UART Module 3 Software Reset
+#define SYSCTL_SRUART_R2 0x00000004 // UART Module 2 Software Reset
+#define SYSCTL_SRUART_R1 0x00000002 // UART Module 1 Software Reset
+#define SYSCTL_SRUART_R0 0x00000001 // UART Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_SRSSI_R3 0x00000008 // SSI Module 3 Software Reset
+#define SYSCTL_SRSSI_R2 0x00000004 // SSI Module 2 Software Reset
+#define SYSCTL_SRSSI_R1 0x00000002 // SSI Module 1 Software Reset
+#define SYSCTL_SRSSI_R0 0x00000001 // SSI Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_SRI2C_R9 0x00000200 // I2C Module 9 Software Reset
+#define SYSCTL_SRI2C_R8 0x00000100 // I2C Module 8 Software Reset
+#define SYSCTL_SRI2C_R7 0x00000080 // I2C Module 7 Software Reset
+#define SYSCTL_SRI2C_R6 0x00000040 // I2C Module 6 Software Reset
+#define SYSCTL_SRI2C_R5 0x00000020 // I2C Module 5 Software Reset
+#define SYSCTL_SRI2C_R4 0x00000010 // I2C Module 4 Software Reset
+#define SYSCTL_SRI2C_R3 0x00000008 // I2C Module 3 Software Reset
+#define SYSCTL_SRI2C_R2 0x00000004 // I2C Module 2 Software Reset
+#define SYSCTL_SRI2C_R1 0x00000002 // I2C Module 1 Software Reset
+#define SYSCTL_SRI2C_R0 0x00000001 // I2C Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_SRUSB_R0 0x00000001 // USB Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SREPHY register.
+//
+//*****************************************************************************
+#define SYSCTL_SREPHY_R0 0x00000001 // Ethernet PHY Module Software
+ // Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCAN_R1 0x00000002 // CAN Module 1 Software Reset
+#define SYSCTL_SRCAN_R0 0x00000001 // CAN Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRADC register.
+//
+//*****************************************************************************
+#define SYSCTL_SRADC_R1 0x00000002 // ADC Module 1 Software Reset
+#define SYSCTL_SRADC_R0 0x00000001 // ADC Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRACMP register.
+//
+//*****************************************************************************
+#define SYSCTL_SRACMP_R0 0x00000001 // Analog Comparator Module 0
+ // Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_SRPWM_R1 0x00000002 // PWM Module 1 Software Reset
+#define SYSCTL_SRPWM_R0 0x00000001 // PWM Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_SRQEI_R1 0x00000002 // QEI Module 1 Software Reset
+#define SYSCTL_SRQEI_R0 0x00000001 // QEI Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SREEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SREEPROM_R0 0x00000001 // EEPROM Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SRWTIMER_R5 0x00000020 // 32/64-Bit Wide General-Purpose
+ // Timer 5 Software Reset
+#define SYSCTL_SRWTIMER_R4 0x00000010 // 32/64-Bit Wide General-Purpose
+ // Timer 4 Software Reset
+#define SYSCTL_SRWTIMER_R3 0x00000008 // 32/64-Bit Wide General-Purpose
+ // Timer 3 Software Reset
+#define SYSCTL_SRWTIMER_R2 0x00000004 // 32/64-Bit Wide General-Purpose
+ // Timer 2 Software Reset
+#define SYSCTL_SRWTIMER_R1 0x00000002 // 32/64-Bit Wide General-Purpose
+ // Timer 1 Software Reset
+#define SYSCTL_SRWTIMER_R0 0x00000001 // 32/64-Bit Wide General-Purpose
+ // Timer 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRCCM register.
+//
+//*****************************************************************************
+#define SYSCTL_SRCCM_R0 0x00000001 // CRC and Cryptographic Modules
+ // Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SRLCD register.
+//
+//*****************************************************************************
+#define SYSCTL_SRLCD_R0 0x00000001 // LCD Module 0 Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SROWIRE register.
+//
+//*****************************************************************************
+#define SYSCTL_SROWIRE_R0 0x00000001 // 1-Wire Module Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SREMAC register.
+//
+//*****************************************************************************
+#define SYSCTL_SREMAC_R0 0x00000001 // Ethernet Controller MAC Module 0
+ // Software Reset
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCWD register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCWD_R1 0x00000002 // Watchdog Timer 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCWD_R0 0x00000001 // Watchdog Timer 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCTIMER_R7 0x00000080 // 16/32-Bit General-Purpose Timer
+ // 7 Run Mode Clock Gating Control
+#define SYSCTL_RCGCTIMER_R6 0x00000040 // 16/32-Bit General-Purpose Timer
+ // 6 Run Mode Clock Gating Control
+#define SYSCTL_RCGCTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer
+ // 5 Run Mode Clock Gating Control
+#define SYSCTL_RCGCTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer
+ // 4 Run Mode Clock Gating Control
+#define SYSCTL_RCGCTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer
+ // 3 Run Mode Clock Gating Control
+#define SYSCTL_RCGCTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer
+ // 2 Run Mode Clock Gating Control
+#define SYSCTL_RCGCTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer
+ // 1 Run Mode Clock Gating Control
+#define SYSCTL_RCGCTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer
+ // 0 Run Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCGPIO
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCGPIO_R17 0x00020000 // GPIO Port T Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R16 0x00010000 // GPIO Port S Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R15 0x00008000 // GPIO Port R Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R14 0x00004000 // GPIO Port Q Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R13 0x00002000 // GPIO Port P Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R12 0x00001000 // GPIO Port N Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R11 0x00000800 // GPIO Port M Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R10 0x00000400 // GPIO Port L Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R9 0x00000200 // GPIO Port K Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R8 0x00000100 // GPIO Port J Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R7 0x00000080 // GPIO Port H Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R6 0x00000040 // GPIO Port G Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R5 0x00000020 // GPIO Port F Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R4 0x00000010 // GPIO Port E Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R3 0x00000008 // GPIO Port D Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R2 0x00000004 // GPIO Port C Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R1 0x00000002 // GPIO Port B Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCGPIO_R0 0x00000001 // GPIO Port A Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCDMA_R0 0x00000001 // uDMA Module Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCEPI register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCEPI_R0 0x00000001 // EPI Module Run Mode Clock Gating
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCHIB_R0 0x00000001 // Hibernation Module Run Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCUART
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCUART_R7 0x00000080 // UART Module 7 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART_R6 0x00000040 // UART Module 6 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART_R5 0x00000020 // UART Module 5 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART_R4 0x00000010 // UART Module 4 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART_R3 0x00000008 // UART Module 3 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART_R2 0x00000004 // UART Module 2 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART_R1 0x00000002 // UART Module 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCUART_R0 0x00000001 // UART Module 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCSSI_R3 0x00000008 // SSI Module 3 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCSSI_R2 0x00000004 // SSI Module 2 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCSSI_R1 0x00000002 // SSI Module 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCSSI_R0 0x00000001 // SSI Module 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCI2C_R9 0x00000200 // I2C Module 9 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCI2C_R8 0x00000100 // I2C Module 8 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCI2C_R7 0x00000080 // I2C Module 7 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCI2C_R6 0x00000040 // I2C Module 6 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCI2C_R5 0x00000020 // I2C Module 5 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCI2C_R4 0x00000010 // I2C Module 4 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCI2C_R3 0x00000008 // I2C Module 3 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCI2C_R2 0x00000004 // I2C Module 2 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCI2C_R1 0x00000002 // I2C Module 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCI2C_R0 0x00000001 // I2C Module 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCUSB_R0 0x00000001 // USB Module Run Mode Clock Gating
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCEPHY
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCEPHY_R0 0x00000001 // Ethernet PHY Module Run Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCCAN_R1 0x00000002 // CAN Module 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCCAN_R0 0x00000001 // CAN Module 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCADC register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCADC_R1 0x00000002 // ADC Module 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCADC_R0 0x00000001 // ADC Module 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCACMP
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCACMP_R0 0x00000001 // Analog Comparator Module 0 Run
+ // Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCPWM_R1 0x00000002 // PWM Module 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCPWM_R0 0x00000001 // PWM Module 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCQEI_R1 0x00000002 // QEI Module 1 Run Mode Clock
+ // Gating Control
+#define SYSCTL_RCGCQEI_R0 0x00000001 // QEI Module 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCEEPROM_R0 0x00000001 // EEPROM Module Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCWTIMER_R5 0x00000020 // 32/64-Bit Wide General-Purpose
+ // Timer 5 Run Mode Clock Gating
+ // Control
+#define SYSCTL_RCGCWTIMER_R4 0x00000010 // 32/64-Bit Wide General-Purpose
+ // Timer 4 Run Mode Clock Gating
+ // Control
+#define SYSCTL_RCGCWTIMER_R3 0x00000008 // 32/64-Bit Wide General-Purpose
+ // Timer 3 Run Mode Clock Gating
+ // Control
+#define SYSCTL_RCGCWTIMER_R2 0x00000004 // 32/64-Bit Wide General-Purpose
+ // Timer 2 Run Mode Clock Gating
+ // Control
+#define SYSCTL_RCGCWTIMER_R1 0x00000002 // 32/64-Bit Wide General-Purpose
+ // Timer 1 Run Mode Clock Gating
+ // Control
+#define SYSCTL_RCGCWTIMER_R0 0x00000001 // 32/64-Bit Wide General-Purpose
+ // Timer 0 Run Mode Clock Gating
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCCCM register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCCCM_R0 0x00000001 // CRC and Cryptographic Modules
+ // Run Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCLCD register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCLCD_R0 0x00000001 // LCD Controller Module 0 Run Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCOWIRE
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCOWIRE_R0 0x00000001 // 1-Wire Module 0 Run Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_RCGCEMAC
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RCGCEMAC_R0 0x00000001 // Ethernet MAC Module 0 Run Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCWD register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCWD_S1 0x00000002 // Watchdog Timer 1 Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_SCGCWD_S0 0x00000001 // Watchdog Timer 0 Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCTIMER_S7 0x00000080 // 16/32-Bit General-Purpose Timer
+ // 7 Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCTIMER_S6 0x00000040 // 16/32-Bit General-Purpose Timer
+ // 6 Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCTIMER_S5 0x00000020 // 16/32-Bit General-Purpose Timer
+ // 5 Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCTIMER_S4 0x00000010 // 16/32-Bit General-Purpose Timer
+ // 4 Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCTIMER_S3 0x00000008 // 16/32-Bit General-Purpose Timer
+ // 3 Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCTIMER_S2 0x00000004 // 16/32-Bit General-Purpose Timer
+ // 2 Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCTIMER_S1 0x00000002 // 16/32-Bit General-Purpose Timer
+ // 1 Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCTIMER_S0 0x00000001 // 16/32-Bit General-Purpose Timer
+ // 0 Sleep Mode Clock Gating
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCGPIO
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCGPIO_S17 0x00020000 // GPIO Port T Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S16 0x00010000 // GPIO Port S Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S15 0x00008000 // GPIO Port R Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S14 0x00004000 // GPIO Port Q Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S13 0x00002000 // GPIO Port P Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S12 0x00001000 // GPIO Port N Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S11 0x00000800 // GPIO Port M Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S10 0x00000400 // GPIO Port L Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S9 0x00000200 // GPIO Port K Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S8 0x00000100 // GPIO Port J Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S7 0x00000080 // GPIO Port H Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S6 0x00000040 // GPIO Port G Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S5 0x00000020 // GPIO Port F Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S4 0x00000010 // GPIO Port E Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S3 0x00000008 // GPIO Port D Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S2 0x00000004 // GPIO Port C Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S1 0x00000002 // GPIO Port B Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCGPIO_S0 0x00000001 // GPIO Port A Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCDMA_S0 0x00000001 // uDMA Module Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCEPI register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCEPI_S0 0x00000001 // EPI Module Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCHIB_S0 0x00000001 // Hibernation Module Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCUART
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCUART_S7 0x00000080 // UART Module 7 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART_S6 0x00000040 // UART Module 6 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART_S5 0x00000020 // UART Module 5 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART_S4 0x00000010 // UART Module 4 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART_S3 0x00000008 // UART Module 3 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART_S2 0x00000004 // UART Module 2 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART_S1 0x00000002 // UART Module 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCUART_S0 0x00000001 // UART Module 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCSSI_S3 0x00000008 // SSI Module 3 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCSSI_S2 0x00000004 // SSI Module 2 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCSSI_S1 0x00000002 // SSI Module 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCSSI_S0 0x00000001 // SSI Module 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCI2C_S9 0x00000200 // I2C Module 9 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCI2C_S8 0x00000100 // I2C Module 8 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCI2C_S7 0x00000080 // I2C Module 7 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCI2C_S6 0x00000040 // I2C Module 6 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCI2C_S5 0x00000020 // I2C Module 5 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCI2C_S4 0x00000010 // I2C Module 4 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCI2C_S3 0x00000008 // I2C Module 3 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCI2C_S2 0x00000004 // I2C Module 2 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCI2C_S1 0x00000002 // I2C Module 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCI2C_S0 0x00000001 // I2C Module 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCUSB_S0 0x00000001 // USB Module Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCEPHY
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCEPHY_S0 0x00000001 // PHY Module Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCCAN_S1 0x00000002 // CAN Module 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCCAN_S0 0x00000001 // CAN Module 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCADC register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCADC_S1 0x00000002 // ADC Module 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCADC_S0 0x00000001 // ADC Module 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCACMP
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCACMP_S0 0x00000001 // Analog Comparator Module 0 Sleep
+ // Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCPWM_S1 0x00000002 // PWM Module 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCPWM_S0 0x00000001 // PWM Module 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCQEI_S1 0x00000002 // QEI Module 1 Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_SCGCQEI_S0 0x00000001 // QEI Module 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCEEPROM_S0 0x00000001 // EEPROM Module Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCWTIMER_S5 0x00000020 // 32/64-Bit Wide General-Purpose
+ // Timer 5 Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCWTIMER_S4 0x00000010 // 32/64-Bit Wide General-Purpose
+ // Timer 4 Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCWTIMER_S3 0x00000008 // 32/64-Bit Wide General-Purpose
+ // Timer 3 Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCWTIMER_S2 0x00000004 // 32/64-Bit Wide General-Purpose
+ // Timer 2 Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCWTIMER_S1 0x00000002 // 32/64-Bit Wide General-Purpose
+ // Timer 1 Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_SCGCWTIMER_S0 0x00000001 // 32/64-Bit Wide General-Purpose
+ // Timer 0 Sleep Mode Clock Gating
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCCCM register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCCCM_S0 0x00000001 // CRC and Cryptographic Modules
+ // Sleep Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCLCD register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCLCD_S0 0x00000001 // LCD Controller Module 0 Sleep
+ // Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCOWIRE
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCOWIRE_S0 0x00000001 // 1-Wire Module 0 Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_SCGCEMAC
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_SCGCEMAC_S0 0x00000001 // Ethernet MAC Module 0 Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCWD register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCWD_D1 0x00000002 // Watchdog Timer 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCWD_D0 0x00000001 // Watchdog Timer 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCTIMER_D7 0x00000080 // 16/32-Bit General-Purpose Timer
+ // 7 Deep-Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_DCGCTIMER_D6 0x00000040 // 16/32-Bit General-Purpose Timer
+ // 6 Deep-Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_DCGCTIMER_D5 0x00000020 // 16/32-Bit General-Purpose Timer
+ // 5 Deep-Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_DCGCTIMER_D4 0x00000010 // 16/32-Bit General-Purpose Timer
+ // 4 Deep-Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_DCGCTIMER_D3 0x00000008 // 16/32-Bit General-Purpose Timer
+ // 3 Deep-Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_DCGCTIMER_D2 0x00000004 // 16/32-Bit General-Purpose Timer
+ // 2 Deep-Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_DCGCTIMER_D1 0x00000002 // 16/32-Bit General-Purpose Timer
+ // 1 Deep-Sleep Mode Clock Gating
+ // Control
+#define SYSCTL_DCGCTIMER_D0 0x00000001 // 16/32-Bit General-Purpose Timer
+ // 0 Deep-Sleep Mode Clock Gating
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCGPIO
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCGPIO_D17 0x00020000 // GPIO Port T Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D16 0x00010000 // GPIO Port S Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D15 0x00008000 // GPIO Port R Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D14 0x00004000 // GPIO Port Q Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D13 0x00002000 // GPIO Port P Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D12 0x00001000 // GPIO Port N Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D11 0x00000800 // GPIO Port M Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D10 0x00000400 // GPIO Port L Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D9 0x00000200 // GPIO Port K Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D8 0x00000100 // GPIO Port J Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D7 0x00000080 // GPIO Port H Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D6 0x00000040 // GPIO Port G Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D5 0x00000020 // GPIO Port F Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D4 0x00000010 // GPIO Port E Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D3 0x00000008 // GPIO Port D Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D2 0x00000004 // GPIO Port C Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D1 0x00000002 // GPIO Port B Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCGPIO_D0 0x00000001 // GPIO Port A Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCDMA_D0 0x00000001 // uDMA Module Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCEPI register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCEPI_D0 0x00000001 // EPI Module Deep-Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCHIB_D0 0x00000001 // Hibernation Module Deep-Sleep
+ // Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCUART
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCUART_D7 0x00000080 // UART Module 7 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART_D6 0x00000040 // UART Module 6 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART_D5 0x00000020 // UART Module 5 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART_D4 0x00000010 // UART Module 4 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART_D3 0x00000008 // UART Module 3 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART_D2 0x00000004 // UART Module 2 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART_D1 0x00000002 // UART Module 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCUART_D0 0x00000001 // UART Module 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCSSI_D3 0x00000008 // SSI Module 3 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCSSI_D2 0x00000004 // SSI Module 2 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCSSI_D1 0x00000002 // SSI Module 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCSSI_D0 0x00000001 // SSI Module 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCI2C_D9 0x00000200 // I2C Module 9 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCI2C_D8 0x00000100 // I2C Module 8 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCI2C_D7 0x00000080 // I2C Module 7 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCI2C_D6 0x00000040 // I2C Module 6 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCI2C_D5 0x00000020 // I2C Module 5 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCI2C_D4 0x00000010 // I2C Module 4 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCI2C_D3 0x00000008 // I2C Module 3 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCI2C_D2 0x00000004 // I2C Module 2 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCI2C_D1 0x00000002 // I2C Module 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCI2C_D0 0x00000001 // I2C Module 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCUSB_D0 0x00000001 // USB Module Deep-Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCEPHY
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCEPHY_D0 0x00000001 // PHY Module Deep-Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCCAN_D1 0x00000002 // CAN Module 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCCAN_D0 0x00000001 // CAN Module 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCADC register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCADC_D1 0x00000002 // ADC Module 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCADC_D0 0x00000001 // ADC Module 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCACMP
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCACMP_D0 0x00000001 // Analog Comparator Module 0
+ // Deep-Sleep Mode Clock Gating
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCPWM_D1 0x00000002 // PWM Module 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCPWM_D0 0x00000001 // PWM Module 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCQEI_D1 0x00000002 // QEI Module 1 Deep-Sleep Mode
+ // Clock Gating Control
+#define SYSCTL_DCGCQEI_D0 0x00000001 // QEI Module 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCEEPROM_D0 0x00000001 // EEPROM Module Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCWTIMER_D5 0x00000020 // 32/64-Bit Wide General-Purpose
+ // Timer 5 Deep-Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_DCGCWTIMER_D4 0x00000010 // 32/64-Bit Wide General-Purpose
+ // Timer 4 Deep-Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_DCGCWTIMER_D3 0x00000008 // 32/64-Bit Wide General-Purpose
+ // Timer 3 Deep-Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_DCGCWTIMER_D2 0x00000004 // 32/64-Bit Wide General-Purpose
+ // Timer 2 Deep-Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_DCGCWTIMER_D1 0x00000002 // 32/64-Bit Wide General-Purpose
+ // Timer 1 Deep-Sleep Mode Clock
+ // Gating Control
+#define SYSCTL_DCGCWTIMER_D0 0x00000001 // 32/64-Bit Wide General-Purpose
+ // Timer 0 Deep-Sleep Mode Clock
+ // Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCCCM register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCCCM_D0 0x00000001 // CRC and Cryptographic Modules
+ // Deep-Sleep Mode Clock Gating
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCLCD register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCLCD_D0 0x00000001 // LCD Controller Module 0
+ // Deep-Sleep Mode Clock Gating
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCOWIRE
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCOWIRE_D0 0x00000001 // 1-Wire Module 0 Deep-Sleep Mode
+ // Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_DCGCEMAC
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DCGCEMAC_D0 0x00000001 // Ethernet MAC Module 0 Deep-Sleep
+ // Mode Clock Gating Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCWD register.
+//
+//*****************************************************************************
+#define SYSCTL_PCWD_P1 0x00000002 // Watchdog Timer 1 Power Control
+#define SYSCTL_PCWD_P0 0x00000001 // Watchdog Timer 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCTIMER register.
+//
+//*****************************************************************************
+#define SYSCTL_PCTIMER_P7 0x00000080 // General-Purpose Timer 7 Power
+ // Control
+#define SYSCTL_PCTIMER_P6 0x00000040 // General-Purpose Timer 6 Power
+ // Control
+#define SYSCTL_PCTIMER_P5 0x00000020 // General-Purpose Timer 5 Power
+ // Control
+#define SYSCTL_PCTIMER_P4 0x00000010 // General-Purpose Timer 4 Power
+ // Control
+#define SYSCTL_PCTIMER_P3 0x00000008 // General-Purpose Timer 3 Power
+ // Control
+#define SYSCTL_PCTIMER_P2 0x00000004 // General-Purpose Timer 2 Power
+ // Control
+#define SYSCTL_PCTIMER_P1 0x00000002 // General-Purpose Timer 1 Power
+ // Control
+#define SYSCTL_PCTIMER_P0 0x00000001 // General-Purpose Timer 0 Power
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCGPIO register.
+//
+//*****************************************************************************
+#define SYSCTL_PCGPIO_P17 0x00020000 // GPIO Port T Power Control
+#define SYSCTL_PCGPIO_P16 0x00010000 // GPIO Port S Power Control
+#define SYSCTL_PCGPIO_P15 0x00008000 // GPIO Port R Power Control
+#define SYSCTL_PCGPIO_P14 0x00004000 // GPIO Port Q Power Control
+#define SYSCTL_PCGPIO_P13 0x00002000 // GPIO Port P Power Control
+#define SYSCTL_PCGPIO_P12 0x00001000 // GPIO Port N Power Control
+#define SYSCTL_PCGPIO_P11 0x00000800 // GPIO Port M Power Control
+#define SYSCTL_PCGPIO_P10 0x00000400 // GPIO Port L Power Control
+#define SYSCTL_PCGPIO_P9 0x00000200 // GPIO Port K Power Control
+#define SYSCTL_PCGPIO_P8 0x00000100 // GPIO Port J Power Control
+#define SYSCTL_PCGPIO_P7 0x00000080 // GPIO Port H Power Control
+#define SYSCTL_PCGPIO_P6 0x00000040 // GPIO Port G Power Control
+#define SYSCTL_PCGPIO_P5 0x00000020 // GPIO Port F Power Control
+#define SYSCTL_PCGPIO_P4 0x00000010 // GPIO Port E Power Control
+#define SYSCTL_PCGPIO_P3 0x00000008 // GPIO Port D Power Control
+#define SYSCTL_PCGPIO_P2 0x00000004 // GPIO Port C Power Control
+#define SYSCTL_PCGPIO_P1 0x00000002 // GPIO Port B Power Control
+#define SYSCTL_PCGPIO_P0 0x00000001 // GPIO Port A Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_PCDMA_P0 0x00000001 // uDMA Module Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCEPI register.
+//
+//*****************************************************************************
+#define SYSCTL_PCEPI_P0 0x00000001 // EPI Module Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_PCHIB_P0 0x00000001 // Hibernation Module Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCUART register.
+//
+//*****************************************************************************
+#define SYSCTL_PCUART_P7 0x00000080 // UART Module 7 Power Control
+#define SYSCTL_PCUART_P6 0x00000040 // UART Module 6 Power Control
+#define SYSCTL_PCUART_P5 0x00000020 // UART Module 5 Power Control
+#define SYSCTL_PCUART_P4 0x00000010 // UART Module 4 Power Control
+#define SYSCTL_PCUART_P3 0x00000008 // UART Module 3 Power Control
+#define SYSCTL_PCUART_P2 0x00000004 // UART Module 2 Power Control
+#define SYSCTL_PCUART_P1 0x00000002 // UART Module 1 Power Control
+#define SYSCTL_PCUART_P0 0x00000001 // UART Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_PCSSI_P3 0x00000008 // SSI Module 3 Power Control
+#define SYSCTL_PCSSI_P2 0x00000004 // SSI Module 2 Power Control
+#define SYSCTL_PCSSI_P1 0x00000002 // SSI Module 1 Power Control
+#define SYSCTL_PCSSI_P0 0x00000001 // SSI Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_PCI2C_P9 0x00000200 // I2C Module 9 Power Control
+#define SYSCTL_PCI2C_P8 0x00000100 // I2C Module 8 Power Control
+#define SYSCTL_PCI2C_P7 0x00000080 // I2C Module 7 Power Control
+#define SYSCTL_PCI2C_P6 0x00000040 // I2C Module 6 Power Control
+#define SYSCTL_PCI2C_P5 0x00000020 // I2C Module 5 Power Control
+#define SYSCTL_PCI2C_P4 0x00000010 // I2C Module 4 Power Control
+#define SYSCTL_PCI2C_P3 0x00000008 // I2C Module 3 Power Control
+#define SYSCTL_PCI2C_P2 0x00000004 // I2C Module 2 Power Control
+#define SYSCTL_PCI2C_P1 0x00000002 // I2C Module 1 Power Control
+#define SYSCTL_PCI2C_P0 0x00000001 // I2C Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_PCUSB_P0 0x00000001 // USB Module Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCEPHY register.
+//
+//*****************************************************************************
+#define SYSCTL_PCEPHY_P0 0x00000001 // Ethernet PHY Module Power
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_PCCAN_P1 0x00000002 // CAN Module 1 Power Control
+#define SYSCTL_PCCAN_P0 0x00000001 // CAN Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCADC register.
+//
+//*****************************************************************************
+#define SYSCTL_PCADC_P1 0x00000002 // ADC Module 1 Power Control
+#define SYSCTL_PCADC_P0 0x00000001 // ADC Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCACMP register.
+//
+//*****************************************************************************
+#define SYSCTL_PCACMP_P0 0x00000001 // Analog Comparator Module 0 Power
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_PCPWM_P0 0x00000001 // PWM Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_PCQEI_P0 0x00000001 // QEI Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCEEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PCEEPROM_P0 0x00000001 // EEPROM Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCCCM register.
+//
+//*****************************************************************************
+#define SYSCTL_PCCCM_P0 0x00000001 // CRC and Cryptographic Modules
+ // Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCLCD register.
+//
+//*****************************************************************************
+#define SYSCTL_PCLCD_P0 0x00000001 // LCD Controller Module 0 Power
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCOWIRE register.
+//
+//*****************************************************************************
+#define SYSCTL_PCOWIRE_P0 0x00000001 // 1-Wire Module 0 Power Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PCEMAC register.
+//
+//*****************************************************************************
+#define SYSCTL_PCEMAC_P0 0x00000001 // Ethernet MAC Module 0 Power
+ // Control
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRWD register.
+//
+//*****************************************************************************
+#define SYSCTL_PRWD_R1 0x00000002 // Watchdog Timer 1 Peripheral
+ // Ready
+#define SYSCTL_PRWD_R0 0x00000001 // Watchdog Timer 0 Peripheral
+ // Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRTIMER register.
+//
+//*****************************************************************************
+#define SYSCTL_PRTIMER_R7 0x00000080 // 16/32-Bit General-Purpose Timer
+ // 7 Peripheral Ready
+#define SYSCTL_PRTIMER_R6 0x00000040 // 16/32-Bit General-Purpose Timer
+ // 6 Peripheral Ready
+#define SYSCTL_PRTIMER_R5 0x00000020 // 16/32-Bit General-Purpose Timer
+ // 5 Peripheral Ready
+#define SYSCTL_PRTIMER_R4 0x00000010 // 16/32-Bit General-Purpose Timer
+ // 4 Peripheral Ready
+#define SYSCTL_PRTIMER_R3 0x00000008 // 16/32-Bit General-Purpose Timer
+ // 3 Peripheral Ready
+#define SYSCTL_PRTIMER_R2 0x00000004 // 16/32-Bit General-Purpose Timer
+ // 2 Peripheral Ready
+#define SYSCTL_PRTIMER_R1 0x00000002 // 16/32-Bit General-Purpose Timer
+ // 1 Peripheral Ready
+#define SYSCTL_PRTIMER_R0 0x00000001 // 16/32-Bit General-Purpose Timer
+ // 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRGPIO register.
+//
+//*****************************************************************************
+#define SYSCTL_PRGPIO_R17 0x00020000 // GPIO Port T Peripheral Ready
+#define SYSCTL_PRGPIO_R16 0x00010000 // GPIO Port S Peripheral Ready
+#define SYSCTL_PRGPIO_R15 0x00008000 // GPIO Port R Peripheral Ready
+#define SYSCTL_PRGPIO_R14 0x00004000 // GPIO Port Q Peripheral Ready
+#define SYSCTL_PRGPIO_R13 0x00002000 // GPIO Port P Peripheral Ready
+#define SYSCTL_PRGPIO_R12 0x00001000 // GPIO Port N Peripheral Ready
+#define SYSCTL_PRGPIO_R11 0x00000800 // GPIO Port M Peripheral Ready
+#define SYSCTL_PRGPIO_R10 0x00000400 // GPIO Port L Peripheral Ready
+#define SYSCTL_PRGPIO_R9 0x00000200 // GPIO Port K Peripheral Ready
+#define SYSCTL_PRGPIO_R8 0x00000100 // GPIO Port J Peripheral Ready
+#define SYSCTL_PRGPIO_R7 0x00000080 // GPIO Port H Peripheral Ready
+#define SYSCTL_PRGPIO_R6 0x00000040 // GPIO Port G Peripheral Ready
+#define SYSCTL_PRGPIO_R5 0x00000020 // GPIO Port F Peripheral Ready
+#define SYSCTL_PRGPIO_R4 0x00000010 // GPIO Port E Peripheral Ready
+#define SYSCTL_PRGPIO_R3 0x00000008 // GPIO Port D Peripheral Ready
+#define SYSCTL_PRGPIO_R2 0x00000004 // GPIO Port C Peripheral Ready
+#define SYSCTL_PRGPIO_R1 0x00000002 // GPIO Port B Peripheral Ready
+#define SYSCTL_PRGPIO_R0 0x00000001 // GPIO Port A Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRDMA register.
+//
+//*****************************************************************************
+#define SYSCTL_PRDMA_R0 0x00000001 // uDMA Module Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PREPI register.
+//
+//*****************************************************************************
+#define SYSCTL_PREPI_R0 0x00000001 // EPI Module Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRHIB register.
+//
+//*****************************************************************************
+#define SYSCTL_PRHIB_R0 0x00000001 // Hibernation Module Peripheral
+ // Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRUART register.
+//
+//*****************************************************************************
+#define SYSCTL_PRUART_R7 0x00000080 // UART Module 7 Peripheral Ready
+#define SYSCTL_PRUART_R6 0x00000040 // UART Module 6 Peripheral Ready
+#define SYSCTL_PRUART_R5 0x00000020 // UART Module 5 Peripheral Ready
+#define SYSCTL_PRUART_R4 0x00000010 // UART Module 4 Peripheral Ready
+#define SYSCTL_PRUART_R3 0x00000008 // UART Module 3 Peripheral Ready
+#define SYSCTL_PRUART_R2 0x00000004 // UART Module 2 Peripheral Ready
+#define SYSCTL_PRUART_R1 0x00000002 // UART Module 1 Peripheral Ready
+#define SYSCTL_PRUART_R0 0x00000001 // UART Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRSSI register.
+//
+//*****************************************************************************
+#define SYSCTL_PRSSI_R3 0x00000008 // SSI Module 3 Peripheral Ready
+#define SYSCTL_PRSSI_R2 0x00000004 // SSI Module 2 Peripheral Ready
+#define SYSCTL_PRSSI_R1 0x00000002 // SSI Module 1 Peripheral Ready
+#define SYSCTL_PRSSI_R0 0x00000001 // SSI Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRI2C register.
+//
+//*****************************************************************************
+#define SYSCTL_PRI2C_R9 0x00000200 // I2C Module 9 Peripheral Ready
+#define SYSCTL_PRI2C_R8 0x00000100 // I2C Module 8 Peripheral Ready
+#define SYSCTL_PRI2C_R7 0x00000080 // I2C Module 7 Peripheral Ready
+#define SYSCTL_PRI2C_R6 0x00000040 // I2C Module 6 Peripheral Ready
+#define SYSCTL_PRI2C_R5 0x00000020 // I2C Module 5 Peripheral Ready
+#define SYSCTL_PRI2C_R4 0x00000010 // I2C Module 4 Peripheral Ready
+#define SYSCTL_PRI2C_R3 0x00000008 // I2C Module 3 Peripheral Ready
+#define SYSCTL_PRI2C_R2 0x00000004 // I2C Module 2 Peripheral Ready
+#define SYSCTL_PRI2C_R1 0x00000002 // I2C Module 1 Peripheral Ready
+#define SYSCTL_PRI2C_R0 0x00000001 // I2C Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRUSB register.
+//
+//*****************************************************************************
+#define SYSCTL_PRUSB_R0 0x00000001 // USB Module Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PREPHY register.
+//
+//*****************************************************************************
+#define SYSCTL_PREPHY_R0 0x00000001 // Ethernet PHY Module Peripheral
+ // Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRCAN register.
+//
+//*****************************************************************************
+#define SYSCTL_PRCAN_R1 0x00000002 // CAN Module 1 Peripheral Ready
+#define SYSCTL_PRCAN_R0 0x00000001 // CAN Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRADC register.
+//
+//*****************************************************************************
+#define SYSCTL_PRADC_R1 0x00000002 // ADC Module 1 Peripheral Ready
+#define SYSCTL_PRADC_R0 0x00000001 // ADC Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRACMP register.
+//
+//*****************************************************************************
+#define SYSCTL_PRACMP_R0 0x00000001 // Analog Comparator Module 0
+ // Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRPWM register.
+//
+//*****************************************************************************
+#define SYSCTL_PRPWM_R1 0x00000002 // PWM Module 1 Peripheral Ready
+#define SYSCTL_PRPWM_R0 0x00000001 // PWM Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRQEI register.
+//
+//*****************************************************************************
+#define SYSCTL_PRQEI_R1 0x00000002 // QEI Module 1 Peripheral Ready
+#define SYSCTL_PRQEI_R0 0x00000001 // QEI Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PREEPROM
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PREEPROM_R0 0x00000001 // EEPROM Module Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRWTIMER
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PRWTIMER_R5 0x00000020 // 32/64-Bit Wide General-Purpose
+ // Timer 5 Peripheral Ready
+#define SYSCTL_PRWTIMER_R4 0x00000010 // 32/64-Bit Wide General-Purpose
+ // Timer 4 Peripheral Ready
+#define SYSCTL_PRWTIMER_R3 0x00000008 // 32/64-Bit Wide General-Purpose
+ // Timer 3 Peripheral Ready
+#define SYSCTL_PRWTIMER_R2 0x00000004 // 32/64-Bit Wide General-Purpose
+ // Timer 2 Peripheral Ready
+#define SYSCTL_PRWTIMER_R1 0x00000002 // 32/64-Bit Wide General-Purpose
+ // Timer 1 Peripheral Ready
+#define SYSCTL_PRWTIMER_R0 0x00000001 // 32/64-Bit Wide General-Purpose
+ // Timer 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRCCM register.
+//
+//*****************************************************************************
+#define SYSCTL_PRCCM_R0 0x00000001 // CRC and Cryptographic Modules
+ // Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PRLCD register.
+//
+//*****************************************************************************
+#define SYSCTL_PRLCD_R0 0x00000001 // LCD Controller Module 0
+ // Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PROWIRE register.
+//
+//*****************************************************************************
+#define SYSCTL_PROWIRE_R0 0x00000001 // 1-Wire Module 0 Peripheral Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_PREMAC register.
+//
+//*****************************************************************************
+#define SYSCTL_PREMAC_R0 0x00000001 // Ethernet MAC Module 0 Peripheral
+ // Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_UNIQUEID0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_UNIQUEID0_ID_M 0xFFFFFFFF // Unique ID
+#define SYSCTL_UNIQUEID0_ID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_UNIQUEID1
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_UNIQUEID1_ID_M 0xFFFFFFFF // Unique ID
+#define SYSCTL_UNIQUEID1_ID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_UNIQUEID2
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_UNIQUEID2_ID_M 0xFFFFFFFF // Unique ID
+#define SYSCTL_UNIQUEID2_ID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_UNIQUEID3
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_UNIQUEID3_ID_M 0xFFFFFFFF // Unique ID
+#define SYSCTL_UNIQUEID3_ID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSCTL_CCMCGREQ
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_CCMCGREQ_DESCFG 0x00000004 // DES Clock Gating Request
+#define SYSCTL_CCMCGREQ_AESCFG 0x00000002 // AES Clock Gating Request
+#define SYSCTL_CCMCGREQ_SHACFG 0x00000001 // SHA/MD5 Clock Gating Request
+
+//*****************************************************************************
+//
+// The following definitions are deprecated.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_DID0
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_DID0_CLASS_BLIZZARD \
+ 0x00050000 // Tiva(TM) C Series TM4C123-class
+ // microcontrollers
+#define SYSCTL_DID0_CLASS_SNOWFLAKE \
+ 0x000A0000 // Tiva(TM) C Series TM4C129-class
+ // microcontrollers
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_RESC
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_RESC_HIB 0x00000040 // HIB Reset
+
+//*****************************************************************************
+//
+// The following are deprecated defines for the bit fields in the SYSCTL_PWRTC
+// register.
+//
+//*****************************************************************************
+#define SYSCTL_PWRTC_VDDA_UBOR0 0x00000010 // VDDA Under BOR0 Status
+#define SYSCTL_PWRTC_VDD_UBOR0 0x00000001 // VDD Under BOR0 Status
+
+#endif
+
+#endif // __HW_SYSCTL_H__
diff --git a/os/common/ext/TivaWare/inc/hw_sysexc.h b/os/common/ext/TivaWare/inc/hw_sysexc.h
new file mode 100644
index 0000000..a6eec99
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_sysexc.h
@@ -0,0 +1,132 @@
+//*****************************************************************************
+//
+// hw_sysexc.h - Macros used when accessing the system exception module.
+//
+// Copyright (c) 2011-2016 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_SYSEXC_H__
+#define __HW_SYSEXC_H__
+
+//*****************************************************************************
+//
+// The following are defines for the System Exception Module register
+// addresses.
+//
+//*****************************************************************************
+#define SYSEXC_RIS 0x400F9000 // System Exception Raw Interrupt
+ // Status
+#define SYSEXC_IM 0x400F9004 // System Exception Interrupt Mask
+#define SYSEXC_MIS 0x400F9008 // System Exception Masked
+ // Interrupt Status
+#define SYSEXC_IC 0x400F900C // System Exception Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_RIS register.
+//
+//*****************************************************************************
+#define SYSEXC_RIS_FPIXCRIS 0x00000020 // Floating-Point Inexact Exception
+ // Raw Interrupt Status
+#define SYSEXC_RIS_FPOFCRIS 0x00000010 // Floating-Point Overflow
+ // Exception Raw Interrupt Status
+#define SYSEXC_RIS_FPUFCRIS 0x00000008 // Floating-Point Underflow
+ // Exception Raw Interrupt Status
+#define SYSEXC_RIS_FPIOCRIS 0x00000004 // Floating-Point Invalid Operation
+ // Raw Interrupt Status
+#define SYSEXC_RIS_FPDZCRIS 0x00000002 // Floating-Point Divide By 0
+ // Exception Raw Interrupt Status
+#define SYSEXC_RIS_FPIDCRIS 0x00000001 // Floating-Point Input Denormal
+ // Exception Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_IM register.
+//
+//*****************************************************************************
+#define SYSEXC_IM_FPIXCIM 0x00000020 // Floating-Point Inexact Exception
+ // Interrupt Mask
+#define SYSEXC_IM_FPOFCIM 0x00000010 // Floating-Point Overflow
+ // Exception Interrupt Mask
+#define SYSEXC_IM_FPUFCIM 0x00000008 // Floating-Point Underflow
+ // Exception Interrupt Mask
+#define SYSEXC_IM_FPIOCIM 0x00000004 // Floating-Point Invalid Operation
+ // Interrupt Mask
+#define SYSEXC_IM_FPDZCIM 0x00000002 // Floating-Point Divide By 0
+ // Exception Interrupt Mask
+#define SYSEXC_IM_FPIDCIM 0x00000001 // Floating-Point Input Denormal
+ // Exception Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_MIS register.
+//
+//*****************************************************************************
+#define SYSEXC_MIS_FPIXCMIS 0x00000020 // Floating-Point Inexact Exception
+ // Masked Interrupt Status
+#define SYSEXC_MIS_FPOFCMIS 0x00000010 // Floating-Point Overflow
+ // Exception Masked Interrupt
+ // Status
+#define SYSEXC_MIS_FPUFCMIS 0x00000008 // Floating-Point Underflow
+ // Exception Masked Interrupt
+ // Status
+#define SYSEXC_MIS_FPIOCMIS 0x00000004 // Floating-Point Invalid Operation
+ // Masked Interrupt Status
+#define SYSEXC_MIS_FPDZCMIS 0x00000002 // Floating-Point Divide By 0
+ // Exception Masked Interrupt
+ // Status
+#define SYSEXC_MIS_FPIDCMIS 0x00000001 // Floating-Point Input Denormal
+ // Exception Masked Interrupt
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the SYSEXC_IC register.
+//
+//*****************************************************************************
+#define SYSEXC_IC_FPIXCIC 0x00000020 // Floating-Point Inexact Exception
+ // Interrupt Clear
+#define SYSEXC_IC_FPOFCIC 0x00000010 // Floating-Point Overflow
+ // Exception Interrupt Clear
+#define SYSEXC_IC_FPUFCIC 0x00000008 // Floating-Point Underflow
+ // Exception Interrupt Clear
+#define SYSEXC_IC_FPIOCIC 0x00000004 // Floating-Point Invalid Operation
+ // Interrupt Clear
+#define SYSEXC_IC_FPDZCIC 0x00000002 // Floating-Point Divide By 0
+ // Exception Interrupt Clear
+#define SYSEXC_IC_FPIDCIC 0x00000001 // Floating-Point Input Denormal
+ // Exception Interrupt Clear
+
+#endif // __HW_SYSEXC_H__
diff --git a/os/common/ext/TivaWare/inc/hw_timer.h b/os/common/ext/TivaWare/inc/hw_timer.h
new file mode 100644
index 0000000..25a7ed9
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_timer.h
@@ -0,0 +1,700 @@
+//*****************************************************************************
+//
+// hw_timer.h - Defines and macros used when accessing the timer.
+//
+// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_TIMER_H__
+#define __HW_TIMER_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Timer register offsets.
+//
+//*****************************************************************************
+#define TIMER_O_CFG 0x00000000 // GPTM Configuration
+#define TIMER_O_TAMR 0x00000004 // GPTM Timer A Mode
+#define TIMER_O_TBMR 0x00000008 // GPTM Timer B Mode
+#define TIMER_O_CTL 0x0000000C // GPTM Control
+#define TIMER_O_SYNC 0x00000010 // GPTM Synchronize
+#define TIMER_O_IMR 0x00000018 // GPTM Interrupt Mask
+#define TIMER_O_RIS 0x0000001C // GPTM Raw Interrupt Status
+#define TIMER_O_MIS 0x00000020 // GPTM Masked Interrupt Status
+#define TIMER_O_ICR 0x00000024 // GPTM Interrupt Clear
+#define TIMER_O_TAILR 0x00000028 // GPTM Timer A Interval Load
+#define TIMER_O_TBILR 0x0000002C // GPTM Timer B Interval Load
+#define TIMER_O_TAMATCHR 0x00000030 // GPTM Timer A Match
+#define TIMER_O_TBMATCHR 0x00000034 // GPTM Timer B Match
+#define TIMER_O_TAPR 0x00000038 // GPTM Timer A Prescale
+#define TIMER_O_TBPR 0x0000003C // GPTM Timer B Prescale
+#define TIMER_O_TAPMR 0x00000040 // GPTM TimerA Prescale Match
+#define TIMER_O_TBPMR 0x00000044 // GPTM TimerB Prescale Match
+#define TIMER_O_TAR 0x00000048 // GPTM Timer A
+#define TIMER_O_TBR 0x0000004C // GPTM Timer B
+#define TIMER_O_TAV 0x00000050 // GPTM Timer A Value
+#define TIMER_O_TBV 0x00000054 // GPTM Timer B Value
+#define TIMER_O_RTCPD 0x00000058 // GPTM RTC Predivide
+#define TIMER_O_TAPS 0x0000005C // GPTM Timer A Prescale Snapshot
+#define TIMER_O_TBPS 0x00000060 // GPTM Timer B Prescale Snapshot
+#define TIMER_O_TAPV 0x00000064 // GPTM Timer A Prescale Value
+#define TIMER_O_TBPV 0x00000068 // GPTM Timer B Prescale Value
+#define TIMER_O_DMAEV 0x0000006C // GPTM DMA Event
+#define TIMER_O_ADCEV 0x00000070 // GPTM ADC Event
+#define TIMER_O_PP 0x00000FC0 // GPTM Peripheral Properties
+#define TIMER_O_CC 0x00000FC8 // GPTM Clock Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CFG register.
+//
+//*****************************************************************************
+#define TIMER_CFG_M 0x00000007 // GPTM Configuration
+#define TIMER_CFG_32_BIT_TIMER 0x00000000 // For a 16/32-bit timer, this
+ // value selects the 32-bit timer
+ // configuration
+#define TIMER_CFG_32_BIT_RTC 0x00000001 // For a 16/32-bit timer, this
+ // value selects the 32-bit
+ // real-time clock (RTC) counter
+ // configuration
+#define TIMER_CFG_16_BIT 0x00000004 // For a 16/32-bit timer, this
+ // value selects the 16-bit timer
+ // configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMR register.
+//
+//*****************************************************************************
+#define TIMER_TAMR_TCACT_M 0x0000E000 // Timer Compare Action Select
+#define TIMER_TAMR_TCACT_NONE 0x00000000 // Disable compare operations
+#define TIMER_TAMR_TCACT_TOGGLE 0x00002000 // Toggle State on Time-Out
+#define TIMER_TAMR_TCACT_CLRTO 0x00004000 // Clear CCP on Time-Out
+#define TIMER_TAMR_TCACT_SETTO 0x00006000 // Set CCP on Time-Out
+#define TIMER_TAMR_TCACT_SETTOGTO \
+ 0x00008000 // Set CCP immediately and toggle
+ // on Time-Out
+#define TIMER_TAMR_TCACT_CLRTOGTO \
+ 0x0000A000 // Clear CCP immediately and toggle
+ // on Time-Out
+#define TIMER_TAMR_TCACT_SETCLRTO \
+ 0x0000C000 // Set CCP immediately and clear on
+ // Time-Out
+#define TIMER_TAMR_TCACT_CLRSETTO \
+ 0x0000E000 // Clear CCP immediately and set on
+ // Time-Out
+#define TIMER_TAMR_TACINTD 0x00001000 // One-shot/Periodic Interrupt
+ // Disable
+#define TIMER_TAMR_TAPLO 0x00000800 // GPTM Timer A PWM Legacy
+ // Operation
+#define TIMER_TAMR_TAMRSU 0x00000400 // GPTM Timer A Match Register
+ // Update
+#define TIMER_TAMR_TAPWMIE 0x00000200 // GPTM Timer A PWM Interrupt
+ // Enable
+#define TIMER_TAMR_TAILD 0x00000100 // GPTM Timer A Interval Load Write
+#define TIMER_TAMR_TASNAPS 0x00000080 // GPTM Timer A Snap-Shot Mode
+#define TIMER_TAMR_TAWOT 0x00000040 // GPTM Timer A Wait-on-Trigger
+#define TIMER_TAMR_TAMIE 0x00000020 // GPTM Timer A Match Interrupt
+ // Enable
+#define TIMER_TAMR_TACDIR 0x00000010 // GPTM Timer A Count Direction
+#define TIMER_TAMR_TAAMS 0x00000008 // GPTM Timer A Alternate Mode
+ // Select
+#define TIMER_TAMR_TACMR 0x00000004 // GPTM Timer A Capture Mode
+#define TIMER_TAMR_TAMR_M 0x00000003 // GPTM Timer A Mode
+#define TIMER_TAMR_TAMR_1_SHOT 0x00000001 // One-Shot Timer mode
+#define TIMER_TAMR_TAMR_PERIOD 0x00000002 // Periodic Timer mode
+#define TIMER_TAMR_TAMR_CAP 0x00000003 // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMR register.
+//
+//*****************************************************************************
+#define TIMER_TBMR_TCACT_M 0x0000E000 // Timer Compare Action Select
+#define TIMER_TBMR_TCACT_NONE 0x00000000 // Disable compare operations
+#define TIMER_TBMR_TCACT_TOGGLE 0x00002000 // Toggle State on Time-Out
+#define TIMER_TBMR_TCACT_CLRTO 0x00004000 // Clear CCP on Time-Out
+#define TIMER_TBMR_TCACT_SETTO 0x00006000 // Set CCP on Time-Out
+#define TIMER_TBMR_TCACT_SETTOGTO \
+ 0x00008000 // Set CCP immediately and toggle
+ // on Time-Out
+#define TIMER_TBMR_TCACT_CLRTOGTO \
+ 0x0000A000 // Clear CCP immediately and toggle
+ // on Time-Out
+#define TIMER_TBMR_TCACT_SETCLRTO \
+ 0x0000C000 // Set CCP immediately and clear on
+ // Time-Out
+#define TIMER_TBMR_TCACT_CLRSETTO \
+ 0x0000E000 // Clear CCP immediately and set on
+ // Time-Out
+#define TIMER_TBMR_TBCINTD 0x00001000 // One-Shot/Periodic Interrupt
+ // Disable
+#define TIMER_TBMR_TBPLO 0x00000800 // GPTM Timer B PWM Legacy
+ // Operation
+#define TIMER_TBMR_TBMRSU 0x00000400 // GPTM Timer B Match Register
+ // Update
+#define TIMER_TBMR_TBPWMIE 0x00000200 // GPTM Timer B PWM Interrupt
+ // Enable
+#define TIMER_TBMR_TBILD 0x00000100 // GPTM Timer B Interval Load Write
+#define TIMER_TBMR_TBSNAPS 0x00000080 // GPTM Timer B Snap-Shot Mode
+#define TIMER_TBMR_TBWOT 0x00000040 // GPTM Timer B Wait-on-Trigger
+#define TIMER_TBMR_TBMIE 0x00000020 // GPTM Timer B Match Interrupt
+ // Enable
+#define TIMER_TBMR_TBCDIR 0x00000010 // GPTM Timer B Count Direction
+#define TIMER_TBMR_TBAMS 0x00000008 // GPTM Timer B Alternate Mode
+ // Select
+#define TIMER_TBMR_TBCMR 0x00000004 // GPTM Timer B Capture Mode
+#define TIMER_TBMR_TBMR_M 0x00000003 // GPTM Timer B Mode
+#define TIMER_TBMR_TBMR_1_SHOT 0x00000001 // One-Shot Timer mode
+#define TIMER_TBMR_TBMR_PERIOD 0x00000002 // Periodic Timer mode
+#define TIMER_TBMR_TBMR_CAP 0x00000003 // Capture mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CTL register.
+//
+//*****************************************************************************
+#define TIMER_CTL_TBPWML 0x00004000 // GPTM Timer B PWM Output Level
+#define TIMER_CTL_TBOTE 0x00002000 // GPTM Timer B Output Trigger
+ // Enable
+#define TIMER_CTL_TBEVENT_M 0x00000C00 // GPTM Timer B Event Mode
+#define TIMER_CTL_TBEVENT_POS 0x00000000 // Positive edge
+#define TIMER_CTL_TBEVENT_NEG 0x00000400 // Negative edge
+#define TIMER_CTL_TBEVENT_BOTH 0x00000C00 // Both edges
+#define TIMER_CTL_TBSTALL 0x00000200 // GPTM Timer B Stall Enable
+#define TIMER_CTL_TBEN 0x00000100 // GPTM Timer B Enable
+#define TIMER_CTL_TAPWML 0x00000040 // GPTM Timer A PWM Output Level
+#define TIMER_CTL_TAOTE 0x00000020 // GPTM Timer A Output Trigger
+ // Enable
+#define TIMER_CTL_RTCEN 0x00000010 // GPTM RTC Stall Enable
+#define TIMER_CTL_TAEVENT_M 0x0000000C // GPTM Timer A Event Mode
+#define TIMER_CTL_TAEVENT_POS 0x00000000 // Positive edge
+#define TIMER_CTL_TAEVENT_NEG 0x00000004 // Negative edge
+#define TIMER_CTL_TAEVENT_BOTH 0x0000000C // Both edges
+#define TIMER_CTL_TASTALL 0x00000002 // GPTM Timer A Stall Enable
+#define TIMER_CTL_TAEN 0x00000001 // GPTM Timer A Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_SYNC register.
+//
+//*****************************************************************************
+#define TIMER_SYNC_SYNCWT5_M 0x00C00000 // Synchronize GPTM 32/64-Bit Timer
+ // 5
+#define TIMER_SYNC_SYNCWT5_NONE 0x00000000 // GPTM 32/64-Bit Timer 5 is not
+ // affected
+#define TIMER_SYNC_SYNCWT5_TA 0x00400000 // A timeout event for Timer A of
+ // GPTM 32/64-Bit Timer 5 is
+ // triggered
+#define TIMER_SYNC_SYNCWT5_TB 0x00800000 // A timeout event for Timer B of
+ // GPTM 32/64-Bit Timer 5 is
+ // triggered
+#define TIMER_SYNC_SYNCWT5_TATB 0x00C00000 // A timeout event for both Timer A
+ // and Timer B of GPTM 32/64-Bit
+ // Timer 5 is triggered
+#define TIMER_SYNC_SYNCWT4_M 0x00300000 // Synchronize GPTM 32/64-Bit Timer
+ // 4
+#define TIMER_SYNC_SYNCWT4_NONE 0x00000000 // GPTM 32/64-Bit Timer 4 is not
+ // affected
+#define TIMER_SYNC_SYNCWT4_TA 0x00100000 // A timeout event for Timer A of
+ // GPTM 32/64-Bit Timer 4 is
+ // triggered
+#define TIMER_SYNC_SYNCWT4_TB 0x00200000 // A timeout event for Timer B of
+ // GPTM 32/64-Bit Timer 4 is
+ // triggered
+#define TIMER_SYNC_SYNCWT4_TATB 0x00300000 // A timeout event for both Timer A
+ // and Timer B of GPTM 32/64-Bit
+ // Timer 4 is triggered
+#define TIMER_SYNC_SYNCWT3_M 0x000C0000 // Synchronize GPTM 32/64-Bit Timer
+ // 3
+#define TIMER_SYNC_SYNCWT3_NONE 0x00000000 // GPTM 32/64-Bit Timer 3 is not
+ // affected
+#define TIMER_SYNC_SYNCWT3_TA 0x00040000 // A timeout event for Timer A of
+ // GPTM 32/64-Bit Timer 3 is
+ // triggered
+#define TIMER_SYNC_SYNCWT3_TB 0x00080000 // A timeout event for Timer B of
+ // GPTM 32/64-Bit Timer 3 is
+ // triggered
+#define TIMER_SYNC_SYNCWT3_TATB 0x000C0000 // A timeout event for both Timer A
+ // and Timer B of GPTM 32/64-Bit
+ // Timer 3 is triggered
+#define TIMER_SYNC_SYNCWT2_M 0x00030000 // Synchronize GPTM 32/64-Bit Timer
+ // 2
+#define TIMER_SYNC_SYNCWT2_NONE 0x00000000 // GPTM 32/64-Bit Timer 2 is not
+ // affected
+#define TIMER_SYNC_SYNCWT2_TA 0x00010000 // A timeout event for Timer A of
+ // GPTM 32/64-Bit Timer 2 is
+ // triggered
+#define TIMER_SYNC_SYNCWT2_TB 0x00020000 // A timeout event for Timer B of
+ // GPTM 32/64-Bit Timer 2 is
+ // triggered
+#define TIMER_SYNC_SYNCWT2_TATB 0x00030000 // A timeout event for both Timer A
+ // and Timer B of GPTM 32/64-Bit
+ // Timer 2 is triggered
+#define TIMER_SYNC_SYNCT7_M 0x0000C000 // Synchronize GPTM Timer 7
+#define TIMER_SYNC_SYNCT7_NONE 0x00000000 // GPT7 is not affected
+#define TIMER_SYNC_SYNCT7_TA 0x00004000 // A timeout event for Timer A of
+ // GPTM7 is triggered
+#define TIMER_SYNC_SYNCT7_TB 0x00008000 // A timeout event for Timer B of
+ // GPTM7 is triggered
+#define TIMER_SYNC_SYNCT7_TATB 0x0000C000 // A timeout event for both Timer A
+ // and Timer B of GPTM7 is
+ // triggered
+#define TIMER_SYNC_SYNCWT1_M 0x0000C000 // Synchronize GPTM 32/64-Bit Timer
+ // 1
+#define TIMER_SYNC_SYNCWT1_NONE 0x00000000 // GPTM 32/64-Bit Timer 1 is not
+ // affected
+#define TIMER_SYNC_SYNCWT1_TA 0x00004000 // A timeout event for Timer A of
+ // GPTM 32/64-Bit Timer 1 is
+ // triggered
+#define TIMER_SYNC_SYNCWT1_TB 0x00008000 // A timeout event for Timer B of
+ // GPTM 32/64-Bit Timer 1 is
+ // triggered
+#define TIMER_SYNC_SYNCWT1_TATB 0x0000C000 // A timeout event for both Timer A
+ // and Timer B of GPTM 32/64-Bit
+ // Timer 1 is triggered
+#define TIMER_SYNC_SYNCWT0_M 0x00003000 // Synchronize GPTM 32/64-Bit Timer
+ // 0
+#define TIMER_SYNC_SYNCWT0_NONE 0x00000000 // GPTM 32/64-Bit Timer 0 is not
+ // affected
+#define TIMER_SYNC_SYNCWT0_TA 0x00001000 // A timeout event for Timer A of
+ // GPTM 32/64-Bit Timer 0 is
+ // triggered
+#define TIMER_SYNC_SYNCWT0_TB 0x00002000 // A timeout event for Timer B of
+ // GPTM 32/64-Bit Timer 0 is
+ // triggered
+#define TIMER_SYNC_SYNCWT0_TATB 0x00003000 // A timeout event for both Timer A
+ // and Timer B of GPTM 32/64-Bit
+ // Timer 0 is triggered
+#define TIMER_SYNC_SYNCT6_M 0x00003000 // Synchronize GPTM Timer 6
+#define TIMER_SYNC_SYNCT6_NONE 0x00000000 // GPTM6 is not affected
+#define TIMER_SYNC_SYNCT6_TA 0x00001000 // A timeout event for Timer A of
+ // GPTM6 is triggered
+#define TIMER_SYNC_SYNCT6_TB 0x00002000 // A timeout event for Timer B of
+ // GPTM6 is triggered
+#define TIMER_SYNC_SYNCT6_TATB 0x00003000 // A timeout event for both Timer A
+ // and Timer B of GPTM6 is
+ // triggered
+#define TIMER_SYNC_SYNCT5_M 0x00000C00 // Synchronize GPTM Timer 5
+#define TIMER_SYNC_SYNCT5_NONE 0x00000000 // GPTM5 is not affected
+#define TIMER_SYNC_SYNCT5_TA 0x00000400 // A timeout event for Timer A of
+ // GPTM5 is triggered
+#define TIMER_SYNC_SYNCT5_TB 0x00000800 // A timeout event for Timer B of
+ // GPTM5 is triggered
+#define TIMER_SYNC_SYNCT5_TATB 0x00000C00 // A timeout event for both Timer A
+ // and Timer B of GPTM5 is
+ // triggered
+#define TIMER_SYNC_SYNCT4_M 0x00000300 // Synchronize GPTM Timer 4
+#define TIMER_SYNC_SYNCT4_NONE 0x00000000 // GPTM4 is not affected
+#define TIMER_SYNC_SYNCT4_TA 0x00000100 // A timeout event for Timer A of
+ // GPTM4 is triggered
+#define TIMER_SYNC_SYNCT4_TB 0x00000200 // A timeout event for Timer B of
+ // GPTM4 is triggered
+#define TIMER_SYNC_SYNCT4_TATB 0x00000300 // A timeout event for both Timer A
+ // and Timer B of GPTM4 is
+ // triggered
+#define TIMER_SYNC_SYNCT3_M 0x000000C0 // Synchronize GPTM Timer 3
+#define TIMER_SYNC_SYNCT3_NONE 0x00000000 // GPTM3 is not affected
+#define TIMER_SYNC_SYNCT3_TA 0x00000040 // A timeout event for Timer A of
+ // GPTM3 is triggered
+#define TIMER_SYNC_SYNCT3_TB 0x00000080 // A timeout event for Timer B of
+ // GPTM3 is triggered
+#define TIMER_SYNC_SYNCT3_TATB 0x000000C0 // A timeout event for both Timer A
+ // and Timer B of GPTM3 is
+ // triggered
+#define TIMER_SYNC_SYNCT2_M 0x00000030 // Synchronize GPTM Timer 2
+#define TIMER_SYNC_SYNCT2_NONE 0x00000000 // GPTM2 is not affected
+#define TIMER_SYNC_SYNCT2_TA 0x00000010 // A timeout event for Timer A of
+ // GPTM2 is triggered
+#define TIMER_SYNC_SYNCT2_TB 0x00000020 // A timeout event for Timer B of
+ // GPTM2 is triggered
+#define TIMER_SYNC_SYNCT2_TATB 0x00000030 // A timeout event for both Timer A
+ // and Timer B of GPTM2 is
+ // triggered
+#define TIMER_SYNC_SYNCT1_M 0x0000000C // Synchronize GPTM Timer 1
+#define TIMER_SYNC_SYNCT1_NONE 0x00000000 // GPTM1 is not affected
+#define TIMER_SYNC_SYNCT1_TA 0x00000004 // A timeout event for Timer A of
+ // GPTM1 is triggered
+#define TIMER_SYNC_SYNCT1_TB 0x00000008 // A timeout event for Timer B of
+ // GPTM1 is triggered
+#define TIMER_SYNC_SYNCT1_TATB 0x0000000C // A timeout event for both Timer A
+ // and Timer B of GPTM1 is
+ // triggered
+#define TIMER_SYNC_SYNCT0_M 0x00000003 // Synchronize GPTM Timer 0
+#define TIMER_SYNC_SYNCT0_NONE 0x00000000 // GPTM0 is not affected
+#define TIMER_SYNC_SYNCT0_TA 0x00000001 // A timeout event for Timer A of
+ // GPTM0 is triggered
+#define TIMER_SYNC_SYNCT0_TB 0x00000002 // A timeout event for Timer B of
+ // GPTM0 is triggered
+#define TIMER_SYNC_SYNCT0_TATB 0x00000003 // A timeout event for both Timer A
+ // and Timer B of GPTM0 is
+ // triggered
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_IMR register.
+//
+//*****************************************************************************
+#define TIMER_IMR_WUEIM 0x00010000 // 32/64-Bit Wide GPTM Write Update
+ // Error Interrupt Mask
+#define TIMER_IMR_DMABIM 0x00002000 // GPTM Timer B DMA Done Interrupt
+ // Mask
+#define TIMER_IMR_TBMIM 0x00000800 // GPTM Timer B Match Interrupt
+ // Mask
+#define TIMER_IMR_CBEIM 0x00000400 // GPTM Timer B Capture Mode Event
+ // Interrupt Mask
+#define TIMER_IMR_CBMIM 0x00000200 // GPTM Timer B Capture Mode Match
+ // Interrupt Mask
+#define TIMER_IMR_TBTOIM 0x00000100 // GPTM Timer B Time-Out Interrupt
+ // Mask
+#define TIMER_IMR_DMAAIM 0x00000020 // GPTM Timer A DMA Done Interrupt
+ // Mask
+#define TIMER_IMR_TAMIM 0x00000010 // GPTM Timer A Match Interrupt
+ // Mask
+#define TIMER_IMR_RTCIM 0x00000008 // GPTM RTC Interrupt Mask
+#define TIMER_IMR_CAEIM 0x00000004 // GPTM Timer A Capture Mode Event
+ // Interrupt Mask
+#define TIMER_IMR_CAMIM 0x00000002 // GPTM Timer A Capture Mode Match
+ // Interrupt Mask
+#define TIMER_IMR_TATOIM 0x00000001 // GPTM Timer A Time-Out Interrupt
+ // Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_RIS register.
+//
+//*****************************************************************************
+#define TIMER_RIS_WUERIS 0x00010000 // 32/64-Bit Wide GPTM Write Update
+ // Error Raw Interrupt Status
+#define TIMER_RIS_DMABRIS 0x00002000 // GPTM Timer B DMA Done Raw
+ // Interrupt Status
+#define TIMER_RIS_TBMRIS 0x00000800 // GPTM Timer B Match Raw Interrupt
+#define TIMER_RIS_CBERIS 0x00000400 // GPTM Timer B Capture Mode Event
+ // Raw Interrupt
+#define TIMER_RIS_CBMRIS 0x00000200 // GPTM Timer B Capture Mode Match
+ // Raw Interrupt
+#define TIMER_RIS_TBTORIS 0x00000100 // GPTM Timer B Time-Out Raw
+ // Interrupt
+#define TIMER_RIS_DMAARIS 0x00000020 // GPTM Timer A DMA Done Raw
+ // Interrupt Status
+#define TIMER_RIS_TAMRIS 0x00000010 // GPTM Timer A Match Raw Interrupt
+#define TIMER_RIS_RTCRIS 0x00000008 // GPTM RTC Raw Interrupt
+#define TIMER_RIS_CAERIS 0x00000004 // GPTM Timer A Capture Mode Event
+ // Raw Interrupt
+#define TIMER_RIS_CAMRIS 0x00000002 // GPTM Timer A Capture Mode Match
+ // Raw Interrupt
+#define TIMER_RIS_TATORIS 0x00000001 // GPTM Timer A Time-Out Raw
+ // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_MIS register.
+//
+//*****************************************************************************
+#define TIMER_MIS_WUEMIS 0x00010000 // 32/64-Bit Wide GPTM Write Update
+ // Error Masked Interrupt Status
+#define TIMER_MIS_DMABMIS 0x00002000 // GPTM Timer B DMA Done Masked
+ // Interrupt
+#define TIMER_MIS_TBMMIS 0x00000800 // GPTM Timer B Match Masked
+ // Interrupt
+#define TIMER_MIS_CBEMIS 0x00000400 // GPTM Timer B Capture Mode Event
+ // Masked Interrupt
+#define TIMER_MIS_CBMMIS 0x00000200 // GPTM Timer B Capture Mode Match
+ // Masked Interrupt
+#define TIMER_MIS_TBTOMIS 0x00000100 // GPTM Timer B Time-Out Masked
+ // Interrupt
+#define TIMER_MIS_DMAAMIS 0x00000020 // GPTM Timer A DMA Done Masked
+ // Interrupt
+#define TIMER_MIS_TAMMIS 0x00000010 // GPTM Timer A Match Masked
+ // Interrupt
+#define TIMER_MIS_RTCMIS 0x00000008 // GPTM RTC Masked Interrupt
+#define TIMER_MIS_CAEMIS 0x00000004 // GPTM Timer A Capture Mode Event
+ // Masked Interrupt
+#define TIMER_MIS_CAMMIS 0x00000002 // GPTM Timer A Capture Mode Match
+ // Masked Interrupt
+#define TIMER_MIS_TATOMIS 0x00000001 // GPTM Timer A Time-Out Masked
+ // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_ICR register.
+//
+//*****************************************************************************
+#define TIMER_ICR_WUECINT 0x00010000 // 32/64-Bit Wide GPTM Write Update
+ // Error Interrupt Clear
+#define TIMER_ICR_DMABINT 0x00002000 // GPTM Timer B DMA Done Interrupt
+ // Clear
+#define TIMER_ICR_TBMCINT 0x00000800 // GPTM Timer B Match Interrupt
+ // Clear
+#define TIMER_ICR_CBECINT 0x00000400 // GPTM Timer B Capture Mode Event
+ // Interrupt Clear
+#define TIMER_ICR_CBMCINT 0x00000200 // GPTM Timer B Capture Mode Match
+ // Interrupt Clear
+#define TIMER_ICR_TBTOCINT 0x00000100 // GPTM Timer B Time-Out Interrupt
+ // Clear
+#define TIMER_ICR_DMAAINT 0x00000020 // GPTM Timer A DMA Done Interrupt
+ // Clear
+#define TIMER_ICR_TAMCINT 0x00000010 // GPTM Timer A Match Interrupt
+ // Clear
+#define TIMER_ICR_RTCCINT 0x00000008 // GPTM RTC Interrupt Clear
+#define TIMER_ICR_CAECINT 0x00000004 // GPTM Timer A Capture Mode Event
+ // Interrupt Clear
+#define TIMER_ICR_CAMCINT 0x00000002 // GPTM Timer A Capture Mode Match
+ // Interrupt Clear
+#define TIMER_ICR_TATOCINT 0x00000001 // GPTM Timer A Time-Out Raw
+ // Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAILR register.
+//
+//*****************************************************************************
+#define TIMER_TAILR_M 0xFFFFFFFF // GPTM Timer A Interval Load
+ // Register
+#define TIMER_TAILR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBILR register.
+//
+//*****************************************************************************
+#define TIMER_TBILR_M 0xFFFFFFFF // GPTM Timer B Interval Load
+ // Register
+#define TIMER_TBILR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAMATCHR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TAMATCHR_TAMR_M 0xFFFFFFFF // GPTM Timer A Match Register
+#define TIMER_TAMATCHR_TAMR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBMATCHR
+// register.
+//
+//*****************************************************************************
+#define TIMER_TBMATCHR_TBMR_M 0xFFFFFFFF // GPTM Timer B Match Register
+#define TIMER_TBMATCHR_TBMR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPR register.
+//
+//*****************************************************************************
+#define TIMER_TAPR_TAPSRH_M 0x0000FF00 // GPTM Timer A Prescale High Byte
+#define TIMER_TAPR_TAPSR_M 0x000000FF // GPTM Timer A Prescale
+#define TIMER_TAPR_TAPSRH_S 8
+#define TIMER_TAPR_TAPSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPR register.
+//
+//*****************************************************************************
+#define TIMER_TBPR_TBPSRH_M 0x0000FF00 // GPTM Timer B Prescale High Byte
+#define TIMER_TBPR_TBPSR_M 0x000000FF // GPTM Timer B Prescale
+#define TIMER_TBPR_TBPSRH_S 8
+#define TIMER_TBPR_TBPSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPMR register.
+//
+//*****************************************************************************
+#define TIMER_TAPMR_TAPSMRH_M 0x0000FF00 // GPTM Timer A Prescale Match High
+ // Byte
+#define TIMER_TAPMR_TAPSMR_M 0x000000FF // GPTM TimerA Prescale Match
+#define TIMER_TAPMR_TAPSMRH_S 8
+#define TIMER_TAPMR_TAPSMR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPMR register.
+//
+//*****************************************************************************
+#define TIMER_TBPMR_TBPSMRH_M 0x0000FF00 // GPTM Timer B Prescale Match High
+ // Byte
+#define TIMER_TBPMR_TBPSMR_M 0x000000FF // GPTM TimerB Prescale Match
+#define TIMER_TBPMR_TBPSMRH_S 8
+#define TIMER_TBPMR_TBPSMR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAR register.
+//
+//*****************************************************************************
+#define TIMER_TAR_M 0xFFFFFFFF // GPTM Timer A Register
+#define TIMER_TAR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBR register.
+//
+//*****************************************************************************
+#define TIMER_TBR_M 0xFFFFFFFF // GPTM Timer B Register
+#define TIMER_TBR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAV register.
+//
+//*****************************************************************************
+#define TIMER_TAV_M 0xFFFFFFFF // GPTM Timer A Value
+#define TIMER_TAV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBV register.
+//
+//*****************************************************************************
+#define TIMER_TBV_M 0xFFFFFFFF // GPTM Timer B Value
+#define TIMER_TBV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_RTCPD register.
+//
+//*****************************************************************************
+#define TIMER_RTCPD_RTCPD_M 0x0000FFFF // RTC Predivide Counter Value
+#define TIMER_RTCPD_RTCPD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPS register.
+//
+//*****************************************************************************
+#define TIMER_TAPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Snapshot
+#define TIMER_TAPS_PSS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPS register.
+//
+//*****************************************************************************
+#define TIMER_TBPS_PSS_M 0x0000FFFF // GPTM Timer A Prescaler Value
+#define TIMER_TBPS_PSS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TAPV register.
+//
+//*****************************************************************************
+#define TIMER_TAPV_PSV_M 0x0000FFFF // GPTM Timer A Prescaler Value
+#define TIMER_TAPV_PSV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_TBPV register.
+//
+//*****************************************************************************
+#define TIMER_TBPV_PSV_M 0x0000FFFF // GPTM Timer B Prescaler Value
+#define TIMER_TBPV_PSV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_DMAEV register.
+//
+//*****************************************************************************
+#define TIMER_DMAEV_TBMDMAEN 0x00000800 // GPTM B Mode Match Event DMA
+ // Trigger Enable
+#define TIMER_DMAEV_CBEDMAEN 0x00000400 // GPTM B Capture Event DMA Trigger
+ // Enable
+#define TIMER_DMAEV_CBMDMAEN 0x00000200 // GPTM B Capture Match Event DMA
+ // Trigger Enable
+#define TIMER_DMAEV_TBTODMAEN 0x00000100 // GPTM B Time-Out Event DMA
+ // Trigger Enable
+#define TIMER_DMAEV_TAMDMAEN 0x00000010 // GPTM A Mode Match Event DMA
+ // Trigger Enable
+#define TIMER_DMAEV_RTCDMAEN 0x00000008 // GPTM A RTC Match Event DMA
+ // Trigger Enable
+#define TIMER_DMAEV_CAEDMAEN 0x00000004 // GPTM A Capture Event DMA Trigger
+ // Enable
+#define TIMER_DMAEV_CAMDMAEN 0x00000002 // GPTM A Capture Match Event DMA
+ // Trigger Enable
+#define TIMER_DMAEV_TATODMAEN 0x00000001 // GPTM A Time-Out Event DMA
+ // Trigger Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_ADCEV register.
+//
+//*****************************************************************************
+#define TIMER_ADCEV_TBMADCEN 0x00000800 // GPTM B Mode Match Event ADC
+ // Trigger Enable
+#define TIMER_ADCEV_CBEADCEN 0x00000400 // GPTM B Capture Event ADC Trigger
+ // Enable
+#define TIMER_ADCEV_CBMADCEN 0x00000200 // GPTM B Capture Match Event ADC
+ // Trigger Enable
+#define TIMER_ADCEV_TBTOADCEN 0x00000100 // GPTM B Time-Out Event ADC
+ // Trigger Enable
+#define TIMER_ADCEV_TAMADCEN 0x00000010 // GPTM A Mode Match Event ADC
+ // Trigger Enable
+#define TIMER_ADCEV_RTCADCEN 0x00000008 // GPTM RTC Match Event ADC Trigger
+ // Enable
+#define TIMER_ADCEV_CAEADCEN 0x00000004 // GPTM A Capture Event ADC Trigger
+ // Enable
+#define TIMER_ADCEV_CAMADCEN 0x00000002 // GPTM A Capture Match Event ADC
+ // Trigger Enable
+#define TIMER_ADCEV_TATOADCEN 0x00000001 // GPTM A Time-Out Event ADC
+ // Trigger Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_PP register.
+//
+//*****************************************************************************
+#define TIMER_PP_ALTCLK 0x00000040 // Alternate Clock Source
+#define TIMER_PP_SYNCCNT 0x00000020 // Synchronize Start
+#define TIMER_PP_CHAIN 0x00000010 // Chain with Other Timers
+#define TIMER_PP_SIZE_M 0x0000000F // Count Size
+#define TIMER_PP_SIZE_16 0x00000000 // Timer A and Timer B counters are
+ // 16 bits each with an 8-bit
+ // prescale counter
+#define TIMER_PP_SIZE_32 0x00000001 // Timer A and Timer B counters are
+ // 32 bits each with a 16-bit
+ // prescale counter
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the TIMER_O_CC register.
+//
+//*****************************************************************************
+#define TIMER_CC_ALTCLK 0x00000001 // Alternate Clock Source
+
+#endif // __HW_TIMER_H__
diff --git a/os/common/ext/TivaWare/inc/hw_types.h b/os/common/ext/TivaWare/inc/hw_types.h
new file mode 100644
index 0000000..6312a28
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_types.h
@@ -0,0 +1,147 @@
+//*****************************************************************************
+//
+// hw_types.h - Common types and macros.
+//
+// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_TYPES_H__
+#define __HW_TYPES_H__
+
+//*****************************************************************************
+//
+// Macros for hardware access, both direct and via the bit-band region.
+//
+//*****************************************************************************
+#define HWREG(x) \
+ (*((volatile uint32_t *)(x)))
+#define HWREGH(x) \
+ (*((volatile uint16_t *)(x)))
+#define HWREGB(x) \
+ (*((volatile uint8_t *)(x)))
+#define HWREGBITW(x, b) \
+ HWREG(((uint32_t)(x) & 0xF0000000) | 0x02000000 | \
+ (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+#define HWREGBITH(x, b) \
+ HWREGH(((uint32_t)(x) & 0xF0000000) | 0x02000000 | \
+ (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+#define HWREGBITB(x, b) \
+ HWREGB(((uint32_t)(x) & 0xF0000000) | 0x02000000 | \
+ (((uint32_t)(x) & 0x000FFFFF) << 5) | ((b) << 2))
+
+//*****************************************************************************
+//
+// Helper Macros for determining silicon revisions, etc.
+//
+// These macros will be used by Driverlib at "run-time" to create necessary
+// conditional code blocks that will allow a single version of the Driverlib
+// "binary" code to support multiple(all) Tiva silicon revisions.
+//
+// It is expected that these macros will be used inside of a standard 'C'
+// conditional block of code, e.g.
+//
+// if(CLASS_IS_TM4C123)
+// {
+// do some TM4C123-class specific code here.
+// }
+//
+// By default, these macros will be defined as run-time checks of the
+// appropriate register(s) to allow creation of run-time conditional code
+// blocks for a common DriverLib across the entire Tiva family.
+//
+// However, if code-space optimization is required, these macros can be "hard-
+// coded" for a specific version of Tiva silicon. Many compilers will then
+// detect the "hard-coded" conditionals, and appropriately optimize the code
+// blocks, eliminating any "unreachable" code. This would result in a smaller
+// Driverlib, thus producing a smaller final application size, but at the cost
+// of limiting the Driverlib binary to a specific Tiva silicon revision.
+//
+//*****************************************************************************
+#ifndef CLASS_IS_TM4C123
+#define CLASS_IS_TM4C123 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
+ (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_TM4C123))
+#endif
+
+#ifndef CLASS_IS_TM4C129
+#define CLASS_IS_TM4C129 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_VER_M | SYSCTL_DID0_CLASS_M)) == \
+ (SYSCTL_DID0_VER_1 | SYSCTL_DID0_CLASS_TM4C129))
+#endif
+
+#ifndef REVISION_IS_A0
+#define REVISION_IS_A0 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+ (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0))
+#endif
+
+#ifndef REVISION_IS_A1
+#define REVISION_IS_A1 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+ (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_0))
+#endif
+
+#ifndef REVISION_IS_A2
+#define REVISION_IS_A2 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+ (SYSCTL_DID0_MAJ_REVA | SYSCTL_DID0_MIN_2))
+#endif
+
+#ifndef REVISION_IS_B0
+#define REVISION_IS_B0 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+ (SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_0))
+#endif
+
+#ifndef REVISION_IS_B1
+#define REVISION_IS_B1 \
+ ((HWREG(SYSCTL_DID0) & (SYSCTL_DID0_MAJ_M | SYSCTL_DID0_MIN_M)) == \
+ (SYSCTL_DID0_MAJ_REVB | SYSCTL_DID0_MIN_1))
+#endif
+
+//*****************************************************************************
+//
+// For TivaWare 2.1, we removed all references to Tiva IC codenames from the
+// source. To ensure that existing customer code doesn't break as a result
+// of this change, make sure that the old definitions are still available at
+// least for the time being.
+//
+//*****************************************************************************
+#ifndef DEPRECATED
+#define CLASS_IS_BLIZZARD CLASS_IS_TM4C123
+#define CLASS_IS_SNOWFLAKE CLASS_IS_TM4C123
+#endif
+
+#endif // __HW_TYPES_H__
diff --git a/os/common/ext/TivaWare/inc/hw_uart.h b/os/common/ext/TivaWare/inc/hw_uart.h
new file mode 100644
index 0000000..cca4b93
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_uart.h
@@ -0,0 +1,367 @@
+//*****************************************************************************
+//
+// hw_uart.h - Macros and defines used when accessing the UART hardware.
+//
+// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_UART_H__
+#define __HW_UART_H__
+
+//*****************************************************************************
+//
+// The following are defines for the UART register offsets.
+//
+//*****************************************************************************
+#define UART_O_DR 0x00000000 // UART Data
+#define UART_O_RSR 0x00000004 // UART Receive Status/Error Clear
+#define UART_O_ECR 0x00000004 // UART Receive Status/Error Clear
+#define UART_O_FR 0x00000018 // UART Flag
+#define UART_O_ILPR 0x00000020 // UART IrDA Low-Power Register
+#define UART_O_IBRD 0x00000024 // UART Integer Baud-Rate Divisor
+#define UART_O_FBRD 0x00000028 // UART Fractional Baud-Rate
+ // Divisor
+#define UART_O_LCRH 0x0000002C // UART Line Control
+#define UART_O_CTL 0x00000030 // UART Control
+#define UART_O_IFLS 0x00000034 // UART Interrupt FIFO Level Select
+#define UART_O_IM 0x00000038 // UART Interrupt Mask
+#define UART_O_RIS 0x0000003C // UART Raw Interrupt Status
+#define UART_O_MIS 0x00000040 // UART Masked Interrupt Status
+#define UART_O_ICR 0x00000044 // UART Interrupt Clear
+#define UART_O_DMACTL 0x00000048 // UART DMA Control
+#define UART_O_9BITADDR 0x000000A4 // UART 9-Bit Self Address
+#define UART_O_9BITAMASK 0x000000A8 // UART 9-Bit Self Address Mask
+#define UART_O_PP 0x00000FC0 // UART Peripheral Properties
+#define UART_O_CC 0x00000FC8 // UART Clock Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_DR register.
+//
+//*****************************************************************************
+#define UART_DR_OE 0x00000800 // UART Overrun Error
+#define UART_DR_BE 0x00000400 // UART Break Error
+#define UART_DR_PE 0x00000200 // UART Parity Error
+#define UART_DR_FE 0x00000100 // UART Framing Error
+#define UART_DR_DATA_M 0x000000FF // Data Transmitted or Received
+#define UART_DR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RSR register.
+//
+//*****************************************************************************
+#define UART_RSR_OE 0x00000008 // UART Overrun Error
+#define UART_RSR_BE 0x00000004 // UART Break Error
+#define UART_RSR_PE 0x00000002 // UART Parity Error
+#define UART_RSR_FE 0x00000001 // UART Framing Error
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ECR register.
+//
+//*****************************************************************************
+#define UART_ECR_DATA_M 0x000000FF // Error Clear
+#define UART_ECR_DATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FR register.
+//
+//*****************************************************************************
+#define UART_FR_RI 0x00000100 // Ring Indicator
+#define UART_FR_TXFE 0x00000080 // UART Transmit FIFO Empty
+#define UART_FR_RXFF 0x00000040 // UART Receive FIFO Full
+#define UART_FR_TXFF 0x00000020 // UART Transmit FIFO Full
+#define UART_FR_RXFE 0x00000010 // UART Receive FIFO Empty
+#define UART_FR_BUSY 0x00000008 // UART Busy
+#define UART_FR_DCD 0x00000004 // Data Carrier Detect
+#define UART_FR_DSR 0x00000002 // Data Set Ready
+#define UART_FR_CTS 0x00000001 // Clear To Send
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ILPR register.
+//
+//*****************************************************************************
+#define UART_ILPR_ILPDVSR_M 0x000000FF // IrDA Low-Power Divisor
+#define UART_ILPR_ILPDVSR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IBRD register.
+//
+//*****************************************************************************
+#define UART_IBRD_DIVINT_M 0x0000FFFF // Integer Baud-Rate Divisor
+#define UART_IBRD_DIVINT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_FBRD register.
+//
+//*****************************************************************************
+#define UART_FBRD_DIVFRAC_M 0x0000003F // Fractional Baud-Rate Divisor
+#define UART_FBRD_DIVFRAC_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_LCRH register.
+//
+//*****************************************************************************
+#define UART_LCRH_SPS 0x00000080 // UART Stick Parity Select
+#define UART_LCRH_WLEN_M 0x00000060 // UART Word Length
+#define UART_LCRH_WLEN_5 0x00000000 // 5 bits (default)
+#define UART_LCRH_WLEN_6 0x00000020 // 6 bits
+#define UART_LCRH_WLEN_7 0x00000040 // 7 bits
+#define UART_LCRH_WLEN_8 0x00000060 // 8 bits
+#define UART_LCRH_FEN 0x00000010 // UART Enable FIFOs
+#define UART_LCRH_STP2 0x00000008 // UART Two Stop Bits Select
+#define UART_LCRH_EPS 0x00000004 // UART Even Parity Select
+#define UART_LCRH_PEN 0x00000002 // UART Parity Enable
+#define UART_LCRH_BRK 0x00000001 // UART Send Break
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_CTL register.
+//
+//*****************************************************************************
+#define UART_CTL_CTSEN 0x00008000 // Enable Clear To Send
+#define UART_CTL_RTSEN 0x00004000 // Enable Request to Send
+#define UART_CTL_RTS 0x00000800 // Request to Send
+#define UART_CTL_DTR 0x00000400 // Data Terminal Ready
+#define UART_CTL_RXE 0x00000200 // UART Receive Enable
+#define UART_CTL_TXE 0x00000100 // UART Transmit Enable
+#define UART_CTL_LBE 0x00000080 // UART Loop Back Enable
+#define UART_CTL_HSE 0x00000020 // High-Speed Enable
+#define UART_CTL_EOT 0x00000010 // End of Transmission
+#define UART_CTL_SMART 0x00000008 // ISO 7816 Smart Card Support
+#define UART_CTL_SIRLP 0x00000004 // UART SIR Low-Power Mode
+#define UART_CTL_SIREN 0x00000002 // UART SIR Enable
+#define UART_CTL_UARTEN 0x00000001 // UART Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IFLS register.
+//
+//*****************************************************************************
+#define UART_IFLS_RX_M 0x00000038 // UART Receive Interrupt FIFO
+ // Level Select
+#define UART_IFLS_RX1_8 0x00000000 // RX FIFO >= 1/8 full
+#define UART_IFLS_RX2_8 0x00000008 // RX FIFO >= 1/4 full
+#define UART_IFLS_RX4_8 0x00000010 // RX FIFO >= 1/2 full (default)
+#define UART_IFLS_RX6_8 0x00000018 // RX FIFO >= 3/4 full
+#define UART_IFLS_RX7_8 0x00000020 // RX FIFO >= 7/8 full
+#define UART_IFLS_TX_M 0x00000007 // UART Transmit Interrupt FIFO
+ // Level Select
+#define UART_IFLS_TX1_8 0x00000000 // TX FIFO <= 1/8 full
+#define UART_IFLS_TX2_8 0x00000001 // TX FIFO <= 1/4 full
+#define UART_IFLS_TX4_8 0x00000002 // TX FIFO <= 1/2 full (default)
+#define UART_IFLS_TX6_8 0x00000003 // TX FIFO <= 3/4 full
+#define UART_IFLS_TX7_8 0x00000004 // TX FIFO <= 7/8 full
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_IM register.
+//
+//*****************************************************************************
+#define UART_IM_DMATXIM 0x00020000 // Transmit DMA Interrupt Mask
+#define UART_IM_DMARXIM 0x00010000 // Receive DMA Interrupt Mask
+#define UART_IM_9BITIM 0x00001000 // 9-Bit Mode Interrupt Mask
+#define UART_IM_EOTIM 0x00000800 // End of Transmission Interrupt
+ // Mask
+#define UART_IM_OEIM 0x00000400 // UART Overrun Error Interrupt
+ // Mask
+#define UART_IM_BEIM 0x00000200 // UART Break Error Interrupt Mask
+#define UART_IM_PEIM 0x00000100 // UART Parity Error Interrupt Mask
+#define UART_IM_FEIM 0x00000080 // UART Framing Error Interrupt
+ // Mask
+#define UART_IM_RTIM 0x00000040 // UART Receive Time-Out Interrupt
+ // Mask
+#define UART_IM_TXIM 0x00000020 // UART Transmit Interrupt Mask
+#define UART_IM_RXIM 0x00000010 // UART Receive Interrupt Mask
+#define UART_IM_DSRMIM 0x00000008 // UART Data Set Ready Modem
+ // Interrupt Mask
+#define UART_IM_DCDMIM 0x00000004 // UART Data Carrier Detect Modem
+ // Interrupt Mask
+#define UART_IM_CTSMIM 0x00000002 // UART Clear to Send Modem
+ // Interrupt Mask
+#define UART_IM_RIMIM 0x00000001 // UART Ring Indicator Modem
+ // Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_RIS register.
+//
+//*****************************************************************************
+#define UART_RIS_DMATXRIS 0x00020000 // Transmit DMA Raw Interrupt
+ // Status
+#define UART_RIS_DMARXRIS 0x00010000 // Receive DMA Raw Interrupt Status
+#define UART_RIS_9BITRIS 0x00001000 // 9-Bit Mode Raw Interrupt Status
+#define UART_RIS_EOTRIS 0x00000800 // End of Transmission Raw
+ // Interrupt Status
+#define UART_RIS_OERIS 0x00000400 // UART Overrun Error Raw Interrupt
+ // Status
+#define UART_RIS_BERIS 0x00000200 // UART Break Error Raw Interrupt
+ // Status
+#define UART_RIS_PERIS 0x00000100 // UART Parity Error Raw Interrupt
+ // Status
+#define UART_RIS_FERIS 0x00000080 // UART Framing Error Raw Interrupt
+ // Status
+#define UART_RIS_RTRIS 0x00000040 // UART Receive Time-Out Raw
+ // Interrupt Status
+#define UART_RIS_TXRIS 0x00000020 // UART Transmit Raw Interrupt
+ // Status
+#define UART_RIS_RXRIS 0x00000010 // UART Receive Raw Interrupt
+ // Status
+#define UART_RIS_DSRRIS 0x00000008 // UART Data Set Ready Modem Raw
+ // Interrupt Status
+#define UART_RIS_DCDRIS 0x00000004 // UART Data Carrier Detect Modem
+ // Raw Interrupt Status
+#define UART_RIS_CTSRIS 0x00000002 // UART Clear to Send Modem Raw
+ // Interrupt Status
+#define UART_RIS_RIRIS 0x00000001 // UART Ring Indicator Modem Raw
+ // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_MIS register.
+//
+//*****************************************************************************
+#define UART_MIS_DMATXMIS 0x00020000 // Transmit DMA Masked Interrupt
+ // Status
+#define UART_MIS_DMARXMIS 0x00010000 // Receive DMA Masked Interrupt
+ // Status
+#define UART_MIS_9BITMIS 0x00001000 // 9-Bit Mode Masked Interrupt
+ // Status
+#define UART_MIS_EOTMIS 0x00000800 // End of Transmission Masked
+ // Interrupt Status
+#define UART_MIS_OEMIS 0x00000400 // UART Overrun Error Masked
+ // Interrupt Status
+#define UART_MIS_BEMIS 0x00000200 // UART Break Error Masked
+ // Interrupt Status
+#define UART_MIS_PEMIS 0x00000100 // UART Parity Error Masked
+ // Interrupt Status
+#define UART_MIS_FEMIS 0x00000080 // UART Framing Error Masked
+ // Interrupt Status
+#define UART_MIS_RTMIS 0x00000040 // UART Receive Time-Out Masked
+ // Interrupt Status
+#define UART_MIS_TXMIS 0x00000020 // UART Transmit Masked Interrupt
+ // Status
+#define UART_MIS_RXMIS 0x00000010 // UART Receive Masked Interrupt
+ // Status
+#define UART_MIS_DSRMIS 0x00000008 // UART Data Set Ready Modem Masked
+ // Interrupt Status
+#define UART_MIS_DCDMIS 0x00000004 // UART Data Carrier Detect Modem
+ // Masked Interrupt Status
+#define UART_MIS_CTSMIS 0x00000002 // UART Clear to Send Modem Masked
+ // Interrupt Status
+#define UART_MIS_RIMIS 0x00000001 // UART Ring Indicator Modem Masked
+ // Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_ICR register.
+//
+//*****************************************************************************
+#define UART_ICR_DMATXIC 0x00020000 // Transmit DMA Interrupt Clear
+#define UART_ICR_DMARXIC 0x00010000 // Receive DMA Interrupt Clear
+#define UART_ICR_9BITIC 0x00001000 // 9-Bit Mode Interrupt Clear
+#define UART_ICR_EOTIC 0x00000800 // End of Transmission Interrupt
+ // Clear
+#define UART_ICR_OEIC 0x00000400 // Overrun Error Interrupt Clear
+#define UART_ICR_BEIC 0x00000200 // Break Error Interrupt Clear
+#define UART_ICR_PEIC 0x00000100 // Parity Error Interrupt Clear
+#define UART_ICR_FEIC 0x00000080 // Framing Error Interrupt Clear
+#define UART_ICR_RTIC 0x00000040 // Receive Time-Out Interrupt Clear
+#define UART_ICR_TXIC 0x00000020 // Transmit Interrupt Clear
+#define UART_ICR_RXIC 0x00000010 // Receive Interrupt Clear
+#define UART_ICR_DSRMIC 0x00000008 // UART Data Set Ready Modem
+ // Interrupt Clear
+#define UART_ICR_DCDMIC 0x00000004 // UART Data Carrier Detect Modem
+ // Interrupt Clear
+#define UART_ICR_CTSMIC 0x00000002 // UART Clear to Send Modem
+ // Interrupt Clear
+#define UART_ICR_RIMIC 0x00000001 // UART Ring Indicator Modem
+ // Interrupt Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_DMACTL register.
+//
+//*****************************************************************************
+#define UART_DMACTL_DMAERR 0x00000004 // DMA on Error
+#define UART_DMACTL_TXDMAE 0x00000002 // Transmit DMA Enable
+#define UART_DMACTL_RXDMAE 0x00000001 // Receive DMA Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_9BITADDR
+// register.
+//
+//*****************************************************************************
+#define UART_9BITADDR_9BITEN 0x00008000 // Enable 9-Bit Mode
+#define UART_9BITADDR_ADDR_M 0x000000FF // Self Address for 9-Bit Mode
+#define UART_9BITADDR_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_9BITAMASK
+// register.
+//
+//*****************************************************************************
+#define UART_9BITAMASK_MASK_M 0x000000FF // Self Address Mask for 9-Bit Mode
+#define UART_9BITAMASK_MASK_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_PP register.
+//
+//*****************************************************************************
+#define UART_PP_MSE 0x00000008 // Modem Support Extended
+#define UART_PP_MS 0x00000004 // Modem Support
+#define UART_PP_NB 0x00000002 // 9-Bit Support
+#define UART_PP_SC 0x00000001 // Smart Card Support
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UART_O_CC register.
+//
+//*****************************************************************************
+#define UART_CC_CS_M 0x0000000F // UART Baud Clock Source
+#define UART_CC_CS_SYSCLK 0x00000000 // System clock (based on clock
+ // source and divisor factor)
+#define UART_CC_CS_PIOSC 0x00000005 // PIOSC
+
+#endif // __HW_UART_H__
diff --git a/os/common/ext/TivaWare/inc/hw_udma.h b/os/common/ext/TivaWare/inc/hw_udma.h
new file mode 100644
index 0000000..85bc014
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_udma.h
@@ -0,0 +1,414 @@
+//*****************************************************************************
+//
+// hw_udma.h - Macros for use in accessing the UDMA registers.
+//
+// Copyright (c) 2007-2016 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_UDMA_H__
+#define __HW_UDMA_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Micro Direct Memory Access register
+// addresses.
+//
+//*****************************************************************************
+#define UDMA_STAT 0x400FF000 // DMA Status
+#define UDMA_CFG 0x400FF004 // DMA Configuration
+#define UDMA_CTLBASE 0x400FF008 // DMA Channel Control Base Pointer
+#define UDMA_ALTBASE 0x400FF00C // DMA Alternate Channel Control
+ // Base Pointer
+#define UDMA_WAITSTAT 0x400FF010 // DMA Channel Wait-on-Request
+ // Status
+#define UDMA_SWREQ 0x400FF014 // DMA Channel Software Request
+#define UDMA_USEBURSTSET 0x400FF018 // DMA Channel Useburst Set
+#define UDMA_USEBURSTCLR 0x400FF01C // DMA Channel Useburst Clear
+#define UDMA_REQMASKSET 0x400FF020 // DMA Channel Request Mask Set
+#define UDMA_REQMASKCLR 0x400FF024 // DMA Channel Request Mask Clear
+#define UDMA_ENASET 0x400FF028 // DMA Channel Enable Set
+#define UDMA_ENACLR 0x400FF02C // DMA Channel Enable Clear
+#define UDMA_ALTSET 0x400FF030 // DMA Channel Primary Alternate
+ // Set
+#define UDMA_ALTCLR 0x400FF034 // DMA Channel Primary Alternate
+ // Clear
+#define UDMA_PRIOSET 0x400FF038 // DMA Channel Priority Set
+#define UDMA_PRIOCLR 0x400FF03C // DMA Channel Priority Clear
+#define UDMA_ERRCLR 0x400FF04C // DMA Bus Error Clear
+#define UDMA_CHASGN 0x400FF500 // DMA Channel Assignment
+#define UDMA_CHIS 0x400FF504 // DMA Channel Interrupt Status
+#define UDMA_CHMAP0 0x400FF510 // DMA Channel Map Select 0
+#define UDMA_CHMAP1 0x400FF514 // DMA Channel Map Select 1
+#define UDMA_CHMAP2 0x400FF518 // DMA Channel Map Select 2
+#define UDMA_CHMAP3 0x400FF51C // DMA Channel Map Select 3
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_STAT register.
+//
+//*****************************************************************************
+#define UDMA_STAT_DMACHANS_M 0x001F0000 // Available uDMA Channels Minus 1
+#define UDMA_STAT_STATE_M 0x000000F0 // Control State Machine Status
+#define UDMA_STAT_STATE_IDLE 0x00000000 // Idle
+#define UDMA_STAT_STATE_RD_CTRL 0x00000010 // Reading channel controller data
+#define UDMA_STAT_STATE_RD_SRCENDP \
+ 0x00000020 // Reading source end pointer
+#define UDMA_STAT_STATE_RD_DSTENDP \
+ 0x00000030 // Reading destination end pointer
+#define UDMA_STAT_STATE_RD_SRCDAT \
+ 0x00000040 // Reading source data
+#define UDMA_STAT_STATE_WR_DSTDAT \
+ 0x00000050 // Writing destination data
+#define UDMA_STAT_STATE_WAIT 0x00000060 // Waiting for uDMA request to
+ // clear
+#define UDMA_STAT_STATE_WR_CTRL 0x00000070 // Writing channel controller data
+#define UDMA_STAT_STATE_STALL 0x00000080 // Stalled
+#define UDMA_STAT_STATE_DONE 0x00000090 // Done
+#define UDMA_STAT_STATE_UNDEF 0x000000A0 // Undefined
+#define UDMA_STAT_MASTEN 0x00000001 // Master Enable Status
+#define UDMA_STAT_DMACHANS_S 16
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CFG register.
+//
+//*****************************************************************************
+#define UDMA_CFG_MASTEN 0x00000001 // Controller Master Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CTLBASE register.
+//
+//*****************************************************************************
+#define UDMA_CTLBASE_ADDR_M 0xFFFFFC00 // Channel Control Base Address
+#define UDMA_CTLBASE_ADDR_S 10
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTBASE register.
+//
+//*****************************************************************************
+#define UDMA_ALTBASE_ADDR_M 0xFFFFFFFF // Alternate Channel Address
+ // Pointer
+#define UDMA_ALTBASE_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_WAITSTAT register.
+//
+//*****************************************************************************
+#define UDMA_WAITSTAT_WAITREQ_M 0xFFFFFFFF // Channel [n] Wait Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_SWREQ register.
+//
+//*****************************************************************************
+#define UDMA_SWREQ_M 0xFFFFFFFF // Channel [n] Software Request
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_USEBURSTSET
+// register.
+//
+//*****************************************************************************
+#define UDMA_USEBURSTSET_SET_M 0xFFFFFFFF // Channel [n] Useburst Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_USEBURSTCLR
+// register.
+//
+//*****************************************************************************
+#define UDMA_USEBURSTCLR_CLR_M 0xFFFFFFFF // Channel [n] Useburst Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_REQMASKSET
+// register.
+//
+//*****************************************************************************
+#define UDMA_REQMASKSET_SET_M 0xFFFFFFFF // Channel [n] Request Mask Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_REQMASKCLR
+// register.
+//
+//*****************************************************************************
+#define UDMA_REQMASKCLR_CLR_M 0xFFFFFFFF // Channel [n] Request Mask Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ENASET register.
+//
+//*****************************************************************************
+#define UDMA_ENASET_SET_M 0xFFFFFFFF // Channel [n] Enable Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ENACLR register.
+//
+//*****************************************************************************
+#define UDMA_ENACLR_CLR_M 0xFFFFFFFF // Clear Channel [n] Enable Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTSET register.
+//
+//*****************************************************************************
+#define UDMA_ALTSET_SET_M 0xFFFFFFFF // Channel [n] Alternate Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ALTCLR register.
+//
+//*****************************************************************************
+#define UDMA_ALTCLR_CLR_M 0xFFFFFFFF // Channel [n] Alternate Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_PRIOSET register.
+//
+//*****************************************************************************
+#define UDMA_PRIOSET_SET_M 0xFFFFFFFF // Channel [n] Priority Set
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_PRIOCLR register.
+//
+//*****************************************************************************
+#define UDMA_PRIOCLR_CLR_M 0xFFFFFFFF // Channel [n] Priority Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_ERRCLR register.
+//
+//*****************************************************************************
+#define UDMA_ERRCLR_ERRCLR 0x00000001 // uDMA Bus Error Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHASGN register.
+//
+//*****************************************************************************
+#define UDMA_CHASGN_M 0xFFFFFFFF // Channel [n] Assignment Select
+#define UDMA_CHASGN_PRIMARY 0x00000000 // Use the primary channel
+ // assignment
+#define UDMA_CHASGN_SECONDARY 0x00000001 // Use the secondary channel
+ // assignment
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHIS register.
+//
+//*****************************************************************************
+#define UDMA_CHIS_M 0xFFFFFFFF // Channel [n] Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHMAP0 register.
+//
+//*****************************************************************************
+#define UDMA_CHMAP0_CH7SEL_M 0xF0000000 // uDMA Channel 7 Source Select
+#define UDMA_CHMAP0_CH6SEL_M 0x0F000000 // uDMA Channel 6 Source Select
+#define UDMA_CHMAP0_CH5SEL_M 0x00F00000 // uDMA Channel 5 Source Select
+#define UDMA_CHMAP0_CH4SEL_M 0x000F0000 // uDMA Channel 4 Source Select
+#define UDMA_CHMAP0_CH3SEL_M 0x0000F000 // uDMA Channel 3 Source Select
+#define UDMA_CHMAP0_CH2SEL_M 0x00000F00 // uDMA Channel 2 Source Select
+#define UDMA_CHMAP0_CH1SEL_M 0x000000F0 // uDMA Channel 1 Source Select
+#define UDMA_CHMAP0_CH0SEL_M 0x0000000F // uDMA Channel 0 Source Select
+#define UDMA_CHMAP0_CH7SEL_S 28
+#define UDMA_CHMAP0_CH6SEL_S 24
+#define UDMA_CHMAP0_CH5SEL_S 20
+#define UDMA_CHMAP0_CH4SEL_S 16
+#define UDMA_CHMAP0_CH3SEL_S 12
+#define UDMA_CHMAP0_CH2SEL_S 8
+#define UDMA_CHMAP0_CH1SEL_S 4
+#define UDMA_CHMAP0_CH0SEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHMAP1 register.
+//
+//*****************************************************************************
+#define UDMA_CHMAP1_CH15SEL_M 0xF0000000 // uDMA Channel 15 Source Select
+#define UDMA_CHMAP1_CH14SEL_M 0x0F000000 // uDMA Channel 14 Source Select
+#define UDMA_CHMAP1_CH13SEL_M 0x00F00000 // uDMA Channel 13 Source Select
+#define UDMA_CHMAP1_CH12SEL_M 0x000F0000 // uDMA Channel 12 Source Select
+#define UDMA_CHMAP1_CH11SEL_M 0x0000F000 // uDMA Channel 11 Source Select
+#define UDMA_CHMAP1_CH10SEL_M 0x00000F00 // uDMA Channel 10 Source Select
+#define UDMA_CHMAP1_CH9SEL_M 0x000000F0 // uDMA Channel 9 Source Select
+#define UDMA_CHMAP1_CH8SEL_M 0x0000000F // uDMA Channel 8 Source Select
+#define UDMA_CHMAP1_CH15SEL_S 28
+#define UDMA_CHMAP1_CH14SEL_S 24
+#define UDMA_CHMAP1_CH13SEL_S 20
+#define UDMA_CHMAP1_CH12SEL_S 16
+#define UDMA_CHMAP1_CH11SEL_S 12
+#define UDMA_CHMAP1_CH10SEL_S 8
+#define UDMA_CHMAP1_CH9SEL_S 4
+#define UDMA_CHMAP1_CH8SEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHMAP2 register.
+//
+//*****************************************************************************
+#define UDMA_CHMAP2_CH23SEL_M 0xF0000000 // uDMA Channel 23 Source Select
+#define UDMA_CHMAP2_CH22SEL_M 0x0F000000 // uDMA Channel 22 Source Select
+#define UDMA_CHMAP2_CH21SEL_M 0x00F00000 // uDMA Channel 21 Source Select
+#define UDMA_CHMAP2_CH20SEL_M 0x000F0000 // uDMA Channel 20 Source Select
+#define UDMA_CHMAP2_CH19SEL_M 0x0000F000 // uDMA Channel 19 Source Select
+#define UDMA_CHMAP2_CH18SEL_M 0x00000F00 // uDMA Channel 18 Source Select
+#define UDMA_CHMAP2_CH17SEL_M 0x000000F0 // uDMA Channel 17 Source Select
+#define UDMA_CHMAP2_CH16SEL_M 0x0000000F // uDMA Channel 16 Source Select
+#define UDMA_CHMAP2_CH23SEL_S 28
+#define UDMA_CHMAP2_CH22SEL_S 24
+#define UDMA_CHMAP2_CH21SEL_S 20
+#define UDMA_CHMAP2_CH20SEL_S 16
+#define UDMA_CHMAP2_CH19SEL_S 12
+#define UDMA_CHMAP2_CH18SEL_S 8
+#define UDMA_CHMAP2_CH17SEL_S 4
+#define UDMA_CHMAP2_CH16SEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_CHMAP3 register.
+//
+//*****************************************************************************
+#define UDMA_CHMAP3_CH31SEL_M 0xF0000000 // uDMA Channel 31 Source Select
+#define UDMA_CHMAP3_CH30SEL_M 0x0F000000 // uDMA Channel 30 Source Select
+#define UDMA_CHMAP3_CH29SEL_M 0x00F00000 // uDMA Channel 29 Source Select
+#define UDMA_CHMAP3_CH28SEL_M 0x000F0000 // uDMA Channel 28 Source Select
+#define UDMA_CHMAP3_CH27SEL_M 0x0000F000 // uDMA Channel 27 Source Select
+#define UDMA_CHMAP3_CH26SEL_M 0x00000F00 // uDMA Channel 26 Source Select
+#define UDMA_CHMAP3_CH25SEL_M 0x000000F0 // uDMA Channel 25 Source Select
+#define UDMA_CHMAP3_CH24SEL_M 0x0000000F // uDMA Channel 24 Source Select
+#define UDMA_CHMAP3_CH31SEL_S 28
+#define UDMA_CHMAP3_CH30SEL_S 24
+#define UDMA_CHMAP3_CH29SEL_S 20
+#define UDMA_CHMAP3_CH28SEL_S 16
+#define UDMA_CHMAP3_CH27SEL_S 12
+#define UDMA_CHMAP3_CH26SEL_S 8
+#define UDMA_CHMAP3_CH25SEL_S 4
+#define UDMA_CHMAP3_CH24SEL_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the Micro Direct Memory Access (uDMA) offsets.
+//
+//*****************************************************************************
+#define UDMA_O_SRCENDP 0x00000000 // DMA Channel Source Address End
+ // Pointer
+#define UDMA_O_DSTENDP 0x00000004 // DMA Channel Destination Address
+ // End Pointer
+#define UDMA_O_CHCTL 0x00000008 // DMA Channel Control Word
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_SRCENDP register.
+//
+//*****************************************************************************
+#define UDMA_SRCENDP_ADDR_M 0xFFFFFFFF // Source Address End Pointer
+#define UDMA_SRCENDP_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_DSTENDP register.
+//
+//*****************************************************************************
+#define UDMA_DSTENDP_ADDR_M 0xFFFFFFFF // Destination Address End Pointer
+#define UDMA_DSTENDP_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the UDMA_O_CHCTL register.
+//
+//*****************************************************************************
+#define UDMA_CHCTL_DSTINC_M 0xC0000000 // Destination Address Increment
+#define UDMA_CHCTL_DSTINC_8 0x00000000 // Byte
+#define UDMA_CHCTL_DSTINC_16 0x40000000 // Half-word
+#define UDMA_CHCTL_DSTINC_32 0x80000000 // Word
+#define UDMA_CHCTL_DSTINC_NONE 0xC0000000 // No increment
+#define UDMA_CHCTL_DSTSIZE_M 0x30000000 // Destination Data Size
+#define UDMA_CHCTL_DSTSIZE_8 0x00000000 // Byte
+#define UDMA_CHCTL_DSTSIZE_16 0x10000000 // Half-word
+#define UDMA_CHCTL_DSTSIZE_32 0x20000000 // Word
+#define UDMA_CHCTL_SRCINC_M 0x0C000000 // Source Address Increment
+#define UDMA_CHCTL_SRCINC_8 0x00000000 // Byte
+#define UDMA_CHCTL_SRCINC_16 0x04000000 // Half-word
+#define UDMA_CHCTL_SRCINC_32 0x08000000 // Word
+#define UDMA_CHCTL_SRCINC_NONE 0x0C000000 // No increment
+#define UDMA_CHCTL_SRCSIZE_M 0x03000000 // Source Data Size
+#define UDMA_CHCTL_SRCSIZE_8 0x00000000 // Byte
+#define UDMA_CHCTL_SRCSIZE_16 0x01000000 // Half-word
+#define UDMA_CHCTL_SRCSIZE_32 0x02000000 // Word
+#define UDMA_CHCTL_DSTPROT0 0x00200000 // Destination Privilege Access
+#define UDMA_CHCTL_SRCPROT0 0x00040000 // Source Privilege Access
+#define UDMA_CHCTL_ARBSIZE_M 0x0003C000 // Arbitration Size
+#define UDMA_CHCTL_ARBSIZE_1 0x00000000 // 1 Transfer
+#define UDMA_CHCTL_ARBSIZE_2 0x00004000 // 2 Transfers
+#define UDMA_CHCTL_ARBSIZE_4 0x00008000 // 4 Transfers
+#define UDMA_CHCTL_ARBSIZE_8 0x0000C000 // 8 Transfers
+#define UDMA_CHCTL_ARBSIZE_16 0x00010000 // 16 Transfers
+#define UDMA_CHCTL_ARBSIZE_32 0x00014000 // 32 Transfers
+#define UDMA_CHCTL_ARBSIZE_64 0x00018000 // 64 Transfers
+#define UDMA_CHCTL_ARBSIZE_128 0x0001C000 // 128 Transfers
+#define UDMA_CHCTL_ARBSIZE_256 0x00020000 // 256 Transfers
+#define UDMA_CHCTL_ARBSIZE_512 0x00024000 // 512 Transfers
+#define UDMA_CHCTL_ARBSIZE_1024 0x00028000 // 1024 Transfers
+#define UDMA_CHCTL_XFERSIZE_M 0x00003FF0 // Transfer Size (minus 1)
+#define UDMA_CHCTL_NXTUSEBURST 0x00000008 // Next Useburst
+#define UDMA_CHCTL_XFERMODE_M 0x00000007 // uDMA Transfer Mode
+#define UDMA_CHCTL_XFERMODE_STOP \
+ 0x00000000 // Stop
+#define UDMA_CHCTL_XFERMODE_BASIC \
+ 0x00000001 // Basic
+#define UDMA_CHCTL_XFERMODE_AUTO \
+ 0x00000002 // Auto-Request
+#define UDMA_CHCTL_XFERMODE_PINGPONG \
+ 0x00000003 // Ping-Pong
+#define UDMA_CHCTL_XFERMODE_MEM_SG \
+ 0x00000004 // Memory Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_MEM_SGA \
+ 0x00000005 // Alternate Memory Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_PER_SG \
+ 0x00000006 // Peripheral Scatter-Gather
+#define UDMA_CHCTL_XFERMODE_PER_SGA \
+ 0x00000007 // Alternate Peripheral
+ // Scatter-Gather
+#define UDMA_CHCTL_XFERSIZE_S 4
+
+#endif // __HW_UDMA_H__
diff --git a/os/common/ext/TivaWare/inc/hw_usb.h b/os/common/ext/TivaWare/inc/hw_usb.h
new file mode 100644
index 0000000..5d4027a
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_usb.h
@@ -0,0 +1,3032 @@
+//*****************************************************************************
+//
+// hw_usb.h - Macros for use in accessing the USB registers.
+//
+// Copyright (c) 2007-2016 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_USB_H__
+#define __HW_USB_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Univeral Serial Bus register offsets.
+//
+//*****************************************************************************
+#define USB_O_FADDR 0x00000000 // USB Device Functional Address
+#define USB_O_POWER 0x00000001 // USB Power
+#define USB_O_TXIS 0x00000002 // USB Transmit Interrupt Status
+#define USB_O_RXIS 0x00000004 // USB Receive Interrupt Status
+#define USB_O_TXIE 0x00000006 // USB Transmit Interrupt Enable
+#define USB_O_RXIE 0x00000008 // USB Receive Interrupt Enable
+#define USB_O_IS 0x0000000A // USB General Interrupt Status
+#define USB_O_IE 0x0000000B // USB Interrupt Enable
+#define USB_O_FRAME 0x0000000C // USB Frame Value
+#define USB_O_EPIDX 0x0000000E // USB Endpoint Index
+#define USB_O_TEST 0x0000000F // USB Test Mode
+#define USB_O_FIFO0 0x00000020 // USB FIFO Endpoint 0
+#define USB_O_FIFO1 0x00000024 // USB FIFO Endpoint 1
+#define USB_O_FIFO2 0x00000028 // USB FIFO Endpoint 2
+#define USB_O_FIFO3 0x0000002C // USB FIFO Endpoint 3
+#define USB_O_FIFO4 0x00000030 // USB FIFO Endpoint 4
+#define USB_O_FIFO5 0x00000034 // USB FIFO Endpoint 5
+#define USB_O_FIFO6 0x00000038 // USB FIFO Endpoint 6
+#define USB_O_FIFO7 0x0000003C // USB FIFO Endpoint 7
+#define USB_O_DEVCTL 0x00000060 // USB Device Control
+#define USB_O_CCONF 0x00000061 // USB Common Configuration
+#define USB_O_TXFIFOSZ 0x00000062 // USB Transmit Dynamic FIFO Sizing
+#define USB_O_RXFIFOSZ 0x00000063 // USB Receive Dynamic FIFO Sizing
+#define USB_O_TXFIFOADD 0x00000064 // USB Transmit FIFO Start Address
+#define USB_O_RXFIFOADD 0x00000066 // USB Receive FIFO Start Address
+#define USB_O_ULPIVBUSCTL 0x00000070 // USB ULPI VBUS Control
+#define USB_O_ULPIREGDATA 0x00000074 // USB ULPI Register Data
+#define USB_O_ULPIREGADDR 0x00000075 // USB ULPI Register Address
+#define USB_O_ULPIREGCTL 0x00000076 // USB ULPI Register Control
+#define USB_O_EPINFO 0x00000078 // USB Endpoint Information
+#define USB_O_RAMINFO 0x00000079 // USB RAM Information
+#define USB_O_CONTIM 0x0000007A // USB Connect Timing
+#define USB_O_VPLEN 0x0000007B // USB OTG VBUS Pulse Timing
+#define USB_O_HSEOF 0x0000007C // USB High-Speed Last Transaction
+ // to End of Frame Timing
+#define USB_O_FSEOF 0x0000007D // USB Full-Speed Last Transaction
+ // to End of Frame Timing
+#define USB_O_LSEOF 0x0000007E // USB Low-Speed Last Transaction
+ // to End of Frame Timing
+#define USB_O_TXFUNCADDR0 0x00000080 // USB Transmit Functional Address
+ // Endpoint 0
+#define USB_O_TXHUBADDR0 0x00000082 // USB Transmit Hub Address
+ // Endpoint 0
+#define USB_O_TXHUBPORT0 0x00000083 // USB Transmit Hub Port Endpoint 0
+#define USB_O_TXFUNCADDR1 0x00000088 // USB Transmit Functional Address
+ // Endpoint 1
+#define USB_O_TXHUBADDR1 0x0000008A // USB Transmit Hub Address
+ // Endpoint 1
+#define USB_O_TXHUBPORT1 0x0000008B // USB Transmit Hub Port Endpoint 1
+#define USB_O_RXFUNCADDR1 0x0000008C // USB Receive Functional Address
+ // Endpoint 1
+#define USB_O_RXHUBADDR1 0x0000008E // USB Receive Hub Address Endpoint
+ // 1
+#define USB_O_RXHUBPORT1 0x0000008F // USB Receive Hub Port Endpoint 1
+#define USB_O_TXFUNCADDR2 0x00000090 // USB Transmit Functional Address
+ // Endpoint 2
+#define USB_O_TXHUBADDR2 0x00000092 // USB Transmit Hub Address
+ // Endpoint 2
+#define USB_O_TXHUBPORT2 0x00000093 // USB Transmit Hub Port Endpoint 2
+#define USB_O_RXFUNCADDR2 0x00000094 // USB Receive Functional Address
+ // Endpoint 2
+#define USB_O_RXHUBADDR2 0x00000096 // USB Receive Hub Address Endpoint
+ // 2
+#define USB_O_RXHUBPORT2 0x00000097 // USB Receive Hub Port Endpoint 2
+#define USB_O_TXFUNCADDR3 0x00000098 // USB Transmit Functional Address
+ // Endpoint 3
+#define USB_O_TXHUBADDR3 0x0000009A // USB Transmit Hub Address
+ // Endpoint 3
+#define USB_O_TXHUBPORT3 0x0000009B // USB Transmit Hub Port Endpoint 3
+#define USB_O_RXFUNCADDR3 0x0000009C // USB Receive Functional Address
+ // Endpoint 3
+#define USB_O_RXHUBADDR3 0x0000009E // USB Receive Hub Address Endpoint
+ // 3
+#define USB_O_RXHUBPORT3 0x0000009F // USB Receive Hub Port Endpoint 3
+#define USB_O_TXFUNCADDR4 0x000000A0 // USB Transmit Functional Address
+ // Endpoint 4
+#define USB_O_TXHUBADDR4 0x000000A2 // USB Transmit Hub Address
+ // Endpoint 4
+#define USB_O_TXHUBPORT4 0x000000A3 // USB Transmit Hub Port Endpoint 4
+#define USB_O_RXFUNCADDR4 0x000000A4 // USB Receive Functional Address
+ // Endpoint 4
+#define USB_O_RXHUBADDR4 0x000000A6 // USB Receive Hub Address Endpoint
+ // 4
+#define USB_O_RXHUBPORT4 0x000000A7 // USB Receive Hub Port Endpoint 4
+#define USB_O_TXFUNCADDR5 0x000000A8 // USB Transmit Functional Address
+ // Endpoint 5
+#define USB_O_TXHUBADDR5 0x000000AA // USB Transmit Hub Address
+ // Endpoint 5
+#define USB_O_TXHUBPORT5 0x000000AB // USB Transmit Hub Port Endpoint 5
+#define USB_O_RXFUNCADDR5 0x000000AC // USB Receive Functional Address
+ // Endpoint 5
+#define USB_O_RXHUBADDR5 0x000000AE // USB Receive Hub Address Endpoint
+ // 5
+#define USB_O_RXHUBPORT5 0x000000AF // USB Receive Hub Port Endpoint 5
+#define USB_O_TXFUNCADDR6 0x000000B0 // USB Transmit Functional Address
+ // Endpoint 6
+#define USB_O_TXHUBADDR6 0x000000B2 // USB Transmit Hub Address
+ // Endpoint 6
+#define USB_O_TXHUBPORT6 0x000000B3 // USB Transmit Hub Port Endpoint 6
+#define USB_O_RXFUNCADDR6 0x000000B4 // USB Receive Functional Address
+ // Endpoint 6
+#define USB_O_RXHUBADDR6 0x000000B6 // USB Receive Hub Address Endpoint
+ // 6
+#define USB_O_RXHUBPORT6 0x000000B7 // USB Receive Hub Port Endpoint 6
+#define USB_O_TXFUNCADDR7 0x000000B8 // USB Transmit Functional Address
+ // Endpoint 7
+#define USB_O_TXHUBADDR7 0x000000BA // USB Transmit Hub Address
+ // Endpoint 7
+#define USB_O_TXHUBPORT7 0x000000BB // USB Transmit Hub Port Endpoint 7
+#define USB_O_RXFUNCADDR7 0x000000BC // USB Receive Functional Address
+ // Endpoint 7
+#define USB_O_RXHUBADDR7 0x000000BE // USB Receive Hub Address Endpoint
+ // 7
+#define USB_O_RXHUBPORT7 0x000000BF // USB Receive Hub Port Endpoint 7
+#define USB_O_CSRL0 0x00000102 // USB Control and Status Endpoint
+ // 0 Low
+#define USB_O_CSRH0 0x00000103 // USB Control and Status Endpoint
+ // 0 High
+#define USB_O_COUNT0 0x00000108 // USB Receive Byte Count Endpoint
+ // 0
+#define USB_O_TYPE0 0x0000010A // USB Type Endpoint 0
+#define USB_O_NAKLMT 0x0000010B // USB NAK Limit
+#define USB_O_TXMAXP1 0x00000110 // USB Maximum Transmit Data
+ // Endpoint 1
+#define USB_O_TXCSRL1 0x00000112 // USB Transmit Control and Status
+ // Endpoint 1 Low
+#define USB_O_TXCSRH1 0x00000113 // USB Transmit Control and Status
+ // Endpoint 1 High
+#define USB_O_RXMAXP1 0x00000114 // USB Maximum Receive Data
+ // Endpoint 1
+#define USB_O_RXCSRL1 0x00000116 // USB Receive Control and Status
+ // Endpoint 1 Low
+#define USB_O_RXCSRH1 0x00000117 // USB Receive Control and Status
+ // Endpoint 1 High
+#define USB_O_RXCOUNT1 0x00000118 // USB Receive Byte Count Endpoint
+ // 1
+#define USB_O_TXTYPE1 0x0000011A // USB Host Transmit Configure Type
+ // Endpoint 1
+#define USB_O_TXINTERVAL1 0x0000011B // USB Host Transmit Interval
+ // Endpoint 1
+#define USB_O_RXTYPE1 0x0000011C // USB Host Configure Receive Type
+ // Endpoint 1
+#define USB_O_RXINTERVAL1 0x0000011D // USB Host Receive Polling
+ // Interval Endpoint 1
+#define USB_O_TXMAXP2 0x00000120 // USB Maximum Transmit Data
+ // Endpoint 2
+#define USB_O_TXCSRL2 0x00000122 // USB Transmit Control and Status
+ // Endpoint 2 Low
+#define USB_O_TXCSRH2 0x00000123 // USB Transmit Control and Status
+ // Endpoint 2 High
+#define USB_O_RXMAXP2 0x00000124 // USB Maximum Receive Data
+ // Endpoint 2
+#define USB_O_RXCSRL2 0x00000126 // USB Receive Control and Status
+ // Endpoint 2 Low
+#define USB_O_RXCSRH2 0x00000127 // USB Receive Control and Status
+ // Endpoint 2 High
+#define USB_O_RXCOUNT2 0x00000128 // USB Receive Byte Count Endpoint
+ // 2
+#define USB_O_TXTYPE2 0x0000012A // USB Host Transmit Configure Type
+ // Endpoint 2
+#define USB_O_TXINTERVAL2 0x0000012B // USB Host Transmit Interval
+ // Endpoint 2
+#define USB_O_RXTYPE2 0x0000012C // USB Host Configure Receive Type
+ // Endpoint 2
+#define USB_O_RXINTERVAL2 0x0000012D // USB Host Receive Polling
+ // Interval Endpoint 2
+#define USB_O_TXMAXP3 0x00000130 // USB Maximum Transmit Data
+ // Endpoint 3
+#define USB_O_TXCSRL3 0x00000132 // USB Transmit Control and Status
+ // Endpoint 3 Low
+#define USB_O_TXCSRH3 0x00000133 // USB Transmit Control and Status
+ // Endpoint 3 High
+#define USB_O_RXMAXP3 0x00000134 // USB Maximum Receive Data
+ // Endpoint 3
+#define USB_O_RXCSRL3 0x00000136 // USB Receive Control and Status
+ // Endpoint 3 Low
+#define USB_O_RXCSRH3 0x00000137 // USB Receive Control and Status
+ // Endpoint 3 High
+#define USB_O_RXCOUNT3 0x00000138 // USB Receive Byte Count Endpoint
+ // 3
+#define USB_O_TXTYPE3 0x0000013A // USB Host Transmit Configure Type
+ // Endpoint 3
+#define USB_O_TXINTERVAL3 0x0000013B // USB Host Transmit Interval
+ // Endpoint 3
+#define USB_O_RXTYPE3 0x0000013C // USB Host Configure Receive Type
+ // Endpoint 3
+#define USB_O_RXINTERVAL3 0x0000013D // USB Host Receive Polling
+ // Interval Endpoint 3
+#define USB_O_TXMAXP4 0x00000140 // USB Maximum Transmit Data
+ // Endpoint 4
+#define USB_O_TXCSRL4 0x00000142 // USB Transmit Control and Status
+ // Endpoint 4 Low
+#define USB_O_TXCSRH4 0x00000143 // USB Transmit Control and Status
+ // Endpoint 4 High
+#define USB_O_RXMAXP4 0x00000144 // USB Maximum Receive Data
+ // Endpoint 4
+#define USB_O_RXCSRL4 0x00000146 // USB Receive Control and Status
+ // Endpoint 4 Low
+#define USB_O_RXCSRH4 0x00000147 // USB Receive Control and Status
+ // Endpoint 4 High
+#define USB_O_RXCOUNT4 0x00000148 // USB Receive Byte Count Endpoint
+ // 4
+#define USB_O_TXTYPE4 0x0000014A // USB Host Transmit Configure Type
+ // Endpoint 4
+#define USB_O_TXINTERVAL4 0x0000014B // USB Host Transmit Interval
+ // Endpoint 4
+#define USB_O_RXTYPE4 0x0000014C // USB Host Configure Receive Type
+ // Endpoint 4
+#define USB_O_RXINTERVAL4 0x0000014D // USB Host Receive Polling
+ // Interval Endpoint 4
+#define USB_O_TXMAXP5 0x00000150 // USB Maximum Transmit Data
+ // Endpoint 5
+#define USB_O_TXCSRL5 0x00000152 // USB Transmit Control and Status
+ // Endpoint 5 Low
+#define USB_O_TXCSRH5 0x00000153 // USB Transmit Control and Status
+ // Endpoint 5 High
+#define USB_O_RXMAXP5 0x00000154 // USB Maximum Receive Data
+ // Endpoint 5
+#define USB_O_RXCSRL5 0x00000156 // USB Receive Control and Status
+ // Endpoint 5 Low
+#define USB_O_RXCSRH5 0x00000157 // USB Receive Control and Status
+ // Endpoint 5 High
+#define USB_O_RXCOUNT5 0x00000158 // USB Receive Byte Count Endpoint
+ // 5
+#define USB_O_TXTYPE5 0x0000015A // USB Host Transmit Configure Type
+ // Endpoint 5
+#define USB_O_TXINTERVAL5 0x0000015B // USB Host Transmit Interval
+ // Endpoint 5
+#define USB_O_RXTYPE5 0x0000015C // USB Host Configure Receive Type
+ // Endpoint 5
+#define USB_O_RXINTERVAL5 0x0000015D // USB Host Receive Polling
+ // Interval Endpoint 5
+#define USB_O_TXMAXP6 0x00000160 // USB Maximum Transmit Data
+ // Endpoint 6
+#define USB_O_TXCSRL6 0x00000162 // USB Transmit Control and Status
+ // Endpoint 6 Low
+#define USB_O_TXCSRH6 0x00000163 // USB Transmit Control and Status
+ // Endpoint 6 High
+#define USB_O_RXMAXP6 0x00000164 // USB Maximum Receive Data
+ // Endpoint 6
+#define USB_O_RXCSRL6 0x00000166 // USB Receive Control and Status
+ // Endpoint 6 Low
+#define USB_O_RXCSRH6 0x00000167 // USB Receive Control and Status
+ // Endpoint 6 High
+#define USB_O_RXCOUNT6 0x00000168 // USB Receive Byte Count Endpoint
+ // 6
+#define USB_O_TXTYPE6 0x0000016A // USB Host Transmit Configure Type
+ // Endpoint 6
+#define USB_O_TXINTERVAL6 0x0000016B // USB Host Transmit Interval
+ // Endpoint 6
+#define USB_O_RXTYPE6 0x0000016C // USB Host Configure Receive Type
+ // Endpoint 6
+#define USB_O_RXINTERVAL6 0x0000016D // USB Host Receive Polling
+ // Interval Endpoint 6
+#define USB_O_TXMAXP7 0x00000170 // USB Maximum Transmit Data
+ // Endpoint 7
+#define USB_O_TXCSRL7 0x00000172 // USB Transmit Control and Status
+ // Endpoint 7 Low
+#define USB_O_TXCSRH7 0x00000173 // USB Transmit Control and Status
+ // Endpoint 7 High
+#define USB_O_RXMAXP7 0x00000174 // USB Maximum Receive Data
+ // Endpoint 7
+#define USB_O_RXCSRL7 0x00000176 // USB Receive Control and Status
+ // Endpoint 7 Low
+#define USB_O_RXCSRH7 0x00000177 // USB Receive Control and Status
+ // Endpoint 7 High
+#define USB_O_RXCOUNT7 0x00000178 // USB Receive Byte Count Endpoint
+ // 7
+#define USB_O_TXTYPE7 0x0000017A // USB Host Transmit Configure Type
+ // Endpoint 7
+#define USB_O_TXINTERVAL7 0x0000017B // USB Host Transmit Interval
+ // Endpoint 7
+#define USB_O_RXTYPE7 0x0000017C // USB Host Configure Receive Type
+ // Endpoint 7
+#define USB_O_RXINTERVAL7 0x0000017D // USB Host Receive Polling
+ // Interval Endpoint 7
+#define USB_O_DMAINTR 0x00000200 // USB DMA Interrupt
+#define USB_O_DMACTL0 0x00000204 // USB DMA Control 0
+#define USB_O_DMAADDR0 0x00000208 // USB DMA Address 0
+#define USB_O_DMACOUNT0 0x0000020C // USB DMA Count 0
+#define USB_O_DMACTL1 0x00000214 // USB DMA Control 1
+#define USB_O_DMAADDR1 0x00000218 // USB DMA Address 1
+#define USB_O_DMACOUNT1 0x0000021C // USB DMA Count 1
+#define USB_O_DMACTL2 0x00000224 // USB DMA Control 2
+#define USB_O_DMAADDR2 0x00000228 // USB DMA Address 2
+#define USB_O_DMACOUNT2 0x0000022C // USB DMA Count 2
+#define USB_O_DMACTL3 0x00000234 // USB DMA Control 3
+#define USB_O_DMAADDR3 0x00000238 // USB DMA Address 3
+#define USB_O_DMACOUNT3 0x0000023C // USB DMA Count 3
+#define USB_O_DMACTL4 0x00000244 // USB DMA Control 4
+#define USB_O_DMAADDR4 0x00000248 // USB DMA Address 4
+#define USB_O_DMACOUNT4 0x0000024C // USB DMA Count 4
+#define USB_O_DMACTL5 0x00000254 // USB DMA Control 5
+#define USB_O_DMAADDR5 0x00000258 // USB DMA Address 5
+#define USB_O_DMACOUNT5 0x0000025C // USB DMA Count 5
+#define USB_O_DMACTL6 0x00000264 // USB DMA Control 6
+#define USB_O_DMAADDR6 0x00000268 // USB DMA Address 6
+#define USB_O_DMACOUNT6 0x0000026C // USB DMA Count 6
+#define USB_O_DMACTL7 0x00000274 // USB DMA Control 7
+#define USB_O_DMAADDR7 0x00000278 // USB DMA Address 7
+#define USB_O_DMACOUNT7 0x0000027C // USB DMA Count 7
+#define USB_O_RQPKTCOUNT1 0x00000304 // USB Request Packet Count in
+ // Block Transfer Endpoint 1
+#define USB_O_RQPKTCOUNT2 0x00000308 // USB Request Packet Count in
+ // Block Transfer Endpoint 2
+#define USB_O_RQPKTCOUNT3 0x0000030C // USB Request Packet Count in
+ // Block Transfer Endpoint 3
+#define USB_O_RQPKTCOUNT4 0x00000310 // USB Request Packet Count in
+ // Block Transfer Endpoint 4
+#define USB_O_RQPKTCOUNT5 0x00000314 // USB Request Packet Count in
+ // Block Transfer Endpoint 5
+#define USB_O_RQPKTCOUNT6 0x00000318 // USB Request Packet Count in
+ // Block Transfer Endpoint 6
+#define USB_O_RQPKTCOUNT7 0x0000031C // USB Request Packet Count in
+ // Block Transfer Endpoint 7
+#define USB_O_RXDPKTBUFDIS 0x00000340 // USB Receive Double Packet Buffer
+ // Disable
+#define USB_O_TXDPKTBUFDIS 0x00000342 // USB Transmit Double Packet
+ // Buffer Disable
+#define USB_O_CTO 0x00000344 // USB Chirp Timeout
+#define USB_O_HHSRTN 0x00000346 // USB High Speed to UTM Operating
+ // Delay
+#define USB_O_HSBT 0x00000348 // USB High Speed Time-out Adder
+#define USB_O_LPMATTR 0x00000360 // USB LPM Attributes
+#define USB_O_LPMCNTRL 0x00000362 // USB LPM Control
+#define USB_O_LPMIM 0x00000363 // USB LPM Interrupt Mask
+#define USB_O_LPMRIS 0x00000364 // USB LPM Raw Interrupt Status
+#define USB_O_LPMFADDR 0x00000365 // USB LPM Function Address
+#define USB_O_EPC 0x00000400 // USB External Power Control
+#define USB_O_EPCRIS 0x00000404 // USB External Power Control Raw
+ // Interrupt Status
+#define USB_O_EPCIM 0x00000408 // USB External Power Control
+ // Interrupt Mask
+#define USB_O_EPCISC 0x0000040C // USB External Power Control
+ // Interrupt Status and Clear
+#define USB_O_DRRIS 0x00000410 // USB Device RESUME Raw Interrupt
+ // Status
+#define USB_O_DRIM 0x00000414 // USB Device RESUME Interrupt Mask
+#define USB_O_DRISC 0x00000418 // USB Device RESUME Interrupt
+ // Status and Clear
+#define USB_O_GPCS 0x0000041C // USB General-Purpose Control and
+ // Status
+#define USB_O_VDC 0x00000430 // USB VBUS Droop Control
+#define USB_O_VDCRIS 0x00000434 // USB VBUS Droop Control Raw
+ // Interrupt Status
+#define USB_O_VDCIM 0x00000438 // USB VBUS Droop Control Interrupt
+ // Mask
+#define USB_O_VDCISC 0x0000043C // USB VBUS Droop Control Interrupt
+ // Status and Clear
+#define USB_O_IDVRIS 0x00000444 // USB ID Valid Detect Raw
+ // Interrupt Status
+#define USB_O_IDVIM 0x00000448 // USB ID Valid Detect Interrupt
+ // Mask
+#define USB_O_IDVISC 0x0000044C // USB ID Valid Detect Interrupt
+ // Status and Clear
+#define USB_O_DMASEL 0x00000450 // USB DMA Select
+#define USB_O_PP 0x00000FC0 // USB Peripheral Properties
+#define USB_O_PC 0x00000FC4 // USB Peripheral Configuration
+#define USB_O_CC 0x00000FC8 // USB Clock Configuration
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FADDR register.
+//
+//*****************************************************************************
+#define USB_FADDR_M 0x0000007F // Function Address
+#define USB_FADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_POWER register.
+//
+//*****************************************************************************
+#define USB_POWER_ISOUP 0x00000080 // Isochronous Update
+#define USB_POWER_SOFTCONN 0x00000040 // Soft Connect/Disconnect
+#define USB_POWER_HSENAB 0x00000020 // High Speed Enable
+#define USB_POWER_HSMODE 0x00000010 // High Speed Enable
+#define USB_POWER_RESET 0x00000008 // RESET Signaling
+#define USB_POWER_RESUME 0x00000004 // RESUME Signaling
+#define USB_POWER_SUSPEND 0x00000002 // SUSPEND Mode
+#define USB_POWER_PWRDNPHY 0x00000001 // Power Down PHY
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXIS register.
+//
+//*****************************************************************************
+#define USB_TXIS_EP7 0x00000080 // TX Endpoint 7 Interrupt
+#define USB_TXIS_EP6 0x00000040 // TX Endpoint 6 Interrupt
+#define USB_TXIS_EP5 0x00000020 // TX Endpoint 5 Interrupt
+#define USB_TXIS_EP4 0x00000010 // TX Endpoint 4 Interrupt
+#define USB_TXIS_EP3 0x00000008 // TX Endpoint 3 Interrupt
+#define USB_TXIS_EP2 0x00000004 // TX Endpoint 2 Interrupt
+#define USB_TXIS_EP1 0x00000002 // TX Endpoint 1 Interrupt
+#define USB_TXIS_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXIS register.
+//
+//*****************************************************************************
+#define USB_RXIS_EP7 0x00000080 // RX Endpoint 7 Interrupt
+#define USB_RXIS_EP6 0x00000040 // RX Endpoint 6 Interrupt
+#define USB_RXIS_EP5 0x00000020 // RX Endpoint 5 Interrupt
+#define USB_RXIS_EP4 0x00000010 // RX Endpoint 4 Interrupt
+#define USB_RXIS_EP3 0x00000008 // RX Endpoint 3 Interrupt
+#define USB_RXIS_EP2 0x00000004 // RX Endpoint 2 Interrupt
+#define USB_RXIS_EP1 0x00000002 // RX Endpoint 1 Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXIE register.
+//
+//*****************************************************************************
+#define USB_TXIE_EP7 0x00000080 // TX Endpoint 7 Interrupt Enable
+#define USB_TXIE_EP6 0x00000040 // TX Endpoint 6 Interrupt Enable
+#define USB_TXIE_EP5 0x00000020 // TX Endpoint 5 Interrupt Enable
+#define USB_TXIE_EP4 0x00000010 // TX Endpoint 4 Interrupt Enable
+#define USB_TXIE_EP3 0x00000008 // TX Endpoint 3 Interrupt Enable
+#define USB_TXIE_EP2 0x00000004 // TX Endpoint 2 Interrupt Enable
+#define USB_TXIE_EP1 0x00000002 // TX Endpoint 1 Interrupt Enable
+#define USB_TXIE_EP0 0x00000001 // TX and RX Endpoint 0 Interrupt
+ // Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXIE register.
+//
+//*****************************************************************************
+#define USB_RXIE_EP7 0x00000080 // RX Endpoint 7 Interrupt Enable
+#define USB_RXIE_EP6 0x00000040 // RX Endpoint 6 Interrupt Enable
+#define USB_RXIE_EP5 0x00000020 // RX Endpoint 5 Interrupt Enable
+#define USB_RXIE_EP4 0x00000010 // RX Endpoint 4 Interrupt Enable
+#define USB_RXIE_EP3 0x00000008 // RX Endpoint 3 Interrupt Enable
+#define USB_RXIE_EP2 0x00000004 // RX Endpoint 2 Interrupt Enable
+#define USB_RXIE_EP1 0x00000002 // RX Endpoint 1 Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IS register.
+//
+//*****************************************************************************
+#define USB_IS_VBUSERR 0x00000080 // VBUS Error (OTG only)
+#define USB_IS_SESREQ 0x00000040 // SESSION REQUEST (OTG only)
+#define USB_IS_DISCON 0x00000020 // Session Disconnect (OTG only)
+#define USB_IS_CONN 0x00000010 // Session Connect
+#define USB_IS_SOF 0x00000008 // Start of Frame
+#define USB_IS_BABBLE 0x00000004 // Babble Detected
+#define USB_IS_RESET 0x00000004 // RESET Signaling Detected
+#define USB_IS_RESUME 0x00000002 // RESUME Signaling Detected
+#define USB_IS_SUSPEND 0x00000001 // SUSPEND Signaling Detected
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IE register.
+//
+//*****************************************************************************
+#define USB_IE_VBUSERR 0x00000080 // Enable VBUS Error Interrupt (OTG
+ // only)
+#define USB_IE_SESREQ 0x00000040 // Enable Session Request (OTG
+ // only)
+#define USB_IE_DISCON 0x00000020 // Enable Disconnect Interrupt
+#define USB_IE_CONN 0x00000010 // Enable Connect Interrupt
+#define USB_IE_SOF 0x00000008 // Enable Start-of-Frame Interrupt
+#define USB_IE_BABBLE 0x00000004 // Enable Babble Interrupt
+#define USB_IE_RESET 0x00000004 // Enable RESET Interrupt
+#define USB_IE_RESUME 0x00000002 // Enable RESUME Interrupt
+#define USB_IE_SUSPND 0x00000001 // Enable SUSPEND Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FRAME register.
+//
+//*****************************************************************************
+#define USB_FRAME_M 0x000007FF // Frame Number
+#define USB_FRAME_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPIDX register.
+//
+//*****************************************************************************
+#define USB_EPIDX_EPIDX_M 0x0000000F // Endpoint Index
+#define USB_EPIDX_EPIDX_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TEST register.
+//
+//*****************************************************************************
+#define USB_TEST_FORCEH 0x00000080 // Force Host Mode
+#define USB_TEST_FIFOACC 0x00000040 // FIFO Access
+#define USB_TEST_FORCEFS 0x00000020 // Force Full-Speed Mode
+#define USB_TEST_FORCEHS 0x00000010 // Force High-Speed Mode
+#define USB_TEST_TESTPKT 0x00000008 // Test Packet Mode Enable
+#define USB_TEST_TESTK 0x00000004 // Test_K Mode Enable
+#define USB_TEST_TESTJ 0x00000002 // Test_J Mode Enable
+#define USB_TEST_TESTSE0NAK 0x00000001 // Test_SE0_NAK Test Mode Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO0 register.
+//
+//*****************************************************************************
+#define USB_FIFO0_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO0_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO1 register.
+//
+//*****************************************************************************
+#define USB_FIFO1_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO1_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO2 register.
+//
+//*****************************************************************************
+#define USB_FIFO2_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO2_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO3 register.
+//
+//*****************************************************************************
+#define USB_FIFO3_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO3_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO4 register.
+//
+//*****************************************************************************
+#define USB_FIFO4_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO4_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO5 register.
+//
+//*****************************************************************************
+#define USB_FIFO5_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO5_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO6 register.
+//
+//*****************************************************************************
+#define USB_FIFO6_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO6_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FIFO7 register.
+//
+//*****************************************************************************
+#define USB_FIFO7_EPDATA_M 0xFFFFFFFF // Endpoint Data
+#define USB_FIFO7_EPDATA_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DEVCTL register.
+//
+//*****************************************************************************
+#define USB_DEVCTL_DEV 0x00000080 // Device Mode (OTG only)
+#define USB_DEVCTL_FSDEV 0x00000040 // Full-Speed Device Detected
+#define USB_DEVCTL_LSDEV 0x00000020 // Low-Speed Device Detected
+#define USB_DEVCTL_VBUS_M 0x00000018 // VBUS Level (OTG only)
+#define USB_DEVCTL_VBUS_NONE 0x00000000 // Below SessionEnd
+#define USB_DEVCTL_VBUS_SEND 0x00000008 // Above SessionEnd, below AValid
+#define USB_DEVCTL_VBUS_AVALID 0x00000010 // Above AValid, below VBUSValid
+#define USB_DEVCTL_VBUS_VALID 0x00000018 // Above VBUSValid
+#define USB_DEVCTL_HOST 0x00000004 // Host Mode
+#define USB_DEVCTL_HOSTREQ 0x00000002 // Host Request (OTG only)
+#define USB_DEVCTL_SESSION 0x00000001 // Session Start/End (OTG only)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CCONF register.
+//
+//*****************************************************************************
+#define USB_CCONF_TXEDMA 0x00000002 // TX Early DMA Enable
+#define USB_CCONF_RXEDMA 0x00000001 // TX Early DMA Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFIFOSZ register.
+//
+//*****************************************************************************
+#define USB_TXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support
+#define USB_TXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size
+#define USB_TXFIFOSZ_SIZE_8 0x00000000 // 8
+#define USB_TXFIFOSZ_SIZE_16 0x00000001 // 16
+#define USB_TXFIFOSZ_SIZE_32 0x00000002 // 32
+#define USB_TXFIFOSZ_SIZE_64 0x00000003 // 64
+#define USB_TXFIFOSZ_SIZE_128 0x00000004 // 128
+#define USB_TXFIFOSZ_SIZE_256 0x00000005 // 256
+#define USB_TXFIFOSZ_SIZE_512 0x00000006 // 512
+#define USB_TXFIFOSZ_SIZE_1024 0x00000007 // 1024
+#define USB_TXFIFOSZ_SIZE_2048 0x00000008 // 2048
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFIFOSZ register.
+//
+//*****************************************************************************
+#define USB_RXFIFOSZ_DPB 0x00000010 // Double Packet Buffer Support
+#define USB_RXFIFOSZ_SIZE_M 0x0000000F // Max Packet Size
+#define USB_RXFIFOSZ_SIZE_8 0x00000000 // 8
+#define USB_RXFIFOSZ_SIZE_16 0x00000001 // 16
+#define USB_RXFIFOSZ_SIZE_32 0x00000002 // 32
+#define USB_RXFIFOSZ_SIZE_64 0x00000003 // 64
+#define USB_RXFIFOSZ_SIZE_128 0x00000004 // 128
+#define USB_RXFIFOSZ_SIZE_256 0x00000005 // 256
+#define USB_RXFIFOSZ_SIZE_512 0x00000006 // 512
+#define USB_RXFIFOSZ_SIZE_1024 0x00000007 // 1024
+#define USB_RXFIFOSZ_SIZE_2048 0x00000008 // 2048
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFIFOADD
+// register.
+//
+//*****************************************************************************
+#define USB_TXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address
+#define USB_TXFIFOADD_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFIFOADD
+// register.
+//
+//*****************************************************************************
+#define USB_RXFIFOADD_ADDR_M 0x000001FF // Transmit/Receive Start Address
+#define USB_RXFIFOADD_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_ULPIVBUSCTL
+// register.
+//
+//*****************************************************************************
+#define USB_ULPIVBUSCTL_USEEXTVBUSIND \
+ 0x00000002 // Use External VBUS Indicator
+#define USB_ULPIVBUSCTL_USEEXTVBUS \
+ 0x00000001 // Use External VBUS
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_ULPIREGDATA
+// register.
+//
+//*****************************************************************************
+#define USB_ULPIREGDATA_REGDATA_M \
+ 0x000000FF // Register Data
+#define USB_ULPIREGDATA_REGDATA_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_ULPIREGADDR
+// register.
+//
+//*****************************************************************************
+#define USB_ULPIREGADDR_ADDR_M 0x000000FF // Register Address
+#define USB_ULPIREGADDR_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_ULPIREGCTL
+// register.
+//
+//*****************************************************************************
+#define USB_ULPIREGCTL_RDWR 0x00000004 // Read/Write Control
+#define USB_ULPIREGCTL_REGCMPLT 0x00000002 // Register Access Complete
+#define USB_ULPIREGCTL_REGACC 0x00000001 // Initiate Register Access
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPINFO register.
+//
+//*****************************************************************************
+#define USB_EPINFO_RXEP_M 0x000000F0 // RX Endpoints
+#define USB_EPINFO_TXEP_M 0x0000000F // TX Endpoints
+#define USB_EPINFO_RXEP_S 4
+#define USB_EPINFO_TXEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RAMINFO register.
+//
+//*****************************************************************************
+#define USB_RAMINFO_DMACHAN_M 0x000000F0 // DMA Channels
+#define USB_RAMINFO_RAMBITS_M 0x0000000F // RAM Address Bus Width
+#define USB_RAMINFO_DMACHAN_S 4
+#define USB_RAMINFO_RAMBITS_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CONTIM register.
+//
+//*****************************************************************************
+#define USB_CONTIM_WTCON_M 0x000000F0 // Connect Wait
+#define USB_CONTIM_WTID_M 0x0000000F // Wait ID
+#define USB_CONTIM_WTCON_S 4
+#define USB_CONTIM_WTID_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VPLEN register.
+//
+//*****************************************************************************
+#define USB_VPLEN_VPLEN_M 0x000000FF // VBUS Pulse Length
+#define USB_VPLEN_VPLEN_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_HSEOF register.
+//
+//*****************************************************************************
+#define USB_HSEOF_HSEOFG_M 0x000000FF // HIgh-Speed End-of-Frame Gap
+#define USB_HSEOF_HSEOFG_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_FSEOF register.
+//
+//*****************************************************************************
+#define USB_FSEOF_FSEOFG_M 0x000000FF // Full-Speed End-of-Frame Gap
+#define USB_FSEOF_FSEOFG_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LSEOF register.
+//
+//*****************************************************************************
+#define USB_LSEOF_LSEOFG_M 0x000000FF // Low-Speed End-of-Frame Gap
+#define USB_LSEOF_LSEOFG_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR0
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR0_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR0_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR0
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR0_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR0_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT0
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT0_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT0_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR1_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR1_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR1_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR1_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT1
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT1_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT1_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR1_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR1_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR1
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR1_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR1_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT1
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT1_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT1_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR2_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR2_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR2_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR2_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT2
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT2_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT2_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR2_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR2_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR2
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR2_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR2_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT2
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT2_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT2_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR3_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR3_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR3_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR3_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT3
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT3_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT3_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR3_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR3_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR3
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR3_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR3_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT3
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT3_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT3_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR4_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR4_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR4_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR4_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT4
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT4_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT4_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR4_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR4_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR4
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR4_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR4_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT4
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT4_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT4_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR5_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR5_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR5_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR5_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT5
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT5_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT5_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR5_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR5_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR5
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR5_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR5_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT5
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT5_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT5_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR6_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR6_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR6_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR6_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT6
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT6_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT6_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR6_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR6_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR6
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR6_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR6_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT6
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT6_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT6_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXFUNCADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_TXFUNCADDR7_ADDR_M 0x0000007F // Device Address
+#define USB_TXFUNCADDR7_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBADDR7_ADDR_M 0x0000007F // Hub Address
+#define USB_TXHUBADDR7_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXHUBPORT7
+// register.
+//
+//*****************************************************************************
+#define USB_TXHUBPORT7_PORT_M 0x0000007F // Hub Port
+#define USB_TXHUBPORT7_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXFUNCADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_RXFUNCADDR7_ADDR_M 0x0000007F // Device Address
+#define USB_RXFUNCADDR7_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBADDR7
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBADDR7_ADDR_M 0x0000007F // Hub Address
+#define USB_RXHUBADDR7_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXHUBPORT7
+// register.
+//
+//*****************************************************************************
+#define USB_RXHUBPORT7_PORT_M 0x0000007F // Hub Port
+#define USB_RXHUBPORT7_PORT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CSRL0 register.
+//
+//*****************************************************************************
+#define USB_CSRL0_NAKTO 0x00000080 // NAK Timeout
+#define USB_CSRL0_SETENDC 0x00000080 // Setup End Clear
+#define USB_CSRL0_STATUS 0x00000040 // STATUS Packet
+#define USB_CSRL0_RXRDYC 0x00000040 // RXRDY Clear
+#define USB_CSRL0_REQPKT 0x00000020 // Request Packet
+#define USB_CSRL0_STALL 0x00000020 // Send Stall
+#define USB_CSRL0_SETEND 0x00000010 // Setup End
+#define USB_CSRL0_ERROR 0x00000010 // Error
+#define USB_CSRL0_DATAEND 0x00000008 // Data End
+#define USB_CSRL0_SETUP 0x00000008 // Setup Packet
+#define USB_CSRL0_STALLED 0x00000004 // Endpoint Stalled
+#define USB_CSRL0_TXRDY 0x00000002 // Transmit Packet Ready
+#define USB_CSRL0_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CSRH0 register.
+//
+//*****************************************************************************
+#define USB_CSRH0_DISPING 0x00000008 // PING Disable
+#define USB_CSRH0_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_CSRH0_DT 0x00000002 // Data Toggle
+#define USB_CSRH0_FLUSH 0x00000001 // Flush FIFO
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_COUNT0 register.
+//
+//*****************************************************************************
+#define USB_COUNT0_COUNT_M 0x0000007F // FIFO Count
+#define USB_COUNT0_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TYPE0 register.
+//
+//*****************************************************************************
+#define USB_TYPE0_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TYPE0_SPEED_HIGH 0x00000040 // High
+#define USB_TYPE0_SPEED_FULL 0x00000080 // Full
+#define USB_TYPE0_SPEED_LOW 0x000000C0 // Low
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_NAKLMT register.
+//
+//*****************************************************************************
+#define USB_NAKLMT_NAKLMT_M 0x0000001F // EP0 NAK Limit
+#define USB_NAKLMT_NAKLMT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP1 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP1_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL1 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL1_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL1_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL1_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL1_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL1_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL1_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL1_ERROR 0x00000004 // Error
+#define USB_TXCSRL1_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL1_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL1_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH1 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH1_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH1_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH1_MODE 0x00000020 // Mode
+#define USB_TXCSRH1_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH1_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH1_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH1_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH1_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP1 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP1_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP1_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL1 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL1_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL1_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL1_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL1_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL1_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL1_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL1_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL1_OVER 0x00000004 // Overrun
+#define USB_RXCSRL1_ERROR 0x00000004 // Error
+#define USB_RXCSRL1_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL1_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH1 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH1_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH1_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH1_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH1_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH1_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH1_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH1_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH1_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH1_DT 0x00000002 // Data Toggle
+#define USB_RXCSRH1_INCOMPRX 0x00000001 // Incomplete RX Transmission
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT1 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT1_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT1_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE1 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE1_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE1_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE1_SPEED_HIGH 0x00000040 // High
+#define USB_TXTYPE1_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE1_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE1_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE1_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE1_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE1_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE1_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE1_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE1_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL1
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL1_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL1_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL1_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL1_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE1 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE1_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE1_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE1_SPEED_HIGH 0x00000040 // High
+#define USB_RXTYPE1_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE1_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE1_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE1_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE1_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE1_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE1_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE1_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE1_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL1
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL1_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL1_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL1_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL1_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP2 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP2_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL2 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL2_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL2_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL2_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL2_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL2_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL2_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL2_ERROR 0x00000004 // Error
+#define USB_TXCSRL2_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL2_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL2_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH2 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH2_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH2_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH2_MODE 0x00000020 // Mode
+#define USB_TXCSRH2_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH2_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH2_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH2_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH2_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP2 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP2_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP2_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL2 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL2_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL2_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL2_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL2_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL2_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL2_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL2_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL2_ERROR 0x00000004 // Error
+#define USB_RXCSRL2_OVER 0x00000004 // Overrun
+#define USB_RXCSRL2_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL2_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH2 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH2_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH2_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH2_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH2_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH2_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH2_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH2_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH2_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH2_DT 0x00000002 // Data Toggle
+#define USB_RXCSRH2_INCOMPRX 0x00000001 // Incomplete RX Transmission
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT2 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT2_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT2_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE2 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE2_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE2_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE2_SPEED_HIGH 0x00000040 // High
+#define USB_TXTYPE2_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE2_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE2_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE2_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE2_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE2_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE2_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE2_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE2_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL2
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL2_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL2_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL2_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL2_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE2 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE2_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE2_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE2_SPEED_HIGH 0x00000040 // High
+#define USB_RXTYPE2_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE2_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE2_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE2_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE2_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE2_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE2_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE2_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE2_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL2
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL2_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL2_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL2_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL2_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP3 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP3_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL3 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL3_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL3_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL3_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL3_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL3_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL3_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL3_ERROR 0x00000004 // Error
+#define USB_TXCSRL3_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL3_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL3_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH3 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH3_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH3_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH3_MODE 0x00000020 // Mode
+#define USB_TXCSRH3_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH3_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH3_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH3_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH3_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP3 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP3_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP3_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL3 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL3_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL3_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL3_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL3_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL3_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL3_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL3_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL3_ERROR 0x00000004 // Error
+#define USB_RXCSRL3_OVER 0x00000004 // Overrun
+#define USB_RXCSRL3_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL3_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH3 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH3_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH3_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH3_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH3_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH3_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH3_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH3_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH3_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH3_DT 0x00000002 // Data Toggle
+#define USB_RXCSRH3_INCOMPRX 0x00000001 // Incomplete RX Transmission
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT3 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT3_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT3_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE3 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE3_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE3_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE3_SPEED_HIGH 0x00000040 // High
+#define USB_TXTYPE3_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE3_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE3_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE3_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE3_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE3_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE3_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE3_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE3_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL3
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL3_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL3_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL3_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL3_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE3 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE3_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE3_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE3_SPEED_HIGH 0x00000040 // High
+#define USB_RXTYPE3_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE3_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE3_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE3_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE3_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE3_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE3_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE3_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE3_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL3
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL3_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL3_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL3_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL3_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP4 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP4_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL4 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL4_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL4_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL4_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL4_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL4_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL4_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL4_ERROR 0x00000004 // Error
+#define USB_TXCSRL4_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL4_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL4_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH4 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH4_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH4_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH4_MODE 0x00000020 // Mode
+#define USB_TXCSRH4_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH4_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH4_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH4_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH4_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP4 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP4_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP4_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL4 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL4_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL4_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL4_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL4_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL4_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL4_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL4_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL4_OVER 0x00000004 // Overrun
+#define USB_RXCSRL4_ERROR 0x00000004 // Error
+#define USB_RXCSRL4_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL4_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH4 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH4_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH4_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH4_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH4_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH4_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH4_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH4_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH4_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH4_DT 0x00000002 // Data Toggle
+#define USB_RXCSRH4_INCOMPRX 0x00000001 // Incomplete RX Transmission
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT4 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT4_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT4_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE4 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE4_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE4_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE4_SPEED_HIGH 0x00000040 // High
+#define USB_TXTYPE4_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE4_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE4_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE4_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE4_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE4_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE4_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE4_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE4_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL4
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL4_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL4_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL4_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL4_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE4 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE4_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE4_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE4_SPEED_HIGH 0x00000040 // High
+#define USB_RXTYPE4_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE4_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE4_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE4_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE4_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE4_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE4_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE4_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE4_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL4
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL4_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL4_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL4_NAKLMT_S \
+ 0
+#define USB_RXINTERVAL4_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP5 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP5_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL5 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL5_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL5_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL5_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL5_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL5_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL5_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL5_ERROR 0x00000004 // Error
+#define USB_TXCSRL5_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL5_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL5_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH5 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH5_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH5_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH5_MODE 0x00000020 // Mode
+#define USB_TXCSRH5_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH5_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH5_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH5_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH5_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP5 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP5_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP5_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL5 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL5_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL5_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL5_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL5_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL5_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL5_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL5_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL5_ERROR 0x00000004 // Error
+#define USB_RXCSRL5_OVER 0x00000004 // Overrun
+#define USB_RXCSRL5_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL5_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH5 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH5_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH5_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH5_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH5_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH5_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH5_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH5_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH5_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH5_DT 0x00000002 // Data Toggle
+#define USB_RXCSRH5_INCOMPRX 0x00000001 // Incomplete RX Transmission
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT5 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT5_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT5_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE5 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE5_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE5_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE5_SPEED_HIGH 0x00000040 // High
+#define USB_TXTYPE5_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE5_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE5_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE5_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE5_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE5_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE5_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE5_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE5_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL5
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL5_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL5_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL5_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL5_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE5 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE5_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE5_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE5_SPEED_HIGH 0x00000040 // High
+#define USB_RXTYPE5_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE5_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE5_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE5_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE5_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE5_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE5_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE5_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE5_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL5
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL5_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL5_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL5_TXPOLL_S \
+ 0
+#define USB_RXINTERVAL5_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP6 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP6_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL6 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL6_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL6_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL6_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL6_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL6_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL6_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL6_ERROR 0x00000004 // Error
+#define USB_TXCSRL6_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL6_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL6_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH6 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH6_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH6_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH6_MODE 0x00000020 // Mode
+#define USB_TXCSRH6_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH6_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH6_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH6_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH6_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP6 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP6_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP6_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL6 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL6_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL6_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL6_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL6_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL6_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL6_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL6_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL6_ERROR 0x00000004 // Error
+#define USB_RXCSRL6_OVER 0x00000004 // Overrun
+#define USB_RXCSRL6_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL6_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH6 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH6_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH6_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH6_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH6_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH6_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH6_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH6_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH6_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH6_DT 0x00000002 // Data Toggle
+#define USB_RXCSRH6_INCOMPRX 0x00000001 // Incomplete RX Transmission
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT6 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT6_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT6_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE6 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE6_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE6_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE6_SPEED_HIGH 0x00000040 // High
+#define USB_TXTYPE6_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE6_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE6_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE6_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE6_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE6_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE6_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE6_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE6_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL6
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL6_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL6_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL6_TXPOLL_S \
+ 0
+#define USB_TXINTERVAL6_NAKLMT_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE6 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE6_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE6_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE6_SPEED_HIGH 0x00000040 // High
+#define USB_RXTYPE6_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE6_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE6_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE6_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE6_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE6_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE6_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE6_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE6_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL6
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL6_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL6_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL6_NAKLMT_S \
+ 0
+#define USB_RXINTERVAL6_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXMAXP7 register.
+//
+//*****************************************************************************
+#define USB_TXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_TXMAXP7_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRL7 register.
+//
+//*****************************************************************************
+#define USB_TXCSRL7_NAKTO 0x00000080 // NAK Timeout
+#define USB_TXCSRL7_CLRDT 0x00000040 // Clear Data Toggle
+#define USB_TXCSRL7_STALLED 0x00000020 // Endpoint Stalled
+#define USB_TXCSRL7_STALL 0x00000010 // Send STALL
+#define USB_TXCSRL7_SETUP 0x00000010 // Setup Packet
+#define USB_TXCSRL7_FLUSH 0x00000008 // Flush FIFO
+#define USB_TXCSRL7_ERROR 0x00000004 // Error
+#define USB_TXCSRL7_UNDRN 0x00000004 // Underrun
+#define USB_TXCSRL7_FIFONE 0x00000002 // FIFO Not Empty
+#define USB_TXCSRL7_TXRDY 0x00000001 // Transmit Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXCSRH7 register.
+//
+//*****************************************************************************
+#define USB_TXCSRH7_AUTOSET 0x00000080 // Auto Set
+#define USB_TXCSRH7_ISO 0x00000040 // Isochronous Transfers
+#define USB_TXCSRH7_MODE 0x00000020 // Mode
+#define USB_TXCSRH7_DMAEN 0x00000010 // DMA Request Enable
+#define USB_TXCSRH7_FDT 0x00000008 // Force Data Toggle
+#define USB_TXCSRH7_DMAMOD 0x00000004 // DMA Request Mode
+#define USB_TXCSRH7_DTWE 0x00000002 // Data Toggle Write Enable
+#define USB_TXCSRH7_DT 0x00000001 // Data Toggle
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXMAXP7 register.
+//
+//*****************************************************************************
+#define USB_RXMAXP7_MAXLOAD_M 0x000007FF // Maximum Payload
+#define USB_RXMAXP7_MAXLOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRL7 register.
+//
+//*****************************************************************************
+#define USB_RXCSRL7_CLRDT 0x00000080 // Clear Data Toggle
+#define USB_RXCSRL7_STALLED 0x00000040 // Endpoint Stalled
+#define USB_RXCSRL7_REQPKT 0x00000020 // Request Packet
+#define USB_RXCSRL7_STALL 0x00000020 // Send STALL
+#define USB_RXCSRL7_FLUSH 0x00000010 // Flush FIFO
+#define USB_RXCSRL7_DATAERR 0x00000008 // Data Error
+#define USB_RXCSRL7_NAKTO 0x00000008 // NAK Timeout
+#define USB_RXCSRL7_ERROR 0x00000004 // Error
+#define USB_RXCSRL7_OVER 0x00000004 // Overrun
+#define USB_RXCSRL7_FULL 0x00000002 // FIFO Full
+#define USB_RXCSRL7_RXRDY 0x00000001 // Receive Packet Ready
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCSRH7 register.
+//
+//*****************************************************************************
+#define USB_RXCSRH7_AUTOCL 0x00000080 // Auto Clear
+#define USB_RXCSRH7_ISO 0x00000040 // Isochronous Transfers
+#define USB_RXCSRH7_AUTORQ 0x00000040 // Auto Request
+#define USB_RXCSRH7_DMAEN 0x00000020 // DMA Request Enable
+#define USB_RXCSRH7_PIDERR 0x00000010 // PID Error
+#define USB_RXCSRH7_DISNYET 0x00000010 // Disable NYET
+#define USB_RXCSRH7_DMAMOD 0x00000008 // DMA Request Mode
+#define USB_RXCSRH7_DTWE 0x00000004 // Data Toggle Write Enable
+#define USB_RXCSRH7_DT 0x00000002 // Data Toggle
+#define USB_RXCSRH7_INCOMPRX 0x00000001 // Incomplete RX Transmission
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXCOUNT7 register.
+//
+//*****************************************************************************
+#define USB_RXCOUNT7_COUNT_M 0x00001FFF // Receive Packet Count
+#define USB_RXCOUNT7_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXTYPE7 register.
+//
+//*****************************************************************************
+#define USB_TXTYPE7_SPEED_M 0x000000C0 // Operating Speed
+#define USB_TXTYPE7_SPEED_DFLT 0x00000000 // Default
+#define USB_TXTYPE7_SPEED_HIGH 0x00000040 // High
+#define USB_TXTYPE7_SPEED_FULL 0x00000080 // Full
+#define USB_TXTYPE7_SPEED_LOW 0x000000C0 // Low
+#define USB_TXTYPE7_PROTO_M 0x00000030 // Protocol
+#define USB_TXTYPE7_PROTO_CTRL 0x00000000 // Control
+#define USB_TXTYPE7_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_TXTYPE7_PROTO_BULK 0x00000020 // Bulk
+#define USB_TXTYPE7_PROTO_INT 0x00000030 // Interrupt
+#define USB_TXTYPE7_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_TXTYPE7_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXINTERVAL7
+// register.
+//
+//*****************************************************************************
+#define USB_TXINTERVAL7_TXPOLL_M \
+ 0x000000FF // TX Polling
+#define USB_TXINTERVAL7_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_TXINTERVAL7_NAKLMT_S \
+ 0
+#define USB_TXINTERVAL7_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXTYPE7 register.
+//
+//*****************************************************************************
+#define USB_RXTYPE7_SPEED_M 0x000000C0 // Operating Speed
+#define USB_RXTYPE7_SPEED_DFLT 0x00000000 // Default
+#define USB_RXTYPE7_SPEED_HIGH 0x00000040 // High
+#define USB_RXTYPE7_SPEED_FULL 0x00000080 // Full
+#define USB_RXTYPE7_SPEED_LOW 0x000000C0 // Low
+#define USB_RXTYPE7_PROTO_M 0x00000030 // Protocol
+#define USB_RXTYPE7_PROTO_CTRL 0x00000000 // Control
+#define USB_RXTYPE7_PROTO_ISOC 0x00000010 // Isochronous
+#define USB_RXTYPE7_PROTO_BULK 0x00000020 // Bulk
+#define USB_RXTYPE7_PROTO_INT 0x00000030 // Interrupt
+#define USB_RXTYPE7_TEP_M 0x0000000F // Target Endpoint Number
+#define USB_RXTYPE7_TEP_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXINTERVAL7
+// register.
+//
+//*****************************************************************************
+#define USB_RXINTERVAL7_TXPOLL_M \
+ 0x000000FF // RX Polling
+#define USB_RXINTERVAL7_NAKLMT_M \
+ 0x000000FF // NAK Limit
+#define USB_RXINTERVAL7_NAKLMT_S \
+ 0
+#define USB_RXINTERVAL7_TXPOLL_S \
+ 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAINTR register.
+//
+//*****************************************************************************
+#define USB_DMAINTR_CH7 0x00000080 // Channel 7 DMA Interrupt
+#define USB_DMAINTR_CH6 0x00000040 // Channel 6 DMA Interrupt
+#define USB_DMAINTR_CH5 0x00000020 // Channel 5 DMA Interrupt
+#define USB_DMAINTR_CH4 0x00000010 // Channel 4 DMA Interrupt
+#define USB_DMAINTR_CH3 0x00000008 // Channel 3 DMA Interrupt
+#define USB_DMAINTR_CH2 0x00000004 // Channel 2 DMA Interrupt
+#define USB_DMAINTR_CH1 0x00000002 // Channel 1 DMA Interrupt
+#define USB_DMAINTR_CH0 0x00000001 // Channel 0 DMA Interrupt
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL0 register.
+//
+//*****************************************************************************
+#define USB_DMACTL0_BRSTM_M 0x00000600 // Burst Mode
+#define USB_DMACTL0_BRSTM_ANY 0x00000000 // Bursts of unspecified length
+#define USB_DMACTL0_BRSTM_INC4 0x00000200 // INCR4 or unspecified length
+#define USB_DMACTL0_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified
+ // length
+#define USB_DMACTL0_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or
+ // unspecified length
+#define USB_DMACTL0_ERR 0x00000100 // Bus Error Bit
+#define USB_DMACTL0_EP_M 0x000000F0 // Endpoint number
+#define USB_DMACTL0_IE 0x00000008 // DMA Interrupt Enable
+#define USB_DMACTL0_MODE 0x00000004 // DMA Transfer Mode
+#define USB_DMACTL0_DIR 0x00000002 // DMA Direction
+#define USB_DMACTL0_ENABLE 0x00000001 // DMA Transfer Enable
+#define USB_DMACTL0_EP_S 4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR0 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR0_ADDR_M 0xFFFFFFFC // DMA Address
+#define USB_DMAADDR0_ADDR_S 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT0
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT0_COUNT_M 0xFFFFFFFC // DMA Count
+#define USB_DMACOUNT0_COUNT_S 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL1 register.
+//
+//*****************************************************************************
+#define USB_DMACTL1_BRSTM_M 0x00000600 // Burst Mode
+#define USB_DMACTL1_BRSTM_ANY 0x00000000 // Bursts of unspecified length
+#define USB_DMACTL1_BRSTM_INC4 0x00000200 // INCR4 or unspecified length
+#define USB_DMACTL1_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified
+ // length
+#define USB_DMACTL1_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or
+ // unspecified length
+#define USB_DMACTL1_ERR 0x00000100 // Bus Error Bit
+#define USB_DMACTL1_EP_M 0x000000F0 // Endpoint number
+#define USB_DMACTL1_IE 0x00000008 // DMA Interrupt Enable
+#define USB_DMACTL1_MODE 0x00000004 // DMA Transfer Mode
+#define USB_DMACTL1_DIR 0x00000002 // DMA Direction
+#define USB_DMACTL1_ENABLE 0x00000001 // DMA Transfer Enable
+#define USB_DMACTL1_EP_S 4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR1 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR1_ADDR_M 0xFFFFFFFC // DMA Address
+#define USB_DMAADDR1_ADDR_S 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT1
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT1_COUNT_M 0xFFFFFFFC // DMA Count
+#define USB_DMACOUNT1_COUNT_S 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL2 register.
+//
+//*****************************************************************************
+#define USB_DMACTL2_BRSTM_M 0x00000600 // Burst Mode
+#define USB_DMACTL2_BRSTM_ANY 0x00000000 // Bursts of unspecified length
+#define USB_DMACTL2_BRSTM_INC4 0x00000200 // INCR4 or unspecified length
+#define USB_DMACTL2_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified
+ // length
+#define USB_DMACTL2_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or
+ // unspecified length
+#define USB_DMACTL2_ERR 0x00000100 // Bus Error Bit
+#define USB_DMACTL2_EP_M 0x000000F0 // Endpoint number
+#define USB_DMACTL2_IE 0x00000008 // DMA Interrupt Enable
+#define USB_DMACTL2_MODE 0x00000004 // DMA Transfer Mode
+#define USB_DMACTL2_DIR 0x00000002 // DMA Direction
+#define USB_DMACTL2_ENABLE 0x00000001 // DMA Transfer Enable
+#define USB_DMACTL2_EP_S 4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR2 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR2_ADDR_M 0xFFFFFFFC // DMA Address
+#define USB_DMAADDR2_ADDR_S 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT2
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT2_COUNT_M 0xFFFFFFFC // DMA Count
+#define USB_DMACOUNT2_COUNT_S 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL3 register.
+//
+//*****************************************************************************
+#define USB_DMACTL3_BRSTM_M 0x00000600 // Burst Mode
+#define USB_DMACTL3_BRSTM_ANY 0x00000000 // Bursts of unspecified length
+#define USB_DMACTL3_BRSTM_INC4 0x00000200 // INCR4 or unspecified length
+#define USB_DMACTL3_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified
+ // length
+#define USB_DMACTL3_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or
+ // unspecified length
+#define USB_DMACTL3_ERR 0x00000100 // Bus Error Bit
+#define USB_DMACTL3_EP_M 0x000000F0 // Endpoint number
+#define USB_DMACTL3_IE 0x00000008 // DMA Interrupt Enable
+#define USB_DMACTL3_MODE 0x00000004 // DMA Transfer Mode
+#define USB_DMACTL3_DIR 0x00000002 // DMA Direction
+#define USB_DMACTL3_ENABLE 0x00000001 // DMA Transfer Enable
+#define USB_DMACTL3_EP_S 4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR3 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR3_ADDR_M 0xFFFFFFFC // DMA Address
+#define USB_DMAADDR3_ADDR_S 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT3
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT3_COUNT_M 0xFFFFFFFC // DMA Count
+#define USB_DMACOUNT3_COUNT_S 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL4 register.
+//
+//*****************************************************************************
+#define USB_DMACTL4_BRSTM_M 0x00000600 // Burst Mode
+#define USB_DMACTL4_BRSTM_ANY 0x00000000 // Bursts of unspecified length
+#define USB_DMACTL4_BRSTM_INC4 0x00000200 // INCR4 or unspecified length
+#define USB_DMACTL4_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified
+ // length
+#define USB_DMACTL4_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or
+ // unspecified length
+#define USB_DMACTL4_ERR 0x00000100 // Bus Error Bit
+#define USB_DMACTL4_EP_M 0x000000F0 // Endpoint number
+#define USB_DMACTL4_IE 0x00000008 // DMA Interrupt Enable
+#define USB_DMACTL4_MODE 0x00000004 // DMA Transfer Mode
+#define USB_DMACTL4_DIR 0x00000002 // DMA Direction
+#define USB_DMACTL4_ENABLE 0x00000001 // DMA Transfer Enable
+#define USB_DMACTL4_EP_S 4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR4 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR4_ADDR_M 0xFFFFFFFC // DMA Address
+#define USB_DMAADDR4_ADDR_S 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT4
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT4_COUNT_M 0xFFFFFFFC // DMA Count
+#define USB_DMACOUNT4_COUNT_S 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL5 register.
+//
+//*****************************************************************************
+#define USB_DMACTL5_BRSTM_M 0x00000600 // Burst Mode
+#define USB_DMACTL5_BRSTM_ANY 0x00000000 // Bursts of unspecified length
+#define USB_DMACTL5_BRSTM_INC4 0x00000200 // INCR4 or unspecified length
+#define USB_DMACTL5_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified
+ // length
+#define USB_DMACTL5_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or
+ // unspecified length
+#define USB_DMACTL5_ERR 0x00000100 // Bus Error Bit
+#define USB_DMACTL5_EP_M 0x000000F0 // Endpoint number
+#define USB_DMACTL5_IE 0x00000008 // DMA Interrupt Enable
+#define USB_DMACTL5_MODE 0x00000004 // DMA Transfer Mode
+#define USB_DMACTL5_DIR 0x00000002 // DMA Direction
+#define USB_DMACTL5_ENABLE 0x00000001 // DMA Transfer Enable
+#define USB_DMACTL5_EP_S 4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR5 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR5_ADDR_M 0xFFFFFFFC // DMA Address
+#define USB_DMAADDR5_ADDR_S 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT5
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT5_COUNT_M 0xFFFFFFFC // DMA Count
+#define USB_DMACOUNT5_COUNT_S 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL6 register.
+//
+//*****************************************************************************
+#define USB_DMACTL6_BRSTM_M 0x00000600 // Burst Mode
+#define USB_DMACTL6_BRSTM_ANY 0x00000000 // Bursts of unspecified length
+#define USB_DMACTL6_BRSTM_INC4 0x00000200 // INCR4 or unspecified length
+#define USB_DMACTL6_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified
+ // length
+#define USB_DMACTL6_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or
+ // unspecified length
+#define USB_DMACTL6_ERR 0x00000100 // Bus Error Bit
+#define USB_DMACTL6_EP_M 0x000000F0 // Endpoint number
+#define USB_DMACTL6_IE 0x00000008 // DMA Interrupt Enable
+#define USB_DMACTL6_MODE 0x00000004 // DMA Transfer Mode
+#define USB_DMACTL6_DIR 0x00000002 // DMA Direction
+#define USB_DMACTL6_ENABLE 0x00000001 // DMA Transfer Enable
+#define USB_DMACTL6_EP_S 4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR6 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR6_ADDR_M 0xFFFFFFFC // DMA Address
+#define USB_DMAADDR6_ADDR_S 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT6
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT6_COUNT_M 0xFFFFFFFC // DMA Count
+#define USB_DMACOUNT6_COUNT_S 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACTL7 register.
+//
+//*****************************************************************************
+#define USB_DMACTL7_BRSTM_M 0x00000600 // Burst Mode
+#define USB_DMACTL7_BRSTM_ANY 0x00000000 // Bursts of unspecified length
+#define USB_DMACTL7_BRSTM_INC4 0x00000200 // INCR4 or unspecified length
+#define USB_DMACTL7_BRSTM_INC8 0x00000400 // INCR8, INCR4 or unspecified
+ // length
+#define USB_DMACTL7_BRSTM_INC16 0x00000600 // INCR16, INCR8, INCR4 or
+ // unspecified length
+#define USB_DMACTL7_ERR 0x00000100 // Bus Error Bit
+#define USB_DMACTL7_EP_M 0x000000F0 // Endpoint number
+#define USB_DMACTL7_IE 0x00000008 // DMA Interrupt Enable
+#define USB_DMACTL7_MODE 0x00000004 // DMA Transfer Mode
+#define USB_DMACTL7_DIR 0x00000002 // DMA Direction
+#define USB_DMACTL7_ENABLE 0x00000001 // DMA Transfer Enable
+#define USB_DMACTL7_EP_S 4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMAADDR7 register.
+//
+//*****************************************************************************
+#define USB_DMAADDR7_ADDR_M 0xFFFFFFFC // DMA Address
+#define USB_DMAADDR7_ADDR_S 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMACOUNT7
+// register.
+//
+//*****************************************************************************
+#define USB_DMACOUNT7_COUNT_M 0xFFFFFFFC // DMA Count
+#define USB_DMACOUNT7_COUNT_S 2
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT1
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT1_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT1_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT2
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT2_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT2_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT3
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT3_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT3_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT4
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT4_COUNT_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT4_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT5
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT5_COUNT_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT5_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT6
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT6_COUNT_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT6_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RQPKTCOUNT7
+// register.
+//
+//*****************************************************************************
+#define USB_RQPKTCOUNT7_COUNT_M 0x0000FFFF // Block Transfer Packet Count
+#define USB_RQPKTCOUNT7_COUNT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_RXDPKTBUFDIS
+// register.
+//
+//*****************************************************************************
+#define USB_RXDPKTBUFDIS_EP7 0x00000080 // EP7 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP6 0x00000040 // EP6 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP5 0x00000020 // EP5 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP4 0x00000010 // EP4 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP3 0x00000008 // EP3 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP2 0x00000004 // EP2 RX Double-Packet Buffer
+ // Disable
+#define USB_RXDPKTBUFDIS_EP1 0x00000002 // EP1 RX Double-Packet Buffer
+ // Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_TXDPKTBUFDIS
+// register.
+//
+//*****************************************************************************
+#define USB_TXDPKTBUFDIS_EP7 0x00000080 // EP7 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP6 0x00000040 // EP6 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP5 0x00000020 // EP5 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP4 0x00000010 // EP4 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP3 0x00000008 // EP3 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP2 0x00000004 // EP2 TX Double-Packet Buffer
+ // Disable
+#define USB_TXDPKTBUFDIS_EP1 0x00000002 // EP1 TX Double-Packet Buffer
+ // Disable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CTO register.
+//
+//*****************************************************************************
+#define USB_CTO_CCTV_M 0x0000FFFF // Configurable Chirp Timeout Value
+#define USB_CTO_CCTV_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_HHSRTN register.
+//
+//*****************************************************************************
+#define USB_HHSRTN_HHSRTN_M 0x0000FFFF // HIgh Speed to UTM Operating
+ // Delay
+#define USB_HHSRTN_HHSRTN_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_HSBT register.
+//
+//*****************************************************************************
+#define USB_HSBT_HSBT_M 0x0000000F // High Speed Timeout Adder
+#define USB_HSBT_HSBT_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LPMATTR register.
+//
+//*****************************************************************************
+#define USB_LPMATTR_ENDPT_M 0x0000F000 // Endpoint
+#define USB_LPMATTR_RMTWAK 0x00000100 // Remote Wake
+#define USB_LPMATTR_HIRD_M 0x000000F0 // Host Initiated Resume Duration
+#define USB_LPMATTR_LS_M 0x0000000F // Link State
+#define USB_LPMATTR_LS_L1 0x00000001 // Sleep State (L1)
+#define USB_LPMATTR_ENDPT_S 12
+#define USB_LPMATTR_HIRD_S 4
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LPMCNTRL register.
+//
+//*****************************************************************************
+#define USB_LPMCNTRL_NAK 0x00000010 // LPM NAK
+#define USB_LPMCNTRL_EN_M 0x0000000C // LPM Enable
+#define USB_LPMCNTRL_EN_NONE 0x00000000 // LPM and Extended transactions
+ // are not supported. In this case,
+ // the USB does not respond to LPM
+ // transactions and LPM
+ // transactions cause a timeout
+#define USB_LPMCNTRL_EN_EXT 0x00000004 // LPM is not supported but
+ // extended transactions are
+ // supported. In this case, the USB
+ // does respond to an LPM
+ // transaction with a STALL
+#define USB_LPMCNTRL_EN_LPMEXT 0x0000000C // The USB supports LPM extended
+ // transactions. In this case, the
+ // USB responds with a NYET or an
+ // ACK as determined by the value
+ // of TXLPM and other conditions
+#define USB_LPMCNTRL_RES 0x00000002 // LPM Resume
+#define USB_LPMCNTRL_TXLPM 0x00000001 // Transmit LPM Transaction Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LPMIM register.
+//
+//*****************************************************************************
+#define USB_LPMIM_ERR 0x00000020 // LPM Error Interrupt Mask
+#define USB_LPMIM_RES 0x00000010 // LPM Resume Interrupt Mask
+#define USB_LPMIM_NC 0x00000008 // LPM NC Interrupt Mask
+#define USB_LPMIM_ACK 0x00000004 // LPM ACK Interrupt Mask
+#define USB_LPMIM_NY 0x00000002 // LPM NY Interrupt Mask
+#define USB_LPMIM_STALL 0x00000001 // LPM STALL Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LPMRIS register.
+//
+//*****************************************************************************
+#define USB_LPMRIS_ERR 0x00000020 // LPM Interrupt Status
+#define USB_LPMRIS_RES 0x00000010 // LPM Resume Interrupt Status
+#define USB_LPMRIS_NC 0x00000008 // LPM NC Interrupt Status
+#define USB_LPMRIS_ACK 0x00000004 // LPM ACK Interrupt Status
+#define USB_LPMRIS_NY 0x00000002 // LPM NY Interrupt Status
+#define USB_LPMRIS_LPMST 0x00000001 // LPM STALL Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_LPMFADDR register.
+//
+//*****************************************************************************
+#define USB_LPMFADDR_ADDR_M 0x0000007F // LPM Function Address
+#define USB_LPMFADDR_ADDR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPC register.
+//
+//*****************************************************************************
+#define USB_EPC_PFLTACT_M 0x00000300 // Power Fault Action
+#define USB_EPC_PFLTACT_UNCHG 0x00000000 // Unchanged
+#define USB_EPC_PFLTACT_TRIS 0x00000100 // Tristate
+#define USB_EPC_PFLTACT_LOW 0x00000200 // Low
+#define USB_EPC_PFLTACT_HIGH 0x00000300 // High
+#define USB_EPC_PFLTAEN 0x00000040 // Power Fault Action Enable
+#define USB_EPC_PFLTSEN_HIGH 0x00000020 // Power Fault Sense
+#define USB_EPC_PFLTEN 0x00000010 // Power Fault Input Enable
+#define USB_EPC_EPENDE 0x00000004 // EPEN Drive Enable
+#define USB_EPC_EPEN_M 0x00000003 // External Power Supply Enable
+ // Configuration
+#define USB_EPC_EPEN_LOW 0x00000000 // Power Enable Active Low
+#define USB_EPC_EPEN_HIGH 0x00000001 // Power Enable Active High
+#define USB_EPC_EPEN_VBLOW 0x00000002 // Power Enable High if VBUS Low
+ // (OTG only)
+#define USB_EPC_EPEN_VBHIGH 0x00000003 // Power Enable High if VBUS High
+ // (OTG only)
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCRIS register.
+//
+//*****************************************************************************
+#define USB_EPCRIS_PF 0x00000001 // USB Power Fault Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCIM register.
+//
+//*****************************************************************************
+#define USB_EPCIM_PF 0x00000001 // USB Power Fault Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_EPCISC register.
+//
+//*****************************************************************************
+#define USB_EPCISC_PF 0x00000001 // USB Power Fault Interrupt Status
+ // and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRRIS register.
+//
+//*****************************************************************************
+#define USB_DRRIS_RESUME 0x00000001 // RESUME Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRIM register.
+//
+//*****************************************************************************
+#define USB_DRIM_RESUME 0x00000001 // RESUME Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DRISC register.
+//
+//*****************************************************************************
+#define USB_DRISC_RESUME 0x00000001 // RESUME Interrupt Status and
+ // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_GPCS register.
+//
+//*****************************************************************************
+#define USB_GPCS_DEVMOD_M 0x00000007 // Device Mode
+#define USB_GPCS_DEVMOD_OTG 0x00000000 // Use USB0VBUS and USB0ID pin
+#define USB_GPCS_DEVMOD_HOST 0x00000002 // Force USB0VBUS and USB0ID low
+#define USB_GPCS_DEVMOD_DEV 0x00000003 // Force USB0VBUS and USB0ID high
+#define USB_GPCS_DEVMOD_HOSTVBUS \
+ 0x00000004 // Use USB0VBUS and force USB0ID
+ // low
+#define USB_GPCS_DEVMOD_DEVVBUS 0x00000005 // Use USB0VBUS and force USB0ID
+ // high
+#define USB_GPCS_DEVMODOTG 0x00000002 // Enable Device Mode
+#define USB_GPCS_DEVMOD 0x00000001 // Device Mode
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDC register.
+//
+//*****************************************************************************
+#define USB_VDC_VBDEN 0x00000001 // VBUS Droop Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCRIS register.
+//
+//*****************************************************************************
+#define USB_VDCRIS_VD 0x00000001 // VBUS Droop Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCIM register.
+//
+//*****************************************************************************
+#define USB_VDCIM_VD 0x00000001 // VBUS Droop Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_VDCISC register.
+//
+//*****************************************************************************
+#define USB_VDCISC_VD 0x00000001 // VBUS Droop Interrupt Status and
+ // Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IDVRIS register.
+//
+//*****************************************************************************
+#define USB_IDVRIS_ID 0x00000001 // ID Valid Detect Raw Interrupt
+ // Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IDVIM register.
+//
+//*****************************************************************************
+#define USB_IDVIM_ID 0x00000001 // ID Valid Detect Interrupt Mask
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_IDVISC register.
+//
+//*****************************************************************************
+#define USB_IDVISC_ID 0x00000001 // ID Valid Detect Interrupt Status
+ // and Clear
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_DMASEL register.
+//
+//*****************************************************************************
+#define USB_DMASEL_DMACTX_M 0x00F00000 // DMA C TX Select
+#define USB_DMASEL_DMACRX_M 0x000F0000 // DMA C RX Select
+#define USB_DMASEL_DMABTX_M 0x0000F000 // DMA B TX Select
+#define USB_DMASEL_DMABRX_M 0x00000F00 // DMA B RX Select
+#define USB_DMASEL_DMAATX_M 0x000000F0 // DMA A TX Select
+#define USB_DMASEL_DMAARX_M 0x0000000F // DMA A RX Select
+#define USB_DMASEL_DMACTX_S 20
+#define USB_DMASEL_DMACRX_S 16
+#define USB_DMASEL_DMABTX_S 12
+#define USB_DMASEL_DMABRX_S 8
+#define USB_DMASEL_DMAATX_S 4
+#define USB_DMASEL_DMAARX_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_PP register.
+//
+//*****************************************************************************
+#define USB_PP_ECNT_M 0x0000FF00 // Endpoint Count
+#define USB_PP_USB_M 0x000000C0 // USB Capability
+#define USB_PP_USB_DEVICE 0x00000040 // DEVICE
+#define USB_PP_USB_HOSTDEVICE 0x00000080 // HOST
+#define USB_PP_USB_OTG 0x000000C0 // OTG
+#define USB_PP_ULPI 0x00000020 // ULPI Present
+#define USB_PP_PHY 0x00000010 // PHY Present
+#define USB_PP_TYPE_M 0x0000000F // Controller Type
+#define USB_PP_TYPE_0 0x00000000 // The first-generation USB
+ // controller
+#define USB_PP_TYPE_1 0x00000001 // Second-generation USB
+ // controller.The controller
+ // implemented in post Icestorm
+ // devices that use the 3.0 version
+ // of the Mentor controller
+#define USB_PP_ECNT_S 8
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_PC register.
+//
+//*****************************************************************************
+#define USB_PC_ULPIEN 0x00010000 // ULPI Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the USB_O_CC register.
+//
+//*****************************************************************************
+#define USB_CC_CLKEN 0x00000200 // USB Clock Enable
+#define USB_CC_CSD 0x00000100 // Clock Source/Direction
+#define USB_CC_CLKDIV_M 0x0000000F // PLL Clock Divisor
+#define USB_CC_CLKDIV_S 0
+
+#endif // __HW_USB_H__
diff --git a/os/common/ext/TivaWare/inc/hw_watchdog.h b/os/common/ext/TivaWare/inc/hw_watchdog.h
new file mode 100644
index 0000000..f15948b
--- /dev/null
+++ b/os/common/ext/TivaWare/inc/hw_watchdog.h
@@ -0,0 +1,122 @@
+//*****************************************************************************
+//
+// hw_watchdog.h - Macros used when accessing the Watchdog Timer hardware.
+//
+// Copyright (c) 2005-2016 Texas Instruments Incorporated. All rights reserved.
+// Software License Agreement
+//
+// Redistribution and use in source and binary forms, with or without
+// modification, are permitted provided that the following conditions
+// are met:
+//
+// Redistributions of source code must retain the above copyright
+// notice, this list of conditions and the following disclaimer.
+//
+// Redistributions in binary form must reproduce the above copyright
+// notice, this list of conditions and the following disclaimer in the
+// documentation and/or other materials provided with the
+// distribution.
+//
+// Neither the name of Texas Instruments Incorporated nor the names of
+// its contributors may be used to endorse or promote products derived
+// from this software without specific prior written permission.
+//
+// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+//
+// This is part of revision 2.1.3.156 of the Tiva Firmware Development Package.
+//
+//*****************************************************************************
+
+#ifndef __HW_WATCHDOG_H__
+#define __HW_WATCHDOG_H__
+
+//*****************************************************************************
+//
+// The following are defines for the Watchdog Timer register offsets.
+//
+//*****************************************************************************
+#define WDT_O_LOAD 0x00000000 // Watchdog Load
+#define WDT_O_VALUE 0x00000004 // Watchdog Value
+#define WDT_O_CTL 0x00000008 // Watchdog Control
+#define WDT_O_ICR 0x0000000C // Watchdog Interrupt Clear
+#define WDT_O_RIS 0x00000010 // Watchdog Raw Interrupt Status
+#define WDT_O_MIS 0x00000014 // Watchdog Masked Interrupt Status
+#define WDT_O_TEST 0x00000418 // Watchdog Test
+#define WDT_O_LOCK 0x00000C00 // Watchdog Lock
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOAD register.
+//
+//*****************************************************************************
+#define WDT_LOAD_M 0xFFFFFFFF // Watchdog Load Value
+#define WDT_LOAD_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_VALUE register.
+//
+//*****************************************************************************
+#define WDT_VALUE_M 0xFFFFFFFF // Watchdog Value
+#define WDT_VALUE_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_CTL register.
+//
+//*****************************************************************************
+#define WDT_CTL_WRC 0x80000000 // Write Complete
+#define WDT_CTL_INTTYPE 0x00000004 // Watchdog Interrupt Type
+#define WDT_CTL_RESEN 0x00000002 // Watchdog Reset Enable
+#define WDT_CTL_INTEN 0x00000001 // Watchdog Interrupt Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_ICR register.
+//
+//*****************************************************************************
+#define WDT_ICR_M 0xFFFFFFFF // Watchdog Interrupt Clear
+#define WDT_ICR_S 0
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_RIS register.
+//
+//*****************************************************************************
+#define WDT_RIS_WDTRIS 0x00000001 // Watchdog Raw Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_MIS register.
+//
+//*****************************************************************************
+#define WDT_MIS_WDTMIS 0x00000001 // Watchdog Masked Interrupt Status
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_TEST register.
+//
+//*****************************************************************************
+#define WDT_TEST_STALL 0x00000100 // Watchdog Stall Enable
+
+//*****************************************************************************
+//
+// The following are defines for the bit fields in the WDT_O_LOCK register.
+//
+//*****************************************************************************
+#define WDT_LOCK_M 0xFFFFFFFF // Watchdog Lock
+#define WDT_LOCK_UNLOCKED 0x00000000 // Unlocked
+#define WDT_LOCK_LOCKED 0x00000001 // Locked
+#define WDT_LOCK_UNLOCK 0x1ACCE551 // Unlocks the watchdog timer
+
+#endif // __HW_WATCHDOG_H__