diff options
Diffstat (limited to 'demos/STM32')
13 files changed, 294 insertions, 3267 deletions
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.project b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.project index b445991..8f3403e 100644 --- a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.project +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.project @@ -77,14 +77,14 @@ </natures>
<linkedResources>
<link>
- <name>os</name>
+ <name>os-community</name>
<type>2</type>
- <locationURI>CHIBIOS/os</locationURI>
+ <locationURI>PARENT-3-PROJECT_LOC/os</locationURI>
</link>
<link>
- <name>test</name>
+ <name>os-git</name>
<type>2</type>
- <locationURI>CHIBIOS/test</locationURI>
+ <locationURI>PARENT-4-PROJECT_LOC/os</locationURI>
</link>
</linkedResources>
</projectDescription>
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.settings/language.settings.xml b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.settings/language.settings.xml deleted file mode 100644 index cb0455a..0000000 --- a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/.settings/language.settings.xml +++ /dev/null @@ -1,11 +0,0 @@ -<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<project>
- <configuration id="0.114656749" name="Default">
- <extension point="org.eclipse.cdt.core.LanguageSettingsProvider">
- <provider copy-of="extension" id="org.eclipse.cdt.ui.UserLanguageSettingsProvider"/>
- <provider-reference id="org.eclipse.cdt.core.ReferencedProjectsLanguageSettingsProvider" ref="shared-provider"/>
- <provider-reference id="org.eclipse.cdt.managedbuilder.core.MBSLanguageSettingsProvider" ref="shared-provider"/>
- <provider copy-of="extension" id="org.eclipse.cdt.managedbuilder.core.GCCBuildCommandParser"/>
- </extension>
- </configuration>
-</project>
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/Makefile b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/Makefile index 5656ad2..4e53d19 100644 --- a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/Makefile +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/Makefile @@ -120,8 +120,6 @@ CSRC = $(STARTUPSRC) \ ./main.c \
./wolf3d_palette.c \
./res/wolf3d_vgagraph_chunk87.c \
- ./stmdrivers/stm32f4xx_fmc.c \
- ./stmdrivers/stm32f429i_discovery_sdram.c \
# eol
# C++ sources that can be compiled in ARM or THUMB mode depending on the global
@@ -157,7 +155,6 @@ INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \ $(CHIBIOS)/os/hal/lib/streams \
$(CHIBIOS)/community/os/various/devices_lib/lcd \
./res \
- ./stmdrivers \
# eol
#
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/debug/RT-STM32F429-DISCOVERY-DMA2D (Run Only).launch b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/debug/RT-STM32F429-DISCOVERY-DMA2D (OpenOCD, Run Only).launch index 2f1fa66..93158b9 100644 --- a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/debug/RT-STM32F429-DISCOVERY-DMA2D (Run Only).launch +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/debug/RT-STM32F429-DISCOVERY-DMA2D (OpenOCD, Run Only).launch @@ -1,52 +1,52 @@ -<?xml version="1.0" encoding="UTF-8" standalone="no"?>
-<launchConfiguration type="org.eclipse.cdt.debug.gdbjtag.launchConfigurationType">
-<stringAttribute key="bad_container_name" value="\RT-STM32F429-DISCOVERY-DMA2D\debug"/>
-<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="1"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="true"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value="set remotetimeout 20 monitor reset init monitor sleep 50 "/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="Generic TCP/IP"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/>
-<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/>
-<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/>
-<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/>
-<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="arm-none-eabi-gdb"/>
-<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard"/>
-<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/>
-<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/>
-<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/>
-<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/>
-<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/>
-<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/>
-<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?><contentList/>"/>
-<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <globalVariableList/> "/>
-<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList/> "/>
-<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="./build/ch.elf"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="RT-STM32F429-DISCOVERY-DMA2D"/>
-<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/>
-<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="0.114656749"/>
-<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS">
-<listEntry value="/RT-STM32F429-DISCOVERY-DMA2D"/>
-</listAttribute>
-<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES">
-<listEntry value="4"/>
-</listAttribute>
-<listAttribute key="org.eclipse.debug.ui.favoriteGroups">
-<listEntry value="org.eclipse.debug.ui.launchGroup.debug"/>
-</listAttribute>
-</launchConfiguration>
+<?xml version="1.0" encoding="UTF-8" standalone="no"?> +<launchConfiguration type="org.eclipse.cdt.debug.gdbjtag.launchConfigurationType"> +<stringAttribute key="bad_container_name" value="\RT-STM32F429-DISCOVERY-DMA2D\debug"/> +<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.delay" value="1"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doHalt" value="true"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.doReset" value="true"/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.initCommands" value="set remotetimeout 20 monitor reset init monitor sleep 50 "/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.jtagDevice" value="Generic TCP/IP"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadImage" value="false"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.loadSymbols" value="true"/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.pcRegister" value=""/> +<intAttribute key="org.eclipse.cdt.debug.gdbjtag.core.portNumber" value="3333"/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.runCommands" value=""/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setPcRegister" value="false"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setResume" value="true"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.setStopAt" value="true"/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.stopAt" value="main"/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsFileName" value=""/> +<stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.symbolsOffset" value=""/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForImage" value="false"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useFileForSymbols" value="false"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForImage" value="true"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useProjBinaryForSymbols" value="true"/> +<booleanAttribute key="org.eclipse.cdt.debug.gdbjtag.core.useRemoteTarget" value="true"/> +<stringAttribute key="org.eclipse.cdt.debug.mi.core.DEBUG_NAME" value="arm-none-eabi-gdb"/> +<stringAttribute key="org.eclipse.cdt.debug.mi.core.commandFactory" value="Standard"/> +<stringAttribute key="org.eclipse.cdt.debug.mi.core.protocol" value="mi"/> +<booleanAttribute key="org.eclipse.cdt.debug.mi.core.verboseMode" value="false"/> +<stringAttribute key="org.eclipse.cdt.dsf.gdb.DEBUG_NAME" value="arm-none-eabi-gdb"/> +<intAttribute key="org.eclipse.cdt.launch.ATTR_BUILD_BEFORE_LAUNCH_ATTR" value="2"/> +<stringAttribute key="org.eclipse.cdt.launch.COREFILE_PATH" value=""/> +<stringAttribute key="org.eclipse.cdt.launch.DEBUGGER_REGISTER_GROUPS" value=""/> +<stringAttribute key="org.eclipse.cdt.launch.FORMAT" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?><contentList/>"/> +<stringAttribute key="org.eclipse.cdt.launch.GLOBAL_VARIABLES" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <globalVariableList/> "/> +<stringAttribute key="org.eclipse.cdt.launch.MEMORY_BLOCKS" value="<?xml version="1.0" encoding="UTF-8" standalone="no"?> <memoryBlockExpressionList/> "/> +<stringAttribute key="org.eclipse.cdt.launch.PROGRAM_NAME" value="./build/ch.elf"/> +<stringAttribute key="org.eclipse.cdt.launch.PROJECT_ATTR" value="RT-STM32F429-DISCOVERY-DMA2D"/> +<booleanAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_AUTO_ATTR" value="true"/> +<stringAttribute key="org.eclipse.cdt.launch.PROJECT_BUILD_CONFIG_ID_ATTR" value="0.114656749"/> +<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_PATHS"> +<listEntry value="/RT-STM32F429-DISCOVERY-DMA2D"/> +</listAttribute> +<listAttribute key="org.eclipse.debug.core.MAPPED_RESOURCE_TYPES"> +<listEntry value="4"/> +</listAttribute> +<listAttribute key="org.eclipse.debug.ui.favoriteGroups"> +<listEntry value="org.eclipse.debug.ui.launchGroup.debug"/> +</listAttribute> +</launchConfiguration> diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/halconf.h b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/halconf.h index e9ab9d7..a0b3a2e 100644 --- a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/halconf.h +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/halconf.h @@ -329,6 +329,12 @@ #define SPI_USE_MUTUAL_EXCLUSION TRUE
#endif
+/*===========================================================================*/
+/* Community drivers' includes */
+/*===========================================================================*/
+
+#include "halconf_community.h"
+
#endif /* _HALCONF_H_ */
/** @} */
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/halconf_community.h b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/halconf_community.h new file mode 100644 index 0000000..44e89df --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/halconf_community.h @@ -0,0 +1,70 @@ +/* + ChibiOS - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _HALCONF_COMMUNITY_H_ +#define _HALCONF_COMMUNITY_H_ + +/** + * @brief Enables the community overlay. + */ +#if !defined(HAL_USE_COMMUNITY) || defined(__DOXYGEN__) +#define HAL_USE_COMMUNITY TRUE +#endif + +/** + * @brief Enables the NAND subsystem. + */ +#if !defined(HAL_USE_NAND) || defined(__DOXYGEN__) +#define HAL_USE_NAND FALSE +#endif + +/** + * @brief Enables the 1-wire subsystem. + */ +#if !defined(HAL_USE_ONEWIRE) || defined(__DOXYGEN__) +#define HAL_USE_ONEWIRE FALSE +#endif + +/*===========================================================================*/ +/* FSMCNAND driver related settings. */ +/*===========================================================================*/ + +/** + * @brief Enables the @p nandAcquireBus() and @p nanReleaseBus() APIs. + * @note Disabling this option saves both code and data space. + */ +#if !defined(NAND_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__) +#define NAND_USE_MUTUAL_EXCLUSION TRUE +#endif + +/*===========================================================================*/ +/* 1-wire driver related settings. */ +/*===========================================================================*/ +/** + * @brief Enables strong pull up feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_STRONG_PULLUP FALSE + +/** + * @brief Enables search ROM feature. + * @note Disabling this option saves both code and data space. + */ +#define ONEWIRE_USE_SEARCH_ROM TRUE + +#endif /* _HALCONF_COMMUNITY_H_ */ + +/** @} */ diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c index 4e8ad57..a8f8007 100644 --- a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/main.c @@ -24,15 +24,138 @@ #include "usbcfg.h"
#endif
-#include "stmdrivers/stm32f429i_discovery_sdram.h"
-#include "stmdrivers/stm32f4xx_fmc.h"
-
+#include "fsmc_sdram.h"
#include "ili9341.h"
#include "stm32_ltdc.h"
#include "stm32_dma2d.h"
#include "res/wolf3d_vgagraph_chunk87.h"
+/*===========================================================================*/
+/* SDRAM related. */
+/*===========================================================================*/
+
+// TODO: Move constants below elsewhere, and normalize their name
+
+/* SDRAM bank base address.*/
+#define SDRAM_BANK_ADDR ((uint32_t)0xD0000000)
+
+/*
+ * FMC SDRAM Mode definition register defines
+ */
+#define FMC_SDCMR_MRD_BURST_LENGTH_1 ((uint16_t)0x0000)
+#define FMC_SDCMR_MRD_BURST_LENGTH_2 ((uint16_t)0x0001)
+#define FMC_SDCMR_MRD_BURST_LENGTH_4 ((uint16_t)0x0002)
+#define FMC_SDCMR_MRD_BURST_LENGTH_8 ((uint16_t)0x0004)
+#define FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
+#define FMC_SDCMR_MRD_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
+#define FMC_SDCMR_MRD_CAS_LATENCY_2 ((uint16_t)0x0020)
+#define FMC_SDCMR_MRD_CAS_LATENCY_3 ((uint16_t)0x0030)
+#define FMC_SDCMR_MRD_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
+#define FMC_SDCMR_MRD_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
+#define FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
+
+/*
+ * FMC_ReadPipe_Delay
+ */
+#define FMC_ReadPipe_Delay_0 ((uint32_t)0x00000000)
+#define FMC_ReadPipe_Delay_1 ((uint32_t)0x00002000)
+#define FMC_ReadPipe_Delay_2 ((uint32_t)0x00004000)
+#define FMC_ReadPipe_Delay_Mask ((uint32_t)0x00006000)
+
+/*
+ * FMC_Read_Burst
+ */
+#define FMC_Read_Burst_Disable ((uint32_t)0x00000000)
+#define FMC_Read_Burst_Enable ((uint32_t)0x00001000)
+#define FMC_Read_Burst_Mask ((uint32_t)0x00001000)
+
+/*
+ * FMC_SDClock_Period
+ */
+#define FMC_SDClock_Disable ((uint32_t)0x00000000)
+#define FMC_SDClock_Period_2 ((uint32_t)0x00000800)
+#define FMC_SDClock_Period_3 ((uint32_t)0x00000C00)
+#define FMC_SDClock_Period_Mask ((uint32_t)0x00000C00)
+
+/*
+ * FMC_ColumnBits_Number
+ */
+#define FMC_ColumnBits_Number_8b ((uint32_t)0x00000000)
+#define FMC_ColumnBits_Number_9b ((uint32_t)0x00000001)
+#define FMC_ColumnBits_Number_10b ((uint32_t)0x00000002)
+#define FMC_ColumnBits_Number_11b ((uint32_t)0x00000003)
+
+/*
+ * FMC_RowBits_Number
+ */
+#define FMC_RowBits_Number_11b ((uint32_t)0x00000000)
+#define FMC_RowBits_Number_12b ((uint32_t)0x00000004)
+#define FMC_RowBits_Number_13b ((uint32_t)0x00000008)
+
+/*
+ * FMC_SDMemory_Data_Width
+ */
+#define FMC_SDMemory_Width_8b ((uint32_t)0x00000000)
+#define FMC_SDMemory_Width_16b ((uint32_t)0x00000010)
+#define FMC_SDMemory_Width_32b ((uint32_t)0x00000020)
+
+/*
+ * FMC_InternalBank_Number
+ */
+#define FMC_InternalBank_Number_2 ((uint32_t)0x00000000)
+#define FMC_InternalBank_Number_4 ((uint32_t)0x00000040)
+
+/*
+ * FMC_CAS_Latency
+ */
+#define FMC_CAS_Latency_1 ((uint32_t)0x00000080)
+#define FMC_CAS_Latency_2 ((uint32_t)0x00000100)
+#define FMC_CAS_Latency_3 ((uint32_t)0x00000180)
+
+/*
+ * FMC_Write_Protection
+ */
+#define FMC_Write_Protection_Disable ((uint32_t)0x00000000)
+#define FMC_Write_Protection_Enable ((uint32_t)0x00000200)
+
+/*
+ * SDRAM driver configuration structure.
+ */
+static const SDRAMConfig sdram_cfg = {
+ .sdcr = (uint32_t)(FMC_ColumnBits_Number_8b |
+ FMC_RowBits_Number_12b |
+ FMC_SDMemory_Width_16b |
+ FMC_InternalBank_Number_4 |
+ FMC_CAS_Latency_3 |
+ FMC_Write_Protection_Disable |
+ FMC_SDClock_Period_2 |
+ FMC_Read_Burst_Disable |
+ FMC_ReadPipe_Delay_1),
+
+ .sdtr = (uint32_t)((2 - 1) | // FMC_LoadToActiveDelay = 2 (TMRD: 2 Clock cycles)
+ (7 << 4) | // FMC_ExitSelfRefreshDelay = 7 (TXSR: min=70ns (7x11.11ns))
+ (4 << 8) | // FMC_SelfRefreshTime = 4 (TRAS: min=42ns (4x11.11ns) max=120k (ns))
+ (7 << 12) | // FMC_RowCycleDelay = 7 (TRC: min=70 (7x11.11ns))
+ (2 << 16) | // FMC_WriteRecoveryTime = 2 (TWR: min=1+ 7ns (1+1x11.11ns))
+ (2 << 20) | // FMC_RPDelay = 2 (TRP: 20ns => 2x11.11ns)
+ (2 << 24)), // FMC_RCDDelay = 2 (TRCD: 20ns => 2x11.11ns)
+
+ .sdcmr = (uint32_t)(((4 - 1) << 5) |
+ ((FMC_SDCMR_MRD_BURST_LENGTH_2 |
+ FMC_SDCMR_MRD_BURST_TYPE_SEQUENTIAL |
+ FMC_SDCMR_MRD_CAS_LATENCY_3 |
+ FMC_SDCMR_MRD_OPERATING_MODE_STANDARD |
+ FMC_SDCMR_MRD_WRITEBURST_MODE_SINGLE) << 9)),
+
+ /* if (STM32_SYSCLK == 180000000) ->
+ 64ms / 4096 = 15.625us
+ 15.625us * 90MHz = 1406 - 20 = 1386 */
+ //.sdrtr = (1386 << 1),
+ .sdrtr = (uint32_t)(683 << 1),
+};
+
+/* SDRAM size, in bytes.*/
#define IS42S16400J_SIZE (8 * 1024 * 1024)
/*
@@ -424,251 +547,11 @@ static void cmd_reset(BaseSequentialStream *chp, int argc, char *argv[]) { NVIC_SystemReset();
}
-static void cmd_write(BaseSequentialStream *chp, int argc, char *argv[]) {
- uint32_t counter = 0;
- uint8_t ubWritedata_8b = 0x3C;
- uint32_t uwReadwritestatus = 0;
- time_measurement_t tm;
-
-
- (void)argv;
- if (argc > 0) {
- chprintf(chp, "Usage: write\r\n");
- return;
- }
-
- chTMObjectInit(&tm);
-
- chTMStartMeasurementX(&tm);
-
- /* Write data value to all SDRAM memory */
- for (counter = 0; counter < IS42S16400J_SIZE; counter++)
- {
- *(volatile uint8_t*) (SDRAM_BANK_ADDR + counter) = (uint8_t)(ubWritedata_8b + counter);
- }
-
- chTMStopMeasurementX(&tm);
- uint32_t write_ms = RTT2MS(tm.last);
-
- if (!uwReadwritestatus) {
- chprintf(chp, "SDRAM written in %dms.\r\n", write_ms);
- }
-
-}
-
-static void cmd_erase(BaseSequentialStream *chp, int argc, char *argv[]) {
- uint32_t counter = 0;
- uint32_t uwReadwritestatus = 0;
- time_measurement_t tm;
-
-
- (void)argv;
- if (argc > 0) {
- chprintf(chp, "Usage: erase\r\n");
- return;
- }
-
- chTMObjectInit(&tm);
-
- //XXX chTMStartMeasurement(&tm);
-
- /* Write data value to all SDRAM memory */
- /* Erase SDRAM memory */
- for (counter = 0; counter < IS42S16400J_SIZE; counter++)
- {
- *(volatile uint8_t*) (SDRAM_BANK_ADDR + counter) = (uint8_t)0x0;
- }
-
- //XXX chTMStopMeasurement(&tm);
- uint32_t write_ms = 0;//XXX RTT2MS(tm.last);
-
- if (!uwReadwritestatus) {
- chprintf(chp, "SDRAM erased in %dms.\r\n", write_ms);
- }
-
-}
-
-static void cmd_selfrefresh(BaseSequentialStream *chp, int argc, char *argv[]) {
- (void)argv;
-
- FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure;
-
- if (argc > 0) {
- chprintf(chp, "Usage: selfrefresh\r\n");
- return;
- }
-
- /* Program a self-refresh mode command */
- FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_Selfrefresh;
- FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
- FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
- FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
-
- /* Send the command */
- FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
-
- /* Wait until the SDRAM controller is ready */
- while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) {
- }
-
- /* Check the bank mode status */
- if(FMC_GetModeStatus(FMC_Bank2_SDRAM) != FMC_SelfRefreshMode_Status) {
- chprintf(chp, "SDRAM is not in self refresh mode, command FAILED.\r\n");
- } else {
- chprintf(chp, "SDRAM is in self refresh mode.\r\n");
- }
-
-}
-
-static void cmd_normal(BaseSequentialStream *chp, int argc, char *argv[]) {
- (void)argv;
-
- FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure;
-
- if (argc > 0) {
- chprintf(chp, "Usage: normal\r\n");
- return;
- }
-
- /* Program a self-refresh mode command */
- FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_normal;
- FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
- FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
- FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
-
- /* Send the command */
- FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
-
- /* Wait until the SDRAM controller is ready */
- while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET) {
- }
-
- /* Check the bank mode status */
- if(FMC_GetModeStatus(FMC_Bank2_SDRAM) != FMC_NormalMode_Status) {
- chprintf(chp, "SDRAM is not in normal mode, command FAILED.\r\n");
- } else {
- chprintf(chp, "SDRAM is in normal mode.\r\n");
- }
-
-}
-
-static void cmd_check(BaseSequentialStream *chp, int argc, char *argv[]) {
- uint32_t counter = 0;
- uint8_t ubWritedata_8b = 0x3C, ubReaddata_8b = 0;
- uint32_t uwReadwritestatus = 0;
- time_measurement_t tm;
-
-
- (void)argv;
- if (argc > 0) {
- chprintf(chp, "Usage: check\r\n");
- return;
- }
-
- chTMObjectInit(&tm);
-
- chTMStartMeasurementX(&tm);
-
- /* Read back SDRAM memory and check content correctness*/
- counter = 0;
- uwReadwritestatus = 0;
- while ((counter < IS42S16400J_SIZE) && (uwReadwritestatus == 0))
- {
- ubReaddata_8b = *(volatile uint8_t*)(SDRAM_BANK_ADDR + counter);
- if ( ubReaddata_8b != (uint8_t)(ubWritedata_8b + counter))
- {
- uwReadwritestatus = 1;
- chprintf(chp, "Error at %d, expected %d but read %d.\r\n", counter, ubWritedata_8b + counter, ubReaddata_8b);
- }
- counter++;
- }
-
- chTMStopMeasurementX(&tm);
- uint32_t check_ms = RTT2MS(tm.last);
-
- //FIXME time this
- if (!uwReadwritestatus) {
- chprintf(chp, "SDRAM read and check completed successfully in %dms.\r\n", check_ms);
- }
-
-}
-
-static void cmd_sdram(BaseSequentialStream *chp, int argc, char *argv[]) {
- uint32_t counter = 0;
- uint8_t ubWritedata_8b = 0x3C, ubReaddata_8b = 0;
- uint32_t uwReadwritestatus = 0;
- time_measurement_t tm;
-
-
- (void)argv;
- if (argc > 0) {
- chprintf(chp, "Usage: sdram\r\n");
- return;
- }
-
- chTMObjectInit(&tm);
-
- chTMStartMeasurementX(&tm);
-
-// /* Erase SDRAM memory */
-// for (counter = 0; counter < IS42S16400J_SIZE; counter++)
-// {
-// *(volatile uint8_t*) (SDRAM_BANK_ADDR + counter) = (uint8_t)0x0;
-// }
-
- /* Write data value to all SDRAM memory */
- for (counter = 0; counter < IS42S16400J_SIZE; counter++)
- {
- *(volatile uint8_t*) (SDRAM_BANK_ADDR + counter) = (uint8_t)(ubWritedata_8b + counter);
- }
-
- chTMStopMeasurementX(&tm);
- uint32_t write_ms = RTT2MS(tm.last);
-
- chTMStartMeasurementX(&tm);
-
- /* Read back SDRAM memory */
- counter = 0;
- while ((counter < IS42S16400J_SIZE))
- {
- ubReaddata_8b = *(volatile uint8_t*)(SDRAM_BANK_ADDR + counter);
- counter++;
- }
-
- chTMStopMeasurementX(&tm);
- uint32_t read_ms = RTT2MS(tm.last);
-
- /* Read back SDRAM memory and check content correctness*/
- counter = 0;
- uwReadwritestatus = 0;
- while ((counter < IS42S16400J_SIZE) && (uwReadwritestatus == 0))
- {
- ubReaddata_8b = *(volatile uint8_t*)(SDRAM_BANK_ADDR + counter);
- if ( ubReaddata_8b != (uint8_t)(ubWritedata_8b + counter))
- {
- uwReadwritestatus = 1;
- chprintf(chp, "Error at %d, expected %d but read %d.\r\n", counter, ubWritedata_8b + counter, ubReaddata_8b);
- }
- counter++;
- }
-
- if (!uwReadwritestatus) {
- chprintf(chp, "SDRAM test completed successfully, writing entire memory took %dms, reading it took %dms.\r\n", write_ms, read_ms);
- }
-
-}
-
static const ShellCommand commands[] = {
{"mem", cmd_mem},
{"threads", cmd_threads},
{"test", cmd_test},
- {"sdram", cmd_sdram},
{"reset", cmd_reset},
- {"write", cmd_write},
- {"check", cmd_check},
- {"erase", cmd_erase},
- {"selfrefresh", cmd_selfrefresh},
- {"normal", cmd_normal},
{NULL, NULL}
};
@@ -730,10 +613,10 @@ int main(void) { #endif /* HAL_USE_SERIAL_USB */
/*
- * Initialise SDRAM, board.h has already configured GPIO correctly
- * (except that ST example uses 50MHz not 100MHz?)
+ * Initialise FSMC for SDRAM.
*/
- SDRAM_Init();
+ fsmcSdramInit();
+ fsmcSdramStart(&SDRAMD, &sdram_cfg);
sdram_bulk_erase();
/*
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf.h b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf.h index bac6cad..7aab0c4 100644 --- a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf.h +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf.h @@ -352,4 +352,9 @@ #define STM32_DMA2D_USE_DMA2D TRUE
#define STM32_DMA2D_IRQ_PRIORITY 11
+/*
+ * Header for community drivers.
+ */
+#include "mcuconf_community.h"
+
#endif /* _MCUCONF_H_ */
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf_community.h b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf_community.h new file mode 100644 index 0000000..81c7e2c --- /dev/null +++ b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/mcuconf_community.h @@ -0,0 +1,28 @@ +/* + ChibiOS/RT - Copyright (C) 2014 Uladzimir Pylinsky aka barthess + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * FSMC driver system settings. + */ +#define STM32_FSMC_USE_FSMC1 TRUE +#define STM32_FSMC_FSMC1_IRQ_PRIORITY 10 + +/* + * FSMC SDRAM driver system settings. + */ +#define STM32_USE_FSMC_SDRAM TRUE +#define STM32_SDRAM_USE_FSMC_SDRAM1 FALSE +#define STM32_SDRAM_USE_FSMC_SDRAM2 TRUE diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/stmdrivers/stm32f429i_discovery_sdram.c b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/stmdrivers/stm32f429i_discovery_sdram.c deleted file mode 100644 index 77d9a15..0000000 --- a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/stmdrivers/stm32f429i_discovery_sdram.c +++ /dev/null @@ -1,332 +0,0 @@ -#include "ch.h"
-#include "hal.h"
-#include "stm32f429i_discovery_sdram.h"
-#include "stm32f4xx_fmc.h"
-
-/**
- * @brief Configures the FMC and GPIOs to interface with the SDRAM memory.
- * This function must be called before any read/write operation
- * on the SDRAM.
- * @param None
- * @retval None
- */
-void SDRAM_Init(void)
-{
- FMC_SDRAMInitTypeDef FMC_SDRAMInitStructure;
- FMC_SDRAMTimingInitTypeDef FMC_SDRAMTimingInitStructure;
-
- /* Enable FMC clock */
- rccEnableAHB3(RCC_AHB3ENR_FMCEN, FALSE);
-
-/* FMC Configuration ---------------------------------------------------------*/
-/* FMC SDRAM Bank configuration */
- /* Timing configuration for 84 Mhz of SD clock frequency (168Mhz/2) */
- /* TMRD: 2 Clock cycles */
- FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2;
- /* TXSR: min=70ns (6x11.90ns) */
- FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 7;
- /* TRAS: min=42ns (4x11.90ns) max=120k (ns) */
- FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4;
- /* TRC: min=63 (6x11.90ns) */
- FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 7;
- /* TWR: 2 Clock cycles */
- FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2;
- /* TRP: 15ns => 2x11.90ns */
- FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2;
- /* TRCD: 15ns => 2x11.90ns */
- FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2;
-
-/* FMC SDRAM control configuration */
- FMC_SDRAMInitStructure.FMC_Bank = FMC_Bank2_SDRAM;
- /* Row addressing: [7:0] */
- FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b;
- /* Column addressing: [11:0] */
- FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_12b;
- FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = SDRAM_MEMORY_WIDTH;
- FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4;
- FMC_SDRAMInitStructure.FMC_CASLatency = SDRAM_CAS_LATENCY;
- FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable;
- FMC_SDRAMInitStructure.FMC_SDClockPeriod = SDCLOCK_PERIOD;
- FMC_SDRAMInitStructure.FMC_ReadBurst = SDRAM_READBURST;
- FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1;
- FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure;
-
- /* FMC SDRAM bank initialization */
- FMC_SDRAMInit(&FMC_SDRAMInitStructure);
-
- /* FMC SDRAM device initialization sequence */
- SDRAM_InitSequence();
-
-}
-
-/*-- GPIOs Configuration -----------------------------------------------------*/
-/*
- +-------------------+--------------------+--------------------+--------------------+
- + SDRAM pins assignment +
- +-------------------+--------------------+--------------------+--------------------+
- | PD0 <-> FMC_D2 | PE0 <-> FMC_NBL0 | PF0 <-> FMC_A0 | PG0 <-> FMC_A10 |
- | PD1 <-> FMC_D3 | PE1 <-> FMC_NBL1 | PF1 <-> FMC_A1 | PG1 <-> FMC_A11 |
- | PD8 <-> FMC_D13 | PE7 <-> FMC_D4 | PF2 <-> FMC_A2 | PG8 <-> FMC_SDCLK |
- | PD9 <-> FMC_D14 | PE8 <-> FMC_D5 | PF3 <-> FMC_A3 | PG15 <-> FMC_NCAS |
- | PD10 <-> FMC_D15 | PE9 <-> FMC_D6 | PF4 <-> FMC_A4 |--------------------+
- | PD14 <-> FMC_D0 | PE10 <-> FMC_D7 | PF5 <-> FMC_A5 |
- | PD15 <-> FMC_D1 | PE11 <-> FMC_D8 | PF11 <-> FMC_NRAS |
- +-------------------| PE12 <-> FMC_D9 | PF12 <-> FMC_A6 |
- | PE13 <-> FMC_D10 | PF13 <-> FMC_A7 |
- | PE14 <-> FMC_D11 | PF14 <-> FMC_A8 |
- | PE15 <-> FMC_D12 | PF15 <-> FMC_A9 |
- +-------------------+--------------------+--------------------+
- | PB5 <-> FMC_SDCKE1|
- | PB6 <-> FMC_SDNE1 |
- | PC0 <-> FMC_SDNWE |
- +-------------------+
-
-*/
-
-// /* Common GPIO configuration */
-// GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
-// GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz;
-// GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
-// GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_NOPULL;
-//
-// /* GPIOB configuration */
-// GPIO_PinAFConfig(GPIOB, GPIO_PinSource5 , GPIO_AF_FMC);
-// GPIO_PinAFConfig(GPIOB, GPIO_PinSource6 , GPIO_AF_FMC);
-//
-// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_5 | GPIO_Pin_6;
-//
-// GPIO_Init(GPIOB, &GPIO_InitStructure);
-//
-// /* GPIOC configuration */
-// GPIO_PinAFConfig(GPIOC, GPIO_PinSource0 , GPIO_AF_FMC);
-//
-// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0;
-//
-// GPIO_Init(GPIOC, &GPIO_InitStructure);
-//
-// /* GPIOD configuration */
-// GPIO_PinAFConfig(GPIOD, GPIO_PinSource0, GPIO_AF_FMC);
-// GPIO_PinAFConfig(GPIOD, GPIO_PinSource1, GPIO_AF_FMC);
-// GPIO_PinAFConfig(GPIOD, GPIO_PinSource8, GPIO_AF_FMC);
-// GPIO_PinAFConfig(GPIOD, GPIO_PinSource9, GPIO_AF_FMC);
-// GPIO_PinAFConfig(GPIOD, GPIO_PinSource10, GPIO_AF_FMC);
-// GPIO_PinAFConfig(GPIOD, GPIO_PinSource14, GPIO_AF_FMC);
-// GPIO_PinAFConfig(GPIOD, GPIO_PinSource15, GPIO_AF_FMC);
-//
-// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_8 |
-// GPIO_Pin_9 | GPIO_Pin_10 | GPIO_Pin_14 |
-// GPIO_Pin_15;
-//
-// GPIO_Init(GPIOD, &GPIO_InitStructure);
-//
-// /* GPIOE configuration */
-// GPIO_PinAFConfig(GPIOE, GPIO_PinSource0 , GPIO_AF_FMC);
-// GPIO_PinAFConfig(GPIOE, GPIO_PinSource1 , GPIO_AF_FMC);
-// GPIO_PinAFConfig(GPIOE, GPIO_PinSource7 , GPIO_AF_FMC);
-// GPIO_PinAFConfig(GPIOE, GPIO_PinSource8 , GPIO_AF_FMC);
-// GPIO_PinAFConfig(GPIOE, GPIO_PinSource9 , GPIO_AF_FMC);
-// GPIO_PinAFConfig(GPIOE, GPIO_PinSource10 , GPIO_AF_FMC);
-// GPIO_PinAFConfig(GPIOE, GPIO_PinSource11 , GPIO_AF_FMC);
-// GPIO_PinAFConfig(GPIOE, GPIO_PinSource12 , GPIO_AF_FMC);
-// GPIO_PinAFConfig(GPIOE, GPIO_PinSource13 , GPIO_AF_FMC);
-// GPIO_PinAFConfig(GPIOE, GPIO_PinSource14 , GPIO_AF_FMC);
-// GPIO_PinAFConfig(GPIOE, GPIO_PinSource15 , GPIO_AF_FMC);
-//
-// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_7 |
-// GPIO_Pin_8 | GPIO_Pin_9 | GPIO_Pin_10 |
-// GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 |
-// GPIO_Pin_14 | GPIO_Pin_15;
-//
-// GPIO_Init(GPIOE, &GPIO_InitStructure);
-//
-// /* GPIOF configuration */
-// GPIO_PinAFConfig(GPIOF, GPIO_PinSource0 , GPIO_AF_FMC);
-// GPIO_PinAFConfig(GPIOF, GPIO_PinSource1 , GPIO_AF_FMC);
-// GPIO_PinAFConfig(GPIOF, GPIO_PinSource2 , GPIO_AF_FMC);
-// GPIO_PinAFConfig(GPIOF, GPIO_PinSource3 , GPIO_AF_FMC);
-// GPIO_PinAFConfig(GPIOF, GPIO_PinSource4 , GPIO_AF_FMC);
-// GPIO_PinAFConfig(GPIOF, GPIO_PinSource5 , GPIO_AF_FMC);
-// GPIO_PinAFConfig(GPIOF, GPIO_PinSource11 , GPIO_AF_FMC);
-// GPIO_PinAFConfig(GPIOF, GPIO_PinSource12 , GPIO_AF_FMC);
-// GPIO_PinAFConfig(GPIOF, GPIO_PinSource13 , GPIO_AF_FMC);
-// GPIO_PinAFConfig(GPIOF, GPIO_PinSource14 , GPIO_AF_FMC);
-// GPIO_PinAFConfig(GPIOF, GPIO_PinSource15 , GPIO_AF_FMC);
-//
-// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_2 |
-// GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5 |
-// GPIO_Pin_11 | GPIO_Pin_12 | GPIO_Pin_13 |
-// GPIO_Pin_14 | GPIO_Pin_15;
-//
-// GPIO_Init(GPIOF, &GPIO_InitStructure);
-//
-// /* GPIOG configuration */
-// GPIO_PinAFConfig(GPIOG, GPIO_PinSource0 , GPIO_AF_FMC);
-// GPIO_PinAFConfig(GPIOG, GPIO_PinSource1 , GPIO_AF_FMC);
-// GPIO_PinAFConfig(GPIOG, GPIO_PinSource4 , GPIO_AF_FMC);
-// GPIO_PinAFConfig(GPIOG, GPIO_PinSource5 , GPIO_AF_FMC);
-// GPIO_PinAFConfig(GPIOG, GPIO_PinSource8 , GPIO_AF_FMC);
-// GPIO_PinAFConfig(GPIOG, GPIO_PinSource15 , GPIO_AF_FMC);
-//
-//
-// GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0 | GPIO_Pin_1 | GPIO_Pin_4 |
-// GPIO_Pin_5 | GPIO_Pin_8 | GPIO_Pin_15;
-//
-// GPIO_Init(GPIOG, &GPIO_InitStructure);
-
-/**
- * @brief Executes the SDRAM memory initialization sequence.
- * @param None.
- * @retval None.
- */
-void SDRAM_InitSequence(void)
-{
- FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure;
- uint32_t tmpr = 0;
-
-/* Step 3 --------------------------------------------------------------------*/
- /* Configure a clock configuration enable command */
- FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_CLK_Enabled;
- FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
- FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
- FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
- /* Wait until the SDRAM controller is ready */
- while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
- {
- }
- /* Send the command */
- FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
-
- //In the ST example, this is 100ms, but the 429 RM says 100us is typical, and
- //the ISSI datasheet confirms this. 1ms seems plenty, and is much shorter than
- //refresh interval, meaning we won't risk losing contents if the SDRAM is in self-refresh
- //mode
-/* Step 4 --------------------------------------------------------------------*/
- /* Insert 1 ms delay */
- chThdSleepMilliseconds(1);
-
-/* Step 5 --------------------------------------------------------------------*/
- /* Configure a PALL (precharge all) command */
- FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_PALL;
- FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
- FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
- FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
- /* Wait until the SDRAM controller is ready */
- while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
- {
- }
- /* Send the command */
- FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
-
-/* Step 6 --------------------------------------------------------------------*/
- /* Configure a Auto-Refresh command */
- FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_AutoRefresh;
- FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
- FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 4;
- FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = 0;
- /* Wait until the SDRAM controller is ready */
- while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
- {
- }
- /* Send the first command */
- FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
-
- /* Wait until the SDRAM controller is ready */
- while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
- {
- }
- /* Send the second command */
- FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
-
-/* Step 7 --------------------------------------------------------------------*/
- /* Program the external memory mode register */
- tmpr = (uint32_t)SDRAM_MODEREG_BURST_LENGTH_2 |
- SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL |
- SDRAM_MODEREG_CAS_LATENCY_3 |
- SDRAM_MODEREG_OPERATING_MODE_STANDARD |
- SDRAM_MODEREG_WRITEBURST_MODE_SINGLE;
-
- /* Configure a load Mode register command*/
- FMC_SDRAMCommandStructure.FMC_CommandMode = FMC_Command_Mode_LoadMode;
- FMC_SDRAMCommandStructure.FMC_CommandTarget = FMC_Command_Target_bank2;
- FMC_SDRAMCommandStructure.FMC_AutoRefreshNumber = 1;
- FMC_SDRAMCommandStructure.FMC_ModeRegisterDefinition = tmpr;
- /* Wait until the SDRAM controller is ready */
- while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
- {
- }
- /* Send the command */
- FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
-
-/* Step 8 --------------------------------------------------------------------*/
-
- /* Set the refresh rate counter */
- /* (7.81 us x Freq) - 20 */
- /* Set the device refresh counter */
- FMC_SetRefreshCount(683);
- /* Wait until the SDRAM controller is ready */
- while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
- {
- }
-}
-
-
-/**
- * @brief Writes a Entire-word buffer to the SDRAM memory.
- * @param pBuffer: pointer to buffer.
- * @param uwWriteAddress: SDRAM memory internal address from which the data will be
- * written.
- * @param uwBufferSize: number of words to write.
- * @retval None.
- */
-void SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBufferSize)
-{
- __IO uint32_t write_pointer = (uint32_t)uwWriteAddress;
-
- /* Disable write protection */
- FMC_SDRAMWriteProtectionConfig(FMC_Bank2_SDRAM, DISABLE);
-
- /* Wait until the SDRAM controller is ready */
- while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
- {
- }
-
- /* While there is data to write */
- for (; uwBufferSize != 0; uwBufferSize--)
- {
- /* Transfer data to the memory */
- *(uint32_t *) (SDRAM_BANK_ADDR + write_pointer) = *pBuffer++;
-
- /* Increment the address*/
- write_pointer += 4;
- }
-
-}
-
-/**
- * @brief Reads data buffer from the SDRAM memory.
- * @param pBuffer: pointer to buffer.
- * @param ReadAddress: SDRAM memory internal address from which the data will be
- * read.
- * @param uwBufferSize: number of words to write.
- * @retval None.
- */
-void SDRAM_ReadBuffer(uint32_t* pBuffer, uint32_t uwReadAddress, uint32_t uwBufferSize)
-{
- __IO uint32_t write_pointer = (uint32_t)uwReadAddress;
-
-
- /* Wait until the SDRAM controller is ready */
- while(FMC_GetFlagStatus(FMC_Bank2_SDRAM, FMC_FLAG_Busy) != RESET)
- {
- }
-
- /* Read data */
- for(; uwBufferSize != 0x00; uwBufferSize--)
- {
- *pBuffer++ = *(__IO uint32_t *)(SDRAM_BANK_ADDR + write_pointer );
-
- /* Increment the address*/
- write_pointer += 4;
- }
-}
-
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/stmdrivers/stm32f429i_discovery_sdram.h b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/stmdrivers/stm32f429i_discovery_sdram.h deleted file mode 100644 index 70688d9..0000000 --- a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/stmdrivers/stm32f429i_discovery_sdram.h +++ /dev/null @@ -1,96 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f429i_discovery_sdram.h
- * @author MCD Application Team
- * @version V1.0.0
- * @date 20-September-2013
- * @brief This file contains all the functions prototypes for the
- * stm324x9i_disco_sdram.c driver.
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32429I_DISCO_SDRAM_H
-#define __STM32429I_DISCO_SDRAM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-//FIXME this should not be needed
-#define STM32F429_439xx
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx.h"
-
-/**
- * @brief FMC SDRAM Bank address
- */
-#define SDRAM_BANK_ADDR ((uint32_t)0xD0000000)
-
-/**
- * @brief FMC SDRAM Memory Width
- */
-/* #define SDRAM_MEMORY_WIDTH FMC_SDMemory_Width_8b */
-#define SDRAM_MEMORY_WIDTH FMC_SDMemory_Width_16b
-
-/**
- * @brief FMC SDRAM CAS Latency
- */
-/* #define SDRAM_CAS_LATENCY FMC_CAS_Latency_2 */
-#define SDRAM_CAS_LATENCY FMC_CAS_Latency_3
-
-/**
- * @brief FMC SDRAM Memory clock period
- */
-#define SDCLOCK_PERIOD FMC_SDClock_Period_2 /* Default configuration used with LCD */
-/* #define SDCLOCK_PERIOD FMC_SDClock_Period_3 */
-
-/**
- * @brief FMC SDRAM Memory Read Burst feature
- */
-#define SDRAM_READBURST FMC_Read_Burst_Disable /* Default configuration used with LCD */
-/* #define SDRAM_READBURST FMC_Read_Burst_Enable */
-
-/**
- * @brief FMC SDRAM Mode definition register defines
- */
-#define SDRAM_MODEREG_BURST_LENGTH_1 ((uint16_t)0x0000)
-#define SDRAM_MODEREG_BURST_LENGTH_2 ((uint16_t)0x0001)
-#define SDRAM_MODEREG_BURST_LENGTH_4 ((uint16_t)0x0002)
-#define SDRAM_MODEREG_BURST_LENGTH_8 ((uint16_t)0x0004)
-#define SDRAM_MODEREG_BURST_TYPE_SEQUENTIAL ((uint16_t)0x0000)
-#define SDRAM_MODEREG_BURST_TYPE_INTERLEAVED ((uint16_t)0x0008)
-#define SDRAM_MODEREG_CAS_LATENCY_2 ((uint16_t)0x0020)
-#define SDRAM_MODEREG_CAS_LATENCY_3 ((uint16_t)0x0030)
-#define SDRAM_MODEREG_OPERATING_MODE_STANDARD ((uint16_t)0x0000)
-#define SDRAM_MODEREG_WRITEBURST_MODE_PROGRAMMED ((uint16_t)0x0000)
-#define SDRAM_MODEREG_WRITEBURST_MODE_SINGLE ((uint16_t)0x0200)
-
-void SDRAM_Init(void);
-void SDRAM_InitSequence(void);
-void SDRAM_WriteBuffer(uint32_t* pBuffer, uint32_t uwWriteAddress, uint32_t uwBufferSize);
-void SDRAM_ReadBuffer(uint32_t* pBuffer, uint32_t uwReadAddress, uint32_t uwBufferSize);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/stmdrivers/stm32f4xx_fmc.c b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/stmdrivers/stm32f4xx_fmc.c deleted file mode 100644 index 1f7ce5d..0000000 --- a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/stmdrivers/stm32f4xx_fmc.c +++ /dev/null @@ -1,1379 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f4xx_fmc.c
- * @author MCD Application Team
- * @version V1.2.1
- * @date 19-September-2013
- * @brief This file provides firmware functions to manage the following
- * functionalities of the FMC peripheral:
- * + Interface with SRAM, PSRAM, NOR and OneNAND memories
- * + Interface with NAND memories
- * + Interface with 16-bit PC Card compatible memories
- * + Interface with SDRAM memories
- * + Interrupts and flags management
- *
- ******************************************************************************
- * @attention
- *
- * <h2><center>© COPYRIGHT 2013 STMicroelectronics</center></h2>
- *
- * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
- * You may not use this file except in compliance with the License.
- * You may obtain a copy of the License at:
- *
- * http://www.st.com/software_license_agreement_liberty_v2
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- *
- ******************************************************************************
- */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_fmc.h"
-#include "ch.h"
-//#include "stm32f4xx_rcc.h"
-
-#define FMC_Bank2 FMC_Bank2_3
-#define FMC_Bank3 FMC_Bank2_3
-
-#define assert_param(expr) chDbgAssert(expr, "STPeriph FMC")
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @defgroup FMC
- * @brief FMC driver modules
- * @{
- */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/* --------------------- FMC registers bit mask ---------------------------- */
-/* FMC BCRx Mask */
-#define BCR_MBKEN_SET ((uint32_t)0x00000001)
-#define BCR_MBKEN_RESET ((uint32_t)0x000FFFFE)
-#define BCR_FACCEN_SET ((uint32_t)0x00000040)
-
-/* FMC PCRx Mask */
-#define PCR_PBKEN_SET ((uint32_t)0x00000004)
-#define PCR_PBKEN_RESET ((uint32_t)0x000FFFFB)
-#define PCR_ECCEN_SET ((uint32_t)0x00000040)
-#define PCR_ECCEN_RESET ((uint32_t)0x000FFFBF)
-#define PCR_MEMORYTYPE_NAND ((uint32_t)0x00000008)
-
-/* FMC SDCRx write protection Mask*/
-#define SDCR_WriteProtection_RESET ((uint32_t)0x00007DFF)
-
-/* FMC SDCMR Mask*/
-#define SDCMR_CTB1_RESET ((uint32_t)0x003FFFEF)
-#define SDCMR_CTB2_RESET ((uint32_t)0x003FFFF7)
-#define SDCMR_CTB1_2_RESET ((uint32_t)0x003FFFE7)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup FMC_Private_Functions
- * @{
- */
-
-/** @defgroup FMC_Group1 NOR/SRAM Controller functions
- * @brief NOR/SRAM Controller functions
- *
-@verbatim
- ===============================================================================
- ##### NOR and SRAM Controller functions #####
- ===============================================================================
-
- [..] The following sequence should be followed to configure the FMC to interface
- with SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank:
-
- (#) Enable the clock for the FMC and associated GPIOs using the following functions:
- RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE);
- RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
-
- (#) FMC pins configuration
- (++) Connect the involved FMC pins to AF12 using the following function
- GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC);
- (++) Configure these FMC pins in alternate function mode by calling the function
- GPIO_Init();
-
- (#) Declare a FMC_NORSRAMInitTypeDef structure, for example:
- FMC_NORSRAMInitTypeDef FMC_NORSRAMInitStructure;
- and fill the FMC_NORSRAMInitStructure variable with the allowed values of
- the structure member.
-
- (#) Initialize the NOR/SRAM Controller by calling the function
- FMC_NORSRAMInit(&FMC_NORSRAMInitStructure);
-
- (#) Then enable the NOR/SRAM Bank, for example:
- FMC_NORSRAMCmd(FMC_Bank1_NORSRAM2, ENABLE);
-
- (#) At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief De-initializes the FMC NOR/SRAM Banks registers to their default
- * reset values.
- * @param FMC_Bank: specifies the FMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FMC_Bank1_NORSRAM1: FMC Bank1 NOR/SRAM1
- * @arg FMC_Bank1_NORSRAM2: FMC Bank1 NOR/SRAM2
- * @arg FMC_Bank1_NORSRAM3: FMC Bank1 NOR/SRAM3
- * @arg FMC_Bank1_NORSRAM4: FMC Bank1 NOR/SRAM4
- * @retval None
- */
-void FMC_NORSRAMDeInit(uint32_t FMC_Bank)
-{
- /* Check the parameter */
- assert_param(IS_FMC_NORSRAM_BANK(FMC_Bank));
-
- /* FMC_Bank1_NORSRAM1 */
- if(FMC_Bank == FMC_Bank1_NORSRAM1)
- {
- FMC_Bank1->BTCR[FMC_Bank] = 0x000030DB;
- }
- /* FMC_Bank1_NORSRAM2, FMC_Bank1_NORSRAM3 or FMC_Bank1_NORSRAM4 */
- else
- {
- FMC_Bank1->BTCR[FMC_Bank] = 0x000030D2;
- }
- FMC_Bank1->BTCR[FMC_Bank + 1] = 0x0FFFFFFF;
- FMC_Bank1E->BWTR[FMC_Bank] = 0x0FFFFFFF;
-}
-
-/**
- * @brief Initializes the FMC NOR/SRAM Banks according to the specified
- * parameters in the FMC_NORSRAMInitStruct.
- * @param FMC_NORSRAMInitStruct : pointer to a FMC_NORSRAMInitTypeDef structure
- * that contains the configuration information for the FMC NOR/SRAM
- * specified Banks.
- * @retval None
- */
-void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct)
-{
- uint32_t tmpr = 0;
-
- /* Check the parameters */
- assert_param(IS_FMC_NORSRAM_BANK(FMC_NORSRAMInitStruct->FMC_Bank));
- assert_param(IS_FMC_MUX(FMC_NORSRAMInitStruct->FMC_DataAddressMux));
- assert_param(IS_FMC_MEMORY(FMC_NORSRAMInitStruct->FMC_MemoryType));
- assert_param(IS_FMC_NORSRAM_MEMORY_WIDTH(FMC_NORSRAMInitStruct->FMC_MemoryDataWidth));
- assert_param(IS_FMC_BURSTMODE(FMC_NORSRAMInitStruct->FMC_BurstAccessMode));
- assert_param(IS_FMC_WAIT_POLARITY(FMC_NORSRAMInitStruct->FMC_WaitSignalPolarity));
- assert_param(IS_FMC_WRAP_MODE(FMC_NORSRAMInitStruct->FMC_WrapMode));
- assert_param(IS_FMC_WAIT_SIGNAL_ACTIVE(FMC_NORSRAMInitStruct->FMC_WaitSignalActive));
- assert_param(IS_FMC_WRITE_OPERATION(FMC_NORSRAMInitStruct->FMC_WriteOperation));
- assert_param(IS_FMC_WAITE_SIGNAL(FMC_NORSRAMInitStruct->FMC_WaitSignal));
- assert_param(IS_FMC_EXTENDED_MODE(FMC_NORSRAMInitStruct->FMC_ExtendedMode));
- assert_param(IS_FMC_ASYNWAIT(FMC_NORSRAMInitStruct->FMC_AsynchronousWait));
- assert_param(IS_FMC_WRITE_BURST(FMC_NORSRAMInitStruct->FMC_WriteBurst));
- assert_param(IS_FMC_CONTINOUS_CLOCK(FMC_NORSRAMInitStruct->FMC_ContinousClock));
- assert_param(IS_FMC_ADDRESS_SETUP_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressSetupTime));
- assert_param(IS_FMC_ADDRESS_HOLD_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressHoldTime));
- assert_param(IS_FMC_DATASETUP_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataSetupTime));
- assert_param(IS_FMC_TURNAROUND_TIME(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_BusTurnAroundDuration));
- assert_param(IS_FMC_CLK_DIV(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision));
- assert_param(IS_FMC_DATA_LATENCY(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataLatency));
- assert_param(IS_FMC_ACCESS_MODE(FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AccessMode));
-
- /* NOR/SRAM Bank control register configuration */
- FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank] =
- (uint32_t)FMC_NORSRAMInitStruct->FMC_DataAddressMux |
- FMC_NORSRAMInitStruct->FMC_MemoryType |
- FMC_NORSRAMInitStruct->FMC_MemoryDataWidth |
- FMC_NORSRAMInitStruct->FMC_BurstAccessMode |
- FMC_NORSRAMInitStruct->FMC_WaitSignalPolarity |
- FMC_NORSRAMInitStruct->FMC_WrapMode |
- FMC_NORSRAMInitStruct->FMC_WaitSignalActive |
- FMC_NORSRAMInitStruct->FMC_WriteOperation |
- FMC_NORSRAMInitStruct->FMC_WaitSignal |
- FMC_NORSRAMInitStruct->FMC_ExtendedMode |
- FMC_NORSRAMInitStruct->FMC_AsynchronousWait |
- FMC_NORSRAMInitStruct->FMC_WriteBurst |
- FMC_NORSRAMInitStruct->FMC_ContinousClock;
-
-
- if(FMC_NORSRAMInitStruct->FMC_MemoryType == FMC_MemoryType_NOR)
- {
- FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank] |= (uint32_t)BCR_FACCEN_SET;
- }
-
- /* Configure Continuous clock feature when bank2..4 is used */
- if((FMC_NORSRAMInitStruct->FMC_ContinousClock == FMC_CClock_SyncAsync) && (FMC_NORSRAMInitStruct->FMC_Bank != FMC_Bank1_NORSRAM1))
- {
- tmpr = (uint32_t)((FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1+1]) & ~(((uint32_t)0x0F) << 20));
-
- FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1] |= FMC_NORSRAMInitStruct->FMC_ContinousClock;
- FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1] |= FMC_BurstAccessMode_Enable;
- FMC_Bank1->BTCR[FMC_Bank1_NORSRAM1+1] = (uint32_t)(tmpr | (((FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision)-1) << 20));
- }
-
- /* NOR/SRAM Bank timing register configuration */
- FMC_Bank1->BTCR[FMC_NORSRAMInitStruct->FMC_Bank+1] =
- (uint32_t)FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressSetupTime |
- (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressHoldTime << 4) |
- (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataSetupTime << 8) |
- (FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_BusTurnAroundDuration << 16) |
- ((FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision) << 20) |
- ((FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataLatency) << 24) |
- FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AccessMode;
-
- /* NOR/SRAM Bank timing register for write configuration, if extended mode is used */
- if(FMC_NORSRAMInitStruct->FMC_ExtendedMode == FMC_ExtendedMode_Enable)
- {
- assert_param(IS_FMC_ADDRESS_SETUP_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressSetupTime));
- assert_param(IS_FMC_ADDRESS_HOLD_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressHoldTime));
- assert_param(IS_FMC_DATASETUP_TIME(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataSetupTime));
- assert_param(IS_FMC_CLK_DIV(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_CLKDivision));
- assert_param(IS_FMC_DATA_LATENCY(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataLatency));
- assert_param(IS_FMC_ACCESS_MODE(FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AccessMode));
-
- FMC_Bank1E->BWTR[FMC_NORSRAMInitStruct->FMC_Bank] =
- (uint32_t)FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressSetupTime |
- (FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressHoldTime << 4 )|
- (FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataSetupTime << 8) |
- ((FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_CLKDivision) << 20) |
- ((FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataLatency) << 24) |
- FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AccessMode;
- }
- else
- {
- FMC_Bank1E->BWTR[FMC_NORSRAMInitStruct->FMC_Bank] = 0x0FFFFFFF;
- }
-
-}
-
-/**
- * @brief Fills each FMC_NORSRAMInitStruct member with its default value.
- * @param FMC_NORSRAMInitStruct: pointer to a FMC_NORSRAMInitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void FMC_NORSRAMStructInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct)
-{
- /* Reset NOR/SRAM Init structure parameters values */
- FMC_NORSRAMInitStruct->FMC_Bank = FMC_Bank1_NORSRAM1;
- FMC_NORSRAMInitStruct->FMC_DataAddressMux = FMC_DataAddressMux_Enable;
- FMC_NORSRAMInitStruct->FMC_MemoryType = FMC_MemoryType_SRAM;
- FMC_NORSRAMInitStruct->FMC_MemoryDataWidth = FMC_NORSRAM_MemoryDataWidth_16b;
- FMC_NORSRAMInitStruct->FMC_BurstAccessMode = FMC_BurstAccessMode_Disable;
- FMC_NORSRAMInitStruct->FMC_AsynchronousWait = FMC_AsynchronousWait_Disable;
- FMC_NORSRAMInitStruct->FMC_WaitSignalPolarity = FMC_WaitSignalPolarity_Low;
- FMC_NORSRAMInitStruct->FMC_WrapMode = FMC_WrapMode_Disable;
- FMC_NORSRAMInitStruct->FMC_WaitSignalActive = FMC_WaitSignalActive_BeforeWaitState;
- FMC_NORSRAMInitStruct->FMC_WriteOperation = FMC_WriteOperation_Enable;
- FMC_NORSRAMInitStruct->FMC_WaitSignal = FMC_WaitSignal_Enable;
- FMC_NORSRAMInitStruct->FMC_ExtendedMode = FMC_ExtendedMode_Disable;
- FMC_NORSRAMInitStruct->FMC_WriteBurst = FMC_WriteBurst_Disable;
- FMC_NORSRAMInitStruct->FMC_ContinousClock = FMC_CClock_SyncOnly;
-
- FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressSetupTime = 15;
- FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AddressHoldTime = 15;
- FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataSetupTime = 255;
- FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_BusTurnAroundDuration = 15;
- FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_CLKDivision = 15;
- FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_DataLatency = 15;
- FMC_NORSRAMInitStruct->FMC_ReadWriteTimingStruct->FMC_AccessMode = FMC_AccessMode_A;
- FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressSetupTime = 15;
- FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AddressHoldTime = 15;
- FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataSetupTime = 255;
- FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_BusTurnAroundDuration = 15;
- FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_CLKDivision = 15;
- FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_DataLatency = 15;
- FMC_NORSRAMInitStruct->FMC_WriteTimingStruct->FMC_AccessMode = FMC_AccessMode_A;
-}
-
-/**
- * @brief Enables or disables the specified NOR/SRAM Memory Bank.
- * @param FMC_Bank: specifies the FMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FMC_Bank1_NORSRAM1: FMC Bank1 NOR/SRAM1
- * @arg FMC_Bank1_NORSRAM2: FMC Bank1 NOR/SRAM2
- * @arg FMC_Bank1_NORSRAM3: FMC Bank1 NOR/SRAM3
- * @arg FMC_Bank1_NORSRAM4: FMC Bank1 NOR/SRAM4
- * @param NewState: new state of the FMC_Bank. This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FMC_NORSRAMCmd(uint32_t FMC_Bank, FunctionalState NewState)
-{
- assert_param(IS_FMC_NORSRAM_BANK(FMC_Bank));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
- FMC_Bank1->BTCR[FMC_Bank] |= BCR_MBKEN_SET;
- }
- else
- {
- /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
- FMC_Bank1->BTCR[FMC_Bank] &= BCR_MBKEN_RESET;
- }
-}
-/**
- * @}
- */
-
-/** @defgroup FMC_Group2 NAND Controller functions
- * @brief NAND Controller functions
- *
-@verbatim
- ===============================================================================
- ##### NAND Controller functions #####
- ===============================================================================
-
- [..] The following sequence should be followed to configure the FMC to interface
- with 8-bit or 16-bit NAND memory connected to the NAND Bank:
-
- (#) Enable the clock for the FMC and associated GPIOs using the following functions:
- (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE);
- (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
-
- (#) FMC pins configuration
- (++) Connect the involved FMC pins to AF12 using the following function
- GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC);
- (++) Configure these FMC pins in alternate function mode by calling the function
- GPIO_Init();
-
- (#) Declare a FMC_NANDInitTypeDef structure, for example:
- FMC_NANDInitTypeDef FMC_NANDInitStructure;
- and fill the FMC_NANDInitStructure variable with the allowed values of
- the structure member.
-
- (#) Initialize the NAND Controller by calling the function
- FMC_NANDInit(&FMC_NANDInitStructure);
-
- (#) Then enable the NAND Bank, for example:
- FMC_NANDCmd(FMC_Bank3_NAND, ENABLE);
-
- (#) At this stage you can read/write from/to the memory connected to the NAND Bank.
-
- [..]
- (@) To enable the Error Correction Code (ECC), you have to use the function
- FMC_NANDECCCmd(FMC_Bank3_NAND, ENABLE);
- [..]
- (@) and to get the current ECC value you have to use the function
- ECCval = FMC_GetECC(FMC_Bank3_NAND);
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief De-initializes the FMC NAND Banks registers to their default reset values.
- * @param FMC_Bank: specifies the FMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FMC_Bank2_NAND: FMC Bank2 NAND
- * @arg FMC_Bank3_NAND: FMC Bank3 NAND
- * @retval None
- */
-void FMC_NANDDeInit(uint32_t FMC_Bank)
-{
- /* Check the parameter */
- assert_param(IS_FMC_NAND_BANK(FMC_Bank));
-
- if(FMC_Bank == FMC_Bank2_NAND)
- {
- /* Set the FMC_Bank2 registers to their reset values */
- FMC_Bank2->PCR2 = 0x00000018;
- FMC_Bank2->SR2 = 0x00000040;
- FMC_Bank2->PMEM2 = 0xFCFCFCFC;
- FMC_Bank2->PATT2 = 0xFCFCFCFC;
- }
- /* FMC_Bank3_NAND */
- else
- {
- /* Set the FMC_Bank3 registers to their reset values */
- FMC_Bank3->PCR3 = 0x00000018;
- FMC_Bank3->SR3 = 0x00000040;
- FMC_Bank3->PMEM3 = 0xFCFCFCFC;
- FMC_Bank3->PATT3 = 0xFCFCFCFC;
- }
-}
-
-/**
- * @brief Initializes the FMC NAND Banks according to the specified parameters
- * in the FMC_NANDInitStruct.
- * @param FMC_NANDInitStruct : pointer to a FMC_NANDInitTypeDef structure that
- * contains the configuration information for the FMC NAND specified Banks.
- * @retval None
- */
-void FMC_NANDInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct)
-{
- uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000;
-
- /* Check the parameters */
- assert_param(IS_FMC_NAND_BANK(FMC_NANDInitStruct->FMC_Bank));
- assert_param(IS_FMC_WAIT_FEATURE(FMC_NANDInitStruct->FMC_Waitfeature));
- assert_param(IS_FMC_NAND_MEMORY_WIDTH(FMC_NANDInitStruct->FMC_MemoryDataWidth));
- assert_param(IS_FMC_ECC_STATE(FMC_NANDInitStruct->FMC_ECC));
- assert_param(IS_FMC_ECCPAGE_SIZE(FMC_NANDInitStruct->FMC_ECCPageSize));
- assert_param(IS_FMC_TCLR_TIME(FMC_NANDInitStruct->FMC_TCLRSetupTime));
- assert_param(IS_FMC_TAR_TIME(FMC_NANDInitStruct->FMC_TARSetupTime));
- assert_param(IS_FMC_SETUP_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime));
- assert_param(IS_FMC_WAIT_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime));
- assert_param(IS_FMC_HOLD_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime));
- assert_param(IS_FMC_HIZ_TIME(FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime));
- assert_param(IS_FMC_SETUP_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime));
- assert_param(IS_FMC_WAIT_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime));
- assert_param(IS_FMC_HOLD_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime));
- assert_param(IS_FMC_HIZ_TIME(FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime));
-
- /* Set the tmppcr value according to FMC_NANDInitStruct parameters */
- tmppcr = (uint32_t)FMC_NANDInitStruct->FMC_Waitfeature |
- PCR_MEMORYTYPE_NAND |
- FMC_NANDInitStruct->FMC_MemoryDataWidth |
- FMC_NANDInitStruct->FMC_ECC |
- FMC_NANDInitStruct->FMC_ECCPageSize |
- (FMC_NANDInitStruct->FMC_TCLRSetupTime << 9 )|
- (FMC_NANDInitStruct->FMC_TARSetupTime << 13);
-
- /* Set tmppmem value according to FMC_CommonSpaceTimingStructure parameters */
- tmppmem = (uint32_t)FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime |
- (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime << 8) |
- (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime << 16)|
- (FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime << 24);
-
- /* Set tmppatt value according to FMC_AttributeSpaceTimingStructure parameters */
- tmppatt = (uint32_t)FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime |
- (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime << 8) |
- (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime << 16)|
- (FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime << 24);
-
- if(FMC_NANDInitStruct->FMC_Bank == FMC_Bank2_NAND)
- {
- /* FMC_Bank2_NAND registers configuration */
- FMC_Bank2->PCR2 = tmppcr;
- FMC_Bank2->PMEM2 = tmppmem;
- FMC_Bank2->PATT2 = tmppatt;
- }
- else
- {
- /* FMC_Bank3_NAND registers configuration */
- FMC_Bank3->PCR3 = tmppcr;
- FMC_Bank3->PMEM3 = tmppmem;
- FMC_Bank3->PATT3 = tmppatt;
- }
-}
-
-
-/**
- * @brief Fills each FMC_NANDInitStruct member with its default value.
- * @param FMC_NANDInitStruct: pointer to a FMC_NANDInitTypeDef structure which
- * will be initialized.
- * @retval None
- */
-void FMC_NANDStructInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct)
-{
- /* Reset NAND Init structure parameters values */
- FMC_NANDInitStruct->FMC_Bank = FMC_Bank2_NAND;
- FMC_NANDInitStruct->FMC_Waitfeature = FMC_Waitfeature_Disable;
- FMC_NANDInitStruct->FMC_MemoryDataWidth = FMC_NAND_MemoryDataWidth_16b;
- FMC_NANDInitStruct->FMC_ECC = FMC_ECC_Disable;
- FMC_NANDInitStruct->FMC_ECCPageSize = FMC_ECCPageSize_256Bytes;
- FMC_NANDInitStruct->FMC_TCLRSetupTime = 0x0;
- FMC_NANDInitStruct->FMC_TARSetupTime = 0x0;
- FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime = 252;
- FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime = 252;
- FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime = 252;
- FMC_NANDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime = 252;
- FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime = 252;
- FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime = 252;
- FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime = 252;
- FMC_NANDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime = 252;
-}
-
-/**
- * @brief Enables or disables the specified NAND Memory Bank.
- * @param FMC_Bank: specifies the FMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FMC_Bank2_NAND: FMC Bank2 NAND
- * @arg FMC_Bank3_NAND: FMC Bank3 NAND
- * @param NewState: new state of the FMC_Bank. This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FMC_NANDCmd(uint32_t FMC_Bank, FunctionalState NewState)
-{
- assert_param(IS_FMC_NAND_BANK(FMC_Bank));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
- if(FMC_Bank == FMC_Bank2_NAND)
- {
- FMC_Bank2->PCR2 |= PCR_PBKEN_SET;
- }
- else
- {
- FMC_Bank3->PCR3 |= PCR_PBKEN_SET;
- }
- }
- else
- {
- /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
- if(FMC_Bank == FMC_Bank2_NAND)
- {
- FMC_Bank2->PCR2 &= PCR_PBKEN_RESET;
- }
- else
- {
- FMC_Bank3->PCR3 &= PCR_PBKEN_RESET;
- }
- }
-}
-/**
- * @brief Enables or disables the FMC NAND ECC feature.
- * @param FMC_Bank: specifies the FMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FMC_Bank2_NAND: FMC Bank2 NAND
- * @arg FMC_Bank3_NAND: FMC Bank3 NAND
- * @param NewState: new state of the FMC NAND ECC feature.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FMC_NANDECCCmd(uint32_t FMC_Bank, FunctionalState NewState)
-{
- assert_param(IS_FMC_NAND_BANK(FMC_Bank));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
- if(FMC_Bank == FMC_Bank2_NAND)
- {
- FMC_Bank2->PCR2 |= PCR_ECCEN_SET;
- }
- else
- {
- FMC_Bank3->PCR3 |= PCR_ECCEN_SET;
- }
- }
- else
- {
- /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
- if(FMC_Bank == FMC_Bank2_NAND)
- {
- FMC_Bank2->PCR2 &= PCR_ECCEN_RESET;
- }
- else
- {
- FMC_Bank3->PCR3 &= PCR_ECCEN_RESET;
- }
- }
-}
-
-/**
- * @brief Returns the error correction code register value.
- * @param FMC_Bank: specifies the FMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FMC_Bank2_NAND: FMC Bank2 NAND
- * @arg FMC_Bank3_NAND: FMC Bank3 NAND
- * @retval The Error Correction Code (ECC) value.
- */
-uint32_t FMC_GetECC(uint32_t FMC_Bank)
-{
- uint32_t eccval = 0x00000000;
-
- if(FMC_Bank == FMC_Bank2_NAND)
- {
- /* Get the ECCR2 register value */
- eccval = FMC_Bank2->ECCR2;
- }
- else
- {
- /* Get the ECCR3 register value */
- eccval = FMC_Bank3->ECCR3;
- }
- /* Return the error correction code value */
- return(eccval);
-}
-/**
- * @}
- */
-
-/** @defgroup FMC_Group3 PCCARD Controller functions
- * @brief PCCARD Controller functions
- *
-@verbatim
- ===============================================================================
- ##### PCCARD Controller functions #####
- ===============================================================================
-
- [..] he following sequence should be followed to configure the FMC to interface
- with 16-bit PC Card compatible memory connected to the PCCARD Bank:
-
- (#) Enable the clock for the FMC and associated GPIOs using the following functions:
- (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE);
- (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
-
- (#) FMC pins configuration
- (++) Connect the involved FMC pins to AF12 using the following function
- GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC);
- (++) Configure these FMC pins in alternate function mode by calling the function
- GPIO_Init();
-
- (#) Declare a FMC_PCCARDInitTypeDef structure, for example:
- FMC_PCCARDInitTypeDef FMC_PCCARDInitStructure;
- and fill the FMC_PCCARDInitStructure variable with the allowed values of
- the structure member.
-
- (#) Initialize the PCCARD Controller by calling the function
- FMC_PCCARDInit(&FMC_PCCARDInitStructure);
-
- (#) Then enable the PCCARD Bank:
- FMC_PCCARDCmd(ENABLE);
-
- (#) At this stage you can read/write from/to the memory connected to the PCCARD Bank.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief De-initializes the FMC PCCARD Bank registers to their default reset values.
- * @param None
- * @retval None
- */
-void FMC_PCCARDDeInit(void)
-{
- /* Set the FMC_Bank4 registers to their reset values */
- FMC_Bank4->PCR4 = 0x00000018;
- FMC_Bank4->SR4 = 0x00000000;
- FMC_Bank4->PMEM4 = 0xFCFCFCFC;
- FMC_Bank4->PATT4 = 0xFCFCFCFC;
- FMC_Bank4->PIO4 = 0xFCFCFCFC;
-}
-
-/**
- * @brief Initializes the FMC PCCARD Bank according to the specified parameters
- * in the FMC_PCCARDInitStruct.
- * @param FMC_PCCARDInitStruct : pointer to a FMC_PCCARDInitTypeDef structure
- * that contains the configuration information for the FMC PCCARD Bank.
- * @retval None
- */
-void FMC_PCCARDInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct)
-{
- /* Check the parameters */
- assert_param(IS_FMC_WAIT_FEATURE(FMC_PCCARDInitStruct->FMC_Waitfeature));
- assert_param(IS_FMC_TCLR_TIME(FMC_PCCARDInitStruct->FMC_TCLRSetupTime));
- assert_param(IS_FMC_TAR_TIME(FMC_PCCARDInitStruct->FMC_TARSetupTime));
-
- assert_param(IS_FMC_SETUP_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime));
- assert_param(IS_FMC_WAIT_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime));
- assert_param(IS_FMC_HOLD_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime));
- assert_param(IS_FMC_HIZ_TIME(FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime));
-
- assert_param(IS_FMC_SETUP_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime));
- assert_param(IS_FMC_WAIT_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime));
- assert_param(IS_FMC_HOLD_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime));
- assert_param(IS_FMC_HIZ_TIME(FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime));
- assert_param(IS_FMC_SETUP_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime));
- assert_param(IS_FMC_WAIT_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime));
- assert_param(IS_FMC_HOLD_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime));
- assert_param(IS_FMC_HIZ_TIME(FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime));
-
- /* Set the PCR4 register value according to FMC_PCCARDInitStruct parameters */
- FMC_Bank4->PCR4 = (uint32_t)FMC_PCCARDInitStruct->FMC_Waitfeature |
- FMC_NAND_MemoryDataWidth_16b |
- (FMC_PCCARDInitStruct->FMC_TCLRSetupTime << 9) |
- (FMC_PCCARDInitStruct->FMC_TARSetupTime << 13);
-
- /* Set PMEM4 register value according to FMC_CommonSpaceTimingStructure parameters */
- FMC_Bank4->PMEM4 = (uint32_t)FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime |
- (FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime << 8) |
- (FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime << 16)|
- (FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime << 24);
-
- /* Set PATT4 register value according to FMC_AttributeSpaceTimingStructure parameters */
- FMC_Bank4->PATT4 = (uint32_t)FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime |
- (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime << 8) |
- (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime << 16)|
- (FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime << 24);
-
- /* Set PIO4 register value according to FMC_IOSpaceTimingStructure parameters */
- FMC_Bank4->PIO4 = (uint32_t)FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime |
- (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime << 8) |
- (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime << 16)|
- (FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime << 24);
-}
-
-/**
- * @brief Fills each FMC_PCCARDInitStruct member with its default value.
- * @param FMC_PCCARDInitStruct: pointer to a FMC_PCCARDInitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void FMC_PCCARDStructInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct)
-{
- /* Reset PCCARD Init structure parameters values */
- FMC_PCCARDInitStruct->FMC_Waitfeature = FMC_Waitfeature_Disable;
- FMC_PCCARDInitStruct->FMC_TCLRSetupTime = 0;
- FMC_PCCARDInitStruct->FMC_TARSetupTime = 0;
- FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_SetupTime = 252;
- FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_WaitSetupTime = 252;
- FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HoldSetupTime = 252;
- FMC_PCCARDInitStruct->FMC_CommonSpaceTimingStruct->FMC_HiZSetupTime = 252;
- FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_SetupTime = 252;
- FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_WaitSetupTime = 252;
- FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HoldSetupTime = 252;
- FMC_PCCARDInitStruct->FMC_AttributeSpaceTimingStruct->FMC_HiZSetupTime = 252;
- FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_SetupTime = 252;
- FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_WaitSetupTime = 252;
- FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HoldSetupTime = 252;
- FMC_PCCARDInitStruct->FMC_IOSpaceTimingStruct->FMC_HiZSetupTime = 252;
-}
-
-/**
- * @brief Enables or disables the PCCARD Memory Bank.
- * @param NewState: new state of the PCCARD Memory Bank.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FMC_PCCARDCmd(FunctionalState NewState)
-{
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
- FMC_Bank4->PCR4 |= PCR_PBKEN_SET;
- }
- else
- {
- /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
- FMC_Bank4->PCR4 &= PCR_PBKEN_RESET;
- }
-}
-
-/**
- * @}
- */
-
-/** @defgroup FMC_Group4 SDRAM Controller functions
- * @brief SDRAM Controller functions
- *
-@verbatim
- ===============================================================================
- ##### SDRAM Controller functions #####
- ===============================================================================
-
- [..] The following sequence should be followed to configure the FMC to interface
- with SDRAM memory connected to the SDRAM Bank 1 or SDRAM bank 2:
-
- (#) Enable the clock for the FMC and associated GPIOs using the following functions:
- (++) RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FMC, ENABLE);
- (++) RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
-
- (#) FMC pins configuration
- (++) Connect the involved FMC pins to AF12 using the following function
- GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FMC);
- (++) Configure these FMC pins in alternate function mode by calling the function
- GPIO_Init();
-
- (#) Declare a FMC_SDRAMInitTypeDef structure, for example:
- FMC_SDRAMInitTypeDef FMC_SDRAMInitStructure;
- and fill the FMC_SDRAMInitStructure variable with the allowed values of
- the structure member.
-
- (#) Initialize the SDRAM Controller by calling the function
- FMC_SDRAMInit(&FMC_SDRAMInitStructure);
-
- (#) Declare a FMC_SDRAMCommandTypeDef structure, for example:
- FMC_SDRAMCommandTypeDef FMC_SDRAMCommandStructure;
- and fill the FMC_SDRAMCommandStructure variable with the allowed values of
- the structure member.
-
- (#) Configure the SDCMR register with the desired command parameters by calling
- the function FMC_SDRAMCmdConfig(&FMC_SDRAMCommandStructure);
-
- (#) At this stage, the SDRAM memory is ready for any valid command.
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief De-initializes the FMC SDRAM Banks registers to their default
- * reset values.
- * @param FMC_Bank: specifies the FMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM
- * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM
- * @retval None
- */
-void FMC_SDRAMDeInit(uint32_t FMC_Bank)
-{
- /* Check the parameter */
- assert_param(IS_FMC_SDRAM_BANK(FMC_Bank));
-
- FMC_Bank5_6->SDCR[FMC_Bank] = 0x000002D0;
- FMC_Bank5_6->SDTR[FMC_Bank] = 0x0FFFFFFF;
- FMC_Bank5_6->SDCMR = 0x00000000;
- FMC_Bank5_6->SDRTR = 0x00000000;
- FMC_Bank5_6->SDSR = 0x00000000;
-}
-
-/**
- * @brief Initializes the FMC SDRAM Banks according to the specified
- * parameters in the FMC_SDRAMInitStruct.
- * @param FMC_SDRAMInitStruct : pointer to a FMC_SDRAMInitTypeDef structure
- * that contains the configuration information for the FMC SDRAM
- * specified Banks.
- * @retval None
- */
-void FMC_SDRAMInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct)
-{
- /* temporary registers */
- uint32_t tmpr1 = 0;
- uint32_t tmpr2 = 0;
- uint32_t tmpr3 = 0;
- uint32_t tmpr4 = 0;
-
- /* Check the parameters */
-
- /* Control parameters */
- assert_param(IS_FMC_SDRAM_BANK(FMC_SDRAMInitStruct->FMC_Bank));
- assert_param(IS_FMC_COLUMNBITS_NUMBER(FMC_SDRAMInitStruct->FMC_ColumnBitsNumber));
- assert_param(IS_FMC_ROWBITS_NUMBER(FMC_SDRAMInitStruct->FMC_RowBitsNumber));
- assert_param(IS_FMC_SDMEMORY_WIDTH(FMC_SDRAMInitStruct->FMC_SDMemoryDataWidth));
- assert_param(IS_FMC_INTERNALBANK_NUMBER(FMC_SDRAMInitStruct->FMC_InternalBankNumber));
- assert_param(IS_FMC_CAS_LATENCY(FMC_SDRAMInitStruct->FMC_CASLatency));
- assert_param(IS_FMC_WRITE_PROTECTION(FMC_SDRAMInitStruct->FMC_WriteProtection));
- assert_param(IS_FMC_SDCLOCK_PERIOD(FMC_SDRAMInitStruct->FMC_SDClockPeriod));
- assert_param(IS_FMC_READ_BURST(FMC_SDRAMInitStruct->FMC_ReadBurst));
- assert_param(IS_FMC_READPIPE_DELAY(FMC_SDRAMInitStruct->FMC_ReadPipeDelay));
-
- /* Timing parameters */
- assert_param(IS_FMC_LOADTOACTIVE_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay));
- assert_param(IS_FMC_EXITSELFREFRESH_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay));
- assert_param(IS_FMC_SELFREFRESH_TIME(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime));
- assert_param(IS_FMC_ROWCYCLE_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay));
- assert_param(IS_FMC_WRITE_RECOVERY_TIME(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime));
- assert_param(IS_FMC_RP_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay));
- assert_param(IS_FMC_RCD_DELAY(FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay));
-
- /* SDRAM bank control register configuration */
- tmpr1 = (uint32_t)FMC_SDRAMInitStruct->FMC_ColumnBitsNumber |
- FMC_SDRAMInitStruct->FMC_RowBitsNumber |
- FMC_SDRAMInitStruct->FMC_SDMemoryDataWidth |
- FMC_SDRAMInitStruct->FMC_InternalBankNumber |
- FMC_SDRAMInitStruct->FMC_CASLatency |
- FMC_SDRAMInitStruct->FMC_WriteProtection |
- FMC_SDRAMInitStruct->FMC_SDClockPeriod |
- FMC_SDRAMInitStruct->FMC_ReadBurst |
- FMC_SDRAMInitStruct->FMC_ReadPipeDelay;
-
- if(FMC_SDRAMInitStruct->FMC_Bank == FMC_Bank1_SDRAM )
- {
- FMC_Bank5_6->SDCR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr1;
- }
- else /* SDCR2 "don't care" bits configuration */
- {
- tmpr3 = (uint32_t)FMC_SDRAMInitStruct->FMC_SDClockPeriod |
- FMC_SDRAMInitStruct->FMC_ReadBurst |
- FMC_SDRAMInitStruct->FMC_ReadPipeDelay;
-
- FMC_Bank5_6->SDCR[FMC_Bank1_SDRAM] = tmpr3;
- FMC_Bank5_6->SDCR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr1;
- }
- /* SDRAM bank timing register configuration */
- if(FMC_SDRAMInitStruct->FMC_Bank == FMC_Bank1_SDRAM )
- {
- tmpr2 = (uint32_t)((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)-1) |
- (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)-1) << 4) |
- (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)-1) << 8) |
- (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)-1) << 12) |
- (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime)-1) << 16) |
- (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay)-1) << 20) |
- (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay)-1) << 24);
-
- FMC_Bank5_6->SDTR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr2;
- }
- else /* SDTR "don't care bits configuration */
- {
- tmpr2 = (uint32_t)((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay)-1) |
- (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay)-1) << 4) |
- (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime)-1) << 8) |
- (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime)-1) << 16);
-
- tmpr4 = (uint32_t)(((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay)-1) << 12) |
- (((FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay)-1) << 20);
-
- FMC_Bank5_6->SDTR[FMC_Bank1_SDRAM] = tmpr4;
- FMC_Bank5_6->SDTR[FMC_SDRAMInitStruct->FMC_Bank] = tmpr2;
- }
-
-}
-
-/**
- * @brief Fills each FMC_SDRAMInitStruct member with its default value.
- * @param FMC_SDRAMInitStruct: pointer to a FMC_SDRAMInitTypeDef structure
- * which will be initialized.
- * @retval None
- */
-void FMC_SDRAMStructInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct)
-{
- /* Reset SDRAM Init structure parameters values */
- FMC_SDRAMInitStruct->FMC_Bank = FMC_Bank1_SDRAM;
- FMC_SDRAMInitStruct->FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b;
- FMC_SDRAMInitStruct->FMC_RowBitsNumber = FMC_RowBits_Number_11b;
- FMC_SDRAMInitStruct->FMC_SDMemoryDataWidth = FMC_SDMemory_Width_16b;
- FMC_SDRAMInitStruct->FMC_InternalBankNumber = FMC_InternalBank_Number_4;
- FMC_SDRAMInitStruct->FMC_CASLatency = FMC_CAS_Latency_1;
- FMC_SDRAMInitStruct->FMC_WriteProtection = FMC_Write_Protection_Enable;
- FMC_SDRAMInitStruct->FMC_SDClockPeriod = FMC_SDClock_Disable;
- FMC_SDRAMInitStruct->FMC_ReadBurst = FMC_Read_Burst_Disable;
- FMC_SDRAMInitStruct->FMC_ReadPipeDelay = FMC_ReadPipe_Delay_0;
-
- FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_LoadToActiveDelay = 16;
- FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_ExitSelfRefreshDelay = 16;
- FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_SelfRefreshTime = 16;
- FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RowCycleDelay = 16;
- FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_WriteRecoveryTime = 16;
- FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RPDelay = 16;
- FMC_SDRAMInitStruct->FMC_SDRAMTimingStruct->FMC_RCDDelay = 16;
-
-}
-
-/**
- * @brief Configures the SDRAM memory command issued when the device is accessed.
- * @param FMC_SDRAMCommandStruct: pointer to a FMC_SDRAMCommandTypeDef structure
- * which will be configured.
- * @retval None
- */
-void FMC_SDRAMCmdConfig(FMC_SDRAMCommandTypeDef* FMC_SDRAMCommandStruct)
-{
- uint32_t tmpr = 0x0;
-
- /* check parameters */
- assert_param(IS_FMC_COMMAND_MODE(FMC_SDRAMCommandStruct->FMC_CommandMode));
- assert_param(IS_FMC_COMMAND_TARGET(FMC_SDRAMCommandStruct->FMC_CommandTarget));
- assert_param(IS_FMC_AUTOREFRESH_NUMBER(FMC_SDRAMCommandStruct->FMC_AutoRefreshNumber));
- assert_param(IS_FMC_MODE_REGISTER(FMC_SDRAMCommandStruct->FMC_ModeRegisterDefinition));
-
- tmpr = (uint32_t)(FMC_SDRAMCommandStruct->FMC_CommandMode |
- FMC_SDRAMCommandStruct->FMC_CommandTarget |
- (((FMC_SDRAMCommandStruct->FMC_AutoRefreshNumber)-1)<<5) |
- ((FMC_SDRAMCommandStruct->FMC_ModeRegisterDefinition)<<9));
-
- FMC_Bank5_6->SDCMR = tmpr;
-
-}
-
-
-/**
- * @brief Returns the indicated FMC SDRAM bank mode status.
- * @param SDRAM_Bank: Defines the FMC SDRAM bank. This parameter can be
- * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
- * @retval The FMC SDRAM bank mode status
- */
-uint32_t FMC_GetModeStatus(uint32_t SDRAM_Bank)
-{
- uint32_t tmpreg = 0;
-
- /* Check the parameter */
- assert_param(IS_FMC_SDRAM_BANK(SDRAM_Bank));
-
- /* Get the busy flag status */
- if(SDRAM_Bank == FMC_Bank1_SDRAM)
- {
- tmpreg = (uint32_t)(FMC_Bank5_6->SDSR & FMC_SDSR_MODES1);
- }
- else
- {
- tmpreg = ((uint32_t)(FMC_Bank5_6->SDSR & FMC_SDSR_MODES2) >> 2);
- }
-
- /* Return the mode status */
- return tmpreg;
-}
-
-/**
- * @brief defines the SDRAM Memory Refresh rate.
- * @param FMC_Count: specifies the Refresh timer count.
- * @retval None
- */
-void FMC_SetRefreshCount(uint32_t FMC_Count)
-{
- /* check the parameters */
- assert_param(IS_FMC_REFRESH_COUNT(FMC_Count));
-
- FMC_Bank5_6->SDRTR |= (FMC_Count<<1);
-
-}
-
-/**
- * @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands.
- * @param FMC_Number: specifies the auto Refresh number.
- * @retval None
- */
-void FMC_SetAutoRefresh_Number(uint32_t FMC_Number)
-{
- /* check the parameters */
- assert_param(IS_FMC_AUTOREFRESH_NUMBER(FMC_Number));
-
- FMC_Bank5_6->SDCMR |= (FMC_Number << 5);
-}
-
-/**
- * @brief Enables or disables write protection to the specified FMC SDRAM Bank.
- * @param SDRAM_Bank: Defines the FMC SDRAM bank. This parameter can be
- * FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
- * @param NewState: new state of the write protection flag.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FMC_SDRAMWriteProtectionConfig(uint32_t SDRAM_Bank, FunctionalState NewState)
-{
- /* Check the parameter */
- assert_param(IS_FUNCTIONAL_STATE(NewState));
- assert_param(IS_FMC_SDRAM_BANK(SDRAM_Bank));
-
- if (NewState != DISABLE)
- {
- FMC_Bank5_6->SDCR[SDRAM_Bank] |= FMC_Write_Protection_Enable;
- }
- else
- {
- FMC_Bank5_6->SDCR[SDRAM_Bank] &= SDCR_WriteProtection_RESET;
- }
-
-}
-
-/**
- * @}
- */
-
-/** @defgroup FMC_Group5 Interrupts and flags management functions
- * @brief Interrupts and flags management functions
- *
-@verbatim
- ===============================================================================
- ##### Interrupts and flags management functions #####
- ===============================================================================
-
-@endverbatim
- * @{
- */
-
-/**
- * @brief Enables or disables the specified FMC interrupts.
- * @param FMC_Bank: specifies the FMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FMC_Bank2_NAND: FMC Bank2 NAND
- * @arg FMC_Bank3_NAND: FMC Bank3 NAND
- * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD
- * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM
- * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM
- * @param FMC_IT: specifies the FMC interrupt sources to be enabled or disabled.
- * This parameter can be any combination of the following values:
- * @arg FMC_IT_RisingEdge: Rising edge detection interrupt.
- * @arg FMC_IT_Level: Level edge detection interrupt.
- * @arg FMC_IT_FallingEdge: Falling edge detection interrupt.
- * @arg FMC_IT_Refresh: Refresh error detection interrupt.
- * @param NewState: new state of the specified FMC interrupts.
- * This parameter can be: ENABLE or DISABLE.
- * @retval None
- */
-void FMC_ITConfig(uint32_t FMC_Bank, uint32_t FMC_IT, FunctionalState NewState)
-{
- assert_param(IS_FMC_IT_BANK(FMC_Bank));
- assert_param(IS_FMC_IT(FMC_IT));
- assert_param(IS_FUNCTIONAL_STATE(NewState));
-
- if (NewState != DISABLE)
- {
- /* Enable the selected FMC_Bank2 interrupts */
- if(FMC_Bank == FMC_Bank2_NAND)
- {
- FMC_Bank2->SR2 |= FMC_IT;
- }
- /* Enable the selected FMC_Bank3 interrupts */
- else if (FMC_Bank == FMC_Bank3_NAND)
- {
- FMC_Bank3->SR3 |= FMC_IT;
- }
- /* Enable the selected FMC_Bank4 interrupts */
- else if (FMC_Bank == FMC_Bank4_PCCARD)
- {
- FMC_Bank4->SR4 |= FMC_IT;
- }
- /* Enable the selected FMC_Bank5_6 interrupt */
- else
- {
- /* Enables the interrupt if the refresh error flag is set */
- FMC_Bank5_6->SDRTR |= FMC_IT;
- }
- }
- else
- {
- /* Disable the selected FMC_Bank2 interrupts */
- if(FMC_Bank == FMC_Bank2_NAND)
- {
-
- FMC_Bank2->SR2 &= (uint32_t)~FMC_IT;
- }
- /* Disable the selected FMC_Bank3 interrupts */
- else if (FMC_Bank == FMC_Bank3_NAND)
- {
- FMC_Bank3->SR3 &= (uint32_t)~FMC_IT;
- }
- /* Disable the selected FMC_Bank4 interrupts */
- else if(FMC_Bank == FMC_Bank4_PCCARD)
- {
- FMC_Bank4->SR4 &= (uint32_t)~FMC_IT;
- }
- /* Disable the selected FMC_Bank5_6 interrupt */
- else
- {
- /* Disables the interrupt if the refresh error flag is not set */
- FMC_Bank5_6->SDRTR &= (uint32_t)~FMC_IT;
- }
- }
-}
-
-/**
- * @brief Checks whether the specified FMC flag is set or not.
- * @param FMC_Bank: specifies the FMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FMC_Bank2_NAND: FMC Bank2 NAND
- * @arg FMC_Bank3_NAND: FMC Bank3 NAND
- * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD
- * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM
- * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM
- * @arg FMC_Bank1_SDRAM | FMC_Bank2_SDRAM: FMC Bank1 or Bank2 SDRAM
- * @param FMC_FLAG: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg FMC_FLAG_RisingEdge: Rising edge detection Flag.
- * @arg FMC_FLAG_Level: Level detection Flag.
- * @arg FMC_FLAG_FallingEdge: Falling edge detection Flag.
- * @arg FMC_FLAG_FEMPT: Fifo empty Flag.
- * @arg FMC_FLAG_Refresh: Refresh error Flag.
- * @arg FMC_FLAG_Busy: Busy status Flag.
- * @retval The new state of FMC_FLAG (SET or RESET).
- */
-FlagStatus FMC_GetFlagStatus(uint32_t FMC_Bank, uint32_t FMC_FLAG)
-{
- FlagStatus bitstatus = RESET;
- uint32_t tmpsr = 0x00000000;
-
- /* Check the parameters */
- assert_param(IS_FMC_GETFLAG_BANK(FMC_Bank));
- assert_param(IS_FMC_GET_FLAG(FMC_FLAG));
-
- if(FMC_Bank == FMC_Bank2_NAND)
- {
- tmpsr = FMC_Bank2->SR2;
- }
- else if(FMC_Bank == FMC_Bank3_NAND)
- {
- tmpsr = FMC_Bank3->SR3;
- }
- else if(FMC_Bank == FMC_Bank4_PCCARD)
- {
- tmpsr = FMC_Bank4->SR4;
- }
- else
- {
- tmpsr = FMC_Bank5_6->SDSR;
- }
-
- /* Get the flag status */
- if ((tmpsr & FMC_FLAG) != FMC_FLAG )
- {
- bitstatus = RESET;
- }
- else
- {
- bitstatus = SET;
- }
- /* Return the flag status */
- return bitstatus;
-}
-
-/**
- * @brief Clears the FMC's pending flags.
- * @param FMC_Bank: specifies the FMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FMC_Bank2_NAND: FMC Bank2 NAND
- * @arg FMC_Bank3_NAND: FMC Bank3 NAND
- * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD
- * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM
- * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM
- * @param FMC_FLAG: specifies the flag to clear.
- * This parameter can be any combination of the following values:
- * @arg FMC_FLAG_RisingEdge: Rising edge detection Flag.
- * @arg FMC_FLAG_Level: Level detection Flag.
- * @arg FMC_FLAG_FallingEdge: Falling edge detection Flag.
- * @arg FMC_FLAG_Refresh: Refresh error Flag.
- * @retval None
- */
-void FMC_ClearFlag(uint32_t FMC_Bank, uint32_t FMC_FLAG)
-{
- /* Check the parameters */
- assert_param(IS_FMC_GETFLAG_BANK(FMC_Bank));
- assert_param(IS_FMC_CLEAR_FLAG(FMC_FLAG)) ;
-
- if(FMC_Bank == FMC_Bank2_NAND)
- {
- FMC_Bank2->SR2 &= (~FMC_FLAG);
- }
- else if(FMC_Bank == FMC_Bank3_NAND)
- {
- FMC_Bank3->SR3 &= (~FMC_FLAG);
- }
- else if(FMC_Bank == FMC_Bank4_PCCARD)
- {
- FMC_Bank4->SR4 &= (~FMC_FLAG);
- }
- /* FMC_Bank5_6 SDRAM*/
- else
- {
- FMC_Bank5_6->SDRTR &= (~FMC_FLAG);
- }
-
-}
-
-/**
- * @brief Checks whether the specified FMC interrupt has occurred or not.
- * @param FMC_Bank: specifies the FMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FMC_Bank2_NAND: FMC Bank2 NAND
- * @arg FMC_Bank3_NAND: FMC Bank3 NAND
- * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD
- * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM
- * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM
- * @param FMC_IT: specifies the FMC interrupt source to check.
- * This parameter can be one of the following values:
- * @arg FMC_IT_RisingEdge: Rising edge detection interrupt.
- * @arg FMC_IT_Level: Level edge detection interrupt.
- * @arg FMC_IT_FallingEdge: Falling edge detection interrupt.
- * @arg FMC_IT_Refresh: Refresh error detection interrupt.
- * @retval The new state of FMC_IT (SET or RESET).
- */
-ITStatus FMC_GetITStatus(uint32_t FMC_Bank, uint32_t FMC_IT)
-{
- ITStatus bitstatus = RESET;
- uint32_t tmpsr = 0x0;
- uint32_t tmpsr2 = 0x0;
- uint32_t itstatus = 0x0;
- uint32_t itenable = 0x0;
-
- /* Check the parameters */
- assert_param(IS_FMC_IT_BANK(FMC_Bank));
- assert_param(IS_FMC_GET_IT(FMC_IT));
-
- if(FMC_Bank == FMC_Bank2_NAND)
- {
- tmpsr = FMC_Bank2->SR2;
- }
- else if(FMC_Bank == FMC_Bank3_NAND)
- {
- tmpsr = FMC_Bank3->SR3;
- }
- else if(FMC_Bank == FMC_Bank4_PCCARD)
- {
- tmpsr = FMC_Bank4->SR4;
- }
- /* FMC_Bank5_6 SDRAM*/
- else
- {
- tmpsr = FMC_Bank5_6->SDRTR;
- tmpsr2 = FMC_Bank5_6->SDSR;
- }
-
- /* get the IT enable bit status*/
- itenable = tmpsr & FMC_IT;
-
- /* get the corresponding IT Flag status*/
- if((FMC_Bank == FMC_Bank1_SDRAM) || (FMC_Bank == FMC_Bank2_SDRAM))
- {
- itstatus = tmpsr2 & FMC_SDSR_RE;
- }
- else
- {
- itstatus = tmpsr & (FMC_IT >> 3);
- }
-
- if ((itstatus != (uint32_t)RESET) && (itenable != (uint32_t)RESET))
- {
- bitstatus = SET;
- }
- else
- {
- bitstatus = RESET;
- }
- return bitstatus;
-}
-
-/**
- * @brief Clears the FMC's interrupt pending bits.
- * @param FMC_Bank: specifies the FMC Bank to be used
- * This parameter can be one of the following values:
- * @arg FMC_Bank2_NAND: FMC Bank2 NAND
- * @arg FMC_Bank3_NAND: FMC Bank3 NAND
- * @arg FMC_Bank4_PCCARD: FMC Bank4 PCCARD
- * @arg FMC_Bank1_SDRAM: FMC Bank1 SDRAM
- * @arg FMC_Bank2_SDRAM: FMC Bank2 SDRAM
- * @param FMC_IT: specifies the interrupt pending bit to clear.
- * This parameter can be any combination of the following values:
- * @arg FMC_IT_RisingEdge: Rising edge detection interrupt.
- * @arg FMC_IT_Level: Level edge detection interrupt.
- * @arg FMC_IT_FallingEdge: Falling edge detection interrupt.
- * @arg FMC_IT_Refresh: Refresh error detection interrupt.
- * @retval None
- */
-void FMC_ClearITPendingBit(uint32_t FMC_Bank, uint32_t FMC_IT)
-{
- /* Check the parameters */
- assert_param(IS_FMC_IT_BANK(FMC_Bank));
- assert_param(IS_FMC_IT(FMC_IT));
-
- if(FMC_Bank == FMC_Bank2_NAND)
- {
- FMC_Bank2->SR2 &= ~(FMC_IT >> 3);
- }
- else if(FMC_Bank == FMC_Bank3_NAND)
- {
- FMC_Bank3->SR3 &= ~(FMC_IT >> 3);
- }
- else if(FMC_Bank == FMC_Bank4_PCCARD)
- {
- FMC_Bank4->SR4 &= ~(FMC_IT >> 3);
- }
- /* FMC_Bank5_6 SDRAM*/
- else
- {
- FMC_Bank5_6->SDRTR |= FMC_SDRTR_CRE;
- }
-}
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
diff --git a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/stmdrivers/stm32f4xx_fmc.h b/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/stmdrivers/stm32f4xx_fmc.h deleted file mode 100644 index 319f53c..0000000 --- a/demos/STM32/RT-STM32F429-DISCOVERY-DMA2D/stmdrivers/stm32f4xx_fmc.h +++ /dev/null @@ -1,1144 +0,0 @@ -/**
- ******************************************************************************
- * @file stm32f4xx_fmc.h
- * @author MCD Application Team
- * @version V1.2.1
- * @date 19-September-2013
- * @brief This file contains all the functions prototypes for the FMC firmware
- * library.
- ******************************************************************************
- * @attention
- *
- * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
- * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
- * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
- * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
- * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
- * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
- *
- * <h2><center>© COPYRIGHT 2011 STMicroelectronics</center></h2>
- ******************************************************************************
- */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_FMC_H
-#define __STM32F4xx_FMC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-//FIXME this should not be needed
-#define STM32F429_439xx
-
-/* Includes ------------------------------------------------------------------*/
-#include "ch.h"
-#include "stm32f4xx.h"
-#include <stddef.h>
-#include <stdint.h>
-#include <stdbool.h>
-
-/** @addtogroup STM32F4xx_StdPeriph_Driver
- * @{
- */
-
-/** @addtogroup FMC
- * @{
- */
-
-/* Exported types ------------------------------------------------------------*/
-
-/**
- * @brief Timing parameters For NOR/SRAM Banks
- */
-typedef struct
-{
- uint32_t FMC_AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the address setup time.
- This parameter can be a value between 0 and 15.
- @note This parameter is not used with synchronous NOR Flash memories. */
-
- uint32_t FMC_AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the address hold time.
- This parameter can be a value between 1 and 15.
- @note This parameter is not used with synchronous NOR Flash memories.*/
-
- uint32_t FMC_DataSetupTime; /*!< Defines the number of HCLK cycles to configure
- the duration of the data setup time.
- This parameter can be a value between 1 and 255.
- @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
-
- uint32_t FMC_BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
- the duration of the bus turnaround.
- This parameter can be a value between 0 and 15.
- @note This parameter is only used for multiplexed NOR Flash memories. */
-
- uint32_t FMC_CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
- This parameter can be a value between 1 and 15.
- @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
-
- uint32_t FMC_DataLatency; /*!< Defines the number of memory clock cycles to issue
- to the memory before getting the first data.
- The parameter value depends on the memory type as shown below:
- - It must be set to 0 in case of a CRAM
- - It is don't care in asynchronous NOR, SRAM or ROM accesses
- - It may assume a value between 0 and 15 in NOR Flash memories
- with synchronous burst mode enable */
-
- uint32_t FMC_AccessMode; /*!< Specifies the asynchronous access mode.
- This parameter can be a value of @ref FMC_Access_Mode */
-}FMC_NORSRAMTimingInitTypeDef;
-
-/**
- * @brief FMC NOR/SRAM Init structure definition
- */
-typedef struct
-{
- uint32_t FMC_Bank; /*!< Specifies the NOR/SRAM memory bank that will be used.
- This parameter can be a value of @ref FMC_NORSRAM_Bank */
-
- uint32_t FMC_DataAddressMux; /*!< Specifies whether the address and data values are
- multiplexed on the databus or not.
- This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
-
- uint32_t FMC_MemoryType; /*!< Specifies the type of external memory attached to
- the corresponding memory bank.
- This parameter can be a value of @ref FMC_Memory_Type */
-
- uint32_t FMC_MemoryDataWidth; /*!< Specifies the external memory device width.
- This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
-
- uint32_t FMC_BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
- valid only with synchronous burst Flash memories.
- This parameter can be a value of @ref FMC_Burst_Access_Mode */
-
- uint32_t FMC_WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
- the Flash memory in burst mode.
- This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
-
- uint32_t FMC_WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
- memory, valid only when accessing Flash memories in burst mode.
- This parameter can be a value of @ref FMC_Wrap_Mode */
-
- uint32_t FMC_WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
- clock cycle before the wait state or during the wait state,
- valid only when accessing memories in burst mode.
- This parameter can be a value of @ref FMC_Wait_Timing */
-
- uint32_t FMC_WriteOperation; /*!< Enables or disables the write operation in the selected bank by the FMC.
- This parameter can be a value of @ref FMC_Write_Operation */
-
- uint32_t FMC_WaitSignal; /*!< Enables or disables the wait state insertion via wait
- signal, valid for Flash memory access in burst mode.
- This parameter can be a value of @ref FMC_Wait_Signal */
-
- uint32_t FMC_ExtendedMode; /*!< Enables or disables the extended mode.
- This parameter can be a value of @ref FMC_Extended_Mode */
-
- uint32_t FMC_AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
- valid only with asynchronous Flash memories.
- This parameter can be a value of @ref FMC_AsynchronousWait */
-
- uint32_t FMC_WriteBurst; /*!< Enables or disables the write burst operation.
- This parameter can be a value of @ref FMC_Write_Burst */
-
- uint32_t FMC_ContinousClock; /*!< Enables or disables the FMC clock output to external memory devices.
- This parameter is only enabled through the FMC_BCR1 register, and don't care
- through FMC_BCR2..4 registers.
- This parameter can be a value of @ref FMC_Continous_Clock */
-
-
- FMC_NORSRAMTimingInitTypeDef* FMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the Extended Mode is not used*/
-
- FMC_NORSRAMTimingInitTypeDef* FMC_WriteTimingStruct; /*!< Timing Parameters for write access if the Extended Mode is used*/
-}FMC_NORSRAMInitTypeDef;
-
-/**
- * @brief Timing parameters For FMC NAND and PCCARD Banks
- */
-typedef struct
-{
- uint32_t FMC_SetupTime; /*!< Defines the number of HCLK cycles to setup address before
- the command assertion for NAND-Flash read or write access
- to common/Attribute or I/O memory space (depending on
- the memory space timing to be configured).
- This parameter can be a value between 0 and 255.*/
-
- uint32_t FMC_WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
- command for NAND-Flash read or write access to
- common/Attribute or I/O memory space (depending on the
- memory space timing to be configured).
- This parameter can be a number between 0 and 255 */
-
- uint32_t FMC_HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
- (and data for write access) after the command de-assertion
- for NAND-Flash read or write access to common/Attribute
- or I/O memory space (depending on the memory space timing
- to be configured).
- This parameter can be a number between 0 and 255 */
-
- uint32_t FMC_HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
- databus is kept in HiZ after the start of a NAND-Flash
- write access to common/Attribute or I/O memory space (depending
- on the memory space timing to be configured).
- This parameter can be a number between 0 and 255 */
-}FMC_NAND_PCCARDTimingInitTypeDef;
-
-/**
- * @brief FMC NAND Init structure definition
- */
-typedef struct
-{
- uint32_t FMC_Bank; /*!< Specifies the NAND memory bank that will be used.
- This parameter can be a value of @ref FMC_NAND_Bank */
-
- uint32_t FMC_Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory Bank.
- This parameter can be any value of @ref FMC_Wait_feature */
-
- uint32_t FMC_MemoryDataWidth; /*!< Specifies the external memory device width.
- This parameter can be any value of @ref FMC_NAND_Data_Width */
-
- uint32_t FMC_ECC; /*!< Enables or disables the ECC computation.
- This parameter can be any value of @ref FMC_ECC */
-
- uint32_t FMC_ECCPageSize; /*!< Defines the page size for the extended ECC.
- This parameter can be any value of @ref FMC_ECC_Page_Size */
-
- uint32_t FMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between CLE low and RE low.
- This parameter can be a value between 0 and 255. */
-
- uint32_t FMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between ALE low and RE low.
- This parameter can be a number between 0 and 255 */
-
- FMC_NAND_PCCARDTimingInitTypeDef* FMC_CommonSpaceTimingStruct; /*!< FMC Common Space Timing */
-
- FMC_NAND_PCCARDTimingInitTypeDef* FMC_AttributeSpaceTimingStruct; /*!< FMC Attribute Space Timing */
-}FMC_NANDInitTypeDef;
-
-/**
- * @brief FMC PCCARD Init structure definition
- */
-
-typedef struct
-{
- uint32_t FMC_Waitfeature; /*!< Enables or disables the Wait feature for the Memory Bank.
- This parameter can be any value of @ref FMC_Wait_feature */
-
- uint32_t FMC_TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between CLE low and RE low.
- This parameter can be a value between 0 and 255. */
-
- uint32_t FMC_TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
- delay between ALE low and RE low.
- This parameter can be a number between 0 and 255 */
-
-
- FMC_NAND_PCCARDTimingInitTypeDef* FMC_CommonSpaceTimingStruct; /*!< FMC Common Space Timing */
-
- FMC_NAND_PCCARDTimingInitTypeDef* FMC_AttributeSpaceTimingStruct; /*!< FMC Attribute Space Timing */
-
- FMC_NAND_PCCARDTimingInitTypeDef* FMC_IOSpaceTimingStruct; /*!< FMC IO Space Timing */
-}FMC_PCCARDInitTypeDef;
-
-/**
- * @brief Timing parameters for FMC SDRAM Banks
- */
-
-typedef struct
-{
- uint32_t FMC_LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
- an active or Refresh command in number of memory clock cycles.
- This parameter can be a value between 1 and 16. */
-
- uint32_t FMC_ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
- issuing the Activate command in number of memory clock cycles.
- This parameter can be a value between 1 and 16. */
-
- uint32_t FMC_SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
- cycles.
- This parameter can be a value between 1 and 16. */
-
- uint32_t FMC_RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
- and the delay between two consecutive Refresh commands in number of
- memory clock cycles.
- This parameter can be a value between 1 and 16. */
-
- uint32_t FMC_WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
- This parameter can be a value between 1 and 16. */
-
- uint32_t FMC_RPDelay; /*!< Defines the delay between a Precharge Command and an other command
- in number of memory clock cycles.
- This parameter can be a value between 1 and 16. */
-
- uint32_t FMC_RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write command
- in number of memory clock cycles.
- This parameter can be a value between 1 and 16. */
-
-}FMC_SDRAMTimingInitTypeDef;
-
-/**
- * @brief Command parameters for FMC SDRAM Banks
- */
-
-
-typedef struct
-{
- uint32_t FMC_CommandMode; /*!< Defines the command issued to the SDRAM device.
- This parameter can be a value of @ref FMC_Command_Mode. */
-
- uint32_t FMC_CommandTarget; /*!< Defines which bank (1 or 2) the command will be issued to.
- This parameter can be a value of @ref FMC_Command_Target. */
-
- uint32_t FMC_AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
- in auto refresh mode.
- This parameter can be a value between 1 and 16. */
-
- uint32_t FMC_ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */
-
-}FMC_SDRAMCommandTypeDef;
-
-/**
- * @brief FMC SDRAM Init structure definition
- */
-
-typedef struct
-{
- uint32_t FMC_Bank; /*!< Specifies the SDRAM memory bank that will be used.
- This parameter can be a value of @ref FMC_SDRAM_Bank */
-
- uint32_t FMC_ColumnBitsNumber; /*!< Defines the number of bits of column address.
- This parameter can be a value of @ref FMC_ColumnBits_Number. */
-
- uint32_t FMC_RowBitsNumber; /*!< Defines the number of bits of column address..
- This parameter can be a value of @ref FMC_RowBits_Number. */
-
- uint32_t FMC_SDMemoryDataWidth; /*!< Defines the memory device width.
- This parameter can be a value of @ref FMC_SDMemory_Data_Width. */
-
- uint32_t FMC_InternalBankNumber; /*!< Defines the number of bits of column address.
- This parameter can be of @ref FMC_InternalBank_Number. */
-
- uint32_t FMC_CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
- This parameter can be a value of @ref FMC_CAS_Latency. */
-
- uint32_t FMC_WriteProtection; /*!< Enables the SDRAM bank to be accessed in write mode.
- This parameter can be a value of @ref FMC_Write_Protection. */
-
- uint32_t FMC_SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM Banks and they allow to disable
- the clock before changing frequency.
- This parameter can be a value of @ref FMC_SDClock_Period. */
-
- uint32_t FMC_ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read commands
- during the CAS latency and stores data in the Read FIFO.
- This parameter can be a value of @ref FMC_Read_Burst. */
-
- uint32_t FMC_ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
- This parameter can be a value of @ref FMC_ReadPipe_Delay. */
-
- FMC_SDRAMTimingInitTypeDef* FMC_SDRAMTimingStruct; /*!< Timing Parameters for write and read access*/
-
-}FMC_SDRAMInitTypeDef;
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup FMC_Exported_Constants
- * @{
- */
-
-/** @defgroup FMC_NORSRAM_Bank
- * @{
- */
-#define FMC_Bank1_NORSRAM1 ((uint32_t)0x00000000)
-#define FMC_Bank1_NORSRAM2 ((uint32_t)0x00000002)
-#define FMC_Bank1_NORSRAM3 ((uint32_t)0x00000004)
-#define FMC_Bank1_NORSRAM4 ((uint32_t)0x00000006)
-
-#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_Bank1_NORSRAM1) || \
- ((BANK) == FMC_Bank1_NORSRAM2) || \
- ((BANK) == FMC_Bank1_NORSRAM3) || \
- ((BANK) == FMC_Bank1_NORSRAM4))
-/**
- * @}
- */
-
-/** @defgroup FMC_NAND_Bank
- * @{
- */
-#define FMC_Bank2_NAND ((uint32_t)0x00000010)
-#define FMC_Bank3_NAND ((uint32_t)0x00000100)
-
-#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \
- ((BANK) == FMC_Bank3_NAND))
-/**
- * @}
- */
-
-/** @defgroup FMC_PCCARD_Bank
- * @{
- */
-#define FMC_Bank4_PCCARD ((uint32_t)0x00001000)
-/**
- * @}
- */
-
-/** @defgroup FMC_SDRAM_Bank
- * @{
- */
-#define FMC_Bank1_SDRAM ((uint32_t)0x00000000)
-#define FMC_Bank2_SDRAM ((uint32_t)0x00000001)
-
-#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_Bank1_SDRAM) || \
- ((BANK) == FMC_Bank2_SDRAM))
-
-/**
- * @}
- */
-
-
-/** @defgroup FMC_NOR_SRAM_Controller
- * @{
- */
-
-/** @defgroup FMC_Data_Address_Bus_Multiplexing
- * @{
- */
-
-#define FMC_DataAddressMux_Disable ((uint32_t)0x00000000)
-#define FMC_DataAddressMux_Enable ((uint32_t)0x00000002)
-
-#define IS_FMC_MUX(MUX) (((MUX) == FMC_DataAddressMux_Disable) || \
- ((MUX) == FMC_DataAddressMux_Enable))
-/**
- * @}
- */
-
-/** @defgroup FMC_Memory_Type
- * @{
- */
-
-#define FMC_MemoryType_SRAM ((uint32_t)0x00000000)
-#define FMC_MemoryType_PSRAM ((uint32_t)0x00000004)
-#define FMC_MemoryType_NOR ((uint32_t)0x00000008)
-
-#define IS_FMC_MEMORY(MEMORY) (((MEMORY) == FMC_MemoryType_SRAM) || \
- ((MEMORY) == FMC_MemoryType_PSRAM)|| \
- ((MEMORY) == FMC_MemoryType_NOR))
-/**
- * @}
- */
-
-/** @defgroup FMC_NORSRAM_Data_Width
- * @{
- */
-
-#define FMC_NORSRAM_MemoryDataWidth_8b ((uint32_t)0x00000000)
-#define FMC_NORSRAM_MemoryDataWidth_16b ((uint32_t)0x00000010)
-#define FMC_NORSRAM_MemoryDataWidth_32b ((uint32_t)0x00000020)
-
-#define IS_FMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NORSRAM_MemoryDataWidth_8b) || \
- ((WIDTH) == FMC_NORSRAM_MemoryDataWidth_16b) || \
- ((WIDTH) == FMC_NORSRAM_MemoryDataWidth_32b))
-/**
- * @}
- */
-
-/** @defgroup FMC_Burst_Access_Mode
- * @{
- */
-
-#define FMC_BurstAccessMode_Disable ((uint32_t)0x00000000)
-#define FMC_BurstAccessMode_Enable ((uint32_t)0x00000100)
-
-#define IS_FMC_BURSTMODE(STATE) (((STATE) == FMC_BurstAccessMode_Disable) || \
- ((STATE) == FMC_BurstAccessMode_Enable))
-/**
- * @}
- */
-
-/** @defgroup FMC_AsynchronousWait
- * @{
- */
-#define FMC_AsynchronousWait_Disable ((uint32_t)0x00000000)
-#define FMC_AsynchronousWait_Enable ((uint32_t)0x00008000)
-
-#define IS_FMC_ASYNWAIT(STATE) (((STATE) == FMC_AsynchronousWait_Disable) || \
- ((STATE) == FMC_AsynchronousWait_Enable))
-/**
- * @}
- */
-
-/** @defgroup FMC_Wait_Signal_Polarity
- * @{
- */
-#define FMC_WaitSignalPolarity_Low ((uint32_t)0x00000000)
-#define FMC_WaitSignalPolarity_High ((uint32_t)0x00000200)
-
-#define IS_FMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FMC_WaitSignalPolarity_Low) || \
- ((POLARITY) == FMC_WaitSignalPolarity_High))
-/**
- * @}
- */
-
-/** @defgroup FMC_Wrap_Mode
- * @{
- */
-#define FMC_WrapMode_Disable ((uint32_t)0x00000000)
-#define FMC_WrapMode_Enable ((uint32_t)0x00000400)
-
-#define IS_FMC_WRAP_MODE(MODE) (((MODE) == FMC_WrapMode_Disable) || \
- ((MODE) == FMC_WrapMode_Enable))
-/**
- * @}
- */
-
-/** @defgroup FMC_Wait_Timing
- * @{
- */
-#define FMC_WaitSignalActive_BeforeWaitState ((uint32_t)0x00000000)
-#define FMC_WaitSignalActive_DuringWaitState ((uint32_t)0x00000800)
-
-#define IS_FMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FMC_WaitSignalActive_BeforeWaitState) || \
- ((ACTIVE) == FMC_WaitSignalActive_DuringWaitState))
-/**
- * @}
- */
-
-/** @defgroup FMC_Write_Operation
- * @{
- */
-#define FMC_WriteOperation_Disable ((uint32_t)0x00000000)
-#define FMC_WriteOperation_Enable ((uint32_t)0x00001000)
-
-#define IS_FMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FMC_WriteOperation_Disable) || \
- ((OPERATION) == FMC_WriteOperation_Enable))
-/**
- * @}
- */
-
-/** @defgroup FMC_Wait_Signal
- * @{
- */
-#define FMC_WaitSignal_Disable ((uint32_t)0x00000000)
-#define FMC_WaitSignal_Enable ((uint32_t)0x00002000)
-
-#define IS_FMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FMC_WaitSignal_Disable) || \
- ((SIGNAL) == FMC_WaitSignal_Enable))
-/**
- * @}
- */
-
-/** @defgroup FMC_Extended_Mode
- * @{
- */
-#define FMC_ExtendedMode_Disable ((uint32_t)0x00000000)
-#define FMC_ExtendedMode_Enable ((uint32_t)0x00004000)
-
-#define IS_FMC_EXTENDED_MODE(MODE) (((MODE) == FMC_ExtendedMode_Disable) || \
- ((MODE) == FMC_ExtendedMode_Enable))
-/**
- * @}
- */
-
-/** @defgroup FMC_Write_Burst
- * @{
- */
-
-#define FMC_WriteBurst_Disable ((uint32_t)0x00000000)
-#define FMC_WriteBurst_Enable ((uint32_t)0x00080000)
-
-#define IS_FMC_WRITE_BURST(BURST) (((BURST) == FMC_WriteBurst_Disable) || \
- ((BURST) == FMC_WriteBurst_Enable))
-/**
- * @}
- */
-
-/** @defgroup FMC_Continous_Clock
- * @{
- */
-
-#define FMC_CClock_SyncOnly ((uint32_t)0x00000000)
-#define FMC_CClock_SyncAsync ((uint32_t)0x00100000)
-
-#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CClock_SyncOnly) || \
- ((CCLOCK) == FMC_CClock_SyncAsync))
-/**
- * @}
- */
-
-/** @defgroup FMC_Address_Setup_Time
- * @{
- */
-#define IS_FMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
-/**
- * @}
- */
-
-/** @defgroup FMC_Address_Hold_Time
- * @{
- */
-#define IS_FMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
-/**
- * @}
- */
-
-/** @defgroup FMC_Data_Setup_Time
- * @{
- */
-#define IS_FMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
-/**
- * @}
- */
-
-/** @defgroup FMC_Bus_Turn_around_Duration
- * @{
- */
-#define IS_FMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
-/**
- * @}
- */
-
-/** @defgroup FMC_CLK_Division
- * @{
- */
-#define IS_FMC_CLK_DIV(DIV) (((DIV) > 0) && ((DIV) <= 15))
-/**
- * @}
- */
-
-/** @defgroup FMC_Data_Latency
- * @{
- */
-#define IS_FMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 15)
-/**
- * @}
- */
-
-/** @defgroup FMC_Access_Mode
- * @{
- */
-#define FMC_AccessMode_A ((uint32_t)0x00000000)
-#define FMC_AccessMode_B ((uint32_t)0x10000000)
-#define FMC_AccessMode_C ((uint32_t)0x20000000)
-#define FMC_AccessMode_D ((uint32_t)0x30000000)
-
-#define IS_FMC_ACCESS_MODE(MODE) (((MODE) == FMC_AccessMode_A) || \
- ((MODE) == FMC_AccessMode_B) || \
- ((MODE) == FMC_AccessMode_C) || \
- ((MODE) == FMC_AccessMode_D))
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup FMC_NAND_PCCARD_Controller
- * @{
- */
-
-/** @defgroup FMC_Wait_feature
- * @{
- */
-#define FMC_Waitfeature_Disable ((uint32_t)0x00000000)
-#define FMC_Waitfeature_Enable ((uint32_t)0x00000002)
-
-#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_Waitfeature_Disable) || \
- ((FEATURE) == FMC_Waitfeature_Enable))
-/**
- * @}
- */
-
-/** @defgroup FMC_NAND_Data_Width
- * @{
- */
-#define FMC_NAND_MemoryDataWidth_8b ((uint32_t)0x00000000)
-#define FMC_NAND_MemoryDataWidth_16b ((uint32_t)0x00000010)
-
-#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_MemoryDataWidth_8b) || \
- ((WIDTH) == FMC_NAND_MemoryDataWidth_16b))
-/**
- * @}
- */
-
-/** @defgroup FMC_ECC
- * @{
- */
-#define FMC_ECC_Disable ((uint32_t)0x00000000)
-#define FMC_ECC_Enable ((uint32_t)0x00000040)
-
-#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_ECC_Disable) || \
- ((STATE) == FMC_ECC_Enable))
-/**
- * @}
- */
-
-/** @defgroup FMC_ECC_Page_Size
- * @{
- */
-#define FMC_ECCPageSize_256Bytes ((uint32_t)0x00000000)
-#define FMC_ECCPageSize_512Bytes ((uint32_t)0x00020000)
-#define FMC_ECCPageSize_1024Bytes ((uint32_t)0x00040000)
-#define FMC_ECCPageSize_2048Bytes ((uint32_t)0x00060000)
-#define FMC_ECCPageSize_4096Bytes ((uint32_t)0x00080000)
-#define FMC_ECCPageSize_8192Bytes ((uint32_t)0x000A0000)
-
-#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_ECCPageSize_256Bytes) || \
- ((SIZE) == FMC_ECCPageSize_512Bytes) || \
- ((SIZE) == FMC_ECCPageSize_1024Bytes) || \
- ((SIZE) == FMC_ECCPageSize_2048Bytes) || \
- ((SIZE) == FMC_ECCPageSize_4096Bytes) || \
- ((SIZE) == FMC_ECCPageSize_8192Bytes))
-/**
- * @}
- */
-
-/** @defgroup FMC_TCLR_Setup_Time
- * @{
- */
-#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FMC_TAR_Setup_Time
- * @{
- */
-#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FMC_Setup_Time
- * @{
- */
-#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FMC_Wait_Setup_Time
- * @{
- */
-#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FMC_Hold_Setup_Time
- * @{
- */
-#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
-/**
- * @}
- */
-
-/** @defgroup FMC_HiZ_Setup_Time
- * @{
- */
-#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/** @defgroup FMC_NOR_SRAM_Controller
- * @{
- */
-
-/** @defgroup FMC_ColumnBits_Number
- * @{
- */
-#define FMC_ColumnBits_Number_8b ((uint32_t)0x00000000)
-#define FMC_ColumnBits_Number_9b ((uint32_t)0x00000001)
-#define FMC_ColumnBits_Number_10b ((uint32_t)0x00000002)
-#define FMC_ColumnBits_Number_11b ((uint32_t)0x00000003)
-
-#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_ColumnBits_Number_8b) || \
- ((COLUMN) == FMC_ColumnBits_Number_9b) || \
- ((COLUMN) == FMC_ColumnBits_Number_10b) || \
- ((COLUMN) == FMC_ColumnBits_Number_11b))
-
-/**
- * @}
- */
-
-/** @defgroup FMC_RowBits_Number
- * @{
- */
-#define FMC_RowBits_Number_11b ((uint32_t)0x00000000)
-#define FMC_RowBits_Number_12b ((uint32_t)0x00000004)
-#define FMC_RowBits_Number_13b ((uint32_t)0x00000008)
-
-#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_RowBits_Number_11b) || \
- ((ROW) == FMC_RowBits_Number_12b) || \
- ((ROW) == FMC_RowBits_Number_13b))
-
-/**
- * @}
- */
-
-/** @defgroup FMC_SDMemory_Data_Width
- * @{
- */
-#define FMC_SDMemory_Width_8b ((uint32_t)0x00000000)
-#define FMC_SDMemory_Width_16b ((uint32_t)0x00000010)
-#define FMC_SDMemory_Width_32b ((uint32_t)0x00000020)
-
-#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDMemory_Width_8b) || \
- ((WIDTH) == FMC_SDMemory_Width_16b) || \
- ((WIDTH) == FMC_SDMemory_Width_32b))
-
-/**
- * @}
- */
-
-/** @defgroup FMC_InternalBank_Number
- * @{
- */
-#define FMC_InternalBank_Number_2 ((uint32_t)0x00000000)
-#define FMC_InternalBank_Number_4 ((uint32_t)0x00000040)
-
-#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_InternalBank_Number_2) || \
- ((NUMBER) == FMC_InternalBank_Number_4))
-
-/**
- * @}
- */
-
-
-/** @defgroup FMC_CAS_Latency
- * @{
- */
-#define FMC_CAS_Latency_1 ((uint32_t)0x00000080)
-#define FMC_CAS_Latency_2 ((uint32_t)0x00000100)
-#define FMC_CAS_Latency_3 ((uint32_t)0x00000180)
-
-#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_CAS_Latency_1) || \
- ((LATENCY) == FMC_CAS_Latency_2) || \
- ((LATENCY) == FMC_CAS_Latency_3))
-
-/**
- * @}
- */
-
-/** @defgroup FMC_Write_Protection
- * @{
- */
-#define FMC_Write_Protection_Disable ((uint32_t)0x00000000)
-#define FMC_Write_Protection_Enable ((uint32_t)0x00000200)
-
-#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_Write_Protection_Disable) || \
- ((WRITE) == FMC_Write_Protection_Enable))
-
-/**
- * @}
- */
-
-
-/** @defgroup FMC_SDClock_Period
- * @{
- */
-#define FMC_SDClock_Disable ((uint32_t)0x00000000)
-#define FMC_SDClock_Period_2 ((uint32_t)0x00000800)
-#define FMC_SDClock_Period_3 ((uint32_t)0x00000C00)
-
-#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDClock_Disable) || \
- ((PERIOD) == FMC_SDClock_Period_2) || \
- ((PERIOD) == FMC_SDClock_Period_3))
-
-/**
- * @}
- */
-
-/** @defgroup FMC_Read_Burst
- * @{
- */
-#define FMC_Read_Burst_Disable ((uint32_t)0x00000000)
-#define FMC_Read_Burst_Enable ((uint32_t)0x00001000)
-
-#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_Read_Burst_Disable) || \
- ((RBURST) == FMC_Read_Burst_Enable))
-
-/**
- * @}
- */
-
-/** @defgroup FMC_ReadPipe_Delay
- * @{
- */
-#define FMC_ReadPipe_Delay_0 ((uint32_t)0x00000000)
-#define FMC_ReadPipe_Delay_1 ((uint32_t)0x00002000)
-#define FMC_ReadPipe_Delay_2 ((uint32_t)0x00004000)
-
-#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_ReadPipe_Delay_0) || \
- ((DELAY) == FMC_ReadPipe_Delay_1) || \
- ((DELAY) == FMC_ReadPipe_Delay_2))
-
-/**
- * @}
- */
-
-/** @defgroup FMC_LoadToActive_Delay
- * @{
- */
-#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
-/**
- * @}
- */
-
-/** @defgroup FMC_ExitSelfRefresh_Delay
- * @{
- */
-#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
-/**
- * @}
- */
-
-/** @defgroup FMC_SelfRefresh_Time
- * @{
- */
-#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
-/**
- * @}
- */
-
-/** @defgroup FMC_RowCycle_Delay
- * @{
- */
-#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
-/**
- * @}
- */
-
-/** @defgroup FMC_Write_Recovery_Time
- * @{
- */
-#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
-/**
- * @}
- */
-
-/** @defgroup FMC_RP_Delay
- * @{
- */
-#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
-/**
- * @}
- */
-
-/** @defgroup FMC_RCD_Delay
- * @{
- */
-#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
-
-/**
- * @}
- */
-
-/** @defgroup FMC_Command_Mode
- * @{
- */
-#define FMC_Command_Mode_normal ((uint32_t)0x00000000)
-#define FMC_Command_Mode_CLK_Enabled ((uint32_t)0x00000001)
-#define FMC_Command_Mode_PALL ((uint32_t)0x00000002)
-#define FMC_Command_Mode_AutoRefresh ((uint32_t)0x00000003)
-#define FMC_Command_Mode_LoadMode ((uint32_t)0x00000004)
-#define FMC_Command_Mode_Selfrefresh ((uint32_t)0x00000005)
-#define FMC_Command_Mode_PowerDown ((uint32_t)0x00000006)
-
-#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_Command_Mode_normal) || \
- ((COMMAND) == FMC_Command_Mode_CLK_Enabled) || \
- ((COMMAND) == FMC_Command_Mode_PALL) || \
- ((COMMAND) == FMC_Command_Mode_AutoRefresh) || \
- ((COMMAND) == FMC_Command_Mode_LoadMode) || \
- ((COMMAND) == FMC_Command_Mode_Selfrefresh) || \
- ((COMMAND) == FMC_Command_Mode_PowerDown))
-
-/**
- * @}
- */
-
-/** @defgroup FMC_Command_Target
- * @{
- */
-#define FMC_Command_Target_bank2 ((uint32_t)0x00000008)
-#define FMC_Command_Target_bank1 ((uint32_t)0x00000010)
-#define FMC_Command_Target_bank1_2 ((uint32_t)0x00000018)
-
-#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_Command_Target_bank1) || \
- ((TARGET) == FMC_Command_Target_bank2) || \
- ((TARGET) == FMC_Command_Target_bank1_2))
-
-/**
- * @}
- */
-
-/** @defgroup FMC_AutoRefresh_Number
- * @{
- */
-#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16))
-
-/**
- * @}
- */
-
-/** @defgroup FMC_ModeRegister_Definition
- * @{
- */
-#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191)
-
-/**
- * @}
- */
-
-
-/** @defgroup FMC_Mode_Status
- * @{
- */
-#define FMC_NormalMode_Status ((uint32_t)0x00000000)
-#define FMC_SelfRefreshMode_Status FMC_SDSR_MODES1_0
-#define FMC_PowerDownMode_Status FMC_SDSR_MODES1_1
-
-#define IS_FMC_MODE_STATUS(STATUS) (((STATUS) == FMC_NormalMode_Status) || \
- ((STATUS) == FMC_SelfRefreshMode_Status) || \
- ((STATUS) == FMC_PowerDownMode_Status))
-
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/** @defgroup FMC_Interrupt_sources
- * @{
- */
-#define FMC_IT_RisingEdge ((uint32_t)0x00000008)
-#define FMC_IT_Level ((uint32_t)0x00000010)
-#define FMC_IT_FallingEdge ((uint32_t)0x00000020)
-#define FMC_IT_Refresh ((uint32_t)0x00004000)
-
-#define IS_FMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
-#define IS_FMC_GET_IT(IT) (((IT) == FMC_IT_RisingEdge) || \
- ((IT) == FMC_IT_Level) || \
- ((IT) == FMC_IT_FallingEdge) || \
- ((IT) == FMC_IT_Refresh))
-
-#define IS_FMC_IT_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \
- ((BANK) == FMC_Bank3_NAND) || \
- ((BANK) == FMC_Bank4_PCCARD) || \
- ((BANK) == FMC_Bank1_SDRAM) || \
- ((BANK) == FMC_Bank2_SDRAM))
-/**
- * @}
- */
-
-/** @defgroup FMC_Flags
- * @{
- */
-#define FMC_FLAG_RisingEdge ((uint32_t)0x00000001)
-#define FMC_FLAG_Level ((uint32_t)0x00000002)
-#define FMC_FLAG_FallingEdge ((uint32_t)0x00000004)
-#define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
-#define FMC_FLAG_Refresh FMC_SDSR_RE
-#define FMC_FLAG_Busy FMC_SDSR_BUSY
-
-#define IS_FMC_GET_FLAG(FLAG) (((FLAG) == FMC_FLAG_RisingEdge) || \
- ((FLAG) == FMC_FLAG_Level) || \
- ((FLAG) == FMC_FLAG_FallingEdge) || \
- ((FLAG) == FMC_FLAG_FEMPT) || \
- ((FLAG) == FMC_FLAG_Refresh) || \
- ((FLAG) == FMC_SDSR_BUSY))
-
-#define IS_FMC_GETFLAG_BANK(BANK) (((BANK) == FMC_Bank2_NAND) || \
- ((BANK) == FMC_Bank3_NAND) || \
- ((BANK) == FMC_Bank4_PCCARD) || \
- ((BANK) == FMC_Bank1_SDRAM) || \
- ((BANK) == FMC_Bank2_SDRAM) || \
- ((BANK) == (FMC_Bank1_SDRAM | FMC_Bank2_SDRAM)))
-
-#define IS_FMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
-
-
-/**
- * @}
- */
-
-/** @defgroup FMC_Refresh_count
- * @{
- */
-#define IS_FMC_REFRESH_COUNT(COUNT) ((COUNT) <= 8191)
-
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/* NOR/SRAM Controller functions **********************************************/
-void FMC_NORSRAMDeInit(uint32_t FMC_Bank);
-void FMC_NORSRAMInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct);
-void FMC_NORSRAMStructInit(FMC_NORSRAMInitTypeDef* FMC_NORSRAMInitStruct);
-void FMC_NORSRAMCmd(uint32_t FMC_Bank, FunctionalState NewState);
-
-/* NAND Controller functions **************************************************/
-void FMC_NANDDeInit(uint32_t FMC_Bank);
-void FMC_NANDInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct);
-void FMC_NANDStructInit(FMC_NANDInitTypeDef* FMC_NANDInitStruct);
-void FMC_NANDCmd(uint32_t FMC_Bank, FunctionalState NewState);
-void FMC_NANDECCCmd(uint32_t FMC_Bank, FunctionalState NewState);
-uint32_t FMC_GetECC(uint32_t FMC_Bank);
-
-/* PCCARD Controller functions ************************************************/
-void FMC_PCCARDDeInit(void);
-void FMC_PCCARDInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct);
-void FMC_PCCARDStructInit(FMC_PCCARDInitTypeDef* FMC_PCCARDInitStruct);
-void FMC_PCCARDCmd(FunctionalState NewState);
-
-/* SDRAM Controller functions ************************************************/
-void FMC_SDRAMDeInit(uint32_t FMC_Bank);
-void FMC_SDRAMInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct);
-void FMC_SDRAMStructInit(FMC_SDRAMInitTypeDef* FMC_SDRAMInitStruct);
-void FMC_SDRAMCmdConfig(FMC_SDRAMCommandTypeDef* FMC_SDRAMCommandStruct);
-uint32_t FMC_GetModeStatus(uint32_t SDRAM_Bank);
-void FMC_SetRefreshCount(uint32_t FMC_Count);
-void FMC_SetAutoRefresh_Number(uint32_t FMC_Number);
-void FMC_SDRAMWriteProtectionConfig(uint32_t SDRAM_Bank, FunctionalState NewState);
-
-/* Interrupts and flags management functions **********************************/
-void FMC_ITConfig(uint32_t FMC_Bank, uint32_t FMC_IT, FunctionalState NewState);
-FlagStatus FMC_GetFlagStatus(uint32_t FMC_Bank, uint32_t FMC_FLAG);
-void FMC_ClearFlag(uint32_t FMC_Bank, uint32_t FMC_FLAG);
-ITStatus FMC_GetITStatus(uint32_t FMC_Bank, uint32_t FMC_IT);
-void FMC_ClearITPendingBit(uint32_t FMC_Bank, uint32_t FMC_IT);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32F4xx_FMC_H */
-/**
- * @}
- */
-
-/**
- * @}
- */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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